US Pat. No. 10,396,935

METHOD AND DEVICE FOR TRANSMITTING UPLINK CONTROL SIGNAL IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for transmitting acknowledgement/negative-acknowledgement (ACK/NACK) information in a wireless communication system, the method performed by a user equipment (UE) and comprising:receiving a physical downlink shard channel (PDSCH); and
transmitting the ACK/NACK information for the PDSCH through a physical uplink control channel (PUCCH) resource,
wherein if the UE receives the PDSCH with a corresponding downlink control channel having an ACK/NACK resource indicator (ARI) field, the PUCCH resource is determined based on the ARI field, and
wherein if the UE receives the PDSCH without the corresponding downlink control channel, the PUCCH resource is determined based on a radio resource control (RRC) message.

US Pat. No. 10,396,931

FIRST NETWORK NODE, SECOND NETWORK NODE AND METHODS FOR TRANSMITTING AND RECEIVING A PROTOCOL DATA UNIT

Telefonaktiebolaget LM Er...

1. A method performed by a first network node, for transmitting a Radio Link Control (RLC) Unacknowledged Mode (UM) Protocol Data Unit (PDU) to a second network node, which first network node and second network node operate in a third generation partnership project (3GPP) wireless communications network, which 3GPP wireless communications network provides a first channel and a second channel, the method comprising:when it is detected by the first network node that the RLC UM PDU has failed to be transmitted over the first channel, wherein the first channel is represented by an unlicensed channel (ULC), deciding to redirect the RLC UM PDU to be transmitted over the second channel, and when RLC UM PDU is too large to be sent in a single transmission over the second channel, wherein the second channel is represented by a Licensed channel (LC),
dividing the RLC UM PDU into two or more re-segmented RLC UM PDUs; and
transmitting the two or more re-segmented RLC UM PDUs to the second network node over the second channel,
wherein each re-segmented RLC UM PDU comprises the following indications:
that the PDU is re-segmented;
an order indicator related to the re-segmented RLC UM PDU; and
whether or not the re-segmented RLC UM PDU is a last re-segmented RLC UM PDU out of the two or more re-segmented RLC UM PDUs,
wherein the indications are comprised in a header of the re-segmented RLC UM PDU.

US Pat. No. 10,396,929

ALL-OPTICAL REGENERATION SYSTEM FOR OPTICAL WAVELENGTH DIVISION MULTIPLEXED COMMUNICATION SYSTEMS

Danmarks Tekniske Univers...

1. An all-optical regeneration system for regeneration of optical wavelength division multiplexed (WDM) data signals in an optical WDM communication system, the all-optical regeneration system comprising:a WDM-to-OTDM converter configured for converting an input WDM data signal comprising multiple wavelength channels into an input optical time domain multiplexing (OTDM) data signal comprising multiple time multiplexed time channels,
an all-optical regenerator unit being applicable depending on the modulation format of said input WDM data signal and configured for regenerating the input OTDM data signal into an output OTDM data signal, wherein the all-optical regenerator is configured to work at a high bitrate value that is substantially a bitrate of a single wavelength channel of the multiple wavelength channels times a number of the multiple wavelength channels, and
an OTDM-to-WDM converter for converting the output OTDM data signal to an output WDM data signal, wherein
said all-optical regenerator system is suitable for phase-keyed information, and an input of the all-optical regenerator unit is in optical communication with an output of the WDM-to-OTDM converter, and an output of the all-optical regenerator unit is in optical communication with an input of the OTDM-to-WDM converter, wherein the WDM-to-OTDM converter and/or the OTDM-to-WDM converter comprises a time-domain optical Fourier transformation (OFT) unit, and the OFT unit comprises a phase-modulation element and a dispersive element.

US Pat. No. 10,396,914

REFERENCE SIGNAL MEASUREMENT FILTERING IN MULTI-BEAM OPERATION

QUALCOMM Incorporated, S...

1. A method for performing measurement filtering of reference signals (RSs) for wireless communications by a user equipment (UE), comprising:receiving, from a base station (BS), a first beam configuration for measuring a first type of RSs from the BS and a second beam configuration for measuring a second type of RSs from the BS, wherein the first beam configuration indicates that at least one type of beam used to transmit the first type of RSs is static during a first set of time periods and the second beam configuration indicates that at least one type of beam used to transmit the second type of RSs varies during a second set of time periods; and
performing a measurement procedure for RSs received from the BS based at least in part on the first beam configuration and the second beam configuration, comprising:
filtering measurements of the first type of RSs received over the first set of time periods; and
refraining from filtering measurements of the second type of RSs received over the second set of time periods.

US Pat. No. 10,396,902

MINIMUM VARIANCE CARRIER RECOVERY WITH INCREASED PHASE NOISE TOLERANCE

Ciena Corporation, Hanov...

1. A method of data symbol recovery in a coherent receiver of an optical communications system, the method comprising:computing probabilistic phase error estimates based on data symbol estimates detected from a received optical signal;
computing a phase rotation based on the probabilistic phase error estimates;
applying the computed phase rotation to at least one data symbol estimate to generate a corresponding rotated symbol estimate; and
determining a recovered symbol value from the rotated symbol estimate, wherein the recovered symbol value belongs to a symbol constellation having a predetermined asymmetry with respect to phase rotation, and the computed phase rotation compensates phase noise that is greater than any decision region of the symbol constellation.

US Pat. No. 10,396,898

OPTICAL MODULE AND OPTICAL TRANSMITTING APPARATUS INSTALLING A NUMBER OF OPTICAL MODULES

SUMITOMO ELECTRIC DEVICE ...

1. An optical module that generates a modulated optical beam, comprising:an electrically insulating carrier that provides a ground pattern and a bias pad on a top surface thereof, the bias pad being electrically isolated from the ground pattern thereby forming a parasitic capacitor against the ground pattern;
a semiconductor element mounted on the ground pattern, the semiconductor element generating the modulated optical beam by being supplied with a bias current;
a capacitor mounted on the ground pattern; and
at least two bonding wires among a first bonding wire connecting the semiconductor element with the bias pad, a second bonding wire connecting the bias pad with the capacitor, and an additional bonding wire connecting the capacitor with the semiconductor element,
wherein the capacitor and the parasitic capacitor are operable in complementary with respect to frequencies, and
wherein the bias current is supplied to the semiconductor element from the capacitor through the at least two bonding wires.

US Pat. No. 10,396,885

DYNAMIC PARTITIONING OF MODULAR PHASED ARRAY ARCHITECTURES FOR MULTIPLE USES

INTEL CORPORATION, Santa...

1. A dynamically configurable modular antenna system comprising:a plurality of antenna modules, each of the antenna modules coupled with one of a plurality of radios and comprising an array of antenna elements coupled to one of a plurality radio frequency (RF) beamforming circuit, the plurality of RF beamforming circuits to adjust phase shifts associated with the antenna elements to generate antenna beams for the antenna modules;
a dynamic configuration unit comprising circuitry to receive an indication of a first usage for a first one of the plurality of antenna modules, and receive an indication of a second usage for a second one of the plurality of antenna modules; and
a main beamforming unit comprising circuitry coupled to the dynamic configuration unit and each of the antenna modules, the main beamforming unit to generate signal adjustments relative to the first one of the plurality of antenna modules to control a first antenna beam associated with the first one of the plurality of antenna modules based at least in part on the first usage, and generate signal adjustments relative to the second one of the plurality of antenna modules such that a second antenna beam associated with the second one of the plurality of antenna modules is generated based at least in part on the second usage, wherein the first usage and the second usage correspond to a first station and a second station, respectively, and
wherein the first one of the plurality of antenna modules to communicate first data with the first station via a first radio of the plurality of radios and utilizing a first orthogonal frequency division multiple access (OFDMA) framing, and the second one of the plurality of antenna modules to communicate second data with the second station via a second radio of the plurality of radios and utilizing a second OFDMA framing, and
wherein the first data and the second data are independent and unique from each other, the first OFDMA framing and the second OFDMA framing are independent from each other, and the first radio and the second radio are independent and unique from each other.

US Pat. No. 10,396,873

CONTROL SIGNALING IN A BEAMFORMING SYSTEM

MEDIATEK INC., HsinChu (...

1. A method comprising:receiving, by a user equipment (UE), a plurality of control beam transmissions from a base station using a set of control beams in a Millimeter Wave (mmWave) beamforming mobile communication network, wherein each control beam comprises a set of downlink (DL) control resource blocks, a set of uplink (UL) control resource blocks, and an associated set of beamforming weights based on preconfigured control beam configuration, wherein each resource block comprises radio resources on a two-dimensional resource grid of both time domain and frequency domain;
selecting a control beam from the plurality of control beam transmissions based on the preconfigured control beam configuration for establishing a connection with the base station; and
performing random access with the base station using the selected control beam, wherein the UE derives allocated DL and UL resource blocks and a selected set of beamforming weights associated with the selected control beam for the random access, wherein the UE performs the random access with the base station via the derived UL and DL control resource blocks of the selected control beam, and wherein the UE transmits over the derived UL control resource blocks and the selected set of beamforming weights for UL transmission and receives over the derived DL resource blocks using spatially reciprocal beamforming weights for DL reception.

US Pat. No. 10,396,853

SURFACE WAVE CONVERTER

Telefonaktiebolaget LM Er...

1. A surface wave converter for transmitting electromagnetic surface wave signals via a surface wave conduit, the surface wave converter comprising:an input port configured to receive an input signal;
a plurality of waveguide adapters for mounting along a circumference of the surface wave conduit, wherein the plurality of waveguide adapters are configured to jointly excite a surface wave on the surface wave conduit based on the input signal; and
an interface configured to distribute the input signal received on the input port of the surface wave converter over the plurality of waveguide adapters via respective waveguide adapter ports; and
wherein the plurality of waveguide adapters are configured to electromagnetically match a transition between an electrical signal at the interface and a surface wave on the surface wave conduit.

US Pat. No. 10,396,848

DEVICES, SYSTEMS AND METHODS FOR TRANSMITTING PROTOCOL CONFIGURATION INFORMATION BETWEEN MULTI-PROTOCOL DEVICES

Cypress Semiconductor Cor...

1. A method, comprising:receiving frequency hop configuration data for a first wireless communication protocol via a second wireless communication protocol in second communication circuits; and
configuring first communication circuits to communicate according to the first communication protocol with frequency hopping indicated by the frequency hop configuration data; wherein
the first communication circuits and second communication circuits are formed in a same combination device.

US Pat. No. 10,396,840

HIGH SPEED SHORT REACH INPUT/OUTPUT (I/O)

INTEL CORPORATION, Santa...

1. An apparatus comprising:a plurality of transmitter circuits on a first die;
a plurality of receiver circuits on a second die;
a plurality of conductive lines communicatively coupling the first die to the second die for the plurality of transmitter circuits to transmit data bits in parallel to the plurality of receiver circuits;
a termination circuit comprising a single shared capacitor, a plurality of termination resistors, and a plurality of reception buffers, each termination resistor corresponding to one of the plurality of conductive lines and one of the reception buffers having a first input and a second input and coupled to the single the shared capacitor, wherein each termination resistor corresponding to one of the reception buffers has a first end connected to the first input and a second end connected to the second input of the corresponding reception buffer and the single shared capacitor, wherein the single shared capacitor is to block direct current (DC) power from the parallel transmission of data bits on the conductive lines; and
a parallel coding block to encode data transmitted by the plurality of transmitter circuits via the plurality of conductive lines according to a DC balanced code.

US Pat. No. 10,396,819

TRANSMITTER APPARATUS AND BIT INTERLEAVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...


US Pat. No. 10,396,816

PAD ENCODING AND DECODING

International Business Ma...

1. An encoding system, comprising:a writing engine for writing a character to a cell of a multi-dimensional shape;
a determination engine for determining a next empty cell by traversing neighboring cells in the multi-dimensional shape until an empty cell is located;
a loop facilitator for repeating the writing and determining for at least one additional character; and
a serialization engine for serializing the cells into a one dimensional string of characters representing an encoded string of alphanumeric characters.

US Pat. No. 10,396,798

RECONFIGURABLE CIRCUIT

NEC CORPORATION, Tokyo (...

9. A reconfigurable circuit comprising:first and second wires; and
two or more paths that are active at different times and that are configured to couple said first wire to said second wire,
wherein each path includes:
a first non-volatile resistive switch, whose first terminal is connected to said first wire;
a first transistor whose drain terminal is connected to a second terminal of said first non-volatile resistive switch;
a second transistor whose source terminal is connected to a second terminal of said first non-volatile resistive switch;
a second non-volatile resistive switch whose first terminal is connected to a drain terminal of said second transistor and whose second terminal is connected to said second wire; and
a 2-input AND circuit whose output is connected to a gate terminal of said first transistor,
wherein a time control signal is supplied to both a first data input of said 2-input AND circuit and a gate terminal of said second transistor, and a write control signal is supplied to a second data input of said 2-input AND circuit.

US Pat. No. 10,396,779

GROUND SWITCHING FOR SPEAKER CURRENT SENSE

TEXAS INSTRUMENTS INCORPO...

1. A circuit, comprising:a pair of high side transistors coupled to a power supply node;
a pair of low side transistors coupled to the pair of high side transistors;
a first sense resistor coupled to one of the low side transistors at a first sense node;
a second sense resistor coupled to another of the low side transistors at a second sense node, wherein the first and second sense resistors are coupled together at a ground node;
a first switch network coupled to the first sense resistor;
a second switch network coupled to the second sense resistor;
a first pair of switches configured to selectively provide a potential of the ground node or a potential of the first sense node as a ground potential to the first switch network; and
a second pair of switches configured to selectively provide the potential of the ground node or a potential of the second sense node as a ground potential to the second switch network.

US Pat. No. 10,396,772

METHODS AND DEVICES TO IMPROVE SWITCHING TIME BY BYPASSING GATE RESISTOR

pSemi Corporation, San D...

1. A switching circuit comprising:a first node;
a second node;
a first terminal;
a second terminal;
a third terminal;
a fourth terminal;
a main FET switch stack;
a bypass FET switch stack, and
wherein:
the main FET switch stack comprises:
a series arrangement of a plurality of main FET switches coupled between the first node and the second node, and
a plurality of main gate resistors, the plurality of the main gate resistors connecting the second terminal to corresponding gates of the plurality of the main FET switches;
the bypass FET switch stack comprises:
a series arrangement of a plurality of first bypass FET switches;
a series arrangement of a plurality of second bypass FET switches;
a plurality of first bypass gate resistors; the plurality of the first bypass gate resistors connecting corresponding gates of the plurality of the first bypass FET switches to the third terminal;
a plurality of second bypass gate resistors; the plurality of the second bypass gate resistors connecting corresponding gates of the plurality of the second bypass FET switches to the fourth terminal, and
a plurality of drain-source resistances, the plurality of the drain-source resistors being coupled across the corresponding drains and sources of the plurality of the first and the second bypass FET switches;
wherein:
drains and sources of the first bypass FET switches are connected to corresponding drains and sources of the second bypass FET switches respectively;
the drains of the bypass FET switches closest to the first terminal and farthest from the second terminal are connected to the first terminal;
the sources of the bypass FET switches closest to the second terminal and farthest from the first terminal are connected to the second terminal;
wherein:
a first supply voltage applied to the first terminal is configured to transition the plurality of the main FET switches from an OFF to an ON state and vice versa;
a second supply voltage applied to the third terminal is configured to open the plurality of the first bypass FET switches when the plurality of the main FET switches are in the OFF or the ON state and to close the plurality of the first bypass FET switches when the plurality of the main FET switches is transitioning from the OFF to the ON state, and
a third supply voltage applied to the fourth terminal is configured to open the plurality of the second bypass FET switches when the plurality of the main FET switches are in the OFF or the ON state and to close the plurality of the second bypass FET switches when the plurality of the main FET switches is transitioning from the ON to the OFF state.

US Pat. No. 10,396,762

FLIP-FLOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

FUJITSU LIMITED, Kawasak...

1. A flip-flop circuit comprising:a data capture circuit that captures data based on a clock;
a data hold circuit that holds an output of the data capture circuit based on the clock; and
a timing control circuit that controls coupling between the output of the data capture circuit and the data hold circuit based on the clock;
when the data capture circuit captures new data based on the clock, the timing control circuit performing control so as to temporarily interrupt the coupling between the output of the data capture circuit and the data hold circuit, wherein the data capture circuit includes
a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type, the first transistor and the second transistor being arranged in series with each other between a first power supply line and a second power supply line and receiving the data by gates of the first transistor and the second transistor, and a third transistor of the second conductivity type, the third transistor being coupled between the first transistor and the second transistor and receiving the clock by a gate of the third transistor,
a clock delay circuit that delays the clock,
a fourth transistor of the first conductivity type, the fourth transistor receiving the clock delayed by the clock delay circuit and being disposed between the first power supply line and a first node to which the first transistor and the third transistor are coupled, and
a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type, the fifth transistor and the sixth transistor being arranged in series with each other between the first power supply line and the second power supply line and receiving the clock by gates of the fifth transistor and the sixth transistor, and a seventh transistor of the first conductivity type, the seventh transistor being coupled between the fifth transistor and the sixth transistor and receiving a signal of the first node by a gate of the seventh transistor.

US Pat. No. 10,396,753

STACKED WAFER-LEVEL PACKAGING DEVICES

Skyworks Solutions, Inc.,...

1. A wireless device comprising:a transceiver configured to generate a radio-frequency (RF) signal;
a front-end module (FEM) in communication with the transceiver, the front-end module including a packaging substrate configured to receive a plurality of components, the front-end module further including a stacked assembly implemented on the packaging substrate, the stacked assembly including a first wafer-level packaging (WLP) device having a radio-frequency shield, the stacked assembly further including a second wafer-level packaging device having a radio-frequency shield, the second wafer-level packaging device positioned over the first wafer-level packaging device such that the radio-frequency shield of the second wafer-level packaging device is electrically connected to the radio-frequency shield of the first wafer-level packaging device; and
an antenna in communication with the front-end module, the antenna configured to transmit an amplified radio-frequency signal.

US Pat. No. 10,396,747

TEMPERATURE COMPENSATED OSCILLATION CIRCUIT, OSCILLATOR, ELECTRONIC APPARATUS, VEHICLE, AND METHOD OF MANUFACTURING OSCILLATOR

Seiko Epson Corporation, ...

1. A temperature compensated oscillation circuit comprising:an oscillation circuit that oscillates a resonator;
a first terminal that is connected to the oscillation circuit and receives an output signal of the resonator;
a second terminal separate from the first terminal;
a fractional N-PLL circuit that multiplies frequency of an oscillation signal which is output by the oscillation circuit, based on a frequency division ratio which is input;
a temperature measurement unit that measures temperature; and
a storage unit that stores a temperature correction table for correcting frequency temperature characteristics of the oscillation signal,
a control unit configured to set an update mode for updating the temperature correction table; and
a temperature correction table updating unit configured to update the temperature correction table in the update mode based on an output signal of the fractional N-PLL circuit and a reference clock signal which is input from the second terminal,
wherein the frequency division ratio of the fractional N-PLL circuit is set based on a measurement value obtained by the temperature measurement unit and the temperature correction table.

US Pat. No. 10,396,737

WIDE DYNAMIC RANGE AMPLIFIER SYSTEM

SKYWORKS SOLUTIONS, INC.,...

1. A broadband amplifier assembly having a signal input and a signal output, comprising:a fixed gain amplifier having an input and an output, the input coupled to the signal input;
an adjustable attenuator having an input and an output, the input of the adjustable attenuator being coupled to the output of the fixed gain amplifier;
a variable gain amplifier having an input coupled to the output of the adjustable attenuator and an output coupled to the signal output, the variable gain amplifier having a substantially constant input-referred linearity across a range of gain levels; and
a controller coupled to the fixed gain amplifier, the adjustable attenuator, and the variable gain amplifier and configured to control an amount of attenuation provided by the adjustable attenuator and an amount of gain provided by the variable gain amplifier to maintain a substantially constant input-referred linearity across a range of output power levels provided by a combination of the fixed gain amplifier, the adjustable attenuator, and the variable gain amplifier.

US Pat. No. 10,396,732

AMPLIFICATION OF FREQUENCY MULTIPLEXED MICROWAVE SIGNALS USING CASCADING MULTI-PATH INTERFEROMETRIC JOSEPHSON DIRECTIONAL AMPLIFIERS WITH NONOVERLAPPING BANDWIDTHS

INTERNATIONAL BUSINESS MA...

2. A cascading microwave directional amplifier (cascade) comprising:a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies, wherein different operating bandwidths have different corresponding center frequencies; and
a series coupling between first Josephson device from the set and an nth Josephson device from the set, wherein the series coupling causes
the first Josephson device to amplify a signal of a first frequency from a frequency multiplexed microwave signal (multiplexed signal) and propagate without amplification a signal of an nth frequency from the multiplexed signal in a first signal flow direction through the series coupling, and
the nth Josephson device to amplify the signal of the nth frequency and propagate without amplification the signal of the first frequency from the multiplexed signal in the first signal flow direction through the series.

US Pat. No. 10,396,709

METHOD AND APPARATUS FOR IN-SITU HEALTH MONITORING OF SOLAR CELLS IN SPACE

United States of America ...

1. An apparatus comprising:one or more than one solar cells configured for exposure to light;
an analog circuit operatively connected to the one or more than one solar cells comprising:
a metal oxide field effect transistor having a gate;
a small value resistor in series with a channel of the metal oxide field effect transistor; and
wherein this series arrangement is in parallel with the one or more than one solar cells;
a difference amplifier circuit configured to amplify the voltage across the small value resistor to generate a solar cell current output that represents a current through the one or more than one solar cells;
an integrator circuit having a first input and a second input, wherein the first input is connected to a voltage input, wherein the second input is connected to a solar cell voltage output of the one or more than one solar cells, wherein, via the voltage input, the apparatus is configured to receive a desired set point voltage, wherein the integrator circuit is configured to integrate error between the desired set point voltage and the solar cell voltage output to produce an output voltage which is applied to the gate of the metal oxide field effect transistor to generate both the solar cell current output and the solar cell voltage output; and
a voltage divider comprised of two series connected resistors in parallel with the one or more than one solar cells, wherein a common node of the voltage divider is connected to both the second input of the integrator circuit and a voltage measuring output of the apparatus, wherein the solar cell voltage output is provided to the integrator circuit via the connection between the common node and the second input.

US Pat. No. 10,396,708

MAINTAINING A SOLAR POWER MODULE

Saudi Arabian Oil Company...

1. A solar power system, comprising:a plurality of solar power cells mounted on an outer surface of a spherical frame, the spherical frame comprising an inner surface that defines an interior volume;
a heat sink that comprises a hollow housing mounted and enclosed within the interior volume of the spherical frame, the hollow housing fluidly isolating an inner volume of the hollow housing from a housing volume defined between the hollow housing and the inner surface of the spherical frame, the housing volume comprising an annulus cross-section; and
a phase change material positioned in, and fluidly sealed within, the inner volume of the hollow housing of the heat sink such that the phase change material is fluidly isolated from the housing volume of the interior volume of the spherical frame, the phase change material thermally coupled to the inner surface of the spherical frame through the hollow housing and the housing volume to receive heat from the outer surface of the spherical frame.

US Pat. No. 10,396,702

MOTOR DRIVE CONTROL DEVICE

HITACHI AUTOMOTIVE SYSTEM...

1. A motor drive control device of a permanent magnet synchronous motor in which each phase is independently controlled, the motor drive control device comprising:a smoothing capacitor interposed between a battery configured to supply electric power to the permanent magnet synchronous motor and the permanent magnet synchronous motor to smoothen the current;
an inverter interposed between the smoothing capacitor and the permanent magnet synchronous motor to convert a DC bus current flowing on the smoothing capacitor side into a multiphase motor current and supply the multiphase motor current to the permanent magnet synchronous motor;
a current detection unit which detects one of the motor current and the DC bus current;
a 0-axis current calculation unit which calculates and outputs a 0-axis current on the basis of the current detected by the current detection unit;
a comparison determination unit which determines a reference 0-axis current value, the reference 0-axis current value being a 0-axis current value when the temperature of a permanent magnet provided in the permanent magnet synchronous motor is a reference temperature, and compares the reference 0-axis current value with the calculated 0-axis current; and
a drive control unit which drives and controls the inverter on the basis of the result of the comparison determination of the comparison determination unit,
wherein, when a region of the 0-axis current value at a temperature lower than the reference temperature is defined as a low-temperature estimation region, and a region of the 0-axis current value at a temperature higher than the reference temperature is defined as first to third high-temperature estimation regions (here, a high-low relation of the temperature of each region is the first high-temperature estimation region the comparison determination unit determines as to which region of the low-temperature estimation region and the first to third high-temperature estimation regions the 0-axis current belongs,
the drive control unit outputs an inverter drive signal based on a drive condition in which a predetermined torque is output when the temperature of the permanent magnet is at the reference temperature, when the 0-axis current is determined to belong to one of the low-temperature estimation region and the first high-temperature estimation region,
the drive control unit outputs an inverter drive signal for reducing the motor current so as to prioritize the prevention of occurrence of irreversible demagnetization of the permanent magnet rather than the output of the predetermined torque, when the 0-axis current is determined to belong to the second high-temperature estimation region, and
the drive control unit outputs an inverter drive signal which sets the motor current to zero so as not to cause irreversible demagnetization of the permanent magnet, when the 0-axis current is determined to belong to the third high-temperature estimation region.

US Pat. No. 10,396,691

MOTOR CONTROL CIRCUIT SYSTEM

1. A motor control circuit system for a driven mechanism, which comprises:a motor driven by an alternating current;
a controller serving as a switch and electrically connected to the motor, wherein the controller is activated to control a start and stop of supplying AC current to the motor; wherein the controller comprises a positive half sine wave controller switch and a negative half sine wave controller switch;
a processor unit electrically linked to the controller, wherein the processor unit comprises a voltage controlling module;
a sensor electrically linked to the controller;
a converter electrically linked to the controller and the processor unit;
wherein the voltage controlling module controls the positive half sine wave controller switch and the negative half sine wave controller switch of the controller so that current starts to pass to the motor when an input voltage of the motor reaches predetermined starting thresholds and stops passing to the motor when the input voltage of the motor reaches predetermined ending thresholds;
wherein for a power supply generating periodic voltage waves, a starting threshold and an ending threshold are set to each half of the voltage waves; the starting threshold is set at one point of the half wave, and the ending threshold is set at the same half wave after the starting threshold; when the input voltage of the motor reaches the starting thresholds, the voltage controlling module turns on the positive half sine wave controller switch or the negative half sine wave controller switch respectively, so as to let current start passing through the motor, and when the input voltage of the motor reaches the ending thresholds, the voltage controlling module turns off the positive half sine wave controller switch or the negative half sine wave controller switch respectively, so as to stop current from passing through the motor; therefore, during the rest part of the voltage waves, the motor will turn with its own rotational inertia so as to save power thereto.

US Pat. No. 10,396,687

STATOR POSITIONER FOR ELECTROSTATIC GENERATOR ELECTRODES AND NEW ELECTRODE DESIGN

Lawrence Livermore Nation...

1. An apparatus, comprising:a carriage body having a first hole having a longitudinal opening;
a first spring;
a first rod that is spring loaded with said first spring, wherein said first rod has a first length, wherein a portion of said first length is located within said first longitudinal opening;
a first support structure having a first proximal end fixedly attached to said body such that said first support structure extends from said body perpendicularly to said first rod;
a first magnet fixedly attached to said first support structure; and
a second support structure having a second proximal end fixedly attached to said body such that said second support structure extends from said body perpendicularly to said first rod and is parallel to said first support structure.

US Pat. No. 10,396,680

DIRECT CURRENT VOLTAGE REGULATION OF PERMANENT MAGNET GENERATOR

HAMILTON SUNDSTRAND CORPO...

1. An aircraft power generation unit to generate direct current (DC) power provided to a load, the unit comprising:permanent magnet generator (PMG) that includes first, second, third and fourth sets of windings, each of the winding sets including three windings;
a rectifier section that includes:
a first six-pulse rectifier connected to the first set of windings and having a first rectifier positive rail and a first rectifier negative rail and forming a first DC voltage (Vdc1) between the first rectifier positive rail and the first rectifier negative rail from voltage received from the first set of windings;
a second six-pulse rectifier connected to the second set of windings and having a second rectifier positive rail and a second rectifier negative rail and forming a second DC voltage (Vdc2) between the second rectifier positive rail and the second rectifier negative rail from voltage received from the second set of windings;
a third six-pulse rectifier connected to the third set of windings and having a third rectifier positive rail and a third rectifier negative rail and forming a third DC voltage (Vdc3) between the third rectifier positive rail and third rectifier negative rail from voltage received from the third set of windings;
a fourth six-pulse rectifier connected to the fourth set of windings and having a fourth rectifier positive rail and a fourth rectifier negative rail and forming a fourth DC voltage (Vdc4) between the fourth rectifier positive rail and fourth rectifier negative rail from voltage received from the fourth set of windings; and
a common local output bus;
an output bus configured to be connected to the load and including a positive output bus rail and a negative output bus rail; and
a controller that receives an input signal from at least one of the output sets and selectively couples either the common local output bus or fourth rectifier negative rail to the output bus negative rail and one or more of the first, second and third six-pulse rectifiers to the output bus positive rail to provide a constant voltage to the load, wherein the controller selectively couples the common local output bus and fourth rectifier negative rail to the output bus negative rail based on a speed of the PMG.

US Pat. No. 10,396,675

SWITCHING POWER SUPPLY APPARATUS

TDK CORPORATION, Minato-...

1. A switching power supply apparatus comprising:a transformer configured to include a primary coil and a secondary coil;
a primary bridge circuit configured to include
a first leg including a first switch element and a second switch element, a first node between the first switch element and the second switch element being connected to the primary coil, and
a second leg including a third switch element and a fourth switch element, a second node between the third switch element and the fourth switch element being connected to the primary coil;
a secondary bridge circuit configured to include
a third leg including a fifth switch element and a sixth switch element, a third node between the fifth switch element and the sixth switch element being connected to the secondary coil, and
a fourth leg including a seventh switch element and an eighth switch element, a fourth node between the seventh switch element and the eighth switch element being connected to the secondary coil;
a control unit configured to control the current flowing through switch elements with respective predetermined pulse widths by maintaining a constant first conduction width and a constant second conduction width during a first time period when a voltage value of the output of the secondary bridge circuit is greater than a predetermined output voltage and perform phase control by changing at least one of the first conduction width and the second conduction width during a second time period when a voltage value of the output of the secondary bridge circuit is less than the predetermined output voltage, the first conduction width being a time width in which a pulse for driving the first switch element and a pulse for driving the fourth switch element overlap temporally, the second conduction width being a time width in which a pulse for driving the second switch element and a pulse for driving the third switch element overlap temporally;
a first smoothing capacitor that is connected to the primary bridge circuit; and
a second smoothing capacitor that is connected to the secondary bridge circuit.

US Pat. No. 10,396,672

CONTROL OF ISOLATED POWER CONVERTERS DURING TRANSIENT LOAD CONDITIONS

Infineon Technologies Aus...

1. A method of controlling a non-resonant isolated power converter, the method comprising:switching primary side switch devices of the non-resonant isolated power converter at a nominal switching period having a positive half cycle and a negative half cycle to transfer energy across a transformer of the non-resonant isolated power converter during the positive half cycle and the negative half cycle of the nominal switching period, the positive half cycle and the negative half cycle of the nominal switching period having a same nominal duration;
responsive to a transient load condition, switching the primary side switch devices at an initial switching period different than the nominal switching period to transfer energy across the transformer during a positive half cycle and a negative half cycle of the initial switching period, the positive half cycle and the negative half cycle of the initial switching period having a same initial duration; and
symmetrically reducing the duration of the positive half cycle and the negative half cycle of the initial switching period for at least one subsequent switching period during the transient load condition.

US Pat. No. 10,396,662

DIRECT CURRENT LINK CIRCUIT

Solaredge Technologies Lt...

1. A method comprising:connecting, through a resonant circuit, a direct current power source alternatively across:
a positive output terminal of a dual direct current output and a neutral terminal during a first portion of a switching cycle, wherein the first portion of the switching cycle comprises a first switched-on-period that corresponds to one half of a resonant period of the resonant circuit; and
a negative output terminal of the dual direct current output and the neutral terminal during a second portion of the switching cycle, wherein the second portion of the switching cycle comprises a second switched-on-period that corresponds to another half of the resonant period associated with the resonant circuit.

US Pat. No. 10,396,661

POWER SUPPLY CONTROL APPARATUS

AutoNetworks Technologies...

1. A power supply control apparatus that includes a semiconductor switch that is arranged midway in a power supply path and is ON if a voltage at a control end of the semiconductor switch is at least a threshold, the power supply control apparatus comprising:a second semiconductor switch that is arranged midway in the power supply path on an upstream side of the semiconductor switch, the second semiconductor switch being ON if a voltage at a control end thereof is at least a second threshold;
a resistor connected between one end of the power supply path on a current input side and the control end of the second semiconductor switch;
a diode having an anode connected to the control end of the semiconductor switch, and a cathode connected to the control end of the second semiconductor switch;
a voltage output unit for outputting a voltage; and
a switch connected between the one end of the power supply path and the control end of the semiconductor switch,
wherein the switch is ON if a differential voltage obtained by subtracting the voltage at the control end of the semiconductor switch from an output voltage that is output by the voltage output unit is at least a predetermined voltage, and is OFF if the differential voltage is smaller than the predetermined voltage.

US Pat. No. 10,396,660

SWITCHING REGULATOR, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ELECTRONIC APPLIANCE

Rohm Co., Ltd., Kyoto (J...

1. A switching regulator configured to generate an output voltage from an input voltage, the switching regulator comprising:an upper switch of which a first terminal is connected to a first application terminal to which the input voltage is applied;
a lower switch of which a first terminal is connected to a second terminal of the upper switch and of which a second terminal is connected to a second application terminal to which a predetermined voltage lower than the input voltage is applied;
an inductor of which a first terminal is connected to a connection node between the upper switch and the lower switch;
an output capacitor connected to a second terminal of the inductor;
a controller configured to generate a control signal for complementarily turning on and off the upper switch and the lower switch according to the output voltage; and
a current extractor configured to extract a constant current from the first terminal or the second terminal of the inductor, wherein
the controller is configured, under a light load, to stop switching control and hold the upper switch and the lower switch in an off state, and
the constant current has a positive temperature characteristic and a value of the constant current is larger than a value obtained by subtracting a leakage current of the lower switch from a leakage current of the upper switch.

US Pat. No. 10,396,632

STATOR FOR ROTARY ELECTRIC MACHINE HAVING INTEGRALLY MOLDED TEMPERATURE SENSOR

TOYOTA JIDOSHA KABUSHIKI ...

1. A stator for a rotary electric machine, the stator comprising:a stator core;
a coil that is wound around the stator core;
a mold portion that includes a coil end portion, the coil end portion projecting outward from the stator core of the coil in an axial direction of the stator, a bulge portion being provided at an end portion of the mold portion in the axial direction of the stator, the mold portion being configured to mold the coil end portion, and a liquid cooling medium being supplied from a cooling medium supply member to an outer peripheral surface of the mold portion; and
a temperature sensor that is provided at the end portion of the mold portion in the axial direction of the stator, the temperature sensor being configured to measure a temperature of the coil, wherein
the bulge portion is provided bulging outward in the axial direction of the stator to surround at least part of a periphery of the temperature sensor,
the bulge portion is configured to restrain the liquid cooling medium from being supplied to the temperature sensor, and
the bulge portion is molded integrally with the mold portion,
wherein the stator core includes a plurality of teeth that are arranged apart from one another in a circumferential direction of the stator, and the coil is wound around each of the teeth of the stator core in a concentrated manner,
wherein a position of the bulge portion in the circumferential direction of the stator is a position between the coils that are adjacent to each other in the circumferential direction of the stator, and
wherein the bulge portion has an insertion hole that opens to one end surface in the axial direction of the stator, the temperature sensor being disposed in the insertion hole.

US Pat. No. 10,396,607

BUS RING UNIT

Suncall Corporation, Kyo...

1. A bus ring unit for electrically connecting pairs of ends of a plurality of stator coils respectively wound around a plurality of teeth of a stator, the pairs of ends appearing on one side in an axial direction of the stator, the bus ring unit comprising:single-phase bus rings for electrically connecting first ends of the pairs of ends of in-phase coils among the stator coils; and
a neutral-point bus ring for electrically connecting second ends of the pairs of ends of the stator coils, wherein
the neutral-point bus ring has a plurality of neutral-point-side rounded regions disposed at intervals in a circumferential direction so as to be positioned on a reference circle coaxial with the stator and positioned in a first axial position, and neutral-point-side connecting regions that are positioned in the first axial position and connect a circumferential edge of one neutral-point-side rounded region and an opposing circumferential edge of adjacent another neutral-point-side rounded region,
the neutral-point-side connecting regions have a pair of neutral-point-side projections that extend radially outward from the circumferential edge of one neutral-point-side rounded region and the opposing circumferential edge of adjacent another neutral-point-side rounded region and are connected to each other at distal ends,
the single-phase bus rings have a plurality of single-phase-side rounded regions disposed at intervals in the circumferential direction so as to be positioned on circles that are coaxial with the stator and have smaller diameters than the reference circle, and single-phase-side connecting regions for connecting a circumferential edge of one single-phase-side rounded region to an opposing circumferential edge of adjacent another single-phase-side rounded region,
the single-phase-side rounded regions have a single-phase-side reference part positioned in the first axial position and a single-phase-side edge part that includes the circumferential edge, wherein the single-phase-side edge part is displaced in the circumferential direction and in the axial direction relative to the single-phase-side reference part such that the circumferential edge is displaced in the circumferential direction relative to the neutral-point-side connecting regions and positioned in a second axial position that is farther from the stator than the first axial position is in the axial direction,
the single-phase-side connecting regions have a pair of single-phase-side projections, wherein each of the pair of single-phase-side projections is positioned in the second axial position, extend radially outward from the circumferential edge of one single-phase-side rounded region and the opposing circumferential edge of adjacent another single-phase-side rounded region beyond portions of the neutral-point-side rounded regions positioned in the first axial position, and are connected to each other at distal ends, and
the single-phase-side rounded regions have a single-phase-side transition part positioned between the single-phase-side reference part and the single-phase-side edge part, and the single-phase-side transition part is inclined so as to be positioned from the first axial position to the second axial position as it extends from the single-phase-side reference part toward the single-phase-side edge part in the circumferential direction.

US Pat. No. 10,396,605

WIRELESS POWER TRANSMITTER AND RECEIVER

LG ELECTRONICS INC., Seo...

1. A method of wireless power transfer, by a power transfer transferring power to a plurality of power receivers, the method comprising:a selection phase for detecting each of the plurality of power receivers and transmitting a digital ping to the each of the plurality of power receivers;
an introduction phase for receiving a request from the each of the plurality of power receivers for a free slot,
wherein the each of the plurality of power receivers is allocated free slots at a specific location,
wherein free slots allocated to different power receivers do not overlap with each other;
a configuration phase for providing a series of locked slots to the each of the plurality of power receivers;
a negotiation phase for receiving at least one negotiation data packet from the each of the plurality of power receivers using the series of locked slots;
a power transfer phase for transferring power to the each of the plurality of power receivers; and
a renegotiation phase for returning to the negotiation phase,
wherein the renegotiation phase further includes receiving a predetermined packet for returning to the negotiation phase from at least one power receiver among the plurality of power receivers,
wherein the predetermined packet includes:
information for a slot number allocated to the at least one power receiver, and/or
predetermined code information indicating a charge completion of the at least one power receiver.

US Pat. No. 10,396,593

RAPID SHUTDOWN OF PHOTOVOLTAIC SYSTEMS

SUNPOWER CORPORATION, Sa...

1. A photovoltaic system comprising:a photovoltaic panel comprising a first group of solar cells, the photovoltaic panel being configured to generate a panel voltage and a panel current; and
a control circuit configured to detect initiation of a rapid shutdown of the photovoltaic system by detecting a shutdown of a photovoltaic inverter, to lower the panel voltage below a safety level in response to detecting initiation of the rapid shutdown by switching out the first group solar cells, to monitor a line that connects the panel voltage to the photovoltaic inverter for a release trigger signal indicating resumption of normal operation, and to switch back the first group of solar cells to restore the panel voltage back to a normal operating level in response to detecting the release trigger signal on the line.

US Pat. No. 10,396,590

VARIABLE POWER ENERGY HARVESTING SYSTEM

TRIUNE SYSTEMS, LLC, Pla...

1. A single-chip system for harvesting energy from a variable output energy harvesting apparatus comprising:energy harvesting apparatus for providing energy input;
a switched mode power supply operably coupled to receive the input of the energy harvesting apparatus, and for providing a system output power signal; and
a control loop having control logic for dynamically adjusting energy harvesting apparatus input to the switched mode power supply, thereby regulating the system output power signal, wherein the control loop further comprises a maximum power point tracking (MPPT) mode and a mode that is configured to exceed an MPPT mode voltage level.

US Pat. No. 10,396,588

RECEIVER FOR WIRELESS POWER RECEPTION HAVING A BACKUP BATTERY

ENERGOUS CORPORATION, Sa...

1. A method for wireless power charging, the method comprising:when a receiver that is embedded within an electronic device is within a threshold distance from a transmitter:
receiving, by the receiver, a plurality of wireless power transmission waves transmitted by the transmitter, wherein each wireless power transmission wave of the plurality of wireless power transmission waves constructively interferes with at least one other wireless power transmission wave of the plurality of wireless power transmission waves at the receiver;
converting, by the receiver, the plurality of wireless power transmission waves into usable electricity; and
providing, by the receiver, the usable electricity to a backup battery of the receiver to provide a full or partial charge of the backup battery, wherein the backup battery of the receiver is distinct and separate from a battery of the electronic device; and
when the receiver is not within the threshold distance from the transmitter, and after providing the usable electricity to the backup battery to provide the full or partial charge of the backup battery, draining the backup battery to provide power to the battery of the electronic device.

US Pat. No. 10,396,587

TETHERLESS DEVICE CHARGING FOR CHAINED DEVICES

INTERNATIONAL BUSINESS MA...

1. A method comprising:receiving, at a first chargeable device, a second chargeable device in a second charging position relative to the first charging device;
wherein the first chargeable device comprises first receiving hardware configured to couple to a powered device when in a first charging position relative to the powered device;
wherein the first receiving hardware is further configured to receive an electrical charge from a power supply of the powered device when the first chargeable device is in the first charging position;
wherein the first chargeable device further comprises first charging hardware configured to receive second receiving hardware of the second chargeable device in the second charging position relative to the first chargeable device;
delivering, by way of the first charging hardware of the first chargeable device, an electrical charge from the powered device to the second chargeable device, responsive to the receiving, when the first chargeable device is in the first charging position and the second chargeable device is in the second charging position.

US Pat. No. 10,396,578

WIRELESS CHARGING SYSTEMS WITH MULTIPLE POWER RECEIVING DEVICES

Apple Inc., Cupertino, C...

1. An electronic device that is configured to receive wireless power from a power transmitting device, the electronic device comprising:a coil that is configured to receive wireless power signals from the power transmitting device;
a display; and
control circuitry configured to:
receive battery charge status information that is associated with a first electronic device that is present on the power transmitting device with the electronic device;
display the battery charge status information on the display; and
in accordance with receiving information indicating placement of a second electronic device on the power transmitting device while the first electronic device is present on the power transmitting device, forgo displaying battery charge status information of the first electronic device on the display.

US Pat. No. 10,396,571

ADAPTIVE OVERVOLTAGE PROTECTION FOR ADAPTIVE POWER ADAPTERS

FAIRCHILD SEMICONDUCTOR C...

13. A method comprising:setting an overvoltage protection threshold at a first level during startup of a power adapter that charges an electronic device;
when an overvoltage condition of the output voltage is not detected, providing an output voltage for charging the electronic device;
detecting the overvoltage condition of the output voltage by comparing the output voltage to the overvoltage protection threshold;
when the overvoltage condition of the output voltage is detected, disabling a drive signal to shut down the output voltage;
detecting, according to a magnitude of a feedback signal, an operating condition of a circuit that controls charging of the electronic device on a secondary side of a transformer of the power adapter; and
setting the overvoltage protection threshold at a second level that is higher than the first level after detecting that the circuit that controls the charging of the electronic device has a normal and proper operating condition.

US Pat. No. 10,396,550

ESD PROTECTION CHARGE PUMP ACTIVE CLAMP FOR LOW-LEAKAGE APPLICATIONS

TEXAS INSTRUMENTS INCORPO...

1. An electrostatic discharge (ESD) protection circuit, comprising:a clamp circuit, including:
a shunt transistor coupled between a first power supply node and a second power supply node, the shunt transistor including a control terminal, and
a sensing circuit configured to sense a voltage of the first power supply node, and to provide a control voltage signal to the control terminal to turn on the shunt transistor in response to a detected increase in the voltage of the first power supply node resulting from an ESD stress event; and
a charge pump circuit, including:
a charge pump capacitor, and
a switching circuit configured to charge the charge pump capacitor when the shunt transistor is off and to discharge the charge pump capacitor to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.

US Pat. No. 10,396,538

HINGED CLAMP FOR SPACER-DAMPER

Hubbell Incorporated, Sh...

1. A method of connecting a spacer-damper to a utility line comprising:positioning a spacer-damper to connect to a utility line, the spacer-damper including a first jaw, a second jaw pivotally connected to the first jaw, and a fastener having an axial length and a radial width, wherein the first jaw includes a first clamping surface defining a first clamping region, a first aperture receiving the fastener and allowing the fastener to move radially between a first section of the aperture and a second section of the aperture spaced laterally from the first section, a keeper surface positioned above the first section of the aperture, and a keeper pocket positioned above the second section of the aperture, and wherein the second jaw includes a second clamping surface and an open-ended second aperture;
engaging the first jaw with a conductor;
pivoting the second jaw from an open position to a closed position adjacent the conductor;
moving the fastener in the radial direction from the first section of the first aperture to the second section of the first aperture; and
tightening the fastener to secure the first and second jaws to the conductor.

US Pat. No. 10,396,516

SLIPRING WITH INTEGRATED HEATING UNIT

1. A slipring module comprising:an isolating body, wherein the isolating body is configured to rotate during operation about an axis of the slipring module and relative to an electrical contact;
at least one slipring track coupled directly to and around the isolating body, the at least one slipring track being electrically conductive; and
at least one heating element configured to generate heat and to increase a temperature of the at least one slipring track for bringing the at least one slipring track to an operation temperature and for removing humidity from the at least one slipring track,
wherein the at least one heating element is embedded into the isolating body under the at least one slipring track, and
wherein the at least one slipring track is electrically isolated from the at least one heating element.

US Pat. No. 10,396,513

PLUG ASSEMBLY AND RECEPTACLE ASSEMBLY WITH TWO ROWS

Molex, LLC, Lisle, IL (U...

1. A plug assembly, comprising:a body with a first flange and a second flange; and
a mating blade positioned between the first and second flange and having a mating end and a body end, the mating blade including a first side and a second side, the first side facing the first flange, the first side having a first pad row, a second pad row and a third pad row, the second pad row being furthest from the mating end and the first and second pad row having pads arranged in a differential signal pattern and the third pad row being positioned between the first and second pad rows and the second side having a fourth pad row, a fifth pad row and a sixth pad row, the fourth and fifth pad rows having pads arranged in a differential signal pattern, the sixth pad row being positioned between the fourth and fifth pad rows and the fifth pad row being furthest from the mating end, wherein the first flange covers the first, second and third pad rows and the second flange covers the fifth pad row but substantially does not cover the fourth and sixth pad rows.

US Pat. No. 10,396,509

ELECTRICAL CONNECTOR AND ELECTRICAL CONNECTOR DEVICE WITH AN ELASTIC ARM-SHAPED MEMBER THAT ENGAGES A MATING CONNECTOR

DAI-ICHI SEIKO CO., LTD.,...

1. An electrical connector which a mating connector having a terminal portion of a signal transmission medium coupled thereto fits in, the electrical connector comprising:a contact member extending in a fit-in direction of the mating connector and arranged so as to be able to make contact with an electrode part of the mating connector; and
a conductive shell member formed of a plate-shaped metal member having a wall surface part in a plate thickness direction and being arranged in a state of surrounding at least part of the contact member, wherein
the conductive shell member is provided with an elastic arm-shaped member which makes contact with the mating connector when fitting in the mating connector and elastically displaces in a direction orthogonal to the fit-in direction,
the elastic arm-shaped member is provided with an engaging piece which makes contact with the mating connector, wherein,
after protruding from the conductive shell member to the fit-in direction or a direction opposite thereto, the elastic arm-shaped member extends in a state of being folded to a direction opposite to a protruding direction,
the engaging piece has a connector contact surface and a shell contact surface, the connector contact surface comes to make contact with a contact face of the mating connector at a depth of the engaging piece in the fit-in direction when an external force is applied to the mating connector in a fit-in state in a removing direction opposite to the fit-in direction, and the shell contact surface is provided to oppose the connector contact surface and comes to make contact with a part of the conductive shell member when the contact face of the mating connector makes contact with the connector contact surface to restrict movement of the mating connector, and
the wall surface part in the plate thickness direction forming the connector contact surface and the shell contact surface to extend approximately orthogonally to the direction in which the elastic arm-shaped member is extending after being folded.

US Pat. No. 10,396,499

ELECTRIC CONNECTOR

Sure-Fire Electrical Corp...

1. An electric connector, comprising:an insulating body comprising an abutting part, and the abutting part comprising an abutting chamber formed inside thereof, and the abutting chamber provided with a plurality of terminal slots formed on upper and lower sidewalls thereof, wherein the abutting part comprises two arms extended from two opposite rear sides thereof in the same direction, and an accommodation space formed between the two arms;
a terminal set comprising upper and lower rows of conductive terminals with the predetermined lengths and smaller widths, and a terminal holder formed integrally with the upper and lower rows of the conductive terminals, and combined between the two arms, wherein the each of upper and lower rows of the conductive terminals comprises a contact part, a solder part formed behind the contact part thereof and exposed to the accommodation space between the two arms, and a terminal arm comprising a predetermined length and a smaller width, and formed between the contact part and the solder part thereof, wherein the contact parts are inserted through the terminal slots corresponding thereto and into the abutting chamber, respectively, and a length of each of the plurality of conductive terminals is lower than a length of the insulating body, and a length of the solder part of each of the plurality of conductive terminals is lower than a length of each of the two arms; and
a signal transmission part electrically connected to the solder parts of the terminal set, and comprising an abutting side electrically connected to the solder parts, and a transmission side formed behind the abutting side and configured to transmit electrical signal to an external device.

US Pat. No. 10,396,491

ALIGNMENT STRUCTURES FOR CHIP MODULES

FOXCONN INTERCONNECT TECH...

1. A coupling system comprising:a first connecting unit including:
an insulative enclosure defining a first mating surface and a second mating surface perpendicular to each other;
a printed circuit board received within the enclosure;
an electrical connector mounted upon the printed circuit board and operationally exposed upon the first mating surface;
a pair of chip modules for extremely high speed communication mounted upon the printed circuit board and operationally facing toward the second mating surface in a hidden manner; and
a second connecting unit, wherein said second connecting unit includes another enclosure with a printed circuit board assembly received within said another enclosure, and defines a first mating face intimately confronting the first mating surface, and a second mating face perpendicular to the first mating face and intimately confronting the second mating surface;
wherein the electrical connector is equipped with magnetic elements; and
wherein one of the electrical connectors of the first connecting unit and the second connecting unit is of a pogo type and the other is of a stationary type.

US Pat. No. 10,396,475

VICE-TYPE TERMINAL BLOCK FOR INTERCONNECTING TWO THIMBLES AND ASSOCIATED CONNECTION

1. A vice-type terminal block for electrically connecting a pair of lugs by clamping them together, each lug comprising a barrel extending along an axis in a centered manner, and a flange connected to said barrel and extending radially relative to said barrel, said flange having, on an opposite side to where said barrel is located, an electrical contact surface normal to said axis, the vice-type terminal block comprising:two opposing plates and a clamping system for moving the two plates towards one another, wherein each plate comprises a slot for receiving one of said lugs thereby positioning the flange of each respective lug on one side of the respective plate and also between the two opposing plates, also thereby positioning the barrel of each respective lug on the other side of the plate opposite the one side, and
a means for supporting the pair of lugs such that their electrical contact surfaces face one another and are aligned.

US Pat. No. 10,396,473

BATTERY TERMINAL CONNECTOR WITH DIFFERENT SHAPES FOR POSITIVE AND CABLE AND NEGATIVE CABLE

1. A terminal connector comprising:a positive connector connectable to a positive terminal of a battery, the positive connector also having a first end of a first shape connectable to a positive cable; and
a negative connector connectable to a negative terminal of the battery, the negative connector also having a first end of a second shape connectable to a negative cable,
wherein the positive cable has an end of a third shape connectable to the first end of the positive connector;
wherein the negative cable has an end of a fourth shape connectable to the first end of the negative connector; and
wherein the first shape is different from the second shape and the third shape is different from the fourth shape so that the first end of the positive connector is not connectable to the fourth shape end of the negative cable, and the first end of negative connector is not connectable to the third shape end of the positive cable.

US Pat. No. 10,396,470

WIRELESS SYSTEM ARCHITECTURE WITH DEPENDENT SUPERSTRATE FOR MILLIMETER-WAVE PHASED-ARRAY ANTENNAS

Peraso Technologies Inc.,...

1. A wireless communications assembly, comprising:a primary board including:
(i) an upper surface bearing a radio controller, and defining a set of control contacts for connection to respective ports of the radio controller;
(ii) a lower surface opposite the upper surface, the lower surface defining a plurality of antenna contacts;
(iii) a plurality of conduits extending through the primary board from the antenna contacts to the control contacts; and
(iv) an antenna ground plane;
a superstrate board including:
(i) an inner surface facing the lower surface of the primary board;
(ii) an outer surface opposite the inner surface;
(iii) a phased array of antenna elements disposed on one of the inner surface and the outer surface; and
a surface-mount package between the lower surface and the inner surface for connecting a subset of the antenna contacts to the antenna elements and to provide a substrate between the antenna elements and the antenna ground layer.

US Pat. No. 10,396,467

METHOD TO BUILD ASYMMETRICAL TRANSMIT/RECEIVE SWITCH WITH 90 DEGREES IMPEDANCE TRANSFORMATION SECTION

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:an impedance matching network comprising a first port, a second port, and a third port;
a first switch circuit coupled between said first port and a circuit ground potential; and
a second switch circuit coupled between said second port and said circuit ground potential, wherein (i) said impedance matching network provides a first impedance value for said first port and for said third port when said second switch circuit is set to connect said second port to said circuit ground potential, (ii) said impedance matching network provides a second impedance value for said second port and for said third port when said first switch circuit is set to connect said first port to said circuit ground potential, and (iii) the first impedance value and the second impedance value are asymmetrical.

US Pat. No. 10,396,464

POWER TRANSMITTING COMMUNICATION UNIT AND POWER TRANSMITTING COMMUNICATION DEVICE

YAZAKI CORPORATION, Toky...

1. A power transmitting communication unit comprising:a base material;
a flat plate-like first electrode that is arranged on the base material and transmits electric power for supplying a load in a non-contact manner;
a flat plate-like second electrode that is arranged side by side with the first electrode on the base material, and transmits electric power for supplying the load in a non-contact manner; and
a slot antenna that transmits or receives radio waves via a slit formed on at least one of the first electrode and the second electrode, the radio waves being for communication and different from the electric power supply to the load.

US Pat. No. 10,396,463

ANTENNA DEVICE

Ricoh Company, Ltd., Tok...

1. An antenna device formed by winding a conductive wire around a magnetic member, the conductive wire forming a coil having a central axis,wherein the magnetic member comprises a plurality of magnetic-member individual pieces spaced apart from each other, including a first row of magnetic-member individual pieces, the first row being arranged in a direction of the central axis of the coil, and
wherein the plurality of magnetic-member individual pieces further includes a second row of magnetic member-individual pieces, the second row being arranged in a direction of the central axis of the coil and being adjacent to the first row.

US Pat. No. 10,396,462

C-BAND CONFORMAL ANTENNA USING MICROSTRIP CIRCULAR PATCHES AND METHODS THEREOF

Wipro Limited, Bangalore...

1. A conformal antenna comprising:a dielectric substrate;
a plurality of circular micro strip antenna patches arranged on the dielectric substrate and coupled to a coaxial feed circuit, wherein the conformal antenna is configured to operate in a frequency range of about 4.0 GHz to about 8.0 GHz;
a memory for storing a plurality of weights;
a controller coupled to the memory, wherein the controller is configured to assign each of the plurality of weights to a corresponding one of the plurality of circular micro strip antenna patches for balancing a signal received from each of the plurality of circular micro strip antenna patches and generate a weight-adjusted signal;
a summation circuit coupled to the controller and the memory for receiving the weight-adjusted signals and configured to sum the weight-adjusted signals and output a summed signal;
a frequency controller circuit coupled to the summation circuit to receive the summed signal and configured to provide an output signal in the frequency range of about 4.0 GHz to about 8.0 GHz; and
an adaptive filter coupled to the frequency controller circuit, the adaptive filter configured to receive the output signal and apply one or more adaptive algorithms to output a first portion of the output signal and to provide a second portion of the output signal to a feedback loop.

US Pat. No. 10,396,459

RADAR APPARATUS AND CONTROLLING METHOD THEREOF

DENSO CORPORATION, Kariy...

1. A radar apparatus mounted on a vehicle, the apparatus comprising:a transmission antenna member which transmits a radar wave;
a transmitting section including;
an oscillator which generates a radio wave necessary to transmit the radar wave; and
a phase shifter which changes a phase of the radio wave generated at the oscillator and supplies, the transmission antenna member, to the radio wave whose phase is changed;
controlling means for controlling the phase shifter;
a reception antenna member which receives a reflected wave of the radar wave; and
a reception section which generates a reception signal including the reflected wave received through the reception antenna section,
wherein the controlling means controls the phase of the radio wave such that, of the received signals generated at the receiving section, a first leak component is subtracted from the received signals by using a second leak component, the first leak component indicating the reflection wave reflected from an object other than a target being detected outside the vehicle, the second leak component indicating the radio wave leaking from the transmitter section to the receiving section.

US Pat. No. 10,396,457

CALIBRATED CIRCUIT BOARDS AND RELATED INTEGRATED ANTENNA SYSTEMS HAVING ENHANCED INTER-BAND ISOLATION

CommScope Technologies LL...

1. An active beam scanning antenna, comprising:a plurality of radiating units that are configured to transmit and receive signals in a first frequency band, each radiating unit including a plurality of radiating elements;
at least one array of radiating elements that are configured to transmit and receive signals in a second frequency band that is different than and does not overlap with the first frequency band; and
a calibration circuit board, the calibration circuit board comprising:
a plurality of transmission line segments that are connected to the respective radiating units;
a plurality of couplers that are provided along the respective transmission line segments; and
a filter coupled along and associated with each respective transmission line segment.

US Pat. No. 10,396,453

ANTENNA, ROTATING UNIT, WIRELESS COMMUNICATION DEVICE AND ROTATING CONTROLLING METHOD

AMBIT MICROSYSTEMS (SHANG...

1. A rotating unit for controlling an antenna to rotate, the rotating unit comprising:an electromagnetic element; and
a rotating circuit electrically coupled with the electromagnetic element;
wherein the rotating circuit controls the electromagnetic element to generate a magnetic force for controlling a rotation of the antenna;
wherein the antenna comprises a housing, an antenna end, a rotating end, and a rotating shaft, the antenna end is positioned at a first end of the housing, the rotating end is positioned at a second end of the housing opposite to the first end, the rotating shaft is positioned between the antenna end and the rotating end, the electromagnetic element generates a magnetic force for controlling the rotating end to rotate around the rotating shaft.

US Pat. No. 10,396,448

RADOME END CAP WITH BULK HEAD MOUNT CONNECTOR

CommScope Technologies LL...

1. An end cap assembly for connecting a cable to an end cap, comprising:an end cap including one or more flanges, each of the one of more flanges include a plurality of edges defining a cavity, the plurality of edges being configured to mate with a portion of a connector;
a flange nut including a first plurality of serrations configured to mate with a second plurality of serrations on an outside of the end cap; wherein the flange nut and the flange are formed so as to allow for attachment of the cable to the end cap.

US Pat. No. 10,396,440

DYNAMIC-RANGE ACTIVE FLAT-TORUS SPLIT-PHASE AGGREGATOR

1. An energy harvesting antenna that is characterized in:a. having two or more largely overlapping coils arranged in a largely flat torus shape;
b. said coils measure largely 85 millimeters in length, 50 millimeters in width, arranged as with conductive sides largely 7 millimeters wide with a gap of largely 6 millimeters between two phase terminals [104-105], and a neutral terminal attached to a center of the coils [107]; thickness of said conductive overlapping coils measures largely 0.31 millimeters per two overlapping coils;
c. wherein, said coils being covered by and separated by thin polymer high-dielectric laminates, measuring largely 0.09 millimeter for external surfaces and 0.13 millimeter between said coils;
d. having a split phase;
e. wherein, the two coils start at two origin points, then largely overlap until converging in a middle grounding point;
wherein, EM waves induce AC current in the split phase in opposite directions due to the middle grounding point, such that at any given time the voltage at the two origin points, with respect to the middle grounding point, is of opposite polarity.

US Pat. No. 10,396,439

ANTENNA DEVICE AND COMMUNICATIONS DEVICE

Panasonic Intellectual Pr...

1. A communication device having a generally rectangular planar shape, the communication device comprising:a display panel;
a cover including a metal surface;
a slit arranged in a side wall of the cover;
a wound coil arranged between the display panel and the cover;
a camera; and
a battery,
wherein the slit, the wound coil, and the camera are positioned in an upper portion along a longitudinal direction of the generally rectangular planar shape of the communication device, and the battery is positioned in a lower portion along the longitudinal direction of the generally rectangular planar shape of the communication device.

US Pat. No. 10,396,431

SYSTEM AND METHOD FOR INTEGRATING AND ADAPTING HYBRID ANTENNA APERTURE WITHIN FULLY METALLIC CHASSIS BASED ON CHASSIS OPERATING CONFIGURATION

Dell Products, LP, Round...

1. An information handling system operable to transition between a plurality of positional configurations comprising:a metallic case containing components of the information handling system including a base housing metal chassis operably connected to a display housing metal chassis via a hinge;
the base housing metal chassis and display housing metal chassis moveable with respect to one another around the hinge according to a plurality of positional configurations;
the base housing metal chassis forming a back edge of a base housing;
a base antenna aperture platform extending from the back edge and forming a portion of the base housing metal chassis;
a base antenna aperture disposed within the base antenna aperture platform; and
a radio frequency front end to transmit a communications signal via the base antenna aperture when the base housing metal chassis and display housing metal chassis are placed in the plurality of positional configurations.

US Pat. No. 10,396,407

SECONDARY BATTERY INTERNAL TEMPERATURE ESTIMATION DEVICE AND SECONDARY BATTERY INTERNAL TEMPERATURE ESTIMATION METHOD

FURUKAWA ELECTRIC CO., LT...

1. A device comprising:a sensor for measuring an external temperature of a secondary battery of a vehicle;
a processor, wherein the processor is communicatively coupled to the sensor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
estimating an internal temperature of the secondary battery of the vehicle on the basis of a relational equation showing a relationship between an external temperature of the secondary battery of the vehicle and an internal temperature of the secondary battery of the vehicle;
calculating element values of an equivalent circuit of the secondary battery, wherein the equivalent circuit of the secondary battery comprises at least a solution resistance and a reaction resistance;
determining coefficients of the relational equation on the basis of the element values of the equivalent circuit, wherein the determining the coefficients comprises determining, on the basis of one or more of the element values, a first coefficient of the relational equation applicable to the solution resistance and determining, on the basis of one or more of the element values, a second coefficient of the relational equation applicable to the reaction resistance; and
applying the coefficients obtained by the determining, wherein the estimating comprises estimating the internal temperature of the secondary battery on the basis of the relational equation to which the coefficients have been applied by the applying.

US Pat. No. 10,396,390

FUEL CELL STACK FOR VEHICLE

HONDA MOTOR CO., LTD., T...

1. A fuel cell stack for a vehicle, comprising:a stack body in which a plurality of power generating cells configured to generate electric power by electrochemical reaction of fuel gas and oxidant gas are stacked; and
a stack casing housing the stack body and mounted within a vehicle, the stack casing comprising:
an upper panel which constitutes an upper surface part of the stack casing, the upper panel including:
an outer plate; and
an inner plate arranged between the outer plate and the stack body in a height direction along a height of the vehicle to constitute a flow passage between the outer plate and the inner plate such that the flow passage communicates with an interior of the stack casing and an exterior of the stack casing.

US Pat. No. 10,396,388

SYSTEM AND METHOD FOR STORING AND RELEASING ENERGY

HYDROGENIOUS TECHNOLOGIES...

1. A system for releasing energy in a form of hydrogen comprising:an unloading unit for unloading hydrogen from a loaded carrier medium;
a heat generation unit for generating heat;
a heat storage unit for storing the heat generated by means of the heat generation unit, wherein the heat storage unit is connected with the unloading unit in order to supply heat;
a power generation unit for generating electric power, wherein the power generation unit is connected with the heat generation unit in order to supply electric power for heat generation, wherein the heat from the heat storage unit is delivered directly to the unloading unit.

US Pat. No. 10,396,387

CARBON NANOTUBE BASED MICROBIAL FUEL CELLS AND METHODS FOR GENERATING AN ELECTRIC CURRENT

1. A microbial fuel cell, comprising:a housing comprising one or more cell compartments with an anode compartment having an anode in a side, and a cathode compartment having a cathode on another side separated by a cation exchange membrane, wherein the cation exchange membrane is a sulfonated tetrafluorethylene based fluoropolymer-copolymer;
wherein the anode is a glassy carbon coated with a multi-walled carbon nanotube/tin oxide nanocomposite configured to attach a plurality of Escherichia coli bacteria, immersed in a solution containing glucose and the cathode is a platinum electrode immersed in another solution containing hexacyano ferrate, and the anode and cathode are electrically connected to one another via a resistance to generate electricity, wherein the power density of the microbial fuel cell is greater than 1400 mW/m2.

US Pat. No. 10,396,380

ON-VEHICLE FUEL CELL SYSTEM

HONDA MOTOR CO., LTD., T...

1. An on-vehicle fuel cell system to be mounted in a fuel cell vehicle, the system comprising:a fuel cell that generate electricity through electrochemical reaction of oxidant gas fed to a cathode side with fuel gas fed to an anode side with an electrolyte membrane being located between the cathode side and the anode side;
an oxidant gas feeding pipe that feeds the oxidant gas to the fuel cell;
an oxidant exhaust gas discharge pipe that discharges, from the fuel cell, oxidant exhaust gas being the oxidant gas at least partially used in the cathode side;
a fuel gas feeding pipe that feeds the fuel gas to the fuel cell;
a fuel exhaust gas discharge pipe that discharges, from the fuel cell, fuel exhaust gas being the fuel gas at least partially used in the anode side;
a mixed exhaust gas discharge pipe that connects the oxidant exhaust gas discharge pipe to the fuel exhaust gas discharge pipe to discharge mixed exhaust gas of the oxidant exhaust gas and the fuel exhaust gas; and
a dilution unit connected to the mixed exhaust gas discharge pipe, into which the mixed exhaust gas is introduced, wherein
the dilution unit includes a stirring chamber that expands from an outlet of the mixed exhaust gas discharge pipe and communicates with the mixed exhaust gas discharge pipe, and
an opening that takes in air into the stirring chamber is formed in a lower face of the stirring chamber.

US Pat. No. 10,396,379

COOLING SYSTEM OF FUEL CELL VEHICLE

Hyundai Motor Company, S...

1. A cooling system of a fuel cell vehicle, comprising:a stack in which a plurality of fuel cells are laminated;
a manifold in which the stack is disposed, and an inside of which cooling water flows to exchange heat with the stack;
a flow control valve installed in the manifold, and is opened and closed to exchange heat of cooling water with the stack based on a temperature of the stack; and
a cooling water flow channel configured to guide the cooling water into the manifold, and which is dually arranged to exchange heat with the stack,
wherein the cooling water flow channel includes:
a normal cooling water flow channel connected directly to at least one of the stack to discharge the cooling water;
a low cooling water flow channel connected to the normal cooling water flow channel and configured to discharge the cooling water to the normal cooling water flow channel based on the temperature of the stack; and
a connector connecting the normal cooling water flow channel and the low cooling water flow channel,
wherein a temperature of the cooling water flowing through the low cooling water flow channel is kept lower than a temperature of the cooling water flowing through the normal cooling water flow channel with the stack in operation, and
wherein the flow control valve is installed in the connector to adjust a flow of the cooling water from the low cooling water flow channel to the normal cooling water flow channel based on the temperature of the stack.

US Pat. No. 10,396,377

FUEL CELL DEVICE

KYOCERA Corporation, Kyo...

1. A fuel cell device comprising:a fuel cell configured to generate power using a fuel gas and an oxygen-containing gas, the power supplied to an external load;
a fuel gas supply device configured to supply the fuel gas to the fuel cell;
an oxygen-containing gas supply device configured to supply the oxygen-containing gas to the fuel cell;
a combusted space where the fuel gas not used for power generation and wasted from the fuel cell is combusted;
an igniter configured to combust the fuel gas not used for power generation and wasted from the fuel cell; and
a controller configured to control operation of the fuel gas supply device, the oxygen-containing gas supply device, and the igniter,
wherein the controller is configured to allow the fuel gas supply device and the oxygen-containing gas supply device to change supply amounts of the fuel gas and the oxygen-containing gas in accordance with changes in power as required by the external load, and
wherein the controller is further configured to allow the fuel gas supply device and the oxygen-containing gas device to supply the fuel gas and the oxygen-containing gas supplied to the fuel cell in a decreased supply amount less than a supply amount to be set in accordance with a decreased power as required by the external load, and configured to cause the igniter to start operation if the power required by the external load decreases and flameout of the combustion in the combusted space is recognized.

US Pat. No. 10,396,371

CONCAVE FUEL CELL KNOCK OUT DRAIN

Ford Global Technologies,...

16. A water removal system for a fuel cell comprising:a reservoir in fluid connection with the fuel cell, the reservoir having a concave, generally conically-shaped bottom wall forming an apex within a cavity of the reservoir, the reservoir further including a valve receptacle extending into the cavity of the reservoir, the valve receptacle defining a drain aperture and an outlet orifice having a bottom edge disposed at the apex of the bottom wall.

US Pat. No. 10,396,362

ELECTRODE ACTIVE MATERIAL SLURRY, PREPARATION METHOD THEREOF, AND ALL-SOLID SECONDARY BATTERY COMPRISING THE SAME

Hyundai Motor Company, S...

1. An electrode active material slurry comprising:a clustered complex and a slurry,
wherein the clustered complex comprises an electrode active material, a solid electrolyte, a conductive material, and a first binder, and the slurry comprises a solvent and a second binder,
wherein the first binder is applied on a surface of the electrode active material, and the second binder is present between the electrode active materials,
wherein the first binder comprises polytetrafluoroethylene (PTFE).

US Pat. No. 10,396,345

APPARATUS AND METHOD FOR MANUFACTURING ELECTRODE

LG CHEM, LTD., Seoul (KR...

1. A method for manufacturing an electrode, the method comprising:a step of preparing a collector;
a coating step of applying an electrode active material to one surface or both surfaces of the collector to manufacture an initial electrode; and
a first cutting step of cutting the initial electrode coated with the electrode active material to manufacture a plurality of middle-stage electrodes,
wherein each of the middle-stage electrodes comprises two coating portions that are areas coated with the electrode active material and a non-coating portion that is an area which is not coated with the electrode active material, the coating portions are spaced apart from each other,
wherein, in the first cutting step, the initial electrode is cut so that for at least one of the plurality of middle-stage electrodes, the two coating portions have an overall length that is different than an overall length of two coating portions for at least one other middle-stage electrode, and
wherein, in each of the middle-stage electrodes, each of the two coating portions has a same length.

US Pat. No. 10,396,344

DRYING METHOD AND BATTERY MANUFACTURING METHOD

TOYOTA JIDOSHA KABUSHIKI ...

1. A drying method that dries an electrode layer including a binder and a solvent, the drying method comprising:a first step of blowing a gas onto a first area of the electrode layer to volatilize the solvent, the electrode layer being coated on a base material; and
a second step of blowing a gas onto a second area of the electrode layer to volatilize the solvent, the second area being located around the first area,
wherein the first area and the second area are arranged in a staggered manner,
in the first step, by non-uniformly volatilizing the solvent, the binder diffuses such that a concentration of the binder in the first area is higher than a concentration of the binder in the second area on a surface of the electrode layer, and
in the second step, by non-uniformly volatilizing the solvent, the binder diffuses such that the concentration of the binder in the first area is lower than the concentration of the binder in the second area on the surface of the electrode layer.

US Pat. No. 10,396,340

DEVICE AND METHOD FOR MAKING A BATTERY SAFE

SAFT, Bagnolet (FR)

1. A safety device for a battery comprising a positive electrical terminal and a negative electrical terminal, each being adapted to be connected to an electrical connector, the battery and the electrical connector being configured so that the electrical connector can be connected to each of the positive and negative electrical terminals at first and second alternate connection positions, the safety device comprising a safety member adapted to be selectively positioned in:a first safety position wherein the safety member prevents the connection of an electrical connector in the second connection position of the positive electrical terminal and in the first connection position of the negative electrical terminal; or
a second safety position wherein the safety member prevents the connection of an electrical connector in the first connection position of the positive electrical terminal and in the second connection position of the negative electrical terminal.

US Pat. No. 10,396,334

BATTERY MODULE AND BATTERY PACK COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A battery module, comprising:a plurality of secondary batteries stacked to each other, each including an electrode assembly, a case and electrode leads; and
a terminal bus bar having a plate-like coupling unit, wherein electrode leads of the same polarity provided in three or more secondary batteries of the plurality of secondary batteries stacked to each other are coupled to the plate-like coupling unit,
wherein two or more electrode leads of the same polarity are stacked to each other and are in contact with one end of the plate-like coupling unit,
wherein each of the other one or more of said electrode leads of the same polarity is in direct contact with the other end of the plate-like coupling unit,
wherein each of said electrode leads of the same polarity is partially bent to form a bent portion, and an end of the bent portion is in contact with the terminal bus bar such that the terminal bus bar is located between the bent portion and the corresponding case, and
wherein the plate-like coupling unit of the terminal bus bar has a protrusion protruding outwards on an outer surface thereof, and the protrusion is interposed between the two or more electrode leads of the same polarity and the other one or more electrode leads of the same polarity such that the two or more electrode leads of the same polarity and the other one or more electrode leads of the same polarity are connected to flat portions of the outer surface of the plate-like coupling unit adjacent to the protrusion.

US Pat. No. 10,396,325

BATTERY MODULE AND BATTERY PACK COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A battery module comprising:a housing comprising a first housing and a second housing, which are coupled to each other to form a accommodation space;
a plurality of secondary batteries accommodated in the accommodation space;
a bolt comprising a screw portion and a bolt head arranged at an end of the screw portion, the bolt being configured to fasten the first housing and the second housing to each other by being mounted such that the screw portion penetrates the first housing to be screw-coupled to the second housing, and that the bolt head is caught by the first housing; and
an O-ring mounted to be interposed between the first housing and the bolt head,
wherein the O-ring comprises:
a hollow pierced such that the screw portion is inserted therein; and
a recognition protrusion formed to protrude in a radial direction of the bolt head as compared with the bolt head.

US Pat. No. 10,396,323

ELECTRICAL BOX FOR BATTERY PACK AND BATTERY PACK STRUCTURE USING SAME

LG CHEM, LTD., Seoul (KR...

1. An electrical box for a battery pack, the electrical box embedded in a battery pack structure in which one or more battery modules are received and comprising:a housing configured to receive a battery protection circuit therein,
wherein the housing comprises a lower housing and an upper housing, the upper housing having a central panel, a vertical wall extending from opposite edges of the central panel and flanges that contact an inner frame constituting a load-bearing structure of the battery pack structure and are configured to support the inner frame,
wherein the flanges comprise:
a first flange connected to each vertical wall, the first flange having a first edge connected to a top edge of the respective vertical wall and a second edge spaced from the first edge; and
a second flange connected to and extending downwardly from a third edge of each first flange, the third edge being between the first edge and the second edge.

US Pat. No. 10,396,317

ULTRASONIC WELDING APPARATUS AND SECONDARY BATTERY WITH ENHANCED ELECTRODE STRUCTURE

LG Chem, Ltd., (KR)

1. A secondary battery, comprising:an electrode assembly in which a cathode plate provided with a cathode tab, an anode plate provided with an anode tab, and a separator are stacked in turn;
a pouch for receiving the electrode assembly;
a cathode lead welded and electrically coupled to the cathode tab at a second welding surface; and
an anode lead welded and electrically coupled to the anode tab at a first welding surface,
wherein a first density of welding points, formed at the first welding surface between the anode lead and the anode tab, is higher than a second density of welding points, formed at the second welding surface between the cathode lead and the cathode tab;
wherein each of the first welding surface and the second welding surface includes a central axis and a plurality of the welding points arranged in a plurality of columns extending perpendicular to the central axis, each of the columns being defined by a linear arrangement of a plurality of discrete welding points;
wherein a number of the welding points at the first welding surface gradually increases from the central axis of the first welding surface outwardly to both sides of the first welding surface, and a number of the welding points at the second welding surface gradually increases from the central axis of the second welding surface outwardly to both sides of the second welding surface; and
wherein, for each of the first and second welding surfaces, a first spacing between an outermost one of the columns and a first one of the columns disposed directly adjacent the outermost column is less than a second spacing between a central one of the columns and a second one of the columns disposed directly adjacent the central column, the second column being disposed between the central column and the first column.

US Pat. No. 10,396,312

ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. An organic light emitting diode (OLED) display comprising:a substrate;
an organic light emitting diode disposed on the substrate;
a first inorganic layer disposed on the substrate and covering the organic light emitting diode, an edge of the first inorganic layer directly contacting the substrate;
a second inorganic layer disposed on the first inorganic layer and contacting the first inorganic layer at an edge of the second inorganic layer, the second inorganic layer entirely and directly contacting the first inorganic layer;
an organic layer disposed on the second inorganic layer and covering a relatively smaller area than the second inorganic layer; and
a third inorganic layer disposed on the organic layer, covering a relatively larger area than the organic layer, and contacting the first inorganic layer and the second inorganic layer at an edge of the third inorganic layer.

US Pat. No. 10,396,306

ELECTROLUMINESCENT DEVICE CAPABLE OF IMPROVING LUMINOUS EFFICIENCY BY PREVENTING A LEAKAGE CURRENT AND IMPROVING ELECTRON TRANSPORT PROPERTIES AND A DISPLAY DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. An electroluminescent device, comprisinga first electrode;
a hole transport layer disposed on the first electrode;
an emission layer disposed on the hole transport layer and comprising at least two light emitting particles;
a first electron transport layer disposed on the emission layer and comprising at least two inorganic-organic composite particles;
a second electron transport layer disposed on the first electron transport layer and comprising at least two inorganic oxide particles; and
a second electrode disposed on the second electron transport layer,
wherein the first electron transport layer has a lower work function than the second electron transport layer.

US Pat. No. 10,396,298

IRIDIUM COMPLEX AND ORGANIC LIGHT-EMITTING DIODE USING THE SAME

National Tsing Hua Univer...

1. An iridium complex represented by general formula (I):
wherein
A1, A2, A3, A4 and A5 are each independently a 5-membered unsaturated ring or a 6-membered unsaturated ring.

US Pat. No. 10,396,295

CONDENSED CYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A condensed cyclic compound represented by Formula 1:Ar1-(L1)a1-Ar2  Formula 1

wherein, in Formulae 1, 2-3, and 3-1,
Ar1 is a group represented by Formula 2-3,
Ar2 is a group represented by Formula 3-1,
L1 is selected from a substituted or unsubstituted C6-C60 arylene group, a substituted or unsubstituted C1-C60 heteroarylene group, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group,
a1 is selected from 0, 1, 2, and 3,
X21 is selected from O, S, and Se,
X31 is selected from a single bond, O, S, N(R33), C(R33)(R34), Si(R33)(R34), Ge(R33)(R34), and P(?O)(R33),
A21, A31, and A32 are each independently selected from a C5-C30 carbocyclic group and a C1-C30 heterocyclic group,
R21 to R23 and R31 to R34 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C7-C60 aryl alkyl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted C2-C60 heteroaryl alkyl group, a substituted or unsubstituted C1-C60 hetero aryloxy group, a substituted or unsubstituted C1-C60 hetero arylthio group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —N(Q1)(Q2), —Si(Q1)(Q2)(Q3), and —B(Q1)(Q2),
R22 and R23 are optionally linked to form a substituted or unsubstituted C5-C30 carbocyclic group or a substituted or unsubstituted C1-C30 heterocyclic group,
R33 and R34 are optionally linked via a first linking group to form a substituted or unsubstituted C5-C30 carbocyclic group or a substituted or unsubstituted C1-C30 heterocyclic group,
b21, b31, and b32 are each independently selected from 1, 2, 3, 4, 5, 6, 7, and 8,
Q1 to Q3 are each independently selected from:
hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, substituted with at least one selected from deuterium, a C1-C60 alkyl group, and a C6-C60 aryl group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C7-C60 arylalkyl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a C2-C60 heteroaryl alkyl group, a C1-C60 hetero aryloxy group, a C1-C60 hetero arylthio group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group; and
a C6-C60 aryl group, substituted with at least one selected from deuterium, a C1-C60 alkyl group, and a C6-C60 aryl group, and
indicates a binding site to a neighboring atom.

US Pat. No. 10,396,294

CARBAZOLE COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A carbazole compound represented by Formulae 1A or 1B
wherein in Formulae 1A and 1B,
A is -(L1)a1-(E1)b1,
L1 is selected from a substituted or unsubstituted C6-C60 arylene group, and a substituted or unsubstituted C1-C60 heteroarylene group;
in Formula 1A, E1 is selected from:
a pyrrolyl group, an imidazolyl group, a pyrazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoimidazolyl group, a thiazolyl group, an isothiazolyl group, a benzothiazolyl group, an isoxazolyl group, an oxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, a carbazolyl group, an imidazopyrimidinyl group, and an imidazopyridinyl group; and
a pyrrolyl group, an imidazolyl group, a pyrazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoimidazolyl group, a thiazolyl group, an isothiazolyl group, a benzothiazolyl group, an isoxazolyl group, an oxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, a carbazolyl group, an imidazopyrimidinyl group, and an imidazopyridinyl group, each substituted with at least one Ar1,
wherein Ar1 is selected from
a phenyl group, a pentalenyl group, an indenyl group, a naphthyl group, an azulenyl group, a heptalenyl group, an indacenyl group, an acenaphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenalenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthrenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a naphthacenyl group, a picenyl group, a perylenyl group, a pentaphenyl group, a hexacenyl group, a pyrrolyl group, an imidazolyl group, a pyrazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoxazolyl group, a benzoimidazolyl group, a furanyl group, a benzofuranyl group, a thiophenyl group, a benzothiophenyl group, a thiazolyl group, an isothiazolyl group, a benzothiazolyl group, an isoxazolyl group, an oxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, a dibenzofuranyl group, a dibenzothiophenyl group, a benzocarbazolyl group, a dibenzocarbazolyl group, an imidazopyrimidinyl group, and an imidazopyridinyl group; and
a phenyl group, a pentalenyl group, an indenyl group, a naphthyl group, an azulenyl group, a heptalenyl group, an indacenyl group, an acenaphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenalenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthrenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a naphthacenyl group, a picenyl group, a perylenyl group, a pentaphenyl group, a hexacenyl group, a pyrrolyl group, an imidazolyl group, a pyrazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoxazolyl group, a benzoimidazolyl group, a furanyl group, a benzofuranyl group, a thiophenyl group, a benzothiophenyl group, a thiazolyl group, an isothiazolyl group, a benzothiazolyl group, an isoxazolyl group, an oxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, a dibenzofuranyl group, a dibenzothiophenyl group, a benzocarbazolyl group, a dibenzocarbazolyl group, an imidazopyrimidinyl group, and an imidazopyridinyl group, each substituted with at least one of a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof and a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, an anthracenyl group, a pyrenyl group, a phenanthrenyl group, a fluorenyl group, a carbazolyl group, a benzocarbazolyl group, a dibenzocarbazolyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, an isoquinolinyl group, a phthalazinyl group, a quinoxalinyl group, a cinnolinyl group, and a quinazolinyl group;
in Formula 1B, E1 is a substituted or unsubstituted electron transporting-cyclic group or a substituted or unsubstituted carbazolyl group, each of which includes at least one N as a ring-forming atom;
wherein in Formulae 1A and 1B,
a1 is selected from integers of 1 to 5;
b1 is 1 or 2, provided that when b1 is 2, two groups E1 are identical to or different from each other;
R1 is selected from a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C2-C20 alkenyl group, a substituted or unsubstituted C2-C20 alkynyl group, and a substituted or unsubstituted C1-C20 alkoxy group;
R2 to R4 are each independently selected from a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C2-C20 alkynyl group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C1-C20 alkoxy group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —N(Q11)(Q12), —Si(Q13)(Q14)(Q15), and —B(Q16)(Q17);
c1 to c3 are each independently 0 to 2;
at least one of substituents of the substituted C6-C60 arylene group, the substituted C1-C60 heteroarylene group, the substituted electron transporting-cyclic group, the substituted carbazolyl group, the substituted C1-C20 alkyl group, the substituted C2-C20 alkenyl group, the substituted C2-C20 alkynyl group, the substituted C3-C10 cycloalkyl group, the substituted C1-C10 heterocycloalkyl group, the substituted C3-C10 cycloalkenyl group, the substituted C1-C10 heterocycloalkenyl group, the substituted C6-C60 aryl group, the substituted C6-C60 aryloxy group, the substituted C6-C60 arylthio group, the substituted C1-C60 heteroaryl group, the substituted monovalent non-aromatic condensed polycyclic group, and the substituted monovalent non-aromatic condensed heteropolycyclic group are selected from
a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, and C1-C20 alkoxy group;
a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, and a C1-C20 alkoxy group, each substituted with at least one of a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q21)(Q22), —Si(Q23)(Q24)(Q25), and —B(Q26)(Q27);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one of a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, and a C1-C20 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q31)(Q32), —Si(Q33)(Q34)(Q35), and —B(Q36)(Q37); and
—N(Q41)(Q42), —Si(Q43)(Q44)(Q45) and —B(Q46)(Q47),
wherein Q11 to Q17, Q21 to Q27, Q31 to Q37, and Q41 to Q47 are each independently selected from a hydrogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C1-C20 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group,
provided that, in Formula 1A, R2 in the number of c1 are all different from A.

US Pat. No. 10,396,291

COMPOUND FOR ORGANIC ELECTRONIC ELEMENT, ORGANIC ELECTRONIC ELEMENT USING THE SAME, AND AN ELECTRONIC DEVICE THEREOF

DUK SAN NEOLUX CO., LTD.,...

1. A compound of Formula 1:
wherein,
Ar1 to Ar3 are each independently selected from the group consisting of a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxy group; and a C6-C30 aryloxy group,
L is

m and o are each an integer of 0 to 4, n is an integer of 0 to 3,
R1 and R2 are each independently selected from the group consisting of deuterium; halogen; a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxy group; a C6-C30 aryloxy group; -L?-N(Ra)(Rb); and a combination thereof, wherein R1 and/or R2 are plural and one or two pair(s) of any two adjacent groups of R1 and/or any two adjacent groups of R2 are linked together to form a benzene ring,
R3 is selected from the group consisting of deuterium; halogen; a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxy group; a C6-C30 aryloxy group; and a combination thereof, wherein any two adjacent groups of R3 are optionally linked together to form a ring,
L? is selected from the group consisting of single bond; a C6-C60 arylene group; a fluorenylene group; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P,
Ra and Rb are each independently selected from the group consisting of C6-C60 aryl group; a fluorenyl group; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P,
each of the above aryl group, fluorenyl group, heterocyclic group, fused ring group, alkyl group, alkenyl group, alkynyl group, alkoxy group, aryloxy group, arylene group and fluorenylene group may be substituted with one or more substituents selected from the group consisting of deuterium; halogen; a silane group; a siloxane group; a boron group; a germanium group; a cyano group; a nitro group; a C1-C20 alkylthio group; a C1-C20 alkoxy group; a C1-C20 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C6-C20 aryl group; a C6-C20 aryl group substituted with deuterium; a fluorenyl group; a C2-C20 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a C3-C20 cycloalkyl group; a C7-C20 arylalkyl group; and a C8-C20 arylalkenyl group.

US Pat. No. 10,396,269

INTERCONNECT STRUCTURES FOR ASSEMBLY OF SEMICONDUCTOR STRUCTURES INCLUDING SUPERCONDUCTING INTEGRATED CIRCUITS

Massachusetts Institute o...

1. A multi-layer semiconductor structure, comprising:a first semiconductor structure having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces;
a second semiconductor structure having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces, wherein at least one of the first and second semiconductor structures is a superconducting semiconductor structure; and
one or more interconnect structures, each of the interconnect structures disposed between the first and second semiconductor structures and coupled to respective ones of the interconnect pads provided on the first and second semiconductor structures, and each of the interconnect structures including a plurality of interconnect sections, wherein at least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material;
wherein each of the interconnect structures has first and second opposing portions and includes:
a first interconnect section having first and second opposing portions, wherein the first portion of the first interconnect section corresponds to the first portion of the interconnect structure;
a second interconnect section having first and second opposing portions, wherein the first portion of the second interconnect section is disposed over the second portion of the first interconnect section; and
a third interconnect section having first and second opposing portions, wherein the first portion of the third interconnect section is disposed over the second portion of the second interconnect section, and the second portion of the third interconnect section corresponds to the second portion of the interconnect structure;
wherein the first interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials; and
wherein the third interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials;
wherein each of the conductive layers has a different, respective melting point;
wherein:
the first interconnect section of the first semiconductor structure consists of a first superconducting layer, a second superconducting layer disposed on the first superconducting layer, and a third conductive layer disposed on the second superconducting layer,
the second interconnect section of the first semiconductor structure consists of a superconducting bump disposed on the third layer of the first interconnect section; and
the third interconnect section of the first semiconductor structure consists of a fourth superconducting layer, a fifth superconducting layer disposed on the fourth superconducting layer, and a sixth conductive layer disposed on the fifth superconducting layer;
wherein at least one of the first, second, and third interconnect sections comprise an interface with a second one of the first, second, and third interconnect sections corresponding to a multi-melt interface that includes at least one superconducting and/or a partially superconducting material.

US Pat. No. 10,396,268

QUBIT NETWORK NON-VOLATILE IDENTIFICATION

INTERNATIONAL BUSINESS MA...

1. A method of forming a superconducting chip comprising:providing resonant units having resonant frequencies, Josephson junctions being in the resonant units;
causing one or more of the Josephson junctions to have a shorted tunnel barrier; and
causing one or more of the Josephson junctions to have no shorted tunnel barrier, wherein the resonant frequencies are designed to fall within a frequency band for each of the resonant units having the no shorted tunnel barrier in the Josephson junctions.

US Pat. No. 10,396,267

THERMOELECTRIC CONVERSION ELEMENT AND METHOD OF MANUFACTURING THE SAME, AND HEAT RADIATION FIN

NEC Corporation, Tokyo (...

1. A heat radiation fin, comprising:a supporting structure;
a magnetic body jointed to said supporting structure and having a magnetization directed in a first direction; and
an electromotive body exhibiting a spin orbit coupling and jointed to said magnetic body wherein said supporting structure includes:
a base member to be coupled to an object to be cooled; and
a plurality of fin members having a plate shape and coupled to said base member, and
wherein a joint surface on which said magnetic body and said supporting structure are jointed and a joint surface on which said magnetic body and said electromotive body have concavities and convexities,
wherein said joint surface has a shape in which a plurality of unit faces is arrayed in a second direction perpendicular to said first direction, and
wherein each of said unit faces is a non-flat face obtained by moving a first generating which is not straight line located in a flat face perpendicular to said first direction, in said first direction.

US Pat. No. 10,396,257

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device, comprising:providing a mold with a mold recess having a bottom and an inner peripheral surface that defines the mold recess and that is connected to the bottom, the bottom including a bottom projection and a bottom recess surrounding the bottom projection to define the bottom projection that has a projection top surface and a projection peripheral surface opposing the inner peripheral surface, the projection top surface defining a part of the bottom;
mounting a light emitting element on the bottom projection in the mold recess such that a light extraction surface of the light emitting element faces the projection top surface and such that an outer peripheral surface of the light emitting element opposes the inner peripheral surface of the mold recess;
providing a covering material in the mold recess to cover the inner peripheral surface of the mold recess, the outer peripheral surface of the light emitting element, and the projection peripheral surface;
removing the mold to provide a recess in the covering material; and
providing a light-transmissive material in the recess in the covering material.

US Pat. No. 10,396,256

ELECTRONIC DEVICE PACKAGE

Industrial Technology Res...

1. An electronic device package, comprising:a substrate;
an electronic device disposed on the substrate; and
a first packaging layer disposed on the substrate, wherein the electronic device is located between the substrate and the first packaging layer, the first packaging layer comprises a first oxynitride layer and a second oxynitride layer, the second oxynitride layer is located between the first oxynitride layer and the electronic device, a composition of the first oxynitride layer comprises SiNx1Oy1, a composition of the second oxynitride layer comprises SiNx2Oy2, and x1>x2, wherein the first oxynitride layer comprises a doping element.

US Pat. No. 10,396,250

LIGHT EMITTING ELEMENT INCLUDING ZNO TRANSPARENT ELECTRODE

SEOUL VIOSYS CO., LTD., ...

1. A light emitting element comprising:a first conductivity type semiconductor layer;
a mesa disposed on the first conductivity type semiconductor layer and comprising an active layer and a second conductivity type semiconductor layer disposed on the active layer;
a ZnO transparent electrode disposed on the mesa;
a first electrode disposed on the first conductivity type semiconductor layer; and
a second electrode at least partially disposed on the ZnO transparent electrode, and comprising a second electrode pad and at least one second electrode extension portion extending from the second electrode pad,
wherein the at least one second electrode extension portion contacts the ZnO transparent electrode,
the ZnO transparent electrode comprises a first region and a second region, the first region comprising a plurality of protrusions protruding upwards from an upper surface of the ZnO transparent electrode and arranged in a predetermined pattern,
the first region having a thickness greater than that of the second region, and
a separation distance between the plural protrusions is smaller than the shortest distance between the at least one second electrode extension portion and one protrusion adjacent to the at least one second electrode extension portion in a horizontal direction.

US Pat. No. 10,396,249

SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING THE SAME

NICHIA CORPORATION, Anan...

1. A semiconductor light emitting element comprising:a semiconductor laminated body including an n-type semiconductor layer and a p-type semiconductor layer, which is formed above an upper surface of the n-type semiconductor layer;
a first metal film provided on an upper surface of the p-type semiconductor layer;
a second metal film having an upper surface and a lower surface extending in a lateral direction, and having a lateral surface extending from the upper surface to the lower surface, the second metal film covering a surface of the first metal film, and provided in contact with the upper surface of the p-type semiconductor layer;
a third metal film having an upper surface and a lower surface extending in a lateral direction, and having a lateral surface extending from the upper surface to the lower surface, the third metal film provided within a portion of the upper surface of the second metal film such that the third metal film is in contact with the second metal film;
a metal oxide film including an oxide of a metal material that is the same as a metal material constituting the second metal film, the metal oxide film covering the lateral surface and the upper surface of the second metal film outside the third metal film in a plan view; and
an insulation film that is made of an oxide to cover a surface of the metal oxide film,
wherein insular regions are provided on a portion of the upper surface of the second metal film in an area directly under the lower surface of the third metal film, the insular regions comprising an oxide of a metal material that is the same as an oxide of a metal material constituting the metal oxide film.

US Pat. No. 10,396,245

LIGHT EMITTING ELEMENT HAVING A CONDUCTIVE PATTERN AND FABRICATION METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A light emitting element, comprising:a base substrate, and
a plurality of light emitting units provided on the base substrate,
wherein each light emitting unit comprises:
an anode electrode,
a hole transport layer,
a light emitting layer,
an electron transport layer, and
a cathode electrode, all of the light emitting units are divided into a plurality of light emitting sets, and the light emitting units in a same light emitting set share a same electron transport layer and share a cathode electrode,
wherein a conductive pattern is provided correspondingly in the periphery of each light emitting unit and has a resistance smaller than a resistance between the cathode electrode and the anode electrode of the corresponding light emitting unit.

US Pat. No. 10,396,242

SEMICONDUCTOR LIGHT EMITTING DEVICE

Nichia Corporation, Anan...

1. A semiconductor light emitting device comprising:a substrate that has a main surface that comprises a plurality of protrusions in a two-dimensionally repeated pattern;
a plurality of semiconductor layers disposed on the main surface of the substrate and comprising a GaN based semiconductor; and
an ohmic electrode disposed on a top layer of the semiconductor layers and comprising a plurality of openings,
wherein each of the protrusions has a side surface that is inclined to a stacking plane of the semiconductor layers and configured to scatter or diffract light generated in the semiconductor layers, and
wherein at least one side surface of the protrusions is located in each of the openings in plan view of the semiconductor light emitting device.

US Pat. No. 10,396,237

LIGHT-EMITTING DIODE SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of a light-emitting diode (LED) substrate, comprising:disposing a supporting substrate supporting a plurality of LED units to be opposed to a receiving substrate so that a side of the supporting substrate facing the receiving substrate supports the plurality of LED units, wherein the receiving substrate is provided thereon with a pixel definition layer, the pixel definition layer defines a plurality of sub-pixel regions, each of the sub-pixel regions is configured to receive at least one of the LED units, a solder point and an auxiliary metal member are both provided in the sub-pixel region, the auxiliary metal member is provided at a periphery of the solder point, an interval is provided between the solder point and the auxiliary metal member in a plan view of the receiving substrate, and a melting point of the auxiliary metal member is higher than a melting point of the solder point; and
irradiating a side of the supporting substrate away from the receiving substrate with laser, stripping the LED units from the supporting substrate, and transferring the LED units onto the receiving substrate so that the at least one of the LED units in the sub-pixel region is in contact with both the solder point and the auxiliary metal member.

US Pat. No. 10,396,222

INFRARED LIGHT-RECEIVING DEVICE

SUMITOMO ELECTRIC INDUSTR...

1. An infrared light-receiving device comprising:a substrate having a principal surface;
an optical absorption layer disposed on the principal surface of the substrate, the optical absorption layer including a type-II superlattice structure; and
an optical filter disposed on the optical absorption layer, the optical filter including an incident surface, the optical filter including a first semiconductor region disposed on the optical absorption layer, a second semiconductor region disposed on the first semiconductor region, and a third semiconductor region disposed on the second semiconductor region, each of the first, second, and third semiconductor regions including an n-type InGaAs layer, wherein
the first semiconductor region has an n-type impurity concentration of 2.0×1019 cm?3 or more,
the third semiconductor region has an n-type impurity concentration of 3.0×1018 cm?3 or less and 8.0×1017 cm?3 or more, and
the second semiconductor region has an n-type impurity concentration between the n-type impurity concentration of the first semiconductor region and the n-type impurity concentration of the third semiconductor region.

US Pat. No. 10,396,221

SOLUTION PROCESS FOR SILVER-CONTAINING CHALCOGENIDE LAYER DEPOSITION

INTERNATIONAL BUSINESS MA...

1. A solar cell, comprising:an Ag2ZnSn(S,Se)4 compound layer on a substrate.

US Pat. No. 10,396,220

DEVICE LAYER THIN-FILM TRANSFER TO THERMALLY CONDUCTIVE SUBSTRATE

International Business Ma...

1. A semiconductor structure, comprising:a thin-film device layer;
an optoelectronic device disposed in the thin-film device layer, the optoelectronic device excitable by light at an application wavelength; and
a surrogate substrate permanently attached to the thin film device layer, wherein the surrogate substrate has a volume of substrate removed therefrom to form a via, the via aligned with a location of the optoelectronic device, a cross-sectional area of the via being about equal to an active area of the optoelectronic device, and a depth of the via being substantially less than a thickness of the surrogate substrate,
wherein the light passes through the via and at least some of the surrogate substrate prior to reaching the optoelectronic device.

US Pat. No. 10,396,213

ACTIVE DEVICE ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

Chunghwa Picture Tubes, L...

1. An active device array substrate, comprising:a substrate;
a first active device, disposed on the substrate and comprising a first gate electrode, a first semiconductor block, a first source electrode and a first drain electrode, wherein the first source electrode and the first drain electrode contact the first semiconductor block and are separate from each other;
a second active device, disposed on the substrate and comprising a second gate electrode, a second semiconductor block, a second source electrode and a second drain electrode, wherein the second source electrode and the second drain electrode contact the second semiconductor block and are separate from each other, and a film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode;
a gate insulation layer, disposed on the substrate, wherein the first gate electrode and the second gate electrode are located between the gate insulation layer and the substrate, and the gate insulation layer is located between the first gate electrode and the first semiconductor block and is also located between the second gate electrode and the second semiconductor block; and
an insulation barrier layer, disposed on the gate insulation layer, and covering the first semiconductor block, and the insulation barrier layer having a first through hole reaching a surface of the first semiconductor block, wherein the insulation barrier layer is disposed between the first source electrode and the first drain electrode and the insulation barrier layer reveals the second semiconductor block, the second source electrode and the second drain electrode, and wherein one of the first source electrode and the first drain electrode contacts the first semiconductor block through the first through hole and the other one is located between the gate insulation layer and the insulation barrier layer.

US Pat. No. 10,396,211

FUNCTIONAL METAL OXIDE BASED MICROELECTRONIC DEVICES

Intel Corporation, Santa...

1. A microelectronic apparatus, comprising:a microelectronic substrate;
a buffer transition layer on the microelectronic substrate;
a functional metal oxide channel on the buffer transition layer; and
an electrode on the functional metal oxide channel;
wherein the microelectronic substrate includes a microelectronic transistor source region formed therein, and wherein the buffer transition layer contacts the microelectronic transistor source region.

US Pat. No. 10,396,205

INTEGRATED CIRCUIT DEVICE

Samsung Electronics Co., ...

1. An integrated circuit device, comprising:a fin-type active region protruding from a substrate and extending longitudinally in a first horizontal direction;
a base burying insulating film including a vertical extension and a horizontal extension on the substrate, the vertical extension covering a lower side wall of the fin-type active region and having a first top surface at a first level, and the horizontal extension being integrally connected to the vertical extension and covering a top surface of the substrate;
an isolation pattern covering a side wall of the vertical extension on the horizontal extension and having a second top surface at a second level, the second level being higher than the first level; and
a gate line having an upper gate and a lower gate, the upper gate extending in a second horizontal direction crossing the first horizontal direction to cover an upper portion of a channel section of the fin-type active region and the second top surface of the isolation pattern, and the lower gate protruding from the upper gate toward the substrate and filling a space on the first top surface between a lower portion of the channel section and an upper side wall of the isolation pattern.

US Pat. No. 10,396,201

METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES

Intel Corporation, Santa...

1. A method of forming a structure comprising:forming openings in source/drain regions of a device disposed on a substrate, the openings beneath dielectric spacers adjacent to a gate electrode, wherein the gate electrode is on a gate dielectric, and wherein the openings further extend beneath the gate dielectric;
forming a dislocation nucleation material in the source/drain openings, wherein the dislocation nucleation material is selectively grown using epitaxial growth, wherein the dislocation nucleation material comprises a lattice constant that is mismatched with a substrate lattice constant, and wherein a plurality of dislocations form in the dislocation nucleation material, and wherein the dislocation nucleation material is in contact with a bottom surface of the dielectric spacers and with a bottom surface of the gate dielectric; and
forming a source/drain material on the dislocation nucleation material, wherein a plurality of source/drain dislocations are formed in the source/drain material.

US Pat. No. 10,396,199

ELECTROSTATIC DISCHARGE DEVICE

TEXAS INSTRUMENTS INCORPO...

1. A device, comprising:a substrate having a top surface;
an n-type region extending from the top surface;
a p-type region within the n-type region and extending from the top surface;
a first n+ region within the p-type region and separated from the n-type region by the p-type region;
a second n+ region within the p-type region and separated from the n-type region and the first n+ region by the p-type region; and
an impedance above the top surface, and coupled between the n-type region and the second n+ region.

US Pat. No. 10,396,197

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

UNISANTIS ELECTRONICS SIN...

1. A semiconductor device comprising:a planar semiconductor layer on a substrate;
a pillar-shaped semiconductor layer on the planar semiconductor layer;
a gate insulating film surrounding the pillar-shaped semiconductor layer;
a first metal surrounding the gate insulating film,
the first metal in contact with an upper portion of the planar semiconductor layer;
an element isolation insulating film surrounding the planar semiconductor layer,
wherein the first metal extends over the element isolation insulating film;
a gate above the first metal and surrounding the gate insulating film, where the gate is electrically insulated from the first metal; and
a second metal above the gate so as to surround the gate insulating film, where the second metal is electrically insulated from the gate, and has an upper portion electrically connected to an upper portion of the pillar-shaped semiconductor layer.

US Pat. No. 10,396,195

SEMICONDUCTOR DEVICE AND METHOD MANUFACTURING THE SAME

Hyundai Motor Company, S...

1. A semiconductor device, comprising:an n? type layer disposed at a first surface of a substrate;
a trench, an n type region, and a p+ type region disposed on the n? type layer;
a p type region disposed on the n type region;
an n+ type region disposed on the p type region;
a gate insulating layer disposed in the trench;
a gate electrode disposed on the gate insulating layer;
an insulating layer disposed on the gate electrode;
a source electrode disposed on the insulating layer, the n+ type region, and the p+ type region; and
a drain electrode disposed at a second surface of the substrate,
wherein the n type region includes a first portion in contact with the side surface of the trench and extending parallel to an upper surface of the substrate and a second portion in contact with the first portion, separated from the side surface of the trench, and extending in a direction vertical to the upper surface of the substrate.

US Pat. No. 10,396,191

SEMICONDUCTOR DEVICE

Epistar Corporation, Hsi...

1. A semiconductor device, comprising:a channel layer formed on a substrate;
a top barrier layer formed on the channel layer, wherein a first heterojunction is formed between the channel layer and the top barrier layer so that a first two-dimensional electron gas is generated in the channel layer;
a buffer structure formed between the substrate and the channel layer;
a back barrier layer formed between the buffer structure and the channel layer, wherein a second heterojunction is formed between the buffer structure and the back barrier layer so that a second two-dimensional electron gas is generated in the buffer structure; and
a source electrode, a drain electrode, and a gate electrode formed on the top barrier layer, respectively;
wherein a sheet carrier density of the second two-dimensional electron gas is less than 8E+10 cm?2.

US Pat. No. 10,396,186

THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for fabricating a thin film transistor, comprising:forming an active layer on a substrate;
forming an insulating layer on the active layer and an exposed surface of the substrate;
forming a first conductive layer on the insulating layer;
patterning the first conductive layer and the insulating layer to form a first stack on the active layer, wherein the first stack comprises a first portion of the first conductive layer and a first portion of the insulating layer, the first stack acts as a gate stack of the thin film transistor, and the active layer comprises a channel region below the gate stack and a source region and a drain region at two sides of the channel region; and
performing plasma treatment on the first conductive layer, the source region, and the drain region, to improve the conductivity of the first conductive layer, the source region, and the drain region.

US Pat. No. 10,396,183

PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFET

INTERNATIONAL BUSINESS MA...

1. A method comprising:creating, in a fin-Field Effect Transistor (finFET), a recess at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into a substrate interfacing with the gate;
filling the recess at least partially with a first conductive material;
insulating the first conductive material from the gate;
replacing the fin with a replacement structure;
connecting electrically, using a second conductive material, the replacement structure to the first conductive material, wherein the first conductive material and the second conductive material are identical;
insulating the second conductive material from a first surface of the finFET;
fabricating a first electrical contact structure on the first surface; and
fabricating a second electrical contact structure on a second surface of the finFET, the second surface being on a different spatial plane than the first surface.

US Pat. No. 10,396,179

FORMING VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS WITH UNIFORM BOTTOM SPACER THICKNESS

INTERNATIONAL BUSINESS MA...

1. A vertical transport field effect transistor with uniform bottom spacer thickness, comprising:a vertical fin on a substrate;
a protective liner segment on the substrate adjacent to the vertical fin;
a conversion segment on the protective liner segment, wherein the conversion segment includes silicon oxide (SiO); and
a gate dielectric layer on the conversion segment, wherein the gate dielectric layer follows the shape and varying thickness of the conversion segment.

US Pat. No. 10,396,178

METHOD OF FORMING IMPROVED VERTICAL FET PROCESS WITH CONTROLLED GATE LENGTH AND SELF-ALIGNED JUNCTIONS

INTERNATIONAL BUSINESS MA...

1. A method of forming a vertical field-effect transistor (FET), the method comprising:depositing a highly doped bottom source-drain layer over a substrate of a first type;
depositing a first heterostructure layer over the highly doped bottom source-drain layer;
depositing a channel layer over the first heterostructure layer;
depositing a second heterostructure layer over the channel layer;
forming a first fin having a hard mask thereon, wherein the hard mask is disposed on the second heterostructure layer;
recessing the first and the second heterostructure layers such that they are narrower than the first fin and the hard mask;
filling gaps formed in the recessed first and second heterostructure layers with a dielectric inner spacer;
laterally trimming the channel layer to a narrower width;
depositing a dielectric bottom outer spacer over the highly doped bottom source-drain layer;
depositing a high-k dielectric layer on the dielectric bottom outer spacer, the first fin, and the hard mask; and
depositing a metal gate layer on top of the high-k dielectric layer.

US Pat. No. 10,396,177

PREVENTION OF EXTENSION NARROWING IN NANOSHEET FIELD EFFECT TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, comprising:forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material;
recessing the first layers relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers;
forming first spacers in recesses formed by recessing the first layers;
forming second spacers in recesses formed by recessing the first layers;
etching the first spacers to expose sidewalls of the second spacer;
forming source/drain extensions in contact with exposed ends of the second layers; and
etching away the first layers of sacrificial material after forming the source/drain extensions to expose the second layers of channel material.

US Pat. No. 10,396,174

STI-DIODE STRUCTURE

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a fin-type diode, comprising:providing a substrate structure, the substrate structure comprising:
a substrate;
a first set of fins on the substrate;
a second set of fins on the substrate;
an isolation region disposed between the first set of fins and the second set of fins and having an upper surface lower than an upper surface of the first set of fins and an upper surface of the second set of fins;
a well region partially in the substrate and overlapping the first set of fins and the second set of fins, or the well region entirely in the substrate and overlapping the first set of fins and the second set of fins;
forming a dielectric layer on a surface of first set of fins and on a surface of the second set of fins above the upper surface of the isolation region;
forming a dummy gate structure covering a portion of the dielectric layer on a distal end of the second set of fins and the upper surface or a portion of the upper surface of the isolation region;
performing a first dopant implantation on the first set of fins to form a first doped region;
performing a second dopant implantation on the second set of fins and a portion of the well region below the second set of fins using the dummy gate structure as a mask to form a second doped region;
wherein the first doped region and the second doped region have different conductivity types;
wherein the first doped region and the well region have a same conductivity type.

US Pat. No. 10,396,172

TRANSISTOR WITH AIR SPACER AND SELF-ALIGNED CONTACT

INTERNATIONAL BUSINESS MA...

1. A semiconductor transistor, comprising:a source region and a drain region formed within a substrate;
a gate formed above the substrate;
a source contact formed above the source region and a drain contact formed above the drain region;
air spacers formed within a dielectric between the gate and each of the source contact and the drain contact;
metal caps formed on the source contact and the drain contact; and
a gate cap between the dielectric and at least a portion of a bottom surface of higher-level contacts, which are contacts formed above the source contact and the drain contact, wherein the gate cap contacts the dielectric on a first side of the gate cap and the gate cap contacts the portion of the bottom surface of the higher-level contacts on a second side of the gate cap that is opposite the first side of the gate cap.

US Pat. No. 10,396,169

NANOSHEET TRANSISTORS HAVING DIFFERENT GATE DIELECTRIC THICKNESSES ON THE SAME CHIP

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first nanosheet stack on a substrate, the first nanosheet stack comprising a first nanosheet formed over a second nanosheet;
a second nanosheet stack on the substrate, the second nanosheet stack comprising a first nanosheet formed over a second nanosheet;
a dielectric layer formed over a channel region of the first nanosheet stack;
a first gate formed over the dielectric layer in the channel region of the first nanosheet stack;
a second gate formed over a channel region of the second nanosheet stack;
a first gate contact on the first gate; and
a second gate contact on the second gate;
wherein a distance between adjacent nanosheets in the first nanosheet stack is greater than a distance between adjacent nanosheets in the second nanosheet stack;
wherein spacers are formed between the adjacent nanosheets in the first nanosheet stack and between adjacent nanosheets in the second nanosheet stack;
wherein a length of the spacers between the adjacent nanosheets in the first nanosheet stack is greater than a length of at least one of the spacers between the adjacent nanosheets in the second nanosheet stack;
wherein the first gate comprises a high-k dielectric film formed on a surface of the dielectric layer in the channel region of the first nanosheet stack; and
wherein the length of a bottom most spacer of the spacers below the adjacent nanosheets in the first nanosheet stack is greater than the length of the at least one of the spacers between the adjacent nanosheets in the second nanosheet stack.

US Pat. No. 10,396,168

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a first pipe gate;
a second pipe gate disposed on the first pipe gate;
an inter-gate insulating layer disposed between the first pipe gate and the second pipe gate;
first memory cells and second memory cells, disposed on the second pipe gate;
a first channel layer extending toward the first memory cells from the inside of the first pipe gate, the first channel layer connecting the first memory cells in series;
a second channel layer extending toward the second memory cells from the inside of the second pipe gate, the second channel layer connecting the second memory cells in series;
a first contact structure connected to the first pipe gate; and
a second contact structure connected to the second pipe gate.

US Pat. No. 10,396,161

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising: a silicon carbide (SiC) substrate of a first conductivity type, having a front surface and a back surface; a SiC layer of the first conductivity type, formed on the front surface of the SiC substrate and having an impurity concentration lower than that of the SiC substrate; a first region of a second conductivity type, selectively formed in the SiC layer at a surface thereof; a source region of the first conductivity type formed in the first region; a contact region of the second conductivity type formed in the first region, the contact region having an impurity concentration higher than that of the first region; a gate insulating film disposed on the SiC layer and on a portion of the first region between the SiC layer and the source region; a first gate electrode disposed on the gate insulating film above the portion of the first region; an interlayer insulating film covering the first gate electrode; a source electrode electrically connected to the source region and the contact region; a drain electrode formed on the back surface of the SiC substrate; a first barrier film formed on and covering the interlayer insulating film, interposing the source electrode and the interlayer insulating film, the first barrier film separating the source electrode from the interlayer insulating film, so as to prevent penetration of metal atoms of the source electrode into the interlayer insulating film; and a first metal electrode formed directly on the source electrode and the first barrier film, wherein the first barrier film is formed by a single-layer structure of titanium nitride (TiN), or a layered structure of titanium (Ti) and TiN, and the first metal electrode is formed by a layered structure of Ti and aluminum (Al).

US Pat. No. 10,396,158

TERMINATION STRUCTURE FOR NANOTUBE SEMICONDUCTOR DEVICES

Alpha and Omega Semicondu...

1. A termination structure for a semiconductor device including an active area and a termination area surrounding the active area, the termination structure being formed in the termination area and comprising:a first semiconductor layer of a first conductivity type comprising a plurality of trenches formed in a top surface of the first semiconductor layer, the trenches forming mesas in the first semiconductor layer;
a first epitaxial layer of the first conductivity type formed on the sidewalls of the mesas;
a second epitaxial layer of a second conductivity type, opposite the first conductivity type, formed on the first epitaxial layer, the trenches between the second epitaxial layer formed on adjacent mesas being filled with a first dielectric layer;
a first termination cell formed in the termination area at an interface to the active area, the first termination cell being formed in a mesa of the first semiconductor layer and having a first width; and
an end termination cell being formed away from the interface to the active area in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

US Pat. No. 10,396,157

SEMICONDUCTOR DEVICE

United Microelectronics C...

1. A semiconductor device comprising:a semiconductor layer having a first device region and a second device region;
a shallow trench isolation structure, in the semiconductor layer, located at a periphery of the first device region and the second device region;
a first insulating layer and a second insulating layer, on the semiconductor layer, respectively located in the first device region and the second device region;
a first gate structure located on the first insulating layer;
a source region and a drain region, in the semiconductor layer, located at two sides of the first gate structure;
a gate doped region in a surface region of the semiconductor layer in the second device region to serve as a second gate structure;
a channel layer located on the second insulating layer; and
a source layer and a drain layer, directly on the shallow trench isolation structure, located at two sides of the channel layer.

US Pat. No. 10,396,156

METHOD FOR FINFET LDD DOPING

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:providing a structure that includes a substrate, a fin over the substrate, and a gate structure engaging the fin;
performing a first implantation process to implant a dopant into the fin adjacent to the gate structure;
forming gate sidewall spacers over sidewalls of the gate structure and fin sidewall spacers over sidewalls of the fin;
performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers;
after the first etching process, performing a second implantation process to implant the dopant into the fin and the fin sidewall spacers;
after the second implantation process, performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers; and
epitaxially growing a semiconductor material in the trench.

US Pat. No. 10,396,154

LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE

International Business Ma...

1. A device comprising:a dielectric pedestal including a nucleation dielectric layer;
a base region comprised of a germanium containing material in contact with the pedestal, wherein the germanium containing material is silicon free germanium; and
an emitter region and collector region present on opposing sides of the base region contacting a sidewall of the pedestal and an upper surface of the nucleation dielectric layer.

US Pat. No. 10,396,152

FABRICATION OF PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE USING INTERFACE INTERACTION

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a plurality of vertically stacked suspended nanowires extending having a gate structure being present on a channel region portion of the suspended nanowires;
a dielectric spacer having a uniform composition in direct contact with the gate structure, the dielectric spacer having a uniform length extending from a upper surface of the gate structure to the base of the gate structure, wherein a first length of the dielectric spacer positioned between adjacently stacked suspended nanowires is substantially equal to a second length of the dielectric spacer adjacent to the upper surface of the gate structure; and
source and drain regions present on source and drain region portions of the plurality of suspended nanowires, wherein the suspended nanowires are uniform in geometry along an entire length of the suspended nanowires from a channel region of the suspended nanowire to the source and drain region portions of the suspended nanowire.

US Pat. No. 10,396,151

VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED GATE TO SOURCE/DRAIN CAPACITANCE

INTERNATIONAL BUSINESS MA...

1. A method of forming a fin field effect transistor device, comprising:forming a vertical fin layer on a bottom source/drain layer;
forming one or more fin templates on the vertical fin layer;
forming a vertical fin below each of the one or more fin templates;
reducing the width of each of the vertical fins to form one or more thinned vertical fins, wherein at least a portion of the fin template overhangs the sides of the underlying thinned vertical fin; and
depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness that tapers in a direction towards the thinned vertical fins.

US Pat. No. 10,396,143

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device comprising: a substrate with an active area and a pad area; a first anode electrode in the active area of the substrate; a second anode electrode on the first anode electrode, the second anode electrode being electrically connected to the first anode electrode; an organic emitting layer on the second anode electrode; a cathode electrode on the organic emitting layer; a first auxiliary electrode in a same layer as the first anode electrode; a second auxiliary electrode in a same layer as the second anode electrode, the second auxiliary electrode being electrically connected to the first auxiliary electrode and the cathode electrode, a first signal line and a second signal line in the active area; a first pad in the pad area and connected to the first signal line, wherein the first pad includes a link region electrically connected to the first signal line and a first bonding region connected to the link region, the first bonding region including one or more first contact holes for electrical connection with the link region; and a second pad in the pad area and connected to the second signal line, wherein the second pad includes a second bonding region corresponding to the first bonding region of the first pad and a contact region corresponding to the link region of the first pad, the contact region being electrically connected to the second bonding region and including one or more second contact holes for electrical connection with the second signal line.

US Pat. No. 10,396,142

ARRAY SUBSTRATE AND AMOLED DISPLAY DEVICE

Wuhan China Star Optoelec...

1. An array substrate, comprising:a substrate;
a driver chip, located on the substrate;
a plurality of data lines, arranged in turn on the substrate and extended longitudinally to be connected electrically to the driver chip;
a plurality of high level lines, arranged in turn on the substrate, and extending longitudinally on the substrate;
a metal block, located on the substrate and electrically connected to the high level lines, so that the high level lines are at the same high level; wherein the data lines are electrically connected to the driver chip through the area which the metal block is located in, and an insulating layer exists between the metal block and the data lines, a hollow area located in the metal block overlapping the data lines to reduce parasitic capacitance formed by the metal block and the data lines, wherein the hollowed area is a plurality of derating slits, the number of the derating slits is multiple, and at least one of the data lines corresponds to at least one of the derating slits one to one,
wherein de-electrostatic slits are provided in the metal block, the de-electrostatic slits are not overlapping the data lines and are surrounded by the metal block.

US Pat. No. 10,396,139

ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY

Samsung Display Co., Ltd....

1. An organic light-emitting diode (OLED) display, comprising:a substrate;
an active pattern formed over the substrate and including: a first region, a second region, a third region, a fourth region, a fifth region, and a sixth region, wherein the second region and the sixth region are: i) electrically connected to each other and ii) formed directly adjacent each other in a first continuous region of the active pattern, and wherein the fourth region and the fifth region are: i) electrically connected to each other and ii) formed directly adjacent each other in a second continuous region of the active pattern;
a gate insulation layer formed over the active pattern;
a first gate electrode formed over the gate insulation layer, wherein the first gate electrode defines a first transistor together with the first region and the second region;
a second gate electrode formed on the same layer as the first gate electrode, wherein the second gate electrode defines: i) a second transistor together with the third region and the fourth region which are arranged in a first direction ii) a third transistor together with the fifth region and the sixth region which are arranged in a second direction, wherein the fifth region and the sixth region are on opposite sides of a gate region of the third transistor, and wherein the second direction is substantially perpendicular to the first direction;
a first insulating interlayer formed over the first gate electrode, the second gate electrode, and the gate insulation layer;
a first conductive pattern formed over the first insulating interlayer, wherein the first conductive pattern overlaps at least a portion of the fourth and fifth regions in a thickness direction of the substrate, wherein the first conductive pattern defines a parasitic capacitor together with the portion of the fourth and fifth regions; and
an OLED configured to receive a driving current from the first transistor,
wherein the second and third transistors are configured to provide an initialization voltage to the first transistor.

US Pat. No. 10,396,119

UNIT PIXEL OF IMAGE SENSOR, IMAGE SENSOR INCLUDING THE SAME AND METHOD OF MANUFACTURING IMAGE SENSOR

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a unit pixel of an image sensor, the method comprising:forming a photoelectric conversion region in a substrate;
forming, in the substrate, a first floating diffusion region spaced apart from the photoelectric conversion region of the substrate, and a second floating diffusion region spaced apart from the first floating diffusion region;
forming a first recess spaced apart from the first floating diffusion region and the second floating diffusion region by removing a portion of the substrate from a first surface of the substrate;
filling the first recess to form a dual conversion gain (DCG) gate that extends perpendicularly or substantially perpendicularly from the first surface of the substrate; and
forming a conductive layer to fill an inside of the first recess.

US Pat. No. 10,396,110

REDUCTION OF TFT INSTABILITY IN DIGITAL X-RAY DETECTORS

Carestream Health, Inc., ...

1. A digital radiographic detector comprising:a two-dimensional array of imaging pixels, each imaging pixel comprising a photo-sensitive element and a switching element;
read-out circuits electrically coupled to the two-dimensional array of imaging pixels to generate a radiographic image by reading out image data from the two-dimensional array of imaging pixels; and
a housing enclosing the two-dimensional array of imaging pixels and the read-out circuits,
wherein each switching element in the two-dimensional array of imaging pixels comprises an active layer formed from indium-gallium-zinc oxide having a thickness less than about 7 nm.

US Pat. No. 10,396,094

THREE-DIMENSIONAL SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A three-dimensional semiconductor device, comprising:a stack of layers comprising gate electrodes disposed one over another on a substrate:
a channel structure extending through the gate electrodes and connected to the substrate;
an insulating gap-fill pattern disposed within the channel structure and surrounded by the channel structure as viewed in a plan view; and
a conductive pattern on the insulating gap-fill pattern,
wherein a portion of the insulating gap-fill pattern extends into the conductive pattern, and
at least a portion of the conductive pattern is interposed between the portion of the insulating gap-fill pattern and the channel structure.

US Pat. No. 10,396,058

LIGHT-EMITTING DEVICE

EPISTAR CORPORATION, Hsi...

1. A light-emitting device comprising:a first light-emitting structure having an active layer;
a second light-emitting structure;
a third light-emitting structure;
a transparent material enclosing the first light-emitting structure, the second light-emitting structure, and the third light-emitting structure;
a first conductive structure overlapping the active layer in a cross-sectional view, and having a first connecting pad connected to the first light-emitting structure, a second connecting pad connected to the second light-emitting structure, and a connecting portion suspended in the transparent material; and
a second conductive structure not overlapping the first conductive structure, and connecting the second light-emitting structure with the third light-emitting structure,
wherein the second light-emitting structure is electrically arranged between the first light-emitting structure and the third light-emitting structure, and
wherein the first connecting pad the second connecting pad, and the connecting portion are formed by a same material.

US Pat. No. 10,396,055

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES

Intel Corporation, Santa...

1. A method comprising:forming a stack comprising multiple integrated circuit (IC) dies including a first IC die and a second IC die;
coupling to the first IC die a first end of a first wire;
anchoring a second end of the first wire to the stack, wherein the first wire comprises the second end and a first portion including the first end;
while the first end is coupled to the first IC die and the second end is anchored to the stack, disposing a package material around the multiple IC dies and the first portion;
after disposing the package material around the multiple IC die, separating the second end from the first portion, including exposing another end of the first portion at a first surface of the package material; and
coupling the first IC die to the second IC die, including forming a redistribution layer on the first surface, wherein the redistribution layer is coupled to the second IC die and to the other end of the first portion.

US Pat. No. 10,396,053

SEMICONDUCTOR LOGIC DEVICE AND SYSTEM AND METHOD OF EMBEDDED PACKAGING OF SAME

General Electric Company,...

1. A reconfigured semiconductor logic device comprising:a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon; and
a redistribution layer comprising:
an insulating layer disposed on the active surface of the semiconductor logic device; and
a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer, wherein the plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer, and wherein the plurality of discrete terminal pads are larger than the plurality of I/O pads;
wherein the plurality of discrete terminal pads comprise:
a plurality of signal terminal pads electrically coupled to signal I/O pads of the plurality of I/O pads;
a plurality of power terminal pads electrically coupled to power I/O pads of the plurality of I/O pads; and
a plurality of ground terminal pads electrically coupled to ground I/O pads of the plurality of I/O pads.

US Pat. No. 10,396,045

METAL ON BOTH SIDES OF THE TRANSISTOR INTEGRATED WITH MAGNETIC INDUCTORS

Intel Corporation, Santa...

1. An apparatus comprising:a circuit structure comprising a device stratum comprising a plurality of transistor devices each comprising a first side and an opposite second side;
an inductor disposed on the second side of the structure; and
a contact coupled to the inductor and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side, wherein the contact does not extend entirely through the device stratum.

US Pat. No. 10,396,027

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A structure, comprising:a contact structure between gate structures and which comprises:
contact trenches in interlevel dielectric material;
a liner material within the contact trenches; and
a conductive material on the liner material; and
an insulator material on a planarized surface of the conductive material, the liner material, the gate structures and exposed portions of the interlevel dielectric material;
a metal material in an opening in the insulator material and on a surface of the insulator material; and
an insulator layer within the opening and on the metal material.

US Pat. No. 10,395,994

EQUAL SPACER FORMATION ON SEMICONDUCTOR DEVICE

International Business Ma...

1. A method for fabricating a semiconductor device having field-effect transistors (FETs) associated with regions of the device, comprising:epitaxially growing a first semiconductor material in a first source/drain region within a first region of the device associated with a first FET;
selectively forming a capping layer on the first semiconductor material, including forming a layer over the first region and a second region of the device associated with a second FET that reacts with the first semiconductor material to form the capping layer; and
epitaxially growing a second semiconductor material in a second source/drain region within the second region of the device, the capping layer capping the growth of the first semiconductor material during the epitaxial growth of the second semiconductor material.

US Pat. No. 10,395,990

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer;
a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and
a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction,
wherein the first gate structure includes a trench defined by the first gate spacer, and a high-k dielectric insulating film extending along a sidewall and a bottom surface of the trench, and
the high-k dielectric insulating film does not extend along a sidewall of the gate insulating support.

US Pat. No. 10,395,986

FULLY ALIGNED VIA EMPLOYING SELECTIVE METAL DEPOSITION

International Business Ma...

1. A method for creating a fully-aligned via (FAV) by employing selective metal deposition, the method comprising:forming metal lines within a first inter-layer dielectric (ILD) layer;
forming a second ILD layer over the first ILD layer;
forming a lithographic stack over the second ILD layer to define areas where via growth is prevented;
recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack; and
performing metal growth over the exposed top surface of the metal lines where via growth is permitted; and
removing the lithographic stack and depositing a conformal metal nitride cap in direct contact with a top surface and an entire length of sidewalls of the metal growth.

US Pat. No. 10,395,985

SELF ALIGNED CONDUCTIVE LINES WITH RELAXED OVERLAY

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure, comprising:a first hardmask on an insulator layer;
a planarizing layer on the first hardmask;
a second hardmask on a portion of the planarizing layer;
a third hardmask on the planarizing layer and on the second hardmask;
sacrificial mandrels on portions of the second hardmask;
a mandrel on the third hardmask; and
an organic planarizing layer on the third hardmask, on spacer material, on the sacrificial mandrels, and on a mandrel including spacer material.

US Pat. No. 10,395,983

METHOD OF FORMING TRENCHES

Taiwan Semiconductor Manu...

1. A method comprising:forming a first material layer over a substrate;
forming a first trench in the first material layer;
forming a second material layer along sidewalls of the first trench;
forming a second trench in the first material layer while the second material layer is disposed along the sidewalls of the first trench, wherein the second material layer has a tapered top surface after the forming of the second trench;
after the forming of the second trench, extending the first trench to expose a portion of the substrate within the first trench; and
forming a conductive feature within the first trench and the second trench such that the conductive feature covers the second material layer having the tapered top surface.

US Pat. No. 10,395,982

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including a first region and a second region;
a lower layer structure on the substrate, the lower layer structure having a first thickness on the first region and a second thickness on the second region, the second thickness being greater than the first thickness, the lower layer structure including an electrode layer at a top and an insulating layer under the electrode layer;
an etch stop layer on the lower layer structure;
an upper layer structure on the etch stop layer, a top surface of the upper layer structure being substantially a same level on the first and second regions, the etch stop layer having an etch selectivity with respect to both the upper layer structure and the lower layer structure;
a first contact plug filling a first opening, the upper layer structure and the etch stop layer including the first opening defined therethrough on the first region, the first contact plug being in connection with the electrode layer of the lower layer structure; and
a second contact plug filling a second opening, the upper layer structure and the etch stop layer including the second opening defined therethrough on the second region, a bottom surface of the first contact plug having a first distance from a bottom surface of the etch stop layer and a bottom surface of the second contact plug having a second distance from the bottom surface of the etch stop layer, the first distance being different from the second distance.

US Pat. No. 10,395,981

SEMICONDUCTOR DEVICE INCLUDING A LEVELING DIELECTRIC FILL MATERIAL

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a dielectric fill material above and laterally adjacent to a transistor element of a semiconductor device and a circuit element, said transistor element comprising a gate electrode structure including a dielectric capping layer, said circuit element having an electrode structure covered by a further dielectric capping layer;
removing a portion of said dielectric fill material so as to expose a surface of said dielectric capping layer and a surface of said further dielectric capping layer;
removing said dielectric capping layer and said further dielectric capping layer after removing said portion of said dielectric fill material, wherein a non-removed portion of said dielectric fill material remains laterally adjacent to said transistor element and said circuit element;
masking said circuit element by a mask layer after removal of said dielectric capping layer of said gate electrode structure and said further dielectric capping layer of said electrode structure;
forming a metal semiconductor compound in a semiconductor containing electrode material of said gate electrode structure, wherein said metal semiconductor compound in said gate electrode structure is formed in the presence of said mask layer so as to prevent formation of a metal semiconductor compound in said electrode structure; and
removing a further portion of said dielectric fill material so as to expose surface areas of drain and source regions of said transistor element.

US Pat. No. 10,395,979

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate;
a first lower insulating interlayer, a protection insulating layer, and a first upper insulating interlayer that are sequentially stacked on the substrate; and
a conductive pattern penetrating the first upper insulating interlayer, the protection insulating layer; and the first lower insulating interlayer,
wherein the conductive pattern comprises a line part extending in a direction parallel to an upper surface of the substrate and contact parts extending from the line part toward the substrate,
wherein the contact parts are spaced apart from each other with an insulating pattern therebetween,
wherein the insulating pattern comprises a portion of the first upper insulating interlayer, a portion of the protection insulating layer, and a portion of the first lower insulating interlayer, and
wherein at least a portion of the insulating pattern has a stepped profile.

US Pat. No. 10,395,975

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

DENSO CORPORATION, Kariy...

1. A semiconductor device comprising:a semiconductor substrate made of a semiconductor material including
a plurality of elements arranged at a front surface portion of the semiconductor substrate,
an insulation film arranged at a rear surface portion of the semiconductor substrate, and
a trench arranged to insulate and separate at least one of the plurality of elements by surrounding the at least one of the plurality of elements,
wherein:
the trench is arranged to penetrate both sides of the semiconductor substrate,
the trench has an inner part where a hollow space is arranged,
the trench has an inner wall surface of the semiconductor material, and the inner wall surface of the semiconductor material is exposed to the hollow space of the trench at both sides of the trench,
the trench has an upper layout with a shape from a bird's eye view that is line-symmetrical with respect to two directions orthogonal to each other as symmetrical lines, and
the at least one of the plurality of elements is surrounded and isolated by the hollow space of the trench and the insulation film and provides a separate semiconductor device that withstands insulation breakdown with other of the plurality of elements adjacent to the at least one of the plurality of elements,
wherein the trench includes two side surfaces of the trench as wall surfaces opposite to each other configured to generate an electrostatic attraction force that prevents tiling of an island constituting an element forming region based on a resulting imbalance of electrostatic attraction forces.

US Pat. No. 10,395,973

ISOLATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a substrate including a trench and a plurality of active regions are defined by the trench, wherein the trench include a first trench and a second trench is wider than the first trench;
a liner lining over inner surfaces of the first and the second trenches;
a gap-fill layer formed over the liner to fill the first and the second the trenches; and
a capping layer formed between the liner and the gap-fill layer and extending over a top surface of the gap-fill layer to form a merged overhang in the first trench.

US Pat. No. 10,395,972

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

MagnaChip Semiconductor, ...

1. A semiconductor device comprising:a substrate;
a deep well region in the substrate;
a body region in the deep well region;
a source region in the body region;
a gate electrode formed on the substrate and overlapping with the body region;
a deep trench in the substrate;
a support formed between air claps respectively formed within the deep trench provided around two adjacent semiconductor devices, the support being configured to maintain a shape of respective air gaps; and
a channel stop implantation region at a bottom of the deep trench,
wherein the deep trench is tapered in shape so that an upper end of the deep trench has a greater width than a lower end of the deep trench.

US Pat. No. 10,395,971

DAM LAMINATE ISOLATION SUBSTRATE

TEXAS INSTRUMENTS INCORPO...

1. An apparatus, comprising:a lead frame;
a dam and adhesive on portions of the lead frame; and
an integrated circuit die having a portion on the dam and another portion on the adhesive, wherein the lead frame includes two lead frames.

US Pat. No. 10,395,963

ELECTROSTATIC CHUCK

ENTEGRIS, INC., Billeric...

1. An electrostatic chuck comprising:an electrode; and
a surface layer activated by a voltage in the electrode to form an electric charge to electrostatically clamp a substrate to the electrostatic chuck, the surface layer including:
(i) a dielectric comprising a bulk resistivity greater than about 1012 ohm-cm;
(ii) a plurality of protrusions extending to a height above portions of the surface layer surrounding the protrusions to support the substrate upon the protrusions during electrostatic clamping of the substrate, the protrusions being substantially equally spaced across the surface layer as measured by a center to center distance between pairs of neighboring protrusions, the protrusions comprising a low stress material having an internal compressive film stress less than about 450 MPa and comprising an overcoating of diamond like carbon; and
(iii) a charge control surface layer coating overlying the dielectric and comprising a thickness in the range of from about 0.1 microns to about 10 microns and a surface resistivity in the range of from about 1×108 ohms/square to about 1×1011 ohms/square, the charge control surface layer comprising a surface coating layer comprising portions of the surface layer surrounding the protrusions, above which the protrusions extend.

US Pat. No. 10,395,962

SUBSTRATE ARRANGEMENT APPARATUS AND SUBSTRATE ARRANGEMENT METHOD

SCREEN Holdings Co., Ltd....

10. A substrate arrangement apparatus for disposing each of a plurality of first substrates in a first substrate group between each pair of a plurality of second substrates in a second substrate group,wherein each substrate in said first substrate group and said second substrate group is curved in a first radial direction to one side in the thickness direction with a minimum curvature, and
said each substrate is curved in a second radial direction to said one side in the thickness direction with a maximum curvature, said second radial direction being orthogonal to said first radial direction with an angle that is greater than or equal to 45 degree and less than or equal to 135 degrees,
wherein the substrate arrangement apparatus comprises
a controller for disposing each of said plurality of first substrates between each pair of said plurality of second substrates, in a state that said first radial direction of said plurality of first substrates is orthogonal to said first radial direction of said plurality of second substrates.

US Pat. No. 10,395,961

POSTURE CHANGING DEVICE

SCREEN Holdings Co., Ltd....

1. A posture changing device for changing a posture of a substrate from one of horizontal and vertical postures to the other posture, the device comprising:a vertical holder for, when a substrate is in a vertical posture, catching and holding a lower edge portion of said substrate on two sides in a circumferential direction of a bottom edge portion of said substrate, with said bottom edge portion projecting downward from said vertical holder;
a horizontal holder for, when said substrate is in a horizontal posture, supporting a lower surface of said substrate from underside on two sides in a radial direction of said substrate, said horizontal holder being disposed above and adjacent to said vertical holder in a state in which said vertical holder holds said substrate in a vertical posture;
a mounting block on which said vertical holder and said horizontal holder are mounted;
a holder rotator that rotates said mounting block about a rotational shaft pointing in a horizontal direction to switch between a vertical holding state and a horizontal holding state, said vertical holding state being a state in which said vertical holder is capable of holding said substrate in a vertical posture, and said horizontal holding state being a state in which said horizontal holder is capable of holding said substrate in a horizontal posture;
a holder shifter that shifts said horizontal holder relative to said vertical holder in a thickness direction of said substrate;
a pusher for transferring said substrate held in a vertical posture to and from said vertical holder;
a controller for, before transfer of said substrate between said vertical holder and said pusher, controlling said holder shifter on the basis of a warped state of said substrate to shift a position in said thickness direction of said horizontal holder by a shift distance from said vertical holder, said shift distance being determined on the basis of said warped state; and
a substrate alignment mechanism for rotating said substrate in a circumferential direction to change a circumferential orientation of said substrate,
wherein, when said substrate is curved in one radial direction to one side in said thickness direction with a minimum curvature, said controller controls said substrate alignment mechanism on the basis of the warped state of said substrate, before transfer of said substrate between said vertical holder and said pusher, to make said one radial direction of said substrate that is held in a vertical posture by said vertical holder, parallel to an up-down direction.

US Pat. No. 10,395,959

SUBSTRATE TRANSPORT

Brooks Automation, Inc., ...

21. A substrate transport comprising:a housing forming an interior environment for housing at least one substrate in a first atmosphere, the housing including
an opening to the interior environment,
a fluid reservoir forming a fluidic barrier non-contacting seal with a second atmosphere different from and external to the first atmosphere where the fluid reservoir is a consumable of the fluidic barrier non-contacting seal that seals contactless the interior environment from the second atmosphere,
a door configured to close the opening, where when the opening is closed the housing is configured to maintain the first atmosphere within the interior environment, and
a redundant seal arrangement disposed on at least one of the housing and the door, the redundant seal arrangement including at least a first seal disposed around a periphery of the opening and at least a second seal where the second seal is disposed between the first seal and the fluidic barrier non-contacting seal.

US Pat. No. 10,395,958

METHODS FOR INSPECTION SAMPLING ON FULL PATTERNED WAFER USING MULTIPLE SCANNING ELECTRON BEAM COLUMN ARRAY

1. A method of operating a multi-column electron beam array, the method comprising:dividing a whole wafer area collectively in equally divided areas allocated to each column of the array;
assigning each of the areas as a column working space having the same dimensions and orientations;
aligning the array of column working spaces to an array of column optical axes;
wherein a field of view of each column is defined as a covered region in which critical wafer patterns can be scanned by one column to take an image;
moving the stage supporting the wafer such that each column working space is fully covered by the field of view of each column completely;
scanning and imaging all critical sites inside the working space while ignoring non-critical patterns; and
wherein a position and dimension of critical sites in different working spaces is independently determined by an algorithm that accounts for lithography conditions and critical features in the patterning database.

US Pat. No. 10,395,957

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus, comprising:a substrate processing unit including a plurality of processing chambers each configured to perform a process on a substrate;
a mounting unit configured to mount thereon at least one carrier, each carrier comprising substrates to be processed;
wherein the substrates of each carrier are processed in accordance with a processing recipe;
wherein each carrier possesses a first substrate number, the first substrate number indicating the number of substrates to be processed per unit time in the substrate processing unit according to the processing recipe;
a substrate transfer device provided between the mounting unit and the processing chambers, wherein the substrate transfer device comprises a transfer arm holding the substrate; and
a computer having:
a memory which stores a plurality second substrate numbers, each second substrate number indicating the number of substrates capable of being processed per unit time in the substrate processing unit for a given operating speed of the substrate transfer device; and
wherein the memory stores a mapping table that correlates each of the plurality of second substrate numbers with a respective operating speed of the substrate transfer device, and
a controller configured to:
compare a first substrate number with each of the plurality of second substrate numbers in the mapping table,
when the first substrate number is not equal to the second substrate number, select, from the mapping table, a smallest second substrate number from the plurality of second substrate numbers that is larger than the first substrate number; and
control the substrate transfer device based on the operating speed in the mapping table which corresponds to the smallest second substrate number.

US Pat. No. 10,395,955

METHOD AND SYSTEM FOR DETECTING A COOLANT LEAK IN A DRY PROCESS CHAMBER WAFER CHUCK

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:configuring a dry wafer processing chamber to process a wafer, wherein the dry wafer processing chamber comprises a wafer chuck with a flat mounting surface for mounting the wafer for processing, the wafer chuck is further configured to include a coolant loop within the wafer chuck, and the coolant loop is disposed under the wafer for transferring heat and cooling the wafer chuck by a coolant during a cooling phase of the processing;
measuring relative humidity (RH) of the dry wafer processing chamber;
detecting a change in the RH greater than a threshold value, the change being caused by a leak in the coolant; and
triggering a shutdown of the processing in response to the change.

US Pat. No. 10,395,949

SUBSTRATE DRYING APPARATUS, STORAGE MEDIUM, AND SUBSTRATE DRYING METHOD

Ebara Corporation, Tokyo...

1. A substrate drying apparatus, comprising:a substrate rotating mechanism configured to rotate a substrate within a horizontal plane;
a rinse agent nozzle configured to eject a rinse agent to the substrate while moving away from a center of the substrate relative to the substrate rotated by the substrate rotating mechanism;
an IPA gas nozzle configured to spout an IPA gas to the substrate while moving away from the center of substrate relative to the substrate rotated by the substrate rotating mechanism with movement of the rinse agent nozzle;
a liquid area sensor mounted on an arm and a dried area sensor mounted on the arm, the sensors respectively configured to sense a film thickness of a liquid film on a surface of the substrate at two places around an interface of the rinse agent by moving away from the center of the substrate with movement of the rinse agent nozzle and the IPA gas nozzle while a rinse agent flow from the rinse agent nozzle and an IPA gas flow from the IPA gas nozzle are supplied to the surface; and
a control unit configured to control drying conditions comprising a rinse agent ejection amount, an arm swing speed, and a substrate rotation speed based on a sensing result of the liquid area sensor and the dried area sensor such that the interface of the rinse agent is spread on the surface of the substrate toward an outer circumference of the substrate by the rinse agent and the drying gas,
wherein the rinse agent nozzle and the IPA gas nozzle are arranged such that the landing area of the rinse agent is on the upstream side compared with the landing area of the IPA gas when viewed in the rotation direction of the substrate.

US Pat. No. 10,395,947

MANUFACTURING METHOD OF A RESIN MOLDED ARTICLE

DENSO CORPORATION, Kariy...

1. A manufacturing method of a resin molded article including:a thermosetting resin member made of thermosetting resin; and a thermoplastic resin member made of thermoplastic resin to seal a sealed surface as part of a surface of the thermosetting resin member, wherein an exposed surface as a remaining part of the surface of the thermosetting resin member is exposed from the thermoplastic resin member, the manufacturing method comprising:
completely hardening, by heating, the thermosetting resin material to form the thermosetting resin member into a shape of a cuboid by using a thermosetting resin material as a raw material of the thermosetting resin member;
removing a surface layer on a topmost surface in at least part of the sealed surface of the thermosetting resin member to form the at least part of the sealed surface as a newly formed surface containing a functional group;
adding, into a thermoplastic resin material as a raw material of the thermoplastic resin member, a functional group-containing additive containing a functional group that is to be chemically bound to the functional group on the newly formed surface, to prepare a material doped with the functional group-containing additive; and
plasticizing injection molding by injection molding the material doped with the functional group-containing additive onto the thermosetting resin member formed with the newly formed surface, and
sealing the sealed surface of the thermosetting resin member with the thermoplastic resin member while chemically binding the functional group on the newly formed surface to the functional group in the functional group-containing additive with which the thermoplastic resin material is doped, wherein
in the removing of the surface layer, the newly formed surface containing the functional group corresponds to a base for the surface layer and the newly formed surface is a roughened surface that is formed as a closed ring that extends around four sides of the cuboid of the thermosetting resin member.

US Pat. No. 10,395,942

ETCHING DEVICE, SUBSTRATE PROCESSING APPARATUS, ETCHING METHOD AND SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....

1. An etching device that performs etching processing using an organic solvent on a process film that is formed on a substrate and made of a Directed Self Assembly material, comprising:a pure water supplier that supplies only pure water to the process film;
an organic solvent supplier that, after the pure water is supplied to the process film by the pure water supplier, supplies the organic solvent to the process film with the pure water remaining on the process film; and
a rinse liquid supplier that, after the organic solvent is supplied by the organic solvent supplier, supplies the pure water used as a rinse liquid to the process film with the organic solvent remaining on the process film.

US Pat. No. 10,395,938

WAFER ELEMENT WITH AN ADJUSTED PRINT RESOLUTION ASSIST FEATURE

INTERNATIONAL BUSINESS MA...

1. A wafer element fabrication method, comprising:forming a single device element directly on an upper surface of a substrate such that the single device element comprises an upper device element surface and a sidewall extending exclusively vertically in a height dimension from the upper surface to the substrate;
forming an adjusted print resolution assist feature (APRAF) directly on the upper surface of the substrate such that the APRAF is smaller than the device element in at least the height dimension; and
depositing surrounding oxide material, which is different from materials of the APRAF, to surround an entirety of the APRAF and to lie directly on the upper surface of the substrate in abutment with an entirety of the sidewall of the single device element.

US Pat. No. 10,395,936

WAFER ELEMENT WITH AN ADJUSTED PRINT RESOLUTION ASSIST FEATURE

INTERNATIONAL BUSINESS MA...

1. A wafer element, comprising:a substrate comprising an upper substrate surface;
a single device element formed directly on the upper substrate surface and comprising an upper device element surface and a sidewall extending exclusively vertically in a height dimension from the upper device element surface to the upper substrate surface;
an adjusted print resolution assist feature (APRAF) formed directly on the upper substrate surface proximate to the single device element, the APRAF being:
smaller than the single device element in at least the height dimension as measured from an uppermost portion thereof to the upper substrate surface, and
tapered with a wide base at the upper substrate surface and a pointed tip at the uppermost portion; and
oxide disposed to surround an entirety of the APRAF and to lie on the upper device element surface and directly on the upper substrate surface in abutment with an entirety of the sidewall of the single device element.

US Pat. No. 10,395,926

MULTIPLE PATTERNING WITH MANDREL CUTS FORMED USING A BLOCK MASK

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:forming a first mandrel line over a hardmask layer;
forming a first block mask over a first portion of the first mandrel line that is linearly arranged between respective second portions of the first mandrel line; and
after forming the first block mask, removing the second portions of the first mandrel line with a first etching process to cut the first mandrel line and expose respective first portions of the hardmask layer,
wherein a second portion of the first mandrel line is covered by the first block mask during the first etching process to define a mandrel cut in the first mandrel line.

US Pat. No. 10,395,925

PATTERNING MATERIAL FILM STACK COMPRISING HARD MASK LAYER HAVING HIGH METAL CONTENT INTERFACE TO RESIST LAYER

International Business Ma...

1. A lithographic patterning method, comprising:forming a multi-layer patterning material film stack on a semiconductor substrate, wherein forming the patterning material film stack comprises forming a hard mask layer and forming a resist layer over the hard mask layer, and wherein an interface portion of the hard mask layer proximate the resist layer has a higher metal content than other portions of the hard mask layer;
exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer;
developing the pattern formed in the resist layer;
etching the hard mask layer in accordance with the developed pattern; and
removing remaining portions of the resist layer.

US Pat. No. 10,395,922

ATOMIC LAYER DEPOSITION SEALING INTEGRATION FOR NANOSHEET COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH REPLACEMENT SPACER

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device comprising:etching exposed portions of a stack of at least two semiconductor materials with an etch process, wherein the etch process includes a stage that removes one of the at least two semiconductor materials at a faster rate than a second of the at least two semiconductor materials to provide a divot region undercutting an overlying spacer, wherein the etch process removes one of the at least two semiconductor materials so that the remaining semiconductor material provides suspended source and drain semiconductor material layers; and
forming a plurality of atomic layer deposited (ALD) conformal dielectric monolayers that fills the divot region, wherein a seam is centrally positioned in the divot resulting from two portions of the conformal dielectric contacting each other in the ALD conformal dielectric layer that fills the divot region.

US Pat. No. 10,395,920

ALKYL-ALKOXYSILACYCLIC COMPOUNDS

VERSUM MATERIALS US, LLC,...

1. A composition for a vapor deposition of a dielectric film comprising a silacyclic compound having the following Formula I:wherein R1 is independently selected from hydrogen, a linear or branched C1 to C10 alkyl group, a linear or branched C2 to C10 alkenyl group, a linear or branched C2 to C10 alkynyl group, a C3 to C10 cyclic alkyl group, a C3 to C10 hetero-cyclic alkyl group, a C5 to C10 aryl group, and a C3 to C10 hetero-aryl group; R2 is selected from hydrogen, a linear or branched C1 to C10 alkyl group, a linear or branched C2 to C10 alkenyl group, a linear or branched C2 to C10 alkynyl group, a C3 to C10 cyclic alkyl group, a C3 to C10 hetero-cyclic alkyl group, a C5 to C10 aryl group, and a C3 to C10 hetero-aryl group; and R3 is selected from a C3 to C10 alkyl di-radical which forms a four-membered, five-membered, or six-membered cyclic ring with the Si atom, wherein the compound is substantially free of at least one impurity selected from the group consisting of halides and water.

US Pat. No. 10,395,919

METHOD AND APPARATUS FOR FILLING A GAP

ASM IP Holding B.V., Alm...

1. A method for filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising:in a cycle, providing an anisotropic plasma comprising a noble gas to bombard a bottom area of a surface of the one or more gaps with ions thereby creating adsorption sites comprising dangling bonds for a first reactant at the bottom area;
in the cycle, after the step of providing an anisotropic plasma, introducing the first reactant to the substrate; and,
in the cycle, allowing the first reactant to react with the created adsorption sites at the bottom area of the surface relative to side walls of the surface to deposit material on the bottom surface relative to the side walls, and
repeating the cycle to fill the one or more gaps from the bottom area upwards,
wherein during introducing the first reactant, a sputtering plasma is created by providing a sputtering gas to relocate material in a top area of the surface relative to the bottom area of the surface.

US Pat. No. 10,395,918

METHOD AND SYSTEM FOR CONTROLLING PLASMA IN SEMICONDUCTOR FABRICATION

TAIWAN SEMICONDUCTOR MANU...

1. A method for controlling a plasma in semiconductor fabrication, comprising:generating the plasma by a remote plasma module;
providing a compound mixing member connected to the remote plasma module by a line, wherein the compound mixing member includes a main body having a first outer surface and a second outer surface and a first end surface and a second end surface opposing the first end surface, the first end surface and the second end surface connecting the first outer surface and the second outer surface;
directing the plasma from the remote plasma module through the line extending into the compound mixing member through a first inlet port disposed on the first end surface;
directing a first processing gas into the compound mixing member through a second inlet port on the second outer surface and directing a second processing gas into the compound mixing member through a third inlet port on the first outer surface, wherein the first processing gas is different than the second processing gas;
mixing the plasma with the first processing gas at a first point and the second processing gas at a second point in a flow path within a body of the compound mixing member, wherein a distance interposes the first point and the second point, and wherein the second point is further from the first inlet port than the first point by the distance;
prior to the mixing, acquiring a parameter data of the plasma while in the compound mixing member wherein the acquiring is performed through a window in the second outer surface;
after acquiring the parameter data, passing the mixed plasma, first processing gas, and second processing gas out of the compound mixing member through an outlet port in the second end surface;
comparing the parameter data to a preset parameter specification; and
terminating operation of the remote plasma module if the parameter data falls outside the preset parameter specification and wherein if the parameter data falls inside the preset parameter specification.

US Pat. No. 10,395,914

EFFICIENT ION TRAPPING

MICROMASS UK LIMITED, Wi...

1. An ion trapping system comprising:a plurality of electrodes;
one or more voltage supplies connected to the electrodes, wherein the electrodes and the one or more voltage supplies are adapted and configured to provide an ion trap;
an ion entrance for receiving ions into the ion trap along an ion entrance axis, in use;
an ion ejecting system for ejecting ions from the ion trap along an ion exit axis in use, wherein the electrodes and voltage supplies are configured such that the maximum dimension over which the ion trap extends orthogonal to the entrance axis is greater than the maximum dimension over which the ion trap extends parallel to the entrance axis; and
further comprising one or more of the following:
an ion deflector arranged upstream of the ion trap, wherein the ion deflector is configured to deflect at least some of the ions travelling towards the ion trap such that ions entering the ion trap enter an ion trapping region at different locations; and/or
an ion deflector arranged upstream of, or at the entrance to, the ion trap, wherein the ion deflector is configured to deflect at least some of the ions travelling towards or into the ion trap such that ions enter the ion trap with different speeds orthogonal to the entrance axis so that the ions spread out within the ion trap in a direction orthogonal to the entrance axis.

US Pat. No. 10,395,906

MEASUREMENT ERROR CORRECTION METHOD BASED ON TEMPERATURE-DEPENDENT DISPLACEMENT IN MEASUREMENT DEVICE AND MASS SPECTROMETER USING THE SAME METHOD

SHIMADZU CORPORATION, Ky...

1. A measurement error correction method based on a temperature-dependent displacement in a measurement device, the measurement error correction method to be used in a measurement device configured to perform a predetermined measurement and acquire measurement data, for correcting an error or discrepancy in measurement data due to a thermal expansion of a specific component member included in the measurement device and having a length contributing to the measurement data, the measurement error correction method comprising:placing a reference member in a same temperature atmosphere as the component member, the reference member made of a material whose coefficient of thermal expansion is different from a coefficient of thermal expansion of the component member; and
measuring a difference in length between the component member and the reference member, with the two members individually demonstrating a thermal expansion in the same temperature atmosphere, and correcting measurement data obtained by a measurement, based on the difference in length.

US Pat. No. 10,395,901

PLASMA IGNITION AND SUSTAINING APPARATUS

Lam Research Corporation,...

1. An apparatus for generating a plasma in a vessel, comprising,a first comb structure configured to partially encircle a circumference of the vessel used to generate the plasma, the first comb structure having a first end and a second end, such that a first separation distance is defined between the first end and the second end, the first comb structure defining a first plurality of fingers oriented perpendicular to the circumference of the vessel, and wherein the first comb structure is configured to be connected to a first end of a coil that is configured to receive an radio frequency (RF) driver signal for generating the plasma in the vessel; and
a second comb structure configured to partially encircle the circumference of the vessel, the second comb structure having a first end and a second end, such that a second separation distance is defined between the first end and the second end of the second comb structure, the second comb structure defining a second plurality of fingers oriented perpendicular to the circumference of the vessel, and wherein the second comb structure is configured to be connected to a second end of the coil;
wherein the first plurality of fingers of the first comb structure are further oriented to face the second plurality of fingers of the second comb structure;
wherein a gap is defined between ends of the first and second plurality of fingers.

US Pat. No. 10,395,900

PLASMA PROCESSING APPARATUS

Samsung Electronics Co., ...

1. A plasma processing apparatus comprising:a chamber;
a window plate disposed in an upper portion of the chamber and having a fastening hole; and
an injector configured to be disposed in the fastening hole, the injector including a first body having a plurality of distribution nozzles for distributing a process gas, and a second body having an accommodating groove to which the first body is configured to be fastened and having a plurality of injection nozzles for injecting the process gas to an interior of the chamber when the injector is disposed in the fastening hole.

US Pat. No. 10,395,895

FEEDBACK CONTROL BY RF WAVEFORM TAILORING FOR ION ENERGY DISTRIBUTION

MKS Instruments, Inc., A...

12. A method for controlling a radio frequency (RF) generator comprising:detecting spectral emissions from a load, the spectral emissions including at least one a harmonic and intermodulation distortion (IMD); and
varying a parameter of an RF output signal of a RF power source in accordance with one of the harmonic or the IMD detected in the spectral emissions, wherein the parameter is one of phase, frequency, or amplitude.

US Pat. No. 10,395,886

APPARATUS OF PLURAL CHARGED-PARTICLE BEAMS

ASML Netherlands B.V., V...

1. A multi-beam apparatus for observing a surface of a sample, comprising:an electron source;
a condenser lens below said electron source;
a source-conversion unit below said condenser lens;
an objective lens below said source-conversion unit;
a deflection scanning unit below said source-conversion unit;
a sample stage below said objective lens;
a beam separator below said source-conversion unit;
a secondary projection imaging system; and
an electron detection device with a plurality of detection elements,
wherein said electron source, said condenser lens and said objective lens are aligned with a primary optical axis of said apparatus, and said sample stage sustains said sample so that said surface faces to said objective lens,
wherein said source-conversion unit comprises a beamlet-forming means with a plurality of beam-limit openings and an image-forming means with a plurality of electron optics elements,
wherein said electron source generates a primary-electron beam along said primary optical axis, and said primary-electron beam is focused by said condenser lens to become a substantially parallel beam and then incident into said source-conversion unit,
wherein a plurality of beamlets of said primary-electron beam exits from said source-conversion unit, said plurality of beamlets respectively passes through said plurality of beam-limit openings and is deflected by said plurality of electron optics elements towards said primary optical axis, and deflection angles of said plurality of beamlets are different;
wherein said plurality of beamlets is focused by said objective lens onto said surface and forms a plurality of probe spots thereon, said deflection scanning unit deflects said plurality of beamlets to scan said plurality of probe spots respectively over a plurality of scanned regions within an observed area on said surface, and currents of said plurality of probe spots are limited by said plurality of beam-limit openings,
wherein a plurality of secondary electron beams is generated by said plurality of probe spots respectively from said plurality of scanned regions and directed into said secondary projection imaging system by said beam separator, said secondary projection imaging system focuses and keeps said plurality of secondary electron beams to be detected by said plurality of detection elements respectively, and each detection element therefore provides an image signal of one corresponding scanned region,
wherein said deflection angles are individually set to reduce aberrations of said plurality of probe spots respectively.

US Pat. No. 10,395,885

CHARGED PARTICLE DEVICE, CHARGED PARTICLE IRRADIATION METHOD, AND ANALYSIS DEVICE

HITACHI, LTD., Tokyo (JP...

1. A charged particle device, comprising:a charged particle source which generates charged particles;
a sample table on which a sample is placed; and
a transport optical system which is disposed between the charged particle source and the sample table and is configured to transport the charged particles as charged particle flux toward the sample table, the transport optical system comprising
a magnetic field generating section which generates a magnetic field having a perpendicular component to a course of the charged particle flux;
an electric field generating section which generates an electric field having a perpendicular component to the course of the charged particle flux; and
a shielding section which shields at least a part of the charged particle flux passed through the magnetic field generating section and the electric field generating section; and
a separation optical system comprising the magnetic field generating section and the electric field generating section,
wherein the perpendicular component of the magnetic field has a magnetic field gradient,
wherein the perpendicular component of the electric field provides an electrostatic force in a direction opposite to a Lorentz force received by the charged particle flux,
wherein the charged particle flux emitted out from the separation optical system have deviated distribution of the charged particles having upward spins and the charged particles having downward spins, and
wherein the shielding section increases a spin polarization degree of the charged particle flux by the shielding.

US Pat. No. 10,395,883

APERTURE SIZE MODULATION TO ENHANCE EBEAM PATTERNING RESOLUTION

Intel Corporation, Santa...

1. A blanker aperture array (BAA) for an e-beam tool, the BAA comprising:a first column of openings along a first direction and having a pitch, each opening of the first column of openings having a dimension in the first direction; and
a second column of openings along the first direction and staggered from the first column of openings, the second column of openings having the pitch, and each opening of the second column of openings having the dimension in the first direction, wherein a scan direction of the BAA is along a second direction orthogonal to the first direction, and wherein the openings of the first column of openings overlap with the openings of the second column of openings by at least 5% but less than 50% of the dimension in the first direction when scanned along the second direction.

US Pat. No. 10,395,874

AUXILIARY SWITCH

1. An auxiliary switch comprising:a housing including a first housing part and a second housing part separate from and releasably connected to the first housing part;
a printed circuit board fixedly mounted within the housing and having an electrical pad and an electrical contact connected to the electrical pad;
a terminal conductor electrically connected to the printed circuit board; and
an actuator mechanism mounted within the housing and having an electrical contactor engaged to the terminal conductor, wherein the actuator mechanism is configured to move within the housing and at least partially displace the electrical contact while maintaining engagement between the contactor and the terminal conductor.

US Pat. No. 10,395,873

CIRCUIT BREAKER, FASTENING ASSEMBLY THEREFOR, AND ASSOCIATED ASSEMBLY METHOD

EATON INTELLIGENT POWER L...

1. A fastening assembly for a circuit breaker, said circuit breaker comprising a base and a bimetal, said fastening assembly comprising:a heater element coupled to said bimetal and said base; and
a plurality of fastening members comprising a nut and a coupling member coupled to said nut, said nut being disposed between said heater element and said bimetal, said coupling member extending through said heater element and into said nut in order to minimize movement of said heater element with respect to said base,
wherein said nut comprises a stabilizing portion and a post portion extending outwardly from said stabilizing portion and away from said bimetal.

US Pat. No. 10,395,870

RELAY WITH FIRST AND SECOND ELECTROMAGNETS FOR PLACING AND KEEPING A CONTACT IN A CLOSED STATE

EPCOS AG, Munich (DE)

1. A relay comprising:a first terminal;
a second terminal;
a contact which in a closed state brings about an electrical connection between the first and second terminals and which in an opened state electrically disconnects the first and second terminals;
an armature which is mechanically connected to the contact;
a first electromagnet which is configured to move the armature from a first position to a second position, thereby placing the contact in the closed state if the first electromagnet is switched on; and
a second electromagnet which is an air-gap-free holding magnet and which is configured to keep the armature in the second position and to keep the contact in the closed state if the contact is in the closed state and the second electromagnet is switched on,
wherein the armature abuts the second electromagnet in the second position without an air gap in-between, does not abut the second electromagnet in the first position, and does not abut the first electromagnet in the second position, and
wherein the first and second electromagnet are arranged displaced from each other along the direction of the movement from the first position to the second position.

US Pat. No. 10,395,860

STRAIN GAUGE PROPORTIONAL PUSH BUTTON

Eaton Intelligent Power L...

1. A transmitter device comprising:a printed circuit board including one or more electrical components thereon; and
a push button comprising:
a flexible membrane;
a dome switch positioned beneath the flexible membrane and attached to the printed circuit board, the dome switch being proximate to the flexible membrane such that depression of the flexible membrane causes the dome switch to snap down and thereby form a closed circuit in the dome switch; and
a force sensor formed on or applied to the printed circuit board and positioned adjacent the dome switch, the force sensor generating an electrical output responsive to an amount of deflection of the printed circuit board caused by pressure exerted thereon by depression of the flexible membrane and the dome switch.

US Pat. No. 10,395,855

SWITCH

MITSUBISHI ELECTRIC CORPO...

1. A switch comprising:a first contact placed to be able to reciprocate in a first direction along an operating shaft and in a second direction opposite to the first direction;
a second contact placed on a side of the first direction with respect to the first contact to be able to reciprocate in the first direction and the second direction along the operating shaft;
a housing box to include inside a housing space housing one end of the second contact on the side of the first direction, to form an opening through which the second contact can pass, and to allow another end of the second contact opposite to the one end to be exposed to the outside of the housing space through the opening;
a surrounding portion erected in the second direction from the opening of the housing box and surrounding a side surface of the second contact;
a slide contact placed between the second contact and the surrounding portion and in contact with the second contact and the surrounding portion;
a partition to be formed integrally with a part of the second contact housed in the housing space and to partition the housing space into a first space on the side of the first direction and a second space on a side of the second direction; and
an energizing portion to energize the second contact in the first direction, wherein
the first contact, the second contact, the housing box, the surrounding portion, and the slide contact are each formed of a conductor,
the partition is formed of an insulator,
the first contact includes a first abutting portion to be able to come into contact with the side surface of the second contact, a second abutting portion formed on the side of the first direction with respect to the first abutting portion to be able to come into contact with an outer surface of the surrounding portion, and an arc generator placed on the side of the first direction with respect to the first abutting portion to generate an arc between the second contact and the arc generator,
a facing portion that faces the one end of the second contact is formed on a part of an inner wall surface forming the first space of the housing space, and
an insulating guide made of an insulator is placed in a part of the side surface of the second contact, the part coming into contact with the slide contact in a state in which the second contact is disposed on the side of the first direction by energizing force of the energizing portion.