US Pat. No. 10,191,835

MULTI-THREADED DEBUGGER SUPPORT

International Business Ma...

1. A method for managing debugging requests associated with a multi-threaded application, the method comprising:receiving, by a control program, a first memory buffer including a Transmission Control Protocol (TCP) request from a debugger, responsive to a first request from a set of debugging requests being input by a user via a graphical user interface, wherein the first memory buffer is associated with a thread of a process that has been designated for debugging, wherein the first memory buffer is separate and distinct from the thread, and wherein the TCP request instructs the control program to perform at least one action on the thread;
generating a bracket for the thread, based on analysis of the first memory buffer, wherein the bracket comprises a set of control registers and an address range associated with execution of the thread;
determining whether the action associated with the TCP request to be performed on the thread is one of an execute type action and a service type action;
responsive to determining the execute type action:
waking up the thread associated with the bracket;
placing the thread on a list for execution of the action; and
executing the thread, while performing the execute type action on the thread, until said thread falls into the address range specified by the bracket, wherein the execute type action manipulates the thread:
responsive to determining the service type action:
setting up a Program Control Block (PCB) for the thread; and
performing the service type action on the thread;
generating, by the control program, debugging event information comprising results associated with one of the execute type action and the service type action, wherein the debugging event information is at least based on the manipulated thread;
inserting the debugging information into the memory buffer associated with a TCP reply of the thread;
determining whether a reply flag associated with the memory buffer is ready to be sent out;
responsive to determining that the reply flag is ready:
passing the memory buffer to the debugger in accordance with the TCP reply; and responsive to determining that the reply flag is not ready;
checking a communication socket for determining whether a further user request has been made from the debugger:
if the further request has not been made:
sleeping the debugger for a period of time, while performing a subsequent check of the reply flag; and
if the further request has been made:
retrieving a user thread associated with the further user request:
modifying a new memory buffer to process the user thread; and
processing the user thread in accordance with the TCP request.

US Pat. No. 10,191,834

METHODS AND SYSTEMS TO IDENTIFY AND REPRODUCE CONCURRENCY VIOLATIONS IN MULTI-THREADED PROGRAMS

Intel Corporation, Santa...

1. A method to identify threads responsible for causing a concurrency violation in a multi-threaded program comprising:executing, with a processor, at least one of a plurality of thread controllers inserted into respective threads of a plurality of threads of a multi-threaded program to be debugged, a first thread controller of the plurality of thread controllers controlling an order in which first operations of a first respective thread of the plurality of threads are executed relative to second operations of a second thread of the plurality of threads, the controlling of the order in which first operations are executed relative to second operations including, when a first condition is met in the first thread, the first thread controller causing the first thread to stall, the stalling of the first thread to cause the first condition to remain satisfied while the other threads of the multi-threaded program continue to execute;
causing the concurrency violation to occur based on a determination that a threshold number of a plurality of respective conditions defined in the respective thread controllers have been concurrently satisfied;
based on the occurrence of the concurrency violation, identifying the respective threads that define the respective conditions that have been satisfied as being responsible for causing the concurrency violation; and
when the threshold number of the plurality of respective conditions have not been satisfied within a threshold duration, halting the plurality of threads of the multithreaded program.

US Pat. No. 10,191,832

MULTI-LANGUAGE PLAYBACK FRAMEWORK

Microsoft Technology Lice...

1. One or more computer-readable storage media storing computer-executable instructions, which when executed by a computer, cause the computer to perform operations, the operations comprising:receiving a language-neutral script comprising a plurality of recorded actions to perform on respective user interface elements of a software product supporting multiple languages;
receiving a language file mapping properties of the respective user interface elements of the language-neutral script to properties of user interface elements in a target language among the multiple languages supported by the software product; and
executing the language-neutral script on a playback engine interfacing with a build of the software product in the target language, wherein executing the language-neutral script on the playback engine comprises:
identifying, among the plurality of recorded actions of the language-neutral script, a given recorded action corresponding to a recorded user interface element of the language-neutral script, the recorded user interface element comprising a plurality of properties, wherein each property of the plurality of properties is a different property type;
finding an under-test user interface element of the build of the software product in the target language equivalent to the recorded user interface element of the language-neutral script by performing an ordered search for the properties of the recorded user interface element within the language file, the ordered search evaluating the properties of the recorded user interface element in a predefined order that prioritizes the different property types relative to each other; and
performing the given recorded action of the language-neutral script on the matching under-test user interface element of the build of the software product in the target language.

US Pat. No. 10,191,830

DATA PROCESSING SYSTEMS FOR PROCESSING AND ANALYZING DATA REGARDING SELF-AWARENESS AND EXECUTIVE FUNCTION

EXQ, LLC, Atlanta, GA (U...

1. A data processing system for processing data regarding performance evaluation for use in the development of a first user's executive functions, the data processing system comprising:a. at least one computer processor; and
b. memory operatively coupled to the at least one computer processor; wherein the at least one computer processor is adapted for:
i. executing computer-readable instructions that, when executed by the at least one computer processor, facilitate performing an electronic activity by the first user;
ii. gathering performance data indicating the first user's performance while the first user performs the electronic activity;
iii. calculating a performance score for the first user based at least in part on the gathered performance data indicating the first user's performance;
iv. digitally storing the performance score for the first user in an electronic record associated with the first user;
v. executing computer-readable instructions that, when executed by the at least one computer processor, facilitate evaluating, by the first user, the electronic activity completed by the first user;
vi. displaying, via a graphical user interface, a visual representation that presents a replay of the first user completing the electronic activity;
vii. while displaying the visual representation presenting a replay of the first user completing the electronic activity, gathering feedback data from the first user indicating the first user's performance on the electronic activity;
viii. automatically calculating a self-awareness score of the first user based at least in part on the feedback data provided by the first user, wherein the self-awareness score of the first user is different from the performance score for the first user; and
ix. digitally storing the self-awareness score of the first user in the electronic record associated with the first user.

US Pat. No. 10,191,829

SEMICONDUCTOR DEVICE AND FAULT DETECTION METHOD THEREFOR

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a processor coupled to a storage device storing instructions for executing:
an arithmetic unit that performs processing for executing a computer program;
a plurality of sound units that convert sound data stored in a memory into a serial signal, add sampling frequency information of the sound data to the serial signal and output the serial signal to a plurality of external terminals, and convert the sound data input from one of the plurality of the external terminals into a parallel signal, add the sampling frequency information of the sound data to the parallel signal, and transfer the parallel signal to the memory;
a route switching unit that switches a transfer route of sound data input to and output from the plurality of sound units, the route switching unit being provided between the plurality of sound units and the plurality of external terminals; and
a memory transfer controller that includes a plurality of memory-transfer control units that control transmission and reception of data between the memory and the plurality of sound units, and a unit control unit that controls the plurality of memory-transfer control units,
wherein the arithmetic unit controls the route switching unit according to the computer program to configure first to third sound data transfer routes configured by one of the sound units and one of the memory-transfer control units, transfers reproduction sound data stored in the memory from the memory to a side of the external terminals via the first sound data transfer route, and transfers two recording sound data generated on account of the reproduction sound data from. the side of the external terminals to the memory via the second and third sound data transfer routes,
wherein the arithmetic unit accumulates, in the memory, two pieces of the recording sound data transferred using the second and third sound. data transfer routes and compares the reproduction sound data and the two pieces of recording sound data and detects a fault in the sound data transfer routes,
wherein the plurality of sound units generate a first count value indicating a length of a cycle of a sampling frequency of the sound data,
wherein the plurality of memory-transfer control units generate a second count mile indicating a length of a transfer interval of the sound data,
wherein the unit control unit generates a third count value indicating a length of a generation interval of a data control signal output by the sound units,
wherein, when the first count value and a first expected value indicating an expected value of the first count value set in advance do not coincide with each other, the arithmetic unit determines that the sound unit has a fault,
wherein, when the second count value and a second expected value indicating an expected value of the second count value set in advance do not coincide with each other, the arithmetic unit determines that the memory-transfer control unit has a fault, and
wherein, when the third count value and a third expected value indicating an expected value of the third count value set in advance do not coincide with each other, the arithmetic unit determines that the sound data transfer route has a fault.

US Pat. No. 10,191,827

METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR UTILIZING LOOPBACK OPERATIONS TO IDENTIFY A FAULTY SUBSYSTEM LAYER IN A MULTILAYERED SYSTEM

SANDISK TECHNOLOGIES LLC,...

1. A method for utilizing loopback operations to identify a faulty subsystem layer in a multilayered system, the method comprising:executing a plurality of loopback operations using a respective plurality of loopback points positioned among subsystem layers of a multilayered system, wherein:
the plurality of loopback operations incrementally test loopback points in the plurality of loopback points; and
each loopback operation tests loopback points that have been previously tested during previously executed loopback operations;
detecting a failed loopback operation among the plurality of loopback operations; and
identifying a faulty subsystem layer among the subsystem layers by comparing the failed loopback operation against a previously conducted successful loopback operation corresponding to a preceding subsystem layer that is adjacent to the faulty subsystem layer within the multilayered system.

US Pat. No. 10,191,825

SYSTEM AND METHOD FOR TESTING A DEVICE USING A LIGHT WEIGHT DEVICE VALIDATION PROTOCOL

WIPRO LIMITED, Bangalore...

1. A method for testing a device, the method comprising:accessing, via a testing engine, a test script corresponding to a test case for testing the device, wherein the test script comprises a set of mutually independent primitive executables;
packetizing, via the testing engine, one or more of the set of primitive executables based on a light weight device validation (LWDV) protocol, wherein the LWDV protocol is configured to represent a message as a series of data fields, wherein the data fields comprise a SYNC byte field, a start byte field, a payload length field, a session identification field, a message identification field, a sequence identification field, a test case identification field, a core data field, and a checksum field, and wherein the message identification field comprises a more bit field; and
transmitting, via the testing engine, the one or more primitive executables to the device for execution, wherein transmitting the one or more primitive executables comprises:
determining an availability of each of one or more resources in the device via the LWDV protocol; and
transmitting the one or more primitive executables to the device based on the availability.

US Pat. No. 10,191,824

SYSTEMS AND METHODS FOR MANAGING A CLUSTER OF CACHE SERVERS

MZ IP Holdings, LLC, Pal...

1. A cache data management system, comprising:a plurality of webserver computers to handle cache data requests;
a computer cluster comprising a plurality of master cache data server computers without a corresponding plurality of slave cache data server computers to store reserve cache data; and
a plurality of proxy computers in communication with the plurality of webserver computers and the computer cluster,
wherein the plurality of proxy computers routes the cache data requests from the plurality of webserver computers to the computer cluster, and
wherein each proxy computer comprises:
a sentinel module to monitor a health of the computer cluster,
wherein the sentinel module detects failures of master cache data server computers; and
a trask monitor agent to manage the computer cluster,
wherein, in response to the sentinel module detecting a failed master cache data server computer, the trask monitor agent replaces the failed master cache data server computer with an initially empty reserve master cache data server computer, and
wherein the initially empty reserve master cache data server computer is populated with the reserve cache data from a master database.

US Pat. No. 10,191,822

HIGH PERFORMANCE PERSISTENT MEMORY

Rambus Inc., Sunnyvale, ...

1. A non-volatile memory module comprising:a circuit board;
a first memory device of a first memory type, the first memory device being disposed on the circuit board;
a second memory device of a second memory type, the second memory device being disposed on the circuit board, wherein the first memory device is volatile memory and the second memory device is non-volatile memory; and
a control element coupled to the first memory device and the second memory device, the control element being disposed on the circuit board, the control element to:
capture a base image of data stored in the first memory device;
store the base image of data in the second memory device;
capture incremental updates to the data stored in the first memory device;
update the base image stored in the second memory device with the incremental updates; and
in response to loss of power to the non-volatile memory module, restore the base image and any incremental updates to the first memory device.

US Pat. No. 10,191,821

COOPERATIVE DATA RECOVERY IN A STORAGE STACK

Dell Products, LP, Round...

1. A computer-implemented method of recovering data in response to a failed input/output request, the method comprising:in a memory storage stack having layers, including a lowest layer, at least one intermediate layer, and a highest layer, in a hierarchical order, wherein each layer has associated storage memory and one or more associated processor and wherein each intermediate layer has a first single layer immediately lower in hierarchical order and a second single layer immediately above in hierarchical order:
seeking data in hierarchical order from the highest layer to the lowest layer in the storage stack and responsive to a failed input/output (I/O) request for data, from a higher layer of the memory storage stack to a lower layer of the memory storage stack in the hierarchical order, generating, at the lower layer, a first help response and sending the first help response from the lower layer to the higher layer to recover the data;
at the higher layer, determining whether a recovery mechanism can fulfill the I/O request and, if not, generating a second help response and sending the second help response to a next higher layer of the memory storage stack in the hierarchical order;
at the next higher layer, determining whether a recovery mechanism can fulfill the I/O request and, if not, generating a third help response and sending the third help response to an even next higher layer of the memory storage stack in the hierarchical order;
in response to determining a recovery mechanism can fulfill the I/O request, obtaining the data using the recovery mechanism and providing the data to the higher layer in response to the I/O request; and
upon the help response reaching the highest layer of the memory storage stack, generating an error at the highest layer.

US Pat. No. 10,191,820

VIRTUAL PROXY BASED BACKUP

EMC IP Holding Company LL...

1. A backup method, comprising:configuring, by one or more processors, one or more virtual proxies associated with backup operations, wherein the one or more virtual proxies are hosted by one or more physical nodes in a cluster environment;
assigning, by one or more processors, one or more virtual machines in the cluster environment to a corresponding at least one of the one or more virtual proxies, wherein at least a subset of the one or more virtual machines is selected to be assigned to the at least one of the one or more virtual proxies based on a localization of the at least the subset of the one or more virtual machines in relation to the corresponding at least one virtual proxy;
performing, by one or more processors, data rollover during backup of at least one of the one or more virtual machines in the cluster environment that is subjected to backup using the corresponding at least one of the one or more virtual proxies to which the at least one of the one or more virtual machines is assigned.

US Pat. No. 10,191,819

DATABASE PROTECTION USING BLOCK-LEVEL MAPPING

Commvault Systems, Inc., ...

1. A data storage system for protecting database files, the system comprising:one or more primary storage devices that store a plurality of application-level blocks associated with a database, and one or more secondary storage devices that store a secondary copy of the database with a plurality of storage blocks, the plurality of storage blocks having a first granularity that is larger than a second granularity of the application-specific blocks;
an index stored in memory that maps the plurality of storage blocks with corresponding application-level blocks, wherein each of the plurality of storage blocks in the secondary copy spans a plurality of the application-level blocks;
in response to instructions to retrieve one or more requested application-level blocks associated with of a database file from the secondary copy, one or more secondary storage controller computers comprising computer hardware are configured to:
access the index that provides a mapping between the plurality of requested application-level blocks and corresponding plurality of storage blocks;
retrieve the corresponding plurality of storage blocks from the secondary copy; and
a data agent executing on one or more computer processors and configured to divide the corresponding plurality of storage blocks retrieved from the secondary copy into the one or more requested application-level blocks; and
a database application executing on one or more computer processors, the database application in communication with the data agent, the database application configured to receive the requested application-level blocks from the data agent.

US Pat. No. 10,191,818

FILTERED REPLICATION OF DATA IN DISTRIBUTED SYSTEM OF DATA CENTERS

SAP SE, Walldorf (DE)

1. A non-transitory computer readable storage medium storing instructions, which when executed by a computer cause the computer to:receive data from a first persistent storage unit associated with a primary data center, wherein receiving the data includes:
determine a modification of the data in the first persistent storage unit at regular time intervals, and
receive the data upon determining the modification of the data in the first persistent storage unit;
determine at least a part of the received data to be replicated by filtering the data based on one or more predetermined conditions, wherein the one or more predetermined conditions define relevant data to be replicated and the one or more predetermined conditions comprise filtering out the data not relevant to other data centers and filtering out restorable data; and
transmit the determined part of the data to replicate in a second persistent storage unit associated with a secondary data center to recover the part of the data during failure of the primary data center.

US Pat. No. 10,191,816

CLIENT-SIDE REPOSITORY IN A NETWORKED DEDUPLICATED STORAGE SYSTEM

Commvault Systems, Inc., ...

1. A method for restoring data to a client system from one or more secondary storage devices, the method comprising:performing with a media agent executing in or more computer processors, a secondary copy operation that copies a plurality of data blocks associated with one or more primary storage devices in a client system to one or more secondary storage devices located remotely from the one or more primary storage devices;
copying at least a portion of the data blocks and a first copy of hash signatures associated with the portion of the data blocks to a client-side repository comprising at least computer memory, wherein the client-side repository is different than the one or more secondary storage devices;
populating an index in communication with the media agent with a second copy of the hash signatures associated with the plurality of the data blocks stored in the one or more secondary storage devices;
receiving a request to restore data to the client system;
querying the client-side repository with the second copy of the hash signature from the index to determine whether the first copy of the hash signature is stored in the client-side repository;
if the querying the client-side repository with the second copy of the hash signature indicates that client-side repository is populated with the first hash signature, accessing the at least one data block associated with the restore data from the client-side repository;
if the querying the client-side repository with the second copy of the hash signature indicates that the client-side repository is not populated with the first hash signature, accessing the at least one data block associated with the restore data from the one or more secondary storage devices; and
monitoring the usage of the client-side repository and the one or more secondary storage devices and pruning the data in the client-side repository based at least in part on the percentage of data restored from the client-side repository.

US Pat. No. 10,191,815

PARALLEL NODE BACKUP FOR CSV

EMC IP Holding Company LL...

1. A method of backing up data stored on a cluster shared volume (CSV), comprising:storing on the cluster shared volume a snapshot of the cluster shared volume;
assigning to each of one or more cluster servers available to participate in backing up the cluster shared volume a task to back up a corresponding assigned portion of the snapshot to a backup storage node separate from the cluster shared volume and the one or more cluster servers, wherein the cluster shared volume is separate from the one or more cluster servers; and
monitoring the respective assigned tasks to completion,
wherein the one or more cluster servers have shared access to the snapshot as stored on the cluster shared volume and each is configured to perform the task assigned to it in parallel with any other cluster servers assigned to back up other portions of the same cluster shared volume snapshot.

US Pat. No. 10,191,814

RESTORING DATA IN A HIERARCHICAL STORAGE MANAGEMENT SYSTEM

International Business Ma...

1. A method for storing data in a hierarchical storage management (HSM) system, the method comprising:receiving, by a first controller, a request to migrate a data item to a first storage tier managed by the first controller, wherein (i) the request associates the data item with at least an initial object ID that is an object ID of a first version of the data item and (ii) the data item is associated with a HSM status parameter value that indicates that the data item is in a resident state, and, in response:
generating, by the first controller, a new object ID;
identifying, by the first controller, a first record in a data structure that includes a plurality of records based, at least in part, on the initial object ID being identical to an object ID of the first record and to a parent object ID of the first record;
replacing, by the first controller, the object ID of the first record with the new object ID;
creating, by the first controller, a new record in the data structure, wherein the new record is associated with the data item;
setting, by the first controller, an object ID field of the new record and a parent object ID field of the new record to the initial object ID; and
storing, by the first controller, the data item to the first storage tier.

US Pat. No. 10,191,813

DATA REPLICATION SNAPSHOTS FOR PERSISTENT STORAGE USING OPERATION NUMBERS

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:maintaining a master copy and a slave copy of a data volume, the master copy including data for a plurality of operations having respective sequential operation numbers, the data for the plurality of the operations being replicated to the slave copy;
generating a snapshot of the master copy, the snapshot being assigned a next operation number in an operation number sequence, the snapshot comprising snapshot data;
writing the snapshot data, as well as the operation number and metadata for the snapshot, to persistent storage; and
while writing the snapshot data to the persistent storage, processing subsequent input/output (I/O) operations by the master copy.

US Pat. No. 10,191,812

RECOVERY MECHANISM FOR LOW LATENCY METADATA LOG

Pavilion Data Systems, In...

1. A storage server comprising:a plurality of physical drives;
a management controller comprising a first memory; and
an input/output (IO) controller operatively coupled to the plurality of physical drives and to the management controller, the IO controller comprising a second memory, wherein the IO controller is to:
generate a first metadata update for a first page of a first metadata table, wherein the first metadata update is associated with storage of first data in at least one of a first physical block address (PBA) on a first physical drive of the plurality of physical drives or a first virtual block address (VBA) mapped to the first PBA;
generate a second metadata update for a second page of one of the first metadata table or a second metadata table, wherein the second metadata update is associated with at least one of the first VBA or the first PBA;
write a first cache entry to a first cache in a first memory of the management controller, the first cache entry comprising the first metadata update and the second metadata update;
write a copy of the first cache entry to a second cache in a second memory of the IO controller, wherein the second cache is a copy of the first cache; and
increment a commit pointer in the first cache and the second cache to indicate that the data has been stored in the first PBA and that all metadata updates associated with storage of the data at the first PBA have been committed.

US Pat. No. 10,191,811

DUAL BOOT COMPUTER SYSTEM

QUANTA COMPUTER INC., Ta...

1. A computer system, comprising:a processor;
a complex programmable logic device (CPLD);
a locally protected primary boot;
a locally modifiable secondary boot, wherein the CPLD is connected to the processor, and configured to control the processor with regard to selecting either the locally protected primary boot or the locally modifiable secondary boot, wherein the locally protected primary boot and the locally modifiable boot are individually partitioned, and the way the locally protected primary boot being partitioned is different from the way the locally modifiable boot being partitioned;
a computer-readable memory storing instructions which, when executed by the processor, causes the processor to perform operations comprising:
commencing a first boot sequence for the computer system with the primary boot;
restarting the computer system and commencing, in response to the restarting, a second boot sequence with the locally modifiable secondary boot;
if the second boot sequence with the secondary boot is successful, storing a copy of the secondary boot in a partition of the primary boot as one of a ONIE u-boot code, a u-boot environment, or a kernel code; and
if the second boot sequence with the secondary boot fails, restarting the computer system and re-commencing a third boot sequence with the primary boot.

US Pat. No. 10,191,810

MOBILE TERMINAL AND RELATED REPAIR METHOD

MEDIATEK SINGAPORE PTE. L...

1. A repair method for a mobile terminal, comprising:obtaining a current storage integrity information of a system partition of the mobile terminal;
matching the current storage integrity information and an original storage integrity information; and
connecting to a server, and obtaining an original system partition document from the server, and repairing the system partition according to the original system partition document when the matching fails,
wherein the step of connecting to the server, and obtaining original system partition document from the server, and repairing the system partition according to the original system partition document when the matching fails further comprising:
checking whether a logic block address of a storage device of the mobile terminal is damaged;
if the logic block address is not damaged, finding abnormal document of the system partition, and repairing the abnormal document according to the original system partition document; and
if the logic block address is damaged, connecting to the server, acquiring the original system partition document from the server, and repairing all document of the system partition according to the original system partition document.

US Pat. No. 10,191,809

CONVERTING A DATA CHUNK INTO A RING ALGEBRAIC STRUCTURE FOR FAST ERASURE CODING

International Business Ma...

1. A method comprising:at a storage manager of a storage system:
arranging a first data chunk into a ring structure;
tagging the first data chunk by appending extra data to the ring structure;
performing erasure coding on the first data chunk utilizing only exclusive or (XOR) operations and the ring structure, wherein erasure coded encoded data resulting from the erasure coding is written to a persistent storage device; and
maintaining an index pointer that references a portion of the ring structure;
wherein the ring structure allows for multiplication of data included in the first data chunk to be implemented by rotation of the data utilizing the index pointer, thereby increasing efficiency of the storage system as the multiplication is simplified to an adjustment of the index pointer.

US Pat. No. 10,191,808

SYSTEMS AND METHODS FOR STORING, MAINTAINING, AND ACCESSING OBJECTS IN STORAGE SYSTEM CLUSTERS

QUALCOMM Incorporated, S...

1. A method, implemented by processor-based logic of a storage system storing source objects as a plurality of fragments upon storage nodes of a plurality of cluster instances of storage system infrastructure components comprising a cluster set, wherein each cluster instance of the plurality of cluster instances operates as a unit for providing reliable storage of a different portion of a source object stored by the storage system, the method comprising:generating a plurality of first encoding fragments from the source object using a first encoding;
partitioning the plurality of first encoding fragments into a plurality of disjoint sets of first encoding fragments, wherein each set of first encoding fragments of the plurality of disjoint sets of first encoding fragments includes a plurality of first encoding fragments;
assigning a first set of first encoding fragments of the plurality of disjoint sets of first encoding fragments to a first cluster instance of the plurality of cluster instances, wherein the first set of first encoding fragments comprise a portion of the plurality of first encoding fragments of the source object to be stored upon the storage nodes of the first cluster instance of the plurality of cluster instances;
assigning a second set of first encoding fragments of the plurality of disjoint sets of first encoding fragments to a second cluster instance of the plurality of cluster instances, wherein the second set of first encoding fragments comprise a different portion of the plurality of first encoding fragments of the source object to be stored upon the storage nodes of the second cluster instance of the plurality of cluster instances;
generating a plurality of second encoding fragments from the first set of first encoding fragments using a second encoding, wherein the plurality of second encoding fragments include the plurality of first encoding fragments of the first set of first encoding fragments and one or more repair fragments generated from the first encoding fragments of the first set of encoding fragments; and
generating a plurality of third encoding fragments from the second set of first encoding fragments using a third encoding, wherein the plurality of third encoding fragments include the plurality of first encoding fragments of the second set of first encoding fragments and one or more repair fragments generated from the first encoding fragments of the second set of encoding fragments.

US Pat. No. 10,191,807

MEMORY SYSTEMS AND OPERATION METHOD THEREOF

SK hynix Inc., Icheon-si...

14. A memory system, comprising:a memory controller including a first-type error correction circuit suitable for generating a first error correction code using a first write data which is a portion of a write data form a host, and a second-type error correction circuit suitable for generating a second error correction code using a second write data which is a remaining portion of the write data, wherein error correction algorithms used by the first-type error correction circuit and the second-type error correction circuit are different from each other; and
a memory module including a plurality of first memory devices suitable for storing the first write data and the first error correction code, and one or more second memory device suitable for storing the second write data and the second error correction code.

US Pat. No. 10,191,806

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method for a rewritable non-volatile memory module comprising a plurality of memory cells, the decoding method comprising:reading, through a memory interface coupled to the rewritable non-volatile memory module, first data from a plurality of first memory cells under a read voltage among the memory cells;
performing, by an error checking and correcting circuit, a first decoding operation on the first data based on a first strict level of a plurality of predetermined strict levels of locating an error bit in the first data;
performing, by the error checking and correcting circuit, the first decoding operation again or a second decoding operation on the first data based on a second strict level or a third strict level of a plurality of predetermined strict levels of locating an error bit in the first data if the first decoding operation fails, comprising:
if an iteration number of the first decoding operation reaches a predetermined number, switching to the second strict level which is higher than the first strict level and performing the second decoding operation based on the second strict level, in order to reduce a probability of a bit being wrongly flipped in the second decoding operation;
if a number of bits flipped by the first decoding operation is zero, switching to the third strict level which is lower than the first strict level and performing the second decoding operation based on the third strict level, in order to raise a probability that at least one bit is flipped in the second decoding operation; and
otherwise, performing the first decoding operation on the first data based on the first strict level again; and
outputting the decoded first data by the error checking and correcting circuit.

US Pat. No. 10,191,805

SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor memory device, comprising:a memory cell array including first and second bank arrays, each bank array including first and second sub arrays;
an error correction circuit configured to perform an error correction code (ECC) encoding on write data to be stored in the memory cell array, and configured to perform an ECC decoding on read data from the memory cell array; and
a control logic circuit configured to control access to the memory cell array and configured to generate an engine configuration selection signal and a density mode signal based on a command,
wherein the error correction circuit is configured to reconfigure a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal,
wherein each unit for which ECC is performed corresponds to correcting an error bit among the read data having n bits, wherein n is a natural number greater than 2 and is variable in response to the engine configuration selection signal,
wherein when the density mode signal indicates a first density mode and the engine configuration selection signal indicates a first engine configuration mode, the error correction circuit is configured to operate as one ECC engine configured to perform an ECC encoding on 2h-bit write data to generate (h+1)-bit parity data, configured to perform an ECC decoding on 2h-bit read data and (h+1)-bit read parity data, and configured to store the 2h-bit write data and the (h+1)-bit parity data in the first bank array, wherein h is a natural number equal to or greater than two, and
wherein when the density mode signal indicates a second density mode and the engine configuration selection signal indicates a second engine configuration mode, the error correction circuit is configured to operate as a plurality of ECC engines, each ECC engine configured to perform an ECC encoding on 2f-bit write data of 2h-bit write data to generate (f+1)-bit parity data, and configured to perform an ECC decoding on 2f-bit read data and (f+1)-bit read parity data, and the ECC engines configured to store a group of the 2f-bit write data in a first sub array of the first bank array and to store a group of the (f+1)-bit parity data in a first sub array of the second bank array, wherein f is a natural number smaller than h.

US Pat. No. 10,191,804

UPDATING RELIABILITY DATA

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory device;
a reliability circuit coupled to the memory device and configured to receive hard data from the memory device and to determine reliability data assigned thereto, the reliability data comprising a first reliability data value in response to the hard data comprising a first value or comprising a second reliability data value in response to the hard data comprising a second value;
an error correction circuit coupled to the reliability circuit and configured to receive the hard data and the reliability data from the reliability circuit, wherein the error correction circuit is further configured to:
iteratively compute parity data for the hard data; and
increment or decrement the reliability data once per L-number of layers of parity data, wherein one iteration includes a plurality of layers of parity data.

US Pat. No. 10,191,803

REWRITING FLASH MEMORIES BY MESSAGE PASSING

California Institute of T...

1. A data storage device comprising:a host interface configured to receive a binary representation of a message m;
a non-volatile memory device;
a memory device interface coupled to the non-volatile memory device; and
a controller configured to:
receive the message m for storing the message m into n cells of the non-volatile memory device;
read a current state s of the n cells of the non-volatile memory device in which a previously received message has been stored;
determine a vector x based on the message m and the current state s of the n cells, wherein the vector x represents the message m and can be written into the n cells over the current state s of the n cells without erasing the n cells; and
if the vector x cannot be determined,
provide a FAIL indication; and
implement an error handling routine;
otherwise,
provide the vector x to the memory device interface for storing the vector x into the n cells of the non-volatile memory device without erasing the n cells.

US Pat. No. 10,191,802

EXTRACT-TRANSFORM-LOAD DIAGNOSTICS

Oracle International Corp...

1. A method for diagnosing extract-transform-load (ETL) errors in a cloud-based data integration system, comprising:initiating, by a computer system, a first process of an extract-transform-load process within the cloud-based data integration system, the first process comprising extracting data from a cloud-based application;
receiving, by the computer system, a first data set associated with the first process;
initiating, by the computer system, a second process of the extract-transform-load process within the cloud-based data integration system, the second process comprising caching the extracted data into a first schema, and the first schema being associated with the cloud-based application;
receiving, by the computer system, a second data set associated with the second process;
initiating, by the computer system, a third process of the extract-transform-load process within the cloud-based data integration system, the third process comprising loading the extracted data from a first schema to a second schema, the second schema being associated with a cloud-based data warehouse, and the first process, the second process, and the third process being distinct processes performed at different times during the extract-transform-load process;
receiving, by the computer system, a third data set associated with the third process;
determining, by the computer system, a first error and a second error in the extract-transform-load process based at least in part on the first data set, the second data set, or the third data set;
determining, by the computer system, a first characteristic associated with the first error, the first characteristic indicating at least that the first error is correctable;
determining, by the computer system, a second characteristic associated with the second error, the second characteristic indicating at least that the second error is fault tolerant;
rejecting, by the computer system, based at least in part on the first characteristic, at least a portion of data associated with the first error; and
transforming, by the computer system, based at least in part on the second characteristic, at least a portion of data associated with the second error.

US Pat. No. 10,191,801

ERROR CORRECTION CODE MANAGEMENT OF WRITE-ONCE MEMORY CODES

TEXAS INSTRUMENTS INCORPO...

1. An electronic device comprising:a write-once memory (WOM) device; and
a memory controller that includes:
a host interface to receive a data word including a first symbol and a second symbol, each of the first and second symbols having at least two bits;
a WOM controller to encode the first symbol and the second symbol and outputs a WOM-encoded word that includes a first WOM code corresponding to the first symbol and a second WOM code corresponding to the second symbol, wherein each of the first and second WOM codes include at least three bits with at least two of the at least three bits having the same logic value;
an error correction code (ECC) controller to encode the WOM-encoded word and output an ECC-encoded word that includes the first and second WOM codes and a first set of ECC bits corresponding to a first write operation; and
a memory device interface to write the ECC-encoded word to a first address of the WOM device as part of the first write operation.

US Pat. No. 10,191,800

METRIC PAYLOAD INGESTION AND REPLAY

Cisco Technology, Inc., ...

1. A method for metric payloads ingestion and playback, the method including:receiving, by a collector executing on a server, time series of metric payloads for a plurality of performance metrics indicating performance of a node or machine, wherein the collector is communicatively connected to a coordinator that provides collectors with information on a plurality of aggregators including assignments of the performance metrics to each aggregator;
storing, by a database executing on the server, the received time series of metric payloads in a payload tracking table of a database, wherein the storing includes:
storing the received time series of metric payloads in different layers and partitioned regions of the payload tracking table, wherein the layers represent time ranges corresponding to time points when the time series of metric payloads are received, and wherein the partitioned regions are assigned to received certain ones of the received time series of metric payloads; and
replaying the stored time series of metric payloads from a select one or more of the partitioned region or layer or both.

US Pat. No. 10,191,799

BER MODEL EVALUATION

SanDisk Technologies LLC,...

1. A storage system comprising:a memory; and
a controller configured to:
read a data set from a target storage location of the memory;
measure a first parameter and a second parameter of the data set to obtain a first actual value of the first parameter and a second actual value of the second parameter;
apply the first actual value or the second actual value to a model; and
based on the application, identify a deviation level of the target storage location relative to the model.

US Pat. No. 10,191,798

EXTENDED INTERFRAME SPACE (EIFS) EXEMPTIONS

QUALCOMM Incorporated, S...

1. An apparatus for wireless communications, comprising:a first interface configured to obtain a frame received over a medium;
a processing system configured to:
detect an occurrence of an error when processing the frame;
determine an intended recipient of the frame based on information included in the frame; and
after detecting the occurrence of the error, select a deferral period based, at least in part, on the determination, wherein the selection comprises selecting a first deferral period if the determination is that the apparatus is not the intended recipient of the frame, wherein the first deferral period is greater than a second deferral period; and
a second interface configured to refrain from outputting a frame for transmission on the medium during the selected deferral period.

US Pat. No. 10,191,797

ELECTRONIC SYSTEM GENERATING MULTI-PHASE CLOCKS AND TRAINING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. An electronic system comprising:a memory controller configured to generate a plurality of controller clocks having different phases from one another based on a reference clock signal, and to transmit a first clock and a second clock having phase difference from each other between the plurality of controller clocks, the phase difference between the first clock and the second clock is 90 or 270 degrees; and
a memory configured to generate a plurality of internal clocks having different phases from one another by receiving the first clock and the second clock, and selectively output a plurality of odd-ordered data or a plurality of even-ordered data among a plurality of data in synchronization with the plurality of internal clocks,
wherein the memory comprises:
a clock receiver configured to generate a first differential clock and a second differential clock in response to the first and second clocks;
a duty cycle correction portion configured to correct duty ratios of the first differential clock and the second differential clock;
a clock division portion configured to output the first and second groups of clocks by dividing an output of the duty cycle correction portion; and
a data input/output portion configured to transmit the plurality of the odd-ordered data or the plurality of the even-ordered data to the memory controller in response to the first group of clocks and an even-odd flag signal.

US Pat. No. 10,191,796

SYSTEM AND METHOD FOR STATISTICAL APPLICATION-AGNOSTIC FAULT DETECTION IN ENVIRONMENTS WITH DATA TREND

Open Invention Network, L...

1. A system, comprising:one or more memory locations configured to store one or more applications and one or more statistical models, wherein each of said one or more application is comprised of one or more processes and threads;
one or more Central Processing Units operatively connected to said one or more memory locations, configured to execute said one or more applications on a host with a host operating system, and configured to generate one or more statistical events for said one or more executing applications and said host operating system; and
a fault detector configured to create one or more statistical models for the execution of said one or more applications, each comprising: one or more of calculating one or more distributions for said one or more statistical events, de-trending the data for said one or more statistical events, transforming the data for said statistical events, and detecting faults in the execution of said one or more applications by detecting significant deviation of recent statistical events from said one or more distributions.

US Pat. No. 10,191,795

METHOD AND SYSTEM FOR TIMEOUT MONITORING

Infineon Technologies AG,...

1. A method for timeout monitoring of commands comprising:assigning, by a first microcontroller, each one of the commands to a corresponding one of a plurality of timeout timers in a FIFO manner when corresponding commands are to be transmitted by the first microcontroller over a high speed serial link (HSSL) to a second microcontroller within a same system;
for a first type of command, transmitting over the HSSL, by the first microcontroller, a subsequent command only after receiving a command acknowledge or a timeout to a previously transmitted command; and
for a second type of command, transmitting over the HSSL, by the first microcontroller, a subsequent command before a command acknowledge or a timeout to a previously transmitted command has been received.

US Pat. No. 10,191,792

APPLICATION ABNORMALITY DETECTION

International Business Ma...

1. A method of operating a computer system comprising:collecting, from the computer system, data indicative of variations in throughput and response time over a period of time;
calculating processing power of the computer system over the period of time;
recording a maximal power;
calculating a standard deviation of the response time (RT-StdDev);
recording the standard deviation of the response time corresponding to a time of the maximal power (RT-StdDevMaxPower); and
generating a notification that the computer system is in a bottleneck state using a comparison of a current processing power to the maximal power and a comparison of the RT-StdDev to the RT-StdDevMaxPower.

US Pat. No. 10,191,791

ENHANCED ADDRESS SPACE LAYOUT RANDOMIZATION

Intel Corporation, Santa...

1. An enhanced address space layout randomization apparatus comprising:a linear address space comprising a metadata data structure;
metadata logic to generate a metadata value; and
enhanced address space layout randomization (ASLR) logic to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address,
the address pointer corresponding to an apparent address in an enhanced address space, a size of the enhanced address space greater than a size of the linear address space.

US Pat. No. 10,191,790

DATA STORAGE DEVICE AND ERROR RECOVERY METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A data storage device comprising:a nonvolatile memory device including a memory block having a plurality of memory regions; and
a controller suitable for searching a first memory region for which error correction is passed, by scanning the plurality of memory regions in a reverse order of a write sequence for the memory block, determining a target memory region in the memory block based on data stored in the first memory region, and performing a recovery operation for the target memory region,
wherein, when it is determined that transaction-begin data is stored in the first memory region, the controller determines a memory region which is indicated by the transaction-begin data, as the target memory region.

US Pat. No. 10,191,789

TRACING SYSTEM OPERATIONS ACROSS REMOTE PROCEDURE LINKAGES TO IDENTIFY REQUEST ORIGINATORS

CrowdStrike, Inc., Irvin...

1. A computing device comprising:one or more processors; and
a security agent configured to be operated by the one or more processors to perform operations including:
receiving one or more event notifications respectively associated with one or more kernel-mode events;
determining, based on the one or more event notifications, that the one or more kernel-mode events are associated with user-mode processing by a remote-procedure-call-utilizing (RPC-utilizing) process of a request message;
retrieving the request message based on information included in one or more remote procedure call (RPC) data structures and based on the one or more event notifications, wherein the retrieving includes:
determining a thread environment block (TEB) of a worker thread that is associated with the user-mode processing by the RPC-utilizing process of the request message, and
tracing from the TEB to the request message through an RPC-specific field of an operating system (OS) data structure; and
identifying an originator of the request message based on metadata of the request message.

US Pat. No. 10,191,788

PROGRAMMABLE DEVICE, HEIRARCHICAL PARALLEL MACHINES, AND METHODS FOR PROVIDING STATE INFORMATION

Micron Technology, Inc., ...

1. A method of providing state information from a parallel machine to another device, wherein the parallel machine includes a plurality of programmable elements, wherein each of the programmable elements is configured to have a corresponding state, comprising:determining state information, wherein the state information comprises the state of each of the programmable elements in the parallel machine;
compressing the state information, wherein compressing the state information comprises aggregating final states in a finite state machine implemented on the parallel machine; and
providing the compressed state information to the other device.

US Pat. No. 10,191,786

APPLICATION PROGRAM INTERFACE MASHUP GENERATION

FUJITSU LIMITED, Kawasak...

1. A method of generating application program interface (API) mashups, the method comprising:grouping, via at least one processor, a plurality of APIs into a plurality of sub-clusters based on at least one keyword for each API of the plurality of APIs;
identifying, via the at least one processor, at least one keyword combination for the plurality of sub-clusters based on real-world data and two or more keywords for the plurality of sub-clusters;
determining, via the at least one processor, one or more possible API mashups including two or more APIs of the plurality of APIs for the at least one keyword combination;
determining, via the at least one processor, a similarity score for each possible API mashup of the one or more possible API mashups; and
identifying, via the at least one processor, at least one API mashup from the one or more possible API mashups based on the similarity score for each possible API mashups of the one or more possible API mashups.

US Pat. No. 10,191,784

ADAPTIVE QUEUED LOCKING FOR CONTROL OF SPECULATIVE EXECUTION

Intel Corporation, Santa...

1. An apparatus, comprising:a queue controller to control removal of threads from a queue, the queue to contain threads that are waiting to be permitted to speculatively execute in a critical section of a multi-threaded program;
a first thread associated with a head node of the queue, the queue controller to control the removal of threads from the queue in response to operations performed by the first thread, and when a number of threads executing in the critical section reaches a quota, the first thread to retry speculatively executing in the critical section and to remain associated with the head node of the queue to prevent a second thread corresponding to a second node of the queue from retrying speculatively executing in the critical section; and
an adjuster to change a number of threads permitted to speculatively execute based on a rate of threads currently speculatively executing transactions in the critical section, the adjuster is implemented via a logic circuit.

US Pat. No. 10,191,783

UDP MULTICAST OVER ENTERPRISE SERVICE BUS

Red Hat, Inc., Raleigh, ...

1. A method comprising:receiving application data from an event listener comprising a transport component and a web component by a processing device of an infrastructure service system, wherein the infrastructure service system comprises a first enterprise service bus (ESB) associated with an enterprise messaging system, wherein the application data comprises business rules to be shared between a first application in communication with the first ESB and a second application in communication with a second ESB associated with the enterprise messaging system;
forming, using the application data, a message by the processing device; and
transmitting, by the processing device, via the first ESB, the message via User Datagram Protocol (UDP) multicast over a public channel to a multicast address associated with a plurality of receivers associated with the second ESB, wherein the second ESB is subscribed to the multicast address.

US Pat. No. 10,191,782

SYSTEM TO SCHEDULE AND PERFORM AUTOMATED SOFTWARE TASKS DURING UNATTENDED SYSTEM TIME USING PREDICTED KNOWLEDGE OF INDIVIDUAL USER BEHAVIOR

Dell Products, LP, Round...

1. A method, comprising:determining, by an information handling system, a future predicted system time that an unattended task is to be executed on the information handling system, the future predicted system time based at least in part on first usage parameters for a user of the information handling system, the first usage parameters indicating first periods of usage activity and second periods of inactivity associated with the information handling system recorded during a first duration, and the first usage parameters indicating critical system parameters relevant to the present state of the information handling system;
ensuring, by the information handling system, that system resources of the information handling system are available for the unattended task to be able to complete;
in response to an arrival of the future predicted system time, executing, by the information handling system, the unattended task;
incrementing, by the information handling system, a count of wake events in response to the executing of the unattended task at the arrival of the future predicted system time;
comparing, by the information handling system, the count of the wake events to a threshold value, the threshold value based on the first periods of usage activity and the second periods of inactivity; and
recording, by the information handling system, the future predicted system time as a wake event of the wake events in response to the count of the wake events being less than the threshold value.

US Pat. No. 10,191,779

APPLICATION EXECUTION CONTROLLER AND APPLICATION EXECUTION METHOD

FUJITSU LIMITED, Kawasak...

1. An application execution controller, configured to instruct an execution of an application in a computing environment having available to allocate to executing applications: one or both of different amounts of computing resources in a plurality of computing resource categories and different types of computing resources in a plurality of computing resource categories; the controller comprising a memory and a processor coupled to the memory, the processor being configured:to collect available resource information detailing configurations of computing resources available to execute the application, wherein the configurations each include an indication of respective an amount and type of computing resources available in each category among the plurality of computing resource categories;
to collect application execution scalability information including, in respect of computing resources in at least one of the categories among the plurality of computing resource categories, an indication of how the one of or both of different amounts and types of computing resources in the respective computing resource category correlate with execution rate of a first portion of the application, the application execution scalability information being specific to an execution mode for the first portion of the application;
to collect performance target information including an indication of one or more performance targets for the execution of the application;
to perform a selection of a configuration from among the configurations detailed in the available resource information which, based on the application execution scalability information will come closest out of the configurations to meeting, the one or more performance targets; and
to instruct the computing environment to execute the first portion of the application using the selected configuration; wherein
for a change in an execution mode during the execution of the application caused by progressing from the first portion of the application to a forthcoming second portion:
the processor is configured to collect an updated version of the application execution scalability information, specific to the changed execution mode for the forthcoming second portion of the execution of the application, and to use the updated version to update a currently held version of the application execution scalability information; and
using the updated version of the application execution scalability information, the processor is configured to perform an updated selection of configuration from among the configurations detailed in the available resource information which, based on the updated application execution scalability information will come closest out of the configurations to meeting the one or more performance targets specified in the performance target information; wherein
the application execution scalability information is provided as a scalability matrix, the scalability matrix including an entry for each pair of factors from among factors comprising each category from among the plurality of computing resource categories and execution rate, the entry representing an effect of a proportional change along a linear scale representing usage of respective different amounts and types of a first factor from a pair of factors on the respective amount and type required of a second factor from the pair of factors, in terms of a proportional change along a linear scale representing the respective different amounts and types of the second factor, and
the processor is configured to instruct the computing environment to perform the execution of the forthcoming second portion of the application using the updated selection of configuration.

US Pat. No. 10,191,778

SYSTEMS, APPARATUS AND METHODS FOR MANAGEMENT OF SOFTWARE CONTAINERS

TURBONOMIC, INC., Boston...

1. A computer-implemented method, comprising:determining, by a pod manager running on a data processor in a container system, a computer resource bundle to be purchased for a pod in the container system using virtual currency units, wherein the pod is a cluster of two or more containers in the computer system sharing at least one resource;
identifying multiple resource providers in the container system offering the computer resource bundle;
determining a purchase price for the computer resource bundle, in virtual currency units, for each of the multiple resource providers;
automatically selecting, by the pod manager, a first one of the multiple resource providers based at least in part on the purchase price for the computer resource bundle for each of the multiple resource providers;
allocating the computer resource bundle from the selected first one of the multiple resource providers to the pod; and
determining, following an increase in the purchase price for the computer resource bundle offered by the selected first one of the multiple resource providers, that the pod is to be moved from the selected first one of the multiple resource providers to a second one of the multiple resource providers based at least in part on a lower purchase price for the computer resource bundle offered by the second one of the multiple resource providers.

US Pat. No. 10,191,776

INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, INFORMATION PROCESSING PROGRAM, AND STORAGE MEDIUM

FUJIFILM CORPORATION, To...

1. An information processing system comprising:a control device that transfers data that is a processing target and a control command describing processing content for the data;
a plurality of processing devices that are provided outside the control device and perform processing according to the control command on the data in a case where the control command is transferred from the control device; and
a planning device that determines a division size of the data such that a difference between a transfer time to transfer divided data obtained by dividing the data from the control device to each of the plurality of processing devices and a processing time to process the divided data in the processing device falls within a predetermined range, on the basis of an amount of the data, the transfer time, and the processing time,
wherein the control device sequentially transfers the divided data obtained by dividing the data according to the division size determined by the planning device to any one of the plurality of processing devices,
each of the plurality of processing devices performs processing according to the corresponding control command on the previously transferred divided data in parallel with the transfer of the divided data from the control device to the processing device in a case where the control command is transferred from the control device,
the transfer time and the processing time are determined in advance for each of the plurality of processing devices, and
the planning device determines the division size for each of the plurality of processing devices, calculates a processing completion time from start of transfer of the divided data from the control device to each of the plurality of processing devices to end of transfer of all pieces of data obtained by processing the divided data from each of the plurality of processing devices to the control device on the basis of the determined division size, and determines a processing device having a shortest processing completion time to be a transfer destination of the divided data of the control device.

US Pat. No. 10,191,773

METHODS, SYSTEMS, AND DEVICES FOR ADAPTIVE DATA RESOURCE ASSIGNMENT AND PLACEMENT IN DISTRIBUTED DATA STORAGE SYSTEMS

Open Invention Network LL...

1. A distributed data storage system for automatic constraint-based data resource arrangement, the data storage system comprising:a plurality of data storage components communicatively coupled to each other, each of said data storage components comprising at least one data resource selected from a data storage media for storing client-related digital information, a data processor for processing said client-related digital information, and a network communications interface for communicating said client-related digital information; and
a constraint engine comprising a constraint processor and a constraint database, said constraint database receiving and storing changeable digital constraint parameters indicative of permissible operational constraints on said data storage system, and said constraint processor automatically determining permissible data resource assignment arrangements in accordance with said changeable digital constraint parameters so to assign at least some of said data resources for use with said client-related digital information in compliance with said permissible operational constraints on said data storage system;
wherein, in response to an operational change to said data storage system, at least some said data resource are automatically reassigned from a current permissible data resource assignment arrangement to an alternate permissible data resource assignment arrangement and wherein a reassignment is selected when a number of reassignment steps is less than a designated reassignment threshold and thereby determined to comply with a designated set of said changeable digital constraint parameters.

US Pat. No. 10,191,771

SYSTEM AND METHOD FOR RESOURCE MANAGEMENT

HUAWEI TECHNOLOGIES CO., ...

1. A method of managing resources of a computing system, the method comprising:monitoring, at a distributed resource management system, a total utilization of a non-elastic resource of the resources of the computing system being used by a plurality of workloads during runtime of the plurality of workloads, wherein monitoring includes obtaining a current utilization of the non-elastic resource by each workload and a resource allocation limit for the non-elastic resource for each workload, each workload associated with one of a plurality of tenants;
determining, at a distributed resource management system, whether a utilization condition is met based on the total utilization of the non-elastic resource;
after determining that both the utilization condition is met, and the current utilization of the non-elastic resource by at least two workloads of the plurality of workloads exceeds its respective resource allocation limit for the non-elastic resource, selecting, at the distributed resource management system, at least one of the at least two workloads on which to perform an enforcement action based on at least one selection criteria; and
performing, at the distributed resource management system, the enforcement action on each selected workload, the enforcement action comprising one of terminating, suspending, or checkpointing each selected workload;
wherein selecting the at least one of the at least two workloads based on the at one selection criteria comprises:
selecting a workload of the least two workloads having a greatest resource overuse ratio or exceeds its resource allocation limit by a greatest amount:
or
selecting a workload of the least two workloads having a lowest priority level when each of the at least two workloads has a priority level;
or
selecting a workload of the least two workloads associated with a tenant having a greater total utilization of the resources of the computing system when each of the at least two workloads is associated with a different one of the plurality of tenants.

US Pat. No. 10,191,770

MAINTENANCE TASKS BASED ON DEVICE ROLE

Microsoft Technology Lice...

1. A computer system comprising:one or more processors; and
one or more computer-readable media having stored thereon instructions that are executable by the one or more processors to configure the computer system to update a computing device, including instructions that are executable to configure the computer system to perform at least the following:
identify a defined computing system role for the computing device, wherein the defined computing system role defines a specific predefined purpose of the computing device;
based on the defined computing system role for the computing device, identify a schedule correlated to the defined computing system role, wherein the schedule comprises predetermined time periods, the predetermined time periods defining at least one of when computing devices having the defined computing system role should he active, when computing devices having the defined computing system role should be idle, or when computing devices having the defined computing system role should have maintenance tasks performed;
based on the predetermined time periods in the schedule, identify one or more times for performing maintenance tasks for the defined computing system role, and thus for the computing device such that the times for performing maintenance on the computing device are directly correlated to and based on the defined computing role for the computing device; and
perform one or more maintenance tasks on the computing device, at the one or more times identified for maintenance for the defined computing system role according to the identified schedule; and
wherein the performing one or more maintenance tasks on the computing device comprises performing updates, including at least one of application updates, operating system updates, application store updates, or security updates.

US Pat. No. 10,191,769

EFFICIENT EVENT FILTER

British Telecommunication...

1. A sequence identification apparatus comprising a processor, wherein the apparatus is adapted to access a directed acyclic graph data structure of equivalence classes of events in event sequences identified in a plurality of time-ordered events, and wherein the graph is optimized such that initial and final sub-sequences of event sequences having common equivalence classes are combined in the graph, the apparatus comprising:a code generator adapted to generate executable code corresponding to the graph such that the code includes an instruction sequence for each event classification of the graph, the instruction sequence for an event classification being adapted to evaluate criteria to determine if an event corresponds to the event classification;
an executor adapted to execute the generated executable code such that, in use, the executable code filters incoming time-ordered events based on the graph; and
a sequence identifier adapted to identify the event sequence and further event sequences based on at least one sequence extending relation defining at least one relation between events, and wherein, in use, the executable code filters incoming time-ordered events satisfying the at least one sequence extending relation,
wherein the filtered incoming time-ordered events indicate an occurrence of interest by the identification of one of: a partial sequence of events in the incoming time-ordered events based on the graph, and a full sequence of events in the incoming time-ordered events based on the graph,
and wherein the incoming time-ordered events are events arising from an arrangement of computing components, and the occurrence of interest is a security occurrence, the apparatus further including a notifier for generating a notification of the security occurrence.

US Pat. No. 10,191,767

SEAMLES SDN-SUPPORTED RAN-APP MIGRATION

NEC CORPORATION, Tokyo (...

1. A method for performing centralized radio access network (CRAN) process migration in a CRAN, wherein the CRAN comprises a number of remote radio access points and a centralized processing center including a number of physical compute hosts that perform at least part of a radio access network (RAN) functionality, wherein the method comprising:executing a CRAN process on a first of the physical compute hosts and starting a new instance of the CRAN process on a second of the physical compute hosts,
duplicating traffic destined to the CRAN process to both instances of the CRAN process,
during a first time interval, processing the traffic on the first and the second physical compute host in parallel and suppressing the output of the second physical compute host, and
when the second physical compute host reaches a same state with respect to the CRAN process as the first physical compute host, forwarding duplicate outputs from both instances to higher layers.

US Pat. No. 10,191,766

AUTHORING AND RUNNING TASK-BASED FLOWS WITHIN A COMPUTING SYSTEM

Microsoft Technology Lice...

1. A computing system, comprising:a processor; and
memory storing instructions executable by the processor, wherein the instructions, when executed, configure the computing system to provide:
an application component configured to:
run a parent application; and
navigate a user through a plurality of parent application pages, each parent application page having user interface (UI) controls;
launch point detector logic configured to detect a launch point indicator that is indicative of a launch point corresponding to a task associated with an application object in the parent application;
flow identifier logic configured to identify a sub-application to be launched based on the launch point indicator; and
a sub-application runtime system configured to:
launch the identified sub-application having a sub-application page configured to perform the task, the sub-application page having a set of UI controls comprising a subset of the UI controls on a parent application page;
receive an indication of user input through the sub-application page; and
provide data associated with the user input to the application object in the parent application.

US Pat. No. 10,191,765

TRANSACTION COMMIT OPERATIONS WITH THREAD DECOUPLING AND GROUPING OF I/O REQUESTS

SAP SE, Walldorf (DE)

1. One or more tangible computer-readable media storing computer-executable instructions for causing a server programmed thereby to perform a method at a master node of a database system, the method comprising:for each of multiple database transactions, receiving from one or more database clients one or more operations to manipulate data stored in the database system;
receiving one or more requests to commit the multiple database transactions to disk; and
performing operations to commit the multiple transactions to disk, including:
with a first thread at the master node:
writing a first prepare log to disk at the master node for a first transaction of the multiple transactions;
defining a first job to direct a slave node of the database system to write a first prepare commit log to disk, the first prepare commit log being for at least a portion of the one or more operations of the first transaction;
enqueuing the first job in a queue maintained by the master node, the queue comprising a data structure, physically stored in memory, configured to store a plurality of jobs, the enqueuing comprising storing the job in the data structure; and
after enqueuing the first job, releasing the first thread;
with a second thread at the master node, which may be the first thread after having been released after enqueuing the first job:
writing a second prepare log to disk at the master node for a second transaction of the multiple transaction;
defining a second job to direct the slave node to write a second prepare commit log to disk, the second prepare commit log being for at least a portion of the one or more operations of the second transaction;
enqueuing the second job in the queue; and
after enqueuing the second job, releasing the second thread;
with a third thread at the master node:
dequeuing the first and second jobs from the queue, the dequeuing comprising removing the first and second jobs from the data structure;
grouping the first and second jobs in a single request to be sent to the slave node; and
sending the request to perform the first and second jobs to the slave node, the slave node processing the first and second jobs after receiving the request, writing the first and second prepare commit logs, and sending an acknowledgement to the master node that the first and second prepare commit logs were written;
receiving the acknowledgement from the slave node;
committing the first and second transactions at the master node;
writing a commit log for the first transaction at the master node;
writing a commit log for the second transaction at the master node; and
sending commit acknowledgements to the one or more database clients for the first and second transactions.

US Pat. No. 10,191,764

AGENT-BASED END-TO-END TRANSACTION ANALYSIS

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method for agent-based transaction analysis comprising:building an instrumented binary code of a software application for a transaction;
configuring an analysis agent for the software application;
starting the software application in an application process environment with the instrumented binary code;
attaching the analysis agent to the instrumented binary code of the software application;
extracting by the analysis agent the metadata from the software application wherein the metadata includes data transmitted as a part of the transaction;
sending the metadata to a central analysis server in an environment separate from the application process environment; and
building by the central analysis server an end-to-end description of the transaction from the metadata.

US Pat. No. 10,191,763

ARCHITECTURE OF NETWORKS WITH MIDDLEBOXES

NICIRA, INC., Palo Alto,...

1. A system for implementing a logical network to communicatively connect a plurality of end machines, the logical network comprising (i) a set of logical forwarding elements collectively implemented by a set of managed forwarding elements and (ii) at least two logical middleboxes, the system comprising:a plurality of host computers on each of which (i) a managed forwarding element executes to implement the set of logical forwarding elements and (ii) a middlebox element executes to implement a first logical middlebox of the logical network, wherein the middlebox elements collectively implement the first logical middlebox and each store state information for the first logical middlebox but do not communicate the state information with the other middlebox elements; and
a set of separate physical middleboxes for implementing a second logical middlebox of the logical network, wherein the second logical middlebox performs an operation that requires state information relating to packets between several different sets of end machines connected by the logical network and the set of separate physical middleboxes share the state information for the second logical middlebox with each other;
wherein the middlebox elements and the set of separate physical middleboxes perform middlebox services on packets between the end machines of the logical network.

US Pat. No. 10,191,760

PROXY RESPONSE PROGRAM, PROXY RESPONSE DEVICE AND PROXY RESPONSE METHOD

Fujitsu Limited, Kawasak...

10. A method for a proxy response by a computer, the method comprising:requesting suspension or pausing of a virtual machine when an idle state of the virtual machine is detected;
changing, when the virtual machine is suspended or paused, settings information of a communication control device that controls communication between a terminal device and the virtual machine, so as to transfer access from the terminal device to the virtual machine that is to be suspended or paused, to the computer;
sending, when the access to the virtual machine that is suspended or paused is transferred, a response to the terminal device on the basis of communication response settings information relating to a communication response to the terminal device by the virtual machine that is suspended or paused; and
requesting resumption of the virtual machine that is suspended or paused in response to the transfer of the access.

US Pat. No. 10,191,759

APPARATUS AND METHOD FOR SCHEDULING GRAPHICS PROCESSING UNIT WORKLOADS FROM VIRTUAL MACHINES

Intel Corporation, Santa...

1. A system comprising:a graphics processing unit (GPU) comprising multiple GPU engines;
a microcontroller in the GPU; and
a storage medium having stored thereon instructions which, when executed, implement a virtual machine manager (VMM) to instantiate a virtualization driver interface (vdriver interface) that is adapted to
(a) communicate with the GPU via the microcontroller,
(b) enable multiple virtual machines (VMs) to communicate with the GPU,
(c) store, to memory that is accessible to the microcontroller, a first GPU state for a first VM among the multiple VMs, and
(d) store, to the memory that is accessible to the microcontroller, a second GPU state for a second VM among the multiple VMs;
wherein each VM, when instantiated, is associated with a unique Peripheral Component Interconnect (PCI) device function number and comprises a paravirtualized GPU driver (pdriver) to enable that VM to communicate with the GPU via the vdriver interface, at least in part by enabling that VM to send GPU state for that VM to the vdriver interface of the VMM, for subsequent utilization by the microcontroller in the GPU;
wherein the microcontroller is adapted to
(a) obtain the first GPU state for the first VM, after the vdriver interface of the VMM has received the first GPU state from the pdriver of the first VM and stored the first GPU state to the memory,
(b) obtain the second GPU state for the second VM, after the vdriver interface of the VMM has received the second GPU state from the pdriver of the second VM and stored the second GPU state to the memory,
(c) assign a first schedule slot for the first VM to access a first GPU engine among the multiple GPU engines,
(d) assign a second schedule slot for the second VM to access a second GPU engine among the multiple GPU engines, and
(e) in preparation for transitioning execution from the first VM to a third VM among the multiple VMs, saving the first GPU state for the first VM and restoring a third GPU state for the third VM;
wherein the GPU is adapted to grant exclusive access to the first GPU engine for the first VM when the first VM accesses the first GPU engine; and
wherein, when the first GPU engine executes a memory access instruction provided by the first VM, the first GPU engine is adapted to use the PCI device function number associated with the first VM to execute the memory access instruction.

US Pat. No. 10,191,755

VIRTUAL REPLICATION

EMC IP Holding Company LL...

1. A system for data replication, the system comprising:a hypervisor having a virtualization layer; wherein the virtualization layer runs in the hypervisor; wherein the virtualization layer consumes storage;
a splitter running in the virtualization layer;
a storage entity corresponding to a virtual disk; wherein the virtual disk is exposed by the virtualization layer to one or more virtual machines running in the hypervisor; wherein the virtual disk is mapped to a portion of the consumed storage; and
memory; one or more processors; computer-executable program logic, stored in one or more portions of the memory, wherein the computer-executable program logic, executed by the one or more processors to perform:
exposing, via the virtualization layer, the storage entity;
splitting IO in the splitter in the virtualization layer; wherein the splitting includes the splitter intercepting IO directed to the virtual disk and creating a copy of the IO sent to the virtual disk.

US Pat. No. 10,191,754

VIRTUAL MACHINE DEVICE HAVING KEY DRIVEN OBFUSCATION AND METHOD

KONINKLIJKE PHILIPS N.V.,...

1. A device comprising:a memory to store multiple operation routines, wherein each operation routine is configured to perform a particular instruction;
at least one processor configured to:
receive an encoded instruction, the encoded instruction being obtained by encoding a plain instruction with a code encoding;
look-up a corresponding operation routine of the multiple operation routines based on the encoded instruction using a look-up table in the memory, the corresponding operation routine being configured to perform the plain instruction corresponding to the encoded instruction; and
receive input data encoded with a first encoding;
perform the corresponding operation routine based on the input data encoded with the first encoding to produce an output; and
encode the output with a second internal encoding.

US Pat. No. 10,191,753

GENERATING VERIFICATION METADATA AND VERIFYING A RUNTIME TYPE BASED ON VERIFICATION METADATA

Oracle International Corp...

1. A non-transitory computer readable medium comprising instructions which, when executed by one or more hardware processors, causes performance of operations comprising:receiving a request to verify a first runtime type, loaded based on a first runtime type reference, wherein the first runtime type includes a statement associated with a second runtime type reference and a third runtime type reference;
responsive to receiving the request to verify the first runtime type:
identifying verification metadata associated with the first runtime type reference for verifying the first runtime type;
determining that the verification metadata comprises a stored assignable relationship between the second runtime type reference and the third runtime type reference;
determining whether an actual assignable relationship between a second runtime type, loaded based on the second runtime type reference, and a third runtime type, loaded based on the third runtime type reference, adheres to the stored assignable relationship between the second runtime type reference and the third runtime type reference; and
responsive at least to determining that the actual assignable relationship adheres to the stored assignable relationship, determining that the first runtime type is verified based on the verification metadata.

US Pat. No. 10,191,751

INFORMATION PROCESSING DEVICE FOR GENERATING APPLICATION PROGRAMMING INTERFACE INFORMATION

FUJITSU LIMITED, Kawasak...

1. An information processing device comprising:a memory; and
a processor coupled to the memory and the processor configured to:
execute an application software,
execute a specific process for coordinating a software module described in a first language with a software module described in a second language that is different from the first language, and
perform loading of a device driver for using a peripheral device, the device driver including a first software module described in the first language and a second software module described in the second language, the first software module being a software module in which a first plurality of interfaces are defined, the second software module being a software module in which a second plurality of interfaces are defined, in response to the loading, generate interface information for associating the first plurality of interfaces with the second plurality of interfaces respectively,
wherein for using the peripheral device,
the application software is configured to make a first access to a first interface selected from the first plurality of first interfaces,
the first software module is configured to make a second access to the specific process based on the first access,
the specific process is configured to make, on the basis of the second access and the generated interface information, a third access to a second interface selected from the second plurality of interfaces, the second interface being associated with the selected first interface, and
the second software module is configured to make a fourth access to the peripheral device based on the third access.

US Pat. No. 10,191,750

DISCOVERING NEW BACKUP CLIENTS

EMC IP Holding Company LL...

1. A system for discovering a new backup client, comprising:an input interface configured to receive a notice from a backup client over a network, wherein the notice indicates the backup client is being added to the network and includes information associated with the backup client, wherein the backup client is configured to provide the notice to the system upon determining a backup server address for one or more backups associated with the backup client; and
a processor configured to:
determine that the backup client is not already configured to perform backups based at least in part on the information associated with the backup client, wherein the information associated with the backup client includes a hardware and software configuration of the backup client;
in response to a determination that the backup client is not already configured to perform backups, provide an indication of the notice;
determine a set of available configuration modes based at least in part on the hardware and software configuration of the backup client; and
configure the backup client according to a selected configuration mode.

US Pat. No. 10,191,749

SCATTER REDUCTION INSTRUCTION

Intel Corporation, Santa...

5. A processor comprising:a register array comprising a first element that stores a first register value that identifies a first memory location, a second element that stores a second register value that identifies a second memory location, and a third element that stores a third register value that identifies a third memory location;
a decoder circuit to:
receive a single instruction multiple data (SIMD) instruction from an application, the SIMD instruction identifying the register array and an array of input values comprising at least a first input value, a second input value, and a third input value; and
decode the SIMD instruction; and
a processor core to:
perform an operation on the first input value and the first register value to obtain a first operation value, and wherein the first register value is stored at a first location of the register array;
perform the operation on the second input value and the second register value to obtain a second operation value, and wherein the second register value is stored at a second register array location of the register array; and
perform the operation the third input value and the third register value, and wherein the second register value is stored at a third location of the register array,
wherein the operation on the first, second, and third input values are performed in parallel;
associate the first operation value with the first location;
associate the second operation value with the second location;
associate a third operation value with the third location;
determine that the first register value and the second register value are the same value, wherein the third register value is different than the first register value and the second register value;
perform a horizontal add operation on the first operation value and the second operation value to obtain a result value;
write the result value to the second memory location, wherein the second memory location and the first memory location are the same when the first register value and the second register value are the same; and
write the third operation value to the third memory location.

US Pat. No. 10,191,748

INSTRUCTION AND LOGIC FOR IN-ORDER HANDLING IN AN OUT-OF-ORDER PROCESSOR

Intel IP Corporation, Sa...

1. A processor comprising:a core comprising an out-of-order pipeline including a decode logic, an issue logic to issue decoded instructions, and at least one execution logic to execute issued instructions of a program, wherein the at least one execution logic is to execute at least some instructions of the program out-of-order, the decode logic to decode a first in-order memory instruction of the program and provide the decoded first in-order memory instruction to the issue logic, the issue logic to order the first in-order memory instruction ahead of a second in-order memory instruction of the program, the first in-order memory instruction comprising a user-level instruction of an instruction set architecture to specify in-order execution of the first in-order memory instruction, wherein the issue logic is to issue the first in-order memory instruction to the at least one execution logic with a higher priority than the second in-order memory instruction by association of a priority indicator with the first in-order memory instruction.

US Pat. No. 10,191,747

LOCKING OPERAND VALUES FOR GROUPS OF INSTRUCTIONS EXECUTED ATOMICALLY

Microsoft Technology Lice...

1. A method comprising:fetching a first group of instructions, configured to execute by a processor, including a group header for the first group of instructions, wherein the group header includes a field including locking information for at least a first operand and a second operand for processing by the first group of instructions;
storing a value of the first operand in a first operand buffer of the processor and storing a value of the second operand in a second operand buffer of the processor;
detecting completion of execution of the first group of instructions by counting:
(1) register writes associated with the first group of instructions or (2) stores associated with the first group of instructions;
based on the locking information, locking a value of the first operand in the first operand buffer of the processor such that the first operand is not cleared from the first operand buffer of the processor in response to the completion of the execution of the first group of instructions even when a second group of instructions, for execution by the processor after the completion of the execution of the first group of instructions, is a new group of instructions comprising different instructions from the first group of instructions; and
based on the locking information, in response to the completion of the execution of the first group of instructions, clearing the value of the second operand from the second operand buffer of the processor.

US Pat. No. 10,191,746

ACCELERATED CODE OPTIMIZER FOR A MULTIENGINE MICROPROCESSOR

INTEL CORPORATION, Santa...

1. A method for accelerating code optimization in a microprocessor, comprising:fetching an incoming macro instruction sequence using an instruction fetch component;
transferring the incoming macro instruction sequence to a decoding component for decoding into a microinstruction sequence;
performing optimization processing by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups, wherein performing the optimization processing includes checking for true dependencies, output dependencies, and anti-dependencies in the microinstruction sequence to determine which microinstructions of the microinstruction sequence are grouped into a same dependent code group of the plurality of dependent code groups;
outputting the plurality of dependent code groups to a plurality of engines of the microprocessor for execution in parallel; and
storing a copy of the optimized microinstruction sequence into a sequence cache for subsequent use upon a subsequent hit on the optimized microinstruction sequence.

US Pat. No. 10,191,745

OPTIMIZED CALL-RETURN AND BINARY TRANSLATION

Intel Corporation, Santa...

1. A processor, comprising:a region formation engine to perform aggressive region formation of a region of code for translation from a guest instruction set architecture code to a translated instruction set architecture code,
wherein the aggressive region formation comprises forming the region of code across a boundary of a return (RET) instruction; and
a binary translator to:
translate the region of code; and
prevent a side entry into the translated region of code at a translated return target (RET_TGT?) included in the translated region of code, wherein the RET_TGT? is translated from a return target (RET_TGT) in the guest instruction set architecture code, and
wherein the side entry is prevented based on an indication mapped to an instruction pointer of the RET_TGT.

US Pat. No. 10,191,743

VERSATILE PACKED DATA COMPARISON PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

Intel Corporation, Santa...

1. A processor comprising:a decode unit to decode a versatile packed data compare instruction, the versatile packed data compare instruction to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, each data element of the second source packed data operand to correspond to a data element of the first source packed data operand in a same relative position, and to indicate a source comparison operation indication operand that is to include at least four comparison operation indicators each operable to versatilely indicate a potentially different comparison operation for a different corresponding pair of corresponding data elements from the first and second source packed data operands, wherein the source comparison operation indication operand comprises a packed data operand that is to include at least four data elements that are each to include a different corresponding one of the comparison operation indicators, and wherein each comparison operation indicator is to be specified in a least significant byte of the corresponding data element; and
an execution unit coupled with the decode unit, the execution unit, in response to the versatile packed data compare instruction, to store a result in a destination storage location to be indicated by the versatile packed data compare instruction, the result to include at least four result indicators that are each to correspond to a different one of the at least four comparison operation indicators, each result indicator to indicate a result of a comparison operation, which is to be indicated by the corresponding comparison operation indicator, which is to have been performed on the corresponding pair of data elements from the first and second source packed data operands.

US Pat. No. 10,191,742

MECHANISM FOR SAVING AND RETRIEVING MICRO-ARCHITECTURE CONTEXT

Intel Corporation, Santa...

1. An apparatus comprising:an execution unit within a processor to execute a code block having been compiled to have a reserved space appended to one end, the reserved space including a metadata block associated with the code block, and a switch code sign signifying an end of the code block and a beginning of the reserved space, wherein the code block and the reserved space appended to its end occupy a contiguous region of memory and boundaries of the code block are defined by conditional instructions;
power management hardware coupled to the execution unit, wherein the power management hardware is to:
monitor a first execution of the code block;
store a micro-architectural context of the processor in the associated metadata block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters;
read the associated metadata block upon a second execution of the code block; and
tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block; and
wherein the metadata block associated with the code block stores the performance data collected from executing the associated code block on two different processor cores that have different performances, and wherein the power management hardware is to determine which one of the two different processor cores is to execute the associated code block based on the performance data.

US Pat. No. 10,191,741

SYSTEM AND METHOD FOR MITIGATING THE IMPACT OF BRANCH MISPREDICTION WHEN EXITING SPIN LOOPS

Oracle International Corp...

1. A method, comprising:performing by a computer:
determining that a sequence of program instructions comprises a conditional branch type instruction that includes a hint or parameter that indicates that a particular branch path should be predicted;
performing dynamic branch prediction of the conditional branch instruction;
in response to said determining, predicting that the path taken following the conditional branch type instruction will be the particular branch path indicated by the hint or parameter included in the conditional branch type instruction, wherein the prediction of the particular branch path according to the hint or parameter overrides an outcome of the dynamic branch prediction;
if the particular branch path is correctly predicted, continuing on the predicted branch path; and
if the particular branch path is incorrectly predicted, incurring a misprediction stall.

US Pat. No. 10,191,740

DEINTERLEAVE STRIDED DATA ELEMENTS PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

Intel Corporation, Santa...

1. A processor comprising:a plurality of packed data registers;
a decode unit to decode an instruction, the instruction to indicate a source operand, to indicate a stride, to indicate at least one set of strided data element positions out of all sets of strided data element positions for the indicated stride, and to indicate at least one destination packed data register of the plurality of packed data registers; and
an execution unit coupled with the plurality of packed data registers, and coupled with the decode unit, the execution unit, in response to the instruction, for each of the indicated at least one set of strided data element positions, to store a corresponding result packed data operand, in a corresponding destination packed data register of the plurality of packed data registers, each result packed data operand to include a plurality of data elements, which are to be from the corresponding indicated set of strided data element positions of the source operand, in which strided data element positions of the set are to be separated from one another by integer multiples of the indicated stride.

US Pat. No. 10,191,739

STATE ESTIMATION PROCESSOR AND STATE ESTIMATION SYSTEM

MEGACHIPS CORPORATION, O...

1. A state estimation processor connected to an external detection device and an external computer, comprising:interface circuitry configured to obtain detection information obtained by the external detection device and output state information to the external computer;
calculating circuitry including a SIMD type arithmetic processing circuitry processes a plurality of information by one command and provided with at least four single precision floating point computing circuits, the one command being executed in parallel to a plurality of data set to each of the at least four single precision floating point computing circuits in a single cycle;
the calculating circuitry configured to:
estimate a state of an object based on the detection information obtained by the interface circuitry;
generate the state information according to the state of the object;
compare first detection information received at a first point in time with second detection information received at a second point in time, which is subsequent to the first point in time;
control the interface circuitry to output a notification to the external computer when it is determined that a difference between the first detection information and the second detection information is less than a predetermined threshold value; and
switch an operational mode from a first operation mode, during which the state information is generated, to a second operation mode in which power consumption is smaller than the first operation mode after controlling the interface circuitry to output the notification to the external computer.

US Pat. No. 10,191,737

PROGRAM CODE COMPARISON AND REPORTING

Accenture Global Solution...

1. A device, comprising:one or more memories; and
one or more processors, communicatively coupled to the one or more memories, configured to:
obtain a first code set and a second code set,
the first code set having at least one difference from the second code set,
the at least one difference relating to addition, removal, or modification of code of the first code set in comparison to code of the second code set, and
the first code set and the second code set relating to one or more of:
extracting input data from a source file,
transforming the input data to form output data, or
storing the output data in a target file;
identify one or more code portions of the first code set and one or more code portions of the second code set,
the one or more code portions of the first code set and the one or more code portions of the second code set including one or more lines of code that are associated with a particular format including at least one of:
a source definition,
a target definition,
a workflow, or
a transformation,
each code portion of the first code set to be compared to a corresponding code portion of the second code set,
the one or more code portions of the first code set including a first code portion and a second code portion and the one or more code portions of the second code set include a third code portion and a fourth code portion,
the first code portion of the first code set corresponding to a format of the third code portion of the second code set,
the second code portion of the first code set corresponding to a format of the fourth code portion of the second code set;
concurrently compare:
the first code portion of the first code set to the third code portion of the of the second code set to identify at least a first difference, and
the second code portion of the first code set to the fourth code portion of the second code set to identify at least a second difference,
where the one or more processors, when concurrently comparing the first code portion of the first code set to the third code portion of the second code set and the second code portion of the first code set to the fourth code portion of the second code set, are to:
perform parallel processing with regard to comparing the first code portion to the third code portion and the second code portion to the fourth code portion;
generate comparison information identifying the at least first difference and the at least second difference; and
store or provide the comparison information.

US Pat. No. 10,191,735

LANGUAGE-INDEPENDENT PROGRAM COMPOSITION USING CONTAINERS

1. An apparatus comprising:a memory;
at least one hardware processor, coupled to said memory, and,
a non-transitory computer readable medium comprising computer executable instructions which when loaded into said memory configure said at least one hardware processor to:
obtain:
an action sequence comprising a plurality of actions; and
a corresponding input dictionary;
instantiate a first container running a first image for a first one of said actions implemented in a first programming language;
execute said first image for said first one of said actions on said input dictionary to obtain a first action result;
update said input dictionary with said first action result to obtain an updated input dictionary;
instantiate a second container running a second image for a second one of said actions implemented in a second programming language different than said first programming language;
execute said second image for said second one of said actions on said updated input dictionary to obtain a second action result; and
update said updated input dictionary with said second action result to obtain a further updated input dictionary;
wherein said input dictionary, said updated input dictionary, and said further updated input dictionary are independent of said first and second programming languages.

US Pat. No. 10,191,734

METHOD AND SYSTEM FOR SOFTWARE APPLICATION OPTIMIZATION USING NATURAL LANGUAGE-BASED QUERIES

Open Text Corporation, W...

1. A method for software application optimization using natural language-based queries, comprising:obtaining, by an application development engine executing on a computing device, a user-provided query input via a user interface,
wherein the user-provided query comprises at least one software application optimization constraint and an optimization action, the at least one software application optimization constraint including information for an identification of an application element that matches the at least one software application optimization constraint, as a candidate for the optimization action, from a plurality of application elements of a software application, and
wherein the user-provided query is a string comprising a human language sentence;
deriving, by the application development engine, a formalized query from the user-provided query by translating the user-provided query into a syntactic construct of segmented sentence elements;
obtaining, by the application development engine, the application element that matches the at least one software application optimization constraint from an application repository, comprising:
deriving a pattern representation of the user-provided query from the formalized query; and
identifying the application element that matches the pattern representation of the user-provided query from the plurality of application elements, including identifying the application element as the candidate for the optimization action; and
optimizing the software application, by the application development engine, by performing the optimization action, including performing a software application revision on the identified application element that matches the pattern representation of the user-provided query.

US Pat. No. 10,191,733

SOFTWARE CHANGE PROCESS ORCHESTRATION IN A RUNTIME ENVIRONMENT

SAP SE, Walldorf (DE)

1. A method comprising:defining, by a computer system, a set of software change processes across different platforms and environments;
mapping, by the computer system, each software change process to at least one tool for performing each software change process to generate a software change process map comprising a list of software change processes and at least one corresponding tool for performing each software change process;
receiving, at the computer system, an indication to initiate a software change process orchestration;
identifying, by the computer system, a first software change process and a second software change process to be performed for the software change process orchestration in response to receiving the indication;
accessing, by the computer system, the software change process map comprising the list of change processes mapped to at least one corresponding tool for performing each change process to identify at least one first corresponding tool for the first software change process and at least one second corresponding tool for the second software change process;
creating, by the computer system, a composed process by combining the first software change process to be performed for the software change process orchestration and the at least one first corresponding tool for performing the first software change process, and the second software change process and the at least one second corresponding tool for performing the second software change process;
triggering, by the computer system, execution of the at least one first corresponding tool for performing the first software change process and the at least one second corresponding tool performing the second software change process of the composed process, using a uniform software logistic protocol that manages calls to tools across different platforms and environments, the software logistic protocol comprising a uniform process interface that starts and monitors a software change process;
monitoring, by the computer system, status of an execution of the at least one first corresponding tool and the at least one second corresponding tool during the first software change process and the second software change process of the composed process; and
presenting, by the computer system, the status of the execution of the at least one first corresponding tool and the at least one second corresponding tool during the software first change process and the second software change process of the composed process on a uniform user interface that is process independent.

US Pat. No. 10,191,732

SYSTEMS AND METHODS FOR PREVENTING SERVICE DISRUPTION DURING SOFTWARE UPDATES

Citrix Systems, Inc., Fo...

1. A method for preventing service disruptions in a computing system, comprising:receiving, at a cloud-based computing system, a plurality of messages for initiating software updates requiring system reboots by a plurality of remote computing machines, where each said message is sent by a respective one of the remote computing machines to itself through a hosted maintenance service; and
performing operations by the cloud-based computing system to schedule maintenance operations across the plurality of remote computing machines for a performance of the system reboots in a one-machine-at-a-time manner, where the operations comprise
sequencing the plurality of messages across the remote computing machines so as to ensure that an operational state of only one remote computing machine of the plurality of remote computing machines is transitioned from an online state to an offline state at any given time; and
making the plurality of messages available to the remote computing machines in accordance with the sequencing.

US Pat. No. 10,191,731

SAFE AND AGILE ROLLOUTS IN A NETWORK-ACCESSIBLE SERVER INFRASTRUCTURE USING SLICES

Microsoft Technology Lice...

1. A method of rolling out updates to a network-accessible server infrastructure which operates a plurality of instances of a supporting service, the supporting service comprised by a plurality of service portions, the instances of the supporting service each including the plurality of service portions, the method comprising:receiving an indication of a partition of the instances of the supporting service into a plurality of slices, each instance of the supporting service partitioned to include one or more slices of the plurality of slices, each slice of an instance of the supporting service including one or more of the service portions of the instance of the supporting service; and
deploying a software update to the plurality of instances of the supporting service by
applying the software update to the plurality of slices in a sequence such that the software update is applied to a same slice in parallel across the instances of the supporting service containing that same slice before being applied to a next slice and
waiting a wait time after each applying of the software update to a slice of the plurality of slices before applying the software domain to a next slice of the plurality of slices in the sequence.

US Pat. No. 10,191,730

APPLICATION UPGRADE METHOD AND APPARATUS

HUAWEI TECHNOLOGIES CO., ...

1. A system for upgrading a deployed application, comprising:a user equipment configured to send an application deployment request to the application deployment server, wherein the application deployment request comprises:
a node template of a to-be-deployed application;
a deployed application identifier of the deployed application to be upgraded by the to-be-deployed application;
a node template identifier of a node template of the deployed application;
a first platform node template identifier of a first platform node template; and
a version requirement of the first platform node template required by the node template of the to-be-deployed application; and
an application deployment server configured to:
receive the application deployment request from the user equipment;
acquire, according to the deployed application identifier, a first platform node identifier of a first platform node corresponding to the first platform node template identifier and acquire a version of the first platform node indicated by the first platform node identifier; wherein the to-be-deployed application runs based on a capability provided by the first platform node, and wherein the first platform node is deployed according to the first platform node template prior to the to-be-deployed application;
determine that the version of the first platform node is below the version requirement of the first platform node template;
acquire a first platform node upgrade package that meets the version requirement, wherein the first platform node upgrade package is acquired according to the version requirement of the first platform node template required by the node template of the to-be-deployed application;
upgrade the first platform node indicated by the first platform node identifier using the first platform node upgrade package;
determine an identifier of a to-be-upgraded application node; and
upgrade the application node after the first platform node is upgraded, wherein the application node is indicated by the identifier of the to-be-upgraded application node.

US Pat. No. 10,191,729

SYSTEM AND METHODOLOGY FOR UPDATING INDIVIDUALIZED SYSTEM DATA TO FACILITATE REPAIR AND/OR REPLACEMENT SERVICE PROVISION

Lenovo Enterprise Solutio...

1. A system, comprising:a storage device hosting a file system and implementing an operating system, the file system storing first individualized system data identifying a computer hardware component;
a replacement computer hardware component comprising an embedded storage module storing second individualized system data identifying the replacement computer hardware component;
wherein the embedded storage module is configured to implement a routine stored thereon using a processor or a controller of the system;
wherein the routine is configured to overwrite the first individualized system data with the second individualized system data in response to determining a mismatch between the first individualized system data and the second individualized system data;
wherein the storage device is physically separate from the computer hardware component and the replacement computer hardware component;
wherein the embedded storage module is configured to automatically implement the routine during a boot process of the system using a target disk mode function of the boot process;
wherein the embedded storage module is further configured to automatically implement the routine as part of a startup process of the operating system;
wherein the first individualized system data and the second individualized system data each comprise vital product data (VPD) corresponding to the computer hardware component; and
wherein the VPD comprises:
a manufacturer name corresponding to the replacement computer hardware component;
a location corresponding to the replacement computer hardware component, wherein the location includes a city name, a state, and a country name;
a serial number corresponding to the replacement computer hardware component, wherein the serial number is an uninterrupted string of alphanumeric characters excluding special characters and spaces;
a component type corresponding to the replacement computer hardware component, wherein the component type comprises a model name;
a universally unique identifier (UUID) corresponding to the replacement computer hardware component, wherein the UUID is a 128-bit value selected from the group consisting of: a MAC address: a DCE security value, a MD5 hash, and a SHA-1 hash; and
asset tag information corresponding to the replacement computer hardware component, wherein the asset tag information is a string encoded as a barcode on a physical tag applied to the replacement computer hardware component.

US Pat. No. 10,191,728

SYSTEM AND METHOD TO REDUCE STORAGE AREA USAGE OF ANDROID APPLICATION

Samsung Electronics Co., ...

1. A mobile device based on an Android™ operating system comprising:a storage device configured to store data;
transceiver circuitry configured to access a server via a wireless communication network and download, from the server, an Android™ application package; and
a package manager configured to:
analyze resources in the downloaded Android™ application package;
identify unnecessary ones of the resources, the unnecessary resources comprising resources that are not suitable for use by the mobile device;
delete the unnecessary resources;
generate, from only resources remaining after deletion of the unnecessary resources, without adding new resources, an optimized Android™ application package having a smaller size than the downloaded Android™ application package;
store the optimized Android™ application package in the storage device in place of the downloaded Android™ application package; and
determine, based on a new signing key, that the optimized Android™ application package has a smaller size than the downloaded Android™ application package.

US Pat. No. 10,191,724

COMPILER-BASED INSTRUCTION SCOREBOARDING

INTEL CORPORATION, Santa...

1. An apparatus comprising:a processor to:
remove one or more unnecessary dependence edges from a data dependency graph which represents one or dependencies between instructions for execution on a processing device;
partition the data dependency graph into a plurality of sub-graphs based on dependence characteristics of the instructions for execution;
determine a live range for each of the plurality of sub-graphs; and
assign a scoreboard entry to each of the plurality of sub-graphs, wherein sub-graphs which have interfering live ranges are assigned different scoreboard indices which identify an execution order for operations in the plurality of sub-graphs.

US Pat. No. 10,191,696

IMAGE FORMING SYSTEM INCLUDING A FIRST IMAGE FORMING APPARATUS AND A SECOND IMAGE FORMING APPARATUS CONNECTED ON A DOWNSTREAM SIDE OF THE FIRST IMAGE FORMING APPARATUS

KONICA MINOLTA, INC., Ch...

1. An image forming system comprising: a first image forming apparatus; and a second image forming apparatus connected on a downstream side of the first image forming apparatus in a paper conveying direction,wherein the first image forming apparatus includes:
a first expander that expands a first image having image expansion time per page including a first time; and
a first image former that forms the first image expanded by the first expander, onto a first face of paper, and
the second image forming apparatus includes:
a second expander that expands a second image having image expansion time per page including a second time longer than the first time; and
a second image former that forms the second image expanded by the second expander, onto the first face on which the first image has been formed.

US Pat. No. 10,191,695

IMAGE FORMING APPARATUS CAPABLE OF MAKING BOOKLET, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM STORING CONTROL PROGRAM THEREFOR

CANON KABUSHIKI KAISHA, ...

5. A control method for an image forming apparatus comprising a reader configured to read an original having a plurality of pages, a storage device configured to store data, a display device configured to display information, and an image forming device configured to form images on a sheet, the control method comprising the steps of:obtaining an opening direction of the original read by the reader, based on a user instruction, the original being for a booklet to which a saddle stitch bookbinding is applied;
storing, in the storage device, print data of a plurality of images generated based on the plurality of pages of the original read by the reader and the opening direction of the original, the plurality of images being printable by the image forming device;
receiving a selection of images to be printed, from among the plurality of images, based on a user instruction;
displaying a plurality of opening directions on the display device as a setting screen about bookbinding print of the selected images, with the stored opening direction initially selected among the displayed plurality of opening directions;
receiving a selection of an opening direction based on a user instruction from among the displayed plurality of opening directions;
determining a print layout based on the received selection of the opening direction; and
causing, in a case where the saddle stitch bookbinding is applied, the image forming device to form the selected images according to the determined print layout.

US Pat. No. 10,191,682

PROVIDING EFFICIENT LOSSLESS COMPRESSION FOR SMALL DATA BLOCKS IN PROCESSOR-BASED SYSTEMS

QUALCOMM Incorporated, S...

1. A compressed memory controller (CMC), comprising:a mask table providing a plurality of masks and an associated plurality of prefixes;
a pattern identification circuit configured to:
receive a plurality of input words;
for each mask of the plurality of masks of the mask table:
apply the mask to each unassigned input word of the plurality of input words to generate a corresponding plurality of patterns;
determine whether a most frequently occurring pattern exists among the plurality of patterns; and
responsive to determining that a most frequently occurring pattern exists among the plurality of patterns:
output the most frequently occurring pattern and an uncompressed data portion of each unassigned input word to an output generation circuit in association with a prefix of the plurality of prefixes associated with the mask; and
assign the prefix associated with the mask to each unassigned input word corresponding to the most frequently occurring pattern; and
output a plurality of assigned prefixes assigned to the plurality of input words to the output generation circuit;
the output generation circuit configured to generate a compressed output block comprising:
the plurality of assigned prefixes assigned to the plurality of input words;
one or more most frequently occurring patterns, each associated with one of the plurality of assigned prefixes; and
one or more uncompressed data portions of a corresponding one or more input words of the plurality of input words.

US Pat. No. 10,191,680

MEMORY ACCESS CONTROL

Hewlett Packard Enterpris...

1. A method performed on a computing device, comprising:receiving a request to execute an instruction specified to access a first unit of memory identified by a target address, wherein the instruction is associated with a second unit of memory associated with a source address;
identifying a sensitivity value of the target address, wherein identifying the sensitivity value comprises extracting bits from the target address;
identifying a trust value of the source address, wherein identifying the trust value comprises extracting bits from the source address; and
determining whether the request to execute the instruction is trusted to access the first memory unit based on the sensitivity value of the target address and the trust value of the source address.

US Pat. No. 10,191,678

SYSTEM AND METHOD FOR DATA RE-PROTECTION WITH ERASURE CODING

EMC IP Holding Company LL...

1. A computer-implemented method to provide data re-protection, comprising:encoding data using an erasure coding technique, wherein the encoding includes dividing the data into k data fragments (D), and
creating, from the data fragments, m redundant coding fragments (C) using a coding matrix, wherein the redundant coding fragments allow for recovery of one or more of the data fragments;
storing the data fragments and redundant coding fragments across a set of storage nodes of a distributed data storage system;
identifying a data fragment for removal from the set of storage nodes; and
performing a re-encoding to reflect the removal of the identified data fragment, wherein the re-encoding includes for each of the redundant coding fragments,
performing a calculation to obtain an updated coding fragment (C?), wherein the calculation is based on an operation performed using at least a portion of the coding matrix and the identified data fragment.

US Pat. No. 10,191,669

REDUNDANT SAS STORAGE VIRTUALIZATION SUBSYSTEM AND SYSTEM USING THE SAME AND METHOD THEREFOR

Infortrend Technology, In...

1. A redundant storage virtualization subsystem (SVS) for providing data storage space, comprising:a redundant external storage virtualization controller (SVC) pair which are for performing IO operations in response to IO requests from a host entity, and comprise a first external SVC and a second external SVC both for coupling to the host entity; and
a group of physical storage devices (PSDs) for providing data storage space to the host entity, in which at least one member of said group of PSDs is coupled to the said redundant external SVC pair through a serial signal interconnect for transmission with serial attached small computer system interface-(SAS) protocol, in which each of the PSDs is a hard disk drive (HDD) or a solid state drive (SSD);
wherein in the redundant external SVC pair, each of the external SVCs further comprises:
a central processing circuitry for performing the IO operations in response to the IO requests;
at least one IO device interconnect controller coupled to said central processing circuitry;
at least one host-side IO device interconnect port provided in one of said at least one IO device interconnect controller for coupling to said host entity; and
at least one SAS device-side IO device interconnect port provided in one of said at least one IO device interconnect controller coupled to said PSDs through said serial-signal interconnect;
wherein when one SVC in said redundant external SVC pair is not on line or goes off line after being on line, the alternate SVC in said redundant external SVC pair will automatically take over the functionality originally performed by said one SVC in the redundant external SVC pair;
wherein an inter-controller communication channel (ICC) is provided between the two SVCs in said redundant external SVC pair for communicating state synchronization information;
wherein said inter-controller communication channel is to exchange parameters and data relating to operation of the redundant storage virtualization subsystem;
wherein said first external SVC and said second external SVC are configured to define at least one virtualized logical media unit (LMU) consisting of sections of said group of PSDs, and are configured to provide a mapping that maps combination of the sections of said group of PSDs to the at least one virtualized LMU visible to the host entity, and the at least one virtualized LMU is contiguously addressable by the host entity to which the at least one virtualized LMU is made available;
wherein the IO requests are parsed to determine what operation is to be performed and on which sections of the virtualized LMU the operation is to be performed;
wherein when the operation comprises internally-emulated, asynchronous device sub-operations, then the SVC executes the associated sub-operations including transferring any associated data to/from the host entity, and wherein when there is a failed operation, the SVC responds to the host entity with a status report indicating that the operation failed;
wherein when one of the SVC pair detects a malfunction of the other SVC, the one SVC monitors a state of the SVS to determine whether to send a signal to the malfunctioning SVC; and
wherein said redundant external SVC pair are alive and perform an IO request rerouting function such that when one of said redundant external SVC pair, both of which are alive, receives one of the I/O requests accessing the at least one virtualized LMU, then the I/O request is dispatched through the one SVC or the other SVC to access the at least one virtualized LMU.

US Pat. No. 10,191,668

METHOD FOR DYNAMICALLY MODELING MEDIUM ERROR EVOLUTION TO PREDICT DISK FAILURE

EMC IP Holding Company LL...

1. A computer-implemented method for predicting disk failures in a redundant array of independent disks (RAID) environment, the method comprising:respectively receiving hard disk status information from each set of a plurality of sets of hard disks in a storage system, wherein the hard disk status information comprises a plurality of states within the set, a number of hard disks within the set, and an indicator of how many hard disks have failed within the set;
for each set of the plurality of sets of hard disks,
calculating a transitional probability that a hard disk will fail within a predetermined period of time based on the respective hard disk status information, wherein calculating the transitional probability comprises:
querying a medium error history of hard disks within the set,
using the medium error history to identify which of the hard disks has experienced at least one medium error,
counting a number of transitions of each of the hard disks having the at least one medium error according to different transition types, each of the transition types representing a specific transition from one of the plurality of states to another of the plurality of states, wherein the one state and the other state are of same state or different states, and
identifying a number of transition types based on the counting, and
generating a first risk profile for the hard disk based on the calculated transitional probability;
generating a second risk profile for a set of hard disks based on two or more of the first risk profiles; and
determining which of the plurality of sets of hard disks has a highest probability of failing within the predetermined period of time based on the second risk profile.

US Pat. No. 10,191,664

MEMORY SYSTEM

SK Hynix Inc., Gyeonggi-...

1. A memory system comprising:a first memory device including a first memory and a first memory controller configured to control the first memory to store data;
a second memory device including a second memory and a second memory controller configured to control the second memory to store data; and
a processor is configured to execute an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the second memory controller transfers a signal between the processor and the second memory device based on at least one of values of a handshaking information field included in the signal,
wherein the first memory includes a plurality of first high-capacity memory cores configured to work as cache memories for the second memory,
wherein the first memory device further includes a first memory management logic operatively and commonly coupled with the plurality of first high-capacity memory cores, and configured to support high-speed data communication between the processor and the plurality of first high-capacity memory cores,
wherein the second memory includes a plurality of second high-capacity memory cores configured to work as system memories,
wherein the second memory device further includes a second memory management logic operatively and commonly coupled with the plurality of second high-capacity memory cores, and configured to support data communication between the processor and the plurality of second high-capacity memory cores,
wherein the second memory management logic includes a buffer configured to buffer write data, based on which the plurality of second memory cores are updated,
wherein the second memory controller firstly buffers the write data in the buffer, and then the second memory management logic independently updates the plurality of second memory cores based on the buffered write data, and
wherein the at least one of values of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

US Pat. No. 10,191,658

LIFECYCLE FOR OFFLINE DATA

SAP SE, Walldorf (DE)

10. The system of claim 9, the operations further comprising, in response to determining that a trigger associated with performing a memory management process has occurred based on the set of memory management rules:identifying, by the memory management process and from the set of memory management rules, a threshold age of particular offline data instances corresponding to a deletion action;
comparing, by the memory management process, the identified threshold age to a current age for each of the set of offline data instances based on their respective creation timestamp or the most recent time of access; and
deleting, by the memory management process and from the set of memory management rules, at least a subset of the set of offline data instances wherein the age of a particular offline data instance meets or exceeds the identified threshold age of the particular offline data instances.

US Pat. No. 10,191,655

MOBILE TERMINAL AND METHOD FOR CONTROLLING THE SAME

LG ELECTRONICS INC., Seo...

1. A mobile terminal, comprising:a display comprising a first region and a second region that extends from at least one side of the first region; and
a controller configured to:
independently switch each of the first region and the second region from either an active state to an inactive state, or from an inactive state to an active state, based on an occurrence of a first event;
independently control brightness of each of the first region and the second region when both the first region and the second region are in the active state based on an occurrence of a second event;
cause the display to display an execution screen of an application in the first region in response to a user input for executing the application, the brightness of the first region increasing from a first preset brightness level to a first predetermined brightness level in response to the user input; and
cause the display to display a screen for controlling execution of the application in the second region in response to the user input, the brightness of the second region decreasing from a second preset brightness level to a second predetermined brightness level in response to the user input,
wherein the user input is received while the first region is in the active state with the first preset brightness level and while the second region is in the active state with the second preset brightness level, and
wherein the execution screen is displayed at the first predetermined brightness level in the first region while the screen for controlling execution of the application is displayed at the second predetermined brightness level in the second region after receiving the user input,
wherein the controller is further configured to set a sequence of switching the first region and the second region according to an order set by a user such that one of the first region and the second region is switched first to the active state or the inactive state before another one of the first region and the second region is switched to the active state or the inactive state according to the set sequence.

US Pat. No. 10,191,654

SYSTEM AND METHOD FOR INPUTTING TEXT INTO ELECTRONIC DEVICES

TOUCHTYPE LIMITED, Londo...

1. A system comprising:one or more processors; and
program instructions that when executed by the one or more processors, cause the one or more processors to perform operations comprising:
instantiate an entry mechanism for entering an input comprising at least one character, symbol, numeral or punctuation mark;
instantiate a typing pane configured to display the input entered via the entry mechanism;
wherein, in response to automatic selection of a prediction based on the input entered via the entry mechanism, the typing pane is configured to replace the input entered via the entry mechanism by the prediction; and
instantiate an undo indication, wherein in response to user selection of the undo indication, the typing pane is configured to replace the selected prediction by the input entered via the entry mechanism;
wherein the undo indication is instantiated in response to the automatic selection of the prediction and in response to one or more subsequent selections of a delete/backspace indication after the automatic selection of the prediction.

US Pat. No. 10,191,653

METHOD AND SYSTEM FOR INK DATA GENERATION, INK DATA RENDERING, INK DATA MANIPULATION AND INK DATA COMMUNICATION

Wacom Co., Ltd., Saitama...

1. A method of outputting digital ink, the method comprising:inputting event data including stylus coordinate positions;
generating a set of control points according to a defined curve interpolation algorithm based on the stylus coordinate positions included in the event data; and
outputting the set of control points, a start parameter indicative of a start point of rendering within a starting segment in which the rendering starts, and an end parameter indicative of an end point of rendering within an ending segment in which the rendering ends, wherein the starting segment and the ending segment are part of a plurality of segments formed by the set of control points.

US Pat. No. 10,191,650

ACTIONABLE CONTENT DISPLAYED ON A TOUCH SCREEN

MICROSOFT TECHNOLOGY LICE...

1. A computer-implemented method comprising:displaying media on a touchscreen display, the media including a photograph;
detecting a user gesture performed on the touchscreen display;
determining text selected by the user gesture;
determining a user intent based at least partly on the text selected by the user gesture;
determining a context associated with the text selected by the user gesture based on the user intent, the context including additional text captured in the media, wherein the additional text is associated with the text selected by the user gesture; and
automatically performing one or more follow-up actions based at least partly on the text selected by the user gesture and based at least partly on the context.

US Pat. No. 10,191,584

REDUCING CONNECTIONS FROM A SENSING MODULE

Synaptics Incorporated, ...

1. An input device, comprising:a first glass layer;
a plurality of transmitter electrodes disposed on the first glass layer and configured for capacitance sensing;
a second glass layer;
a plurality of receiver electrodes disposed on the second glass layer and configured for capacitance sensing; and
a multiplexer disposed on the first glass layer and coupled to a plurality of sources and a sensing channel,
wherein the multiplexer selectively couples one of the plurality of sources to the sensing channel based on at least a control signal, and
wherein the plurality of sources comprises the plurality of transmitter electrodes and the plurality of receiver electrodes.

US Pat. No. 10,191,581

FOLDING DISPLAY DEVICE

SHANGHAI TIANMA MICRO-ELE...

1. A folding display device, comprising:a folding shaft
a display panel configured to be folded along the folding shaft;
wherein, the folding shaft is configured to partition the display panel into a first display portion and a second display portion, wherein
a folding state detecting electrode is provided on the first display portion and/or the second display portion, and the folding state detecting electrode is a capacitive detecting electrode,
wherein a first folding state detecting electrode is provided on a side of the first display portion that is close to the folding shaft, and a second folding state detecting electrode is provided on a side of the second display portion that is close to the folding shaft, and the first folding state detecting electrode and the second folding state detecting electrode are mutual-capacitive detecting electrodes,
wherein at least one of the first folding state detecting electrode and the second folding state detecting electrode comprises a plurality of first folding state detecting subelectrodes electrically independent.

US Pat. No. 10,191,580

DISPLAY DEVICE AND METHOD OF DRIVING THE SAME IN TWO MODES

Samsung Display Co., Ltd....

1. A display device, comprising:a display panel comprising a first display substrate and a second display substrate facing the first display substrate;
scan line groups, each scan line group comprising a first scan line sub-group, a second scan line sub-group connected to the first scan line sub-group, and a third scan line sub-group disposed between the first scan line sub-group and the second scan line sub-group;
source line groups, each source line group comprising a first source line sub-group, a second source line sub-group connected to the first source line sub-group, and a third source line sub-group disposed between the first source line sub-group and the second source line sub-group;
a first driver configured to provide first scan signals to the scan line groups in a first mode and to provide second scan signals to the scan line groups in a second mode, a magnetic field being induced by a current path formed by the first scan line sub-group and the second scan line sub-group;
a second driver configured to provide first sensing signals corresponding to a variation in a capacitance from the source line groups in the first mode, and to provide second sensing signals according to a resonant frequency associated with an input device, the second sensing signals being provided from the source line groups in the second mode; and
a touch sensor configured to receive the first sensing signals and the second sensing signals and to determine coordinate information of an input position based on the first sensing signals and the second sensing signals.

US Pat. No. 10,191,577

ELECTRONIC DEVICE

Samsung Electronics Co., ...

1. An electronic device comprising:a housing comprising a first surface that faces in a first direction, and a second surface that faces in a second direction opposite to the first direction, the housing comprising a transparent plate forming at least a part of the first surface of the housing;
a display disposed between the transparent plate and the second surface of the housing, and comprising a first surface that faces in the first direction and a second surface that faces in the second direction;
at least one sensor disposed between the second surface of the display and the second surface of the housing, the sensor configured to be exposed to light passing through the display;
a processor electrically coupled with the display and the at least one sensor; and
a memory electrically coupled with the processor,
wherein the memory stores instructions and the processor is configured to execute the instructions to:
receive a user input for capturing an image facing the first direction;
in response to receiving the user input, activate the at least one sensor during a first time period to receive the light being passed through the transparent plate;
during the first time period, deactivate the display except for a first region in which the at least one sensor is disposed, and display a graphical object on the first region for applying a filter effect to the image;
in response to detecting that the first time period has elapsed from the time for receiving the user input, deactivate the at least one sensor during a second time period; and
during the second time period, activate the display including the first region for displaying the image to which the filter effect is applied;
wherein the first time period and the second time period are repeatedly alternating, and
wherein the filter effect is based on a shape of the graphical object.

US Pat. No. 10,191,575

IN-CELL TOUCH TYPE LIQUID CRYSTAL DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. A liquid crystal display device comprising:a substrate including first and second touch blocks adjacent to each other, the first and second touch blocks including first and second sub-pixels, respectively;
a first electrode in each of the first and second sub-pixels;
a second electrode in each of the first and second touch blocks, wherein the second electrode of the first touch block and the second electrode of the second touch block are separated from each other;
first and second data lines disposed at side portions of the first and second sub-pixels, respectively; and
wherein the first and second sub-pixels face in the same direction, and are disposed between the first and second touch blocks,
wherein the first and second sub-pixels are disposed between the first and second data lines, and a field blocking line is disposed between the first and second sub-pixels.

US Pat. No. 10,191,571

SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A substrate, comprising:a base; and
a signal line arranged on the base,
wherein the signal line comprises at least two main film layers, a first additional film layer arranged between every two adjacent main film layers of the at least two main film layers, and at least one of a second additional film layer arranged on one side of the signal line adjacent to the base and a third additional film layer arranged on the other side of the signal line away from the base, wherein an electrical conductivity of each of the at least two main film layers is larger than that of the first additional film layer; and a crystallinity of each of the at least two main film layers is lower than that of the first additional film layer, and the second additional film layer and the third additional film layer are configured to increase an adhesive force of the signal line, and the second additional film layer directly contacts an entirety of a surface of the signal line on the one side of the signal line adjacent to the base and has a same outermost boundary as that of the signal line, and the third additional film layer contacts an entirety of a surface of the signal line on the other side of the signal line away from the base and has a same outermost boundary as that of the signal line.

US Pat. No. 10,191,569

OPERATING TOOL, INPUT DEVICE, AND ELECTRONIC DEVICE

MITSUBISHI ELECTRIC CORPO...

1. An operating tool comprising:a holder to be fixed onto a detection surface of a touch panel;
a movable member movably supported by the holder;
a movable contact point that is provided on the movable member, and that moves, while making contact with the detection surface of the touch panel, as the movable member moves; and
a plurality of holder contact points that are provided on the holder, and that are to be in contact with the detection surface of the touch panel in a positional relationship of the plurality of holder contact points, the positional relationship corresponding to a function of the operating tool, wherein
the touch panel is a capacitance-type touch panel,
the movable member, the movable contact point, and the plurality of holder contact points are formed of electrically-conductive members,
the holder is formed of an electrically non-conductive member, and
the plurality of holder contact points are electrically connected to the movable member.

US Pat. No. 10,191,553

USER INTERACTION WITH INFORMATION HANDLING SYSTEMS USING PHYSICAL OBJECTS

Dell Products, L.P., Rou...

1. A method for user interaction with information handling systems, the method comprising:acquiring image data associated with an information handling system;
identifying a plurality of physical objects from the image data including a first physical object used by a user;
identifying that the first physical object corresponds to a virtual input device from a set of virtual input devices accessible to the information handling system;
identifying a virtual input device category of the virtual input device from a set of virtual input device categories of the set of virtual input devices;
updating tracking information for the virtual input device corresponding to the first physical object, wherein the tracking information is based on a motion of the first physical object;
assigning the virtual input device as an active virtual input device associated with user input to the information handling system;
determining a gesture from a motion of the virtual input device performed by the user corresponding to the tracking information based on the virtual input device category;
identifying a user input command associated with the virtual input device based on the gesture from a set of user input commands accessible to the information handling system and the virtual input device category; and
executing the user input command on the information handling system based on the virtual input device category, wherein the set of virtual input device categories comprise a pointer category, a stylus category, and a dial category.

US Pat. No. 10,191,548

OPERATION APPARATUS

FUJITSU TEN LIMITED, Kob...

1. An operation apparatus that is operable in a plurality of operation modes, the operation apparatus comprising:a touch sensor that generates an output based on an operation performed to the touch sensor by an operator;
a transducer attached to the touch sensor and configured to vibrate the touch sensor so as to give a touch feeling to the operator contacting the touch sensor; and
a controller configured to (i) determine a content of the operation performed to the touch sensor by the operator based on the output of the touch sensor and (ii) select one of the plurality of operation modes based on the determined content of the operation performed to the touch sensor by the operator, wherein
the controller causes the transducer to vibrate the touch sensor with different patterns of vibration so as to give different touch feelings to the operator contacting the touch sensor depending on the determined content of the operation performed to the touch sensor by the operator, the patterns of vibration resulting in a slippery touch feeling, a click touch feeling or a rough touch feeling depending on the operation mode, and
when an adjustment operation is performed after the operation mode is started, a predetermined touch feeling selected from the different touch feelings is given to the operator each time when an operation amount reaches a predetermined amount, the adjustment operation including an operation of drawing a circle or a line, the predetermined amount including an operation distance and a direction of the operation of drawing the cirlci or the line.

US Pat. No. 10,191,543

WEARABLE DEVICE TOUCH DETECTION

Microsoft Technology Lice...

1. A wearable device comprising:at least one pressure sensor on an inner surface of the wearable device, the at least one pressure sensor being configured to detect pressure imparted on the inner surface of the wearable device by a user wearing the wearable device;
at least one other sensor configured to detect movement of the wearable device; and
at least one processor or hardware logic circuit configured to:
based at least on the pressure imparted on the inner surface of the wearable device being detected by the at least one pressure sensor, detect that the user is touching a surface other than the inner surface of the wearable device; and
activate the at least one other sensor responsive to detecting that the user is touching the surface other than the inner surface of the wearable device.

US Pat. No. 10,191,542

VISUAL DISPLAY WITH ILLUMINATORS FOR GAZE TRACKING

Tobii AB, Danderyd (SE)

1. A method of determining a gaze direction of an eye watching a visual display, the method comprising:selecting either a bright-pupil imaging mode or a dark-pupil imaging mode;
determining an image sensor to use for gaze direction determination;
selectively illuminating an eye of a user using a plurality of reference illuminators embedded beneath a screen of a display device;
determining a location of a reflection on the eye from at least one of the plurality of reference illuminators;
determining a particular reference illuminator of the plurality of reference illuminators to use for gaze direction determination based on:
whether the bright-pupil imaging mode or the dark-pupil imaging mode is selected;
the image sensor selected; and
the location of the reflection on the eye from the particular reference illuminator being nearer to a pupil center of the eye than a remainder of the plurality of reference illuminators; and
determining a gaze direction of the eye based on the image sensor selected and the reflection from the particular reference illuminator.

US Pat. No. 10,191,541

AUGMENTING VIRTUAL REALITY CONTENT WITH REAL WORLD CONTENT

Sony Interactive Entertai...

1. A method for changing a virtual reality scene displayed in a head mounted display (HMD), comprising:obtaining sensor data from sensors on the HMD, the sensors including inertial sensors;
processing the sensor data for determining that a criteria is met to transition from the virtual reality scene to an augmented virtual reality scene to be presented by the HMD, the criteria corresponding to predetermined indicators that are suggestive of disorientation of a user when wearing the HMD and being presented the virtual reality scene, the augmented virtual reality scene being a modified version of the virtual reality scene;
overlaying, based on said determining that the criteria is met, at least part of a real world object from a real world view into the virtual reality scene for the augmented virtual reality scene, the real world view being captured by one or more cameras of the HMD;
determining that the criteria is still met after said overlaying and continuing to sequentially overlay additional real world objects as long as the criteria is still met.

US Pat. No. 10,191,539

USER AWARE ODOMETRY CORRECTION TECHNOLOGY

Intel Corporation, Santa...

1. A system comprising:a display;
a camera;
wireless interface circuitry;
a battery;
a housing including a wearable form factor;
one or more drift detectors to generate one or more first signals;
a perception monitor to generate one or more second signals;
one or more processors;
memory; and
one or more storage devices to store instructions, which when executed by at least one of the one or more processors, cause the system to:
detect a pose drift condition with respect to the display based on at least one of the one or more first signals;
detect a reduced perception state with respect to a wearer of the display based on at least one of the one or more second signals; and
trigger a correction of the pose drift condition during the reduced perception state that is to include a selection of a pre-assigned value based on a perception tolerance in the reduced perception state and an application of the pre-assigned value to the display.

US Pat. No. 10,191,538

ELECTRONIC DEVICE DISPLAYS AN IMAGE OF AN OBSTRUCTED TARGET

1. A method executed in a computer system in which two wearable electronic devices (WEDs) capture information while at a geographical location to display a three-dimensional (3D) image of a person that is obstructed from view to one of the two WEDs, the method comprising:capturing, with a first WED at the geographical location, an image of the person;
capturing, with a second WED at the geographical location, an object that blocks the person from being visible with the second WED;
determining, based on the image of the person captured with the first WED and the object captured with the second WED, a location where the person would be visible to the second WED if the person were not blocked by the object; and
displaying, with a display of the second WED at the geographical location, the 3D image of the person over the object at the location where the person would be visible to the second WED if the person were not blocked by the object.

US Pat. No. 10,191,537

SMART WEARABLE DEVICES AND METHODS FOR CUSTOMIZED HAPTIC FEEDBACK

SONY CORPORATION, Tokyo ...

1. A wearable sensor apparatus, comprising:(a) a processor;
(b) a plurality of sensors operably coupled to the processor, said sensors comprising at least one biological sensor configured to measure an internal physical condition of a wearer and at least one non-biological sensor configured to measure an external condition of a wearer;
(c) at least one haptic output coupled to the processor;
(d) a communications module operably coupled to the processor, the module having a transmitter and a receiver: and
(e) programming in a non-transitory computer readable medium and executable on the processor for performing steps comprising:
(i) designating a haptic output for possible sensor results of each sensor;
(ii) acquiring sensor data from at least one sensor worn by a user;
(iii) processing the acquired sensor data with possible sensor results;
(iv) initiating the designated haptic output for matching sensor data;
(v) communicating acquired sensor data to a remote computer;
(vi) executing program commands received from the remote computer;
(vii) identifying at least one possible sensor result from a sensor;
(viii) designating a recipient of a communication regarding the sensor result; and
(ix) sending the communication to the recipient over the communications module when the acquired sensor data and the possible sensor results match.

US Pat. No. 10,191,536

METHOD OF OPERATING A CONTROL SYSTEM AND CONTROL SYSTEM THEREFORE

KONINKLIJKE PHILIPS N.V.,...

1. A method of operating a control system for controlling a device, the control system comprising a motion capture equipment, and a controller for providing control signals for controlling one or more device functions of the device, the method comprising the steps of:capturing, by the motion capture equipment, motion picture images of a space and providing the motion picture images to the controller;
performing a pattern recognition analysis on one or more of the motion picture images for distinguishing input from known and unknown users,
analyzing, by the controller, the motion picture images for detecting user input from a user in the space, comprising:
monitoring one or more gesture zones in said motion picture images, each gesture zone being associated with one respective device function of said one or more device functions,
determining the gesture zone wherein the gesture is detected for establishing the selected device function to control,
detecting by the controller a gesture performed by the user; and
providing, by the controller in response to said detecting of the gesture, a control signal to the device for controlling a selected device function of said one or more device functions.

US Pat. No. 10,191,535

REDUCED ENERGY CONSUMPTION IN A COMPUTER SYSTEM THROUGH SOFTWARE AND HARDWARE COORDINATED CONTROL OF MULTIPLE POWER SUPPLIES

Apple Inc., Cupertino, C...

1. A computing system, comprising:a standby power supply electrically coupled to a sensor, wherein the sensor is configured to produce a sensor signal based on an output from the standby power supply during a standby mode of the computing system; and
a controller electrically coupled to the sensor, wherein the controller is configured to:
receive the sensor signal from the sensor,
when the sensor signal indicates that the output has reached or exceeded an output threshold, enable a main power supply to provide power to an external load removably attached to the computing system, and
determine whether the external, removably attached load is a memory device and provide an enable signal to the main power supply when the memory device has a capacity that is equal to or greater than a memory threshold.

US Pat. No. 10,191,534

STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS

TEXAS INSTRUMENTS INCORPO...

1. A cache memory system, comprising:a cache memory including a tag memory array and a data memory array, wherein the data memory array includes a plurality of cache lines and being divided into a plurality of cache ways, wherein the cache memory is configured to access data in a plurality of addressable locations of the data memory array in response to cache access requests, each cache access request including a request address;
a plurality of pipeline stages, each pipeline stage receiving a respective request address corresponding to one of the cache access requests;
a plurality of buffers, each buffer receiving a respective request address corresponding to one of the cache access requests;
a plurality of decoders, each decoder receiving bits from a set field of a request address received at a respective one of either the pipeline stages or the buffers, and configured to decode the received bits of the set field to output a set of decoded output signals;
a plurality of logic gates to receive the sets of decoded output signals from each of the plurality of decoders, each logic gate outputting a respective power enable signal; and
a memory nap controller to track in-flight cache accesses and to control a desired power state of at least a first group of a plurality of contiguous cache lines of the data memory array, the first group of the plurality of contiguous cache lines being organized as a first power group, wherein the first power group is controllable to be in one of a first desired power state or a second desired power state in response to a first power group enable signal output by the memory nap controller, wherein the first power group receives a first voltage in the first desired power state and a second voltage in the second desired power state, the first voltage being greater than the second voltage, and wherein the first power group enable signal is generated based on a plurality of the power enable signals output by the plurality of logic gates, the plurality of the power enable signals upon which the first power group enable signal is generated including at least a subset of all of the power enable signals.

US Pat. No. 10,191,533

METHOD OF ENABLING SLEEP MODE, MEMORY CONTROL CIRCUIT UNIT AND STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A sleep mode enabling method for a memory storage apparatus, wherein a potential signal on a device sleep signal pin of the memory storage apparatus is initially at a first logic level, the sleep mode enabling method comprising:setting a sleep pin connecting flag as a first value if the potential signal on the device sleep signal pin of the memory storage apparatus is at a second logic level opposite to the first logic level;
enabling a device sleep function of the memory storage apparatus if a device sleep function enabling command is received, the sleep pin connecting flag is set as the first value and the device sleep function flag is set as the first value, comprising:
determining whether the sleep pin connecting flag is set as the first value after setting the device sleep function flag as the first value; and
enabling the device sleep function of the memory storage apparatus if the sleep pin connecting flag is set as the first value; and
setting the device sleep function flag as the first value in response to the device sleep function enabling command received from a host system.

US Pat. No. 10,191,532

CONFIGURING POWER MANAGEMENT FUNCTIONALITY IN A PROCESSOR

Intel Corporation, Santa...

1. A system comprising:a plurality of processors;
a processor interconnect to communicatively couple two or more of the plurality of processors;
a system memory comprising a dynamic random access memory communicatively coupled to one or more of the plurality of processors over a memory interconnect;
at least one of the plurality of processors comprising:
a plurality of cores formed on a single semiconductor die, a core of the plurality of cores to execute one or more threads;
the core of the plurality of cores comprising a fetch unit to fetch instructions from an instruction cache, a decode unit to decode the instructions and a plurality of execution units to perform out-of-order execution of the instructions;
one or more control registers to store a first indication that two or more cores of the plurality of cores are to operate at independent performance states comprising active power states in which the two or more cores are to operate at different frequencies and a second indication that a first set of cores are to operate at a common performance state comprising an active power state in which the first set of cores are to operate at a common frequency;
a plurality of voltage regulators formed on the single semiconductor die, a voltage regulator of the plurality of voltage regulators associated with one of the plurality of cores;
a power controller formed on the single semiconductor die, the power controller to control the plurality of voltage regulators to provide a voltage and/or frequency to a first core of the plurality of cores independently of a voltage and/or frequency to one or more other cores and to determine whether to update the voltage and/or frequency of the first core based on a workload of the first core, thermal constraints, and activity counters; and
at least one additional voltage regulator formed on the single semiconductor die and associated with processor circuitry external to the plurality of cores, the at least one additional voltage regulator to allow the processor circuitry external to the plurality of cores to operate at a different voltage and/or frequency than one or more cores of the plurality of cores.

US Pat. No. 10,191,531

HYBRID CONVERTER SYSTEM

GENERAL ELECTRIC COMPANY,...

1. A voltage converter, comprising:a first set of silicon (Si)-based power devices coupled to a first direct current (DC) voltage source;
a second set of Si-based power devices coupled to a second DC voltage source;
a first set of silicon-carbide (SiC)-based power devices coupled to the first set of Si-based power devices and to the second set of Si-based power devices, wherein each SiC-based power device of the first set of SiC-based power devices is configured to switch at a higher frequency as compared to each Si-based power device of the first and second sets of the Si-based power electronic devices;wherein Si-based power devices in the voltage converter are twice that of SiC-based power devices in the voltage converter;wherein the voltage converter further comprises:a capacitor coupled to across the first set of SiC-based power devices;
wherein the first set of SiC-based power devices is connected across a first output terminal of the first set of Si-based power devices and a second output terminal of the second set of Si-based power devices; and
wherein the first and second output terminals of the first and second sets of Si-based power devices are obtained at interconnection points of Si-based power devices in the first and second sets respectively.

US Pat. No. 10,191,530

SELF-CONTAINED METHOD AND DEVICE FOR MANAGING A FIRST ELECTRONIC APPARATUS

Orange, Paris (FR)

1. A method for managing a multimedia providing apparatus, the multimedia providing apparatus comprising a functional device that in operation provides multimedia data to a multimedia production apparatus for use by the multimedia reproduction apparatus and a management device, wherein the multimedia providing apparatus and the multimedia reproduction apparatus are locally connected, the method, carried out by the management device, comprising:transmitting, from the management device of the multimedia providing apparatus to the multimedia reproduction apparatus, a request for the status of the multimedia reproduction apparatus;
receiving, at the management device of the multimedia providing apparatus from the multimedia reproduction apparatus in response to the request, data indicating the activity status of the multimedia reproduction apparatus; and
changing, by the management device, the activity state of the functional device of the multimedia providing apparatus based on the activity status indicated by the received data.

US Pat. No. 10,191,529

REAL-TIME DATA MANAGEMENT FOR A POWER GRID

ACCENTURE GLOBAL SERVICES...

1. A method for data transfer in a power grid, the method comprising:monitoring, by a processor, a data transfer rate at which power grid data is communicated to data consumer instances via a communication bus, the communication bus configured to exchange the power grid data between data producers and the data consumer instances, the power grid data comprising data related to the power grid received from a plurality of different equipment operable as the data producers within the power grid;
identifying, by the processor, sub-processes of a data consumer instance that process power grid data only in parallel and sub-processes of the data consumer instance that process power grid data only in serial, wherein the sub-processes of the data consumer instance that process the power grid data only in parallel comprise parallelizable threads and the sub-process of the data consumer instance that process the power grid data only in serial comprise non-parallelizable threads;
determining, by the processor, an estimated parallel processing time of the sub-processes of the data consumer instance that process power grid data only in parallel and an estimated serial processing time of the sub-processes of the data consumer instance that process power grid data only in serial; and
controlling, by the processor, the data transfer rate based the estimated parallel processing time and the estimated serial processing time.

US Pat. No. 10,191,528

SENSOR FOR DETECTING PRESENCE OF MATERIAL

Apple Inc., Cupertino, C...

1. A device comprising:one or more sensors configured to detect a material covering the device; and
logic coupled to the one or more sensors, the logic configured to:
detect one or more characteristics of the material covering the device, wherein the material has a first characteristic if the material is covering a first portion of the device from a first direction, and has a second characteristic if the material is covering the first portion of the device from a second direction different from the first direction, and
change an operating state of the device based on the detected one or more characteristics, wherein changing the operating state comprises:
in accordance with the material having the first characteristic, the device entering a first operating state, and
in accordance with the material having the second characteristic, the device entering a second operating state different from the first operating state.

US Pat. No. 10,191,527

BROWN-OUT DETECTOR

ARM Limited, Cambridge (...

1. An integrated circuit, comprising:a first stage having first transistors and resistors arranged to receive an input voltage and provide a first voltage that is substantially independent of temperature while remaining related to the input voltage;
a second stage configured to provide a single-ended to differential up-converter circuit and having second transistors arranged to receive the input voltage and receive the first voltage from the first stage and up-convert the first voltage as the input voltage lowers, wherein the second stage is configured to provide a second voltage corresponding to a differential voltage of the input voltage and the first voltage; and
a third stage having third transistors arranged to receive the second voltage and provide a high-gain output voltage corresponding to an error signal.

US Pat. No. 10,191,526

APPARATUS AND METHOD FOR TRANSMITTING DATA SIGNAL BASED ON DIFFERENT SUPPLY VOLTAGES

QUALCOMM Incorporated, S...

1. An apparatus, comprising:a pair of input transistors configured to generate an output differential data signal at output terminals based on an input differential data signal applied to control terminals of the pair of input transistors; and
a first pair of over-voltage protection transistors coupled in series with the pair of input transistors between the output terminals and a voltage rail, respectively, wherein the first pair of over-voltage protection transistors include control terminals configured to receive a first bias voltage based on a common mode voltage of the output differential data signal, and wherein the first bias voltage biases the first pair of over-voltage protection transistors to prevent over-voltage stress to the first pair of over-voltage protection transistors and the pair of input transistors, wherein the first bias voltage is at a first voltage level if the common mode voltage is formed using a supply voltage provided by a High-Definition Multimedia Interface (HDMI) data sink device.

US Pat. No. 10,191,525

MODULES STORING POWER CONFIGURATION PARAMETERS

HEWLETT PACKARD ENTERPRIS...

1. A method comprising:detecting a presence of a module in a socket;
based on detecting the presence of the module, supplying power to a memory of the module while restricting power to an integrated circuit of the module;
reading information stored in the memory of the module that specifies a power-on sequence for the integrated circuit of the module; and
applying power to the integrated circuit of the module according to the power-on sequence specified in the information when an alignment of the module with the socket is confirmed.

US Pat. No. 10,191,524

LOW-POWER TYPE-C RECEIVER WITH HIGH IDLE NOISE AND DC-LEVEL REJECTION

Cypress Semiconductor Cor...

1. A device comprising:a receiver circuit coupled to a Configuration Channel (CC) line of a Universal Serial Bus (USB) Type-C subsystem, wherein the receiver circuit is configured to:
receive valid BMC-encoded data from an incoming signal on the CC line when the incoming signal has more than 250 mV of direct current (DC) offset with respect to a local ground; and
operate in the presence of a VBUS charging current that is specified in a USB-PD specification.

US Pat. No. 10,191,523

SYSTEMS AND METHODS FOR MANAGEMENT OF EXHAUST TEMPERATURE IN AN INFORMATION HANDLING SYSTEM

Dell Products L.P., Roun...

1. An information handling system comprising:at least one information handling resource, including a first and a second information handling resource;
heat-rejecting media thermally coupled to the at least one information handling resource for transferring heat generated to an exterior of an enclosure housing the at least one information handling resource, wherein the heat-rejecting media is proximate to an exhaust of the enclosure such that the heat-rejecting media is subject to physical contact with a user of the information handling system via the exhaust while the information handling system is operational and while the enclosure is closed;
a temperature sensor for sensing an ambient temperature associated with the at least one information handling resource; and
a thermal management driver comprising a program of instructions embodied in non-transitory computer-readable media and executable by a processor, the thermal management driver configured to:
based on a first power consumed by the first information handling resource, a second power consumed by the second information handling resource, and thermal resistances associated with the heat-rejecting media, calculate an exhaust temperature and a second exhaust temperature of the heat-rejecting media proximate to, respectively, the exhaust of the enclosure and a second exhaust of the enclosure; and
based on a determination that at least one of the exhaust temperature and the second exhaust temperature is greater than a maximum temperature that is safe for human contact, control at least one of an operating frequency of the at least one information handling resource and a flow rate of fluid proximate to the heat-rejecting media to lower the at least one of the exhaust temperature and the second exhaust temperature to a new exhaust temperature that is below the maximum temperature that is safe for human contact.

US Pat. No. 10,191,508

PERIPHERAL MODULE AND CIRCUIT ARRANGEMENT FOR A DIGITAL INPUT OF THE PERIPHERAL MODULE

Siemens Aktiengesellschaf...

1. A circuit arrangement for a digital input of an electronic peripheral module, comprising:an inlet connection forming a digital input;
a ground connection;
a semiconductor switching device arranged between the inlet connection and the ground connection, said semiconductor switching device limiting an input current;
a reference voltage source connected to a control input of the semiconductor switching device to control the semiconductor switching device; and
a regulator configured to regulate the reference voltage source depending on an input voltage at the inlet connection such that, for a first voltage value, the semiconductor switching device adjusts the input current for the input voltage to a first input current and, for a second voltage value, adjusts the first input current for the input voltage to a second input current;
wherein the first voltage value is greater than the second voltage value and the first input current is less than the second input current on account of the regulator;
wherein the semiconductor switching device comprises a first transistor with a collector, an emitter and a base, the base being connected to the control input, and the regulator including a second transistor with a collector, an emitter and a base, the base of the second transistor being connected to the collector of the first transistor via a voltage divider and the collector of the second transistor being connected to the control input; and
wherein the electronic peripheral module includes a means for level detection which is connected to the inlet connection.

US Pat. No. 10,191,482

MOTOR CONTROLLER AND METHODS OF MONITORING MOTOR STATUS

Regal Beloit America, Inc...

1. A motor controller for controlling an electric motor, said motor controller comprising:at least one integrated sensor disposed on the electric motor, said at least one integrated sensor configured to collect sensor data associated with a status of the electric motor for a period of time, the period of time beginning at an activation time and extending at least until an installation time, wherein the activation time is a time at which the energy management system is activated to power said at least one integrated sensor;
an energy management system configured to power said at least one integrated sensor for at least a portion of the period of time; and
a memory device configured to store the sensor data.

US Pat. No. 10,191,476

METHOD AND APPARATUS FOR GENERATING GEOMETRIC DATA FOR USE IN ADDITIVE MANUFACTURING

RENISHAW PLC, Wotton-Und...

1. Apparatus for generating geometric data for use in an additive manufacturing process, the apparatus comprising a processing unit, the processing unit programmed to:receive data defining surface geometry of a plurality of objects to be built together in an additive manufacturing process;
provide a user interface that allows a user to define a location of each object within a common build volume;
identify at least one selected object from a user selection of at least one of the plurality of objects located in the common build volume;
carry out a slicing operation on the at least one selected object located in the common build volume independently from at least one unselected object of the plurality of objects located in the common build volume such that sections of the at least one selected object are determined without carrying out a slicing operation on the at least one unselected object; and
output control data based upon the determined sections for controlling an additive manufacturing apparatus to build the plurality of objects,
wherein the user interface comprises a display and a user input device,
the user can select through the user input device the at least one selected object, and
the processing unit is programmed to at least one of determine and re-determine the sections of the at least one selected object whilst sections of the at least one unselected object remain at least one of undefined and previously defined, the processing unit causing the display to display the at least one selected object for which sections have been at least one of determined and re-determined together with the at least one unselected object such that relative positions of the objects can be observed by the user on the display.

US Pat. No. 10,191,472

NUMERICAL CONTROLLER PROVIDED WITH PROGRAM PRE-READING FUNCTION

FANUC Corporation, Minam...

1. A numerical controller which executes a plurality of numerical control (“NC”) programs at a same time in parallel by successively pre-reading blocks of the plurality of NC programs from a memory or from a storage device connected via a network so that the generation of an alarm or an immediate axes stop due to the pre-reading failing to be performed in time becomes less liable to occur, the numerical controller comprising:non-transitory computer readable memory;
one or more hardware processors coupled to the non-transitory memory and configured to read instructions from the non-transitory memory to cause the numerical controller to perform operations comprising:
storing execution times of the respective blocks in the plurality of NC programs;
reading out, when one block in an NC program among the plurality of NC programs is pre-read, the execution time of the pre-read block, and calculates a sum total of the execution time of the pre-read block and the execution times of other blocks in the NC program which have been pre-read;
extracting, from the plurality of NC programs, one NC program having the smallest sum total of the execution times calculated; and
subsequently performing pre-reading of one block of the NC program which is extracted and has the smallest sum total of the execution times among those of the plurality of NC programs.

US Pat. No. 10,191,469

NUMERICAL CONTROL DEVICE FOR SAFETY APPROACH TO RESTARTING MACHINING POINT

FANUC Corporation, Minam...

1. A numerical control device for moving a tool to a restarting machining point when restarting machining after machining interruption based on machining program, the numerical control device comprising:an approach path calculation unit configured to calculate an approach path to the restarting machining point of the tool;
a manual operation approach command unit configured to receive a manual operation approach instruction by an operator; and
an approaching operation switching unit configured to switch automatic operation approach and manual operation approach, wherein approaching operation switching unit is further configured to determine when the tool is within a predetermined approach region for safely moving the tool to the restarting machining point by automatic operation, the predetermined approach region is an area based on both (i) the restarting machining point and (ii) a manual operation starting point, the manual operation starting point being a point when the operator stops the automatic operation approach during the automatic operation approach to conduct manual operation approach,
wherein the approaching operation switching unit is configured to receive switching request from the operator during the manual operation approach and switch to the automatic operation approach, or receive manual intervention by the operator during the automatic operation approach and switch to the manual operation approach.

US Pat. No. 10,191,456

METHOD AND SYSTEM FOR SOFTWARE DEFINED METALLURGY

Desktop Metal, Inc., Bur...

1. A system for generating a user-adjustable thermal processing parameter profile for use by a furnace, comprising:a user interface configured to receive one or more materials properties provided by a user;
a processor;
a memory with computer code instructions stored thereon, the memory operatively coupled to the processor such that, when executed by the processor, the computer code instructions cause the system to implement:
communicating with the furnace to ascertain one or more thermal processes associated with the furnace;
identifying one or more part characteristics associated with a part to be processed by the furnace; and
determining a thermal processing parameter profile of at least one thermal processing parameter corresponding to each of the one or more thermal processes, based on (i) the one or more part characteristics and (ii) the one or more materials properties, the thermal processing parameter profile characterizing a cycle of the each of the one or more thermal processes; a binder trap configured to store binder hydrocarbon products; and a valve that controls a path from the binder trap to the furnace, such that through the valve, the binder hydrocarbon products are selectively introduced to the furnace to control a carbon potential of the furnace environment.

US Pat. No. 10,191,443

IMAGE FORMING APPARATUS

Canon Kabushiki Kaisha, ...

1. An image forming apparatus comprising:an openable member rotatable relative to a main assembly of the image forming apparatus; and
a supporting member connected between said main assembly of the image forming apparatus and said openable member and configured to support said openable member when said openable member is opened,
wherein said supporting member includes a first arm member and a second arm member which are slidable relative to each other, a pinion provided on said first arm member, a viscous damper mounted on a rotation shaft of said pinion, a rack provided on said second arm member and engaged with said pinion, and
wherein by opening said openable member, relative slide movement is caused between said first arm member and said second arm member so that said pinion engaged with said rack rotates and a braking force is produced by said viscous damper.

US Pat. No. 10,191,409

IMAGE FORMING APPARATUS HAVING CONTROLLED TONER DISCHARGE AMOUNT

CANON KABUSHIKI KAISHA, ...

1. An image forming apparatus comprising:an image bearing member;
a developing device that develops an electrostatic latent image formed on the image bearing member;
a toner bottle which is configured to supply the developing device with toner, and having a storage portion storing the toner and a discharge portion made of resin and discharging the toner stored in the toner storage portion, with the storage portion configured to rotate relatively to the discharge portion;
an attachment portion configured to be attached with the toner bottle;
a driving portion configured to drive the storage portion in a state that the toner bottle is attached to the attachment portion;
a controller controlling the driving portion;
a memory disposed in the toner bottle and memorizing information regarding component dimensions of a molded discharge portion of the toner bottle; and
an information reading portion that reads information regarding the component dimensions of the molded discharge portion;
wherein the controller controls the driving portion so that a discharge amount of the toner from the discharge portion becomes a specific toner amount targeted based on the information regarding the component dimensions of the molded discharge portion.

US Pat. No. 10,191,402

METHOD FOR FORMING DEVELOPER COMPOSED WITH MOTHER PARTICLES CONTAINING EXTERNAL ADDITIVE

Oki Data Corporation, To...

1. A method for forming a developer composed with a plurality of mother particles containing a coloring agent and an external additive by:fusing a first group of external additive particles of the external additive on and at least partially inside mother particles during a pre-external addition process in which the first group of external additive particles is added to a precursor of the developer before pulverization of the precursor, the first group of external additive particles of the external additive being 60% or more of a total amount of the external additive particles of the external additive added; and
fusing a second group of external additive particles of the external additive on the mother particles during a post-external addition process in which the mother particles are stirred with the second group of external additive particles after the pulverization of the precursor, the second group of external additive particles of the external additive being 40% or less of the total amount of the external additive particles of the external additive added, wherein
an average circularity degree of the developer is ranged within 0.955 to 0.970, and
the developer thus formed is configured to have a peeling rate (%) of the external additive calculated by a following formula (1) is 30.6% or less, being calculated when ultrasonic waves are applied to a polyoxyethylene lauryl ether solution in which the developer is dispersed,
peeling rate (%)=[1?(X/Y)]×100  (1)
wherein X is an amount (weight %) of the external additive included in the developer after the ultrasonic waves are applied,
Y is an amount (weight %) of the external additive included in the developer before the ultrasonic waves are applied,
the polyoxyethylene lauryl ether solution is set such that a density=5% and a temperature=32° C., and
the application of the ultrasonic waves is set such that strength=40 kHz and time=10 minutes.

US Pat. No. 10,191,319

DISPLAY PANEL AND DISPLAY APPARATUS HAVING A PHOTOCHROMIC LAYER

BOE TECHNOLOGY GROUP CO.,...

1. A display panel having a subpixel region and an inter-subpixel region, comprising:a base substrate; and
a photochromic layer on the base substrate at least partially in the subpixel region for preventing light leakage in the subpixel region;
wherein the photochromic layer comprises a plurality of photochromic blocks;
the display panel has a spacer region configured to receive a spacer for maintaining a gap between a first display substrate and a second display substrate facing the first display substrate;
the spacer region is in a light leakage preventing region; and
one of the plurality of photochromic blocks is in the light leakage preventing region.

US Pat. No. 10,191,295

ADVANCED RETROREFLECTING AERIAL DISPLAYS

Looking Glass Factory, In...

1. A retroreflecting display comprising:a first light source that generates a first light output;
a first beam splitter module; and
a retroreflector module opposite the first light source;
wherein the first light source transmits the first light output to the first beam splitter module; wherein the first beam splitter module splits the first light output into a first reflected component and a second transmitted component of the first light output;
wherein the first beam splitter module transmits the second transmitted component to the retroreflector module; wherein the retroreflector module retroreflects the second transmitted component back to the first beam splitter module; wherein the first beam splitter module splits the second transmitted component into a third reflected component and a fourth transmitted component; wherein the third reflected component converges to a first visible real image in free space; further comprising a second light source and a second beam splitter module, the second light source oriented at a ninety-degree angle relative to the first light source ; wherein the second beam splitter module is oriented at a ninety-degree angle relative to the first beam splitter module; wherein, prior to reaching the first beam splitter module, the first light output is transmitted in part by the second beam splitter module; wherein the second light source transmits the second light output to the second beam splitter module; wherein the second beam splitter module splits the second light output into a fifth reflected component and a sixth transmitted component of the second light output; wherein the second beam splitter module reflects the fifth reflected component to the first beam splitter module; wherein the first beam splitter module splits the fifth reflected component into a seventh reflected component and an eighth transmitted component; wherein the retroreflector module retroreflects the eighth transmitted component back to the first beam splitter module; wherein the first beam splitter module splits the eighth transmitted component into a ninth reflected component and a tenth transmitted component; wherein the ninth reflected component converges to a second visible real image in free space.

US Pat. No. 10,191,286

OPTICAL IMAGING STRUCTURE AND VIRTUAL REALITY SPECTACLES

BOE TECHNOLOGY GROUP CO.,...

1. An optical imaging structure, comprising:an eyeglass component for observation by left and right eyes; and
at least one light guide wall distributed along an edge of the eyeglass component, wherein, two opposite end faces of the at least one light guide wall are respectively a light incoming face and a light outgoing face, and the light outgoing face of the at least one light guide wall faces towards an observation side of the optical imaging structure;
wherein, the at least one light guide wall protrudes over the eyeglass component in a direction from the light incoming face to the light outgoing face of the at least one light guide wall, an inner rim of the light outgoing face of the at least one light guide wall joins the edge of the eyeglass component and extends in an optical axis direction of the eyeglass component, and, the light outgoing face of the at least one light guide wall is gradually distanced from the eyeglass component from the inner rim to an outer rim of the light outgoing face; and
wherein, the at least one light guide wall comprises at least a first light guide wall and a second light guide wall respectively disposed at left and right sides of the eyeglass component.

US Pat. No. 10,191,272

ELECTROWETTING ASSEMBLY TECHNIQUE AND CELL STRUCTURE

ABL IP HOLDING LLC, Cony...

1. A method, comprising steps of:preparing a light transmissive member including: a well having a sealed distal end, an opening at a proximal end of the well, and an electrode landing zone around the opening at the proximal end of the well;
forming control channel electrodes electrically isolated from each other on the light transmissive member, each control channel electrode comprising a first part formed on a respective portion of an interior wall surface of the well and a second part formed on a respective portion of the electrode landing zone;
forming a dielectric layer including a first portion covering the first parts of the control channel electrodes on the portions of the interior wall surface of the well and a second portion covering some but not all of the second parts of the control channel electrodes on portions of the electrode landing zone;
installing a flexible circuit board over at least some of the second parts of the control channel electrodes on the electrode landing zone, wherein a surface of the flexible circuit board facing the electrodes includes electrical contacts isolated from each other, each electrical contact being located on the flexible circuit board to contact a part of a respective control channel electrode not covered by the dielectric layer;
installing a flexible seal on the second portion of the dielectric layer, the flexible seal surrounding and having an opening aligned around the proximal end of the well;
installing first and second fluids in the well such that the first fluid is at the sealed distal end of the well and the second fluid fills a remainder of the well to the opening at the proximal end of the well, wherein: the first fluid is relatively non-conductive, the second fluid is relatively conductive, and the first and second fluids are immiscible with respect to each other;
forming a common electrode on at least a portion of a light transmissive plate; and
installing the light transmissive plate over the flexible seal, in such a manner that:
the light transmissive plate covers the opening at the proximal end of the well,
the light transmissive plate forms a contact seal with the flexible seal around the opening at the proximal end of the well, and
the common electrode contacts the second fluid.

US Pat. No. 10,191,271

IMAGE PICKUP SYSTEM

OLYMPUS CORPORATION, Tok...

1. An image pickup system comprising:a light source apparatus configured to sequentially emit lights with a plurality of mutually different wavelength bands as illumination light for illuminating an object;
an objective optical system configured to form an image of light from the object illuminated by the illumination light;
an image pickup device provided with an image pickup surface formed by two-dimensionally arranging a plurality of pixels for receiving the light formed by the objective optical system and photoelectrically converting the received light to generate electric signals;
a judging portion configured to perform a judgment process for judging: the object is observed in which of a distant view and a near view; and
an image pickup control portion configured to perform control for setting a reading mode of the image pickup device to either a single pixel reading mode which is a mode for sequentially reading the electric signals generated by the respective pixels arranged on the image pickup surface one by one, or a pixel addition reading mode which is a mode for, with electric signals generated by one pixel group constituted by a plurality of pixels arranged mutually adjoining one another on the image pickup surface as electric signals corresponding to one pixel, sequentially reading the electric signals corresponding to one pixel, according to a judgment result obtained by the judgment process of the judging portion; wherein
the light source apparatus is configured to be able to sequentially emit light of a red wavelength band, light of a green wavelength band and light of a blue wavelength band as the illumination light; and
the image pickup control portion performs control for setting the reading mode of the image pickup device to the single pixel reading mode when a judgment result that the object is observed in the distant view is obtained, and it is detected that the light of the blue wavelength band is emitted from the light source apparatus as the illumination light; and performs control for setting the reading mode of the image pickup device to the pixel addition reading mode when the judgment result that the object is observed in the distant view is obtained, and it is detected that the light of the red wavelength band is emitted from the light source apparatus as the illumination light.

US Pat. No. 10,191,249

SUBMINIATURE OPTICAL SYSTEM AND PORTABLE DEVICE INCLUDING THE SAME

Samsung Electro-Mechanics...

1. An optical system, comprising:a first lens which has positive refractive power;
a second lens which has negative refractive power;
a third lens which has positive refractive power, a convex object-side surface, and a concave image-side surface;
a fourth lens which has negative refractive power, a concave object-side surface, and a concave image-side surface;
a fifth lens which has positive refractive power, and a meniscus shape of which an image-side surface is convex; and
an image sensor,
wherein the first lens to the image sensor are sequentially disposed from an object side, and
wherein when a distance from an object-side surface of the first lens to an image plane of the image sensor is TTL and a focal length of the optical system is F, 0.7

US Pat. No. 10,191,247

IMAGING LENS HAVING FOUR LENS ELEMENTS, AND ELECTRONIC APPARATUS HAVING THE SAME

Genius Electronic Optical...

1. An imaging lens comprising first, second, third, and fourth lens elements arranged from an object side to an image side in the given order, each of the first, second, third, and fourth lens elements having an object-side surface facing toward the object side and an image-side surface facing toward the image side, wherein:the image-side surface of the first lens element comprises a concave portion in a vicinity of a periphery of the first lens element;
the image-side surface of the second lens element comprises a convex portion in a vicinity of an optical axis of the second lens element;
the third lens element has a positive refractive power and the object-side surface of the third lens element comprises a concave portion in a vicinity of an optical axis of the third lens element;
the object-side surface of the fourth lens element comprises a convex portion in a vicinity of an optical axis of the fourth lens element;
the imaging lens has a fixed focal length and does not include any lens element with refractive power other than the first, second, third, and fourth lens elements; and
the imaging lens satisfies
1.30?Gaa/(G12+G23)?1.83, where
Gaa represents a sum of a distance between the image-side surface of the first lens element and the object-side surface of the second lens element at the optical axis, a distance between the image-side surface of the second lens element and the object-side surface of the third lens element at the optical axis, and a distance between the image-side surface of the third lens element and the object-side surface of the fourth lens element at the optical axis,
G12 represents a distance between the image-side surface of the first lens element and the object-side surface of the second lens element at the optical axis,
G23 represents a distance between the image-side surface of the second lens element and the object-side surface of the third lens element at the optical axis.

US Pat. No. 10,191,246

ZOOM LENS AND IMAGING APPARATUS

FUJIFILM Corporation, To...

1. A zoom lens consisting of, in order from an object side:a first lens group that has a positive refractive power;
a second lens group that has a negative refractive power;
a third lens group that has a positive refractive power;
a fourth lens group that has a negative refractive power; and
a fifth lens group that has a positive refractive power,
wherein all intervals between the lens groups adjacent to each other change during zooming,
wherein an aperture diaphragm is disposed between a surface of the second lens group closest to an image side and a surface of the fourth lens group closest to the object side,
wherein the first lens group and the fifth lens group each consist of two or less lenses,
wherein a lens of the second lens group closest to the object side is a meniscus lens which has a negative refractive power and of which an object side surface has a convex shape,
wherein a lens of the fourth lens group closest to the image side is a meniscus lens which has a negative refractive power and of which an image side surface has a convex shape, and
wherein the following conditional expression (3) is satisfied,
?0.35 where f4 is a focal length of the fourth lens group, and
f1 is a focal length of the first lens group.

US Pat. No. 10,191,243

EXPANDABLE MIRRORS

FORD GLOBAL TECHNOLOGIES,...

5. A mirror implementable in a vehicle, comprising:a first pane having a first reflective surface;
a second pane having a second reflective surface;
a third pane having a third reflective surface,
a mechanism connected with each of the first and second panes, wherein the mechanism is configured, when actuated, to expand a viewing area of the mirror from a first size to a second size larger than the first size, the expanded viewing area comprising the first and second reflective surfaces; and
a positioning motor configured to integrally position the first pane and the second pane as a whole for adjusting an orientation of the viewing area of the mirror,
wherein the mechanism comprises a plurality of guiding rails connecting the first, second and third panes, and wherein the mechanism is configured to expand the viewing area of the mirror by sliding the second and third panes along the plurality of guiding rails to expose each of the first, second and third reflective surfaces such that the viewing area of the mirror comprises the first, second and third reflective surfaces.

US Pat. No. 10,191,239

HYBRID CABLE TRANSITION ASSEMBLY

CommScope Technologies LL...

1. An assembly for breaking out hybrid power/fiber cable, comprising:a hybrid power/fiber cable comprising a plurality of conductors and a plurality of optical fibers, wherein first lengths of the conductors and the optical fibers are circumferentially surrounded by an armor layer, and wherein a portion of the armor layer is circumferentially surrounded by a cable jacket, and wherein second lengths of the conductors and the optical fibers are free of the armor layer and the cable jacket;
a breakout sleeve having an internal bore, a portion of the cable jacket and a portion of the armor layer residing in the internal bore, and portions of the second lengths of the conductors and optical fibers residing in the internal bore;
wherein the breakout sleeve is fixed to the cable jacket and includes arcuate, flexible electrical contacts in the internal bore, and wherein the electrical contacts engage the armor layer.

US Pat. No. 10,191,230

OPTICAL CONNECTORS WITH REVERSIBLE POLARITY

Senko Advanced Components...

1. A reversible polarity fiber optic connector comprising:at least first and second optical ferrules;
a connector housing at least partially surrounding the first and second optical ferrules and having a first exterior wall positioned above the first and second optical ferrules and a second exterior wall positioned beneath the first and second optical ferrules;
a latch coupling positioned on each of the first and second exterior walls of the housing;
a removable latch for engaging either of the first and second exterior wall latch couplings on the connector housing;
wherein positioning the removable latch on the first exterior wall of the connector housing yields a fiber optic connector with a first polarity and positioning the removable latch on the second exterior wall of the housing yields a fiber optic connector with a second polarity, the second polarity being opposite to the first polarity.

US Pat. No. 10,191,229

PLUGGABLE MECHANISM OF OPTICAL TRANSCEIVER

Sumitomo Electric Industr...

1. An optical transceiver that electrically communicates with a host system by being engaged with and disengaged from a cage provided in the host system, the optical transceiver comprising:a housing providing an optical receptacle in one end and an electrical plug in another end thereof, the optical receptacle receiving an optical connector therein, the electrical plug to be engaged with the cage and
a slider movable between a first position and a second position along a direction connecting the optical receptacle with the electrical plug, the slider having a composite opening assembled with both of a bail and a pull-tab, alternatively; and
wherein the composite opening includes a curved opening and a square opening,
wherein the bail provides a hook engaged with the curved opening in the slider; the hook causing a motion of the slider to be movable between the first position and the second position by sliding within the curved opening synchronizing with a rotation of the bail in front of the optical receptacle, and
wherein the pull-tab provides a tab engaged with the square opening of the slider, the tab causing the motion of the slider to be movable between the first position and the second position synchronizing with a linear motion of the pull-tab.

US Pat. No. 10,191,226

CYLINDRICAL OPTICAL FERRULE ALIGNMENT APPARATUS

CommScope, Inc. of North ...

1. A device comprising:a housing including a first port for receiving a first connector;
a ferrule alignment sleeve attached to said housing, wherein said sleeve extends in a longitudinal direction and forms an inner, generally tubular area;
a first rim formed around a first opening at one end of said generally tubular area to receive an end of a first ferrule of the first connector, such that the first ferrule engages said inner, generally tubular area as the first ferrule is inserted into said sleeve;
a first tab adjacent said first rim and projecting away from said first rim and said generally tubular area to interact with a feature attached to the first ferrule to angularly align the first ferrule within said generally tubular area; and
a second tab adjacent said first rim and projecting away from said first rim and said tubular area, wherein said second tab is spaced a predetermined distance away from said first tab.

US Pat. No. 10,191,223

OPTICAL CONNECTOR

Sumitomo Electric Industr...

1. An optical connector comprising:a first plug that secures a first fiber with a first ferrule in an end thereof;
a second plug that secures a second fiber with a second ferrule in an end thereof, the first plug and the second plug jointly rotating around an optical axis common to the first ferrule and the second ferrule, the second plug having a projection;
a sleeve that receives the first ferrule of the first plug in one end thereof and the second ferrule of the second plug in another end thereof;
a shell that encloses the first plug and the second plug therein, the shell providing a hollow that engages with the projection of the second plug; and
a spring provided between the first plug and the shell, the spring pushing the first plug against the second plug outward from the shell,
wherein the first ferrule of the first plug makes physical contact against the second ferrule of the second plug,
wherein the shell has a slit and a cut, the slit providing the hollow in one end thereof,
wherein the cut extends from an edge of the shell facing the second plug to another end of the slit, and
wherein the slit circumferentially extends on a surface of the shell and has an edge closer to the edge of the shell, the edge of the slit making a distance to the edge of the shell gradually increasing from the end continuous to the cut to the hollow.

US Pat. No. 10,191,219

OPTICAL SELECTOR ARRANGEMENT

BAE Systems plc, London ...

1. An optical selector arrangement, comprising:a first set of optical ports, having a first number of optical ports, the first number being greater than or equal to 2;
a second set of optical ports for communicating with the first set of optical ports, the second set of optical ports having a second number of optical ports, the second number being greater than the first number;
a selector interface comprising the second set of optical ports; and
a selector arranged to selectively optically couple the first set of optical ports to a subset of the second set of optical ports of the selector interface corresponding to the first number of optical ports, the selector being rotatable relative to the selector interface to facilitate the selection by optically aligning the first set of optical ports to the subset of the second set of optical ports of the selector interface, the selector being configured to be continuously relatively rotatable over multiple rotations, so as to selectively optically couple the first set of optical ports to a different subset of the second set of optical ports of the selector interface.

US Pat. No. 10,191,150

HIGH PRECISION RADAR TO TRACK AERIAL TARGETS

1. High Precision Radar To Track Aerial Targets, installed on the ground, in a container or in a vehicle, which determines the following parameters of the target, namely, azimuth angle (?a), elevation angle (?e), range, speed and flying direction and transmits them to another system said radar comprising an array of two collinear antennas with narrow beam in elevation wherein electromagnetic wave energy radiated from said antennas is spread over a 120-degrees beam width in azimuth installed on a platform and rotating around a vertical axis at a rotational frequency of, at least, 50 rpm, wherein the precise azimuth angle of the target (?a) is determined through correlation of the signal detected by the said antennas and a +1/?1 step function, wherein an adder is configured to sum the signals of target localizers gaining 3 dB wherein a correlator is configured to correlate an output lobe of the adder and the +1/?1 function, wherein a zero localizer is configured to search for a transition of said correlated signal through zero.

US Pat. No. 10,191,148

RADAR SYSTEM FOR VEHICLE AND METHOD FOR MEASURING AZIMUTH THEREIN

MANDO CORPORATION, Pyeon...

1. A system for blocking a reflection signal from a ground surface or from an elevation angle direction, the system comprising:two or more main reception antennas configured to receive echo signals reflected from a target, and generate a main reception signal based on the received echo signals;
a single side lobe suppression antenna configured to receive a side lobe suppression reception signal reflected from the ground surface or from the elevation angle direction; and
a radar configured to
compare a magnitude of the main reception signal with a magnitude of the received side lobe suppression reception signal, and
calculate an azimuth angle of the target by using the received main reception signal when the magnitude of the main reception signal is larger than the magnitude of the side lobe suppression reception signal,
wherein the azimuth angle is calculated by using the speed of light, a measured phase difference of the received echo signals, a distance between the two or more main reception antennas, and a frequency of the main reception signal, and
wherein
each main reception antenna of the two or more main reception antennas includes a phase delay unit installed in a center of a line of the each main reception antenna, and configured to adjust, by using the phase delay unit, a first phase and a second phase of the received echo signals with reference to the center of the line of the each main reception antenna, to have the same phase, in the radar, and
the side lobe suppression antenna includes a vertical connection part installed in a center of a line of the side lobe suppression antenna, and configured to adjust, by using the vertical connection part, a first phase and a second phase of the side lobe suppression reception signal with reference to the center of the line of the side lobe suppression antenna, to have 180 degree phase difference, in the radar.

US Pat. No. 10,191,143

METHOD AND APPARATUS FOR CALIBRATING AN IQ MODULATOR

Infineon Technologies AG,...

1. A method for calibrating an IQ modulator, the method comprising:a) setting one or more control values of the IQ modulator corresponding to a desired constellation point of a constellation diagram to generate an IQ modulating signal;
b) mixing the IQ modulating signal with a carrier signal to generate an IQ modulated transmit signal;
c) transmitting the IQ modulated transmit signal towards a predefined object at a predefined location;
d) receiving a reflection of the IQ modulated transmit signal from the predefined object;
e) mixing the received reflection of the IQ modulated transmit signal with the carrier signal to generate a down-converted receive signal;
f) comparing an amplitude and/or phase of the down-converted receive signal with the desired constellation point of the constellation diagram; and
g) adjusting the one or more control values of the IQ modulator until a deviation between the amplitude and/or phase of the down-converted receive signal and the desired constellation point falls below a predefined threshold.

US Pat. No. 10,191,138

RFID-BASED SYSTEMS FOR MONITORING LARGE AREAS

AVERY DENNISON RETAIL INF...

1. A system for locating RFID tags in an area, comprising:a platform;
an RFID reader head associated with the platform;
at least one support extending between the platform and an anchor position within an area, with a separate anchor position being associated with each support; and
at least one support adjustment device, with a separate support adjustment device being associated with each support, wherein each support adjustment device is operable to adjust the length of the associated support between the platform and the anchor position associated with said support, thereby varying the location of the RFID reader head in the area.

US Pat. No. 10,191,120

APPARATUS FOR DETECTING DEFECT OF ELECTRIC POWER SYSTEM

LSIS CO., LTD., Anyang-s...

1. An apparatus for detecting a defect of an electric power system, the apparatus comprising:a first state signal output mechanism configured to output a first state signal corresponding to a magnetic force generated at a periphery of a line;
a second state signal output mechanism configured to output a second state signal based on a magnitude of a line current and an increase ratio thereof;
a defect determination mechanism configured to determine whether the electric power system is defective based on the first state signal and the second state signal; and
an optical signal conversion mechanism disposed between the first state signal output mechanism and the defect determination mechanism and configured to convert the first state signal into an optical signal when the first state signal is output from the first state signal output mechanism.

US Pat. No. 10,191,097

SQUARE-WAVE-BASED IMPEDANCE ANALYSIS

TEXAS INSTRUMENTS INCORPO...

1. An impedance analyzer to analyze the impedance of a device under test (DUT) over a range of frequencies, the impedance analyzer comprising:a microcontroller to generate a first square wave signal at a first frequency;
parallel signal transmission paths between the microcontroller and the DUT, each parallel path to transmit one of the first square wave signal or a square wave signal based on the first square wave signal, the parallel paths comprising:
a first path comprising a first anti-aliasing filter for filtering the first square wave signal to remove frequencies higher than a first filter frequency, the first path to deliver the first square wave signal to the DUT; and
a second path comprising a clock synthesizer integrated circuit (IC), separate from the microcontroller, to generate a second square wave signal, based on the first square wave signal, at a second frequency, the second path further comprising a second anti-aliasing filter for filtering the second square wave signal to remove second frequencies higher than a second filter frequency, the second filter frequency being higher than the first filter frequency; and
a path selection switch controllable by the microcontroller to select one of the parallel paths.

US Pat. No. 10,191,086

POWER DETECTION CIRCUIT

Apple Inc., Cupertino, C...

1. An apparatus, comprising:an inverter coupled to a first power supply, wherein the inverter is configured to generate a signal dependent upon a second power supply; and
a latch configured to:
store a first value dependent upon a first voltage level of the second power supply and a first value of the signal; and
store a second value dependent upon a second voltage level of the second power supply and a second value of the signal, wherein the second value of the signal is different from the first value of the signal.

US Pat. No. 10,191,083

MAGNETIC SHIELDED PROBE CARD

1. A method of forming an integrated circuit die, comprising:providing a semiconductor wafer that includes more than one of said integrated circuit die;
testing said semiconductor wafer that includes said more than one of said integrated circuit die using a probe card; and
singulating the wafer to form said integrated circuit die;
said probe card comprising:
a mechanical support fixture having an inner aperture with a plurality of probes secured to said fixture that include probe tips that extend into said inner aperture for contacting probe pads on die of a wafer to be probed, and
at least one magnetic shield comprising a magnetic material that at least substantially surrounds a projected volume over an area that encloses said probe tips of said probes,
wherein said magnetic material has a relative magnetic permeability between 800 and 5,000.

US Pat. No. 10,191,053

METHODS FOR MEASURING AND REPORTING VASCULARITY IN A TISSUE SAMPLE

Flagship Biosciences, Inc...

1. A method for measuring and reporting vascularity in a biological tissue sample, comprising:acquiring at least one digital image of a stained tissue section, wherein the stained tissue section is stained in such a manner to allow identification of at least one vessel object and at least one tissue object;
detecting within the at least one digital image at least one vessel object, wherein the vessel object is selected from the group consisting of fully formed vessels and vessel fragments;
detecting at least one tissue object within the digital image;
calculating a vessel proximity score based on the detected vessel object and tissue object; and
digitally omitting from the vessel proximity score any detected vessels having a diameter or vessel area greater than a maximum vessel size.

US Pat. No. 10,191,047

SENSOR INTEGRATION IN LATERAL FLOW IMMUNOASSAYS AND ITS APPLICATIONS

Robert Bosch GmbH, Stutt...

1. A method comprising:determining a parameter of a sample in a lateral flow immunoassay device, and
determining a concentration of an analyte in the sample based on the determined parameter;
wherein:
the lateral immunoassay device comprises:
a) a solid support;
b) a sample portion for receiving the sample;
c) a conjugate portion comprising conjugate particulate material;
d) a diagnostic portion comprising a binder for the analyte in the sample;
e) an absorbent portion of absorbent material for providing capillary flow; and
f) at least one electrical sensor; and
the sample portion, conjugate portion, diagnostic portion, and absorbent portion are in capillary flow communication, whereby the sample flows across the binder in the diagnostic portion to provide contact between the sample and the binder;
wherein the at least one electrical sensor is connected to a processing unit that is configured to compute:
the parameter of the sample at the diagnostic portion using a signal provided by the at least one electrical sensor; and
the concentration of the analyte using (a) a signal generated from a binding of the binder and the analyte in the sample and (b) the parameter of the sample; and
wherein the at least one electrical sensor and the binder for the analyte are both placed on one side of the solid support, the at least one electrical sensor being located on a portion of the solid support different from the binder for the analyte.

US Pat. No. 10,191,020

FLAME IONIZATION DETECTION BURNER ASSEMBLIES FOR USE IN COMPRESSIBLE FLUID-BASED CHROMATOGRAPHY SYSTEMS

WATERS TECHNOLOGIES CORPO...

1. A burner assembly of a flame-based detector comprising:(1) a burner comprising a burner body having a fluid inlet for receiving combustion gases and a fluid outlet for delivering combustion gases to a flame position, the burner body defining a flow path extending from the fluid inlet to the flame position and having a longitudinal axis;
and
(2) a restrictor comprising a hollow body comprising a first end for receiving at least a portion of a mobile phase flow stream from a chromatography system and a second end for delivering the at least a portion of the mobile phase flow stream as a decompressed mobile phase flow stream to the burner; and
wherein during flame-based detection of one or more constituents of the at least a portion of the mobile phase flow stream:
at least the second end of the restrictor is inserted into the burner; and
the second end of the restrictor having a tip that is angled to deliver the decompressed mobile phase flow stream to the burner body flow path at an angle substantially non-parallel to the longitudinal axis of the burner.

US Pat. No. 10,191,018

DUAL ONLINE LIQUID CHROMATOGRAPHY DEVICE AND CONTROL METHOD THEREOF

KOREA UNIVERSITY RESEARCH...

1. A dual online liquid chromatography device comprising:a first pump for injecting a first solvent or a mixed solution containing the first solvent and a second solvent;
a second pump for injecting the first solvent or the mixed solution containing the first solvent and the second solvent;
a sample intake valve connected to the first pump and a sample injector for injecting a sample;
a column selection valve connected to the second pump and the sample intake valve; and
a dual column valve having one side connected to the column selection valve and the other side connected to a first column and a second column, and comprising a plurality of ports, wherein the dual column valve further comprises:
a first column port connected to the first column;
a solid phase extraction column selection port and a solid phase extraction column channel port constituting opposite ends of a first solid phase extraction column (SPE1);
a solid phase extraction column inlet port connected to one side of the column selection valve and selectively connected to the solid phase extraction column selection port or the solid phase extraction column channel port;
a first outlet port adjacent to the solid phase extraction column channel port;
a second outlet port adjacent to the first outlet port;
a second solid phase extraction column selection port and a second solid phase extraction column channel port constituting opposite ends of a second solid phase extraction column (SPE2);
a second solid phase extraction column inlet port connected to the other side of the column selection valve and selectively connected to the second solid phase extraction column selection port and the second solid phase extraction column channel port; and
a second column port connected to the second column.

US Pat. No. 10,191,017

DYNAMIC CHARACTERISTIC CALCULATION APPARATUS AND ITS METHOD FOR MACHINE TOOL

JTEKT CORPORATION, Osaka...

1. An apparatus calculating a dynamic characteristic of a machine tool that executes an interrupted machining of a workpiece by moving a rotational tool having one or plural tool tips relative to the workpiece comprising:a vibration detector configured to detect a vibration property of said rotational tool mounted on the machine tool when said rotational tool is excited to vibrate by a target member prior to the interrupted machining of the workpiece; and
a processor configured to:
calculate a natural frequency of said rotational tool mounted on the machine tool on a basis of said detected vibration property,
replace a pre-excitation natural frequency stored in a memory with said calculated natural frequency, said pre-excitation frequency being determined based on constructional information of said machine tool before said rotation tool is excited to vibrate by the target member, and
generate a command for said machine tool to change a rotational velocity of said rotational tool in said interrupted machining based upon said calculated natural frequency, wherein
said machine tool includes a driving device configured to move said rotational tool relative to said workpiece; and
said rotational tool is excited to vibrate, prior to the interrupted machining of the workpiece, by contacting said rotational tool with said target member mounted on said machine tool without use of man power by driving said driving device without said rotational tool being rotated, or
said rotational tool is excited to vibrate prior to the interrupted machining of the workpiece by contacting said rotational tool with said target member by driving said driving device while said rotational tool is rotated in a counter rotational direction against a rotational direction of the tool when machining.

US Pat. No. 10,191,016

METHOD AND SYSTEM FOR PASSIVE DETECTION, LOCALIZATION AND CHARACTERIZATION OF MECHANICAL WAVE SOURCES USING ULTRASONIC GUIDED WAVES

1. A method of estimating and storing for subsequent, non-contemporaneous use, one or more spatial channel impulse responses corresponding to one or more spatial points of interest on a structure when the structure is in a known state comprising:collecting first data at one or more spatial points of interest on the structure using a movable transducer, used only in this step, wherein collecting first data includes individually exciting at least one fixed transducer on the structure with a known excitation function and recording measurements at the one or more spatial points of interest with the movable transducer;
computing one or more spatial channel impulse response estimates for each of the one or more spatial points of interest based on the collected first data; and
storing said spatial channel impulse response estimates for subsequent, non-contemporaneous use after the structure has transitioned to an unknown state.

US Pat. No. 10,191,015

OBJECT INFORMATION ACQUIRING APPARATUS AND LASER APPARATUS

CANON KABUSHIKI KAISHA, ...

1. An object information acquiring apparatus comprising:irradiation means configured to irradiate an object with a laser beam;
a shutter unit having a shutter disposed on a light path of the laser beam from the irradiation means to the object, configured to restrict an output of the laser beam from the irradiation means to the object;
control means configured to control an irradiation of the laser beam by the irradiation means and an operation of the shutter unit;
a probe configured to receive an acoustic wave generated from the object irradiated with the laser beam; and
construction means configured to generate, using the acoustic wave, characteristic information relating to the object,
wherein the irradiation means is configured to generate the laser beam at a plurality of wavelengths and to irradiate the laser beam with a wavelength selected from among the plurality of wavelengths, and
wherein the control means performs, while the wavelength of the laser beam is switched, a control of closing the shutter and a control of stopping or suppressing the generation of the laser beam by the irradiation means.

US Pat. No. 10,191,014

SYSTEM AND METHOD FOR NONDESTRUCTIVE EVALUATION OF A TEST OBJECT

The Boeing Company, Chic...

1. A system for nondestructive evaluation of a test object, the system comprising:a platform;
an electromagnetic acoustic transducer (EMAT) mounted on the platform and positioned to generate a magnetic field in the test object to create acoustic vibrations that travel along a surface of the test object;
an infrared detector mounted on the platform and positioned to record thermal images of a plurality of test areas on the surface of the test object to detect flaws in the surface of the test object within the plurality of test areas as at least one of the platform and the test object move relative to each other;
a velocity interferometer system for any reflector (VISAR) mounted on the platform and oriented to detect a presence of one of the vibrations in the test object caused by the EMAT in one of the plurality of test areas aligned with the infrared detector; and
a controller connected to the EMAT, the VISAR, and the infrared detector, wherein the controller actuates the EMAT to create the vibrations in the test object the VISCAR, and the infrared detector, wherein the connection synchronizes the creation of the vibrations by the EMAT with the recording of the thermal images of the plurality of test areas by the infrared detector, wherein the controller receives signals from the VISAR indicating the presence of the vibrations in the one of the plurality of test areas aligned with the infrared detector, and the infrared detector is triggered to record each of the thermal images of the one of the plurality of test areas aligned with the infrared detector in response to the VISCAR detecting the one of the vibrations in the one of the plurality of test areas, wherein the controller receives a signal from the infrared detector indicative of the thermal images of the surface of the test object, and the controller records locations of the flaws appearing on the thermal images of the plurality of test areas, wherein the controller receives and records as at least one of the platform and the test object move relative to each other.

US Pat. No. 10,191,011

RUGGEDIZED APPARATUS FOR ANALYSIS OF NUCLEIC ACID AND PROTEINS

NetBio, Inc., Waltham, M...

1. An apparatus for processing a sample of biomolecular analyte, the apparatus comprising:a holder for supporting a test module, said test module comprising a transparent plate comprising one or more channels, at least one channel in fluid communication with the sample;
an electrophoresis device connected to the holder and for providing energy to the test module;
a light source for emitting a light beam that excites fluorescence in the sample of biomolecular analyte;
a light detector; and
a plurality of optical devices rigidly mounted to a base plate, the base plate being supported by a frame including at least one damping device to reduce the transmission of vibrations generated below the frame to base plate.

US Pat. No. 10,191,010

TRANSFER MEMBRANE RETAINING JIG AND SEPARATION-TRANSFER DEVICE

SHARP LIFE SCIENCE CORPOR...

1. A transfer-membrane retaining jig for retaining a transfer membrane in a separation-transfer device that separates analyte by way of electrophoresis, dispenses the analyte thus separated from a dispensing part, and transfers the analyte thus separated to the transfer membrane by causing the transfer membrane to abut the dispensing part and move along a predetermined direction, the transfer-membrane retaining jig comprising:a fixing part that fixes at least one end of the transfer membrane in the predetermined direction,
wherein the fixing part includes: an elastic body that abuts the transfer membrane from an opposite side to the dispensing part; and
a pressing member that presses the transfer membrane against the elastic body.

US Pat. No. 10,191,009

ELECTROCHEMICAL DETERMINATION OF HEAVY METALS

UNIVERSITY OF LOUISVILLE ...

1. A method of analyzing dissolved metals in a sample solution, the sample solution being contained in a cell having a fixed and known volume, the method comprising:initiating a first reduction reaction in the sample solution which contains two or more dissolved metals by applying a first deposition potential for an interval of time representing a first deposition pulse, wherein the first reduction reaction results in non-exhaustive deposition of one or more of the dissolved metals upon an electrode, wherein the one or more dissolved metals deposited during the first reduction reaction comprise one or more interferents;
initiating a first oxidation reaction by applying a stripping potential for an interval of time, representing a first stripping pulse, that is sufficient to strip the one or more interferents from the electrode that were deposited during the first reduction reaction, and measuring electrical current generated during the first stripping pulse;
after the first oxidation reaction, initiating a second reduction reaction by applying a deposition potential for an interval of time, representing a second deposition pulse, that results in exhaustive deposition of the one or more interferents upon the electrode;
initiating a second oxidation reaction by applying a stripping potential for an interval of time, representing a second stripping pulse, that is sufficient to strip all the one or more interferents from the electrode that were deposited during the second reduction reaction, and measuring electrical current generated during the second stripping pulse;
after the second oxidation reaction, initiating a third reduction reaction in the sample solution by applying a second deposition potential different from the first deposition potential for an interval of time representing a third deposition pulse, wherein the third reduction reaction results in non-exhaustive deposition of the one or more dissolved metals comprising the one or more interferents and at least one analyte upon the electrode;
initiating a third oxidation reaction by applying a stripping potential for an interval of time, representing a third stripping pulse, that is sufficient to strip the one or more interferents and the at least one analyte from the electrode that were deposited during the third reduction reaction, and measuring electrical current generated during the third stripping pulse;
after the third oxidation reaction, initiating a fourth reduction reaction by applying a deposition potential different from the first deposition potential, for an interval of time that results in exhaustive deposition of the one or more interferents and the at least one analyte upon the electrode;
initiating a fourth oxidation reaction by applying a stripping potential for an interval of time, representing a fourth stripping pulse, that is sufficient to strip the one or more interferents and the at least one analyte from the electrode that were deposited during the fourth reduction reaction, and measuring electrical current generated during the fourth stripping pulse; and
calculating a concentration of the at least one analyte in the sample solution based on a quantitative difference between the absolute charge associated with stripping the one or more interferents from the electrode, subtracted from the absolute charge associated with stripping the one or more interferents and the at least one analyte from the electrode.

US Pat. No. 10,191,008

GAS SENSOR WITH SOLID ELECTROLYTE HAVING WATER VAPOR DIFFUSION BARRIER COATING

Life Safety Distribution ...

1. A gas sensor comprising:(a) a housing;
(b) a ceramic substrate having a capillary extending through the ceramic substrate, and at least one of a sensing electrode, a reference electrode, or a counter electrode disposed on a first surface;
(c) solid electrolyte in contact with the at least one of the sensing electrode, the reference electrode, or the counter electrode;
(d) a barrier coating disposed over the solid elect wherein the barrier coating encapsulates the at least one of the sensing electrode, the reference electrode, or the counter electrode and the solid electrolyte, wherein the barrier coating comprises a layer of silicone and a layer of parylene, wherein the layer of parylene is on the outer surface of the layer of silicone, wherein the layer of silicone directly covers the solid electrolyte.

US Pat. No. 10,191,007

SULFUR OXIDES DETECTION SYSTEM

TOYOTA JIDOSHA KABUSHIKI ...

1. A sulfur oxides detection system comprising:a device part arranged in an exhaust passage of an internal combustion engine and comprising a first electrochemical cell having a first solid electrolyte layer having oxide ion conductivity, a first electrode arranged on one surface of the first solid electrolyte layer so as to be exposed to gas to be measured, and a second electrode arranged on an other surface of the first solid electrolyte layer so as to be exposed to the atmospheric air, and a diffusion regulating layer to regulate diffusion of the gas to be measured;
a power supply to supply voltage across the first electrode and the second electrode;
a detector to detect a first current correlation parameter correlated with a current flowing between the first electrode and the second electrode; and
an electronic control part to control the power supply and to acquire the first current correlation parameter from the detector, wherein
the electronic control part is to control the power supply so that a first voltage which is a decomposition start voltage of water and sulfur oxides or greater is to be applied across the first electrode and the second electrode and to calculate a concentration of sulfur oxides in the gas to be measured based on the first current correlation parameter detected by the detector if the first voltage is applied across the first electrode and the second electrode and
the electronic control part is to judge whether a concentration of water in the gas to be measured is stable and does not calculate the concentration of sulfur oxides in the gas to be measured if the electronic control part judges that the concentration of water in the gas to be measured is not stable.

US Pat. No. 10,191,006

HUMIDITY SENSOR

ABLIC INC., (JP)

1. A humidity sensor, comprising:a semiconductor substrate;
an insulating film formed on a surface of the semiconductor substrate;
a plurality of first electrodes and a plurality of second electrodes, both formed on the insulating film and arranged so that each of the plurality of first electrodes is adjacent to one of the plurality of second electrodes in each of four directions of up, down, right, and left when viewed in plan view, while each of the plurality of second electrodes is adjacent to one of the plurality of first electrodes in each of four directions of up, down, right, and left when viewed in plan view, except in a perimeter of the arrangement;
a first metal wiring completely embedded in the insulating film and electrically connecting, through a via, one of the plurality of first electrodes to another one of the plurality of first electrodes;
a second metal wiring completely embedded in the insulating film and electrically connecting, through a via, one of the plurality of second electrodes to another one of the plurality of second electrodes; and
a humidity sensitive film formed on the plurality of first electrodes and the plurality of second electrodes.

US Pat. No. 10,191,005

ULTRA-COMPACT, PASSIVE, VARACTOR-BASED WIRELESS SENSOR USING QUANTUM CAPACITANCE EFFECT IN GRAPHENE

Regents of the University...

1. A sensor comprising:a graphene quantum capacitance varactor comprising:
an insulator layer;
a dielectric layer;
a gate electrode between the insulator layer and the dielectric layer;
a graphene layer on the dielectric layer, wherein capacitance of the graphene layer changes in response to a sensed electrical charge collected proximate to the graphene layer upon exposure to a sample, and wherein the graphene layer comprises an exposed surface opposite the dielectric layer; and
at least one contact electrode on the graphene layer and making electrical contact with the graphene layer.

US Pat. No. 10,191,004

MICROCANTILEVER BASED SELECTIVE VOLATILE ORGANIC COMPOUND (VOC) SENSORS AND METHODS

University of South Carol...

1. A system for identifying a volatile organic compound; the system comprising:a fluid flow path configured for carrying a volatile organic compound;
a power source configured for supplying a driving voltage; and
a triangular microcantilever held in electrical communication with the power source, the microcantilever comprising a first arm extending from a base, a second arm extending from the base, and a tip at a junction of the first arm and the second arm, the first arm having a cross section that decreases in size with a first regular taper, the first regular taper beginning at the base and extending to the tip, the second arm having a cross section that decreases in size with a second regular taper, the second regular taper beginning at the base and extending to the tip, the tip being in the fluid flow path, wherein upon contact between the microcantilever and the volatile organic compound in conjunction with application of the driving voltage to the microcantilever, the first arm exhibits a first electrical resistance, the second arm exhibits a second electrical resistance, and the tip exhibits a third electrical resistance, the third electrical resistance differing from the first and second electrical resistances.

US Pat. No. 10,191,003

METHODS AND APPARATUS FOR A MOISTURE DETECTOR

Helvetia Wireless LLC, S...

1. A sensor for detecting a spread of a liquid, the sensor comprising:a substrate;
a first conductor, the first conductor having a first sheet resistance;
a second conductor, the second conductor having a second sheet resistance; and
a processing circuit; wherein:
a magnitude of the first sheet resistance is greater than a magnitude of the second sheet resistance;
a portion of the first conductor is positioned a first distance away from a portion of the second conductor;
a first portion of the liquid is positioned relative to a first end portion of the first conductor in accordance with a first voltage applied between the first end portion of the first conductor and a first end portion of the second conductor;
a second portion of the liquid is positioned relative to a second end portion of the first conductor in accordance with a second voltage applied between the second end portion of the first conductor and the first end portion of the second conductor;
the first portion of the liquid is positioned a second distance away from the second portion of the liquid along the first conductor;
the second distance relates to the spread of the liquid with respect to the first conductor;
the processing circuit determines a third distance from the first end portion of the first conductor to the first portion of the liquid in accordance with the first voltage;
the processing circuit determines a fourth distance from the second end portion of the first conductor to the second portion of the liquid in accordance with the second voltage; and
the processing circuit relates a position of at least one of the third distance from the first end portion of the first conductor and the fourth distance from the second end portion of the first conductor to a position on the substrate.

US Pat. No. 10,191,001

CONVEYOR-BELT SYSTEM FOR MEASURING CONDITIONS THAT VARY THE RESONANT FREQUENCY OF A RESONANT CIRCUIT

Laitram, L.L.C., Harahan...

1. A conveyor belt comprising:an endless belt body;
a plurality of resonant circuits disposed at sensor positions in the endless belt body, each of the resonant circuits including:
an inductor; and
a capacitor connected to the inductor to form the resonant circuit with a resonant frequency determined by the inductance of the inductor and the capacitance of the capacitor;
a plurality of capacitor plates, wherein each of the resonant circuits is connected to one or more capacitor plates to capacitively couple the resonant circuit through one or more stationary capacitor plates external to the conveyor belt;
wherein at least one of the inductance of the inductor and the capacitance of the capacitor is varied by a varying condition affecting the conveyor belt.