US Pat. No. 10,141,674

TAMPER RESISTANT MECHANISM FOR ELECTRICAL WIRING DEVICES

Hubbell Incorporated, Sh...

1. An electrical receptacle comprising:a base having a first connector member and a second connector member, each capable of supplying electrical power;
a cover having a first horizontal line phase slot aligned with the first connector member and a second horizontal line phase slot aligned with the second connector member; and
a first tamper resistant cartridge disposed between the first and second connector members and the first and second line phase slots, the first tamper resistant cartridge including:
a first shutter assembly including:
a first shutter aligned with the first horizontal line phase prong slot; and
a first slider aligned with the second connector member that normally blocks access to the second connector member;
a second shutter assembly including:
a second shutter aligned with the second horizontal line phase prong slot; and
a second slider aligned with the first connector member that normally blocks access to the first connector member;
wherein rotation of the first shutter causes the first slider to move to a position that enables access to the second connector member, and wherein rotation of the second shutter causes the second slider to move to a position that enables access to the first connector member.

US Pat. No. 10,141,673

DETECTION OF A PLUG COUPLED TO A CONNECTOR HOUSING

Hewlett Packard Enterpris...

1. An apparatus comprising:a plug coupleable to a connector housing on a computing device, wherein the computing device includes:
a first airflow path based on the plug being coupled to the connector housing that prevents airflow through the connector housing; and
a second airflow path based on an absence of the plug being coupled to the connector housing such that air flows through the connector housing;
an electrical contact supported by the plug, the electrical contact interfaceable with a connector pin in the connector housing, wherein the computing device:
detects whether the plug is coupled to the connector housing based on whether the electrical contact is interfaced with the connector pin; and
controls an operating state of a network switch that corresponds to the connector housing based on whether the plug is coupled to the connector housing, including causing the network switch to power down in response to detecting that the plug is not coupled to the connector housing.

US Pat. No. 10,141,670

SUBSTRATE CONNECTOR INCLUDING A SPRING PIN ASSEMBLY FOR ELECTROSTATIC CHUCKS

LAM RESEARCH CORPORATION,...

1. A substrate connector to provide a connection to a substrate during substrate processing, comprising:a spring pin assembly defining a first contact and including a first groove, wherein the first groove extends inward relative to the first contact;
a retention spring clip including a body arranged in the first groove and projections extending from the body; and
a second contact including a body defining a cavity, wherein the cavity defines a second groove in opposing inner side walls of the cavity and the second groove extends outward in a direction opposite the first groove,
wherein the second contact is arranged around the first contact of the spring pin assembly, and
wherein the projections of the retention spring clip extend outward from the first groove into the second groove in the second contact.

US Pat. No. 10,141,668

DETACHABLE FLEX-TO-FLEX ELECTRICAL CONNECTION

Palo Alto Research Center...

1. A detachable electrical connection assembly comprising:a conductive material;
an adhesive material consisting of an adhesive composition configured to permit non-permanent attachment, detachment and re-attachment of the adhesive material, wherein at least a portion of the conductive material is positioned between the adhesive material having the adhesive composition which permits non-permanent attachment, detachment, and re-attachment of the adhesive material;
the conductive material and the adhesive material being located on a first surface of a first substrate;
conductive ink drops selectively located on portions of the conductive material of the first substrate; and
a second substrate having at least some conductive material on a first surface corresponding to at least some of the conductive ink dots, wherein the second substrate is positioned wherein at least some of the conductive material on the second substrate are in contact with at least some of the conductive ink dots.

US Pat. No. 10,141,665

MAGNETIC COUPLING SYSTEMS

1. A set of magnetic jumper cables, comprising:two lengths of elongate, insulated, electrically-isolated electric conductors; and
magnetic couplers configured in electrical connection with at least one end of each of the two lengths of elongate, insulated, electric conductors,
the magnetic couplers comprising:
insulative material, the insulative material defining indentations on indented sides of individual magnetic couplers, and
magnetic elements positioned within the insulative material such that the magnetic elements are in electrical connection with respective elongate, insulated, electrically-isolated electric conductors and the magnetic elements are exposed at the indentations.

US Pat. No. 10,141,664

DISTRIBUTION BLOCK AND DIN RAIL RELEASE MECHANISM

Hubbell Incorporated, Sh...

1. An electrical distribution block comprising:a base having a lower portion, an upper portion, a first side portion extending from the top portion, and a second side portion extending from the top portion opposite the first side portion, wherein the first side portion includes a first base mating feature and the second side portion includes a second base mating feature, and wherein the bottom portion includes a channel configured to receive a DIN rail;
a first sidewall removably connected to the first base mating feature;
a second sidewall removably connected to the second base mating feature; and
a conductor block connected to the upper portion of the base, wherein the conductor block includes a primary conductor receiving portion and a secondary conductor receiving portion.

US Pat. No. 10,141,659

EXOTHERMIC AND MECHANICAL ELECTRICAL CONNECTOR

Hubbell Incorporated, Sh...

1. An electrical connector comprising:an electrically conductive connector having a mechanical connector for removably receiving a conductor, the mechanical connector including a threaded portion, and a parallel groove clamp comprising a head, a moveable jaw acting as a translatable clamping member, a fastener having the threaded portion, and a nut connected to the fastener;
an arm extending from the electrically conductive connector;
a component connected to the arm at an interface, wherein the interface comprises an exothermic weld, and wherein the arm is integrally formed with the head and includes a bottom portion connected to the component.

US Pat. No. 10,141,657

RADAR DEVICE

Panasonic Corporation, O...

1. A radar device comprising:radar transmission circuitry which, in operation, transmits a radar signal through a transmitting array antenna at a predetermined transmission period; and
radar reception circuitry which, in operation, receives a reflected wave signal which is the radar signal reflected by an object through a receiving array antenna, wherein
the transmitting array antenna and the receiving array antenna each include a plurality of subarray elements,
the subarray elements are linearly arranged in a first direction in each of the transmitting array antenna and the receiving array antenna,
each subarray element includes a plurality of antenna elements,
a dimension of each subarray element in the first direction is larger than a predetermined antenna element spacing, and
an absolute value of a difference between a subarray element spacing of the transmitting array antenna and a subarray element spacing of the receiving array antenna is equal to the predetermined antenna element spacing.

US Pat. No. 10,141,656

STRUCTURAL ANTENNA ARRAY AND METHOD FOR MAKING THE SAME

The Boeing Company, Chic...

1. A structural antenna array comprising:a core comprising intersecting wall sections, wherein said core further comprises antenna elements formed on a first surface of said wall sections, and feed elements formed on a second surface of said wall sections;
a distribution substrate layer coupled to said core and in electrical communication with said antenna elements and said feed elements;
a first skin coupled to said core opposite said distribution substrate layer; and
a second skin coupled to said distribution substrate layer opposite said first skin, wherein said first skin and said second skin each comprises:
a first non-conductive substrate layer;
a dielectric substrate layer coupled to said first non-conductive substrate layer; and
a second non-conductive substrate layer coupled to said dielectric substrate layer opposite said first non-conductive substrate layer.

US Pat. No. 10,141,654

TRACKING ANTENNA SYSTEM ADAPTABLE FOR USE IN DISCRETE RADIO FREQUENCY SPECTRUMS

Sea Tel, Inc., Concord, ...

1. A tracking antenna system comprising:a reflector configured to receive a plurality of radio waves that include first radio waves within a first range of radio frequencies and second radio waves within a second range of frequencies;
a pedestal that supports the reflector, wherein the pedestal includes one or more motion control units for rotating the reflector about at least one axis;
a damping assembly that is coupled to the pedestal, wherein the damping assembly damps vibrations of the pedestal;
a first feed that is coupled to the reflector, wherein the first feed is configured to receive the first radio waves and send them to a first RF module that is coupled to the reflector, wherein the first RF module is configured to convert the first radio waves to first electronic signals; and
a module mount that is coupled to the reflector and that is configured for interchangeable mounting of the first RF module and a second RF module, wherein the module mount includes a protrusion that extends from the reflector;
wherein the first RF module is removably coupled to the reflector by the module mount and supported by the protrusion of the module mount.

US Pat. No. 10,141,652

ANTENNA APPARATUS AND DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. An antenna apparatus comprisingan antenna radiator comprising a top edge, a bottom edge, and a first side edge, wherein the bottom edge comprises an end;
an antenna cable trough disposed on the antenna radiator and extending from the bottom edge to near the top edge;
a feedpoint disposed on the antenna radiator at the end and near the first side edge; and
a first protruding metal strip inserted in the antenna cable trough and separated from the antenna radiator,
wherein the antenna apparatus is configured to be disposed within a printed circuit board (PCB) metal layer.

US Pat. No. 10,141,650

ANTENNA MODULE AND ELECTRONIC DEVICE

MURATA MANUFACTURING CO.,...

1. An antenna module comprising:a multilayer body including a plurality of insulator layers laminated on one another in a laminating direction;
a surface-mounted device mounted on a top surface of the multilayer body;
an antenna coil including a plurality of coil conductors and a plurality of interlayer connection conductors that define a helical or substantially helical shape; and
at least one wiring conductor that is provided on at least one of the plurality of insulator layers and that is electrically connected with the surface-mounted device or the antenna coil; wherein
a coil winding axis of the antenna coil extends in a direction in which surfaces of the plurality of insulator layers extend;
the plurality of coil conductors of the antenna coil are provided on more than one of the plurality of insulator layers;
each of the plurality of interlayer connection conductors electrically connects end portions of corresponding ones of the plurality of coil conductors to each other; and
the at least one wiring conductor is located in a space defined by a structure of the antenna coil;
the at least one wiring conductor is disposed in the laminating direction of the insulator layers.

US Pat. No. 10,141,648

HIGH FREQUENCY SIMULTANEOUS METRICS ANTENNA (HF-SIMANT)

The United States of Amer...

17. An antenna comprising:a loop made of conductive material;
two baluns connected to, and intersecting, opposing sides of the loop, wherein each balun has an output;
a 180° hybrid coupler having two input ports, a sum output port, and a delta output port, wherein the two input ports are connected to the outputs of the baluns;
a first low noise amplifier (LNA) connected to the sum output port;
a second LNA connected to the delta output port; and
first and second receivers connected to the first and second LNAs respectively,
wherein the antenna sets a system noise level below external high frequency noise by utilizing a computation for a system noise figure that ignores bias tees and transient protection devices, wherein the computation for the system noise figure (NF) is:

wherein i=? or ? corresponding to the noise figure of a dipole or loop mode, respectively, Ti is a system noise temperature, and T0 is a standard noise temperature.

US Pat. No. 10,141,647

SIX DEGREES OF FREEDOM GROUND EXPLOITING VECTOR SENSOR ANTENNA (6GE ANTENNA)

The United States of Amer...

1. An antenna comprising:a ground plane having a center;
six receive ports mounted to the ground plane in a circular configuration around the center and separated from each other by approximately 60 degrees;
three conductive half-loops, each respectively disposed in one of three mutually orthogonal planes, wherein each half-loop has two ends and wherein each end is respectively connected to one of the six receive ports; and
three 180° hybrids, each 180° hybrid having two input ports, a delta output port, and a sum output port, wherein the two input ports of each 180° hybrid are respectively connected to the two receive ports of one of the half-loops.

US Pat. No. 10,141,645

MULTIBAND ANTENNA

RF INDUSTRIES PTY LTD, S...

1. An antenna comprising:at least first and second radiating elements disposed in a substantially collinear configuration on a surface of an elongated dielectric substrate, the first radiating element comprising a feed point;
a first inter-element phasing section disposed on the surface of the elongated dielectric substrate, and conductively coupled to the first and second radiating elements, the first inter-element phasing section having a meander line configuration adapted such that the first and second radiating elements radiate electro-magnetic radiation substantially in-phase over a first range of frequencies;
at least third and fourth radiating elements disposed in a substantially collinear configuration on the surface of the elongated dielectric substrate, wherein the third radiating element is electromagnetically coupled in parasitic relation to the first radiating element; and
a second inter-element phasing section disposed on the surface of the elongated dielectric substrate and conductively coupled to the third and fourth radiating elements, the second inter-element phasing section having a meander line configuration adapted such that the third and fourth radiating elements radiate electromagnetic radiation substantially in-phase over a second range of frequencies which is different from the first range of frequencies.

US Pat. No. 10,141,643

HIGH-FREQUENCY FILTER INCLUDING MATCHING CIRCUIT

SKYWORKS FILTER SOLUTIONS...

1. A high-frequency filter comprising:a first input to receive a first signal;
a first filter;
a second filter;
a first matching circuit connected to an input of the first filter and to an input of the second filter, the first signal being provided to one of the input of the first filter and the input of the second filter via the first matching circuit, the first matching circuit including a first resonator connected in series between the first input and the input of only one of the first filter and the second filter;
a second input to receive a second signal;
a first reception filter; and
a second reception filter, the first filter being a first transmission filter, and the second filter being a second transmission filter, the first signal being a transmission signal, and the second signal being a reception signal that is provided to the first reception filter and to the second reception filter.

US Pat. No. 10,141,640

ISOLATION OF POLARIZATIONS IN MULTI-POLARIZED SCANNING PHASED ARRAY ANTENNAS

John Howard, Upper Mount...

1. A multi-polarized phased array antenna, which comprises:an element, the element being directly connected to a first polarization signal at a first angle, a second polarization signal at a second angle, the first polarization signal at a third angle, and the second polarization signal at a fourth angle, the first polarization signal comprising a first polarization, the second polarization signal comprising a second polarization, the first polarization being different from the second polarization;
a first feed line directly connecting the first polarization signal to the element, the first feed line being associated with the first polarization;
a second feed line directly connecting the second polarization signal to the element, the second feed line being associated with the second polarization;
a first phase shifter operatively coupled in the first feed line; and
a second phase shifter operatively coupled in the second feed line, one of the first polarization signal and the second polarization signal being cancelled at a feed point in at least one of the first feed line and the second feed line by operation of at least three of the first phase shifter, second phase shifter, first angle, second angle, third angle, and fourth angle, the array antenna being configured to perform elevation scanning by applying a phase shift in the first feed line,
at least one of the first phase shifter and the second phase shifter comprising at least one of a digital phase shifter and analog phase shifter, the analog phase shifter comprising a length of conductor in addition to that required to couple at least one of (1) the first feed line across the first phase shifter and (2) the second feed line across the second phase shifter using a straight conductor, the length of conductor providing a phase shift, the first phase shifter providing a first 180° phase shift between the first and third angles, the second phase shifter providing a second 180° phase shift between the second and fourth angles.

US Pat. No. 10,141,639

ANTENNA

Tyco Electronics Japan G....

1. An antenna, comprising:an electrical cable;
an antenna body including an element part and a ground part integrally formed from a metal plate, the element part having an electric wire connecting part electrically connected with the electrical cable; and
a resin antenna holder having an antenna holding part connected to the antenna body and a cable holding part holding the electrical cable in a direction different from a direction in which the electrical cable extends from the electric wire connecting part, the antenna holding part having a plurality of staking bosses and a constriction smaller in width than other parts of the antenna holding part, the cable holding part having a holding floor, a holding wall standing from a first end in the width direction of the holding floor, and a plurality of first holding claws, the antenna holder preventing pull forces and vibration occurring on the electrical cable from being transmitted to the electric wire connecting part.

US Pat. No. 10,141,636

VOLUMETRIC SCAN AUTOMOTIVE RADAR WITH END-FIRE ANTENNA ON PARTIALLY LAMINATED MULTI-LAYER PCB

16. A vehicular radar system comprising:a first printed circuit board (PCB) having a chip connection end, a transmission end, a top, and a bottom;
a plurality of end-fire antennas positioned on the first PCB each having:
a ground structure positioned adjacent to the chip connection end of the first PCB on the bottom of the first PCB,
a chip connection lead positioned adjacent to the chip connection end of the first PCB and electrically coupled to the RFIC,
a balun positioned adjacent to the chip connection lead and configured to convert an unbalanced signal to a balanced signal or to convert a balanced signal to an unbalanced signal,
a wave section having a first wave section and a second wave section separated by a space and configured to transmit a wireless radar signal, and
a tapered section positioned between the balun and the wave section and tapered towards the balun from the wave section;
a second PCB coupled to the top or the bottom of the first PCB, having a greater rigidity than the first PCB, and positioned between the balun of each of the plurality of end-fire antennas and the chip connection end of the first PCB; and
a radio frequency integrated circuit (RFIC) coupled to the plurality of end-fire antennas and configured to control the plurality of end-fire antennas.

US Pat. No. 10,141,635

SYSTEMS, APPARATUS, AND METHODS TO OPTIMIZE ANTENNA PERFORMANCE

ANTWAVE TECHNOLOGY LIMITE...

1. A modified dipole antenna comprising:a first arm having a surface layer made of a metal and an inner layer made of a non-metal, wherein a feed of a radio frequency signal cable is attached to the surface layer of the first arm; and
a second arm having a surface layer made of a metal and an inner layer made of a non-metal, wherein the radio frequency signal cable is passed through the inner layer of the second arm and ground is attached to the surface layer of the second arm,
wherein length of the first arm is determined from a first dielectric constant of a first dielectric material and length of the second arm is determined from a second dielectric constant of a second dielectric material;
wherein the first arm and the second arm is bent in a spiral shape forming different radii of the first arm and the second arm and wherein the radii of the first arm and the second arm are dependent on resonance frequencies of the wireless transceiver.

US Pat. No. 10,141,632

WIRELESS ELECTRONIC DEVICES WITH METAL PERIMETER PORTIONS INCLUDING A PLURALITY OF ANTENNAS

SONY MOBILE COMMUNICATION...

1. A wireless electronic device, comprising:a ground plane;
a first metal band extending along a perimeter around and spaced apart from the ground plane, the first metal band comprising a first radiating antenna element;
a second metal band extending along the perimeter opposite the first metal band, the second metal band comprising a second radiating antenna element;
a first input connector port on the perimeter galvanically insulating a first end of the first metal band from a first end of the second metal band, the first input connector port comprising a first insulator that galvanically insulates the first end of the first metal band from the first end of the second metal band, and the first input connector port being configured to receive a first mating connector from an exterior of the wireless electronic device and to provide an electrical connection to the first mating connector; and
a second input connector port on the perimeter galvanically insulating a second end of the first metal band and a second end of the second metal band, the second input connector port comprising a second insulator that galvanically insulates the second end of the first metal band from the second end of the second metal band, and the second input connector port being configured to receive a second mating connector from the exterior of the wireless electronic device and to provide an electrical connection to the second mating connector.

US Pat. No. 10,141,630

ANTENNA INCORPORATED INTO DEVICE HINGE AND METHOD

Intel Corporation, Santa...

1. An antenna for a device having a hinge connecting first and second housing portions, comprising:a first antenna element mounted on the hinge in a position to expose the first antenna element when the first and second housing portions are in a first position;
a second antenna element mounted on the hinge in a position to expose the second antenna element when the first and second housing portions are in a second position; and
an antenna switch in the hinge and operable to connect the first antenna element to at least one of a transmitting circuit and a receiving circuit of the device at a first hinge position, the antenna switch being operable to connect the second antenna element to at least one of the transmitting circuit and the receiving circuit at a second hinge position, the antenna switch being operable to switch between the first and second antenna elements when the hinge is moved between the first and second hinge positions.

US Pat. No. 10,141,628

ANTENNA DEVICE AND METHOD FOR OPERATING THE SAME

Fraunhofer-Gesellschaft z...

1. An active antenna device for sending RFID signals, comprising:a terminal for receiving an RFID signal to be transmitted;
an antenna for generating a radio signal based on the RFID signal to be transmitted;
a controller that is configured to control properties of the antenna;
a coupler between the terminal and the antenna that is configured to decouple a signal portion from the RFID signal to be transmitted;
an energy converter that is connected between the coupler and the controller and configured to provide a power signal for the operation of the controller based on the decoupled signal portion; and
an energy storage device between the energy converter and the controller that is configured to at least partially receive the electric energy from the energy converter and to provide the controller with the same;
wherein the active antenna device is an energy self-sufficient device.

US Pat. No. 10,141,625

MOBILE TERMINAL

LG ELECTRONICS INC., Seo...

1. A mobile terminal comprising:a plurality of patch antennas arranged in an array;
an integrated circuit (IC) configured to control transmission and reception of radio signals via the plurality of patch antennas; and
a case disposed to cover the IC, wherein the case comprises:
a base forming an exterior appearance of the mobile terminal;
a heat dissipation sheet coupled to an inner surface of the base and configured to dissipate heat generated by the IC, wherein the heat dissipation sheet comprises an opening corresponding to the plurality of patch antennas; and
a dielectric member disposed at the opening and formed of a dielectric material to allow radio signals to be transmitted to and from the plurality of patch antennas through the opening.

US Pat. No. 10,141,624

METHOD FOR DYNAMIC HEAT SENSING IN HYPERSONIC APPLICATIONS

RAYTHEON COMPANY, Waltha...

1. A heat sensing system in a flight vehicle having a radome surrounding a main antenna configured for sending and/or receipt of a signal, the sensor system comprising:at least one auxiliary antenna associated with a region of the radome, the at least one auxiliary antenna being configured to receive infrared or optical energy to determine a measured temperature of the region based on the infrared or optical energy;
a processor operatively coupled to the auxiliary antenna and configured to identify whether the measured temperature exceeds a predetermined temperature; and
a controller operatively coupled to the at least one auxiliary antenna and the processor,
wherein the controller receives information from the processor regarding the measured temperature; and
wherein the controller is configured to rotate the flight vehicle to a different orientation when the measured temperature exceeds the predetermined temperature.

US Pat. No. 10,141,623

MULTI-LAYER PRINTED CIRCUIT BOARD HAVING FIRST AND SECOND COAXIAL VIAS COUPLED TO A CORE OF A DIELECTRIC WAVEGUIDE DISPOSED IN THE CIRCUIT BOARD

International Business Ma...

8. A communication system, comprising:a dielectric waveguide comprising a core and a cladding, wherein the cladding is disposed on at least two sides of the core, and wherein a material of the core has a higher dielectric constant than a material of the cladding;
a first coaxial via comprising a first center conductor and a first outer conductor surrounding the first center conductor, wherein the first center conductor extends at least partially into a first end of the core;
a second coaxial via comprising a second center conductor and a second outer conductor surrounding the second center conductor, wherein the second center conductor extends at least partially into a second end of the core; and
a pair of conductive ground planes, wherein the core and cladding are sandwiched between the pair of conductive ground planes, wherein the core and cladding directly contact both ground planes in the pair of conductive ground planes,
wherein the first and second center conductors do not extend all the way through the core of the dielectric waveguide.

US Pat. No. 10,141,620

PHASE SHIFT DEVICE

ALCAN Systems GmbH, Darm...

1. Phase shift device comprising a planar transmission line that is formed by a signal electrode and a ground electrode which are separated by a dielectric substance, and further comprising a tunable dielectric material, wherein the signal electrode of the planar transmission line is divided into several pieces and comprises overlapping areas of adjacent pieces, wherein the overlapping areas of adjacent pieces of the signal electrode of the planar transmission line are filled with the tunable dielectric material, the signal electrode and the tunable dielectric material thereby forming a varactor comprising a dielectric tunable component with a metal-insulator-metal type capacitor.

US Pat. No. 10,141,618

SYSTEM AND METHOD OF COOLING HIGH VOLTAGE BATTERY

HYUNDAI MOTOR COMPANY, S...

1. A system of cooling a high voltage battery of a vehicle, comprising:an air conditioner pressure transducer (APT) configured to output a signal simultaneously indicating whether or not ignition of a vehicle is turned on and whether or not an air conditioner is operated;
a cooling fan motor configured to cool the high voltage battery of the vehicle; and
a cooling fan motor controller configured to control the cooling fan motor on the basis of the output signal from the APT when an error is generated in a controller area network (CAN) transceiver.

US Pat. No. 10,141,617

GAS TURBINE-HEATED HIGH-TEMPERATURE BATTERY

Siemens Aktiengesellschaf...

13. A power plant system comprising:a gas turbine comprising a compression stage, a combustion chamber, a turbine stage, a heat exchanger, and a steam turbine,
a first circuit in which a working fluid flows first from the compression stage, then to the combustion chamber, then to the turbine stage, then to the heat exchanger, and then to a point downstream of the heat exchanger,
wherein the heat exchanger is configured to transfer thermal energy from the working fluid to a second fluid,
a high-temperature battery,
a feed line configured to configured to provide fluid communication between the heat exchanger and the high-temperature battery,
a discharge line configured to provide fluid communication between the high-temperature battery and the point in the first circuit downstream of the heat exchanger, and
a second circuit in which a second fluid flows: first through the heat exchanger where the second fluid is heated therein by a transfer of thermal energy from the working fluid to the second fluid; then to the high-temperature battery through the feed line; then through the high-temperature battery; and then to the point in the first circuit downstream of the heat exchanger through the discharge line,
wherein in the heat exchanger the first circuit and the second circuit are fluidically discrete from each other so that the working fluid and the second fluid are not in direct fluid communication with each other,
wherein the first circuit and the second circuit merge at the point in the first circuit downstream of the heat exchanger, thereby forming a combined exhaust gas flow,
wherein the steam turbine is operated with steam, and wherein a thermal energy of the steam is extracted at least partially from the combined exhaust gas flow, and
wherein the high-temperature battery and the gas turbine produce electricity.

US Pat. No. 10,141,615

BATTERY HOUSING STRUCTURE

NGK Insulators, Ltd., Na...

1. A battery housing structure comprising:at least one battery including: at least one electric cell for a sodium-sulfur battery; a container provided with a first wall having a relatively high thermal conductivity and a second wall having a relatively low thermal conductivity, and configured to house said at least one electric cell therein; an electrode terminal penetrating said second wall; and a wiring for electrically connecting said at least one electric cell and said electrode terminal to each other inside said container; and
a battery housing that houses said at least one battery therein, said battery housing including: a plate having a first portion overlapping an outer surface of said first wall and a second portion surrounding said first portion; and a supporter for supporting said plate at a support position apart from said first portion, said second portion of said plate is a hollow member such that the entirety of said second portion is extending horizontally from said first portion and protruding from the outer surface of said first wall, said plate defining a first main surface that is brought into direct contact with the outer surface of said first wall at said first portion and is apart from said container at said second portion, a second main surface exposed to a first space, to which heat is allowed to radiate and a second space in which said at least one battery is housed, wherein
the first space is separated from the second space via said second portion,
the outer surface of said first wall is oriented upward in a vertical direction, and
said second portion has elasticity and said second portion is deformed such that said plate is hunched downward so as to press said first portion against said first wall such that thermal resistance between said plate and said first wall is reduced, whereby said heat is allowed to radiate.

US Pat. No. 10,141,614

BATTERY PACK

MILWAUKEE ELECTRIC TOOL C...

1. A battery pack configured to be interfaced with an electrical device, the battery pack comprising:a battery pack housing;
a positive terminal, a negative terminal, and a sense terminal configured to be interfaced with corresponding terminals of the electrical device;
a plurality of battery cells arranged within the housing, each of the plurality of battery cells having a lithium-based chemistry and a respective state of charge, power being transferable between the plurality of battery cells and the electrical device;
means for monitoring the plurality of battery cells;
means for detecting a charge imbalance among the plurality of battery cells based on the respective state of charge of each of the plurality of battery cells; and
a microprocessor programmed to disable the battery pack when the charge imbalance is detected.

US Pat. No. 10,141,613

BATTERY MODULE SYSTEM

The Boeing Company, Chic...

1. A method for providing power in an aircraft, wherein the method comprises:receiving, at a battery module processor in a battery module, at least one cell signal associated with at least one cell in the battery module, wherein the at least one cell signal includes at least one of a temperature signal, a voltage signal, or a current signal;
determining, by the battery module processor, a status of the at least one cell based on the at least one cell signal;
removably coupling the battery module processor to a master/module interface, wherein the master/module interface is connected to a battery master system;
communicating, from the battery module processor, the status of the at least one cell to the master/module interface;
receiving the status of the at least one cell at the battery master system from the battery module processor through the master/module interface;
interfacing the battery master system with an aircraft host system through an aircraft/master interface; and
delivering power from the at least one cell to the master/module interface.

US Pat. No. 10,141,611

INTERNAL SHORT DETECTION AND MITIGATION IN BATTERIES

Robert Bosch GmbH, Stutt...

1. A method for identifying a material type of a dendrite causing an internal short within a battery, the method comprising:receiving, by a battery management system, an output from sensing circuitry within the battery indicative of a first voltage level;
detecting, by the battery management system, a change from the first voltage level to a second voltage level that is indicative of the internal short between an electrode and a sensing sheet;
determining by the battery management system, a resistance and a two-dimensional position of the internal short on the sensing sheet; and
identifying, by the battery management system, the material type of the dendrite causing the internal short based on the resistance of the internal short; and
treating, by the battery management system, the internal short based on the identification of the material type of the dendrite,
wherein treating the internal short based on the identification of the material type of the dendrite further includes activating, by the battery management system, a dendrite elimination protocol, wherein the dendrite elimination protocol includes providing a current through the internal short, and wherein the current is sufficient to raise a temperature of the dendrite above a melting point of the material type of the dendrite.

US Pat. No. 10,141,610

NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY AND POSITIVE ELECTRODE ACTIVE MATERIAL FOR USE IN SAME

TOYOTA JIDOSHA KABUSHIKI ...

1. A non-aqueous electrolyte secondary battery comprising a positive electrode, a negative electrode, and a non-aqueous electrolyte, whereinthe positive electrode comprises a positive electrode active material,
the positive electrode active material is formed of a particulate lithium composite oxide comprising at least lithium, nickel, cobalt, manganese and tungsten as constituent elements; and a nickel oxide layer formed on a surface of the lithium composite oxide;
with the metals other than lithium in the lithium composite oxide being 100% by mole, tungsten accounts for 0.05% by mole or greater, but 2% by mole or less;
with the lithium composite oxide being 100 parts by mass, the nickel oxide content is 0.01 part by mass or greater, but 2 parts by mass or less; and
nickel oxide accounts for 90% by mass or more of a total mass of the nickel oxide layer.

US Pat. No. 10,141,609

ELECTRODE COIL FOR A GALVANIC ELEMENT, AND METHOD FOR PRODUCING SAME

Robert Bosch GmbH, Stutt...

1. An electrode coil (2) for a galvanic element (1), the electrode coil comprising a first electrode (4), a second electrode (6), a separator (30) and a reference electrode (8), the first electrode (4) and the second electrode (6) being insulated from one another by the separator (30), and the reference electrode (8) being arranged between the first electrode (4) and the second electrode (6), characterized in that the reference electrode (8) includes a reference current collector (16), wherein the reference electrode (8) is adhesively bonded onto the second electrode (6) such that the reference current collector (16) projects past an edge of the second electrode (6), wherein the first electrode (4) includes a first current collector (12), wherein the first current collector (12) includes two regions that are separated by an open gap (18), and wherein the reference current collector (16) is disposed within the open gap (18).

US Pat. No. 10,141,608

ELECTROLYTE FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY CONTAINING THE SAME

SK Innovation Co., Ltd., ...

1. An electrolyte for a secondary battery comprising:a lithium salt;
a non-aqueous organic solvent; and
a cyclic sulfate compound represented by
the following Chemical Formula 2, 3, 4 or 5:

wherein, in the Chemical Formulas, m is an integer of 1 to 4, n is an integer of 0 to 2, and p is an integer of 0 to 6.

US Pat. No. 10,141,606

ELECTROLYTE SOLUTION, ELECTROCHEMICAL DEVICE, LITHIUM ION SECONDARY BATTERY, AND MODULE

DAIKIN INDUSTRIES, LTD., ...

1. An electrolyte solution comprisinga solvent, and
an electrolyte salt,
the solvent containing a compound (A) represented by the following formula (A) in an amount of 0.001 to 9.5 ppm in the electrolyte solution:
wherein R1 and R2 may be the same as or different from each other, and individually represent a C1-C7 alkyl group.

US Pat. No. 10,141,602

LITHIUM SOLID BATTERY, LITHIUM SOLID BATTERY MODULE, AND PRODUCING METHOD FOR LITHIUM SOLID BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A lithium solid battery comprising:a solid electrolyte layer comprising:
a sulfide glass comprising:
an ion conductor that comprises a Li element, a P element and a S element, wherein
the solid electrolyte layer has an average pore radius calculated by mercury press-in method of 0.0057 ?m or less.

US Pat. No. 10,141,601

ELECTROLYTE FOR ELECTROCHEMICAL DEVICE AND THE ELECTROCHEMICAL DEVICE THEREOF

TAIWAN HOPAX CHEMS. MFG. ...

1. An electrolyte for an electrochemical device, comprising:95-19.95 wt % of a salt,
80.0-90.0 wt % of a non-aqueous solvent, and
0.05-10.00 wt % of an additive comprising a compound represented by formula (II):

wherein R4 is C1-C3 alkyl or C1-C3 alkoxy;
R5 is empty orbital or R5 together with R6, and the nitrogen atom and the boron atom to which R5 and R6 are linked is five-membered or six-membered ring having lactone structure;
R6 is lone pair or R6 together with R5, and the boron atom and the nitrogen atom to which R5 and R6 are linked is five-membered or six-membered ring having lactone structure;
R7 is C1-C3 alkyl or R7 together with R8, and the nitrogen atom and the carbon atom to which R7 and R8 are linked is five-membered or six-membered heterocyclic ring;
R8 is hydrogen or R8 together with R7, and the carbon atom and the nitrogen atom to which R7 and R8 are linked is five-membered or six-membered heterocyclic ring;
R9 and R10 are independently hydrogen, C1-C3 alkyl, phenyl or oxo, provided that when one of R9 and R10 is oxo, the other is absent.

US Pat. No. 10,141,600

THIN FILM PATTERN LAYER BATTERY SYSTEMS

Apple Inc., Cupertino, C...

1. An assembly method comprising:forming a base layer on a process substrate;
forming a thin film battery stack on the base layer, the thin film battery stack comprising at least an anode layer, a cathode layer, a cathode current collector layer, an anode current collector layer, and an electrolyte layer between the anode layer and the cathode layer; and
attaching the thin film battery stack to a patterned layer having pattern holes configured for electrical power connection to the thin film battery stack, the patterned holes including:
a first pattern hole that physically exposes the cathode current collector layer; and
a second pattern hole that physically exposes the anode current collector layer.

US Pat. No. 10,141,597

BIPOLAR LI-ION BATTERY HAVING IMPROVED SEALING AND ASSOCIATED METHOD OF PRODUCTION

1. A bipolar Li-ion battery comprising:at least one first and second electrochemical cells stacked on top of one other in a direction of stacking and each comprising an anode, a cathode and an electrolyte;
at least one bipolar current collector having two faces, one face of which is covered with the anode of lithium-based insertion material of the first electrochemical cell and the opposite face is covered with the cathode of lithium-based insertion material of the second electrochemical cell, the bipolar current collector comprising at its periphery, on one of its faces, at least one first sealing device comprising a first heat-sensitive frame of an electrically insulating and heat-sensitive material, and two first adhesive frames of adhesive arranged individually on either side of the first heat-sensitive frame in a radial direction, perpendicular to the direction of stacking of the electrochemical cells, the first device constituting a first peripheral wall impervious to the electrolyte of the first or second electrochemical cell, which surrounds the latter;
at least one first current collector adjacent to the bipolar current collector, one face of which is covered with the cathode of the first electrochemical cell;
at least one second current collector adjacent to the bipolar current collector, one face of which is covered with the anode of the second electrochemical cell;
the first or second current collector adjacent to the bipolar current collector also comprising, at its periphery, on its covered face, at least one second sealing device comprising a second heat-sensitive frame of an electrically insulating and heat-sensitive material, and two second adhesive frames of adhesive arranged individually on either side of the second heat-sensitive frame in the radial direction perpendicular to the direction of stacking of the electrochemical cells, the second device constituting a second peripheral wall impervious to the electrolyte of the first or second electrochemical cell, which surrounds the latter;
each impervious peripheral wall being obtained by a heat-sealing technique of at least one first and at least one second sealing device on the face of the first or second current collector adjacent to the bipolar current collector that does not have the first or the second sealing device.

US Pat. No. 10,141,596

STACK ARRAY IN SOLID OXIDE FUEL CELL POWER GENERATION SYSTEM

1. A stack array in a Solid Oxide Fuel Cell (SOFC) power generation system, the stack array comprising a supporting body (5) and a plurality of stack groups (2);wherein, the supporting body (5) has a layered structure comprising at least one layer of supporting unit (6);
each layer of the supporting units (6) supports at least one stack group (2);
each stack group (2) consists of a plurality of stacks (4), and each stack (4) is horizontally arranged; and
fasteners (7) are provided between the stacks (4) to enable the stack groups (2) and the supporting units (6) to form a pressurized fastening structure that is fastened and connected through a screw hole, and a reformer (3) is provided in the fasteners (7), and a gas pipe (8) between the reformer (3) and the stack (4) is provided in the fasteners (7).

US Pat. No. 10,141,595

FUEL CELL STACK

HONDA MOTOR CO., LTD., T...

1. A fuel cell stack comprising:a stacked body in which a plurality of power generation cells are stacked in a stacking direction, each of the power generation cells including an electrolyte electrode assembly and a separator, the electrolyte electrode assembly including an electrolyte and electrodes disposed on both sides of the electrolyte;
terminal plates, insulation members, and end plates that are disposed on both sides of the stacked body in the stacking direction;
a coolant channel through which a coolant flows in a direction along an electrode surface; and
a coolant manifold that is connected to the coolant channel and through which the coolant flows in the stacking direction,
wherein the coolant manifold includes
a first coolant inlet manifold and a second coolant inlet manifold that are independent from each other, and
a first coolant outlet manifold and a second coolant outlet manifold that are independent from each other,
wherein a coolant passage is formed between each of the insulation members and a corresponding one of the end plates, the coolant passage allowing the coolant to flow in a direction along a plate surface of the end plate,
wherein the coolant passage includes
a first coolant passage connected to the first coolant inlet manifold and to the first coolant outlet manifold, and
a second coolant passage connected to the second coolant inlet manifold and to the second coolant outlet manifold, and
wherein a surface area of a region in which the first coolant passage is formed is larger than a surface area of a region in which the second coolant passage is formed, and a flow rate of the coolant flowing through the first coolant passage is larger than a flow rate of the coolant flowing through the second coolant passage.

US Pat. No. 10,141,594

SYSTEMS AND METHODS FOR ASSEMBLING REDOX FLOW BATTERY REACTOR CELLS

VRB Energy Inc., George ...

1. A redox flow battery system reactor assembly comprising:a plurality of outer frames;
a plurality of inner frames; and
a rib and channel interlock system integrated in the plurality of outer frames and the plurality of inner frames, the rib and channel interlock system configured to create a plurality of seal systems, each seal system enclosing an outer circumference of an electrolyte compartment when the plurality of outer frames and the plurality of inner frames are compressed together in a stack configuration,
wherein each seal system comprises a primary seal and a secondary seal defined in part by the rib and channel interlock system, and
wherein the secondary seal is a lower pressure seal than the primary seal.

US Pat. No. 10,141,593

COMPOSITE MEMBRANES, METHODS OF MAKING SAME, AND APPLICATIONS OF SAME

VANDERBILT UNIVERSITY, N...

1. A composite membrane, comprising:a fiber network of first polymer fibers surrounded by a matrix formed from second polymer fibers or a fiber network of the second polymer fibers surrounded by a matrix formed from the first polymer fibers, wherein
the first polymer fibers are formed from a first solution, and the first solution comprises a charged polymer and a first uncharged polymer having a repeat unit of a formula of:

 wherein each of X and Y is a non-hydroxyl group; and
the second polymer fibers are formed from a second solution, and the second solution comprises a second uncharged polymer,
wherein the second uncharged polymer is polyvinylidene difluoride (PVDF) or polyphenylsulfone (PPSU).

US Pat. No. 10,141,591

FUEL CELL SYSTEM AND CONTROL METHOD OF THE SAME

Toyota Jidosha Kabushiki ...

1. A fuel cell system, comprising:a fuel cell stack;
a compressor configured to supply a cathode gas to the fuel cell stack through a cathode gas flow path;
a pressure regulation valve configured to regulate a pressure of the cathode gas flow path;
a flowmeter configured to measure a flow rate of the cathode gas that is to be supplied to the fuel cell stack;
a pressure sensor configured to measure the pressure of the cathode gas flow path; and
a controller, wherein
the controller is configured to:
(i) calculate a torque target value of the compressor and an opening position target value of the pressure regulation valve from a flow rate target value of the cathode gas and a pressure target value of the cathode gas flow path, the flow rate target value of the cathode gas and the pressure target value being determined according to a required power output of the fuel cell stack;
(ii) calculate a torque feedback value of the compressor from a difference between a flow rate measurement value and the flow rate target value of the cathode gas, and control the compressor using a torque command value obtained by adding the torque target value and the torque feedback value; and
(iii) calculate an opening position feedback value of the pressure regulation valve from a difference between a pressure measurement value and the pressure target value of the cathode gas flow path, and control an opening position of the pressure regulation valve using an opening position command value obtained by adding the opening position target value of the pressure regulation valve and a delayed opening position feedback value that is obtained by delaying the opening position feedback value.

US Pat. No. 10,141,590

FUEL CELL SYSTEM AND METHOD OF CONTROLLING FUEL CELL SYSTEM

NISSAN MOTOR CO., LTD., ...

1. A fuel cell system that generates power by supplying anode and cathode gases to a fuel cell, comprising:a compressor configured to adjust a flow rate of the cathode gas supplied to the fuel cell;
a relief valve configured to adjust a pressure of the cathode gas supplied to the fuel cell;
a pulsation operation unit configured to pulsate an anode gas pressure;
a target flow rate setting unit configured to set a target flow rate of the cathode gas on the basis of a request from the fuel cell;
a first target pressure setting unit configured to set a first target pressure of the cathode gas on the basis of a request from the fuel cell;
a second target pressure setting unit configured to set a second target pressure of the cathode gas for maintaining a pressure difference between an anode and a cathode of the fuel cell within a predetermined allowable pressure difference range;
a target pressure setting unit configured to set the higher one of the first and second target pressures as a target pressure; and
a control unit configured to control the compressor and the relief valve on the basis of the target flow rate and the target pressure,
wherein the control unit controls the compressor on the basis of the target flow rate and a limitative pressure obtained by limiting pulsation of the target pressure when the target pressure is pulsated in response to pressure pulsation of the anode gas.

US Pat. No. 10,141,589

FUEL CELL SYSTEM AND A METHOD FOR CONTROLLING A FUEL CELL SYSTEM

Toyota Jidosha Kabushiki ...

7. A method for controlling a fuel cell system having a fuel cell and a tank that stores gas used in the fuel cell, the method comprising:measuring a fill-time pressure that is pressure during gas filling in a piping for filling the tank with the gas;
measuring the supply piping pressure that is pressure on start of the fuel cell in a supply piping for supplying the gas from the tank to the fuel cell;
measuring an internal pressure of the tank;
deriving the estimated pressure value of the supply piping pressure on start of the fuel cell based on a first pressure value that shows the fill-time pressure, the internal temperature when the first pressure value was measured, and the internal temperature when the supply piping pressure was measured; and
detecting as the supply piping pressure the lower value among the estimated pressure value and a second pressure value that shows the measured supply piping pressure.

US Pat. No. 10,141,587

FUEL CELL SYSTEM WITH CATHODE BYPASS VALVE AND CONTROL METHOD FOR FUEL CELL SYSTEM

NISSAN MOTOR CO., LTD., ...

1. A fuel cell system, comprising;a cathode gas supply device that supplies cathode gas to a fuel cell;
a bypass valve that bypasses the cathode gas to be supplied to the fuel cell by the cathode gas supply device;
a sensor that detects a state of the cathode gas to be supplied to the fuel cell without being bypassed by the bypass valve;
a pressure adjusting device that adjusts a pressure of the cathode gas to be supplied to the fuel cell;
a controller programmed to:
calculate a target flow rate and a target pressure of the cathode gas to be supplied to the fuel cell according to an operating state of the fuel cell;
control at least one of a pressure operation amount sufficient for the pressure adjusting device to supply an operating pressure of the cathode gas or a flow rate operation amount sufficient for the cathode gas supply device to supply an operating flow rate of the cathode gas on the basis of a flow rate and the pressure of the cathode gas detected by the sensor and the calculated target flow rate and the calculated target pressure;
open and close the bypass valve on the basis of the flow rate of the cathode gas detected by the sensor and the calculated target flow rate; and
increase the pressure of the cathode gas to be supplied to the fuel cell by increasing the at least one operation amount calculated when the bypass valve is opened.

US Pat. No. 10,141,585

MULTI-COMPONENT BIPOLAR PLATE FOR AN ELECTROCHEMICAL CELL

Nuvera Fuels Cells, LLC, ...

1. A bipolar plate assembly, comprising:a first seal assembly including a first high pressure seal, a second high pressure seal, and an insert plate disposed between the first high pressure seal and the second high pressure seal;
the insert plate has a plurality of ridges formed on an upper surface and a lower surface of the insert plate configured to penetrate into the first high pressure seal and the second high pressure seal when the first high pressure seal and the second high pressure seal are pressed onto the insert plate, thereby forming the seal assembly; and
a frame and a base configured to be joined to form a bipolar plate and define a high pressure zone;
wherein the seal assembly when installed in the bipolar plate is configured to seal the portion of the high pressure zone defined by the bipolar plate.

US Pat. No. 10,141,584

SEPARATOR OF FUEL CELL AND FUEL CELL HAVING THE SAME

HYUNDAI MOTOR COMPANY, S...

8. A fuel cell comprising:a separator including a plurality of channels, and an inlet hole and an outlet hole respectively formed in a first side and a second side of the plurality of channels such that a reaction gas flows into and out from the separator to be exposed to a reaction surface including a membrane electrode assembly, the inlet hole being larger in size than the outlet hole; and
a gas diffusion layer disposed between a bottom of the separator and the membrane electrode assembly and activating and guiding a reaction gas flowing inside through the inlet hole to the membrane electrode assembly,
wherein a plurality of inlet holes and a plurality of outlet holes are formed in a longitudinal direction of the plurality of channels, and centers of the plurality of inlet holes and centers of the plurality of outlet holes are not aligned,
wherein the centers of the plurality of inlet holes are positioned higher above the reaction surface than the centers of the plurality of outlet holes.

US Pat. No. 10,141,583

BIPOLAR PLATE AND FUEL CELL COMPRISING A BIPOLAR PLATE OF THIS TYPE

Volkswagen AG, Wolfsburg...

1. A bipolar plate for a fuel cell comprising:a profiled anode plate and a profiled cathode plate, each having an active area and two distributor areas for the supply and removal of operating media to or from, respectively, the active area, the distributor areas each having an anode gas main port for the supply and discharge of fuel, a cathode gas main port for the supply and discharge of oxidants, and a coolant main port for the supply and discharge of coolant, the anode gas main port, the cathode gas main port and the coolant main port situated along a lateral edge of the bipolar plate, the anode and cathode plates being formed and situated one over another in such a way that the bipolar plate has channels for the operating media, the channels connecting the anode gas main port, the cathode gas main port and the coolant main port of both distributor areas to one another, the distributor areas having at least one overlap section, the channels overlapping one another in a non-fluidically connected way in the at least one overlap section,
the cathode gas main port being situated between the anode gas main port and the coolant main port and cathode channels of the channels proceeding from the cathode gas main port extending linearly at least across the distributor area of the bipolar plate.

US Pat. No. 10,141,582

SOFC INTERCONNECT BARRIERS AND METHODS OF MAKING SAME

Sonata Scientific LLC, B...

1. A barrier layer on a metallic substrate, the metallic substrate comprising a first portion adjacent to a vitreous reactive solid and a second portion adjacent to an electrode, the barrier layer being on the first portion between the metallic substrate and the vitreous reactive solid, the barrier layer not being between the second portion and the electrode, the barrier layer substantially reducing chemical reaction between the metallic substrate and the reactive solid, and the barrier layer comprising an insulating thin film material deposited by atomic layer deposition.

US Pat. No. 10,141,581

METHOD FOR THE DEPASSIVATION OF A LITHIUM-THIONYL BATTERY, A DEVICE FOR CARRYING OUT THE METHOD, AND A BATTERY DEVICE

4114, Jona (CH)

1. A method for depassivation of a lithium-thionyl battery, comprising:a) applying at least one current test load (LAST) to an electrode of the battery, wherein at least one of a shape, a magnitude, or a point in time of the application of the at least one current test load (LAST) occurs dependent on a measurement of a time-dependent response signal (u(t), du(t)) on the battery, and energy of the current test load (LAST) is drawn from the battery,
b) comparing the response signal (u(t), du(t)) of the battery arising from application of the at least one current test load (LAST) to at least one predefined criterion, and
c) establishing an operating state or issuing an error message depending on satisfaction of the at least one predefined criterion,
wherein a temporal change variable (ddu(t)) is calculated as a difference between a response signal (du(t2)) at time t2 and a response signal (du(t1)) at time t1 as: ddu(t2)=du(t2)?du(t1), and
wherein a second predefined criterion comprises verifying at least one of (a) whether the temporal change variable (ddu(t)) has reached a certain threshold (X) or (b) whether a predetermined time (T) has elapsed.

US Pat. No. 10,141,580

BATTERY

BATTERY RESEARCH TECHNOLO...

1. A battery including:a casing having an inner surface defining a chamber in which an electrolyte is disposed therein;
a conductive surface located within the chamber adjacent the inner surface of the casing, the conductive surface being configured for electrical communication with an anode terminal of the battery;
a permeable separator sheet located within the casing configured for electrically isolating the electrolyte from the conductive surface;
a conductive rod having a first end configured for electrical communication with a cathode terminal of the battery, and, a second end of the conductive rod configured for electrical communication with the electrolyte; and
an opening disposed in the casing;
wherein the casing includes at least a first and second portion that are movably attached to each other, the first and second portions being movable relative to each other between at least a first attached position whereby the opening is substantially blocked from allowing ingress of a liquid into the casing via the opening, and, a second attached position whereby the opening is substantially unblocked so as to allow ingress of the liquid into contact with the electrolyte in the chamber via the opening to activate the battery by generating a potential difference between the conductive surface and the conductive rod.

US Pat. No. 10,141,578

METHOD FOR PRODUCING FUEL CELL MEMBRANE ELECTRODE ASSEMBLY

HONDA MOTOR CO., LTD., T...

1. A method for producing a fuel cell membrane electrode assembly comprising the steps of:preparing an electrolyte membrane;
preparing a catalyst layer-including substrate in which a first catalyst layer is formed on one face of a sheet-like substrate;
laminating the catalyst layer-including substrate so that the first catalyst layer opposes one face of the electrolyte membrane;
bonding the electrolyte membrane and the catalyst layer including substrate;
making a cut by way of energy rays so that the catalyst layer-including substrate bonded with the electrolyte membrane becomes a predetermined shape;
peeling an unwanted portion of the catalyst layer-including substrate other than a portion of the predetermined shape from the electrolyte membrane;
forming a second catalyst layer on one other face of the electrolyte membrane, and
punching out the electrolyte membrane and the second catalyst layer so that the catalyst layer-including substrate of the predetermined shape bonded to the one face is surrounded,
wherein the energy rays penetrate the electrolyte membrane without penetrating the catalyst layer-including substrate.

US Pat. No. 10,141,577

MANUFACTURING METHOD FOR CATALYST ELECTRODE, CATALYST ELECTRODE MANUFACTURED BY MEANS OF METHOD, AND BATTERY COMPRISING SAME

KOREA UNIVERSITY RESEARCH...

1. A catalytic electrode structure, comprising an electrode support, and a porous continuous electroconductive material on the electrode support in direct contact therewith, with no binder binding the porous continuous electroconductive material onto the electrode support, wherein the porous continuous electroconductive material comprises pores whose diameters are within a range of 1 to 1000 nm, and wherein at least some of the pores are connected with each other.

US Pat. No. 10,141,576

ELECTRODE STRUCTURE FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY HAVING THE ELECTRODE STRUCTURE

1. An electrode for a lithium battery, the electrode comprising:a current collector;
nanoparticles distributed on the current collector such that 5 to 95% of an entire surface area of a plane of the current collector is exposed, each of the nanoparticles comprising a transition metal or an oxide of the transition metal; and
an active material layer disposed on the current collector.

US Pat. No. 10,141,575

ELECTRODE, NONAQUEOUS ELECTROLYTE BATTERY, BATTERY PACK, AND VEHICLE

KABUSHIKI KAISHA TOSHIBA,...

1. An electrode comprising:a current collector; and
an electrode layer disposed on the current collector and including lithium fluoride,
wherein a first content of lithium fluoride based on a weight of the electrode layer in a first region of the electrode layer is within a range of 0.02% by weight or more and less than 2% by weight, the first region being adjacent to an interface between the electrode layer and the current collector, and having a first thickness equal to 20% with respect to a thickness of the electrode layer,
and a second content of lithium fluoride based on a weight of the electrode layer in a second region of the electrode layer is within a range of from 2% by weight to 10% by weight, the second region being adjacent to a surface on a reverse side of the electrode layer with respect to the interface between the electrode layer and the current collector, and having the first thickness.

US Pat. No. 10,141,573

LITHIUM SECONDARY BATTERY NEGATIVE ELECTRODE ACTIVE MATERIAL AND METHOD FOR MANUFACTURING SAME

NATIONAL INSTITUTE OF ADV...

1. A negative electrode for a lithium secondary battery comprising:a negative electrode active material containing a precipitate including an Sn—Sb based sulfide obtained by adding alkali metal sulfide to a mixed solution of tin halide and antimony halide in a solvent, the solution further containing an organic acid, wherein the Sn—Sb based sulfide has a disordered crystal structure which is in an intermediate state of a crystal and an amorphous;
wherein the Sn—Sb based sulfide includes 10 to 90 mole percent Sn based on the total moles of Sn and Sb; and
wherein the organic acid includes tartaric acid, citric acid, malic acid, lactic acid, gluconic acid, succinic acid, fumaric acid, maleic acid, formic acid, valeric acid, acetic acid, ascorbic acid, or an amino acid.

US Pat. No. 10,141,571

NICKEL-COBALT COMPOSITE HYDROXIDE AND METHOD AND DEVICE FOR PRODUCING SAME, CATHODE ACTIVE MATERIAL FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY AND METHOD FOR PRODUCING SAME, AND NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

SUMITOMO METAL MINING CO....

1. In combination, a nickel-cobalt composite hydroxide and a production device for producing the nickel-cobalt composite hydroxide, the combination comprising:the nickel-cobalt composite hydroxide comprising
a general formula: Ni1-x-yCoxMy(OH)2 (where, 0.05?x?0.50, 0?y?0.10, 0.05?x+y?0.50, and M is at least one kind of metal element selected from among Al, Mg, Mn, Ti, Fe, Cu, Zn and Ga,
an average particle size of within a range from 10 ?m to 30 ?m, and
(D50?D10)/D50?0.30, and (D90?D50)/D50?0.30 among D10, D50 and D90 of the nickel-cobalt composite hydroxide; and
the production device comprising
a reaction vessel;
a constant volume pump for continuously supplying an aqueous solution including nickel and cobalt, an aqueous solution including an ammonium ion donor, and a caustic alkali aqueous solution to the reaction vessel;
a constant volume pump for with an extraction nozzle for continuously extracting nickel-cobalt composite hydroxide generated by a reaction inside the reaction vessel from the reaction vessel by way of the extraction nozzle;
a separation apparatus separating the extracted nickel-cobalt composite hydroxide into a large particle size portion and a small particle size portion by classification; and
a reflux apparatus continuously returning the small particle size portion separated out to the reaction vessel.

US Pat. No. 10,141,570

POSITIVE ELECTRODE ACTIVE MATERIAL FOR LITHIUM SECONDARY CELL

1. A positive electrode active material for a lithium secondary cell, comprising a particle having a surface portion where one or a combination of two or more (these are referred to as “surface element A”) of the group consisting of Al, Ti and Zr is present, on a surface of a particle comprising a lithium metal composite oxide having a layer crystal structure and represented by the general formula: Li1+xM1?xO2, wherein x=0 to 0.07 and M is one or a combination of two or more (referred to as “constituent element M”) of the group consisting of Mn, Co, Ni, transition elements in the third group elements through and including the 11th group elements of the periodic table, and elements in the first period through and including the third period of the periodic table,wherein a ratio (CA/CM) of a concentration (at %) (referred to as “CA”; in the case where the surface element A contains two or more elements, the total concentration) of the surface element A to a concentration (at %) (referred to as “CM”; in the case where the constituent element M contains two or more elements, the total concentration) of the constituent element M is higher than 0 and lower than 0.8, as measured by X-ray photoelectron spectroscopy (XPS); an amount of surface lithium impurity is smaller than 0.40% by weight; and in an X-ray diffraction pattern measured by a powder X-ray diffractometer (XRD) using CuK?1 radiation, a ratio (003)/(104) of an integral intensity of a peak originated from the (003) plane to an integral intensity of a peak originated from the (104) plane is higher than 1.15.

US Pat. No. 10,141,569

BATTERY LIFE BY CONTROLLING THE VOLTAGE WINDOW OF THE NEGATIVE ELECTRODE

GM GLOBAL TECHNOLOGY OPER...

1. A method for improving a life cycle of a battery containing a lithium-silicon thin-film negative electrode, the method comprising:providing the battery, including:
a positive electrode;
the lithium-silicon thin-film negative electrode having at least 10% of its capacity attributed to a silicon-based active material and a thickness of less than about 50 ?m;
a separator positioned between the positive and negative electrodes; and
an electrolyte; and
operating the battery within a voltage potential window ranging from about 0.7 V and about 0.07 V versus a lithium reference electrode so that a stress amplitude of the lithium-silicon thin-film negative electrode is maintained from about ?0.5 GPa to about 0.3 GPa during the operating of the battery.

US Pat. No. 10,141,567

CATHODE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY, METHOD OF PREPARING THE SAME, AND LITHIUM SECONDARY BATTERY CONTAINING THE SAME

1. A cathode active material for a lithium secondary battery, the cathode active material comprising:a core made of a compound reversibly intercalating and deintercalating lithium; and
a coating layer positioned on at least a portion of a surface of the compound,
wherein the coating layer is a composite coating layer containing Li3PO4 and LiF, and
the core is doped with fluorine.

US Pat. No. 10,141,565

NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY COMPRISING SURFACE-COATED POSITIVE ELECTRODE MATERIAL

Toyota Jidosha Kabushiki ...

1. A non-aqueous electrolyte secondary battery comprising a non-aqueous electrolyte solution and a positive electrode provided with a positive electrode mixture layer, whereinthe positive electrode mixture layer includes positive electrode active material particles,
a surface of each of the positive electrode active material particles is coated with a film formed of an inorganic solid electrolyte, and
a positive electrode active material of the positive electrode active material particles is a lithium-containing composite oxide having a spinel structure, is represented by the compositional formula: LiNi0.5Mn1.5O4, performs charge and discharge at an electric potential of 4.5 V or more with respect to the lithium metal, and contains at least one of Ti and Mg as a dopant.

US Pat. No. 10,141,564

LITHIUM TITANATE STRUCTURES FOR LITHIUM ION BATTERIES FORMED USING ELEMENT SELECTIVE SPUTTERING

GM GLOBAL TECHNOLOGY OPER...

1. A method, comprising:subjecting a lithium titanate precursor structure to element selective sputtering to form a lithium titanate structure including a lithium titanate core and a conformal layer on the lithium titanate core, wherein the conformal layer includes titanium oxide and the lithium titanate structure has a surface essentially devoid of lithium.

US Pat. No. 10,141,563

NEGATIVE-ELECTRODE ACTIVE MATERIAL, PRODUCTION PROCESS FOR THE SAME AND ELECTRIC STORAGE APPARATUS

KABUSHIKI KAISHA TOYOTA J...

1. A production process for negative-electrode active material, the production process comprising the steps of:a reaction step of obtaining a lamellar polysilane by reacting a hydrogen chloride (HCl) aqueous solution with calcium disilicide;
an impurity removal step of turning the lamellar polysilane into an impurity-reduced lamellar polysilane by removing halogen elements from the lamellar polysilane; and
a calcination step of obtaining a nanometer-size silicon powder by heat treating the impurity-reduced lamellar polysilane at a temperature exceeding 100° C. under a nonoxidizing atmosphere,
wherein said impurity removal step is carried out by neutralizing a reaction solution including said lamellar polysilane with a base after said reaction step.

US Pat. No. 10,141,562

ANODE AND BATTERY

Murata Manufacturing Co.,...

1. An anode comprising:an anode active material layer having opposed first and second surfaces and containing an anode active material comprising a silicon material; and
a coating layer formed by vapor-phase deposition that coats the first surface of the anode active material layer, the coating layer containing an oxide selected from the group consisting of FeO, CoO, NiO and combinations thereof,
wherein the silicon material is
an alloy of silicon including at least one selected from the group consisting of tin, cobalt, manganese, zinc, indium, silver, germanium, bismuth and chromium, or
a compound of silicon including oxygen and carbon.

US Pat. No. 10,141,560

ENERGY STORAGE DEVICE INCLUDING A PRESSING MEMBER PRESSING A SEPARATOR TOWARD AN ELECTRODE ASSEMBLY

GS YUASA INTERNATIONAL LT...

1. An energy storage device, comprising:an electrode assembly in which electrode plates are stacked;
a current collector connected to an end portion of the electrode assembly;
a container which accommodates the electrode assembly and the current collector; and
a spacer which is disposed between the electrode assembly and an inner surface of the container, the spacer including a projecting portion projecting toward the electrode assembly,
wherein the end portion of the electrode assembly includes:
an electrode plate welded portion at which the stacked electrode plates are welded to each other in a stacking direction and not joined to the current collector; and
a current collector joined portion which is joined to the current collector and is arranged adjacently to the electrode plate welded portion in a current collector extending direction that intersects with the stacking direction,
wherein the electrode assembly includes a separator disposed on an outermost side of the electrode assembly, and further includes a non-coated portion where an active material layer is not formed on the end portion of the electrode assembly, and
wherein the projecting portion presses the separator toward the non-coated portion such that a gap between the separator and the non-coated portion in the stacking direction is closed.

US Pat. No. 10,141,559

POROUS INTERLAYER FOR A LITHIUM-SULFUR BATTERY

GM GLOBAL TECHNOLOGY OPER...

1. A method for making a porous interlayer for a lithium-sulfur battery, the method comprising;dispersing an electronic component selected from a carbon material, a conductive polymeric material, and combinations thereof in a first liquid to form a first dispersion;
exposing a porous support structure to the first dispersion, whereby the electronic component remains on a surface of the porous support structure and the first liquid filters through the porous support structure;
dispersing a negatively charged or chargeable lithium ion conducting component in a second liquid to form a second dispersion; and
exposing the porous support structure to the second dispersion, whereby the negatively charged or chargeable lithium ion conducting component remains on the surface of the porous support structure and the second liquid filters through the porous support structure.

US Pat. No. 10,141,558

SEPARATOR FOR LITHIUM-ION BATTERY AND METHOD FOR PREPARING THE SAME

BYD COMPANY LIMITED, She...

1. A separator for a lithium-ion battery, comprising:a substrate comprising a base polymer, a first polymer, and a first inorganic material;
a coating comprising a second polymer and a second inorganic material; and
a middle layer formed between the substrate and the coating and comprising a part of the substrate and a part of the coating, wherein
the first polymer and the second polymer independently comprise an acid radical in a side chain thereof, the first inorganic material is reactive with the first polymer via a first neutralization reaction, and the second inorganic material is reactive with the second polymer via a second neutralization reaction.

US Pat. No. 10,141,557

ADHESIVE FOR LITHIUM ION SECONDARY BATTERIES, SEPARATOR FOR LITHIUM ION SECONDARY BATTERIES, AND LITHIUM ION SECONDARY BATTERY

ZEON CORPORATION, Tokyo ...

1. An adhesive for a lithium ion secondary battery, for bonding members for constituting a lithium ion secondary battery,the adhesive comprising a particulate polymer, wherein
the particulate polymer has a core-shell structure including a core portion and a shell portion that partially covers an outer surface of the core portion,
the core portion is formed from a polymer having a swelling degree in an electrolytic solution of 5 times or more and 30 times or less,
the shell portion is formed from a polymer having a swelling degree in the electrolytic solution of more than 1 time and 4 times or less,
the amount of the particulate polymer is 50% by weight or more and 99.9% by weight or less with respect to solid content of the adhesive,
each of the swelling degrees represents a ratio (W1/W0) of W1 with respect to W0,
W0 represents a weight of a 1-cm square piece of a film having a thickness of 0.5 mm that is produced from the polymer of the core portion or the polymer of the shell portion,
W1 represents a weight of the 1-cm square piece that has been immersed in the electrolytic solution at 60° C. for 72 hours, and
the electrolytic solution consists of a mixed solvent of ethylene carbonate, diethyl carbonate and vinylene carbonate (volume mixing ratio of ethylene carbonate/diethyl carbonate/vinylene carbonate=68.5/30/1.5) and 1 mol/L of LiPF6.

US Pat. No. 10,141,555

MULTI-LAYERED POROUS FILM AND NONAQUEOUS-ELECTROLYTE SECONDARY BATTERY

Sumitomo Chemical Company...

1. A method of fabricating a multi-layered porous film including: a base film and a functional layer containing therein both an inorganic filler and a binder resin, the functional layer being formed on a surface of the base film, the multi-layered porous film having a length equal to or greater than 200 meters, wherein a difference between a maximum basis weight and a minimum basis weight of the multi-layered porous film in a length-wise direction thereof is equal to or smaller than 2 grams/m2, the basis weight being measured every 100 meters interval, the method comprising:immersing a gravure roll having protrusions and recesses formed on a surface thereof, into a coating liquid containing therein inorganic fillers and binder resins to thereby retain the coating liquid in the recesses formed on a surface of the gravure roll, and causing the gravure roll to make contact with a continuously fed base film to thereby coat the coating liquid retained in the recesses, onto a surface of the base film, thereby forming a functional layer containing inorganic fillers and binder resins, on a surface of the base film,
the gravure roll employed for gravure coating comprising a roll body composed of a metal, a plurality of protrusions being formed on an outer surface of the roll body, and each obliquely extending at a predetermined angle relative to a central axis of the roll body, a plurality of recesses each being formed between the adjacent obliquely extending protrusions and each retaining the coating liquid therein, the roll body being entirely covered on an outer surface thereof with a diamond like carbon (DLC) layer, each of the obliquely extending protrusions having a trapezoidal cross-section a head of which is cut down and which has a width gradually reducing towards the head, wherein each of the recesses has a trapezoidal cross-section,
wherein the DLC layer is water-repellent.

US Pat. No. 10,141,552

PROTECTION SYSTEM FOR A BATTERY DURING RECOIL OF A SHOOTING DEVICE

1. A protection system for camera system comprising:a camera with a lens and a mount to mechanically couple with a weapon that propels projectiles from a discharge end along a longitudinal axis from the weapon;
a battery compartment formed as part of the camera system;
a battery with internal components including active electrode material formed within one or more cells surrounded with at least one cell wall defining a soft pouch cell-type for insertion into the battery compartment in which a gap is formed between the cell wall and an end wall of the battery compartment closest to the lens along a battery's longitudinal axis which is parallel to the longitudinal axis of the weapon; and
a piece of material forming a collector protector device which is formed as a substantially U-shape surrounding three sides of the soft pouch cell-type that is separate from the battery and separate from the battery compartment formed to fill the gap in order to hold the active electrode materials against the soft pouch cell-type thereby reducing any stress on current collector components which are disposed inside the soft pouch cell-type of the battery during shock and vibration in a direction along the battery's longitudinal axis, and the piece of material selected to allow for expansion and contraction of the active electrode materials due to thermal changes or state-of-charge level changes, and the collector protector device formed to fill the gap to hold the active electrode materials against the soft pouch cell-type, which is independent of any other cushioning material used to maintain an electrical contact, via contact springs or spring loaded.

US Pat. No. 10,141,551

BATTERY SYSTEM

SAMSUNG SDI CO., LTD., Y...

1. A battery system, comprising:a first battery pack including at least one first battery cell;
a second battery pack connected to the first battery pack in parallel and including at least one second battery cell;
a bidirectional power converter connected between the first battery pack and the second battery pack; and
a current controller to set a discharge current limit of the first battery pack based on a state of charge (SOC) of the first battery pack, and to control the bidirectional power converter to cause the first battery pack to output a discharge current that is less than or equal to the discharge current limit, wherein:
when the SOC of the first battery pack is equal to or greater than a first reference value, the current controller is to set the discharge current limit of the first battery pack to be a first current value corresponding to a maximum discharge rate of the first battery pack, and
when the SOC of the first battery pack is less than a second reference value that is less than the first reference value, the current controller is to set the discharge current limit of the first battery pack to be a second current value that is less than the first current value.

US Pat. No. 10,141,550

POUCH BATTERY CELL ASSEMBLY FOR TRACTION BATTERY

Ford Global Technologies,...

8. A pouch battery cell assembly for a traction battery comprising:a housing defining a cavity;
an almond-shaped first intermediate terminal member disposed at least partially within the housing and defining an access port open to an exterior of the housing and the cavity;
a first terminal tab embedded within the first intermediate terminal member;
an almond-shaped second intermediate terminal member disposed at least partially within the housing and spaced from the first intermediate terminal member;
a second terminal tab embedded within the second intermediate terminal member;
a central member extending between the first and second intermediate terminal members; and
a seal extending about an upper portion of each of the first and second intermediate terminal members and the central member.

US Pat. No. 10,141,549

POUCH CASE FOR SECONDARY BATTERY AND POUCH TYPE SECONDARY BATTERY INCLUDING THE SAME

LG CHEM, LTD., Seoul (KR...

1. A pouch case for a secondary battery, comprising an inner layer, a metallic layer, and an outer layer,wherein the inner layer comprises a foaming activator containing an isocyanate-based compound which generates a gas by a reaction with a foaming agent,
wherein the inner layer further comprises at least one catalyst selected from the group consisting of tertiary amine-based catalysts and organometallic catalysts, and
wherein, when the foaming agent is introduced by an external factor caused by a crack or rupture, a protective gas layer is formed by a gas evolution reaction on an outer surface of the inner layer by a reaction between the isocyanate compound of the foaming activator and the foaming agent.

US Pat. No. 10,141,547

NONAQUEOUS SECONDARY BATTERY AND METHOD FOR MANUFACTURING SAME

TOKYO OHKA KOGYO CO., LTD...

1. A nonaqueous secondary battery comprising:a positive electrode;
a negative electrode;
a substrate;
a cover member; and
an electrolyte,
wherein the positive electrode and the negative electrode are arranged in substantially the same plane and respective end surfaces of the positive electrode and the negative electrode face each other at a distance;
the substrate fixingly supports the positive electrode and the negative electrode;
the cover member has gas barrier properties and defines an airtight chamber together with the substrate;
the cover member comprises glass, a glass film, or silicon, and
a noble metal or a hydrofluoric acid-resistant inorganic oxide selected from the group consisting of Al2O3, ZrO2, ZnO, Nb2O5, Ta2O5, and TiO2 is vapor-deposited to the cover member which is brought into contact with the electrolyte;
the airtight chamber contains the positive electrode and the negative electrode;
the electrolyte is contained in the airtight chamber and is configured to be present at least between the facing end surfaces of the positive electrode and the negative electrode.

US Pat. No. 10,141,546

INNER CASE OF BATTERY MODULE ASSEMBLY FOR VEHICLE'S BATTERY PACK

LG CHEM, LTD., Seoul (KR...

1. A battery pack comprising:a battery module assembly comprising four battery modules, each module having a plurality of cylindrical secondary battery cells (hereinafter, also referred to as ‘cells’), are electrically connected in series, and a bus bar directly connected to a first side surface of the battery module assembly; and
an inner case, comprising:
a side frame directly contacting two facing sides, other than said first side surface, among sides of the battery module assembly and comprising side frame apertures;
an upper frame comprising a bottom surface configured to directly contact and completely encompass an upper surface of the battery module assembly and the upper frame is directly connected to the side frame, wherein the side frame extends downward from the upper frame; and
an electrode post assembly that comprises two electrode posts, each electrode post having a metal plate, wherein each metal plate is electrically connected to and directly contacts the bus bar at the first side surface and the metal plate directly contacts a top surface of the upper frame, wherein the top surface of the upper frame is opposite to the bottom surface of the upper frame,
wherein the side frame extends from the upper frame to a bottom surface of the battery module assembly,
wherein the side frame is fixedly connected to threaded holes formed at said two facing sides the battery module assembly via screws extending through each of said side frame apertures,
wherein the electrode post assembly is electrically connected to an electrode of the battery module assembly via said bus bar,
wherein the upper frame and the side frame are comprised of a polymer material,
wherein the inner case is configured to be disposed within a lower case and an upper case,
wherein the top surface of the upper frame includes at least one enclosed handle and a space configured to mount a battery management unit thereon, and
wherein the inner case forms a u-shape and is open at an end opposite to the upper frame.

US Pat. No. 10,141,544

ELECTROLUMINESCENT DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display device comprising:a first electrode;
a second electrode;
a light-emitting layer between the first electrode and the second electrode; and
a protective film over the second electrode,
wherein the protective film comprises a first insulating film and a second insulating film over the first insulating film,
wherein the first insulating film comprises one or more of aluminum oxide, hafnium oxide, and zirconium oxide,
wherein the second insulating film comprises one or more of aluminum oxide, hafnium oxide, and zirconium oxide, and
wherein a water vapor transmission rate of the protective film is lower than 1×10?2 g/(m2·day) under a condition of 40° C. and a relative humidity of 90%.

US Pat. No. 10,141,542

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device, which includes a display region in which pixels are arranged, comprising:a first organic insulating film;
a first groove;
a first inorganic partition portion;
a second organic insulation film;
a second groove,
wherein the first groove separates the first organic insulation film and has a frame shape surrounding the display region,
the first inorganic partition portion is in the first groove and has a frame shape surrounding the display region,
the second groove separates the second organic insulation film,
the first inorganic partition portion includes an upper surface that is below an upper surface of the second organic insulating film, and
the second groove is inside the first groove.

US Pat. No. 10,141,541

PACKAGE COMPONENT OF AN OLED DEVICE AND A PACKAGE METHOD THEREOF, AND A DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A package component of an Organic Light Emitting Diode (OLED) device, comprising:a substrate, loading the OLED device;
a first blocking layer covering the OLED device, a first side of the first blocking layer far away from the OLED device comprising a first pattern region and a second pattern region alternately set along a predetermined direction, a second side of the first blocking layer is flat, and the second side is contacted with the OLED device, wherein thickness of the first blocking layer at the first pattern region is smaller than that at the second pattern region; and
a buffer layer coated on the first blocking layer, comprising heat-dissipating particles.

US Pat. No. 10,141,540

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A method of manufacturing a display device, the method comprising:forming a display module including a first area defined therein, the display module comprising a display panel including a lower surface and an upper surface opposite the lower surface, a first film under the lower surface of the display panel, a second film on the upper surface of the display panel, and an adhesive layer between the lower surface of the display panel and the first film;
weakening an adhesive force of a first adhesive portion of the adhesive layer in the first area to be weaker than an adhesive force of a second adhesive portion of the adhesive layer outside the first area;
cutting the first film and the adhesive layer along an edge of the first area; and
removing a portion of the first film and the first adhesive portion from the first area.

US Pat. No. 10,141,539

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a first substrate;
a circuit layer which is arranged on the first substrate and includes pixel circuits arranged in a matrix;
a resin layer which is arranged on the circuit layer and has a first groove and a second groove;
organic light emitting elements on the resin layer, each of the organic light emitting elements being arranged in a matrix and being connected to corresponding one of the pixel circuits;
a bank on the resin layer;
a sealing layer on the organic light emitting elements; and
a layer including a filling material on the sealing layer, wherein
the organic light emitting elements include anodes on the resin layer, an organic layer including an organic emitting layer on the anodes, and a cathode on the organic layer,
the bank is arranged between the anodes and the organic layer and includes an organic insulation material,
each of the organic light emitting elements includes corresponding one of the anodes, corresponding one of regions of the organic layer, and corresponding one of regions of the cathode,
the organic light emitting elements share the organic layer and the cathode,
the bank covers a peripheral region of each of the anodes and exposes a part of an upper surface of each of the anodes,
the first groove has a first width,
the second groove has a second width and surrounds the pixel circuits and the organic light emitting elements in plan view, the first groove arranged between the pixel circuits and the second groove in the plan view,
the bank has a third groove directly above the first groove and a fourth groove directly above the second groove,
the third groove has a third width,
the fourth groove surrounds the pixel circuits and the organic light emitting elements in the plan view,
a first portion of the bank is arranged in the second groove, and
a side surface of the second groove is covered with the first portion.

US Pat. No. 10,141,538

SEALANT, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising: a display region, a dummy region and a sealant region which are arranged from inside to outside, whereina plurality of reflection columns are provided in the dummy region, and heights of the plurality of reflection columns are sequentially reduced from outside to inside.

US Pat. No. 10,141,537

DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising:a first substrate;
a second substrate provided opposite to the first substrate, a sealing adhesive layer being provided between the first substrate and the second substrate, the sealing adhesive layer being configured to bond the first substrate and the second substrate to form a sealed structure;
a fusion layer, wherein the fusion layer is provided between the sealing adhesive layer and the first substrate and at a region corresponding to the sealing adhesive layer, and the fusion layer includes a metal material; and
a protective layer, the protective layer being provided outside of the fusion layer and directly contacting the fusion layer on an outside surface of the fusion layer, and the protective layer being provided with a same thickness as the fusion layer on a surface of the first substrate facing the second substrate.

US Pat. No. 10,141,536

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A method for manufacturing a display device, comprising:forming an insulating film over and in contact with a first substrate with flexibility;
forming a first sealant continuously surrounding a display region over the insulating film;
irradiating the first sealant with a first laser beam;
bonding a second substrate with flexibility to the first substrate with the first sealant;
irradiating the first sealant with a second laser beam;
forming a second sealant continuously surrounding the first sealant in a gap between the first substrate and the second substrate and on a side surface of the first substrate and a side surface of the second substrate; and
forming a member in contact with a side surface of the second sealant,
wherein the member comprises a bottom surface portion in contact with a top surface of the insulating film.

US Pat. No. 10,141,533

QUANTUM DOT-BASED LIGHTING SYSTEM FOR AN AIRCRAFT

1. An aircraft cabin lighting unit comprising:a plurality of quantum dot light-emitting diodes (“QLEDs”), including a first QLED of a first color and a second QLED of a second color;
one or more light-emitting diodes (“LEDs”); and
logic circuitry configured to:
control the plurality of QLEDs to emit light in a first brightness ratio to create a light of a first metamer of a color,
control the plurality of QLEDs to emit light in a second brightness ratio to create a light of a second metamer of the color, and
control the LEDs to operate in conjunction with the plurality of QLEDs to create the light of the first metamer of the color and to create the light of the second metamer of the color.

US Pat. No. 10,141,532

CURABLE ENCAPSULANTS AND USE THEREOF

1. A curable encapsulant comprising:a) from about 70 to about 90 wt %, based on the total weight of the curable encapsulant, of a polyisobutylene having a Mw of from about 1,000 to about 95,000 Da;
b) from about 10 to about 50 wt %, based on the total weight of the curable encapsulant, of a functionalized polyisobutylene having (i) a Mw of from about 1,000 to about 95,000 Da and (ii) greater than one free-radical reactive functional group per polymer chain, wherein the free-radical reactive functional group is selected from the group consisting of terminal (meth)acrylates and/or, terminal acrylates;
c) a free radical initiator; and
d) a UV absorber;
wherein the curable encapsulant is (i) essentially free of an acrylic monomer with Mw less than about 1,000 Da or volatile organic compound with Mw less than about 1,000 Da, (ii) essentially free of a tackifier, and (iii) a hot melt.

US Pat. No. 10,141,531

HYBRID PLANAR-GRADED HETEROJUNCTION FOR ORGANIC PHOTOVOLTAICS

The Regents of the Univer...

1. An organic photosensitive optoelectronic device comprising:two electrodes in superposed relation;
a mixed photoactive layer located between the two electrodes, wherein the mixed photoactive layer is a single layer having first and second boundary interfaces and comprises at least one donor material having a highest occupied molecular orbital (HOMO) energy and at least one acceptor material having a lowest unoccupied molecular orbital energy (LUMO), wherein a concentration of the at least one acceptor material in the mixed layer is at a maximum at the first boundary interface and decreases in the direction of the second boundary interface to form a concentration gradient of the at least one acceptor material within the mixed layer, and wherein a concentration of the at least one donor material in the mixed layer is at a maximum at the second boundary interface and decreases in the direction of the first boundary interface to form a concentration gradient of the at least one donor material within the mixed layer; and
a first photoactive layer adjacent to the mixed photoactive layer and interfacing with the first boundary interface, wherein the first photoactive layer comprises a material having a LUMO energy within 0.3 eV of the LUMO energy of the at least one acceptor material;
wherein the at least one donor material is present in a lesser amount than the at least one acceptor material at the second boundary interface.

US Pat. No. 10,141,529

ENHANCING DRIVE CURRENT AND INCREASING DEVICE YIELD IN N-TYPE CARBON NANOTUBE FIELD EFFECT TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a nanotube over a surface of a substrate;
forming an insulating layer over the nanotube;
exposing end portions of the nanotube;
forming a low work function metal over the end portions of the nanotube;
forming a wetting layer between the low work function metal and the nanotube; and
forming a capping layer over the low work function metal, wherein the capping layer comprises gold.

US Pat. No. 10,141,528

ENHANCING DRIVE CURRENT AND INCREASING DEVICE YIELD IN N-TYPE CARBON NANOTUBE FIELD EFFECT TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A semiconductor device, comprising:a nanotube over a surface of a substrate;
an insulating layer patterned on portions of the nanotube such that end portions of the nanotube are not covered by the insulating layer;
a wetting layer formed directly on the nanotube;
a low work function metal formed directly on top of the wetting layer so as to be over the end portions of the nanotube.

US Pat. No. 10,141,527

FOLDABLE SUBSTRATE, METHOD FOR FORMING THE SAME AND FLEXIBLE DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A foldable substrate, comprising:a plurality of rigid supporting portions separated from each other, every two of which are not in contact with each other; and
a flexible foldable portion connecting two adjacent rigid supporting portions of the plurality of rigid supporting portions;
the flexible foldable portion is made of an organic material;
the plurality of rigid supporting portions each comprises:
an organic base substrate provided with a groove; and
a hard substrate arranged in and adapted to the groove, wherein the hard substrate fits tightly to the groove.

US Pat. No. 10,141,526

PEELING METHOD USING SEPARATING PEELING LAYER AND LAYER TO BE PEELED

Semiconductor Energy Labo...

1. A peeling method comprising:a first step of forming a peeling layer over a first substrate,
a second step of forming a layer to be peeled over the peeling layer, wherein the layer to be peeled comprises a first layer comprising a region in contact with the peeling layer,
a third step of disposing a bonding layer so as to overlap with the peeling layer and the layer to be peeled, wherein the bonding layer is a sheet-like adhesive,
a fourth step of curing the bonding layer,
a fifth step of removing a first portion comprised in the first layer, wherein the first portion comprises a region overlapping with the peeling layer and the bonding layer, and
a sixth step of separating the peeling layer and the layer to be peeled,
wherein the bonding layer cured in the fourth step has a portion having hardness higher than Shore D of 70, and
wherein, in the fifth step, the first portion is removed by laser light irradiation.

US Pat. No. 10,141,525

LIGHT-EMITTING DEVICE, MODULE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:a first flexible substrate comprising a first organic resin material;
a first bonding layer over the first flexible substrate;
an element layer comprising a light-emitting element over the first bonding layer;
a second bonding layer over the element layer; and
a second flexible substrate comprising a second organic resin material over the second bonding layer,
wherein an opening is provided in the element layer, the second bonding layer, and the second flexible substrate,
wherein the light-emitting element is configured to emit light on the second flexible substrate side,
wherein the second flexible substrate has higher average transmittance of light having a wavelength of greater than or equal to 400 nm and less than or equal to 800 nm than the first flexible substrate,
wherein the first flexible substrate is yellower than the second flexible substrate, and
wherein the first organic resin material comprises aramid.

US Pat. No. 10,141,522

COMPOUND, MATERIAL FOR ORGANIC ELECTROLUMINESCENCE ELEMENT, ORGANIC ELECTROLUMINESCENCE ELEMENT, AND ELECTRONIC DEVICE

IDEMITSU KOSAN CO., LTD.,...

1. A compound represented by formula (1):wherein:each of R1 to R6 is independently a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 ring carbon atoms, a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 18 ring carbon atoms, a halogen atom, or a cyano group;
one of R7 to R10 is a single bond bonded to *a, and each of the others of R7 to is independently a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 ring carbon atoms, a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 18 ring carbon atoms, a halogen atom, or a cyano group;
one of R11 to R14 is a single bond bonded to *b, and each of the others of R11 to R14 is independently a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 ring carbon atoms, a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 18 ring carbon atoms, a halogen atom, or a cyano group;
each of R15 to R18 is independently a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 ring carbon atoms, a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 18 ring carbon atoms, a halogen atom, or a cyano group;
with the proviso that each of adjacent two groups selected from R1 to R6, adjacent two groups selected from R7 to R10, adjacent two groups selected from R11 to R14, and adjacent two groups selected from R15 to R18 may be respectively bonded to each other to form a substituted or unsubstituted ring;
each of L1 and L2 is independently a single bond, a substituted or unsubstituted arylene group having 6 to 18 ring carbon atoms, or a substituted or unsubstituted heteroarylene group having 5 to 18 ring atoms; and
each of Ar1 and Ar2 is independently a substituted or unsubstituted aryl group having 6 to 18 ring carbon atoms;
provided that at least one selected from Ar1 and Ar2 is a substituted or unsubstituted fluoranthenyl group.

US Pat. No. 10,141,521

COMPOUND, ORGANIC OPTOELECTRONIC ELEMENT COMPRISING SAME, AND DISPLAY DEVICE

SAMSUNG SDI CO., LTD., Y...

1. A compound represented by the following Chemical Formula 1:
wherein, in Chemical Formula 1,
L is a substituted or unsubstituted C6 to C30 arylene group, or a substituted or unsubstituted C2 to C30 heteroarylene group,
m is an integer ranging from 0 to 3,
Ar is a substituted or unsubstituted C6 to C30 aryl group or a substituted or unsubstituted C2 to C30 heteroaryl group,
X is O, S, SO2 (O?S?O), PO(P?O), NR?, CR?R? or SiR?R?,
R? and R? are each independently hydrogen, deuterium, a halogen, a cyano group, a hydroxyl group, an amino group, a substituted or unsubstituted C1 to C20 amine group, a nitro group, a carboxyl group, a ferrocenyl group, a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C2 to C30 heteroaryl group, a substituted or unsubstituted C1 to C20 alkoxy group, a substituted or unsubstituted C6 to C20 aryloxy group, a substituted or unsubstituted C3 to C40 silyloxy group, a substituted or unsubstituted C1 to C20 acyl group, a substituted or unsubstituted C2 to C20 alkoxycarbonyl group, a substituted or unsubstituted C2 to C20 acyloxy group, a substituted or unsubstituted C2 to C20 acylamino group, a substituted or unsubstituted C2 to C20 alkoxycarbonylamino group, a substituted or unsubstituted C7 to C20 aryloxycarbonylamino group, a substituted or unsubstituted C1 to C20 sulfamoylamino group, a substituted or unsubstituted C1 to C20 sulfonyl group, a substituted or unsubstituted C1 to C20 alkylthiol group, a substituted or unsubstituted C6 to C20 arylthiol group, a substituted or unsubstituted C1 to C20 heterocyclothiol group, a substituted or unsubstituted C1 to C20 ureide group, a substituted or unsubstituted C3 to C40 silyl group, or a combination thereof,
R1 is hydrogen, deuterium, a halogen, a cyano group, a hydroxyl group, an amino group, a substituted or unsubstituted C1 to C20 amine group, a nitro group, a carboxyl group, a ferrocenyl group, a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C2 to C30 heteroaryl group, a substituted or unsubstituted C1 to C20 alkoxy group, a substituted or unsubstituted C6 to C20 aryloxy group, a substituted or unsubstituted C3 to C40 silyloxy group, a substituted or unsubstituted C1 to C20 acyl group, a substituted or unsubstituted C2 to C20 alkoxycarbonyl group, a substituted or unsubstituted C2 to C20 acyloxy group, a substituted or unsubstituted C2 to C20 acylamino group, a substituted or unsubstituted C2 to C20 alkoxycarbonylamino group, a substituted or unsubstituted C7 to C20 aryloxycarbonylamino group, a substituted or unsubstituted C1 to C20 sulfamoylamino group, a substituted or unsubstituted C1 to C20 sulfonyl group, a substituted or unsubstituted C1 to C20 alkylthiol group, a substituted or unsubstituted C6 to C20 arylthiol group, a substituted or unsubstituted C1 to C20 heterocyclothiol group, a substituted or unsubstituted C1 to C20 ureide group, a substituted or unsubstituted C3 to C40 silyl group, or a combination thereof,
when X is O, SO2 (O?S?O), PO(P?O), NR?, CR?R? or SiR?R?, R2 is hydrogen, deuterium, a halogen, a cyano group, a hydroxyl group, an amino group, a substituted or unsubstituted C1 to C20 amine group, a nitro group, a carboxyl group, a ferrocenyl group, a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C2 to C30 heteroaryl group, a substituted or unsubstituted C1 to C20 alkoxy group, a substituted or unsubstituted C6 to C20 aryloxy group, a substituted or unsubstituted C3 to C40 silyloxy group, a substituted or unsubstituted C1 to C20 acyl group, a substituted or unsubstituted C2 to C20 alkoxycarbonyl group, a substituted or unsubstituted C2 to C20 acyloxy group, a substituted or unsubstituted C2 to C20 acylamino group, a substituted or unsubstituted C2 to C20 alkoxycarbonylamino group, a substituted or unsubstituted C7 to C20 aryloxycarbonylamino group, a substituted or unsubstituted C1 to C20 sulfamoylamino group, a substituted or unsubstituted C1 to C20 sulfonyl group, a substituted or unsubstituted C1 to C20 alkylthiol group, a substituted or unsubstituted C6 to C20 arylthiol group, a substituted or unsubstituted C1 to C20 heterocyclothiol group, a substituted or unsubstituted C1 to C20 ureide group, a substituted or unsubstituted C3 to C40 silyl group, or a combination thereof, and
when X is S, R2 is a halogen, a cyano group, a hydroxyl group, an amino group, a substituted or unsubstituted C1 to C20 amine group, a nitro group, a carboxyl group, a ferrocenyl group, a substituted or unsubstituted C1 to C20 alkyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C2 to C30 heteroaryl group, a substituted or unsubstituted C1 to C20 alkoxy group, a substituted or unsubstituted C6 to C20 aryloxy group, a substituted or unsubstituted C3 to C40 silyloxy group, a substituted or unsubstituted C1 to C20 acyl group, a substituted or unsubstituted C2 to C20 alkoxycarbonyl group, a substituted or unsubstituted C2 to C20 acyloxy group, a substituted or unsubstituted C2 to C20 acylamino group, a substituted or unsubstituted C2 to C20 alkoxycarbonylamino group, a substituted or unsubstituted C7 to C20 aryloxycarbonylamino group, a substituted or unsubstituted C1 to C20 sulfamoylamino group, a substituted or unsubstituted C1 to C20 sulfonyl group, a substituted or unsubstituted C1 to C20 alkylthiol group, a substituted or unsubstituted C6 to C20 arylthiol group, a substituted or unsubstituted C1 to C20 heterocyclothiol group, a substituted or unsubstituted C1 to C20 ureide group, a substituted or unsubstituted C3 to C40 silyl group, or a combination thereof.

US Pat. No. 10,141,515

SPACE-THROUGH CHARGE TRANSFER COMPOUND, AND ORGANIC LIGHT EMITTING DIODE AND DISPLAY DEVICE USING THE SAME

LG Display Co., Ltd., Se...

1. A space-through charge transfer compound, comprising:a naphthalene core;
an electron donor moiety selected from the group consisting of carbazole and phenylcarbazole; and
an electron acceptor moiety selected from the group consisting of pyridine, diazine, triazole, and phenyl benzodiazole,
wherein the electron donor moiety and the electron acceptor moiety are combined to first and eighth positions of the naphthalene core with a benzene linker, respectively.

US Pat. No. 10,141,511

DEPOSITION MASK, APPARATUS FOR MANUFACTURING DISPLAY APPARATUS, AND METHOD OF MANUFACTURING DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A deposition mask extending in a first direction, the deposition mask comprising:a pattern portion comprising a plurality of pattern holes; and
a clamping portion comprising a protrusion portion to be attached to a clamp and an indentation portion formed in a direction toward the pattern portion,
wherein the pattern portion comprises a blocking portion that at least partially overlaps the protrusion portion in the first direction and has an area gradually decreasing in a second direction from the protrusion portion toward the indentation portion, the second direction crossing the first direction.

US Pat. No. 10,141,510

OLED DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

6. A manufacturing method of an organic light emitting diode display panel, comprising manufacturing an anode layer, a light emitting layer and a cathode layer on a base substrate, wherein the method further comprises:manufacturing by an entire-surface coating process a hole transport layer having a first preset thickness between the anode layer and the light emitting layer; and
manufacturing by an inkjet printing process a hole transport layer having a second preset thickness in a first preset region of the hole transport layer having the first preset thickness,
wherein the organic light emitting diode display panel comprises an R pixel region, a G pixel region and a B pixel region, the thickness of the hole transport layer corresponding to the R pixel region being an eighth preset thickness, the thickness of the hole transport layer corresponding to the G pixel region being a ninth preset thickness, and the thickness of the hole transport layer corresponding to the B pixel region being a tenth preset thickness, wherein the eighth preset thickness is smaller than the ninth preset thickness, and the ninth preset thickness is smaller than the tenth preset thickness.

US Pat. No. 10,141,509

CROSSBAR RESISTIVE MEMORY ARRAY WITH HIGHLY CONDUCTIVE COPPER/COPPER ALLOY ELECTRODES AND SILVER/SILVER ALLOYS ELECTRODES

International Business Ma...

1. A method comprising:depositing a first electrode, a first metal cap, a first metal film, and a first hardmask (HM) on a silicon surface, wherein the deposited first metal film contains one or more crystal grains, wherein the one or more crystal grains in the first metal film contain a plurality of respective grain boundaries;
increasing respective sizes of the plurality of respective grain boundaries in the one or more crystal grains in the first metal film by subtractive etching;
forming a resistive random access memory (RRAM) cell, wherein the RRAM cell contains a critical dimension that is inversely proportional to a diameter of each respective crystal grains in the first metal film;
depositing the RRAM cell over the deposited first electrode;
depositing a second electrode, a second metal cap, a second metal film, and a second hardmask (HM) over the deposited RRAM cell, wherein the second metal film contains one or more crystal grains, wherein a diameter of each of the one or more crystal grains of the second film corresponds inversely to the critical dimension of the RRAM cell; and
depositing a spacer over the second HM.

US Pat. No. 10,141,508

CLAMP ELEMENTS FOR PHASE CHANGE MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method for forming cell structures, comprising:forming a mask material having a mask hole, the mask hole formed non-orthogonally relative to a row of contacts;
forming a conductive material and a spacer material over the mask material and in a portion of the mask hole;
removing portions of the conductive material and the spacer material to expose contacts from the row of contacts underlying the mask hole and to form a plurality of conductive elements and a plurality of spacer elements; and
forming a plurality of bit lines over the plurality of conductive elements and spacer elements.

US Pat. No. 10,141,506

RESISTIVE SWITCHING CO-SPUTTERED PT—(NIO—AL2O3)—PT DEVICES

National University of Si...

1. A capacitor-like structure, comprising:a first electrode constructed of a first metal,
a co-sputtered transition metal oxide (TMO) layer on the first electrode, wherein the co-sputtered TMO layer is a nickel oxide (NiO)-aluminum oxide (Al2O3) layer having a composition of substantially 84% NiO and 16% Al2O3, wherein substantially refers to a percentage within ±10%;
a second electrode constructed of a second metal in contact with the co-sputtered TMO layer,
wherein the capacitor-like structure is resistively switchable due to formation and rupture of conducting nano-filaments (CFs) through the co-sputtered TMO layer in response to application of a voltage between the first electrode and the second electrode.

US Pat. No. 10,141,500

MAGNETOELECTRIC CONVERTING ELEMENT AND MODULE UTILIZING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A magnetoelectric converting element comprising:a substrate;
a magnetosensitive layer formed on/over the substrate;
a first insulating layer having a first opening exposing a part of the magnetosensitive layer;
an underlying conductive layer formed on/over the part of the magnetosensitive layer;
a second insulating layer having a second opening exposing a part of the underlying conductive layer; and
a terminal conductor formed on/over the part of the underlying conductive layer,
wherein the second opening is located inside the first opening in plan view, and
wherein an entirety of the terminal conductor is contained within the first opening when viewed in plan.

US Pat. No. 10,141,495

MICROSYSTEMS-BASED METHOD AND APPARATUS FOR PASSIVE DETECTION AND PROCESSING OF RADIO-FREQUENCY SIGNALS

1. A radiofrequency device, comprising:a passive impedance transforming voltage amplifier receivingly connected to an antenna for receiving radiofrequency (RF) signals, the impedance transforming voltage amplifier adapted to produce an RF actuation signal; and
a MEMS switch having a radiofrequency (RF) actuation electrode receivingly connected to the impedance transforming voltage amplifier;
wherein:
the MEMS switch further comprises a DC bias electrode positioned to latch the MEMS switch in a closed position by electrostatic attraction when energized by a suitable voltage;
the MEMS switch further comprises a bridge that physically and electrically contacts at least the DC bias electrode when the MEMS switch is in the closed position; and
the bridge is configured with a mechanical mode of vibration that, when subjected to the RF actuation signal having a fundamental frequency that matches at least one frequency of the said mechanical mode of vibration, allows the MEMS switch to be periodically urged toward the closed position.

US Pat. No. 10,141,493

THERMAL MANAGEMENT FOR SUPERCONDUCTING INTERCONNECTS

Microsoft Technology Lice...

1. An interconnect for coupling a superconducting system and a non-superconducting system, the interconnect comprising:a first end configured for coupling to the superconducting system, wherein the interconnect comprises a superconducting element having a critical temperature; and
a second end configured for coupling to the non-superconducting system, such that during operation of the superconducting system and the non-superconducting system, a first portion of the interconnect near the first end having a first temperature equal to or below the critical temperature of the superconducting element, a second portion of the interconnect near the second end having a second temperature above the critical temperature of the superconducting element, and wherein the interconnect is further configured to reduce a length of the second portion such that temperature substantially over an entire length of the interconnect is maintained at a temperature equal to or below the critical temperature of the superconducting element.

US Pat. No. 10,141,492

ENERGY HARVESTING FOR WEARABLE TECHNOLOGY THROUGH A THIN FLEXIBLE THERMOELECTRIC DEVICE

NIMBUS MATERIALS INC., F...

1. A flexible thermoelectric device, comprising:a lower dielectric layer comprising flexible material to provide structure to the flexible thermoelectric device;
a lower conduction layer comprising a plurality of electrically conductive pads disposed directly on and across a surface of the lower dielectric layer, the plurality of electrically conductive pads comprising a plurality of N-designated conductive pads and a plurality of P-designated conductive pads, where the plurality of electrically conductive pads are arranged in pairs such that each pair comprises one N-designated conductive pad of the plurality of N-designated conductive pads and one P-designated conductive pad of the plurality of P-designated conductive pads that are adjacent to one another across the surface of the lower dielectric layer, where the N-designated conductive pad and the P-designated conductive pad in each pair are electrically coupled to one another through an electrically conductive lead extending between the N-designated conductive pad and the P-designated conductive pad adjacent to one another in the pair, the electrically conductive lead extending across the surface of the lower dielectric layer, being parallel to lengths of the N-designated conductive pad and the P-designated conductive pad in the pair, and being narrower in width compared to widths of the N-designated conductive pad and the P-designated conductive pad in the pair, where the widths of the N-designated conductive pad and the P-designated conductive pad are a dimension perpendicular to the length thereof;
a plurality of N-type thin film thermoelectric conduits, each N-type thin film thermoelectric conduit on top of a respective N-designated conductive pad of the plurality of N-designated conductive pads, each N-type thin film thermoelectric conduit having a top surface and a bottom surface, where the bottom surface directly contacts the respective N-designated conductive pad, and the top surface is opposite to the bottom surface;
a plurality of P-type thin film thermoelectric conduits, each P-type thin film thermoelectric conduit on top of a respective P-designated conductive pad of the plurality of P-designated conductive pads, each P-type thin film thermoelectric conduit having a top surface and a bottom surface, where the bottom surface directly contacts the respective P-designated conductive pad, and the top surface is opposite to the bottom surface;
an internal dielectric layer comprising a flexible dielectric material extending across the top surfaces of all the N-type thin film thermoelectric conduits and all the P-type thin film thermoelectric conduits, the internal dielectric layer being electrically insulating, and a surface of the internal dielectric layer being parallel to the top surfaces of each N-type thin film thermoelectric conduit and each P-type thin film thermoelectric conduit;
a thermal insulator to fill a space around each N-type thin film thermoelectric conduit and each P-type thin film thermoelectric conduit, the thermal insulator and the internal dielectric layer being laminated on top of the N-type thin film thermoelectric conduits and the P-type thin film thermoelectric conduits;
a plurality of contact holes extending through the internal dielectric layer and the thermal insulator such that each contact hole extends through a thickness of the internal dielectric layer directly into a thickness of the thermal insulator, and ends on the top surface of the respective N-type thin film thermoelectric conduit or the respective P-type thin film thermoelectric conduit;
a plurality of electrically conductive contacts, each electrically conductive contact fills a respective contact hole of the plurality of contact holes such that each electrically conductive contact extends perpendicularly through the respective contact hole from the top surface of the respective N-type thin film thermoelectric conduit or the respective P-type thin film thermoelectric conduit, through the thermal insulator, and through the thickness of the internal dielectric layer, where each electrically conductive contact includes an outward extension that emerges outward from the respective contact hole above the internal dielectric layer;
a plurality of another electrically conductive leads, each of which bridges between the outward extension of a first respective electrically conductive contact of the plurality of electrically conductive contacts outwardly extending from the N-type thin film thermoelectric conduit on the N-designated conductive pad of a first pair of the pairs and the outward extension of a second respective electrically conductive contact of the plurality of electrically conductive contacts outwardly extending from the P-type thin film thermoelectric conduit on the P-designated conductive pad in a second pair of the pairs, where the first pair and the second pair are adjacent to each other, such that all N-type and P-type thin film thermoelectric conduits of the flexible thermoelectric device are connected in series by the electrically conductive lead in each pair and the another electrically conductive leads, each another electrically conductive lead being disposed directly on the top surface of the internal dielectric layer between the outward extension of the first respective electrically conductive contact and the outward extension of the second respective electrically conductive contact; and
an upper dielectric layer comprising flexible material on top of the plurality of another electrically conductive leads to provide structure to the flexible thermoelectric device,
wherein each N-type thin film thermoelectric conduit and each P-type thin film thermoelectric conduit comprises thermoelectric material no thicker than 50 microns, and
wherein the flexible thermoelectric device is bendable to fit a shape of a target platform in which the flexible thermoelectric device is used to harvest thermal energy.

US Pat. No. 10,141,491

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device comprising:providing an undivided base having a first main surface and a second main surface on the opposite side from the first main surface, the undivided base having conductive patterns disposed on the first main surface and conductive patterns disposed on the second main surface;
mounting a plurality of light emitting elements on the conductive patterns on the first main surface;
forming a light reflecting member that integrally covers side surfaces of the light emitting elements and the first main surface of the undivided base; and
after the forming of the light reflecting member, forming at least one groove on the second main surface of the undivided base at a position corresponding to a space between the light emitting elements so that the groove reaches the first main surface and the undivided base is divided into a plurality of base members without a further step of separating the light reflecting member.

US Pat. No. 10,141,488

LIGHTING DEVICE

NICHIA CORPORATION, Anan...

1. A lighting device comprising:a lightguide panel having an end face that is a light-receiving surface; and
a light-emitting device that emits light toward the end face of the lightguide panel, the light-emitting device including:
a light-emitting element; and
a first light-transmissive member located between the end face of the lightguide panel and the light-emitting element, the first light-transmissive member having a plurality of protrusions on a surface thereof, wherein
at least one of the plurality of protrusions is in direct contact with the end face of the lightguide panel.

US Pat. No. 10,141,487

COVER FOR LIGHT EMITTER

SHINKO ELECTRIC INDUSTRIE...

1. A cover for a light emitter having one or more light emitting devices, comprising:a glass plate having an upper face, a lower face, and a peripheral side surface;
a frame made of metal having an opening smaller than the glass plate; and
a low melting glass having a lower melting point than the glass plate, the glass plate being sealed to the frame with the low melting glass to close the opening,
wherein the frame has an encircling step formed on a side thereof to which the glass plate is sealed,
wherein the encircling step includes:
a placement face situated at a recessed position relative to an upper surface of the frame, the placement face being in contact with a perimeter of the lower face of the glass plate to have the glass plate placed thereon; and
a wall face connecting the upper surface of the frame and the placement face,
wherein the wall face includes first wall faces situated at opposite ends of each inner side of the encircling step and a second wall face situated between the first wall faces, and
the second wall face includes a face extending at a smaller inclination angle than the first wall faces with respect to the placement face, and
wherein gaps between the first wall faces and the peripheral side surface of the glass plate and a gap between the second wall face and the peripheral side surface of the glass plate are filled with the low melting glass.

US Pat. No. 10,141,486

PROCESS METHOD USING ORGANIC SILICONE RESIN PHOTOCONVERTER TO BOND-PACKAGE LED BY TANDEM ROLLING

Jiangsu Cherrity Optronic...

1. A process method for bond-packaging an LED using an organic silicone resin photoconverter by tandem rolling, comprising the following continuous process flow: preparation of a semi-cured photoconversion sheet, pseudo-curing of the semi-cured photoconversion sheet, preparation of a flip chip LED array sheet, forming of LED package elements by dual-roller roll-bonding, curing of the LED package elements, and cutting of the LED package elements, wherein the process comprises the following basic steps:step 1: preparation of a semi-cured photoconversion sheet: obtaining the semi-cured photoconversion sheet formed of a first protective film, a semi-cured photoconversion film, and a second protective film, wherein the semi-cured photoconversion film comprises semi-cured organic silicone resin and a photoconversion material;
step 2: pseudo-curing of the semi-cured photoconversion sheet: in a vacuum condition, by means of low-temperature freezing, pseudo-curing the semi-cured photoconversion sheet obtained in step 1, to obtain a pseudo-cured photoconversion sheet;
step 3: preparation of a flip chip LED array sheet: obtaining the flip chip LED array sheet, flip chip LEDs in the flip chip LED array sheet being arranged on a carrier film in an array manner, wherein the flip chip LEDs being arranged in an array manner means arrangement in an array by using an individual flip chip LED as a unit or arrangement in an array by using a flip chip LED assembly as a unit, and the flip chip LED assembly is formed of two or more individual flip chip LEDs;
step 4: forming of LED package elements by dual-roller roll-bonding: in a vacuum condition, removing the second protective film of the pseudo-cured photoconversion sheet in step 2, to obtain the pseudo-cured photoconversion sheet containing no protective film on a single side, then enabling the pseudo-cured photoconversion sheet to turn from a pseudo-cured state to a semi-cured state by means of heating or/and illumination, and subsequently performing dual-roller roll-bonding on the semi-cured photoconversion sheet and the flip chip LED array sheet, such that the flip chip LEDs in the flip chip LED array are bonded to and inserted in the semi-cured photoconversion sheet, to obtain the LED package elements;
step 5: curing of the LED package elements: in a vacuum condition, curing the LED package elements by means or heat curing or/and photocuring, to obtain the cured LED package elements; and
step 6: cutting of the LED package elements: removing the first protective film of the cured LED package elements in step 5, and cutting the cured LED package elements, to obtain finished LED package elements having slits for splitting into single LED package elements.

US Pat. No. 10,141,485

VEHICLE LAMP USING SEMICONDUCTOR LIGHT EMITTING DEVICE

LG Electronics Inc., Seo...

1. A lamp for a vehicle, comprising:a light source unit configured to emit light, the light source unit comprising:
a substrate that includes a wiring electrode,
a plurality of semiconductor light emitting devices electrically connected to the wiring electrode,
a plurality of phosphor layers that respectively cover the plurality of semiconductor light emitting devices and that are configured to convert wavelengths of light, and
barrier ribs disposed on the substrate and configured to reflect light, the barrier ribs being interposed between the plurality of semiconductor light emitting devices,
wherein a height of each of the barrier ribs exceeds a height of each of the plurality of semiconductor light emitting devices in a thickness direction of the plurality of semiconductor light emitting devices.

US Pat. No. 10,141,479

LIGHT-EMITTING PACKAGE STRUCTURE PROVIDED WITH PREDETERMINED VIEW ANGLE

LITE-ON OPTO TECHNOLOGY (...

1. A light-emitting package structure, comprising:a carrier substrate having a circuit structure;
a thin film chip disposed on the carrier substrate and having an epitaxial structure and at least two electrodes disposed on a bottom surface of the epitaxial structure, the at least two electrodes contacting the circuit structure;
an underfill material disposed in a gap between the at least two electrodes of the thin film chip for supporting the thin film chip;
a wavelength converting layer at least covering the epitaxial structure of the thin film chip; and
a reflecting wall surrounding the wavelength converting layer and the thin film chip, wherein a reflectivity of the reflecting wall is larger than 70%, and a ratio between a total luminous intensity of light emitted by the light-emitting package structure in an illumination angle of ±40 degrees and a luminous intensity area within a view angle of light emitted by the light-emitting package structure is larger than 0.7.

US Pat. No. 10,141,478

STRUCTURE OF A REFLECTIVE ELECTRODE AND AN OHMIC LAYER OF A LIGHT EMITTING DEVICE

LG INNOTEK CO., LTD., Se...

1. A light emitting device comprising:a substrate;
a first conductive layer on the substrate;
a second conductive layer on the first conductive layer;
a metal layer on the second conductive layer;
a light emitting structure on the metal layer and the second conductive layer, the light emitting structure including a first semiconductor layer containing AlGaN, an active layer, and a second semiconductor layer containing AlGaN;
a first electrode on the light emitting structure; and
a passivation layer disposed on a side surface of the light emitting structure,
wherein a first region of the metal layer directly contacts with the light emitting structure, a second region of the second conductive layer directly contacts with the light emitting structure, and a third region of the first conductive layer directly contacts with the light emitting structure,
wherein the second region of the second conductive layer is disposed at a periphery of the first region of the metal layer,
wherein a portion of the passivation layer including a first roughness is disposed on a top surface of the light emitting structure,
wherein a first portion of the top surface of the light emitting structure includes a second roughness,
wherein the second region of the second conductive layer and the first portion of the top surface of the light emitting structure are vertically overlapped,
wherein a width of the second conductive layer is greater than a width of the metal layer, and
wherein a thickness from a top surface of the substrate to a bottom surface of the metal layer at a center portion of the metal layer is less than a thickness from the top surface of the substrate to the bottom surface of the metal layer at an edge portion of the metal layer.

US Pat. No. 10,141,474

PASSIVATION METHOD

Taiwan Semiconductor Manu...

1. A method of passivating an absorber layer of a solar cell module, comprising the steps of:providing an absorber layer formed over a substrate, the absorber layer having a planar upper surface; and
forming a porous alumina passivation layer on the upper surface of the absorber layer, wherein the porous alumina passivation layer has a passivating region directly over and in contact with the upper surface of the absorber layer operating to passivate the absorber layer and wherein in the passivating region the passivation layer has pore dimensions sufficient to provide a non-planar, textured upper surface;
conformably forming a buffer layer over the passivating region of the passivation layer; and
conformably forming a transparent conducting oxide layer over the buffer layer, thereby providing the buffer layer and transparent conducting oxide layer each with a non-planar, textured upper surface over the passivating region of the passivation layer,
wherein the non-planar, textured upper surfaces of the porous alumina passivation layer, buffer layer and transparent conducting oxide layer provide the solar cell with increased light scattering effect, as compared to planar, non-textured upper surfaces, as light passes through the textured upper surfaces to an area of the upper surface of the absorber layer in contact with and passivated by the passivating region of the porous alumina passivation layer.

US Pat. No. 10,141,472

PHOTODIODE STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A method, comprising:forming a waveguide structure in a dielectric layer;
forming an amorphous Ge material over an upper surface of the waveguide structure in a back end of the line (BEOL) metal layer; and
crystallizing the amorphous Ge material into a crystalline Ge structure by an annealing process with a metal layer in contact with the Ge material,
wherein the forming of the Ge material adjacent to the waveguide structure in a back end of the line (BEOL) metal layer comprises:
depositing a barrier layer of nitride directly on the upper surface of the waveguide structure, followed by a patterning of the barrier layer;
depositing the amorphous Ge material directly on the barrier layer, followed by a patterning of the amorphous Ge material;
opening a via to expose portions of the amorphous Ge material;
depositing the metal layer on the amorphous Ge material through the opening of the via; and
crystallizing of the amorphous Ge material through the annealing process to form the crystalline Ge structure aligned with the via.

US Pat. No. 10,141,470

PHOTODIODE TYPE STRUCTURE, COMPONENT AND METHOD FOR MANUFACTURING SUCH A STRUCTURE

1. A photodiode type structure intended to receive electromagnetic radiation in a given wavelength range, the photodiode type structure comprising:a support including at least one semiconductor layer, the semiconductor layer including of a first semiconductor zone of a first type of conductivity, the first semiconductor zone being made of a first semiconductor material having a forbidden band gap such that the first semiconductor zone is transparent in the given wavelength range;
a mesa in contact with the semiconductor layer, the mesa including a second semiconductor zone, known as absorption zone, the second semiconductor zone being of a second type of conductivity opposite to the first type of conductivity so as to form a semiconductor junction having a space charge zone, the second semiconductor zone being made of a second semiconductor material having a forbidden band gap suited to favoring the absorption of electromagnetic radiation, the second semiconductor zone having a concentration of majority carriers such that the second semiconductor zone is included within the space charge zone, and is thus depleted, in the absence of polarization of the structure; and
a third semiconductor zone of the second type of conductivity made of a third semiconductor material having a forbidden band gap such that the third semiconductor zone is transparent in the given wavelength range, the third semiconductor zone being interposed between the first and the second semiconductor zones while being at least partially arranged in the semiconductor layer and while forming the semiconductor junction with the first semiconductor zone in the semiconductor layer, wherein the third semiconductor zone also forming with the second semiconductor zone a potential barrier for minority carriers of the second semiconductor zone.

US Pat. No. 10,141,467

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

LG ELECTRONICS INC., Seo...

1. A solar cell comprising:a semiconductor substrate with a front surface, a back surface, and an edge connecting the front surface and the back surface;
a first conductive type region formed on substantially the entirety of the front surface of the semiconductor substrate;
a second conductive type region formed on the back surface of the semiconductor substrate, the second conductive type region being spaced from an edge of the semiconductor substrate and having a conductive type different from that of the first conductive type region;
an isolation portion formed at a perimeter of the second conductive type region on the back surface of the semiconductor substrate, wherein the isolation portion has a lower dopant concentration than the second conductive type region;
an anti-reflective film formed over substantially the entirety of the first conductive type region;
a passivation film formed over substantially the entirety of the second conductive type region and the isolation portion;
a first electrode connected to the first conductive type region through the anti-reflective film; and
a second electrode connected to the second conductive type region through the passivation film; wherein the semiconductor substrate comprises a base region in which the first and second conductive type regions are not disposed;
wherein the second conductive type region has a boundary portion in direct contact with the isolation portion, and in which a doping concentration of the boundary portion is changed linearly in relation to a distance from the edge of the semiconductor substrate at a predetermined slope,
wherein the second conductive type region comprises an effective area in direct contact with the boundary portion; wherein a doping concentration of the base region is a first concentration and a doping concentration of the effective area is a second concentration, the doping concentration of the boundary portion changes from a third concentration less than the second concentration and greater than the first concentration to the first concentration, and the third concentration is 1×1015/cm2 or more;
wherein a width of the isolation portion is smaller than a distance between the edge of the semiconductor substrate and an end of the second electrode that is closest to the edge of the semiconductor substrate,
wherein the second electrode is connected to the effective area of the second conductive type region,
wherein the second electrode includes:
a plurality of finger electrodes extended in a first direction; and
a plurality of bus bar electrodes extended in a second direction crossing the first direction, and
wherein the second conductive type region includes a first portion corresponding to the plurality of finger electrodes.

US Pat. No. 10,141,466

SUBSTRATE FOR SOLAR CELL, AND SOLAR CELL

SHIN-ETSU CHEMICAL CO., L...

1. A method for manufacturing a solar cell using a silicon substrate of square shape with corners as viewed in plan view, having a first corner and a second corner not diagonal to the first corner, which is provided with a chamfer at the first corner or a notch at or near the first corner and with a notch at or near the second corner or a chamfer at the second corner, the notch or chamfer at the second corner is selected to be different from the chamfer or notch at the first corner,wherein the first and second corners are used to identify the direction of the substrate and discriminate the front and back surfaces of the substrate during manufacturing.

US Pat. No. 10,141,462

SOLAR CELLS HAVING DIFFERENTIATED P-TYPE AND N-TYPE ARCHITECTURES

SunPower Corporation, Sa...

1. A solar cell, comprising:an N-type semiconductor substrate having a light-receiving surface and a back surface;
a plurality of N-type polycrystalline silicon regions disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate; and
a plurality of P-type polycrystalline silicon regions disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate, wherein a total area of the plurality of N-type polycrystalline silicon regions is greater than a total area of the plurality of P-type polycrystalline silicon regions in the plurality of corresponding trenches.

US Pat. No. 10,141,461

TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD

INTERNATIONAL BUSINESS MA...

1. A multi junction photovoltaic device, comprising:a semiconductor layer having substantially symmetrical pyramidal shapes with (111) facets exposed to form a textured surface;
a first p-n junction formed directly on the textured surface; and
at least one other p-n junction formed over the first p-n junction and following the textured surface.

US Pat. No. 10,141,458

VERTICAL GATE GUARD RING FOR SINGLE PHOTON AVALANCHE DIODE PITCH MINIMIZATION

OmniVision Technologies, ...

1. A photon detection device, comprising:a single photon avalanche diode (SPAD) disposed in a first region of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined at an interface between an n doped layer and a p doped layer of the SPAD in the first region of the first semiconductor layer;
a vertical gate structure disposed in the first semiconductor layer proximate to the SPAD, wherein the vertical gate structure surrounds the SPAD to isolate the SPAD in the first region of the first semiconductor layer from a second region of the first semiconductor layer on an opposite side of the vertical gate structure, wherein the n doped layer and the p doped layer of the SPAD laterally extend within the first region of the first semiconductor layer to contact the vertical gate structure; and
a depletion layer generated around a perimeter of the SPAD at an interface of the vertical gate structure and the p doped layer in response to a gate bias voltage coupled to the vertical gate structure, wherein the depletion layer isolates the SPAD from the second region of the first semiconductor layer on the opposite side of the vertical gate structure.

US Pat. No. 10,141,457

SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A solar cell comprising:a crystalline silicon semiconductor substrate of a first conductive type;
an emitter region having a second conductive type different from the first conductive type and at a first surface of the crystalline silicon semiconductor substrate, wherein the emitter region forms a p-n junction along with the crystalline silicon semiconductor substrate;
a silicon carbide layer directly on a second surface opposite the first surface of the crystalline silicon semiconductor substrate configured to form a first charge accumulation layer in the second surface of the crystalline silicon semiconductor substrate, and having a first impurity doping concentration of the first conductive type, the first charge accumulation layer to accumulate charge caused by a difference in band gap between the crystalline silicon semiconductor substrate and the silicon carbide layer;
a first electrode on the first surface of the crystalline silicon semiconductor substrate and coupled to the emitter region;
a heavily doped region under the first electrode and containing impurities of a second conductive type at a doping concentration higher than the crystalline semiconductor substrate and a second charge accumulation layer;
a second electrode on the second surface of the crystalline silicon semiconductor substrate and coupled to the crystalline silicon semiconductor substrate;
a surface field region partially in the second surface of the crystalline silicon semiconductor substrate and having a second impurity doping concentration of the first conductive type higher than the first impurity doping concentration of the silicon carbide layer; and
an anti-reflection part on the emitter region,
wherein the silicon carbide layer has a plurality of openings and the second electrode contacts the surface field region through the plurality of openings of the silicon carbide layer,
wherein a conduction band average energy level of the crystalline silicon semiconductor substrate is higher than a conduction band average energy level of the silicon carbide layer, and
wherein an amount of impurities contained of the silicon carbide layer is 1×1018/cm3 to 5×1020/cm3, and
wherein the emitter region is formed of a silicon carbide to form the second charge accumulation layer in the first surface of the crystalline silicon semiconductor substrate to accumulate charge caused by a difference in band gap between the crystalline silicon semiconductor substrate and the emitter region.

US Pat. No. 10,141,454

FIELD-EFFECT TRANSISTORS HAVING BLACK PHOSPHORUS CHANNEL AND METHODS OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a phosphorene-containing layer over a substrate, wherein a channel region, a source region, and a drain region are defined in the phosphorene-containing layer, and further wherein the channel region is disposed between a source region and a drain region; and
forming a passivation layer over the source region and the drain region defined in the phosphorene-containing layer.

US Pat. No. 10,141,453

SEMICONDUCTOR DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A semiconductor device comprising:a substrate; and
a thin film transistor supported on the substrate, the thin film transistor including a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,
a signal line connected to the source electrode and a scanning line connected to the gate electrode, the scanning line extending along a first direction and the signal line extending along a second direction crossing the first direction,wherein:the drain electrode, the source electrode and the oxide semiconductor layer are arranged in line along either the first direction or the second direction;
the source electrode is shaped so as to project along the second direction, and the drain electrode is arranged so as to oppose the source electrode with the oxide semiconductor layer interposed therebetween;
the drain electrode is shaped so as to project toward the oxide semiconductor layer;
a width W1 and a width W2 satisfy a relationship |W1?W2|?1 ?m, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects;
the width W1 and the width W2 are 3 ?m or more and 6 ?m or less;
the oxide semiconductor layer and the drain electrode are misaligned from each other in the first direction; and
a width W3 is 1 ?m or more and is less than the width W1, where the width W3 is a width in the first direction of an overlapping portion between the oxide semiconductor layer and the drain electrode.

US Pat. No. 10,141,448

VERTICAL FETS WITH DIFFERENT GATE LENGTHS AND SPACER THICKNESSES

International Business Ma...

1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:patterning fins having a uniform fin height in a substrate, wherein at least a first one of the fins comprises a vertical fin channel of a first VFET and wherein at least a second one of the fins comprises a vertical fin channel of a second VFET;
forming bottom source and drains at a base of the fins, wherein the bottom source and drains are doped;
forming first bottom spacers on the bottom source and drains at the base of the fins;
selectively forming second bottom spacers on the first bottom spacers at the base of the at least one second fin, wherein the second bottom spacers are configured to serve as a dopant source;
annealing the substrate under conditions sufficient to drive dopants i) from the bottom source and drains into the at least one first fin and ii) from the bottom source and drains and from the second bottom spacers into the at least one second fin, forming bottom junctions at the base of the at least one first fin having a height H1 and bottom junctions at the base of the at least one second fin having a height H2, wherein H2>H1;
forming gates along sidewalls of the fins above the bottom source and drains, wherein the gates along the sidewalls of the at least one first fin have a gate length Lg1 and the gates along the sidewalls of the at least one second fin have a gate length Lg2, wherein Lg1>Lg2 based on H2>H1;
forming top spacers above the gates at tops of the fins; and
forming top source and drains above the top spacers at the tops of the fins.

US Pat. No. 10,141,447

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor device, comprising:an active fin extended in a first direction on a substrate;
a gate structure extended in a second direction, wherein the gate structure intersects the active fin, and covers an upper portion of the active fin;
a source/drain region on the active fin adjacent to the gate structure;
a silicide layer on the source/drain region;
a contact plug connected to the source/drain region; and
a void between the silicide layer and the contact plug.

US Pat. No. 10,141,444

OXIDE THIN-FILM TRANSISTOR WITH ILLUMINATED OHMIC CONTACT LAYERS, ARRAY SUBSTRATE AND METHODS FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an oxide thin-film transistor, comprising:forming a pattern of a light shielding layer on a base substrate that is made of a light-transmissive material, wherein the light shielding layer is made of an organic material;
forming a pattern of an oxide semi-conductor layer above the base substrate, wherein an orthographic projection of the pattern of the light shielding layer onto the base substrate is completely located within and is smaller than an orthographic projection of the pattern of the oxide semi-conductor layer onto the base substrate;
providing the ultraviolet light source at a side of the base substrate away from the light shielding layer;
illuminating, by the ultraviolet light source, two opposite boundary regions of the pattern of the oxide semi-conductor layer that are not shielded by the light shielding layer, wherein the illuminated two opposite boundary regions of the pattern of the oxide semi-conductor layer form ohmic contact layers and a region of the pattern of the oxide semi-conductor layer that is not illuminated forms a semi-conductor active layer;
forming a gate insulator on the semi-conductor active layer and forming a gate electrode on the gate insulator; and
forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are connected to the semi-conductor active layer via the ohmic contact layers respectively,
wherein the oxide thin-film transistor is of a top-gate structure, and the gate electrode is arranged between the semi-conductor active layer and the source electrode and the drain electrode in a direction in which the semi-conductor active layer, the gate insulator, and the gate electrode are stacked, and the light shielding layer is sandwiched between the oxide semi-conductor layer and the base substrate.

US Pat. No. 10,141,441

VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE

INTERNATIONAL BUSINESS MA...

1. A method of making a vertical transistor device, the method comprising:forming a front gate and a back gate opposite a major surface of a substrate, the front gate and the back gate being symmetric and arranged on opposing sides of a channel between the front gate and the back gate, the channel extending from a drain to a source;
forming a mask to cover the front gate;
removing the back gate; and
replacing the back gate with a layer of insulator and another back gate stack, the another back gate stack only covering a junction between the channel and the source, and remaining portions of the back gate being the layer of insulator.

US Pat. No. 10,141,438

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
a first III-V compound layer over the substrate;
a first passivation layer on the first III-V compound layer;
a source electrode penetrating the first passivation layer to electrically contact the first III-V compound layer; and
a drain electrode penetrating the first passivation layer to electrically contact the first III-V compound layer,
wherein a lower portion of the source electrode directly surrounded by the first passivation layer, the lower portion comprising:
an upper part having a first width; and
a lower part having a second width, the first width being greater than the second width; and
wherein an upper portion of the source electrode further comprises a third width measured from one side to an opposite side of an outer circumference of the upper portion, the third width being smaller than the first width.

US Pat. No. 10,141,437

EXTREME HIGH MOBILITY CMOS LOGIC

Intel Corporation, Santa...

1. A transistor, comprising:a doped silicon semi-insulating substrate;
a buffer layer disposed above the doped silicon semi-insulating substrate;
a bottom barrier layer disposed above the buffer layer wherein the bottom barrier layer comprises a material different than the buffer layer;
a group III-V material quantum well layer disposed above the bottom barrier layer;
a top barrier layer disposed above the group III-V material quantum well layer;
a gate stack disposed above the top barrier layer, the gate stack comprising:
a high-k gate dielectric layer disposed above the top barrier layer; and
a metal gate electrode disposed above the high-k gate dielectric layer; and
a semiconductor cap layer on an etch stop layer on the top barrier layer, wherein the gate stack is in an opening through the semiconductor cap layer.

US Pat. No. 10,141,436

TUNNEL FIELD EFFECT TRANSISTOR HAVING ANISOTROPIC EFFECTIVE MASS CHANNEL

Purdue Research Foundatio...

1. A tunnel field effect transistor (TFET) device, comprising:a substrate;
heavily doped source and drain regions disposed at opposite ends of the substrate separated by a channel region, where the channel region is intrinsic or lightly doped with doping of less than 1018/cm3 and the source and drain regions doped with doping of between about 1018/cm3 to about 1021/cm3, collectively forming a structure wherein the structure is PiN or NiP;
a gate terminal separated from the channel region by a dielectric layer;
a source and drain terminal coupled to the source and drain regions, respectively,
the channel region comprising a channel material having a first effective mass along a longitudinal axis extending from the source region to the drain region and a second effective mass along a lateral axis perpendicular to the longitudinal axis, wherein a ratio of the first effective mass to the second effective mass is between 1 and 50, the channel region comprising a first substantially parallelogram portion having a first length defined along a longitudinal axis extending from the source region to the drain region and a second substantially parallelogram portion connected to the first substantially parallelogram portion having a second length defined along the longitudinal axis and larger than the first length, the TFET device having an effective channel length defined along the longitudinal axis that is an average of the first and second lengths.

US Pat. No. 10,141,429

FINFET HAVING ISOLATION STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of making a transistor, comprising:forming a fin structure protruding from an upper surface of a substrate, the fin structure extending along a first direction and comprising a lower portion and an upper portion;
forming a first isolation structure over the upper surface of the substrate and surrounding the lower portion of the fin structure;
patterning a recess in the fin structure;
depositing a second isolation structure in the recess;
forming a gate structure over the fin structure and extending along a second direction different from the first direction, the gate structure and the fin structure defining a non-overlapping region in the upper portion of the fin structure, wherein the patterning the recess in the fin structure comprises patterning the recess in the non-overlapping region of the fin structure; and
forming a drain contact region in the non-overlapping region of the fin structure, the second isolation structure being between the drain contact region and the gate structure.

US Pat. No. 10,141,428

FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a plurality of fins from a first material, the plurality of fins formed over a substrate and defining troughs therebetween;
depositing a semiconductor layer formed from a second material over the plurality of fins, the second material being different than the first material;
depositing dielectric material covering the plurality of fins and the semiconductor layer, the dielectric material defining dielectric regions;
diffusing the second material from the semiconductor layer into an entirety of each fin of the plurality of fins;
removing the dielectric regions; and
planarizing an upper surface of the dielectric regions to be planar with an upper surface of the plurality of fins.

US Pat. No. 10,141,427

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING GATE PATTERN, MULTI-CHANNEL ACTIVE PATTERN AND DIFFUSION LAYER

Samsung Electronics Co., ...

1. A method for fabricating a semiconductor device comprising:forming a multi-channel active pattern protruding from an isolation layer;
forming a dummy gate pattern on the multi-channel active pattern, the dummy gate pattern overlapping a portion of the multi-channel active pattern;
after forming the dummy gate pattern on the multi-channel active pattern, forming a pre-liner layer on a top surface of the multi-channel active pattern not overlapping the dummy gate pattern;
forming an impurity supply layer on a top surface of the pre-liner layer that is on the multi-channel active pattern not overlapping the dummy gate pattern;
forming a first diffusion layer in the multi-channel active pattern not overlapping the dummy gate pattern by performing a first thermal process on the impurity supply layer at a first temperature; and
after forming the first diffusion layer in the multi-channel active pattern not overlapping the dummy gate pattern, forming a second diffusion layer in the multi-channel active pattern along an outer periphery of the multi-channel active pattern not overlapping the dummy gate pattern by performing a second thermal process on the impurity supply layer at a second temperature.

US Pat. No. 10,141,426

VERTICAL TRANSISTOR DEVICE

INTERNATIONAL BUSINESS MA...

1. A vertical transistor device comprising:a semiconductor substrate including a substrate material;
a first semiconductor fin forming a vertical channel region comprising a semiconductor material arranged on the semiconductor substrate;
a first source/drain region comprising a first portion directly vertically beneath the semiconductor material of the first semiconductor fin and a second portion, the first portion comprising a doped portion of the semiconductor substrate arranged below and in contact with the second portion, the second portion comprising a doped epitaxially grown semiconductor material, the doped epitaxially grown semiconductor material being a dissimilar material from the substrate material, and the first source/drain region comprising a graduated doping concentration profile that extends from the doped epitaxially grown semiconductor material to the vertical channel region;
a first spacer layer arranged directly on the second portion of the first source/drain region;
a first gate stack arranged directly on the first spacer layer, the first gate stack comprising gate dielectric material, a work function metal, and a conductive metal; a sidewall of the first gate stack directly contacting a sidewall of the first semiconductor fin, and a top surface of the first semiconductor fin arranged above a top surface of the first gate stack; and
a second spacer layer arranged directly on the first gate stack and extending higher than the first semiconductor fin;
wherein the first gate stack of the vertical transistor device wraps around horizontal sides of the vertical channel region, and the conductive metal of the first gate stack is arranged in contact the second spacer layer.

US Pat. No. 10,141,424

METHOD OF PRODUCING A CHANNEL STRUCTURE FORMED FROM A PLURALITY OF STRAINED SEMICONDUCTOR BARS

IBM CORPORATION, Yorktow...

1. A Method for fabricating a structure with semiconducting bars suitable for forming at least one transistor channel, including:providing at least a semiconducting structure on a substrate, composed of an alternation of first bars based on at least a first material and second bars based on at least a second material, the second material being a semiconducting material, the first bars and the second bars being stacked, then
forming a sacrificial gate and first insulating spacers on each side of the sacrificial gate, then
removing regions of the stack located on each side of the insulating spacers, then
removing end portions from the first bars by selective etching of the first material relative to the second material so as to expose spaces around the ends of the second bars,
forming of internal spacers in said spaces around said ends of the second bars, then
forming of semiconducting source and drain blocks by growth of at least one semiconducting material on each side of the insulating spacers and the internal spacers,
then,
removing exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around a central portion of the second bars, then
growing or depositing a layer of a semiconducting material around the second bars in the opening such that the semiconducting material is in contact with the second bars, the semiconducting material having a mesh parameter different from the mesh parameter of the second material so as to induce a strain on the layer of the semiconducting material.

US Pat. No. 10,141,419

TWO-STEP DUMMY GATE FORMATION

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a semiconductor fin between opposite portions of the isolation regions, wherein the semiconductor fin is higher than top surfaces of the isolation regions;
a gate stack on a top surface and opposite sides of the semiconductor fin; and
a gate spacer contacting a sidewall of the gate stack, wherein the gate spacer comprises:
a lower portion having a first inner edge contacting a sidewall of the gate stack; and
an upper portion over the lower portion, the upper portion having a second inner edge contacting the sidewall of the gate stack, wherein the first inner edge and the second inner edge are in different vertical planes.

US Pat. No. 10,141,416

SEMICONDUCTOR STRUCTURE WITH ENLARGED GATE ELECTRODE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

8. A method for manufacturing a semiconductor structure, comprising:forming a trench over a substrate;
forming a gate dielectric layer on sidewalls and a bottom of the trench;
forming a plurality of conductive layers over the gate dielectric layer on the sidewalls and the bottom of the trench;
forming a blocking structure in a lower portion of the trench over the plurality of conductive layers;
etching a portion of each of the plurality of conductive layers not covered by the blocking structure, wherein the etching forms a sloped top surface of each of the plurality of conductive layers, wherein the sloped top surface extends from a termination point level with and interfacing a top surface of the blocking structure upwards towards another termination point closer a nearest sidewall of the trench;
after the etching, removing the blocking structure; and
after removing the blocking structure, depositing at least one additional conductive gate layer over the etched plurality of conductive layers.

US Pat. No. 10,141,415

COMBINED GATE AND SOURCE TRENCH FORMATION AND RELATED STRUCTURE

Infineon Technologies Ame...

1. A method of forming a semiconductor device, said method comprising:forming a semiconductor substrate including a drain region, a drift region above said drain region, a base region above said drift region, and a source region above said base region, said drain region, said drift region and said source region having a first conductivity type and said base region having a second conductivity type opposite said first conductivity type;
forming a gate trench and a first portion of a source trench in said semiconductor substrate and both extending into said drift region to a same first depth in said semiconductor substrate, said first portion of said source trench being wider than said gate trench;
forming a gate electrode in said gate trench;
after forming said gate trench and said first portion of said source trench, forming a second portion of said source trench under said first portion and extending deeper into said drift region than said first portion, said second portion being narrower than said first portion and extending to a second depth in said semiconductor substrate greater than said first depth;
lining sidewalls of said first portion, sidewalls of said second portion and a bottom of said second portion with a dielectric material; and
forming a conductive filler in said source trench, said conductive filler insulated from the surrounding semiconductor substrate by said dielectric material.

US Pat. No. 10,141,412

FIELD EFFECT TRANSISTOR USING TRANSITION METAL DICHALCOGENIDE AND A METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A field effect transistor (FET), comprising:a gate dielectric layer;
a channel layer formed on the gate dielectric layer; and
a gate electrode, wherein:
the channel layer includes a body region having a first side and a second side opposite to the first side, the body region being a channel of the FET,
the channel layer further includes first finger regions each protruding from the first side of the body region and second finger regions each protruding from the second side of the body region,
a source electrode covers the first finger regions, and a drain electrode covers the second finger regions,
the channel layer is a single layer or multiple layers of MoS2,
each of the first finger regions and each of the second finger regions extend along a first direction, and
the first direction corresponds to a zigzag edge structure of the MoS2 layer, which extends perpendicular to atomic bonds located at the edge.

US Pat. No. 10,141,411

TEMPERATURE SENSING SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate of silicon carbide, wherein the semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated through an epitaxial growth technique by depositing the n-type drift region on the semiconductor substrate and then by depositing the p-type body region on the n-type drift region; and
a temperature sensor portion disposed in the semiconductor substrate and separated from the drift region by the body region,
wherein the body region extends from the temperature sensor portion through the areas having a plurality of trench gates, and
wherein the temperature sensor portion comprises:
an n-type cathode region being in contact with the body region; and
a p-type anode region separated from the body region by the cathode region.

US Pat. No. 10,141,406

TENSILE STRAINED NFET AND COMPRESSIVELY STRAINED PFET FORMED ON STRAIN RELAXED BUFFER

International Business Ma...

1. A fabrication method, comprising:obtaining a structure including a substrate and a strain relaxed silicon germanium buffer layer on the substrate;
forming an epitaxial silicon germanium layer on a first region of the strain relaxed buffer layer, the epitaxial silicon germanium layer being doped with dopants of a first conductivity type;
forming a tensile strained layer comprising silicon directly on the epitaxial silicon germanium layer;
forming an epitaxial relaxed layer comprising silicon on a second region of the strain relaxed buffer layer, the epitaxial relaxed layer being doped with dopants of a second conductivity type that is opposite in polarity to the first conductivity type;
forming a compressively strained silicon germanium layer directly on the epitaxial relaxed layer;
electrically isolating the first and second regions;
forming first and second recesses extending respectively within the first and second regions of the strain relaxed silicon germanium buffer layer; and
forming the epitaxial silicon germanium layer within the first recess and forming the epitaxial relaxed layer within the second recess;
wherein the strain relaxed buffer layer has at least a top region having the composition Si1-xGex where x is between 0.2 and 0.3, the epitaxial silicon germanium layer has the composition Si1-yGey where y is equal to or exceeds x by 0.02 or less, and the compressively strained silicon germanium layer has the composition Si1-zGez where z is between 0.2 and 0.3.

US Pat. No. 10,141,405

LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE

International Business Ma...

1. A method of forming a lateral bipolar junction transistor (LBJT) comprising:providing a germanium containing material on a nucleation dielectric layer with a bonding method;
patterning the germanium containing material selectively to the nucleation dielectric layer to form a base region present overlying a pedestal of the passivating layer;
forming emitter and collector extension regions on opposing sides of the base region; and
forming an emitter region and collector region on exposed portions of the nucleation dielectric layer extending into contact with the emitter and collector extension regions.

US Pat. No. 10,141,403

INTEGRATING THIN AND THICK GATE DIELECTRIC NANOSHEET TRANSISTORS ON SAME CHIP

International Business Ma...

13. A semiconductor structure, comprising:a single nanosheet stack formed over a substrate;
a thin gate dielectric nanosheet transistor formed by fabricating a first portion of the single nanosheet stack, the thin gate dielectric nanosheet transistor including a plurality of nanosheets separated from each other by a first distance; and
a thick gate dielectric nanosheet transistor formed by fabricating a second portion of the single nanosheet stack, the thick gate dielectric nanosheet transistor including a plurality of nanosheets separated from each other by a second distance, the second distance being greater than the first distance.

US Pat. No. 10,141,402

FINFET DEVICES

INTERNATIONAL BUSINESS MA...

1. A structure comprising a plurality of fin structures which are supported by lined insulator material, wherein the lined insulator material is provided on an in-situ doped material.

US Pat. No. 10,141,401

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:performing a first plasma etching process on a substrate to form a first trench in the substrate, wherein the first plasma etching process uses a first etching gas and a first deposition gas, the first trench surrounds a first portion of the substrate, the first portion has a top surface and a first inclined surface, the first inclined surface connects the top surface to a bottom surface of the first trench, and the first inclined surface is inclined relative to the top surface at a first angle;
removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench, wherein the second trench surrounds a third portion of the substrate under the first portion, the third portion has a first sidewall, the first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle;
forming an isolation structure in the first trench and the second trench, wherein the isolation structure has a second inclined surface, and the first inclined surface and the second inclined surface form second sidewalls of a recess;
forming a gate insulating layer over the top surface and the first inclined surface, wherein the gate insulating layer extends into the recess and partially covers the second inclined surface, the recess is filled with the gate and the gate insulating layer, and the gate is over the isolation structure partially; and
forming a gate over the gate insulating layer and the isolation structure, wherein the gate crosses the first portion, and the gate extends into the recess.

US Pat. No. 10,141,397

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) forming a first epitaxial layer of a first conductivity type over a semiconductor substrate;
(b) forming a first trench in the first epitaxial layer;
(c) filling the first trench with a semiconductor material of a second conductivity type opposite to the first conductivity type;
(d) after the step (c), forming a second epitaxial layer of the first conductivity type over the first epitaxial layer including the first trench filled with the semiconductor material;
(e) forming a second trench in the second epitaxial layer, the second trench being planarly superposed on the first trench and connected with the first trench;
(f) filling the second trench with the semiconductor material of the second conductivity type; and
(g) after the step (f), forming an element section over the second epitaxial layer.

US Pat. No. 10,141,395

HIGH-K METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

INTERNATIONAL BUSINESS MA...

1. A metal-insulator-metal (MIM) capacitor, comprising, in a cross-sectional view:a first metal plate;
a second metal plate;
a third metal plate; and
a layer of high-k material contacting the first metal plate, the second metal plate, and the third metal plate.

US Pat. No. 10,141,394

INTEGRATED CIRCUIT COMPRISING A METAL-INSULATOR-METAL CAPACITOR AND FABRICATION METHOD THEREOF

IMEC vzw, Leuven (BE)

1. An integrated circuit (IC) comprising:a semiconductor substrate; and
a plurality of metallization levels, each metallization level comprising a layer of intermetal dielectric having metal areas embedded therein,
a metal-insulator-metal capacitor (MIMCAP) comprising a bottom electrode, a top electrode and a metal-insulator-metal (MIM) stack comprising a lower conductive layer, an upper conductive layer and an insulator layer sandwiched between the lower and upper conductive layers,
wherein the bottom electrode comprises a planar metal area of a lower metallization level, the planar metal area having perforations formed therethrough,
wherein the IC comprises cavities, each cavity extending through one of the perforations and into the semiconductor substrate, each cavity being separated from edges of a corresponding perforation by a first intermetal dielectric material of the lower metallization level,
wherein the MIM stack comprises a planar portion of the MIM stack on at least a part of an upper surface of the bottom electrode and a plurality of non-planar portions of the MIM stack extending into the cavities, the MIM stack lining the sidewalls and bottoms of the cavities, and
wherein the top electrode comprises:
a planar portion of the top electrode formed by a planar metal area of an upper metallization level adjacent to the lower metallization level, wherein the planar portion of the top electrode is formed on at least a part of an upper surface of the planar portion of the MIM stack, and wherein the planar portion of the top electrode has sidewalls lined by portions of the MIM stack, and
non-planar portions of the top electrode extending from the planar portion of the top electrode into the cavities.

US Pat. No. 10,141,393

THREE DIMENSIONAL CAPACITOR

Cypress Semiconductor Cor...

1. A device, comprising:a first conductor disposed directly on a substrate, wherein a bottom surface of the first conductor is in contact with a semiconducting portion of the substrate and the first conductor further includes a top surface, first and second sidewalls;
a dielectric structure disposed at least partly over the first conductor; and
a second conductor disposed over and covering the dielectric structure partly, wherein the second conductor is not disposed over the top surface of the first conductor.

US Pat. No. 10,141,392

MICROSTRUCTURE MODULATION FOR 3D BONDED SEMICONDUCTOR STRUCTURE WITH AN EMBEDDED CAPACITOR

International Business Ma...

11. A method of forming a three-dimensional (3D) bonded semiconductor structure, the method comprising:providing a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and a first metallic capacitor plate structure having a columnar grain microstructure embedded in the first bonding oxide layer, and a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and a second metallic capacitor plate structure having a columnar grain microstructure embedded in the second bonding oxide layer;
forming a high-k dielectric material on a surface of the first metallic capacitor plate structure or the second metallic capacitor plate structure; and
bonding the first semiconductor structure to the second semiconductor structure, wherein the bonding provides a bonding interface between the first and second bonding oxide layers and another bonding interface between the high-k dielectric material and the first metallic capacitor plate structure or the second metallic capacitor plate structure.

US Pat. No. 10,141,387

DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising: a substrate; a light emitting diode disposed above the substrate; a first transistor disposed above the substrate and comprising: a first semiconductor layer; a first top gate electrode disposed above the first semiconductor layer; a first bottom gate electrode disposed under the first semiconductor layer; a first source electrode electrically connected to the first semiconductor layer; and a first drain electrode electrically connected to the first semiconductor layer, wherein the first drain electrode is electrically connected to the light emitting diode; and a second transistor disposed above the substrate and comprising a second semiconductor layer; wherein one of the first semiconductor layer and the second semiconductor layer comprises a first silicon semiconductor layer, and the other comprises a first oxide semiconductor layer, wherein the second transistor further comprises a first gate electrode and a second gate electrode, the first gate electrode is disposed above the second semiconductor layer, and the second gate electrode is disposed under the second semiconductor layer, wherein the second transistor further comprises a second drain electrode electrically connected to the second semiconductor layer, and the second drain electrode is electrically connected to the first source electrode through a conductive line or by direct contact, wherein the second transistor further comprises a second source electrode electrically connected to the second semiconductor layer, and the second source electrode is electrically connected to the first drain electrode through a conductive line or by direct.

US Pat. No. 10,141,386

ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising: a base substrate, a plurality of pixel units disposed on a side of the base substrate, a chip for providing signal to the plurality of pixel units, and signal lines corresponding to each of the plurality of the pixel units,wherein the chip is disposed on an opposed side of the base substrate having the plurality of pixel units disposed thereon,
wherein via holes penetrating at least the base substrate are disposed on the array substrate,
wherein the signal lines electrically connect each of the plurality of the pixel units to the chip through the via holes,
wherein the signal lines comprise wires that comprise first wires and second wires, the first wires at least comprise gate lines, and the second wires at least comprise data lines, and
wherein the chip at least comprises a gate driving chip connected to the gate lines and a source driving chip connected to the data lines.

US Pat. No. 10,141,385

THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY PANEL USING SAME

HON HAI PRECISION INDUSTR...

1. A thin film transistor (TFT) substrate, the TFT substrate defining a display area and a non-display area surrounding the display area, the TFT substrate comprising:a substrate;
a plurality of first scanning lines on the substrate and in the display area, each of the plurality of first scanning lines extending along a first direction;
a plurality of data lines on the substrate and in the display area, each of the plurality of data lines extending along a second direction that is different from the first direction, each of the plurality of data lines electrically insulated from the plurality of first scanning lines;
a conductive layer on the substrate and above the plurality of first scanning lines;
at least one electrically insulating layer on the substrate and between the plurality of first scanning lines and the conductive layer;
a touch sensing layer on the substrate and above the conductive layer;
wherein the conductive layer forms a plurality of second scanning lines in the display area and a plurality of touch traces; each of the plurality of touch traces is electrically coupled to the touch sensing layer; each of the plurality of second scanning lines is electrically coupled to one of the plurality of first scanning lines by extending through the at least one electrically insulating layer.

US Pat. No. 10,141,382

METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL HAVING POLYMER NETWORK LIQUID CRYSTAL

Samsung Display Co., Ltd....

1. A method of manufacturing an organic light emitting diode display panel, comprising:forming a lower substrate, the lower substrate comprising a first area and a second area;
forming an organic light emitting device on the lower substrate;
disposing a polymer network liquid crystal on the organic light emitting device;
forming a second optical layer in the second area, the second optical layer comprising the polymer network liquid crystal; and
varying an optical property of the polymer network liquid crystal so as to form a first optical layer in the first area in which the first optical layer has a first refractive index different than a second refractive index of the second optical layer.

US Pat. No. 10,141,377

ELECTROLUMINESCENT DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An electroluminescent display device comprising:a substrate on which first and second pixel regions are defined;
a passivation layer over the substrate;
a first electrode in each of the first and second pixel regions on the passivation layer;
a bank layer exposing the first electrode;
a light emitting layer on the first electrode exposed by the bank layer; and
a second electrode on the light emitting layer,
wherein the bank layer includes first and second openings exposing the first electrodes corresponding to the first and second pixel regions, respectively,
wherein the bank layer further includes a third opening exposing the first electrode corresponding to a third pixel region,
wherein a depth of the first opening is larger than a depth of the third opening,
wherein a height of the bank layer of the third pixel region is smaller than a height of the bank layer of the first pixel region, and
wherein the passivation layer has a groove in the second opening of the second pixel region, and each of the bank layer of the first and second pixel regions has a same height.

US Pat. No. 10,141,374

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a plurality of first interconnects provided along a first direction, respectively;
a plurality of second interconnects provided along a second direction different from the first direction, respectively;
a plurality of third interconnects provided along a third direction different from the first and second directions, respectively;
a plurality of memory cells including variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects and coupled with the mutually different second interconnects; and
a plurality of selectors which couple the third interconnects with the first interconnects,
wherein one of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects,
a plurality of gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween, and
wherein in each of the selectors, gates provided on the side surfaces of the semiconductor layer are coupled with each other in common along a second direction, and
the gates are separated between the selectors.

US Pat. No. 10,141,372

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

8. A three-dimensional semiconductor device, comprising:a substrate including a cell array region, a dummy region, a contact region, and an overlapped region,
the contact region being adjacent to the cell array region in a first direction, the dummy region being adjacent to the cell array region in a second direction, the overlapped region being adjacent to the contact region in the second direction and adjacent to the dummy region in the first direction, the second direction being perpendicular to the first direction;
a first stack structure including a plurality of first electrodes vertically stacked on the substrate, the first stack structure extending along the first direction on the cell array region and the contact region; and
a second stack structure including a plurality of second electrodes vertically stacked on the substrate, the second stack structure spaced apart from the first stack structure in the second direction and provided on the dummy region and the overlapped region,
wherein the second stack structure has a first staircase structure extending in the first direction and a second staircase structure extending in the second direction,
the first staircase structure has a first slope with respect to the top surface of the substrate and the second staircase structure has a second slope with respect to the top surface of the substrate, and
the second slope is greater than the first slope.

US Pat. No. 10,141,370

OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME

1. An optoelectronic device comprising:a plurality of light-emitting diodes comprising semiconductor elements; and
current-limiting components, each said component being series-connected with a corresponding one of the plurality of semiconductor elements and having a resistance which increases along with current intensity flowing through the corresponding series-connected current-limiting component and semiconductor element.

US Pat. No. 10,141,368

SEMICONDUCTOR DEVICE

HAMAMATSU PHOTONICS K.K.,...

1. A semiconductor device comprising: a semiconductor substrate that has a first surface and a second surface opposite to each other and in which a through hole to extend from the first surface to the second surface is formed;a first wiring that is provided on the first surface and has a portion located above a first opening of the through hole on the a first surface side;
an insulating layer that is provided on an inner surface of the through hole and the second surface and is continuous through a second opening of the through hole on the a second surface side; and
a second wiring that is provided on a surface of the insulating layer and is electrically connected to the first wiring in an opening of the insulating layer on the first surface side, wherein the through hole is a vertical hole, and on both sides of a center line of the through hole in a plane including the center line of the through hole, a segment that connects a first point corresponding to an edge of the opening of the insulating layer and a second point corresponding to an edge of the second opening is a first segment, a segment that connects the second point and a third point corresponding to an intersection point between the second opening and the surface of the insulating layer is a second segment, and a segment that connects the third point and the first point is a third segment, a first area of the insulating layer that is located on an inner surface side of the through hole with respect to the first segment is larger than the sum of a second area of the insulating layer that is surrounded by the first segment, the second segment, and the third segment and a third area of the insulating layer that is located on a side opposite the inner surface side of the through hole with respect to the third segment.

US Pat. No. 10,141,367

PHOTOELECTRIC CONVERSION APPARATUS AND PHOTOELECTRIC CONVERSION SYSTEM

CANON KABUSHIKI KAISHA, ...

1. A photoelectric conversion apparatus comprising:a plurality of pixels, each pixel including
a pixel electrode having a first electrode and a second electrode on an upper part of a substrate,
an upper electrode arranged on an upper part of the pixel electrode,
a photoelectric conversion layer arranged between the pixel electrode and the upper electrode,
a first signal output circuit including a first amplification unit having an input node directly connected to the first electrode, and
a second signal output circuit including a second amplification unit having an input node directly connected to the second electrode; and
a control unit configured to supply an electric potential to the second electrode that a potential of the second electrode with respect to signal charges decreases as compared with a potential of the first electrode with respect to signal charges in an electric potential supplied to the first electrode during a first period in which the first signal output circuit outputs a signal.

US Pat. No. 10,141,362

SEMICONDUCTOR DEVICE HAVING PROTECTION LAYER WRAPPING AROUND CONDUCTIVE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising: an image sensor device layer; a first bonding layer over the image sensor device layer; a second bonding layer bonded with the first bonding layer; a substrate over the second bonding layer; and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer, wherein the conductive via comprises: a protection layer peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer, wherein the protection layer covers a sidewall cut formed at an interface between the second bonding layer and the first bonding layer; and a conductive material peripherally enclosed by the protection layer, wherein the protection layer has a protrusion protruding from an outer sidewall of the protection layer and in contact with the first bonding layer and the second bonding layer.

US Pat. No. 10,141,361

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An image sensor comprising:a first semiconductor section including a first semiconductor substrate and a first multi-wiring layer, the first semiconductor substrate including a photodiode, and the first multi-wiring layer including a first insulating interlayer and first and second wirings; and
a second semiconductor section including a second semiconductor substrate and a second multi-wiring layer, the second semiconductor section including at least a part of a signal processing circuit, and the second multi-wiring layer including a second insulating interlayer and third and fourth wirings,
wherein,
the first semiconductor section and the second semiconductor section are bonded together such that the first multi-wiring layer and the second multi-wiring layer face each other,
the first wiring of the first multi-wiring layer directly contacts the third wiring of the second multi-wiring layer in a pixel region including the photodiode, and
the second wiring of the first multi-wiring layer directly contacts the fourth wiring of the second multi-wiring layer in a peripheral region other than the pixel region.

US Pat. No. 10,141,360

ISOLATED GLOBAL SHUTTER PIXEL STORAGE STRUCTURE

OmniVision Technologies, ...

1. An imaging system, comprising:a pixel array of pixel cells, wherein each one of the pixel cells includes:
a photodiode disposed in a semiconductor material to accumulate image charge in response to incident light directed to the photodiode;
a global shutter gate transistor, wherein a portion of the global shutter gate transistor is disposed in the semiconductor material and coupled to the photodiode to selectively deplete the image charge from the photodiode;
a storage transistor, wherein a portion of the storage transistor is disposed in the semiconductor material to store the image charge; and
an optical isolation structure disposed in the semiconductor material proximate to the storage transistor to isolate a sidewall of the storage transistor from stray light and stray charge in the semiconductor material outside of the storage transistor, wherein the optical isolation structure includes a deep trench isolation structure formed in the semiconductor material, wherein the deep trench isolation structure is filled with tungsten, wherein the optical isolation structure further includes a P+ passivation formed over an interior sidewall of the deep trench optical isolation structure between the tungsten and the semiconductor material;
control circuitry coupled to the pixel array to control operation of the pixel array; and
readout circuitry coupled to the pixel array to readout image data from the plurality of pixels.

US Pat. No. 10,141,090

RESIN COMPOSITION, PASTE FOR FORMING A VARISTOR ELEMENT, AND VARISTOR ELEMENT

NAMICS CORPORATION, Niig...

1. A resin composition comprising:(A) an epoxy resin;
(B) a curing agent; and
(C) carbon nanotubes,
wherein the carbon nanotubes contain therein semiconducting single-walled carbon nanotubes in an amount of 70% by weight or more.

US Pat. No. 10,141,087

WIRING HARNESS PRODUCTION MOUNTING

LASELEC, Toulouse (FR)

1. A system for the production of wire harnesses, comprising:at least one cable routing element (200, 21);
at least one display screen (101) for displaying data for assisting with the production of wire harnesses;
at least one attachment surface (103, 400) associated with said at least one display screen, said at least one attachment surface being configured to receive said at least one cable routing element (200, 21); and
a processing unit configured to implement a method for assisting with the production of wire harnesses, the processing unit operatively connected to the at least one display screen (101) and configured to provide the data for assisting with the production of the wire harnesses,
wherein said at least one cable routing element comprises an attachment suction cup that attaches said at least one cable routing element to said at least one attachment surface (103, 400) associated with said at least one display screen.

US Pat. No. 10,141,085

CONDUCTOR JOINT AND CONDUCTOR JOINT COMPONENT

1. A system comprising: a fiber-structured heating element; a copper conductor; and a conductor joint therebetween, wherein dimensions of the fiber-structured heating element being length (L)>>width (W)>>thickness (T), and which heating element comprises carbon fiber strands, wherein the copper conductor is transversely disposed relative to a longitudinal direction (L) of the heating element to form a layered structure in a thickness direction (T), on both opposing sides of the heating element, the copper conductor comprising copper strands separable from each other, wherein the copper strands of the copper conductor, a number and a diameter of which are configured to transfer electric power of more than ten kW, are quantitatively evenly distributed on both opposing sides and corresponding surfaces of the heating element, having a material including carbon fiber strands of the heating element in between, so that on each of said both opposing sides the strands distributed thereto extend along and cover the width (W) of the heating element, the strands on each side of said both opposing sides being further disposed in a planar manner in such a way that the strands lie in one plane, adjacent to each other, and the ends of the strands further extend on each of said both opposing sides, in a width direction (W) of the heating element, beyond the heating element, wherein portions of the ends of the strands extending beyond the heating element overlap each other, and an electric joint is formed between lateral faces of these portions of overlapping strands.

US Pat. No. 10,141,084

ELECTRONIC DEVICE

Cheil Industries, Inc., ...

1. An electronic device, comprising:an anisotropic conductive film, the anisotropic conductive film including an insulating layer and a conductive layer laminated on the insulating layer, the conductive layer containing insulating particles and conductive particles, wherein,
the lowest melt viscosity of the insulating layer is in the range of about 2,000 Pa·s to about 10,000 Pa·s and the lowest melt viscosity of the conductive layer is in the range of about 5,000 to about 50,000 Pa·s, provided that the lowest melt viscosity of the conductive layer is at least about 3,000 Pa·s greater than that of the insulating layer,
the insulating layer is from greater than 1 to about 4 times thicker than the conductive layer,
the insulating layer is formed from a first composition that comprises a first polymer resin, a first radically polymerizable material, and a first radical initiator, wherein the first polymer resin includes one or more of an olefinic resin, a butadiene resin, an acrylonitrile-butadiene copolymer, a carboxyl-terminated acrylonitrile-butadiene copolymer, a polyimide resin, a polyamide resin, a polyester resin, a polyvinyl butyral resin, an ethylene-vinyl acetate copolymer, a styrene-butylene-styrene (SBS) resin, a styrene-ethylene-butylene-styrene (SEBS) resin, an acrylonitrile-butadiene rubbers (NBRs), a urethane resin, a (meth)acrylic resin, or a phenoxy resin, and the first radically polymerizable material includes a first epoxy (meth)acrylate oligomer, the first epoxy (meth)acrylate oligomer being present in an amount of 20 to 40 wt %, based on a total weight of the first composition,
the conductive layer is formed from a second composition that comprises a second polymer resin, a second radically polymerizable material, and a second radical initiator, wherein the second polymer resin includes one or more of an olefinic resin, a butadiene resin, an acrylonitrile-butadiene copolymer, a carboxyl-terminated acrylonitrile-butadiene copolymer, a polyimide resin, a polyamide resin, a polyester resin, a polyvinyl butyral resin, an ethylene-vinyl acetate copolymer, a styrene-butylene-styrene (SBS) resin, a styrene-ethylene-butylene-styrene (SEBS) resin, an acrylonitrile-butadiene rubbers (NBRs), a urethane resin, a (meth)acrylic resin, or a phenoxy resin, and the second radically polymerizable material includes a second epoxy (meth)acrylate oligomer, the second epoxy (meth)acrylate oligomer being present in an amount of 20 to 30 wt %, based on a total weight of the second composition,
a size of the conductive particles is in the range of about 1 to about 30 ?m, the conductive particles being present in an amount of about 1 to about 30% by weight, based on the total weight of the second composition,
a size of the insulating particles is in the range of about 0.1 to about 20 ?m, the insulating particles being present in an amount of about 2 to about 20% by weight, based on the total weight of the second composition.

US Pat. No. 10,141,083

TRANSPARENT CONDUCTIVE FILM COMPOSITE AND TRANSPARENT CONDUCTIVE FILM

INDUSTRIAL TECHNOLOGY RES...

1. A transparent conductive film, consisting of:(a) a metallic material; and
(b) a dispersant,
wherein a weight ratio of the metallic material to the dispersant ranges from 0.14:1 to 20:1,
wherein the metallic material (a) comprises:
(a1) 84-99.99 wt % of metal nanowires; and
(a2) 0.01-16 wt % of micron metal flakes,
wherein a sheet resistance of the transparent conductive film is 10052/or less, and a transparency of the transparent conductive film is 95% or greater.

US Pat. No. 10,141,082

OXIDATION RESISTANT COPPER NANOPARTICLES AND METHOD FOR PRODUCING SAME

KOREA INSTITUTE OF SCIENC...

1. A method for producing copper nanoparticles, comprising the steps of:preparing a first solution by stirring together a solvent, a polymer, and an organic acid, wherein the polymer is selected from the group consisting of polyacetylene, polyaniline, polypyrrole, polythiophene, poly(3,4-ethylenedioxythiophene) and a combination thereof,
wherein the organic acid is selected from the group consisting of erythorbic acid, glucuronolactone, triformin (2,3-diformyloxypropyl formate) and a combination thereof;
producing a second solution by mixing the first solution, a copper precursor, and a first reducing agent;
producing a third solution by mixing a second reducing agent with the second solution for 30 minutes to 5 hours; and
separating and collecting copper nanoparticles from the third solution.

US Pat. No. 10,141,081

PHASE CONTRAST X-RAY IMAGING DEVICE AND PHASE GRATING THEREFOR

Siemens Healthcare GmbH, ...

1. A phase grating for a phase contrast X-ray imaging, the phase grating comprising:a transverse surface to be aligned substantially transversely with respect to a radiation incidence direction, said transverse surface being spanned by an x-axis and a y-axis perpendicular to said x-axis;
a multiplicity of grating webs composed of a basic material and alternately arranged with optically denser interspaces, said grating webs dividing said transverse surface into grating strips that are in each case elongated in a y-direction of said y-axis and that are lined up parallel alongside one another in an x-direction of said x-axis;
at least one of said grating webs extending within said transverse surface across a plurality of said grating strips; and
the phase grating, at each said grating strip along a z-axis that extends perpendicularly to said transverse surface, having a homogeneous total thickness of said basic material that differs between mutually adjacent said grating strips.

US Pat. No. 10,141,080

INSOLUBLE CESIUM GLASS

QSA GLOBAL, INC., Burlin...

1. A cesium-137 gamma radiation source consisting of a mixed metal oxide of cesium-137 and a metal chosen from the group consisting of niobium, tantalum, vanadium and mixtures thereof, in which an insoluble radioactive product is formed, as a mixture, solid solution or ternary compound, by a process of reacting at least one dissolved compound of the at least one metal with a soluble cesium-137 compound followed by forming a solid radioactive component of a gamma radiation source.

US Pat. No. 10,141,079

TARGETRY COUPLED SEPARATIONS

TerraPower, LLC, Bellevu...

1. A method for manufacturing 99Mo radioisotope, the method comprising:providing a source containing a first mass of uranium particles, the uranium particles having an average particle size of from 10% to 200% of a recoil distance of 99Mo in the uranium particles;
enclosing the source in a neutronically-translucent container;
exposing the source to neutrons, thereby reducing the first mass of uranium particles in the source to a second mass of uranium particles less than the first mass and creating at least some atoms of the 99Mo radioisotope;
removing, after exposing the source to neutrons, at least some of the atoms of the 99Mo radioisotope from the source without removing uranium particles from the source;
wherein the removing operation further comprises:
passing an extraction material selected to dissolve the 99Mo radioisotope through the container, thereby contacting the uranium particles with the extraction material; and
wherein the extraction material is supercritical carbon dioxide containing a ligand that dissolves the 99Mo radioisotope and does not dissolve the uranium.

US Pat. No. 10,141,078

LIQUID FUEL NUCLEAR FISSION REACTOR FUEL PIN

TerraPower, LLC, Bellevu...

1. A nuclear fission fuel pin comprising:cladding defining an elongated enclosure, the enclosure having a fission region and a fertile blanket region;
a solution of a first fissile nuclear fission fuel material dissolved in neutronically translucent liquid carrier material, the solution being distributed into the elongated enclosure including into the fission region and into the fertile blanket region; and
a solid phase, undissolved fertile nuclear fission fuel material, in foam form, disposed in the fertile blanket region of the elongated enclosure and in direct physical contact with the solution in the elongated enclosure, the fertile nuclear fission fuel material being transmutable into a second fissile nuclear fission fuel material directly diffusible into the solution.