US Pat. No. 10,431,743

MANUFACTURING METHOD OF AN OLED ANODE AND AN OLED DISPLAY DEVICE THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method of an OLED anode, comprising following steps:forming an anode film layer on a substrate, wherein a material of the anode film layer is an ITO material;
forming a photoresist film layer on the anode film layer;
patterning the photoresist film layer to acquire a photoresist-mask pattern, the photoresist-mask pattern comprising: a photoresist full-retention area, a photoresist half-retention area, and a photoresist full-removal area, wherein the photoresist half-retention area is located between the photoresist full-retention area and the photoresist full-removal area;
using the photoresist-mask pattern as an anti-etching layer, and etching the anode film layer to acquire an anode pattern;
removing the photoresist half-retention area;
performing a plasma treatment to a portion of the anode pattern outside the photoresist full-retention area by adopting a first gas, wherein, the first gas comprises at least one of an O2, N2O, CF4, and Ar, and
removing the photoresist-mask pattern.

US Pat. No. 10,431,742

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A method of manufacturing an organic light-emitting display apparatus, the method comprising:forming a lift-off layer on a substrate comprising a first electrode, the lift-off layer comprising a fluoropolymer;
sequentially forming a barrier layer and a photoresist on the lift-off layer, the barrier layer comprising an inorganic material;
patterning the photoresist and the barrier layer to remove a first portion of the photoresist corresponding to the first electrode such that a second portion other than the first portion remains;
etching a portion of the lift-off layer corresponding to the first portion to expose the first electrode;
forming an organic functional layer and an auxiliary electrode over the first electrode and the second portion of the photoresist, the organic functional layer comprising an emission layer; and
removing the lift-off layer, the barrier layer, the photoresist, the organic functional layer, and the auxiliary electrode remaining on the second portion,
wherein the barrier layer comprises at least one of a metal nitride and a metal oxynitride.

US Pat. No. 10,431,739

CLAMP ELEMENTS FOR PHASE CHANGE MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method for forming cell structures, comprising:forming a chalcogenic material over a plurality of contacts;
after forming the chalcogenic material, forming a mask material;
removing portions of the mask material to form a plurality of mask elements, wherein at least a mask hole is located between the plurality of mask elements and positioned non-orthogonally relative the plurality of contacts;
removing a portion of the chalcogenic material to form a plurality of chalcogenic material elements; and
forming a plurality of bit lines over the chalcogenic material elements.

US Pat. No. 10,431,738

INTEGRATED FAN-OUT PACKAGE AND METHOD FOR FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A method for fabricating an integrated fan-out package, comprising:mounting a plurality of memory devices onto a carrier, and one of the memory devices including stacked memory chips and a controller;
forming a first insulating portion of an insulation encapsulation over the carrier to encapsulate the memory devices;
mounting an integrated circuit onto the memory devices, the integrated circuit being electrically connected to the memory devices;
forming a second insulating portion of the insulation encapsulation over the first insulating portion to encapsulate the integrated circuit; and
forming a redistribution circuit structure on the insulation encapsulation and the integrated circuit, the redistribution circuit structure being electrically connected to the integrated circuit and the memory devices, wherein the integrated circuit comprises an active surface and a rear surface, the active surface or the rear surface of the integrated circuit faces the memory devices after the integrated circuit is mounted onto the memory devices.

US Pat. No. 10,431,737

CO-FIRED PASSIVE INTEGRATED CIRCUIT DEVICES

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a first passive device and a second passive device over a carrier substrate, wherein the first passive device is different than the second passive device, wherein the first passive device is laterally adjacent to the second passive device, and wherein the first passive device and the second passive device each include at least one material layer that includes a co-fired ceramic material;
performing a co-firing process while at least a portion of the first passive device and at least a portion of the second passive device are exposed, wherein the co-firing process is performed to cause chemical changes in the co-fired ceramic material; and
removing the carrier substrate after performing the co-firing process.

US Pat. No. 10,431,732

SHIELDED MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A magnetically shielded semiconductor device comprising:a substrate having a top surface and a bottom surface;
an electromagnetic-field-susceptible semiconductor component located in the substrate;
a top magnetic shield located over the top surface of the substrate, wherein the top magnetic shield is formed with an opening;
a package substrate mounted to the top magnetic shield, wherein the package substrate defines a void vertically aligned with the opening of the top magnetic shield such that the package substrate lies free from directly disposing over the opening of the top magnetic shield;
a bottom magnetic shield located under the bottom surface of the substrate; and
a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.

US Pat. No. 10,431,731

METHOD FOR FORMING PZT FERROELECTRIC FILM

JAPAN ADVANCED INSTITUTE ...

1. A method for forming a PZT ferroelectric film, wherein the method comprises:a step of applying a liquid composition for forming a PZT ferroelectric film;
a step of drying the film applied with the liquid composition;
a step of irradiating UV rays onto the dried film at a temperature of 150 to 200° C. in an oxygen-containing atmosphere; and
after the application step, the drying step, and the UV irradiation step once, or more times, a step of firing for crystallizing a precursor film of the UV-irradiated ferroelectric film by raising a temperature with a temperature rising rate of 0.5° C./second or higher in an oxygen-containing atmosphere or by raising a temperature with a temperature rising rate of 0.2° C./second or higher in a non-oxygen containing atmosphere, followed by keeping the temperature at 400 to 500° C.; and further,
an amount of the liquid composition in each application is set such that thickness of the ferroelectric film be 150 nm or more for each application and ozone is supplied during the UV irradiation.

US Pat. No. 10,431,730

DIELECTRIC ELASTOMER DRIVING MECHANISM

Seiki Chiba, Tokyo (JP) ...

1. A dielectric elastomer driving mechanism comprising:a driver that includes a dielectric elastomer driving element having a dielectric elastomer layer and a pair of electrode layers sandwiching the dielectric elastomer layer, a tension maintaining element maintaining, in a potential-free state in which no voltage is applied to the pair of electrode layers, the dielectric elastomer driving element in a state in which tension occurs, and an output portion moving along with expanding or contracting of the dielectric elastomer driving element;
a follower that includes a following element actuating in accordance with a driving force inputted; and
a power transmitter that is connected to the output portion of the driver and transmits a driving force of the driver to the follower,
wherein the power transmitter includes a wire that causes the follower to actuate in a first specific direction, and
the follower includes an auxiliary elastic portion exerting an auxiliary elastic force that causes the following element to actuate in a second specific direction that is different from the first specific direction.

US Pat. No. 10,431,728

SUPERCONDUCTING BUMP BONDS

Google LLC, Mountain Vie...

1. A method comprising:providing a first chip comprising a first circuit element;
forming a first aluminum interconnect pad on a first surface of the first chip so that the first aluminum interconnect pad is electrically connected to the first circuit element;
forming a first titanium nitride barrier layer on the first aluminum interconnect pad;
providing a second chip comprising a second circuit element;
forming an indium bump bond; and
joining the first chip to the second chip with the indium bump bond so that the first circuit element is electrically connected to the second circuit element, wherein joining the first chip to the second chip is performed at room temperature.

US Pat. No. 10,431,727

LIGHT EMITTING APPARATUS

SUMITOMO ELECTRIC INDUSTR...

1. A light emitting apparatus comprising:a module including a Peltier device with a first face and a second face, a supporting member with a principal surface, and a light emitting semiconductor device, the first face being opposite to the second face; and
a package housing the module, the package including a lead terminal and a supporting face supporting the second face of the Peltier device, wherein
the principal surface of the supporting member has a first area and a second area adjacent to the first area,
the supporting member supports the first face of the Peltier device on the first area of the principal surface thereof,
the supporting member supports the light emitting semiconductor device on the second area of the principal surface thereof,
the supporting member has a circuit board to, which the light emitting semiconductor device and Peltier device are connected, the circuit board being connected to the lead terminal through a wiring conductor in the package,
the circuit board includes a multi-laver circuit board having a first face and a second face opposite to the first face thereof, the first face of the multi layer circuit having a first area disposed along a side of the multi-layer circuit board, a second area adjoining the first area, and a difference in level at a boundary between the first area and the second area, the second face of the multi-layer circuit board having the light emitting semiconductor device disposed thereon, and
the multi -layer circuit board first face has a pad electrode on the first area thereof, the pad electrode being connected to the lead terminal through a wiring conductor.

US Pat. No. 10,431,726

FLEXIBLE THERMOELECTRIC GENERATOR AND METHODS OF MANUFACTURING

North Carolina State Univ...

1. A flexible thermoelectric generator comprising:a plurality of pillars having a first side and a second side;
a first plurality of flexible interconnects electrically connecting pairs of the plurality of pillars on the first side;
a second plurality of flexible interconnects electrically connecting the pairs of plurality of pillars on the second side, wherein the first plurality and the second plurality of flexible interconnects alternate among the pairs of plurality of pillars to form an electrical circuit having a first end and a second end;
a first flexible material covering the first and second plurality of flexible interconnects, wherein the first flexible material has an external surface, and wherein the first flexible material is configured to conduct thermal energy from the external surface to the plurality of pillars; and
a second flexible material between each of the plurality of pillars, and with respect to the each of the plurality of pillars, only directly adjacent to the each of the plurality of pillars,
wherein the first flexible material covering the first and second plurality of flexible interconnects comprises polydimethylsiloxane (PDMS) and at least one of:
nanowires,
carbon nanotubes,
graphene, or
a liquid metal.

US Pat. No. 10,431,722

LIGHT EMITTING ELEMENT, LIGHT EMITTING ELEMENT ARRAY, AND LIGHT TRANSMISSION DEVICE

FUJI XEROX CO., LTD., Mi...

1. A light emitting element comprising:a semiconductor stack structure including:
a light emitting part; and
a light receiving part configured to receive light propagating in a lateral direction through a semiconductor layer from the light emitting part,
wherein the light receiving part is configured to convert a received light into a detected monitor current, and
wherein the light emitting part and the light receiving part share a quantum layer; and
a light reflection layer that covers ? or more of a lateral surface of the quantum layer in the light receiving part.

US Pat. No. 10,431,719

DISPLAY WITH COLOR CONVERSION

X-Celeprint Limited, Cor...

1. A color-conversion structure, comprising:an article comprising a color-conversion material disposed within a color-conversion layer, wherein the color-conversion material re-emits or redirects light by absorbing electromagnetic radiation of a relatively higher frequency and emitting electromagnetic radiation of a relatively lower frequency;
at least a portion of a tether connected to the article, wherein the at least a portion of a tether extends from the article.

US Pat. No. 10,431,718

SUBSTRATE WITH TOPOLOGICAL FEATURES FOR STEERING FLUIDIC ASSEMBLY LED DISKS

eLux Inc., Vancouver, WA...

1. A display panel, the display panel comprising:a substrate with a top surface;
a material layer disposed over the top surface of the substrate, wherein the material layer includes:
a plurality of wells, and wherein each of the plurality of wells extends to a first depth into the material layer;
at least one object steering feature surrounding two or more of the plurality of wells, wherein the object steering feature extends a second depth into the material layer, and wherein the second depth is less than the first depth; and
wherein the material layer includes a first sub-layer disposed over the top surface of the substrate and a second sub-layer disposed over the first sub-layer.

US Pat. No. 10,431,717

LIGHT-EMITTING DIODE (LED) AND MICRO LED SUBSTRATES AND METHODS FOR MAKING THE SAME

Intel Corporation, Santa...

1. An integrated circuit (IC) structure comprising:a substrate comprising a metal and oxygen;
a first core, a second core, and a third core over the substrate, the cores comprising a group III semiconductor material, the cores doped with n-type dopants;
a first active layer on a surface of the first core, the first active layer comprising a first atomic concentration of indium;
a second active layer on a surface of the second core, the second active layer comprising a second atomic concentration of indium;
a third active layer on a surface of the third core, the third active layer comprising a third atomic concentration of indium; and
a cladding on the first, second, and third active layers, the cladding doped with p-type dopants.

US Pat. No. 10,431,716

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

1. A light-emitting diode, comprising:a first-type nitride region composed of an n-type nitride;
a light-emitting region; and
a second-type nitride region;
wherein:
the first-type nitride region comprises a first nitride layer and a second nitride layer;
a doping concentration of the second nitride layer is higher than a doping concentration of the first nitride layer; and
the second nitride layer has high-doped emitting points pointing to the first nitride layer to thereby improve electron expansion capacity and injection efficiency.

US Pat. No. 10,431,715

DEVICE AND METHOD FOR PRODUCING A DEVICE

OSRAM Opto Semiconductors...

1. A device comprising:a first component;
a second component; and
a connecting element arranged between the first component and the second component,
wherein the connecting element comprises at least a first phase and a second phase,
wherein the first phase comprises a first metal having a first concentration (c11), a second metal having a second concentration (c12) and a third metal having a third concentration (c13),
wherein the second phase comprises the first metal having a fourth concentration (c25), the second metal and the third metal,
wherein the first metal, the second metal and the third metal are different from one another and are suitable for reacting at a processing temperature of less than 200° C., and
wherein the following applies: c11?c25 and c11?c13? c12.

US Pat. No. 10,431,714

ENGINEERED SUBSTRATES FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS

Qromis, Inc., Santa Clar...

1. A method for fabricating semiconductor devices, the method comprising:forming an engineered substrate having a first layer comprising a first material, a second layer comprising a second material, and a third layer comprising a dissolvable material and disposed between the first layer and the second layer;
forming a first buffer structure on the second layer;
forming a first transducer structure on the first buffer structure, the first transducer structure having a plurality of semiconductor materials including a radiation-emitting active region, wherein at least one of the first material and the second material in the engineered substrate has a coefficient of thermal expansion approximately matched to a coefficient of thermal expansion of at least one of the plurality of semiconductor materials;
forming a reflective contact electrically coupled to a first semiconductor material of the plurality of semiconductor materials;
forming an insulating layer on the reflective contact;
forming a plurality of buried contacts electrically coupled to a second semiconductor material of the plurality of semiconductor materials, wherein each buried contact passes through the insulating layer, the reflective contact and the first semiconductor material of the plurality of semiconductor materials, and wherein a first end of each buried contact protrudes into the second semiconductor material of the plurality of semiconductor materials, and a second end of each buried contact protrudes through the insulating layer;
forming a first electrode on the insulating layer, wherein the first electrode is electrically and physically coupled to the second end of each buried contact;
forming a second electrode electrically coupled to the reflective contact, wherein a portion of the second electrode is over the insulating layer; and exposing the third layer to a solvent to dissolve the dissolvable material in the third layer, thereby separating the first layer from the second layer.

US Pat. No. 10,431,713

NITRIDE UNDERLAYER AND FABRICATION METHOD THEREOF

XIAMEN SANAN OPTOELECTRON...

1. A nitride underlayer comprising, from bottom up:a substrate;
a sputtered AlN buffer layer; and
an AlXIn1-X-YGaYN layer (0?X?1, 0?Y?1) grown via MOCVD,
wherein the sputtered AlN buffer layer has a flat surface and band-shaped holes therein formed with laser scanning and configured to provide a stress release path to release stress during growth of the AlXIn1-X-YGaYN layer, and
wherein side walls of the holes and the AlN buffer layer are connected.

US Pat. No. 10,431,711

SEMICONDUCTOR HETEROSTRUCTURE POLARIZATION DOPING

Sensor Electronic Technol...

1. A semiconductor heterostructure comprising:a doped region including:
an n-type semiconductor side formed of a group III nitride including aluminum and gallium, wherein the n-type semiconductor side is n-type doped and includes a first molar fraction of aluminum nitride; and
a p-type semiconductor side formed of a group III nitride including aluminum and indium, wherein a second molar fraction of aluminum nitride and a molar fraction of indium nitride decrease along a growth direction of the p-type semiconductor side, and
wherein the molar fraction of indium nitride is less than 0.3.

US Pat. No. 10,431,710

LIGHT EMITTING DEVICE

PLAYNITRIDE INC., Tainan...

1. A light emitting device, comprising:an epitaxial structure comprising:
a first type semiconductor layer comprising a first semiconductor sublayer;
a second type semiconductor layer; and
a light emitting layer disposed between the first type semiconductor layer and the second type semiconductor layer;
wherein, the first semiconductor sublayer has a heavily doped part and a lightly doped part which are doped by a first type dopant, the lightly doped part is disposed between the light emitting layer and the heavily doped part, a doping concentration of the first type dopant in the heavily doped part is between 1017 atoms/cm3 and 1018 atoms/cm3, and a doping concentration of the first type dopant in the lightly doped part is less than or equal to 1016 atoms/cm3,
wherein the first semiconductor sublayer is a single layer, in an image of an electron microscope or a secondary ion mass spectrometry, the heavily doped part and the lightly doped part of the first semiconductor sublayer show consistent grayscale level.

US Pat. No. 10,431,708

INTEGRATED CIRCUIT INCLUDING ESD DEVICE AND RADIATION EMITTING DEVICE

Infineon Technologies AG,...

1. An integrated circuit, comprising:an ESD device in a semiconductor substrate;
a device in the semiconductor substrate that emits radiation upon electrostatic discharge current beginning to flow through a pin electrically coupled to the ESD device, the ESD device having a pn-junction connected in parallel with the device in the semiconductor substrate that emits radiation upon electrostatic discharge current beginning to flow through a pin electrically coupled to the ESD device, wherein upon occurrence of the electrostatic discharge the ESD device receives the emitted radiation to accelerate avalanche breakdown in the ESD device; and wherein
the ESD device is configured to protect a circuit block different from the ESD device from damage that would otherwise be caused by electrostatic discharge.

US Pat. No. 10,431,707

MONOLITHICALLY INTEGRATED PHOTODETECTOR AND RECEIVER

Hewlett Packard Enterpris...

1. A device comprising:an avalanche photodetector to enable carrier multiplication for increased responsivity; and
a receiver including a transimpedance amplifier (TIA), an adaptively-tuned continuous-time linear equalizer (CTLE) cascaded with the TIA, and a slicer bank coupled to the CTLE to identify a data pass bit error rate (BER), wherein the receiver is based on source-synchronous complementary metal-oxide semiconductor (CMOS);
wherein the photodetector and receiver are monolithically integrated on a single chip.

US Pat. No. 10,431,706

PHOTOACTIVE DEVICE

The Regents of the Univer...

1. A photoactive device, comprising:a photovoltaic device configured to receive incident light, the photovoltaic device having electrodes and one or more layers between the electrodes that includes at least one photoactive layer, wherein the photovoltaic device is configured to absorb a portion of the incident light and to transmit therethrough, at an unchanged angle of incidence, a remaining portion of the incident light that is not absorbed by the photovoltaic device;
a substrate positioned below the photovoltaic device; and
an angular selective nanostructure backreflective layer positioned below the substrate, wherein the photovoltaic device overlays the substrate and the nanostructure backreflective layer such that the nanostructure backreflective layer receives the remaining portion of the incident light transmitted through the photovoltaic device, and wherein the nanostructure backreflective layer includes a plurality of nanoparticles each having an elongated body extending axially along an axis, wherein each of the axes are parallel to one another, wherein the plurality of nanoparticles are arranged within the nanostructure backreflective layer to scatter different portions of the light received from the photovoltaic device, the arrangement of the plurality of nanoparticles being angular selective in that the scattering is based on an angle of the elongated body axes with respect to a surface of the photovoltaic device and the angle of incidence of the remaining portion of the incident light such that at least some of the remaining portion of the incident light received by the backreflective layer at non-orthogonal angles of incidence is reflected back to the photovoltaic device at least in part by interaction of the light with the plurality of nanoparticles, while a majority of light received by the backreflective layer at an orthogonal angle of incidence is passed through the backreflective layer, wherein the elongated body axes of the plurality of nanoparticles are not parallel to the surface of the photovoltaic device.

US Pat. No. 10,431,705

COOLING SYSTEM FOR HIGH PERFORMANCE SOLAR CONCENTRATORS

International Business Ma...

1. A photovoltaic system, comprising:a cooling apparatus, comprising:
a heat exchanger comprising a metal plate with a bend therein that positions a first surface of the metal plate at an angle of about 100 degrees to about 150 degrees relative to a second surface of the metal plate, and a plurality of fins attached to a side of the metal plate opposite the first surface and the second surface, wherein each of the plurality of fins extends along an entire length of the side and crosses the bend;
a wrapper that collectively surrounds the fins and is open at a top and a bottom of each of the fins to form a channel to permit formation of a convective airflow through the wrapper along the channel containing the fins to enhance a flow of air past the fins by constraining the flow of air along a length of the fins, wherein the wrapper is made of a sheet material bent to surround the fins;
a vapor chamber extending along the first surface and the second surface of the metal plate, crossing the bend, wherein the vapor chamber is at least partially embedded in the metal plate;
a cladding material between the vapor chamber and the heat exchanger, wherein the cladding material is configured to thermally couple the vapor chamber to the heat exchanger;
at least one photovoltaic cell thermally coupled to the vapor chamber, wherein the photovoltaic cell is attached to the vapor chamber with the photovoltaic cell being soldered to the vapor chamber; and
a concentrating solar collector attached to either the first surface or the second surface of the metal plate and surrounding the photovoltaic cell.

US Pat. No. 10,431,704

METHOD FOR PRODUCING A UV PHOTODETECTOR

MERCK PATENT GMBH, Darms...

1. A method for producing a solar-blind UV photodetector, comprisingdepositing a liquid composition comprising a liquid carrier and gallium metal ions onto a substrate, where one or more of the gallium metal ions is bound to an oximate or hydroxamate ligand,
processing the deposited composition by evaporating the liquid carrier and heating residual material at a temperature of from 240 to 600° C., resulting in a UV photodetector material which consists of Ga2O3, and
providing electrodes to the UV photodetector material to result in a solar-blind UV photodetector.

US Pat. No. 10,431,703

OPTICAL CLADDING LAYER DESIGN

Juniper Networks, Inc., ...

1. An apparatus, comprising:a cladding layer defining a longitudinal direction transverse to a first surface of the cladding layer and a lateral direction parallel to the cladding layer, the cladding layer having a first thickness in a first lateral region and a second thickness in a second lateral region, the second thickness being greater than the first thickness;
a silicon semiconductor layer positioned on a second surface of the cladding layer opposite the first surface of the cladding layer; and
a buried oxide layer positioned on the silicon semiconductor layer, wherein the buried oxide layer includes a hole, at least a portion of the hole being longitudinally aligned with at least a portion of the second lateral region.

US Pat. No. 10,431,701

SEMICONDUCTOR DEVICE, ARRAY SUBSTRATE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

BOE Technology Group Co.,...

1. A semiconductor device, comprising:a substrate;
a thin film transistor positioned on the substrate; and
a first light detection structure adjacent to the thin film transistor, wherein:
the first light detection structure comprises a first bottom electrode, a first top electrode, and a first photosensitive portion disposed between the first bottom electrode and the first top electrode;
one of a source electrode and a drain electrode of the thin film transistor is disposed in the same layer as the first bottom electrode of the first light detection structure; and
the other of the source electrode and the drain electrode of the thin film transistor is the first top electrode.

US Pat. No. 10,431,699

TRENCH SEMICONDUCTOR DEVICE HAVING MULTIPLE ACTIVE TRENCH DEPTHS AND METHOD

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device comprising:a region of semiconductor material having a first conductivity type and a major surface;
a first active trench extending from a first portion of the major surface into the region of semiconductor material to a first depth, wherein the first active trench has a first width;
a second active trench extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein the second active trench has a second width, and wherein the second depth is greater than the first depth;
a third trench extending from a fourth portion of the major surface into the region of semiconductor material to a third depth, wherein the third trench is configured as a termination trench, and wherein the third trench is disposed at an edge of the semiconductor device such that the third trench is an outermost trench for the semiconductor device, and wherein the third trench is laterally interposed between the edge and the first and second active trenches, and wherein the third depth is greater than the first depth, and wherein the third trench has a third width that is greater than the first width and the second width;
a first conductive material within the first active trench and separated from the region of semiconductor material by a first dielectric region;
a second conductive material within the second active trench and separated from the region of semiconductor material by a second dielectric region;
a third conductive material adjoining a third portion of the major surface, wherein the third conductive material is configured to provide a Schottky barrier;
a conductive spacer disposed along a sidewall of the third trench and separated from the region of semiconductor material by a third dielectric region that adjoins sidewall and lower surfaces of the third trench; and
a dielectric layer different than the third dielectric region disposed adjacent the conductive spacer within the third trench such that the conductive spacer is laterally interposed between the dielectric layer and the third dielectric region, wherein:
the third depth is greater than the first depth in a range greater than zero to approximately 3.0 microns;
the third depth and the second depth are substantially equal;
the third conductive material physically contacts the conductive spacer; and
the first active trench is interposed between the second active trench and the third trench.

US Pat. No. 10,431,698

SEMICONDUCTOR DEVICE WITH NON-OHMIC CONTACT BETWEEN SIC AND A CONTACT LAYER CONTAINING METAL NITRIDE

Infineon Technologies Aus...

1. A semiconductor device, comprising:a contact layer in contact with silicon carbide (SiC) material, the contact layer comprising a metal nitride having a nitrogen content in a range of 10 to 50 atomic %; and
a non-ohmic contact formed between the SiC material and the contact layer.

US Pat. No. 10,431,697

BI-DIRECTIONAL ZENER DIODE HAVING A FIRST AND SECOND IMPURITY REGIONS GROUPS FORMED IN SURFACE PORTION OF A SUBSTRATE AND A FIRST ELECTRODE ELECTRICALLY CONNECTED TO AT LEAST ONE FIRST IMPURITY REGIONS, AND NOT CONNECTED FROM AT LEAST ANOTHER ONE

ROHM CO., LTD., Kyoto (J...

1. A bidirectional Zener diode comprising:a substrate;
a base region of a first conductivity type formed in a surficial portion of the substrate;
a first impurity region group extending along a predetermined array direction, in which a plurality of first impurity regions of a second conductivity type is arranged in a manner spaced apart from each other along the predetermined array direction, each of the first impurity regions being formed in a surficial portion of the base region so as to form a pn junction between the first impurity region and the base region;
a second impurity region group extending in parallel with the first impurity region group along the predetermined array direction, in which a plurality of second impurity regions of a second conductivity type is arranged in a manner spaced apart from each other along the predetermined array direction, each of the second impurity regions being formed in a surficial portion of the base region in a manner spaced apart from the first impurity regions so as to form a pn junction between the second impurity region and the base region;
a first electrode arranged at a surface of the substrate so as to be connected electrically to at least one of the first impurity regions, and to be disconnected from at least another one of the first impurity regions; and
a second electrode arranged at the surface of the substrate so as to be connected electrically to at least one of the second impurity regions.

US Pat. No. 10,431,696

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH NANOWIRE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device structure, comprising:a substrate comprising a first fin portion;
a first nanowire over the first fin portion, wherein the first nanowire has a polygonal cross-section;
a first gate structure surrounding the first nanowire; and
two first source/drain portions adjacent to the first nanowire, wherein the first nanowire comprises:
two first edge portions adjacent to the two first source/drain portions respectively; and
a first central portion between the two first edge portions,
wherein the two first edge portions have a hexagonal cross-section, and the first central portion has a quadrilateral cross-section.

US Pat. No. 10,431,692

PREPARATION METHODS FOR SEMICONDUCTOR LAYER AND TFT, TFT AND ARRAY SUBSTRATE COMPRISING SEMICONDUCTOR LAYER

BOE TECHNOLOGY GROUP CO.,...

1. A preparation method for a transistor, comprising:forming a silicon dioxide insulating layer as sidewalls at two opposing ends of a semiconductor layer to be formed on a flexible substrate;
subjecting two opposing surfaces of the sidewalls to amination treatment using aminopropyltriethoxy silane (APTES) solution so that an aminosiloxane monolayer self-assembly is formed on the two opposing surfaces of the sidewalls;
carboxylating a carbon nanotube solution and making the carboxylated carbon nanotube solution on a surface of the flexible substrate and between the two opposing surfaces formed with the aminosiloxane monolayer self-assembly to form a carbon nanotube film between the two opposing surfaces;
removing portions of the carbon nanotube film above a top surface of the sidewalls to form the semiconductor layer no higher than the top of the sidewalls;
forming a gate insulating film on the semiconductor layer;
forming via holes in the gate insulating layer;
forming a metal film by vapor deposition or sputtering process; and
forming a source and a drain at the via holes by patterning process such that the source and the drain are in contact with the semiconductor layer.

US Pat. No. 10,431,690

HIGH ELECTRON MOBILITY TRANSISTORS WITH LOCALIZED SUB-FIN ISOLATION

Intel Corporation, Santa...

1. A field effect transistor (FET), comprising:a sub-fin structure comprising:
a fin of a first crystalline material over a surface of a substrate comprising a second crystalline material and surrounded by a dielectric trench material; and a sub-fin isolation material, wherein the sub-fin isolation material is amorphous and extends through at least a portion of the first crystalline material, wherein the sub-fin isolation material has a first lateral dimension orthogonal to a longest length of the fin of the first crystalline material, and the first lateral dimension is larger than a width of the fin of the first crystalline material;
a fin structure comprising a third crystalline material and including a source and a drain on opposite ends of a channel region, the fin structure extending from the sub-fin structure with the channel region separated from the first crystalline material by the sub-fin isolation material;
a gate electrode stack over the channel region, wherein at least a gate electrode of the gate electrode stack has a second lateral dimension orthogonal to the longest length of the fin structure that is larger than the width of the fin structure, and a portion of the gate electrode stack extends over the sub-fin isolation material beyond an edge of the fin structure;
a source contact coupled to the source; and
a drain contact coupled to the drain.

US Pat. No. 10,431,688

THIN-FILM TRANSISTOR STRUCTURE WITH THREE-DIMENSIONAL FIN-SHAPE CHANNEL AND PREPARATION METHOD THEREOF

SUN YAT-SEN UNIVERSITY, ...

1. A preparation method of a thin-film transistor structure with a three-dimensional fin-shape channel, characterized in that, the channel has a fin-type structure which is thick in a middle and thin in both sides, and a preparation process is specifically as follows:(a) depositing and etching a bottom gate electrode on a substrate;
(b) depositing a bottom dielectric layer at an upper part of a structure obtained from the step (a), and sequentially depositing a semiconductor film on the bottom dielectric layer;
(c) etching the semiconductor film to obtain a fin-shape channel;
(d) respectively depositing a source electrode and a drain electrode on the semiconductor film located at both sides of the fin-shape channel, and etching, wherein the source electrode and the drain electrode are not located on a thick portion of the fin-shape channel;
(e) depositing a top dielectric layer and a top gate electrode at an upper part of a structure obtained from the step (d); and
(f) etching the top gate electrode, and completing a preparation of a dual-gate fin-shape channel thin-film transistor.

US Pat. No. 10,431,687

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

16. A method for forming a semiconductor device structure, comprising:forming a fin structure over a semiconductor substrate;
forming a gate electrode over the semiconductor substrate to cover a portion of the fin structure, wherein the gate electrode includes a first portion and a second portion, the second portion nearer a sidewall of the fin structure, wherein the second portion has a width equal to or greater than the first portion;
forming a protection layer over the first portion of the gate electrode and over the second portion of the gate electrode, the protection layer having a first thickness over the first portion and a second thickness over the second portion, the first thickness being greater than the second thickness; and
after forming the protection layer, plasma etching a recess in the gate electrode, wherein the plasma etching reduces the width of the second portion such that it is less than the first portion.

US Pat. No. 10,431,686

INTEGRATED CIRCUIT (IC) EMPLOYING A CHANNEL STRUCTURE LAYOUT HAVING AN ACTIVE SEMICONDUCTOR CHANNEL STRUCTURE(S) AND AN ISOLATED NEIGHBORING DUMMY SEMICONDUCTOR CHANNEL STRUCTURE(S) FOR INCREASED UNIFORMITY

QUALCOMM Incorporated, S...

1. An integrated circuit (IC), comprising:a substrate comprising a diffusion region;
a semiconductor channel structure array disposed above the substrate in the diffusion region and comprising a plurality of channel structures each spaced by a channel structure pitch;
each channel structure among the plurality of channel structures disposed immediately adjacent to at least one neighboring channel structure among the plurality of channel structures; and
the plurality of channel structures comprising:
an active channel structure disposed along a first longitudinal axis, and comprising:
a channel region of the active channel structure;
a first source/drain region disposed at a first end portion of the channel region; and
a second drain/source region at a second end portion of the channel region; and
an isolated neighboring dummy channel structure disposed immediately adjacent to the active channel structure, the isolated neighboring dummy channel structure comprising:
a second channel structure having an outer surface and disposed along a second longitudinal axis substantially parallel to the first longitudinal axis; and
a capping layer disposed on at least a portion of the outer surface of the second channel structure; and
a gate disposed around at least a portion of the channel region of the active channel structure.

US Pat. No. 10,431,685

SEMICONDUCTOR DEVICE INCLUDING GATE HAVING DENTS AND SPACER PROTRUSIONS EXTENDING THEREIN

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including a fin-shaped active region that protrudes from the substrate, the fin-shaped active region including a first side wall opposite a second side wall;
a gate insulating film covering a top surface, the first side wall, and the second side wall of the fin-shaped active region;
a gate electrode on the top surface, the first side wall, and the second side wall of the fin-shaped active region, the gate electrode covering the gate insulating film, the gate electrode including a first sidewall opposite a second sidewall;
one pair of insulating spacers on the first sidewall and the second sidewall of the gate electrode, upper portions of the one pair of insulating spacers including protrusions that protrude from the upper portions of the one pair of insulating spacers toward the gate electrode; and
a source region and a drain region on the substrate and respectively located adjacent to the first sidewall and the second sidewall of the gate electrode such that the gate electrode extends between the source region and the drain region, the source region and the drain region forming a source/drain pair, wherein
the upper portions of the one pair of insulating spacers are defined from regions that extend from uppermost surfaces to heights greater than middle heights, respectively, for the one pair of insulating spacers.

US Pat. No. 10,431,684

METHOD FOR IMPROVING TRANSISTOR PERFORMANCE

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device comprising:a chip of single-crystalline semiconductor having a chip surface and a first zone of field effect transistors (FETs) and circuitry extending to a first depth from the chip surface, the first zone parallel to the chip surface; and
a second zone of polycrystalline semiconductor, the second zone parallel to the chip surface and having a center plane at a second depth from the chip surface, the second depth greater than the first depth, the second zone including a height, lateral extensions and four side surfaces of the chip, the second zone aligned with the FETs in a vertical direction, the vertical direction being perpendicular to a plane parallel to the chip surface.

US Pat. No. 10,431,683

METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH A COMPRESSIVE STRESSED CHANNEL

INTERNATIONAL BUSINESS MA...

1. A method for making a semiconductor device, the method comprising:a) etching a stack of layers arranged on a substrate and comprising at least one layer of a second semiconductor, which is crystalline, arranged between the substrate and at least one layer of a first semiconductor, which is crystalline, wherein the second semiconductor is different from the first semiconductor and subjected to a compressive stress, forming at least one nanowire stack comprising at least one second semiconductor nanowire arranged between the substrate and at least one first semiconductor nanowire,
b) making at least one dummy gate and outer spacers, the at least one dummy gate arranged between the outer spacers, covering at least one part of the nanowire stack, then
c) etching the nanowire stack so only said at least one part of the nanowire stack is preserved, then
d) removing at least one portion of the second semiconductor nanowire, then
e) depositing, into at least one space formed by removing the at least one portion of the second semiconductor nanowire, at least one sacrificial material portion, then
f) making source and drain regions, and making inner spacers around parts of at least one portion of the first semiconductor nanowire which is covered with the outer spacers, then
g) removing the at least one dummy gate and the at least one sacrificial material portion,
h) making a gate between the outer spacers and around the at least one portion of the first semiconductor nanowire forming a channel.

US Pat. No. 10,431,682

VERTICAL VACUUM CHANNEL TRANSISTOR

INTERNATIONAL BUSINESS MA...

1. A vertical transistor, comprising:a fin arranged on a source over a substrate;
a drain arranged over the source such that the source and drain are arranged vertically with respect to one another;
a vacuum channel comprising an opening within the fin arranged between the source and the drain;
a conductive gate stack arranged on and in contact with a first side fin, the conductive gate stack comprising a gate dielectric, a gate workfunction metal, and a gate metal, the gate dielectric arranged on a first sidewall of the opening of the vacuum channel; and
an oxide arranged on an opposing second side of the fin with respect to the conductive gate stack, the oxide arranged on a second sidewall of the opening of the vacuum channel.

US Pat. No. 10,431,681

SEMICONDUCTOR DEVICES AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A method for forming a semiconductor device, the method comprising:depositing a mask layer on a lateral surface of a semiconductor substrate;
structuring the mask layer after depositing to form an opening in the mask layer, wherein the structuring comprises reforming an edge side of the mask layer that faces the opening and is perpendicular to the lateral surface into a mask bevel edge that is angled relative to the lateral surface; and
etching at least a part of the mask layer and the semiconductor substrate during the same etching process to form a trench within an active region of a semiconductor substrate extending into the semiconductor substrate,
wherein the trench comprises a width of less than 10 ?m, and
wherein a sidewall of the trench formed by the etching process comprises a bevel portion based on a reproduction of the mask bevel edge of the mask layer in the semiconductor substrate.

US Pat. No. 10,431,680

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

14. A semiconductor device, comprising:a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and
an insulating layer covering an inner sidewall of the trench such that the insulating layer is in contact with the inner sidewall of the trench,
wherein the inner sidewall of the trench, at an interface with the insulating layer, has at least one plane in a {320} family of planes of the crystal structure or a plane having an angle within 2 degrees of the {320} family of planes of the crystal structure, and
wherein a top surface of the semiconductor substrate has at least one plane in a {100} family of planes of the crystal structure.

US Pat. No. 10,431,679

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a substrate having at least a gate trench extending along a first direction formed therein, wherein the gate trench comprises a plurality of first regions having a depth d1 and a plurality of second regions having a depth d2 arranged alternatingly along the first direction;
a gate dielectric layer conformally covering the gate trench;
a gate metal formed on the gate dielectric layer and partially filling the gate trench; and
a plurality of intervening structures arranged separately along the first direction in a lower portion of the gate trench and disposed between the gate metal and the gate dielectric layer, wherein each of the intervening structures is disposed in one of the second regions.

US Pat. No. 10,431,678

TERMINATION DESIGN FOR TRENCH SUPERJUNCTION POWER MOSFET

NXP USA, Inc., Austin, T...

1. A method for fabricating a semiconductor device comprising:forming a drain with a doped semiconductor substrate;
growing an epitaxial layer on the drain;
forming a plurality of trench stripes in the epitaxial layer, each of the trench stripes disposed in parallel with another of the trench stripes and extending from a top region of a first surface of the semiconductor device to a bottom region of the first surface, the first surface opposing the doped semiconductor substrate;
forming a first polysilicon layer in each of the trench stripes separated from the epitaxial layer by a trench drift oxide, the first polysilicon layer extending between the drain and the first surface proximal to the top region and the bottom region, the first polysilicon layer extending between the drain and a level below the first surface in a middle region between the top region and the bottom region;
depositing a second polysilicon layer over the first polysilicon layer in the middle region, the second polysilicon layer separated from the first polysilicon layer by an inter-poly dielectric, wherein the first polysilicon forms a shield, and the second polysilicon forms a gate; and
forming a source in a silicon mesa stripe surrounding the first trench stripe, wherein the method further comprises:
forming a first semicircular trench between a first one and a second one of the trench stripes, forming a second semicircular trench between the first one and a third one of the trench stripes, the first semicircular trench encircling a fourth trench stripe, the second semicircular trench encircling a fifth trench stripe, the first semicircular trench and the second semicircular trench including the first polysilicon layer.

US Pat. No. 10,431,677

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor layer of SiC which includes an active portion;
a plurality of MIS transistors which are formed at the active portion, the active portion partitioned into the plurality of MIS transistors by a plurality of gate trenches, and each of the MIS transistors having a first conductive-type source region, a second conductive-type channel region, and a first conductive-type drain region sequentially along a side surface of the gate trench;
a plurality of first gate finger trenches which are arranged by extended portions of the gate trenches at a gate finger portion;
a gate electrode embedded in each of the gate trenches and the first gate finger trenches via a gate insulating film;
a second conductive-type first bottom-portion impurity region which is formed at least at a bottom portion of the first gate finger trenches;
a gate finger which is electrically connected to the first gate finger trenches and the gate electrode;
a source electrode formed over the semiconductor layer;
a conductive film between the source electrode and the semiconductor layer, having a second insulating film between the conductive film and the semiconductor layer, the conductive film being present only on the second insulating film, the source electrode being in direct contact with a second conductive-type channel contact region in the semiconductor layer, and the conductive film being between two adjacent gate trenches;
and;
a second conductive-type electric field relaxation region which is formed more deeply than a bottom portion of the first gate finger trench.

US Pat. No. 10,431,675

SINGLE WALLED CARBON NANOTUBE TRIODE

United States of America ...

1. A carbon nanotube triode apparatus, the apparatus comprising:a plurality of Horizontally Aligned Single Wall Carbon Nano Tubes (HA-SWCNT) disposed on an electrically insulating thermally conductive layer of a substrate;
a first contact disposed on the substrate and electrically coupled to a first end of the HA-SWCNT, wherein the first contact is disposed overlapping the first end of the HA-SWCNT in a view perpendicular to the electrically insulting and thermally conductive layer;
a second contact disposed on the substrate, said second contact being entirely separated from the HA-SWCNT by a gap in the view perpendicular to the electrically insulting and thermally conductive layer; and
a gate terminal coincident with a plane of the substrate below the electrically insulting and thermally conductive layer.

US Pat. No. 10,431,674

BIPOLAR JUNCTION TRANSISTOR

UNITED MICROELECTRONICS C...

1. A bipolar junction transistor, comprising:an emitter region comprises a short side and a long side;
a base region comprising a first base region and a second base region, each of the first base region and the second base region comprises a short side and a long side, and the first base region is above the emitter region and the second base region is below the emitter region in a vertical direction extending along the short sides of the first base region and the second base region; and
a collector region comprising a first collector region above the first base region and a second collector region below the second base region in the vertical direction, each of the first collector region and the second collector region comprises a short side and a long side,
wherein an edge of the short side of the emitter region is aligned with an edge of the short side of the first base region, an edge of the short side of the second base region, an edge of the short side of the first collector region, and an edge of the short side of the second collector region respectively, according to a top view, a length of the long side of the emitter region is same as a length of the long side of the first base region and a length of the long side of the first collector region, respectively and a length of the short side of the first base region is less than a length of the short side of the first collector region.

US Pat. No. 10,431,673

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device comprising:at least one fin protruding from a substrate and extending in a first direction;
a plurality of source/drain regions on the at least one fin;
a recess region being between the plurality of source/drain regions;
a device isolation region including a capping layer and a device isolating layer, the capping layer extending along an inner surface of the recess region and the device isolating layer on the capping layer to fill the recess region;
a dummy gate structure on the device isolation region, the dummy gate structure extending in a second direction different from the first direction, and the dummy gate structure including a dummy gate insulating layer;
a plurality of outer spacers on opposite sidewalls of the dummy gate structure;
a plurality of first inner spacers being between the dummy gate structure insulating layer and the plurality of outer spacers; and
a second inner spacer being between the device isolation region and the dummy gate insulating layer, and the second inner spacer being between the plurality of first inner spacers and spaced apart from the capping layer, wherein
the plurality of first inner spacers overlap vertically with a part of the dummy gate structure, and
a width of the second inner spacer is smaller than a width of an upper surface of the dummy gate structure.

US Pat. No. 10,431,672

METHOD OF FORMING A III-V AND ZN BASED FINFET STRUCTURE USING LOW TEMPERATURE DEPOSITION TECHNIQUES

International Business Ma...

1. A method for forming a semiconductor structure comprising:providing a gate structure, wherein the gate structure comprises a gate dielectric in contact with a III-V fin structure;
depositing a spacer material over the gate structure and the fin structure;
recessing the spacer material to form at least one sidewall spacer in contact with the gate structure;
recessing a portion of the fin structure to create a recessed III-V fin structure, wherein the recessing of a portion of the fin structure creates an opening between at least two portions of the deposited spacer material; and
depositing a Zn based material over i) the spacer material, ii) the recessed at least one fin structure, and iii) the gate structure.

US Pat. No. 10,431,671

FIN FIELD-EFFECT TRANSISTOR

Semiconductor Manufacturi...

1. A fin field-effect transistor, comprising:a substrate;
a fin formed on a surface of the substrate;
a liner oxide layer formed on the surface of the substrate at both sides of the fin;
an isolation layer formed on a surface of the liner oxide layer;
a gate dielectric layer formed by oxidizing a transitional layer and oxidizing a surface portion of the fin formed on the surface of the substrate wherein the transitional layer at least has atoms identical to atoms of the fin, on a side and top surface of the fin and a top surface of the isolation layer, wherein the isolation layer is surrounded by the liner oxide layer and the gate dielectric layer, a thickness of the transitional layer is smaller than a thickness of the gate dielectric layer, the thickness of the transitional layer is in a range of approximately 5 ?˜40 ?, and the thickness of the gate dielectric layer is in a range of approximately 10 ?˜60 ?;
a gate electrode layer formed on a surface of the gate dielectric layer; and
doping regions formed in the fin at both sides of the gate electrode layer.

US Pat. No. 10,431,670

SOURCE AND DRAIN FORMATION TECHNIQUE FOR FIN-LIKE FIELD EFFECT TRANSISTOR

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a fin structure, wherein the fin structure includes a channel region disposed between a source region and a drain region;
forming a gate structure over the channel region of the fin structure;
forming a solid phase diffusion (SPD) layer over a topmost surface of the source region and a topmost surface of the drain region of the fin structure; and
after forming the SPD layer, performing a microwave annealing (MWA) process to diffuse a dopant from the SPD layer into the fin structure, such that a doped feature is formed in the source region and the drain region of the fin structure, wherein the source region and the drain region further include sidewall surfaces, and further wherein the SPD layer is disposed over the sidewall surfaces, such that the dopant diffuses laterally and vertically into the source region and the drain region.

US Pat. No. 10,431,669

POLYSILICON THIN FILM AND MANUFACTURING METHOD THEREOF, TFT AND MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of a polysilicon thin film, the method comprising:forming a polysilicon layer;
after forming the polysilicon layer, supplying oxygen gas into a process chamber and performing oxygen plasma treatment on a surface of the polysilicon layer so that oxygen terminal groups are formed on the surface of the polysilicon layer; and
after supplying the oxygen gas, supplying polar gas into the process chamber so that polar molecules of the polar gas are adsorbed onto the oxygen terminal groups formed on the surface of the polysilicon layer so as to form the polysilicon thin film, the surface of the polysilicon layer in the formed polysilicon film has a hole density higher than an electron density.

US Pat. No. 10,431,668

METHOD OF FABRICATING THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A method of fabricating a thin film transistor, comprising:forming an active layer having a channel region, a source electrode contact region, and a drain electrode contact region, on a base substrate;
forming a first photoresist layer on a side of the active layer distal to the base substrate, the first photoresist layer is formed in a region outside that corresponding to the channel region;
forming an insulating material layer on a side of the first photoresist layer distal to the base substrate;
forming a first conductive metal material layer on a side of the insulating material layer distal to the first photoresist layer;
removing the first photoresist layer, the insulating material layer, the first conductive metal material layer, in the region outside that corresponding to the channel region by a lift-off method, a portion of the insulating material layer in a region corresponding to the channel region remains thereby forming a first gate insulating layer, a portion of the first conductive metal material layer in the region corresponding to the channel region remains thereby forming a gate electrode;
forming a second gate insulating layer between the channel region of the active layer and the first gate insulating layer, the second gate insulating layer is formed to be in contact with the channel region of the active layer; and
forming a source electrode, a drain electrode, and the second gate insulating layer in a single process, the source electrode and the drain electrode are formed on a side of the active layer distal to the base substrate;
wherein the second gate insulating layer is formed to have a resistivity higher than that of the first gate insulating layer; and
a projection of the second gate insulating layer on the base substrate substantially overlaps with that of the channel region, the projection of the second gate insulating layer on the base substrate and that of the channel region are substantially coextensive with each other;
wherein forming the source electrode, the drain electrode, and the second gate insulating layer comprises:
forming a second conductive metal material layer on a side of the active layer distal to the base substrate, the second conductive metal material layer is formed to comprise a first portion in a region corresponding to the source electrode contact region of the active layer, a second portion in a region corresponding to the drain electrode contact region of the active layer, and a third portion in a region corresponding to the channel region of the active layer;
forming the first photoresist layer on a side of the second conductive metal material layer distal to the active layer, the first photoresist layer is formed in the region outside that corresponding to the channel region; and
oxidizing the third portion of the second conductive metal material layer thereby forming the second gate insulating layer, the first portion remains substantially unoxidized thereby forming the source electrode, the second portion remains substantially unoxidized thereby forming the drain electrode.

US Pat. No. 10,431,667

VERTICAL FIELD EFFECT TRANSISTORS WITH UNIFORM THRESHOLD VOLTAGE

INTERNATIONAL BUSINESS MA...

14. A semiconductor structure, comprising:semiconductor fins on a substrate, the semiconductor fins being arranged in a direction;
a top source/drain region formed on a top portion of the semiconductor fins;
a spacer layer between the semiconductor fins, the spacer layer being on a surface of the substrate upon which the semiconductor fins are formed;
a work function metal layer on sidewalls of the semiconductor fins, a thickness of the work function metal layer in the direction being uniform; and
a high dielectric constant layer, wherein a first portion of the high dielectric constant layer is on sidewalls of the semiconductor fins, and a second portion of the high dielectric constant layer is over the spacer layer, wherein the high dielectric constant layer and the work function metal layer are on the spacer layer.

US Pat. No. 10,431,666

METHOD OF MAKING A SEMICONDUCTOR SWITCH DEVICE

NXP B.V., Eindhoven (NL)...

1. A method of making a semiconductor switch device, the method comprising:providing a semiconductor substrate having:
a major surface; and
a first semiconductor region having a first conductivity type located adjacent the major surface;
depositing a gate dielectric on the major surface of the substrate;
implanting ions into the first semiconductor region through an opening in a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region, the well region having a second conductivity type different to the first conductivity type;
depositing and patterning a gate electrode material on the gate dielectric to form a gate electrode located directly above the well region; and
performing ion implantation to:
form a source region having said first conductivity type located in the well region on a first side of the gate electrode, and
form a drain region having said first conductivity type located outside the well region on a second side of the gate electrode;
wherein a lateral dimension of the opening in the mask is substantially equal to Lsource+Lg+MTL;
wherein Lsource is a length of the source region measured from an edge of the gate electrode on the first side of the gate electrode;
wherein Lg is a gate length of the semiconductor switch device; and
wherein MTL is a mask tolerance of the opening, and wherein MTL?400 nm.

US Pat. No. 10,431,629

MEMORY ARRAYS AND METHODS OF FORMING AN ARRAY OF MEMORY CELLS

Micron Technology, Inc., ...

12. A method of forming an array of memory cells, comprising:forming access lines relative to a substrate;
forming lines of spaced sense line contacts between and along first pairs of the access lines and forming lines of spaced inner electrode material between and along second pairs of the access lines;
forming lines of covering material that are elevationally over and along the lines of the spaced sense line contacts and between the lines of spaced inner electrode material;
forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material and elevationally over and along the lines of spaced inner electrode material;
removing the covering material over the spaced sense line contacts and exposing the spaced sense line contacts; and
forming sense lines that are electrically coupled to the spaced sense line contacts.

US Pat. No. 10,431,620

SEMICONDUCTOR DEVICE AND ELECTRONIC APPLIANCE

Sony Corporation, Tokyo ...

1. A semiconductor device comprising:a first semiconductor substrate electrically connected to a second semiconductor substrate,
a diffusion prevention film that prevents diffusion of a dangling bond terminating atom used for reducing an interface state of the first semiconductor substrate and the second semiconductor substrate, and
an atom supply film that supplies the dangling bond terminating atom,
wherein the first semiconductor substrate and the second semiconductor substrate are stacked with the diffusion prevention film and the atom supply film between the first semiconductor substrate and the second semiconductor substrate; and
wherein the interface state of the first semiconductor substrate is lower than that of the second semiconductor substrate.

US Pat. No. 10,431,613

IMAGE SENSOR COMPRISING NANOANTENNA

SAMSUNG ELECTRONICS CO., ...

1. An image sensor in which a plurality of nanoantennas are arranged so as to satisfy a sub-wavelength condition, wherein each of the plurality of nanoantennas comprises:a respective diode comprising a first conductive semiconductor layer and a second conductive semiconductor layer; and
a respective transistor comprising a third conductive semiconductor layer that is in contact with the second conductive semiconductor layer, a gate electrode that is in contact with each of the third conductive semiconductor layer and the second conductive semiconductor layer, and a diffusion node that is in contact with the third conductive semiconductor layer and is not in contact with the second conductive semiconductor layer,
wherein the respective diode is disposed on a first surface of the third conductive semiconductor layer and the diffusion node is disposed on a second surface of the third conductive semiconductor which opposes the first surface of the third conductive semiconductor.

US Pat. No. 10,431,612

SWITCHES WITH MULTIPLE FIELD-EFFECT TRANSISTORS HAVING PROXIMITY ELECTRODES

SKYWORKS SOLUTIONS, INC.,...

1. A field-effect transistor (FET) device comprising:an insulator layer;
a substrate layer implemented under the insulator layer;
an active silicon layer implemented over the insulator layer with a first active FET and a second active FET formed from the active silicon layer, each of the first active FET and the second active FET including a source terminal, a drain terminal, and a gate terminal;
a first proximity electrode implemented adjacent to the first active FET, the first proximity electrode configured to receive a voltage and to generate an electric field between the first proximity electrode and a region generally underneath the first active FET; and
a second proximity electrode implemented adjacent to the second active FET, the second proximity electrode configured to receive a voltage and to generate an electric field between the second proximity electrode and a region generally underneath the second active FET.

US Pat. No. 10,431,530

POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

MagnaChip Semiconductor, ...

1. A method of manufacturing a power semiconductor module, the method comprising:preparing a Direct Bonded Copper (DBC) substrate comprising a metal pattern;
forming the power semiconductor module by wire bonding the metal pattern of the DBC substrate and an electrode of a power semiconductor element;
testing whether the power semiconductor module is defective;
coupling the DBC substrate to a base plate; and
coupling the DBC substrate and a lead frame,
wherein the lead frame comprises a first body connected to a first terminal, a second body connected to a second terminal, and third and fourth bodies connected to a third common terminal having a length larger than a length of the first terminal or the second terminal.

US Pat. No. 10,431,504

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES BY BONDING A SEMICONDUCTOR DISK ON A BASE SUBSTRATE, COMPOSITE WAFER AND SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A method of manufacturing semiconductor devices, the method comprising:attaching, by adhesion bonding, a semiconductor disk of a first crystalline material on a process surface of a base substrate, wherein the first crystalline material has a first lattice system and wherein a bonding layer is formed between the semiconductor disk and the base substrate; and
forming by epitaxy a second semiconductor layer of a second crystalline material with a second, different lattice system on a first semiconductor layer formed from the semiconductor disk,
wherein the attaching, by adhesion bonding uses ceramic-forming polymers and the bonding layer includes a ceramic as main constituent.

US Pat. No. 10,431,487

MICRO-TRANSFER-PRINTABLE FLIP-CHIP STRUCTURES AND METHODS

X-Celeprint Limited, Cor...

1. A semiconductor structure suitable for transfer printing, comprising:a handle substrate;
a cured bonding layer disposed in contact with the handle substrate;
a capping layer disposed in contact with the bonding layer;
a patterned release layer disposed in contact with the capping layer; and
a completed semiconductor device disposed on or over the patterned release layer and attached to an anchor disposed on the handle substrate with at least one tether,
wherein the at least one tether is in a common plane with an exposed entry path to the patterned release layer.

US Pat. No. 10,431,485

ARTICLE TRANSPORT FACILITY

Daifuku Co., Ltd., Osaka...

1. An article transport facility comprising:a fixed support portion that is provided in a fixed state and supports an article;
a moving member that moves along a moving path that extends via a stop position that is set for the fixed support portion;
a transfer apparatus that is provided with a moving support portion configured to move integrally with the moving member along a widthwise direction that is orthogonal to a lengthwise direction of the moving path within a horizontal plane, and receives and supplies an article from and to the fixed support portion while the moving support portion moves to protrude and retract between a retracted position at which the moving support portion is housed within the moving path in terms of the widthwise direction and a protruding position at which the moving support portion protrudes outward from the moving path in the widthwise direction; and
a control unit that controls movement of the moving member and a transfer operation that is performed by the transfer apparatus, the control unit configured to execute a stopping control to stop the moving member at the stop position, and a protrusion control to move the moving support portion of the transfer apparatus from the retracted position to the protruding position,
wherein the article transport facility further comprises:
a detection target member that is provided at a position corresponding to the stop position, and has a length that is equal to a length of an acceptable stop range that is an acceptable range of the stop position, in the lengthwise direction; and
a detection unit that is provided on the moving member, at a fixed position relative to the retracted position, and detects the detection target member with the moving member being located within the acceptable stop range, and
the control unit is configured to start execution of the protrusion control upon the moving member reaching a protrusion start position as a result of the stopping control, the protrusion start position being set upstream of the stop position in a direction in which the moving member moves, and after the moving member has reached a protrusion monitoring start position that is set downstream of the protrusion start position in the direction in which the moving member moves toward the stop position, the control unit is configured to continue execution of the protrusion control as long as the detection unit is detecting the detection target member.

US Pat. No. 10,431,455

FEMTOSECOND LASER-INDUCED FORMATION OF SINGLE CRYSTAL PATTERNED SEMICONDUCTOR SURFACE

THE REGENTS OF THE UNIVER...

1. A method of manufacturing a surface corrugation in a material using light energy, said method comprising:applying a plurality of laser energy pulses focused at a surface of the material, each of said plurality of laser energy pulses being about 150 femtoseconds in duration, said plurality of laser energy inducing point defect accumulation and diffusion in the material resulting in epitaxial surface corrugation, the epitaxial surface corrugation having a period less than 0.3 times a wavelength of the laser.

US Pat. No. 10,431,446

WET PROCESSING APPARATUS

NATIONAL INSTITUTE OF ADV...

1. A heating wet processing method, comprising:a placing step of placing a plate-shaped object to be processed on a stage by mounting the object on engaging pins separated from one another at predetermined intervals in a circumferential direction around a condensing plate, the object being mounted on the engaging pins in a state when a surface of the object is oriented upward, and;
a supplying step of supplying a processing liquid from above the stage to the surface of the object placed on the stage; and
a processing step of heating at least an interface between the object and the processing liquid by emitting light:
to the condensing plate to irradiate the object with the light condensed by the condensing plate from a position facing the object engaged by the engaging pins in a state, and
from a position blocked with respect to the stage with a blocking member and irradiate the light to the condensing plate, when the supplying step is supplying the processing liquid, wherein the condensing plate is mounted on the blocking member.

US Pat. No. 10,431,435

WAFER CARRIER WITH INDEPENDENT ISOLATED HEATER ZONES

Applied Materials, Inc., ...

1. An apparatus comprising:a puck to carry a workpiece for fabrication processes;
a heater plate having a plurality of thermally isolated blocks each thermally coupled to the puck, and each having a heater to heat a respective block of the heater plate; and
a cooling plate fastened to and thermally coupled to the heater plate, the cooling plate having a cooling channel to carry a heat transfer fluid to transfer heat from the cooling plate,
wherein each heater extends into a corresponding bore of the cooling plate,
wherein the cooling channel is on each of two opposite sides of each thermally isolated block and thermally coupled to each thermally isolated block to remove heat from the two sides of each thermally isolated block through a heat transfer surface, wherein the heat transfer surface is adjacent to and surrounds the heater of the respective block, and wherein the cooling plate is laterally adjacent to a portion of each of the plurality of thermally isolated blocks.

US Pat. No. 10,431,433

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus comprising:a chamber main body defining a chamber;
a stage, provided in the chamber, including a lower electrode and an electrostatic chuck provided on the lower electrode, on which a focus ring is arranged to surround a substrate mounted on the electrostatic chuck;
a first high frequency power supply configured to supply a first high frequency power for generating plasma of a gas in the chamber;
a second high frequency power supply configured to supply a second high frequency power for ion attraction to the lower electrode;
a DC power supply configured to generate a negative DC voltage to be applied to the focus ring in order to correct inclination of an incident direction of ions to an edge region of the substrate mounted on the electrostatic chuck with respect to a vertical direction;
a switching unit configured to stop the application of the DC voltage to the focus ring; and
a controller configured to control one or both of the high frequency power supply and the second high frequency power supply and control the switching unit,
wherein the controller controls one or both of the first high frequency power supply and the second high frequency power supply to periodically stop the supply of one or both of the first high frequency power and the second high frequency power, and
the controller also controls the switching unit to apply the DC voltage to the focus ring from a first time after a predetermined period of time in which a self-bias voltage of the lower electrode is decreased from a start point of each period in which one or both of the first high frequency power and the second high frequency power are supplied and to stop the application of the DC voltage to the focus ring during each period in which the supply of one or both of the first high frequency power and the second high frequency power is stopped.

US Pat. No. 10,431,432

PLASMA TREATMENT SYSTEM INCLUDING COVER PLATE TO INSULATE WINDOW

SAMSUNG ELECTRONICS CO., ...

1. A plasma treatment system, comprising:a window;
an antenna electrode disposed on the window; and
a cover plate disposed between the antenna electrode and the window, the cover plate extending to a side surface of the window to cover a top surface and at least a portion of the side surface of the window,
wherein the cover plate comprises:
a disk portion disposed on the window to have an opening partially exposing the window;
an upper edge end portion connected to an edge of a top surface of the disk portion to enclose the antenna electrode; and
upper blocks upwardly protruding from the disk portion, the upper blocks disposed between the opening and the antenna electrode and the upper blocks being spaced apart from each other in a substantially equal interval.

US Pat. No. 10,431,431

GAS SUPPLY DELIVERY ARRANGEMENT INCLUDING A GAS SPLITTER FOR TUNABLE GAS FLOW CONTROL

LAM RESEARCH CORPORATION,...

1. A gas supply delivery arrangement for supplying process gas to a chamber of a plasma processing system wherein a semiconductor substrate is processed with gases introduced through at least first, second, and third gas injection zones, comprising:a plurality of process gas supply inlets and a plurality of tuning gas inlets; a mixing manifold comprising a plurality of gas supply sticks each of which is adapted to provide fluid communication with a respective process gas supply;
a plurality of tuning gas sticks each of which is adapted to provide fluid communication with a respective tuning gas supply;
a first gas outlet adapted to deliver gas to the first gas injection zone, a second gas outlet adapted to deliver gas to the second gas injection zone, and a third gas outlet adapted to deliver gas to the third gas injection zone;
a gas splitter in fluid communication with the mixing manifold, the gas splitter including a first valve arrangement which splits mixed gas exiting the mixing manifold into:
a first mixed gas which can be supplied to the first gas outlet; and
a second mixed gas which can at different times be supplied to:
only the second gas outlet;
only the third gas outlet; and
the second and third gas outlets; and
a second valve arrangement which, at different times, selectively delivers tuning gas from the tuning gas sticks to:
only the first gas outlet;
only the second gas outlet;
only the third gas outlet;
only the first and second gas outlets;
only the first and third gas outlets;
only the second and third gas outlets; and
the first, second, and third gas outlets.

US Pat. No. 10,431,430

PLASMA TREATMENT OF AN ELASTOMERIC MATERIAL FOR ADHESION

NIKE, Inc., Beaverton, O...

1. A plasma treatment system, the plasma treatment system comprising:a first plasma torch;
a first multi-axis conveyance mechanism coupled with the first plasma torch, the first multi-axis conveyance mechanism able to position the first plasma torch within a 20-40 millimeter offset height range from a surface of an elastomeric component;
a component identification mechanism; and
computer readable media having instructions embodied thereon that when executed by a processor:
generate a tool path for the first multi-axis conveyance mechanism based on an input from the component identification mechanism; and
control the first plasma torch and the first multi-axis conveyance mechanism to apply plasma to the surface while maintaining the 20-40 millimeter offset height range to form an altered region extending from the surface into the elastomeric component.

US Pat. No. 10,431,426

GAS PLENUM ARRANGEMENT FOR IMPROVING ETCH NON-UNIFORMITY IN TRANSFORMER-COUPLED PLASMA SYSTEMS

LAM RESEARCH CORPORATION,...

1. A gas plenum arrangement for a substrate processing system, the gas plenum arrangement comprising:a gas plenum body having an inner opening and an outer edge, wherein
the gas plenum body is arranged to define a gas plenum between a coil and a processing chamber, and
the coil is arranged around and outside of the outer edge of the gas plenum body; and
a plurality of discrete flux attenuating portions, wherein
the plurality of discrete flux attenuating portions is arranged outside of the outer edge of the gas plenum body and extends radially outward from the outer edge of the gas plenum body, and
the plurality of discrete flux attenuating portions (i) overlaps, in a vertical direction, some angular portions of the coil outside of the outer edge of the gas plenum body and (ii) does not overlap, in the vertical direction, other angular portions of the coil outside of the outer edge of the gas plenum body.

US Pat. No. 10,431,425

POLY-PHASED INDUCTIVELY COUPLED PLASMA SOURCE

Tokyo Electron Limited, ...

1. A system for plasma processing comprising:a metal source configured to supply a metal for ionized physical vapor deposition on a substrate in a process chamber;
a high-density plasma source configured to generate a dense plasma, the high-density plasma source comprising a plurality of individual inductively coupled antennas arranged in a pattern around an axis in the process chamber;
a substrate bias source configured to provide a potential necessary to thermalize and further ionize the plasma;
the high density plasma source including a control system and matching network coupled with the plurality of antennas and configured to deliver power to each individual antenna at an individual phase orientation determined according to a phase arrangement;
the high density plasma source further configured, according to the phase arrangement, for dynamically varying the delivery of power and phase orientation over time to each individual antenna in the process chamber according to a phase pattern to dynamically vary the radiation pattern delivered to the plasma, and for delivering power, in the phase pattern, to a first group of antennas at a synchronized phase at a first time period, and then for sequentially delivering power to other different groups of the antennas at a synchronized phase progressively in the process chamber at further sequential time periods following the first time period for consistent plasma processing.

US Pat. No. 10,431,423

METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

Taiwan Semiconductor Manu...

1. A method of semiconductor device fabrication, comprising:identifying a first template having a first layout pattern with a first pattern density (PD) and a second template having a second layout pattern with a second PD less than the first PD;
splitting the first template into a plurality of subset templates, wherein a first subset template has a first subset PD that is outside of a PD target, and wherein the second PD is outside of the PD target;
performing a PD uniformity (PDU) optimization to both the first subset template and the second template to make the first subset PD and the second PD satisfy the PD target; and
performing multiple individual electron beam (e-beam) lithography exposure processes with an e-beam lithography tool to a semiconductor substrate, using respective ones of the subset templates.

US Pat. No. 10,431,421

APPARATUS AND TECHNIQUES FOR BEAM MAPPING IN ION BEAM SYSTEM

VARIAN SEMICONDUCTOR EQUI...

1. An apparatus for monitoring of an ion beam, comprising:a processor; and
a memory unit coupled to the processor, including a display routine, the display routine operative on the processor to manage monitoring of the ion beam, the display routine comprising:
a measurement processor to:
receive a plurality of spot beam profiles of the ion beam, the spot beam profiles collected during a fast scan of the ion beam and a slow mechanical scan of a detector, conducted simultaneously with the fast scan, the fast scan comprising a plurality of scan cycles having a frequency of 10 Hz or greater along a fast scan direction, and the slow mechanical scan being performed in a direction parallel to the fast scan direction;
receive position information from the detector, the position information comprising a plurality of detector locations, collected at a plurality of instances, wherein the plurality of spot beam profiles correspond to the plurality of detector locations;
determine a spot beam center position at the plurality of detector locations;
determine a difference between the spot beam center position and an ideal center position at a plurality of detector locations; and
send a signal to display the difference as a function of detector location.

US Pat. No. 10,431,419

SPARSE SAMPLING METHODS AND PROBE SYSTEMS FOR ANALYTICAL INSTRUMENTS

Battelle Memorial Institu...

1. A method for sparse sampling with an analytical probe, the method comprising:a) acquiring in a serial mode a plurality of contiguous measured values lying at positions along a scan path extending in a line toward a first direction and having random perturbations in a second direction, wherein the random perturbations are limited within a predetermined distance from the line; and
b) inpainting among the measured values and reconstructing a representation of actual information.

US Pat. No. 10,431,417

CHARGED PARTICLE BEAM DEVICE AND SAMPLE HOLDER

Hitachi High-Technologies...

1. A charged particle beam device comprising a charged particle source, a sample holder placed with a sample thereon, a charged particle beam optical system in which the sample is irradiated with a charged particle emitted from the charged particle source as a charged particle beam, a detector detecting a signal emitted from the sample, and a controller controlling each constituent element, whereinthe sample holder includes
a sample placement portion including a first top surface on which a counterbore part is formed and a rotational axis for rotating the first top surface horizontally, the counterbore part being aligned by being mounted with a sample supporting member having a pattern for alignment including a central marker and a pattern and an address marker for analyzing magnification and a rotation angle,
a sample base portion including an opening through which the sample placement portion is capable of moving vertically and a second top surface around the opening, and
a sample cover portion which has conductivity, includes a window through which the pattern for alignment of the sample supporting member is exposed, and is pressed down toward a direction of the second top surface of the sample base portion, so that a top surface of the sample supporting member placed on the sample placement portion and the second top surface are flush with each other.

US Pat. No. 10,431,416

OBSERVATION SUPPORT UNIT FOR CHARGED PARTICLE MICROSCOPE AND SAMPLE OBSERVATION METHOD USING SAME

HITACHI HIGH-TECHNOLOGIES...

1. An observation support device for observation by irradiating a sample disposed in a non-vacuum space separated by a diaphragm from an inner space of a charged particle optical lens barrel that generates a charged particle beam, with the charged particle beam, comprising:a cover comprising a main body portion which defines a hole portion that forms an observation region where the sample is observed,
wherein the observation support device is disposed directly between the sample and the diaphragm and is mounted on the sample.

US Pat. No. 10,431,413

X-RAY SOURCE AND SYSTEM COMPRISING AN X-RAY SOURCE

LIGHTLAB SWEDEN AB, Upps...

1. An x-ray source configured to provide an omnidirectional transmission of x-ray radiation, the x-ray source comprising:an anode;
a field emission cathode;
an evacuated chamber transparent to x-ray radiation, the anode and the field emission cathode being arranged inside of the evacuated envelope,
wherein the evacuated envelope is an extended tube shaped evacuated chamber having an essentially circular symmetry, the field emission cathode is arranged adjacently to an inside surface of the extended tube shaped evacuated chamber, and the anode is centrally arranged inside of the extended tube shaped evacuated chamber,
the field emission cathode surrounds the anode,
the field emission cathode comprises a plurality of ZnO nanostructures selected to be at least 1 micrometer,
the field emission cathode is substantially transparent to X-ray radiation and formed as a transmission cathode, and
the x-ray source is connected to a controllable high voltage source, electrons during operation of the x-ray source are accelerated from the field emission cathode in a direction towards the anode, and x-ray radiation is omnidirectionally irradiated from the anode towards and through the field emission cathode and out from the x-ray source.

US Pat. No. 10,431,412

COMPACT ION BEAM SOURCES FORMED AS MODULAR IONIZER

Massachusetts Institute o...

1. A compact ion beam source comprising:an electron beam unit, comprising:
a modular housing unit that is selectively impermeable to gasses including oxidizing gaseous molecules, the modular housing unit comprising:
a base portion; and
a membrane window made of a single monolayer two-dimensional material and selectively transmissive to electrons;
an electron beam source disposed in the modular housing unit, the electron beam source comprising:
at least one field emitter element disposed over the base portion, comprising:
a first end that is proximate to the base portion; and
a field emitter tip disposed proximate to a second end that is opposite to the first end; and
at least one gate electrode disposed proximate to the second end of the at least one field emitter element, to apply a potential difference proximate to the field emitter tip of the at least one field emitter elements, thereby extracting electrons from the at least one field emitter tip to form an electron beam; and
at least one anode component disposed in the modular housing unit and configured to accelerate the electron beam in a path directed at the membrane window of the modular housing unit.

US Pat. No. 10,431,409

ELECTRICAL SWITCHING APPARATUS AND ACCESSORY WIRE RETENTION ASSEMBLY THEREFOR

EATON INTELLIGENT POWER L...

1. An accessory wire retention assembly for an electrical switching apparatus, said electrical switching apparatus comprising a housing, separable contacts and an accessory enclosed by the housing, an operating mechanism for opening and closing said separable contacts, and a number of wires adapted to be electrically connected to said accessory, the housing including an interior, an exterior, and an aperture, said wires extending from the interior through said aperture to the exterior, said accessory wire retention assembly comprising:an insert structured to cooperate with the housing and to establish a predetermined position of said wires with respect to said accessory and said aperture; and
a fastening mechanism structured to fasten said wires to said insert to maintain said wires in said predetermined position,
wherein said insert is an elongated molded member comprising a number of molded features structured to cooperate with the housing, said wires, and said fastening mechanism, and
wherein said housing further includes a base and a cover coupled to said base; wherein said aperture extends through said base; and wherein said number of molded features includes a guide portion structured to cooperate with said base to accurately position said insert and said wires proximate said accessary and said aperture.

US Pat. No. 10,431,408

TEMPERATURE SENSITIVE SYSTEM

Tsinghua University, Bei...

5. A temperature sensitive system comprising: a power supply, a detector, a first electrode, a second electrode and an actuator; the power supply, the detector, the first electrode, the second electrode and the actuator are connected to form a loop circuit; wherein the loop circuit is in an on state or an off state, the state of the loop circuit is switched by a deformation of the actuator in response to a temperature change of the actuator; the detector is connected to the actuator in parallel or in series and shows a current change of the loop circuit; wherein the actuator is a free-standing composite structure comprising vanadium dioxide and a plurality of carbon nanotubes.

US Pat. No. 10,431,406

PYROTECHNIC CIRCUIT BREAKER

AUTOLIV DEVELOPMENT AB, ...

1. A pyrotechnic circuit breaker comprising:a housing including a first housing part, a second housing part and at least one cutting chamber;
at least one electrical conductor to be sectioned traversing at least a part of the housing at a level of the at least one cutting chamber, the at least one electrical conductor including a molded-on insert moulded thereon;
at least one punch arranged in the housing facing the at least one cutting chamber and moveable between a first position and a second position, the at least one punch designed to section the at least one electrical conductor during movement of the at least one punch from the first to the second position; and
at least one pyrotechnical actuator for making the at least one punch pass from the first position to the second position when activated;
a seal for sealing the at least one cutting chamber, the seal disposed between the molded-on insert and one of the first housing part and the second housing part,
wherein the seal is compressed directly between the molded-on insert and the one of the first and second housing parts to confine gases in the at least one cutting chamber;
wherein the at least one electrical conductor is elongated in a direction of elongation and wherein the molded on insert surrounds the at least one electrical conductor at a first distinct zone and a second distinct zone, the first and second distinct zones spaced from one another in the direction of elongation.

US Pat. No. 10,431,405

SWITCHING DEVICE COMPRISING A VACUUM TUBE

SIEMENS AKTIENGESELLSCHAF...

1. A switching device comprising:a vacuum tube;
an adjustable drive configured to open and close contacts of the switching device; and
a sensor configured to detect a position of the switching device relative to a mounting location at which the switching device is mounted wherein the detected position is used to adjust the adjustable drive, to at least one of open and close the contacts, wherein the sensor for measuring the position of the switching device is configured to detect a change in an angular position of the switching device.

US Pat. No. 10,431,403

REACTIVE FORCE GENERATION DEVICE

YAMAHA CORPORATION, Hama...

1. A reactive force generation device comprising:a to-be-depressed member including a base section, and a dome section formed of an elastic material and protruding from the base section, a sectional shape of the dome section orthogonal to an axis line of the dome section being substantially line-symmetric about a symmetry axis, the dome section having a three-dimensional shape that is substantially symmetric with respect to a virtual plane containing the symmetry axis and the axis line; and
an opposed member having an opposed surface opposed to a distal end of the dome section, the opposed member in a non-operated state being located remote from the to-be-depressed member,
at least one of the opposed member and the to-be-depressed member being constructed to make a swinging movement in response to a depressing operation applied thereto, wherein the opposed member relatively approaches the base section in response to the depressing operation, the dome section deforms by contact between the opposed surface and the distal end during the relative approaching, and the relative approaching is stopped in a depression-completed state corresponding to a maximum movable range of the opposed member relative to the base section,
the virtual plane being defined so as not to vary throughout an entire depression stroke from an initial state, where no depressing operation is applied yet, to the depression-completed state,
the to-be-depressed member and the opposed member being constructed in such a manner that, as for a variation amount of an angle of the axis line relative to a normal line of the opposed surface during the depression stroke, an acute-side angle defined between the axis line and the normal line of the opposed surface in the initial state falls in an angle range from a first variation amount of the angle of the axis line relative to the normal line during a transition from the initial state to a state where the distal end of the dome section starts contacting the opposed surface to a second variation amount of the angle of the axis line relative to the normal line during a transition from the initial state to the depression-completed state,
the first variation amount of the angle of the axis line relative to the normal line being greater than zero degree.

US Pat. No. 10,431,402

BUTTON SWITCH WITH ADJUSTABLE TACTILE FEEDBACK

DARFON ELECTRONICS CORP.,...

1. A button switch connected to a cap, the button switch comprising:a base having a pillar extending along a Z-axis, the Z-axis, an X-axis and a Y-axis being perpendicular to each other;
a cover disposed on the base;
a flexible acoustic member having a fixing rod and a flexible rod, the fixing rod being fixed to the base;
a sleeve rotatably jacketing the pillar to be movable upward and downward between a high position and a low position along the Z-axis, an upper end of the sleeve passing through the cover to be connected to the cap, the sleeve having an outer annular surface, the outer annular surface having a first convex portion, a first concave portion, a second convex portion, a second concave portion, and a protruding edge located between the second convex portion and the second concave portion;
an upward-force-applying member abutting against the sleeve and the base respectively for driving the sleeve to move away from the base; and
a resilient arm adjacent to the pillar, the resilient arm selectively abutting against the first convex portion at a first position or a second position with rotation of the sleeve on the pillar around the Z-axis when the sleeve is located at the high position, the resilient arm moving to a position corresponding to the first concave portion when the sleeve is located at the low position;
wherein when the sleeve rotates to make the resilient arm abut against the first convex portion at the first position, the protruding edge is misaligned with the flexible rod, and the sleeve receives an external force to move downward along the Z-axis, the flexible rod does not need to cross the protruding edge and the resilient arm moves from the first position to the position corresponding to the first concave portion with downward movement of the sleeve;
when the sleeve rotates to make the resilient arm abut against the first convex portion at the second position, the protruding edge is located above the flexible rod, and the sleeve receives the external force to move downward along the Z-axis, the flexible rod needs to cross the protruding edge and the resilient arm moves from the second position to a position corresponding to the second concave portion with downward movement of the sleeve;
when the sleeve moves downward along the Z-axis and deformation of the flexible rod caused by pressing of the protruding edge is not enough to make the flexible rod cross the protruding edge, the flexible rod deforms downward with the protruding edge;
when deformation of the flexible rod is enough to make the flexible rod cross the protruding edge, the flexible rod is released and then moves upward to collide with the cover for making a sound;
when the external force is released, the upward-force-applying member drives the sleeve to move upward relative to the pillar along the Z-axis for making the resilient arm abut against the first convex portion at the first position or the second position.

US Pat. No. 10,431,400

PROGRAM SWITCH AND MODULAR PROGRAM SWITCH ARRANGEMENT FOR MOUNTING ON A PRINTED CIRCUIT BOARD AND METHOD FOR PRODUCING SUCH A PROGRAM SWITCH ARRANGEMENT

1. A program switch for forming a modular program switch arrangement and for mounting on a printed circuit board, the program switch comprising:a housing;
an insulator component with contact elements arranged thereon; and
a switching element movable between an on switching position and an off switching position and the switching element contacting the contact elements in the on switching position, wherein the housing has a first side wall and a second side wall and at least two connection elements are arranged on each side of the first side wall and the second side wall and spaced apart from each other for connection to adjacent program switches, wherein the at least two connection elements on each side wall are identical, wherein an inner side of the housing is embodied such that the insulator component is positioned in a defined manner in the housing such that the switching element is assigned unambiguously to the on switching position and the off switching position.

US Pat. No. 10,431,396

CHARGING RAM ASSEMBLY, AND PIN ASSEMBLY AND SECURING METHOD THEREFOR

EATON INTELLIGENT POWER L...

1. A pin assembly for a charging ram assembly of an electrical switching apparatus, said charging ram assembly comprising a biasing element, a ram member structured to bias said biasing element, and a plate member, said pin assembly comprising:a pin member structured to extend through said biasing element and said plate member, said pin member having a first end portion and a second end portion disposed opposite and distal from said first end portion;
a plurality of collar members comprising a first collar member and a second collar member each being coupled to said first end portion, each of said first collar member and said second collar member comprising a first disc-shaped portion, a second disc-shaped portion disposed opposite the first portion, and a third disc-shaped portion extending between the first portion and the second portion; and
a securing apparatus comprising a retaining member coupled to said first collar member and said second collar member in order to prevent said pin member from moving with respect to said first collar member and said second collar member,
wherein the first portion, the second portion, and the third portion each have a width; and
wherein the width of the third portion is less than the width of the first portion and the width of the second portion.

US Pat. No. 10,431,395

MULTI-FUNCTION CONTROLLER AND MOBILE DEVICE HAVING SAME

HON HAI PRECISION INDUSTR...

1. A multi-function controller comprising:a mounting member having a receiving hole defined therein;
a control member partially received in the receiving hole of the mounting member, and being capable of being pressed and rotated with respect to the mounting member;
a first switch located at an end of the mounting member;
a second switch disposed at a peripheral wall of the mounting member,
a third switch located spaced from the second switch and at the peripheral wall of the mounting member; and
a processing unit, the processing unit being electrically connected to the first switch, the second switch, and the third switch;
wherein the processing unit is configured for selectively receiving a first control signal from the first switch when the control member is pressed, receiving a second control signal from the second switch when the control member is rotated clockwise, or receiving a third control signal from the third switch when the control member is rotated counterclockwise, wherein the control member comprises a control tube received in the receiving hole of the mounting member and a control ring, the control tube comprises a conventional audio jack, an open end and a closed end, the control ring extends from the open end of the control tube.

US Pat. No. 10,431,394

CAPACITOR

Panasonic Intellectual Pr...

1. A capacitor comprising a capacitor element including a positive electrode and a negative electrode, whereinat least one of the positive electrode and the negative electrode contains activated carbon,
a sum of volumes per unit weight of pores having a pore diameter of from 30 ? to 100 ? inclusive among pores of the activated carbon is 0.2 cm3/g or more,
in a volume distribution of the pores of the activated carbon, a top of a maximum peak in the volume distribution is situated at a position corresponding to a pore diameter of more than 1 ? and less than 20 ?, and
an absolute value of an average slope of the volume distribution of the pores of the activated carbon versus the logarithmic pore diameter at pore diameters ranging from 40 ? to 100 ? is less than an absolute value of an average slope of the volume distribution of the pores of the activated carbon versus the pore diameter at pore diameters ranging from 100 ? to 300 ?.

US Pat. No. 10,431,392

ELECTRICAL STORAGE DEVICE, MANUFACTURING METHOD OF THE SAME, AND SEPARATOR

PANASONIC INTELLECTUAL PR...

1. An electrical storage device comprising:an electrical storage element including:
an anode body;
a cathode body facing the anode body; and
a separator including a separator substrate and a conductive polymer adhering to the separator substrate, and interposed between the anode body and the cathode body; and
an electrolytic solution with which the electrical storage element is impregnated, wherein:
the separator includes a first surface layer having a first surface facing the anode body, and a second surface layer having a second surface facing the cathode body,
the first surface layer includes a first region that is not provided with the conductive polymer,
the second surface layer includes a second region provided with the conductive polymer,
the first surface layer includes a third region provided with the conductive polymer, and
an area, of the third region in the first surface layer, facing the anode body is smaller than an area, of the second region in the second surface layer, facing the cathode body.

US Pat. No. 10,431,391

CAPACITOR PACKAGE STRUCTURE AND ANTI-OXIDATION ELECTRODE FOIL THEREOF

APAQ TECHNOLOGY CO., LTD....

1. An anti-oxidation electrode foil, comprising:a base material structure having a top surface and a bottom surface;
a first conductive material structure disposed on the top surface of the base material structure; and
a first carbonaceous material structure disposed on the first conductive material structure;
wherein one portion of the first conductive material structure is a first outermost layer for contacting the first carbonaceous material structure, the first outermost layer of the first conductive material structure is a first oxygen-containing metal compound layer formed by an oxidation process, and the first oxygen-containing metal compound layer is disposed between the other portion of the first conductive material structure and the first carbonaceous material structure so as to prevent oxygen from contacting the other portion of the first conductive material structure;
wherein, the first conductive material structure composed of a Ti layer, a TiNx layer formed on the Ti layer, and a TiNxCy layer (0?x?1) formed on the TiNx layer; the first conductive material structure is heated so as to transform the TiNxCy layer into a TiNxCyOz layer.

US Pat. No. 10,431,390

ELECTROLYTIC CAPACITOR AND METHOD FOR MANUFACTURING SAME

Panasonic Intellectual Pr...

1. An electrolytic capacitor comprising:an anode body having a dielectric layer on a surface of the anode body;
a cathode body; and
an electrolytic solution interposed between the anode body and the cathode body,
wherein:
the electrolytic solution contains a first ester compound and a second ester compound, the first ester compound being a condensate of boric acid and a sugar alcohol, and
the second ester compound contains at least one condensate selected from the group consisting of a condensate of boric acid and a monool compound and a condensate of boric acid and a polyol compound excluding a sugar alcohol.

US Pat. No. 10,431,385

MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a pair of external electrodes;
a first internal electrode that contains a base metal and is coupled to one of the pair of external electrodes;
a dielectric layer that is stacked on the first internal electrode and contains a ceramic material and the base metal, wherein a main component of the dielectric layer is the ceramic material; and
a second internal electrode that is stacked on the dielectric layer, contains the base metal, and is coupled to another one of the pair of external electrodes, wherein
a concentration of the base metal in each of five regions is within ±20% of an average of the concentrations of the base metal in the five regions, each of the five regions including the base metal, the five regions being obtained by dividing a region of the dielectric layer equally into five in a stacking direction, the region of the dielectric layer being located from a location 50 nm away from the first internal electrode to a location 50 nm away from the second internal electrode in the stacking direction between the first internal electrode and the second internal electrode, wherein abundance of Ba and Ti in each of the five regions is more than 90% as measured by measuring abundance of Ba atoms and Ti atoms by a transmission electron microscope,
an average grain size in the dielectric layer is 200 nm or less, and
the region located from the location 50 nm away from the first internal electrode to the location 50 nm away from the second internal electrode includes both a crystal grain of the ceramic material and a crystal grain boundary of the crystal grain.

US Pat. No. 10,431,383

MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a pair of external electrodes;
a first internal electrode that contains a base metal and is coupled to one of the pair of external electrodes;
a dielectric layer that is stacked on the first internal electrode and contains a ceramic material and the base metal, wherein a main component of the dielectric layer is the ceramic material; and
a second internal electrode that is stacked on the dielectric layer, contains the base metal, and is coupled to another one of the pair of external electrodes, wherein
a concentration of the base metal in each of five regions is within ±20% of an average of the concentrations of the base metal in the five regions, each of the five regions including the base material, the five regions being obtained by dividing a region of the dielectric layer equally into five in a stacking direction, the region of the dielectric layer being located from a location 50 nm away from the first internal electrode to a location 50 nm away from the second internal electrode in the stacking direction between the first internal electrode and the second internal electrode, wherein abundance of Ba and Ti in each of the five regions is more than 90% as measured by measuring abundance of Ba atoms and Ti atoms by a transmission electron microscope,
a thickness of the first internal electrode and a thickness of the second internal electrode are 0.2 ?m or greater, and
the region located from the location 50 nm away from the first internal electrode to the location 50 nm away from the second internal electrode includes both a crystal grain of the ceramic material and a crystal grain boundary of the crystal grain.

US Pat. No. 10,431,381

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body having a length and a width substantially equal to each other, and including dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, the capacitor body having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces and the third and fourth surfaces and opposing each other;
a first external electrode disposed on the third surface of the capacitor body, a portion of the first external electrode extending to cover a portion of the fifth surface of the capacitor body; and
a second external electrode disposed on the fourth surface of the capacitor body, a portion of the second external electrode extending to cover a portion of the sixth surface of the capacitor body,
wherein each of the plurality of first internal electrodes has a first lead portion exposed to a first corner of the capacitor body in which the third and fifth surfaces of the capacitor body meet each other and covered with the first external electrode, such that adjacent edges of each of the plurality of first internal electrodes are spaced apart from the third and fifth surfaces of the capacitor body, respectively, by a substantially same distance, and
each of the plurality of second internal electrodes has a second lead portion exposed to a second corner of the capacitor body at which the fourth and sixth surfaces of the capacitor body meet each other and covered with the second external electrode, such that adjacent edges of each of the plurality of second internal electrodes are spaced apart from the fourth and sixth surfaces of the capacitor body, respectively, by a substantially same distance.

US Pat. No. 10,431,379

METHOD OF MANUFACTURING A MULTILAYER CERAMIC CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A method of manufacturing a multilayer ceramic capacitor, comprising:preparing a first ceramic green sheet on which a plurality of stripe-type first inner electrode patterns are formed to be spaced apart from one another by a predetermined distance and a second ceramic green sheet on which a plurality of stripe-type second inner electrode patterns are formed to be spaced apart from one another by a predetermined distance;
forming a ceramic green sheet laminate by alternately stacking the first ceramic green sheet and the second ceramic green sheet in such a manner that a central portion of each of the stripe-type first inner electrode patterns and a predetermined distance between the stripe-type second inner electrode patterns overlap with each other;
forming first and second groove portions on at least one of a top surface and a bottom surface of the ceramic green sheet laminate, wherein the first groove portions are formed at locations aligned, in a stacking direction of the ceramic green sheet laminate, with the predetermined distance formed between the stripe-type first inner electrode patterns formed on the first ceramic green sheet, and the second groove portions are formed at locations aligned, in the stacking direction of the ceramic green sheet laminate, with the predetermined distance formed between the stripe-type second inner electrode patterns formed on the second ceramic green sheet; and
cutting the ceramic green sheet laminate.

US Pat. No. 10,431,375

HARDENED INDUCTIVE DEVICE AND SYSTEMS AND METHODS FOR PROTECTING THE INDUCTIVE DEVICE FROM CATASTROPHIC EVENTS

ABB Schweiz AG, Baden (C...

1. An inductive device comprising: a tank with top, bottom and side walls, and wherein each said side wall has an outer substrate surface; a core having at least one core limb extending between a pair of yokes, at least one coil assembly mounted to the at least one core limb, and an insulating medium disposed in an internal volume of said tank; and a coating layer bonded to said tank side wall outer substrate surfaces, and wherein said coating is a polyurea coating upon reaction, said polyurea coating formed of first and second components prior to reaction, comprising: a first component comprising a member selected from the group consisting of an aromatic diisocyanate and an aliphatic diisocyanate; and a second component comprising a polyamine.

US Pat. No. 10,431,372

HIGH CURRENT, LOW EQUIVALENT SERIES RESISTANCE PRINTED CIRCUIT BOARD COIL FOR POWER TRANSFER APPLICATION

Futurewei Technologies, I...

1. A device, comprising:a housing; and
a wireless charging coil, the coil including a layered structure of electric conductors on a printed circuit board (PCB), wherein the layered structure comprises:
a first layer including a first electrically conductive trace comprising a first turn and a second turn adjacent to the first turn;
a second layer including a second electrically conductive trace comprising a third turn and a fourth turn adjacent to the third turn; and
a plurality of vias coupling the first layer and the second layer, wherein the plurality of the vias include a first via, a second via and a third via distributed separately along a length of the first turn, each of the first via, the second via and the third via electrically connecting the first turn and the third turn, wherein the plurality of the vias further include a fourth via, a fifth via and sixth via distributed separately along a length of the second turn, each of the fourth via, fifth via and sixth via connecting the second turn and the fourth turn, wherein thickness of the device is less than 1 centimeter.

US Pat. No. 10,431,342

TRACKING THE PROBABILITY FOR IMMINENT HYPOGLYCEMIA IN DIABETES FROM SELF-MONITORING BLOOD GLUCOSE (SMBG) DATA

University of Virginia Pa...

1. A method for maintaining the health of a diabetic patient by preventing the occurrence of a hypoglycemic event in said patient, comprising:obtaining self monitoring blood glucose (SMBG) readings from the patient;
measuring glycemic variability of said patient and low blood glucose (BG) of said patient based on said obtained SMBG readings;
creating in a processor a bivariate distribution that maps probability for an upcoming hypoglycemic event in said patient jointly to values of said measured glycemic variability and said measured low blood glucose (BG);
optimizing in said processor the bivariate distribution to achieve prediction of a predetermined percentage of hypoglycemic events below a predetermined BG value occurring in said patient within a predetermined future time period;
tracking in said processor the optimized distribution over time using routine SMBG readings from the patient;
outputting via said processor a message to said patient when said optimized distribution indicates a certain probability for the occurrence of a hypoglycemic event in said patient within said predetermined future time period, based on SMBG data obtained from said patient; and
causing said patient to take a physical action in response to receiving said message to prevent a hypoglycemic event from occurring in said patient.

US Pat. No. 10,431,320

SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND METHOD OF OPERATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of testing a semiconductor memory device comprising a memory cell block including a plurality of memory cells, a first group of word lines coupled to first memory cells among the plurality, and a second group of word lines coupled to second memory cells among the plurality that alternate with the first group, the method comprising:writing data to the first and second memory cells during a first period;
applying a first boosted voltage to the second group of word lines and a second boosted voltage to the first group of word lines during a second period after the first period, wherein the first boosted voltage has a voltage level different from that of the second boosted voltage; and
reading the data from the first memory cells coupled to the first group of the word lines during a third period after the second period to determine whether each of the first memory cells is defective.

US Pat. No. 10,431,319

SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells; and
a controller, wherein the controller is coupled to the array of memory cells and includes control circuitry configured to:
store a number of sets of trim settings; and
select a particular set of trims settings of the number of sets of trim settings including particular trim setting parameters based on desired operational characteristics for the array of memory cells, wherein the particular trim setting parameters include programming signal magnitude, sensing signal magnitude, erase signal magnitude, programming signal length, erase signal length, and sensing signal length.

US Pat. No. 10,431,318

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor; and
a ninth transistor,
wherein:
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor have a same conductivity type;
one of a source and a drain of the first transistor is electrically connected to a first wiring;
the other of the source and the drain of the first transistor is electrically connected to a second wiring;
one of a source and a drain of the second transistor is electrically connected to the second wiring;
the other of the source and the drain of the second transistor is electrically connected to a third wiring;
one of a source and a drain of the third transistor is electrically connected to a fourth wiring;
the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring;
one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor;
one of a source and a drain of the sixth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor;
a gate of the sixth transistor is electrically connected to the gate of the first transistor;
a gate of the seventh transistor is electrically connected to the other of the source and the drain of the third transistor;
one of a source and a drain of the eighth transistor is electrically connected to the fourth wiring;
the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor;
the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring;
a first conductive layer is electrically connected to a third conductive layer through a second conductive layer;
the first conductive layer is configured to be the gate of the first transistor;
the third conductive layer is configured to be a gate of the third transistor, and
the second wiring is configured to transmit a signal being output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor.

US Pat. No. 10,431,317

MEMORY SYSTEM

NXP B.V., Eindhoven (NL)...

1. A memory system comprising:a memory cell comprising:
a poly-fuse-resistor,
a bipolar junction transistor having a collector-emitter channel and a base-terminal, wherein the collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal; and the base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor, and
a NOR logic gate having p-channel transistors configured to provide the transistor-control-signal.

US Pat. No. 10,431,316

MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A memory system comprising:a nonvolatile memory device including a plurality of memory cells; and
a controller including a control unit and a random-access memory, and configured to determine, by applying a program verify voltage to at least one memory cell to be programmed with program data, whether the program data is programmed,
wherein the control unit determines percentages of a count of read requests received from a host device and a count of program requests received from the host device, and adjusts a level of the program verify voltage based on the percentages.

US Pat. No. 10,431,315

OPERATION METHOD OF A NONVOLATILE MEMORY DEVICE FOR CONTROLLING A RESUME OPERATION

SAMSUNG ELECTRONICS CO., ...

1. An operation method of a nonvolatile memory device for erasing a selected memory block from among a plurality of memory blocks, the method comprising:performing an erase operation;
suspending the erase operation after performing a first portion of the erase operation;
resuming the erase operation to perform a second portion of the erase operation, wherein the erase operation is resumed when a resume time, which is a time elapsed since the erase operation was suspended, is less than a reference time, wherein the reference time is a length of time for securing reliability of the erase operation with respect to a threshold voltage distribution of the suspended erase operation; and
erasing a memory block different than the selected memory block when the resume time is equal to or greater than the reference time.

US Pat. No. 10,431,314

NON-VOLATILE MEMORY DEVICE FOR IMPROVING DATA RELIABILITY AND OPERATING METHOD THEREOF

Samsung Electronics Co., ...

1. A non-volatile memory device, comprising:a memory cell array comprising a plurality of memory cells connected to a plurality of word lines, some of the plurality of word lines corresponding to a deterioration area; and
a voltage generator configured to generate a program voltage provided to the plurality of memory cells through the plurality of word lines,
wherein control logic implemented by the non-volatile memory device is configured to control a program operation and an erase operation on the plurality of word lines,
wherein the deterioration area comprises word lines of a first group, where data of at least one first bit is written in each of the plurality of memory cells, and word lines of a second group where data of at least two second bits is written in each of the plurality of memory cells, wherein the at least two second bits are more than the at least one first bits, and
wherein the control logic is configured to control a program sequence so that each of the word lines of the second group is programmed after an adjacent word line of the first group is programmed, and control a distribution so that a threshold voltage level corresponding to an erase state of each of the word lines of the first group is higher than a threshold voltage level corresponding to an erase state of each of the word lines of the second group.

US Pat. No. 10,431,313

GROUPING MEMORY CELLS INTO SUB-BLOCKS FOR PROGRAM SPEED UNIFORMITY

SanDisk Technologies LLC,...

1. A memory device, comprising:a set of NAND strings which extends through a plurality of word line layers, wherein the plurality of word line layers are vertically spaced apart from one another by dielectric layers in a stack, the set of NAND strings comprises one row of NAND strings at one distance from a first edge of the plurality of word line layers and another row of NAND strings at another distance from the first edge of the plurality of word line layers, greater than the one distance; and
a control circuit configured to program the one row of NAND strings and to separately program the another row of NAND strings, wherein the control circuit is configured to program the one row of NAND strings using incremental step pulse programming with one initial program voltage and to program the another row of NAND strings using incremental step pulse programming with another initial program voltage which is higher than the one initial program voltage.

US Pat. No. 10,431,312

NONVOLATILE MEMORY APPARATUS AND REFRESH METHOD THEREOF

Winbond Electronics Corp....

1. A non-volatile memory apparatus, comprising:a non-volatile memory; and
a control circuit, coupled to the non-volatile memory and refreshing a non-selected block when an erasing operation is performed, wherein the non-selected block comprises a plurality of memory sectors, each of the memory sectors comprises a plurality of memory cells, and the control circuit determines whether threshold voltages of the memory cells in the memory sectors are larger than a refresh read reference voltage and smaller than a refresh program verify reference voltage, wherein the control circuit determines that a memory cell needs refreshing if the threshold voltage of the memory cell is larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage,
wherein the control circuit further determines whether a first memory sector to which a current address corresponds comprises the memory cell having the threshold voltage larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage, and if the first memory sector to which the current address corresponds does not comprise the memory cell having the threshold voltage larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage, a refresh operation of the remaining memory sectors in the non-selected block is skipped to complete the refresh operation of the non-selected block.

US Pat. No. 10,431,311

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a plurality of conductors being stacked with insulators being interposed therebetween;
a pillar through the plurality of conductors, the pillar including a first pillar portion, a second pillar portion above the first pillar portion, and a joint portion between the first pillar portion and the second pillar portion, the pillar functioning as a transistor in parts where the pillar crosses the respective conductors; and
a controller configured to perform a write operation, wherein
among the plurality of conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line,
among the plurality of conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line,
the controller
performs a program loop which includes a program operation in the write operation, the program operation including a pre-charge operation,
applies a first voltage higher than a ground voltage to the first word line, the first dummy word line, the second dummy word line, and the second word line, in the pre-charge operation in the write operation for which the first word line is selected,
applies a second voltage lower than the first voltage to the first word line, and applies the first voltage to the second dummy word line and the second word line, in the pre-charge operation in the write operation for which the second word line is selected.

US Pat. No. 10,431,310

BOOSTED CHANNEL PROGRAMMING OF MEMORY

Micron Technology, Inc., ...

1. A method of operating a memory, comprising:boosting a channel voltage of a first memory cell selected for programming to a first voltage level for a particular programming pulse, and boosting a channel voltage of a second memory cell selected for programming to a second voltage level for the particular programming pulse;
boosting the channel voltage of the first memory cell selected for programming to a third voltage level, greater than the first voltage level, for a subsequent programming pulse, and boosting the channel voltage of the second memory cell selected for programming to a fourth voltage level, greater than the second voltage level, for the subsequent programming pulse; and
boosting the channel voltage of the first memory cell selected for programming to a fifth voltage level, greater than the third voltage level, for a next subsequent programming pulse, and boosting the channel voltage of the second memory cell selected for programming to a sixth voltage level, greater than the fourth voltage level, for the next subsequent programming pulse;
wherein the sixth voltage level is greater than the fifth voltage level;
wherein a difference between the third voltage level and the first voltage level is the same as a difference between the fifth voltage level and the third voltage level;
wherein a difference between the fourth voltage level and the second voltage level is the same as a difference between the sixth voltage level and the fourth voltage level;
wherein the second memory cell is selected for programming to a data state corresponding to a range of threshold voltages less than a range of threshold voltages corresponding to a data state to which the first memory cell is selected for programming; and
wherein the difference between the third voltage level and the first voltage level is different than the difference between the fourth voltage level and the second voltage level.

US Pat. No. 10,431,309

SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a bit line;
a source line;
a memory cell unit including
a first selection transistor connected to the bit line,
a second selection transistor connected to the source line, and
a plurality of memory cells connected in series between the first selection transistor and the second selection transistor, the memory cells including
a first memory cell,
a second memory cell located closer to the first selection transistor than the first memory cell,
a third memory cell located closer to the first selection transistor than the second memory cell, and
a fourth memory cell located closer to the first selection transistor than the third memory cell;
a first word line connected to the first memory cell;
a second word line connected to the second memory cell;
a third word line connected to the third memory cell;
a fourth word line connected to the fourth memory cell;
a driver circuit configured to apply a voltage to
the first word line,
the second word line,
the third word line, and
the fourth word line;
a first transistor including a first diffused layer connected to the first word line and a second diffused layer connected to the driver circuit;
a second transistor connected between the second word line and the driver circuit;
a third transistor connected between the third word line and the driver circuit; and
a fourth transistor connected between the fourth word line and the driver circuit,
wherein when data is written into the first memory cell,
a first voltage is applied to
the first word line,
a second voltage is applied to
the second word line,
a third voltage is applied to
the third word line, and
a fourth voltage is applied to
the fourth word line,
wherein the first voltage is larger than the second voltage, the third voltage and the fourth voltage, the second voltage is larger than the third voltage, and the fourth voltage is larger than the third voltage,
wherein the second word line, the third word line, and the fourth word line are not located above the first diffused layer and the second diffused layer, and
wherein each of the first word line, the second word line, the third word line, and the fourth word line is arranged in a first direction,
wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor has a gate length in a second direction perpendicular to the first direction,
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged in the first direction, and
wherein a distance between the first transistor and the memory cell unit is smaller than a distance between the second transistor and the memory cell unit.

US Pat. No. 10,431,307

ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIONS WITH CONTENT ADDRESSABLE MEMORY (CAM) CIRCUITS

INTERNATIONAL BUSINESS MA...

1. A circuit comprising:a first portion of a content addressable memory (CAM) configured to perform a first inequality operation implemented between 1 to n CAM entries, wherein the 1 to n CAM entries of the first portion are read from left to right to perform the first inequality operation;
a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries, wherein the 1 to n CAM entries of the second portion are read from right to left to perform the second inequality operation;
a first matchline configured to indicate a match or mismatch for each of the 1 to n CAM entries implemented in the first portion; and
a second matchline configured to indicate a match or mismatch for each of the 1 to n CAM entries implemented in the second portion,
wherein the first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines,
wherein two valid bits are provided for each of the 1 to n CAM entries as extra bits, in addition to data bits defining each of the 1 to n CAM entries, to indicate that the data bits defining each of the 1 to n CAM entries comprise a valid pattern,
wherein the first and second portions of the CAM are each comprised of binary CAM (BCAM) cells,
wherein, for each 1 to n CAM entry, the valid bit is latched in a latch circuit, wherein the latch circuit is coupled to a precharge driver for the first and second matchlines such that the first and second matchlines will only be precharged when the valid bit for a corresponding one of the 1 to n CAM entries is latched in the latch circuit, and
wherein, for each 1 to n CAM entry, one valid bit is provided for the first matchline and another valid bit is provided for the second matchline.

US Pat. No. 10,431,306

RECONFIGURABLE SEMICONDUCTOR INTEGRATED CIRCUIT

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor integrated circuit comprising:first wiring lines;
at least two second wiring lines intersecting with the first wiring lines;
third wiring lines intersecting with the first wiring lines;
first memory elements disposed in a cross region between the first wiring lines and the second wiring lines, at least one of the first memory elements including a first terminal connected to corresponding one of the first wiring lines and a second terminal connected to corresponding one of the second wiring lines;
second memory elements disposed in a cross region between the first wiring lines and the third wiring lines, at least one of the second memory elements including a third terminal connected to corresponding one of the first wiring lines and a fourth terminal connected to corresponding one of the third wiring lines;
a first write control circuit connected to the first wiring lines;
a first circuit connected to one of the second wiring lines, the first circuit supplying a first potential;
a second circuit connected to the other one of the second wiring lines, the second circuit supplying a second potential lower than the first potential;
SRAM cells disposed to correspond to the third wiring lines, and at least one of the SRAM cells being connected to corresponding one of the third wiring lines; and
a selection circuit including input terminals corresponding to the first wiring lines and an output terminal, each of the input terminals being electrically connected to corresponding one of the first wiring lines, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.

US Pat. No. 10,431,305

HIGH-PERFORMANCE ON-MODULE CACHING ARCHITECTURES FOR NON-VOLATILE DUAL IN-LINE MEMORY MODULE (NVDIMM)

Advanced Micro Devices, I...

1. A hybrid memory module, comprising:a first non-volatile memory;
a first integrated control buffer coupled directly to the first non-volatile memory, wherein the first integrated control buffer operates as both a data buffer and a multiplexer; and
a first volatile memory and a first volatile memory tag unit coupled directly to the first integrated control buffer, wherein the first integrated control buffer is integrated with first cache integration logic to perform cache operations and the first integrated control buffer performs data multiplexing between at least two of the first non-volatile memory, the first volatile memory, and the first volatile memory tag unit, wherein the cache operations include at least one of instructing the first non-volatile memory and the first volatile memory to load a cache line when a miss operation occurs, write back to the cache line when an eviction occurs, or read the cache line when a hit operation occurs.

US Pat. No. 10,431,304

METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION

ARM Ltd., Cambridge (GB)...

1. A method comprising:applying a first programing signal across first and second terminals of a correlated electron switch (CES) element to place the CES element in a conductive or low impedance state;
applying a second programming signal across the first and second terminals to place the CES element in an insulative or high impedance state, the second programming signal comprising a second voltage across the first and second terminals; and
applying a third voltage across the first and second terminals as a supply voltage during a read operation, and wherein a magnitude of the third voltage is equal or greater to a magnitude of the second voltage.

US Pat. No. 10,431,303

RESISTANCE CHANGE TYPE MEMORY INCLUDING WRITE CONTROL CIRCUIT TO CONTROL WRITE TO VARIABLE RESISTANCE ELEMENT

NATIONAL INSTITUTE OF ADV...

1. A resistance change type memory comprising:a variable resistance element connected between a first bit line and a second bit line;
a write control circuit including
a first transistor including a first terminal connected to the first bit line;
a second transistor including a second terminal connected to the first bit line;
a first element including a first output terminal outputting a first signal which controls ON and OFF of the first transistor;
a first interconnect connected to the first output terminal; and
a second element including a first input terminal connected to the first interconnect, and a second output terminal outputting a second signal which controls ON and OFF of the second transistor, the second signal being based on the first signal from the first interconnect,
the write control circuit controlling write to the variable resistance element;
a second interconnect supplied with a first voltage and connected to the first bit line via the first transistor; and
a third interconnect supplied with a second voltage which is higher than the first voltage, and connected to the first bit line via the second transistor,
wherein the write control circuit:
supplies the first voltage to the first bit line via the first transistor which is in an ON state;
sets the second transistor in an ON state after supplying the first voltage; and
supplies the second voltage to the first bit line with a first pulse width via the second transistor which is in the ON state.

US Pat. No. 10,431,302

METHODS, ARTICLES, AND DEVICES FOR PULSE ADJUSTMENT TO PROGRAM A MEMORY CELL

Micron Technology, Inc., ...

1. A method, comprising:determining that a resistance value for a memory cell is lower than a previous resistance value for the memory cell;
adjusting a parameter of an electrical pulse based at least in part on determining that the resistance value is lower than the previous resistance value; and
applying the electrical pulse to the memory cell based at least in part on the adjusted parameter.

US Pat. No. 10,431,301

AUTO-REFERENCED MEMORY CELL READ TECHNIQUES

Micron Technology, Inc., ...

1. A method, comprising:initializing a counter in a controller coupled with a memory array;
activating at least a portion of a first group of memory cells of the memory array by applying a read voltage to the memory array;
determining that a set of memory cells has been activated based at least in part on applying the read voltage;
updating the counter to a first value based at least in part on determining that the set of memory cells has been activated;
comparing the first value of the updated counter to a threshold stored at the controller; and
reading one or more memory cells of the memory array based at least in part on the comparison.

US Pat. No. 10,431,300

NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A nonvolatile memory device comprising:a memory cell array including a plurality of memory cells and dummy cells formed on a body;
a row decoder connected to the memory cells through word lines;
a dummy bit line bias circuit connected to the dummy cells through a dummy bit line;
a dummy word line bias circuit connected to the dummy cells through a plurality of dummy word lines;
a write driver and sense amplifier connected to the memory cells through bit lines;
a source line driver connected to the memory cells through a plurality of source lines; and
a leakage detector connected to the dummy cells through a dummy source line.

US Pat. No. 10,431,299

SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A semiconductor storage device comprising:a plurality of memory cells, each of the plurality of memory cells being capable of storing data of n bits (n is an integer equal to or larger than 3);
a word line which is connected to the plurality of memory cells; and
a control circuitry including a first latch circuitry, a second latch circuitry, a third latch circuitry, and a fourth latch circuitry, wherein the control circuitry is configured to;
in response to a first read request, perform a first read operation of reading first data out of the plurality of memory cells with a first voltage applied to the word line, and storing the first data in the second latch circuitry, and
in response to a second read request,
perform a second read operation of reading second data out of the plurality of memory cells with a second voltage within first voltage range and a third voltage within a second voltage range applied the word line, and storing the second data in the third latch circuitry, the first voltage range smaller than the first voltage, the second voltage range larger than the first voltage,
perform first logical operation of logically processing the first data stored in the second latch circuitry and the second data stored in the third latch circuitry,
store third data generated by the first logical operation in the first latch circuitry, and
output the third data stored in the first latch circuitry.

US Pat. No. 10,431,298

NONVOLATILE MEMORY AND WRITING METHOD

Toshiba Memory Corporatio...

1. A method for controlling a memory cell array including a plurality of memory cells, each of the plurality of memory cells being configured to store data by correlating three bits with eight threshold regions, the eight threshold regions corresponding to first to eighth threshold regions defined in ascending order of threshold voltage, each of the plurality of memory cells connected to a word line, the three bits respectively corresponding to first to third pages, a threshold voltage of an unwritten state of the memory cells being set at the first threshold region, the method comprising:when writing a first value to the first page of an unwritten memory cell, performing programming such that the threshold voltage of the unwritten memory cell is within the fifth threshold region;
when performing writing of the second page of the memory cell after the writing of the first page of the memory cell,
if a value corresponding to the first page of the memory cell is a second value and a value to be written to the second page is the first value, performing programming such that the threshold voltage of the memory cell is within the second threshold region, and
if a value corresponding to the first page of the memory cell is the first value and a value to be written to the second page is the first value, performing programming such that the threshold voltage of the memory cell is within the seventh threshold region;
when performing writing of the third page of the memory cell after the writing of the second page of the memory cell,
if a value corresponding to the first page of the memory cell is the second value, a value corresponding to the second page of the memory cell is the second value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the fourth threshold region,
if a value corresponding to the first page of the memory cell is the second value, a value corresponding to the second page of the memory cell is the first value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the third threshold region;
if a value corresponding to the first page of the memory cell is the first value, a value corresponding to the second page of the memory cell is the second value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the sixth threshold region,
if a value corresponding to the first page of the memory cell is the first value, a value corresponding to the second page of the memory cell is the first value, and a value to be written to the third page is the first value, performing programming such that the threshold voltage of the memory cell is within the eighth threshold region, and
when reading out data from the first page, reading out the data using a fourth read voltage, the fourth read voltage being a boundary voltage between the fourth threshold region and the fifth threshold region, and determining data of the first page on a basis of the read out data;
when reading out data from the second page, reading out the data using a first, a third and a sixth read voltage, the first read voltage being a boundary voltage between the first threshold region and the second threshold region, the third read voltage being a boundary voltage between the third threshold region and the fourth threshold region, the sixth read voltage being a boundary voltage between the sixth threshold region and the seventh threshold region, and determining data of the second page on a basis of the read our data; and
when reading out data from the third page, reading out the data using a second, a fifth and a seventh read voltage, the second read voltage being a boundary voltage between the second threshold region and the third threshold region, the fifth read voltage being a boundary voltage between the fifth threshold region and the sixth threshold region, the seventh read voltage being a boundary voltage between the seventh threshold region and the eighth threshold region, and determining data of the third page on a basis of the read out data.

US Pat. No. 10,431,297

SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells arranged in a matrix, each of the memory cells being capable of storing data of three bits including a first bit, a second bit, and a third bit; and
a control circuit which is configured to controls the memory cell array,
wherein the control circuit writes two-bit data of the first bit and the second bit to a first memory cell,
the control circuit subsequently writes two-bit data of the first bit and the second bit to a second memory cell adjacent to the first memory cell, and
the control circuit subsequently writes, to the first memory cell, three-bit data formed of the third bit and the two-bit data of the first bit and the second bit stored in the first memory cell.

US Pat. No. 10,431,296

SERIALIZED SRAM ACCESS TO REDUCE CONGESTION

Taiwan Semiconductor Manu...

1. A system, comprising:a plurality of memory arrays each comprising a plurality of columns having a plurality of bit-cells therein, wherein each of the plurality of memory arrays is configured to receive a serialized input signal and generate a serialized output signal;
a plurality of clock generators, wherein each of the plurality of clock generators is configured to generate an array-specific clock signal for a respective one of the plurality of memory arrays, and wherein the respective one of the plurality of memory arrays is configured to sequentially latch a respective bit of the serialized input signal or sequentially output a respective bit of the serialized output signal when the array-specific clock signal is active.

US Pat. No. 10,431,295

STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A static random access memory (SRAM) comprising:a memory cell, wherein the memory cell comprises at least two p-type pass gates;
a bit line connected to the memory cell;
a bit line bar connected to the memory cell;
a word line connected to the memory cell;
an n-type transistor connected between a ground voltage and a first node;
a first inverter having an input terminal configured to receive a data signal and an output terminal connected to the word line, the first inverter being connected between a supply voltage and the first node; and
a voltage control unit configured to control the N-type transistor and to control the memory cell by providing an operating voltage on the first node which affects operation of the first inverter and thereby causes a voltage on the word line to undergo at least a double transition including a first transition to the ground voltage and then a second transition to an intermediate voltage which is greater than the ground voltage but substantially lower than the supply voltage; and
wherein:
the voltage control unit includes a p-type capacitor-connected transistor connected to the first node and thereby to the word line; and
the voltage control unit is further configured to selectively adjust voltages correspondingly of the bit line and the bit line bar.

US Pat. No. 10,431,294

WRITE LEVEL ARBITER CIRCUITRY

Micron Technology, Inc., ...

1. A semiconductor device comprising:memory comprising a group of storage elements;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory;
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory; and
arbiter circuitry configured to detect which phase of the plurality of phases captures a write start signal for the write command, wherein the arbiter circuitry comprises a latch that is configured to:
receive a first indication of a pulse in a first phase of the plurality of phases; and
receive a second indication of a pulse in a second phase of the plurality of phases.

US Pat. No. 10,431,293

SYSTEMS AND METHODS FOR CONTROLLING DATA STROBE SIGNALS DURING READ OPERATIONS

Micron Technology, Inc., ...

1. An apparatus comprising:a first data strobe (DQS) output buffer (OB) and a second DQS OB each coupled to a DQS terminal, the first DQS OB and the second DQS OB configured to provide a DQS signal to the DQS terminal responsive to a read clock signal; and
control logic configured to receive the read clock signal to control the first DQS OB and the second DQS OB,
wherein the apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.

US Pat. No. 10,431,292

METHOD AND APPARATUS FOR CONTROLLING ACCESS TO A COMMON BUS BY MULTIPLE COMPONENTS

Micron Technology, Inc., ...

1. An apparatus comprising:a first memory die;
a first bus;
a common bus; and
an interface control logic stacked with the first memory die and coupled to the first memory die through the first bus and the common bus, the interface control logic including:
a plurality of delay circuits configured to output a plurality of strobe signals having different amounts of delay from one another; and
a multiplexer configured to select a first one of the plurality of strobe signals, responsive to a first command, based on a type of the first command and a first latency of the first memory die, transferred through the common bus and output the first one of the plurality of strobe signals to the first bus;
wherein the first memory die is configured to capture the first command responsive to the first one of the plurality of strobe signals.

US Pat. No. 10,431,291

SYSTEMS AND METHODS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL VOLTAGE BOOSTING

Micron Technology, Inc., ...

1. A memory device, comprising:a memory array having at least one memory cell;
a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof;
a first bus configured to provide a first electric power to the sense amplifier circuit; and
a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell, wherein the first bus is electrically coupled to a first power supply, wherein the second bus is electrically coupled to a second power supply, and wherein the second power supply is configured to deliver a voltage higher than the first power supply.

US Pat. No. 10,431,290

PROTOCOL FOR MEMORY POWER-MODE CONTROL

Rambus Inc., Sunnyvale, ...

1. A dynamic random access memory (DRAM) device comprising:a memory core having a plurality of memory cells;
a command/address (CA) interface to receive command and address information;
a data interface to output data in response to a command received via the CA interface;
an interface to receive a power mode signal; and
a plurality of mode registers to store parameter values including a first parameter value that sets a power down mode for the CA interface and the data interface, such that a combination of the first parameter value and a level of the power mode signal determine which of the data interface and the CA interface are powered down in response to a transition in the level of the power mode signal, the parameter values further associated with a plurality of operating clock frequencies of a clock signal.

US Pat. No. 10,431,289

MEMORY DEVICES WITH SELECTIVE PAGE-BASED REFRESH

Micron Technology, Inc., ...

1. A memory device comprising:a main memory including a memory region having a plurality of memory pages; and
a controller operably coupled to the main memory, wherein the controller is configured to:
track a first subset of the plurality of memory pages having a first refresh schedule and a second subset of the plurality of memory pages having a second refresh schedule that is different than the first refresh schedule, wherein at least one of the first and second refresh schedules is a function of an elapsed time since the last refresh operation,
refresh the first subset of memory pages according to the first refresh schedule, and
refresh the second subset of memory pages according to the second refresh schedule.

US Pat. No. 10,431,288

SYSTEMS AND METHODS FOR MAINTAINING REFRESH OPERATIONS OF MEMORY BANKS USING A SHARED ADDRESS PATH

Micron Technology, Inc., ...

1. A method comprising:receiving an instruction to refresh a row address stored in a counter of a memory device;
blocking incrementing the row address when the memory device transitioned from a first mode of operation to a second mode of operation and an immediately previous refresh operation was unpaired;
incrementing the row address stored in the counter when the memory device did not transition from the first mode of operation to the second mode of operation, or the memory device transitioned from the first mode of operation to the second mode of operation and the immediately previous refresh operation was paired; and
refreshing the row address stored in the counter.

US Pat. No. 10,431,287

SEMICONDUCTOR MEMORY DEVICE INCLUDING A MEMORY CELL WITH FIRST AND SECOND TRANSISTORS

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a memory cell including a first transistor comprising a first oxide semiconductor, a first insulation film, and a first control electrode, a second transistor comprising a second oxide semiconductor, a second insulation film, a second control electrode which is independent from the first control electrode, and a capacitance element configured to store a charge based on a product between input data and a coupling weight of a neuron model; wherein the first transistor is connected to the second transistor in series and the capacitor is connected to a common node of the first and second transistors; and
a control circuit configured to turn on the first transistor when the charge is written to the capacitance element, and to turn on the second transistor when the charge is read from the capacitance element.

US Pat. No. 10,431,286

REFRESH IN NON-VOLATILE MEMORY

Micron Technology, Inc., ...

9. An apparatus, comprising:an array of memory cells; and
a processor configured to:
determine a threshold miss rate based on a number of memory cells that fail to refresh;
determine a refresh rate of the array of memory cells based on the threshold miss rate; and
refresh a memory cell of the array of memory cells in response to the array of memory cells being accessed a threshold number of accesses, wherein the threshold is based on the refresh rate.

US Pat. No. 10,431,284

DYNAMIC REFERENCE VOLTAGE DETERMINATION

Micron Technology, Inc., ...

14. An electronic memory apparatus, comprising:a first memory cell comprising a first digit line;
a second memory cell comprising a second digit line; and
a controller coupled with the first memory cell and the second memory cell, wherein the controller is operable to:
activate a first switching component coupled with the first and second digit lines; and
determine a reference voltage based at least in part on a voltage of a conductive path, wherein the conductive path is established between the first and second digit lines when the first switching component is activated.

US Pat. No. 10,431,283

APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR ACCESSING FERROELECTRIC MEMORY

Micron Technology, Inc., ...

1. A method, comprising:increasing a voltage of a first cell plate of a capacitor to change a voltage of a second cell plate of the capacitor, a second digit line, and a second sense node;
decreasing the voltage of the second cell plate and the second digit line to change the voltage of the first cell plate, a first digit line, and a first sense node, wherein decreasing the voltage of the second cell plate and the second digit line includes decreasing the voltage of the second cell plate from an increased voltage to an initial voltage of the second cell plate;
driving the first sense node to a first voltage and driving the second sense node to a second voltage responsive to the voltage of the first sense node being greater than the voltage of the second sense node; and
driving the first sense node to the second voltage and driving the second sense node to the first voltage responsive to the voltage of the first sense node being less than the voltage of the second sense node.

US Pat. No. 10,431,282

ARRAY DATA BIT INVERSION

Micron Technology, Inc., ...

1. A method, comprising:sensing, by a sense component through a first set of transistors, a first logic value stored at a memory cell; and
applying an output of the sense component to the memory cell through a second set of transistors different than the first set of transistors, the output of the sense component corresponding to the first logic value, wherein a second logic value different than the first logic value is stored at the memory cell based at least in part on the applying.

US Pat. No. 10,431,281

ACCESS SCHEMES FOR SECTION-BASED DATA PROTECTION IN A MEMORY DEVICE

Micron Technology, Inc., ...

1. A method, comprising:initializing a timer associated with sections of a memory device, each of the sections comprising memory cells associated with one of a plurality of word lines of the section that is configured to selectively couple the memory cells with one of a plurality of digit lines of the section;
selecting one of the sections for a voltage adjustment operation based at least in part on a determined value of the timer; and
performing the voltage adjustment operation on the selected section by activating each of the plurality of word lines of the selected section.

US Pat. No. 10,431,280

FERROELECTRIC OPENING SWITCH

1. A ferroelectric opening switch, comprising:a ferroelectric material comprising at least one crystal having a permanent electric dipole determined by the crystallographic symmetry of the ferroelectric material and a having plurality of nucleation sites; and
a voltage source for applying an electric field to the ferroelectric material;
wherein polarization reversal of the electric dipoles is nucleated at the nucleation sites when the electric field is applied, thereby changing current flow in the switch.

US Pat. No. 10,431,276

SEMICONDUCTOR DEVICES INCLUDING REVERSIBLE AND ONE-TIME PROGRAMMABLE MAGNETIC TUNNEL JUNCTIONS

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a plurality of word lines;
a plurality of bit lines crossing the plurality of word lines, the plurality of bit lines including first bit lines and second bit lines, the second bit lines spaced apart from the first bit lines in a direction of extension of the plurality of word lines;
a plurality of first memory cells connected between the plurality of word lines and the first bit lines, each of the plurality of first memory cells including a first memory element and a first selection element, the first memory element and the first selection element connected to each other; and
a plurality of second memory cells connected between the plurality of word lines and the second bit lines, each of the plurality of second memory cells including a second memory element and a second selection element, the second memory element and the second selection element connected to each other,
wherein the first memory element includes a first magnetic tunnel junction, and the second memory element includes a second magnetic tunnel junction, each of the first and second magnetic tunnel junctions including a pinned layer, a free layer, and a tunnel barrier layer between the pinned layer and the free layer,
wherein the tunnel barrier layers of a first portion of the second magnetic tunnel junctions have an irreversible resistance state,
wherein the first magnetic tunnel junction has a rewritable structure, and is configured to have one of (i) a first resistance corresponding to first data, and (ii) a second resistance corresponding to second data;
wherein at least one second magnetic tunnel junction among the first portion of the second magnetic tunnel junctions has a third resistance corresponding to the first data, the at least one second magnetic tunnel junction having been programmed through a first one-time programming operation,
wherein at least one other second magnetic tunnel junction from among the first portion of the second magnetic tunnel junctions has a fourth resistance corresponding to the second data, the at least one other second magnetic tunnel junction having been programmed through a second one-time programming operation,
wherein the first to fourth resistances are different from each other,
wherein one or more of the plurality of first memory cells are configured as one or more first reference cells for a reading operation on the plurality of first memory cells, and one or more of the plurality of second memory cells are configured as one or more second reference cells for a reading operation on the plurality of second memory cells, and
wherein the one or more of the plurality of first memory cells includes one or more pairs of first memory cells, and a pair of first memory cells among the one or more pairs of first memory cells are connected in parallel to one of the first bit lines.

US Pat. No. 10,431,275

METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS HAVING HYBRID OXIDE AND NOBLE METAL CAPPING LAYERS

Samsung Electronics Co., ...

1. A magnetic apparatus residing on a substrate and usable in a magnetic device, the magnetic apparatus comprising:a magnetic junction; and
a hybrid capping layer adjacent to the magnetic junction, the hybrid capping layer including an insulating layer, a discontinuous oxide layer, and a noble metal layer, the discontinuous oxide layer being between the insulating layer and the noble metal layer, the insulating layer being between the magnetic junction and the noble metal layer.

US Pat. No. 10,431,274

SEMICONDUCTOR MEMORY DEVICE

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:a plurality of banks, each having a dedicated line and sharing a global line;
a plurality of sub-global lines shared by neighboring banks among the plurality of banks;
a plurality of data input/output circuits coupled to the plurality of banks, respectively, through the dedicated line and coupling the dedicated lines of corresponding banks to the sub-global lines in response to bank strobe signals, respectively; and
a plurality of data intervention blocks corresponding to the plurality of sub-global lines, respectively, and coupling the global line to corresponding sub-global lines in response to a delayed write strobe signal or read strobe signals.

US Pat. No. 10,431,273

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a row decoder provided on a semiconductor substrate; and
a memory cell array provided above the row decoder and including a first block,
wherein the first block includes:
a first region spreading along a first plane formed by a first direction that is an in-plane direction of the semiconductor substrate and a second direction that is the in-plane direction and is different from the first direction and having a first width along the second direction;
a second region spreading along the first plane, having a second width larger than the first width along the second direction, and being adjacent to the first region in the first direction; and
a third region spreading along the first plane, having a third width smaller than the first width along the second direction, and located between the first region and the second region to connect the first region and the second region,
wherein the first region, the second region, and the third region include a plurality of first word lines stacked along a third direction that is a vertical direction of the semiconductor substrate, and the first region further includes a first selection gate line provided above a first word line of an uppermost layer, and
the memory cell array further includes:
a first insulating layer buried in a first trench between the first region and the second region and being in contact with the third region in the second direction;
a first contact plug provided in the first insulating layer and electrically connected to the row decoder; and
a first interconnect configured to connect the first selection gate line and the first contact plug.

US Pat. No. 10,431,272

VOLTAGE CONTROL CIRCUIT INCLUDING ASSIST CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a volatile memory cell array connected to a plurality of word lines and comprising a memory cell that comprises at least one transistor;
a word line driver connected to the plurality of word lines, wherein a first node is connected to the word line driver and receives a voltage derived from a main power supply voltage; and
an assist circuit comprising an N-channel metal oxide semiconductor (NMOS) transistor having a diode connection structure, the NMOS transistor having a drain to source path connected between the first node and a point of reference potential, the assist circuit adjusting a word line voltage of a word line among the plurality of word lines by performing voltage pull-down for the first node.

US Pat. No. 10,431,271

APPARATUSES AND METHODS FOR PROVIDING AN INDICATOR OF OPERATIONAL READINESS OF VARIOUS CIRCUITS OF A SEMICONDUCTOR DEVICE FOLLOWING POWER UP

Micron Technology, Inc., ...

17. An apparatus, comprising:a supply voltage detection circuit configured to receive a supply voltage and further configured to provide a power up signal responsive to the supply voltage; and
a power supply ready circuit coupled to the first circuit, the second circuit configured to provide a ready detect signal that is active to a control circuit that enables a third circuit when the first signal is active.

US Pat. No. 10,431,270

APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS

Micron Technology, Inc., ...

1. An apparatus comprising:first and second memory access lines;
a memory cell coupled to the first and second memory access lines and configured to have a threshold voltage; and
memory access circuits coupled to the first and second memory access lines and configured to apply a pre-bias voltage across the memory cell by the first and second memory access lines,
wherein the pre-bias voltage is initially held constant and then increased and held constant until a ratio of the increased pre-bias voltage to the threshold voltage is above a threshold value.

US Pat. No. 10,431,269

METHODS AND APPARATUS FOR REDUCING POWER CONSUMPTION IN MEMORY CIRCUITRY BY CONTROLLING PRECHARGE DURATION

Altera Corporation, San ...

1. A method of operating an integrated circuit, comprising:during a decode time period, using a decoder circuit to address a memory cell;
using a precharge circuit to precharge a bit line that is coupled to the memory cell;
keeping the precharge circuit turned off during the decode time period; and
after the bit line is precharged, asserting a word line signal to access the memory cell.

US Pat. No. 10,431,268

SEMICONDUCTOR DEVICE AND MEMORY CONTROLLER RECEIVING DIFFERENTIAL SIGNAL

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a differential signal phase detector configured to receive a differential signal comprising a first signal and a second signal, detect a phase between the first and second signals, and generate a mode control signal according to the phase detected; and
a receiver configured to receive the differential signal and, based on the mode control signal, perform a processing operation using the differential signal in a differential mode, or, perform a processing operation using the first signal and a reference voltage in a single mode.

US Pat. No. 10,431,266

SEMICONDUCTOR STORAGE DEVICE

Toshiba Memory Corporatio...

1. A semiconductor storage device, comprising:a first terminal configured to output a signal to an external device;
a plurality of first output buffers and a plurality of second output buffers connected to the first terminal;
a register configured to retain a first signal corresponding to the plurality of second output buffers and a second signal corresponding to the plurality of first output buffers;
a plurality of first pre-drivers, each first pre-driver connected to one of the plurality of first output buffers, each first pre-driver including a plurality of first transistors connected in parallel between a first inverter and a ground voltage supply terminal, wherein the plurality of first transistors are configured to operate in accordance with values of the first signal;
a plurality of second pre-drivers, each second pre-driver connected to one of the plurality of second output buffers, each second pre-driver including a plurality of second transistors connected in parallel between a second inverter and a power voltage supply terminal, wherein the plurality of second transistors are configured to operate in accordance with values of the second signal;
a first output control circuit connected to the plurality of first pre-drivers through a plurality of first signal lines, the first output control circuit configured to select at least one of the plurality of first signal lines in accordance with values of a third signal corresponding to a conversion of the second signal;
a second output control circuit connected to the plurality of second pre-drivers through a plurality of second signal lines, the second output control circuit configured to select at least one of the plurality of second signal lines in accordance with values of a fourth signal corresponding to a conversion of the first signal; and
a third output control circuit configured to transmit an output signal to the first and second output control circuits.

US Pat. No. 10,431,265

ADDRESS FAULT DETECTION IN A FLASH MEMORY SYSTEM

SILICON STORAGE TECHNOLOG...

1. A flash memory system, comprising:a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
an address fault detection array comprising memory cells arranged in rows and columns, wherein each of the plurality of word lines is coupled to a row in the address fault detection array; and
a comparator for comparing a row address received by the row decoder with a value output from the address fault detection array in response to an assertion of a word line by the row decoder and for indicating a fault if the compared values are different and for indicating a fault in response to the assertion of multiple word lines by the row decoder;
wherein the address fault detection array comprises a column of cells, wherein a first value in a cell indicates that bits in a row containing that cell were stored in an inverted manner and a second value in the cell indicates that bits in the row containing that cell were stored in a non-inverted manner.

US Pat. No. 10,431,264

APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

Micron Technology, Inc., ...

1. A system, comprising:a host configured to generate instructions; and
a memory device comprising an array of memory cells coupled to sensing circuitry comprising a sense amplifier and a compute component, wherein the memory device is configured to:
receive an instruction from the host; and
execute the instruction to perform at least one of a NAND operation and an AND operation using data values stored in the array as inputs by controlling the sensing circuitry without transferring data externally from the array and the sensing circuitry.

US Pat. No. 10,431,261

FLEXIBLE-MOUNT ELECTRICAL CONNECTION

Western Digital Technolog...

1. A flexible-mount electrical connection comprising:a mating connector configured to physically couple with a hard drive connector; and
a plurality of electrical pins that suspend the mating connector over a void in a printed circuit board (PCB), each electrical pin having:
a connector portion positioned within the mating connector configured to electrically couple with hard drive connector pins positioned within the hard drive connector; and
an extended portion extending externally away from the mating connector, the extended portion having:
an attachment portion configured to electrically couple the electrical pin to the PCB; and
a curved shape formed therein configured to reduce transmission of vibrations in the connector portion along each axis of a three-dimensional space to the attachment portion.

US Pat. No. 10,431,260

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND INFORMATION PROCESSING METHOD

Ricoh Company, Ltd., Tok...

1. An information processing apparatus comprising circuitry configured to:acquire time data relating to a state of an object in each process of an operation performed on the object, the operation including at least one process;
calculate an achievement value indicating a state of each process, based on the time data acquired;
compare the achievement value of each process with a reference value; and
generate a chart that visually represents a result of comparison for each process, the visual representation of the result of comparison being different according to the result of comparison.

US Pat. No. 10,431,257

DATA CENTER DUAL STAGE DRIVE WITH DATA STRIPING

KABUSHIKI KAISHA TOSHIBA,...

1. A disk drive comprising:a first magnetic head and a second magnetic head;
a voice-coil motor configured for coarse positioning of the first magnetic head and the second magnetic head;
a first microactuator coupled to the voice-coil motor and the first magnetic head;
a second microactuator coupled to the voice-coil motor and the second magnetic head; and
a controller configured to:
receive from a host device a write command that includes a set of data that has a first data block and a second data block;
select a first storage block disposed on a first disk surface for storing the first data block and a second storage block disposed on a second disk surface for storing the second data block;
position the first magnetic head over the first storage block with the voice-coil motor, the first microactuator, and a first servo controller and writing the first data block to the first storage block; and
position the second magnetic head over the second storage block with the voice-coil motor, the second microactuator, and a second servo controller and writing the second data block to the second storage block.

US Pat. No. 10,431,256

METHOD OF PERFORMING READ/WRITE PROCESS ON RECORDING MEDIUM, PARAMETER ADJUSTMENT METHOD, STORAGE DEVICE, COMPUTER SYSTEM, AND STORAGE MEDIUM EMPLOYING THE METHODS

Seagate Technology LLC, ...

11. A storage device comprising:a recording medium comprising a plurality of tracks, each of the plurality of tracks comprising a plurality of data sectors;
a media interface which writes information to, or reads information from, the recording medium by accessing the recording medium;
a processor which controls the media interface to write data to, or read data from, the plurality of data sectors of a target track of the recording medium; and
a memory containing code objects configured to cause the processor to
write test data to the plurality of data sectors of the target track,
read the test data from the plurality of data sectors of the target track,
count a total number of error-corrected error correcting code (“ECC”) symbols in the read of each of the plurality of data sectors,
determine whether the total number of error-corrected ECC symbols of a data sector exceeds a first threshold value,
upon determining that the total number of error-corrected ECC symbols exceeds the first threshold value, determining the data sector to be a defective sector,
analyze a distribution of defective data sectors on the target track to determine whether an area of the track containing the defective data sectors is greater than a second threshold,
upon determining that the area of the target track is greater than the second threshold, determine whether corresponding defective areas occur in one or more consecutive adjacent tracks of the target track, and
upon determining that corresponding defective areas occur in one or more consecutive adjacent tracks of the target track, determine the area of the target track and the corresponding areas of the one or more consecutive adjacent tracks including the defective data sectors to be a massive defective area.

US Pat. No. 10,431,254

SYSTEM FOR PROVIDING AN ACCLIMATION ENCLOSURE FOR A DATA STORAGE LIBRARY

International Business Ma...

1. An enclosure configured to surround at least one library access opening that permits access to an interior of a data storage library, the enclosure comprising:a plurality of side wall panels configured to surround the data storage library and the at least one library access opening, wherein at least one of the plurality of side wall panels is configured to permit access to the at least one library access opening of the data storage library;
at least one top panel coupled to the plurality of side wall panels and disposed over a top surface of the data storage library so as to enclose the data storage library to form a chamber around the data storage library;
a plurality of top side panels coupled to the plurality of side wall panels and the at least one top panel, wherein each of the top side panels is configured to extend only to at least one environmental conditioning unit enclosure coupled to the top surface of the data storage library such that waste heat generated by at least one environmental conditioning unit within the at least one environmental conditioning unit enclosure is not captured within the enclosure;
at least one enclosure access opening in the at least one of the plurality of side wall panels to permit access to an interior of the chamber; and
at least one vent formed in at least one of the plurality of side wall panels, wherein the at least one vent is separate from the at least one enclosure access opening, and further wherein the at least one vent is configured to selectively allow ambient external air from outside the enclosure to intrude into the chamber,
wherein the enclosure is configured to selectively permit environmental conditions within the chamber to acclimate between environmental conditions outside the enclosure and environmental conditions within the data storage library.

US Pat. No. 10,431,253

WAVEGUIDE INPUT COUPLER WITH ASYMMETRIC TAPER

Seagate Technology, LLC, ...

1. An apparatus comprising:an input waveguide disposed on a substrate-parallel plane and configured to receive light from an input surface of the apparatus;
a mode converter joining the input waveguide at a junction away from the input surface, the mode converter converting the light from a fundamental mode to a higher-order mode; and
an input coupler proximate to and overlapping the mode converter parallel to the substrate-parallel plane and offset therefrom in a downtrack direction, the input coupler extending from the input surface to an output end of the mode converter and comprising first and second edges forming an asymmetric taper that transitions from a wider crosstrack dimension near the input surface to a narrower crosstrack dimension away from the input surface, the mode converter located between the first and second edges.

US Pat. No. 10,431,252

SUBSTRATE FOR MAGNETIC DISK AND MAGNETIC DISK

HOYA CORPORATION, Tokyo ...

1. An annular substrate to be polished for manufacturing a magnetic-disk substrate having a circular hole at a center, and comprising a pair of main surfaces and a side wall surface orthogonal to the main surfaces,a roundness of the circular hole being 1.5 ?m or less,
in the side wall surface of the circular hole, three outlines in a circumferential direction of the side wall surface, which include an outline at a center position of a thickness of the substrate and outlines at two positions that are spaced apart from the center position in opposite directions along a substrate thickness direction by a predetermined distance, being obtained,
a difference between a maximum value and a minimum value of radii of three inscribed circles that are respectively derived from the three outlines being 3.5 ?m or less, and
when positions spaced apart from the center position in the opposite directions along the substrate thickness direction by 200 ?m exist on the side wall surface, the predetermined distance being 200 ?m, and when positions spaced apart from the center position in the opposite directions of the substrate thickness direction by 200 ?m do not exist on the side wall surface, the predetermined distance being 100 ?m,
a substrate thickness of the annular substrate being 0.8 mm or less.

US Pat. No. 10,431,251

MAGNETIC TAPE DEVICE AND MAGNETIC REPRODUCING METHOD

FUJIFILM Corporation, To...

1. A magnetic tape device comprising:a magnetic tape; and
a reproducing head,
wherein the reproducing head is a magnetic head including a tunnel magnetoresistance effect type element as a reproducing element,
the magnetic tape includes a non-magnetic support, and a magnetic layer including ferromagnetic powder, a binding agent, and fatty acid ester on the non-magnetic support,
a center line average surface roughness Ra measured regarding a surface of the magnetic layer is equal to or smaller than 2.0 nm,
a full width at half maximum of spacing distribution measured by optical interferometry regarding the surface of the magnetic layer before performing a vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 7.0 nm,
a full width at half maximum of spacing distribution measured by optical interferometry regarding the surface of the magnetic layer after performing the vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 7.0 nm,
a difference Safter?Sbefore between a spacing Safter measured by optical interferometry regarding the surface of the magnetic layer after performing the vacuum heating with respect to the magnetic tape and a spacing Sbefore measured by optical interferometry regarding the surface of the magnetic layer before performing the vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 8.0 nm, and
?SFD in a longitudinal direction of the magnetic tape calculated by Expression 1 is equal to or smaller than 0.50,
?SFD=SFD25° C.?SFD?190° C.  Expression 1
in Expression 1, the SFD25° C. is a switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of 25° C., and the SFD?190° C. is a switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of ?190° C.

US Pat. No. 10,431,250

MAGNETIC TAPE HAVING CHARACTERIZED MAGNETIC LAYER

FUJIFILM Corporation, To...

1. A magnetic tape comprising:a non-magnetic support; and
a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic support,
wherein the center line average surface roughness Ra measured regarding the surface of the magnetic layer is equal to or smaller than 1.8 nm,
the logarithmic decrement acquired by a pendulum viscoelasticity test performed regarding the surface of the magnetic layer is 0.010 to 0.050,
?SFD in a longitudinal direction of the magnetic tape calculated by Expression 1 is equal to or greater than 0.35,
?SFD=SFD25° C.?SFD?190° C.  Expression 1
in Expression 1, the SFD25° C. is the switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of 25° C., and the SFD?190° C. is the switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of ?190° C., and
the logarithmic decrement on the magnetic layer side is determined by the following method:
securing a measurement sample of the magnetic tape with the measurement surface, which is the surface on the magnetic layer side, facing upward on a substrate in a pendulum viscoelasticity tester;
disposing a columnar cylinder edge which is 4 mm in diameter and equipped with a pendulum 13 g in weight on the measurement surface of the measurement sample such that the long axis direction of the columnar cylinder edge runs parallel to the longitudinal direction of the measurement sample;
raising the surface temperature of the substrate on which the measurement sample has been positioned at a rate of less than or equal to 5° C./min up to 80° C.;
inducing initial oscillation of the pendulum;
monitoring the displacement of the pendulum while it is oscillating to obtain a displacement-time curve for a measurement interval of greater than or equal to 10 minutes; and
obtaining the logarithmic decrement ? from the following equation:

wherein the interval from one minimum displacement to the next minimum displacement is adopted as one wave period; the number of waves contained in the displacement-time curve during one measurement interval is denoted by n, the difference between the minimum displacement and the maximum displacement of the nth wave is denoted by An, and the logarithmic decrement is calculated using the difference between the next minimum displacement and maximum displacement of the nth wave (An+1 in the above equation).

US Pat. No. 10,431,247

MAGNETIC HEAD CONTROL CAPABLE OF AVOIDANCE MEDIA BUMPS DURING SEEKING PROCESS

Kabushiki Kaisha Toshiba,...

1. A magnetic disk drive comprising:a selector selecting a plurality of evaluation commands in order in a command reordering operation;
a determiner determining whether media bumps which influence a dynamic flying height (DFH) control exist in a seek section between completion of a previous command and start of a selected evaluation command or not; and
a calculator calculating a delay time necessary for avoidance of the media bumps if it is determined by the determiner that the media bumps which influence the dynamic flying height (DFH) control exist; wherein
the reordering operation compares a latency time which is obtained by summing a seek time which is determined in accordance with a seek distance, a rotational latency time which is determined after a seek completion and the delay time of each of a plurality of evaluation commands, and selects the evaluation command of the shortest latency time as the command to be next processed.

US Pat. No. 10,431,245

PIEZOELECTRIC ELEMENT HAVING POLYMER COATING, PIEZOELECTRIC ACTUATOR USING SAID PIEZOELECTRIC ELEMENT, AND HEAD SUSPENSION USING SAID PIEZOELECTRIC ACTUATOR

NHK Spring Co., Ltd., Ka...

1. A piezoelectric element, comprising:an element body configured to deform, so as to elongate and contract along a deformation direction, in response to a voltage applied thereto;
electrodes formed on opposite sides of the element body;
peripheral end faces defining a peripheral shape of the element body; and
polymer coatings formed by vapor deposition polymerization to have first portions and second portions, the first portions coating at least respective opposite end faces of the peripheral end faces of the element body in an orthogonal direction relative to the deformation direction, and the second portions continuously extending from the first portions and located on respective side portions of one of the electrodes in said orthogonal direction to coat the side portions of said one of the electrodes so that said one of the electrodes has an exposed portion exposing outside at a middle portion defined in said orthogonal direction between the side portions that are covered with the second portions of polymer coatings.

US Pat. No. 10,431,244

DEVICES INCLUDING A NEAR FIELD TRANSDUCER (NFT) INCLUDING PEG AND DISC FROM DIFFERENT MATERIALS

Seagate Technology LLC, ...

1. A device having an air bearing surface (ABS), the device comprising:a near field transducer (NFT) comprising:
a disc configured to convert photons incident thereon into plasmons; and
a peg configured to couple plasmons coupled from the disc into an adjacent magnetic storage medium,
wherein the peg extends beyond the disc, and the peg comprises rhodium (Rh), aluminum (Al), iridium (Ir), silver (Ag), copper (Cu), palladium (Pd), platinum (Pt), alloys thereof, or combinations thereof and
wherein the disc comprises a disc material comprising gold or a gold alloy and the peg comprises a peg material, wherein the disc material is different from the peg material.

US Pat. No. 10,431,243

SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, SIGNAL PROCESSING PROGRAM

NEC CORPORATION, Tokyo (...

4. A signal processing method implemented using a signal processing apparatus, the method comprising:transforming, by the signal processing apparatus, input signal samples into frames of amplitude components representing different frequencies in a frequency domain;
smoothing, by the signal processing apparatus, the amplitude components along time to obtain time-smoothed amplitude components,
smoothing, by the signal processing apparatus, the time-smoothed amplitude components along frequency to obtain frequency-smoothed amplitude components;
calculating, by the signal processing apparatus, differences of the frequency-smoothed amplitude components along the frequency;
accumulating, by the signal processing apparatus, the differences to obtain an accumulated value; and
analyzing, by the signal processing apparatus, the input signal samples to detect a male voice in accordance with the accumulated value.

US Pat. No. 10,431,242

SYSTEMS AND METHODS FOR IDENTIFYING SPEECH BASED ON SPECTRAL FEATURES

GoPro, Inc., San Mateo, ...

1. A system that identifies speech, the system comprising:one or more physical processors configured by machine-readable instructions to:
access audio information defining audio content, the audio content having a duration;
segment the audio content into audio segments, individual audio segments corresponding to a portion of the duration, the audio segments including a first audio segment corresponding to a first portion of the duration;
determine energy features of the audio segments, the energy features characterizing energy of the audio segments, the energy features including a first energy feature of the first audio segment;
determine entropy features of the audio segments, the entropy features characterizing spectral flatness of the audio segments, the entropy features including a first entropy feature of the first audio segment;
determine frequency features of the audio segments, the frequency features characterizing highest frequencies of the audio segments, the frequency features including a first frequency feature of the first audio segment;
identify one or more of the audio segments as containing speech based on the energy features, the entropy features, and the frequency features by generating a binary curve indicating the one or more of the audio segments as containing speech, wherein the first audio segment is identified as containing speech based on the first energy feature, the first entropy feature, and the first frequency feature, wherein the binary curve is smoothed based on a number of silent audio segments; and
effectuate storage of the identification of the one or more of the audio segments as containing speech in a storage medium.

US Pat. No. 10,431,241

SPEECH ENHANCEMENT METHOD AND APPARATUS FOR SAME

SAMSUNG ELECTRONICS CO., ...

1. An electronic device comprising:a plurality of microphones disposed on an upper part of the electronic device;
a processor configured to:
operate in a first mode, in which an estimation of a direction of a user and a beamforming operation based on the estimated direction are deactivated, to:
receive at least one signal from any one or any combination of the plurality of microphones; and
determine whether the received at least one signal is associated with a speech of the user to activate the deactivated estimation of the direction and the deactivated beamforming operation;
based on the at least one signal being determined to be associated with the speech of the user, operate in a second mode, in which the estimation of the direction and the beamforming operation are activated, to:
estimate the direction of the user, based on a difference between at least two of a plurality of signals that is received from at least two of the plurality of microphones; and
based at least on the estimated direction, beamform the received plurality of signals such that at least one of the plurality of signals from the estimated direction is emphasized and at least another one of the plurality of signals is suppressed; and
output the plurality of beamformed signals to perform speech recognition based on the plurality of beamformed signals.

US Pat. No. 10,431,240

SPEECH ENHANCEMENT METHOD AND SYSTEM

Samsung Electronics Co., ...

1. A speech enhancement method comprising:receiving at least one speech signal;
generating a first speech signal by performing a primary speech enhancement on the at least one speech signal;
selecting a noise removing gain corresponding to the first speech signal from pre-learned noise removing gain information; and
generating a second speech signal by performing a secondary speech enhancement on the first speech signal based on the selected noise removing gain,
wherein the selecting of the noise removing gain comprises:
obtaining an a priori signal-to-noise ratio (SNR) and an a posteriori SNR regarding the first speech signal; and
selecting the noise removing gain corresponding to the a priori SNR and the a posteriori SNR, from among a plurality of noise removing gains included in the pre-learned noise removing gain information.

US Pat. No. 10,431,239

HEARING SYSTEM

1. A binaural hearing aid system comprising a first hearing aid device configured to be worn at, behind and/or in an ear of a user, and a second hearing aid device configured to be worn at, behind and/or in an ear of a user, wherein the first hearing aid device comprises:a direction sensitive input sound transducer unit configured to convert acoustical sound signals into electrical noisy sound signals,
a wireless sound receiver unit configured to receive wireless sound signals from a remote device, the wireless sound signals representing noiseless electrical sound signals,
and
a memory storing sets of head related impulse responses for different positions relative to the direction sensitive input transducer unit,
wherein a processing unit is configured to estimate the direction to an active source, and the processing unit configured to map the electrical noisy sound signals and the wireless sound signals into binaural electrical output signals by convolving the noiseless electrical sound signals with the set of the head related impulse responses stored in the memory in correspondence with the estimated sound source location.

US Pat. No. 10,431,237

DEVICE AND METHOD FOR ADJUSTING SPEECH INTELLIGIBILITY AT AN AUDIO DEVICE

MOTOROLA SOLUTIONS, INC.,...

1. A device comprising:a microphone;
a transmitter; and
a controller having access to a memory storing a plurality of preconfigured voice tags associated with respective noise levels, each of the plurality of preconfigured voice tags comprising a respective voice recording of a given user,
the controller configured to:
determine a noise level at the microphone;
select a voice tag, of the plurality of preconfigured voice tags, based on the noise-level;
determine an intelligibility rating of a mix of the voice tag and noise received at the microphone; and
when the intelligibility rating is below a threshold intelligibility rating, enhance speech from the given user received at the microphone based on the intelligibility rating prior to transmitting, at the transmitter, a signal representing intelligibility enhanced speech.

US Pat. No. 10,431,236

DYNAMIC PITCH ADJUSTMENT OF INBOUND AUDIO TO IMPROVE SPEECH RECOGNITION

Sphero, Inc., Boulder, C...

1. A system for dynamically adjusting the pitch of inbound audio, comprising:at least one processor; and
memory encoding computer executable instructions that, when executed by the at least one processor, perform a method comprising:
receiving an input audio segment;
detecting one or more clusters of speech input within the input audio segment;
detecting an average pitch for at least one of the one or more clusters of speech input;
determining, based on at least the average pitch and an expected content for the input audio segment, whether the pitch of the input audio segment should be adjusted;
based on determining that the pitch should be adjusted, adjusting the pitch of at least one of the one or more speech clusters to generate an adjusted audio segment; and
transmitting the adjusted audio segment to a speech recognition component.

US Pat. No. 10,431,235

METHODS AND SYSTEMS FOR SPEECH ADAPTATION DATA

Elwha LLC, Bellevue, WA ...

1. A method for controlling a computer processor to perform operations comprising:detecting speech data of a particular party at a personal device of the particular party, the speech data being related to a speech-facilitated interaction of the particular party with a target device;
acquiring at the personal device adaptation data that is at least partly based on at least one previous speech interaction of the particular party;
converting the speech data at the personal device into converted data based at least partly on feedback from the target device at least indicating that the target device is able to process the converted data more quickly than the speech data; and
transmitting the adaptation data and the converted data from the personal device to the target device to facilitate speech recognition.

US Pat. No. 10,431,234

DEVICE AND METHOD FOR TRANSMITTING AND RECEIVING VOICE DATA IN WIRELESS COMMUNICATION SYSTEM

SAMSUNG ELECTRONICS CO., ...

1. An operating method of a transmission terminal for transmitting an audio signal, the method comprising:generating bandwidth information indicating a first bandwidth range, and bit rate information indicating a first bit rate range;
transmitting the bandwidth information indicating a first bandwidth range and the bit rate information indicating a first bit rate range to a reception terminal;
receiving combination determination information from the reception terminal;
compressing the audio signal according to the received combination determination information; and
transmitting the compressed audio signal to the reception terminal,
wherein the combination determination information is determined based on bandwidth information indicating a second bandwidth range, and bit rate information indicating a second bit rate range, by the reception terminal, and
wherein the second bandwidth range is comprised in the first bandwidth range, and the second bit rate range is comprised in the first bit rate range.

US Pat. No. 10,431,232

APPARATUS AND METHOD FOR SYNTHESIZING AN AUDIO SIGNAL, DECODER, ENCODER, SYSTEM AND COMPUTER PROGRAM

Fraunhofer-Gesellschaft z...

1. An apparatus for synthesizing an audio signal, comprising:a processing unit configured to apply a spectral tilt to the code of a codebook used for synthesizing a current frame of the audio signal,
wherein the spectral tilt is based on the spectral tilt of the current frame of the audio signal,
wherein the apparatus is configured to determine the spectral tilt of the current frame of the audio signal on the basis of spectral envelope information for the current frame of the audio signal,
wherein the processing unit is configured to apply the spectral tilt by filtering the code from the codebook based on a transfer function modeling the spectral tilt, and
wherein the processing unit comprises a hardware implementation.

US Pat. No. 10,431,231

HIGH-BAND RESIDUAL PREDICTION WITH TIME-DOMAIN INTER-CHANNEL BANDWIDTH EXTENSION

Qualcomm Incorporated, S...

1. A device comprising:a low-band mid signal decoder configured to decode a low-band portion of an encoded mid signal to generate a decoded low-band mid signal;
a low-band residual prediction unit configured to process the decoded low-band mid signal to generate a low-band residual prediction signal;
an up-mix processor configured to generate a low-band left channel and a low-band right channel based partially on the decoded low-band mid signal and the low-band residual prediction signal;
a high-band mid signal decoder configured to decode a high-band portion of the encoded mid signal to generate a time-domain decoded high-band mid signal;
a high-band residual prediction unit configured to process the time-domain decoded high-band mid signal to generate a time-domain high-band residual prediction signal; and
an inter-channel bandwidth extension decoder configured to generate a high-band left channel and a high-band right channel based on the time-domain decoded high-band mid signal and the time-domain high-band residual prediction signal.

US Pat. No. 10,431,228

PROVING FILE OWNERSHIP

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:receiving a first digital fingerprint;
using first and second information unpredictable to another system to modify a digital representation of an instance of content to result in a modified digital representation of the instance of content, wherein the modified digital representation is generated by permutating segments of the digital representation of the instance of content based on the first information, wherein a size of the segments of the digital representation of the instance of content is determined based on the second information;
calculating, based at least in part on the modified digital representation of the instance of content, a second digital fingerprint using a fingerprinting algorithm configured to produce matching digital fingerprints from different digital encodings of the same content;
verifying that the first digital fingerprint matches the second digital fingerprint; and
performing one or more operations corresponding to the first digital fingerprint matching the second digital fingerprint, wherein the one or more operations include providing access to the content.