US Pat. No. 10,141,470

PHOTODIODE TYPE STRUCTURE, COMPONENT AND METHOD FOR MANUFACTURING SUCH A STRUCTURE

1. A photodiode type structure intended to receive electromagnetic radiation in a given wavelength range, the photodiode type structure comprising:a support including at least one semiconductor layer, the semiconductor layer including of a first semiconductor zone of a first type of conductivity, the first semiconductor zone being made of a first semiconductor material having a forbidden band gap such that the first semiconductor zone is transparent in the given wavelength range;
a mesa in contact with the semiconductor layer, the mesa including a second semiconductor zone, known as absorption zone, the second semiconductor zone being of a second type of conductivity opposite to the first type of conductivity so as to form a semiconductor junction having a space charge zone, the second semiconductor zone being made of a second semiconductor material having a forbidden band gap suited to favoring the absorption of electromagnetic radiation, the second semiconductor zone having a concentration of majority carriers such that the second semiconductor zone is included within the space charge zone, and is thus depleted, in the absence of polarization of the structure; and
a third semiconductor zone of the second type of conductivity made of a third semiconductor material having a forbidden band gap such that the third semiconductor zone is transparent in the given wavelength range, the third semiconductor zone being interposed between the first and the second semiconductor zones while being at least partially arranged in the semiconductor layer and while forming the semiconductor junction with the first semiconductor zone in the semiconductor layer, wherein the third semiconductor zone also forming with the second semiconductor zone a potential barrier for minority carriers of the second semiconductor zone.

US Pat. No. 10,141,467

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

LG ELECTRONICS INC., Seo...

1. A solar cell comprising:a semiconductor substrate with a front surface, a back surface, and an edge connecting the front surface and the back surface;
a first conductive type region formed on substantially the entirety of the front surface of the semiconductor substrate;
a second conductive type region formed on the back surface of the semiconductor substrate, the second conductive type region being spaced from an edge of the semiconductor substrate and having a conductive type different from that of the first conductive type region;
an isolation portion formed at a perimeter of the second conductive type region on the back surface of the semiconductor substrate, wherein the isolation portion has a lower dopant concentration than the second conductive type region;
an anti-reflective film formed over substantially the entirety of the first conductive type region;
a passivation film formed over substantially the entirety of the second conductive type region and the isolation portion;
a first electrode connected to the first conductive type region through the anti-reflective film; and
a second electrode connected to the second conductive type region through the passivation film; wherein the semiconductor substrate comprises a base region in which the first and second conductive type regions are not disposed;
wherein the second conductive type region has a boundary portion in direct contact with the isolation portion, and in which a doping concentration of the boundary portion is changed linearly in relation to a distance from the edge of the semiconductor substrate at a predetermined slope,
wherein the second conductive type region comprises an effective area in direct contact with the boundary portion; wherein a doping concentration of the base region is a first concentration and a doping concentration of the effective area is a second concentration, the doping concentration of the boundary portion changes from a third concentration less than the second concentration and greater than the first concentration to the first concentration, and the third concentration is 1×1015/cm2 or more;
wherein a width of the isolation portion is smaller than a distance between the edge of the semiconductor substrate and an end of the second electrode that is closest to the edge of the semiconductor substrate,
wherein the second electrode is connected to the effective area of the second conductive type region,
wherein the second electrode includes:
a plurality of finger electrodes extended in a first direction; and
a plurality of bus bar electrodes extended in a second direction crossing the first direction, and
wherein the second conductive type region includes a first portion corresponding to the plurality of finger electrodes.

US Pat. No. 10,141,466

SUBSTRATE FOR SOLAR CELL, AND SOLAR CELL

SHIN-ETSU CHEMICAL CO., L...

1. A method for manufacturing a solar cell using a silicon substrate of square shape with corners as viewed in plan view, having a first corner and a second corner not diagonal to the first corner, which is provided with a chamfer at the first corner or a notch at or near the first corner and with a notch at or near the second corner or a chamfer at the second corner, the notch or chamfer at the second corner is selected to be different from the chamfer or notch at the first corner,wherein the first and second corners are used to identify the direction of the substrate and discriminate the front and back surfaces of the substrate during manufacturing.

US Pat. No. 10,141,463

PHOTOVOLTAIC DEVICES AND METHODS FOR MAKING THE SAME

First Solar Malaysia SDN....

1. A photovoltaic device, comprising:a support layer;
a cadmium and tellurium layer comprising cadmium and tellurium, and being of p-type; and
a transparent conductive oxide layer;
wherein the photovoltaic device is free of a CdS layer,
wherein the cadmium and tellurium layer comprises zinc, selenium, mercury, lead, or any combination thereof,
wherein a concentration of the zinc, selenium, mercury, lead, or any combination thereof within the cadmium and tellurium layer is compositionally graded, and
wherein a total atomic percentage of the zinc, selenium, mercury, lead, or any combination thereof of the cadmium and tellurium layer is up to about 10 atomic %.

US Pat. No. 10,141,462

SOLAR CELLS HAVING DIFFERENTIATED P-TYPE AND N-TYPE ARCHITECTURES

SunPower Corporation, Sa...

1. A solar cell, comprising:an N-type semiconductor substrate having a light-receiving surface and a back surface;
a plurality of N-type polycrystalline silicon regions disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate; and
a plurality of P-type polycrystalline silicon regions disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate, wherein a total area of the plurality of N-type polycrystalline silicon regions is greater than a total area of the plurality of P-type polycrystalline silicon regions in the plurality of corresponding trenches.

US Pat. No. 10,141,461

TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD

INTERNATIONAL BUSINESS MA...

1. A multi junction photovoltaic device, comprising:a semiconductor layer having substantially symmetrical pyramidal shapes with (111) facets exposed to form a textured surface;
a first p-n junction formed directly on the textured surface; and
at least one other p-n junction formed over the first p-n junction and following the textured surface.

US Pat. No. 10,141,458

VERTICAL GATE GUARD RING FOR SINGLE PHOTON AVALANCHE DIODE PITCH MINIMIZATION

OmniVision Technologies, ...

1. A photon detection device, comprising:a single photon avalanche diode (SPAD) disposed in a first region of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined at an interface between an n doped layer and a p doped layer of the SPAD in the first region of the first semiconductor layer;
a vertical gate structure disposed in the first semiconductor layer proximate to the SPAD, wherein the vertical gate structure surrounds the SPAD to isolate the SPAD in the first region of the first semiconductor layer from a second region of the first semiconductor layer on an opposite side of the vertical gate structure, wherein the n doped layer and the p doped layer of the SPAD laterally extend within the first region of the first semiconductor layer to contact the vertical gate structure; and
a depletion layer generated around a perimeter of the SPAD at an interface of the vertical gate structure and the p doped layer in response to a gate bias voltage coupled to the vertical gate structure, wherein the depletion layer isolates the SPAD from the second region of the first semiconductor layer on the opposite side of the vertical gate structure.

US Pat. No. 10,141,457

SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A solar cell comprising:a crystalline silicon semiconductor substrate of a first conductive type;
an emitter region having a second conductive type different from the first conductive type and at a first surface of the crystalline silicon semiconductor substrate, wherein the emitter region forms a p-n junction along with the crystalline silicon semiconductor substrate;
a silicon carbide layer directly on a second surface opposite the first surface of the crystalline silicon semiconductor substrate configured to form a first charge accumulation layer in the second surface of the crystalline silicon semiconductor substrate, and having a first impurity doping concentration of the first conductive type, the first charge accumulation layer to accumulate charge caused by a difference in band gap between the crystalline silicon semiconductor substrate and the silicon carbide layer;
a first electrode on the first surface of the crystalline silicon semiconductor substrate and coupled to the emitter region;
a heavily doped region under the first electrode and containing impurities of a second conductive type at a doping concentration higher than the crystalline semiconductor substrate and a second charge accumulation layer;
a second electrode on the second surface of the crystalline silicon semiconductor substrate and coupled to the crystalline silicon semiconductor substrate;
a surface field region partially in the second surface of the crystalline silicon semiconductor substrate and having a second impurity doping concentration of the first conductive type higher than the first impurity doping concentration of the silicon carbide layer; and
an anti-reflection part on the emitter region,
wherein the silicon carbide layer has a plurality of openings and the second electrode contacts the surface field region through the plurality of openings of the silicon carbide layer,
wherein a conduction band average energy level of the crystalline silicon semiconductor substrate is higher than a conduction band average energy level of the silicon carbide layer, and
wherein an amount of impurities contained of the silicon carbide layer is 1×1018/cm3 to 5×1020/cm3, and
wherein the emitter region is formed of a silicon carbide to form the second charge accumulation layer in the first surface of the crystalline silicon semiconductor substrate to accumulate charge caused by a difference in band gap between the crystalline silicon semiconductor substrate and the emitter region.

US Pat. No. 10,141,456

SCHOTTKY DIODE AND METHOD FOR ITS MANUFACTURING

Fraunhofer Gesellschaft Z...

1. A Schottky diode comprising:a drift region comprising diamond having a first conductivity type;
a plurality of junction barrier Schottky regions comprising diamond having a second conductivity type opposite the first conductivity type and being arranged on a top of the drift region and separated by spaces;
at least one Schottky contact being applied to the top of the drift region, thereby covering the junction barrier Schottky regions and filling the spaces between the junction barrier Schottky regions; and
at least one Ohmic contact on the drift region.

US Pat. No. 10,141,454

FIELD-EFFECT TRANSISTORS HAVING BLACK PHOSPHORUS CHANNEL AND METHODS OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a phosphorene-containing layer over a substrate, wherein a channel region, a source region, and a drain region are defined in the phosphorene-containing layer, and further wherein the channel region is disposed between a source region and a drain region; and
forming a passivation layer over the source region and the drain region defined in the phosphorene-containing layer.

US Pat. No. 10,141,453

SEMICONDUCTOR DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A semiconductor device comprising:a substrate; and
a thin film transistor supported on the substrate, the thin film transistor including a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,
a signal line connected to the source electrode and a scanning line connected to the gate electrode, the scanning line extending along a first direction and the signal line extending along a second direction crossing the first direction,wherein:the drain electrode, the source electrode and the oxide semiconductor layer are arranged in line along either the first direction or the second direction;
the source electrode is shaped so as to project along the second direction, and the drain electrode is arranged so as to oppose the source electrode with the oxide semiconductor layer interposed therebetween;
the drain electrode is shaped so as to project toward the oxide semiconductor layer;
a width W1 and a width W2 satisfy a relationship |W1?W2|?1 ?m, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects;
the width W1 and the width W2 are 3 ?m or more and 6 ?m or less;
the oxide semiconductor layer and the drain electrode are misaligned from each other in the first direction; and
a width W3 is 1 ?m or more and is less than the width W1, where the width W3 is a width in the first direction of an overlapping portion between the oxide semiconductor layer and the drain electrode.

US Pat. No. 10,141,448

VERTICAL FETS WITH DIFFERENT GATE LENGTHS AND SPACER THICKNESSES

International Business Ma...

1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:patterning fins having a uniform fin height in a substrate, wherein at least a first one of the fins comprises a vertical fin channel of a first VFET and wherein at least a second one of the fins comprises a vertical fin channel of a second VFET;
forming bottom source and drains at a base of the fins, wherein the bottom source and drains are doped;
forming first bottom spacers on the bottom source and drains at the base of the fins;
selectively forming second bottom spacers on the first bottom spacers at the base of the at least one second fin, wherein the second bottom spacers are configured to serve as a dopant source;
annealing the substrate under conditions sufficient to drive dopants i) from the bottom source and drains into the at least one first fin and ii) from the bottom source and drains and from the second bottom spacers into the at least one second fin, forming bottom junctions at the base of the at least one first fin having a height H1 and bottom junctions at the base of the at least one second fin having a height H2, wherein H2>H1;
forming gates along sidewalls of the fins above the bottom source and drains, wherein the gates along the sidewalls of the at least one first fin have a gate length Lg1 and the gates along the sidewalls of the at least one second fin have a gate length Lg2, wherein Lg1>Lg2 based on H2>H1;
forming top spacers above the gates at tops of the fins; and
forming top source and drains above the top spacers at the tops of the fins.

US Pat. No. 10,141,447

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor device, comprising:an active fin extended in a first direction on a substrate;
a gate structure extended in a second direction, wherein the gate structure intersects the active fin, and covers an upper portion of the active fin;
a source/drain region on the active fin adjacent to the gate structure;
a silicide layer on the source/drain region;
a contact plug connected to the source/drain region; and
a void between the silicide layer and the contact plug.

US Pat. No. 10,141,444

OXIDE THIN-FILM TRANSISTOR WITH ILLUMINATED OHMIC CONTACT LAYERS, ARRAY SUBSTRATE AND METHODS FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an oxide thin-film transistor, comprising:forming a pattern of a light shielding layer on a base substrate that is made of a light-transmissive material, wherein the light shielding layer is made of an organic material;
forming a pattern of an oxide semi-conductor layer above the base substrate, wherein an orthographic projection of the pattern of the light shielding layer onto the base substrate is completely located within and is smaller than an orthographic projection of the pattern of the oxide semi-conductor layer onto the base substrate;
providing the ultraviolet light source at a side of the base substrate away from the light shielding layer;
illuminating, by the ultraviolet light source, two opposite boundary regions of the pattern of the oxide semi-conductor layer that are not shielded by the light shielding layer, wherein the illuminated two opposite boundary regions of the pattern of the oxide semi-conductor layer form ohmic contact layers and a region of the pattern of the oxide semi-conductor layer that is not illuminated forms a semi-conductor active layer;
forming a gate insulator on the semi-conductor active layer and forming a gate electrode on the gate insulator; and
forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are connected to the semi-conductor active layer via the ohmic contact layers respectively,
wherein the oxide thin-film transistor is of a top-gate structure, and the gate electrode is arranged between the semi-conductor active layer and the source electrode and the drain electrode in a direction in which the semi-conductor active layer, the gate insulator, and the gate electrode are stacked, and the light shielding layer is sandwiched between the oxide semi-conductor layer and the base substrate.

US Pat. No. 10,141,443

SEMICONDUCTOR DEVICES FINFET DEVICES WITH OPTIMIZED STRAINED-SOURECE-DRAIN RECESS PROFILES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate;
a gate stack over the substrate; and
a strained layer in a recess of the substrate and aside the gate stack,
wherein a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7,
wherein the semiconductor device further comprises a spacer on a sidewall of the gate stack, a top edge of the recess is covered by and spaced apart from an outer edge of the spacer, a sidewall of the recess connecting the top edge and a bottom edge of the recess is a curved surface without a sharp turning point, and an included angle between an upper portion of the sidewall of the recess and a surface of the substrate is from about 50 degrees to 90 degrees, and
wherein the substrate is a substrate with at least one fin extending in a first direction, and the gate stack extends in a second direction different from the first direction and is across the at least one fin.

US Pat. No. 10,141,442

SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

INTEL CORPORATION, Santa...

1. A semiconductor device, comprising:a gate stack on a substrate, wherein the gate stack is comprised of a metallic gate electrode above a portion of the substrate, and a gate dielectric layer between the metallic gate electrode and the portion of the substrate, the gate dielectric layer also along sidewalls of the metallic gate electrode, the gate dielectric layer comprising a top high-k dielectric portion and a bottom portion having a dielectric constant less than or equal to a dielectric constant of silicon dioxide;
a pair of source/drain regions in the substrate, the portion of the substrate between the pair of source/drain regions, wherein a lattice constant of the pair of source/drain regions is different than a lattice constant of the portion of the substrate, and wherein at least a portion of the pair of source/drain regions is under a portion of the gate dielectric layer and under a portion of the metallic gate electrode;
a shallow trench isolation structure laterally adjacent to one of the pair of source/drain regions; and
an inter-layer dielectric layer directly laterally adjacent to and in contact with a portion of the gate dielectric layer along the sidewalls of the metallic gate electrode, the inter-layer dielectric layer over the pair of source/drain regions, the inter-layer dielectric layer also over the shallow trench isolation structure;
wherein the pair of source/drain regions have an undercut profile of approximately 55 degrees with respect to an uppermost surface of the substrate, the undercut profile extending from the gate dielectric layer into the substrate, such that the undercut profile commences from and is in contact with a bottommost surface of the bottom portion of the gate dielectric layer; and
wherein a top surface of the one of the pair of source/drain regions that is laterally adjacent to the shallow trench isolation structure is higher than a top surface of the shallow trench isolation structure.

US Pat. No. 10,141,441

VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE

INTERNATIONAL BUSINESS MA...

1. A method of making a vertical transistor device, the method comprising:forming a front gate and a back gate opposite a major surface of a substrate, the front gate and the back gate being symmetric and arranged on opposing sides of a channel between the front gate and the back gate, the channel extending from a drain to a source;
forming a mask to cover the front gate;
removing the back gate; and
replacing the back gate with a layer of insulator and another back gate stack, the another back gate stack only covering a junction between the channel and the source, and remaining portions of the back gate being the layer of insulator.

US Pat. No. 10,141,440

DRIFT-REGION FIELD CONTROL OF AN LDMOS TRANSISTOR USING BIASED SHALLOW-TRENCH FIELD PLATES

Polar Semiconductor, LLC,...

1. A Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistor comprising:a substrate layer;
an active device layer vertically adjacent to and separated from the substrate layer by a metallurgical junction, the active device layer comprising:
a source;
a body having a body contact region and a channel region; and
a drain having a drain contact region and a drift region, the drift region laterally extending from a drift-region/body metallurgical junction and a drift-region/drain-contact-region interface; and
an interconnect layer vertically adjacent to and separated from the active device layer by an interface surface, the interconnect layer comprising:
a gate extending from a first end located above the source, over the channel region, and to a second end located above the drift region; and
one or more contacts providing electrical connection between one or more nets in the interconnect layer and each of the source, the body contact region and the drain contact region in the active device layer; and
a pair of adjacent trenches vertically extending from the interface surface to a dielectric trench bottom, the trenches laterally separated from one another by the drift region, each of the trenches having first and second conductive field plates longitudinally separated from one another by an intervening dielectric, the first and second conductive field plates electrically connected to one or more biasing circuit nets in the interconnection layer, the first and second conductive field plates separated from the drift region by a dielectric material.

US Pat. No. 10,141,439

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first GaN based semiconductor layer of a first conductive type;
a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, the second GaN based semiconductor layer having an impurity concentration of the first conductive type lower than that of the first GaN based semiconductor layer;
a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer;
a fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, the fourth GaN based semiconductor layer having the impurity concentration of the first conductive type higher than that of the second GaN based semiconductor layer;
a gate insulating film provided on the second GaN based semiconductor layer, the third GaN based semiconductor layer, and the fourth GaN based semiconductor layer;
a gate electrode provided on the gate insulating film;
a first electrode provided on the fourth GaN based semiconductor layer;
a second electrode provided at a side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer;
a third electrode provided on the second GaN based semiconductor layer; and
a plurality of fifth GaN based semiconductor layers of the second conductive type provided above a part of the second GaN based semiconductor layer, the plurality of fifth GaN based semiconductor layers surrounding the first electrode and the third electrode, the plurality of fifth GaN based semiconductor layers being provided to be separated from each other, the plurality of fifth GaN based semiconductor layers having substantially the same impurity concentration of the second conductive type as the third GaN based semiconductor layer;
wherein the first electrode is provided in a groove having a bottom-face and side-faces, the third GaN based semiconductor layer is exposed to the bottom-face, the fourth GaN based semiconductor layer is exposed to the side-faces, and the first electrode is in contact with the third GaN based semiconductor layer.

US Pat. No. 10,141,438

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
a first III-V compound layer over the substrate;
a first passivation layer on the first III-V compound layer;
a source electrode penetrating the first passivation layer to electrically contact the first III-V compound layer; and
a drain electrode penetrating the first passivation layer to electrically contact the first III-V compound layer,
wherein a lower portion of the source electrode directly surrounded by the first passivation layer, the lower portion comprising:
an upper part having a first width; and
a lower part having a second width, the first width being greater than the second width; and
wherein an upper portion of the source electrode further comprises a third width measured from one side to an opposite side of an outer circumference of the upper portion, the third width being smaller than the first width.

US Pat. No. 10,141,437

EXTREME HIGH MOBILITY CMOS LOGIC

Intel Corporation, Santa...

1. A transistor, comprising:a doped silicon semi-insulating substrate;
a buffer layer disposed above the doped silicon semi-insulating substrate;
a bottom barrier layer disposed above the buffer layer wherein the bottom barrier layer comprises a material different than the buffer layer;
a group III-V material quantum well layer disposed above the bottom barrier layer;
a top barrier layer disposed above the group III-V material quantum well layer;
a gate stack disposed above the top barrier layer, the gate stack comprising:
a high-k gate dielectric layer disposed above the top barrier layer; and
a metal gate electrode disposed above the high-k gate dielectric layer; and
a semiconductor cap layer on an etch stop layer on the top barrier layer, wherein the gate stack is in an opening through the semiconductor cap layer.

US Pat. No. 10,141,436

TUNNEL FIELD EFFECT TRANSISTOR HAVING ANISOTROPIC EFFECTIVE MASS CHANNEL

Purdue Research Foundatio...

1. A tunnel field effect transistor (TFET) device, comprising:a substrate;
heavily doped source and drain regions disposed at opposite ends of the substrate separated by a channel region, where the channel region is intrinsic or lightly doped with doping of less than 1018/cm3 and the source and drain regions doped with doping of between about 1018/cm3 to about 1021/cm3, collectively forming a structure wherein the structure is PiN or NiP;
a gate terminal separated from the channel region by a dielectric layer;
a source and drain terminal coupled to the source and drain regions, respectively,
the channel region comprising a channel material having a first effective mass along a longitudinal axis extending from the source region to the drain region and a second effective mass along a lateral axis perpendicular to the longitudinal axis, wherein a ratio of the first effective mass to the second effective mass is between 1 and 50, the channel region comprising a first substantially parallelogram portion having a first length defined along a longitudinal axis extending from the source region to the drain region and a second substantially parallelogram portion connected to the first substantially parallelogram portion having a second length defined along the longitudinal axis and larger than the first length, the TFET device having an effective channel length defined along the longitudinal axis that is an average of the first and second lengths.

US Pat. No. 10,141,429

FINFET HAVING ISOLATION STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of making a transistor, comprising:forming a fin structure protruding from an upper surface of a substrate, the fin structure extending along a first direction and comprising a lower portion and an upper portion;
forming a first isolation structure over the upper surface of the substrate and surrounding the lower portion of the fin structure;
patterning a recess in the fin structure;
depositing a second isolation structure in the recess;
forming a gate structure over the fin structure and extending along a second direction different from the first direction, the gate structure and the fin structure defining a non-overlapping region in the upper portion of the fin structure, wherein the patterning the recess in the fin structure comprises patterning the recess in the non-overlapping region of the fin structure; and
forming a drain contact region in the non-overlapping region of the fin structure, the second isolation structure being between the drain contact region and the gate structure.

US Pat. No. 10,141,428

FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a plurality of fins from a first material, the plurality of fins formed over a substrate and defining troughs therebetween;
depositing a semiconductor layer formed from a second material over the plurality of fins, the second material being different than the first material;
depositing dielectric material covering the plurality of fins and the semiconductor layer, the dielectric material defining dielectric regions;
diffusing the second material from the semiconductor layer into an entirety of each fin of the plurality of fins;
removing the dielectric regions; and
planarizing an upper surface of the dielectric regions to be planar with an upper surface of the plurality of fins.

US Pat. No. 10,141,427

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING GATE PATTERN, MULTI-CHANNEL ACTIVE PATTERN AND DIFFUSION LAYER

Samsung Electronics Co., ...

1. A method for fabricating a semiconductor device comprising:forming a multi-channel active pattern protruding from an isolation layer;
forming a dummy gate pattern on the multi-channel active pattern, the dummy gate pattern overlapping a portion of the multi-channel active pattern;
after forming the dummy gate pattern on the multi-channel active pattern, forming a pre-liner layer on a top surface of the multi-channel active pattern not overlapping the dummy gate pattern;
forming an impurity supply layer on a top surface of the pre-liner layer that is on the multi-channel active pattern not overlapping the dummy gate pattern;
forming a first diffusion layer in the multi-channel active pattern not overlapping the dummy gate pattern by performing a first thermal process on the impurity supply layer at a first temperature; and
after forming the first diffusion layer in the multi-channel active pattern not overlapping the dummy gate pattern, forming a second diffusion layer in the multi-channel active pattern along an outer periphery of the multi-channel active pattern not overlapping the dummy gate pattern by performing a second thermal process on the impurity supply layer at a second temperature.

US Pat. No. 10,141,426

VERTICAL TRANSISTOR DEVICE

INTERNATIONAL BUSINESS MA...

1. A vertical transistor device comprising:a semiconductor substrate including a substrate material;
a first semiconductor fin forming a vertical channel region comprising a semiconductor material arranged on the semiconductor substrate;
a first source/drain region comprising a first portion directly vertically beneath the semiconductor material of the first semiconductor fin and a second portion, the first portion comprising a doped portion of the semiconductor substrate arranged below and in contact with the second portion, the second portion comprising a doped epitaxially grown semiconductor material, the doped epitaxially grown semiconductor material being a dissimilar material from the substrate material, and the first source/drain region comprising a graduated doping concentration profile that extends from the doped epitaxially grown semiconductor material to the vertical channel region;
a first spacer layer arranged directly on the second portion of the first source/drain region;
a first gate stack arranged directly on the first spacer layer, the first gate stack comprising gate dielectric material, a work function metal, and a conductive metal; a sidewall of the first gate stack directly contacting a sidewall of the first semiconductor fin, and a top surface of the first semiconductor fin arranged above a top surface of the first gate stack; and
a second spacer layer arranged directly on the first gate stack and extending higher than the first semiconductor fin;
wherein the first gate stack of the vertical transistor device wraps around horizontal sides of the vertical channel region, and the conductive metal of the first gate stack is arranged in contact the second spacer layer.

US Pat. No. 10,141,425

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising:forming a first oxide semiconductor layer over and in contact with an insulating surface;
forming a second oxide semiconductor layer over the first oxide semiconductor layer;
performing first heat treatment in a first atmosphere after the step of forming the second oxide semiconductor layer;
forming a third oxide semiconductor layer over the second oxide semiconductor layer;
forming an insulating film over and in contact with the third oxide semiconductor layer; and
performing second heat treatment after the step of forming the insulating film,
wherein the first atmosphere is any one of a nitrogen atmosphere, an oxygen atmosphere, and a dry-air atmosphere.

US Pat. No. 10,141,424

METHOD OF PRODUCING A CHANNEL STRUCTURE FORMED FROM A PLURALITY OF STRAINED SEMICONDUCTOR BARS

IBM CORPORATION, Yorktow...

1. A Method for fabricating a structure with semiconducting bars suitable for forming at least one transistor channel, including:providing at least a semiconducting structure on a substrate, composed of an alternation of first bars based on at least a first material and second bars based on at least a second material, the second material being a semiconducting material, the first bars and the second bars being stacked, then
forming a sacrificial gate and first insulating spacers on each side of the sacrificial gate, then
removing regions of the stack located on each side of the insulating spacers, then
removing end portions from the first bars by selective etching of the first material relative to the second material so as to expose spaces around the ends of the second bars,
forming of internal spacers in said spaces around said ends of the second bars, then
forming of semiconducting source and drain blocks by growth of at least one semiconducting material on each side of the insulating spacers and the internal spacers,
then,
removing exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around a central portion of the second bars, then
growing or depositing a layer of a semiconducting material around the second bars in the opening such that the semiconducting material is in contact with the second bars, the semiconducting material having a mesh parameter different from the mesh parameter of the second material so as to induce a strain on the layer of the semiconducting material.

US Pat. No. 10,141,423

THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A fabrication method of a thin film transistor (TFT), comprising steps of:forming a protection layer in an area above an active layer between a source electrode and a drain electrode to be formed;
forming a source-drain metal layer above the active layer having the protection layer formed thereabove;
coating a photoresist on the source-drain metal layer, and forming a photoresist reserved area and a photoresist non-reserved area, wherein the photoresist reserved area corresponds to areas of the source electrode and the drain electrode to be formed, and the photoresist non-reserved area corresponds to the other area;
etching off the source-drain metal layer corresponding to the photoresist non-reserved area to form the source electrode and the drain electrode and expose the protection layer above the active layer; and
removing the photoresist above the source electrode and the drain electrode and the protection layer.

US Pat. No. 10,141,421

VERTICAL POWER MOSFET AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor layer of a first conductivity type;
a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite to the first conductivity type;
a doped semiconductor region of the first conductivity type between and contacting the first and the second body regions, wherein the doped semiconductor region has a bottom portion extending into the semiconductor layer to separate a top surface layer of the semiconductor layer into a first region and a second region;
a gate dielectric layer over the first and the second body regions and the doped semiconductor region; and
a first gate electrode and a second gate electrode over the gate dielectric layer, and overlapping the first and the second body regions, respectively, wherein the first and the second gate electrodes are physically separated from each, and are electrically interconnected, and wherein the doped semiconductor region is overlapped by a region between the first and the second gate electrodes.

US Pat. No. 10,141,419

TWO-STEP DUMMY GATE FORMATION

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a semiconductor fin between opposite portions of the isolation regions, wherein the semiconductor fin is higher than top surfaces of the isolation regions;
a gate stack on a top surface and opposite sides of the semiconductor fin; and
a gate spacer contacting a sidewall of the gate stack, wherein the gate spacer comprises:
a lower portion having a first inner edge contacting a sidewall of the gate stack; and
an upper portion over the lower portion, the upper portion having a second inner edge contacting the sidewall of the gate stack, wherein the first inner edge and the second inner edge are in different vertical planes.

US Pat. No. 10,141,416

SEMICONDUCTOR STRUCTURE WITH ENLARGED GATE ELECTRODE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

8. A method for manufacturing a semiconductor structure, comprising:forming a trench over a substrate;
forming a gate dielectric layer on sidewalls and a bottom of the trench;
forming a plurality of conductive layers over the gate dielectric layer on the sidewalls and the bottom of the trench;
forming a blocking structure in a lower portion of the trench over the plurality of conductive layers;
etching a portion of each of the plurality of conductive layers not covered by the blocking structure, wherein the etching forms a sloped top surface of each of the plurality of conductive layers, wherein the sloped top surface extends from a termination point level with and interfacing a top surface of the blocking structure upwards towards another termination point closer a nearest sidewall of the trench;
after the etching, removing the blocking structure; and
after removing the blocking structure, depositing at least one additional conductive gate layer over the etched plurality of conductive layers.

US Pat. No. 10,141,415

COMBINED GATE AND SOURCE TRENCH FORMATION AND RELATED STRUCTURE

Infineon Technologies Ame...

1. A method of forming a semiconductor device, said method comprising:forming a semiconductor substrate including a drain region, a drift region above said drain region, a base region above said drift region, and a source region above said base region, said drain region, said drift region and said source region having a first conductivity type and said base region having a second conductivity type opposite said first conductivity type;
forming a gate trench and a first portion of a source trench in said semiconductor substrate and both extending into said drift region to a same first depth in said semiconductor substrate, said first portion of said source trench being wider than said gate trench;
forming a gate electrode in said gate trench;
after forming said gate trench and said first portion of said source trench, forming a second portion of said source trench under said first portion and extending deeper into said drift region than said first portion, said second portion being narrower than said first portion and extending to a second depth in said semiconductor substrate greater than said first depth;
lining sidewalls of said first portion, sidewalls of said second portion and a bottom of said second portion with a dielectric material; and
forming a conductive filler in said source trench, said conductive filler insulated from the surrounding semiconductor substrate by said dielectric material.

US Pat. No. 10,141,412

FIELD EFFECT TRANSISTOR USING TRANSITION METAL DICHALCOGENIDE AND A METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A field effect transistor (FET), comprising:a gate dielectric layer;
a channel layer formed on the gate dielectric layer; and
a gate electrode, wherein:
the channel layer includes a body region having a first side and a second side opposite to the first side, the body region being a channel of the FET,
the channel layer further includes first finger regions each protruding from the first side of the body region and second finger regions each protruding from the second side of the body region,
a source electrode covers the first finger regions, and a drain electrode covers the second finger regions,
the channel layer is a single layer or multiple layers of MoS2,
each of the first finger regions and each of the second finger regions extend along a first direction, and
the first direction corresponds to a zigzag edge structure of the MoS2 layer, which extends perpendicular to atomic bonds located at the edge.

US Pat. No. 10,141,411

TEMPERATURE SENSING SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate of silicon carbide, wherein the semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated through an epitaxial growth technique by depositing the n-type drift region on the semiconductor substrate and then by depositing the p-type body region on the n-type drift region; and
a temperature sensor portion disposed in the semiconductor substrate and separated from the drift region by the body region,
wherein the body region extends from the temperature sensor portion through the areas having a plurality of trench gates, and
wherein the temperature sensor portion comprises:
an n-type cathode region being in contact with the body region; and
a p-type anode region separated from the body region by the cathode region.

US Pat. No. 10,141,409

THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising: a source electrode, a drain electrode, a gate electrode; an active region and a gate insulating layer, wherein, the source electrode, the drain electrode and the gate electrode are composed of graphene, the active region is composed of doped oxidized graphene, the gate insulating layer is composed of oxidized graphene,and wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is formed by reducing oxidized graphene, and the doped oxidized graphene composing the active region is formed by treating oxidized graphene.

US Pat. No. 10,141,408

METHOD AND ARRANGEMENT FOR REDUCING CONTACT RESISTANCE OF TWO-DIMENSIONAL CRYSTAL MATERIAL

INSTITUTE OF MICROELECTRO...

1. A method, comprising:forming a contact material layer on a two-dimensional crystal material layer, the contact material layer forming an electrical contact to the two-dimensional crystal material layer;
performing ion implantation on at least the two-dimensional crystal material layer, to bombard the two-dimensional crystal material layer so as to create vacancies therein; and
performing thermal annealing of the contact material layer and the two-dimensional crystal material layer for interaction of the vacancies with the contact material layer and implanted ions, so that they form bonds to modify a contact interface between the contact material layer and the two-dimensional crystal material layer.

US Pat. No. 10,141,406

TENSILE STRAINED NFET AND COMPRESSIVELY STRAINED PFET FORMED ON STRAIN RELAXED BUFFER

International Business Ma...

1. A fabrication method, comprising:obtaining a structure including a substrate and a strain relaxed silicon germanium buffer layer on the substrate;
forming an epitaxial silicon germanium layer on a first region of the strain relaxed buffer layer, the epitaxial silicon germanium layer being doped with dopants of a first conductivity type;
forming a tensile strained layer comprising silicon directly on the epitaxial silicon germanium layer;
forming an epitaxial relaxed layer comprising silicon on a second region of the strain relaxed buffer layer, the epitaxial relaxed layer being doped with dopants of a second conductivity type that is opposite in polarity to the first conductivity type;
forming a compressively strained silicon germanium layer directly on the epitaxial relaxed layer;
electrically isolating the first and second regions;
forming first and second recesses extending respectively within the first and second regions of the strain relaxed silicon germanium buffer layer; and
forming the epitaxial silicon germanium layer within the first recess and forming the epitaxial relaxed layer within the second recess;
wherein the strain relaxed buffer layer has at least a top region having the composition Si1-xGex where x is between 0.2 and 0.3, the epitaxial silicon germanium layer has the composition Si1-yGey where y is equal to or exceeds x by 0.02 or less, and the compressively strained silicon germanium layer has the composition Si1-zGez where z is between 0.2 and 0.3.

US Pat. No. 10,141,405

LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE

International Business Ma...

1. A method of forming a lateral bipolar junction transistor (LBJT) comprising:providing a germanium containing material on a nucleation dielectric layer with a bonding method;
patterning the germanium containing material selectively to the nucleation dielectric layer to form a base region present overlying a pedestal of the passivating layer;
forming emitter and collector extension regions on opposing sides of the base region; and
forming an emitter region and collector region on exposed portions of the nucleation dielectric layer extending into contact with the emitter and collector extension regions.

US Pat. No. 10,141,403

INTEGRATING THIN AND THICK GATE DIELECTRIC NANOSHEET TRANSISTORS ON SAME CHIP

International Business Ma...

13. A semiconductor structure, comprising:a single nanosheet stack formed over a substrate;
a thin gate dielectric nanosheet transistor formed by fabricating a first portion of the single nanosheet stack, the thin gate dielectric nanosheet transistor including a plurality of nanosheets separated from each other by a first distance; and
a thick gate dielectric nanosheet transistor formed by fabricating a second portion of the single nanosheet stack, the thick gate dielectric nanosheet transistor including a plurality of nanosheets separated from each other by a second distance, the second distance being greater than the first distance.

US Pat. No. 10,141,402

FINFET DEVICES

INTERNATIONAL BUSINESS MA...

1. A structure comprising a plurality of fin structures which are supported by lined insulator material, wherein the lined insulator material is provided on an in-situ doped material.

US Pat. No. 10,141,401

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:performing a first plasma etching process on a substrate to form a first trench in the substrate, wherein the first plasma etching process uses a first etching gas and a first deposition gas, the first trench surrounds a first portion of the substrate, the first portion has a top surface and a first inclined surface, the first inclined surface connects the top surface to a bottom surface of the first trench, and the first inclined surface is inclined relative to the top surface at a first angle;
removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench, wherein the second trench surrounds a third portion of the substrate under the first portion, the third portion has a first sidewall, the first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle;
forming an isolation structure in the first trench and the second trench, wherein the isolation structure has a second inclined surface, and the first inclined surface and the second inclined surface form second sidewalls of a recess;
forming a gate insulating layer over the top surface and the first inclined surface, wherein the gate insulating layer extends into the recess and partially covers the second inclined surface, the recess is filled with the gate and the gate insulating layer, and the gate is over the isolation structure partially; and
forming a gate over the gate insulating layer and the isolation structure, wherein the gate crosses the first portion, and the gate extends into the recess.

US Pat. No. 10,141,397

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) forming a first epitaxial layer of a first conductivity type over a semiconductor substrate;
(b) forming a first trench in the first epitaxial layer;
(c) filling the first trench with a semiconductor material of a second conductivity type opposite to the first conductivity type;
(d) after the step (c), forming a second epitaxial layer of the first conductivity type over the first epitaxial layer including the first trench filled with the semiconductor material;
(e) forming a second trench in the second epitaxial layer, the second trench being planarly superposed on the first trench and connected with the first trench;
(f) filling the second trench with the semiconductor material of the second conductivity type; and
(g) after the step (f), forming an element section over the second epitaxial layer.

US Pat. No. 10,141,395

HIGH-K METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

INTERNATIONAL BUSINESS MA...

1. A metal-insulator-metal (MIM) capacitor, comprising, in a cross-sectional view:a first metal plate;
a second metal plate;
a third metal plate; and
a layer of high-k material contacting the first metal plate, the second metal plate, and the third metal plate.

US Pat. No. 10,141,394

INTEGRATED CIRCUIT COMPRISING A METAL-INSULATOR-METAL CAPACITOR AND FABRICATION METHOD THEREOF

IMEC vzw, Leuven (BE)

1. An integrated circuit (IC) comprising:a semiconductor substrate; and
a plurality of metallization levels, each metallization level comprising a layer of intermetal dielectric having metal areas embedded therein,
a metal-insulator-metal capacitor (MIMCAP) comprising a bottom electrode, a top electrode and a metal-insulator-metal (MIM) stack comprising a lower conductive layer, an upper conductive layer and an insulator layer sandwiched between the lower and upper conductive layers,
wherein the bottom electrode comprises a planar metal area of a lower metallization level, the planar metal area having perforations formed therethrough,
wherein the IC comprises cavities, each cavity extending through one of the perforations and into the semiconductor substrate, each cavity being separated from edges of a corresponding perforation by a first intermetal dielectric material of the lower metallization level,
wherein the MIM stack comprises a planar portion of the MIM stack on at least a part of an upper surface of the bottom electrode and a plurality of non-planar portions of the MIM stack extending into the cavities, the MIM stack lining the sidewalls and bottoms of the cavities, and
wherein the top electrode comprises:
a planar portion of the top electrode formed by a planar metal area of an upper metallization level adjacent to the lower metallization level, wherein the planar portion of the top electrode is formed on at least a part of an upper surface of the planar portion of the MIM stack, and wherein the planar portion of the top electrode has sidewalls lined by portions of the MIM stack, and
non-planar portions of the top electrode extending from the planar portion of the top electrode into the cavities.

US Pat. No. 10,141,393

THREE DIMENSIONAL CAPACITOR

Cypress Semiconductor Cor...

1. A device, comprising:a first conductor disposed directly on a substrate, wherein a bottom surface of the first conductor is in contact with a semiconducting portion of the substrate and the first conductor further includes a top surface, first and second sidewalls;
a dielectric structure disposed at least partly over the first conductor; and
a second conductor disposed over and covering the dielectric structure partly, wherein the second conductor is not disposed over the top surface of the first conductor.

US Pat. No. 10,141,392

MICROSTRUCTURE MODULATION FOR 3D BONDED SEMICONDUCTOR STRUCTURE WITH AN EMBEDDED CAPACITOR

International Business Ma...

11. A method of forming a three-dimensional (3D) bonded semiconductor structure, the method comprising:providing a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and a first metallic capacitor plate structure having a columnar grain microstructure embedded in the first bonding oxide layer, and a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and a second metallic capacitor plate structure having a columnar grain microstructure embedded in the second bonding oxide layer;
forming a high-k dielectric material on a surface of the first metallic capacitor plate structure or the second metallic capacitor plate structure; and
bonding the first semiconductor structure to the second semiconductor structure, wherein the bonding provides a bonding interface between the first and second bonding oxide layers and another bonding interface between the high-k dielectric material and the first metallic capacitor plate structure or the second metallic capacitor plate structure.

US Pat. No. 10,141,387

DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising: a substrate; a light emitting diode disposed above the substrate; a first transistor disposed above the substrate and comprising: a first semiconductor layer; a first top gate electrode disposed above the first semiconductor layer; a first bottom gate electrode disposed under the first semiconductor layer; a first source electrode electrically connected to the first semiconductor layer; and a first drain electrode electrically connected to the first semiconductor layer, wherein the first drain electrode is electrically connected to the light emitting diode; and a second transistor disposed above the substrate and comprising a second semiconductor layer; wherein one of the first semiconductor layer and the second semiconductor layer comprises a first silicon semiconductor layer, and the other comprises a first oxide semiconductor layer, wherein the second transistor further comprises a first gate electrode and a second gate electrode, the first gate electrode is disposed above the second semiconductor layer, and the second gate electrode is disposed under the second semiconductor layer, wherein the second transistor further comprises a second drain electrode electrically connected to the second semiconductor layer, and the second drain electrode is electrically connected to the first source electrode through a conductive line or by direct contact, wherein the second transistor further comprises a second source electrode electrically connected to the second semiconductor layer, and the second source electrode is electrically connected to the first drain electrode through a conductive line or by direct.

US Pat. No. 10,141,386

ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising: a base substrate, a plurality of pixel units disposed on a side of the base substrate, a chip for providing signal to the plurality of pixel units, and signal lines corresponding to each of the plurality of the pixel units,wherein the chip is disposed on an opposed side of the base substrate having the plurality of pixel units disposed thereon,
wherein via holes penetrating at least the base substrate are disposed on the array substrate,
wherein the signal lines electrically connect each of the plurality of the pixel units to the chip through the via holes,
wherein the signal lines comprise wires that comprise first wires and second wires, the first wires at least comprise gate lines, and the second wires at least comprise data lines, and
wherein the chip at least comprises a gate driving chip connected to the gate lines and a source driving chip connected to the data lines.

US Pat. No. 10,141,385

THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY PANEL USING SAME

HON HAI PRECISION INDUSTR...

1. A thin film transistor (TFT) substrate, the TFT substrate defining a display area and a non-display area surrounding the display area, the TFT substrate comprising:a substrate;
a plurality of first scanning lines on the substrate and in the display area, each of the plurality of first scanning lines extending along a first direction;
a plurality of data lines on the substrate and in the display area, each of the plurality of data lines extending along a second direction that is different from the first direction, each of the plurality of data lines electrically insulated from the plurality of first scanning lines;
a conductive layer on the substrate and above the plurality of first scanning lines;
at least one electrically insulating layer on the substrate and between the plurality of first scanning lines and the conductive layer;
a touch sensing layer on the substrate and above the conductive layer;
wherein the conductive layer forms a plurality of second scanning lines in the display area and a plurality of touch traces; each of the plurality of touch traces is electrically coupled to the touch sensing layer; each of the plurality of second scanning lines is electrically coupled to one of the plurality of first scanning lines by extending through the at least one electrically insulating layer.

US Pat. No. 10,141,382

METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL HAVING POLYMER NETWORK LIQUID CRYSTAL

Samsung Display Co., Ltd....

1. A method of manufacturing an organic light emitting diode display panel, comprising:forming a lower substrate, the lower substrate comprising a first area and a second area;
forming an organic light emitting device on the lower substrate;
disposing a polymer network liquid crystal on the organic light emitting device;
forming a second optical layer in the second area, the second optical layer comprising the polymer network liquid crystal; and
varying an optical property of the polymer network liquid crystal so as to form a first optical layer in the first area in which the first optical layer has a first refractive index different than a second refractive index of the second optical layer.

US Pat. No. 10,141,377

ELECTROLUMINESCENT DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An electroluminescent display device comprising:a substrate on which first and second pixel regions are defined;
a passivation layer over the substrate;
a first electrode in each of the first and second pixel regions on the passivation layer;
a bank layer exposing the first electrode;
a light emitting layer on the first electrode exposed by the bank layer; and
a second electrode on the light emitting layer,
wherein the bank layer includes first and second openings exposing the first electrodes corresponding to the first and second pixel regions, respectively,
wherein the bank layer further includes a third opening exposing the first electrode corresponding to a third pixel region,
wherein a depth of the first opening is larger than a depth of the third opening,
wherein a height of the bank layer of the third pixel region is smaller than a height of the bank layer of the first pixel region, and
wherein the passivation layer has a groove in the second opening of the second pixel region, and each of the bank layer of the first and second pixel regions has a same height.

US Pat. No. 10,141,374

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a plurality of first interconnects provided along a first direction, respectively;
a plurality of second interconnects provided along a second direction different from the first direction, respectively;
a plurality of third interconnects provided along a third direction different from the first and second directions, respectively;
a plurality of memory cells including variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects and coupled with the mutually different second interconnects; and
a plurality of selectors which couple the third interconnects with the first interconnects,
wherein one of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects,
a plurality of gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween, and
wherein in each of the selectors, gates provided on the side surfaces of the semiconductor layer are coupled with each other in common along a second direction, and
the gates are separated between the selectors.

US Pat. No. 10,141,372

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

8. A three-dimensional semiconductor device, comprising:a substrate including a cell array region, a dummy region, a contact region, and an overlapped region,
the contact region being adjacent to the cell array region in a first direction, the dummy region being adjacent to the cell array region in a second direction, the overlapped region being adjacent to the contact region in the second direction and adjacent to the dummy region in the first direction, the second direction being perpendicular to the first direction;
a first stack structure including a plurality of first electrodes vertically stacked on the substrate, the first stack structure extending along the first direction on the cell array region and the contact region; and
a second stack structure including a plurality of second electrodes vertically stacked on the substrate, the second stack structure spaced apart from the first stack structure in the second direction and provided on the dummy region and the overlapped region,
wherein the second stack structure has a first staircase structure extending in the first direction and a second staircase structure extending in the second direction,
the first staircase structure has a first slope with respect to the top surface of the substrate and the second staircase structure has a second slope with respect to the top surface of the substrate, and
the second slope is greater than the first slope.

US Pat. No. 10,141,370

OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME

1. An optoelectronic device comprising:a plurality of light-emitting diodes comprising semiconductor elements; and
current-limiting components, each said component being series-connected with a corresponding one of the plurality of semiconductor elements and having a resistance which increases along with current intensity flowing through the corresponding series-connected current-limiting component and semiconductor element.

US Pat. No. 10,141,368

SEMICONDUCTOR DEVICE

HAMAMATSU PHOTONICS K.K.,...

1. A semiconductor device comprising: a semiconductor substrate that has a first surface and a second surface opposite to each other and in which a through hole to extend from the first surface to the second surface is formed;a first wiring that is provided on the first surface and has a portion located above a first opening of the through hole on the a first surface side;
an insulating layer that is provided on an inner surface of the through hole and the second surface and is continuous through a second opening of the through hole on the a second surface side; and
a second wiring that is provided on a surface of the insulating layer and is electrically connected to the first wiring in an opening of the insulating layer on the first surface side, wherein the through hole is a vertical hole, and on both sides of a center line of the through hole in a plane including the center line of the through hole, a segment that connects a first point corresponding to an edge of the opening of the insulating layer and a second point corresponding to an edge of the second opening is a first segment, a segment that connects the second point and a third point corresponding to an intersection point between the second opening and the surface of the insulating layer is a second segment, and a segment that connects the third point and the first point is a third segment, a first area of the insulating layer that is located on an inner surface side of the through hole with respect to the first segment is larger than the sum of a second area of the insulating layer that is surrounded by the first segment, the second segment, and the third segment and a third area of the insulating layer that is located on a side opposite the inner surface side of the through hole with respect to the third segment.

US Pat. No. 10,141,367

PHOTOELECTRIC CONVERSION APPARATUS AND PHOTOELECTRIC CONVERSION SYSTEM

CANON KABUSHIKI KAISHA, ...

1. A photoelectric conversion apparatus comprising:a plurality of pixels, each pixel including
a pixel electrode having a first electrode and a second electrode on an upper part of a substrate,
an upper electrode arranged on an upper part of the pixel electrode,
a photoelectric conversion layer arranged between the pixel electrode and the upper electrode,
a first signal output circuit including a first amplification unit having an input node directly connected to the first electrode, and
a second signal output circuit including a second amplification unit having an input node directly connected to the second electrode; and
a control unit configured to supply an electric potential to the second electrode that a potential of the second electrode with respect to signal charges decreases as compared with a potential of the first electrode with respect to signal charges in an electric potential supplied to the first electrode during a first period in which the first signal output circuit outputs a signal.

US Pat. No. 10,141,362

SEMICONDUCTOR DEVICE HAVING PROTECTION LAYER WRAPPING AROUND CONDUCTIVE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising: an image sensor device layer; a first bonding layer over the image sensor device layer; a second bonding layer bonded with the first bonding layer; a substrate over the second bonding layer; and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer, wherein the conductive via comprises: a protection layer peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer, wherein the protection layer covers a sidewall cut formed at an interface between the second bonding layer and the first bonding layer; and a conductive material peripherally enclosed by the protection layer, wherein the protection layer has a protrusion protruding from an outer sidewall of the protection layer and in contact with the first bonding layer and the second bonding layer.

US Pat. No. 10,141,361

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An image sensor comprising:a first semiconductor section including a first semiconductor substrate and a first multi-wiring layer, the first semiconductor substrate including a photodiode, and the first multi-wiring layer including a first insulating interlayer and first and second wirings; and
a second semiconductor section including a second semiconductor substrate and a second multi-wiring layer, the second semiconductor section including at least a part of a signal processing circuit, and the second multi-wiring layer including a second insulating interlayer and third and fourth wirings,
wherein,
the first semiconductor section and the second semiconductor section are bonded together such that the first multi-wiring layer and the second multi-wiring layer face each other,
the first wiring of the first multi-wiring layer directly contacts the third wiring of the second multi-wiring layer in a pixel region including the photodiode, and
the second wiring of the first multi-wiring layer directly contacts the fourth wiring of the second multi-wiring layer in a peripheral region other than the pixel region.

US Pat. No. 10,141,360

ISOLATED GLOBAL SHUTTER PIXEL STORAGE STRUCTURE

OmniVision Technologies, ...

1. An imaging system, comprising:a pixel array of pixel cells, wherein each one of the pixel cells includes:
a photodiode disposed in a semiconductor material to accumulate image charge in response to incident light directed to the photodiode;
a global shutter gate transistor, wherein a portion of the global shutter gate transistor is disposed in the semiconductor material and coupled to the photodiode to selectively deplete the image charge from the photodiode;
a storage transistor, wherein a portion of the storage transistor is disposed in the semiconductor material to store the image charge; and
an optical isolation structure disposed in the semiconductor material proximate to the storage transistor to isolate a sidewall of the storage transistor from stray light and stray charge in the semiconductor material outside of the storage transistor, wherein the optical isolation structure includes a deep trench isolation structure formed in the semiconductor material, wherein the deep trench isolation structure is filled with tungsten, wherein the optical isolation structure further includes a P+ passivation formed over an interior sidewall of the deep trench optical isolation structure between the tungsten and the semiconductor material;
control circuitry coupled to the pixel array to control operation of the pixel array; and
readout circuitry coupled to the pixel array to readout image data from the plurality of pixels.

US Pat. No. 10,141,090

RESIN COMPOSITION, PASTE FOR FORMING A VARISTOR ELEMENT, AND VARISTOR ELEMENT

NAMICS CORPORATION, Niig...

1. A resin composition comprising:(A) an epoxy resin;
(B) a curing agent; and
(C) carbon nanotubes,
wherein the carbon nanotubes contain therein semiconducting single-walled carbon nanotubes in an amount of 70% by weight or more.

US Pat. No. 10,141,087

WIRING HARNESS PRODUCTION MOUNTING

LASELEC, Toulouse (FR)

1. A system for the production of wire harnesses, comprising:at least one cable routing element (200, 21);
at least one display screen (101) for displaying data for assisting with the production of wire harnesses;
at least one attachment surface (103, 400) associated with said at least one display screen, said at least one attachment surface being configured to receive said at least one cable routing element (200, 21); and
a processing unit configured to implement a method for assisting with the production of wire harnesses, the processing unit operatively connected to the at least one display screen (101) and configured to provide the data for assisting with the production of the wire harnesses,
wherein said at least one cable routing element comprises an attachment suction cup that attaches said at least one cable routing element to said at least one attachment surface (103, 400) associated with said at least one display screen.

US Pat. No. 10,141,085

CONDUCTOR JOINT AND CONDUCTOR JOINT COMPONENT

1. A system comprising: a fiber-structured heating element; a copper conductor; and a conductor joint therebetween, wherein dimensions of the fiber-structured heating element being length (L)>>width (W)>>thickness (T), and which heating element comprises carbon fiber strands, wherein the copper conductor is transversely disposed relative to a longitudinal direction (L) of the heating element to form a layered structure in a thickness direction (T), on both opposing sides of the heating element, the copper conductor comprising copper strands separable from each other, wherein the copper strands of the copper conductor, a number and a diameter of which are configured to transfer electric power of more than ten kW, are quantitatively evenly distributed on both opposing sides and corresponding surfaces of the heating element, having a material including carbon fiber strands of the heating element in between, so that on each of said both opposing sides the strands distributed thereto extend along and cover the width (W) of the heating element, the strands on each side of said both opposing sides being further disposed in a planar manner in such a way that the strands lie in one plane, adjacent to each other, and the ends of the strands further extend on each of said both opposing sides, in a width direction (W) of the heating element, beyond the heating element, wherein portions of the ends of the strands extending beyond the heating element overlap each other, and an electric joint is formed between lateral faces of these portions of overlapping strands.

US Pat. No. 10,141,084

ELECTRONIC DEVICE

Cheil Industries, Inc., ...

1. An electronic device, comprising:an anisotropic conductive film, the anisotropic conductive film including an insulating layer and a conductive layer laminated on the insulating layer, the conductive layer containing insulating particles and conductive particles, wherein,
the lowest melt viscosity of the insulating layer is in the range of about 2,000 Pa·s to about 10,000 Pa·s and the lowest melt viscosity of the conductive layer is in the range of about 5,000 to about 50,000 Pa·s, provided that the lowest melt viscosity of the conductive layer is at least about 3,000 Pa·s greater than that of the insulating layer,
the insulating layer is from greater than 1 to about 4 times thicker than the conductive layer,
the insulating layer is formed from a first composition that comprises a first polymer resin, a first radically polymerizable material, and a first radical initiator, wherein the first polymer resin includes one or more of an olefinic resin, a butadiene resin, an acrylonitrile-butadiene copolymer, a carboxyl-terminated acrylonitrile-butadiene copolymer, a polyimide resin, a polyamide resin, a polyester resin, a polyvinyl butyral resin, an ethylene-vinyl acetate copolymer, a styrene-butylene-styrene (SBS) resin, a styrene-ethylene-butylene-styrene (SEBS) resin, an acrylonitrile-butadiene rubbers (NBRs), a urethane resin, a (meth)acrylic resin, or a phenoxy resin, and the first radically polymerizable material includes a first epoxy (meth)acrylate oligomer, the first epoxy (meth)acrylate oligomer being present in an amount of 20 to 40 wt %, based on a total weight of the first composition,
the conductive layer is formed from a second composition that comprises a second polymer resin, a second radically polymerizable material, and a second radical initiator, wherein the second polymer resin includes one or more of an olefinic resin, a butadiene resin, an acrylonitrile-butadiene copolymer, a carboxyl-terminated acrylonitrile-butadiene copolymer, a polyimide resin, a polyamide resin, a polyester resin, a polyvinyl butyral resin, an ethylene-vinyl acetate copolymer, a styrene-butylene-styrene (SBS) resin, a styrene-ethylene-butylene-styrene (SEBS) resin, an acrylonitrile-butadiene rubbers (NBRs), a urethane resin, a (meth)acrylic resin, or a phenoxy resin, and the second radically polymerizable material includes a second epoxy (meth)acrylate oligomer, the second epoxy (meth)acrylate oligomer being present in an amount of 20 to 30 wt %, based on a total weight of the second composition,
a size of the conductive particles is in the range of about 1 to about 30 ?m, the conductive particles being present in an amount of about 1 to about 30% by weight, based on the total weight of the second composition,
a size of the insulating particles is in the range of about 0.1 to about 20 ?m, the insulating particles being present in an amount of about 2 to about 20% by weight, based on the total weight of the second composition.

US Pat. No. 10,141,083

TRANSPARENT CONDUCTIVE FILM COMPOSITE AND TRANSPARENT CONDUCTIVE FILM

INDUSTRIAL TECHNOLOGY RES...

1. A transparent conductive film, consisting of:(a) a metallic material; and
(b) a dispersant,
wherein a weight ratio of the metallic material to the dispersant ranges from 0.14:1 to 20:1,
wherein the metallic material (a) comprises:
(a1) 84-99.99 wt % of metal nanowires; and
(a2) 0.01-16 wt % of micron metal flakes,
wherein a sheet resistance of the transparent conductive film is 10052/or less, and a transparency of the transparent conductive film is 95% or greater.

US Pat. No. 10,141,082

OXIDATION RESISTANT COPPER NANOPARTICLES AND METHOD FOR PRODUCING SAME

KOREA INSTITUTE OF SCIENC...

1. A method for producing copper nanoparticles, comprising the steps of:preparing a first solution by stirring together a solvent, a polymer, and an organic acid, wherein the polymer is selected from the group consisting of polyacetylene, polyaniline, polypyrrole, polythiophene, poly(3,4-ethylenedioxythiophene) and a combination thereof,
wherein the organic acid is selected from the group consisting of erythorbic acid, glucuronolactone, triformin (2,3-diformyloxypropyl formate) and a combination thereof;
producing a second solution by mixing the first solution, a copper precursor, and a first reducing agent;
producing a third solution by mixing a second reducing agent with the second solution for 30 minutes to 5 hours; and
separating and collecting copper nanoparticles from the third solution.

US Pat. No. 10,141,081

PHASE CONTRAST X-RAY IMAGING DEVICE AND PHASE GRATING THEREFOR

Siemens Healthcare GmbH, ...

1. A phase grating for a phase contrast X-ray imaging, the phase grating comprising:a transverse surface to be aligned substantially transversely with respect to a radiation incidence direction, said transverse surface being spanned by an x-axis and a y-axis perpendicular to said x-axis;
a multiplicity of grating webs composed of a basic material and alternately arranged with optically denser interspaces, said grating webs dividing said transverse surface into grating strips that are in each case elongated in a y-direction of said y-axis and that are lined up parallel alongside one another in an x-direction of said x-axis;
at least one of said grating webs extending within said transverse surface across a plurality of said grating strips; and
the phase grating, at each said grating strip along a z-axis that extends perpendicularly to said transverse surface, having a homogeneous total thickness of said basic material that differs between mutually adjacent said grating strips.

US Pat. No. 10,141,080

INSOLUBLE CESIUM GLASS

QSA GLOBAL, INC., Burlin...

1. A cesium-137 gamma radiation source consisting of a mixed metal oxide of cesium-137 and a metal chosen from the group consisting of niobium, tantalum, vanadium and mixtures thereof, in which an insoluble radioactive product is formed, as a mixture, solid solution or ternary compound, by a process of reacting at least one dissolved compound of the at least one metal with a soluble cesium-137 compound followed by forming a solid radioactive component of a gamma radiation source.

US Pat. No. 10,141,079

TARGETRY COUPLED SEPARATIONS

TerraPower, LLC, Bellevu...

1. A method for manufacturing 99Mo radioisotope, the method comprising:providing a source containing a first mass of uranium particles, the uranium particles having an average particle size of from 10% to 200% of a recoil distance of 99Mo in the uranium particles;
enclosing the source in a neutronically-translucent container;
exposing the source to neutrons, thereby reducing the first mass of uranium particles in the source to a second mass of uranium particles less than the first mass and creating at least some atoms of the 99Mo radioisotope;
removing, after exposing the source to neutrons, at least some of the atoms of the 99Mo radioisotope from the source without removing uranium particles from the source;
wherein the removing operation further comprises:
passing an extraction material selected to dissolve the 99Mo radioisotope through the container, thereby contacting the uranium particles with the extraction material; and
wherein the extraction material is supercritical carbon dioxide containing a ligand that dissolves the 99Mo radioisotope and does not dissolve the uranium.

US Pat. No. 10,141,078

LIQUID FUEL NUCLEAR FISSION REACTOR FUEL PIN

TerraPower, LLC, Bellevu...

1. A nuclear fission fuel pin comprising:cladding defining an elongated enclosure, the enclosure having a fission region and a fertile blanket region;
a solution of a first fissile nuclear fission fuel material dissolved in neutronically translucent liquid carrier material, the solution being distributed into the elongated enclosure including into the fission region and into the fertile blanket region; and
a solid phase, undissolved fertile nuclear fission fuel material, in foam form, disposed in the fertile blanket region of the elongated enclosure and in direct physical contact with the solution in the elongated enclosure, the fertile nuclear fission fuel material being transmutable into a second fissile nuclear fission fuel material directly diffusible into the solution.

US Pat. No. 10,141,077

SYSTEM AND METHOD FOR CHARACTERIZATION OF ELECTRICAL PROPERTIES OF THE HEART FROM MEDICAL IMAGES AND BODY SURFACE POTENTIALS

Siemens Healthcare GmbH, ...

1. A method for estimating patient-specific cardiac electrical properties from medical image data and non-invasive electrocardiography measurements of a patient, comprising:generating a patient-specific anatomical heart model and a patient-specific anatomical torso model from medical image data of a patient and an electrical coupling model between the patient-specific anatomical heart model and the patient-specific anatomical torso model;
generating a mechanical activation time map of the heart from a dynamic cardiac image sequence of the patient;
identifying a line of block from the mechanical activation time map; and
estimating spatially varying patient-specific cardiac electrical parameters for the patient by:
simulating cardiac electrophysiology over time at a plurality of nodes in the patient-specific anatomical heart model using a computational cardiac electrophysiology model, and
adjusting at least one cardiac electrical parameter of the computational cardiac electrophysiology model based on the mechanical activation time map, the non-invasive electrocardiography measurements of the patient, the simulated cardiac electrophysiology, and the line of block identified from the mechanical activation time map.

US Pat. No. 10,141,076

PROGRAMMING AND VIRTUAL REALITY REPRESENTATION OF STIMULATION PARAMETER GROUPS

Nuvectra Corporation, Pl...

1. A medical system, comprising:one or more implantable medical devices configured to deliver a medical therapy to a patient; and
a portable electronic device on which a touch-sensitive user interface is implemented, wherein the user interface is configured to provide a visual representation of the medical therapy through a hierarchy that includes:
a lower level representation of the medical therapy that corresponds to a stimulation program, wherein the stimulation program can run on the one or more implantable medical devices to cause the one or more implantable medical devices to stimulate a body tissue of the patient as part of the medical therapy, and wherein the stimulation program includes a plurality of configurable stimulation parameters;
a middle level representation of the medical therapy that is at least one hierarchical level above the lower level representation of the medical therapy, wherein the middle level representation of the medical therapy corresponds to a stimulation program-set that includes a plurality of different stimulation programs; and
an upper level representation of the medical therapy that is at least one hierarchical level above the middle level representation of the medical therapy, wherein the upper level representation of the medical therapy corresponds to a scrollable collection of stimulation program-sets, wherein the stimulation program-sets are represented by a plurality of digital cards, respectively;
wherein the portable electronic device provide visual representation and tracking of the medical therapy at least in part via the hierarchy.

US Pat. No. 10,141,075

PREDICTING AND MITIGATING RISK OF ECTASIA AND OPTIMIZING THERAPEUTIC OUTCOMES

THE CLEVELAND CLINIC FOUN...

1. A system for evaluating an eye of a patient, comprising:a modeling component configured to determine a representation of at least the cornea of the eye from a three-dimensional structural image of the eye and at least one biomechanical property of the eye;
a feature extractor configured to extract a plurality of features from the model of at least the cornea of the eye;
a user interface configured to accept input from a clinician defining an objective function as a function of at least one parameter for the eye after the therapeutic procedure;
an ectasia evaluation component configured to calculate at least one parameter associated with the risk of ectasia in the eye from the extracted plurality of features and the objective function, the calculated at least one parameter including a variable in a therapeutic procedure representing a surgical parameter that can be varied by a clinician in the therapeutic procedure; and
a system output configured to provide the calculated at least one parameter to one of a treatment system and a user.

US Pat. No. 10,141,074

VASCULAR FLOW ASSESSMENT

Cath Works Ltd., (IL)

1. A vascular assessment apparatus comprising:a processor communicatively coupled to a medical imaging device; and
a memory storing non-transitory computer-readable instructions, which when executed, cause the processor to:
receive a set of medical images of a coronary vessel tree of a subject from the medical imaging device, wherein a first of the medical images of the set was acquired from a first viewing angle, and a second of the images of the set was acquired from a second viewing angle;
perform image analysis to identify vascular features within and corresponding among the set of medical images;
combine geometrical information for the corresponding vascular features to produce a stenotic model of the coronary vessel tree, the stenotic model having measurements of the coronary vessel tree at locations along vessels of the coronary vessel tree;
determine a flow characteristic from the stenotic model;
calculate a first index indicative of vascular function, based, at least in part, on the flow characteristic from the stenotic model;
receive another medical image of the coronary vessel tree of the subject;
analyze the other medical image to identify vascular features within the other medical image that correspond to vascular features that are represented in the stenotic model or provided in at least some of the medical images from the set;
modify the geometrical information for the corresponding vascular features in the stenotic model to create an updated stenotic model from at least some of the identified vascular features within the other medical image;
determine a modified flow characteristic from the updated stenotic model; and
calculate a second index indicative of vascular function, based, at least in part, on the modified flow characteristic in the updated stenotic model.

US Pat. No. 10,141,073

SYSTEMS AND METHODS FOR CONTROLLING ACQUISITION OF SENSOR INFORMATION

Elwha LLC, Bellevue, WA ...

1. A system, comprising:a network of remote non-contact physiological sensors separately deployed throughout a room, the remote non-contact physiological sensors including at least one microphone and at least one image-capture device configured to measure a physiological parameter of an individual;
a motion sensor configured to measure movement of the individual relative to the network of remote non-contact physiological sensors;
a light sensor configured to measure lighting in the room;
a computing device operably connected to the network of remote non-contact physiological sensors, the motion sensor, and the light sensor, the computing device including a processor programmed to
query the motion sensor to initiate measurement of movement of the individual relative to the network of remote non-contact physiological sensors;
query the light sensor to initiate measurement of lighting in the room;
receive a set of motion sensor values from the motion sensor, the set of motion sensor values representative of the movement of the individual relative to the network of remote non-contact physiological sensors;
receive a set of light sensor values from the light sensor, the set of light sensor values representative of the lighting in the room;
query at least one of the remote non-contact physiological sensors to remotely measure the physiological parameter of the individual to acquire a set of physiological sensor values if the set of motion sensor values and the set of light sensor values meets or exceeds a threshold value; and
re-query at least one of the motion sensor or the light sensor if the set of motion sensor values or the set of light sensor values fails to meet or exceed the threshold value.

US Pat. No. 10,141,072

EFFICIENT ENCODER BASED ON MODIFIED RU ALGORITHM

SK Hynix Inc., Gyeonggi-...

1. A memory system, comprising:a memory device; and
a controller coupled with the memory device, wherein the memory device includes a memory component, and the controller is configured to:
receive information data from the memory component;
perform a first stage of encoding using a sparse circulant calculation circuit to generate first stage data;
perform a second stage of encoding to generate first portion parity information and second portion parity information;
wherein the second portion parity information is generated based at least in part on the first portion parity information and the first stage data, and wherein the second portion parity information is generated by an XOR calculation of the first portion parity information and the first stage data;
output the second portion parity information; and
generate information including the second portion parity information, which contributes to improving the speed of the memory device.

US Pat. No. 10,141,071

PREDICTIVE COUNT FAIL BYTE (CFBYTE) FOR NON-VOLATILE MEMORY

Intel Corporation, Santa...

1. An apparatus comprising:logic circuitry, coupled to non-volatile memory of a solid state drive (SSD), the logic circuitry to determine a number of memory cells of the non-volatile memory that are allowed to fail program verification in a current program loop,
wherein the logic circuitry is to determine the number of memory cells based at least on information from a previous program loop, wherein the information from the previous program loop includes a number of bytes below a program verify voltage for a level N of a multi-level programming of the non-volatile memory, wherein the previous program loop is to be executed prior to the current program loop, wherein the logic circuitry is to cause inhibition of one or more program verification pulses to be issued in the current program loop and any subsequent program loop based on a determination that the number of memory cells of the non-volatile memory has reached a threshold value, wherein the threshold value is lower than an Error Correction Code (ECC) limit of the non-volatile memory.

US Pat. No. 10,141,070

SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. A sense-amplifier test device comprising:a drive signal generator configured to generate a test voltage applying signal for supplying a ground voltage to a pull-up power-supply line of a sense-amplifier driver, based on a test mode signal; and
wherein the sense-amplifier driver is configured to supply the ground voltage to the pull-up power-supply line, based on the test voltage applying signal.

US Pat. No. 10,141,069

NEURAL NETWORK AND ELECTRONIC DEVICE INCLUDING ARTIFICIAL NEURAL ARRAY

Semiconductor Energy Labo...

1. An electronic device comprising:a first circuit comprising a first transistor, a second transistor, and a capacitor;
a second circuit comprising a third transistor; and
first to sixth wirings,
wherein:
a gate of the first transistor is electrically connected to the first wiring,
a first terminal of the first transistor is electrically connected to the second wiring,
a second terminal of the first transistor is electrically connected to a gate of the second transistor,
a first terminal of the capacitor is electrically connected to the third wiring,
a second terminal of the capacitor is electrically connected to the gate of the second transistor,
a first terminal of the second transistor is electrically connected to the fourth wiring,
a gate of the third transistor is electrically connected to the third wiring,
a first terminal of the third transistor is electrically connected to the fifth wiring,
a second terminal of the second transistor is electrically connected to the sixth wiring, and
a second terminal of the third transistor is electrically connected to the sixth wiring.

US Pat. No. 10,141,068

MAGNETIC ELEMENT, SKYRMION MEMORY, SKYRMION MEMORY-DEVICE, SOLID-STATE ELECTRONIC DEVICE, DATA-STORAGE DEVICE, DATA PROCESSING AND COMMUNICATION DEVICE

RIKEN, Saitama (JP)

1. A magnetic element capable of generating and erasing a skyrmion, comprising:a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material;
a current path provided at least partially enclosing an end region including an end portion of the magnet, the current path being provided on one surface of the magnet; and
a skyrmion sensor that detects the generation and erasing of the skyrmion, wherein
with Wm being a width of the magnet and hm being a height of the magnet, a size of the magnet, with the skyrmion of a diameter ? being generated, is such that 2?>Wm>?/2 and 2?>hm>?/2.

US Pat. No. 10,141,067

MAGNETIC MEMORY DEVICE

Toshiba Memory Corporatio...

1. A magnetic memory device, comprising:a magnetic body, the magnetic body including
a first extending region, a first length of the first extending region along a first direction being longer than a second length of the first extending region along a second direction crossing the first direction, the first extending region including a first end portion extending in the first direction and a second end portion extending in the first direction and separated from the first end portion in the second direction,
a second extending region, a third length of the second extending region along the first direction being longer than a fourth length of the second extending region along a third direction crossing the first direction, the second extending region including a third end portion extending in the first direction and a fourth end portion extending in the first direction and separated from the third end portion in the third direction, and
a first connecting region provided between the first end portion and the third end portion, a length of the first connection region along the first direction being longer than a length of the first connection region along the second direction and longer than a length of the first connection region along the third direction, the first connecting region connecting the first end portion with the third end portion,
a position of the second end portion along a fourth direction being different from a position of the fourth end portion along the fourth direction, the fourth direction being perpendicular to the first direction and the second direction, and
the first extending region including a first magnetic domain and a first other region provided around the first magnetic domain in a first state.

US Pat. No. 10,141,066

MEMORY DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A memory device, comprising:a memory block including a plurality of cell strings;
a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and
a control circuit configured to control the peripheral circuit for programming the selected memory cells in response to a program command, and to increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed.

US Pat. No. 10,141,065

ROW REDUNDANCY WITH DISTRIBUTED SECTORS

Cypress Semiconductor Cor...

1. A semiconductor device comprising:an embedded flash memory comprising a memory bank that includes multiple physical sectors, wherein each physical sector comprises a plurality of erase sectors, and wherein:
multiple portions of an additional erase sector are respectively distributed among the multiple physical sectors; and
the multiple portions of the additional erase sector are configured as a row-redundancy sector for the memory bank.

US Pat. No. 10,141,064

PREVENTION OF NEIGHBORING PLANE DISTURB IN NON-VOLATILE MEMORY

SanDisk Technologies LLC,...

1. An apparatus, comprising:a first group of memory cells connected to a first word line;
a second group of memory cells connected to a second word line, the second word line different than the first word line;
a voltage supply connected to a node to supply a first voltage level to both of the first word line and the second word line;
a control circuit connected to the first and second groups and to the voltage supply, the control circuit configured to perform one or more memory operations concurrently on the first group and the second group such that both the first word line and the second word line concurrently receive the first voltage level from the node; and
a first unidirectional circuit element through which the first word line is directly connected to the node when receiving the first voltage level, the first unidirectional circuit element configured to allow current to flow from the node to the first word line and to prevent current from flowing from the first word line to the second word line; and
a second unidirectional circuit element through which the second word line is directly connected to the node when receiving the first voltage level, the second unidirectional circuit element configured to allow current to flow from the node to the second word line and to prevent current from flowing from the second word line to the first word line.

US Pat. No. 10,141,063

MEMORY CONTROLLER, MEMORY DEVICE AND METHOD OF OPERATING

TAIWAN SEMICONDUCTOR MANU...

1. A device, comprising:a memory cell array having memory cells arranged in rows and columns;
a word line driver configured to be coupled to the memory cells of a memory device via corresponding word lines;
a bit line driver configured to be coupled to the memory cells via corresponding bit lines;
source lines coupled to the memory cells; and
a number of source lines equals a number of rows in the memory cell array;
wherein, in a programming operation,
the bit line driver is configured to supply a selected bit line voltage to a selected bit line among the bit lines and supply an unselected bit line voltage to an unselected bit line among the bit lines, the selected bit line coupled to a memory cell in the memory cells, and selected to be written to among the memory cells, the unselected bit line coupled to a memory cell unselected to be written to among the memory cells,
the word line driver is configured to supply a selected word line voltage to a selected word line among the word lines and supply an unselected word line voltage, different from the selected word line voltage, to an unselected word line among the word lines, the selected word line coupled to the selected memory cell, the unselected word line coupled to the unselected memory cell, wherein
the unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a lower threshold voltage of the unselected memory cell.

US Pat. No. 10,141,062

SENSING CIRCUIT WITH SAMPLED REFERENCE CURRENT OR VOLTAGE FOR FLASH MEMORY SYSTEM

SILICON STORAGE TECHNOLOG...

1. A method of operating a non-volatile memory device comprising a sensing circuit coupled to a selected memory cell, the method comprising:closing one or more switches to cause the device to operate in a first mode, wherein during the first mode a reference element draws a current and the current is mirrored by a current mirror to generate a reference current, the current mirror comprising a first transistor and a second transistor; and
opening the one or more switches to cause the device to operate in a second mode, wherein during the second mode the reference element is detached from the second transistor of the current mirror and the second transistor of the current mirror continues providing the reference current and the reference current is compared against a current drawn by a selected memory cell to determine a value stored in the selected memory cell.

US Pat. No. 10,141,061

MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory system comprising:a semiconductor memory capable of reading data from memory cells on a page basis; and
a controller which controls the semiconductor memory,
wherein the semiconductor memory is configured to execute a first reading operation, a second reading operation when the first reading operation fails, and a third reading operation when the second reading operation fails,
wherein in the first reading operation, a first voltage is applied to a selected word line of the semiconductor memory,
in the second reading operation, a second voltage and a third voltage are sequentially applied to the selected word line, and the second voltage is different from the first voltage, and
in the third reading operation, a fourth voltage and a fifth voltage are sequentially applied to the selected word line, and the fourth voltage is different from the first voltage, the second voltage, and the third voltage, and
wherein an absolute value of a difference between the second voltage and the fourth voltage is different from an absolute value of a difference between the third voltage and the fifth voltage.

US Pat. No. 10,141,060

MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory system comprising:a semiconductor memory including a memory cell; and
a controller configured to control the semiconductor memory and capable of creating second data based on first data read from the memory cell,
wherein upon receiving a physical erase request for the first data held in the memory cell from an external device, the controller transmits one of an erase instruction and a write instruction for the second data to the semiconductor memory.

US Pat. No. 10,141,059

FAILURE DETECTION CIRCUITRY FOR ADDRESS DECODER FOR A DATA STORAGE DEVICE

Taiwan Semiconductor Manu...

1. A data storage device, comprising:a memory array including a plurality of memory cells that are arranged in a plurality of rows and a plurality of columns to form an array, a first group of columns and a second group of columns from among the plurality of columns being logically grouped into a first memory sub-array and a second memory sub-array, respectively, from among a plurality of memory sub-arrays; and
a row decoder configured to:
decode a row address within an address to access a memory cell from among the plurality of memory cells to provide a plurality of wordlines (WLs) corresponding to the row address, a first WL and a second WL from among the plurality of WLs being associated with a first row from among the plurality of rows and corresponding to the first memory sub-array and the second memory sub-array, respectively, and
indicate a failure in the decoding of the row address when the first WL differs from the second WL.

US Pat. No. 10,141,058

MULTI-CHIP NON-VOLATILE SEMICONDUCTOR MEMORY PACKAGE INCLUDING HEATER AND SENSOR ELEMENTS

1. A non-volatile memory system, comprising:a chip package, the chip package comprising
a first non-volatile semiconductor memory device;
a heater element that provides heat to the first non-volatile semiconductor memory device; and
a thermal sensing element, the thermal sensing element has a parameter that changes in response to changes in temperature; and
a heat control circuit coupled to provide a heat drive signal; wherein
the heater element includes a first terminal coupled to receive the heat drive signal, and
the heat control circuit is coupled to receive a heat enable signal and a temperature range lower limit detect signal, the heat control circuit provides a low impedance path between a power supply potential and the first terminal of the heater element in response to the heat enable signal being in an enable logic level and the temperature range lower limit detect signal indicating the temperature of the thermal sensing element is below a temperature range lower value.

US Pat. No. 10,141,057

ERASING METHOD OF SINGLE-GATE NON-VOLATILE MEMORY

Yield Microelectronics Co...

1. An erasing method of a single-gate non-volatile memory, wherein said single-gate non-volatile memory comprises a P-type semiconductor substrate, a transistor and a capacitor structure, wherein said transistor and said capacitor structure disposed in said semiconductor substrate, and wherein said transistor includes a first electrically-conductive gate and multiple first ion-doped regions that are separately disposed at both sides of said first electrically-conductive gate and respectively function as the source and the drain, and wherein said capacitor structure includes a second electrically-conductive gate and a second ion-doped region, wherein said first electrically-conductive gate and said second electrically-conductive gate electrically interconnected to form a single floating gate, and wherein said erasing method is characterized in:respectively applying a substrate voltage Vsub, a source voltage Vs and a drain voltage Vd to said P-type semiconductor substrate, said source and said drain, and not applying a voltage to said first ion-doped regions, wherein said voltages meet the following conditions:
Vd>Vs?Vsub, and
Vsub is grounded.

US Pat. No. 10,141,056

MEMORIES INCLUDING MULTIPLE ARRAYS OF NON-VOLATILE MEMORY CELLS SELECTIVELY CONNECTED TO SENSE CIRCUITRY USING DIFFERENT NUMBERS OF DATA LINES

Micron Technology, Inc., ...

1. A memory, comprising:a first array of non-volatile memory cells;
a second array of non-volatile memory cells;
a first plurality of data lines comprising a first number of data lines, each data line of the first plurality of data lines selectively connected to a respective subset of non-volatile memory cells of the first array of non-volatile memory cells;
a second plurality of data lines comprising a second number of data lines, less than the first number of data lines, each data line of the second plurality of data lines selectively connected to a respective subset of non-volatile memory cells of the second array of non-volatile memory cells; and
sense circuitry selectively connected to the first plurality of data lines and selectively connected to the second plurality of data lines;
wherein the memory is configured, when reading non-volatile memory cells of the second array of non-volatile memory cells, to connect the sense circuitry to each data line of the second plurality of data lines; and
wherein the memory is configured, when reading non-volatile memory cells of the first array of non-volatile memory cells, to connect the sense circuitry to a number of data lines of the first plurality of data lines equal to the second number.

US Pat. No. 10,141,055

METHODS AND APPARATUS FOR PATTERN MATCHING USING REDUNDANT MEMORY ELEMENTS

Micron Technology, Inc., ...

1. A memory, comprising:an array of memory cells comprising a plurality of cell pairs, each cell pair of the plurality of call pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory, and
control circuitry configured to apply a same pair of voltages to control gates of each cell pair of the plurality of cell pairs when checking for a match of the stored bit of data of the plurality of cell pairs and data value of the particular bit position of the pattern, wherein voltage levels of the same pair of voltages are responsive to the data value of the particular bit position of the pattern;
wherein the plurality of cell pairs comprises a first cell pair coupled to a first data line, a second cell pair coupled to a second data line, and a third cell pair coupled to a third data line.

US Pat. No. 10,141,054

SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first circuit including a flip-flop; and
a second circuit comprising a first transistor, a second transistor, and a third transistor,
wherein:
the first circuit is configured to retain data while a power supply voltage is supplied,
the second circuit is configured to retain the data while the power supply voltage is not supplied,
each of the first transistor and the second transistor comprises a channel formation region including an oxide semiconductor,
the third transistor comprises a channel formation region including silicon,
a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor,
a gate of the third transistor is electrically connected to one of a source and a drain of the second transistor, and
the first circuit is electrically connected to one of a source and a drain of the third transistor and the other of the source and the drain of the first transistor.

US Pat. No. 10,141,053

METHOD FOR DRIVING A SEMICONDUCTOR DEVICE INCLUDING DATA MIGRATION BETWEEN A VOLATILE MEMORY AND A NONVOLATILE MEMORY FOR POWER-SAVING

Semiconductor Energy Labo...

1. A method for driving a semiconductor device including a volatile memory and a nonvolatile memory, the method comprising the steps of:operating the volatile memory with a normal mode;
monitoring access requirements to the volatile memory and detecting an access frequency of the volatile memory;
comparing a used space of the volatile memory and an available space of the nonvolatile memory when the access frequency of the volatile memory is smaller than a first set value;
forwarding data stored in the volatile memory to the nonvolatile memory when the used space of the volatile memory is smaller than the available space of the nonvolatile memory;
changing the volatile memory from the normal mode to a stop mode;
monitoring access requirements to the nonvolatile memory and measuring a data transferring speed of the nonvolatile memory;
returning the volatile memory from the stop mode to the normal mode when the data transferring speed of the nonvolatile memory is higher than a second set value; and
forwarding part of data in the volatile memory to the nonvolatile memory when an available space of the volatile memory is smaller than a third set value,
wherein the third set value is configured to be changed depending on temperature of the volatile memory;
wherein the normal mode is a mode supplying a first power supply voltage to the volatile memory, and
wherein the stop mode is a mode not supplying any power supply voltage to the volatile memory.

US Pat. No. 10,141,052

METHODS, ARTICLES, AND DEVICES FOR PULSE ADJUSTMENT TO PROGRAM A MEMORY CELL

MICRON TECHNOLOGY, INC., ...

1. A method of operating a memory device, comprising:determining a set of pulse parameters for a programming electrical pulse, the set of pulse parameters including a fall time of the programming electrical pulse; and
applying, to a memory cell of a memory array, the programming electrical pulse based at least in part on the fall time of the programming electrical pulse, wherein the programming electrical pulse comprises a voltage pulse.

US Pat. No. 10,141,051

MEMORY DEVICE ARCHITECTURE

MICRON TECHNOLOGY, INC., ...

1. A system, comprising:a memory device comprising:
an array of memory cells occupying a footprint; and
a plurality of word line drivers and digit line drivers in a circuit level positioned below the array of memory cells, wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points distributed within the footprint.

US Pat. No. 10,141,049

NONVOLATILE MEMORY SYSTEM STORING SYSTEM DATA IN MARGINAL WORD LINES

SANDISK TECHNOLOGIES LLC,...

1. A non-volatile storage system, comprising:a first non-volatile memory structure that includes a plurality of word line units that each include one word line and a plurality of non-volatile storage elements, the word line units are arranged in blocks, a block is a unit of erase, the plurality of word line units include a first word line unit in a first block and a second word line unit in the first block; and
one or more control circuits in communication with the first non-volatile memory structure, the one or more control circuits are configured to write host data to the first word line unit, the one or more control circuits are configured to not write host data to the second word line unit, the one or more control circuits are configured to write system data associated with host data to the second word line unit by programming the system data to non-volatile storage elements connected to a word line determined to have failed.

US Pat. No. 10,141,048

STACK CAPACITOR FOR NEURAL NETWORK

International Business Ma...

1. A method of forming a memory cell comprising:providing a first field effect transistor (FET) comprising a first functional gate stack that contacts a portion of a first semiconductor material portion and first source/drain regions located on opposite sides of the first functional gate stack in a first active region of a substrate, a second FET comprising a second functional gate stack that contacts a portion of a second semiconductor material portion and second source/drain regions located on opposite sides of the second functional gate stack in a second active region of the substrate, and a third FET comprising a third functional gate stack that contacts a portion of a third semiconductor material portion and third source/drain regions located on opposite sides of the third functional gate stack in a third active region of the substrate;
forming first source/drain contact structures overlying and contacting the first source/drain regions, a second source/drain contact structure overlying and contacting one of the second source/drain regions, a third source/drain contact structure overlying and contacting one of the third source/drain regions, and a source/drain interconnect structure connecting the other of the second source/drain regions and the other of the third source/drain regions, wherein the first, the second and the third source/drain contact structures and the source/drain interconnect structure are laterally surrounded by an interlevel dielectric (ILD) layer located over the substrate;
forming a capacitor bottom electrode structure overlying and contacting the source/drain interconnect structure and a functional gate of the first functional gate stack, wherein the capacitor bottom electrode structure is laterally surrounded by an insulator layer located over the ILD layer; and
forming a stack capacitor array overlying the capacitor bottom electrode contact structure and comprising:
a plurality of bottom electrodes, with each of the plurality of bottom electrodes having a horizontal portion contacting the capacitor bottom electrode contact structure and vertical portions extending upwards from the horizontal portion,
an anchor structure connecting the vertical portions of the plurality of bottom electrodes together,
a capacitor dielectric present on physically exposed surfaces of the plurality of bottom electrodes and the anchor structure, and
a top electrode present on the capacitor dielectric.

US Pat. No. 10,141,047

STATIC RANDOM ACCESS MEMORY

1. A static random access memory (SRAM) comprising:a plurality of memory cells each having a pair of cross-coupled inverters, a first of the inverters being supplied by first and second power supply rails and a second of the inverters being supplied by third and fourth supply rails, an input of the second inverter being coupled to a first bit line via a first transistor; and
a power supply circuit adapted to apply, during a read phase of one of the memory cells, a first voltage difference across the first and second power supply rails and a second voltage difference across the third and fourth power supply rails of said memory cell, the second voltage difference being greater than the first voltage difference.

US Pat. No. 10,141,046

MEMORY DEVICE COMPRISING AN ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. A memory cell comprising:an electrically floating body region comprising a first conductivity type selected from p-type conductivity type and n-type conductivity type;
a source line region comprising a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type, said source line region in physical contact with said electrically floating body region;
a drain region comprising said second conductivity type in physical contact with said electrically floating body region and spaced apart from said source line region;
a first charge injector region, wherein said first charge injector region comprises said second conductivity type and is in physical contact with said electrically floating body region and spaced apart from said source line region and said drain region;
a second charge injector region, wherein said second charge injector region comprises said second conductivity type and is in physical contact with said electrically floating body region and spaced apart from said source line region, said drain region, and said first charge injector region;
a gate positioned in between said source line region and said drain region, the same gate being positioned between said first charge injector region and said second charge injector region; and
wherein said electrically floating body region is configured to have more than one stable state through an application of a bias on said first and second charge injector regions.

US Pat. No. 10,141,045

DUAL RAIL DEVICE WITH POWER DETECTOR FOR CONTROLLING POWER TO FIRST AND SECOND POWER DOMAINS

Taiwan Semiconductor Manu...

1. A dual rail device comprising:a first power domain circuit coupled to a first power supply through a first header control switch;
a second power domain circuit coupled to a second power supply, wherein the first and second power supplies have different steady-state voltage levels and wherein the first power domain circuit is interfaced to the second power domain circuit; and
a power detector circuit for providing a control signal for controlling the first header control switch responsive to detection of a voltage level of the second power supply.

US Pat. No. 10,141,044

MEMORY INTERFACE CIRCUIT HAVING SIGNAL DETECTOR FOR DETECTING CLOCK SIGNAL

MEDIATEK INC., Hsin-Chu ...

1. A memory interface circuit, comprising:a plurality of receivers, for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively; and
a signal detector, for detecting whether the memory interface circuit receives the clock signal or not, without using a clock enable signal from a pin of a memory module, to generate a detection result to enable or disable the plurality of receivers;
wherein the signal detector detects a swing of the clock signal to generate the detection result and when the swing of the clock signal is greater than a first threshold, the signal detector starts to generate the detection result to enable the plurality of receivers; and when the swing of the clock signal is less than a second threshold, the signal detector starts to generate the detection result to disable the plurality of receivers.

US Pat. No. 10,141,043

DRAM AND METHOD FOR MANAGING POWER THEREOF

NANYA TECHNOLOGY CORPORAT...

1. A dynamic random access memory (DRAM), comprising:a plurality of banks, each of the banks including a plurality of subarrays;
a power source; and
a control device configured to derive information on a quantity of operated subarrays among the subarrays, and determine how much electrical energy to provide based on the information,
wherein the power source provides the resultant amount of electrical energy based on the determination from the control device;
wherein the control device determines to provide a first amount of electrical energy when a quantity ratio of the operated subarrays is greater than or equal to a highest endpoint of a ratio range, and provide a second amount of electrical energy less than the first amount of electrical energy when the quantity ratio of the operated subarrays is less than or equal to a lowest endpoint of the ratio range.

US Pat. No. 10,141,042

METHOD AND APPARATUS FOR PRECHARGE AND REFRESH CONTROL

Micron Technology, Inc., ...

1. An apparatus, comprising:a command decoder configured to receive a first command and a second command, and further configured to provide a first control signal and a second control signal responsive to the first command and the second command, respectively;
an address decoder configured to receive at least a portion of address signals and further configured to activate one bank selection signal of a plurality of bank selection signals corresponding to a plurality of banks, responsive to the at least a portion of address signals; and
a plurality of control logic circuits, wherein each control logic circuit of the plurality of control logic circuits is configured to receive the first control signal, the second control signal and a corresponding bank selection signal of the plurality of bank selection signals,
wherein the first command is indicative of performing a first memory operation for a first bank of the plurality of banks identified by the at least a portion of address signals, and the second command is indicative of performing the first memory operation and a second memory operation different from the first memory operation for the first bank of the plurality of banks, and
wherein a control logic circuit of the plurality of control logic circuits corresponding to the first bank is configured to provide a bank row activation signal to the first bank responsive to the bank selection signal corresponding to the first bank and the second control signal in the second memory operation.

US Pat. No. 10,141,041

SYSTEMS AND METHODS FOR MAINTAINING REFRESH OPERATIONS OF MEMORY BANKS USING A SHARED

Micron Technology, Inc., ...

1. A memory device comprising:a plurality of memory banks, wherein each memory bank of the plurality of memory banks comprises a plurality of rows, wherein each row of the plurality of rows comprises a row address;
a counter configured to store and increment a first row address of a first row of a first set of memory banks of the plurality of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode; and
circuitry configured to block incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.

US Pat. No. 10,141,040

CELL PERFORMANCE RECOVERY USING CYCLING TECHNIQUES

MICRON TECHNOLOGY, INC., ...

1. A method, comprising:applying a plurality of access pulses to a memory cell in an operation state;
determining a sampling frequency based at least in part on a delay between at least two access pulses of the plurality of access pulses;
monitoring a remnant polarization of the memory cell based at least in part on the sampling frequency, wherein the remnant polarization corresponds to an amount of charge capable of being stored by the memory cell; and
determining a first peak magnitude in the remnant polarization of the memory cell as a function of a number of the applied plurality of access pulses based at least in part on monitoring the remnant polarization of the memory cell.

US Pat. No. 10,141,038

COMPUTER SYSTEM AND MEMORY DEVICE

Toshiba Memory Corporatio...

1. A computer system comprising:a memory device including a memory cell array, the memory device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array;
a processor configured to receive a first data from the memory device, the first data read from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data read from the selected region by the second read operation.

US Pat. No. 10,141,037

MAGNETIC MEMORY DEVICE

Kabushiki Kaisha Toshiba,...

1. A magnetic memory device, comprising:a conductive layer including a first portion, a second portion, and a third portion between the first portion and the second portion;
a first magnetic layer separated from the third portion in a second direction crossing a first direction, the first direction being from the first portion toward the second portion;
a second magnetic layer provided between the third portion and the first magnetic layer, the second magnetic layer being electrically connected with the third portion;
a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, the first nonmagnetic layer being curved; and
a controller electrically connected to the first portion and the second portion,
the controller implementing
a first operation of supplying a first current to the conductive layer from the first portion toward the second portion, and
a second operation of supplying a second current to the conductive layer from the second portion toward the first portion.

US Pat. No. 10,141,036

SEMICONDUCTOR MEMORY DEVICE AND READING METHOD THEREOF

Winbond Electronics Corp....

1. A reading method of a semiconductor storage device, comprising steps of:pre-charging a selected bit line; and
reading a voltage or a current of the pre-charged selected bit line through a sense node,
wherein the step of pre-charging the selected bit line comprises steps of:
pre-charging the sense node to a first voltage;
for a bit line node coupled between the sense node and a bit line, pre-charging the bit line node to a first clamp voltage based on the first voltage of the sense node;
pre-charging the bit line node to a second clamp voltage greater than the first clamp voltage after pre-charging the selected bit line by the first clamp voltage; and
pre-charging the sense node to a second voltage greater than the first voltage.

US Pat. No. 10,141,035

MEMORY CELL WITH A READ SELECTION TRANSISTOR AND A PROGRAM SELECTION TRANSISTOR

UNITED MICROELECTRONICS C...

1. A memory cell comprising:a read selection transistor having a first terminal coupled to a bit line, a second terminal, and a control terminal coupled to a read word line;
a program selection transistor having a first terminal directly coupled to the second terminal of the read selection transistor, a second terminal coupled to a high voltage control line, and a control terminal coupled to a program word line; and
an anti-fuse capacitor having a first terminal directly coupled to the second terminal of the read selection transistor, and a second terminal coupled to a low voltage control line.

US Pat. No. 10,141,034

MEMORY APPARATUS WITH NON-VOLATILE TWO-TERMINAL MEMORY AND EXPANDED, HIGH-SPEED BUS

CROSSBAR, INC., Santa Cl...

1. An electronic memory, comprising:a memory cell array comprising multiple banks of non-volatile, two-terminal memory;
a set of mode registers to facilitate programming the electronic memory according to a programmed operation setting of a set of defined operation settings;
logic circuitry configured to implement operations on a subset of the multiple banks of the memory cell array according to the programmed operation setting and in response to a memory command received from a host device;
a bus interface facilitating communication with the host device, further comprising:
a command and address input comprising greater than ten signal pins for receipt of the memory command and of a physical memory address for the memory command, and
a bidirectional data bus for receiving new data to write to the physical memory address in response to the memory operation being a memory write, or for receiving stored data from the physical memory address and outputting the stored data in response to the memory operation being a memory read, the bidirectional data bus comprising greater than eight signal pins; and
a command and address decoder configured to receive greater than twenty bits of command and address information from the memory command, identify from the greater than twenty bits of command and address information a memory operation specified by the memory command, a target bank of the multiple banks of non-volatile, two-terminal memory and the physical memory address within the target bank.

US Pat. No. 10,141,033

MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS

Intel Corporation, Santa...

1. A system comprising:a system memory; and
a processor coupled to the system memory, the processor comprising:
a cache to store a plurality of cache lines;
a plurality of general purpose registers;
a plurality of 128-bit packed data registers, including a first destination 128-bit packed data register, and a second destination 128-bit packed data register;
an instruction fetch unit to fetch instructions, including a load from memory instruction;
a decode unit to decode the load from memory instruction, the load from memory instruction indicating a starting memory location in a memory, the starting memory location associated with data to be loaded, and the load from memory instruction having a first field to specify the first destination 128-bit packed data register, and having a second field to specify the second destination 128-bit packed data register; and
a memory access unit coupled to the decode unit, and coupled to the plurality of 128-bit packed data registers, the memory access unit to perform a load from memory operation in response to the decoded load from memory instruction, the load from memory operation to:
load a first 128-bit data from the indicated starting memory location, and store the loaded first 128-bit data in the first destination 128-bit packed data register; and
load a second 128-bit data, which is adjacent to the first 128-bit data, and store the loaded second 128-bit data in the second destination 128-bit packed data register.

US Pat. No. 10,141,032

DOUBLE-BARRIER VACUUM SEAL FOR SEALED SYSTEM

Western Digital Technolog...

1. A system assembly comprising:a hermetically-sealed enclosure;
a first sealing member at an interface of the enclosure and an external environment;
a second sealing member spaced from the first sealing member; and
a vacuum source, operating in a space between the first sealing member and the second sealing member, thereby generating a lower pressure in the space than in the enclosure and than in the external environment.

US Pat. No. 10,141,030

UNLOADING MECHANISM ASSEMBLY

Wistron Corporation, New...

1. An unloading mechanism assembly, adapted to unload an optical disk drive from a housing of an electronic device, the unloading mechanism assembly comprising:a guiding component, disposed at a side of the optical disk drive along a first direction and having a first position limiting slot, wherein the first position limiting slot extends along a second direction, and the first direction is perpendicular to the second direction;
a push rod, disposed in parallel with the guiding component along the first direction;
a driving module, coupled between the guiding component and the push rod and comprising a driving rod movably disposed through the first position limiting slot along a third direction respectively perpendicular to the first direction and the second direction, wherein the push rod is adapted to drive the driving module to pivotally rotate with respect to the guiding component, so as to drive the driving rod of the driving module to enter or to exit the first position limiting slot; and
a stroke limiting pedestal, disposed between the guiding component and the driving module, fixed to the housing, and having a first surface and a second surface opposite to each other and a position limiting groove disposed through the first surface and the second surface, wherein the first surface faces toward the guiding component and an opening direction of the position limiting groove is parallel to the third direction.

US Pat. No. 10,141,029

SECURING APPARATUS FOR DATA STORAGE DEVICE

HONG FU JIN PRECISION IND...

7. A securing apparatus, configured to mount a data storage device in an enclosure, comprising:an enclosure configured to receive a data storage device and comprising a panel;
a shielding assembly secured to the panel and comprising a frame and a rotating plate rotatably mounted to the frame;
a sliding pole slidably mounted to the frame and defining a plurality of latching slots; and
a pressing module slidably mounted to the panel;
wherein the frame defines an aperture for the data storage device to pass through; the rotating plate comprises a plurality of first hooks; and the sliding pole is slidable relative to the frame to engage the first hooks in the latching slots, and the rotating plate is secured to the frame and shields the aperture, preventing the data storage device from being taken out of the aperture, the pressing module is slidable relative to the panel to push the sliding pole, and for disengaging first hooks from the latching slots, and the rotating plate is rotatable relative to the frame to open the aperture, the pressing module comprises an operation pole, and the operation pole comprises two sliding posts; the panel defines two sliding slots; the two sliding posts are slidably received in the two sliding slots, the pressing module further comprises a bracket secured to the panel and a sliding member slidably mounted to the bracket, and the operation pole is slidable relative to the frame to slide the sliding member, the bracket defines a plurality of sliding slots, the sliding member comprises two sliding shafts, and the two sliding shafts are slidably inserted in the two sliding slots.

US Pat. No. 10,141,028

SYSTEM AND METHOD FOR PLAY WHILE RECORDING PROCESSING

Intel Corporation, Santa...

1. At least one non-transitory computer-readable storage media comprising instructions stored thereon that, when executed by a system, cause the system to:receive an indication of one of an MP3 file format, a G2 file format, a WAV file format, or an ACWMA file format;
receive an audio file in a first file format;
encode a first portion of the audio file in the one of the MP3 file format, the G2 file format, the WAV file format, or the ACWMA file format based on the indication;
store the encoded first portion of the audio file as a stored first portion within an encoded audio file on a first computer-readable storage medium accessible to the system, the audio file representing media;
encode a second portion of the audio file in the one of the MP3 file format, the G2 file format, the WAV file format, or the ACWMA file format based on the indication;
store the encoded second portion of the audio file as a stored second portion within the encoded audio file on the first computer-readable storage medium accessible to the system, the second portion of the audio file being different than the first portion; and
render the media represented by the encoded second portion of the audio file while the first portion of the audio file is being encoded and stored, wherein the render involves a read of the encoded second portion of the audio file from the encoded audio file on the first computer-readable storage medium.

US Pat. No. 10,141,026

ACCESS CONTROL FOR HARDWARE RESOURCES

International Business Ma...

1. A method comprising:receiving an access request for a configuration module in a Field Programmable Gate Array (FPGA), the configuration module being operable to configure functionality of the FPGA based on configuration information stored thereon;
determining whether the access request conforms to a specification specifying access control related to the configuration module; and
in response to determining that the access request conforms to the specification, transmitting the access request to the configuration module for access of the configuration information.

US Pat. No. 10,141,024

HIERARCHICAL AND REDUCED INDEX STRUCTURES FOR MULTIMEDIA FILES

DIVX, LLC, San Diego, CA...

1. A method of decoding a media file for playing back by a playback device, comprising:a media file comprising a plurality of groups of frames, wherein each group of frames comprises a set of encoded video frames; and
a hierarchical index comprising a top-level index indexing references to the plurality of group of frames, wherein each reference to a frame in the plurality of frames comprises a seek point referencing a location from which an individual frame of encoded video can be retrieved;
requesting the hierarchical index;
receiving a user request;
selecting a seek point from the hierarchical index based on the user request;
requesting at least one encoded video frame using the selected seek point from the selected subset of seek points by calculating an offset between the selected seek point and the nearest group of frames;
selecting a group of frames from the plurality of groups of frames using the hierarchical index and the calculated offset; and
decoding at least one encoded video frame in the selected group of frames.

US Pat. No. 10,141,023

METHOD AND SYSTEM FOR MULTIMEDIA SUMMARY GENERATION

INDUSTRIAL TECHNOLOGY RES...

1. A method for multimedia summary generation adapted to a multimedia system, wherein the method comprises following steps:capturing a multimedia information from a multimedia source, wherein the multimedia information comprises at least a video clip or a picture;
processing the video clip or the picture of the multimedia information according to a predetermined condition to generate a multimedia summary candidate, wherein the predetermined condition comprises at least a system setting value, an overlapping time, a maximum video clip length, a minimum video clip length, a people capturing ratio or a combination thereof, for determining a start point and an end point of the video clip, wherein the predetermined condition further comprises screening video clips and pictures similar to the video clip and the picture from the multimedia information by using a clustering algorithm to form a multimedia summary candidate group;
generating a multimedia summary list by checking whether a threshold is predetermined;
outputting the multimedia summary candidate to join the multimedia summary list when no threshold is predetermined,
checking whether the multimedia summary candidate meets the predetermined threshold when the threshold is predetermined;
joining the multimedia summary candidate to the multimedia summary list when the multimedia summary candidate meets the predetermined threshold;
ignoring the multimedia summary candidate when the multimedia summary candidate does not meet the predetermined threshold;
combining the multimedia summary candidate in the multimedia summary candidate list to generate a multimedia summary; and
sending message of the video clips and pictures similar to the video clip and the picture from the multimedia information to generate an Internet spread website via the Internet after forming the multimedia summary candidate group,
wherein the predetermined threshold is realizable at least by a number of users selecting the multimedia summary candidate, a ratio of the number of users selecting the multimedia summary candidate or a combination thereof.

US Pat. No. 10,141,022

METHOD AND ELECTRONIC DEVICE FOR GENERATING MULTIPLE POINT OF VIEW VIDEO

HTC Corporation, Taoyuan...

1. A method of generating a multiple point of view (MPOV) video applicable to an electronic device comprising a processor, the method comprising:obtaining, by the electronic device, a plurality of media contents;
identifying, by the processor of the electronic device, from the plurality of media contents, a first media content and a second media content as relevant media contents related to a same event based on each metadata that corresponds to each of the media contents, wherein the metadata comprises a time information, an audio information and a location information;
transmitting, by the electronic device, a set of relevance criteria to other electronic device for identifying, by the other electronic device, a third media content from another media contents captured by an image capturing component of the other electronic device as one of the relevant media contents relating to the same event as the first media content and the second media content;
receiving, by the electronic device, the third media content identified by the other electronic device from the other electronic device for generating the MPOV video; and
generating, by the processor of the electronic, the MPOV video by combining a partial period from each of the first, second and third media contents into one frame as a highlight of the event, and simultaneously displaying the first, second and third media contents in different sections of the frame.

US Pat. No. 10,140,345

SYSTEM, METHOD, AND COMPUTER PROGRAM FOR IDENTIFYING SIGNIFICANT RECORDS

AMDOCS DEVELOPMENT LIMITE...

1. A computer program product embodied on a non-transitory computer readable medium, comprising computer code for:storing, in a database, a plurality of records for a plurality of customers, each record of the plurality of records storing an event sequence associated with customer interactions that includes a plurality of events of different event types;
receiving, via an input device, an indication of one or more aspects associated with one or more of the records;
identifying, based on the indication, a subset of the records having the one or more aspects, the subset including at least two of the records;
processing, utilizing at least one processor, events included in the subset of the records by:
identifying, for each record in the subset of records, an anchor event included therein, the anchor event being an event for which a decision of significance is to be tested,
identifying, for each record in the subset of records, a first subset of events included therein occurring before the anchor event identified for the record and a second subset of events included therein occurring after the anchor event identified for the record,
determining a target measurement value from one of the records in the subset of the records,
calculating a mean measurement value the records in the subset of the records according to the target measurement value, the mean measurement value calculated using the equation:

wherein i is the record identifier of the record,
wherein Xio is a measurement value for the record,
calculating a variance measurement value based on the mean measurement value, the variance measurement value calculated using the equation:

comparing, utilizing the at least one processor, the records in the subset of the records, utilizing the mean measurement value and the variance measurement value, to identify a particular event in a particular record of the subset of the records that causes the particular record to deviate from other records in the subset of the records; and
displaying, via at least one display, an indication of the particular event of the particular record of the subset of the records that causes the particular record to deviate from other records in the subset of the records.

US Pat. No. 10,140,344

EXTRACT METADATA FROM DATASETS TO MINE DATA FOR INSIGHTS

Microsoft Technology Lice...

1. A system comprising:one or more processors; and
one or more computer-readable storage devices having stored thereon instructions that are executable by the one or more processors to configure the computer system to analyze data, including instructions that are executable to configure the computer system to perform at least the following:
obtaining a graph, the graph comprising set of a plurality of data entities and relationships, wherein each data entity represents a node in the graph and each relationship represents an edge connecting a node in the graph to another node in the graph;
identifying a plurality of composite collections of data entities and relationships, each of the plurality of composite collections comprising a subset of the set of a plurality of data entities and relationships, each of the plurality of composite collections comprising a sub-tree of the graph which includes nodes and edges of the graph within a particular relationship scope, and each composite collection of the plurality of composite collections being identified by traversing the graph, beginning at a particular entity for each composite collection and including each entity connected through a connecting relationship associated with the particular relationship scope, and analyzing the associated connecting relationships; and
providing one or more of the plurality of composite collections of data entities and relationships to a data mining engine, each composite collection of data entities and relationships being provided individually, each as a separate unit to the data mining engine.

US Pat. No. 10,140,343

SYSTEM AND METHOD OF REDUCING DATA IN A STORAGE SYSTEM

CA, Inc., New York, NY (...

1. A method of reducing data in a storage system, comprising:accessing the data stored in the storage system by a processor;
parsing the data accessed from the storage system into subsets of data using the processor, the parsing comprising categorizing the subsets of data, in response to a query, into a plurality of categories including a category to determine relevancy, wherein data in the relevancy category is generated by correlating identified patterns to generate a relationship sequence and to correlate each relationship in the relationship sequence, and wherein the relationships are used to determine the relevancy of the data;
for each of the categorized subsets of data, using the processor to
detect the subsets of data to be purged based on a threshold condition having been satisfied, and ranking the subsets of data for which the threshold condition has been satisfied, and
detect the subsets of data to be masked based on a policy having been satisfied, and ranking the subsets of data for which the policy has been satisfied;
individually marking each of the subsets of data based on the ranking for purging using the processor when the threshold condition has been satisfied, and individually marking each of the subsets of data for masking based on the ranking using the processor when the policy has been satisfied;
identifying pattern changes using the processor between each of the subsets of data prior to a first purging and the marked subsets of data for purging or between each of the subsets of data prior to a first masking and the marked subsets of data for masking; and
processing each of the subsets of data, prior to the first purging and prior to the first masking, for permanent changes by reducing the amount of data using the processor when pattern changes satisfying a predetermined criteria have been identified, and providing the permanently changed subsets of data with the reduced amount of data to the storage system for storage.

US Pat. No. 10,140,340

STANDARDIZING ATTRIBUTES AND ENTITIES IN A SOCIAL NETWORKING SYSTEM

Microsoft Technology Lice...

1. A process comprising:receiving into a computer processor data extracted from profiles on a social networking system, the data relating to a personal attribute;
writing the data to a database when a first personal attribute exceeds a first threshold;
generating a plurality of pairings, each of the plurality of pairings comprising the first personal attribute and one of a plurality of other similar personal attributes;
for at least one pairing of the plurality of pairings:
determining a degree of similarity between the first personal attribute and the other similar personal attribute in the at least one pairing;
in response to the degree of similarity between the first personal attribute and the other similar personal attribute exceeding a second threshold, providing a plurality of users an opportunity to provide input regarding the degree of similarity of the at least one pairing;
receiving into the computer processor input from the plurality of users, the input indicating an agreement or disagreement by each of the users regarding the degree of similarity of the at least one pairing; and
writing the at least one pairing to the database based on the input from the plurality of users;
wherein the determination of the degree of similarity between the first personal attribute and the other similar personal attribute is based on all of the following:
a distribution over a plurality of industries of the first personal attribute and the other similar personal attribute;
a co-occurrence within a profile in the social networking service of the first personal attribute and the other similar personal attribute;
a skill within a profile of a connection within the social networking system;
a difference in characters and positions of characters of the first personal attribute and the other similar personal attribute;
a ratio of a number of profiles including the first personal attribute and a number of profiles including the other similar personal attribute; and
a first webpage containing the first personal attribute and a second webpage containing the other similar personal attribute, wherein the first webpage is linked to the second webpage.

US Pat. No. 10,140,337

FUZZY JOIN KEY

SAP SE, Walldorf (DE)

1. A system comprising:a first memory storing a first database table and a second database table;
a second memory storing processor-executable process steps; and
a processor to execute the processor-executable process steps to cause the system to:
identify a first one or more columns of the first database table as associated with a first entity and a first one or more columns of the second database table as associated with the first entity;
map the data of each row of the first one or more columns of the first database table to respective first rows of a predetermined schema associated with the entity;
map the data of each row of the first one or more columns of the second database table to respective second rows of the predetermined schema associated with the entity;
determine matching ones of the first rows and the second rows;
based on the matching ones of the first rows and the second rows, identify the first one or more columns of the first database table and the first one or more columns of the second database table as a JOIN key between the first database table and the second database table; and
execute a JOIN of the first database table and the second database table by applying the JOIN key.

US Pat. No. 10,140,336

ACCURACY TESTING OF QUERY OPTIMIZERS

Pivotal Software, Inc., ...

1. A computer-implemented method comprising:obtaining, by a testing system comprising one or more computers, a plurality of query plans generated by a plurality of respective query optimizers, each query plan of the plurality of query plans being alternative query plans for computing results for a query;
computing, for each query plan of the plurality of query plans, a respective estimated cost to compute results for the query using the query plan;
executing each query plan of the plurality of query plans to compute a respective actual cost of executing the query plan;
performing a clustering algorithm on the plurality of query plans using the respective estimated cost and respective actual cost to classify each query plan as belonging to a cluster or as being an outlier;
computing, for each query optimizer from query plans generated by the optimizer, a respective rank correlation score, including:
selecting, by the testing system, no more than N different query plans generated by the query optimizer, including selecting at least one outlier according to the clustering algorithm;
generating, by the testing system, (i) a first ranking of query plans generated by the query optimizer, ordered according to the respective actual cost of each query plan generated by the query optimizer, and (ii) a second ranking of query plans generated by the query optimizer, ordered according to the respective estimated cost of each query plan generated by the query optimizer;
computing, by the testing system based at least on the first ranking of the different query plans and the second ranking of the different query plans, a first rank correlation score indicative of an accuracy of the query optimizer in estimating costs associated with executing query plans, wherein determining the first rank correlation score comprises performing a pair-wise comparison of each pair of plans that were incorrectly ranked in the second ranking, including iteratively:
computing a weight of each particular plan, the weight representing a comparison of an actual cost of a highest-ranked plan to an actual cost for the particular plan,
weighting a distance between each pair of incorrectly ranked plans according to a first weight for a first plan and a second weight for a second plan, and
adding the weighted distance for the pair of plans to the first rank correlation score for the query optimizer;
ranking the plurality of query optimizers according to the respective rank correlation score computed for each of the plurality of query optimizers; and
improving performance of a database system, including selecting, by the testing system, as a preferred query optimizer for generating query plans for the database system, a highest-ranked query optimizer according to the ranking of the plurality of query optimizers.

US Pat. No. 10,140,335

CALCULATION SCENARIOS WITH EXTENDED SEMANTIC NODES

SAP SE, Walldorf (DE)

1. A method for implementation by one or more data processors forming at least part of a computer system, the method comprising:receiving, by a database server, a higher-level language query associated with a calculation scenario that defines a data flow model that includes a plurality of calculation nodes, each calculation node defining one or more operations to execute on the database server, at least one of the calculation nodes being a semantic node specifying an operation involving aggregating previously aggregated database elements, the higher-level language query producing erroneous results when aggregating previously aggregated database elements;
modifying, by the database server, the higher-level programming language query using the semantic node, the modified higher-level programming language query producing accurate results;
modifying, by the database server, the calculation scenario based on the modified higher-level programming language query;
instantiating, by the database server, the modified calculation scenario;
executing, by the database server, the operations defined by the calculation nodes of the modified calculation scenario to result in at least one result set; and
providing, by the database server to the application server, the at least one result set.

US Pat. No. 10,140,334

MULTI STAGE AGGREGATION USING DIGEST ORDER AFTER A FIRST STAGE OF AGGREGATION

International Business Ma...

1. A method of processing a database query including an aggregation operation and table grouping columns by a plurality of processing nodes each including a processor, comprising:generating, at each processing node, a digest for each of a plurality of database object elements of that processing node based on a first mathematical hash function applied to the table grouping columns that provides unordered digests across the database object elements, wherein generating a digest includes:
generating a hash value for a first column of the table grouping columns of a database object element; and
utilizing the generated hash value in the first mathematical hash function and applying the first mathematical hash function to a second column of the table grouping columns of the database object element to produce the digest value for that database object element;
mapping, at each processing node, the plurality of database object elements of that processing node into a plurality of groups within a hash table based on a second mathematical hash function applied to a corresponding digest, wherein the second mathematical hash function produces a value different than the digest to identify a group location and preserve order of the digests within the hash table, and wherein locations within the hash table for the groups are ordered based on the order of corresponding digests to arrange the database object elements in the hash table in digest order;
extracting, at each processing node, the database object elements of that processing node sequentially from the plurality of groups in the hash table in digest order;
performing, at each processing node, the aggregation operation on the database object elements of that processing node in digest order to produce aggregation information;
transferring the database object elements and aggregation information in digest order between the plurality of processing nodes, wherein the database object elements within a same group and including a same digest are transferred to a same processing node;
applying, at each processing node, a merge sort to the transferred database object elements in digest order and aggregating the sorted database object elements with a same digest; and
producing resulting data for the database query grouped by the database table grouping columns based on the aggregated sorted database object elements.

US Pat. No. 10,140,333

TRUSTED QUERY SYSTEM AND METHOD

Dassault Systemes, Veliz...

1. A method for performing queries on a search engine, based on input from a user, the method comprising:retrieving database entries from one or more relational databases;
flattening the one or more relational databases with a plurality of the database entries;
indexing the plurality of flattened database entries to form a full-text search engine index;
prompting the user to enter an input;
continuously monitoring the user input;
each time an input is entered by the user, processing the user input by:
computing a set of non-null partial queries in response to the input entered by the user, the non-null partial queries each being both valid on the one or more relational databases and having matching, instantiated records on the one or more relational databases thereby always resulting in non-null responses;
associating a structured item to each non-null partial query;
allowing the user to select one of the structured items;
if the user selects one of the structured items, replacing the user input by the nonnull partial query associated to the selected structured item;
when the user validates the input, executing the input as a query; and
providing documents to the user corresponding to the executed query.

US Pat. No. 10,140,332

METHOD AND SYSTEM FOR DATA CACHE HANDLING

KING.COM LTD., St. Julia...

1. A method implemented in a server, said server configured to support a computer implemented game playable on respective user devices in communication with said server, said method comprising:receiving a request from one of said user devices for one or more records which provide information to said computer implemented game played on the user device;
retrieving any of said one or more records associated with said computer implemented game from a first data store storing a first subset of data if said one or more records is in said first subset of data;
retrieving any of said one or more records associated with said computer implemented game from a second data store storing a second subset of data if said one or more records is in said second subset of data and has not been retrieved from said first data store; and
retrieving any of said one of more records associated with said computer implemented game from a third data store storing said data if said one or more records are not in said first and second subsets of data,
wherein each of said records associated with said computer implemented game of said first subset of data are deleted from said first data store upon expiry of a first set time period since said each record of said first subset of data were stored in said first data store,
wherein each of said records of said second subset of data are deleted from said second data store upon expiry of a second set time period since said each record of said second subset of data were stored in said second data store,
wherein the first time period and the second time period are of different lengths,
wherein the first time period is correlated to at least one of:
a play length of the computer game; and
frequency of user interaction with said computer implemented game.

US Pat. No. 10,140,331

CONDITIONAL COMMIT FOR DATA IN A DATABASE

Matrixx Software, Inc., ...

1. A database, comprising:an interface to receive a first set of information from the database; and
a hardware processor to:
read, via a first process, a first portion of the first set of information without a first read latch occurring during the read in the database, wherein the first portion comprises a first database initial value of a first database entry;
start a first calculation using the first portion of the first set of information;
after the reading of the first set of information is performed, read, via a second process, the first portion and a second portion of the first set of information without a second read latch occurring during the read in the database, wherein the second portion comprises a second database initial value of a second database entry;
update, via the second process, the first set of information to a second set of information in the database, wherein updating is based at least in part on the first database initial value of the first database entry and the second database initial value of the second database entry, wherein updating comprises updating the first database initial value of the first database entry to a first updated value and updating the second database initial value of the second database entry to a second updated value;
after the updating of the first set of information, read, via the first process, the second updated value of the second database entry; and
after the reading of the second updated value of the second database entry, calculate, for the first process, a second set of information update using the first database initial value and the second updated value;
update, via the first process, the second set of information in the database based at least in part on the second set of information update and based at least in part on one or more conditions, wherein the one or more conditions limit changes allowable to the first set of information from the database that occurred after receiving the first set of information from the database.

US Pat. No. 10,140,330

DATA CONSISTENCY MAINTENANCE FOR SEQUENTIAL REQUESTS

International Business Ma...

1. A method comprising:responsive to receiving, from a client device, a write request for a data entry stored on a first storage device:
(i) writing, by one or more processors, the data entry to the first storage device; and
(ii) generating, by the one or more processors, a first identifier associated with the data entry stored on the first storage device;
sending, by the one or more processors, the first identifier to the client device;
in response to receiving a read request for the data entry from the client device, retrieving, by the one or more processors, the data entry from a second storage device, wherein the read request includes the first identifier;
retrieving, by the one or more processors, a second identifier from the second storage device, wherein the second identifier is associated with the data entry stored on the second storage device; and
in response to the first identifier and the second identifier not matching, updating, by the one or more processors, the data entry stored on the second storage device with the data entry stored on the first storage device.

US Pat. No. 10,140,326

PAGED INVERTED INDEX

SAP SE, Walldorf (DE)

1. A system, comprising:one or more memories;
an in-memory database management system coupled to the one or more memories and configured to:
store a paged inverted index as a plurality of pages comprising:
a first data structure,
wherein the first data structure stores a plurality of value identifiers and a plurality of offsets, and
wherein a value identifier of the plurality of value identifiers corresponds to an offset in the plurality of offsets, and
a second data structure,
wherein the second data structure stores a plurality of row positions,
wherein a row position in the plurality of row positions is at a location in the second data structure that corresponds to the offset stored in the first data structure, and
wherein the row position identifies a row position in a database table that stores data associated with the value identifier; and
an execution engine configured to:
execute on a processor coupled to the one or more memories;
access the paged inverted index; and
determine the row position in the database table that stores the data associated with the value identifier.

US Pat. No. 10,140,324

PROCESSING SPATIOTEMPORAL DATA RECORDS

CRFS Limited, Cambridge ...

1. A computing device-implemented method of processing a primary data record comprising location data, time data and measurement data, a spatial tree index comprising spatial tree nodes linked by pointers, each spatial tree node corresponding to a given spatial region and further including a pointer to a respective time tree index, and a plurality of time tree indexes, each time tree index corresponding to a respective spatial tree node and comprising time tree nodes linked by pointers, wherein each time tree node corresponds to a given time period, the method comprising:writing the primary data record to a primary data table;
determining whether a spatial tree leaf node exists which corresponds to the spatial region that includes the location data;
on a negative determination, generating a spatial tree leaf node which corresponds to the spatial region that includes the location data, and creating or updating spatial tree nodes connecting the spatial tree leaf node to a spatial tree root node;
for the spatial tree nodes which correspond to each region that includes the location data, updating the respective time tree index by:
determining whether a time tree leaf node exists which corresponds to the time period that includes the time data;
on a negative determination, generating the time tree leaf node which corresponds to the time period that includes the time data, and creating or updating time tree nodes connecting the time tree leaf node to a time tree root node; and
updating the time tree leaf node to include a pointer to the primary data record,
wherein the spatial tree index is a quad tree index, such that the spatial tree root node corresponds to an overall spatial region and each higher level of the spatial tree index includes 4n?1 nth level spatial tree nodes, each of the nth level spatial tree nodes corresponding to a spatial sub-region formed by dividing the overall spatial region into 4n?1 equal sized parts, in which n is equal to a number of connections between the spatial tree root node and an nth level spatial tree node plus one.

US Pat. No. 10,140,323

DATA MODEL INDEXING FOR MODEL QUERIES

Microsoft Technology Lice...

1. A system, comprising:one or more processors; and
one or more hardware storage devices having stored thereon computer-executable instructions that are executable by the one or more processors to cause the computer system to:
identify a plurality of logical data models that each corresponds to a physical data model, wherein each given logical data model of the plurality of logical data models includes a logical data model index corresponding to the given logical data model that is configured to index a plurality of queries and at least partial query results corresponding to each of the plurality of queries, the indexed queries comprising queries issued to the given logical data model, and wherein each logical data model of the plurality of logical data models includes a different semantic mapping set that maps at least one logical data model entity to at least one entity of the physical data model;
receive a model query that identifies a particular logical data model of the plurality of logical data models; and
in response to the received model query, access the logical data model index corresponding to the particular logical data model to determine whether results of the model query have been previously returned.

US Pat. No. 10,140,321

PRESERVING PRIVACY IN NATURAL LANGAUGE DATABASES

NUANCE COMMUNICATIONS, IN...

1. A method comprising:sanitizing sensitive information found in a transcription from a first speaker, to yield a clean transcription comprising sanitized text and non-sanitized text, wherein a first feature vector associated with the non-sanitized text in the transcription identifies the first speaker;
generating a mean feature vector by taking a mean of the first feature vector for the transcription of the first speaker and a second feature vector associated with a second document and which identifies a second speaker, wherein the first speaker and the second speaker are different speakers; and
replacing, via a processor of a computing device, the first feature vector associated with the non-sanitized text with the mean feature vector to anonymize the non-sanitized text.

US Pat. No. 10,140,320

SYSTEMS, METHODS, AND MEDIA FOR GENERATING ANALYTICAL DATA

SDL Inc., Wakefield, MA ...

1. A method for utilizing content rich analytical data, comprising:obtaining informational content via multiple channels including at least one of RSS feeds, news feeds, web content aggregators, web engines, social networking medias, search engines, online ad engines, banner engines, online news groups, and forums;
storing the informational content in a Darwin Information Typing Architecture database in a native extensible markup language format, the stored informational content including at least one of interactive objects, media files, hotspots, and extensible markup language cross-references;
capturing an audit trail during a user session;
grouping a subset of correlated actions within the audit trail as a transaction by:
capturing an opening action performed by an end user on one or more publishing servers using a client device associated with the end user, the client device communicatively coupled with the one or more publishing servers via a network, the one or more publishing servers adapted to publish informational content to the end user, the opening action performed by the client device on a document,
determining actual informational content provided to the end user by applying a filter key associated with the informational content,
generating a unique transaction key in response to the captured opening action performed by the client device on the document,
correlating a subsequent XML cross referencing (XREF) action that is performed by the client device to the document opening action via the transaction key, the XML cross referencing action and created EXREF event relative to opening of the document,
evaluating a natural language of informational content of the document opened by the client device, and
generating a natural language preference for the natural language of the document based on the opening action and the correlated cross reference action;
generating content rich analytical data from the audit trail, the content rich analytical data filtered and formatted based on a plurality of preferences that include the generated natural language preference generated from behavior of the end user including opening actions of the end user;
obtaining informational content for the end user from the informational content stored in the database;
translating the obtained informational content according to a language that corresponds to the generated natural language preference of the end user as determined from the content rich analytical data generated from the audit trail;
reformatting the native extensible markup language format of the obtained informational content obtained from the database according to the generated natural language preference of the end user in a format for use by a web browser of the user client device to display the obtained informational content on the client device in a format that is perceivable to the end user; and
providing the translated and formatted informational content to the end user.

US Pat. No. 10,140,319

SYSTEM FOR IDENTIFYING ANOMALIES BY AUTOMATICALLY GENERATING AND ANALYZING A STRUCTURE

Bank of America, Charlot...

1. A system for automatically analyzing a data model and identifying anomalies within the data model, the system comprising:a memory device comprising computer-readable program code;
a communication device; and
a processing device operatively coupled to the memory device and the communication device, wherein the processing device is configured to execute the computer-readable program code to:
based on input received from a graphical user interface, retrieve data comprising a plurality of elements and a plurality of tables, the data retrieved from a database;
identify elements within the plurality of tables as facts or dimensions by analyzing the elements and the plurality of tables based on a data type corresponding to the elements, a column name corresponding to the elements, and one or more constraints corresponding to the elements within the plurality of tables, wherein identifying the elements comprises:
identifying when the elements comprise a qualitative non-numerical data type and identifying the elements as the dimensions, and identifying when the elements have a quantitative numerical type and identifying the elements as the facts;
identifying when the column name of the elements meet a list of terms stored as associated with the facts or the dimensions and identifying the elements as the facts or the dimensions based on the lists of terms; and
identifying when the one or more constraints comprise rules that limit the elements to entries that are the facts or the dimensions based on the rules and identifying the elements as the facts or the dimensions based on the rules;
identify each of the tables associated with the data as either a fact table or a dimension table based on identifying the elements within the tables as the facts or the dimensions, wherein the plurality of tables comprises at least one fact table and at least one dimension table;
determine that a set of elements within a single column of a first dimension table is a primary key for the dimension table by determining that each element of the set is unique to one another;
identify a reference key corresponding to the primary key;
based on identifying the reference key corresponding to the primary key, determine at least one relationship between at least two tables;
generate the data model of the data retrieved from the database;
identify data anomalies from the at least one relationship, wherein data anomalies are ragged hierarchies, many to many relationships, and double counting;
generate a data analysis report comprising:
generating a list of columns of the tables associated with the data model, a list of other tables that share at least one column with the at least one dimension table, one or more lists of data anomalies, and a list of parents and children, wherein a child is a column associated with the reference key and a parent is a column associated with the primary key;
compiling the list of the columns, the list of other tables, the one or more lists of data anomalies, and the list of parents and children; and
present the data analysis report to a user.

US Pat. No. 10,140,316

SYSTEM AND METHOD FOR SEARCHING, WRITING, EDITING, AND PUBLISHING WAVEFORM SHAPE INFORMATION

1. A system for searching, writing, editing, and publishing waveform shape information, the system comprising:a processor; and
a memory configured to store instructions executable by the processor, comprising:
a shape code value generator for providing a shape code value from a search term, the shape code value defining a wave shape by a plurality of breakpoints, each break point comprising a pair of coordinates and an interpolation value, the pair of coordinates defining the position of the break point and the interpolation value defining the path from a break point to a succeeding break point; and
a shape data file generator for generating a shape data file from the shape code value and for publishing the shape data file;
whereby waveform signals are provided from the shape data file by a waveform signal generator.

US Pat. No. 10,140,315

IDENTIFYING VISUAL PORTIONS OF VISUAL MEDIA FILES RESPONSIVE TO VISUAL PORTIONS OF MEDIA FILES SUBMITTED AS SEARCH QUERIES

Shutterstock, Inc., New ...

1. A computer-implemented method for identifying visual portions of visual media files that are responsive to at least one visual media input file submitted as a search query, the method comprising:cropping at least a visual portion of each of a plurality of visual media files from a collection of media files;
generating a data vector for each cropped visual portion for each of the plurality of visual media files;
determining a visual similarity between the data vector for each cropped visual portion of each of the plurality of visual media files and a reference data vector representative of at least one reference visual media file associated with at least one known object; and
when the visual similarity between the data vector for the cropped visual portion of one of the plurality of visual media files and the reference data vector exceeds a similarity threshold value, associating metadata for the at least one known object with the cropped visual portion of one of the plurality of visual media files and indexing the cropped visual portion of the one of the plurality of visual media files with the associated metadata in an index;
comparing each of the cropped visual portions of the plurality of visual media files to one another to identify at least two cropped visual portions that when compared have a visual similarity score that exceeds another similarity threshold value, and removing at least one of the at least two cropped visual portions from the index when the compared at least two cropped visual portions have a visual similarity score that exceed the another similarity threshold value;
receiving from a user a search query, for the collection of media files, comprising at least one visual media input file;
analyzing the index of visual portions of the plurality of visual media files from the collection of media files to identify at least one responsive visual media file from the collection that comprises a visual portion associated with a visual similarity score, to the at least one visual media input file, which exceeds a similarity threshold value;
generating an input data vector for the at least one visual media input file;
performing a dot product between the input data vector for the at least one visual media input file with the data vector for each cropped visual portion for each of the plurality of visual media files to generate a dot product similarity score for each cropped visual portion for each of the plurality of visual media files;
identifying a data vector for at least one responsive visual media file having a dot product similarity score exceeding a dot product similarity threshold value as being similar to the at least one visual media input file; and
providing, in response to the search query, an identifier of the at least one responsive visual media file from the collection of media files for display as responsive to the search query.

US Pat. No. 10,140,314

PREVIEWS FOR CONTEXTUAL SEARCHES

Adobe Systems Incorporate...

1. In a digital media environment to facilitate creation of content using one or more computing devices, a method comprising:outputting, via a user interface for a digital media application, an image panel displaying image search results having candidate images for insertion in an image frame placed in a document exposed for editing via an editing panel of the user interface, wherein the image search results contain images matching at least one of image frame size or image frame shape;
detecting input to select a particular image within an arrangement of candidate images displayed in the image panel;
responsive to detection of the input, generating a preview image of the document having the particular image inserted into the image frame; and
displaying the preview image in the user interface as a preview that replaces a view of the document exposed for editing in the editing panel as long as the input to select the particular image is maintained.

US Pat. No. 10,140,313

PARALLEL PROCESSING OF LARGE DATA FILES ON DISTRIBUTED FILE SYSTEMS WITH DYNAMIC WORKLOAD BALANCING

INTERNATIONAL BUSINESS MA...

1. A computer program product for parallel processing of files on a distributed file system, the computer program product comprising:a computer storage medium containing computer executable program code stored thereon, the computer executable program code comprising:
computer executable program code in response to a request to process as input a file stored on a distributed file system, a single coordinator of data scanning and processing services for partitioning the file into a set of predetermined sized blocks;
computer executable program code for assigning one or more blocks in the set of predetermined sized blocks by the single coordinator to a reader in a set of readers;
computer executable program code for recording block assignments by the coordinator to a control table accessible to all readers;
computer executable program code for accessing the control table by the set of readers to search the control table for a row currently assigned to a respective reader;
computer executable program code in response to locating the row currently assigned to the respective reader, for changing a state of the row by the respective reader to “in progress”, and for updating a timestamp associated with the row in the control table;
computer executable program code in response to a determination all blocks currently assigned to the respective reader are exhausted, for scanning the control table by the reader for a set of the blocks available, and for dynamically re-assigning by the reader an available block from another owning reader to the respective reader using a set of predefined heuristics and changing the row owner to the respective reader; and
computer executable program code in response to a determination no rows are available, for completing processing and returning an end of file indication by the respective reader to the single coordinator, wherein
computer executable program code for dynamically re-assigning an available block from another owning reader to the respective reader further comprises:
computer executable program code for locking the control table by a reader, to prevent any other readers from changing state in the control table, wherein
a number of unprocessed blocks, is less than or equal to a number of processing engines;
computer executable program code for fragmenting one or more blocks by subdividing existing unprocessed blocks into several smaller blocks, without changing a current assignment, wherein
the fragmenting causes a reduction in size of each block fragmented and a fragment block less than a current size of each the one or more blocks to create a set of fragmented blocks;
computer executable program code for inserting entries for the set of fragmented blocks in rows inserted into the control table, wherein
each of the inserted entries includes a new identifier, a new block size in bytes and a respective offset from an end of a newly sized original block and wherein the fragmented blocks just created retain a same owner engine as an original block from which the fragment blocks came; and
computer executable program code for unlocking the control table.

US Pat. No. 10,140,312

LOW LATENCY DISTRIBUTED STORAGE SERVICE

Amazon Technologies, Inc....

1. A distributed storage service, comprising:a plurality of computing devices that implement:
a storage subsystem comprising a plurality of storage nodes configured to store data and metadata for a plurality of file systems;
a low latency metadata subsystem comprising one or more low latency servers, wherein a low latency server maintains a metadata cache and a metadata journal for one or more of the plurality of file systems associated with the low latency server; and
an access subsystem comprising a plurality of access nodes, wherein the access nodes are configured to:
receive file system requests for the plurality of file systems; and
for file system requests directed to the file systems associated with the low latency servers that require metadata operations, send metadata requests to the low latency servers associated with respective ones of the one or more file systems;
wherein the one or more low latency servers are configured to:
receive a metadata request for a file system associated with the low latency server from one of the access nodes;
determine one or more write operations according to the metadata request;
write one or more journal entries to the metadata journal for the file system specifying the one or more write operations; and
send a notification indicating results of the metadata request to the respective access node, wherein the one or more write operations specified by the one or more journal entries are committed in the storage subsystem subsequent to sending the notification.

US Pat. No. 10,140,311

SYSTEM AND METHOD OF INTERACTING WITH DATA AT A WIRELESS COMMUNICATION DEVICE

1. A wireless communication device, comprising:a processor;
a display device; and
a memory coupled to the processor, the memory including instructions executable by the processor to perform operations, the operations comprising:
receiving a communication request input, wherein the communication request input identifies an action to be executed with respect to a data file, the action executable by the processor when the processor has access to a set of capabilities, and wherein the communication request input is received when the processor does not have access to the set of capabilities;
generating delayed action metadata associated with the data file in response to the communication request input, wherein the delayed action metadata indicates that the action is to be executed responsive to the processor being connected via a wireless wide area network to a first external resource associated with the set of capabilities within a time period, and wherein the delayed action metadata indicates that the action is to be executed responsive to the processor connecting to a second external resource associated with the set of capabilities after the time period; and
upon detecting that the processor has not connected to the first external resource within the time period, sending a transmission based on the delayed action metadata via the wireless wide area network to the second external resource to execute the action.

US Pat. No. 10,140,310

IDENTIFYING AND UTILIZING SYNCHRONIZED CONTENT

Amazon Technologies, Inc....

1. A system comprising:an audiobook a comprising audio data representing a content item;
an electronic book comprising text data representing the content item; and
a synchronization file for the content item, the synchronization file comprising:
audiobook availability data that identifies first audio portions of the audio data that are available for synchronized output with the text data;
audiobook null data that identifies second audio portions of the audio data that are unavailable for synchronized output with the text data;
electronic book availability data that identifies first text portions of the text data that are available for synchronized output with the audio data; and
electronic book null data that identifies second text portions of the text data that are unavailable for synchronized output with the audio data; and a user device comprising:
one or more processors;
a speaker configured to output the audio data of the audiobook;
a display operable to display the text data of the electronic book; and
one or more computer-readable media storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
outputting, during a first period of time, a first portion of the content item where the audio data and the text data are synchronized;
at least partly during the first period of time and while the first portion of the content item is output:
identifying, using the synchronization file, a second portion of the content item where synchronization of the audio data and the text data is less than a predetermined threshold, wherein the second portion of the content item is scheduled to be output during a second period of time that is subsequent the first period of time;
outputting, using at least one of the display or the speaker, an alert indicating that the content item does not have synchronization availability for the second portion of the content item;
presenting, on the display, an input control configured to cause the user device to refrain from presenting the second portion of the content item;
receiving input via the input control; and
based at least in part on receiving the input, refraining from presenting the second portion of the content item.

US Pat. No. 10,140,308

ENHANCING DATA RETRIEVAL PERFORMANCE IN DEDUPLICATION SYSTEMS

INTERNATIONAL BUSINESS MA...

1. A system for processing data, comprising:a data deduplication engine; and
a storage processor in communication with the data deduplication engine, wherein the storage processor is configured for, for data segments previously deduplicated by the data deduplication engine, establishing a supplemental hot-read link, that is associated with and supplements a primary link, for those of the data segments determined to be read on a frequent and recently used basis; wherein the primary link is used to access the data segments during a first read operation and the supplemental hot-read link is used to access those of the data segments determined to be read on the frequent and recently used basis during a subsequent read operation after the determining,
storing in a cache those of the data segments determined to be read on a most recently used (MRU) and most frequently used (MFU) basis; wherein the primary link points to those of the data segments stored on a hard disk or tape storage drive and the supplemental hot-read link points to those of the data segments stored in the cache;
establishing an application-specific table of hash digests to track read activity of the previously deduplicated data segments that are the MRU and the MFU;
configuring the supplemental hot-read link and the primary link in the table of hash digests by storing, for each of the data segments, a hash digest and corresponding primary link and a tally of a usage of reads; wherein the supplemental hot-read link is additionally stored with the hash digest for those of the data segments determined to be the MRU and MFU;
using a threshold to determine which of the data segments are the MRU and the MFU;
preventing an overflow of the cache by adjusting the threshold;
for a read-access request for one of the data segments that are the MRU and the MFU, determining if the supplemental hot-read link is established, wherein:
if the supplemental hot-read link is established, reading the data segment that is the MRU and the MFU associated by the supplemental hot-read link, and
if the supplemental hot-read link is not established, providing an indication that the supplemental hot-read link is not established and alternatively reading from the primary link for the data segment that is the MRU and the MFU;
performing a cleanup operation of the table of hash digests; and
pursuant to establishing the table, if the data segment that is the MRU and the MFU exceeds the threshold, creating the supplemental hot-read link if the supplemental hot-read link is not preexisting, and storing a copy of the data segment that is the MRU and the MFU in the cache without removing the data segment that is the MRU and the MFU in a primary storage location.

US Pat. No. 10,140,305

MULTI-STRUCTURAL, MULTI-LEVEL INFORMATION FORMALIZATION AND STRUCTURING METHOD, AND ASSOCIATED APPARATUS

GENERAL HARMONICS INTERNA...

1. An apparatus for structuring information, the apparatus comprising:a processor; and
a computer-readable storage medium having computer-readable program code portions stored therein that, in response to execution by the processor, cause the apparatus to at least:
analyze an original digital information file to determine an original information quantity and an original information value associated therewith;
apply an initial manipulation process to the original digital information file to form a first resulting digital information file, and apply a subsequent manipulation process to the first resulting digital information file to form a second resulting digital information file, each manipulation process being configured to replace a combination of a plurality of elements of the processed digital information file with a representative element and a first indicia associated with an interrelationship between the representative element and at least one of the plurality of elements in the combination, so as to reduce the information quantity of and to structure the processed digital information file, the representative element being determined to reduce the information value of the processed digital information file by no more than a selected threshold; and
successively apply manipulation processes to the previously resulting digital information file until successive manipulation process applications do not achieve a threshold reduction in the information quantity in the subsequent resulting digital information file over the previously resulting digital information file, the last resulting digital information file thereby having a primary structure with a reduced information quantity with respect to the original information quantity and a resulting information value within the selected threshold of the original information value.

US Pat. No. 10,140,303

APPLICATION AWARE SNAPSHOTS

NexGen Storage, Inc., Lo...

1. A primary data storage system with snapshot capability, the system comprising:an input/output port configured to receive a block command packet that embodies one of a read block command and a write block command and transmitting a block result packet in reply to a block command packet;
a data store system having at least one data store configured to receive and store data in response to a write block command and retrieve and provide data in response to a read block command;
wherein the data store system is adaptable to accommodating at least a first storage element;
a data protection module that is adapted to: (a) identify the first storage element of the data store system, (b) identify a manager of the first storage element and the manager type of the of the identified manager, (c) associate the identified manager and manager type of the identified manager with the first storage element, and (d) initiate an application-consistent snapshot of the first storage element that is in accordance with the manager and manager type, wherein any resulting application-consistent snapshot includes metadata that relates to the relative quality of the snapshot;
wherein the data protection module is adaptable to producing a plurality of snapshots of the first storage element and associating a snapshot quality with each of the plurality of snapshots;
wherein the data protection module comprises a retention module for deleting at least one snapshot of the plurality of snapshots and retaining at least one of the plurality of snapshots based upon the relative snapshots qualities of the plurality of snapshots.

US Pat. No. 10,140,302

AUTONOMIC GENERATION OF DOCUMENT STRUCTURE IN A CONTENT MANAGEMENT SYSTEM

International Business Ma...

1. A computer-implemented method for autonomically generating structure in a document in a content management system, the method comprising the steps of:reading a synchronization rule for the document that specifies structure that does not exist in the document, the synchronization rule governing synchronization between content in the document and metadata related to the content in the document;
specifying in an autonomic structure policy at least one criterion that determines how the portion of the specified structure that does not exist is autonomically generated in the document;
autonomically generating in the document at least a portion of the specified structure that does not exist according to the at least one criterion in the autonomic structure policy; and
autonomically populating with data at least one autonomically-generated structure in the document.

US Pat. No. 10,140,301

DEVICE, METHOD, AND GRAPHICAL USER INTERFACE FOR SELECTING AND USING SETS OF MEDIA PLAYER CONTROLS

Apple Inc., Cupertino, C...

1. A portable electronic device, comprising:a touch-sensitive display, the touch-sensitive display configured to separately display sets of media player controls, including a first predefined set of media player controls and a second predefined set of media player controls;
one or more processors;
memory; and
one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for:
displaying the first predefined set of media player controls while playing a first media item;
detecting gestures on the touch-sensitive display while displaying the first predefined set of media player controls and playing the first media item;
in response to detecting a first gesture, of the detected gestures, on a first media player control in the first predefined set of media player controls, activating the first media player control and controlling playing of the first media item in accordance with activation of the first media player control, wherein the first gesture is a first type of gesture; and,
in response to detecting a second gesture, of the detected gestures, replacing display of the first predefined set of media player controls with display of the second predefined set of media player controls and maintaining playing of the first media item, wherein the second gesture is distinct from the first gesture, the second gesture is a second type of gesture different from the first type of gesture, and the second gesture is detected while displaying the first predefined set of media player controls, and wherein the media player controls in the first predefined set of media player controls are distinct from the media player controls in the second predefined set of media player controls.

US Pat. No. 10,140,300

METHOD AND APPARATUS FOR STAGED CONTENT ANALYSIS

1. A method, comprising:filtering out, by a processing system comprising a processor, redundant content in a group of content streams to generate a filtered group of content streams;
performing, by the processing system comprising a processor, a coarse feature analysis of the filtered group of content streams at a multiple frame level;
identifying, by the processing system, a subset of the group of content streams having a potential occurrence of a general feature according to the coarse feature analysis;
performing, by the processing system, a specialized analysis on the subset at a frame by frame level to determine an occurrence of the general feature;
generating, by the processing system, a weighted content description of the group of content streams based on the occurrence of the general feature;
generating, by the processing system, statistics associated with the weighted content description according to a number of instances of the general feature; and
generating, by the processing system, an indication that the statistics associated with the weighted content description for the general feature violate user defined rules for the filtered group of the content streams.

US Pat. No. 10,140,298

SOCIAL NETWORKING RESPONSE MANAGEMENT SYSTEM

International Business Ma...

1. A method for managing electronic social networking, comprising:defining content from a first user for communication to other users on an electronic social networking system;
applying natural language processing (NLP) and analytic analysis to the content to identify a workflow for accessing and responding to the content by the first user and the other users;
defining a set of rules as part of the workflow for controlling access and responses to the content, the set of rules including user actions for defining a level of permission for each user of the other users in relation to the workflow;
the defining of the set of rules including identifying a plurality of areas of interest to the other users in relation to the workflow using the analytic analysis by analyzing information from the social networking system, the areas of interest including one or more of: an expertise, work experience, a current project, a skill; and
controlling the access and the responding to the content by the first user and the other users based on the defined set of rules for the workflow which includes the areas of interest to the other users;
the controlling the access and the responding to the content including:
allowing a first group of one or more specified responders of the other users to respond to the content based on the defined set of rules for the workflow;
blocking a second group of one or more specified responders of the other users from responding to the content based on the defined set of rules for the workflow;
allowing a first sub-group of the first group to replace the content based on the defined set of rules for the workflow;
allowing a second sub-group of the first group to edit and/or replace the content after a period of time has elapsed, based on the defined set of rules for the workflow; and
allowing the second group of the one or more specified responders of the other users to respond to the content, in response to the first group of the one or more specified responders of the other users completing a response.

US Pat. No. 10,140,296

REVERSIBLE REDACTION AND TOKENIZATION COMPUTING SYSTEM

Bank of America Corporati...

1. A reversible data redaction system, comprising:a first computing system comprising a first database storing a plurality of electronic documents;
a second computing system including a second database storing a plurality of computer executable instructions for applying one or more rules in relation to managing non-public information in electronic documents;
a reversible data redaction engine comprising a processor and a non-transitory memory device, the non-transitory memory device storing instructions that, when executed by the processor, cause the reversible data redaction engine to:
identify an electronic document of the plurality of electronic documents stored in the first database;
analyze the electronic document to determine a document type, a source of the electronic document, and a destination to which the electronic document is to be communicated;
redact at least a portion of the electronic document by executing the computer executable instructions to apply the one or more rules based on at least one of the document type, the source of the electronic document, or the destination of the electronic document, wherein a first redacted portion is for presentation to a first recipient and a second redacted portion is for presentation to a second recipient; and
split the electronic document into the first redacted portion and the second redacted portion, wherein the first redacted portion is for communication via a first network to a first recipient and the second redacted portion is for communication via a second network to a second recipient.

US Pat. No. 10,140,295

METHOD, SYSTEM AND SOFTWARE FOR SEARCHING, IDENTIFYING, RETRIEVING AND PRESENTING ELECTRONIC DOCUMENTS

Camelot UK Bidco Limited,...

1. A computer-implemented method of improving performance of a computer to enhance relevance ranking of results in a computer-implemented search of a corpus of documents having in part homogeneous structured data having a field structure, using an underlying search engine offering a distribution-biased OR operator, the method comprising:a. as a preparatory phase, before a request function receives any queries, based on knowledge of the field structure of the documents to be searched and the content of some of the fields, determining a mapping or policy for automatically, by a processor, replacing a received search clause with a sequence of multiple search clauses of anticipated nested respective responsive scopes, such that a set of documents responsive to one search clause in the sequence of search clauses is predicted to be a subset of the set of documents responsive to the next search clause in the sequence of search clauses;
b. on an ongoing basis, operating at a search-controller level to mediate between the request function and an underlying search engine, and electronically receiving a query comprising at least one search clause from the request function;
c. by the processor, according to the mapping or policy determined in preparatory-phase step (a), transforming at least one of the at least one received search clause received in step (b) into an automatically generated, intentionally redundant sequence of search clauses representing the anticipated nesting of respective responsive scopes designed in the step (a) mapping or policy, so as to correspond to gradations of focus on a topic of interest interpreted to be suggested by the at least one received search clause;
d. combining the generated sequence of search clauses with a distribution-biased OR operator and submitting the combination to the underlying search engine to be executed against a database associated with the search engine, wherein scoring of the distribution-biased OR operation reflects not only aggregate scoring from respective counts of matches for the alternate clauses under the distribution-biased OR but also the evenness of distribution of that aggregate across its contributing component scores coming from those respective alternate clauses;
e. automatically executing the submitted combination of search clauses, by the underlying search engine, such that the nesting of the individual clauses' respective responsive scopes induces scopes of focus induce the underlying search engine to return a set of responsive documents for the entire OR combination that corresponds to the responsive set for the broadest of the submitted, automatically generated sequence of individual search clauses; and
f. automatically relevance-scoring the broad set of responsive documents returned in step (e), via the underlying search engine's processing of the distribution-biased OR-connected sequence of search clauses automatically generated and submitted in steps (c) and (d), yielding scoring more sensitive to gradations of focus on a topic of interest as suggested in the at least one search clause received in step (b).

US Pat. No. 10,140,294

DOCUMENT MANAGEMENT SYSTEMS AND METHODS

ACCENTURE GLOBAL SERVICES...

1. A method for managing an electronic document transaction, comprising:communicating, by one or more of a document management application supporting one or more integration protocols and a document management module in communication with the document management application, with one or more of a user relationship management system, and a document management system using the one or more integration protocols;
receiving a request at one of a document management application and a document management module from the user relationship management system to execute the document management application comprising a previously-created document management process and implement the previously-created document management process;
displaying, on a graphical user interface at a host computer, an indication of a set of documents to be acquired from a plurality of documents identified in the previously-created document management process, the set of documents comprising at least one document comprising a digital signature;
communicating, by one or more of the document management application supporting one or more integration protocols and the document management module in communication with the document management application, with a signature acquisition module using the one or more integration protocols configured to acquire a digital signature from a signature input device to create a digitally-signed electronic document;
receiving the digitally-signed electronic document created with the digital signature from the signature acquisition module;
creating an association in the form of a transaction file between user identification information and the digitally-signed electronic document, wherein the transaction file represents a single file that is created for each user transaction, and wherein the transaction file includes a plurality of required documents for a user transaction with respect to at least one of the plurality of documents;
communicating, by one or more of the document management application supporting the one or more integration protocols and the document management module in communication with the document management application, with a scanning device using the one or more integration protocols, the scanning device configured to acquire one or more images of one of the set of documents to be acquired identified in the previously-created document management process, the previously-created document management process indicating an image acquisition procedure at the graphical user interface;
receiving the acquired one or more images of one of the set of documents;
adding the one or more acquired images to the transaction file;
comparing at least one of the received images of one of the set of documents to a document template to automatically identify the one indicated document, the document template being created in the previously-created document management process and defining dimensions, textual characteristics, and at least one characteristic image, the at least one characteristic image being a characteristic of the indicated document that differentiates the indicated document from other documents, the template including fields defined therein from data to be extracted;
communicating, through the document management application, with an optical character recognition (OCR) library and extracting data from the at least one received image corresponding to the defined fields within the document template using the OCR library;
adding the extracted data to the transaction file;
transmitting the transaction file to a database;
comparing the extracted data with one or more of corresponding data extracted from another of the set of documents and user data input at the graphical user interface;
determining whether a confidence level associated with the comparison of the extracted data with the one or more of corresponding data extracted from another of the set of documents and user data input at the graphical user interface is within a confidence interval, wherein the confidence interval is set based on detection rates associated with a document type of the one of the set of documents, wherein the detection rates depend on quality of the acquired one or more images of the one of the set of documents, and wherein the confidence interval is variably defined to indicate an acceptable difference between a plurality of sets of the extracted data that are compared with each other; and
in response to a determination that the confidence level is within the confidence interval, generating an indication of a match between the extracted data with the one or more of corresponding data extracted from another of the set of documents and user data input at the graphical user interface.

US Pat. No. 10,140,292

DEVICE AND COMPUTERIZED METHOD FOR PICTURE BASED COMMUNICATION

AVAZ, INC., Palo Alto, C...

1. A computerized method for picture based communication, the method comprising:presenting, by a user interface module, a plurality of pictures to a user on a screen of a device;
receiving, by said user interface module, at least one picture selected by said user;
receiving, by said user interface module, one or more attributes of at least one picture selected by said user;
constructing, by a graph generation module, at least one connected graph in semantic interlingua, wherein said at least one connected graph is made of words and relationships with said selected at least one picture;
generating, by a sentence generation module, a sentence in at least one target language based on said at least one connected graph, said generation further comprising:
generating a graph representation from said connected graph in said semantic interlingua using at least one graph rule applied by a rule engine;
generating separate tree representations for each node in said graph representation, wherein said tree representation is generated based on at least one graph-to-tree rule applied by said rule engine;
generating a cumulative tree representation based on said separate tree representations, wherein said separate tree representations are analyzed based on at least one graph to tree rule, and cumulative tree representation is analyzed by at least one tree rule, applied by said rule engine, wherein analyzing at least one graph further comprises:
traversing said graph representation node-by-node, wherein said graph representation is traversed from an entry node and proceeding outwards along edges,
selecting edges in said graph representation from among those which create a cycle in the graph, or which cause an entry node to have at least one input edge, cause a node that is not an entry node to have two or more input edges, and cause a node to have more than one input edges of give type,
forming said selected edges, breaking edges having a start node, an end node, and a relation, and
transforming said cumulative tree representation into said sentence in said at least one target language, wherein said cumulative tree representation is transformed based on at least one sequence transformation rule applied by said rule engine; and
communicating, by an output module, said sentence in said at least one target language to a party receiving said communication on said device in a mode as configured by the user, wherein said communicating comprises causing to display said sentence on said screen of said device, wherein said at least one target language is based on an input representing mode of communication received from said user.

US Pat. No. 10,140,291

TASK-ORIENTED MESSAGING SYSTEM

International Business Ma...

1. A computer-implemented method comprising:identifying an electronic message generated by a first user with an electronic communication tool and directed to a first recipient;
intercepting the electronic message before the electronic message is available to the first recipient;
analyzing the electronic message to identify a set of requests to perform a corresponding set of tasks;
responsive to identifying the set of requests, composing a task statement that summarizes each request to perform a corresponding task;
sending; to the first recipient, the electronic message using the electronic communication tool;
receiving a reply message from the first recipient;
determining that one or more tasks of the corresponding set of tasks are not addressed in the reply message;
responsive to a determination that the one or more tasks are not addressed in the reply message, generating an interactive interface including the task statement and a corresponding set of selectable disposition actions for each of the one or more tasks that is not addressed including respond later, respond now, ignore, delegate, open the electronic message in a native messaging application, and already answered;
displaying, to the first recipient, the electronic message and the interactive interface including the task statement and the corresponding set of selectable disposition actions;
responsive to selection, by the first recipient, of a disposition action from the corresponding set of selectable disposition actions, taking the disposition action; and
responsive to selection of the disposition action to ignore a first task of the corresponding set of tasks, recording the first task as addressed to prevent generation of the first task in a subsequent interactive interface corresponding to the electronic message.

US Pat. No. 10,140,290

MESSAGE TONE EVALUATION IN WRITTEN MEDIA

International Business Ma...

1. A computer program product for message tone evaluation between entities in an organization, the computer program product comprising a computer readable storage medium having program code embodied therewith, the program code comprising the programming instructions for:intercepting a message or a group of messages between a sender entity and a recipient entity in an organization;
extracting text content for the message or group of messages and obtaining analysis of the tone of the text content, wherein the tone comprises emotions, social tendencies, writing styles and sentiment of positive and negative sentiments;
formatting a tone weighting for a communication relationship of the sender entity to the recipient entity including additional metadata relating to the message or group of messages, wherein the metadata comprises date and location tags as well as a medium used for interaction, wherein the metadata helps with additional metrics and analysis by recognizing other factors influencing the tone;
referencing a graph in which nodes represent entities in the organization and edges between the nodes have tone weightings for a tone for a communication relationship between the entities, wherein the tone weightings comprise a numerical value;
updating the graph with a tone weighting for the intercepted message or group of messages by setting or updating an edge tone weighting between the nodes for the sender entity and the recipient entity;
analyzing, by the processor, the graph to obtain analysis of one or more entities of the organization and the tone weightings of their communication relationships; and
capturing an insight into an interaction tone of the organization based on the analysis.

US Pat. No. 10,140,289

IDENTIFYING PROPAGANDA IN GLOBAL SOCIAL MEDIA

Galisteo Consulting Group...

1. A computer implemented method for identifying propaganda, wherein a computer has a source dataset stored thereon, comprising:the computer tokenizing each document in the source dataset;
the computer generating a term-by-document matrix;
the computer applying weights to the term-by-document matrix to generate a weighted term-by-document matrix;
the computer performing a matrix multiplication of a translation matrix and the weighted term-by-document matrix to generate a multilingualized weighted matrix;
the computer factorizing the multilingualized weighted matrix to generate an ordered list of topics and a topic-by-document block matrix;
the computer calculating a contribution per user-specified grouping within the source dataset to each topic within the ordered list of topics; and
the computer generating output enabling significant patterns, trends, and differences between groupings to be identified;
wherein the tokenization, generating of a matrix, applying weights, matrix multiplication, factorizing, calculating, and generating of output are performed regardless of the number, type, or size of documents, regardless of the number or type of terms associated with each document, and regardless of the provenance of the dataset.

US Pat. No. 10,140,288

PROCESSING TEXT WITH DOMAIN-SPECIFIC SPREADING ACTIVATION METHODS

1. One or more non-transitory electronic memory devices including computer instructions for performing a method comprising using a central processing unit (CPU) to create, from a text of one or more documents containing natural language stored in a non-transitory electronic memory device, a semantic network having a plurality of nodes corresponding to sets of semantic and episodic concepts and weighted links between the sets of semantic and episodic concepts,the sets of semantic concepts consisting of a plurality of semantic concepts associated with a plurality of known words;
the sets of episodic concepts consisting of a plurality of episodic concepts associated with the semantic concepts; and
utilizing, using the CPU, spreading activation algorithms to refine the weighted links in the semantic network.

US Pat. No. 10,140,286

OPTIMIZED GRAPH TRAVERSAL

Google LLC, Mountain Vie...

1. A system comprising:a front end server that is configured to receive a given phrase that is input through a user interface by a digital component provider;
a knowledge graph traverser that is configured to determine an entity that is being referred to by the given phrase, wherein the knowledge graph traverser performs the determination by accessing a knowledge graph comprising nodes that each uniquely identify different entities, and identifying a particular node that uniquely identifies the entity being referred to by the given phrase, wherein the nodes of the knowledge graph are connected by edges that represent relationships between connected nodes; and
a property selector that interacts with the graph traverser and is configured to:
identify properties of the entity by accessing other nodes that are connected to the particular node that identifies the entity;
access a search query history that includes previous search queries provided by users;
determine, from among the properties that were identified for the entity, one or more properties that occur in the previous search queries provided by the users at a greater frequency than other properties that were identified for the entity; and
based on characteristics of the digital component provider, select, from among the one or more properties that occur in the previous search queries provided by the users at the greater frequency than the other properties that were identified for the entity, a subset of the properties that were identified for the entity,
wherein the knowledge graph traverser is further configured to identify additional phrases by accessing the knowledge graph using the subset of properties that were identified for the entity, and
wherein the front-end server updates the user interface to present at least some of the additional phrases with programmatic controls that assign one or more of the additional phrase as distribution criteria for digital components of the digital component provider in response to activation of the programmatic controls.

US Pat. No. 10,140,285

SYSTEM AND METHOD FOR GENERATING PHRASE BASED CATEGORIES OF INTERACTIONS

1. A computer-implemented method of generating phrase based categories for interactions recorded at a call center, the method comprising:displaying, using a computer processor, a graphical user interface to a user, the graphical user interface comprising: an input area for the user to input a base category and one or more phrases, for analysis of the base category, and an input area for the user to input a candidate phrase for analysis;
obtaining via user input the base category;
generating, using the computer processor, a base trend for the base category based on a frequency of appearance of at least one of the one or more phrases in a set of recorded interactions that are specific to the call center, the base trend comprising a series of numbers of interactions per time unit for each of a series of time units, each recorded interaction comprising a text recording of a conversational exchange, wherein at least some of the text recordings are produced via a speech to text process applied to an audio recording;
obtaining via user input the candidate phrase;
generating, using the computer processor, an accuracy value for the candidate phrase by determining a correlation between: a first candidate trend determined based on the frequency of appearance of the candidate phrase in the set of recorded interactions determined using a first accuracy value; and a second candidate trend determined based on the frequency of appearance of the candidate phrase in the set of recorded interactions determined using a second accuracy value;
generating, using the computer processor, a candidate trend for the candidate phrase based on a frequency of appearance of the candidate phrase in the set of recorded interactions determined using the generated accuracy value, each of the candidate trend, the first candidate trend, and the second candidate trend comprising a series of numbers of interactions per time unit for each of a series of time units;
calculating, using the computer processor, a correlation level for the candidate trend based on the candidate trend and the base trend, wherein the correlation level quantifies a difference in a behavior of the candidate trend and the base trend;
if the correlation level is greater than a threshold level then including, using the computer processor, the candidate phrase in the base category; and
displaying to the user the candidate phrase.

US Pat. No. 10,140,283

PREDICTIVE TEXT DICTIONARY POPULATION

BlackBerry Limited, Wate...

1. A method of populating a predictive text dictionary of a computing device, the method comprising:receiving a selection of one or more word categories, wherein the one or more word categories include a plurality of words, each of the plurality of words is associated with a date when the word was added to the one or more word categories, one of the one or more word categories is a location-specific category, and each word in the location-specific category is associated with a location;
in response to receiving the selection, updating a user preference to include the selected one or more word categories, wherein the user preference includes a date when a last previous update occurred for the predictive text dictionary of the computing device;
sending a request, from the computing device to a server through a communication network, for a new word, wherein the server determines that a location of the computing device is different than a previous location of the computing device, and the new word is selected at least partially based on the date when the last previous update occurred for the predictive text dictionary of the computing device prior to a date when the new word was added to the one or more word categories, and a location associated with the new word matching the location of the computing device if the new word is in the location-specific category;
receiving, at the computing device, the new word from the server through the communication network;
updating, by the computing device, the predictive text dictionary of the computing device to include an addition of the received new word, wherein updating the predictive text dictionary also includes discarding an existing word from the predictive text dictionary, and the existing word is associated with the previous location of the computing device;
receiving text input at the computing device; and
in response to receiving the text input, presenting, at the computing device, at least one predicted word that is based on the text input and the updated predictive text dictionary.

US Pat. No. 10,140,281

METHOD AND SYSTEM FOR DISTRIBUTED LATENT DIRICHLET ALLOCATION COMPUTATION USING ADDITION OF APPROXIMATE COUNTERS

ORACLE INTERNATIONAL CORP...

1. A method for a distributed system, including a first computing device and a second computing device communicatively connected via a network, running a distributed uncollapsed Gibbs sampler comprising:the first computing device running the uncollapsed Gibbs sampler over a Dirichlet distribution of a plurality of words in a set of documents to produce sampler result data, further comprising:
receiving, from the second computing device, a first approximate counter value that corresponds to a particular counter of the distributed uncollapsed Gibbs sampler,
using one or more probabilistic techniques to increment a second approximate counter value that also corresponds to the particular counter;
adding the first approximate counter value to the second approximate counter value to produce an aggregate approximate counter value, and
converting the aggregate approximate counter value to an expected value represented by the aggregate approximate counter value; and
using the expected value generated from the aggregate approximate counter value as the value of the particular counter; and
determining, from the sampler result data, one or more sets of correlated words.

US Pat. No. 10,140,280

ASYNCHRONOUS DYNAMIC FUNCTIONS FOR CALCULATION ENGINES

Microsoft Technology Lice...

1. A method of providing a data calculation framework for a user application, the method comprising:providing one or more functions for use by a calculation engine of the user application;
monitoring an availability status of each of the one or more functions, wherein the availability status is related to a present capability of one of each of the one or more functions to process expressions associated with the calculation engine;
determining that the calculation engine issues a call for evaluation of a nested expression comprising at least a child function embedded in a parent function, and responsively dispatching at least a first evaluation process for a first portion of the nested expression that employs the child function;
determining, during the monitoring, that the parent function has an unavailable status;
during evaluation of the nested expression, indicating to the calculation engine, based on the unavailable status of the parent function, a predetermined result for at least the parent function;
determining, during the monitoring based on availability of a child result from the first evaluation process, that the parent function has an available status;
responsive to the available status of the parent function, dispatching at least a second evaluation process for a second portion of the nested expression that employs the child result; and
responsive to receiving a parent result from the second evaluation process, indicating the parent result to the calculation engine.

US Pat. No. 10,140,278

COMPUTER-IMPLEMENTED METHODS AND SYSTEMS FOR ASSOCIATING FILES WITH CELLS OF A COLLABORATIVE SPREADSHEET

Adobe Systems Incorporate...

1. A computer-implemented method comprising:receiving, from a client device, by an attachment module hosted on a cloud storage device, a first request to attach a file to a cell of a collaborative spreadsheet, wherein the collaborative spreadsheet is stored on the cloud storage device, wherein the first request identifies the cell and is received in response to a user interaction at the client device with an attachment icon of the collaborative spreadsheet in a graphical user interface, wherein the graphical user interface presents the collaborative spreadsheet in a viewing area and the attachment icon in a toolbar;
sending, by the attachment module in response to the first request, a second request to the client device to provide the file; and
after receiving the file from the client device in response to the second request, attaching, by the attachment module, the file to the cell of the collaborative spreadsheet based on the first request, the attaching comprising:
in response to receiving the file from the client device, generating a unique identifier of the file and storing the file on the cloud storage device,
in response to the unique identifier being generated, inserting the unique identifier of the file in the cell identified in the first request and marking a type of the cell as being an attached file,
including in an attribute of the cell and based on the file being stored on the cloud storage device, a reference associated with a storage location of the file on the cloud storage device, the reference being different from the unique identifier and allowing access to the file from the cell of the collaborative spreadsheet, and
representing attachment of the file to the cell with a graphical component, wherein, when the collaborative spreadsheet is presented in the graphical user interface, the graphical component is presented in the cell of the collaborative spreadsheet based on the unique identifier of the file;
wherein the file is stored separately from the collaborative spreadsheet and is accessible from the cell of the collaborative spreadsheet based on the reference in the attribute of the cell to the storage location of the file.

US Pat. No. 10,140,277

SYSTEM AND METHOD FOR SELECTING DATA SAMPLE GROUPS FOR MACHINE LEARNING OF CONTEXT OF DATA FIELDS FOR VARIOUS DOCUMENT TYPES AND/OR FOR TEST DATA GENERATION FOR QUALITY ASSURANCE SYSTEMS

Intuit Inc., Mountain Vi...

1. A computing system implemented method for efficiently learning new forms in an electronic document preparation system, the method comprising:receiving form data related to a new form having a plurality of data fields;
gathering training set data related to previously filled forms, each previously filled form having one or more completed data fields that correspond to a respective data field of the new form;
deleting from the training set data one or more sets of data of a previously filled form where a first set of data of the previously filled form matched a second set of data of the previously filled form and the deleted training set data includes the second set of data;
generating, for a first selected data field, dependency data indicating one or more possible dependencies for an acceptable function, the possible dependencies including one or more data fields of the new form other than the first selected data field, the possible dependencies further including one or more constants of the first selected data field, the possible dependencies further including one or more values of data fields from a form other than the new form;
generating, for a first selected data field of the plurality of data fields of the new form and based on the dependency data, candidate function data including a plurality of candidate functions;
generating, for the first selected data field and based on the dependency data, grouping data by forming a plurality of groups from the training set data based on respective categories and assigning each of a plurality of the previously filled forms to a respective one of the groups based on the categories;
generating, for the first selected data field, sampling data by selecting one or more previously filled forms from each group;
generating, for each candidate function, test data by applying the candidate function to a portion of the training set data corresponding to the sampling data related to the candidate function;
identifying one or more candidate functions of the plurality of candidate functions that have associated test data that are a best match to the training set data as compared with other candidate functions of the plurality of candidate functions;
generating one or more additional candidate functions, the additional candidate functions being based on the identified one or more candidate functions that have associated test data that are a best match;
repeatedly identifying generated candidate functions that have associated test data that are a best match to the training set data and generating one or more additional candidate functions, the additional candidate functions being based on the identified one or more candidate functions that have associated test data that are a best match until one or more candidate functions are determined to have associated test data that matches the training set data with a predetermined tolerance;
identifying, from the plurality of candidate functions, an acceptable function for the first selected data field by comparing the test data to the training set data and identifying test data that matches the training set data within a predetermined tolerance, the identified acceptable function being a candidate function associated with the matching test data; and
generating and outputting results data indicating the acceptable function for the first data field of the new form.

US Pat. No. 10,140,276

SYSTEM AND METHOD FOR DYNAMICALLY GENERATING CLIENT-SIDE DATABASE FORMS

Quest Software Inc., Ali...

1. A method comprising, on a backend computing system comprising at least one server computer:centrally maintaining a plurality of form-generator client applications;
centrally maintaining a plurality of entity adapters, each entity adapter providing a standard interface to one or more of a plurality of database entities, the plurality of database entities logically representing data stored in a database on the backend computing system;
allowing a user of a client device to select a form-generation category from a plurality of form-generation categories;
identifying a form-generator client application of the plurality of form-generator client applications that is appropriate for the form-generation category;
generating a webpage comprising a reference to a network location of the form-generator client application;
serving the webpage to the client device;
receiving, at the network location, a request from the client device for the form-generator client application;
supplying the form-generator client application to the client device so that the form-generator client application can be loaded on the client device;
receiving, from the loaded form-generator client application, a request for an entity schema of at least one database entity of the plurality of database entities;
acquiring, using an entity adapter of the plurality of entity adapters that is associated with the at least one database entity, a standardized schema for the at least one database entity;
transmitting the standardized schema to the loaded form-generator client application so that a client-side database form can be dynamically generated by the loaded form-generator client application, on the client device, in accordance with a structure of the at least one database entity as represented by the standardized schema;
providing, to the dynamically-generated client-side database form, a web application programming interface (API) for performing a set of persistent storage operations, wherein the web API defines the set of persistent storage operations in terms of hypertext transfer protocol methods;
receiving, via the web API, from the dynamically-generated client-side database form on the client device, one or more persistent storage operations of the set relative to the at least one database entity; and
performing the one or more persistent storage operations in the database relative to the at least one database entity.

US Pat. No. 10,140,275

MESSAGE INFORMATION GENERATING APPARATUS, OUTGOING CALL CONTROL APPARATUS, MESSAGE INFORMATION GENERATING METHOD, AND OUTGOING CALL CONTROL METHOD

FUJITSU LIMITED, Kawasak...

1. A non-transitory computer-readable recording medium having stored therein a message information generating program, which when processed by one or more processors, causes a computer to execute a process comprising:acquiring first information having both a character string input by handwriting and a character color related to the character string input by the handwriting as a handwritten input content on an electronic message board;
specifying a form of the character string based on the color related to the character string acquired first information;
specifying an address associated with the specified form by referring to a storage configured to store an address of a message destination in association with a form of a character string; and
generating and sending message information with the specified address as a destination, the message information including second information corresponding to the character string.

US Pat. No. 10,140,274

AUTOMATED MESSAGE MODIFICATION BASED ON USER CONTEXT

International Business Ma...

1. A method of dynamically modifying an incoming message based on user context comprising:analyzing an incoming message directed to a user to determine a message content associated with the incoming message, wherein analyzing the incoming message comprises determining a message sentiment associated with the message content;
determining a user context based on one or more environmental parameters associated with the user;
determining whether there is sensitive content in the incoming message based on the message content and user context; and
in response to determining that there is sensitive content in the incoming message, generating a modified message by removing the sensitive content from the incoming message for display to the user, wherein generating the modified message comprises:
selecting a pre-configured template based on the message sentiment; and
revising the pre-configured template to include a summary of the message content.

US Pat. No. 10,140,273

LIST MANIPULATION IN NATURAL LANGUAGE PROCESSING

International Business Ma...

1. A method comprising:receiving an input text comprising a plurality of lists associated with at least one clinical trial, wherein each respective list comprises a plurality of respective list items;
segmenting the input text into tokens;
annotating tokens for parts of speech, wherein annotating tokens for parts of speech comprises annotating tokens for conjunctions, wherein a conjunction is selected from the group consisting of: a respective word from a set of conjunction words, a comma, and a dash, wherein annotating tokens for parts of speech further comprises:
identifying respective lists of the plurality of lists based on respective tokens annotated as conjunctions;
identifying respective list items based on respective tokens annotated as conjunctions by:
identifying a first discrete list item based on the first discrete list item being located adjacent to a first token annotated as a comma;
identifying a first implied list item based on a second token annotated as a dash located between a first number and a second number;
annotating tokens for prefix modifiers and suffix modifiers, wherein a respective prefix modifier is explicitly or impliedly before respective list items, wherein a respective suffix modifier is explicitly or impliedly after respective list items;
annotating a lemma form to respective portions of the input text containing any one of a subset of terms related to the lemma form, wherein the lemma form is associated with a trigger, wherein annotating the lemma form further comprises:
identifying a scope associated with the trigger, wherein the scope comprises a term associated with any one of the subset of terms related to the lemma form, wherein the scope limits a meaning of the trigger; and
annotating at least a portion of the input text for domain specific content;
retrieving a list modification rule set based on the input text, annotating tokens for parts of speech, annotating tokens for prefix modifiers and suffix modifiers, annotating the lemma form, and annotating for domain specific content;
matching a portion of the input text to an implied list indicator stored in the list modification rule set, wherein the implied list indicator is associated with a first explicit list;
modifying the plurality of lists based on the list modification rule set to generate modified input text, wherein the modified input text expands the input text to explicitly state each respective list item by:
appending, to each respective list item in a first list of the plurality of lists, a prefix modifier, a suffix modifier, or both a prefix modifier and a suffix modifier to the respective list item;
replacing, in a second list of the plurality of lists, the implied list indicator with the first explicit list by:
appending the first explicit list to the input text at a location containing the implied list indicator, wherein the first explicit list comprises a plurality of list items; and
deleting the implied list indicator from the input text;
identifying extraneous text of the input text based on the list modification rule set; and
deleting extraneous text from the input text;
storing the modified input text in a database of clinical trials, wherein the modified input text includes at least one list item appended with a prefix modifier, at least one list item appended with a suffix modifier, at least one list item appended with both a prefix modifier and a suffix modifier, the implied list indicator replaced by the first explicit list, and at least a portion of the input text deleted and not replaced;
matching the modified input text to one or more patient profiles in a database of patient profiles;
scoring each respective match; and
outputting one or more patient profiles to a user interface, wherein patient profiles having a score above a threshold are identified as eligible for the at least one clinical trial and patient profiles having a score below the threshold are identified as not eligible for the at least one clinical trial.

US Pat. No. 10,140,272

DYNAMIC CONTEXT AWARE ABBREVIATION DETECTION AND ANNOTATION

International Business Ma...

1. A method, in a data processing system comprising a processor and a memory having instructions which, when executed by the processor, cause the processor to configure the data processing system to implement a context aware abbreviation detection and annotation (CAADA) system, the method comprising:identifying, by the CAADA system, in received content, an instance of a full name of an entity;
performing, by the CAADA system, analysis of a context window associated with the instance of the full name of the entity to identify a presence of a pattern of content representative of an abbreviation;
identifying, by the CAADA system, an abbreviation being present in association with the instance of the full name of the entity based on results of the analysis of the context window;
generating, by the CAADA system, a mapping data structure that maps the full name of the entity to the abbreviation;
analyzing, by the CAADA system, the received content to identify other instances of the abbreviation that match the abbreviation and the pattern of content representative of the abbreviation;
generating, by the CAADA system, a global abbreviation list data structure comprising each instance of the abbreviation within the received content;
comparing, by the CAADA system, the abbreviation in the mapping data structure to the abbreviation in the global abbreviation list data structure to identify matches between entries in the mapping data structure to entries in the global abbreviations list data structure;
responsive to matching an abbreviation in the global abbreviation list data structure to an abbreviation in the mapping data structure, generating, by the CAADA system, annotations in an annotation data structure for each instance of the abbreviation in received content along with the full name of the entity associated with the abbreviation;
annotating, by the CAADA system, the received content based on the annotation data structure to thereby generate abbreviation annotations for each instance of the abbreviation in the received content; and
outputting, by the CAADA system, the annotated received content along with the annotation data structure for use by a cognitive system to perform a cognitive operation based on the annotated received content and the annotation data structure.

US Pat. No. 10,140,271

DYNAMIC ADAPTATION OF A NARRATIVE ACROSS DIFFERENT TYPES OF DIGITAL MEDIA

Telltale, Incorporated, ...

1. A method comprising:maintaining, at a server system, a narrative state for a narrative to be presented to a user across a plurality of digital media; and
in response to determining that the user has logged into a first client system, transmitting, by the server system, a copy of the narrative state to the first client system, wherein the first client system is configured to present the narrative to the user via a first digital medium in the plurality of digital media, and wherein upon receiving the copy of the narrative state, the first client system is configured to:
adapt, based on the copy of the narrative state and one or more first rules, the first client system's presentation of the narrative to the user via the first digital medium, wherein the adapting takes into account information included in the copy of the narrative state that identifies portions of the narrative which have already been consumed by the user while operating a second client system different from the first client system, the second client system being configured to present the narrative via a second digital medium different from the first digital medium;
update the copy of the narrative state based on portions of the narrative consumed by the user via the first client system; and
upon determining that the user has logged out of the first client system, transmit the updated copy of the narrative state to the server system for storage on the server system.

US Pat. No. 10,140,270

DIGITAL DOCUMENT CHANGE CONFLICT RESOLUTION

Microsoft Technology Lice...

1. A method, comprising:detecting a conflict relating to a graphical object in a first version of a digital document and the graphical object in a second version of the digital document;
categorizing the conflict as a conflict to be resolved automatically based on an application of conflict resolution logic, wherein the conflict resolution logic comprises:
applying at least one conflict rule evaluating a property affecting a presentation of the graphical object, and
determining that the conflict modifies the presentation of the graphical object; and
automatically resolving the conflict by updating, in a user interface of a productivity service, one or more of the first version of the digital document and the second version of the digital document based on the categorizing.