US Pat. No. 10,601,117

ANTENNA AND MOBILE TERMINAL

HUAWEI DEVICE CO., LTD., ...

1. An antenna comprising:a first radiation part configured to generate a first frequency and comprising:
a capacitor structure configured as a series-distributed capacitor structure in a composite right/left-handed transmission line configuration;
a first radiator comprising a first end and a second end; and
a second radiator configured as a parallel distributed inductor in the composite right/left-handed transmission line configuration and comprising:
a first end coupled to the second end of the first radiator using the capacitor structure; and
a second end coupled to a grounding part, wherein a length of the second radiator is approximately one-eighth of as wavelength corresponding to the first frequency;
a matching circuit;
a feed source coupled to the first end of the first radiator using the matching circuit and coupled to the grounding part; and
a second radiation part, wherein a first end of the second radiation part is coupled to the second end of the first radiator, and wherein the second radiation part and the capacitor structure generate a second frequency.

US Pat. No. 10,601,116

WIRELESS TERMINAL

Huawei Technologies Co., ...

1. A wireless terminal, comprising:a first antenna and a second antenna;
a printed circuit board;
a bracket;
a resonator; and
wherein:
the first antenna is located at a first side edge of the printed circuit board,
the second antenna is located at a second side edge of the printed circuit board,
the printed circuit board functions as a metal ground of the first antenna and the second antenna,
the resonator is located on the bracket,
a ground point of the resonator is located on the printed circuit board,
a clearance exists between the resonator and the printed circuit board, and
the resonator comprises a structure formed by at least one metal strip that extends from a third side edge of the printed circuit board.

US Pat. No. 10,601,112

ANTENNA SYSTEM AND MOBILE TERMINAL

AAC Technologies Pte. Ltd...

1. An antenna system, comprising:a metal shell comprising a top frame, a bottom frame and a middle back cover; a notch is defined respectively between the middle back cover and the top frame and between the middle back cover and the bottom frame, the top frame is connected with the middle back cover by a connecting rib;
a system ground connected with the metal shell;
a mainboard comprising a mainboard ground connected with the system ground and a main circuit;
an antenna unit adjacent to the top frame or bottom frame;
the mainboard circuit comprises a first radio frequency source, a first antenna terminal, a second antenna terminal, a second radio frequency source and a few matching networks, at least one of the matching networks is provided between the first radio frequency source and the first antenna terminal, at least another one of the matching networks is provided between the second radio frequency source and the second antenna terminal, at least a further one of the matching networks is provided between the first antenna terminal and the second antenna terminal;
the antenna unit is connected with the mainboard by the first antenna terminal and/or the second antenna terminal, so that the antenna unit is coupled with the top frame or the bottom frame to form a first antenna, a second antenna and a third antenna;
each one of the matching networks comprises a first matching element and a second matching element; the first matching element of the matching network is connected in series in the main circuit, one end of the second matching element is connected with the main circuit while the other end of the second matching element is connected with the mainboard ground;
each first matching element and each second matching element can be chosen from one of a capacitance, an inductance, a resistance and a switch to form different connection manners of the antenna unit,
wherein the first radio frequency resource, the first antenna terminal, the second antenna terminal and the second radio frequency source are successively arranged, two matching networks are provided in series between the first antenna terminal and the first radio frequency source; another one matching network is arranged between the first antenna terminal and the second antenna terminal; a further one matching network is arranged between the second antenna terminal and the second radio frequency source, and both of the first antenna terminal and the second antenna terminal are directly connected to the mainboard ground through a second matching element.

US Pat. No. 10,601,110

WIRELESS DEVICE AND ANTENNA SYSTEM WITH EXTENDED BANDWIDTH

Fractus Antennas, S.L., ...

1. A wireless device comprising a radiating system that covers multiple frequency bands allocated in at least a first frequency region and a second frequency region, the radiating system comprising:a radiofrequency system comprising at least a matching network that provides impedance matching to the radiating system at the multiple frequency bands; and
a radiating structure comprising:
an antenna element capable of transmitting and receiving signals in the multiple frequency bands and connected to a feeding line through the radiofrequency system; and
at least a ground plane layer,
wherein a maximum length of the antenna element is shorter than L/12 but longer than L/22, where L is the free-space wavelength corresponding to a lowest frequency related to a lowest frequency region of operation.

US Pat. No. 10,601,086

COOLING SYSTEM FOR COOLING ELECTROCHEMICAL CELLS OF A BATTERY SYSTEM

Samsung SDI Co., Ltd., Y...

1. A cooling system for cooling electrochemical cells of a battery system, the cooling system comprising:a housing configured to accommodate a plurality of stacked electrochemical cells, the housing comprising:
a structured side wall having a plurality of protrusions therein, the protrusions being adapted to respectively receive a section of a thermally conductive element arranged between two adjacent ones of the stacked electrochemical cells, spaces between adjacent ones of the protrusions on an outer side of the structured side wall forming an outer receiving structure; and
a holding device configured to receive the housing, the holding device comprising a plurality of cooling fins configured to respectively fit into the outer receiving structure of the structured side wall.

US Pat. No. 10,601,080

DEVICES, SYSTEMS, AND METHODS TO MITIGATE THERMAL RUNAWAY CONDITIONS IN MOLTEN FLUID ELECTRODE APPARATUS

Vissers Battery Corporati...

1. An apparatus comprising:a fluid electrode material comprising fluid negative electrode material and fluid positive electrode material;
a reaction chamber comprising a fluid negative electrode formed from at least a portion of the fluid negative electrode material, a fluid positive electrode formed from at least a portion of the fluid positive electrode material, and a solid electrolyte between the fluid negative electrode and the fluid positive electrode;
a heating system configured to maintain the fluid negative electrode and the fluid positive electrode in a fluid state; and
a thermal runaway mitigation system configured to, in response to a thermal runaway trigger, cool at least a portion of the fluid electrode material to a temperature below the melting point of the at least the portion of the fluid electrode material to place the at least the portion of fluid electrode material in a solid state.

US Pat. No. 10,601,079

BATTERY ASSEMBLY INCLUDING CELL STRIP ARRAY AND METHOD

FORD GLOBAL TECHNOLOGIES,...

1. A battery assembly, comprising:a layer of electrolyte provided by a single, continuous layer of material;
a plurality of first electrodes arranged on a first side of the layer of electrolyte;
a plurality of second electrodes arranged on a second side of the layer of electrolyte;
a plurality of battery cells each including a portion of the layer of electrolyte, one of the first electrodes, and one of the second electrodes;
wherein the first electrodes include a plurality of anodes and a plurality of cathodes,
wherein the second electrodes include a plurality of anodes and a plurality of cathodes, and
wherein each of the cells includes an anode arranged on one of the first and second sides and a cathode arranged on the other of the first and second sides.

US Pat. No. 10,601,078

METHOD OF PRODUCING LITHIUM ION SECONDARY BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A method of producing a lithium ion secondary battery comprising:preparing an alkaline negative electrode composite material including a negative electrode active material, a binder, an alkaline component, and an aqueous solvent;
adding an oxalate complex lithium salt that is acidic in the aqueous solvent to the alkaline negative electrode composite material; and
applying the negative electrode composite material to which the oxalate complex lithium salt has been added to a surface of a negative electrode current collector and drying the negative electrode composite material to form a negative electrode active material layer,
wherein the negative electrode composite material to which the oxalate complex lithium salt has been added has a pH of 6.7 to 7.2.

US Pat. No. 10,601,071

METHODS OF MAKING AND INSPECTING A WEB OF VITREOUS LITHIUM SULFIDE SEPARATOR SHEET AND LITHIUM ELECTRODE ASSEMBLIES

POLYPLUS BATTERY COMPANY,...

1. A method of inspecting a battery cell, the method comprising:i) providing an electrode assembly comprising:
a dense solid inorganic electrolyte sheet as an ionically conductive separator layer having first and second opposing principal side surfaces; and
a material layer comprising electroactive lithium disposed on the first principal side surface; and
ii) spectrophotometrically inspecting the electrode assembly for defects or flaws at an interface between the material layer comprising electroactive lithium and the inorganic electrolyte sheet;
wherein the spectrophotometric inspection is an automated inspection comprising:
providing a source of light of a specified wavelength, or the wavelength selectable from a range of wavelengths;
providing sensors for measuring intensity of the light;
providing a computer that interfaces with the sensors for collecting light intensity data;
shining the light at the solid electrolyte sheet for transmission or reflection measurements;
measuring the transmitted or reflected light intensity using said sensors; and
storing data from said sensors using said computer.

US Pat. No. 10,601,070

FAST-CHARGING LITHIUM ION BATTERIE UNIT

StoreDot Ltd., Herzeliya...

1. A method of extending a cycling lifetime of a lithium ion battery, the method comprising:initially operating the battery at a narrow range of voltages which is smaller than 1.5V, and
consecutively, upon detection of a specified deterioration in a capacity of the battery, operating the battery at least at one broader range of voltages which is larger than 1.5V,
wherein the narrow range is within 3.1-4.3V and at least one of the broader range(s) is within 1.8-4.3 V.

US Pat. No. 10,601,062

SODIUM METAL BATTERIES WITH INTERCALATING CATHODE

Dynantis Corp., Santa Ba...

1. A storage cell comprising:a negative electrode comprising molten sodium metal;
a positive electrode having a solid sodium-intercalating metal oxide as the active cathode material;
a molten sodium haloaluminate catholyte; and
a solid sodium-conducting separation element intermediate between the negative electrode and the molten sodium haloaluminate catholyte;
wherein the molten sodium haloaluminate catholyte permeates the solid metal oxide of the positive electrode, and
wherein the sodium intercalating metal oxide is ?-Fe2O3.

US Pat. No. 10,601,033

HIGH-PERFORMANCE RECHARGEABLE BATTERIES HAVING A SPALLED AND TEXTURED CATHODE LAYER

International Business Ma...

1. A method of forming a rechargeable battery stack, the method comprising:providing a cathode material substrate having a first textured surface and a non-textured surface opposite the first textured surface of the cathode material substrate;
forming a stressor layer on the first textured surface of the cathode material substrate, wherein the stressor layer has a textured bottom surface and a textured top surface; and
performing a spalling process to remove a spalled cathode material layer from the cathode material substrate, wherein the spalled cathode material layer is attached to the stressor layer and includes the first textured surface and a second textured surface that is opposite the first textured surface and wherein the spalling process comprises forming a crack in the cathode material substrate at a located between the first textured surface of the cathode material substrate and the non-textured surface of the cathode material substrate, and fracturing the cathode material substrate at the crack.

US Pat. No. 10,601,032

COMPOSITE ELECTRODE MATERIAL

National Chiao Tung Unive...

1. A composite electrode material, disposed on a surface of an electrode of an electrochemical energy storage device and comprising:a plurality of conductive material layers, wherein each of the conductive material layers has a thickness of 0.3 nm to 100 nm; and
a plurality of active material layers, wherein the conductive material layers and the active material layers are stacked alternately along a direction non-parallel to the surface of the electrode, and are arranged disorderly along a direction parallel to the surface of the electrode, each of the active material layers has a thickness of 0.3 nm to 100 nm, a number of the conductive material layers is N or N+1, a number of the active material layers is N, and N is an integer equal to or greater than 2, so that the conductive material layers and the active material layers are sufficiently mixed, thereby maintaining a high specific capacitance of the electrochemical energy storage device at a high current density charging/discharging.

US Pat. No. 10,601,030

FUNCTIONAL POLYMER BINDER FOR SULFUR CATHODE FABRICATION

The Regents of the Univer...

1. A polymeric conductive binder comprising:
Poly[(2-ethyldimethylammonioethyl methacrylate ethyl sulfate)-co-(1-vinylpyrrolidone)].

US Pat. No. 10,601,029

POSITIVE ELECTRODE FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERY USING THE SAME

SANYO Electric Co., Ltd.,...

1. A positive electrode for a nonaqueous electrolyte secondary battery, comprising a lithium transition metal oxide,wherein,
a tungsten oxide is present on at least a part of a surface of the lithium transition metal oxide,
a carbonate compound that exists in a portion other than the surface of the lithium transition metal oxide is present on a part of a surface of the tungsten oxide, and
at least one interface between a particle of tungsten oxide and a particle of carbonate compound is not touching the lithium transition metal oxide.

US Pat. No. 10,601,019

ENERGY STORAGE DEVICE

GS YUASA INTERNATIONAL LT...

1. An energy storage device, comprising:an electrode assembly including a body portion and a first tab portion projecting from the body portion; and
a container housing the electrode assembly,
wherein a first current collector electrically connected to the first tab portion and the container, or the first tab portion and the container, include a swaged joint portion including a concavo-convex structure projecting toward an other side from one side in a first direction, and
wherein a member selected from the group consisting of the container, the first current collector, and the first tab portion, in which the member is disposed inside the concavo-convex structure, includes an expanding portion which projects in a second direction intersecting with the first direction.

US Pat. No. 10,601,017

CONDUCTOR MODULE

YAZAKI CORPORATION, Mina...

1. A conductor module comprising:at least two or more connection conductors that are electrically connected to one of two electrode terminals of a battery cell in a battery module having a plurality of the battery cells;
a film-like wiring member having flexibility in which at least two or more detection conductors are formed, the detection conductors electrically connecting a connection conductor of the connection conductors and a state detection device detecting a state of the battery cell electrically connected to the connection conductor;
fixing members that fix the connection conductor to the wiring member; and
a reinforcing member that reinforces the wiring member, wherein
the wiring member has a connection conductor accommodating portion accommodating the connection conductor and a through-hole penetrating from a front surface of the wiring member to a back surface of the wiring member,
at least two through-holes, including the through-hole, are formed in a first opposing region of the wiring member, which opposes one end face between two end faces of the connection conductor opposing each other in an opposing direction of the connection conductors with an electrical connection portion where the connection conductor and a detection conductor, of the detection conductors, are electrically connected interposed between the at least two of the through-holes when viewed from the opposing direction,
the fixing members are fixed to the connection conductor in a state where relative movement with respect to the connection conductor is restricted, are arranged in the through-holes, and have distal ends positioned radially outward of the through-holes when viewed from an axial direction of the throughholes, and
the reinforcing member is formed on at least one of the front surface and the back surface, and is formed to surround at least the two of the through-holes when viewed from the axial direction of the through-holes.

US Pat. No. 10,601,016

CENTER CONTACT PLATE CONFIGURED TO ESTABLISH ELECTRICAL BONDS TO DIFFERENT GROUPS OF BATTERY CELLS IN A BATTERY MODULE

TIVENI MERGECO, INC., Sa...

1. A center contact plate configured to establish electrical bonds between battery cells in a battery module, comprising:at least one primary conductive layer including:
a first set of holes formed within the at least one primary conductive layer that are aligned with positive terminals of a first group of battery cells that are configured to be connected in parallel with each other; and
a second set of holes formed within the at least one primary conductive layer that are aligned with negative terminals of a second group of battery cells that are configured to be connected in parallel with each other,
wherein the first and second sets of holes are each clustered together on different sides of the at least one primary conductive layer; and
a cell terminal connection layer including a first set of bonding connectors and a second set of bonding connectors,
wherein the at least one primary conductive layer includes first and second primary conductive layers sandwiching part of the cell terminal connection layer.

US Pat. No. 10,601,015

BUS BAR MODULE

YAZAKI CORPORATION, Toky...

1. A bus bar module comprising:a plurality of first bus bars configured to electrically connect electrode terminals to each other in one electrode row arranged in a same direction included in a battery assembly that is a plurality of batteries superimposed in the same direction, and electrically connect the electrode terminals of the two adjacent batteries to each other in the one electrode row;
a plurality of second bus bars configured to electrically connect electrode terminals to each other in another electrode row arranged in the same direction included in the battery assembly, and electrically connect the electrode terminals of the two adjacent batteries to each other in the other electrode row;
a resin-made first holding member that holds the first bus bars;
a resin-made second holding member that holds the second bus bars;
a resin-made bridging member that bridges the first holding member and the second holding member;
a circuit board; and
a heat shielding plate, wherein
the bridging member includes a first side that faces away from the battery assembly and a second side that faces toward the battery assembly, the circuit board is supported on and engages the first side of the bridging member, and the heat shielding plate is supported on and engages the second side of the bridging member such that the bridging member supports the circuit board at a position that is spaced away from the battery assembly, and the bridging member supports the heat shielding plate at a position that is between the circuit board and the battery assembly.

US Pat. No. 10,601,011

COMPOSITION FOR SECONDARY BATTERY POROUS MEMBRANE, POROUS MEMBRANE FOR SECONDARY BATTERY, AND SECONDARY BATTERY

ZEON CORPORATION, Chiyod...

1. A composition for a secondary battery porous membrane comprising:inorganic oxide particles X;
a metal hydroxide Y;
a binder;
a wetting agent;
and water, wherein
the metal hydroxide Y is a divalent or trivalent hydroxide,
the metal hydroxide Y is contained in an amount of at least 0.001 parts by mass and not more than 10 parts by mass per 100 parts by mass of the inorganic oxide particles X, and
the wetting agent is at least one selected from the group consisting of an ethylene oxide-propylene oxide copolymer and a monovalent low-molecular weight anionic surfactant.

US Pat. No. 10,601,010

RECOMBINATION VENT CAP

1. A vent cap assembly for recombining water for a battery, the vent cap assembly comprising:a cylindrical base having an upper portion and a lower portion integrally formed with the upper portion of the base, the lower portion of the base configured to be inserted into a vent port of the battery, and wherein the upper portion of the base has a diameter larger than a diameter of the lower portion of the base;
a cap enclosing the cylindrical base; and
a catalyst component received in the base configured to hydronate hydrogen and oxygen to water.

US Pat. No. 10,601,007

COOLING PLATE FOR A BATTERY CELL IN THE FORM OF A MOUNTING PLATE

Robert Bosch GmbH, Stutt...

1. A battery cell module comprising:a cooling plate (10) for battery cells (40), wherein the cooling plate (10) is in the form of a mounting plate and has mounting elements (12) configured for directly mounting the cooling plate (10) into a motor vehicle,
characterized in that the cooling plate (10), together with a first housing (20), forms a first closed-off space (30) for accommodating battery cells (40),
wherein the cooling plate (10), together with a second housing (20), forms a second closed-off space (30) for accommodating battery cells (40),
wherein the second closed-off space (30) is separated from the first closed-off space;
wherein the first housing (20) includes an outer periphery;
wherein the cooling plate (10) includes an outer periphery; and
wherein the entire outer periphery of the cooling plate (10) is outside of the outer periphery of the first housing (20).

US Pat. No. 10,601,000

METHOD FOR PRODUCING ORGANIC DEVICE

SUMITOMO CHEMICAL COMPANY...

1. A method for producing an organic device in which a first electrode layer, a single or multiple organic functional layers, and a second electrode layer are arranged on one main surface of a support substrate having flexibility in this order, the method comprising:a first forming step of forming the first electrode layer and at least one layer of the organic functional layers on the support substrate to produce a support substrate with an organic functional layer;
a winding step of winding the support substrate with an organic functional layer and a protective film by arranging the protective film on the organic functional layer after the first forming step;
a peeling step of feeding out the protective film and the support substrate with the at least one layer of the organic functional layers that have been wound in, and peeling off the protective film before forming at least one layer selected from the second electrode layer and an organic functional layer not formed in the first forming step and being one of the organic functional layers comprising the multiple organic functional layers;
a heating step of heating the support substrate with an organic functional layer before forming at least one layer selected from the second electrode layer and an organic functional layer not formed in the first forming step and being one of the organic functional layers comprising the multiple organic functional layers, after the peeling step; and
a second forming step of forming at least one layer selected from the second electrode layer and an organic functional layer not formed in the first forming step and being one of the organic functional layers comprising the multiple organic functional layers, on the support substrate with an organic functional layer, after the heating step.

US Pat. No. 10,600,995

DISPLAY DEVICE AND ORGANIC LUMINESCENT DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A method of manufacturing an electroluminescent device, the method comprising:forming a lower structure having a peripheral area and an emission area, the emission area being surrounded by the peripheral area and comprising an electroluminescent unit comprising a lower electrode, an electroluminescent layer on the lower electrode, and an upper electrode on the electroluminescent layer;
forming a passivation film on the upper electrode by an evaporation process such that an outline of the passivation film is located outside an outline of the upper electrode, the passivation film comprising an inorganic material having a substantially insulating property; and
forming a flexible encapsulation multilayer on the emission area and the peripheral area of the lower structure, the flexible encapsulation multilayer comprising at least three layers and having a bottom surface comprising only at least one inorganic material deposited by at least one non-evaporation process; and
wherein a surface of the peripheral area comprises an inorganic surface portion located outside the upper electrode in a plan view and substantially surrounding the emission area of the lower structure, and
wherein an entirety of the inorganic surface portion directly contacts the bottom surface of the flexible encapsulation multilayer.

US Pat. No. 10,600,994

ORGANIC LIGHT-EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic light-emitting display (OLED) device, comprising:a pixel drive circuit and an organic light-emitting element on an array substrate;
a passivation layer comprising an inorganic thin film including an organosilicon compound, the passivation layer covering the pixel drive circuit and the organic light-emitting element to block permeation of moisture, wherein an amount of Si—CH3 bonds in the passivation layer is less than 1/1000 of an amount of Si—O bonds in the passivation layer; and
an adhesive layer on the passivation layer.

US Pat. No. 10,600,987

ELECTROLUMINESCENT DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An electroluminescent display device comprising:a first electrode;
a hole auxiliary layer on the first electrode;
a light emitting material layer on the hole auxiliary layer;
a capping layer on the light emitting material layer; and
a single-layer second electrode between the capping layer and the light emitting layer, the single-layer second electrode being on and in direct contact with the light emitting material layer and the capping layer,
the single-layer second electrode including a first metal that is doped with a second metal material, the second metal material having a refractive index of 1.4 or higher,
wherein a content of the second metal material is within the range of about 2% to 5% of a content of the first metal by weight;
wherein the first metal includes an alloy of magnesium and silver;
wherein a content of silver is equal to or more than a content of magnesium; and
wherein a content ratio of magnesium and silver is within a range of 1:1 to 1:5.

US Pat. No. 10,600,985

ORGANIC ELECTROLUMINESCENCE DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. An organic electroluminescence display apparatus comprising:a substrate;
an insulating layer disposed on the substrate, the insulating layer comprising: a flat surface; and a first concave surface and a second concave surface extending from one end and another end of the flat surface, respectively;
a first electrode on the insulating layer, the first electrode comprising: a first concave electrode surface overlapping with the first concave surface; a second concave electrode surface overlapping with the second concave surface; and a flat electrode surface overlapping with the flat surface;
an organic layer on the first electrode;
a second electrode on the organic layer; and
a plurality of light shielding members on the second electrode and comprising a first light shielding member and a second light shielding member arranged with an opening therebetween, the opening overlapping with the organic layer,
wherein one end of the first light shielding member is away from the opening,
wherein a first shortest distance is defined as a shortest distance from the one end of the first light shielding member to a first boundary axis between the first concave surface and the flat surface, a second shortest distance is defined as a shortest distance from another end of the first light shielding member to the first boundary axis, the another end of the first light shielding member being adjacent to the opening, and a third shortest distance is defined as a shortest distance from the insulating layer to the first light shielding member, and
wherein the first shortest distance is greater than twice the third shortest distance, and
wherein the second shortest distance is from 1 ?m to 100 ?m.

US Pat. No. 10,600,984

PRODUCTION METHOD OF ORGANIC EL DEVICE

SUMITOMO CHEMICAL COMPANY...

1. A method for producing an organic EL device having an anode, a cathode, at least one organic functional layer disposed between the anode and the cathode, and a sealing layer, comprisinga step of forming the anode, a step of forming the cathode, a step of forming the at least one organic functional layer and a step of forming the sealing layer,
wherein the average concentration: A (ppm) of a sulfur oxide to which the organic EL device during production is exposed from initiation time of the step of forming the at least one organic functional layer until termination time of the step of forming the sealing layer and the exposure time thereof: B (sec) satisfy the formula (1-1):
0.2315?A×B<2.2  (1-1)wherein the exposure time thereof B(sec) means the exposure time which organic EL device during production is exposed to a sulfur oxide from initiation time of the step of forming the at least one organic functional layer until termination time of the step of forming the sealing layer;wherein the organic EL device is a blue organic EL device; and
wherein light emission lifetime of the EL device is improved by exposing the EL device to an amount of sulfur oxide that satisfies formula (1-1).

US Pat. No. 10,600,982

ELECTROLUMINESCENCE DEVICE AND METHOD FOR PRODUCING SAME

SHARP KABUSHIKI KAISHA, ...

1. An electroluminescence device comprising:a base material having flexibility; and
a plurality of layers including a function layer including an electroluminescence element provided on the base material,
the plurality of layers further including:
a sealing film configured to seal the electroluminescence element;
a first adjustment layer provided at an end portion of the electroluminescence device on one side in a film thickness direction and configured to adjust a neutral surface of the electroluminescence device; and
a second adjustment layer provided at an end portion of the electroluminescence device on another side in the film thickness direction and configured to adjust a neutral surface of the electroluminescence device, wherein
the first adjustment layer and the second adjustment layer use such materials that have a same thickness and a same Young's modulus; and
the first adjustment layer and the second adjustment layer adjust a maximum value of a distortion rate in the function layer to be 1% or less.

US Pat. No. 10,600,981

EXCIPLEX-SENSITIZED FLUORESCENCE LIGHT EMITTING SYSTEM

Universal Display Corpora...

1. An organic light emitting device comprising:an anode;
a cathode; and
an emissive layer disposed between the anode and the cathode, the emissive layer comprising:
a first sub-layer comprising a first compound and a second compound; and
a second sub-layer comprising the first compound, the second compound, and a fluorescent third compound;
wherein the first compound and the second compound form an exciplex;
wherein the fluorescent third compound is not present in the first sub-layer; and
wherein emission from the exciplex occurs within an energy region that overlaps an excitation band of the fluorescent third compound.

US Pat. No. 10,600,979

QUANTUM DOT DISPLAY DEVICE AND MANUFACTURE METHOD THEREOF

Shenzhen China Star Optoe...

1. A quantum dot display device, comprising:a flexible substrate;
a first electrode layer disposed on the flexible substrate;
a component combination layer disposed on the first electrode layers; and
a second electrode layer disposed on the component combination layer;
wherein the first electrode layer is one of an anode and a cathode of the quantum dot display device and the second electrode layer is the other one of the anode and the cathode;
wherein the component combination layer comprises an electron transport layer, a carbon quantum dot light emitting layer, a hole transport layer, and a hole injection layer;
wherein the first electrode layer and the second electrode layer are made of organic materials without having metal materials, the material of the first electrode layer comprises one of a fullerene-graphene material and a carbon nanotube-graphene material and the material of the second electrode layer comprises the other one of the fullerene-graphene material and the carbon nanotube-graphene material;
wherein the first electrode layer made of the fullerene-graphene material comprises a first graphene layer and a first fullerene layer, the second electrode layer made of the carbon nanotube-graphene material comprises a second graphene layer and a first carbon nanotube layer, the first graphene layer and the first fullerene layer are combined together, and the second graphene layer and the first carbon nanotube layer are combined together; or the first electrode layer made of the carbon nanotube-graphene material comprises a third graphene layer and a second carbon nanotube layer, the second electrode layer made of the fullerene-graphene material comprises a fourth graphene layer and a second fullerene layer, the third graphene layer and the second carbon nanotube layer are combined together, and the fourth graphene layer and the second fullerene layer are combined together;
wherein the first electrode layer made of the fullerene-graphene material comprises at least two first graphene layers and at least two first fullerene layers, the second electrode layer made of the carbon nanotube-graphene material comprises at least two second graphene layers and at least two first carbon nanotube layers, the at least two first graphene layers and the at least two first fullerene layers are combined together, and the at least two second graphene layers and the at least two first carbon nanotube layer are combined togethers; or the first electrode layer made of the carbon nanotube-graphene material comprises at least two third graphene layers and at least two second carbon nanotube layers, the second electrode layer made of the fullerene-graphene material comprises at least two fourth graphene layers and at least two second fullerene layers, the at least two third graphene layers and the at least two second carbon nanotube layers are combined together, and the at least two fourth graphene layers and the at least two second fullerene layers are combined together;
wherein the hole injection layer, the hole transport layer, the carbon quantum dot light emitting layer, and the electron transport layer are disposed on the first electrode layer according to a preset order, and the preset order is the hole injection layer, the hole transport layer, the carbon quantum dot light emitting layer, and the electron transport layer or the preset order is the electron transport layer, the carbon quantum dot light emitting layer, the hole transport layer, and the hole injection layer;
wherein the carbon quantum dot light emitting layer comprises carbon quantum dots or graphene quantum dots.

US Pat. No. 10,600,964

HIGHLY CRYSTALLINE ELECTRICALLY CONDUCTING ORGANIC MATERIALS, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME

ROHM AND HAAS ELECTRONIC ...

1. A melted and annealed composition comprising:a composition comprising a regioregular oligothiophene, a benzothiophene oligomer, and/or a compound of formula (X):

where R3 and R4 can be the same or different and are independently a hydrogen, an alkyl group having 2 to 10 carbon atoms, an alkoxyalkyl group having 2 to 10 carbon atoms, a polyalkylene oxide group, an alkoxy group having 1 to 13 carbon atoms, an alkenyl group having 2 to 13 carbon atoms, an alkenyloxy group having 2 to 13 carbon atoms, a cycloalkyl group having 3 to 6 carbon atoms, a cycloalkoxy having 3 to 6 carbon atoms, an aryl group having 6 to 14 carbon atoms, an aryloxy group having 6 to 14 carbon atoms, an arylalkyl group having 7 to 13 carbon atoms, an alkylaryl group having 7 to 13 carbon atoms, or an alkylaryloxy group having 7 to 13 carbon atoms;
where the regioregular oligothiophene, the benzothiophene oligomer, and the compound of formula (X) each have a number average molecular weight of less than or equal to 475 grams per mole; and
where the composition is melted and then annealed for 5 to 1,000 seconds at a temperature between a melting point and a glass transition temperature of the composition to form the melted and annealed composition; wherein the melted and annealed composition has a charge mobility that is greater than the composition that is either not annealed or annealed at the same temperature between the melting point and the glass transition temperature but without being subjected to prior melting.

US Pat. No. 10,600,963

METAL PLATE, METHOD OF MANUFACTURING METAL PLATE, AND METHOD OF MANUFACTURING MASK BY USING METAL PLATE

Dai Nippon Printing Co., ...

1. A method of manufacturing an elongated metal plate used for manufacturing a deposition mask having a plurality of through-holes foil led in the metal plate, the method comprising:providing a base metal made of an invar material containing 34-38% by weight of nickel;
a rolling step of rolling the base metal to obtain the metal plate having a plate thickness of 80 ?m or less and an average value of plate thicknesses in a longitudinal direction within a ±3% range around a predetermined value; and
a cutting step of cutting off one end and the other end of the metal plate in a width direction over a predetermined range;
wherein the following two conditions (1) and (2) are satisfied as to a variation in plate thickness of the metal plate:(1) when an average value of the plate thicknesses of the metal plate in the longitudinal direction is represented as A, and a value obtained by multiplying a standard deviation of the plate thicknesses of the metal plate in the longitudinal direction by 3 is represented as B, (B/A)×100(%) is 5% or less; and(2) when a value obtained by multiplying a standard deviation of the plate thicknesses of the metal plate in a width direction by 3 is represented as C, and a value of a plate thickness of the metal plate at a central portion in the width direction, which is obtained when plate thicknesses of the metal plate are measured along the width direction in order to calculate the standard deviation of the plate thicknesses of the metal plate in the width direction, is represented as X, (C/X)×100(%) is 3% or less.

US Pat. No. 10,600,961

SCALABLE AND LOW-VOLTAGE ELECTROFORMING-FREE NANOSCALE VANADIUM DIOXIDE THRESHOLD SWITCH DEVICES AND RELAXATION OSCILLATORS WITH CURRENT CONTROLLED NEGATIVE DIFFERENTIAL RESISTANCE

HRL Laboratories, LLC, M...

1. A threshold switch device comprising:a complementary metal-oxide-semiconductor (CMOS)-compatible substrate;
a first electrode on the CMOS-compatible substrate, the first electrode extending along a first direction;
a second electrode on the first electrode, the second electrode extending along a second direction crossing the first direction; and
a switching layer between the first electrode and the second electrode, the switching layer providing a first contact with the first electrode and a second contact with the second electrode at least along a thickness direction (TD) overlap of the device between the first electrode and the second electrode;
the switching layer being a thin film substantially composed of polycrystalline vanadium dioxide (VO2) in the form of nanocrystals that are columnar and vertically continuous from a bottom edge to a top edge of the thin film, the switching layer having no epitaxial relationship with the CMOS-compatible substrate.

US Pat. No. 10,600,959

DOPANT-DRIVEN PHASE TRANSITIONS IN CORRELATED METAL OXIDES

President and Fellows of ...

1. A system comprising:a film of samarium perovskite nickelate, the film of samarium perovskite nickelate having at least one catalyst electrode deposited onto a surface thereof;
the film of samarium perovskite nickelate including a plurality of dopant ions and a plurality of electronic carriers introduced therein so as to chemically induce a non-volatile increase in resistivity of the samarium perovskite nickelate;
wherein the non-volatile increase in resistivity is between three and eight orders of magnitude.

US Pat. No. 10,600,954

METHOD FOR PRODUCING HERMETIC PACKAGE

NIPPON ELECTRIC GLASS CO....

1. A method of producing a hermetic package, the method comprising the steps of:preparing a ceramic base and forming a sealing material layer on the ceramic base;
preparing a glass substrate and arranging the ceramic base and the glass substrate so that the glass substrate is brought into contact with the sealing material layer on the ceramic base; and
irradiating the sealing material layer with laser light from a glass substrate side to seal the ceramic base and the glass substrate with each other through intermediation of the sealing material layer, to thereby provide a hermetic package,
wherein the ceramic base comprises a base part and a frame part formed on the base part and the sealing material layer is formed on a top of the frame part, and
wherein the forming a sealing material layer is performed by applying and firing a sealing material paste to form a sealing material layer formed of a sintered body of a sealing material on the ceramic base.

US Pat. No. 10,600,948

PACKAGE WITH THERMOELECTRIC POWER FEEDBACK LOOP

Intel Corporation, Santa...

1. A system comprising:an electronic device comprising one or more integrated circuit (IC) packages, comprising:
one or more IC chips disposed on a substrate;
one or more thermoelectric power feedback systems, comprising:
one or more thermoelectric devices coupled to the one or more IC chips to generate power based on heat produced by the one or more IC chips; and
a power routing system configured to directly, electrically couple the one or more thermoelectric devices to a power grid disposed on the substrate such that the generated power is directly fed to the one or more IC chips; and
a plurality of conductive contacts configured to couple the one or more IC chips to a printed circuit board of the electronic device, wherein the plurality of conductive contacts comprises a plurality of power balls and a plurality of input/output (I/O) balls, wherein the power routing system is configured to supply the generated power to the one or more IC chips such that one or more of the plurality of conductive contacts that would otherwise be implemented as one or more power balls to supply a supply power equivalent to the generated power, are implemented as one or more I/O balls.

US Pat. No. 10,600,944

LEAD FRAME, PACKAGE AND LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A lead frame comprising:electrodes;
hanger leads disposed spaced apart from the electrodes; and
an outer frame attached to the electrodes and the hanger leads,
the lead frame partially defining a box-shaped package, which has a first recess for mounting a light emitting element, as combined with a support member made of a resin for supporting the electrodes, the first recess having an opening defined by lateral walls formed by the support member and a bottom face at least partially formed by the electrodes,
at least a portion of lower faces of the electrodes, at least a portion of lower faces of the hanger leads, and at least a portion of a lower face of a planned formation area for the support member being coplanarly formed,
lower face edges of the electrodes being rounded while upper face edges of the electrodes are not rounded; and
upper face edges of the hanger leads being rounded while lower face edges of the hanger leads are not rounded.

US Pat. No. 10,600,934

LIGHT EMITTING DEVICE WITH TRANSPARENT CONDUCTIVE GROUP-III NITRIDE LAYER

EXALOS AG, Schlieren (CH...

1. A method for manufacturing a light-emitting semiconductor device, the method comprising: depositing an n-type layer composed of a nitride of at least one group-III element; depositing a p-type layer over the n-type layer, the p-type layer composed of a nitride of at least one group-III element; and depositing a transparent, current spreading layer on the p-type layer, the transparent, current spreading layer being n-type and composed of a nitride of at least one group-III element, the transparent, current spreading layer being configured to be transparent to light emitted from the light-emitting semiconductor structure and of sufficiently high electrical conductivity to provide lateral spreading of injection current for the light-emitting semiconductor structure within the transparent, current spreading layer; and producing a current aperture stop between the transparent, current spreading layer and the p-type layer from a part of the p-type layer by effecting a diffusion of foreign atoms locally into the p-type layer to increase the local resistivity of said part of the p-type layer.

US Pat. No. 10,600,933

VERTICAL STRUCTURE LEDS

LG INNOTEK CO., LTD., Se...

1. A light-emitting device, comprising:a conductive support structure comprising a metal;
a GaN-based semiconductor structure disposed on the conductive support structure, the GaN-based semiconductor structure including a p-type GaN-based layer, a GaN-based active layer and an n-type GaN-based layer, wherein the GaN-based semiconductor structure has a first surface, a side surface and a second surface, wherein the first surface, relative to the second surface, is proximate to the conductive support structure, wherein the second surface is opposite to the first surface, wherein the conductive support structure is thicker than the p-type GaN-based semiconductor layer, and wherein the conductive support structure is thicker than the n-type GaN-based semiconductor layer;
a p-type electrode disposed on the conductive support structure;
an n-type electrode disposed on the second surface of the GaN-based semiconductor structure; and
a passivation layer disposed on the side surface and the second surface of the GaN-based semiconductor structure,
wherein the passivation layer comprises:
a first portion disposed on the second surface of the GaN-based semiconductor structure; and
a second portion disposed between the conductive support structure and the first surface of the GaN-based semiconductor structure,
wherein the first portion is overlapped with the second portion in a thickness direction of the GaN-based semiconductor structure, and
wherein the first portion has a width greater than a width of the second portion.

US Pat. No. 10,600,910

HIGH VOLTAGE (HV) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) IN SEMICONDUCTOR ON INSULATOR (SOI) TECHNOLOGY

QUALCOMM Incorporated, S...

1. An integrated circuit, comprising:a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer, the MOSFET including a source region, a drain region, a front gate, and an extended drain region between the drain region and a well proximate the front gate; and
a plurality of discrete back gates on a second surface opposite the first surface of the insulator layer and overlapped by the extended drain region.

US Pat. No. 10,600,902

SELF-REPAIRING FIELD EFFECT TRANSISITOR

Vishay Siliconix, LLC, S...

1. A device comprising:a plurality of source contacts within a field effect transistor;
a plurality of field effect transistor cells within the field effect transistor, wherein each cell includes a corresponding source contact;
a source interconnect within the field effect transistor; and
a plurality of source fuse links disposed between the source interconnect and corresponding ones of the plurality of source contacts in corresponding trenches through an encapsulate layer, wherein a top of a gate of at least one of the plurality of field effect transistor cell is below the bottom of the encapsulate layer, wherein the encapsulate layer is disposed between the source interconnect and the plurality of source contacts within the field effect transistor, and wherein each source contact is coupled to the source interconnect by a given one of the plurality of source fuse links configured to blow in response to a high current.

US Pat. No. 10,600,901

COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

FUJITSU LIMITED, Kawasak...

1. A compound semiconductor device, comprising:a carrier transit layer;
a carrier supply layer that is formed over the carrier transit layer and is made of InAlN; and
a spacer layer that is formed between the carrier transit layer and the carrier supply layer and has a stacked structure of a layer of InAlGaN contacts with the carrier transit layer and a layer of AlGaN contacts with the carrier supply layer, wherein
a composition ratio of In of the layer of InAlGaN is not less than 0.05 nor more than 0.2 and
a composition ratio of Al of the layer of AlGaN is not less than 0.5 nor more than 0.7.

US Pat. No. 10,600,900

SEMICONDUCTOR DEVICE AND ELECTRIC APPARATUS

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a nitride semiconductor layer;
a first gate electrode;
a source electrode provided on the nitride semiconductor layer;
a drain electrode provided on the nitride semiconductor layer;
a first insulating layer provided between the nitride semiconductor layer and the first gate electrode;
a first conductor layer provided between the first gate electrode and the first insulating layer, and suppressing generation of charges at respective interfaces with adjacent layers;
a first dielectric layer provided between the first gate electrode and the first conductor layer; and
a second dielectric layer provided between the first gate electrode and the first dielectric layer,
wherein dipoles exist at an interface between the first dielectric layer and the second dielectric layer.

US Pat. No. 10,600,897

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:an active region through which main current flows, the active region provided in a semiconductor substrate of a first conductivity type;
a termination region surrounding a periphery of the active region;
a first semiconductor region of a second conductivity type provided in the active region, in a surface layer on a first main surface side of the semiconductor substrate;
a second semiconductor region of the first conductivity type selectively provided in the first semiconductor region;
a third semiconductor region of the second conductivity type selectively provided in the first semiconductor region, the third semiconductor region having an impurity concentration that is higher than an impurity concentration of the first semiconductor region;
a fourth semiconductor region of the second conductivity type selectively provided in the termination region, in the surface layer on the first main surface side of the semiconductor substrate;
a fifth semiconductor region of the first conductivity type that is a region of the semiconductor substrate excluding the first semiconductor region and the fourth semiconductor region;
a gate insulating film provided in contact with a region of the first semiconductor region, the region between the fifth semiconductor region and the second semiconductor region;
a gate electrode provided opposing the first semiconductor region, across the gate insulating film;
an interlayer insulating film provided on a first main surface of the semiconductor substrate and covering the second semiconductor region, the third semiconductor region, the fourth semiconductor region and the gate electrode;
a first contact hole opened in the interlayer insulating film and exposing the second semiconductor region and the third semiconductor region;
a plurality of second contact holes opened in the interlayer insulating film, each of the plurality of second contact holes selectively exposing the fourth semiconductor region;
a first metal film provided along inner walls of the plurality of second contact holes, the first metal film having an adhesive property with the semiconductor substrate and forming an ohmic contact with the semiconductor substrate;
a second metal film embedded on the first metal film, in the plurality of second contact holes;
a first electrode provided on the interlayer insulating film and electrically connected with the first semiconductor region via the second semiconductor region and the third semiconductor region, in the first contact hole, the first electrode further electrically connected with the fourth semiconductor region via the second metal film and the first metal film, in the plurality of second contact holes; and
a second electrode provided at a second main surface of the semiconductor substrate.

US Pat. No. 10,600,893

INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES

INTERNATIONAL BUSINESS MA...

1. A method, comprising:forming a plurality of nanowire structures on a surface of an electrically conductive layer by applying an electric potential to the electrically conductive layer through a wiring path;
forming a discontinuity in the wiring path after the plurality of nanowire structures are formed; and
depositing an insulator layer over the plurality of nanowire structures so as to cover a top surface of the plurality of nanowire structures with the insulator layer, wherein before the forming the plurality of nanowire structures, a barrier layer is formed on an entire surface of a semiconductor structure, the method further comprising:
etching a portion of the barrier layer on a drain region of the semiconductor structure;
depositing an isolation layer on the drain region; and
depositing the electrically conductive layer on the isolation layer.

US Pat. No. 10,600,892

INTEGRATED FERROELECTRIC CAPACITOR/ FIELD EFFECT TRANSISTOR STRUCTURE

Samsung Electronics Co., ...

1. A method of forming a semiconductor structure, the method comprising:providing a functional gate structure located on a surface of a semiconductor material portion and laterally surrounded by a middle-of-the-line (MOL) dielectric material;
recessing the functional gate structure to provide a capacitor cavity located above a remaining portion of the functional gate structure; and
forming a ferroelectric capacitor in the capacitor cavity, the ferroelectric capacitor comprising a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure, wherein the bottom electrode structure is located entirely beneath the U-shaped ferroelectric material liner.

US Pat. No. 10,600,886

VERTICAL FIELD EFFECT TRANSISTORS WITH BOTTOM SOURCE/DRAIN EPITAXY

International Business Ma...

20. A vertical fin field-effect-transistor comprising at least:a substrate;
a first source/drain layer comprising a plurality of pillar structures, wherein each pillar structure of the plurality of pillar structures comprises a tapered configuration;
a plurality of fins each disposed on and in contact with a pillar structure in the plurality of pillar structures;
a doped epitaxy layer grown from the first source/drain layer in contact with the plurality of fins and the plurality of pillar structures;
a gate structure in contact with the plurality of fins; and
a second source/drain layer disposed on gate structure.

US Pat. No. 10,600,872

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A silicon carbide semiconductor device, comprising:a silicon carbide semiconductor substrate of a first conductivity type, having a front surface;
a first silicon carbide layer of the first conductivity type provided on the front surface of the substrate, the first silicon carbide layer having a first surface, and a second surface opposite to the first surface and facing the front surface of the substrate;
a second silicon carbide layer of the first conductivity type selectively provided in the first surface of the first silicon carbide layer, the second silicon carbide layer having a first surface, and a second surface opposite to the first surface and facing the first surface of the first silicon carbide layer;
a third silicon carbide layer of a second conductivity selectively provided on the first surface of the second silicon carbide layer, the third silicon carbide layer having a first surface, and a second surface opposite to the first surface and facing the first surface of the second silicon carbide layer;
a trench at least penetrating the third silicon carbide layer and reaching the second silicon carbide layer; and
a gate insulating film provided on a surface of the trench, the gate insulating film having a first surface, and a second surface opposite to the first surface and facing the trench, a part of the first surface facing the second silicon carbide layer, wherein
fluorine and chlorine are both undetectable
in the gate insulating film,
at a boundary between the first surface of the gate insulating film and the second silicon carbide layer, or
at a boundary between the trench and the second surface of the gate insulating film.

US Pat. No. 10,600,862

HIGH VOLTAGE TERMINATION STRUCTURE OF A POWER SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal and a second load terminal and including a drift region with dopants of a first conductivity type;
an active region having at least one power cell that extends at least partially into the semiconductor body and that is electrically connected with the first load terminal and that comprises a part of the drift region, the at least one power cell comprising a section of the drift region and being configured to conduct a load current between the terminals and to block a blocking voltage applied between the terminals;
a chip edge that laterally terminates the semiconductor body;
a non-active termination structure arranged in between the chip edge and the active region and comprising an ohmic layer, a first semiconductor region and a second semiconductor region, each comprising dopants of a second conductivity type, wherein the first semiconductor region is electrically connected to the first load terminal and laterally overlaps therewith;
wherein the ohmic layer:
is made of amorphous silicon or semi-insulating polycrystalline silicon;
is arranged above a surface of the semiconductor body;
forms an ohmic connection between an electrical potential of the first load terminal and an electrical potential of the second load terminal;
laterally overlaps with the second semiconductor region; and
is laterally structured along the ohmic connection.

US Pat. No. 10,600,845

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device, comprising:a plurality of global bit lines extending along a first direction;
a pair of word lines separated from each other, extending along a second direction;
a bit line between the pair of word lines, extending along a third direction different from the first direction and the second direction;
variable resistivity layers between the bit line and each word line of the pair of word lines, the variable resistivity layers functioning as a memory element;
a selector between the bit line and one of the plurality of global bit lines,
wherein the selector includes:
a semiconductor layer coupled with the bit line and the one of the plurality of global bit lines, and
a pair of gates on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating layers therebetween; and
a control circuit configured to perform respective operations of reading, writing, and erasing on the memory element.

US Pat. No. 10,600,834

IMAGE SENSOR CAPABLE OF IMPROVING COLOR SHADING EFFECT

SK hynix Inc., Gyeonggi-...

1. An image sensor, comprising:a pixel array where a plurality of pixel groups are arrayed,
wherein each of the pixel groups comprises:
a first pixel suitable for sensing a first color signal that is color-separated through a first color filter; and
a second pixel suitable for sensing a second color signal that is color-separated through a second color filter and has a longer wavelength than the first color signal,
wherein a volume of the first color filter positioned in a peripheral area of the pixel array is different from a volume of the first color filter positioned in a central area of the pixel array, or
wherein a volume of the second color filter positioned in the peripheral area of the pixel array is different from a volume of the second color filter positioned in the central area of the pixel array.

US Pat. No. 10,600,831

IMAGE PICKUP APPARATUS, ENDOSCOPE AND IMAGE PICKUP APPARATUS MANUFACTURING METHOD

OLYMPUS CORPORATION, Tok...

1. An image pickup apparatus comprising:an image pickup device that is a rectangular parallelepiped semiconductor including a light receiving face configured to receive incident light, a back face opposite to the light receiving face and four side faces, a light receiving portion being formed on the light receiving face;
an optical member bonded to the light receiving face; and
a wiring board bonded to the back face; wherein
an alignment mark is present on each of two orthogonal side faces among the side faces of the image pickup device, the alignment mark being at a predetermined relative position relative to the light receiving portion.

US Pat. No. 10,600,830

SENSOR PACKAGE STRUCTURE

KINGPAK TECHNOLOGY INC., ...

1. A sensor package structure, comprising:a substrate having an upper surface and a lower surface opposing to the upper surface, wherein the substrate includes a plurality of solder pads arranged on the upper surface;
a sensor chip having a top surface and a bottom surface opposing to the top surface, wherein the bottom surface of the sensor chip is disposed directly on the upper surface of the substrate and surrounded by the solder pads, and the sensor chip includes a plurality of connecting pads arranged on the top surface;
a plurality of wires, wherein one end of the wires are respectively connected to the solder pads, and the other end of the wires are respectively connected to the connecting pads;
a transparent layer having a first surface and a second surface opposing to the first surface, wherein the second surface has a central region facing the sensor chip and a ring-shaped supporting region enclosing the central region;
a support disposed directly on the upper surface of the substrate and arranged outside the sensor chip, wherein a top side of the support abuts against the supporting region of the transparent layer, a part of each of the wires is embedded in the support, and a height from the upper surface of the substrate to the top side of the support is larger than a height from the upper surface of the substrate to a top of any of the wires, and wherein the support includes:
a supporting layer disposed directly on the upper surface of the substrate; and
a combining layer disposed directly on the supporting layer, wherein a top side of the combining layer abuts against the supporting region of the transparent layer; and
a packaging compound disposed directly on the upper surface of the substrate and directly connected to a side edge of the support and a side edge of the transparent layer,
wherein a height from the upper surface of the substrate to a top of the supporting layer is smaller than or equal to a height from the upper surface of the substrate to the top surface of the sensor chip, the part of each of the wires is embedded in the combining layer, and the supporting layer does not contact with any of the wires, and
wherein the supporting layer is disposed on the upper surface of the substrate and arranged between the sensor chip and the solder pads.

US Pat. No. 10,600,827

IMAGE SENSOR AND IMAGE-CAPTURING DEVICE

NIKON CORPORATION, Tokyo...

1. An image sensor, comprising:a photoelectric conversion unit that photoelectrically converts light transmitted through a microlens;
an accumulation unit that accumulates an electric charge generated by the photoelectric conversion unit;
a light shielding unit that blocks light which enters the accumulation unit; and
a readout unit that reads out a signal based on a voltage of the accumulation unit, wherein:
a part of the photoelectric conversion unit is provided in the micro lens side of the light shielding unit along an optical axis of the microlens,
the accumulation unit and the readout unit are provided along an optical axis direction of the microlens,
the light shielding unit has an opening, and
at least a part of the photoelectric conversion unit passes through the opening.

US Pat. No. 10,600,825

MANUFACTURING METHOD FOR TFT ARRAY SUBSTRATE AND TFT ARRAY SUBSTRATE

SHENZHEN CHINA STAR OPTOE...

1. A manufacturing method for thin film transistor (TFT) array substrate, comprising:providing a substrate;
forming a first buffer layer on the substrate; the first buffer layer being disposed with a plurality of arc protrusions or a plurality of arc recesses;
forming a second buffer layer on the first buffer layer; forming an amorphous silicon (a-Si) layer on the second buffer layer, performing an excimer laser annealing (ELA) on the a-Si layer to form a polysilicon layer; and
patterning the polysilicon layer to form a plurality of active layers respectively located above the plurality of arc protrusions or the plurality of arc recesses.

US Pat. No. 10,600,824

DISPLAY DEVICE HAVING A SHIELDING LAYER

Samsung Display Co., Ltd....

1. A display device comprising:a flexible substrate;
a buffer layer on the flexible substrate and including an inorganic material;
a display area including a plurality of pixels, wherein each pixel includes a pixel circuit on the buffer layer and a display element electrically connected to the pixel circuit, and the pixel circuit includes a first thin film transistor (TFT), a second TFT, and a storage capacitor; and
a non-display area adjacent to the display area,
wherein the flexible substrate comprises:
at least one base layer;
at least one inorganic barrier layer; and
a shielding layer including a portion having a certain area and an opening adjacent to the portion.

US Pat. No. 10,600,822

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:a transistor substrate including a first lead-out wiring to be supplied with a first video signal, a second lead-out wiring to be supplied with a second video signal, a third lead-out wiring to be supplied with a third video signal, and an insulating film; and
a semiconductor chip electrically connected to the first to third lead-out wirings, wherein
one of the first to third lead-out wirings overlaps with other two of the first to third lead-out wirings.

US Pat. No. 10,600,821

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A manufacturing method of an organic light emitting diode display device, comprising:preparing a thin film transistor layer on a glass substrate;
preparing a plurality of organic light emitting diode elements on a thin film transistor layer;
preparing a barrier layer and a buffer layer on the thin film transistor layer, wherein the barrier layer covers the plurality of organic light emitting diode elements;
preparing a plurality of island structures on the barrier layer or on the buffer layer, wherein the plurality of island structures are located a non-light emitting region on the barrier layer or the buffer layer; wherein a shape of the island structure is one of a pyramid shape, a lens shape and a particle shape;
preparing the plurality of island structures on the barrier layer or on the buffer layer specifically comprises:
patterning the barrier layer or the buffer layer by one of photolithography, transferring and laser etching to obtain the plurality of island structures, or preparing the plurality of island structures on the barrier layer or the buffer layer by inkjet printing;
wherein as the plurality of island structures are prepared on the barrier layer or the buffer layer by inkjet printing, a material of the island structures is an inorganic nanomaterial.

US Pat. No. 10,600,820

ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY AND ELECTRONIC DEVICE

SHENZHEN CHINA STAR OPTOE...

1. An array substrate, wherein the array substrate comprises a fan-out area, a first metal line, a second metal line and a common electrode line insulated from each other and stacked in the fan-out area, the second metal line is located between the first metal line and the common electrode line, and on any cross section perpendicular to the extension path of the first metal line, the first metal line comprises a first end and a second end in a first direction, the second metal line does not exceed the first end in the first direction, and the common electrode line does not exceed the second end in the first direction; wherein on a cross section perpendicular to the extension path of the first metal line, the first metal line is trapezoid shaped, the two ends of the long side in a pair of parallel sides of the trapezoid are respectively the first end and the second end, the two ends of the short side corresponding to the long side are respectively a third end and a fourth end; wherein the third end is located on one side of the first end, and the second metal line does not exceed the third end in the first direction.

US Pat. No. 10,600,819

DISPLAY DEVICE HAVING A PLURALITY OF PAD TERMINALS

Samsung Display Co., Ltd....

1. A display device, comprising:a substrate including a display area to display an image and a pad area positioned around the display area;
a first pad unit disposed on the pad area, and including a first terminal region having a plurality of first pad terminals arranged in a first direction; and
a printed circuit board including a base film and a second pad unit positioned at one side of the base film, the second pad unit being coupled with the first pad unit by contact with the plurality of first pad terminals;
wherein each of the plurality of first pad terminals includes at least three first connection pad terminals arranged in a first row disposed at a first angle lamer than 0° and smaller than 90° relative to the first direction, the plurality of first connection pad terminals being in contact with the second pad unit of the printed circuit board through a conductive ball;
a plurality of second connection pad terminals spaced apart from the plurality of first connection pad terminals, and arranged in a second row disposed at a second angle larger than 0° and smaller than 90° relative to the first direction, the plurality of second connection pad terminals being in contact with the second pad unit of the printed circuit board through another conductive ball; and
a first terminal connection line configured to connect one of the plurality of first connection pad terminals and one of the plurality of second connection pad terminals, and having at least one bent shape, and
wherein the first terminal connection line is disposed in a different layer from that of the first connection pad terminal and the second connection pad terminal.

US Pat. No. 10,600,817

THIN FILM TRANSISTOR AND FLAT DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a thin film transistor (TFT), the TFT including:
a scan line,
an active layer including an oxide semiconductor, the active layer having a first region, a second region, and a third region that are linearly and sequentially aligned along a first direction, the second region being a channel region between the first region and the third region,
an insulating layer between the active layer and the scan line, wherein the scan line, the insulating layer, and the active layer are sequentially stacked on a substrate along a third direction, the insulating layer covering the scan line, the third direction being substantially perpendicular to the first direction,
a first electrode having a first contact portion contacted with the first region of the active layer, and
a second electrode having a second contact portion contacted with the third region of the active layer;
a first capacitor electrode on a substrate;
a second capacitor electrode connected to the second electrode of the TFT, the second capacitor electrode being insulated from the first capacitor electrode; and
a pixel electrode connected to the second electrode of the TFT and to the second capacitor electrode,
wherein the scan line includes a straight portion extending along the first direction,
wherein the first contact portion and the second contact portion overlap with edge portions of the scan line in a second direction, the second direction being substantially perpendicular to the first direction and the third direction,
wherein the straight portion of the scan line includes a first portion that overlaps the first and second contact portions, and second portions that do not overlap the first and second electrodes and disposed at both sides of the first portion in the first direction, and
wherein a width of the first electrode and a width of the second electrode in the second direction are larger than widths of the second portions of the straight portion in the second direction,
the first contact portion overlaps an end portion of the first region of the active layer at one side of the active layer in the first direction, and
the second contact portion overlaps an end portion of the third region of the active layer at an opposite side of the active layer in the first direction.

US Pat. No. 10,600,815

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:a first substrate including a first basement, a scanning line and a signal line, arranged in a display area which displays images, a switching element arranged in the display area and electrically connected to the scanning line and the signal line, and a first conductive layer arranged in a periphery region surrounding the display area and formed from a material different from that of the scanning line;
a second substrate including a second basement opposing the first conductive layer and spaced therefrom, and a second conductive layer, and comprising a first hole which penetrates the second basement; and
a connecting material electrically connecting the first conductive layer and the second conductive layer via the first hole,
wherein the first conductive layer comprises a slit.

US Pat. No. 10,600,813

DISPLAY DEVICE FABRICATED WITH FEWER MASKS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A method of manufacturing a display device, the method comprising:receiving a base substrate comprising a first light blocking area extending in a first direction, a second light blocking area extending in a second direction intersecting the first direction, and a pixel area defined by the first light blocking area and the second light blocking area;
forming a light blocking pattern on the base substrate, at least a portion of the light blocking pattern positioned at the first light blocking area;
forming a data line on the base substrate and at the second light blocking area;
forming a first insulating layer on the light blocking pattern and the data line;
forming a semiconductor layer on the first insulating layer to overlap the light blocking pattern on a plane;
forming a second insulating layer on the semiconductor layer;
forming a color filter on the second insulating layer, the color filter having an island shape and at least a portion of the color filter positioned at the pixel area;
forming a third insulating layer on the second insulating layer and the color filter;
forming a gate wiring on the third insulating layer and at the first light blocking area;
forming a pixel electrode on the third insulating layer, at least a portion of the pixel electrode positioned at the pixel area; and
forming a bridge electrode on the third insulating layer, at least a portion of the bridge electrode positioned at the first light blocking area,
wherein the second insulating layer and the third insulating layer directly contact one another over the semiconductor layer.

US Pat. No. 10,600,812

MANUFACTURING METHOD OF ARRAY SUBSTRATE

Au Optronics Corporation,...

1. A manufacturing method of an array substrate, comprising:forming a plurality of scan lines on a substrate, the substrate having a pixel region and a fan-out region;
forming a plurality of data lines;
forming a plurality of transistors, wherein each of the transistors is electrically connected to the corresponding scan line and the corresponding data line;
forming a plurality of common electrodes;
forming a plurality of pixel electrodes, wherein each of the pixel electrodes is electrically connected to the corresponding transistor;
forming a plurality of first fan-out lines in the fan-out region;
forming a plurality of second fan-out lines in the fan-out region; and
forming a plurality of third fan-out lines in the fan-out region, wherein each of the third fan-out lines comprises:
a transparent conductive layer; and
an auxiliary conductive layer, disposed on the transparent conductive layer and in contact with the transparent conductive layer;
wherein the third fan-out lines and the common electrodes are formed by a same photomask.

US Pat. No. 10,600,811

TFT ARRAY SUBSTRATE AND LCD

WUHAN CHINA STAR OPTOELEC...

1. A thin film transistor (TFT) array substrate, comprising: a base substrate and a planarization layer disposed on the base substrate; one end of the base substrate being provided with a groove, the base substrate comprising a functional area and a peripheral area located outside the functional area; the planarization layer has a first portion corresponding to the functional area of the base substrate; a portion of the first portion adjacent to the groove being disposed with at least one pit; the pit having a depth less than the thickness of the first portion; wherein the planarization layer is formed with a notch that corresponds to the groove of the base substrate and the portion of the first portion of the planarization layer is adjacent to the notch, wherein the pit that is formed in the portion of the first portion of the planarization layer is adjacent to the notch of the planarization layer.

US Pat. No. 10,600,810

BACKSIDE FIN RECESS CONTROL WITH MULTI-HSI OPTION

Intel Corporation, Santa...

1. A semiconductor device, comprising:a first fin comprising:
a first active channel region on a top portion of the first fin;
a first sub-channel region underneath the first active channel region; and
a first active channel height from a top surface of the first active channel region to a top surface of the first sub-channel region; and
a second fin comprising:
a second active channel region on a top portion of the second fin;
a second sub-channel region underneath the second active channel region of the second fin, wherein the first and second sub-channel regions comprise an insulator material;
a second active channel height from a top surface of the second active channel region to a top surface of the second sub-channel region,
wherein the first and second fins have a same height and the first active channel height is substantially different from the second active channel height; and
etch stop layers between the active channel regions and the sub-channel regions, wherein first surfaces of the etch stop layers are in contact with the active channel region and second surfaces of the etch stop layers are in contact with the insulator material of the first and second sub-channel regions.

US Pat. No. 10,600,807

INTEGRATED STRUCTURES AND METHODS OF FORMING VERTICALLY-STACKED MEMORY CELLS

Micron Technology, Inc., ...

1. A method of forming a system, comprising:forming an opening which extends through a gate material, through an insulative material under the gate material, and through a stack of alternating dielectric levels and conductive levels under the insulative material; a first region of the opening within the insulative material being wider along a cross-section than a second region of the opening within the gate material, and being wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels; and
forming semiconductive material within the opening adjacent the insulative material, adjacent the gate material, adjacent the dielectric levels of the stack, and the conductive levels of the stack.

US Pat. No. 10,600,806

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a semiconductor device comprising:forming a channel hole penetrating a molded structure formed on a substrate;
forming a preliminary channel layer on a side surface of the channel hole;
forming a preliminary filling layer on the preliminary channel layer to fill the channel hole;
forming a first recess in the channel hole by removing a part of each of the preliminary channel layer and the preliminary filling layer, wherein a channel layer and a filling layer are formed by the forming of the first recess;
forming a spacer on a side surface of the first recess, the spacer having a bottom hole exposing an upper surface of the filling layer;
removing the filling layer completely via the bottom hole;
forming a preliminary passivation layer to fill the bottom hole;
forming a second recess by removing a part of the preliminary passivation layer and a part of the spacer; and
forming a pad to fill the second recess.

US Pat. No. 10,600,805

VERTICAL MEMORY DEVICES WITH COMMON SOURCE INCLUDING ALTERNATELY REPEATED PORTIONS HAVING DIFFERENT WIDTHS

Samsung Electronics Co., ...

1. A vertical memory device, comprising:gate lines spaced apart from each other on a substrate in a first direction vertical to a top surface of the substrate;
channels extending through ones of the gate lines in the first direction; and
opening structures extending through the gate lines on the substrate, each of the opening structures including first and second openings alternately and repeatedly arranged in a second direction parallel to the top surface of the substrate, the first and second openings having first and second widths, respectively, in a third direction that is parallel to the top surface of the substrate and crossing the second direction, the second width being greater than the first width, and the opening structures being spaced apart from each other in the third direction,
wherein at least one of the channels is disposed between the second openings of neighboring ones of the opening structures in the third direction, the second openings facing each other in the third direction.

US Pat. No. 10,600,804

VERTICAL MEMORY DEVICES

Samsung Electronics Co., ...

1. A vertical memory device, comprising:a substrate, an upper portion of the substrate including an impurity region doped with carbon or p-type impurities;
a gate electrode structure on the substrate, the gate electrode structure including gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; and
a channel extending through the gate electrode structure in the vertical direction on the substrate, the channel including a first portion and a second portion,
the first portion having a slanted sidewall with respect to the upper surface of the substrate,
the second portion contacting an upper surface of the first portion,
the second portion having a slanted sidewall with respect to the upper surface of the substrate,
a width of an upper surface of the second portion being less than a width of the upper surface of the first portion, and
the channel contacting the impurity region.

US Pat. No. 10,600,803

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a semiconductor substrate;
a first wiring layer above the semiconductor substrate, the first wiring layer being a lowermost wiring layer above the semiconductor substrate;
a second wiring layer above the first wiring layer;
a memory pillar extending in a first direction intersecting the semiconductor substrate and through the first and second wiring layers, the memory pillar comprising a first semiconductor layer, a second semiconductor layer located above the first semiconductor layer, and a charge storage layer disposed between the second semiconductor layer and the second wiring layer;
a first plug contacting and electrically connected to the first wiring layer;
a second plug contacting and electrically connected to the second wiring layer;
a first pillar located next to the first plug, and closest to the first plug, and extending through the first wiring layer and not extending through the second wiring layer; and
a second pillar located next to the second plug, and closest to the second plug, and extending through the first and second wiring layers,
wherein a first point is a center of the first plug in a first cross-section viewed from the first direction at a level of an upper surface of the first wiring layer, a second point is a center of the first pillar in the first cross-section, a third point is a center of the second plug in a second cross-section viewed from the first direction at a level of an upper surface of the second wiring layer, and a fourth point is a center of the second pillar in the second cross-section, and
a distance from the first point to the second point is greater than a distance from the third point to the fourth point.

US Pat. No. 10,600,802

MULTI-TIER MEMORY DEVICE WITH ROUNDED TOP PART OF JOINT STRUCTURE AND METHODS OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate;
an inter-tier dielectric layer located over the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer;
a memory stack structure vertically extending through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack, wherein the memory stack structure is located in a memory opening that extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack,wherein:the memory stack structure comprises a semiconductor channel and a memory film laterally surrounding the semiconductor channel;
the memory film comprises an upper portion embedded in the second alternating stack, a lower portion embedded in the first alternating stack, and an inter-tier level portion embedded in the inter-tier dielectric layer and laterally protrudes outward relative to outer sidewalls of the upper portion and the lower portion; and
the inter-tier level portion of the memory film has a convex upper surface that contacts a concave downward-facing surface of the inter-tier dielectric layer and the inter-tier level portion of the memory film that has the convex upper surface has a lateral extent in a range from 10 nm to 200 nm in a vertical cross-sectional view within a vertical plane that includes a vertical axis passing through a geometrical center of the memory opening.

US Pat. No. 10,600,799

MEMORY DEVICE AND LOW BREAKDOWN VOLTAGE TRANSISTOR

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor substrate having a main surface, the main surface including a memory cell region and a logic region in a plan view,
wherein the memory cell region comprises:
a plurality of first protruding portions each of which protrudes from an upper surface of the semiconductor substrate and extends in a first direction along the main surface of the semiconductor substrate;
a first element isolation region embedded in a first trench between adjacent ones of the plurality of first protruding portions; and
a first transistor that is formed over upper surfaces of the plurality of first protruding portions via a first insulating film and is provided with both a first gate electrode extending in a second direction intersecting the first direction at a right angle and a first source/drain region formed in the upper surfaces of the plurality of first protruding portions,
wherein the logic region comprises:
a plurality of second protruding portions each of which protrudes from the upper surface of the semiconductor substrate and extends in the first direction;
a second element isolation region embedded in a second trench between adjacent ones of the plurality of second protruding portions; and
a second transistor provided with both a second gate electrode that is formed over upper surfaces of the plurality of second protruding portions via a second insulating film and extends in the second direction and a second source/drain region formed in the upper surfaces of the plurality of second protruding portions,
wherein the memory cell region further comprises:
a fourth insulating film including a third insulating film and a charge storage film that are sequentially formed over the plurality of first protruding portions; and
a third gate electrode that is adjacent to a sidewall of the first gate electrode via the fourth insulating film and extends in the second direction,
wherein the fourth insulating film is interposed between the third gate electrode and the plurality of first protruding portions,
wherein the third gate electrode and the first source/drain region form a third transistor,
wherein the first transistor and the third transistor form a nonvolatile memory element,
wherein in a direction perpendicular to the main surface of the semiconductor substrate, a distance between the upper surfaces of the plurality of first protruding portions and a bottom surface of the first element isolation region in the memory cell region is larger than a distance between the upper surfaces of the plurality of second protruding portions and a bottom surface of the second element isolation region in the logic region, and
wherein an angle between an upper surface and a sidewall of each of the plurality of first protruding portions is smaller than an angle between an upper surface and a sidewall of each of the plurality of second protruding portions.

US Pat. No. 10,600,791

SEMICONDUCTOR MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor memory device, comprising:a word line buried in an upper portion of a substrate and extending in a first direction;
a word line contact plug connected to the word line; and
a device isolation layer in the substrate to define active portions,
wherein an end portion of the word line includes a contact surface exposed in the first direction and extending along a second direction, intersecting the first direction,
wherein the word line contact plug is connected to the contact surface, and
wherein the word line contact plug includes
a first portion overlapping the end portion of the word line; and
a second portion overlapping with the device isolation layer.

US Pat. No. 10,600,787

SILICON PMOS WITH GALLIUM NITRIDE NMOS FOR VOLTAGE REGULATION

Intel Corporation, Santa...

1. An apparatus comprising:a silicon substrate comprising a trench;
a gallium nitride material in the trench of the silicon substrate;
a source electrode on the gallium nitride material;
a drain electrode on the gallium nitride material;
a gate electrode on the gallium nitride material between the source electrode and the drain electrode; and
an island of oxide in the trench, the island of oxide having a long axis in a direction substantially parallel to a [11?2] direction of the silicon substrate and being adjacent to a further trench,
wherein the further trench exposes one or both of the silicon substrate and a gallium nitride seed layer on the silicon substrate, and
wherein the further trench is filled with the gallium nitride material.

US Pat. No. 10,600,783

SELF-CUT SIDEWALL IMAGE TRANSFER PROCESS

International Business Ma...

1. A semiconductor structure comprising:a set of first structures formed on a first region of a silicon substrate, wherein each of the first structures comprises a mandrel having a first hardmask disposed on a top surface thereof, wherein the mandrel has a first width and a first height;
a set of second structures formed on a second region of the silicon substrate, wherein each of the second structures comprises a mandrel having a second hardmask disposed on a top surface thereof and an oxide layer disposed on the hardmask, wherein the mandrel has a second width and a second height;
a set of third structures formed on a third region of the silicon substrate, wherein each of the third structures comprises a mandrel having a third hardmask disposed on a top surface thereof, wherein the mandrel has a third width and a third height;
wherein the set of first structures and the set of third structures are separated by the set of second structures and further wherein the second width is greater than the first width and the third width.

US Pat. No. 10,600,782

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate;
an upper surface electrode disposed on an upper surface of the semiconductor substrate; and
a lower surface electrode disposed on a lower surface of the semiconductor substrate,
wherein
the semiconductor substrate comprises:
a diode region; and
an IGBT region provided adjacent to the diode region,
the diode region comprises:
a first conductive-type anode region provided in a portion disposed at the upper surface of the semiconductor substrate;
a second conductive-type cathode region provided in a portion disposed at the lower surface of the semiconductor substrate; and
a second conductive-type diode drift region provided between the anode region and the cathode region,
the IGBT region comprises:
a second conductive-type emitter region provided in a portion disposed at the upper surface of the semiconductor substrate;
a first conductive-type collector region provided in a portion disposed at the lower surface of the semiconductor substrate;
a second conductive-type IGBT drift region provided between the emitter region and the collector region, and provided adjacent to the diode drift region;
a first conductive-type body region provided between the emitter region and the IGBT drift region;
a gate trench extending from the upper surface of the semiconductor substrate to a depth reaching the IGBT drift region through the emitter region and the body region;
a second conductive-type buffer region provided between the IGBT drift region and the collector region and having a higher impurity concentration than the IGBT drift region; and
a plurality of first conductive-type low concentration regions provided between the buffer region and the collector region, arranged with intervals therebetween in a direction parallel to the semiconductor substrate, and having a lower impurity concentration than the collector region,
a gate electrode is disposed in the gate trench, and
the collector region comprises a first contact portion that is in contact with the buffer region between the low concentration regions adjacent to each other.

US Pat. No. 10,600,780

3D CHIP SHARING DATA BUS CIRCUIT

Xcelsis Corporation, San...

1. A three-dimensional (3D) circuit comprising:a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate;
a second IC die vertically stacked with the first IC die and comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate; and
a data input/output (I/O) circuit defined on the second semiconductor substrate to receive data from and to supply data to at least a first external circuit outside of the 3D circuit,
wherein data signals from the data I/O circuit are supplied from the second IC die to a first set of circuits defined on the first IC die.

US Pat. No. 10,600,776

DEVICE AND METHOD FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION

NXP B.V., Eindhoven (NL)...

1. An electrostatic discharge (ESD) protection device, the ESD protection device comprising:a first bipolar device connected to a first node;
a second bipolar device connected to the first bipolar device and to a second node; and
a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes, wherein the first bipolar device, the second bipolar device, and the MOS device are formed on a deep well structure, wherein the deep well structure comprises a deep N-well layer that is formed on top of a substrate layer and below an N-well, and wherein the N-well is in contact with the deep N-well layer and in contact with the substrate layer.

US Pat. No. 10,600,775

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Macronix International Co...

1. An electrostatic discharge protection device comprising:a semiconductor substrate;
a first N-type doped well and a second N-type doped well on the substrate, each of the first N-type doped well and the second N-type doped well comprising a first N+ region and a first P+ region;
a P-type doped well between the first N-type doped well and the second N-typed doped well on the substrate, the P-type doped well comprising a second N+ region, a third N+ region, and a second P+ region between the second N+ region and the third N+ region; and
a first contact and a second contact positioned above a surface of the first N-type doped well and above a surface of the second N-type doped well, respectively, between the first N+ region and the first P+ region;
a poly resistor connected between the first N-type doped well and the second N-typed doped well.

US Pat. No. 10,600,770

SEMICONDUCTOR DICE ASSEMBLIES, PACKAGES AND SYSTEMS, AND METHODS OF OPERATION

Micron Technology, Inc., ...

1. An assembly, comprising:an interposer comprising a glass material;
a semiconductor die comprising a logic die having a proximity coupling on a side of the interposer; and
at least one other semiconductor die comprising a proximity coupling configured for
communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer, the at least one other die comprising a number of stacked memory dice, each of the logic die and the memory dice comprising a proximity coupling for mutual signal communication;
wherein:
the logic die is in electrically conductive communication with conductive traces of the interposer for communicating power and ground/bias;
the number of stacked memory dice comprises memory dice stacked in stair-step fashion with exposed bond pads on treads of stairs; and
further comprising wire bonds respectively extending from the exposed bond pads to conductive traces of the interposer for communicating power and ground/bias; and
the interposer comprises an optical waveguide for signal communication with an optical I/O of the logic die and extends to a socket for optical signal communication with higher level packaging.

US Pat. No. 10,600,765

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a plurality of semiconductor chips provided on a circuit pattern within a case defined by an outer frame in a plan view, said case having a longer side extending along a longer-side direction and a shorter side that is shorter than said longer side and extends along a shorter-side direction that is transverse to the longer-side direction and within the same plane as the longer-side direction;
bonding wires for electrically connecting said plurality of semiconductor chips and said circuit pattern together;
a plurality of main electrodes provided within said case and disposed to extend along the longer-side direction of said case; and
two complex elements, each of said complex elements including two of said plurality of semiconductor chips connected to each other,
wherein one of said two complex elements is configured such that said two of said plurality of semiconductor chips are connected by a plurality of the bonding wires via a via-circuit pattern provided on a place interposed between said two of said plurality of semiconductor chips in a plan view, and
wherein another one of said two complex elements is configured such that said two of said plurality of semiconductor chips of said another one of said two complex elements are connected directly by another plurality of the bonding wires,
wherein each said main electrode is disposed proximate to an edge of said longer side extending in the longer-side direction of said case and spaced away from said complex elements at a location between said edge of said longer side and said complex elements,
wherein said plurality of semiconductor chips are arranged along the longer-side direction of said case,
wherein said bonding wires are strung along the longer-side direction of said case,
wherein each said main electrode is disposed in a vicinity of one of sides extending in the longer-side direction of said case,
wherein each said main electrode and said circuit pattern are connected together by ultra-sonic bonding, soldering, or brazing,
wherein said case has a recessed portion on a top surface of said case, and
wherein each said main electrode has an edge extended from said recessed portion and bent at a bend location of said main electrode such that said edge extends from said bend location to a free end of said edge in an inward direction of said case toward said circuit pattern in a plan view in said recessed portion, and said free end of said edge overlaps said circuit pattern and said bend location is proximate to said longer side of said case.

US Pat. No. 10,600,762

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Micron Technology, Inc., ...

1. An apparatus comprising a first die and a second die, each of the first and second dies including a face-side and a back-side, the face-side of the first die being defined by first and second edges substantially parallel to each other, and the face-side of the second die being defined by third and fourth edges substantially parallel to each other;wherein the first die comprises, on the face-side thereof:
at least one first interconnection region between the first and second edges;
at least one first probe pad between the at least one first interconnection region and the first edge at a position that is closer to the at least one first interconnection region than the first edge;
at least one first coupling region between the at least one first interconnection region and the second edge; and
at least one first redistribution wiring including a first portion electrically coupling the at least one first interconnection region to the at least one first probe pad and a second portion electrically coupling the at least one first interconnection region to the at least one first coupling region;
wherein the second die comprises, on the face-side thereof:
at least one second interconnection region between the third and fourth edges;
at least one second probe pad between the at least one second interconnection region and the fourth side edge at a position that is closer to the at least one second interconnection region than the fourth edge;
at least one second coupling region between the at least one second interconnection region and the at least one second probe pad; and
at least one second redistribution wiring including a third portion electrically coupling the at least one second interconnection region to the at least one second coupling region and a fourth portion electrically coupling the at least one coupling region to the at least one second probe pad;
wherein a distance between the at least one first interconnection region and the at least one first probe pad is substantially equal to a distance between the at least one second interconnection region and the at least one second probe pad; and
wherein the first die is bonded to the second die in a face-to-face relationship such that the at least one first interconnection region and the at least one second interconnection region are between the at least one first probe pad and the at least one second probe pad, and the at least one first coupling region is electrically coupled to the at least one second coupling region.

US Pat. No. 10,600,761

NANOSCALE INTERCONNECT ARRAY FOR STACKED DIES

Invensas Corporation, Sa...

1. A method of fabricating a microelectronic assembly, comprising:forming an insulating layer comprising a diblock copolymer on a substrate, the insulating layer including a self-assembled nanoscale matrix array of a first polymer and a second polymer;
removing the second polymer from the nanoscale matrix array to reveal a plurality of nanoscale holes in the nanoscale matrix array;
filling the plurality of nanoscale holes with one or more conductive materials to form a plurality of nanoscale conductors within the insulating layer, the nanoscale conductors extending from a first surface of the insulating layer to a second surface of the insulating layer opposite the first surface;
joining the array of nanoscale conductors within the insulating layer to a plurality of first element contacts at a first face of a first microelectronic element, the plurality of first element contacts facing the first surface of the insulating layer;
removing the substrate from the second surface of the insulating layer;
joining the array of nanoscale conductors within the insulating layer to a plurality of second element contacts at a second face of a second microelectronic element, the plurality of second element contacts facing the second surface of the insulating layer; and
forming electrical interconnections between the first element contacts of the first microelectronic element and the second element contacts of the second microelectronic element with the plurality of nanoscale conductors, wherein the plurality of nanoscale conductors are arranged without regard to a specific alignment of the plurality of nanoscale conductors to either the plurality of first element contacts or the plurality of second element contacts.

US Pat. No. 10,600,760

ULTRATHIN LAYER FOR FORMING A CAPACITIVE INTERFACE BETWEEN JOINED INTEGRATED CIRCUIT COMPONENT

Invensas Corporation, Sa...

1. A wafer-level package, comprising:first and second integrated circuit dies, each integrated circuit die
interfacing a single ultrathin layer of a first dielectric material between respective bonding surfaces of the first and second integrated circuit dies, each respective bonding surface partly comprising respective second dielectric layers of a second dielectric material;
each integrated circuit die comprising at least one conductive pad recessed from each respective bonding surface, wherein the respective conductive pads of the first and second integrated circuit dies are on opposing sides of the single ultrathin layer of the first dielectric material;
an instance of a third layer of a third dielectric material between each recessed conductive pad and each respective bonding surface of the first and second integrated circuit dies, each instance of the third layer of the third dielectric material filling-in respective recesses between the respective recessed conductive pads and the respective bonding surfaces;
a total thickness of the single ultrathin layer of the first dielectric material and two respective instances of the third layer of the third dielectric material being 25 nanometers or less, wherein the total thickness also comprises a distance between the respective recessed conductive pads on opposing sides of the single ultrathin layer;
a capacitive interface comprising the single ultrathin layer of the first dielectric material, the two respective instances of the third layer of the third dielectric material in the respective recesses, and the respective recessed conductive pads of the first and second integrated circuit dies;
a conductive power connection between the first and second integrated circuit dies, the conductive power connection disposed only through the second layer of the second dielectric material and through the single ultrathin layer of the first dielectric material; and
a conductive ground connection between the first and second integrated circuit dies, the conductive ground connection disposed only through the second layer of the second dielectric material and through the single ultrathin layer of the first dielectric material.

US Pat. No. 10,600,759

POWER AND GROUND DESIGN FOR THROUGH-SILICON VIA STRUCTURE

ADVANCED SEMICONDUCTOR EN...

11. A semiconductor package, comprising:a first substrate;
a semiconductor device on the first substrate and comprising:
a second substrate including a first surface and a second surface opposite the first surface;
active circuitry on the first surface of the second substrate;
a first conductive layer extending from the second surface of the second substrate toward the active circuitry and electrically connected to the active circuitry and defining a space in the semiconductor device; and
an encapsulation layer in the space defined in the semiconductor device,
wherein the active circuitry comprises a second conductive layer and a first dielectric layer, wherein the second conductive layer comprises a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer.

US Pat. No. 10,600,758

SEMICONDUCTOR SENSOR PACKAGE

STMICROELECTRONICS PTE LT...

1. A method, comprising: forming a plurality of through holes in a substrate, the substrate including a first surface and a second surface;forming a plurality of first trenches in the first surface of the substrate, each first trench of the plurality of first trenches being substantially parallel to each other, each first trench of the plurality of first trenches is overlapping and aligned with a number of through holes of the plurality of through holes;
forming a plurality of second trenches in the first surface of the substrate, each second trench of the plurality of second trenches being transverse to the plurality of first trenches and overlapping at least one of the through holes of the plurality of through holes; and
forming a non-conductive material in the plurality of through holes, the plurality of first trenches, and the plurality of second trenches.

US Pat. No. 10,600,756

WIRE BONDING TECHNIQUE FOR INTEGRATED CIRCUIT BOARD CONNECTIONS

United States of America,...

1. A method for connecting a chip die to a circuit board with a capillary dispenser to deposit gold, said dispenser forming a free air ball (FAB) at a depositing tip, said method comprising:forming a first bond by depositing the gold at the FAB from the tip to a board pad on the circuit board;
forming a second bond by depositing the gold at the FAB from the tip to a die pad on the chip die;
extruding a filament of the gold by the tip in a normal direction from said second bond;
rotating said filament laterally away from said first bond along a first radius;
extruding said filament while rotating said filament towards said first bond along a second radius; and
forming a third bond by depositing the gold at the FAB by the tip on said first bond to form said third bond.

US Pat. No. 10,600,755

METHOD OF MANUFACTURING AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURED THEREBY

Amkor Technology, Inc., ...

11. A method of manufacturing an electronic device, the method comprising:providing a substrate comprising a substrate conductive interconnection structure;
providing a semiconductor die comprising a die conductive interconnection structure protruding from a first side of the die; and
pressing a first surface of the die conductive interconnection structure and a first surface of the substrate conductive interconnection structure together with an interface layer comprising at least one layer of ink at an interface between the first surface of the die conductive interconnection structure and the first surface of the substrate conductive interconnection structure,
wherein after said pressing, the interface layer has a substantially consistent thickness,
wherein said pressing comprises performing said pressing utilizing a thermocompression bonding process.

US Pat. No. 10,600,754

BONDING METHOD

KAIJO CORPORATION, Tokyo...

1. A bonding method using a bonding apparatus including a rotation drive mechanism for rotating a bonding stage about a ?-axis, the method comprising the steps of:(e) locking said bonding stage with respect to said ?-axis, and bonding a wire or bump onto a certain area of a substrate held on said bonding stage;
(f) unlocking the bonding stage with respect to said ?-axis, and rotating said bonding stage about said ?-axis with said rotation drive mechanism; and
(g) locking said bonding stage with respect to said ?-axis, and bonding a wire or bump onto a remaining region of said substrate.

US Pat. No. 10,600,753

FLIP CHIP BACKSIDE MECHANICAL DIE GROUNDING TECHNIQUES

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC) package comprising:a semiconductor die including a first side and a second side opposite the first side, the first side including active circuitry;
a sheet attached to the second side, the sheet including a tip that electrically connects with the second side; and
a lid attached to a substrate, and contacting the sheet;
wherein the tip includes two parallel surfaces, and wherein each of the two parallel surfaces forms an acute angle with respect to a plane along a surface of the sheet, and wherein the tip extends from an edge of a hole in the sheet.

US Pat. No. 10,600,752

RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

ABLIC Inc., (JP)

1. A method of manufacturing a resin-encapsulated semiconductor device,the resin-encapsulated semiconductor device including:
a resin encapsulation body having a first surface and a second surface that is opposite to the first surface;
a semiconductor chip embedded in the resin encapsulation body; and
an external terminal formed on an element surface of the semiconductor chip, and embedded in the resin encapsulation body,
the method comprising:
preparing a substrate having a first main surface and a second main surface that is opposite to the first main surface;
forming a conductive layer on the first main surface;
forming the external terminal by connecting a bump electrode formed on the semiconductor chip to the conductive layer;
forming the resin encapsulation body on the first main surface by covering the external terminal and the semiconductor chip with resin;
exposing a surface of the semiconductor chip that is opposite to the element surface by grinding the resin encapsulation body and the semiconductor chip from a surface of the resin encapsulation body that is opposite to a surface thereof in contact with the first main surface;
forming a metal layer on the exposed surface of the semiconductor chip;
exposing the external terminal and the first surface of the resin encapsulation body; and
performing singulation by cutting the resin encapsulation body between adjacent semiconductor chips to obtain the resin-encapsulated semiconductor device.

US Pat. No. 10,600,751

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

International Business Ma...

1. A pillar-type connection comprising:a first conductive layer that includes a hollow core;
a second conductive layer coupled to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core; and
a conductive via that terminates at a top surface of the first conductive layer.

US Pat. No. 10,600,750

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

11. A semiconductor die, comprising:a substrate;
a contact exposed at a surface of the substrate;
an interconnect structure electrically coupled to the contact, wherein the interconnect structure includes a top surface having a first portion over the contact and a second portion laterally offset from the contact; and
a solder material disposed at least partially on the second portion of the top surface of the interconnect structure.

US Pat. No. 10,600,749

CONTACT HOLE STRUCTURE AND FABRICATING METHOD OF CONTACT HOLE AND FUSE HOLE

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor structure, comprising:providing a dielectric layer having a conductive pad and a fuse formed therein, wherein the dielectric layer comprises a silicon oxide layer and a silicon nitride layer over the silicon oxide layer;
forming a first mask covering the dielectric layer and having a first opening directly over the conductive pad;
performing a first removing process using the first mask as a mask to remove a portion of the dielectric layer to form a first trench, wherein the conductive pad is directly under the first trench and is not exposed from the first trench;
removing the first mask;
forming a second mask covering the dielectric layer and having a second opening exposing the first trench and a third opening directly over the fuse; and
performing a second removing process using the second mask as a mask to remove the dielectric layer directly under the first trench and the dielectric layer directly over the fuse thereby forming a contact hole and a fuse hole respectively, wherein the conductive pad is exposed from the contact hole.

US Pat. No. 10,600,747

VERTICAL CAPACITORS FOR MICROELECTRONICS

Invensas Corporation, Sa...

1. An apparatus, comprising:a capacitor layer to underlie a semiconductor chip, a die, or an integrated circuit;
vertical capacitor plates in the capacitor layer interleaved with vertical dielectric layers;
electrodes of each vertical capacitor plate at a top surface and a bottom surface of the capacitor layer; and
power pass-throughs or ground pass-throughs on the top surface and the bottom surface of the capacitor layer.

US Pat. No. 10,600,746

RADIO FREQUENCY TRANSISTOR AMPLIFIERS AND OTHER MULTI-CELL TRANSISTORS HAVING GAPS AND/OR ISOLATION STRUCTURES BETWEEN GROUPS OF UNIT CELL TRANSISTORS

Cree, Inc., Durham, NC (...

1. A multi-cell transistor, comprising:a semiconductor structure; and
a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure,
wherein the unit cell transistors are spaced apart from each other along a second direction and arranged in a plurality of groups, wherein a first distance in the second direction between two adjacent unit cell transistors in a first of the groups is less than a second distance in the second direction between a first unit cell transistor that is at one end of the first of the groups and a second unit cell transistor that is in a second of the groups, where the second unit cell transistor is adjacent the first unit cell transistor,
wherein the multi-cell transistor further comprises a metal isolation structure that extends above the semiconductor structure in the first direction between the first of the groups and the second of the groups, and
wherein the metal isolation structure is electrically connected to source regions of the unit cell transistors.

US Pat. No. 10,600,745

COMPENSATING FOR MEMORY INPUT CAPACITANCE

Micron Technology, Inc., ...

1. An apparatus, comprising:a substrate;
an access line comprising a first portion in contact with the substrate and a second portion;
a memory die coupled with the substrate via the second portion of the access line;
a memory controller coupled with the access line and configured to transmit, through the access line to the memory die, a signal having an amplitude level and modulated with a modulation scheme having at least two levels; and
an inductive region coupled with the access line and configured to change a first noise level associated with the amplitude level of the signal to a second noise level based at least in part on altering a capacitance of the access line.

US Pat. No. 10,600,744

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a lead frame;
a transistor including a plurality of drain electrode pads, a plurality of source electrode pads, and a gate electrode pad on one surface, the plurality of drain electrode pads, the plurality of source electrode pads, and the gate electrode pad facing a front surface of the lead frame and being connected to the lead frame; and
an encapsulation resin that has a rectangular-plate shape and encapsulates the transistor and the lead frame so that a part of the lead frame is exposed from a back surface of the encapsulation resin, wherein
the lead frame includes a drain frame electrically connected to the plurality of drain electrode pads, a source frame electrically connected to the plurality of source electrode pads, and a gate frame electrically connected to the gate electrode pad,
the drain frame includes a plurality of drain frame fingers,
the plurality of drain frame fingers are spaced apart from each other in a first direction, extended in a second direction that is orthogonal to the first direction in a plan view, and each one of the plurality of the drain frame fingers is connected to a respective one of the plurality of drain electrode pads,
the source frame includes a plurality of source frame fingers,
the plurality of source frame fingers are spaced apart from each other in the first direction, extended in the second direction, and each one of the plurality of the source frame fingers is connected to a respective one of the plurality of source electrode pads,
each one of the plurality of the drain frame fingers and each one of the plurality of the source frame fingers are alternately arranged in the first direction and overlap each other as viewed in the first direction,
in a region where the plurality of drain frame fingers and the plurality of source frame fingers overlap one another as viewed in the first direction, at least either one of the plurality of drain frame fingers and the plurality of source frame fingers are not exposed from the back surface of the encapsulation resin, and
in the region where the plurality of drain frame fingers and the plurality of source frame fingers overlap one another as viewed in the first direction, either one of the plurality of drain frame fingers and the plurality of source frame fingers are exposed from the back surface of the encapsulation resin, and the other one of the plurality of drain frame fingers and the plurality of source frame fingers are not exposed from the back surface of the encapsulation resin.

US Pat. No. 10,600,743

ULTRA-THIN THERMALLY ENHANCED ELECTRO-MAGNETIC INTERFERENCE SHIELD PACKAGE

Inari Semiconductor Labs ...

1. A method of fabricating an electronic package, comprising the steps of:connecting a plurality of semiconductor chips to at least one surface of a substrate using a connect pad;
encapsulating the semiconductor chips with a non-conductive material by a first molding process;
reducing a thickness of the semiconductor chips by a process of trimming or grinding from a top encapsulation layer of the semiconductor chips to form thin semiconductor chips; and
forming an electro-magnetic interference shield layer over the thin semiconductor chips by a second molding process.

US Pat. No. 10,600,742

CHIP WITH CIRCUIT FOR DETECTING AN ATTACK ON THE CHIP

Infineon Technologies AG,...

1. A chip, comprising:a substrate region having a substrate contact;
an RS latch having two complementary nodes representing a storage state of the RS latch;
a control circuit comprising a control input connected directly to the substrate contact and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input; and
an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

US Pat. No. 10,600,741

SEMICONDUCTOR PACKAGE WITH PLATED METAL SHIELDING AND A METHOD THEREOF

Utac Headquarters PTE. LT...

1. A method of manufacturing semiconductor devices, comprising:obtaining a molded array that includes a package side and an interfacing side, wherein the molded array includes a plurality of dies coupled to a substrate and molding compound encapsulating the plurality of dies, wherein surfaces of the molding compound has have a natural surface roughness;
coupling the interfacing side of the molded array with a tape;
performing a cut through procedure from the package side to the interfacing side, thereby forming a plurality of singulated semiconductor devices on the tape;
performing an abrasion procedure to roughen all surfaces of the molding compound such that, after the abrasion procedure, all surfaces of the molding compound have an unnatural surface roughness that is rougher than the natural surface roughness, wherein the abrasion procedure comprises:
i. coating all exposed surfaces of the molding compound with an adhesion promoter material;
ii. heating the molded array with the adhesion promoter material such that the adhesion promoter material reacts with a portion of the molding compound, resulting in a baked film; and
iii. etching away the baked film, resulting in the molding compound having the roughened surfaces;
adhering a metal layer on the roughened surfaces; and
removing the plurality of singulated semiconductor devices from the tape.

US Pat. No. 10,600,740

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH EPITAXIAL LAYERS AND AN ALIGNMENT MARK

Infineon Technologies Aus...

1. A semiconductor substrate, comprising:an alignment mark contained within in a kerf region of a semiconductor wafer or in an inactive region of a semiconductor die, the alignment mark comprising a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m in a process surface of a semiconductor layer, and at least one fin within the groove at a distance of at least 60 ?m to a closest inner corner of the groove.

US Pat. No. 10,600,738

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
an insulating film formed to cover the semiconductor substrate;
a first electric conductor formed on the insulating film;
a second electric conductor formed on the insulating film at a distance from the first electric conductor;
an embedded body formed to fill space between the first electric conductor and the second electric conductor;
a protective film formed to cover the first electric conductor, the second electric conductor and the embedded body;
a solder layer formed to cover the protective film; and
a glass coating film covering an upper surface of each of the first electric conductor and the second electric conductor,
a position of an upper surface of the embedded body being matched to a position of an upper surface of the glass coating film, and
the first electrical conductor is electrically isolated from the second electrical conductor.

US Pat. No. 10,600,737

PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT

STMicroelectronics (Rouss...

1. A process, comprising:forming an opening in a porous material dielectric region, said opening having a side wall and a bottom wall;
depositing a non-porous dielectric barrier on said side wall and said bottom wall;
performing an anisotropic etch to completely remove a portion of the non-porous dielectric barrier along the bottom wall, wherein performing the anisotropic etch comprises performing a plasma etch; and
filling the opening with metal material to form an electrically conductive element that is laterally separated from an upper portion of the porous material dielectric region by the non-porous dielectric barrier along the side wall but is in contact with a lower portion of the porous material dielectric region along the bottom wall.

US Pat. No. 10,600,736

SEMICONDUCTOR BACKMETAL (BM) AND OVER PAD METALLIZATION (OPM) STRUCTURES AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device, comprising:a semiconductor layer having a first side and a second side opposite the first side;
one or more electrically conductive pads coupled at the second side;
one or more electrically insulative layers coupled at the second side and having one or more openings providing access to the one or more electrically conductive pads;
an electrically conductive layer coupled on the first side of the semiconductor layer;
one or more backmetal (BM) layers coupled on the electrically conductive layer;
one or more over-pad metallization (OPM) layers coupled over the one or more electrically conductive pads, the one or more OPM layers comprising a nickel layer, and;
a diffusion barrier layer coupled over the one or more OPM layers;
wherein the semiconductor device comprises one of an insulated gate bipolar transistor (IGBT) or a diode;
wherein a perimeter of each of the one or more OPM layers is entirely within a perimeter of each of the one or more electrically conductive pads; and
wherein a largest planar surface of the electrically conductive layer and a side surface of the electrically conductive layer substantially perpendicular to the largest planar surface of the electrically conductive layer are both directly coupled to the semiconductor layer.

US Pat. No. 10,600,735

3D CHIP SHARING DATA BUS

Xcelsis Corporation, San...

1. A three-dimensional (3D) circuit comprising:a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate; and
a second IC die vertically stacked with the first IC die and comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate, wherein at least one particular second-set interconnect layer comprises a plurality of interconnect segments that form a data bus for supplying data signals to the first IC die.

US Pat. No. 10,600,693

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS

Tessera, Inc., San Jose,...

1. A method of forming arrays of fin field effect transistors (finFETs) having fin(s) with reduced dimensional variations, comprising:forming a first array of vertical fins, a second array of vertical fins, and one or more dummy fins on a substrate, wherein the one or more dummy fins are on a dummy fin fill between the first array of vertical fins and the second array of vertical fins; and
removing the one or more dummy fins and dummy fin fill to form a step in the substrate and a gap between the first array of vertical fins and the second array of vertical fins.

US Pat. No. 10,600,691

3D CHIP SHARING POWER INTERCONNECT LAYER

Xcelsis Corporation, San...

1. A three-dimensional (3D) circuit comprising:a first integrated circuit (IC) die comprising a first semiconductor substrate and a first set of interconnect layers defined on the first semiconductor substrate; and
a second IC die vertically stacked with the first IC die and comprising a second semiconductor substrate and a second set of interconnect layers defined on the second semiconductor substrate, wherein at least one particular second-set interconnect layer comprises a plurality of interconnect segments for supplying power signals to the first IC die.

US Pat. No. 10,600,688

METHODS OF PRODUCING SELF-ALIGNED VIAS

Micromaterials LLC, Wilm...

1. A method to provide a self-aligned via, the method comprising:forming a seed gapfill layer on recessed first insulating layers positioned between first conductive lines, the first conductive lines extending along a first direction;
forming pillars from the seed gapfill layer, the pillars extending above the first conductive lines;
depositing a second insulating layer in gaps between the pillars on the first conductive lines;
removing the pillars to form gaps in the second insulating layer;
depositing a third insulating layer in the gaps in the second insulating layer, onto the recessed first insulating layers and on the second insulating layer to form an overburden of third insulating layer on the second insulating layer; and
selectively etching a portion of the overburden of the third insulating layer and some of the second insulating layer to expose the first conductive lines and form vias and a trench extending in a second direction different from the first direction.

US Pat. No. 10,600,687

PROCESS INTEGRATION TECHNIQUES USING A CARBON LAYER TO FORM SELF-ALIGNED STRUCTURES

TOKYO ELECTRON LIMITED, ...

11. A method of utilizing a tone inversion process step to form self-aligned contacts, the method comprising:providing a substrate having patterned structures which provide gate regions and self-aligned contact regions in which a self-aligned contact will be formed;
forming a gate liner above at least a portion of the gate regions and the self-aligned contact regions;
providing a carbon layer in a portion of the self-aligned contact regions;
forming recessed carbon layer portions in the self-aligned structure region, wherein a height of each recessed carbon layer portion is lower than a height of the self-aligned contact regions;
removing the patterned structures;
forming self-aligned contacts in the self-aligned contact regions;
providing, over the self-aligned contacts, a blocking mask above the recessed carbon layer portions in the self-aligned contact regions;
removing at least some of the recessed carbon layer portions in areas not protected by the blocking mask;
removing the blocking mask from above the self-aligned contact regions; and
removing the recessed carbon layer portions from the self-aligned contact regions.

US Pat. No. 10,600,680

CHEMOEPITAXY ETCH TRIM USING A SELF ALIGNED HARD MASK FOR METAL LINE TO VIA

International Business Ma...

1. An electrical communication structure comprising:metal vias in a dielectric layer;
a neutral charged di-block polymer layer on at least a portion of dielectric layer; and
metal lines present in a layer including a block copolymer composition from a self-assembled di-block copolymer layer that is present atop the neutral charged di-block polymer layer, wherein the metal lines are self-aligned to the metal vias.

US Pat. No. 10,600,678

SELF-ALIGNED ISOTROPIC ETCH OF PRE-FORMED VIAS AND PLUGS FOR BACK END OF LINE (BEOL) INTERCONNECTS

Intel Corporation, Santa...

1. A method of fabricating an integrated circuit structure, the method comprising:forming a dielectric layer above a substrate;
forming a plurality of holes or trenches in the dielectric layer;
filling the plurality of holes or trenches with a sacrificial or permanent placeholder material;
forming a patterning layer above the dielectric layer and the sacrificial or permanent placeholder material;
forming openings in the patterning layer to expose a portion of the sacrificial or permanent placeholder material of a subset of the plurality of holes or trenches, each opening smaller than the corresponding portion of the sacrificial or permanent placeholder material of the subset of the plurality of holes or trenches; and
removing the sacrificial or permanent placeholder material of the subset of the plurality of holes or trenches through the openings in the patterning layer.

US Pat. No. 10,600,677

METHOD FOR MANUFACTURING BONDED SOI WAFER

SHIN-ETSU HANDOTAI CO., L...

1. A method for manufacturing a bonded SOI wafer comprising a step of performing a heat treatment to each bonded SOI wafer having an oxide film on a back surface thereof in an argon atmosphere to flatten a front surface of an SOI layer,wherein, at the time of performing the heat treatment in the argon atmosphere in a batch processing heat treatment furnace, a silicon wafer is arranged as a dummy wafer between the adjacent bonded SOI wafers housed in the batch processing heat treatment furnace to perform the heat treatment.

US Pat. No. 10,600,676

GROUP III NITRIDE COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR DEVICE

SUMITOMO ELECTRIC INDUSTR...

1. A group III nitride composite substrate with a diameter of 75 mm or more comprising a support substrate and a group III nitride film having a thickness of 10 ?m or more and 250 ?m or less that are bonded to each other,the support substrate being a hetero-composition substrate having a chemical composition different from a group III nitride,
the group III nitride composite substrate having a support-substrate-side main surface and a group III-nitride-film-side main surface,
a mean value mS of a root mean square roughness of the support-substrate-side main surface being 0.3 nm or more and 20 nm or less, and
a ratio sS/mS of a standard deviation sS of the root mean square roughness, to the mean value ms of the root mean square roughness of the support-substrate-side main surface, being 0.005 or more and 0.4 or less, wherein
a ratio W/D of a warp W of the support-substrate-side main surface to the diameter D is ?7×10?4 or more and 8×10?4 or less.

US Pat. No. 10,600,675

TECHNIQUES AND STRUCTURE FOR FORMING THIN SILICON-ON-INSULATOR MATERIALS

Varian Semiconductor Equi...

1. A method, comprising:providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising:
an insulator layer; and
a silicon layer, the silicon layer disposed on the insulator layer, the silicon layer, the silicon layer characterized by a non-uniform thickness, comprising a first silicon thickness variation, across the SOI substrate;
forming an oxide layer on the silicon layer across the SOI substrate, when the silicon layer has the non-uniform thickness, the oxide layer having a uniform thickness across the SOI substrate; and
selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a non-uniform oxide thickness, wherein
after thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness is configured to generate a second silicon thickness variation in the silicon layer across the SOI substrate, less than the first silicon thickness variation.

US Pat. No. 10,600,674

SEMICONDUCTOR DEVICES WITH BACK SURFACE ISOLATION

Efficient Power Conversio...

1. A transistor device comprising:a substrate;
at least one buffer layer comprising a compound semiconductor material;
a device layer including a current conducting region formed over the at least one buffer layer;
a source contact and a drain contact formed on a top surface of the device layer; and
a conductive well formed in the substrate and disposed laterally underneath both the source and drain contacts, wherein the conductive well is electrically isolated in at least one bias polarity from the substrate, such that a potential under the source contact and the drain contact is independent from a potential of the substrate; and
a conductive via extending from the top surface of the device layer through the device layer and through the buffer layer to penetrate and terminate within the conductive well, electrically connecting the source contact to the conductive well;
wherein the substrate has a backside opposite a side adjacent the buffer layer and the drain contact is independent in potential from the backside of the substrate; and
wherein the conductive well has a doping of opposite polarity to the substrate.

US Pat. No. 10,600,671

MICRO-TRANSFER-PRINTABLE FLIP-CHIP STRUCTURES AND METHODS

1. A semiconductor structure, comprising:a destination substrate comprising two or more contact pads disposed on a surface of the destination substrate;
a completed semiconductor device disposed on the surface, the completed semiconductor device comprising two or more electrical contacts disposed on a common side of the completed semiconductor device; and
connection posts, each of the connection posts (i) extending from the completed semiconductor device, (ii) electrically connected to at least one of the two or more electrical contacts, and (iii) in electrical contact with one of the contact pads,
wherein the completed semiconductor device is tilted or angled with respect to the surface of the destination substrate.

US Pat. No. 10,600,670

FRAME MOUNTING AFTER FOIL EXPANSION

Infineon Technologies AG,...

1. An apparatus, the apparatus comprising:an expansion unit configured for expanding a foil;
a mounting unit configured for subsequently mounting the expanded foil on a frame and a workpiece on the expanded foil, wherein the expansion unit comprises a fixing mechanism configured for radially symmetrically clamping a portion of the foil before expanding foil,
wherein the expansion unit, which expands the foil by at least 0.1%, is configured to apply a radially symmetrically tensile stress to the foil prior to its mounting on the frame and conserved thereafter.

US Pat. No. 10,600,669

SUBSTRATE FIXTURE AND SUBSTRATE FIXING DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A substrate fixture comprising:a monopolar chuck main body comprising an insulated plate and an electrode embedded in the insulated plate;
a tray placed on the monopolar chuck main body, having an upper surface in which a plurality of concave parts for accommodating therein a plurality of substrates is formed, and formed of an insulator having a volume resistivity equal to or lower than a volume resistivity of the insulated plate; and
an yttrium oxide layer formed on the upper surface of the tray.

US Pat. No. 10,600,667

SYSTEMS AND METHODS FOR WAFER ALIGNMENT

Micron Technology, Inc., ...

1. A non-transitory computer-readable storage medium comprising instructions that, when executed by one or more processing devices, cause the one or more processing devices to:determine a center location of each of a plurality of features on a wafer;
determine an average center location of the plurality of features;
compare the average center location with a reference location; and
generate an instruction to adjust a position of the wafer in response to the comparison.

US Pat. No. 10,600,666

ARTICLE TRANSPORT FACILITY

Daifuku Co., Ltd., Osaka...

1. An article transport facility comprising:article transport vehicles each of which is capable of traveling along any of travel paths to transport an article; and
a storage device configured to store one or more articles;
wherein the travel paths include a first path that extends by way of the storage device, and a plurality of second paths connected to the first path at mutually different locations along the first path,
wherein each of the plurality of second paths is arranged to extend by way of at least one processing device configured to process an article or one or more contents thereof;
wherein the article transport facility includes a transport device which has a connecting portion connected to the storage device, and which is configured to transport an article to be carried into, or being carried out from, the storage device,
wherein the transport device is provided separately from the article transport vehicles,
wherein, with a first side being one side, with respect to the first path, along a lateral width direction of the first path and a second side being the other side, with respect to the first path, along a lateral width direction of the first path, the connecting portion is located on the first side with respect to the first path whereas a subject path which is one of the plurality of second paths is located on the second side with respect to the first path,
wherein a transporting path of an article by the transport device is so located to cross the first path in plan view and to extend at least from the connecting portion and to the second side with respect to the first path, and
wherein a first transfer portion at which an article is transferred between the transport device and the article transport vehicle traveling along the subject path is set in a portion of the transporting path that is located on the second side with respect to the first path.

US Pat. No. 10,600,665

SUBSTRATE PROCESSING APPARATUS

BROOKS AUTOMATION, INC., ...

1. A substrate processing apparatus comprising:a frame;
a first arm connected to the frame, the first arm being a three link arm configured to extend and retract along a first radial axis and having an upper arm, a forearm and an end effector;
a second arm connected to the frame, the second arm being a three link arm configured to extend and retract along a second radial axis and having an upper arm, a forearm and an end effector, where the first and second arms have a common axis of rotation on a common base from which the first and second arms depend, and the end effectors of each of the first and second arms move along a common transfer plane; and
a drive section coupled to the first and second arms, the drive section having two degrees of freedom disposed co-axially forming a coaxial drive spindle and being configured to extend both the first and second arms with the coaxial drive spindle along respective radial axes and rotate both the first and second arms with the coaxial drive spindle about the common axis of rotation so that the extension and retraction of the first and second arms along the respective radial axes is decoupled and the first arm has at least one link of the three link arm with a different length than a corresponding link of the second arm.

US Pat. No. 10,600,663

NOZZLE AND WORK POLISHING APPARATUS

FUJIKOSHI MACHINERY CORP....

1. A nozzle comprising:a liquid flow passage through which a liquid flows;
a gas flow passage through which a gas flows, the gas flow passage communicating with the liquid flow passage and feed the gas to the liquid flow passage; and
a plasma generating mechanism for generating plasma in the gas fed from the gas flow passage to the liquid flow passage,
wherein the plasma generating mechanism includes a first electrode provided so as to be exposed to an inside of the liquid flow passage,
a second electrode provided so as not to be exposed to the inside of the liquid flow passage and so as to be exposed to an inside of the gas flow passage, and
a power source for applying a predetermined voltage across the first electrode and the second electrode,
wherein the liquid with which the gas including the generated plasma is mixed as bubbles having a predetermined diameter is spouted, and
wherein the second electrode is provided distantly from a delivery port toward an inside of the gas flow passage, the delivery port being provided at a portion in which the gas flow passage is connected to the liquid flow passage.

US Pat. No. 10,600,662

SILICON CARBIDE SUBSTRATE HEATING

Varian Semiconductor Equi...

1. A heating system, comprising:a silicon carbide substrate; and
a heating element, wherein the heating element comprises one or more light emitting diodes (LEDs) that emits light at a wavelength between 600 nm and 650 nm, wherein the wavelength is selected based on an absorption coefficient of the silicon carbide substrate.

US Pat. No. 10,600,660

METHOD OF SELECTIVELY ETCHING FIRST REGION MADE OF SILICON NITRIDE AGAINST SECOND REGION MADE OF SILICON OXIDE

TOKYO ELECTRON LIMITED, ...

1. A method of etching a first region made of silicon nitride selectively against a second region made of silicon oxide, comprising:preparing a processing target object having the first region and the second region within a chamber provided in a chamber main body of a plasma processing apparatus;
generating plasma of a first gas including a gas containing hydrogen within the chamber to form a modified region by modifying a part of the first region with active species of the hydrogen; and
generating plasma of a second gas including a gas containing fluorine within the chamber to remove the modified region with active species of the fluorine,
wherein the processing target object is placed, within the chamber, on a stage including therein an electrode to which a high frequency power for attracting ions onto the processing target object is allowed to be supplied, and
the high frequency power is not supplied to the electrode in the generating of the plasma of the second gas.

US Pat. No. 10,600,659

SEMICONDUCTOR PACKAGE WITH REDUCED PARASITIC COUPLING EFFECTS AND PROCESS FOR MAKING THE SAME

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a silicon-on-insulator (SOI) structure including an epitaxial layer, a buried oxide (BOX) layer over the epitaxial layer, and a silicon handle layer over the BOX layer, wherein:
the epitaxial layer has a first sacrificial epitaxial section, a first active epitaxy section and an isolation region; and
the isolation region surrounds the first active epitaxy section and separates the first active epitaxy section from the first sacrificial epitaxial section;
forming at least one first etchable structure that extends through the first sacrificial epitaxial section and the BOX layer to the silicon handle layer;
integrating a first active device in or on the first active epitaxy section, such that the epitaxial layer is formed as a device layer; and
forming a (back-end-of-line) BEOL layer underlying the device layer, wherein:
the BEOL layer has an upper surface including a first surface portion and a second surface portion surrounding the first surface portion;
the first sacrificial epitaxial section is over the first surface portion and not over the second surface portion;
the first epitaxy section and the isolation region are over the second surface portion and not over the first surface portion; and
the BEOL layer comprises a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion.

US Pat. No. 10,600,658

APPARATUS AND METHOD FOR BENDING A SUBSTRATE

Infineon Technologies AG,...

1. A method, comprising:placing a substrate on a first curved surface of a first tool;
arranging a semiconductor body on the substrate;
using a second tool with a second surface to apply a first pressure to the substrate and to the semiconductor body arranged on the substrate so as to press the semiconductor body onto the substrate and the substrate onto the first curved surface of the first tool, and pre-bend the substrate with the semiconductor body mounted thereon;
removing the pre-bended substrate with the semiconductor body mounted thereon from the first tool; and
after removing the pre-bended substrate with the semiconductor body mounted thereon from the first tool, mounting the pre-bended substrate with the semiconductor body mounted thereon to a bended base plate or heat sink.

US Pat. No. 10,600,656

DIRECTED SELF-ASSEMBLY FOR COPPER PATTERNING

International Business Ma...

1. A process of forming patterned copper lines, comprising:assembling an etch stack, wherein the etch stack includes a resist, a hardmask, an organic planarizing layer (OPL), and a copper substrate, and wherein the copper substrate has been annealed at a temperature above 200° C.;
lithographically patterning the resist to produce a template;
forming a patterned block copolymer mask layer on the etch stack by directed self-assembly, wherein the patterned block copolymer includes a first block and a second block;
etching portions of the block copolymer mask layer, wherein the etching removes the first block to produce a first pattern;
etching the first pattern into the hardmask;
partially removing the second block;
etching the first pattern into the OPL, wherein the etching the first pattern includes removing the remainder of the second block and partially removing the patterned hardmask;
coating the patterned OPL with a coating material;
etching back a layer of the coating material and the remainder of the hardmask to expose the surface of the patterned OPL;
removing the patterned OPL to produce a second pattern; and
transferring the second pattern to the copper substrate to form the patterned copper lines, wherein the patterned copper lines have a pitch that is less than 30 nm.

US Pat. No. 10,600,654

ETCHING PROCESS METHOD

Tokyo Electron Limited, ...

1. An etching process method comprising:outputting a first high frequency power of a first frequency from a first high frequency power supply, and outputting a second high frequency power of a second frequency, which is lower than the first high frequency, from a second high frequency power supply in an environment where a substrate temperature is controlled to be less than or equal to ?35° C.;
adding a hydrocarbon gas containing at least 3 carbon atoms to an etching gas containing carbon, hydrogen, and fluorine for generating a plasma; and
etching a silicon oxide film or a laminated film made up of laminated layers of silicon-containing films having different compositions using generated plasma,
wherein the hydrocarbon gas contains one double bond between carbon atoms, and
wherein the hydrocarbon gas is butene.

US Pat. No. 10,600,653

METHOD FOR FORMING A FINE PATTERN

Samsung Electronics Co., ...

14. A method for forming a fine pattern, the method comprising:sequentially forming a lower layer and an organic mask layer on a semiconductor substrate;
forming a hard mask pattern on the organic mask layer, the hard mask pattern comprising: first line portions extending in parallel in a first direction; and a first connection portion between the first line portions adjacent to each other;
anisotropically etching the organic mask layer using the hard mask pattern as an etch mask to form an organic mask pattern which comprises: second line portions under the first line portions of the hard mask pattern; and a second connection portion under the first connection portion of the hard mask pattern; and
selectively ion-beam-etching the second connection portion of the organic mask pattern,
wherein the ion-beam-etching of the second connection portion comprises: irradiating an ion beam in an incident direction which is parallel to a plane defined by the first direction and a second direction perpendicular to a top surface of the semiconductor substrate, and
wherein the incident direction of the ion beam is not perpendicular to the top surface of the semiconductor substrate.

US Pat. No. 10,600,649

SYSTEMS AND METHOD FOR CHARGE BALANCED SEMICONDUCTOR POWER DEVICES WITH FAST SWITCHING CAPABILITY

GENERAL ELECTRIC COMPANY,...

1. A method of manufacturing a semiconductor device, comprising:performing a first implantation in a semiconductor layer via ion implantation, forming a first implantation region, wherein the semiconductor layer comprises a top epitaxial (epi) layer, wherein the top epi layer is disposed upon at least one epi layer having a first conductivity type that includes a plurality of charge balance (CB) regions having a second conductivity type to form at least one CB layer; and
performing a second implantation in the semiconductor layer via ion implantation, forming a second implantation region opposite the first implantation region, wherein the first and second implantation regions overlap with one another;
wherein the first and second implantation regions combine to form a connection region extending into the semiconductor layer to at least one of the plurality of CB regions of the at least one CB layer.

US Pat. No. 10,600,647

COATING APPARATUS

SCREEN Holdings Co., Ltd....

1. A method of adjusting a coating apparatus comprising:a nozzle dispensing chemical to a substrate;
a pipe in communication with the nozzle;
a chemical supplying unit supplying the chemical through the pipe to the nozzle;
an open/close valve on the pipe between the nozzle and the chemical supplying unit, and having an open/close drive unit that allows adjustment of opening operation and closing operation in accordance with first electric signals, the open/close valve opening/closing the pipe; and
a suck back valve on the pipe between the nozzle and the open/close valve, and having a suction/push drive unit that allows adjustment of a volume variation in a flow path in communication with an upstream side and a downstream side of the pipe in accordance with second electric signals;
the method comprising:
a selecting step of selecting any nozzle-side filter of a plurality of nozzle-side filters having different respective fineness for providing the nozzle-side filter on the pipe between the nozzle and the suck back valve;
a first changing step of changing an operating amount of the closing operation of the open/close valve in accordance with the fineness of the selected nozzle-side filter for applying the first electric signals to the open/close drive unit; and
a second changing step of changing an operating amount of the suction operation of the suck back valve in accordance with the fineness of the selected nozzle-side filter for applying the second electric signals to the suction/push drive unit.

US Pat. No. 10,600,645

MANUFACTURING METHOD OF GALLIUM NITRIDE SUBSTRATE

Samsung Electronics Co., ...

1. A method of manufacturing a gallium nitride substrate, the method comprising:forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein due to the presence of one or more impurity particles and the silicon substrate is exposed through the one or more holes in the first buffer layer;
forming a silicon nitride region in the silicon substrate at the exposed portion of the silicon substrate;
forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and
forming a GaN layer on the second buffer layer,
wherein the one or more holes of the first buffer layer are filled by the second buffer layer.

US Pat. No. 10,600,644

MONO- AND MULTILAYER SILICENE PREPARED BY PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION

The Government of the Uni...

1. A process for making a naturally hydrogenated silicene film, comprising the steps of:placing a substrate into a plasma-enhanced chemical vapor deposition (PECVD) chamber;
setting the substrate to a temperature of about 20 to about 290° C.;
providing a starting material comprising a mixture of H2 and SiH4 having an H2:SiH4 ratio between 100:1 and 400:1; and
depositing a two-dimensional silicene film on the substrate from the H2:SiH4 starting material by means of PECVD, deposition occurring for about 10 to 25 minutes at an RF power of about 10 W to about 90 W and a chamber pressure of about 100 mTorr to about 1300 mTorr.

US Pat. No. 10,600,643

METHOD OF FORMING THIN FILM AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE USING THE SAME

Samsung Electronics Co., ...

1. A method of forming a thin film, the method comprising:forming a first reaction inhibiting layer chemisorbed on a first portion of a lower film by supplying a reaction inhibiting compound having a carbonyl group to an exposed surface of the lower film at a temperature of about 300° C. to about 600° C.;
forming a first precursor layer of a first material chemisorbed on a second portion of the lower film at a temperature of about 300° C. to about 600° C., the second portion being exposed through the first reaction inhibiting layer; and
forming a first monolayer containing the first material on the lower film by supplying a reactive gas to the first reaction inhibiting layer and the first precursor layer and removing the first reaction inhibiting layer from the surface of the lower film, and thus exposing the first portion.

US Pat. No. 10,600,640

REDUCTION OF SURFACE ROUGHNESS IN EPITAXIALLY GROWN GERMANIUM BY CONTROLLED THERMAL OXIDATION

Stratio, Inc., Palo Alto...

1. A method for reducing surface roughness in germanium, the method comprising:obtaining a substrate that includes a layer of germanium that has a top surface having a first surface roughness;
depositing a capping layer of silicon oxide on the top surface of the layer of germanium so that the capping layer covers the entire top surface of the layer of germanium; and
subsequent to the depositing, oxidizing the top surface of the layer of germanium through thermal oxidation by diffusing oxygen through the capping layer into the layer of germanium so that the top surface of the layer of germanium is converted into a layer of germanium oxide located on top of an unoxidized layer of germanium, causing a top surface of the unoxidized layer of germanium to have a second surface roughness that is less than the first surface roughness.

US Pat. No. 10,600,639

SIN SPACER PROFILE PATTERNING

Applied Materials, Inc., ...

1. An etching method comprising:oxidizing an exposed nitride surface on a semiconductor substrate within a processing region of a semiconductor processing chamber;
forming an inert plasma within the processing region of the semiconductor processing chamber;
modifying at least part of the oxidized nitride with effluents of the inert plasma;
forming a remote plasma from a fluorine-containing precursor to produce plasma effluents;
flowing the plasma effluents to the processing region of the semiconductor processing chamber; and
removing the modified oxidized nitride from the semiconductor substrate.

US Pat. No. 10,600,637

FORMATION OF SIOC THIN FILMS

ASM IP Holding B.V., Alm...

1. A method of forming a silicon oxycarbide (SiOC) thin film on a substrate in a reaction space by a plasma enhanced atomic layer deposition (PEALD) process, wherein the PEALD process comprises at least one deposition cycle comprising:contacting a surface of the substrate with a vapor phase silicon precursor that does not comprise nitrogen, wherein the vapor phase silicon precursor comprises bis(triethoxysilyl)ethane (BTESE) or 3-methoxypropyltrimethoxysilane (MPTMS);
contacting the surface of the substrate with at least one reactive species generated by plasma formed from a second reactant comprising hydrogen, wherein the second reactant does not comprise oxygen; and
optionally repeating the contacting steps until a SiOC film of a desired thickness has been formed.

US Pat. No. 10,600,636

TOUCH SUBSTRATE AND FABRICATION METHOD THEREOF, AND ELECTRONIC DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A fabrication method of a touch substrate, comprising:providing a substrate; and
sequentially forming a first touch electrode layer, a first insulating layer, a second touch electrode layer, and a second insulating layer on the substrate, wherein the first touch electrode layer comprises a first touch electrode, and the second touch electrode layer comprises a second touch electrode; and
wherein the step of forming the first insulating layer and the step of forming the second insulating layer are performed by using a single mask.

US Pat. No. 10,600,634

SEMICONDUCTOR SUBSTRATE POLISHING METHODS WITH DYNAMIC CONTROL

GlobalWafers Co., Ltd., ...

1. A method for polishing a semiconductor substrate having a front surface and a back surface generally parallel to the front surface, the method comprising:rough polishing a semiconductor substrate by contacting the semiconductor substrate with an abrasive slurry to produce a rough-polished semiconductor substrate;
analyzing the rough-polished semiconductor substrate to measure the edge roll-off of the rough-polished semiconductor substrate, the rough-polished semiconductor substrate having a central axis, the edge roll-off being measured at a reference point, the distance between the central axis and the reference point being about 98.0% or more of the radius of the rough-polished semiconductor substrate;
contacting a front surface of the rough polished semiconductor substrate or a front surface of a different semiconductor substrate with a polishing pad to finish polish the front surface;
supplying a first polishing slurry comprising silica to the polishing pad at a first polishing slurry volume;
supplying a second polishing slurry to the polishing pad at a second polishing slurry volume, the first and second polishing slurries being supplied to finish polish the front surface of the semiconductor substrate, the first polishing slurry comprising a higher concentration of silica relative to the second slurry; and
controlling an amount of at least one of the first polishing slurry and the second polishing slurry supplied to the polishing pad as a whole during the finish polish based on the measured edge roll-off,
wherein the amount of the at least one of the first polishing slurry and the second polishing slurry supplied to the polishing pad is controlled by controlling a ratio of the first polishing slurry volume to the second polishing slurry volume.

US Pat. No. 10,600,630

OVERSAMPLED TIME OF FLIGHT MASS SPECTROMETRY

Micromass UK Limited, Wi...

1. A method of mass spectrometry comprising:passing ions to a Time of Flight mass analyser operating in an oversampling mode of operation wherein ions are pulsed into a Time of Flight region with a pulse rate such that packets or groups of ions associated with multiple different pulses are simultaneously present in the Time of Flight region; and
alternately or sequentially recording ion signals for said ions on a plurality of different channels such that the channel on which the ion signals are recorded changes over time, in order to obtain a plurality of first oversampled mass spectral data sets, each containing overlapping mass spectra associated with packets or groups of ions from multiple different pulses that were simultaneously present in the Time of Flight region, each oversampled mass spectral data set being associated with one of the plurality of different channels, wherein ions arriving at the Time of Flight mass analyser during a first time period are recorded on a first channel to obtain an associated oversampled mass spectral data set and wherein ions arriving at the Time of Flight mass analyser at a second, different time period are recorded on a second channel to obtain another associated oversample mass spectral data set.

US Pat. No. 10,600,629

DETECTION OF ANALYTES USING POROUS MASS SPECTROMETRY SURFACE

THE REGENTS OF THE UNIVER...

1. A method for making a porous semiconductor substrate for ionizing a target comprising:(a) providing a semiconductor material;
(b) determining a desired length of etching time of the semiconductor material based on the molecular weight of the target, and determining a desired porosity wherein the desired porosity is determined to be no more than 40% if the target is larger than 2000 Daltons in molecular weight;
(c) etching the semiconductor material for the desired length of etching time to produce an etched semiconductor material; and
(d) contacting the etched semiconductor material with an initiator to produce the porous semiconductor substrate.

US Pat. No. 10,600,628

RESONANT TRANSMISSION LINE TO DELIVER PRECISION RF VOLTAGE

MKS Instruments, Inc., A...

22. A method of conveying a time-varying voltage signal from a signal generation, control, and analysis subsystem to a quadrupole analyzer, and for monitoring and adaptively controlling an amplitude of the time-varying voltage signal, comprising:electrically coupling the time-varying voltage signal to a first end of a transmission line, the transmission line extending from the first end at the signal generation, control, and analysis subsystem to a second end at the quadrupole analyzer,
configuring a physical length of the transmission line to correspond to an electrical length substantially equal to a positive integer multiple of one half wavelength of the time-varying voltage signal;
sampling, with a rectifier circuit, the time-varying voltage coupled to the first end to produce a feedback signal, and conveying the feedback signal to an adaptive control facility, the adaptive control facility configured to adjust a generator of the time-varying voltage signal, based on a sampling of the time-varying voltage signal at the first end, to maintain the amplitude of the time-varying voltage signal at a required level; and
increasing an amplitude of the time-varying voltage signal with at least one transformer at the second subsystem, the at least one transformer electrically coupled to the second end.

US Pat. No. 10,600,627

HYBRID MASS SPECTROMETER

Micromass UK Limited, Wi...

14. A method of mass spectrometry comprising:separating ions temporally in a first device;
analysing the mass or mass to charge ratio of ions in a mass or mass to charge ratio analyser disposed downstream of said first device;
determining the transit time of ions through an one or more intermediate regions or devices disposed between said first device and said mass to charge ratio analyser; and
switching or adjusting the operation of one or more devices disposed between said first device and said mass or mass to charge ratio analyser based on the determined transit time of ions through said one or more intermediate regions or devices.

US Pat. No. 10,600,621

PLASMA ELECTRODE AND PLASMA PROCESSING DEVICE

TOKYO ELECTRON LIMITED, ...

1. A plasma electrode, comprising:a first electrode plate having a plurality of cylindrical protrusions and to which high frequency power is applied;
a ground plate provided with a plurality of cylindrical first through holes having an inner diameter larger than an outer diameter of the protrusions; and
an insulating plate provided with a plurality of cylindrical second through holes having an inner diameter larger than the outer diameter of the protrusions and disposed between the first electrode plate and the ground plate,
wherein the first electrode plate, the insulating plate, and the ground plate are overlappingly arranged so that the protrusions are arranged inside the first through holes and the second through holes,
a third through hole is provided in each of the protrusions along a center axis of each of the protrusions,
a first flow path is provided between the first electrode plate and the insulating plate,
a second flow path communicating with the first flow path is provided around the protrusions,
a fourth through hole is provided in the ground plate around each of the first through holes,
one of the third through hole and the fourth through hole discharges a first processing gas to below the ground plate,
the other of the third through hole and the fourth through hole exhausts a gas existing below the ground plate,
the second flow path communicates with a gap formed between outer walls of the protrusions and inner walls of the first through holes, and supplies a second processing gas supplied via the first flow path to the gap,
the second processing gas supplied to the gap is converted into plasma in the gap by the high frequency power applied to the first electrode plate,
the third through hole discharges the first processing gas to below the ground plate,
the fourth through hole exhausts the gas existing below the ground plate, and
the fourth through hole has a center axis arranged at a position equidistant from center axes of three adjacent third through holes in the ground plate.

US Pat. No. 10,600,620

TEMPERATURE CONTROL IN RF CHAMBER WITH HEATER AND AIR AMPLIFIER

Lam Research Corporation,...

1. An apparatus, comprising:a heater for receiving and heating a flow of air;
an air amplifier coupled to pressurized gas, the air amplifier having an input that receives the flow of air from the heater, the air amplifier having an output;
a duct coupled to the output of the air amplifier;
a plenum being defined by a partial enclosure having a top surface and side walls, wherein the top surface has an inlet and an open bottom, and wherein the side walls have outlets, the duct is coupled to the inlet and the open bottom of the plenum is placed over a window of a plasma chamber so that the flow of air is distributed over the window;
a temperature sensor situated about the window of the plasma chamber; and
a controller defined to control the air amplifier and the heater based on a temperature measured by the temperature sensor.

US Pat. No. 10,600,611

ION SOURCE CRUCIBLE FOR SOLID FEED MATERIALS

Applied Materials, Inc., ...

1. An indirectly heated cathode ion source, comprising:an arc chamber, comprising a plurality of electrically conductive side walls connecting a first end and a second end;
an indirectly heated cathode disposed on the first end of the arc chamber; and
a crucible disposed on the second end of the arc chamber, wherein the crucible comprises a target holder having a recessed cavity into which a feed material is disposed.

US Pat. No. 10,600,603

SWITCHING DEVICE AND SWITCH-OFF METHOD FOR OPERATING A SWITCHING DEVICE

Siemens Aktiengesellschaf...

1. A switching device, comprising:a first conventional switching point, a second conventional switching point and a non-conventional switching point together forming a series circuit;
said series circuit configured to intentionally ignite an arc in at least one of the conventional switching points when the conventional switching points are switched off; and
said non-conventional switching point being a thyristor.

US Pat. No. 10,600,602

FUSE ELEMENT AND FUSE DEVICE

DEXERIALS CORPORATION, T...

1. A fuse element constituting a current path of a fuse device in which self-generated heat caused by a rate-exceeding current flowing therethrough causes blowout of the fuse element comprising:a low melting point metal layer; and
a high melting point metal layer laminated onto the low melting point metal layer, the high melting point metal layer having a melting point higher than a melting point of the low melting point metal layer;
wherein the fuse element is connected between two electrodes on an insulating substrate and connected onto the electrodes by a solder at a reflow temperature of the solder,
wherein the fuse element has a laminated structure in which the low melting point metal layer is an inner layer and the high melting point metal layer is an outer layer laminated on an upper surface and on a lower surface of the low melting point metal layer, and
wherein the melting point of the low melting point metal layer and a melting point of the solder are equal to or lower than 260° C., and
wherein the low melting point metal layer and the solder are melted at the reflow temperature of the solder.

US Pat. No. 10,600,597

MINIATURE SAFETY SWITCH

1. A miniature safety switch for use in motor vehicle electronics, the miniature safety switch comprising:a housing having a housing base made of an insulating material and a housing cover that can be fitted, or is fitted, on said housing base, said housing base having a base side;
first and second elongate and flat contact arms embedded parallel to one another in terms of a longitudinal direction thereof in said housing base and protrude out at said base side from said housing base;
a fixed contact disposed in said housing and attached to said first contact arm;
a bimetallic snap disk having a moving contact and attached to said second contact arm;
a compression spring being supported on said first contact arm beneath said fixed contact in the longitudinal direction;
a positive temperature coefficient (PTC) resistor being electrically incorporated in such a way that, as a result of heat generated by said PTC resistor, said bimetallic snap disk remains in an open position thereof in an event of triggering, said PTC resistor being brought into direct contact with said bimetallic snap disk by means of said compression spring; and
said compression spring being a conical spring having a base-side spring end contacting said first contact arm and an apex-side spring end contacting said PTC resistor.

US Pat. No. 10,600,594

GAS-INSULATED VACUUM LOAD BREAK SWITCH

ABB Schweiz AG, Baden (C...

1. A gas-insulated vacuum load break switch, comprising:a conductive line, a control operating mechanism, a support box and a transmission apparatus, wherein
the conductive line has three phases, the three phases of the conductive line being of a same structure and independent from each other;
each phase of the conductive line comprises a load break switch unit with a vacuum interrupter, an isolating switch unit with an isolator, a plastic housing supporting the load break switch unit and the isolating switch unit, and an earthing switch unit;
the control operating mechanism comprises a load break switch operating mechanism for controlling the load break switch unit, an operating rod for controlling the isolating switch unit, and an earthing switch operating mechanism for controlling the earthing switch unit; and
the transmission apparatus comprises a load break switch transmission apparatus for the load break switch unit, an isolating switch transmission apparatus for the isolating switch unit, and an earthing switch transmission apparatus for the earthing switch unit.

US Pat. No. 10,600,592

SINGLE BOTTLE INTERRUPTER

Hubbell Incorporated, Sh...

1. A vacuum interrupter for interrupting a voltage, the vacuum interrupter comprising:a vacuum bottle having a single pair of axially separable contacts, wherein at least one of the separable contacts is a moveable contact;
a jacket encasing the vacuum bottle, wherein the jacket has a ribbed outer surface;
a housing, having an inner surface and a circumferentially ribbed outer surface, wherein the housing encases the jacket such that the inner surface of the housing interfaces with the ribbed outer surface of the jacket;
a bi-stable mechanism including,
an actuator, and
a cam pivotable by the actuator, the cam moving the moveable contact; and
a bellows assembly positioned above the vacuum bottle and coupled to the housing, the bellows assembly including an outer cylindrical shell surrounding an opening spring, a spring plate, a contact spring, and a bellows, the bellows assembly reciprocating the moveable contact to prevent arcing between the pair of contacts and biasing the pair of contacts apart from each other.

US Pat. No. 10,600,591

LUMINOUS KEYBOARD HAVING TRANSLUCENT LIGHT DIFFUSING RUBBER DOMES

PRIMAX ELECTRONICS LTD., ...

1. A luminous keyboard, comprising:a plurality of keys, each of the keys comprising:
a key cap;
a scissors foot mechanism, located below the key cap and pivotally connected to the key cap; and
a rubber dome, disposed below the key cap and pushing the key cap upward, wherein the rubber dome is made of a translucent material doped with a plurality of light-diffusion particles, and when the rubber dome is irradiated by a light ray, a part of the light ray passes through the rubber dome, and the other part of the light ray is reflected by the rubber dome;
a thin-film circuit board, disposed below the rubber dome, wherein the rubber dome can receive an external force from the key cap to be deformed downward to trigger the thin-film circuit board to generate an input signal;
a support plate, located below the thin-film circuit board, wherein the scissors foot mechanism passes through the thin-film circuit board to be pivotally connected to the support plate, and the support plate comprises a plurality of light-transmission through holes;
a light guide plate, located below the support plate, wherein the light guide plate comprises an upper surface and a plurality of light-diffusion protrusions formed on the upper surface;
a reflector, located below the light guide plate; and
a circuit board assembly, located below the reflector, wherein the circuit board assembly comprises a printed circuit board and a plurality of light sources electrically connected to the printed circuit board, and each of the keys corresponds to at least one of the light source, so that each of the keys receives the light ray emitted from the light source, wherein
after the light ray sequentially passes through the light guide plate, the support plate, and the thin-film circuit board, the part of the light ray passes through the rubber dome and then, is emitted outward through the key cap, and the other part of the light ray is reflected for a first time as being reflected downward by the rubber dome, then is reflected for a second time as being reflected outward by the reflector, is diffused by the light-diffusion protrusions of the light guide plate, and finally, is emitted outward through the key cap.

US Pat. No. 10,600,589

KEYBOARD HAVING A SWITCH DEVICE

LENOVO (SINGAPORE) PTE LT...

1. A switch device comprising:a base plate;
a push button movable orthogonal to an upper surface side of said base plate when said push button is depressed;
a pair of stabilizer members supported between said push button and said base plate, wherein each of said pair of stabilizer members includes
a first shaft portion rotatably supported on a lower surface side of said push button; and
a second shaft portion, which has a rotation axis parallel to a rotation axis of said first shaft portion, rotatably supported by a bearing provided on said upper surface side of said base plate; and
a multi-layered membrane sheet located on an upper surface of said base plate, wherein said membrane sheet includes a first sheet in contact with said base plate, a second sheet in contact with said second shaft portion, and a third sheet in contact with said first and second sheets, wherein only said first sheet is provided with a cut-out shaped portion in an area corresponding to an area within which said second shaft portion is allowed to move.

US Pat. No. 10,600,587

ELECTRICAL SWITCHING APPARATUS AND TRANSFER ASSEMBLY THEREFOR

EATON INTELLIGENT POWER L...

1. A transfer assembly for an electrical switching apparatus, said electrical switching apparatus comprising a first housing, a pair of separable contacts disposed internal with respect to said first housing, and an operating handle having an ON position and an OFF position, the ON position corresponding to said separable contacts being closed, the OFF position corresponding to said separable contacts being open, said transfer assembly comprising:a rotary handle;
a number of transfer components each structured to cooperate with said rotary handle, one of said transfer components being structured to engage said operating handle in order to allow said rotary handle to move said operating handle between the ON position and the OFF position; and
a support assembly comprising a second housing and a support member coupled to and disposed internal with respect to said second housing, said second housing being structured to be coupled to said first housing, said rotary handle being coupled to said second housing,
wherein each of said transfer components is coupled to said support member,
wherein said support member and said second housing are separate and distinct components,
wherein said one of said transfer components is a sliding member; and wherein said support assembly further comprises a number of coupling members extending through said support member and at least partially into said sliding member in order to couple said sliding member to said support member, and
wherein said support member comprises a first wall, a second wall disposed opposite and generally parallel to said first wall, and a third wall extending between and being disposed generally perpendicular to said first wall and said second wall; and wherein said coupling members extend through said third wall.

US Pat. No. 10,600,583

METHOD OF MAKING A POROUS NITROGEN-DOPED CARBON ELECTRODE FROM BIOMASS

King Saud University, Ri...

1. A method of making a porous nitrogen-doped carbon electrode from date palm (Phoenix dactylifera L.) pollen grains, comprising the steps of:stirring a volume of date palm (Phoenix dactylifera L.) pollen grains into an aqueous solution of potassium hydroxide (KOH) for one hour to produce a precursor carbon solution;
drying the precursor carbon solution for a period of six hours at a temperature of 80° C. to produce precursor carbon;
heating the precursor carbon at a temperature of 800° C. for two hours under an argon atmosphere to produce porous nitrogen-doped graphite carbon;
washing the porous nitrogen-doped graphite carbon in an aqueous solution of HCl, deionized water, and ethanol;
drying the porous nitrogen-doped graphite carbon for 24 hours at a temperature of 80° C.;
mixing the porous nitrogen-doped graphite carbon with a polyvinylidene difluoride (PVDF) binder and carbon black in an isopropanol solvent to form a slurry; and
coating nickel foam with the slurry to form a porous nitrogen-doped carbon electrode and dried at a temperature of 100° C., wherein the dried nitrogen-doped carbon electrode has a porous, cage-type structure wherein the pore volume is at least 0.8 cm3/g, having a Brunauer-Emmett-Teller (BET) surface area within about 86-87 m2/g, a wall thickness of at least about 30.8-80.0 nm and a mean pore diameter in the range of about 50 to about 450 nm.

US Pat. No. 10,600,581

ELECTRIC DOUBLE LAYER CAPACITANCE DEVICE

BASF SE, Ludwigshafen (D...

1. An electrode comprising a binder and activated carbon, wherein the activated carbon comprises:a surface area of greater than 1500 m2/g, as determined by nitrogen sorption at 77 K and BET analysis; and
a pore structure comprising mesopores having a diameter ranging from 2.0 nm to 10.0 nm and a pore volume ranging from 0.01 cc/g to 0.25 cc/g for pores having a pore diameter of 0.6 nm to 1.0 nm, as determined from N2 sorption derived DFT,
wherein the electrode has a specific capacitance of at least 100 F/g and a specific power of at least 25 W/g when each of the specific capacitance and specific power is measured in an electric double layer capacitor device comprising an electrolyte comprising equal volumes of propylene carbonate and dimethylcarbonate and further comprising 1.0 M tetraethylammonium tetrafluoroborate.

US Pat. No. 10,600,580

EXPLOSION-PROOF APPARATUS

SAMSUNG ELECTRONICS CO., ...

1. An explosion-proof apparatus comprising:a stopper having a hollow cylindrical shape that is open at a first side and closed at a second side opposite to the first side, the stopper being configured to be combined with an electrolytic condenser by surrounding a top side of the electrolytic condenser and a lateral side of the electrolytic condenser connected to the top side, through the first side of the stopper; and
a holder provided on the stopper and configured to support the stopper to be combined to the electrolytic condenser,
wherein the first side of the stopper is spaced apart from the top side of the electrolytic condenser.

US Pat. No. 10,600,576

VOLUMETRIC EFFICIENCY WET ELECTROLYTE CAPACITOR HAVING A FILL PORT AND TERMINATIONS FOR SURFACE MOUNTING

VISHAY SPRAGUE, INC., Be...

1. A wet electrolytic capacitor, comprising:a body defining an interior area and comprising a fill port formed through a wall of the body, the body having a first portion and a second portion;
a compressible fill port plug positioned adjacent the fill port;
a fill port cover welded to the body and covering the fill port plug and configured to compress the fill port plug against the fill port to seal the fill port.

US Pat. No. 10,600,573

CAPACITOR COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor component comprising:a body in which a dielectric layer and an internal electrode are alternately stacked; and
an external electrode disposed on the body and connected to the internal electrode,
wherein the dielectric layer includes a composite layer including a first dielectric material and a metallic particle and first and second protective layers spaced apart by the composite layer and including a second dielectric material; and
wherein a thickness of each of the first and second protective layers is equal to or greater than ? of a thickness of the dielectric layer.

US Pat. No. 10,600,572

DIELECTRIC COMPOSITION AND MULTILAYER CERAMIC CAPACITOR CONTAINING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic capacitor comprising:a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and
first and second external electrodes disposed on an external surface of the ceramic body,
wherein each dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell including Ba(Ti1-xSnx)O3, the shell covering at least 30% of a surface of the core, and the shell having a thickness within a range of 2 nm to 50 nm.

US Pat. No. 10,600,571

MULTILAYER CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component comprising:a ceramic body including dielectric layers and first and second internal electrodes alternately laminated with the dielectric layers disposed therebetween in a stacking direction, the first and second internal electrodes being exposed to first and second external surfaces of the ceramic body, respectively, in a length direction; and
first and second external electrodes disposed on the first and second external surfaces of the ceramic body to be electrically connected to the first and second internal electrodes, respectively, the first and second external electrodes extending along a surface of the ceramic body in the length direction,
wherein Lb/La is greater than zero and less than or equal to 0.6, where a longest distance from the first external electrode to the second external electrode in the length direction is denoted by “La”, and a shortest distance from the first external electrode to the second external electrode in the length direction is denoted by “Lb”,
wherein BWd is greater than BWc, where an average length of an extending portion of each of the first and second external electrodes in the length direction, corresponding to an edge of the ceramic body, is denoted by “BWc”, and an average length of an extending portion of each of the first and second external electrodes in the length direction, corresponding to a center of the surface of the ceramic body is denoted by “BWd”,
wherein the ceramic body has a hexahedral shape having at least one rounded corner, and
wherein 0

US Pat. No. 10,600,569

FINGER METAL-ON-METAL CAPACITOR CONTAINING NEGATIVE CAPACITANCE MATERIAL

QUALCOMM Incorporated, S...

9. An integrated circuit, comprising:a first layer comprising a plurality of electrodes;
a dielectric layer deposited in a channel between at least one set of electrodes of the first layer and formed on sidewalls of the plurality of electrodes of the first layer, the channel extending between a sidewall of a first electrode and a sidewall of a second electrode of the at least one set of electrodes;
a negative capacitance material deposited in the channel;
a second dielectric layer formed across an upper surface of the plurality of electrodes, an upper surface of the dielectric layer, and an upper surface of the negative capacitance material;
a second layer comprising a plurality of electrodes formed on the second dielectric layer;
a third dielectric layer deposited in a channel between at least one set of electrodes of the plurality of electrodes of the second layer and formed on sidewalls of the plurality of electrodes of the second layer, the channel extending between a sidewall of a third electrode and a sidewall of a fourth electrode of the at least one set of electrodes of the plurality of electrodes of the second layer; and
a second negative capacitance material deposited in the channel between the at least one set of electrodes of the plurality of electrodes of the second layer.

US Pat. No. 10,600,568

CAPACITOR AND METHOD OF FABRICATING THE SAME

United Microelectronics C...

1. A capacitor, comprising:a first electrode located on a top surface of a dielectric layer;
a dielectric covering a sidewall and a top surface of the first electrode; and
a second electrode covering the dielectric and the dielectric layer, wherein an orthographic projection area of the second electrode on the dielectric layer is greater than an orthographic projection area of the first electrode on the dielectric layer, and a bottommost surface of the second electrode is in direct physical contact with the dielectric layer, wherein the bottommost surface of the second electrode is coplanar with a bottommost surface of the first electrode and a bottommost surface of the dielectric.

US Pat. No. 10,600,567

MULTILAYER CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer capacitor comprising:a capacitor body; and
a plurality of outer connectors provided on outer surfaces of the capacitor body; wherein
the capacitor body includes a plurality of dielectric layers and a plurality of conductor layers stacked alternatingly along a height direction;
the capacitor body includes a first principal surface and a second principal surface that face each other in the height direction, a first side surface and a second side surface that face each other in a length direction that is perpendicular or substantially perpendicular to the height direction, and a third side surface and a fourth side surface that face each other in a width direction that is perpendicular or substantially perpendicular to the height direction and the length direction;
the plurality of outer connectors includes:
a first outer connector that covers a first portion of the first side surface, a first portion of the third side surface, and a first portion of at least one of the first and second principal surfaces;
a second outer connector that covers a first portion of the second side surface, a first portion of the fourth side surface, and a second portion of at least one of the first and second principal surfaces;
a third outer connector that covers a second portion of the second side surface, a second portion of the third side surface, and a third portion of at least one of the first and second principal surfaces; and
a fourth outer connector that covers a second portion of the first side surface, a second portion of the fourth side surface, and a fourth portion of at least one of the first and second principal surfaces;
the plurality of conductor layers includes a plurality of first conductor layers connected to the first and second outer connectors and a plurality of second conductor layers connected to the third and fourth outer connectors;
the capacitor body includes an effective portion defined by electrostatic capacitance portions stacked along the height direction, each of the electrostatic capacitance portions being defined by one of the plurality of first conductor layers and one of the plurality of second conductor layers being disposed opposite to each other with one of the plurality of dielectric layers interposed therebetween;
in a case where L0 is a maximum external dimension of the multilayer capacitor in the length direction, W0 is a maximum external dimension of the multilayer capacitor in the width direction, and H0 is a maximum external dimension of the multilayer capacitor in the height direction, L0, W0, and H0 satisfy a condition of 2.67?L0/H0 and further satisfy a condition of 1/1.72?L0/W0?1.72; and
the effective portion overlaps with one or more of portions of the first, second, third, and fourth outer connectors that cover one or more of the first, second, third and fourth portions of the at least one of the first principal surface and the second principal surface when viewed in the height direction.

US Pat. No. 10,600,565

MANUFACTURE METHOD OF COIL COMPONENT, AND COIL COMPONENT

Murata Manufacturing Co.,...

1. A coil component comprising:a base insulating resin;
a first spiral wiring stacked on the base insulating resin;
a first insulating resin that is stacked on the first spiral wiring, the first insulating resin covering the first spiral wiring;
a second spiral wiring that is stacked directly on and in direct contact with the first insulating resin, the second spiral wiring being connected to the first spiral wiring through a via wiring extending in a layer stacking direction;
a second insulating resin that is stacked on the second spiral wiring, the second insulating resin covering the second spiral wiring; and
a magnetic resin that covers a lower surface of the base insulating resin and an upper surface of the second insulating resin, the magnetic resin being in direct contact with a surface of the base insulating resin opposite to the first insulating resin,
wherein the first spiral wiring is stacked on and in direct contact with the base insulating resin, and
an innermost side edge of the first and second insulating resins have a tapered cross-section.

US Pat. No. 10,600,564

INDUCTIVE POWER TRANSFER SYSTEM PRIMARY TRACK TOPOLOGIES

AUCKLAND UNISERVICES LIMI...

1. A multiphase Inductive Power Transfer (IPT) primary track conductor arrangement comprising phase conductors including a first phase conductor and a second phase conductor, the phase conductors being arranged substantially in a plane and being operable to provide a magnetic field for inductive power transfer on one side of the plane, the phase conductors also being arranged to overlap each other such that there is minimal mutual coupling between the phase conductors, and the arrangement being associated with a magnetically permeable member, the magnetically permeable member being provided on an opposite side of the plane,wherein a forward current path of the first phase conductor and a return current path of the first phase conductor are arranged to produce a first series of alternating pole areas, and a forward current path of the second phase conductor and a return current path of the second phase conductor are arranged to produce a second series of alternating pole areas, and wherein the magnetically permeable member is configured to channel flux between adjacent pole areas.

US Pat. No. 10,600,561

COIL DEVICE

IHI CORPORATION, Tokyo (...

1. A first coil device that faces a second coil device in a first direction and wirelessly performs power transmission or power reception, the first coil device comprising:a first coil portion that faces a second coil portion of the second coil device in the first direction and includes a conductive wire;
at least one nonmagnetic member that includes a protrusion protruding to an outside of the first coil portion in a second direction orthogonal to the first direction;
the nonmagnetic member includes an eddy current interrupter that interrupts a part of an eddy current generated in the nonmagnetic member;
the nonmagnetic member includes a hollow portion recessed to an opposite side from a side facing the second coil portion in the first direction such that the protrusion extends from within the recessed hollow portion, down a side wall defining the recess of the hollow portion and outward from the recessed hollow Portion in the second direction;
the protrusion having a discontinuous portion in a portion of the protrusion extending down the side wall such that the hollow portion is disconnected from a portion of the protrusion that extends outward from the recessed hollow portion in the second direction; and
the first coil portion is located within the hollow portion.

US Pat. No. 10,600,560

ELECTRONIC COMPONENT INCLUDING OUTER ELECTRODES AND A SHIELD ELECTRODE

MURATA MANUFACTURING CO.,...

1. An electronic component comprising:a main body having a rectangular or substantially rectangular parallelepiped shape;
an inner conductor that is provided inside the main body;
one or more outer electrodes that are provided on a bottom surface of the main body and are not provided on four side surfaces of the main body; and
a shield electrode that covers the four side surfaces of the main body and has a rectangular or substantially rectangular cylindrical shape; wherein
the shield electrode is not physically connected to the one or more outer electrodes at a surface of the main body and is physically connected to the inner conductor at a surface of the main body; and
the main body includes a stack of a plurality of insulator layers on top of one another in a stacking direction that connects the top surface and the bottom surface of the main body;
the plurality of insulator layers include a first insulator layer; and
the electronic component further comprises;
one or more passive elements that are provided in the main body; and
a first ground conductor that is provided on the first insulator layer, which is positioned closer to the top surface of the main body than the one or more passive elements.

US Pat. No. 10,600,552

SURFACE-MOUNTED REACTOR AND MANUFACTURING METHOD THEREFOR

HITACHI METALS, LTD., To...

1. A surface mountable reactor, comprising:a coil;
a first magnetic core comprising an axial portion around which the coil is disposed and flange portions at both ends of the axial portion;
a second magnetic core that is disposed outside the coil to connect the flange portions of the first magnetic core; and
a resin mount disposed outside the coil, wherein the second magnetic core comprises a plurality of components separable toward outside the coil,
a circumference of the coil is surrounded by the second magnetic core and the resin mount,
the coil is housed in a space surrounded by (i) the flange portions of the first magnetic core, (ii) the second magnetic core, and (iii) the resin mount, and
the coil has end portions disposed outside the resin mount to form mount terminals.

US Pat. No. 10,600,544

STACKED BODY AND METHOD OF PRODUCING STACKED BODY

MURATA MANUFACTURING CO.,...

1. A stacked body comprising:a base including a plurality of insulating base material layers made of thermoplastic resin;
a conductive pattern located on the plurality of insulating base material layers; and
a dummy pattern electrically isolated from the conductive pattern and extending along at least a portion of the conductive pattern outside of the conductive pattern on the plurality of insulating base material layers on which the conductive pattern is located in a plan view; wherein
the plurality of insulating base material layers are stacked on each other;
the conductive pattern includes a plurality of linear portions at an outermost side of the conductive pattern in a plan view;
the dummy pattern is located along the conductive pattern; and
a bent portion or a wide portion, which has a larger width than the other linear portions in a direction perpendicular or substantially perpendicular to a direction in which a linear portion extends, in a plan view, is located on at least one of the linear portion of the conductive pattern and the dummy pattern extending along the linear portion, excluding an end portion of the linear portion and an end portion of the dummy pattern.

US Pat. No. 10,600,542

POLARITY-SWITCHING MAGNET DIODE

1. A polarity-switching magnetic diode comprising:a first non-magnetized ferrous element magnetically coupled to a magnetic flux element;
a second non-magnetized ferrous element magnetically coupled to the magnetic flux element;
wherein the magnetic flux element comprises a first effective pole, a second effective pole, and a first gap; and
a control coil wrapped around a portion of the magnetic flux element such that the first gap extends at least partially into the control coil, wherein the control coil has a first active magnetic state and a second active magnetic state,
wherein the first active magnetic state directs a north temporary polarity from the first non-magnetized ferrous element along the magnetic flux element towards the first effective pole and directs a south temporary polarity from the second non-magnetized ferrous element along the magnetic flux element towards the second effective pole; and
wherein the second active magnetic state directs the north temporary polarity from the first non-magnetized ferrous element along the magnetic flux element towards the second effective pole and directs the south temporary polarity from the second non-magnetized ferrous element along the magnetic flux element towards the first effective pole.

US Pat. No. 10,600,519

NUCLEAR REACTOR MODULE

ROLLS-ROYCE plc, London ...

1. A method of constructing a nuclear reactor module, the method comprising:providing a first formwork defining a chamber in which is mounted a nuclear reactor comprising a nuclear reactor pressure vessel configured to contain nuclear fuel when in use;
providing a second formwork defining a containment structure configured to contain an internal pressure generated by an escape of coolant from a reactor coolant circuit, the first formwork being housed within the second formwork;
filling one or more voids within the first formwork with concrete through at least one concrete supply pipe that extends from outside of the second formwork, through the second formwork, and through a wall of the first formwork so as to open into the one or more voids of the first formwork;
forming the containment structure by filling one or more voids within the second formwork with concrete; and
venting the one or more voids within the first formwork through one or more vent pipes, thereby forming a concrete support structure for the nuclear reactor,
wherein the filling of the one or more voids within the second formwork occurs after the filling of the one or more voids within the first formwork.