US Pat. No. 10,797,735

RF CONTROL CIRCUIT AND MOBILE TERMINAL

GUANGDONG OPPO MOBILE TEL...

1. A radio frequency (RF) control circuit, comprising:a transceiver module, configured to transmit a primary component carrier (PCC) signal of a local data signal and receive a PCC signal of an external data signal through a PCC path, and configured to transmit a secondary component carrier (SCC) signal of the local data signal and receive a SCC signal of the external data signal through a SCC path,
wherein the transceiver module comprises: an access point (AP), configured to transmit the local data signal to a RF transceiver chip and receive the external data signal from the RF transceiver chip; and
the RF transceiver chip is configured to transmit and receive the PCC signals through the PCC path and transmit and receive the SCC signals through the SCC path;
a front-end module, configured to receive the external data signal and transmit the local data signal;
a power amplifier connected between the transceiver module and the front-end module, and configured to perform an amplification processing on the local data signal;
wherein a PCC signal-output terminal of the power amplifier is connected to the front-end module such that a transmission sub-path of the PCC path is formed; and
a SCC signal-output terminal of the power amplifier is connected to the front-end module such that a transmission sub-path of the SCC path is formed; and
a working mode switching switch,
wherein a switch-control terminal of the working mode switching switch is connected to the AP, a switch-input terminal of the working mode switching switch is connected to a transmission sub-path of the SCC path, and a switch-output terminal of the working mode switching switch is grounded,
when the SCC path or the PCC path operates separately, the working mode switching switch is turned off such that the transmission sub-path of the SCC path is disconnected to the ground;
when the SCC path and the PCC path operate simultaneously, the working mode switching switch is turned on such that the transmission sub-path of the SCC path is connected to the ground;
wherein when a signal-transmitting process is performed on both the SCC path and the PCC path simultaneously, the AP transmits the local data signals to the RF transceiver chip;
the RF transceiver chip transmits the local data signals to the power amplifier through a signal-transmitting terminal;
the power amplifier then transmits amplified local data signals in a SCC frequency band to the ground through the SCC signal-output terminal, the transmission sub-path of the SCC path, and the working mode switching switch;
at the same time, the power amplifier transmits amplified local data signals in a PCC frequency hand to the front-end module through the PCC signal-output terminal and the transmission sub-path of the PCC path; and the front-end module then transmits the amplified local data signals in the PCC frequency band.

US Pat. No. 10,797,734

SYSTEM WITH MULTIPLE VIRTUAL RADIO UNITS IN A RADIO UNIT THAT IS REMOTE FROM AT LEAST ONE BASEBAND CONTROLLER

CommScope Technologies LL...

1. A communication system, comprising:at least one baseband controller configured to process signals in a baseband frequency band;
at least one radio unit that is physically remote from the at least one baseband controller, wherein each radio unit comprises:
a plurality of virtual radio units (VRUs) in a physical housing of the respective radio unit, wherein at least two of the plurality of VRUs are each implemented in a different processing core of a programmable processor;
a fronthaul interface configured to communicate with the at least one baseband controller using a packet-based protocol on behalf of each VRU; and
at least one radio frequency front end unit configured to transmit from and receive on behalf of each of the VRUs.

US Pat. No. 10,797,733

DISTRIBUTED ANTENNA SYSTEMS

Genghiscomm Holdings, LLC...

1. A multi-user multiple antenna system, comprising:a central processor;
the central processor communicatively coupled to a plurality of distributed access points via a network;
the central processor configured to select two or more of the plurality of distributed access points to serve each of a plurality of user devices based on signal power of wireless links between each user device and the plurality of distributed access points; and
the central processor employing subspace processing of signals transmitted and/or received across the plurality of distributed access points for producing a plurality of non-interfering spatial subchannels.

US Pat. No. 10,797,732

DISTRIBUTED ANTENNA SYSTEMS

Genghiscomm Holdings, LLC...

1. A multi-user multiple antenna system, comprising:a central processor; and
a plurality of geographically distributed access points communicatively coupled to the central processor via a network and configured to serve a plurality of client devices;
wherein the central processor, the plurality of geographically distributed access points, or the plurality of client devices computes channel estimates of wireless channels between the geographically distributed access points and the client devices;
and wherein the central processor computes access-point weights from the channel estimates to synthesize an antenna array from the plurality of geographically distributed access points that implements spatial multiplexing.

US Pat. No. 10,797,731

SOFTWARE DEFINED RADIO FOR AUXILIARY RECEIVER

Microsoft Technology Lice...

1. A first base station comprising:a wireless receiver configured to communicate in accordance with a plurality of protocols;
a processor; and
a memory in communication with the processor, the memory comprising executable instructions that, when executed by the processor, cause the processor to control the first base station to perform functions of:
determining whether to operate in a primary mode or in an auxiliary mode, wherein while operating in the auxiliary mode, the first base station provides an additional bandwidth for a source device that is in communication with a second base station different from the first base station;
in response to determining to operate in the auxiliary mode:
scanning a range of frequencies and detecting an uplink transmission sent by the source device to the second base station;
based on the detected uplink transmission, determining, from the plurality of protocols, a protocol used by the source device for the uplink transmission;
configuring the wireless receiver to operate according to the determined protocol used by the source device for the uplink transmission;
intercepting, using the wireless receiver operating according to the determined protocol, a first data stream sent from the source device to a destination device via the second base station, the first data stream being addressed to the destination device; and
sending, to the destination device, the intercepted first data stream as a second data stream, wherein the second data stream is a redundant data stream with respect to the first data stream.

US Pat. No. 10,797,730

APPARATUS AND METHOD FOR CREATING AN ASYMMETRIC CHECKSUM

SIEMENS AKTIENGESELLSCHAF...

1. A method for a first communication partner to create an asymmetric checksum on a computer-aided basis, the method comprising:computing, by a processor of a computing system, a mapped checksum by means of a bijective mapping of a first checksum, wherein the first checksum is assigned from a set of all possible checksums to a respective message from a set of all possible messages by means of a first function, the first checksum is conditioned by virtue of a second function mapping the set of all possible checksums onto a first set of checksums;
distributing, by the processor, a piece of information that defines an inverse function for the bijective mapping of the first checksum to at least one second communication partner, wherein the inverse function is used to compute the first checksum from the mapped checksum; and
transmitting, by the processor, the mapped checksum and the respective message to the at least one second communication partner.

US Pat. No. 10,797,729

POLAR-CODE BASED ENCODER AND METHOD FOR CONFIGURING DIVIDE AND CONQUER STRUCTURE OF POLAR-CODE BASED ENCODER

MITSUBISHI ELECTRIC CORPO...

1. A method for configuring a Divide and Conquer structure of a polar-code based encoder performing a transfer of useful data to a polar-code based decoder via a Binary Discrete-input Memory-less Channel, the method being performed by the polar-code based encoder, the Divide and Conquer structure consisting of a multiplexer followed by a polarization block of size N=2L, the multiplexer having useful data bits and a set of frozen bits as inputs so as to form input data x1:N(in),wherein the polarization block of size N comprises a set of front kernels followed by a shuffler and two complementary polarization sub-blocks of size N/2 with a similar structure as the polarization block of size N but with half its size, wherein the shuffler distributes its odd entries to one of the complementary polarization sub-blocks and its even entries to the other one of the complementary polarization sub-blocks, such that the Divide and Conquer structure is recursive with a depth equal to L,
wherein a dynamically configurable interleaver is present between the shuffler and one and/or the other of the complementary polarization sub-blocks at each recursion of the Divide and Conquer structure,
and in that the method comprises:
detecting change in the Binary Discrete-input Memory-less Channel;
obtaining probability functions p1:N(out), which characterize channel transitions probabilities of the Binary Discrete-input Memory-less Channel at output of the polarization block of size N, according to the detected change in the Binary Discrete-input Memory-less Channel;
computing probability functions p1:N(in), which characterize channel transitions probabilities of an equivalent Binary Discrete-input Memory-less Channel at input of the polarization block of size N, from the obtained probability functions p1:N(out) for a set of interleaving configurations of the dynamically configurable interleavers, determining corresponding positions of the frozen bits and determining a corresponding figure of merit value, wherein the figure of merit is an estimation representative of performance of the transfer to the polar-code based decoder via the Binary Discrete-input Memory-less Channel; and
selecting and applying the interleaving configuration of the dynamically configurable interleavers which shows the best performance of the transfer to the polar-code based decoder via the Binary Discrete-input Memory-less Channel in view of the determined corresponding figure of merit values.

US Pat. No. 10,797,728

SYSTEMS AND METHODS FOR DIVERSITY BIT-FLIPPING DECODING OF LOW-DENSITY PARITY-CHECK CODES

Marvell Asia Pte, Ltd., ...

1. A method for decoding an LDPC codeword, the method comprising:performing, using a processing circuitry comprising at least one decoder, a first iteration of decoding the LDPC codeword using a first decoding technique comprising first instructions to produce a first decoding output;
determining, whether the LDPC codeword has been decoded;
in response to determining that the LDPC codeword has not been decoded:
calculating a first syndrome weight of the first decoding output;
computing a difference between the first syndrome weight of the first decoding output and an original syndrome weight of the LDPC codeword;
comparing the computed difference between the first syndrome weight and the original syndrome weight to a threshold syndrome weight;
in response to determining that the computed difference between the first syndrome weight and the original syndrome weight is greater than the threshold syndrome weight:
decoding, using the processing circuitry, the LDPC codeword using a second decoding technique, comprising second instructions different from the first instructions of the first decoding technique, to produce a second decoding output;
in response to determining that the computed difference between the first syndrome weight and the original syndrome weight is less than the threshold syndrome weight:
performing a second iteration of decoding the LDPC codeword using the first decoding technique.

US Pat. No. 10,797,727

LOW-DENSITY PARITY-CHECK (LDPC) ENCODE USING AN LDPC DECODER

Xilinx, Inc., San Jose (...

1. A decoder circuit, comprising:a low-density parity-check (LDPC) repository to store parity-check information associated with one or more LDPC codes;
an LDPC code configurator configured to receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and to update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code;
LDPC decoder circuitry configurable, based on control signals, to perform LDPC decoding of codewords or LDPC encoding of information using the parity-check information from the LDPC repository; and
wherein the LDPC decoder circuitry includes a plurality of circuit blocks forming a data path, wherein the data path is configured to selectively bypass selected ones of the plurality of circuit blocks in response to the control signals indicating encode or decode.

US Pat. No. 10,797,726

NETWORK DATA PREDICTION METHOD, NETWORK DATA PROCESSING DEVICE AND NETWORK DATA PROCESSING METHOD

REALTEK SEMICONDUCTOR COR...

6. A standalone network data processing device that does not comprise a communication network or channel, comprising:a data processing circuit configured to generate a first data block and a second data block according to an Open Systems Interconnection model (OSI model);
an error detection data generating circuit coupled to the data processing circuit and configured to process the first data block based on an error detection method to generate a first check code;
an encoding circuit coupled to the error detection data generating circuit and configured to encode the first data block and the first check code to generate a first network data;
a data transceiving circuit coupled to the encoding circuit and configured to transmit the first network data and receive a second network data, wherein the second network data comprises a second check code; and
a decoding circuit coupled to the data processing circuit and the data transceiving circuit and configured to perform decoding to generate a target data from a portion of the second data block and a portion of the second network data, and configured to use the second check code to check the target data to generate a check result
wherein the data processing circuit processes the target data when the check result indicates that the target data is correct, or the decoding circuit decodes the second network data when the check result indicates that the target data is incorrect.

US Pat. No. 10,797,725

PARALLEL-TO-SERIAL CONVERSION CIRCUIT

SK hynix Inc., Gyeonggi-...

1. A parallel-to-serial conversion circuit comprising:first to fourth data lines;
first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; and
first to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line,
wherein two of the first to fourth drivers are simultaneously activated.

US Pat. No. 10,797,724

METHOD AND APPARATUS FOR PROCESSING DATA

BEIJING BAIDU NETCOM SCIE...

1. A method for processing data, comprising:sorting to-be-compressed at least one piece of data in a predetermined order;
for a piece of data in the sorted at least one piece of data, in response to the piece of data having a common prefix with a previous piece of data of the piece of data, adding the common prefix to a common prefix set;
dividing the sorted at least one piece of data into at least one group based on the common prefix set and determining a common prefix of each group, wherein dividing the sorted at least one piece of data comprises:
determining a local minimum value of lengths of common prefixes in the common prefix set,
diving the at least one piece of data in to the at least one group according to the local minimum value, data corresponding to the local minimum value being divided into a next group, and
for a group in the at least one group, determining a longest common prefix corresponding to the data in the group as a common prefix of the group; and
for the group in the at least one group, storing the common prefix of the group and a non-common prefix portion of each piece of data in the group, and recording a common prefix corresponding to each piece of data in the each group and a shared length between the each piece of data and the common prefix.

US Pat. No. 10,797,723

BUILDING A CONTEXT MODEL ENSEMBLE IN A CONTEXT MIXING COMPRESSOR

International Business Ma...

1. A method of adding context models to a context model ensemble in a context mixing compressor of a data storage system, the method comprising:for each context model among more than two different context models included in a base set of context models, measuring, by a controller, a respective individual compression ratio (CR) of a context mixing compressor obtained by utilizing said each context model alone on a common dataset;
based on the measuring of the respective individual CRs, adding to a context model ensemble, by the controller, a first context model within the base set of context models that has a maximum measured CR when utilized alone to compress the common dataset;
following addition of the first context model to the context model ensemble and based on a desired number of distinct context models not being in the context model ensemble, said desired number being at least two:
measuring, by the controller, a respective CR for the context mixing compressor on the common dataset for each of the context models in the base set of context models that is not in the context model ensemble as utilized in conjunction with one or more context models already added to the context model ensemble; and
adding to the context model ensemble, by the controller, one or more additional context models, in the base set of context models, that, utilized in conjunction with the one or more context models already added to the context model ensemble, result in a maximum CR for the common dataset, wherein the adding the one or more additional context models is performed until the context model ensemble has increased to the desired number of distinct context models, and wherein limiting a size of the context model ensemble to the desired number of context models increases throughput while only marginally reducing the maximum subsequent CR that is achieved by the data storage system.

US Pat. No. 10,797,722

SYSTEM AND METHOD FOR PROVIDING HARDWARE BASED FAST AND SECURE EXPANSION AND COMPRESSION FUNCTIONS

The Boeing Company, Chic...

1. A method for encoding data with low side channel leakage comprising the steps of:receiving an input having a first length of input data bits;
partitioning the input data bits into groups of input data bits, each group comprising at least one bit;
selecting subkeys from key material stored in electronic flip-flops for the groups of input data bits, such that one subkey is selected for each group of input data bits; and
applying at least one XOR operation between the subkeys and the groups to generate an output having a second length of output data bits, wherein the first length is independent of the second length, wherein a data expansion function is performed if the first length is less than or equal to the second length, wherein a data compression function is performed if the first length is greater than or equal to the second length, and wherein the at least one XOR operation is implemented by a tree of XOR gates symmetrically arranged in layers such that the XOR gates in each layer are at the same distance from the input with respect to the number of XOR gates leading to them, wherein switching transients of the XOR gates are in the range of a few picoseconds, whereby transients of individual switching events are masked.

US Pat. No. 10,797,721

DIGITAL TO ANALOG CONVERTER, METHOD FOR DRIVING THE SAME, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A digital to analog converter, comprising: a first resistor string, 2m first multiplexers, a first voltage selector, a second resistor string, a second voltage selector, and a second multiplexer, wherein:the first resistor string comprises: 2m pairs of first resistors and first switches connected in series between a high-voltage reference signal terminal and a low-voltage reference signal terminal, wherein the first resistors have same resistance, and the first switches are initially turned on; and the 2m first resistors constitute (2m+1) first voltage dividing ends, the (2m+1) first voltage dividing ends one-to-one corresponding to (2m+1) input-output ends of the first voltage selector, wherein 2m first voltage dividing ends are one-to-one coupled with 2m input-output ends through the 2m first multiplexers, and the remaining one first voltage dividing end is coupled directly with the remaining one input-output end;
the 2m first multiplexers are configured to connect the 2m input-output ends with control ends of their corresponding 2m first switches upon reception of a first control signal, and to connect the 2m input-output ends with their corresponding 2m first voltage dividing ends upon reception of a second control signal;
the second resistor string comprises 2n second resistors connected in series between a high-voltage terminal of the first voltage selector and the second multiplexer, wherein a sum of the resistances of the 2n second resistors is equal to the resistance of a first resistor, and the 2n second resistors constitute 2n second voltage dividing ends;
the second multiplexer is configured to connect a low-voltage terminal of the first voltage selector with ground upon reception of the first control signal, and to connect the low-voltage terminal of the first voltage selector with the second resistor string upon reception of the second control signal;
the first voltage selector is configured to select one of the first switches to be turned off, according to a received m-bit digital signal when the low-voltage terminal is grounded, and to select the second resistor string, instead of the first resistor paired with the turned-off first switch, to be connected in series to the first resistor string, according to the received m-bit digital signal when the low-voltage terminal is connected with the second resistor string; and
the second voltage selector is configured to select a voltage signal at one of the second voltage dividing ends for output, according to a received n-bit digital signal.

US Pat. No. 10,797,720

APPARATUS AND METHOD FOR MEASURING CURRENT SOURCE MISMATCHES IN CURRENT-STEERING DAC BY RE-USING R2R NETWORK

QUALCOMM Incorporated, S...

1. An apparatus for measuring current mismatch, comprising:a current digital-to-analog converter (DAC) configured to convert an input digital signal into an output analog current, comprising:
a first current-generating section configured to generate a first current based on a first set of control signals;
a second current-generating section configured to generate a second current based on a second set of control signals, wherein the first and second currents are summed to generate the output analog current;
a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the second current-generating section using the first current; and
a comparator coupled to the current combining circuit and to the first current-generating section.

US Pat. No. 10,797,719

MAPPING CIRCUIT AND METHOD FOR SELECTING CELLS OF A MULTI CORE HYBRID I/Q DIGITAL TO ANALOG CONVERTER

Intel IP Corporation, Sa...

1. A method for selecting cells of a multi core hybrid I/Q digital to analog converter, comprising:defining a first group of cores and a second group of cores for each data symbol to be transmitted;
selecting a first number of cells of the first group of cores for an I-code of the data symbol; and
selecting a second number of cells of the second group of cores for a Q-code of the data symbol,
wherein the cells for the I-code of the data symbol are selected only from the first group of cores and the cells for the Q-code of the data symbol are selected only from the second group of cores.

US Pat. No. 10,797,718

TINY LOW POWER CURRENT MODE ANALOG TO DIGITAL CONVERTERS FOR ARTIFICIAL INTELLIGENCE

1. A system for current signal conditioning in an integrated circuit, the system comprising:a plurality of current-mode signal-conditioners (iSC)s each having an analog current input port (AI), an analog current output port (AO), and a digital output port (DO);
a plurality of scaled reference current sources (IR);
the first IR source coupled to the AI port of the first iSC;
the second and each subsequent IR source each having a digital input port (DR) for controlling the polarity of the IR source;
the AO port of the first iSC and the AO port of each subsequent iSC coupled to the AI port of each corresponding subsequent successive iSC;
the AO port of each iSC coupled to its corresponding IR source; and
the DO port of each iSC coupled to the DR port of each corresponding IR source.

US Pat. No. 10,797,717

SIGNAL PROCESSING DEVICE AND TRANSCEIVER

ICOM INCORPORATED, Osaka...

1. A signal processing device, comprising:an A-D converter that converts an analog signal, that is input into the signal processing device, to a digital signal in which portions where an amplitude exceeds a predetermined range are clipped, and outputs the digital signal; and
a controller that includes:
a counter that calculates, for the digital signal output by the A-D converter, a number of clipped samples for each predetermined number of period samples;
a frequency converter that performs frequency conversion of the digital signal output by the A-D converter;
a filter that removes unnecessary signal components of the digital signal that is subjected to the frequency conversion by the frequency converter;
a rate converter that converts a sampling rate of the A-D converter to a sampling rate that is an integer multiple of a value obtained by dividing by the number of period samples;
a digital amplifier that amplifies the digital signal for which the rate converter has converted the sampling rate, and outputs the digital signal that is amplified; and
an amplification factor adjuster that multiplies a preset amplification factor of the digital amplifier by an amplification factor adjustment coefficient, based on a ratio of the number of clipped samples to the number of period samples, to adjust the amplification factor of the digital amplifier.

US Pat. No. 10,797,716

IMAGING SYSTEMS HAVING SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS WITH REDUCED NON-LINEARITY

SEMICONDUCTOR COMPONENTS ...

1. An image sensor, comprising:a plurality of image sensor pixels;
an output line coupled to the plurality of image sensor pixels; and
a data converter configured to receive signals from the output line, wherein the data converter comprises:
a coarse digital-to-analog converter (DAC) section having a first array of capacitors; and
a fine digital-to-analog converter (DAC) section having a second array of capacitors, wherein the fine DAC section is configured to receive a pedestal value during a reset sampling phase and to receive a dynamically adjustable value that is different than the pedestal value during a signal sampling phase to reduce differential non-linearity at the data converter.

US Pat. No. 10,797,715

FILTERING METHOD AND FILTER

INFINEON TECHNOLOGIES AG,...

1. A method, comprising:integrating values of an input signal by an integrator comprising a memory;
storing an integration value in the memory;
cyclically resetting the memory after integrating a first predefined number of values of the input signal;
in a steady operating mode, generating a value of an output signal based on the integration value stored in the memory each time after integrating the first predefined number of values of the input signal; and
in an initial operating mode, generating an initial value of the output signal based on the integration value stored in the memory after integrating a second predefined number of values of the input signal, wherein the second predefined number is smaller than the first predefined number.

US Pat. No. 10,797,714

PIPELINED SAR WITH TDC CONVERTER

Taiwan Semiconductor Manu...

1. A circuit, comprising:a voltage-to-time conversion element configured to receive an input voltage at an input and to generate a time domain representation of the input voltage, the voltage-to-time conversion element comprising:
an amplifier comprising an amplifier input coupled to the input;
a zero crossing detector coupled to an output of the amplifier; and
a current source selectively coupled to the amplifier input by way of a switching element.

US Pat. No. 10,797,713

HIGH-SPEED HIGH-RESOLUTION DIGITALLY-CONTROLLED OSCILLATOR AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A DCO (digitally-controlled oscillator) comprising:a ring oscillator having a plurality of gain stages cascaded in a ring topology with a negative feedback to output an oscillation signal at an inter-stage node in accordance with a supply voltage at a supply node;
a low-speed DAC (digital-to-analog converter) configured to output a supply current to the supply node to establish the supply voltage in accordance with a coarse control word;
a varactor array configured to provide a capacitive load to said inter-stage node in accordance with a control voltage array; and
a high-speed DAC array configured to output said control voltage array in accordance with a fine control word,
wherein the low-speed DAC further comprises:
a current to voltage conversion circuit configured to convert a summed current into a bias voltage; and
a low pass filter configured to filter the bias voltage into a filtered bias voltage.

US Pat. No. 10,797,712

MAINTAINING A DIGITALLY CONTROLLED OSCILLATOR AT AN IDEAL STATE BY CHANGING THE VOLTAGE SUPPLY

INTERNATIONAL BUSINESS MA...

1. An apparatus comprising:a digital phase locked loop (DPLL) comprising a digitally controlled oscillator (DCO), the DCO comprising delay elements and a current fill factor corresponding to a proportion of the delay elements in operation; and
a voltage regulator controller operable to obtain a result of a comparison between a predefined fill factor having been set in advance to a fixed value and the current fill factor, the voltage regulator controller being operable to adjust voltage supplied to the DCO based on the result, the predefined fill factor indicating a predetermined proportion of the delay elements to be in operation.

US Pat. No. 10,797,711

OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

SEIKO EPSON CORPORATION, ...

1. An oscillator comprising:a quartz crystal resonator that performs a thickness-shear vibration, the quartz crystal resonator including:
a piezoelectric substrate including a vibration portion formed in a thin flat plate and a support portion formed to be thicker than the vibration portion;
a first excitation electrode provided at a position corresponding to the vibration portion in a first main surface of the piezoelectric substrate; and
a second excitation electrode provided at a position corresponding to the vibration portion in a second main surface of the piezoelectric substrate; and
a circuit device electrically coupled to the quartz crystal resonator, wherein
the circuit device includes an oscillation circuit that generates a reference clock signal by oscillating the quartz crystal resonator, and a PLL circuit that receives the reference clock signal,
the PLL circuit includes a phase comparison circuit that performs a phase comparison between the reference clock signal and a feedback clock signal, a control voltage generation circuit that generates a control voltage based on a result of the phase comparison, a voltage control oscillation circuit that generates a clock signal having a frequency corresponding to the control voltage, and a frequency division circuit that divides a frequency of the clock signal and outputs the feedback clock signal, and
an oscillation frequency of the quartz crystal resonator is higher than or equal to 200 MHz, and a phase comparison frequency of the phase comparison circuit is higher than or equal to 200 MHz.

US Pat. No. 10,797,710

CLOCK GENERATOR AND METHOD FOR GENERATING CLOCK SIGNAL

NXP USA, Inc., Austin, T...

1. A clock generator that generates a clock signal, comprising:an oscillator that generates the clock signal;
a feedback circuit connected to the oscillator to receive the clock signal, wherein the feedback circuit generates a feedback signal indicative of a frequency of the clock signal;
a voltage detector connected to the feedback circuit to receive the feedback signal, wherein the voltage detector compares a source voltage with a charged voltage generated using the feedback signal, and generates a detection signal indicative of the comparison between the source voltage and the charged voltage;
a control voltage generator connected to the voltage detector to receive the detection signal, wherein the control voltage generator generates a control voltage using the detection signal; and
a bias current source connected to the control voltage generator to receive the control voltage, wherein the bias current source generates a bias current using the control voltage, and wherein the frequency of the clock signal generated by the oscillator is dependent on the bias current,
wherein the voltage detector comprises a charge capacitor that provides the charged voltage, and wherein the charge capacitor is charged in response to the feedback signal.

US Pat. No. 10,797,709

METHOD AND CIRCUITS FOR FINE-CONTROLLED PHASE/FREQUENCY OFFSETS IN PHASE-LOCKED LOOPS

Analog Bits Inc., Sunnyv...

1. A method for operating a phase locked loop (PLL) device, the method comprising:receiving, at a phase and frequency detector (PFD) and charge pump (CP) portion, a reference clock signal and a feedback clock signal set;
generating, at the PFD and the CP portion, an intermediary signal based on a difference between the reference clock signal and a feedback clock signal set;
using the intermediary signal from the PFD and the CP portion to drive a voltage controlled oscillator (VCO) such that a VCO clock signal is generated;
frequency dividing the VCO clock signal by a first static factor to generate a first statically divided VCO clock signal;
splitting the first statically divided VCO clock signal by:
frequency dividing the first statically divided VCO clock signal further by a second static factor to generate a second statically divided VCO clock signal as an output signal of the PLL device, while
(ii) frequency dividing the first statically divided VCO clock signal further by a dynamic division ratio to generate a third dynamically divided VCO clock signal; and
based on the third dynamically divided VCO clock signal, generating the feedback clock signal set for the PFD and CP portion at a first clock granularity determined by the VCO clock signal and not less than a second clock granularity of the VCO clock signal.

US Pat. No. 10,797,708

APPARATUSES AND METHODS FOR INDIRECTLY DETECTING PHASE VARIATIONS

Micron Technology, Inc., ...

1. An apparatus, comprising:a phase deviation detection circuit configured to detect a variation in a phase of a clock signal after an initial phase lock operation based on variations in gate delays of an oscillation circuit, and to initiate a phase-lock operation in response to detecting variations in the gate delays of the oscillation circuit, wherein the phase deviation detection circuit is configured to count oscillations of an oscillation clock signal provided from the oscillation circuit over a time period to detect variation in the gate delays.

US Pat. No. 10,797,707

DELAY LOCKED LOOP DETECTION METHOD AND SYSTEM

CSMC TECHNOLOGIES FAB2 CO...

1. A system of detecting a work state of a delay locked loop, comprising:a signal generator configured to generate a reference clock;
a pre-receiving circuit configured to receive the reference clock, amplify and shape the reference clock, and provide an amplified and shaped signal to the delay locked loop; and
a testing instrument configured to acquire a clock signal output from the delay locked loop and determine whether a time delay of the clock signal is consistent with expectation,
wherein the pre-receiving circuit comprises at least one of:
a differential comparator configured to amplify the received reference clock and output a double-ended signal;
a double-end-to-single-end module coupled to an output end of a differential comparator configured to receive a double-ended signal output from the differential comparator and convert the double-ended signal into a single ended signal; or
a buffer amplifying module coupled to an output end of a double-end-to-single-end module configured to receive a single ended signal, shape the single ended signal and enhance a driving capability of the shaped single ended signal.

US Pat. No. 10,797,706

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a lookup table comprising a memory;
a first circuit; and
a second circuit,
wherein the first circuit receives a first signal and a second signal,
wherein the second circuit sends a third signal,
wherein when the first circuit receives the third signal, the first circuit sends a fourth signal and a fifth signal,
wherein when the lookup table receives the fourth signal and the fifth signal, the lookup table sends a sixth signal and a seventh signal,
wherein when the second circuit receives the sixth signal and the seventh signal, the second circuit sends an eighth signal,
wherein when the first circuit receives the eighth signal, the first circuit sends a ninth signal, and
wherein the sixth signal and the seventh signal are generated from data stored in the memory.

US Pat. No. 10,797,705

CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

SEIKO EPSON CORPORATION, ...

1. A circuit device comprising:a first output signal line from which a first output signal constituting differential output signals is output;
a second output signal line from which a second output signal constituting the differential output signals is output; and
first to n-th output drivers for differential input and differential output that are coupled to the first output signal line and the second output signal line, n being an integer of 2 or more, wherein
in a first mode, i number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on a first input signal and a second input signal constituting differential input signals, i being an integer of 1?i?n,
in a second mode, j number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on the first input signal and the second input signal, j being an integer of 1?j?n and j?i, and
the first to n-th output drivers include
output drivers of a first group including drive current sources that apply drive currents each having a current value Is, and
output drivers of a second group including drive current sources that apply drive currents each having a current value a×Is, a being an integer of 2 or more.

US Pat. No. 10,797,704

DIFFERENTIAL SIGNAL TRANSFER SYSTEMS AND ASSOCIATED METHODS

Maxim Integrated Products...

1. A differential signal transfer system, comprising:a dynamic level-shifter, configured to:
receive an input signal including a differential-mode component and a first common-mode component, and
generate a level-shifted signal from the input signal, the level-shifted signal including the differential-mode component and a second common-mode component that is different from the first common-mode component,
the dynamic level-shifter including:
an input port configured to receive the input signal,
an output port configured to output the level-shifted signal,
first and second resistive devices each electrically coupled between the input port and the output port,
a first common-mode control circuit configured to sink current through each of the first and second resistive devices,
a second common-mode control circuit configured to source current through each of the first and second resistive devices, and
third and fourth resistive devices electrically coupled in series across the output port, the third and fourth resistive devices being electrically coupled together at a common-mode node CM, and each of the first common-mode control circuit and the second common-mode control circuit being electrically coupled to the common-mode node CM; and
a common-mode rejection device configured to receive the level-shifted signal and generate an output signal therefrom, the output signal including the differential-mode component.

US Pat. No. 10,797,703

DRIVING APPARATUS

RichWave Technology Corp....

1. A driving apparatus, comprising:a first voltage dividing circuit, dividing a first input signal to generate a first voltage dividing control signal;
a second voltage dividing circuit, dividing a second input signal to generate a second voltage dividing control signal, wherein the first input signal and the second input signal are inverted with respect to each other;
a first stage inverter circuit, coupled to the first voltage dividing circuit and generating a first output signal according to the first voltage dividing control signal; and
a second stage inverter circuit, coupled to the second voltage dividing circuit and the first stage inverter circuit, and the second stage inverter circuit generating a second output signal and a first driving signal according to the second voltage dividing control signal, wherein the first output signal is configured to bias the second stage inverter circuit, and the second output signal is configured to bias the first stage inverter circuit.

US Pat. No. 10,797,702

APPARATUS FOR FLEXIBLE ELECTRONIC INTERFACES AND ASSOCIATED METHODS

Altera Corporation, San ...

1. An integrated circuit die, comprising:a flexible interface circuit in the integrated circuit die;
logic circuitry in the integrated circuit die; and
a programmable interconnect in the integrated circuit die, the programmable interconnect coupling the flexible interface circuit to the logic circuitry.

US Pat. No. 10,797,701

COMPENSATING FOR DEGRADATION OF ELECTRONICS DUE TO RADIATION VULNERABLE COMPONENTS

Honeywell International I...

1. A method comprising:receiving, by a processing circuit, a signal indicating an amount of radiation received at a radiation sensor;
determining, by the processing circuit, an amount of radiation received over a time period at the radiation sensor;
monitoring, by the processing circuit, the output of a circuit component;
determining, by the processing circuit, a compensation factor for the circuit component based on the amount of radiation received over the time period at the radiation sensor, wherein the compensation factor is based on both a predicted change in performance for the circuit component based on the amount of radiation and the monitored output; and
correcting, by the processing circuit, an output signal of the circuit component for a performance change of the circuit component over the time period, based on the compensation factor.

US Pat. No. 10,797,700

APPARATUS FOR TRANSMITTING AND RECEIVING A SIGNAL, A METHOD OF OPERATING THE SAME, A MEMORY DEVICE, AND A METHOD OF OPERATING THE MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A signal transmitting and receiving apparatus, comprising:a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin;
a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and
an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit,
wherein the signal transmitting and receiving apparatus receives the first signal from outside the signal transmitting and receiving apparatus through the first pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled, and
the first signal is a data signal and the second signal is a read data strobe signal.

US Pat. No. 10,797,699

SYSTEM AND METHOD FOR CALIBRATING AN ELECTRO-PERMANENT MAGNET KEY SWITCH ASSEMBLY

Dell Products, LP, Round...

1. A plurality of electro-permanent magnet (EPM) key assemblies of an information handling system comprising:the plurality of EPM key assemblies including a plurality of electro-permanent magnets (EPMs) comprising:
a low-coercivity magnet;
a high-coercivity magnet; and
a magnetic field sensor to detect the magnitude of the one or more magnetic field of the EPMs; and
a calibration module to calibrate the magnitude of the one or more magnetic field of the EPMs by:
receiving a sensed magnitude value of the magnetic field associated with the plurality of the EPMs; and
adjusting the magnitude value of the magnetic field associated with each of the EPMs to a value commensurate with each other based on the established value when that magnitude value deviates from an established value by a threshold amount.

US Pat. No. 10,797,698

SYSTEMS AND METHODS FOR SELECTING LIGHT EMITTERS FOR EMITTING LIGHT

Waymo LLC, Mountain View...

1. A circuit comprising:a plurality of light emitters connected between a first node and a second node;
a plurality of capacitors, wherein each capacitor in the plurality of capacitors corresponds to a respective light emitter in the plurality of light emitters;
a plurality of discharge-control switches, wherein each discharge-control switch corresponds to a respective capacitor in the plurality of capacitors; and
a pulse-control switch connected to the plurality of light emitters,
wherein, during a first period, the pulse-control switch restricts current flow and each capacitor in the plurality of capacitors is charged via the first node,
wherein, during a second period, one or more of the plurality of discharge-control switches allows current flow that discharges one or more corresponding capacitors of the plurality of capacitors, and
wherein, during a third period, the pulse-control switch allows current flow that discharges one or more undischarged capacitors of the plurality of capacitors through one or more corresponding light emitters of the plurality of light emitters, thereby causing the one or more corresponding light emitters to emit respective pulses of light.

US Pat. No. 10,797,697

PHASE RELATIONSHIP SENSING SYSTEM

Tactual Labs Co., New Yo...

1. A phase relationship system, comprising:a first plurality of antennas operably connected to a signal generator, wherein the signal generator is adapted to generate a plurality of signals, wherein at least one of the plurality of signals is generated having a first phase;
a second plurality of antennas operably connected to a receiver, wherein the second plurality of antennas is adapted to receive at least one of the plurality of signals;
an infusion electrode operably connected to the signal generator, wherein the infusion electrode is adapted to transmit a signal having a second phase that is in a predetermined phase relationship with respect to the at least one of the plurality of signals having a first phase, wherein the first phase and the second phase are different, wherein the infusion electrode is adapted to be operably connected to a body part and the infusion signal is transmitted into the body part thereby impacting determination of hover for the body part due, at least in part, to the phase relationship between the infusion signal and the at least one of the plurality of signals generated having the first phase; and
a signal processor adapted to process and determine measurements of received signals.

US Pat. No. 10,797,696

FACTOR 1 INDUCTIVE SENSOR DEVICE

SENSTRONIC (SOCIETE PAR A...

1. Proximity or presence sensor device, of the inductive type and functioning in “factor 1” mode with a variation in its detection distance Sn for the various metals, said sensor device comprising both an LC resonant circuit fed or charged by an excitation pulse generator defining successive and repetitive detection phases, as well as an operational chain of means for the acquisition and processing of the response signal in the form of free oscillations, supplied by said LC detection circuit during each detection phase, comprising in particular a sampling means and an analogue/digital conversion circuit, and lastly a functional assembly of evaluation means for evaluating at least one time-locked value of the processed signal and for providing information or a logical detection or non-detection signal, said device also comprising a management and control unit microcontroller as said evaluation means for controlling the functioning of said device, wherein the acquisition and processing means comprise both analogue means for the filtration and/or amplification of the sampled response signal, after its acquisition and before its digital conversion, as well as means for compensating for the deviation in temperature of the response signal by correcting the sampled signal after its digital conversion, associated with or comprising a temperature sensor which provides information about the temperature of at least one part of the sensor device, comprising the LC resonant circuit and means for the acquisition and processing of the operational chain located upstream of the A/D conversion circuit.

US Pat. No. 10,797,695

CURRENT SUBTRACTION CIRCUITRY

SEMICONDUCTOR COMPONENTS ...

1. Circuitry, comprising:a first current branch configured to convey a first current amount;
a second current branch configured to convey a second current amount, wherein the second current branch splits into first and second sub-branches; and
an amplifier circuit configured to force the first current amount through the first sub-branch such that the amount of current flowing through the first sub-branch is equal to the first current amount and such that the second sub-branch conveys an amount of current that is equal to the difference between the first and second current amounts, wherein the second sub-branch comprises a first transistor of a first channel type, wherein the first current branch comprises a second transistor of the first channel type, wherein the first sub-branch comprises a third transistor of the first channel type, wherein the third and first transistors are connected in parallel, and wherein the sum of the current flowing through the third and first transistors is equal to the second current amount.

US Pat. No. 10,797,694

SWITCH CIRCUIT AND METHOD OF SWITCHING RADIO FREQUENCY SIGNALS

pSemi Corporation, San D...

1. A method of switching an RF signal comprising:generating a voltage substantially negative with respect to ground using a negative voltage generator circuit comprising a charge pump;
generating one or more control signals using an integrated digital logic circuit;
controlling, using the generated one or more control signals, a switch transistor grouping to a switch ON state or a switch OFF state and a shunt transistor grouping to a shunt ON state or a shunt OFF state, wherein the controlling the shunt transistor grouping to the shunt OFF state and the controlling the switch transistor grouping to the switch OFF state is controlled, at least in part, with the substantially negative voltage;
passing the RF signal between a first RF node and a second RF node using the switch transistor grouping comprising stacked switch N-type metal oxide semiconductor field effect transistors (NMOSFETs) in the switch ON state, the stacked switch NMOSFET transistors coupling the RF nodes; and
not shunting the first RF node to ground using the shunt transistor grouping comprising stacked shunt NMOSFET transistors in the shunt OFF state, the stacked shunt NMOSFET transistors coupling the first RF node and ground;
wherein the generatings, the controlling, the passing and the not shunting take place in a single integrated circuit chip.

US Pat. No. 10,797,693

DRIVE CIRCUIT, POWER MODULE AND ELECTRIC POWER CONVERSION SYSTEM

Mitsubishi Electric Corpo...

1. A drive circuit comprising:a control circuit providing control voltage to a control terminal of a switching device in accordance with input signal; and
a capacitor having one end connected to a high side main terminal of the switching device,
wherein the control circuit increases an output current capacity of the control circuit when the input signal becomes ON signal and voltage at the other end of the capacitor drops,
wherein the control circuit includes a detection circuit, in which each of the input signal and the voltage at the other end of the capacitor is inputted, and the detection circuit outputs an output signal in accordance with the received input signal and the voltage at the other end of the capacitor,
wherein the control circuit further includes a switching unit that switches the output current capacity of the control circuit in accordance with the output signal of the detection circuit, and
wherein the detection circuit is a flip-flop circuit.

US Pat. No. 10,797,692

INTEGRATED CIRCUIT DEVICE

FUJI ELECTRIC CO., LTD., ...

1. An integrated circuit device, comprising:a circuit device main body configured to execute a predetermined processing function;
a communication control circuit configured to perform data communication with an external control device; and
an operation mode determination circuit configured to selectively determine, as an operation mode of the circuit device main body, a normal mode for executing the predetermined processing function or a debug mode for setting an execution condition of the predetermined processing function, and to generate an operation mode output value for determining the operation mode of the circuit device main body according to a logical state of a particular one communication signal data-communicated with the external control device after a reset operation performed by a reset circuit is released, the reset circuit being configured to output a reset signal at a time of turning-on of a power supply so as to initialize the operation mode determination circuit and perform the reset operation,
wherein the circuit device main body is configured to set the execution condition of the predetermined processing function in the normal mode of the circuit device main body according to information obtained from the data communication with the external control device when the debug mode is set.

US Pat. No. 10,797,691

METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK

pSemi Corporation, San D...

1. A method of fabricating an RF switch comprising:fabricating an integrated circuit (IC) that includes the RF switch;
wherein the fabricating includes forming at least a plurality of N-type metal oxide semiconductor field effect transistors (NMOSFETs) by forming a source, a drain, a gate and a body for respective NMOSFETs of the plurality in a silicon layer of a substrate;
wherein the fabricating further includes fabricating one or more layers of metallization over the silicon layer;
wherein the one or more layers of metallization to couple the plurality of NMOSFETs into a stack to pass an RF signal through the stack of NMOSFETs in an ON state of the stack of NMOSFETs in accordance with RF switch operation;
wherein the one or more layers of metallization to couple the plurality of NMOSFETs of the stack to not pass an RF signal through the stack of NMOSFETs in an OFF state of the stack of NMOSFETs in accordance with RF switch operation; and
wherein the one or more layers of metallization to couple an electrical bias to the body of the respective NMOSFETs, in accordance with RF switch operation, at least in a portion of the OFF state of the stack to have a DC voltage level substantially more negative than a lowest voltage level of the following: ground, a DC voltage level of the source of the respective NMOSFETs, and a DC voltage level of the drain of the respective NMOSFETs.

US Pat. No. 10,797,690

METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK

pSemi Corporation, San D...

1. A method of operating a module, the module including at least one integrated circuit chip comprising a plurality of series N-type metal oxide semiconductor (NMOS) field effect transistors configured in a series connected stack configuration that comprises at least one series NMOS field effect transistor including a body, the at least one series NMOS field effect transistor either to pass an RF signal in a series enable state or to not pass the RF signal in a series disable state, the method further comprising:electrically biasing the body of the at least one series NMOS field effect transistor of the module in the series disable state to have a voltage level substantially more negative than the lowest voltage level of the following: ground, a DC voltage level of a source of the at least one series NMOS field effect transistor of the module, and a DC voltage level of a drain of the at least one series NMOS field effect transistor of the module.

US Pat. No. 10,797,689

OVER-VOLTAGE CLAMP CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. A device comprising:a power transistor having a first terminal coupled to a voltage input, a second terminal coupled to a voltage output, and a control terminal;
a feedback converter coupled to the voltage output, and configured to deliver a feedback signal responsive to an output current sensed at the voltage output; and
a control circuit including:
a first transistor having a first terminal coupled to the control terminal of the power transistor, a control terminal configured to receive the feedback signal, and a second terminal; and
a second transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to a voltage supply terminal, and a control terminal coupled to receive a clamp threshold signal based on a difference between the feedback signal and a reference signal.

US Pat. No. 10,797,688

COMPARATOR CIRCUIT, CORRESPONDING DEVICE AND METHOD

STMicroelectronics S.r.l....

1. A circuit, comprising:a first current path including a first current generator and a first transistor, the first current generator coupled between a supply line and a first node and the first transistor having a current path coupled between the first node and a reference node configured to receive a reference signal;
a second current path including a second current generator and a second transistor, the second current generator coupled between the supply line and a second node and the second transistor having a current path coupled between the second node and an input node configured to receive an input signal;
wherein control terminals of the first transistor and the second transistor are coupled at third node;
a third current generator configured to sink a current from the third node to a ground node;
a third current path between the supply line and the third node, the third current path including a third transistor having a control terminal coupled with the first node;
a fourth current path between the supply line and the third node, the fourth current path including a fourth transistor having a control terminal coupled with the second node; and
an output node coupled to the fourth current path and configured to generate an output signal switchable between a first and a second state as a result of a level of the input signal at the input node crossing a level of the reference signal at the reference node.

US Pat. No. 10,797,687

SIGNAL DUTY CYCLE ADAPTIVE-ADJUSTMENT CIRCUIT AND METHOD FOR RECEIVING TERMINAL

INTERNATIONAL GREEN CHIP ...

7. A signal duty cycle adaptive-adjustment method for a receiving terminal, characterized by including:Step 602, turning off a first path switch (SW-M), and turning off a second path switch (SW-N);
Step 603, detecting, by a received signal activity indicating circuit, whether or not a valid input signal is input; if not, returning to Step 602;
Step 604, turning on the first path switch (SW-M), turning off the second path switch (SW-N), and initializing a number of times Nstep to 1;
Step 605, extracting and estimating a duty cycle parameter to obtain a duty cycle deviation, and obtaining an error signal through error computation;
Step 606, inputting the error signal to a filter feedback circuit, adjusting an output voltage of a digital-to-analog conversion circuit to generate a reference voltage, outputting, by an analog level comparison circuit, a subsequent waveform under a new reference voltage, and increasing the number of times Nstep by 1;
Step 607, judging whether or not the number of times Nstep is equal to 8 or a waveform duty cycle is close to an expected value, namely judging whether or not an output duty cycle error signal is smaller than a preset threshold; if the condition is not met, returning to Step 605;
Step 608, turning off the first path switch (SW-M), and turning on the second path switch (SW-N); and
Step 609, inputting an adjusted signal to a decoding circuit, and starting to receive and process subsequent valid data; and after a process is completed, returning to Step 603.

US Pat. No. 10,797,686

PHASE PREDICTOR AND ASSOCIATED METHOD OF USE

Microchip Technology Inc....

13. A phase predictor comprising:an event clock cycle predictor for receiving a system clock running in a system clock domain and an event clock running in an event clock domain, the event clock cycle predictor for determining an event clock cycle prediction of the event clock relative to the system clock cycle;
a phase difference predictor for emulating a predicted event clock in the system clock domain based upon the event clock cycle prediction, for predicting a phase difference between the event clock and the system clock based and for aligning the predicted event clock with the system clock based upon the predicted phase difference, wherein the predicted phase difference is predicted at an edge of the system clock and is equal to a time between the edge of the system clock and a previous edge of the predicted event clock.

US Pat. No. 10,797,685

JITTER CANCELLATION WITH AUTOMATIC PERFORMANCE ADJUSTMENT

Micron Technology, Inc., ...

1. An apparatus, comprising:a feedback loop configured to receive a first signal and output a second signal;
a first circuit configured to introduce, into the feedback loop, a first delay that is based at least in part on a supply voltage; and
a second circuit configured to introduce, into the feedback loop, a second delay that is proportional to the supply voltage.

US Pat. No. 10,797,684

SUPERCONDUCTING WAVEFORM SYNTHESIZER

GOVERNMENT OF THE UNITED ...

1. A superconducting waveform synthesizer to produce an arbitrary waveform, the superconducting waveform synthesizer comprising:a primary Josephson junction that:
receives a primary current bias pulse that consists essentially of a positive-polarity current pulse; and
produces a primary quantized output pulse from the primary current bias pulse; a secondary Josephson junction that:
receives a secondary current bias pulse that consists essentially of a negative-polarity current pulse; and
produces a secondary quantized output pulse from the secondary current bias pulse;
a combiner that:
receives the primary quantized output pulse from the primary Josephson junction;
receives the secondary quantized output pulse from the secondary Josephson junction; and
produces a quantized pulse pattern from a combination of the primary quantized output pulse and the secondary quantized output pulse;
a converter that:
receives the quantized pulse pattern from the combiner; and
produces the arbitrary waveform from the converter.

US Pat. No. 10,797,683

CALIBRATION CIRCUIT AND ASSOCIATED CALIBRATING METHOD CAPABLE OF PRECISELY ADJUSTING CLOCKS WITH DISTORTED DUTY CYCLES AND PHASES

Faraday Technology Corp.,...

1. A calibration circuit, comprising:a duty cycle correction circuit, configured for generating a first duty cycle adjusted clock based on a first input clock, and generating a second duty cycle adjusted clock based on a second input clock, wherein frequency of the first input clock and frequency of the second input clock are equivalent;
a phase correction circuit, electrically connected to the duty cycle correction circuit, configured for generating a first delay adjusted clock based on a phase of the first duty cycle adjusted clock, and generating a second delay adjusted clock based on a phase of the second duty cycle adjusted clock;
a clock selection circuit, electrically connected to the phase correction circuit, comprising:
a first clock selector, configured for outputting a first selected signal based on a first feedback clock, wherein the first feedback clock is generated from the first delay adjusted clock;
a comparison circuit, electrically connected to the first clock selector, configured for generating a comparison signal based on a second feedback clock and the first selected signal, wherein the second feedback clock is generated from the second delay adjusted clock; and
a second clock selector, electrically connected to the comparison circuit, configured for outputting a second selected signal based on the second feedback clock, the comparison signal, and the first selected signal, wherein the second selected signal is related to generation of a detection signal, wherein the detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock; and
a first control circuit, electrically connected to the duty cycle correction circuit, the phase correction circuit, and the clock selection circuit, configured for controlling the duty cycle correction circuit and the phase correction circuit in response to the detection signal.

US Pat. No. 10,797,682

COMMON SIGNAL ATTENUATION CIRCUIT AND RAMP SIGNAL GENERATOR USING THE SAME

SK hynix Inc., Gyeonggi-...

1. A common signal attenuation circuit comprising:a sensing block suitable for sensing differential signals;
a common signal generation block suitable for summing the differential signals, which are sensed by the sensing block, and generating a common signal having a common voltage noise, wherein the differential signals include first and second differential signals having opposite phases to each other, and differential components of the first and second differential signals are removed and the common voltage noise of the first and second differential signals is doubled in the opposite phases; and
an attenuation block suitable for adjusting the common voltage noise included in the common signal by combining the common signal having the adjusted common voltage noise to the differential signals,
wherein the differential signals are of current-type, and
wherein the common signal generation block comprises:
a third PMOS transistor suitable for transmitting the first current-type differential signal sensed by the sensing block;
a fourth PMOS transistor suitable for transmitting the second current-type differential signal sensed by the sensing block; and
a first NMOS transistor suitable for generating the common signal having a common voltage noise by combining the first current-type differential signal and the second current-type differential signal with each other.

US Pat. No. 10,797,681

METHOD OF FABRICATING NOVEL PACKAGES FOR ELECTRONIC COMPONENTS

Zhuhai Crystal Resonance ...

1. A method of fabricating packaged components, said method comprising the stages of:a) Obtaining an active membrane layer on a carrier substrate;
b) Depositing a front electrode onto a front of the active membrane layer;
c) Obtaining an inner front section comprising at least a silicon handle or wafer;
d) Attaching an inner front end section to an outer surface of the front electrode;
e) Detaching the carrier substrate from a back surface of an active membrane on the opposite surface from the front surface on which the front electrode is deposited;
f) Optionally trimming the active membrane to a specified thickness;
g) Patterning the active membrane layer into an array of at least one island of membrane;
h) Selectively removing the front electrode and bonding layer;
i) Selectively applying an inner passivation layer;
j) Selectively depositing a back electrode layer and optionally a frame layer and optionally a mass loading layer on the thus exposed back surface of the active membrane;
k) Selectively depositing an outer passivation layer patterned to selectively expose a first route and a second route for respectively routing signals from external contacts to the front and back electrodes;
l) Selectively depositing a first internal conductive route that is coupled to the back electrode layer and a second internal route that is coupled to the front electrode layer by a part of the back electrode layer isolated from the membrane by way of a filled through-via traversing the inner passivation layer;
m) Optionally thinning the silicon handle or wafer to a desired thickness;
n) Creating an array of at least one front cavity by selectively removing at least the silicon handle or wafer of the inner front end section, to fabricate a cavity opposite each island of membrane;
o) Obtaining an outer front end section and bonding the outer front end section to the inner front end section such that the outer front end section spans across and seals the at least one cavity of the array of front cavities;
p) Optionally thinning the outer front end section;
q) Optionally trimming the exposed outer passivation layer;
r) Applying an organic back end comprising a selectively deposited inner organic layer comprising an array of back cavities therethrough, comprising one back cavity and a pair of through via holes per trimmed island of active membrane, wherein the through via holes are opposite internal pads of a routing layer, and are open to the routing layer through the apertures in the outer passivation layer, and further comprising back trenches through the inner organic layer, opposite the region wherein the silicon handle or wafer of a front inner layer is exposed by the patterning of the silicon oxide and inner passivation layer;
s) Selectively applying an outer back organic layer onto an inner back organic layer comprising through via holes over the through via holes in the inner back organic layer and extensions to the back trenches, thereby creating deep trenches, but spanning and sealing the at least one upper cavity;
t) Optionally fabricating deep trenches on a front side of the package, wherein said deep trenches on the front side are aligned with the deep trenches on the back side of the package and traverse the front outer layer and any package bonding layer to the silicon handle or wafer of the front inner layer;
u) Optionally applying a sealing liner coating onto the outer surface of both the back and front ends and into the deep trenches and then removing the sealing liner coating from in and around the via holes;
v) Filling the array of via holes through the outer and inner organic layers with a metal that contacts a conductive inner pad layer to create filled vias and extending the filled vias to create external pads;
w) Applying a barrier layer and solder bumps to the external pads of the filled vias;
x) Reflowing the solder bumps;
y) Optionally thinning the outer back layer of a front end section; and
z) Dicing arrays into separate component dies.

US Pat. No. 10,797,680

ELASTIC WAVE DEVICE, HIGH-FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION APPARATUS

MURATA MANUFACTURING CO.,...

2. An elastic wave device comprising:a supporting substrate;
an acoustic reflection layer disposed on the supporting substrate;
a piezoelectric layer disposed on the acoustic reflection layer with no conductor layer disposed therebetween; and
an interdigital transducer electrode disposed on the piezoelectric layer; wherein
the acoustic reflection layer includes:
three or more low acoustic impedance layers; and
two or more high acoustic impedance layers; and
a film thickness of a low acoustic impedance layer of the three or more low acoustic impedance layers closest to the piezoelectric layer is larger than a film thickness of a low acoustic impedance layer of the three or more low acoustic impedance layers closest to the low acoustic impedance layer that is closest to the piezoelectric layer.

US Pat. No. 10,797,679

ELASTIC WAVE DEVICE

MURATA MANUFACTURING CO.,...

1. An elastic wave device, comprising:a piezoelectric substrate; and
an IDT electrode provided on one main surface of the piezoelectric substrate; wherein
the IDT electrode includes a first busbar and a second busbar that are opposed to each other, a plurality of first electrode fingers each of which includes one end connected to the first busbar, and a plurality of second electrode fingers each of which includes one end connected to the second busbar, the plurality of second electrode fingers being interdigitated with the plurality of first electrode fingers, the IDT electrode including an intersecting region where the first electrode fingers and the second electrode fingers overlap each other in an elastic wave propagation direction;
when a direction perpendicular or substantially perpendicular to the elastic wave propagation direction is defined as an intersecting direction in plan view, the intersecting region includes a center region positioned in a central portion in the intersecting direction and a first low acoustic velocity region and a second low acoustic velocity region that are individually disposed on respective sides of the center region in the intersecting direction and that have a lower acoustic velocity than the center region, the first low acoustic velocity region being positioned on a side of the first busbar, the second low acoustic velocity region being positioned on a side of the second busbar;
a first high acoustic velocity region that is positioned between the first busbar and the first low acoustic velocity region and that has a higher acoustic velocity than the center region, and a second high acoustic velocity region that is positioned between the second busbar and the second low acoustic velocity region and that has a higher acoustic velocity than the center region are provided;
a groove portion overlaps with one of the first electrode fingers and the second electrode fingers in plan view in a portion positioned in the first low acoustic velocity region and the second low acoustic velocity region on the one main surface of the piezoelectric substrate; and
an acoustic velocity adjusting layer made of a material different from a material of the piezoelectric substrate is provided in the groove portion.

US Pat. No. 10,797,678

ACOUSTIC WAVE DEVICE, RADIO-FREQUENCY FRONT END CIRCUIT, AND COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. An acoustic wave device comprising:a piezoelectric body;
an IDT electrode provided on the piezoelectric body; and
a first dielectric film provided on the piezoelectric body and covering the IDT electrode; wherein
the IDT electrode includes a first busbar and a second busbar that face each other, a plurality of first electrode fingers with first ends that are electrically connected to the first busbar, and a plurality of second electrode fingers with first ends that are electrically connected to the second busbar and that are interdigitated with the plurality of first electrode fingers,
when an acoustic wave propagation direction is a first direction and a direction perpendicular or substantially perpendicular to the acoustic wave propagation direction is a second direction, the IDT electrode includes a crossing region that is a portion of the IDT electrode where the first electrode fingers and the second electrode fingers overlap in the first direction;
the crossing region includes a center region located in a central portion of the first electrode fingers and the second electrode fingers in the second direction, a first edge region located outside the center region on the first busbar side in the second direction, and a second edge region located outside the center region on the second busbar side in the second direction,
a first gap region is located outside the first edge region on the first busbar side in the second direction and a second gap region is located outside the second edge region on the second busbar side in the second direction;
Love waves are utilized as acoustic waves;
a mass-adding film is provided inside the first dielectric film in the first edge region and the second edge region; and
when T1 is a film thickness of a portion of the first dielectric film located between the IDT electrode and the mass-adding film and T2 is a film thickness of a portion of the first dielectric film located between the mass-adding film and a surface of the first dielectric film on an opposite side from the piezoelectric body, T1/(T1+T2)

US Pat. No. 10,797,677

CRYSTAL VIBRATION ELEMENT AND CRYSTAL DEVICE

KYOCERA Corporation, Kyo...

1. A crystal vibration element comprisinga crystal blank of a thickness shear vibration-use cut plate shape in which a long direction is a vibration direction and
a pair of excitation electrodes on the two surfaces of the crystal blank, wherein
the crystal blank comprises
a flat plate part comprising a pair of major surfaces,
a pair of tableland-shaped first mesa parts projecting from the pair of major surfaces and
a pair of tableland-shaped second mesa parts projecting from upper surfaces of the pair of first mesa parts,
in the flat plate part, a length in the long direction is longer than a length in a short direction perpendicular to the long direction in a plan view, and the length in the long direction is less than 1000 ?m,
the first mesa part is longer in length in the long direction than length in the short direction and is located on an inner side from an outer edge of the major surface of the flat plate part over the entire circumference of the outer edge,
the second mesa part is longer in length in the long direction than length in the short direction, is located on an inner side from an outer edge of the upper surface of the first mesa part at two sides of the long direction, and has a width equivalent to a width of the upper surface of the first mesa part in the short direction, and
the excitation electrode reaches an outer edge of an upper surface of the second mesa part at the two sides of the long direction, an outer edge of the excitation electrode is located on an inner side from the outer edge of the upper surface of the first mesa part at the two sides of the long direction, and the outer edge of the excitation electrode is located on an inner side from the outer edge of the upper surface of the second mesa part at two sides of the short direction.

US Pat. No. 10,797,676

ACOUSTIC RESONATOR WITH ENHANCED BOUNDARY CONDITIONS

QUALCOMM Incorporated, S...

1. A resonator comprising:a volume of piezoelectric material comprising an upper surface and a lower surface;
a bottom electrode extending along a portion of the lower surface of the volume of piezoelectric material; and
a multi-layered top electrode extending along a portion of the upper surface of the volume of piezoelectric material, the multi-layered top electrode comprising:
an active region comprising a first portion of an interface layer, the first portion of the interface layer having a first thickness, the active region overlapping a portion of the bottom electrode;
a frame region comprising a second portion of the interface layer, the second portion of the interface layer having a second thickness, the second thickness being different from the first thickness;
an outer region comprising a third portion of the interface layer, the third portion of the interface layer having a third thickness, the third thickness being different from the second thickness;
a first interface sub-layer of the interface layer including a first interface material deposited from the frame region through the active region and the outer region; and
a second interface sub-layer of the interface layer disposed below the first interface sub-layer of the interface layer and including a second interface material deposited in the frame region.

US Pat. No. 10,797,675

TRANSVERSELY EXCITED FILM BULK ACOUSTIC RESONATOR USING ROTATED Z-CUT LITHIUM NIOBATE

Resonant Inc., Goleta, C...

1. An acoustic resonator device comprising:a substrate having a surface;
a rotated z-cut lithium niobate plate having front and back surfaces, the back surface attached to the surface of the substrate except for a portion of the lithium niobate plate forming a diaphragm that spans a cavity in the substrate; and
an interdigital transducer (IDT) formed on the front surface of the lithium niobate plate such that interleaved fingers of the IDT are disposed on the diaphragm, the IDT and the lithium niobate plate configured such that a radio frequency signal applied to the IDT excites a shear primary acoustic mode within the diaphragm, wherein
the Euler angles of the lithium niobate plate are [0°, ?, 90° ], where ? is greater than or equal to ?15° and less than 0°.

US Pat. No. 10,797,674

SIGNAL ACQUISITION DEVICE FOR HIGH-VOLTAGE LOOP, DETECTOR, BATTERY DEVICE, AND VEHICLE

CONTEMPORARY AMPEREX TECH...

1. An apparatus for processing signals of a high-voltage loop, comprising:a filter circuit configured to filter a signal from an element to be detected in the high-voltage loop;
a differential amplification circuit configured to amplify the filtered signal; and
a processor configured to process the amplified signal;
wherein the filter circuit connects to the element to be detected, the differential amplification circuit connects to the filter circuit, and the processor connects to the differential amplification circuit,
wherein the filter circuit further comprises a common-mode filter element, the common-mode filter element comprises a fourth resistor, a first filter capacitor, a fifth resistor, and a second filter capacitor;
wherein a first end of the fourth resistor connects to the first input end of the filter circuit, and a second end of the fourth resistor connects to a first end of the first filter capacitor;
a second end of the first filter capacitor is grounded;
a first end of the fifth resistor connects to the second input end of the filter circuit, a second end of the fifth resistor connects to a first end of the second filter capacitor; and
a second end of the second filter capacitor is grounded,
wherein the filter circuit further comprises a differential-mode filter element, the differential-mode filter element comprises the fourth resistor, the fifth resistor, and a third filter capacitor; and
wherein a first end of the third filter capacitor connects to a second end of the fourth resistor and a first input end of the differential amplification circuit, and a second end of the third filter capacitor connects to a second end of the fifth resistor and a second input end of the differential amplification circuit.

US Pat. No. 10,797,673

HIERARCHICAL CASCADING IN TWO-DIMENSIONAL FINITE ELEMENT METHOD SIMULATION OF ACOUSTIC WAVE FILTER DEVICES

RESONANT INC., Santa Bar...

1. A method of generating an optimized microwave acoustic wave (AW) structure, comprising:receiving, by a computing system, a set of frequency response requirements and a physical model of the AW structure;
partitioning, by the computing system, the physical model into a first plurality of unit blocks;
identifying, by the computing system, at least one core block within the first plurality of unit blocks;
computing, by the computing system, characteristics of each of the at least one core block;
deriving, by the computing system, characteristics for each unit block of a second plurality of unit blocks from the computed characteristics of the at least one core block, the second plurality of unit blocks comprising a subset of unit blocks of the first plurality of unit blocks not including the at least one core block;
combining, by the computing system, the second plurality of unit blocks into a single block having computed characteristics derived from the derived characteristics of each unit block of the second plurality of unit blocks and the computed characteristics of the at least one core block by hierarchically cascading sets of adjacent unit blocks into the single block, such that the single block subsumes the second plurality of unit blocks;
deriving, by the computing system, a frequency response of the AW structure at least partially from the computed characteristics of the single block;
comparing, by the computing system, the frequency response to the set of frequency response requirements; and
optimizing, by the computing system, the AW structure based on the comparison to provide an optimized design, the optimized design serving as an input to a manufacturing process.

US Pat. No. 10,797,672

SIGNAL CHANNEL EXPANDING SYSTEM BASED ON PAD

SHENZHEN CHINA STAR OPTOE...

1. A signal channel expanding system based on PAD, comprising:a motherboard disposed on an array tester; and
a plurality of array test pads disposed on a periphery of the motherboard and configured to control the motherboard;
wherein each of the array test pads comprises a plurality of pins, each of the pins corresponds to a signal channel, the array test pads comprise at least two left driving array test pads and at least two right driving array test pads,
wherein a length of each of the pins is 3.7 mm, and a width thereof is greater than or equal to 2.5 mm.

US Pat. No. 10,797,671

ELECTRONIC DEVICE AND EQUALIZER ADJUSTMENT METHOD

UNLIMITER MFA CO., LTD., ...

7. An electronic device, comprising:an equalizer;
a storage module, which stores a list of age gain values, the list of age gain values comprising a plurality of age segments between a first age segment and a Nth age segment, respectively increasing from the first age segment to the Nth age segment, each of the age segments comprising a group correction parameter, the group correction parameter comprising a plurality of compensation gain values respectively corresponding to a plurality of target frequency, and the compensation gain values in the same target frequency are increased as N increases; and
an equalizer adjustment module, electrically connected to the storage module and the equalizer, the equalizer adjustment module comprising:
an age data acquisition unit, which obtains an age data of a user;
a parameter inquiry unit, which obtains a target age segment according to the age data, wherein the target age segment is one of the age segments, the parameter inquiry unit obtaining the group correction parameter corresponding to the target age segment; and
a parameter setting unit, which is used to adjust a gain value setting of the equalizer to sound at different frequencies according to the group correction parameter.

US Pat. No. 10,797,670

AUDIO DEVICE WITH DYNAMICALLY RESPONSIVE VOLUME

Lutron Technology Company...

1. A device comprising:a microphone;
a speaker; and
a control circuit operably coupled to the microphone, the control circuit configured to:
play an audio track at the first volume level via the speaker;
receive a request via the microphone to play the audio track at a second volume level greater than the first volume level;
in response to the request, increase a volume level of the speaker from the first volume level to the second volume level and continue to play the audio track at the second volume level via the speaker;
detect an interrupt within a detection zone;
compare the second volume level to a threshold in response to the detection of the interrupt within the detection zone;
determine, based on the comparison, whether the second volume level is above or below the threshold; and
based on the determination that the second volume level is above the threshold, reduce the second volume level to the first volume level and continue to play the audio track at the first volume level; and
based on the determination that the second volume level is below the threshold, maintain the volume level at the second volume level.

US Pat. No. 10,797,669

SPEAKER WITH AUTOMATIC VOLUME CONTROL

Federal Signal Corporatio...

1. An apparatus for providing alerts, the apparatus comprising:a housing and a cover;
a hinge positioned between the housing and the cover to allow the cover to be pivoted relative to the housing from a close position to an open position, thereby maintaining all wiring of the apparatus in a connected state;
an audio device having a driver configured to compress air, the driver being operable in a first configuration as a speaker to provide alerts and operable in a second configuration as a microphone configured to sense an ambient noise level, the driver being positioned in, and fixed relative to, the housing;
a control board including a programmable logic controller data interface programmed to allow third parties to control or monitor the speaker, the control board being positioned in, and fixed relative to, the cover;
a wire electrically connecting the control board to a component positioned in, and fixed relative to, the housing; and
a processor configured to adjust a volume of the speaker based upon the ambient noise level.

US Pat. No. 10,797,668

MULTI-INPUT AMPLIFIER WITH VARIABLE GAIN FOR INDIVIDUAL INPUTS

SKYWORKS SOLUTIONS, INC.,...

1. A signal amplifier configured to process signals across a plurality of gain modes, the amplifier comprising:a multiplexer having a plurality of branches that direct signals from a corresponding plurality of input ports to an output port, each of the plurality of branches including a band selection switch and an attenuation selection branch, the band selection switch having a shunt switch circuit that selectively couples the corresponding input port to a reference potential node, the attenuation selection branch having a variable attenuation circuit, individual attenuation selection branches configured to provide a bypass path so that a signal received at a corresponding input port of the plurality of input ports is directed to the output port without being attenuated by a variable-attenuation element of the variable attenuation circuit; and
an amplification stage coupled to the output port of the multiplexer, the amplification stage configured to amplify signals received from the multiplexer to provide an amplified output signal, an amplification of the amplification stage or an attenuation of the variable attenuation circuit based on a gain mode of the plurality of gain modes.

US Pat. No. 10,797,667

AUDIO NOTIFICATIONS

Sonos, Inc., Santa Barba...

1. A playback device comprising:a network interface;
an audio stage comprising an amplifier;
one or more speaker drivers;
one or more processors; and
a housing, the housing carrying at least the network interface, the audio stage, the one or more speaker drivers, the one or more processors, and tangible, non-transitory, computer-readable media storing instructions executable by the one or more processors to cause the playback device to perform operations comprising:
while playing back a first audio notification via the audio stage and the one or more speaker drivers, receiving, via the network interface, an alert communication from a network-enabled device connected to the playback device via a local area network, the alert communication comprising (i) an audio notification identifier that identifies a second audio notification and (ii) a priority identifier that identifies a priority level of the second audio notification;
responsive to receiving the alert communication, adding the second audio notification to a notification queue at a particular queue position, wherein the particular queue position of the second audio notification in the notification queue is based on the priority level of the second audio notification relative to other audio content in the notification queue;
determining, based on the particular queue position of the second audio notification, that the second audio notification is ready for playback;
determining that the playback device has been playing back the first audio notification for a threshold amount of time corresponding to a partially-played back notification and
based on both (i) the second audio notification being ready for playback and (ii) the playback device having played back the first audio notification for the threshold amount of time corresponding to a partially-played back notification, stopping playback of the first audio notification and starting playback of the second audio notification via the audio stage and the one or more speaker drivers.

US Pat. No. 10,797,666

PORT VELOCITY LIMITER FOR VENTED BOX LOUDSPEAKERS

Samsung Electronics Co., ...

1. A method comprising:determining an energy stored in a port of a vented box loudspeaker based on a physical model of the vented box loudspeaker;
determining a time-varying attenuation to apply to a source signal for reproduction via the vented box loudspeaker based on the energy stored in the port; and
limiting velocity of air in the port during the reproduction of the source signal by controlling the energy stored in the port in real-time, wherein the controlling comprises attenuating the source signal based on the time-varying attenuation.

US Pat. No. 10,797,665

PROGRAMMABLE GAIN AMPLIFIER SYSTEMS AND METHODS

SYNAPTICS INCORPORATED, ...

1. A method comprising:amplifying a difference between a positive voltage input signal (Vp) and a negative voltage input signal (Vn) to generate an amplified differential output voltage comprising a positive voltage output signal (Voutp) and a negative voltage output signal (Voutn);
generating an itail voltage corresponding to a greater of the positive voltage input signal (Vp) and the negative voltage input signal (Vn);
applying the itail voltage and a first voltage corresponding to the positive voltage input signal (Vp) to a first resistor (rgp) to generate the positive voltage output signal (Voutp); and
applying the itail voltage and a second voltage corresponding to the negative voltage input signal (Vn) to a second resistor (rgn) to generate the negative voltage output signal (Voutn);
outputting a positive output current (Ioutp) corresponding to the current flowing through the first resistor (rgp), wherein if the positive voltage input signal (Vp) is greater than the negative voltage input signal (Vn), the positive output current (Ioutp) is proportional to the positive voltage input signal (Vp) minus the negative voltage input signal (Vn); and
outputting a negative output current (Ioutn) corresponding to the current flowing through the second resistor (rgn), wherein if the negative voltage input signal (Vn) is greater than the positive voltage input signal (Vp), the negative output current (Ioutn) is proportional to the negative voltage input signal (Vn) minus the positive voltage input signal (Vp).

US Pat. No. 10,797,664

APPARATUSES AND METHODS FOR A CHOPPER INSTRUMENTATION AMPLIFIER

Micron Technology, Inc., ...

1. An instrumentation amplifier comprising:a pair of input terminals;
first and second intermediate nodes;
an output terminal;
a first amplifying stage coupled between the pair of input terminals and the first intermediate node, the first amplifying stage comprises a first chopper amplifier and a first voltage follower;
a second amplifying stage coupled between the first intermediate node and the second intermediate node, the second amplifying stage comprises a second chopper amplifier and a second voltage follower; and
a third amplifying stage coupled between the second intermediate node and the output terminal, the third amplifying stage comprises a non-chopper amplifier;
wherein a gain of the first amplifying stage is greater than a gain of the third amplifying stage and a gain of the second amplifying stage is greater than the gain of the third amplifying stage, and wherein the first voltage follower and the second voltage follower comprise chopper amplifiers.

US Pat. No. 10,797,663

CAPACITIVE LOADING MODE MEASUREMENT CIRCUIT WITH COMPENSATION OF MEASUREMENT ERRORS DUE TO PARASITIC SENSOR IMPEDANCES

1. An impedance measurement circuit for determining a sense current of a guard-sense capacitive sensor operated in loading mode including an electrically conductive sense electrode and an electrically conductive guard electrode proximally arranged and mutually galvanically separated from each other, the impedance measurement circuit includinga periodic signal voltage source that is configured to provide a periodic measurement voltage to the guard electrode,
a sense current measurement circuit that is configured to determine a current flowing through the sense electrode that is indicative of an unknown impedance and represents a position of an object relative to the sense electrode,
a differential amplifier that is configured to sense a complex voltage difference between the sense electrode and the guard electrode,
demodulation means that are configured for demodulating an output signal of the differential amplifier and for obtaining, with reference to the periodic measurement voltage, an in-phase component and a quadrature component,
a first control loop that is configured to receive the in-phase component as an input signal, and a second control loop that is configured to receive the quadrature component as an input signal,
wherein an output signal of the first control loop and an output signal of the second control loop are used to form a complex voltage that serves as a complex reference voltage for the sense current measurement circuit.

US Pat. No. 10,797,662

AMPLIFYING CIRCUIT INCLUDING MILLER COMPENSATION CIRCUIT

SAMSUNG ELECTRONICS CO., ...

1. An amplifying circuit comprising:an amplifier configured to receive a first input voltage, and output a first output voltage by amplifying the first input voltage; and
a common-mode feedback circuit configured to enable the first output voltage to operate in a common mode by receiving the first output voltage and performing a feedback to adjust at least one feedback voltage applied to the amplifier based on the first output voltage,
wherein the amplifier comprises:
a first amplifier configured to receive and amplify the first input voltage to generate a second input voltage; and
a second amplifier configured to receive and amplify the second input voltage to generate the first output voltage,
wherein the at least one feedback voltage is applied to the first amplifier, and
wherein the common-mode feedback circuit comprises:
an output voltage sensing circuit configured to output a first sensing voltage by sensing the first output voltage;
an operational amplifier configured to adjust the at least one feedback voltage that is applied to the amplifier, based on the first sensing voltage and a reference voltage; and
a first Miller compensation circuit configured to perform dominant pole compensation by using a Miller effect for the common-mode feedback circuit, the first Miller compensation circuit comprising a first resistor and a first capacitor that are connected in series with each other.

US Pat. No. 10,797,661

CAPACITIVE-COUPLED CHOPPER INSTRUMENTATION AMPLIFIERS AND ASSOCIATED METHODS

Maxim Integrated Products...

1. A capacitive-coupled chopper instrumentation amplifier (CCIA), comprising:a first chopper;
a first gain stage;
a capacitive isolation stage electrically coupled between inputs of the first gain stage and the first chopper;
a second gain stage;
a second chopper electrically coupled between outputs of the first gain stage and inputs of the second gain stage;
clamping circuitry electrically coupled between the inputs of the first gain stage and a reference voltage rail, the clamping circuitry configured to clamp the inputs of the first gain stage to the reference voltage rail in response to assertion of a control signal; and
a controller configured to:
detect a change in a first common-mode voltage exceeding a threshold value, the first common-mode voltage being a common-mode voltage at inputs of the CCIA, and
in response to detecting the change in the first common-mode voltage exceeding the threshold value, assert the control signal to cause the clamping circuitry to clamp the inputs of the first gain stage to the reference voltage rail.

US Pat. No. 10,797,660

MULTIPHASE BUCK-BOOST AMPLIFIER

MAXIM INTEGRATED PRODUCTS...

1. A system comprising:a first buck-boost amplifier that is connected to a battery, that includes a first inductor, and that drives a first load;
a second buck-boost amplifier that is connected to the battery, that includes a second inductor, and that drives a second load;
a third inductor;
a plurality of switches connected to the third inductor; and
a controller that drives the plurality of switches to connect the third inductor to the first buck-boost amplifier or the second buck-boost amplifier.

US Pat. No. 10,797,659

AUDIO AMPLIFIER HAVING MULTIPLE SIGMA-DELTA MODULATORS TO DRIVE AN OUTPUT LOAD

SEMICONDUCTOR COMPONENTS ...

1. An audio amplifier comprising:a first clock generator configured to generate a first clock signal defining a first sampling rate;
a second clock generator configured to generate a second clock signal defining a second sampling rate greater than the first sampling rate;
a first sigma-delta modulator configured to receive a digital audio signal and the first clock signal, and configured to generate a first multi-level output signal according to the first clock signal; and
a second sigma-delta modulator configured to receive the first multi-level output signal from the first sigma-delta modulator and the second clock signal, and configured to generate a second multi-level output signal according to the second clock signal, the second multi-level output signal having a number of levels less than a number of levels of the first multi-level output signal, the number of levels of the second multi-level output signal being two or three.

US Pat. No. 10,797,658

LOW POWER OPTICAL LINK

Xilinx, Inc., San Jose, ...

1. An optical receiver circuit, comprising:an input terminal to receive an input signal indicative of information contained in an optical signal;
an output terminal to provide an output signal based at least in part on the input signal; and
a first amplifier stage coupled between the input and output terminals of the optical receiver circuit, the first amplifier stage comprising:
a first inverter including an output coupled to the output terminal of the optical receiver circuit;
a first inductor coupled between the input terminal of the optical receiver circuit and an input of the first inverter; and
a second inductor and a first resistor coupled between the input and the output of the first inverter;
a single-ended to differential conversion circuit coupled to an output of the first amplifier stage and configured to generate first and second delayed signals based at least in part on the input signal, wherein the first and second delayed signals form a differential signal indicative of the input signal;
a second amplifier stage coupled to the single-ended to differential conversion circuit and configured to generate a first component of a differential output signal based at least in part on the first delayed signal; and
a third amplifier stage coupled to the single-ended to differential conversion circuit and configured to generate a second component of the differential output signal based at least in part on the second delayed signal.

US Pat. No. 10,797,657

MATCHING NETWORK AND POWER AMPLIFIER CIRCUIT

MURATA MANUFACTURING CO.,...

1. A matching network of a power amplifier circuit that receives, at an input node, a high-frequency signal and that outputs, to an output node, a signal obtained by amplifying a power of the high-frequency signal with a differential amplifier, the matching network comprising:an input-side winding connected between differential outputs of the differential amplifier;
an output-side winding that is coupled to the input-side winding via an electromagnetic field, wherein a first end of the output-side winding is connected to a reference potential;
a first LC series resonant circuit connected in parallel with the input-side winding, the first LC series resonant circuit comprising a first capacitive element and a first inductive element connected in series with each other; and
a second LC series resonant circuit connected in parallel with the output-side winding, the second LC series resonant circuit comprising a second capacitive element and a second inductive element connected in series with each other.

US Pat. No. 10,797,656

BREAKDOWN PROTECTION CIRCUIT FOR POWER AMPLIFIER

ANALONG DEVICES GLOBAL UN...

1. An apparatus comprising:an amplifier; and
a protection circuit comprising a transistor, wherein the transistor is a physical transistor, wherein a control terminal of the transistor is electrically coupled to a control terminal of the amplifier, wherein a power terminal of the transistor is electrically coupled to a power terminal of the amplifier, wherein the protection circuit is configured to reduce a voltage swing at the amplifier based at least in part on a presence of a threshold power at the control terminal of the amplifier or the power terminal of the amplifier.

US Pat. No. 10,797,655

WIRELESS RECEIVER

Taiwan Semiconductor Manu...

1. A low noise amplifier (LNA), comprising:a first transistor, having a first type, and configured to provide a first transconductance; and
a second transistor, having a second type being different from the first type, and configured to provide a second transconductance; and
a common-mode feedback circuit, wherein the common-mode feedback circuit comprises at least one resistor having a first end coupled to a gate of the second transistor and a second end, opposite the first end, coupled to a drain of the second transistor,
wherein the LNA is configured to use a sum of the first and second transconductances to amplify an input signal, and wherein respective source ends of the first and second transistors are coupled together by a blocking capacitor.

US Pat. No. 10,797,654

AMPLIFYING DEVICE COMPRISING A COMPENSATION CIRCUIT

DEVIALET, Paris (FR)

1. An amplification device of an input signal comprising:a differential input for the input signal,
a differential output for an output signal,
a first amplification stage having an input,
a second amplification stage having an input,
the inputs of each amplification stage forming the differential input,
each amplification stage comprising:
an output for a load, the outputs of each amplification stage forming the differential output,
a switching circuit, the switching circuit being able to generate, as output, a switched signal having at least two states,
an inductive element connected between the output of the switching circuit and the output of the amplification stage, the inductive element being able to smooth the switched signal generated by the switching circuit to obtain a smoothed signal, the smoothed signal having a useful component and a stray component, the switched signals at the output of the switching circuits of each amplification stage being opposite,
the amplification device further comprising a compensation circuit, for each amplification stage, the amplification device being capable of generating a compensation signal of the stray component of the smoothed signal generated in the inductive element of said amplification stage, each compensation circuit being connected to the output of the corresponding amplification stage and the output of the switching circuit of the other amplification stage, the differences of each smoothed signal and the corresponding compensation signal forming the output signal at the output of the amplification device; wherein
(a) the amplification stages are amplification stages of a digital signal, the device further comprising at least one analog amplifier, the output of which is connected at the output of one of the amplification stages;
(b) the or each analog amplifier is either a class A amplifier and a class AB amplifier; and
(c) the device further comprises a device for measuring the output current of each analog amplifier and a control module capable of receiving at least the measurement of the output current of each analog amplifier, the control module being able to generate the signals at the input of the amplification stages as a function of the measured output currents so that, on the one hand, the switched signals at the output of the switching circuits of said stages are opposite, and on the other hand, the output current of each of the analog amplifiers is minimized.

US Pat. No. 10,797,653

CONSECUTIVE DOHERTY AMPLIFIER

Sumitomo Electric Device ...

1. A consecutive Doherty amplifier that outputs an amplified signal by receiving an input radio frequency (RF) signal, the consecutive Doherty amplifier comprising:an input terminal that receives the input RF signal thereto;
a carrier amplifier that receives the input RF signal provided in the input terminal without interposing any signal splitters;
a power splitter that splits a signal output from the carrier amplifier into a first split signal and a second split signal;
a peak amplifier that receives the second split signal; and
a phase compensator provided between the power splitter and the peak amplifier, the phase compensator compensating a phase difference between the first split signal output from the power splitter and a signal output from the peak amplifier;
wherein the consecutive Doherty amplifier outputs the first split signal when the peak amplifier turns off, and the first split signal combined with the signal output from the peak amplifier when the peak amplifier turns on,
wherein the carrier amplifier integrates the power splitter therein,
wherein the carrier amplifier includes a plurality of cells each concurrently receiving the input RF signal,
wherein the cells in a portion thereof outputs the first split signal and in a rest portion thereof outputs the second split signal, and
wherein the cells collectively have a function of the power splitter.

US Pat. No. 10,797,652

DC-TO-DC CONVERTER BLOCK, CONVERTER, AND ENVELOPE TRACKING SYSTEM

WUPATEC, Limoges (FR)

1. A high-frequency and high-power multi-power supply voltage dc/dc converter block comprising:a power circuit, the output of the power circuit being the output of the dc/dc converter block, the power circuit comprising N depletion high-electron-mobility (HEMT) transistors, N being a positive integer greater than or equal to 3; and
a driving circuit comprising depletion HEMT transistors configured to drive gates of the N depletion HEMT transistors of the power circuit,
wherein the power circuit is power supplied with N non-zero and positive power supply voltages including a low power supply voltage, a high power supply voltage, and (N?2) intermediary power supply voltages, the high power supply voltage being greater than the low power supply voltage, each intermediary power supply voltage being different from the low and high power supply voltages and the (N?2) intermediary power supply voltages being different from each other and comprised between the low and high power supply voltages, and
the driving circuit comprises, for each gate of the respective depletion HEMT transistor of the power circuit to be driven,
a first depletion HEMT driving transistor of the depletion HEMT transistors of the driving circuit,
a second depletion HEMT driving transistor of the depletion HEMT transistors of the driving circuit,
first, second, and third resistors,
a Schottky diode, and
an auxiliary power supply voltage,
the source of the first depletion HEMT driving transistor being connected to the ground,
the drain of the first depletion HEMT driving transistor being connected to one of the terminals of the first resistor and to one of the terminals of the second resistor,
the gate of the first depletion HEMT driving transistor being connected to a corresponding input of the driving circuit, the gate of the second depletion HEMT driving transistor being connected to the other of the terminals of the first resistor,
the source of the second depletion HEMT driving transistor being connected to the other of the terminals of the second resistor, to the cathode of the Schottky diode and to one of the terminals of the third resistor,
the anode of the Schottky diode being connected to the auxiliary power supply voltage,
the other of the terminals of the third resistor being connected to the gate of the corresponding depletion HEMT transistor of the power circuit to be driven,
the drain of the second depletion HEMT driving transistor being connected to the low power supply voltage when the low power supply voltage is connected to the conduction output terminal of the corresponding depletion HEMT transistor of the power circuit to be driven, or being connected to the corresponding intermediary or high power supply voltage when the intermediary or high power supply voltage is connected to the conduction input terminal of the corresponding depletion HEMT transistor of the power circuit to be driven,
the auxiliary power supply voltage being greater than the pinch-off voltage of the second depletion HEMT driving transistor, and
the low power supply voltage being greater than the auxiliary power supply voltage plus the pinch-off voltage of the corresponding depletion HEMT transistor of the power circuit to be driven.

US Pat. No. 10,797,651

AMPLIFIER OFFSET CANCELLATION USING AMPLIFIER SUPPLY VOLTAGE

Cirrus Logic, Inc., Aust...

1. A method for power supply offset rejection for an amplifier, comprising:converting a power supply voltage of the amplifier into a quantity indicative of the power supply voltage, wherein the quantity is a digital signal;
generating a correction signal by multiplying the quantity by a transfer function defining a response from the power supply voltage to an output signal of the amplifier; and
subtracting the correction signal from a signal within a signal path of a circuit comprising the amplifier.

US Pat. No. 10,797,650

ENVELOPE TRACKING AMPLIFIER APPARATUS

Qorvo US, Inc., Greensbo...

1. An envelope tracking (ET) amplifier apparatus comprising:a tracker circuit comprising a main voltage amplifier circuit configured to generate a main modulated voltage;
an amplifier apparatus coupled to the tracker circuit and comprising:
a local voltage amplifier circuit configured to generate a local modulated voltage; and
an amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage; and
a control circuit configured to:
activate the amplifier circuit in response to the RF signal being modulated above a defined modulation bandwidth; and
activate the local voltage amplifier circuit to provide the local modulated voltage to the amplifier circuit as the modulated voltage.

US Pat. No. 10,797,649

MULTI-MODE ENVELOPE TRACKING AMPLIFIER CIRCUIT

Qorvo US, Inc., Greensbo...

1. A multi-mode envelope tracking (ET) amplifier circuit comprising:an output node;
at least one power amplifier circuit coupled to the output node and configured to amplify a radio frequency (RF) signal;
ET tracker circuitry configured to provide an ET modulated voltage to the output node;
fast switcher circuitry comprising a first switcher path and a second switcher path and configured to generate an alternate current (AC) current; and
a control circuit configured to activate the fast switcher circuitry to provide the AC current to the output node via the first switcher path and the second switcher path in a high-resource block (RB) mode.

US Pat. No. 10,797,648

MIXER MODULE

RichWave Technology Corp....

1. A mixer module, comprising:a mixer, mixing an input signal to generate a first signal;
at least one DC offset circuit, generating a second signal based on the first signal;
a filter, filtering out an AC portion of the second signal and generating a third signal according to a DC portion of the second signal; and
a controller, controlling the at least one DC offset circuit based on the third signal to reduce a DC portion of the first signal.

US Pat. No. 10,797,647

RECEIVER APPARATUS

GM GLOBAL TECHNOLOGY OPER...

1. A receiver apparatus, the apparatus comprising:a transconductance mixer comprising a gate, a source and a drain, wherein the source is configured to receive a first signal from a first low noise amplifier at a receiving frequency and the drain is configured to output a second signal at an intermediate frequency to a second low noise amplifier; and
a local oscillator configured to apply a third signal to the gate, wherein the local oscillator comprises:
a signal driver configured to drive a driver signal;
a multiplier configured to receive the driver signal output by the signal driver, multiply the signal, and output a multiplied signal;
a differential to single ended transformer configured to receive the multiplied signal, transform the multiplied signal, and output a transformed signal;
a gain amplifier configured to receive the transformed signal, amplify the transformed signal, and output the gain amplified signal; and
a filter comprising a notch filter and a bandpass filter, the filter configured to receive the gain amplified signal, filter the gain amplified signal to reject out-of-band harmonics and noise, and output a filtered signal as the third signal to the gate.

US Pat. No. 10,797,646

VARIABLE GAIN POWER AMPLIFIERS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:an oscillator that includes a first output and a second output;
a power amplifier that includes:
a first amplifier stage that includes an input coupled to the first output of the oscillator and includes an output;
a second amplifier stage that includes an input coupled to the output of the first amplifier stage and includes an output;
a third amplifier stage that includes an input coupled to the second output of the oscillator and includes an output;
a fourth amplifier stage that includes an input coupled to the output of the third amplifier stage and includes an output; and
a selection circuit that includes a first input coupled to the output of the second amplifier stage and a second input coupled to the output of the fourth amplifier stage,
wherein the oscillator is configured to:
provide a first oscillating signal at the first output; and
provide a second oscillating signal at the second output that is an attenuated version of the first oscillating signal.

US Pat. No. 10,797,645

CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

Seiko Epson Corporation, ...

1. A circuit device having a first mode in which the circuit device outputs a clock signal and a second mode in which the circuit device does not output the clock signal, the circuit device comprising:an oscillation circuit generating the clock signal;
a non-volatile memory in which characteristic adjustment data of the oscillation circuit is stored;
a reset circuit generating a reset signal; and
a storage circuit into which the characteristic adjustment data is loaded from the non-volatile memory when the reset signal transitions from active to inactive, wherein
the reset circuit causes the reset signal to transition from active to inactive when the circuit device shifts from the second mode to the first mode,
the first mode is a normal operating mode of the circuit device, and
the second mode is a standby mode of the circuit device.

US Pat. No. 10,797,644

OSCILLATOR, ELECTRONIC APPARATUS, AND VEHICLE

SEIKO EPSON CORPORATION, ...

1. An oscillator comprising:a resonation element;
a first package that houses the resonation element and is airtightly sealed;
a circuit element that
has an active surface,
is positioned outside the first package and electrically connected to the resonation element, and
has an oscillation circuit and a temperature compensation circuit; and
a second package that houses the first package and the circuit element and is sealed in a depressurized state, wherein:
the first package includes
a first base that has two first main surfaces and a first recessed portion that is provided on one of the first main surfaces, and
a first lid that is joined to the first base so as to close an opening of the first recessed portion,
the second package includes
a second base that has two second main surfaces and a second recessed portion that is provided on one of the second main surfaces, and
a second lid that is joined to the second base so as to close an opening of the second recessed portion,
the active surface of the circuit element is attached to the first base via a first metal bump that electrically connects the circuit element and the first package,
the active surface, except a part attached to the first base via the first metal bump, is separated apart from the first base and is exposed to an atmosphere inside the second package, and
the first base is attached to the second base.

US Pat. No. 10,797,643

OSCILLATION CIRCUIT, MICROCOMPUTER AND ELECTRONIC DEVICE

SEIKO EPSON CORPORATION, ...

1. An oscillation circuit, comprising:a charge-discharge type oscillation unit that performs an oscillation operation at an oscillating frequency that is associated with a value of a control current; and
a control current generation unit that generates the control current,
wherein the control current generation unit includes:
a reference voltage generation circuit that generates a reference voltage that has a first temperature characteristic;
a temperature characteristic slope correction circuit that corrects a slope of a temperature characteristic of the reference voltage in accordance with first correction information and generates an output voltage that has a second temperature characteristic; and
a voltage-current conversion circuit that converts the output voltage of the temperature characteristic slope correction circuit into the control current, and that corrects the value of the control current in accordance with second correction information,
wherein the temperature characteristic slope correction circuit includes:
a constant voltage generation circuit that generates a constant voltage;
a differential amplifier circuit that amplifies the reference voltage with the constant voltage as a reference; and
a first resistor that has a resistance value that is set in accordance with the first correction information and sets an amplification factor of the differential amplifier circuit, and
the temperature characteristic slope correction circuit corrects the slope of the temperature characteristic of the reference voltage based on the resistance value of the first resistor.

US Pat. No. 10,797,642

RESONANT CLOCK CIRCUIT WITH MAGNETIC SHIELD

INTERNATIONAL BUSINESS MA...

1. A semiconductor device, comprising:a first resonant clock circuit having a first inductor and a first capacitor;
a second resonant clock circuit having a second inductor and a second capacitor electrically connected to the first resonant clock circuit by first and second conducting materials, respectively,
a first magnetic layer; and
a second magnetic layer;
wherein the first and second magnetic layers are disposed above the first and second conducting materials, respectively, to use a parasitic capacitance of at least one of the first and second resonant clock circuits to operate at least one of the first and second resonant clock circuits.

US Pat. No. 10,797,641

SYSTEM AND METHOD FOR TESTING PHOTOSENSITIVE DEVICE DEGRADATION

Hunt Perovskite Technolog...

1. A system comprising:a light source plate, wherein the light source plate emits light at an intensity level;
a cell interface plate;
a container proximate to the light source plate and coupled to the cell interface plate, wherein the container comprises a plurality of photosensitive devices, wherein a plurality of pins associated with a plurality of pixels of each of the plurality of photosensitive devices interfaces with the container, and wherein the container interfaces the plurality of pins to the cell interface plate;
a light metering device proximate to the light source plate, wherein the light metering device measures the intensity of emissions from the light source plate to the photosensitive devices;
a light power source coupled to the light source plate, wherein the light power source controls one or more of current and voltage to the light source plate;
a multiplexor coupled to the cell interface plate, wherein the multiplexor activates circuitry to address the plurality of pixels; and
a measuring device coupled to the multiplexor, wherein the measuring device receives one or more performance measurements associated with the plurality of pixels.

US Pat. No. 10,797,640

SYSTEM AND METHOD FOR AUTOMATED PERFORMANCE ASSESSMENT OF PEROVSKITE OPTOELECTRONIC DEVICES

OKINAWA INSTITUTE OF SCIE...

1. A system for assessing performance of a plurality of devices, the system comprising:a chamber housing a device holder configured to hold the plurality of devices, the chamber having a chamber wall defining an opening that is sealed with a window;
a light source configured to emit light that enters the chamber through the window to shine the plurality of devices in the device holder, wherein the plurality of devices are a plurality of perovskite solar cells;
a switch board coupled to the device holder for allowing selection of a device among the plurality of devices for measurement;
a DC voltage supply coupled to the switch board to apply voltage to the device;
a source/measure unit (SMU) coupled to the switch board for measuring current of the device;
a computer implemented with a software program including computer executable instructions to control at least the SMU, the DC voltage supply, the switch board, and the light source, to obtain at least one of first current-versus-voltage (I-V) data based on a first procedure and second I-V data based on a second procedure for analyzing hysteresis behavior of the device, and
wherein the first procedure includes averaging of current values measured from the SMU over an acquisition time for each voltage value to obtain the first I-V data, and the second procedure includes obtaining a steady-state current value measured from the SMU for each voltage to obtain the second I-V data.

US Pat. No. 10,797,639

SYSTEM AND METHOD FOR PERFORMING POWER UTILITY REMOTE CONSUMER ENERGY AUDITING WITH THE AID OF A DIGITAL COMPUTER

CLEAN POWER RESEARCH, L.L...

1. A method for performing power utility remote consumer energy auditing, comprising the steps of:assessing through a power metering infrastructure energy loads for a building situated in a known location as measured over a seasonal time period; and
operating under a control of a power utility through which the building is provided electric power a digital computer, the digital computer comprising a processor and a memory that is adapted to store program instructions for execution by the processor, the program instructions capable of:
obtaining outdoor temperatures for the building as measured over the seasonal time period;
determining a baseload energy consumption from the energy loads;
calculating seasonal fuel consumption rates and balance point temperatures using only the energy loads and the outdoor temperatures;
generating temperature distributions from the outdoor temperatures over the seasonal time period;
disaggregating seasonal fuel consumption based on the baseload energy consumption, seasonal fuel consumption rates, balance point temperatures, and temperature distributions into component loads of consumption;
performing energy auditing for a multiplicity of the power utility's customers remotely and totaling the season fuel consumption with seasonal fuel consumptions of the customers; and
factoring the seasonal fuel consumptions as aggregated into balancing power output of power generation equipment operated under control of the power utility.

US Pat. No. 10,797,638

PLANAR SOLAR CONCENTRATOR

NATIONAL TAIWAN NORMAL UN...

1. A planar solar concentrator comprising:a light collecting assembly including
a light collecting unit including a light collector which has an input surface that is for receiving an incident light from a light source, an output surface that is opposite to said input surface in an upright direction, and a curved surface that extends to interconnect said input and output surfaces, and that has a curvature to direct the incident light toward a collecting zone on said output surface, and
a waveguide slab extending in a longitudinal direction to terminate at a rear end segment and a front end segment which is coupled to said collecting zone so as to permit the incident light to be introduced into said waveguide slab, said waveguide slab being configured to permit the incident light from said light collector to be directed toward a rear end surface of said rear end segment, said waveguide slab further extending in a transverse direction relative to the longitudinal direction; and
a light condensing unit which is slidably coupled to said rear end surface, and which is configured for condensing the incident light from said waveguide slab, said light condensing unit being coupled such that based on an elevation angle of the light source, said light condensing unit is permitted to be driven to slide in the transverse direction.

US Pat. No. 10,797,637

SYSTEM AND METHOD FOR DEBRIS REMOVAL

Snolar Technologies Ltd.,...

7. A debris removal wing for removing debris from solar modules in a solar module array, the debris removal wing comprising:a body having a first side configured to be positioned proximate an operating surface of a target solar module, the body having a leading end portion having a width spanning a working portion of the solar module array;
an air inlet in the body configured to receive pressurized air;
a first air outlet in the body configured to direct a first portion of the pressurized air out the leading end portion of the debris removal wing in a blowing direction, the blowing direction including a first vector component parallel with operating surfaces of solar modules of the working portion of the solar module array when the wing is positioned with the first side substantially parallel and adjacent to the operating surface of the target solar module for cleaning; and
at least one extending member extending from the leading end portion of the body in a leading direction, the at least one extending member having a distal end curved away from the operating surfaces of the solar modules when the wing is positioned with the first side substantially parallel and adjacent to the operating surface of the target solar module for cleaning.

US Pat. No. 10,797,636

WATERLESS CLEANING SYSTEM AND METHOD FOR SOLAR TRACKERS USING AN AUTONOMOUS ROBOT

EVERMORE UNITED S.A., Ro...

1. A solar tracker waterless cleaning system for cleaning solar panels of a solar tracker, said solar tracker being able to be positioned at a pre-determined angle, said solar tracker waterless cleaning system comprising:a docking station, coupled with an edge of said solar tracker; and
an autonomous robotic cleaner (ARC) capable of omnidirectional travel independent of the docking station,
said ARC comprising:
at least one rechargeable power source;
at least one cleaning cylinder, for cleaning dirt off of a surface of said solar tracker without water; and
a controller, for controlling a cleaning process of said ARC and for transmitting and receiving signals to and from said ARC,
said controller comprising a motion sensor, for determining an angle of said solar tracker and a heading of said ARC;
said at least one cleaning cylinder further comprising a plurality of fins which rotates and exerts a pressure of less than 0.1 g/cm2 on said surface of said solar tracker for generating a directional air flow for pushing said dirt off of said surface of said solar tracker;
said docking station comprising at least one electrical connector for recharging said rechargeable power source,
wherein said ARC can anchor in said docking station;
wherein said ARC cleans said solar tracker when said solar tracker is positioned at said pre-determined angle;
wherein said pre-determined angle is determined from a horizontal angle of zero degrees;
wherein said motion sensor is used for navigating said ARC over said surface of said solar tracker;
wherein said plurality of fins touches said surface of said solar tracker when said plurality of fins rotates; and
wherein said ARC cleans said solar tracker by said directional air flow and said touch of said plurality of fins pushing said dirt off of said surface of said solar tracker while said motion sensor navigates said ARC autonomously over said surface of said solar tracker.

US Pat. No. 10,797,635

SOLAR MODULE MOUNTING BRACKET ASSEMBLIES

NEXTRACKER INC., Fremont...

1. A solar module mounting bracket assembly, comprising:a rail configured to support a solar module thereon;
a pair of braces each having a first end portion movably coupled to the rail, wherein the pair of braces are movable relative to the rail between a collapsed configuration, and an expanded configuration, in which the pair of braces cooperatively define a channel dimensioned for receipt of a frame member; and
a plurality of coupling devices disposed on an upper side of the rail, wherein the plurality of coupling devices are configured to fix a solar module to the rail.

US Pat. No. 10,797,634

HEIGHT-ADJUSTABLE RAIL-LESS SOLAR PANEL MOUNTING DEVICE FOR ROOFS

Sunmodo Corporation, Van...

1. A device for mounting a solar panel to a roof surface, comprising:a base securable to the roof surface;
a slider captively slidable along the base along a lengthwise axis thereof;
a platform positioned above the slider, the platform including a centerline of which the solar panel can be mounted on either side of the centerline thereof;
a height adjuster and a threaded locking fastener are positioned on opposite sides of the platform proximate to the centerline and are each upwardly oriented;
the height adjuster by rotatably engaging the platform through the slider, causes the platform and the solar panel to move a distance relative to the slider, the base, and the roof surface; and
the threaded locking fastener slidably engages the base into the slider and is impingeable against the base to control sliding of the slider relative to the base.

US Pat. No. 10,797,633

THERMAL EMITTER FOR ENERGY CONVERSION TECHNICAL FIELD

Mitsubishi Electric Resea...

1. A thermophotovoltaic (TPV) system for converting heat into electricity, the TPV system includes a thermal emitter and a photovoltaic cell arranged in proximity to each other, wherein the thermal emitter is configured to absorb the heat to emit photons of radiation toward the photovoltaic cell which is configured to convert energy of the emitted photons into the electricity, wherein the thermal emitter, comprising:a substrate;
a grating arranged atop the substrate, such that the grating forms an emitting surface of the thermal emitter oriented toward the photovoltaic cell, the grating includes a plurality of equidistant structures each having a cross-section with a trapezoid shape, wherein material of the substrate and material of the grating include refractory metal to convert the heat incoming to a surface of the thermal emitter opposite to the emitting surface into the radiation, wherein the refractory metal in the material of the substrate is the same or different from the refractory metal in the material of the grating; and
a dielectric layer arranged between the grating and the substrate.

US Pat. No. 10,797,632

SENSITIVE DIRECTIONAL ELEMENT FOR GENERATOR PROTECTION

Schweitzer Engineering La...

1. A system for protecting an electric power generation installation in an electric power delivery system, comprising:a first protective device in electrical communication with a first generator of the generation installation, comprising:
a first voltage sensor component in electrical communication with a potential transformer of the electric power delivery system, obtaining a voltage signal corresponding with a voltage of the first generator;
a first sensitive current sensor component in electrical communication with a current transformer, obtaining a sensitive current signal of the first generator;
a first processor;
a first non-transitory computer-readable storage medium in communication with the processor, the first voltage sensor component, and the sensitive current sensor component, comprising instructions that when operated cause the processor to:
detect a ground fault of the generator installation using voltage signals from the voltage sensor component;
calculate sensitive current values of the first generator using the sensitive current signal, and store the sensitive current values;
when the ground fault is detected,
calculate an incremental residual current of the first generator as a difference between a present sensitive current value and a previous sensitive current values from the stored sensitive current values of the first generator;
calculate an admittance of the first generator using the incremental residual current of the first generator; and
determine a direction to the ground fault as forward to the first generator by comparing the admittance of the first generator against a forward admittance threshold; and
upon determination of a forward fault, effect a protective action of the first generator.

US Pat. No. 10,797,631

POWER OUTPUT DEVICE

KABUSHIKI KAISHA TOYOTA J...

1. A power output device comprising:a field winding;
a motor including a plurality of star-connected motor windings having three or more phases;
a capacitor;
an inverter circuit configured to convert electric power supplied from the capacitor and supply the converted electric power to the motor windings;
a battery connected to the field winding; and
a controller, wherein
the inverter circuit includes a positive bus bar, a negative bus bar, and a plurality of switching element pairs respectively corresponding to the motor windings, wherein the switching element pairs each include an upper arm switching element and a lower arm switching element that are connected in series to each other,
the capacitor is connected to the positive bus bar and the negative bus bar,
the field winding is connected to one of the positive bus bar or the negative bus bar, and a neutral point of the motor, and
the controller is configured to control the switching element pairs to charge the capacitor by stepping up a voltage of the battery and to supply a direct current to the field winding.

US Pat. No. 10,797,630

METHOD OF MODULATING CASCADED THREE-PHASE VFD

Delta Electronics (Shangh...

1. A method of modulating a cascaded three-phase VFD, wherein each stage of the cascaded three-phase converter comprises three power units, to provide corresponding output voltages of phase A, phase B and phase C, and the method comprises:in step 1: obtaining a plurality of space voltage vectors according to states of switches and output levels of the power units in the stage, and dividing the plurality of space voltage vectors into large vectors, medium vectors, small vectors and zero vectors according to lengths of the plurality of space voltage vectors;
in step 2, arranging the plurality of space voltage vectors into a vector space, and dividing the vector space into a plurality of sectors by the plurality of space voltage vectors, wherein each of the sectors corresponds to a group consisting of the large vector, the medium vector, the small vector and the zero vector;
in step 3, determining a sector in which a reference voltage vector is located, wherein the reference voltage vector is composed by the group consisting of the large vector, the medium vector, the small vector and the zero vector, corresponding to the sector;
in step 4, in one switching period, respectively calculating action time of the vectors in the group;
in step 5, allocating an action order to the zero vector, the small vector, the medium vector and the large vector;
in step 6, generating a three-phase modulated wave signal based on the action order and the action time of the vectors in the group; and
in step 7, generating switching signals for the power units in the stage according to the generated three-phase modulated wave signals.

US Pat. No. 10,797,629

LOW SPEED SENSORLESS ROTOR ANGLE ESTIMATION

TEXAS INSTRUMENTS INCORPO...

1. A method for controlling a brushless motor, the method comprising:injecting a periodic signal into a field oriented controller of the brushless motor, the motor having a rotor and a stator;
measuring phase currents in stator windings of the brushless motor;
determining a d-axis current and a q-axis current with a transform of the phase currents;
demodulating the d-axis current and the q-axis current to extract an angle dependent current signature that includes a sine component of a rotor angle estimate and a cosine component of the rotor angle estimate, in which demodulating the d-axis current includes correcting a direct current (DC) offset of the demodulated d-axis current; and
determining the rotor angle estimate by processing the sine component and cosine component.

US Pat. No. 10,797,628

GAS TURBINE ENGINE AND ELECTRICAL SYSTEM

Rolls-Royce North America...

9. An electrical system coupled to a gas turbine engine, and to a primary electrical bus and a secondary electrical bus, the electrical system comprising:a first electrical machine and a second electrical machine, the first and second electrical machines coupled to the gas turbine engine, the first electrical machine electrically coupled in parallel to both the primary electrical bus and to the secondary electrical bus via a first pair of inverter/converter controllers, and the second electrical machine electrically coupled in parallel to both the primary electrical bus and to the secondary electrical bus via a second pair of inverter/converter controllers;
a first controller configured to control operation of the gas turbine engine;
a second controller coupled to the first controller, the second controller configured to respond to control inputs from the first controller and control an electrical output of the first and second electrical machines to the primary and secondary electrical busses;
an energy storage system; and
a converter controller coupled to the energy storage system, the second controller, the primary electrical bus, and the secondary electrical bus;
wherein the converter controller is configured to control an amount of electrical power, under direction from the second controller, passing between the energy storage system and at least one of the primary and secondary electrical busses,
wherein the first pair of inverter/converter controllers comprises a first inverter/converter controller and a second inverter/converter controller, the first inverter/converter controller coupled to the primary electrical bus, the second inverter/converter controller coupled to the secondary electrical bus, and
wherein the second pair of inverter/converter controllers comprises a third inverter/converter controller and a fourth inverter/converter controller, the third inverter/converter controller coupled to the primary electrical bus, the fourth inverter/converter controller coupled to the secondary electrical bus.

US Pat. No. 10,797,627

COMPRESSED AIR TURBINE DC POWER GENERATOR SYSTEM

SUZHOU DSM GREEN POWER LT...

1. A compressed air turbine DC power generator system, comprising:an air pressure powered turbine engine;
a direct current generator configured to generate a direct current by using power output of the air pressure powered turbine engine as a driving input; and
a control unit configured to control a rotating speed of the air pressure powered turbine engine to generate the power output and adjust an output current and/or an output voltage of the direct current generator,
wherein the air pressure powered turbine engine comprises an air intake adjusting valve, and the control unit is further configured to receive a power generation activation command from a CAN bus, the power generation activation command is configured to instruct the control unit to control the air intake adjusting valve to open or close and determine a generation mode of the system, including at least one of a current-constant generation mode, a voltage-constant generation mode, a power-constant generation mode, and a power-reduced generation mode.

US Pat. No. 10,797,626

MOTOR DRIVE CONTROL DEVICE AND CONTROL METHOD FOR MOTOR DRIVE CONTROL DEVICE

MINEBEA MITSUMI INC., Na...

1. A motor drive control device causing a single phase motor comprising a coil of a first system and a coil of a second system to be driven, the motor drive control device comprising:a first driving circuit configured to perform control to energize the coil of the first system;
a second driving circuit configured to perform control to energize the coil of the second system; and
a driving control unit configured to control an operation of the first driving circuit and an operation of the second driving circuit, wherein
the driving control unit comprises:
a driving voltage detecting unit configured to detect a driving voltage applied to the first driving circuit and a driving voltage applied to the second driving circuit; and
a compensation control unit configured to compare the driving voltage applied to the first driving circuit and the driving voltage applied to the second driving circuit, select one driving circuit between the first driving circuit and the second driving circuit based on the comparison result, and cause the selected driving circuit to execute a maintenance operation for maintaining rotation of the single phase motor.

US Pat. No. 10,797,625

DETECTION DEVICE AND DETECTION METHOD FOR DETECTING NUMBER OF REVOLUTIONS OF SENSORLESS EPB MOTOR

ERAE AMS CO., LTD., Daeg...

1. A device for detecting a number of revolutions of a sensorless motor for an electronic parking brake (EPB), the device comprising:an actuator driving motor used to set and release a parking brake of an EPB system;
an electronic control module for controlling the motor;
a vehicle battery for supplying power to the motor and the electronic control module; and
a main processing unit for receiving an output signal of the electronic control module and estimating the number of revolutions of the motor,
wherein an output signal of the motor corresponds to either a current or a voltage,
wherein the electronic control module further comprises a ripple measuring unit for receiving the output signal of the motor and measuring a ripple of the motor, and
wherein the ripple measuring unit includes:
a ripple signal selector for selecting only a ripple signal from the output signal of the motor;
a first level translator for receiving both the ripple signal selected by the ripple signal selector and a direct current signal of the battery and translating and combining the ripple signal and the direct current signal; and
a second level translator for receiving and translating the direct current signal of the battery.

US Pat. No. 10,797,624

ROTATION ANGLE CORRECTION DEVICE AND MOTOR CONTROL SYSTEM

RENESAS ELECTRONICS CORPO...

1. A rotation angle correction device for correcting an output rotation angle of a resolver digital converter that converts a signal output from a resolver attached to a motor, comprising:an arrival time measurement unit that measures an arrival time that is a time until the output rotation angle reaches a specified rotation angle from a reference angle in a current cycle;
a reference time calculation unit that calculates a reference time that is a time until the output rotation angle reaches the specified rotation angle from the reference angle assuming that the motor rotates in the current cycle at the same angular velocity as an angular velocity in a previous cycle;
a time difference calculation unit that calculates a time difference between the arrival time and the reference time;
an error angle calculation unit that multiplies the time difference and the angular velocity in the previous cycle to obtain an error angle; and
a correction unit that corrects the output rotation angle based on the error angle.

US Pat. No. 10,797,623

SEMICONDUCTOR DEVICE AND METHOD OF DETECTING ITS ROTATION ABNORMALITY

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a resolver rotation angle conversion circuit including:
a first tracking loop circuit that generates first rotation angle information for performing a control using a first proportional and integral processing to a rotation angle signal indicative of a rotation angle of a motor outputted by a resolver; and
a second tracking loop circuit that generates second rotation angle information for performing an abnormality detection using a second proportional and integral processing to the rotation angle signal, a gain of the second proportional and integral processing being higher than a gain of the first proportional and integral processing;
a motor rotation angle conversion circuit that generates rotation angle temporal change information by converting the second rotation angle information with respect to each phase of the motor to an angular change of the motor for one revolution; and
a determination circuit that determines a vibration frequency of the motor using a peak cycle of the rotation angle temporal change information, and determines that an abnormality occurred to the motor when the vibration frequency of the motor is different from a natural vibration frequency of the motor.

US Pat. No. 10,797,622

TRIGGER SWITCH

SATORI ELECTRIC CO., LTD....

7. A trigger switch, comprising:an actuator movable between an OFF position and a maximum position, the actuator being biased toward the OFF position, and movable toward the maximum position by operation of a user;
a pressure sensitive sensor for detecting applied pressing force;
a pressing member for pressing the pressure sensitive sensor; and
a compression spring intervening between the actuator and the pressing member,
wherein, when the actuator is located near the OFF position in comparison to a threshold position, the pressing member is linked to the actuator via the compression spring, and thereby presses the pressure sensitive sensor to apply force converted by the compression spring and corresponding to the position of the actuator, and
when the actuator is located at the threshold position, the pressing member abuts the actuator directly without intervention of the compression spring, and thereby presses the pressure sensitive sensor to apply pressing force applied to the actuator by the user.

US Pat. No. 10,797,621

METHOD FOR OPERATING A SYSTEM WITH DRIVES, WHICH ARE MECHANICALLY COUPLED TOGETHER, AND WITH A HIGHER-LEVEL COMPUTER, AND SYSTEM

14. A system, comprising:drives, that are mechanically coupled; and
a higher-level computer, connected to the drives via a data-bus connection, the higher-level computer including controllers, each controller being biuniquely allocated to a respective drive;
wherein the system is adapted to perform a method including:
determining, in each drive, a respective actual quantity value;
transmitting the respective actual quantity value to the higher-level computer via the data-bus connection;
determining, by the higher-level computer, for each drive, a setpoint quantity value allocated to the respective drive;
controlling, by the controller allocated to the respective drive, the actual quantity value of the respective drive to the setpoint quantity value of the respective drive, the controller determining as a control value a setpoint speed value allocated to the respective drive and transmitting the control value to the respective drive via the data-bus connection;
supplying, to an individual controller of the respective drive, the respective actual speed value of an electric motor of the drive, determined in the drive;
controlling, by the individual controller of the respective drive, the respective actual speed value to the respective setpoint-speed value transmitted by the higher-level computer to set a motor voltage and/or a motor current of the electric motor of the respective drive; and
wherein no master-slave control is performed or performable by the system.

US Pat. No. 10,797,620

ROTATING MACHINE CONTROL DEVICE AND ELECTRIC POWER STEERING CONTROL DEVICE

Mitsubishi Electric Corpo...

1. A control device for a rotating machine having a stator including a first winding set and a second winding set, the control device comprising:a relay for supplying or interrupting current from a DC power supply;
a capacitor for suppressing variation in current supplied from the DC power supply;
control command generator for generating a first control command that specifies current to flow through the first winding set, and a second control command that specifies current to flow through the second winding set;
voltage calculator for calculating a first voltage command from the first control command and calculating a second voltage command from the second control command;
first voltage energizer for applying voltage to the first winding set on the basis of the first voltage command; and
second voltage energizer for applying voltage to the second winding set on the basis of the second voltage command, wherein
electric discharge control for electric charge of the capacitor is performed while torque generated by current flowing from the capacitor to the first winding set and torque generated by current flowing from the capacitor to the second winding set are cancelled out with each other,
wherein the first control command and the second control command are a first current command and a second current command in a rotating two-axis coordinate system, respectively, and the first current command and the second current command have phases opposite to each other.

US Pat. No. 10,797,619

VORTEX FLUX GENERATOR

Silicon Turbine Systems, ...

1. A vortex flux generator comprising:a magnetic circuit configured to produce a magnetic field;
a quench controller configured to provide a variable current;
a vortex material configured to form and subsequently dissipate a vortex in response to the variable current thereby causing a modulation of the magnetic field;
an inductor disposed in a vicinity of the vortex such that the modulation of the magnetic field induces an electrical current in the inductor; and
a dissipation superconductor electrically disposed in parallel with the vortex material and configured to carry, without quenching, an entirety of the variable current during dissipation of the vortex in the vortex material.

US Pat. No. 10,797,618

VIBRATION-BASED ENERGY HARVESTER WITH STRAIN OPTIMISED TOPOLOGY

Cambridge Enterprise Limi...

1. An energy harvesting apparatus comprising:a frame;
a first member comprising a piezoelectric material, the first member fixed to the frame at a first position and at a second position, and extending between the first and second positions, the first member being configured to vibrate in a first direction;
a cantilever beam having a first end fixed to the first member between the first position and the second position and having a second end fixed to a proof mass, wherein the cantilever beam is coplanar with the first member and wherein the cantilever beam and the first member extend in a plane orthogonal to the first direction; and
an electrode fixed to the first member at a position between the first position and the second position.

US Pat. No. 10,797,617

ELECTROMECHANICAL TRANSDUCER

COMMONWEALTH SCIENTIFIC A...

1. A micro-electro-mechanical transducer, including:a plurality of first mechanical resonator structures having respective different first fundamental oscillation resonance frequencies;
a second mechanical resonator structure including one or more electromechanical transducer components, and having a second fundamental oscillation resonance frequency that is substantially greater than the first fundamental resonance frequencies of the first mechanical resonator structures; and
a plurality of variable capacitors associated with the first mechanical resonator structures and/or the second mechanical resonator structure;
wherein the spatial dimensions of the first and second mechanical resonator structures are less than 4 mm;
wherein oscillations of the first mechanical resonator structures driven by external mechanical vibrations cause the first mechanical resonator structures to intermittently couple with the second resonating structure to drive oscillations of the second resonating structure such that the electromechanical transducer components of the second mechanical resonator structure convert the oscillations of the second resonating structure to 1) electrical energy using the variable capacitors or 2) signals by electrostatic transduction using the variable capacitors;
wherein each of the first mechanical resonator structures includes one or more coupling members extending towards the second resonating structure such that oscillations of the first mechanical resonator structure cause the coupling members to intermittently press against the second resonating structure and thus drive the oscillations of the second resonating structure; and
wherein the second mechanical resonator structure includes a proof mass suspended by elongate beams such that the oscillations of the second mechanical resonator structure are in opposing directions that are orthogonal to the longitudinal axes of the elongate beams.

US Pat. No. 10,797,616

POWER ELECTRONIC CONVERTERS THAT TAKE PART IN THE GRID REGULATION WITHOUT AFFECTING THE DC-PORT OPERATION

1. A DC/AC power electronic converter system, comprisinga power electronic converter having a DC port, a storage port, and an AC port connected to a power source having a voltage and a current,
a PWM block that generates pulses to operate the power electronic converter,
a subtraction block that subtracts a first voltage signal from a second voltage signal to generate an input for the PWM block,
an inner-loop controller that generates the first voltage signal according to the voltage and current of the power source,
a power controller that generates the second voltage signal according to signals such as a real power set-point, a filtered storage voltage, a given rated storage voltage, and the voltage and current of the power source,
a storage voltage controller that generates the real power set-point for the power controller according to a filtered storage voltage, a given rated storage voltage, and the DC-port power.

US Pat. No. 10,797,615

UNCERTAINTY BASED CONTROLLER DESIGN FOR AN INVERTER

Mohit Chhabra, Wheeling,...

1. A control system for a power inverter, where the power inverter is configured to supply power to a load, and the control system for the power inverter comprising:a plurality of output voltage sensors (22), and plurality of output current sensors (23) configured to measure output AC voltages and output AC currents of the power inverter;
an input voltage sensor (13) and input current sensor (24), configured to measure input DC voltage and input DC current of the power inverter;
a controller coupled to the power inverter, and being configured to:
provide a control signal associated with a DC voltage reference (29), and a reactive power reference (30) to the power inverter;
determine a target amplitude and target frequency for the AC output voltage (22) and AC output current (23) of the power inverter;
apply a low pass filter (15, 16, 17,18) to the output power of the power inverter, where the low pass band of the filter is determined based on a target amplitude and a target frequency of the output voltage (22) and output current (23).

US Pat. No. 10,797,614

CURRENT REDUCTION SYSTEM FOR INVERTERS CONNECTED TO A COMMON BUS

GE Global Sourcing, Norw...

1. A system comprising:plural inverters connected to a common bus and at least one capacitor, each of the inverters configured to convert a direct current (DC) through the common bus to an alternating current (AC) by alternating switches of the inverter between open and closed states in a switching cycle having a switching frequency and a switching phase; and
a controller circuit configured to adjust the DC conducted onto the common bus to the inverters so that a root mean square of the AC that is output by the inverters meets one or more designated criteria, the controller circuit configured to adjust the DC by controlling at least one of the inverters to apply a frequency shift to the switching cycle of the at least one inverter such that the switching cycle of the at least one inverter having the frequency shift differs from the switching cycle of at least one other inverter and such that two or more of the inverters output the AC with different output frequencies.

US Pat. No. 10,797,613

POWER SUPPLY SYSTEM WITH ACTIVELY SWITCHED BUS CAPACITOR

Advanced Energy Industrie...

1. A power supply system comprising:a primary rectifier configured to rectify an AC voltage to produce a bus voltage on a DC bus;
a voltage monitor configured to monitor the AC voltage;
a capacitor switchably coupled to the DC bus via a switch, wherein a series combination of the switch and capacitor are coupled across outputs of the primary rectifier;
a charger configured to charge the capacitor with power from the DC bus;
a switch controller configured to close, in response to the voltage monitor indicating a sag in at least one phase of the AC voltage, the switch to enable the capacitor to discharge to the DC bus.

US Pat. No. 10,797,612

POWER DISTRIBUTION NETWORK

GE Aviation Systems LLC, ...

1. A power distribution system comprising:a first set of power converters arranged conductively connected in series to define a power converter series, with each of the first set of power converters having a respective set of individual power inputs and having a respective set of individual power outputs;
an overall power input conductively connected to the set of individual power inputs: and
at least one controller module communicatively connected with the first set of power converters and configured to controllably adjust the power conversion of the first set of power converters such that each of the first set of power converters are limited to a predetermined amount of power;
a set of power sources arranged in series to define a power source series connected with the first set of power converters;
wherein the set of power sources are low voltage power sources;
a second set of power converters adapted to convert low voltage power from the set of power sources respectfully connected with each of the first set of power converters, to a high voltage power supplied to the first set of power converters.

US Pat. No. 10,797,611

DIAGNOSTICS FOR MULTI-LEVEL MEDIUM VOLTAGE DRIVE USING MECHANICAL BYPASS

SIEMENS AKTIENGESELLSCHAF...

1. A closed-loop system for monitoring and verifying a bypass condition of a power cell, the system comprising:a power cell comprising:
a first output terminal and a second output terminal, and
a first communication interface positioned at the power cell; and
a bypass mechanism operably connected to the first output terminal and the second output terminal and configured to create a shunt path between the first output terminal and the second output terminal, the bypass mechanism comprising a second communication interface positioned at the bypass mechanism and configured to establish a communication link to the first communication interface and to transmit a bypass signal to the first communication interface in response to a change in state of the bypass mechanism,
wherein the bypass mechanism is further adapted to change its state in response to an input voltage received from a controller and to send an output to the controller indicating that the bypass mechanism has changed its state,
wherein the power cell is adapted to transmit a signal to the controller, wherein the signal indicates that the power cell has detected the state in change of the bypass mechanism based on the bypass signal,
wherein both the bypass mechanism and the power cell report to the controller regarding the change in state thus resulting in a closed-loop system including the controller, the bypass mechanism and the power cell.

US Pat. No. 10,797,610

ADAPTIVE SYNCHRONOUS RECTIFIER SENSING DEGLITCH

DIALOG SEMICONDUCTOR INC....

1. A method for controlling a synchronous rectification (SR) switch on a secondary side of a flyback converter, comprising:during a first part of a power switch cycle, monitoring an unfiltered SR switch signal to control whether the SR switch is turned on; and
during a remaining second part of the power switch cycle, monitoring a filtered SR switch signal to control whether the SR switch is turned on.

US Pat. No. 10,797,609

SYSTEMS AND METHODS FOR TRANSFERRING POWER ACROSS AN ISOLATION BARRIER USING AN ACTIVE SELF SYNCHRONIZED RECTIFIER

Analog Devices Internatio...

1. A circuit for transferring power across an isolation barrier, the circuit comprising:a first DC output terminal;
a second DC output terminal; and
a rectifier comprising:
an isolation component having a first terminal and a second terminal;
a first active device coupled between the first terminal of the isolation component and the first DC output terminal;
a second active device coupled between the second terminal of the isolation component and the first DC output terminal;
a third active device coupled between the first terminal of the isolation component and the second DC output terminal;
a fourth active device coupled between the second terminal of the isolation component and the second DC output terminal;
a first inductor coupled between the first and second active devices and the first DC output terminal; and
a second inductor coupled between the third and fourth active devices and the second DC output terminal.

US Pat. No. 10,797,608

FLYBACK CONVERTER WITH EDGE-BASED ISOLATED COMMUNICATION

DIALOG SEMICONDUCTOR INC....

1. A receiver for a flyback converter, comprising;a synchronous rectifier switch transistor coupled to a secondary winding of a transformer for the flyback converter;
a buffer for buffering an input signal to form a first voltage signal;
an inverter for inverting the input signal to form a complement of the first voltage signal;
a comparator having a first input and a second input;
a first resistor and a second resistor connected in series between the first input and the second input;
a first capacitor connected to the first resistor to form a first high-pass filter configured to high-pass filter the first voltage signal to form a first filtered signal; and
a second capacitor connected to the second resistor to form a second high-pass filter configured to high-pass filter the complement of the first voltage signal to form a second filtered signal; wherein the comparator is configured to assert a receiver signal responsive to a difference between the first filtered signal and the second filtered signal exceeding a positive threshold voltage and configured to ground the receiver signal responsive to the difference being less than a negative threshold voltage, and wherein the receiver is further configured to control a switching of the synchronous rectifier switch transistor responsive to the receiver signal.

US Pat. No. 10,797,607

HYBRID SWITCHED-CAPACITOR CONVERTER

Infineon Technologies Aus...

1. An apparatus comprising:a switched-capacitor converter operative to produce a first voltage, the switched-capacitor converter including multiple capacitors, each of the multiple capacitors switched between being coupled to an input voltage and being coupled to a reference voltage;
a transformer including a primary winding, the multiple capacitors controllably switched in a circuit path including the primary winding to convert the first voltage into a second voltage; and
a voltage converter coupled to a secondary winding of the transformer, the voltage converter operative to convert the second voltage into an output voltage;
wherein the multiple capacitors include a first capacitor and a second capacitor;
wherein a combination of the first capacitor, the second capacitor, and the primary winding are coupled in series, the apparatus further comprising:
a controller operative to switch between: i) a first mode in which a node of the first capacitor is coupled to the input voltage while a node of the second capacitor is coupled to the reference voltage, and ii) a second mode in which the node of the first capacitor is coupled to the reference voltage while the node of the second capacitor is coupled to the input voltage.

US Pat. No. 10,797,606

CONTROLLER WITH LIMIT CONTROL TO CHANGE SWITCHING PERIOD OR SWITCHING FREQUENCY OF POWER CONVERTER AND METHODS THEREOF

Power Integrations, Inc.,...

1. A controller for use in a power converter, comprising:a control loop clock generator configured to generate a switching frequency signal in response to a load signal and a limit signal, wherein the switching frequency signal is responsive to an output load of the power converter and the limit signal is representative of a maximum length of a current half cycle of the switching frequency signal;
a limit control configured to generate the limit signal in response to the switching frequency signal, wherein a rate of change between consecutive half cycles of the switching frequency signal is controlled in response to the limit signal to prevent a length of the current half cycle from exceeding the maximum length; and
a request transmitter circuit configured to generate a request signal in response to the switching frequency signal to control switching of a switching circuit coupled to an energy transfer element and an input of the power converter.

US Pat. No. 10,797,605

RESONANT SWITCHING CONVERTER

Silergy Semiconductor Tec...

1. A resonant switching converter, comprising:a) a multi-level generating circuit configured to generate a first voltage signal having at least two values, wherein said first voltage signal is zero in a first time interval, and is not zero and not greater than an input voltage of said resonant switching converter in a second time interval;
b) a resonant tank configured to multiplex at least two power transistors in said multi-level generating circuit, and to receive said first voltage signal to achieve resonant control; and
c) said multi-level generating circuit being configured to control said first voltage signal in accordance with said input voltage, wherein a ratio of said first voltage signal to said input voltage is relatively large in said second time interval when said input voltage is relatively small, and said ratio of said first voltage signal to said input voltage in said second time interval is relatively small when said input voltage is relatively large.

US Pat. No. 10,797,604

LLC RESONANT CONVERTER

ASIAN POWER DEVICES INC.,...

1. An LLC resonant converter, comprising:a switch module connected between an input voltage and a ground;
a transformer having a primary side winding and at least one secondary side winding;
an output circuit connected between the at least one secondary side winding and a load;
a resonant circuit coupled between the primary side winding and the switch module and comprising at least one leakage inductor, a first resonant capacitor, and a resonant inductor, with the at least one leakage inductor connected to the safety capacitor and a first end of the primary side winding, the first resonant capacitor connected to the switch module and a second end of the primary side winding, and the resonant inductor straddlingly connected to the first end and the second end of the primary side winding; and
the safety capacitor connected between the at least one leakage inductor and the switch module, wherein the at least one leakage inductor has a first terminal connected to the primary side winding and a second terminal connected to the switch module through only a first voltage transmission path having the safety capacitor;
wherein the safety capacitor enables isolation of the first voltage transmission path with respect to the leakage inductor and the first resonant capacitor enables isolation of a second voltage transmission path with respect to the second end of the primary side winding in order to isolate the primary side winding and the at least one secondary side winding from each other.

US Pat. No. 10,797,603

METHOD AND APPARATUS FOR CONTROLLING A FLYBACK CONVERTER

Delta Electronics (Shangh...

1. A method for controlling a flyback converter, the flyback converter including a main switch, a transformer and an auxiliary switch, the method comprising:obtaining a first voltage signal and a second voltage signal, the first voltage signal representing an input voltage of the flyback converter, and the second voltage signal representing an output voltage of the flyback converter;
controlling turn-on of the auxiliary switch, wherein a turn-on time period of the auxiliary switch is determined according to the first voltage signal and the second voltage signal; and
turning on the main switch at zero voltage switching condition, wherein the main switch is turned on at a time delayed for a duration of a dead time after turning off of the auxiliary switch, wherein the dead time is constant.

US Pat. No. 10,797,602

CONTROLLER WITH VARIABLE SAMPLING GENERATOR

Power Integrations, Inc.,...

1. A controller for use in a power converter, comprising:a comparator configured to compare a sense signal representative of an amount of energy delivered to an output of the power converter, to a target value;
an update clock generator configured to receive the sense signal and to generate a clock signal having a clock frequency in response to the sense signal; and
a request control coupled to the comparator and to the update clock generator, the request control configured to generate a request signal having a request frequency that is responsive to an output of the comparator and that controls an operational state of a power switch of the power converter, the request control further configured to update a rate at which the request frequency of the request signal is responsive to the clock frequency of the clock signal.

US Pat. No. 10,797,601

CURRENT PULSE GENERATOR WITH INTEGRATED BUS BOOST CIRCUIT

Efficient Power Conversio...

1. A current pulse generator integrated circuit, comprising:a boost circuit connected to a boost input terminal and a boost output terminal of the integrated circuit, wherein the boost circuit comprises:
a first gate driver circuit having an input for receiving a boost control signal; and
a first field effect transistor (FET) having a gate terminal connected to an output of the first gate driver circuit, a drain terminal, and a source terminal connected to ground;
a synchronous rectifier connected to the boost input terminal of the integrated circuit and to the drain terminal of the first FET; and
a load driver circuit connected to a load driver terminal of the integrated circuit, wherein the load driver circuit comprises:
a second gate driver circuit having an input for receiving a load driver control signal; and
a second FET having a gate terminal connected to an output of the second gate driver circuit, a drain terminal connected to the load driver terminal of the integrated circuit, and a source terminal connected to ground;
wherein the synchronous rectifier comprises a third FET having a gate terminal connected to a boost control voltage, a source terminal connected to the boost input terminal of the integrated circuit, and a drain terminal connected to the boost output terminal of the integrated circuit and to the drain terminal of the first FET, and
wherein both the boost circuit and the load driver circuit are monolithically integrated together on a single semiconductor die to form the integrated circuit.

US Pat. No. 10,797,600

POWER SUPPLY APPARATUS, MICROBIAL FUEL CELL VOLTAGE BOOSTING CIRCUIT AND MICROBIAL FUEL CELL VOLTAGE BOOSTING SYSTEM

Asahi Kasei Microdevices ...

1. A power supply apparatus comprising:an inductor connected to an input terminal to which input voltage is applied;
a first switch connected between a point between the inductor and an output terminal, and a ground terminal;
a drive unit that operates the first switch using a signal having amplitude corresponding to the input voltage; and
a control unit that has a first hysteresis comparator that, for controlling operation of the first switch, detects an output voltage to be output at the output terminal, and a second hysteresis comparator that, for controlling outputting of the output voltage, detects the output voltage to be output at the output terminal, wherein
a first voltage threshold is an upper threshold of the first hysteresis comparator, a second voltage threshold is a lower threshold of the first hysteresis comparator, a third voltage threshold is an upper threshold of the second hysteresis comparator, a fourth voltage threshold is a lower threshold of the second hysteresis comparator,
the control unit stops operation of the first switch upon detection at the first hysteresis comparator that the output voltage is equal to or higher than the first voltage threshold, and thereafter starts operation of the first switch upon detection at the first hysteresis comparator that the output voltage is equal to or lower than the second voltage threshold,
a second switch between the inductor and the output terminal, wherein the control unit turns on the second switch and causes outputting of the output voltage to be started upon detection at the second hysteresis comparator that the output voltage is equal to or higher than the third voltage threshold, and thereafter turns off the second switch and causes outputting of the output voltage to be stopped upon detection at the second hysteresis comparator that the output voltage is equal to or lower than the fourth voltage threshold, and
the second voltage threshold is greater than the third voltage threshold.

US Pat. No. 10,797,599

METHOD FOR REGULATING OUTPUT CHARACTERISTICS OF PHOTOVOLTAIC MODULE AND DIRECT CURRENT/DIRECT CURRENT CONVERTER

SUNGROW POWER SUPPLY CO.,...

1. A method for regulating output characteristics of a photovoltaic module, the method being applied to a direct current/direct current (DC/DC) converter connected with the photovoltaic module, and the method comprising:determining whether an output voltage of the DC/DC converter detected in a real-time manner is greater than a first preset voltage threshold;
controlling an output current of the DC/DC converter to be greater than a first preset current threshold and less than zero or controlling an output power of the DC/DC converter to be greater than a first preset power threshold and less than zero, in a case that the output voltage is greater than the first preset voltage threshold;
determining whether the output voltage detected in a real-time manner is less than a third preset voltage threshold, wherein the third preset voltage threshold is less than the first preset voltage threshold; and
controlling the output current to be greater than zero or controlling the output power to be greater than zero, in a case that the output voltage is less than the third preset voltage threshold.

US Pat. No. 10,797,598

CALIBRATED RIPPLE INJECTION-BASED CONSTANT ON-TIME BUCK CONVERTER WITH PRE-BIAS STARTUP IN CONTINUOUS CONDUCTION MODE

Microchip Technology Inco...

1. A constant on-time controller for a buck converter, the controller comprising:a pulse width modulator (PWM) comparator that generates an on-time request;
an error amplifier that regulates an average feedback voltage to an internal reference voltage, and passes a feedback node ripple signal to an input of the PWM comparator;
an on-time generator that outputs an on-time signal that controls an on-time of the buck converter based on the on-time request;
a MOSFET driver that drives the buck converter based on the output of the on-time generator; and
an injection signal generator coupled to said on-time generator, said injection signal generator comprising a first switch and a second switch, a fixed signal generator, and a bias current source;
wherein said first switch is coupled to said second switch;
wherein said first and second switches are coupled to said fixed signal generator, and to an output of the injection signal generator;
wherein said bias current source is coupled between said first and second switches and said output of said injection signal generator; and
wherein the error amplifier receives a feedback voltage based on the output of the injection signal generator.

US Pat. No. 10,797,597

TRANSIENT ENHANCING CIRCUIT AND CONSTANT-ON-TIME CONVERTER USING THE SAME

ELITE SEMICONDUCTOR MEMOR...

1. A transient enhancing circuit for a constant-on-time converter, the constant-on-time converter comprising an error amplifier and a comparator, the transient enhancing circuit comprising:a first sample-and-hold circuit having an input terminal and an output terminal, wherein the input terminal of the first sample-and-hold circuit is coupled to an output terminal of the error amplifier, and the output terminal of the first sample-and-hold circuit is coupled to a first input terminal of the comparator;
a zero-current detection circuit coupled to the first sample-and-hold circuit,
wherein the zero-current detection circuit is arranged for outputting a control signal when current flowing through a load coupled to the constant-on-time converter is detected to be zero;
a second sample-and-hold circuit having an input terminal and an output terminal, wherein the input terminal of the second sample-and-hold circuit is coupled to the output terminal of the first sample-and-hold circuit, and the output terminal of the second sample-and-hold circuit is coupled to the first input terminal of the comparator; and
a clamping circuit having a first terminal and the second terminal, wherein the first terminal of the clamping circuit is coupled to the output terminal of the second sample-and-hold circuit and the second terminal of the clamping circuit is coupled to the ground,
wherein the zero-current detection circuit is coupled to second sample-and-hold circuit.

US Pat. No. 10,797,596

TRANSIENT BOOSTER FOR ZERO STATIC LOADLINE SWITCHING REGULATOR

Apple Inc., Cupertino, C...

1. A switching regulator comprising:an input configured to receive an input DC voltage;
an output configured to deliver a regulated output voltage to a load;
a switching stage coupled between the input and the output; and
a control circuit configured to operate the switching stage to produce the regulated output voltage from the input DC voltage, wherein the control circuit comprises:
a control loop configured to receive a feedback signal corresponding to a load on the regulator and a reference signal and to generate an error signal from a comparison of the first feedback signal to the reference signal;
a controller configured to receive the error signal and operate the switching stage responsive thereto; and
a transient response circuit configured to boost the error signal responsive to a load transient, wherein the transient response circuit is configured to boost the error signal to a predetermined intermediate value between its saturation level and its full scale level.

US Pat. No. 10,797,595

POWER SUPPLY AND CONTROL METHOD FOR POWER SUPPLY

FDK CORPORATION, Tokyo (...

1. A power supply comprising:a first switching element that switches a current inputted from an input terminal;
a second switching element that switches between a ground potential and an output of the first switching element;
an inductance element that connects between an output terminal and the output of the first switching element and includes a detection terminal;
a current detection circuit that outputs a voltage value based on a current flowing through the inductance element, the current detection circuit being connected to an output terminal end of the inductance element and to the detection terminal; and
a control circuit that:
controls a first control terminal of the first switching element and a second control terminal of the second switching element;
converts the voltage value into a digital value when the voltage value reaches a peak;
calculates a peak value of the current based on the digital value and a first resistance of an equivalent series resistance of the inductance element between the output terminal end and the detection terminal; and
calculates an output current flowing to a load connected to the power supply based on the peak value.

US Pat. No. 10,797,594

SHARED COMPARATOR FOR CHARGE PUMPS

pSemi Corporation, San D...

1. A power converter circuit including:(a) at least one set of N series switches where N?2, each set configured as one of M charge pump legs where M?1, wherein each pair of adjacent series switches in each charge pump leg defines a stack-node VCXM located between the adjacent series switches, where N?1?X>1;
(b) at least one voltage scaling circuit, each coupled to a corresponding stack-node VCXM and configured to output a voltage proportional to a voltage at the corresponding stack-node VCXM;
(c) at least one multiplexor, each having (1) at least one input, each input coupled to the output of a corresponding one of the at least one voltage scaling circuit, and (2) at least one output; and
(d) at least one comparator circuit, each having a first input coupled to a corresponding output of one of the at least one multiplexor, and a second input coupled to a reference signal, and configured to output a signal indicative of a difference between a selected input to the multiplexor and the reference signal;
wherein the number of comparator circuits is less than (N?1)×M.

US Pat. No. 10,797,593

KAPPA SWITCHING DC-DC CONVERTER WITH CONTINUOUS INPUT AND OUTPUT CURRENTS

Analog Devices Internatio...

1. A bidirectional switching power converter system that is operable in a first mode in which a power signal flows in a power signal path from a first node to a second node to provide a stepped-down power signal at the second node, and the power converter system is operable in a second mode in which a different power signal flows in the power signal path from the second node to the first node to provide a stepped-up power signal at the first node, the power converter system comprising:a switching circuit coupled to the second node;
a capacitor provided in parallel with the switching circuit;
a first inductor coupled between a first terminal of the capacitor and the first node;
a second inductor coupled between a second terminal of the capacitor and a reference node; and
a control circuit configured to provide switch control signals to respective switches in the switching circuit to configure the converter system to operate in the first mode or the second mode.

US Pat. No. 10,797,592

POWER SYSTEM BASED ON CURRENT SOURCE

Raytheon Company, Waltha...

1. A power branching unit comprising:an input configured to receive a regulated current;
an output configured to provide the regulated current; and
multiple converter groups coupled between the input and the output, each converter group comprising:
multiple direct current/direct current (DC/DC) converters;
multiple protection devices each configured to selectively prevent one of the DC/DC converters from receiving the regulated current; and
an active clamp configured to (i) temporarily sink a portion of the regulated current in response to one of the DC/DC converters failing and (ii) selectively shunt the regulated current around all of the DC/DC converters in response to all of the DC/DC converters failing.

US Pat. No. 10,797,591

POWER CONTROLLERS WITH FREQUENCY JITTERING, AND CONTROL METHODS THEREOF

LEADTREND TECHNOLOGY CORP...

1. A power controller for use of a power converter with an inductive device, wherein the power converter provides an output power source, the power controller comprising:a PWM signal generator controlling a power switch to generate consecutive switching cycles, wherein in each switching cycle the PWM signal generator controls a peak to regulate the output power source, and the peak is capable of representing a current flowing through the inductive device; and
a jitter inducer connected to the PWM signal generator, for altering the peak, so as to make a difference between two consecutive peaks, wherein the difference has a sign and a magnitude, and the jitter inducer makes the sign changed switching cycle by switching cycle.

US Pat. No. 10,797,590

SYSTEMS AND METHODS FOR REDUCING ELECTROMAGNETIC INTERFERENCE USING SWITCHING FREQUENCY JITTERING

On-Bright Electronics (Sh...

1. A system for regulating a power converter, the system comprising:a comparator configured to receive a first input signal and a second input signal and generate a comparison signal based on at least information associated with the first input signal and the second input signal, the first input signal being associated with at least a feedback signal related to an output voltage of a power converter, the second input signal being associated with at least a first current flowing through a primary winding of the power converter;
a signal combiner configured to combine a current-jittering signal and a third input signal to generate the second input signal, the current-jittering signal being a different signal from the third input signal; and
a signal generator configured to receive the comparison signal and output a drive signal to a switch based on at least information associated with the comparison signal, the drive signal being associated with a switching frequency related to the power converter including the switch;
wherein the comparator and the signal generator are configured to, in response to at least the current jittering signal,
change a peak value of the first current within a first predetermined range to generate a disturbance to the peak value of the first current based at least in part on an amplitude of the current-jittering signal; and
change the switching frequency of the power converter within a second predetermined range based at least in part on the current-jittering signal; wherein:
the disturbance to the peak value of the first current = a constant × the amplitude of the current-jittering signal.

US Pat. No. 10,797,589

METHODS AND APPARATUS TO COMPENSATE FOR POWER FACTOR LOSS USING A PHASOR CANCELLATION BASED COMPENSATION SCHEME

TEXAS INSTRUMENTS INCORPO...

1. A power factor correction (PFC) controller circuit for a power converter, the PFC controller circuit comprising:a phase locked loop phase angle determiner to determine a first phase angle of an input voltage of the power converter;
a compensating current determiner to determine, based on the first phase angle, a compensating current to compensate for a capacitive current introduced by at least one filter capacitor of the power converter;
a switch controller to cause a controlled current drawn by a power stage of the power converter to be adjusted based on the compensating current to reduce a phase offset between the first phase angle of the input voltage and a second phase angle of an input current drawn at an input of the power converter; and
a load adjustment determiner to determine a tracking error current, the tracking error current to compensate for changes in an amount of current drawn by a load supplied by the power converter, and the switch controller further to cause the controlled current to be further adjusted by the tracking error current.

US Pat. No. 10,797,588

CONVERTER CONTROL SYSTEM

Toyota Jidosha Kabushiki ...

1. A converter control system comprising:a first step-up converter configured to be driven in accordance with a first PWM driving signal;
a second step-up converter configured to be driven in accordance with a second PWM driving signal;
a first electronic control unit configured to generate the first PWM driving signal based on a first duty ratio and a first carrier based on a carrier command; and
a second electronic control unit configured to generate the second PWM driving signal based on a second duty ratio and a second carrier based on the carrier command, the second carrier being asynchronous in phase with the first carrier, the second electronic control unit including a monitoring correction device, the monitoring correction device being configured to execute a synchronization monitoring process, the synchronization monitoring process being a process of determining whether the first carrier and the second carrier are synchronous with each other based on the first PWM driving signal, the first duty ratio, and the second carrier, the monitoring correction device being configured to, when it is determined that the first carrier and the second carrier are not synchronous with each other, execute a shutdown process and a first restart process, the shutdown process being a process of shutting down the second step-up converter, the first restart process being a process of restarting generation of the second PWM driving signal with the second carrier synchronous with the first carrier with the use of the first PWM driving signal and the first duty ratio.

US Pat. No. 10,797,587

POWER CONVERTER WITH SNUBBER CIRCUIT

HAMILTON SUNSTRAND CORPOR...

1. A power converter comprising:power conversion circuitry including:
a converter coil,
a power source, and
a switch connected to the converter coil to control current flowing through the converter coil from the power source, the power conversion circuitry including a converter output connectable to a converter load; and
parallel snubber circuitry having resonant circuitry connected in parallel with the converter coil, the resonant circuitry including a parallel snubber circuitry coil and a capacitor connected in series, the parallel snubber circuitry including a parallel snubber output connectable to a parallel snubber circuitry load, and
wherein the power converter further comprises series snubber circuitry associated with the converter coil including a series inductor disposed in series with the converter coil and the capacitor with respect to the power source, and a series snubber diode disposed between the parallel and converter coil.

US Pat. No. 10,797,586

POWER MODULE BASED ON NORMALLY-ON SEMICONDUCTOR SWITCHES

ABB Schweiz AG, Baden (C...

1. A power module, comprising:a plurality of normally-on semiconductor switches based on a wide bandgap substrate, the normally-on semiconductor switches connected in parallel;
a balancing unit comprising a capacitor and a balancing semiconductor switch connected in series, which are connected in parallel to the normally-on semiconductor switches;
a controller adapted for providing a gate signal for the normally-on semiconductor switches and for providing a gate signal for the balancing semiconductor switch;
wherein the controller is adapted for turning the normally-on semiconductor switches on and off with a given switching frequency;
wherein the controller is adapted for turning off the balancing semiconductor switch, when the normally-on semiconductor switches are turned on and for turning on the balancing semiconductor switch, when the normally-on semiconductor switches are turned off.

US Pat. No. 10,797,585

MULTI-PHASE CONTROL FOR PULSE WIDTH MODULATION POWER CONVERTERS

SEMICONDUCTOR COMPONENTS ...

1. A Pulse Width Modulation (PWM) controller for controlling a plurality of phases, the PWM controller comprising:a phase sequencer circuit to determine a selected phase of the plurality of phases;
a common ramp generation circuit to generate a common ramp signal;
a CSR signal multiplexer circuit to select a current sense signal of the selected phase from a plurality of current sense signals respectively corresponding to respective currents of the plurality of phases;
a summing circuit to generate, using the common ramp signal and the current sense signal selected by the CSR signal multiplexer circuit, a comparison threshold signal; and
a phase activation circuit to determine, using the comparison threshold signal, to turn on a PWM signal of the selected phase;
wherein the common ramp generation circuit sets a value of the common ramp signal to a predetermined reset value in response to a PWM signal of the plurality of phases being turned on, and decreases or increases the value of the common ramp signal at a controlled rate otherwise.

US Pat. No. 10,797,584

ACTIVE FILTER DEVICE, AIR CONDITIONING DEVICE, AND AIR CONDITIONING SYSTEM

DAIKIN INDUSTRIES, LTD., ...

1. An active filter device connected to a power converter to be supplied with electric power via a distribution board, the active filter device comprising:a current source having an output connected to a power receiving path of the power converter, the current source being capable of generating a first current compensation portion for either or both reducing a harmonic current in the power converter or improving a fundamental power factor in the power converter;
a first detector detecting a first current flowing in the power receiving path of the power converter; and
a second detector detecting a second current flowing in a power receiving path of the distribution board,
a controller calculating the first current compensation portion based on the first current value detected by the first detector, calculating, based on the second current value detected by the second detector, a second current compensation portion for either or both reducing a harmonic current in the power receiving path of the distribution board or improving a fundamental power factor in the power receiving path of the distribution board, and allowing the current source to generate an output current obtained through superimposition of the second current compensation portion and the first current compensation portion.

US Pat. No. 10,797,583

SECONDARY WINDING SENSE FOR HARD SWITCH DETECTION

Power Integrations, Inc.,...

1. A controller configured for use in a power converter, the controller comprising:a control loop clock generator configured to generate a switching frequency signal in response to a sense signal representative of a characteristic of the power converter, the control loop clock generator further coupled to receive a load signal that is responsive to an output load of the power converter, the control loop clock generator further configured to terminate a switching of a half line cycle in response to a hard switch sense output;
a hard switch sense circuit configured to generate the hard switch sense output in response to the switching frequency signal and a rectifier conduction signal representative of a polarity of an energy transfer element of the power converter, to determine if power converter switching losses occur due to hard switching; and
a request transmitter circuit configured to generate a request signal in response to the switching frequency signal to control switching of a switching circuit coupled to an input of the energy transfer element of the power converter, wherein the request signal terminates the half line cycle in response to the hard switch sense output.

US Pat. No. 10,797,582

CROSS CONDUCTION PROTECTION IN A VOLTAGE CONVERTER

Infineon Technologies Aus...

1. An apparatus comprising:a voltage converter including a primary winding coupled to a secondary winding, the secondary winding configured to receive energy from the primary winding to produce an output voltage to power a load;
a first switch and a second switch configured to control current through the primary winding;
a controller configured to: i) via a feedback voltage signal indicating current through the primary winding, determine a flow of current through a body diode of the second switch, and ii) control subsequent activation of the first switch to an ON state based on the determined flow of current through the body diode of the second switch; and
wherein the feedback voltage signal transitions from a positive voltage value to a negative voltage value during a dead time in which both the first switch and the second switch are in an OFF state.

US Pat. No. 10,797,581

POWER SUPPLY SYSTEM FOR CONTROLLING A ZVS PARAMETER TO OPTIMIZE EFFICIENCY USING ARTIFICIAL INTELLIGENCE

SEMICONDUCTOR COMPONENTS ...

1. A power supply system comprising:a power stage including a power switch and an inductor;
a power supply controller connected to the power stage;
a metering circuit configured to sense measured conditions of the power stage; and
a system performance controller configured to be coupled to the power supply controller and the metering circuit, the system performance controller configured to compute an energy conversion efficiency based on the measured conditions and select a value for a zero voltage switching (ZVS) control parameter that results in the energy conversion efficiency achieving a threshold condition, the ZVS control parameter indicating a magnitude of a reverse current through the inductor to discharge a parasitic capacitance of the power switch.

US Pat. No. 10,797,580

DETECTION CIRCUIT, SWITCHING REGULATOR HAVING THE SAME AND CONTROL METHOD

ALPHA AND OMEGA SEMICONDU...

1. A detection circuit for detecting an inductor current flowing through an inductor, the inductor being coupled to a switch, the detection circuit comprising:a comparison circuit having a first node, the comparison circuit being configured to compare a conduction time of a diode of the switch with a time threshold to provide a first voltage at the first node; and
a signal generating circuit coupled to the first node, the signal generating circuit being configured to output a first detection signal according to the first voltage, the first detection signal indicating whether the inductor current flowing through the inductor reaches a first current threshold.

US Pat. No. 10,797,579

DUAL SUPPLY LOW-SIDE GATE DRIVER

TEXAS INSTRUMENTS INCORPO...

1. An automotive system, comprising:a first regulator configured to provide a first output voltage based on a first input voltage level;
a second regulator configured to provide a second output voltage based on a second input voltage level;
a first driver circuit coupled to the first regulator and a switch, wherein the first driver circuit is configured to drive the switch based on the first output voltage;
a second driver circuit coupled to the second regulator and the switch, wherein the second driver circuit is configured to drive the switch based on the second output voltage;
a driver controller coupled to the first driver circuit and the second driver circuit, wherein the driver controller is configured to select one of the first driver circuit and the second driver circuit to drive the switch based on a control signal;
a switch node coupled to the switch, wherein a switch node voltage at the switch node is a function of the switch being turned on and off; and
a load coupled to the switch node.

US Pat. No. 10,797,578

VERTICALLY MOUNTED AND MAGNETICALLY DRIVEN POWER GENERATION APPARATUS

12. A vertically mounted and magnetically driven power generation apparatus comprising:a support frame having:
a center axis vertically and centrally passing through the support frame;
multiple shelves vertically arranged and spaced apart from each other, each shelf having a through hole formed through the shelf and tapering downwards; and
multiple struts securely connected with the multiple shelves;
a transmission mechanism having:
a spindle vertically mounted through the support frame along the center axis; and
multiple magnetic driven members securely mounted around the spindle and located within the through holes of the respective shelves of the support frame;
multiple magnetic drive assemblies mounted on inner walls of the through holes of the respective shelves and located around the respective magnetic driven members of the transmission mechanism with a gap defined between each magnetic drive assembly and a corresponding magnetic driven member, wherein the transmission mechanism is vertically and suspendedly rotatable around the center axis by magnetic repulsion forces generated between the multiple magnetic drive assemblies and the respective magnetic driven members;
at least one power generator mounted in the support frame and connected with the spindle of the transmission mechanism; and
multiple magnetically stabilizing modules mounted in the support frame, each magnetically stabilizing module having:
a positioning board securely mounted to the multiple struts and having a center hole formed through the positioning board and aligned with the center axis;
a first permanent magnet ring annularly mounted on an inner wall of the center hole of the positioning board; and
an inner permanent magnet securely mounted to the spindle of the transmission mechanism, located within the first permanent magnet ring, and spaced apart from the first permanent magnet ring by gaps in a contactless manner by way of magnetic repulsion in a radial direction;
at least one motor, wherein each of the at least one motor includes:
a rotor securely mounted to the spindle of the transmission mechanism and having:
a flywheel body being disc-shaped, having an up-down symmetry, and including:
a top portion being disc-shaped and tapering upwards; and
a bottom portion formed on a bottom surface of the top portion, being disc-shaped, tapering downwards, and being symmetrical to the top portion according to an up-down symmetry; and
two permanent magnets respectively mounted on a top and a bottom of the flywheel body; and
two stators respectively located on a top end and a bottom end of the rotor, each stator having:
a winding-fixing board; and
a winding set mounted inside the winding-fixing board;
wherein the two permanent magnets of the rotor respectively mounted on the top end and the bottom end of the rotor are located within the winding sets of the respective stators.

US Pat. No. 10,797,577

PRIMARY ELEMENT OF AN IRONLESS LINEAR MOTOR

ETEL S.A., Motiers (CH)

1. A primary element of an ironless linear motor, the primary element comprising:cooling plates, each of the cooling plates being connected to a connecting piece extending in a region of an edge of the cooling plate, the connecting pieces being configured to supply coolant, the connecting pieces being located one above the other in a direction perpendicular to the cooling plates so as to form a common connecting region of the cooling plates at an end face of the primary element;
a plurality of coils disposed between the cooling plates; and
a coolant distribution header releasably attached to the connecting region,
wherein the connecting pieces each have a recess, which alone or together with an opposite recess of an oppositely-disposed one of the connecting pieces, has a depth sufficient to accommodate one of the cooling plates.

US Pat. No. 10,797,576

VIBRATION MOTOR

AAC Technologies Pte. Ltd...

1. A vibration motor comprising:a housing;
an elastic connecting piece;
a vibrating component, the vibrating component comprises a counterweight suspended in the housing by the elastic connecting piece;
a fixed component, the fixed component includes coils while the vibrating component includes a magnet, or the fixed component includes a magnet while the vibrating component includes coils;
a damping piece, the damping piece is directly fixed on a side of the counterweight and can be subjected to elastic deformation along the vibrating direction of the vibrating component;
wherein
the counterweight includes a restricting protrusion extending from the side of the counterweight for abutting against and restricting the damping piece.

US Pat. No. 10,797,575

VIBRATION GENERATOR HAVING SWING UNIT, FRAME AND ELASTIC MEMBER

MINEBEA MITSUMI INC., Ki...

1. A vibrator generator comprising:a top plate;
a bottom plate;
a frame including an annular shape, the frame covered by the top plate and by the bottom plate;
a swing unit including a plate shape;
a coil disposed at the bottom plate; and
an elastic member connecting the swing unit and the frame,
wherein:
the swing unit faces to the coil in a direction from the bottom plate to the top plate,
the swing unit includes a first weight and a second weight and a magnetic body arranged between the first weight and the second weight,
an outer circumferential surface of the first weight and an outer circumferential surface of the second weight are attached to an outer circumferential surface of the magnetic body in a swing direction of the swing unit,
the first weight and the second weight hold the magnetic body in the swing direction of the swing unit,
a whole of the first weight and a whole of the second weight are separated in the swing direction of the swing unit, and
the elastic member is joined to an outer circumferential surface of the first weight or an outer circumferential surface of the second weight.

US Pat. No. 10,797,574

ELECTRICAL MACHINE

ROLLS -ROYCE plc, London...

1. An electrical machine having:a stator with windings;
a first rotor rotatably fixed relative to a drive mechanism, the first rotor being radially inwards of the stator, the first rotor carrying alternating polarity first field magnets arranged in a circumferential direction of the first rotor,
wherein, on rotation of the drive mechanism, the windings interact with the magnetic flux produced by the first magnets to create an EMF across the windings;
a second rotor inwards of the stator, the second rotor carrying alternating polarity second field magnets arranged in a circumferential direction of the second rotor, the second rotor having a first rotational position relative to the first rotor in which the second magnets of the second rotor are aligned relative to the first magnets of the first rotor to reduce the magnetic flux energy of the combined magnets of the first and second rotors, the second rotor having a second rotational position relative to the first rotor in which the second magnets of the second rotor are aligned relative to the first magnets of the first rotor to increase the magnetic flux energy of the combined magnets of the first and second rotors, and the second rotor being freely rotatable relative to the drive mechanism, by a distance of at least between the first and second rotational positions; and
an electrical output regulator configured to regulate an electrical current drawn from the windings to produce a torque on the first and second rotors,
wherein, as the drive mechanism increases from zero rotational speed, the torque rises above a threshold level that moves the second rotor from the first rotational position to the second rotational position, and, as the drive mechanism further increases the rotational speed, the torque peaks and then drops below the threshold level to move the second rotor back to the first rotational position, and
wherein as the drive mechanism increases from zero or low rotational speed, the second rotor is in the first rotational position relative to the first rotor, the electrical output regulator is configured to operate a current controlled pulse width modulation mode that intermittently short circuits the windings for short periods at a pulse width modulation frequency until the torque rises above the threshold level.

US Pat. No. 10,797,573

AXIAL MOTOR/GENERATOR HAVING MULTIPLE INLINE STATORS AND ROTORS WITH STACKED/LAYERED PERMANENT MAGNETS, COILS, AND A CONTROLLER

POWER IT PERFECT, INC., ...

1. A system that is configured to operate as an electric motor or an electric generator, the system comprising:a housing;
a shaft; and
a plurality of slice assemblies disposed about the shaft, each of the slice assemblies comprising:
a rotor assembly, comprising:
a rotor plate coupled to the shaft, the rotor plate defining:
circumferentially distributed equidistant first openings formed through the rotor plate, each of the first openings having a first radial angle; and
circumferentially distributed equidistant first gaps circumferentially interposed between the first openings, each of the first gaps having a second radial angle;
and
a set of isolated permanent magnets distributed about the shaft and extending within the respective first openings formed through the rotor plate, each of the permanent magnets having a magnetization direction co-axial to the shaft, and a magnetic flux of each of the permanent magnets flowing in a direction opposite that in which a magnetic flux of a circumferentially adjacent one of the permanent magnets flows;
and
a stator assembly, comprising:
a stator plate coupled to the housing, the stator plate defining:
circumferentially distributed equidistant second openings formed through the stator plate, each of the second openings having a third radial angle; and
circumferentially distributed equidistant second gaps circumferentially interposed between the second openings, each of the second gaps having a fourth radial angle;
and
a set of isolated coil assemblies distributed about the shaft and extending within the respective second openings formed through the stator plate, each of the coil assemblies comprising one or more insulated conductive wires wound about a powdered metal core having insulated metal grains, the wound insulated conductive wires being normal to the magnetic flux of each of the permanent magnets of the rotor assembly when each of the permanent magnets is proximate the corresponding coil assembly, and at least one of the isolated coil assemblies being configurable to output electrical power while the shaft is rotating or to input electrical power to rotate the shaft;
wherein:
(i) the set of isolated permanent magnets of each of the slice assemblies is offset by a fifth radial angle about the shaft from the set of isolated permanent magnets of an axially adjacent one of the slice assemblies; and
the fifth radial angle is determined by multiplying a reciprocal of the total number of slice assemblies in the system by a sum of the first and second radial angles;
and/or
(ii) the set of isolated coil assemblies of each of the slice assemblies is offset by a sixth radial angle about the shaft from the set of isolated coil assemblies of an axially adjacent one of the slice assemblies; and
the sixth radial angle is determined by multiplying the reciprocal of the total number of slice assemblies in the system by a sum of the third and fourth radial angles.

US Pat. No. 10,797,572

METHOD FOR PRODUCING A WINDING OF A WINDING CARRIER OF AN ELECTRIC MACHINE

Vitesco Technologies GmbH...

1. A method for producing a winding of a winding carrier of an electric machine, the method comprising:providing a laminated sheet package, the laminated sheet package includes:
an axis,
at least one first slot, extending in a direction of the axis, for receiving at least one first winding segment for producing the winding, wherein the at least one first slot, when viewed in the direction of the axis, is disposed on a first circle, the axis running through a circle center of the first circle;
disposing the at least one first winding segment in the at least one first slot, wherein a first region of the at least one first winding segment protrudes from the laminated sheet package; and
bending the first region by exerting a first force, acting in the direction of the axis, and a frictional force, acting tangentially to the first circle, on the first region in a first direction tangential to the first circle;
wherein bending of the first region is performed by way of a first pressure unit having a first contact face that is configured as a doughnut-shaped face having a linear structure or a non-structured rough surface extending away from the axis, the first contact face contacting an exposed end portion of the first region creating the frictional force that pulls the exposed end portion in the first direction tangential to the first circle.

US Pat. No. 10,797,571

COIL MANUFACTURING DEVICE AND COIL MANUFACTURING METHOD

NITTOKU CO., LTD., Saita...

1. A coil manufacturing device for manufacturing a coil by rotating a winding core and winding a wire around the rotating winding core, the coil manufacturing device comprising:a recess formed in the winding core, the recess being configured to suspend the wire wound around the winding core in the recess; and
a wire bundling device configured to bundle the wire suspended in the recess,
wherein
the winding core includes:
a winding barrel having the wire wound therearound;
a fixed-side flange placed at one end of the winding barrel; and
a movable-side flange placed at another end of the winding barrel, and
the recess includes a cutout formed in a part of an outer periphery of the winding barrel, a cutout formed in a part of an outer periphery of the fixed-side flange, and a cutout formed in a part of an outer periphery of the movable-side flange, the cutouts being continuous in an axial direction.

US Pat. No. 10,797,570

ELECTRIC DRIVE DEVICE AND ELECTRIC POWER STEERING APPARATUS

Hitachi Automotive System...

1. An electric drive device comprising:a motor housing accommodating therein an electric motor that drives a mechanical control element; and
an electronic control unit provided at a side end wall side of the motor housing which is an opposite side to an output shaft portion of a rotation shaft of the electric motor and having a control circuit unit, a power supply circuit unit and a power conversion circuit unit that are configured to drive the electric motor, and wherein
at least a power-conversion-circuit heat releasing section is formed at the side end wall of the motor housing, the power conversion circuit unit is mounted on the power-conversion-circuit heat releasing section, and heat generated at the power conversion circuit unit is released to the motor housing through the power-conversion-circuit heat releasing section,
the power conversion circuit unit is defined by a rotation shaft-side line formed so as to face toward the rotation shaft of the electric motor, a control output terminal-side line formed so as to face toward three-phase coil input terminals of the electric motor and being parallel to the rotation shaft-side line and side lines connecting both end portions of the rotation shaft-side line and the control output terminal-side line, and the power conversion circuit unit is packaged with synthetic resin, and
three-phase control output terminals connected to the three-phase coil input terminals are formed at the control output terminal-side line, and power switching elements forming upper and lower arms for each phase are arranged in a zigzag formation along the control output terminal-side line with the power switching elements being offset from a substantially middle between the rotation shaft-side line and the control output terminal-side line toward the control output terminal-side line.

US Pat. No. 10,797,569

SEMICONDUCTOR DEVICE

DENSO CORPORATION, Kariy...

5. A semiconductor device comprising:a plurality of control modules to control a rotating electric machine, wherein:
the plurality of control modules are circularly arranged around a rotary shaft of the rotating electric machine;
each control module includes at least one switching element supplied with a current from a bus bar coupled to a power source; and
the at least one switching element in one of the control modules having a highest heat radiation efficiency under a structural condition of arrangement has a lower resistance than another switching element.

US Pat. No. 10,797,568

MOTOR UNIT AND VEHICLE

Honda Motor Co., Ltd., T...

1. A motor unit comprising:a drive motor that includes an output shaft having a hollow portion;
a torque sensor arranged within the hollow portion; and
a cooling mechanism that has one end of a coolant path arranged inside the hollow portion and cools the drive motor and the torque sensor,
wherein the cooling mechanism includes a pipe that is secured to a stator-side component of the drive motor, is arranged inside the output shaft, and allows a coolant to flow through the pipe, and
wherein the torque sensor is a magnetostrictive torque sensor that includes a plurality of magnetostrictive layers arranged on an inner circumferential surface of the output shaft, and a plurality of coils arranged in the pipe.

US Pat. No. 10,797,567

ROTOR ASSEMBLY INCLUDING A HOUSING FOR A SENSOR ARRAY COMPONENT AND METHODS FOR USING SAME

LIFE TECHNOLOGIES CORPORA...

1. A rotor assembly comprising:a rotor plate to rotate around a first axis;
a bucket rotatably attached to the rotor plate and to rotate around a second axis;
a stop plate to rotate around the first axis relative to the rotor plate between an open position and a closed position, when in the closed position, the stop plate is to engage the bucket to fix an angular position of the bucket relative to a plane of rotation of the rotor assembly; and
a housing for a sensor array component, the housing disposed in the bucket, the housing including a housing body defining:
a solution inlet and a solution outlet to engage ports of a flow cell of a sensor array, the housing body defining a flow path beginning at the solution outlet;
a transfer basin defined by the housing body and in the flow path;
a solution retainer defined by the housing body and disposed between the solution outlet and the transfer basin within the flow path; and
a collection reservoir defined by the housing body in fluid communication with the transfer basin within the flow path at an opposite end of the flow path from the solution retainer.

US Pat. No. 10,797,566

ELECTRIC DRIVE DEVICE AND ELECTRIC POWER STEERING DEVICE

HITACHI AUTOMOTIVE SYSTEM...

1. An electric drive device comprising:a motor housing structured to house an electric motor, wherein the motor housing includes an end face part including a through hole, wherein an end part of a rotating shaft of the electric motor opposite to an output part of the rotating shaft extends through the through hole, and wherein the electric motor is structured to drive a controlled object of a mechanical system;
an electronic control part housed in an accommodation space formed by a cover attached to the end face part of the motor housing, wherein the electronic control part is placed adjacent to the end face part, and configured to drive the electric motor, wherein the electronic control part includes a control circuit part, a power supply circuit part, and a power conversion circuit part; and
a watertight cover attached to a portion of the end face part of the motor housing around the through hole through which the rotating shaft extends, wherein the watertight cover covers the through hole and the end part of the rotating shaft from outside and has a watertight function;
wherein the watertight cover includes a waterproof breathable member structured to suppress passing of water and allow passing of air and water vapor.

US Pat. No. 10,797,565

MOTOR WITH INNER FAN

Hitachi Industrial Produc...

1. A motor with an inner fan, comprising:a rotor that rotates with a shaft;
a stator that opposes the outer peripheral surface of the rotor;
an end ring that is connected to the rotor;
stator wiring that is connected to the stator;
a fan that rotates with the shaft through a sleeve;
a fan guide that opposes a tip end of a blade outer periphery of the fan; and
a frame that stores the rotor, the stator, the fan, the fan guide, the end ring, and the stator wiring,
wherein the rotor includes an axial duct and a radial duct, the axial duct penetrating the rotor in the axial direction of the rotor, the radial duct communicating with the axial duct and penetrating the rotor radially from the inside to the outside of the rotor,
the fan is an inner fan that is arranged inside the frame, and the tip end of the blade outer periphery of the fan is exposed,
the inner fan is of a diagonal flow type, and
a discharge direction of the inner fan is an inward direction,
wherein the fan guide is of a double structure,
an outside diameter side of the fan guide is arranged along a tip end part of a blade outer periphery of the inner fan, and
an inside diameter side of the fan guide is arranged along an outside diameter side contour of the stator wiring.

US Pat. No. 10,797,564

ABOVE GROUND ENERGY RESOURCE DEVICE THAT UTILIZES A VEHICLE'S SPINNING TIRE, AND IS MADE SERVICEABLE BY UTILIZING MAGNETS, PINS AND BRAKES

1. An energy production system having an energy generating apparatus, and means for driving said apparatus comprising:an ingress ramp, a housing platform, a roller, and an exit ramp,
and said roller, which said roller is cylindrical in shape, is fitted inside said housing platform, supported by carrier bearings and knuckles in said housing platform, and in which said roller rolls when a vehicular tire interacts with a protruded surface of said roller, causing said roller to spin,
and such said spinning action of said roller causes a driven gear, attached to a shaft of said cylindrical roller, to turn and revolve,
and said driven gear turns a smaller radius receiving gear to increase the rotational speed of said receiving gear, and where both said receiving gear and said driven gear are supported and mated together in an overdrive transfer box,
and which said overdrive transfer box is provided bearings and knuckles in said overdrive transfer box as a support foundation for said driving gear and said receiving gear,
and where an output shaft is connected from said receiving gear to a universal joint, and which said universal joint is directly connected to an input shaft,
and where said input shaft is directly connected to a differential, which said differential changes the direction of the rotating energy of said cylindrical roller,
and where the output of said differential is directly connected to said driving gear of a time-gear set,
and where an output that rotates, of said time-gear set, is an input to a generator set, said generator set which has a regulated voltage output and frequency output of compatible wattage to an electrical distribution grid.

US Pat. No. 10,797,563

POWER GENERATING DEVICE

ADAMANT NAMIKI PRECISION ...

1. A power generating device comprising:a unit case,
a power generating motor fixed inside the unit case and having a motor input shaft and a gear attached to the motor input shaft,
a case side input shaft rotationally attached to the unit case and connected to the motor input shaft through the gear for transmitting rotational force of the case side input shaft to the gear,
a crown gear connected to the case side input shaft and meshing with the gear, the crown gear being arranged by cutting out the unit case,
covers attached to two side surfaces of the unit case and having bearings that rotatably support the case side input shaft projecting from the unit case, and
a guide case slidably retaining the unit case therein, and having a rack fixed to the guide case and meshing with the case side input shaft so that when the unit case slides inside the guide case, the power generating motor rotates and generates electricity.

US Pat. No. 10,797,562

HIGH TORQUE AND POWER DENSITY DRIVE SYSTEM WITH SHORTENED OVERALL WIDTH

Atieva, Inc., Newark, CA...

1. A powertrain assembly, comprising:an electric motor, said electric motor comprising:
a hollow rotor shaft; and
a rotor lamination stack containing a plurality of permanent magnets, wherein said rotor lamination stack encircles said hollow rotor shaft, and wherein said rotor lamination stack is attached directly to said hollow rotor shaft;
a differential gear assembly mounted within said hollow rotor shaft, wherein a first output shaft coupled to said differential gear assembly exits said hollow rotor shaft from a first end of said hollow rotor shaft, wherein a second output shaft coupled to said differential gear assembly exits said hollow rotor shaft from a second end of said hollow rotor shaft, and wherein said second end of said hollow rotor shaft is distal from said first end of said hollow rotor shaft;
a first planetary gear assembly coupled to said first output shaft, wherein said first planetary gear assembly is coaxially aligned with said hollow rotor shaft, said first planetary gear assembly comprising a first planetary gear carrier;
a first constant velocity (CV) joint component, said first CV joint component further comprising a first CV joint housing member, wherein said first planetary gear carrier is integral to said first CV joint component;
a second planetary gear assembly coupled to said second output shaft, wherein said second planetary gear assembly is coaxially aligned with said hollow rotor shaft, said second planetary gear assembly comprising a second planetary gear carrier; and
a second CV joint component, said second CV joint component further comprising a second CV joint housing member, wherein said second planetary gear carrier is integral to said second CV joint component.

US Pat. No. 10,797,561

BRUSHLESS WIPER MOTOR

Mitsuba Corporation, Kir...

1. A brushless wiper motor, the brushless wiper motor including a motor unit and a gear unit, the motor unit having a stator, a rotor inside the stator, and a rotation shaft whose one end side in an axial direction is fixed to an axial center of the rotor, the gear unit having a gear case connected to the motor unit and housing the other end side of the rotation shaft in the axial direction, and a gear cover sealing an opening of the gear case, the wiper apparatus comprising:a first bearing fixed onto the rotation shaft to a first side of a worm provided on the other end side of the rotation shaft in the axial direction;
a first bearing attaching portion provided in the gear case and fixing the first bearing;
a second bearing fixed onto the rotation shaft at a second side of the worm so as to be opposed to the first bearing;
a second bearing attaching portion provided in the gear case and fixing the second bearing;
a stopper member fixing the first bearing to the first bearing attaching portion from a side of the motor unit; and
a stopper member attaching portion provided in the gear case and fixing the stopper member by press-fitting from a direction crossing the axial direction of the rotation shaft,
wherein the first bearing is clamped between the first bearing attaching portion and the stopper member fixed to the stopper member attaching portion.