US Pat. No. 10,340,827

FAULT TOLERANT CURRENT MEASUREMENT IN MOTOR CONTROL SYSTEMS

STEERING SOLUTIONS IP HOL...

1. A system for determining a sensor failure in a motor control system with at least three phase current measurements, the system comprising:a current controller configured to generate an input voltage command for a motor using feedforward control;
a failed sensor identification module, in response to the current controller operating using the feedforward control, configured to:
determine that a current offset error is indicative of a failure of a current sensor, the current offset error determined based on a magnitude and a phase of a diagnostic current; and
determine that the current offset error is indicative of a multi-point failure based on a determination that the magnitude of the diagnostic current is above a first predetermined threshold, and that the current offset error is indicative of a single point failure based on a determination that the magnitude is between a second predetermined threshold and the first predetermined threshold.

US Pat. No. 10,340,823

METHOD OF DETERMINING THE ROTOR POSITION OF A PERMANENT-MAGNET MOTOR

Dyson Technology Limited,...

1. A method of determining the position of a rotor of a brushless permanent-magnet motor, the method comprising:exciting and freewheeling a phase winding of the motor, wherein the phase winding is freewheeled when a phase current exceeds an upper threshold and freewheeling comprises freewheeling until the phase current falls below a lower threshold;
measuring a first time interval between the start and end of freewheeling or the start and end of excitation, wherein the first time interval is measured using a controller, and wherein the first time interval begins when the phase current exceeds the upper threshold and ends when the phase current falls below the lower threshold;
using the measured first time interval to define a saturation threshold, wherein the saturation threshold is defined such that when the measured first time interval is less than the saturation threshold, the rotor is in a pre-determined position;
sequentially exciting and freewheeling the phase winding using the controller, wherein the controller outputs control signals to sequentially excite and freewheel the phase winding, wherein the phase winding is freewheeled when the phase current exceeds the upper threshold and freewheeling comprises freewheeling until the phase current falls below the lower threshold;
measuring a second time interval corresponding to the time interval between either the start and end of freewheeling or the start and end of excitation, wherein the second time interval is measured using the controller, and wherein the second time interval begins when the phase current exceeds the upper threshold and ends when the phase current falls below the lower threshold;
comparing the measured second time interval against the saturation threshold using the controller; and
determining, using the controller, that the rotor is at a predetermined position when the measured second time interval is less than the saturation threshold.

US Pat. No. 10,340,821

ROTOR FLUX ANGLE AND TORQUE TRAJECTORY CONTROL APPARATUS AND METHODS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (“IC”), comprising:a low speed estimator to generate a low speed estimate of a flux angle of a rotor (“LS_?_EST”) in a motor;
a high speed estimator to generate a high speed estimate of the rotor flux angle (“HS_?_EST”) in the motor; and
an acceleration control logic module coupled to the low speed estimator and to the high speed estimator and configured to:
track a low speed estimate of an angular velocity of the rotor (“LS_?_EST”) relative to a low rotorangular velocity threshold value (“? LOW THRS”) and a high speed estimate of an angular velocity of the rotor (“HS_?_EST”) relative to a high rotor angular velocity threshold value (“?_HIGH_THRS”); and
select LS_? EST or HS_?_EST as an estimated rotor flux angle based on LS_?_EST relative to_LOW_THRS and HS_?_ESET relative to ?_HIGH_THRS.

US Pat. No. 10,340,819

FAULT SHUTDOWN CONTROL OF AN ELECTRIC MACHINE IN A VEHICLE OR OTHER DC-POWERED TORQUE SYSTEM

GM Global Technology Oper...

1. A direct current (DC)-powered torque system comprising:a DC power supply;
a polyphase electric machine having an output shaft operable for transmitting an output torque;
a DC voltage bus;
an alternating current (AC) voltage bus;
a contactor pair;
a power inverter module (PIM) having a plurality of semiconductor switches, wherein the PIM is selectively connected to the DC power supply via the contactor pair and the DC voltage bus, and is directly connected to the electric machine via the AC voltage bus;
a DC link capacitor in electrical parallel with the plurality of semiconductor switches;
a voltage sensor configured to measure a DC link voltage across the DC link capacitor; and
a controller having memory programmed with a set of calibrated values, including an inductance of the electric machine and a DC link capacitance of the DC link capacitor, wherein the controller is programmed to execute a control action with respect to the torque system in response to a predetermined fault condition, wherein the predetermined fault condition results in an opening of the contactor pair and a polyphase short condition, the control action including:
calculating a back electromotive force of the electric machine using the set of calibrated values and the DC link voltage from the voltage sensor; and
transmitting switching control signals to the semiconductor switches to transition from the polyphase short condition to a polyphase open condition only when the calculated back electromotive force is less than a calibrated value and a voltage rise on a DC side of the PIM is less than a calibrated voltage rise.

US Pat. No. 10,340,815

LIQUID EJECTING APPARATUS AND CIRCUIT BOARD

Seiko Epson Corporation, ...

1. A liquid ejecting apparatus comprising:a first ejecting section that includes a first drive element and ejects liquid by driving the first drive element;
a first drive circuit that includes a first transistor and outputs a first drive signal to the first drive element;
a second drive circuit that includes a second transistor and outputs a second drive signal to the first drive element; and
a circuit substrate on which the first drive circuit and the second drive circuit are mounted, wherein
the first drive circuit is mounted on a first surface of the circuit substrate,
the second drive circuit is mounted on a second surface of the circuit substrate on an opposite side from the first surface, and
the first transistor and the second transistor are disposed at positions that do not overlap one another in plan view of the circuit substrate.

US Pat. No. 10,340,814

GATE-BLOCKING A DC/DC CONVERTER BASED UPON OUTPUT CURRENT OF AN AC REACTOR IN A POWER CONVERSION DEVICE

Sumitomo Electric Industr...

1. A power conversion device provided between a DC power supply and an AC electric path and performing DC/AC power conversion in a state in which a DC voltage of the DC power supply is lower than a peak value of an AC voltage of the AC electric path, the power conversion device comprising:a DC/DC converter provided between the DC power supply and a DC bus;
an intermediate capacitor connected to the DC bus and having such a small capacitance as not to smooth a pulsation that is included in a voltage of the DC bus and has a frequency twice as high as a frequency of the AC voltage;
an inverter connected to the DC bus;
a filter circuit provided between the inverter and the AC electric path and having an AC reactor and an AC-side capacitor;
a current sensor configured to detect a current flowing through the AC reactor; and
a control unit configured to perform control such that, for generating the AC voltage from the DC voltage, a period during which the DC/DC converter boosts the DC voltage and the inverter performs one of polarity non-inversion passing and polarity inversion passing, and a period during which the DC/DC converter is stopped and the inverter performs step-down operation and one of polarity non-inversion passing and polarity inversion passing, arise alternately in one AC cycle, wherein
the control unit temporarily performs gate blocking for only the DC/DC converter, upon occurrence of a phenomenon in which, by start of power feeding to a load connected to the AC electric path, an absolute value of the current flowing through the AC reactor reaches a predetermined converter gate block threshold value lower than an instantaneous overcurrent protection threshold value.

US Pat. No. 10,340,811

INVERTER SWITCHING DEVICES WITH GATE COILS TO ENHANCE COMMON SOURCE INDUCTANCE

FORD GLOBAL TECHNOLOGIES,...

1. A half-bridge power module comprising;a body encapsulating a pair of transistor dies and positive, negative, and AC conductive tracks for carrying bridge currents;
a pair of gate drive pins projecting from the body; and
a pair of gate drive coils connecting a respective gate drive pin and transistor die, wherein each gate drive coil has at least one winding turn, and wherein the gate drive coils are encapsulated in a region disposed between the positive and negative conductive tracks containing a flux generated by the currents having a locally greatest rate of change.

US Pat. No. 10,340,810

BIDIRECTIONAL DC CONVERTER ASSEMBLY HAVING CASCADE OF ISOLATED RESONANT CONVERTER AND STEP-UP/STEP-DOWN CONVERTER

1. A bidirectional DC/DC converter assembly for an electric vehicle having a high-voltage (HV) level and a low-voltage (LV) level, the bidirectional DC/DC converter assembly comprising:a first DC/DC converter having a first port and a second port, the first DC/DC converter connected to the HV level by the first port being connected to the HV level;
a second DC/DC converter having a third port and a fourth port, the second DC/DC converter connected to the first DC/DC converter by the third port being connected to the second port, the second DC/DC converter connected to the LV level by the fourth port being connected to the LV level, wherein the second DC/DC converter is a series resonant switching converter formed by a DC/AC converter, a transformer, and an AC/DC converter;
wherein when energy is to flow in a first direction from the HV level to the LV level the first DC/DC converter is operable as a buck converter to convert a high DC voltage inputted to the first port into an intermediate DC voltage that is outputted at the second port;
wherein when energy is to flow in a second direction from the LV level to the HV level the first DC/DC converter is operable as a boost converter to convert at intermediate DC voltage inputted to the second port into a high DC voltage that is outputted at the first port; and
a peak current controller associated with the first DC/DC converter, the peak current controller including a current sensor for measuring an inductor current of an inductor of the first DC/DC converter,
wherein, when the inductor current is a bidirectional inductor current having a polarity that changes between positive and negative during a change in the flow of energy between the first and second directions, the peak current controller generates a modified current variable that is a summation of the bidirectional inductor current and an offset value, the offset value being such that the modified current variable has a constant polarity,
wherein the peak current controller uses the modified current variable as a set point in controlling power switches of the first DC/DC converter during a change in operation of the first DC/DC converter between the buck converter and the boost converter in correspondence with the change in the flow of energy between the first and second directions.

US Pat. No. 10,340,809

BIDIRECTIONAL DC-DC RESONANT CONVERTER

Eltek AS, Drammen (NO)

1. Bi-directional DC-DC resonant converter with bi-directional voltage control, comprising:primary converter terminals defining a primary voltage;
secondary converter terminals defining a secondary voltage;
a transformer device having primary transformer terminals and secondary transformer terminals;
a resonant tank device having first and second primary resonant tank terminals defining a primary resonant tank voltage and first and second secondary resonant tank terminals defining a secondary resonant tank voltage, wherein the primary tank terminals are connected to the secondary transformer terminals;
a primary switching circuit connected between the primary converter terminals and the primary transformer terminals; and
a secondary switching circuit connected between the secondary resonant tank terminals and the secondary converter terminals;
wherein the resonant tank device comprises a configuration switch for configuration of the converter between a first state, in which power is transferred from the secondary converter terminals to the primary converter terminals, and a second state, in which power is transferred from the primary converter terminals to the secondary converter terminals;
wherein the resonant tank device comprises a resonant inductor, a magnetizing inductor and a resonant capacitor connected to the configuration switch;
wherein a first gain is defined as the ratio between a first harmonic approximation of the secondary resonant tank voltage and a first harmonic approximation of the primary resonant tank voltage when operating at a first series resonance frequency in the first state;
wherein a second gain is defined as the ratio between a first harmonic approximation of the secondary resonant tank voltage and a first harmonic approximation of the primary resonant tank voltage when operating at a second series resonance frequency in the second state; and
wherein the first gain is different from the second gain.

US Pat. No. 10,340,807

GATE DRIVE APPARATUS FOR RESONANT CONVERTERS

Futurewei Technologies, I...

1. A device comprising:a gate drive bridge coupled between a bias voltage of a power converter and ground, wherein the gate drive bridge comprises two high-side switches and two low-side switches, and wherein a duty cycle of the two low-side switches is greater than a duty cycle of the two high-side switches; and
a transformer connected to the gate drive bridge, wherein the transformer comprises:
a primary winding connected to two legs of the gate drive bridge respectively; and
a plurality of secondary windings configured to generate gate drive signals for low side switches, high side switches and secondary switches of the power converter.

US Pat. No. 10,340,800

SHORT CIRCUIT PROTECTION FOR A POWER CONVERTER

Dialog Semiconductor (UK)...

1. A switched mode power converter configured to convert electrical power between a first voltage at a first port and a second voltage at a second port; wherein the first and second voltages are relative to a reference potential; wherein the power converter comprisesan inductive element having a first side and a second side; wherein the first side of the inductive element is coupled to the first port;
a power switch configured to couple or to decouple the second side of the inductive element to or from the reference potential;
a capacitive element having a first side and a second side; wherein the first side of the capacitive element is coupled to the power switch; wherein the second side of the capacitive element is coupled to the second port and wherein the second side of the inductive element is coupled to the first side of the capacitive element;
an auxiliary switch configured to couple or to decouple the second side of the capacitive element to or from the reference potential; and
a control unit configured to control the power switch and the auxiliary switch in a repetitive manner to convert electrical power, wherein the control unit is configured to detect a short circuit situation at the first or second port and in reaction to this, put both the power switch and the auxiliary switch in an off-state such that the capacitive element and the inductive element are arranged in series between the first and second port.

US Pat. No. 10,340,799

STEP-UP/DOWN POWER SUPPLY AND POWER SUPPLY CIRCUIT

Hitachi Automotive System...

1. A step-up/down power supply comprising:a step-down unit that generates an output voltage lower than an input voltage by turning on or off a step-down switch in which the input voltage of the step-up/down power supply is applied to an end of the step-down switch;
a step-up unit that generates an output voltage higher than the input voltage by turning on or off a step-up switch in which a ground is applied to an end of the step-down switch; and
a step-down gate voltage control circuit that controls a gate voltage of the step-down switch,
wherein the step-down gate voltage control circuit includes a gate voltage generating circuit that generates a first voltage and a second voltage for turning on the step-down switch, and a gate voltage switching circuit that switches between the first voltage and the second voltage,
wherein the gate voltage generating circuit includes a first generating circuit generating the first voltage and a second generating circuit generating the second voltage,
wherein a load current for driving the second generating circuit is greater than that of the first generating circuit,
wherein the gate voltage switching circuit:
when the input voltage is equal to or lower than a first voltage threshold corresponding to the output voltage and a voltage generated from the first generating circuit becomes the first voltage, switches a voltage for turning on the step-down switch to the first voltage, and
when the input voltage is higher than the first voltage threshold, switches the voltage for turning on the step-down switch to the second voltage,
wherein the gate voltage switching circuit includes:
an initiation determining circuit in which output is transitioned from Low to High in order to initiate the first generating circuit;
a voltage determining circuit in which output is transitioned from Low to High in a case in which a voltage generated from the first generating circuit is the first voltage; and
a step-up/down determining circuit in which output is transitioned from Low to High in a case in which the input voltage is equal to or lower than the first voltage threshold corresponding to the output voltage, and output of the voltage determining circuit is from Low to High, and
wherein the initiation determining circuit is reset by an operation of switching the output of the step-up/down determining circuit from High to Low, and a state of the first generating circuit becomes a stop state from an operation state by switching the output from High to Low.

US Pat. No. 10,340,797

REGULATOR CONTROL INTEGRATED CIRCUIT HAVING COT AND VALLEY CURRENT MODES

Active-Semi, Inc., (VG)

1. A voltage regulator control integrated circuit having a valley current (VC) mode and a constant on-time (COT) mode, the voltage regulator control integrated circuit comprising:a sequential logic element having a set input lead, a reset input lead, and an output lead;
a comparator circuit that supplies a set signal SET to the sequential logic element;
a osc/one-shot circuit that supplies a reset signal RESET to the sequential logic element, wherein in the COT mode the reset signal RESET is a delayed one-shot pulse signal, and wherein in the VC mode the reset signal RESET is a free-running oscillating signal;
a compensation signal generator circuit that supplies a compensation voltage signal VC to the comparator circuit, wherein in the COT mode the compensation voltage signal VC is an AC ground signal, and wherein in the VC mode the compensation voltage signal VC is a ramp signal;
a current sense circuit that outputs a voltage signal VCURRENT indicative of a magnitude of a current, wherein the current sense circuit supplies the voltage signal VCURRENT to the comparator circuit; and
an error amplifier circuit that supplies an error voltage signal VE to the comparator circuit.

US Pat. No. 10,340,796

CONSTANT ON TIME BOOST CONVERTER CONTROL

Cirrus Logic, Inc., Aust...

1. A controller for controlling at least one switch of a boost switching converter comprising an inductor coupled to a first terminal of a power supply, a first switch coupled between the inductor and an output of the boost switching converter, and a second switch coupled between the inductor and a second terminal of the power supply, the controller comprising:a current estimator configured to determine an estimated inductor current through the inductor during a first phase of a particular switching cycle of the boost switching converter in which the inductor is discharging, the first switch is activated, and the second switch is deactivated, wherein the current estimator is configured to estimate the inductor current by applying volt-second balance calculations to determine the estimated inductor current based on: (a) a previous sample of a current through the inductor during a second phase of the particular switching cycle of the boost switching converter in which the inductor is charging, the second switch is activated, and the first switch is deactivated, (b) a power supply voltage between the first terminal of the power supply and the second terminal of the power supply, and (c) an output voltage at the output of the boost switching converter; and
a switch control configured to control activation and deactivation of the at least one switch based on the estimated inductor current.

US Pat. No. 10,340,791

CHARGE PUMP

Dialog Semiconductor (UK)...

7. A DC-DC voltage converter circuit comprising:a charge pump;
a measurement circuit adapted to:
measure at a first time an output voltage of the charge pump;
store said first measured voltage:
measure and store at a second later time a second output voltage of said charge pump;
compare said stored second measured voltage with said stored first measured voltage; and
a logic circuit arranged to cooperate with the measurement circuit to optimize a charge pump efficiency during a charge pumping operation, by adjusting an operational parameter of the charge pump based on the comparison.

US Pat. No. 10,340,786

HIGH FREQUENCY WIRELESS POWER RECTIFIER STARTUP CIRCUIT DESIGN

Integrated Device Technol...

1. A rectifier, comprising:a first transistor and a second transistor coupled in series between a rectifier output and a ground, wherein a first AC input is coupled to a first node between the first transistor and the second transistor;
a third transistor and a fourth transistor coupled in series between the rectifier output and the ground, wherein a second AC input is coupled to a second node between the third transistor and the fourth transistor;
a first control circuit coupled between a gate of the first transistor and a gate of the fourth transistor to control operation of the first and the fourth transistors;
a first startup circuit directly connected between the gate of the first transistor and the first node, the first startup circuit controlling the gate of the first transistor in a startup time period prior to an operating period of the rectifier, wherein the first startup circuit maintains a low impedance between the gate of the first transistor and the first node during a startup time and maintains a high impedance between the gate of the first transistor and the first node during the operating period of the rectifier; and
a second startup circuit directly connected between the gate of the fourth transistor and the ground.

US Pat. No. 10,340,778

PARALLEL MAGNETIC CIRCUIT MOTOR

QM Power, Inc., Kansas C...

1. A machine, comprising:a rotor without magnets; and
a stator comprising a plurality of phase sections, each phase section corresponding to one of a plurality of electrically independent phases of the machine and each phase section having pairs of pole faces of permanent magnets arranged with same facing magnetic poles in which a magnetic pole of a permanent magnet faces a same magnetic pole of another permanent magnet, a plurality of stator poles between the same facing permanent magnet pole faces, and a winding on each of the stator poles.

US Pat. No. 10,340,775

APPARATUS FOR WINDING AND TERMINATING DYNAMO ELECTRIC MACHINE CORES

1. Apparatus for winding and terminating coils wound with at least one electric wire on a core of a dynamo electric machine; the core having a longitudinal axis; the apparatus comprising:a wire dispenser; the dispenser having a tubular portion for passage of the wire and an exit from where the wire reaches the core;
a first motor for translating the dispenser with respect to the core during winding or the termination of leads;
tubular support for supporting the core;
a second motor for rotating the tubular support of the core around a rotation axis;
a pulley wheel where the wire is wound before entering the passage portion of the dispenser;
a recovery device of the wire that draws the wire returning from the pulley wheel;
characterized in that the feeding the wire comprises:
a device for applying torque in two directions on the pulley wheel as a function of the position of the dispenser in the translation and the position of the core in the rotation.

US Pat. No. 10,340,772

ELECTRONICALLY COMMUTATED FAN MOTORS AND SYSTEMS

Orange Motor Company L.L....

1. A refrigeration system comprising:a refrigerant line coupling a compressor, a condenser, a valve mechanism, and an evaporator;
an evaporator fan comprising an electronically commutated fan motor;
a cooling system control circuit electrically coupled to the electronically commutated fan motor; and
the electronically commutated fan motor comprising
a motor housing comprising an exterior wall;
a shaft;
a shaft drive assembly rotatably coupled to the shaft;
a power input connector;
a control input connector;
a switch attached to the motor housing comprising a base and an actuator accessible outside the motor housing, the actuator comprising a first actuator position and a second actuator position;
a controller configured to control the shaft drive assembly based on a control signal from the control input connector, a power signal from the power input connector, and a switch signal from the switch;
wherein operation of the shaft drive assembly and the shaft is characterized by a rotation speed and a rotation direction; and
the controller is configured to control the rotation direction of the shaft drive assembly and the shaft based on the switch signal and the power signal;
wherein the controller is configured to switch the direction of rotation in response to the actuator moving from the first actuator position to the second actuator position;
wherein the controller configured to sense when a power signal is present at the power input connector;
wherein the controller is configured to disable changes to the rotation direction of the evaporator fan when a power signal is detected at the power input connector; and
the control circuit configured to provide a control signal to the control input connector for adjusting a speed of a blower fan.

US Pat. No. 10,340,771

FAN MOTOR WITH HEAT SINK AND DISCHARGE SECTION

DENSO CORPORATION, Kariy...

1. A fan motor comprising:a motor body including a stator and a rotor that rotates in response to a magnetic field of the stator;
a fan that rotates accompanying rotation of the rotor;
a controller that includes a circuit board configuring a control circuit to control passing of current to the stator and a circuit element attached to the circuit board;
a heat sink that is attached to the controller and that includes a heat dissipating section for dissipating heat from the controller, the heat dissipating section including at least a projection configuring the heat dissipating section;
a case body that includes a motor holder provided at a periphery of the rotor, and a center piece supporting the stator, with the heat dissipating section disposed between the center piece and the motor holder and the center piece forming an airflow passage along which airflow passes;
an introduction section through which airflow flowing toward the heat dissipating section is introduced;
a discharge section through which the airflow that has been introduced through the introduction section is discharged toward the fan side; and
a facing wall that is disposed at a downstream side of the airflow passing through the projection with respect to the heat dissipating section, that extends in a direction to obstruct the airflow, and that extends along an axial direction of the motor,
wherein the projection and the facing wall are disposed facing each other in a radial direction of the motor.

US Pat. No. 10,340,770

STATOR UNIT, MOTOR, AND PARALLEL FAN

NIDEC CORPORATION, Kyoto...

1. A stator unit comprising:a cylindrical bearing housing extending along a central axis extending in a vertical direction;
a base member fixing the bearing housing;
a stator fixed to an outer circumferential surface of the bearing housing; and
a mold resin portion covering the stator; wherein
the stator includes:
a stator core including a plurality of teeth projecting radially outward;
an insulator covering a portion of a surface of the stator core; and
a plurality of coils each of which is defined by a conducting wire wound around a separate one of the teeth with the insulator therebetween; and
a sealing agent is located between the outer circumferential surface of the bearing housing and the insulator, and/or between the insulator and the stator core.

US Pat. No. 10,340,769

AUXILIARY DRIVE DEVICE

BorgWarner Inc., Auburn ...

1. An auxiliary drive device comprisingan electric motor having a rotor, which is rotatable about an axis, and a stator that is received within the rotor; and
a viscous clutch having a housing, a clutch disk and a reservoir, the housing being coupled to the rotor for common rotation about the axis, the clutch disk being received in the housing and being rotatable about the axis relative to the housing, the housing and the clutch disk forming a working chamber, the reservoir being coupled in fluid communication to the working chamber.

US Pat. No. 10,340,766

WATERPROOF STABILIZER AND WATERPROOFING METHOD THEREOF

1. A waterproof stabilizer, comprising: a fixing assembly, a rotating assembly, a circuit board and a waterproof assembly, wherein the rotating assembly comprises a first motor, a second motor, a third motor, a first connecting arm and a second connecting arm, wherein the first motor, the second motor and the third motor are orthogonally arranged in space, a rotor of the first motor is connected with the fixing assembly, a stator of the first motor is fixedly connected with a rotor of the second motor via the first connecting arm, a stator of the second motor is fixedly connected with a rotor of the third motor via the second connecting arm, and the first motor, the second motor and the third motor are respectively connected to the circuit board via a connecting base;a first protective case and a first protective cover are arranged on an outside of the first motor, a side wall of the first protective case is connected to the first connecting arm, and the first protective cover is covered on the first protective case; a second protective case and a second protective cover are arranged on an outside of the second motor, a side wall of the second protective case is connected to the second connecting arm, and the second protective cover is covered on the second protective case;
a waterproof assembly comprises a first sealing ring, a second sealing ring, a third sealing ring, a fourth sealing ring, a first waterproof plug, a second waterproof plug, a third waterproof plug, a first waterproof layer, a second waterproof layer, a third waterproof layer, and a waterproof membrane;
wherein the first sealing ring is arranged between the fixing assembly and the rotor of the first motor;
the second sealing ring is arranged between the first protective case and the first protective cover;
the third sealing ring is sleeved on a shaft of the second motor;
the fourth sealing ring is arranged between the second protective case and the second protective cover;
the first waterproof plug is arranged between the side wall of the first protective case and the first connecting arm;
the second waterproof plug is arranged between the side wall of the second protective case and the second connecting arm;
the third waterproof plug is arranged at an end of a shaft of the third motor, and a shaft hole of the third motor is plugged by the third waterproof plug;
the first waterproof layer is arranged on a surface of the circuit board, the second waterproof layer is covered on the first waterproof layer, and the third waterproof layer is covered on the second waterproof layer; and
the waterproof membrane is covered on a surface of the connecting base.

US Pat. No. 10,340,765

DRIVE APPARATUS HAVING MOTOR UNIT RECEIVED IN MOTOR CASE

DENSO CORPORATION, Kariy...

1. A drive apparatus comprising:a motor unit;
a motor case that is shaped into a tubular form and has a first space, which receives the motor unit;
a frame that contacts an inner peripheral wall of the motor case at a contact location and is fixed to an inside of the motor case;
at least one cutout that is formed in at least one of the inner peripheral wall of the motor case and an outer peripheral wall of the frame and is located on an opposite side of the contact location, which is opposite from the first space, wherein the at least one cutout forms a seal groove, which is located between the motor case and the frame and extends in a circumferential direction;
a cover that covers the seal groove and forms a second space on an opposite side of the frame, which is opposite from the first space; and
a seal material that is received in the seal groove and contacts each of the motor case, the frame and the cover in a radial direction relative to an axis of the motor unit, wherein:
the cover includes an inserting portion that is inserted into an inside of the at least one cutout and inserted into the seal material, and
the seal material includes one portion, which seals between the inserting portion and the frame, and another portion, which seals between the inserting portion and the motor case.

US Pat. No. 10,340,762

STATOR FOR ELECTRIC ROTARY MACHINE AND METHOD FOR PRODUCING THE STATOR

HONDA MOTOR CO., LTD., T...

1. A stator for an electric rotary machine comprising:a stator core, which has plural slots; and
a coil, which is attached to the stator core, wherein:
the coil has plural slot coils and plural connection coils, each slot coil being inserted into the slot, each connection coil connecting the slot coils in a position lying further axially outwards than an axial end face of the stator core, and the coil being constituted in such a way that the slot coil and the connection coil are joined at an abutment portion;
the connection coil is accommodated in an accommodating portion, which is provided in an insulation plate that is made of an insulation material and that is disposed outwards of the axial end face of the stator core;
the connection coil is such that a connection coil main body extends from one side to an other side in a circumferential direction;
the connection coil main body abuts against the insulation plate in such a state that the connection coil is accommodated in the accommodating portion; and
in a hole portion, where the abutment portion is accommodated, of the insulation plate, the connection coil and the slot coil are spaced apart from the insulation plate in the circumferential direction to thereby form a first gap portion.

US Pat. No. 10,340,757

ROTOR MEMBER, ROTOR AND ELECTRIC MOTOR

FANUC CORPORATION, Yaman...

1. A rotor member that is fixed by press-fitting to a rotary shaft part of a rotating electrical machine, comprising:a cylindrical sleeve part having a first end at an axial-direction first side thereof, and a second end at an axial-direction second side thereof;
a plurality of magnet segments that are arranged to align in a circumferential direction at an outer side in the radial direction of the sleeve part; and
a cylindrical member that covers the plurality of the magnet segments from an outer side in the radial direction, and sandwiches the plurality of the magnet segments with the sleeve part, wherein
an inner circumferential face of the sleeve part has a tapered face that continuously expands towards the outer side in the radial direction as approaching the second end from the first end, and wherein
a thrust member that thrusts the cylindrical member to the outer side in the radial direction against the sleeve part is present between the plurality of the magnet segments which are adjacent in the circumferential direction, wherein
the thrust member thrusts the cylindrical member to the outer side in the radial direction such that a gap is formed between an inner circumferential face of the cylindrical member and a radially outer corner of each magnet segment that is directly adjacent to the thrust member in the circumferential direction, the radially outer corner of each magnet segment being the radially outer corner directly adjacent to the thrust member in the circumferential direction.

US Pat. No. 10,340,756

ROTATING ELECTRIC MACHINE AND VEHICLE EQUIPPED WITH ROTATING ELECTRIC MACHINE

Hitachi Automotive System...

1. A rotating electric machine, comprising:a stator core having a plurality of slots formed therein;
a stator winding assuming a plurality of phases, which includes a plurality of coil windings wound with a wave winding pattern, each coil winding made up with slot conductors each inserted at one of the slots at the stator core to form one of a plurality of layers and cross conductors each connecting same-side ends of slot conductors inserted at different slots so as to form a coil end; and
a rotor rotatably disposed via an air gap so as to be allowed to rotate relative to the stator core, which includes a plurality of magnets and a plurality of magnetic auxiliary salient pole portions each formed between poles formed with the magnets, wherein:
the cross conductors connect the slot conductors so as to run astride slots with a slot pitch Np set to N+1 at coil ends on one side and run astride slots with the slot pitch Np set to N?1 at coil ends on another side, with N representing a number of slots per pole;
the stator winding are arranged into stator winding groups, and each stator winding group comprises a plurality of circumferential windings of the same phase so that there is no phase difference between groups corresponding to a single phase;
the stator winding includes a plurality of slot conductor groups each made up with a plurality of slot conductors corresponding to a single phase;
the plurality of slot conductors in each slot conductor group are inserted at a predetermined number Ns of successive slots forming a continuous range along a circumference of the stator core so that the slot conductors in the slot conductor group take successive slot positions and successive layer positions; and
the predetermined number Ns is set so that Ns=NSPP+NL when NSPP represents a number of slots per pole per phase, NL represents a number of layers, and the number of layers is expressed as 2×NL;
the rotor includes magnetic resistance-altering portions located at positions each offset along a circumferential direction from a q-axis passing through a center of a corresponding magnetic auxiliary salient portion; and
the magnetic resistance-altering portion is provided on every other magnetic pole formed with the magnet, and a magnetic pole provided with the magnetic resistance-altering portion and a magnetic pole without the magnetic resistance-altering portion are alternately arranged.

US Pat. No. 10,340,754

ROTATING ELECTRICAL MACHINE AND METHOD OF MANUFACTURING ROTATING ELECTRICAL MACHINE

Mitsubishi Electric Corpo...

1. A rotating electrical machine comprising:a stator core including a plurality of stacked electromagnetic steel sheets, the stator core including a core back and a tooth protruding from the core back, wherein
the tooth includes:
a plurality of first welded portions arranged on a first lateral face of the tooth and arranged in a stacking direction of the plurality of electromagnetic steel sheets; and
a plurality of second welded portions arranged on a second lateral face of the tooth and arranged in the stacking direction, and
the plurality of first welded portions and the plurality of second welded portions are arranged in a staggered fashion in the stacking direction.

US Pat. No. 10,340,750

FOREIGN OBJECT DETECTION MANIPULATION METHOD

Nokia Technologies Oy, E...

1. A method, comprising:receiving a wireless power signal from a wireless energy transmitter device;
determining a power level value of the received wireless power signal;
manipulating the determined power level value to obtain a manipulated power level value; and
sending the manipulated power level value to the wireless energy transmitter device.

US Pat. No. 10,340,747

POWER TRANSMITTING METHOD AND POWER TRANSMITTER FOR COMMUNICATION WITH POWER RECEIVER

Samsung Electronics Co., ...

1. A method of controlling power transmission of a wireless power transmitter, the method comprising:transmitting, by a resonator, first power for detecting a change of impedance;
in response to the change of impedance being detected, transmitting, by the resonator, second power for communicating with a wireless power receiver;
increasing the second power from a first magnitude to a second magnitude;
receiving a signal from the wireless power receiver while transmitting the second power;
in response to receiving the signal, transmitting a connection request signal to the wireless power receiver; and
transmitting, by the resonator, third power to the wireless power receiver for charging the wireless power receiver.

US Pat. No. 10,340,743

POWER TRANSMISSION DEVICE, POWER TRANSMISSION METHOD, AND WIRELESS POWER TRANSFER SYSTEM

IHI CORPORATION, Tokyo (...

1. A power transmitter that wirelessly transmits power to a power receiver, the power transmitter comprising:a power converter that converts power fed from a power source into a first direct current (DC) power;
an inverter circuit that converts the first DC power output from the power converter into a first alternating current (AC) power;
a power transmission coil that generates a magnetic field based on the first AC power fed from the inverter circuit, and is magnetically coupled with a power reception coil included in the power receiver;
a sensor that detects a current value and a voltage value of the first DC power; and
a controller that controls the power converter,
wherein the controller
controls the power converter to raise a voltage of the first DC power up to a first voltage value lower than a power feeding time voltage value predetermined as a voltage value at a time of feeding power to the power receiver, and
determines whether power is not allowed to be fed to the power receiver based on the current value of the first DC power detected by the sensor when the voltage of the first DC power is the first voltage value.

US Pat. No. 10,340,738

WIRELESS INDUCTIVE POWER TRANSFER

KONINKLIJKE PHILIPS N.V.,...

1. A power transmitter for transferring power to a power receiver using an inductive power signal, wherein the power transmitter comprises:a first inductor for providing via the first inductor an inductive power signal to the power receiver;
a second inductor for receiving data signals from the power receiver,
a capacitor in a series coupling with the second inductor;
wherein the first and second inductors are separate inductors in a power transfer circuit and a data signal receiving circuit,
wherein the data signal receiving circuit comprises a data extracting circuit for extracting the data signals received by the second inductor and a driver for generating a drive signal for the series coupling of the second inductor and the capacitor during a drive time interval including the communication period,
the power transmitter comprising a control unit for controlling the power signal supplied via the first inductor to the power receiver in dependence on the data signals received and
the power transmitter is arranged to transfer power via the first inductor during power transfer periods of a repeating time frame and receive data signal via the second inductor during communication periods of a repeating time frame, a power of the inductive power signal being reduced for the communication period relative to the power transfer period,
wherein a control circuit is arranged for application of a controlled electrical coupling of the data extraction circuit to the second inductor during a communication period and electrical decoupling of the data extraction circuit from the second inductor during at least a part of power transfer periods; and the data signal receiving circuit further comprises a discharge circuit for discharging the capacitor during a discharge time interval of the time frame at least partially preceding the communication period.

US Pat. No. 10,340,734

POWER GENERATION SYSTEMS WITH MONITORING FOR ANOMALY DETECTION VIA NONLINEAR RELATIONSHIP MODELING

NEC Corporation, Tokyo (...

1. A power generator system with anomaly detection, comprising:a power generator that includes one or more physical components configured to provide electrical power;
a plurality sensors configured to make measurements of a state of respective physical components, outputting respective time series of said measurements; and
a monitoring system, comprising:
a fitting module configured to determine a predictive model for each pair of a set of time series, to determine polynomial bases for modeling a polynomial relationship between the time series, to solve a corresponding Sparse Group Lasso problem for the set of time series, and to correct coefficients of a solution of the corresponding Sparse Group Lasso problem by linear regression;
an anomaly detection module configured to compare new values of each pair of time series to values predicted by the respective predictive model to determine if the respective predictive model is broken and to determine a number of broken predictive models; and
an alert module configured to generate an anomaly alert if the number of broken predictive models exceeds a threshold.

US Pat. No. 10,340,731

SYSTEM AND METHOD FOR PRESERVING BACK-UP BATTERY FOR IMPROVED BACK-UP AVAILABILITY

Honeywell International I...

1. A battery management system, comprising:a main battery and a back-up battery;
a load electrically connected to:
a main battery through a first switch, a first resistor and a first diode in series;
a back-up battery through a second switch, a second resistor and a second diode in series; and
a voltage monitoring circuit electrically connected to said main battery, said back-up battery and the load, wherein said voltage monitoring circuit monitors a voltage from said main battery and triggers a changeover to said back-up battery based on a low threshold voltage, establishing a main battery interface path by a diode for switching between the main battery and the back-up battery to avoid power interruptions, wherein the low threshold voltage of said voltage monitoring circuit is dynamically tunable to factor external variables.

US Pat. No. 10,340,729

APPARATUS AND METHOD FOR CONTROLLING ELECTRIC CURRENTS WITH PULSE WIDTH MODULATION SIGNAL

LG CHEM, LTD., Seoul (KR...

11. A method of controlling electric currents, comprising:measuring, by a battery voltage measuring unit, a voltage of a battery;
measuring, by a rectifier voltage measuring unit, a voltage of a rectifier;
generating, by a pulse width modulation (PWM) signal generating unit, a PWM signal based on a difference between the voltage of the battery and the voltage of the rectifier;
receiving, by a first switch unit connected with the PWM signal generating unit, the PWM signal and generating a switch control signal corresponding to the PWM signal;
receiving, by a second switch unit connected with the first switch unit, the switch control signal and connecting or blocking a flow of a current from the rectifier to the battery according to the switch control signal; and
decreasing, by a current decreasing unit connected with the second switch unit, a current value of a current passing through the second switch unit and providing the battery with a current having the decreased current value.

US Pat. No. 10,340,726

METHOD AND POWER TRANSMITTER FOR CONTROLLING POWER TRANSMISSION

Samsung Electronics Co., ...

1. A method of controlling power transmission in a power transmitter, the method comprising:receiving, from at least one power receiver, a first message including a first voltage and a second voltage that is greater than the first voltage;
transmitting power to the at least one power receiver;
receiving, from the at least one power receiver, a second message including a third voltage measured at the at least one power receiver while transmitting the power; and
adjusting an amount of the power based on whether the third voltage is between the first voltage and the second voltage,
wherein the first voltage is a minimum voltage for the at least one power receiver.

US Pat. No. 10,340,725

WIRELESS POWER RECEPTION DEVICE

LG INNOTEK CO., LTD., Se...

1. A wireless power reception device comprising:a first shielding member;
a mounting member comprising an inner mounting member and an outer mounting member;
an inner coil mounted on the inner mounting member; and
a second shielding member disposed between the inner mounting member and the first shielding member,
wherein the outer mounting member surrounds a side surface of the second shielding member, and
wherein the inner mounting member has a portion higher than a portion of the outer mounting member.

US Pat. No. 10,340,723

ELECTRONIC DEVICE AND METHOD FOR WIRELESS CHARGING IN ELECTRONIC DEVICE

Samsung Electronics Co., ...

1. An electronic device comprising:a sensing circuit; and
a communication interface; and
at least one processor operatively coupled to the sensing circuit and the communication interface, configured to:
receive, from an external device, switch operation information associated with an operation of a switch included in the external device via the communication interface, wherein the switch is pressed by the electronic device when the electronic device is mounted on the external device;
identify a mounting state of the electronic device based on the switch operation information; and
perform a charging operation based on the mounting state of the electronic device.

US Pat. No. 10,340,717

CHARGING SYSTEM, CHARGING METHOD, AND POWER ADAPTER

Guangdong Oppo Mobile Tel...

1. A system for charging, comprising:a first rectification unit, configured to rectify an input alternating current (AC) voltage and output a voltage of a first pulsating waveform;
a switch unit, configured to modulate the voltage of the first pulsating waveform according to a control signal;
a transformer, configured to output a voltage of a second pulsating waveform based on the voltage of the modulated first pulsating waveform;
a second rectification unit, configured to rectify the voltage of the second pulsating wave form and output a voltage of a third pulsating waveform;
a filter unit, configured to filter the voltage of the third pulsating waveform and output a second direct current (DC) voltage;
a controllable switch, configured to control whether the filter unit operates;
a first charging interface;
a sampling unit, configured to sample at least one of an output voltage or an output current of the second rectification unit to obtain at least one of a voltage sampling value or a current sampling value;
a control unit, coupled with the sampling unit, the switch unit, and the controllable switch, respectively, the control unit being configured to control the controllable switch to cause the filter unit to operate to
output the second DC voltage via the first charging interface;
control the controllable switch to cause the filter unit to stop operating to output the voltage of the third pulsating waveform via the first charging interface; and
output the control signal to the switch unit to adjust at least one of a duty ratio of the control signal based on the voltage sampling value or the current sampling value, wherein the voltage of the third pulsating waveform or the second DC voltage meets charging requirements; and
a second charging interface and a battery coupled with the second charging interface, wherein the second charging interface is configured to apply the voltage of the third pulsating waveform or the second DC voltage to the battery when the second charging interface is coupled to the first charging interface.

US Pat. No. 10,340,716

ELECTRIC STORAGE DEVICE AND START-UP METHOD

MURATA MANUFACTURING CO.,...

1. An electric storage device, comprising:a control unit, a charge/discharge management unit, and a current generation unit, which are connected through an input/output unit; and
an electric storage unit that is connected to the charge/discharge management unit, and is further connected to the current generation unit through a switch, wherein:
the current generation unit is configured to generate a first current to charge the electric storage unit based on a voltage of the electric storage unit that is lower than a threshold value,
the switch is configured to be turned off in a shutdown state of the electric storage device, and
the control unit and the charge/discharge management unit are configured to consume zero power during a standby state of the electric storage device.

US Pat. No. 10,340,715

POWER CONTROL APPARATUS, POWER CONTROL METHOD, AND POWER CONTROL SYSTEM

KYOCERA Corporation, Kyo...

1. A power control apparatus that connects to a grid and is capable of controlling charging and discharging of a storage cell, the power control apparatus comprising:a controller configured to reduce a difference from a power purchase amount by controlling charging and discharging of the storage cell, the power purchase amount being established in a power purchase plan;
wherein the controller is further configured, upon acquiring a demand response request issued over a network, to make a comparison between a current amount of stored power in the storage cell and an amount of stored power necessary to comply with the demand response request, and to set a target power for power purchase from the grid on the basis of a result of the comparison,
wherein the demand response request is a request to reduce power usage at a predetermined time after the demand response request is received by the controller, and
wherein as a result of the comparison, when determining that the current amount of stored power in the storage cell does not satisfy the amount of stored power necessary to comply with the demand response request, the controller sets the target power to a first target value higher than a standard value that matches the power purchase amount at a corresponding time in the power purchase plan.

US Pat. No. 10,340,713

DEDICATED USB POWER PORTS COUPLED WITH A MULTI-PORT USB POWERED HUB

1. An apparatus, comprising:a powered universal serial bus hub comprising:
a first non-dedicated universal serial bus port that enables data communication and data transfer between the non-dedicated universal serial bus port and a first electronic device connected to the non-dedicated universal serial bus port; and
a dedicated universal serial bus port that provides dedicated charging to a second electronic device connected to the dedicated universal serial bus port,
wherein the dedicated universal serial bus port is created by unsoldering a first data pin and a second data pin from a circuit board of a second non-dedicated universal serial bus port and re-soldering the first data pin directly to the second data pin together in a crossed configuration such that communications and data transfer between the dedicated universal serial bus port and a second electronic device connected to the dedicated universal serial bus port are disabled, and
wherein the dedicated universal serial bus port provides the dedicated charging to the second electronic device without intervention of additional circuitry or software to enable charging of the second electronic device.

US Pat. No. 10,340,712

SECURE DEVICE CHARGING

CHARGEBOX LTD, London (G...

1. An apparatus for authenticating an initiation of a charging process for a secure charging apparatus, the apparatus comprising:circuitry configured to authorize a user;
circuitry configured to confirm connection of a device;
circuitry configured to determine if initial provision of a charging current to the device has commenced and been accepted, thereby confirming charging of the device is possible;
a locking mechanism configured to secure the device in the apparatus; and
circuitry configured to control the locking mechanism, wherein the circuitry configured to control the locking mechanism is configured to enable the locking mechanism only if:
(i) the user authorization is successful;
(ii) the confirmation of the connection is successful; and
(iii) the determination that the initial provision of the charging current to the device has commenced and been accepted is successful, and
wherein the charging process can continue only if the locking mechanism is enabled.

US Pat. No. 10,340,709

ELECTRIC BATTERY RAPID RECHARGING SYSTEM INCLUDING A MOBILE CHARGING STATION HAVING A COOLANT SUPPLY LINE AND AN ELECTRICAL SUPPLY LINE

Lightening Energy, Dover...

1. A mobile charging station comprising:a base portion comprising:
a charging source providing an electrical charge;
a coolant source providing coolant;
a supply line connected to the charging source and the coolant source and extendible outside of the base portion; and
a connector fixed to an end of the supply line, the connector being configured for insertion into a receptacle of a military device, the supply line including a coolant supply line configured for delivering coolant from the coolant source to the connector, the supply line including an electrical supply line configured for delivering electrical charge from the charging source to the connector, the connector having both an electrical supply section connected to the electrical supply line for delivering the electrical charge and a coolant supply section connected to the coolant supply line for delivering the coolant, and the connector being configured for connecting to the military device, the mobile charging station being or included on or in a ground vehicle, an aircraft or a marine vehicle.

US Pat. No. 10,340,707

ADJUSTMENT OF STATES OF CHARGE OF BATTERY CELLS

AUDI AG, Ingolstadt (DE)...

1. A method for the adjustment of states of charge of battery cells, comprising:determination of the states of charge of the battery cells that are operated electrically in parallel connection;
selection of those battery cells whose states of charge are to be adjusted in accordance with a predeterminable selection rule;
activation of those battery cells that are adjusted by means of a respective semiconductor switch of the battery cells and deactivation of the remaining battery cells by means of the semiconductor switches of the respective remaining battery cells;
carrying out the adjustment of the states of charge and monitoring the states of charge; and
termination of the adjustment of the states of charge when a predetermined state of charge has been attained by the activated battery cells.

US Pat. No. 10,340,706

ASSEMBLED BATTERY MONITORING APPARATUS AND ASSEMBLED BATTERY MONITORING SYSTEM

DENSO CORPORATION, Kariy...

1. An assembled battery monitoring apparatus comprising:a first operation functioning device that carries out a monitoring process on an assembled battery configured by a plurality of battery cells connected in series and communicates with a host controller through a communication input-and-output interface and a communication controller only in an ordinary operational timing in which the host controller controls an external power source to supply an operation power source;
a second operation functioning device that carries out a monitoring process on the assembled battery in response to a command received by the first operation functioning device from the host controller in the ordinary operational timing and in a non-ordinary operational timing in which the external power source stops supplying the operation power source;
a power supply switching device that performs switching so as to enable the assembled battery to supply the operation power source in the non-ordinary operational timing;
a first inner power circuit that is configured to receive a power supply from the external power source or the assembled battery to supply the operation power source to the first operation functioning device; and
a second inner power circuit that is configured to receive a power supply from the external power source or the assembled battery to supply the operation power source to the second operation functioning device,
wherein the power supply switching device stops the first inner power circuit from supplying the operational power source to the first operation functioning device in response to detecting a voltage drop in the external power source and changes a supply source of the operation power source in response to the command received by the first operation functioning device from the host controller.

US Pat. No. 10,340,698

LARGE-SCALE SPACE-BASED SOLAR POWER STATION: PACKAGING, DEPLOYMENT AND STABILIZATION OF LIGHTWEIGHT STRUCTURES

California Institute of T...

1. A space-based solar power station comprising:a plurality of independently operable unconnected compactible satellite modules disposed in space in an orbital array formation, wherein each of the compactible satellite modules comprises:
a plurality of moveably interconnected structural elements each having a finite thickness and are foldable relative to each other along at least one fold axis via a slip-fold and are configured to slip relative to each other in a direction parallel to the at least one fold axis such that the dimensional extent of the satellite modules is compactible;
a plurality of independent power generation tiles disposed on each of the plurality of moveably interconnected structural elements, each of the independent power generation tiles having at least one photovoltaic cell and at least one power transmitter collocated thereon, the at least one photovoltaic cell and the at least one power transmitter in signal communication with each other such that an electrical current generated by the collection of solar radiation by the at least one photovoltaic cell powers the at least one power transmitter, and where each of the at least one power transmitters comprises:
an antenna configured to receive a radio frequency power signal; and
control electronics in signal communication with the antenna and configured to control the phase of the radio frequency power signal such that the at least one power transmitter is in phased signal coordination with at least one other power transmitter on the plurality of other power generation tiles thereby forming an independent phased array of power transmitters;
wherein the independent phased array of power transmitters is configured to transmit a power signal to a remote location.

US Pat. No. 10,340,695

BATTERY ENERGY STORAGE DESIGN WITH BLACK STARTING CAPABILITY

General Electric Company,...

1. A method for black-starting a power system using a battery energy storage system, the power system comprising one or more loads coupled to a system bus, the method comprising:obtaining, by the one or more controllers, a signal requesting a black-start of the power system using the battery energy storage system;
increasing, by one or more controllers, a system bus voltage to a nominal voltage level using the battery energy storage system for a start period according to a start ramp; and
maintaining, by one or more controllers, the system bus voltage at about the nominal voltage level using the battery energy storage system during a normal period following the start period, wherein the start period has a sync period and a nominal period, the system bus voltage is increased using the battery energy storage system to a sync threshold level during the sync period and the battery energy storage system comprises a plurality of battery energy storage units, each battery energy storage unit comprising one or more battery energy storage devices and an inverter, wherein during the sync period, a plurality of battery energy storage units are individually connected to the system bus per each battery storage unit's own criteria of bus voltage and phase.

US Pat. No. 10,340,694

HYBRID TACTICAL QUIET GENERATOR

Hamilton Sundstrand Corpo...

1. An Output Supply System (OSS) comprising:an Electric Power Generating System (EPGS), comprising;
a first Permanent Magnet Synchronous Machine (PMSM);
a first three-phase multifunction converter;
a first three-position switch;
a battery management system, wherein the PMSM, the first three-phase multifunction converter, the first three-position switch, and the battery management system are in electronic communication; and
a first tangible, non-transitory memory configured to communicate with a first controller, the first tangible, non-transitory memory having instructions stored thereon that, in response to execution by the first controller, cause the first controller to perform operations comprising:
receiving, by the first controller, at least one of an input from a first sensor or a first parameter;
determining, by the first controller, a second parameter based on the input of the first sensor;
selecting, by the first controller, a first configuration of the first three-phase multifunction converter and a position of the first three-position switch in response to at least one of the first parameter or the second parameter; and
commanding, by the first controller, the first three-position switch to at least one of a first position, a second position, or a third position and commanding the first configuration of the first three-phase multifunction converter.

US Pat. No. 10,340,692

UNIVERSAL POWER CONTROL DEVICE

1. An electrical wiring device comprising:a housing assembly including a plurality of terminals at least partially disposed therein, the plurality of terminals being configured to be coupled to an AC power source and at least one electrical load;
a sensor element coupled to the plurality of terminals and configured to provide a sensor signal for monitoring at least one load power parameter of the at least one electrical load;
at least one variable control mechanism coupled to the housing assembly, the at least one variable control mechanism being configured to adjustably select a user adjustable load setting, the user adjustable load setting being adjustable between a minimum setting and a maximum setting;
at least one series pass element coupled between the AC power source and at least one electrical load, the at least one series pass element being configured to provide output power to the at least one electrical load in accordance with the user load setting, the output power being less than or equal to the AC power; and
a regulation circuit coupled to the sensor element and the at least one series pass element, the regulation circuit being configured to enter an automatic calibration mode when AC power is applied to at least a portion of the plurality of terminals, when in the automatic calibration mode the regulation circuit being configured to direct the at least one series pass element to provide a plurality of output power levels to the at least one load while monitoring the at least one load power parameter, the regulation circuit being configured to identify a load type based on variation in the at least one load power parameter in response to the plurality of output power levels, the regulation circuit selecting at least one calibration value based on the identified load type, the at least one selected calibration value corresponding to at least one setting between and including the minimum setting or the maximum setting.

US Pat. No. 10,340,691

RACK POWER DISTRIBUTION VIA MODULAR, EXPANDABLE BUS BAR FOR MODULAR AND SCALABLE/EXPANDABLE INFORMATION HANDLING SYSTEM

Dell Products, L.P., Rou...

1. A rack-based information handling system (IHS), comprising:a rack having a modular structure that supports insertion from a front of the rack of different numbers and sizes of information technology (IT) gear to create one or more IT nodes, the rack vertically provisioned into an upper standard zone, a switch zone, and a lower standard zone, the switch zone designed with at least one switch bay and at least one power bay, each of the at least one switch bay and the at least one power bay configured to enable insertion of a fill-width chassis, the upper standard zone and the lower standard zone each divided into tiers by shelves, the shelves including full-width shelfs providing full-width IT bays for insertion of full-width IT nodes and shelves including partitions defining partial-width bays for insertion of multiple side-by-side partial-width IT nodes;
a power bay chassis having an exterior casing and configured as a full width IT node for insertion into one of the at least one power bay chassis of the switch zone, the exterior casing presenting a volumetric enclosure with opposed side panels, a top and a bottom panel, and a back and a front side, the power bay chassis being a separate physical component from other IT nodes within the rack, the power bay chassis further comprising, within the volumetric enclosure, a plurality of power supply units that electrically connects to an alternating current (AC) switch to receive AC power, a power controller, and a power distribution unit (PDU) having a positive distribution conductor and a negative distribution conductor directed toward a rear of the rack, the PDU electrically connected to the one or more PSUs to receive direct current (DC) electrical power; and
a modular busbar assembly attached to the rear of the rack, the modular busbar assembly comprising (i) a first positive and a first negative vertical busbar segment extending vertically along a rear of the rack and in direct electrical connection, respectively, to the positive distribution conductor and to the negative distribution conductor of the PDU and spanning one or more nodes inserted into the rack to provide hot pluggable electrical power to an aft-directed connection of an IT node inserted into the rack and (ii) second, separate, positive and negative vertical busbar segments modularly attached to the first positive and negative vertical busbar segments, respectively, to electrically connect with the positive and negative distribution conductor, respectively, of the PDU, the second, separate positive and negative vertical busbar segments extending vertically and spanning at least one additional node that is vertically adjacent to the one or more nodes powered by the first positive and negative busbar segments to provide electrical power to the additional adjacent nodes.

US Pat. No. 10,340,690

INTERFERENCE SUPPRESSION STAGE AND POWER SUPPLY

Robert Bosch GmbH, Stutt...

1. An interference suppression stage (12) of a power supply (2), the interference suppression stage (12) comprising:an input (14) connected to an input module (4) of the power supply (2), the input module (4) connected to an electrical supply system (6),
an output (16) connected to an output module (8) of the power supply (2), the output module (8) connected to an electrical load (10),
at least two power paths (18a-c) connected in parallel between input (14) and output (16), wherein each of the power paths (18a-c) are configured to be switched between an active state (A) and an inactive state (I),
a control unit (20) configured to switch at least one of the power paths (18a-c) to the inactive state (I) in a saving mode (S),
wherein the control unit (20) switches different power paths (18a-c) alternately in time to inactive (I) in saving mode (S),
wherein the saving mode (S) is activated when the electrical current (E) flowing through the interference suppression stage (12) is below a limit current (G).

US Pat. No. 10,340,689

SYSTEM AND METHOD FOR POWER MANAGEMENT

NXP B.V., Eindhoven (NL)...

1. A power management device, comprising:a first port configured to be coupled to a first power source;
a second port configured to be coupled to a second power source;
a switched capacitor converter;
an inductor coupled in parallel with a switch;
wherein the switched capacitor converter is coupled between the first port and one end of the inductor coupled in parallel with the switch;
wherein another end of the inductor coupled in parallel with the switch, is coupled to the second port;
a first power controller configured to regulate power transfer between the first power source and the second power source using commands sent to the first power source; and
a second power controller configured to regulate power transfer between the first power source and the second power source using commands sent to the switch.

US Pat. No. 10,340,684

VOLTAGE DERIVATIVE AND ZERO-SEQUENCE BROKEN CONDUCTOR DETECTION

Schweitzer Engineering La...

1. A system for detecting a broken conductor, comprising:a plurality of circuit breakers in electrical communication with a conductor, wherein each circuit breaker is configured to open and close an electrical path of the conductor;
a plurality of intelligent electronic devices in communication with the plurality of circuit breakers and the conductor, such that each circuit breaker is in communication with at least one intelligent electronic device,
wherein each intelligent electronic device is configured to obtain electrical measurements from the conductor, determine phasor data from the measurements, and transmit the phasor data; and
a central controller device in communication with the plurality of intelligent electronic devices configured to receive the phasor data from the plurality of intelligent electronic devices and use the received phasor data to detect a broken conductor condition of the conductor by comparing a rate of change of voltage from the phasor data of each of the plurality of intelligent electronic devices.

US Pat. No. 10,340,680

METHOD AND DEVICE FOR SHUTTING DOWN AN INSTALLATION PART EXHIBITING AN INSULATION FAULT IN AN UNGROUNDED POWER SUPPLY SYSTEM

6. A device for shutting down an installation part (6) provided with connected equipment in an ungrounded power supply system (2) in case of an insulation fault in a direct-current circuit (8) connected to the installation part (6) to be shut down, comprising an insulation monitoring device (20) for determining an insulation resistance (Riso) of the ungrounded power supply system (2), characterized in that the insulation monitoring device (20) comprises a voltage measuring device (26) for determining a displacement direct voltage (Uv) between a respective outer conductor of the ungrounded power supply system (2) and ground and an evaluating device (28) for combined evaluation of the insulation-resistance value (Riso) and the displacement direct voltage (Uv).

US Pat. No. 10,340,677

FLEXIBLE ELECTRICAL CONTACT MODULE

NDI Engineering Company, ...

1. A system for conducting electricity, the system comprising a first body, a second body configured to move relative to the first body in a primary movement direction, and one or more electrical contact modules disposed between and in contact with the first body and the second body, each electrical contact module comprising:a plurality of laminations, each lamination comprising a metal sheet having a central longitudinal portion aligned on a first plane, a first plurality of fingers extending outward from the central longitudinal portion and aligned on a second plane angled relative to the first plane at a first angle, and a second plurality of fingers extending outward from the central longitudinal portion and aligned on a third plane angled relative to the first plane at an angle supplementary to the first angle, such that the lamination has an arrow shape from an end view, each pair of longitudinally adjacent fingers separated from one another by a gap; and
at least a first clamping bar and a second clamping bar parallel to the central longitudinal portions of the plurality of laminations and disposed to compressively hold the plurality of laminations together in a stack disposed between the clamping bars along a clamping axis disposed orthogonal to the primary movement direction, each lamination separated from an adjacent lamination in the stack by a shim having a thickness that defines a space between parallel fingers of the adjacent laminations.

US Pat. No. 10,340,674

REVERSIBLE CABLE SUPPORT BAR

1. A cable management tool, comprising: an elongated body portion having one or more sets of slots configured to be filled with cable ties, wherein each set of slots of the one or more sets of slots has at least two slots with a same shape; a first part extending from a first end of the body portion and configured to be attached to a chassis, wherein the first part includes: a first arm portion having a first length, a first U-shape slot on a first end of the first arm portion, a second U-shape slot on a second end of the first arm portion, wherein the first U-shape slot and the second U-shape slot have their openings point at opposite directions, thereby forming a first H-shape, and are configured to enable vertical movement of the first arm portion, and the first end and the second end are opposite ends of the first arm portion; a second part extending from a second end of the body portion and configured to be attached to the chassis, wherein the second part includes: a second arm portion having a second length, a third U-shape slot on a first end of the second arm portion, a fourth U-shape slot on a second end of the second arm portion, wherein the third U-shape slot and the fourth U-shape slot have their openings point at opposite directions, thereby forming a second H-shape, and are configured to enable vertical movement of the second arm portion, and the first end and the second end are opposite ends of the second arm portion, wherein the one or more sets of slots include a first set of vertical pairs of slots and a second set of horizontal pairs of slots, wherein the first set of vertical pairs of slots and the second set of horizontal pairs of slots include a same number of pairs of slots.

US Pat. No. 10,340,671

CONDUCTOR COVER APPLICATOR WITH SPOOL

Cantega Technologies Inc....

1. An applicator for applying a conductor cover to a cable, the applicator comprising:a structural element comprising a hot stick;
a spool connected to rotate relative to the structural element;
the conductor cover, which is tubular and split longitudinally to define a first longitudinal edge and a second longitudinal edge, the conductor cover being resilient to assume a tubular conformation, with the second longitudinal edge curled over the first longitudinal edge to overlap a portion of an exterior surface of the conductor cover, in a lowest energy state of the conductor cover, the spool to storing the conductor cover in a pre-application state where the conductor cover is flattened against the resiliency of the conductor cover and wrapped more than one time around the spool with the first longitudinal edge and the second longitudinal edge of the conductor cover spread open and perpendicular to a spool axis; and
a lock attached to the structural element or the spool, the lock holding the conductor cover wrapped around the spool in the pre-application state, the applicator being configured to, during use, unwind the conductor cover from the pre-application state on the spool to curl the second longitudinal edge over the first longitudinal edge into the tubular conformation around the cable.

US Pat. No. 10,340,670

LOW VOLTAGE ELECTRICAL DISTRIBUTION INSTALLATION

SCHNEIDER ELECTRIC INDUST...

1. A low voltage electrical distribution installation comprising:at least one busbar linked electrically to a power supply busbar, or to an upstream protection switchgear, and to switchgears of an electrical equipment item,
wherein, for each of at least two bars, an insulating support configured to house said bar over substantially all of its length, each insulating support comprising a clip and a runner being configured to fix the respective insulating support to another adjacent insulating support, the number of insulating supports being able to be adapted to demand, each insulating support situated at the end of a group of insulating supports, being configured to be fixed to at least one upright belonging to a device housing the switchgear, via at least one crossmember extending substantially at right angles to the longitudinal direction of said corresponding bar, said at least one crossmember being fixed to the upright(s), and to said insulating support so as to offer total accessibility to the connection surface of the bar and such that the assembly comprising the upright(s), the crossmember(s) and the insulating supports housing the bars, forms a rigid assembly,
wherein said clip provided on each insulating support is integrated with the insulating support and configured to cooperate with a runner on an adjacent insulating support, and said runner provided on each insulating support is configured to cooperate with a clip on an adjacent insulating support.

US Pat. No. 10,340,669

POWER DISTRIBUTION LOOP WITH FLOW-THROUGH JUNCTION LOCATIONS

Amazon Technologies, Inc....

1. A data center comprising:computing rooms;
electrical rooms comprising electrical equipment configured to distribute electrical power to the computing rooms; and
an electrical power distribution loop electrically coupled to a utility power source, wherein the electrical power distribution loop comprises feed-through junction locations, each junction location comprising:
a bus connected at a first end and a second end to the electrical power distribution loop;
a tap electrically coupled to the bus between the first end and the second end; and
a disconnect switch electrically coupled downstream of the tap;
wherein a particular one of the junction locations is configured to flow electrical power while a particular one of the electrical rooms is being connected to or disconnected from the particular one of the junction locations, such that electrical power flow through the electrical power distribution loop to electrical rooms electrically coupled to other ones of the junction locations is not interrupted.

US Pat. No. 10,340,668

STACKABLE MODULE

1. A stackable module with a housing provided to hold an electric/electronic component and with a clamping device for attaching to a support rail,wherein the clamping device has two latching/gripping hooks, which are displaceable in mutually opposite directions between an open position and a fastening position,
and a force deflection mechanism to adjust the latching/gripping hooks between the open position and the fastening position, that is actuable by means of an actuating element, and able to be subjected to an actuating force from an outer side,
wherein the latching/gripping hooks bound a free opening distance which, for release fastening to the support rail, is greater in the open position and smaller in the fastening position than a provided support rail extent, and
wherein the force deflection mechanism has an actuating-element-side deflection profile and a hook-side displacement part, which has a deformation portion which is deformable by a displacement force in order to generate a hook-side displacement, wherein between the deflection profile and the deformation portion, a sliding contact is able to be formed, at which the deformation portion is able to be subjected to the displacement force via the deflection profile.

US Pat. No. 10,340,665

SPARK PLUG HAVING AN INCREASED TIGHTENING TORQUE

Robert Bosch GmbH, Stutt...

1. A spark plug, comprising:an insulator;
a casing including a sealing surface; and
a gasket which rests against the sealing surface;
wherein the sealing surface includes a plurality of recesses, wherein a form-locked connection is present between the recesses and the gasket.

US Pat. No. 10,340,664

CORONA IGNITION DEVICE

BorgWarner Ludwigsburg Gm...

1. A corona ignition device, comprising:a central electrode;
an insulator in which the central electrode sits;
a coil connected to the central electrode;
a housing which holds the insulator and surrounds the coil;
a cover which closes the housing at an end facing away from the insulator; and
a spring arranged between the cover and the coil, wherein the spring comprises a metal plate having spring lugs.

US Pat. No. 10,340,663

QUANTUM CASCADE LASER

SHARP KABUSHIKI KAISHA, ...

1. A quantum cascade laser comprising:a semiconductor substrate; and
an active layer that is disposed on the semiconductor substrate and has a cascade structure, in which a plurality of unit layered bodies, each composed of a quantum well light emitting layer and an injection layer, are stacked such that the quantum well light emitting layers and the injection layers are alternately stacked,
wherein each of the plurality of unit layered bodies has a subband level structure having an upper laser emission level, a lower laser emission level, and a relaxation miniband that is composed of at least two energy levels which function as relaxation levels with an energy spacing smaller than the energy difference (EUL) between the upper laser emission level and the lower laser emission level,
the energy width (EMB) of the relaxation miniband is set to be smaller than the energy (ELO?EUL) obtained by subtracting the energy difference (EUL) between the upper laser emission level and the lower laser emission level from the energy (ELO) of longitudinal optical phonons (EMB light is generated due to intersubband transition of electrons from the upper laser emission level to the lower laser emission level in the quantum well light emitting layer, and
the electrons subjected to the intersubband transition are relaxed in the relaxation miniband included in the injection layer and are injected from the injection layer into a quantum well light emitting layer in the unit layered body at a subsequent stage.

US Pat. No. 10,340,662

QUANTUM CASCADE LASER

Sharp Kabushiki Kaisha, ...

1. A quantum cascade laser comprising:a first electrode;
a first contact layer that is in contact with the first electrode and is made of a first compound semiconductor;
a second electrode having a polarity opposite to that of the first electrode;
a second contact layer that is in contact with the second electrode and is made of a second compound semiconductor; and
an active layer disposed between the first contact layer and the second contact layer and including two or more active layer units, wherein
each of the active layer units includes one or more quantum well layers made of a third compound semiconductor and one or more barrier layers made of a fourth compound semiconductor, and each of the quantum well layers and each of the barrier layers are alternately stacked,
the third compound semiconductor is Alx3Iny3Ga(1-x3-y3)N (0?x3?1, 0?y3?1),
the fourth compound semiconductor is Alx4Iny4Ga(1-x4-y4)N (0?x4?1, 0?y4?1),
the fourth compound semiconductor has a band gap energy higher than that of the third compound semiconductor,
at least one of the barrier layers has a thickness of 1.8 nm or more, and
a main surface of each of the quantum well layers and a main surface of each of the barrier layers have an off-angle of ±1° with respect to a (1?100) orientation.

US Pat. No. 10,340,661

ELECTRO-OPTICAL DEVICE WITH LATERAL CURRENT INJECTION REGIONS

International Business Ma...

1. A lateral current injection electro-optical device comprising:an active region comprising a stack of III-V semiconductor gain materials stacked along a stacking direction z, the active region formed as a slab having two pairs of opposite, lateral surface portions, each extending parallel to said stacking direction z,
wherein the slab is a form factor, whereby a length of the slab is larger than a width thereof,
wherein said width, said length, and said stacking direction z are perpendicular; and
two paired elements, including:
a pair of doped layers of III-V semiconductor materials, including an n-doped layer and a p-doped layer,
wherein the p-doped layer and the n-doped layer are arranged on respective sides of the slab, contiguously with the opposite, lateral surface portions of one of said two pairs of lateral surface portions,
wherein a maximum length of each of the p-doped layer and the n-doped layer is less than a length of said opposite, lateral surface portions of said one of said two pairs, and
wherein each of the p-doped layer and the n-doped layer comprises, on a top surface portion thereof, a recess extending laterally along the slab and parallel to its length, so as for the active region and the contiguous pair of doped layers to have a rib waveguide configuration; and
a pair of lateral waveguide cores,
wherein the lateral waveguide cores are laterally butt-jointed to the opposite, lateral surface portions of the other one of said two pairs of surface portions, and
wherein the two paired elements are laterally arranged on opposite sides of the slab, the elements distinctly adjoining respective elements of the lateral surface portions of the slab such that the elements are separated from each other by the slab.

US Pat. No. 10,340,657

LASER DEVICE

1. A laser device, comprisinga tunable laser comprising a laser cavity and a laser control module placed outside the laser cavity,
wherein:
the tunable laser is configured to generate laser light having a center frequency,
the laser control module is configured to receive at least a portion of the laser light generated by the laser, to generate a control signal and to feed the control signal back to the laser for stabilizing the frequency, and
the laser control module comprises an interferometer comprising interferometer mirrors and a tunable interferometer length, wherein the interferometer length is tunable by an actuator arranged between the interferometer mirrors and by thermal variation.

US Pat. No. 10,340,656

SEMICONDUCTOR LASER SOURCE

1. A semiconductor laser source able to emit at least one optical signal of wavelength ?Li, said laser source comprising:a substrate made of silicon extending mainly in a plane called the “plane of the substrate”;
a structured layer formed on an upper face of the substrate made of silicon and having an upper face on the opposite side to the substrate made of silicon, said structured layer comprising:
a passive optical component chosen from a group consisting of an optical reflector and a waveguide, said passive optical component being encapsulated in silica or produced on a silica layer; and
at least one pad extending from a lower face, making direct contact with the substrate made of silicon, to an upper face flush with the upper face of the structured layer, said pad being made entirely from a material the thermal conductivity at 20° C. of which is higher than the thermal conductivity at 20° C. of silica, in order to form a thermal bridge through the structured layer; and
an optical amplifier made of III-V material configured, when supplied with power, to amplify the optical signal of wavelength ?Li, said optical amplifier being bonded directly, by direct bonding, to the upper face of the structured layer so that the optical signal amplified by the optical amplifier is reflected or guided by said passive optical component, said optical amplifier being bonded directly, by direct bonding, at least partially to the upper face of the pad in order to dissipate heat generated by the optical amplifier to the substrate made of silicon, wherein
the pad is produced from silicon nitride, and
the passive optical component is disposed directly below, in a direction perpendicular to the plane of the substrate, the optical amplifier and is narrower than the optical amplifier in a dimension parallel to the plane of the substrate.

US Pat. No. 10,340,652

LASER DEVICE AND METHOD FOR DRIVING LASER DEVICE

LUTRONIC CORPORATION, Go...

1. A laser apparatus, comprising:a pumping laser supply unit emitting a pumping laser having a nano-second pulse width; and
a laser output unit disposed on one side of the pumping laser supply unit and generating an output laser pumped by the pumping laser to have a nano-second pulse width corresponding to the pulse width of the pumping laser,
wherein the laser output unit comprises an output laser medium that comprises Er:YAG and the pumping laser supplied to the laser output unit has a wavelength of 630-670 nm.

US Pat. No. 10,340,649

C-BAND AND L BAND AMPLIFIER DESIGN WITH INCREASED POWER EFFICIENCY AND REDUCED COMPLEXITY

NEC CORPORATION, Tokyo (...

1. An improved optical transmission system for carrying C-band and L-band optical signals, the system having a C-band optical path including a C-band optical amplifier and an L-band optical path including an L-band optical amplifier, wherein the C-band optical path and the L-band optical path are substantially isolated from one another, said system including an input optical path and an optical circulator, said input optical path in optical communication with the optical circulator, the circulator in further optical communication with the C-band optical path and the L-band optical path, said system including an output optical path and a second circulator, said second optical circulator in optical communication with the C-band optical path at a point in the path after the C-band optical amplifier, said second optical circulator in optical communication with the L-band optical path at a point in the path before the L-band optical amplifier, and said optical circulator in optical communication with the output path,said system CHARACTERIZED IN THAT:the system is configured such that a pre-determined amount of C-band optical energy is applied to an input of the L-band optical amplifier;
the amount of C-band optical energy applied to the input is the L-band optical amplifier is more than 1% but less than 10% of the total C-band optical energy and is between 5 to 25 dB less than the power level of an L-band signal input to the L-band optical amplifier;
the optical circulator is configured to apply the pre-determined amount of C-band optical energy to the L-band optical path such that it is received by the L-band optical amplifier;
the optical circulator directs a portion of the C-band optical energy output from the C-band optical amplifier to an input of the L-band optical amplifier; and
no optical isolators are interposed between the circulators and the amplifiers.

US Pat. No. 10,340,648

CABLE CONNECTOR CLOCKING DEVICE AND RELATED COMPONENTS, SYSTEMS, AND METHODS

Lockheed Martin Corporati...

1. A clocking assembly for cable connectors comprising:at least one socket adapter sub-assembly comprising:
a socket portion having a first end and a second end, wherein the first end is configured to be connected to a cable connector;
an adapter portion comprising:
a generally cylindrical body portion having a first end and a second end, wherein the second end of the socket portion is connected to the first end of the cylindrical body portion; and
at least one indicium proximate to the first end of the cylindrical body portion configured to indicate a clock angle of the cable connector when the cable connector is connected to the socket portion; and
a fastener fixedly securing the socket portion to the adapter portion, the fastener extending through an opening in the cylindrical body portion of the adapter portion, the fastener comprising a spindle portion having a first non-circular cross-section and the opening in the cylindrical body portion having a second non-circular cross-section configured to prevent rotation of the fastener with respect to the adapter portion; and
an adapter holder sub-assembly comprising:
at least one clamp portion configured to receive the adapter portion of the socket adapter sub-assembly within the at least one clamp portion; and
a face portion having a plurality of indicia indicative of different clock angles, wherein:
the at least one clamp portion has an unclamped configuration, in which the at least one socket adapter sub-assembly is rotatable to align the indicium of the adapter portion with an indicium of the plurality of indicia of the face portion; and
the at least one clamp portion has a clamped configuration, in which the at least one socket adapter sub-assembly is retained with the indicium of the adapter portion aligned with an indicium of the plurality of indicia of the face portion.

US Pat. No. 10,340,644

ELECTRIC VEHICLE CHARGING CONNECTOR DEVICE AND A PLUG CONNECTOR AND A RECEPTACLE CONNECTOR THEREOF

CHENG UEI PRECISION INDUS...

1. An electric vehicle charging connector device and a plug connector and a receptacle connector thereof, wherein the plug connector is docked with the receptacle connector, wherein:the plug connector includes:
a first insulating body having a first outer ring base and a first inner ring base inside the first outer ring base, the first inner ring base protruding towards the first outer ring base to form a plurality of columns extending longitudinally, each two of the plurality of the columns defining a guiding groove therebetween;
a first circuit board disposed at a side of the first insulating body and having a plurality of first through holes each located corresponding to the guiding groove;
a plurality of contact terminals each inserted in the guiding groove and in each of the plurality of the first through holes of the first circuit board;
a first electrode unit disposed inside the first insulating body, and including a first conducting sleeve and a second conducting sleeve, the first conducting sleeve being positively charged, the second conducting sleeve being negatively charged; and
a first jumper unit electrically connected with the first electrode unit and including a first jumper body and a second jumper body, the first jumper body being riveted to the first conducting sleeve and the second jumper body being riveted to the second conducting sleeve;
the receptacle connector includes:
a second insulating body having a second outer ring base and an inner side of the second outer ring base defined with an outer ring groove, a retaining wall rising from a middle of the outer ring groove, the retaining wall extending laterally to form a stair surface, a plurality of slits disposed on the stair surface;
a second circuit board disposed at a side of the second insulating body and having a plurality of second through holes located corresponding to the plurality of the slits;
a plurality of docking terminals each abutting on the retaining wall and inserted in each of the plurality of the second through holes of the second circuit board through each of the plurality of the slits;
a second electrode unit disposed inside the second insulating body, and including a third conducting sleeve and a fourth conducting sleeve, the third conducting sleeve being negatively charged, the fourth conducting sleeve being positively charged; and
a second jumper unit electrically connected with the second electrode unit and including a third jumper body and a fourth jumper body, the third jumper body being riveted to the third conducting sleeve and the fourth jumper body being riveted to the fourth conducting sleeve.

US Pat. No. 10,340,639

SHIELD SHELL AND SHIELDED CONNECTOR

YAZAKI CORPORATION, Toky...

1. A shield shell comprising:a housing accommodation portion that includes a shell fixing portion configured to be fixed to a conductive mounting target and that is configured to accommodate a housing; and
a shield member mounting portion that is formed so as to be continuous to the housing accommodation portion and that has an outer surface on which a shield member is mounted by fastening of a binding member,
wherein a fastening position aligning unit is provided on an entire circumference or at a plurality of positions of the outer surface of the shield member mounting portion;
wherein the fastening position aligning unit includes an inclined portion and a restricting portion;
wherein the inclined portion is inclined in a tapered shape from a base end side of the shield member mounting portion toward an open end side of the shield member mounting portion; and
wherein the restricting portion is continuous to a lowest portion of the inclined portion and restricts the binding member from moving toward the open end side of the shield member mounting portion when the shield member is pulled toward the open end side of the shield member mounting portion,
wherein the restricting portion intersects the inclined portion at an acute angle.

US Pat. No. 10,340,638

SHIELDED AND MULTISHIELDED COAXIAL CONNECTORS

Holland Electronics, LLC,...

1. A coaxial connector for passing signals similar to those passed by F-Type connectors, the connector comprising:a body, an electrical contact, and a metallic waveguide;
the body including a connection that incorporates the electrical contact;
the electrical contact aligned along a body centerline and electrically isolated from the body; and,
the waveguide fixed within the body and the body centerline passes through a central aperture of the waveguide;
wherein the waveguide faces the electrical contact and is configured to limit entry of stray RF signals into a body region that includes the electrical contact.

US Pat. No. 10,340,637

ELECTRICALLY CONDUCTIVE SUPPORT SURFACE AND RELATED METHODS

1. Apparatus for electrically grounding a portable mat and electrically connecting the mat to at least one other electrically-conductive component, the mat having a top and a bottom and configured to be deployed on or near the surface of the earth, the apparatus comprising:a cover constructed at least partially of electrically-conductive material, said cover being configured to be attached to the mat sufficient to prevent said cover from separating from the mat during use thereof, said cover including metallic, liquid permeable grating configured to extend at least partially across the top of the mat and be electrically grounded to the earth; and
at least one electrically-conductive interface configured to facilitate electrical connection of said cover to at least one other electrically-conductive component.

US Pat. No. 10,340,636

ELECTRIC PLUG LOCKERS

1. A device, comprising:a male connector comprising:
a first loop portion with a first opening operable to expand to fit over a first head of a first power cord;
a first neck with a proximal end connected to the first loop portion and a distal end connected to a male fastener, wherein the first loop portion and the first neck are elastic material; and
the male fastener; and
a female connector comprising:
a second loop portion with a second opening operable to expand to fit over a second head of a second power cord;
a second neck with a proximal end connected to the second loop portion and a distal end connected to a female fastener, wherein the second loop portion and the second neck are the elastic material; and
the female fastener, wherein the female fastener is configured to connect to the male fastener of the male connector.

US Pat. No. 10,340,634

APPARATUS FOR EJECTING AT LEAST ONE INTEGRATED CIRCUIT CARD

Microsoft Technology Lice...

1. An apparatus comprising:a housing;
a tray connected to the housing in a movable manner, the tray having a retracted closed position and an ejected open position with respect to the housing;
an ejector configured to eject the tray to the ejected open position, the ejector having a first position and a second position, wherein the ejector is configured to receive an external force to eject the tray to the ejected open position and maintain the second position even when the external force is removed; and
a switch movable into a first electric position and a second electric position, the switch comprising a first electric contact element and a second electric contact element;
wherein the ejector is configured to receive the external force at the first electric contact element to move the first electric contact element into contact with the second electric contact element to consequently close the switch, and the ejector is configured to maintain the switch in the first electric position in response to the ejector being moved to the second position and to cause the ejection of the tray to the ejected open position.

US Pat. No. 10,340,632

ELECTRICAL CONNECTOR ASSEMBLY WITH STAGED RELEASE

Lear Corporation, Southf...

1. An electrical connector assembly comprising:a first connector including a first electrical terminal;
a second connector including a second electrical terminal, the first connector and the second connector being movable from a mated position toward an unmated position, the second connector including a first block, a second block, and a third block; and
a connector position assurance that is movable between an assurance position and a pre-lock position, the connector position assurance including a stop tab, wherein:
the first block is positioned to engage the stop tab when the connector position assurance is located in the pre-lock position;
the second block is positioned to engage the stop tab when the first connector is located a first distance from the second connector; and
the third block is positioned to engage the stop tab when the first connector is located a second distance from the second connector.

US Pat. No. 10,340,628

CAP FOR COVERING A PLUG OPENING

Appleton Grp LLC, Rosemo...

1. A cap for covering a plug opening, said cap comprising:a first recessed portion having a cross section complementary to a cross section of said plug opening, wherein a first operative end of said first recessed portion is configured to fit into said plug opening;
a sealing lip configured on an exterior surface of the first recessed portion to allow tight fitment of said first recessed portion within an interior of said plug opening;
a top lid configured on said first recessed portion, said top lid and said first recessed portion adapted to prevent ingress of foreign particles to said plug;
a lanyard extending from said first recessed portion;
a ring configured at a free end of said lanyard, said ring adapted to be fitted on a body of said plug, said lanyard and said ring allowing said cap to remain attached to said plug in the configuration when said first recessed portion is fitted on or not fitted on said plug; and
further including a second recessed portion co-axially extending from an opposite operative surface of said top lid from the first recessed portion.

US Pat. No. 10,340,626

CONNECTOR MOUNTING STRUCTURE

Sumitomo Wiring Systems, ...

1. A connector mounting structure that uses a bolt for mounting a connector housing made of synthetic resin on a case made of metal, comprising:a tubular metal member including a bolt insertion hole, the bolt being inserted through the bolt insertion hole, the metal member being configured to contact a seating surface of a head of the bolt with the bolt tightened;
wherein:
the connector housing has an integral mounting piece with an insertion hole through which the bolt and the metal member are inserted; and
a groove extends circumferentially around an edge of the bolt insertion hole in the case and a rubber ring is provided in the groove and sandwiched between the case and the mounting piece.

US Pat. No. 10,340,598

LOOP ANTENNA ARRAY

Nippon Telegraph and Tele...

1. A plurality of loop antenna arrays, comprising:a plurality of loop antennas, wherein
the number of the plurality of loop antennas is 2 to the n-th power (n is an integer of 2 or more) and a group of 2 to the (n?1)-th power of the plurality of loop antennas is a unit loop antenna array;
centers of the plurality of loop antennas are arranged on a same straight line segment;
a direction of a current flowing through a loop antenna positioned at one end side of the same straight line segment in one of the unit loop antenna arrays and a direction of a current flowing through a loop antenna positioned at the one end side in another of the unit loop antenna arrays are opposite from each other;
the plurality of loop antennas comprise two loop antennas through which currents flow in opposite directions from each other, the two loop antennas arranged so that a straight line distance between centers of the two loop antennas is shorter than twice a distance from a center point between the centers to a communication area boundary, which is a magnetic field strength contour that allows a terminal device to communicate, through a point having a distance in a direction passing through the loop antenna; and
the two loop antennas have the same shape while positions of the centers of the two loop antennas are different.

US Pat. No. 10,340,597

KIT FOR FACILITATING TRANSMISSION OF WIRELESS LOCAL-AREA NETWORK RADIO SIGNALS OVER A PRE-EXISTING COAXIAL CABLE DISTRIBUTION NETWORK

1. A kit for facilitating transmission of wireless local-area network (LAN) radio signals over a pre-existing coaxial cable distribution network, the kit comprising:a splitter comprising at least one input port and a plurality of output ports, wherein the at least one input port is configured to be communicatively coupled with at least one external antenna connector of a wireless LAN router, wherein the plurality of output ports is configured to be communicatively coupled to a plurality of cables of the cable distribution network, wherein the splitter is configured to provide a plurality of bidirectional signal pathways between the at least one input port and the plurality of output ports, wherein an operating frequency range of the plurality of bidirectional signal pathways matches at least one frequency band of the wireless LAN radio signals;
a cable impedance matching unit coupled to the at least one external antenna connector of the wireless LAN router, wherein the cable impedance matching unit is configured to match an output port impedance of the at least one external antenna connector with a cable impedance of the plurality of cables;
at least one attenuator, wherein a first end of at least one attenuator is configured to be communicatively coupled to at least one output port of the plurality of output ports, wherein a second end of the at least one attenuator is configured to be communicatively coupled to at least one cable of the plurality of cables, wherein the at least one attenuator is configured to provide delay equalization and a predetermined common attenuation across the plurality of cables; and
a plurality of antennas corresponding to a plurality of terminal ends of the cable distribution network, wherein an antenna of the plurality of antennas comprises:
an antenna element configured to perform wireless transmission and reception of the wireless LAN radio signals;
an antenna connector configured to be communicatively coupled to a terminal connector associated with a terminal end of the plurality of terminal ends; and
an antenna impedance matching unit configured to match an antenna impedance of the antenna element with a cable impendence of the terminal connector.

US Pat. No. 10,340,569

MULTIPLEXER AND LOW PASS FILTER FOR MULTIPLEXER

1. A multiplexer through which different frequency bands pass comprising:a housing that includes an I/O terminal and a channel group which inputs and/or outputs frequencies of different ranges, includes a plurality of connectors, and is separated from the I/O terminal;
a low-pass filter provided inside the housing, electrically connected to the I/O terminal, and formed of a distributed constant type;
a common capacitor provided in parallel to the low-pass filter and electrically connected to a contact point between the I/O terminal and the low-pass filter; and
a cavity filter which includes a plurality of cavities which are formed in the housing and a resonator which is respectively installed in the cavities,
wherein a part of the cavity filter is electrically connected between the low-pass filter and a part of the channel group, and
wherein the other part of the cavity filter is electrically connected between the common capacitor and the other part of the channel group.

US Pat. No. 10,340,567

MICROWAVE SWITCHING DEVICE WITH THE STATE OF THE CONNECTIONS OF THE INPUTS AND OUTPUTS BEING READ BY TELEMETRY

THALES, Courbevoie (FR)

1. A microwave switching device comprising:a switching matrix with M inputs and N outputs comprising at least one surface-mount microwave switch with ohmic contacts with at least one input and at least one output position;
a control bus for the one or more microwave switches of the switching matrix;
a remote-control bus for the M inputs;
a telemetry bus for the N outputs;
a bias tee positioned on each input of the switching matrix; and
a bias tee positioned on each output of the switching matrix.

US Pat. No. 10,340,550

LITHIUM ION SECONDARY CELL

NEC ENERGY DEVICES, LTD.,...

1. A lithium ion secondary cell comprising a positive electrode active material layer containing lithium manganese-based oxide as a positive electrode active material, a negative electrode active material layer containing a negative electrode active material, and an electrolytic solution used to immerse the positive electrode active material layer and the negative electrode active material layer,wherein the positive electrode active material layer comprises carbon nanotubes and the electrolytic solution comprises sulfonic acid ester in amount of not less than 0.1% by mass and not more than 6.0% by mass with respect to the total mass of the solvent and the sulfonic acid ester,
wherein a surface of the positive electrode active material layer is covered in a ratio not less than 40% and not more than 90% of a surface area with the carbon nanotubes having a mean D/G ratio, measured by Raman spectroscopy, of not less than 0.3 and not more than 0.6, the outermost cylinder of carbon nanotubes has a diameter of not less than 0.5 nm and not more than 50 nm,
wherein solid electrolyte interface films cover the surface of the positive electrode active material, and
wherein the solid electrolyte films are obtained during an initial charge of the cell by decomposition of the sulfonic acid ester through a catalytic function of the carbon nanotubes.

US Pat. No. 10,340,527

LITHIUM-ION SECONDARY BATTERY AND METHOD OF MANUFACTURING THE SAME

HITACHI CHEMICAL COMPANY,...

1. A lithium-ion secondary battery comprising:a positive electrode including a positive current collector and a sulfur-based positive active material containing at least sulfur (S);
a negative electrode including a negative current collector and a silicon-based negative active material containing at least silicon (Si) or a tin-based negative active material containing tin (Sn); and
a separator, wherein:
the positive current collector is made of an aluminum perforated foil having a plurality of through holes formed to pierce the foil from a front surface to a back surface thereof;
the negative current collector is made of a copper foil having a plurality of through holes; and
the positive electrode and the negative electrode are stacked via the separator;
the through holes formed in the aluminum perforated foil and the through holes formed in the copper foil each have a density of 1×104 holes/m2 or more and a hole opening rate of 3 to 50%; and
when the respective average inside diameters of the through holes formed in the aluminum perforated foil and the through holes formed in the copper foil are defined as R (?m), the respective hole opening rates of the aluminum perforated foil and the copper foil are indicated by the following expression:

US Pat. No. 10,340,451

SWITCHING ELEMENT HAVING OVERLAPPED WIRING CONNECTIONS AND METHOD FOR FABRICATING SEMICONDUCTOR SWITCHING DEVICE

NEC CORPORATION, Minato-...

1. A switching element comprising:a first variable resistance element comprising a first input/output terminal and a first connection terminal;
a second variable resistance element comprising a second input/output terminal and a second connection terminal;
a rectifying element comprising a control terminal and a third connection terminal;
a first wiring connected to the first input/output terminal of the first variable resistance element;
a second wiring connected to the second input/output terminal of the second variable resistance element; and
a third wiring connected to the control terminal of the rectifying element, wherein
the first connection terminal, the second connection terminal and the third connection terminal are interconnected,
one of the first wiring and the second wiring overpasses another of the first wiring and the second wiring,
one of the first wiring and the second wiring is a horizontal line commonly connecting a plurality of first input/output terminals of first variable resistance elements, comprising the first variable resistance element, arranged in a horizontal direction,
the another of the first wiring and the second wiring is a vertical line commonly connecting a plurality of second input/output terminals of second variable resistance elements, comprising the second variable resistance element, arranged in a vertical direction,
the third wiring is a diagonal line commonly connecting a plurality of control terminals of rectifying elements, comprising the rectifying element, arranged in a diagonal direction, and has a folded structure comprising another diagonal line commonly connecting at least one of other control terminals of at least one of other rectifying elements arranged in the diagonal direction located differently from the plurality of control terminals of the rectifying elements, and
the third wiring is configured to be connected to a programming line.

US Pat. No. 10,340,449

RESISTIVE MEMORY DEVICE CONTAINING CARBON BARRIER AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A resistive memory device comprising at least one resistive memory element, wherein the at least one resistive memory element comprises;a carbon barrier material portion; and
a layer stack that is disposed between a first electrode and a second electrode, wherein the layer stack comprises:
a first interfacial metal oxide layer;
a resistive memory material portion in direct contact with a surface of the first interfacial metal oxide layer; and
a second interfacial metal oxide layer in direct contact with a surface of the resistive memory material portion,
wherein the carbon barrier material portion directly contacts the first interfacial metal oxide layer,
wherein the carbon barrier material portion directly contacts the first electrode, and
wherein:
the first electrode comprises a pillar shaped conductive material portion that contacts a first electrically conductive line that extends along a first direction;
the second electrode comprises a portion of a second electrically conductive line that extends along a second direction that is different from the first direction; and
the carbon barrier material portion and the resistive memory material portion are located at a region in which the pillar shaped conductive material portion and the second electrically conductive line have a minimum spacing therebetween.

US Pat. No. 10,340,446

SEMICONDUCTOR STRUCTURE MULTILAYERS HAVING A DUSTING MATERIAL AT AN INTERFACE BETWEEN A NON-MAGNETIC LAYER AND A MAGNETIC LAYER

International Business Ma...

1. A method of forming a semiconductor structure, comprising:forming a multilayer stack of two or more multilayers disposed over a seed layer, each of the two or more multilayers comprising:
a magnetic layer; and
an additional layer disposed over a top surface of the magnetic layer;
wherein the additional layer is non-magnetic, the additional layer comprising a first non-magnetic material and a dusting material comprising a second non-magnetic material different than the first non-magnetic material; and
wherein the multilayer stack provides a reference layer of a perpendicular magnetic tunnel junction stack.

US Pat. No. 10,340,436

THERMOELECTRIC ELEMENT, THERMOELECTRIC MODULE, AND HEAT CONVERSION APPARATUS INCLUDING THE SAME

LG INNOTEK CO., LTD., Se...

1. A thermoelectric module comprising:a first substrate;
a thermoelectric element disposed on the first substrate; and
a second substrate disposed on the thermoelectric element,
wherein the thermoelectric element comprises:
a first element portion disposed on the first substrate and having a first cross-sectional area;
a connection portion connected to the first element portion; and
a second element portion connected to the connection portion, disposed between the connection portion and the second substrate, and having a second cross-sectional area;
wherein the connection portion has a third cross-sectional area,
wherein the third cross-sectional area is smaller than at least one of the first cross-sectional area and the second cross-sectional area,
wherein the first cross-sectional area increases as the first element portion is distanced from the connection portion,
wherein the second cross-sectional area increases as the second element portion is distanced from the connection portion,
wherein the first element portion and the second element portion each is formed with two protrusions protruding toward the connection portion and a recess between the two protrusions recessing toward the corresponding first or second substrate, and
wherein the first element portion, the second element portion, and the connection portion are formed from stacked unit members and each of the stacked unit members are formed of the same material.

US Pat. No. 10,340,433

LIGHT EMITTING DEVICE

LG INNOTEK CO., LTD., Se...

1. A light emitting device comprising:a body having a cavity;
first and second lead frames disposed in the cavity;
a third lead frame disposed in the cavity and disposed between the first and second lead frames;
a fourth lead frame disposed in the cavity, disposed between the first and second lead frames, and spaced apart from the third lead frame;
a first light emitting chip disposed on the first lead frame; and
a second light emitting chip disposed on the second lead frame,
wherein the body includes: first and second lateral sides disposed in opposition to each other; and third and fourth lateral sides disposed in opposition to each other,
wherein the first lead frame includes a first lead part protruding through the first lateral side of the body and a second lead part protruding through the second lateral side of the body,
wherein the second lead frame includes a third lead part protruding through the first lateral side of the body and a fourth lead part protruding through the second lateral side of the body,
wherein the third lead frame includes a fifth lead part protruding through the first lateral side of the body,
wherein the fourth lead frame includes a sixth lead part protruding through the second lateral side of the body,
wherein top surfaces of the first, second, third and fourth lead frames are disposed on a bottom of the cavity,
wherein respective bottom surfaces of each of the first, second, third and fourth lead frames are exposed to a bottom of the body,
wherein, in the body, the first and second lateral sides have respective lengths longer than respective lengths of the third and fourth lateral sides,
wherein the fifth lead part of the third lead frame is disposed between the first lead part of the first lead frame and the third lead part of the second lead frame,
wherein the sixth lead part of the fourth lead frame is disposed between the second lead part of the first lead frame and the fourth lead part of the second lead frame,
wherein the first light emitting chip is electrically connected with the first and third lead frames,
wherein the second light emitting chip is electrically connected with the second and fourth lead frames, and
wherein the first and second light emitting chips are individually driven.

US Pat. No. 10,340,404

MULTILAYER FILM AND PHOTOVOLTAIC MODULE

LG Chem, Ltd., Seoul (KR...

1. A photovoltaic module, comprising:a photovoltaic cell; and
a multilayer film disposed below the photovoltaic cell,
wherein the multilayer film comprises a first layer disposed below the photovoltaic cell and including a first matrix resin and first inorganic particles having a band gap energy of 3.3 eV or more; and a second layer disposed below the first layer and including a second matrix resin and second inorganic particles having a band gap energy of less than 3.3 eV,
wherein the only inorganic particles present in the first layer are the first inorganic particles, and the only inorganic particles present in the second layer are the second inorganic particles,
wherein the first layer is disposed closer to incident light than the second layer,
wherein the first layer is directly stacked on the second layer,
wherein the multilayer film has a reflectance of 20.4% or more with respect to UV rays in a wavelength range of 280 to 400 nm, and a reflectance of more than 80% with respect to visible rays in a wavelength range of 400 to 1200 nm,
wherein the first inorganic particles are barium sulfate (BaSO4) and the second inorganic particles are titanium dioxide (TiO2),
wherein the first layer includes the first inorganic particles in an amount of 10 to 200 parts by weight with respect to 100 parts by weight of the first matrix resin, and the second layer includes the second inorganic particles in an amount of 10 to 200 parts by weight with respect to 100 parts by weight of the second matrix resin, and
wherein each of the first matrix resin and the second matrix resin is a mixture consisting of a copolymer of vinylidene fluoride and chlorotrifluoroethylene, a copolymer of vinylidene fluoride and hexafluoropropylene, and an acrylic polymer of methyl methacrylate, glycidyl methacrylate and methyl methacrylic acid.

US Pat. No. 10,340,400

PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING THE SAME, AND CAMERA

CANON KABUSHIKI KAISHA, ...

1. A photoelectric conversion device that includes a silicon substrate,wherein the silicon substrate includes a first portion configured to perform photoelectric conversion, and a second portion containing carbon, the second portion being arranged farther apart from a light receiving surface of the silicon substrate than the first portion,
wherein a carbon peak concentration in the second portion is 1×1018 [atoms/cm3] to 1×1020 [atoms/cm3], and
wherein an oxygen peak concentration in the second portion is 1/1000 to 1/10 of the carbon peak concentration.

US Pat. No. 10,340,397

OPTICAL SENSOR DEVICE

ABLIC Inc., (JP)

6. An optical sensor device, comprising:a die pad portion;
an optical sensor element disposed on the die pad portion;
a plurality of leads formed separately around the die pad portion;
a first resin molding portion holding a periphery of the die pad portion and first peripheries of the plurality of leads excluding a portion in which a surface of each of the plurality of leads used as a wire bonding portion is exposed after integration by contact fitting molding using a first resin; and
a second resin molding portion covering an entire periphery of the first resin molding portion, at least a part of an upper surface of the optical sensor element, and second peripheries of the plurality of leads by contact fitting molding using a second resin, the second resin molding portion having one of a resin with transparency, a resin containing a filler of finely pulverized glass having a first filter function, and a resin containing a dye or a pigment having a second filter function.

US Pat. No. 10,340,395

SEMICONDUCTOR VARIABLE CAPACITOR USING THRESHOLD IMPLANT REGION

QUALCOMM Incorporated, S...

18. A semiconductor variable capacitor comprising:a first non-insulative region disposed in a gate region above a first semiconductor region;
a second non-insulative region disposed above the first semiconductor region;
a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region; and
a control region disposed above a second semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region,
wherein the first semiconductor region is a retrograde well formed on a semiconductor substrate, and
wherein the Vt implant region is disposed directly on the first semiconductor region and has a same doping type as the first semiconductor region.

US Pat. No. 10,340,391

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

United Microelectronics C...

1. A method for fabricating a semiconductor device, comprising:forming an oxide semiconductor layer, over a substrate;
forming a metal nitride layer over the oxide semiconductor layer;
patterning the metal nitride layer to form a source electrode and a drain electrode of a metal nitride; and
forming a metal-nitride oxidation layer on a surface of the source electrode and the drain electrode,
wherein a metal plasma is provided under a power range of 5 kw to 15 kw and flashing of only N2 by a range of 30 sccm to 50 sccm for forming the metal nitride layer having reduced oxidation, thereby facilitating reduction of thickness of the metal-nitride oxidation layer to be equal to or less than 0.2 of a thickness of the drain electrode or the source electrode.

US Pat. No. 10,340,386

ELECTRONIC DEVICE INCLUDING LIGHT DETECTION DEVICE AND OPERATION METHOD THEREOF

Samsung Electronics Co., ...

1. An electronic device comprising:a housing;
a display exposed through a surface of the housing;
a light emitting unit configured to be disposed on at least a part of a rear surface of the display, and including at least one light source for outputting light of at least one wavelength band;
a light receiving unit configured to include at least one area for receiving light of the at least one wavelength band;
a light blocking element that blocks light output from the at least one light source, from entering a switch for turning on/off at least one pixel of the display;
a processor electrically connected with the display, the light emitting unit, and the light receiving unit; and
a memory electrically connected with the processor,
wherein the memory includes instructions configured to cause, when executed, the processor to output light through the at least one light source in a state where one or more pixels included in a specific area of the display, which includes an area covering the at least one light source, are turned off or displayed in a specific color.

US Pat. No. 10,340,369

TUNNELING FIELD EFFECT TRANSISTOR

GLOBALFOUNDRIES Inc., Gr...

1. A tunneling field effect transistor device comprising a drain region, a source region and a gate region, the device comprising:a semiconductor substrate;
a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above said substrate, said body having an axis that is oriented substantially perpendicular to an upper surface of said substrate, said body having two side surfaces and an upper surface, said body extending a full length of said drain region, said gate region and said source region, wherein said first semiconductor material is part of said drain region;
a second semiconductor material positioned above at least a portion of said gate region and above said source region, wherein said second semiconductor material defines said channel region;
a third semiconductor material positioned above said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material, wherein said third semiconductor material is part of said source region; and
a gate structure positioned above said first, second and third semiconductor materials in said gate region, wherein said gate structure includes a gate insulation layer and said third semiconductor material has an uppermost surface having a height greater than a height of an uppermost surface of said gate insulation layer.

US Pat. No. 10,340,355

METHOD OF FORMING A DUAL METAL INTERCONNECT STRUCTURE

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming source/drain regions on opposite sides of at least one gate structure located over a channel region of a semiconductor fin;
forming a single interlevel dielectric (ILD) layer overlying the source/drain regions and the at least one gate structure;
forming source/drain contact trenches through the ILD layer, each of the source/drain contact trenches exposing at least a portion of one of the source/drain regions; and
forming a source/drain contact structure within each of the source/drain contact trenches, wherein each of the source/drain contact structures comprises a first contact conductor portion located at a bottom portion of each of the source/drain contact trenches and contacting one of the source/drain regions, and a second contact conductor portion overlying the first contact conductor portion, wherein the first contact conductor comprises a first metal and the second contact conductor portion comprises a second metal having a lower electromigration resistance and a lower electrical resistance than the first metal, and wherein each of the source/drain contact structures further comprises an elemental metal liner located on sidewalls of each of the source/drain contact trenches, a metal nitride liner located on the elemental metal liner and a bottom surface of each of the source/drain contact trenches, wherein the metal nitride liner contacts sidewalls and a bottommost surface of the first contact conductor portion, a contact liner located over the metal nitride liner and directly contacting a top surface of the first contact conductor portion, and an adhesion layer portion located on the contact liner and contacting sidewalls and a bottommost surface of the second contact conductor portion, wherein the elemental metal liner has a bottommost surface that is coplanar with a bottommost surface of the metal nitride liner.

US Pat. No. 10,340,346

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a drain layer of a first conductivity type extending in a first direction and a second direction crossing the first direction;
a drift layer of the first conductivity type formed on a surface that is one surface perpendicular to a third direction crossing the first direction and the second direction of the drain layer;
a base region of a second conductivity type formed on a surface of the drift layer;
a source region of the first conductivity type formed on a surface of the base region;
a plurality of trenches formed in an array in the first direction and the second direction, the plurality of trenches each reaching the drift layer through the base region along the third direction from a surface of the source region;
a base contact region of the second conductivity type formed along the second direction in a region in which the plurality of trenches do not contiguously exist along the second direction between the plurality of trenches along the first direction, the base contact region being formed in the source region to electrically connect the source region to the base region being separate from the plurality of trenches;
a plurality of gate regions each formed along an inner wall of corresponding one of the plurality of trenches, via an insulating film, inside the corresponding one of the plurality of trenches;
a plurality of field plate electrodes each formed in an adjacent from corresponding one of the gate regions, via the insulating film, inside the corresponding one of the plurality of trenches along the third direction, and formed longer than the corresponding one of the gate regions in the third direction;
a plurality of first source contacts each formed on the base contact region and the source region along the second direction between the plurality of trenches along the first direction, the first source contacts electrically connect the base contact region to the source region;
a plurality of second source contacts on each of the field plate electrode connected the corresponding one of the field plate electrodes;
a plurality of gate contacts on the corresponding one of the gate regions, electrically connected the corresponding gate region;
a first metal layer being connected to the base contact region and the source region via a first source contact, and being connected to corresponding one of the field plate electrodes via a second source contact;
a second metal layer being insulated via the insulating film from the first metal layer, and being connected to corresponding one of the gate regions via a gate contact; and
a third metal layer formed to be layered in the third direction of the first metal layer and the second metal layer, to be connected to the first metal layer and to be insulated from the second metal layer via the insulating film.

US Pat. No. 10,340,345

NITRIDE SEMICONDUCTOR EPITAXIAL WAFER AND FIELD EFFECT NITRIDE TRANSISTOR

SUMITOMO CHEMICAL COMPANY...

1. A nitride semiconductor epitaxial wafer, comprising:a substrate;
a GaN layer configured to be an electron transit layer provided over the substrate;
an AlGaN layer configured to be an electron feed layer provided over the GaN layer;
wherein the GaN layer comprises a wurtzite crystal structure, and a measured ratio c/a of the lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in the a-axis orientation of the GaN layer is not more than 1.6266 despite the application of lattice mismatch stresses at interfaces between the GaN layer and the substrate and the AlGaN layer, and
wherein the measured ratio c/a allows the occurrence of only negative charges on the surface of the GaN layer on which a two-dimensional electron gas is induced spatially due to the lattice mismatch stresses to suppress current collapse.

US Pat. No. 10,340,344

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Sumitomo Electric Industr...

1. A method for manufacturing a silicon carbide semiconductor device, comprising the steps of:preparing an intermediate substrate including one main surface and the other main surface opposite to the one main surface;
arranging a sodium blocking member as being in contact with the one main surface of the intermediate substrate;
annealing the intermediate substrate while the sodium blocking member is in contact with the one main surface; and
removing the sodium blocking member from the one main surface after the step of annealing the intermediate substrate,
the intermediate substrate including a silicon carbide substrate having a first main surface facing the one main surface and a second main surface opposite to the first main surface, which forms the other main surface of the intermediate substrate, a gate insulating film partially in contact with the first main surface of the silicon carbide substrate, and a source electrode in contact with the first main surface exposed through the gate insulating film, and
the sodium blocking member being composed of a material having a diffusion constant of sodium not greater than a diffusion constant of sodium into the silicon carbide substrate.

US Pat. No. 10,340,342

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:a collection region;
a base region adjacent to the collection region;
an emission region adjacent to the base region, wherein the base region comprises:
a first base region; and
a second base region, wherein the collection region is located on a first side of the first base region, the second base region is located on a second side of the first base region opposite the first side of the first base region, the second base region is located between the emission region and the first base region, is adjacent to the emission region, and has a width smaller than the width of the first base region; and
a doped semiconductor layer on the emission region, wherein the width of the doped semiconductor layer is larger than the width of the emission region, a conductive type of the doped semiconductor layer is the same as a conductive type of the emission region.

US Pat. No. 10,340,338

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a first surface;
an insulating isolation structure disposed at a side of the first surface and composed of an insulator having a first depth; and
a gate electrode,
the semiconductor substrate having a source region disposed in contact with the first surface, a drain region disposed in contact with the first surface, a reverse conductivity region disposed in contact with the first surface and having a second depth, a body region disposed in contact with the first surface so as to surround the source region, and a drift region disposed in contact with the first surface so as to surround the drain region and the reverse conductivity region and sandwich the body region between the source region and the drift region,
the source region, the drift region, and the drain region being of a first conductivity type,
the body region and the reverse conductivity region being of a second conductivity type which is opposite to the first conductivity type,
the reverse conductivity region being disposed between the source region and the drain region,
the insulating isolation structure being disposed between the drain region and the reverse conductivity region,
the gate electrode facing and being insulated from a portion of the body region which is sandwiched by the source region and the drift region,
the first depth being larger than the second depth.

US Pat. No. 10,340,334

SEMICONDUCTOR DEVICE INCLUDING AN LDMOS TRANSISTOR AND A RESURF STRUCTURE

Infineon Technologies AG,...

1. A semiconductor device, comprising:a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface;
an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate; and
a RESURF (REduced SURface Field structure) structure comprising a doped buried layer arranged in the semiconductor substrate,
wherein the LDMOS transistor comprises a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type,
wherein the source region comprises a first well and a second well of the same second conductivity type,
wherein the first well is more highly doped than the second well,
wherein the first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.

US Pat. No. 10,340,329

DISPLAY PANEL INCLUDING POWER SUPPLY COMPENSATION FILM HAVING REDUCED SHEET RESISTANCE ARRANGED ON OPPOSITE SURFACE OF SUBSTRATE FROM POWER SUPPLY LINE LAYER

Shanghai Tianma Micro-Ele...

1. A display panel, comprising:a substrate, a power supply line layer and a power supply compensation film, wherein the power supply compensation film is arranged on a back surface of the substrate, the power supply line layer is arranged on a front surface of the substrate, and the back surface of the substrate is a surface opposite to a light emitting surface of the display panel;
the display panel comprises:
a display area and a non-display area surrounding the display area, and the non-display area comprises a first frame area and a second frame area positioned on two opposite sides of the display area;
the power supply line layer comprises:
a first power supply line arranged in the first frame area and the second frame area, and a plurality of second power supply lines arranged in the display area, and the first power supply line is electrically connected with the plurality of second power supply lines; and
the power supply compensation film is electrically connected with the first power supply line, and a sheet resistance of the power supply compensation film is smaller than a sheet resistance of the power supply line layer.

US Pat. No. 10,340,313

NON-COMMON CAPPING LAYER ON AN ORGANIC DEVICE

Universal Display Corpora...

1. An apparatus comprising:a plurality of OLEDs provided on a first substrate, wherein each OLED comprises:
a first electrode;
a second electrode disposed over the first electrode; and
an organic electroluminescent (EL) material disposed between the first and the second electrodes, wherein the plurality of OLEDs comprising a first portion and a second portion;
a first capping layer disposed over the plurality of OLEDs, wherein a first portion of the first capping layer is disposed over at least the first portion of the plurality of OLEDs and a second portion of the first capping layer is disposed over the second portion of the plurality of OLEDs, wherein the first capping layer and the second electrode are in contact with each other throughout the first and second portions of the first capping layer, such that the first capping layer is optically coupled to at least the first portion and the second portion of the plurality of OLEDs,
wherein substantially all of the light emitting from the first portion and the second portion of the plurality of OLEDs in a direction perpendicular to the second electrode propagates through the first capping layer,
wherein the first capping layer is the only capping layer over the first portion of the plurality of OLEDs and has a first optical thickness that is between 90-130 nm;
a second capping layer disposed over the second portion of the plurality of OLEDs and in contact with the first capping layer throughout the second portion of the first capping layer, such that the second capping layer is optically coupled to the first capping layer and the second portion of the plurality of OLEDs but not the first portion of the plurality of OLEDs,
wherein substantially all of the light emitting from the second portion of the plurality of OLEDs in a direction perpendicular to the second electrode and propagating through the first capping layer also propagates through the second capping layer,
wherein the first capping layer and the second capping layer are the only capping layers over the second portion of the plurality of OLEDs and in combination have a second optical thickness between 125-200 nm that is different from the first optical thickness; and
wherein the second portion of the plurality of OLEDs emits light of different wavelength from the first portion when a driving voltage is applied across the first and second electrodes and the first capping layer having the first optical thickness enhances the amount of light outcoupled from the first portion and the first and second capping layer having the second optical thickness enhance the amount of light outcoupled from the second portion;
wherein the plurality of OLEDs further comprises a third portion of the plurality of OLEDs that is different from the first and second portions of the plurality of OLEDs, wherein the second electrode and a third portion of the first capping layer extend over the third portion of the plurality of OLEDs, wherein the second electrode is in contact with the first capping layer throughout the third portion of the first capping layer such that the first capping layer is also optically coupled to the third portion of the plurality of OLEDs, the apparatus further comprising:
a third capping layer disposed over the third portion of the plurality of OLEDs and in contact with the first capping layer throughout the third portion of the first capping layer such that the third capping layer is optically coupled to the first capping layer and the third portion of the plurality of OLEDs, wherein substantially all of the light emitting from the third portion of the plurality of OLEDs in a direction perpendicular to the second electrode and propagating through the first capping layer also propagates through the third capping layer; wherein the first capping layer and the third capping layer are the only capping layers over the third portion of the plurality of OLEDs and in combination have a third optical thickness between 125-200 nm that is different from the first optical thickness and the second optical thickness; and
wherein the third portion of the plurality of OLEDs emits light of different wavelength from the first portion and the second portion when a driving voltage is applied across the first and second electrodes and the first and the third capping layers having the third optical thickness enhances the amount of light outcoupled from the third portion.

US Pat. No. 10,340,312

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

Hefei Reliance Memory Lim...

1. A re-writeable non-volatile memory device, comprising:a re-writeable non-volatile two-terminal memory element (ME) comprising:
a first terminal,
a second terminal,
a first layer, and
a second layer of reactive metal in direct contact with the first layer, the second layer and the first layer operative to store at least one-bit of data as a state of the re-writable non-volatile two-terminal ME.

US Pat. No. 10,340,311

MAGNETORESISTIVE EFFECT ELEMENT WITH MAGNETIC LAYERS AND MAGNETIC MEMORY

Toshiba Memory Corporatio...

1. A magnetoresistive effect element comprising:a first magnetic layer;
a nonmagnetic layer provided on the first magnetic layer;
a second magnetic layer provided on the nonmagnetic layer;
a first insulating layer provided at least on a side surface of the second magnetic layer;
a second insulating layer covering at least a part of the first insulating layer;
a conductive layer provided between the first insulating layer and the second insulating layer; and
an electrode including a first portion on the second magnetic layer and a second portion on a side surface of the second insulating layer,
wherein a height of a lower surface of the second portion of the electrode is equal to or less than a height of an upper surface of the conductive layer,
a height of an upper surface of the first insulating layer is greater than a height of an upper surface of the second magnetic layer, and
the second insulating layer is provided between the first insulating layer and the first portion of the electrode to be in contact with the upper surface of the second magnetic layer.

US Pat. No. 10,340,308

DEVICE WITH MULTIPLE VERTICALLY SEPARATED TERMINALS AND METHODS FOR MAKING THE SAME

X Development LLC, Mount...

1. A light emitting device, comprising:a plurality of light emitting elements arranged at different locations in a common plane, each light emitting element comprising:
at least one layer of a semiconductor material;
a first electrical terminal for providing charge carriers to a first portion of the light emitting element, the first electrical terminal being located at a first location along an axis perpendicular to the common plane;
a second electrical terminal for providing charge carriers to a second portion of the light emitting element, the second electrical terminal being located at a second location along the axis perpendicular to the common plane different from the first location; and
a third electrical terminal for providing charge carriers to a third portion of the light emitting element, the third electrical terminal being located at a third location along the axis perpendicular to the common plane different from the first and second locations;
a first electrode layer comprising one or more electrodes each being in electrical contact with the first electrical terminal of one or more of the plurality of light emitting elements;
a second electrode layer comprising one or more electrodes each being in electrical contact with the second electrical terminal of one or more of the plurality of light emitting elements;
a third electrode layer comprising one or more electrodes each being in electrical contact with the third electrical terminal of one or more of the plurality of light emitting elements;
a first electrically insulating layer disposed between the plurality of light emitting elements and also disposed between the first and second electrode layers along the axis perpendicular to the common plane; and
a second electrically insulating layer disposed between the plurality of light emitting elements and also disposed between the second and third electrode layers along the axis perpendicular to the common plane.

US Pat. No. 10,340,307

LIGHT EMITTING DIODE HAVING CURRENT CONFINEMENT STRUCTURE

MIKRO MESA TECHNOLOGY CO....

1. A light-emitting diode (LED), comprising:a first type semiconductor layer comprising a first low resistance portion, at least one second low resistance portion, and a high resistance portion, wherein the high resistance portion is between the first low resistance portion and the second low resistance portion, and a resistivity of the first type semiconductor layer increases from the first low resistance portion toward the high resistance portion and decreases from the high resistance portion toward the second low resistance portion, wherein the first low resistance portion has a top surface, a bottom surface, and an outer periphery between the top surface and the bottom surface, and the outer periphery of the first low resistance portion is enclosed by the high resistance portion;
a first electrode electrically connected to the first low resistance portion and substantially no current flowing between the first electrode and the second low resistance portion, wherein the high resistance portion is configured to confine charge carriers substantially within the first low resistance portion;
a second type semiconductor layer, wherein at least a portion of the first type semiconductor layer is between the first electrode and the second type semiconductor layer; and
a second electrode electrically connected to the second type semiconductor layer.

US Pat. No. 10,340,306

SEMICONDUCTOR PACKAGE WITH CHAMFERED CORNERS AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A method for forming an image sensor device, comprising:forming a first plurality of openings in an optically transmissive cover;
coupling the optically transmissive cover to a wafer comprising a plurality of die;
etching a second plurality of openings through the wafer, the second plurality of openings aligning with the first plurality of openings in the optically transmissive cover; and
singulating the optically transmissive cover and the wafer into a plurality of image sensor devices, wherein each image sensor device includes one of a rounded corner or a chamfered corner edge.

US Pat. No. 10,340,305

IMAGE SENSOR AND IMAGE SENSOR PIXEL HAVING JFET SOURCE FOLLOWER

DARTMOUTH COLLEGE, Hanov...

1. An image sensor comprising a plurality of pixels, at least one pixel comprising:a floating diffusion region formed in a semiconductor substrate;
a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion;
a JFET having (i) a source and a drain coupled by a channel region, and (ii) a gate comprising the floating diffusion region; and
wherein the channel region comprises a first doped region of a first conductivity type configured to conduct current between the source and drain along a lateral direction substantially parallel to a surface of the substrate, the floating diffusion region comprises a second doped region of a second conductivity type opposite to the first conductivity type, and wherein the second doped region of the floating diffusion is disposed adjacent to and beneath the first doped region along the lateral direction between the source and drain.

US Pat. No. 10,340,304

CMOS IMAGE SENSOR

SEMICONDUCTOR MANUFACTURI...

1. A CMOS image sensor, comprising:a substrate having a first region and a second region connecting with the first region at a first end of the first region;
a transfer transistor formed on the surface of the substrate in the second region;
a floating diffusion (FD) region formed in the surface of the substrate at one side of the transfer transistor in the second region;
a third implanting region formed in the surface of the substrate in the first region, being formed from a first implanting region;
a second implanting region and an adjacent fifth implanting region formed under the third implanting region; and
a fourth implanting region formed under the second implanting region and the fifth implanting region, being electrically connected with the third implanting region by the fifth implanting region, wherein the third implanting region and the fourth implanting region have side surfaces coinciding with an edge of the transfer transistor.

US Pat. No. 10,340,300

IMAGE SENSOR WITH TRENCHED FILLER GRID

Taiwan Semiconductor Manu...

1. An image sensor, comprising:a first photodiode;
a dielectric grid comprising a first dielectric structure, wherein:
the first dielectric structure comprises a bottommost surface in direct physical contact with a substrate and an uppermost surface; and
the first dielectric structure has a substantially homogeneous material composition which extends between the bottommost surface and the uppermost surface;
a reflective layer having a first portion overlying and in direct physical contact with the uppermost surface;
a first color filter material structure over the first photodiode and having a sidewall in direct physical contact with a sidewall of the reflective layer; and
a lens structure in direct physical contact with the first color filter material structure and the first portion of the reflective layer.

US Pat. No. 10,340,299

OPTICAL SENSOR PACKAGE MODULE AND MANUFACTURING METHOD THEREOF

PIXART IMAGING INC., Hsi...

1. An optical sensor package module comprising:a substrate;
a sensor chip disposed on the substrate and including an array of pixels located at a top side thereof for receiving light; and
a shielding assembly disposed on the substrate and surrounding the sensor chip for limiting influx of light onto the sensor chip, wherein the shielding assembly includes a shielding element disposed on the sensor chip by an adhesive structure, and the shielding element has a first aperture to expose at least a first subset of the pixels that is configured to receive corresponding light;
wherein the adhesive structure is an adhesive layer disposed between the sensor chip and the shielding element and having a through hole to expose the first subset of the pixels, the through hole corresponding to the first aperture.

US Pat. No. 10,340,298

SEMICONDUCTOR DEVICE HAVING NEGATIVE FIXED CHARGE, POSITIVE FIXED CHARGE AND ELECTRONIC APPARATUS CAPABLE OF REDUCING A LEAKING CURRENT OF A PN JUNCTION REGION

Sony Semiconductor Soluti...

1. A semiconductor device comprising:at least one negative fixed charge film that has a negative fixed charge, wherein the at least one negative fixed charge film extends from a P-type region to a depletion layer on a surface of a PN junction formed in a semiconductor substrate, wherein the negative fixed charge film has a boundary located in the depletion layer in the PN junction; and
a positive fixed charge film that has a positive fixed charge, wherein the positive fixed charge film extends from an N-type region to the depletion layer on the surface of the PN junction, wherein the positive fixed charge film has a boundary located in the depletion layer in the PN junction.

US Pat. No. 10,340,296

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a plurality of thin film transistors arranged in an array, each of the thin film transistors includes a base substrate, the base substrate comprising:
a gate electrode,
a gate insulating layer,
an oxide active layer,
a light absorption layer for preventing the oxide active layer from irradiated by light,
a source-drain electrode,
a pixel electrode connected to the source-drain electrode, and
a passivation layer for protecting the thin film transistor,
wherein the gate electrode, the gate insulating layer, the oxide active layer, the source-drain electrode, the pixel electrode, the passivation layer and the light absorption layer are sequentially provided on the base substrate, the passivation layer is directly formed on the pixel electrode, the light absorption layer is directly formed on the passivation layer, an orthographic projection of the light absorption layer on the oxide active layer at least partly covers an active region of the oxide active layer, and the light absorption layer is made of black zirconia.

US Pat. No. 10,340,294

METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND THIN FILM TRANSISTOR

INDUSTRY-UNIVERSITY COOPE...

1. A method for manufacturing a thin film transistor, the method comprising:forming a patterned metal oxide semiconductor layer and a patterned wiring layer on a substrate; and
etching the wiring layer to form a channel part using an etchant,
wherein the wiring layer includes a compensation layer,
wherein the compensation layer is formed from a material including a metal of a metal oxide component among components of a material forming the metal oxide semiconductor layer,
wherein the compensation layer adjusts for a loss of a surface composition of the metal oxide semiconductor layer and suppresses generation of residue during the etching of the wiring layer,
wherein the loss of the surface composition and the generation of the residue are caused by the etchant, and
wherein the wiring layer further includes:
a metal layer formed opposite to the metal oxide semiconductor layer with the compensation layer interposed therebetween,
an additional compensation layer formed opposite to the compensation layer with the metal layer interposed therebetween, and
a transparent conductive layer formed opposite to the metal layer with the additional compensation layer interposed therebetween.

US Pat. No. 10,340,292

EXTREMELY THIN SILICON-ON-INSULATOR SILICON GERMANIUM DEVICE WITHOUT EDGE STRAIN RELAXATION

International Business Ma...

1. A semiconductor structure comprising:a substrate;
a strained silicon germanium layer disposed on the substrate, wherein the strained silicon germanium layer is free of edge strain relaxation;
a plurality of gate stacks, wherein each gate stack of the plurality of gates stacks is disposed on and in contact with a different portion of the strained silicon germanium layer;
a first plurality of oxide regions within and formed from the strained silicon germanium layer; and
a second plurality of oxide regions within and formed from the strained silicon germanium layer, wherein each different portion of the strained silicon germanium layer is situated between and contacts one oxide region in the first plurality of oxide regions and one oxide region in the second plurality of oxide regions.

US Pat. No. 10,340,291

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate including a main surface and a back surface;
a first semiconductor region of a first conductivity type formed in the semiconductor substrate;
a first active region and a second active region whose peripheries are defined by an element isolation region, in the first semiconductor region;
a first semiconductor layer formed on the main surface of the semiconductor substrate via a first insulating film, in the first active region;
a first gate electrode formed on a surface of the first semiconductor layer via a first gate insulating film;
a first sidewall spacer formed on a side wall of the first gate electrode;
first epitaxial layers formed on the first semiconductor layer at both sides of the first gate electrode;
a second semiconductor region and a third semiconductor region of a second conductivity type formed in the first semiconductor layer and the first epitaxial layers at both sides of the first gate electrode, the second conductivity type being a conductivity type opposite to the first conductivity type;
a fourth semiconductor region of the first conductivity type formed below the first insulating film, in the first active region;
a first silicide layer formed on a surface of the first semiconductor region, in the second active region;
an interlayer insulating film covering the first gate electrode; and
a first power supply wiring formed over the interlayer insulating film,
wherein, in a plan view, the second active region extends in a first direction,
wherein, in a plan view, the first power supply wiring extends in the first direction so as to overlap with the second active region,
wherein the first power supply wiring is connected to the second semiconductor region,
wherein the first gate electrode extends in a second direction perpendicular to the first direction, and lies on the element isolation region between the first active region and the second active region, and
wherein the first silicide layer is connected to the first power supply wiring.

US Pat. No. 10,340,290

STACKED SOI SEMICONDUCTOR DEVICES WITH BACK BIAS MECHANISM

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor device, comprising:a first semiconductor layer formed on an upper surface of a first buried insulating layer;
a first circuit element formed in and above said first semiconductor layer, said first circuit element comprising drain and source regions that are formed at least partially in said first semiconductor layer;
a conductive layer formed above said first circuit element, wherein said conductive layer is electrically isolated from said drain and source regions that are formed at least partially in said first semiconductor layer;
a second buried insulating layer formed on an upper surface of said conductive layer; and
a second semiconductor layer formed on an upper surface of said second buried insulating layer.

US Pat. No. 10,340,289

CASCODE RADIO FREQUENCY (RF) POWER AMPLIFIER ON SINGLE DIFFUSION

QUALCOMM Incorporated, S...

1. An amplifier, comprising:a cascode structure comprising a first transistor having first characteristics coupled to a second transistor having second characteristics different than the first characteristics, the first transistor located with the second transistor on a single diffusion, the single diffusion having no intervening insulating layer separating the first transistor from the second transistor, the single diffusion comprising at least a P-type well region, a floating P body region having a P+ island, and a no well region having a native state of a silicon-on-insulator (SOI) layer on which the amplifier is located.

US Pat. No. 10,340,288

METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVING UNIDIRECTIONAL LAYOUT USING SELF-ALIGNED DOUBLE PATTERNING

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a first set of metal features extending in a first lateral direction in a first metal layer of a memory cell;
forming a second set of metal features extending in a second lateral direction perpendicular to the first lateral direction in a second metal layer of said memory cell;
forming a third set of metal features extending in the second lateral direction in a second metal layer of a functional cell for providing routing compatibility between said memory cell and said functional cell; and
placing said memory cell adjacent to said functional cell for forming an integrated circuit device.

US Pat. No. 10,340,287

APPARATUSES AND METHODS FOR FORMING MULTIPLE DECKS OF MEMORY CELLS

Micron Technology, Inc., ...

1. An apparatus comprising:a first deck including alternating levels of first conductor materials and levels of first dielectric materials;
first memory cells located in the first deck, each of the first memory cells located in a respective level of the levels of first conductor materials;
a second deck including alternating levels of second conductor materials and levels of second dielectric materials;
second memory cells located in the second deck, each of the second memory cells located in a respective level of the levels of second conductor materials;
a level of third conductor material located between the first and second decks;
a level of fourth conductor material located between the first and second decks; and
a level of a dielectric material located between the level of third conductor material and the level of fourth conductor material.

US Pat. No. 10,340,285

NON-VOLATILE MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device comprising:a plurality of memory cells stacked in a first direction and electrically connected in series;
at least one of the memory cells including:
a first electrode;
a first semiconductor layer extending in the first direction through the first electrode;
a memory film provided between the first electrode and the first semiconductor layer; and
a first insulating core layer provided inside the first semiconductor layer; and
a select transistor provided above the memory cells in the first direction and electrically connected to the memory cells in series, the select transistor including:
a second electrode;
a second semiconductor layer extending in the first direction through the second electrode, the second semiconductor layer being coupled to the first semiconductor layer of the at least one of the memory cells;
a gate insulating film provided between the second electrode and the second semiconductor layer; and
a second insulating core layer provided inside the second semiconductor layer;
a thickness of the second semiconductor layer in a second direction orthogonal to the first direction being thinner than a thickness of the first semiconductor layer in the second direction.

US Pat. No. 10,340,281

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three-dimensional (3D) semiconductor device, comprising:a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater;
a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers above the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein two of the respective contact regions are positioned higher than one of the respective contact regions disposed between said two of the respective contact regions, and an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer, wherein the uppermost active layer of each of the sub-stacks in the respective contact regions is continuously extended from one of the active layers in the array area respectively; and
multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer of the uppermost active layer in each of the sub-stacks.

US Pat. No. 10,340,279

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Sony Semiconductor Soluti...

1. A method of manufacturing a semiconductor device comprising:selecting a first through electrode from a plurality of through electrodes, the through electrodes penetrating a plurality of conductive layers and a plurality of insulating layers that are alternately stacked, wherein
antifuses are each provided between corresponding ones of the through electrodes and corresponding ones of the conductive layers;
applying a first voltage and a second voltage, the first voltage being applied to one or more of the through electrodes excluding the first electrode, and the second voltage being applied to the first through electrode; and
causing the first through electrode to be electrically floated after the second voltage is applied to the first through electrode.

US Pat. No. 10,340,276

METHOD OF MAINTAINING THE STATE OF SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising:
said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a transistor comprising a source region, a floating body region, a drain region, and a gate;
a first bipolar device having a first floating base region, a first emitter, and a first collector; and
a second bipolar device having a second floating base region, a second emitter, and a second collector;
wherein said first floating base region and said second floating base region are common to said floating body region;
wherein said first collector is common to said second collector;
wherein application of back bias to said first and second collectors results in at least two stable floating base region charge levels;
wherein said transistor is usable to access said memory cell;
a first control circuit configured to apply said back bias to said first and second collectors; and
a second control circuit configured to access a selected memory cell selected from said semiconductor memory cells and perform a read or write operation on said selected memory cell.

US Pat. No. 10,340,275

STACKABLE THIN FILM MEMORY

Intel Corporation, Santa...

1. A memory, comprising:a thin film transistor over a first metal layer over a substrate, the thin film transistor comprising:
a thin film transistor layer having an upper surface and a lower surface;
a gate dielectric layer on the lower surface of the thin film transistor layer;
a gate electrode on the gate dielectric layer;
a source region on the upper surface of the thin film transistor layer; and
a drain region on the upper surface of the transistor layer; and
a memory element coupled to the thin film transistor.

US Pat. No. 10,340,274

LDMOS FINFET DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:a semiconductor substrate;
first and second fins on the semiconductor substrate and separated by a trench, the first fin comprising a first portion including a first conductivity type and a second portion including a second conductivity type different from the first conductivity type, the first and second portions adjacent to each other, the second portion connected to the second fin through the semiconductor substrate;
a gate structure on the first and second portions, the gate structure comprising:
a gate insulator layer on the first and second portions;
a gate on a portion of the gate insulator layer on the first portion; and
a dummy gate on the second portion and comprising an insulating layer or an undoped semiconductor layer, the dummy gate being adjacent to the gate.

US Pat. No. 10,340,273

DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES

Intel Corporation, Santa...

1. A structure comprising:a first fin comprising silicon and including a first region over a second region;
a gate stack adjacent to a sidewall surface of the first region, wherein the gate stack includes a gate dielectric and a gate electrode;
a first source and a first drain coupled to the first region;
a first dielectric layer adjacent to a sidewall surface of the second region, wherein the first dielectric layer comprises an impurity that is also present within the second region and associated with a conductivity type;
a second fin comprising silicon and including a third region over a fourth region;
a second gate stack is adjacent to a sidewall surface of the third region;
a second source and a second drain coupled to the third region;
a second dielectric layer adjacent to a sidewall surface of the fourth region; and
an isolation material between the first gate stack and a substrate surface that intersects the sidewall surface of the second region, wherein the isolation material is further between the first dielectric layer and the second dielectric layer, and wherein the isolation material comprises a plurality of dielectric layers including a layer comprising silicon and nitrogen that is adjacent to the first dielectric layer and is adjacent to the second dielectric layer.

US Pat. No. 10,340,271

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor structure, comprising:providing a semiconductor substrate having a first region, a second region, and an isolation region between the first region and the second region;
forming a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region;
forming an isolation structure, covering portions of side surfaces of the first fins and the second fins and with a top surface below the top surfaces of the first fins and the second fins, over the semiconductor substrate; and
forming an isolation layer over the isolation structure in the isolation region and with a top surface coplanar or above the top surfaces of the first fins and the second fins, wherein forming the isolation layer comprises:
forming a sacrificial layer over the isolation structure, the first fins and the second fins and exposing a portion of the isolation structure in the isolation region;
forming an initial isolation layer on exposed portion of the isolation structure and on the sacrificial layer;
removing a portion of the initial isolation layer on the sacrificial layer; and
removing the sacrificial layer.

US Pat. No. 10,340,270

INTEGRATED CIRCUIT HAVING FINFETS WITH DIFFERENT FIN PROFILES

Taiwan Semiconductor Manu...

1. A method of forming an integrated circuit, comprising:forming a first top fin, a second top fin, and a third top fin extending from a substrate;
forming a first mask over the first top fin;
forming a second mask over the second top fin and the third top fin;
removing a portion of the substrate to form a first base fin and a second base fin, the first top fin extending from the first base fin, the second top fin and the third top fin extending from the second base fin; and
after removing the portion of the substrate to form the first base fin and the second base fin, reducing a width of the first base fin.

US Pat. No. 10,340,269

CONTACT RESISTANCE REDUCTION TECHNIQUE

Taiwan Semiconductor Manu...

1. A device comprising:a fin extending from a substrate;
a gate structure on a top surface and sidewalls of the fin;
a strained material stack on the fin adjacent the gate structure, the strained material stack comprising:
a first boron-doped (B-doped) silicon-germanium (SiGeB) layer on the fin;
a second SiGeB layer on the first SiGeB layer, the second SiGeB layer having a higher concentration of Ge than the first SiGeB layer;
a B-doped germanium-tin (GeSnB) layer on the second SiGeB layer; and
a third SiGeB layer on the GeSnB layer;
a metal-silicide layer on the third SiGeB layer; and
a metal contact on the metal-silicide layer.

US Pat. No. 10,340,261

SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CHIPS CONNECTED BY HYBRID BONDING METHOD

Micron Technology, Inc., ...

1. An apparatus comprising:a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays; and
a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits,
wherein the first and second semiconductor chips are stacked with each other so that each of the plurality of first bonding electrodes is electrically connected to an associated one of the plurality of second bonding electrodes,
wherein each of the memory cell arrays includes a plurality of first signal lines extending in a first direction, a plurality of second signal lines extending in a second direction different from the first direction, and a plurality of memory cells each disposed on an associated one of intersections of the plurality of first and plurality of second signal lines,
wherein the plurality of memory cell arrays include first and second memory cell arrays adjacent in the second direction to each other,
wherein the plurality of first bonding electrodes include:
a first group located at one end of the first memory cell array in the first direction and electrically connected to predetermined ones of the plurality of first signal lines in the first memory cell array;
a second group located at another end of the first memory cell array in the first direction and electrically connected to remaining ones of the plurality of first signal lines in the first memory cell array; and
a third group located at one end of the second memory cell array in the first direction and electrically connected to predetermined ones of the plurality of first signal lines in the second memory cell array, a position of the third group in the first direction being located between positions of the first and second groups in the first direction.

US Pat. No. 10,340,260

MAGNETIC SMALL FOOTPRINT INDUCTOR ARRAY MODULE FOR ON-PACKAGE VOLTAGE REGULATOR

Intel Corporation, Santa...

1. An electronic assembly including:a first IC including contact pads and a voltage regulator circuit; and
an inductor module including:
a module substrate including a magnetic dielectric material;
a first surface at the top of the inductor module and a second surface at the bottom of the inductor module;
a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil oriented to extend in the direction from the first surface to the second surface and including a first end and a second end and a core, wherein the coil core includes the magnetic dielectric material; and
a plurality of conductive contact pads electrically coupled to the first and second coil ends, wherein contact pads electrically coupled to the first coil ends are arranged on the first surface, and the contact pads electrically coupled to the second coil ends are arranged on the second surface;
wherein the first IC is arranged on a surface of the inductor module and wherein at least a portion of the contact pads of the inductor module are electrically coupled to the contact pads of the voltage regulator circuit.

US Pat. No. 10,340,259

METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE

MediaTek Inc., Hsin-Chu ...

1. A method for fabricating a semiconductor package, comprising:providing a carrier;
adhering semiconductor dice to a top surface of the carrier by an adhesive that is in direct physical contact with the top surface of the carrier, wherein each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface, and wherein a plurality of input/output (I/O) pads are distributed on the active surface of each of the semiconductor dice;
printing interconnect features, the printing comprising:
printing a first conductive pad on the carrier;
printing a second conductive pad on the active surface of at least one of the semiconductor dice; and
printing a conductive wire connecting the first and second conductive pads, wherein the interconnect features comprise the first conductive pad, the second conductive pad and the conductive wire;
encapsulating the top surface of the carrier, the semiconductor dice and the interconnect features with an encapsulant; and
removing the carrier.

US Pat. No. 10,340,258

INTERCONNECT STRUCTURES, PACKAGED SEMICONDUCTOR DEVICES, AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. An interconnect structure, comprising:a polymer material; and
a conductive line comprising:
a post passivation interconnect (PPI) pad disposed above an uppermost surface of the polymer material; and
a PPI line disposed below the uppermost surface of the polymer material, wherein:
the PPI line is coupled to the PPI pad through a transition structure;
the transition structure is interposed between and different than the PPI line and the PPI pad;
the transition structure extends over the polymer material;
the transition structure has an uppermost surface disposed above an uppermost surface of the PPI line;
in a top-down view, the transition structure has a shape that tapers from a first width of the uppermost surface of the transition structure to a second width of the lowermost surface of the transition structure; and
the first width is greater than the second width.

US Pat. No. 10,340,256

DISPLAY DEVICES

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate having a surface comprising a display area and a non-display area adjacent to the display area;
a plurality of light-emitting diodes disposed on the display area of the substrate, wherein the light-emitting diode comprises a contact electrode;
an anisotropic conductive layer disposed between the substrate and the plurality of light-emitting diodes, wherein the anisotropic conductive layer has a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the anisotropic conductive layer is in a shape of a curve;
a covering layer contacting at least a portion of one of the plurality of light-emitting diodes, wherein the covering layer has a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the covering layer is in a shape of a curve; and
a connection structure disposed on the non-display area and/or the display area of the substrate, wherein the connection structure comprises an electrode having a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the electrode is in a shape of a curve.

US Pat. No. 10,340,253

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:a first die and a second die side by side;
a first encapsulant, encapsulating sidewalls of the first die and sidewalls of the second die;
a bridge, electrically connecting the first die and the second die through two conductive bumps;
an underfill layer, filling the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsulant;
a second encapsulant over the first die and the second die, encapsulating sidewalls of the underfill layer and sidewalls of the bridge;
a dielectric layer, sandwiched between the first die and the second encapsulant, and between the second die and the second encapsulant; and
a redistribution layer (RDL) structure over the bridge, electrically connected to the first die and the second die though a plurality of through integrated fan-out vias (TIVs),
wherein bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.

US Pat. No. 10,340,251

METHOD FOR MAKING AN ELECTRONIC COMPONENT PACKAGE

NXP USA, Inc., Austin, T...

17. A method of making an electronic component package, the method comprising:applying a sacrificial material to a first glass carrier;
applying a second glass carrier to a top side of the sacrificial material;
curing the sacrificial material with UV radiation through the second glass carrier while the second glass carrier is applied to the top side;
after the curing, removing the second glass carrier from the sacrificial material, wherein the top side has a top surface defined by the second glass carrier, and wherein after the removing of the second glass carrier, an unfeatured area of the top surface has a roughness (Ra) of 1 nm or less;
after the removing, forming a redistribution structure over the top side of the sacrificial material, the redistribution structure including at least one redistribution layer;
attaching a plurality of electronic components to the redistribution structure;
after the attaching, encapsulating the plurality of electronic components to form an encapsulated panel that includes the redistribution structure;
removing the first glass carrier and the sacrificial material from the encapsulated panel after the encapsulating;
singulating the encapsulated panel into a plurality of electronic component packages, each electronic component package of the plurality of electronic component packages including at least one electronic component of the plurality of electronic components.

US Pat. No. 10,340,249

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:forming a first opening in a first photosensitive adhesive layer, the first photosensitive adhesive layer being adjacent a first side of a first integrated circuit device;
plating a first reflowable layer in the first opening;
forming a second opening in a second photosensitive adhesive layer, the second photosensitive adhesive layer being adjacent a first side of a second integrated circuit device;
plating a second reflowable layer in the second opening;
pressing the first and second photosensitive adhesive layers together, thereby physically connecting the first and second integrated circuit devices; and
reflowing the first and second reflowable layers, thereby forming a conductive connector electrically connecting the first and second integrated circuit devices.

US Pat. No. 10,340,248

BONDING SYSTEMS

TOKYO ELECTRON LIMITED, ...

1. A bonding system comprising:a substrate transfer device configured to transfer a first substrate and a second substrate in an atmospheric pressure atmosphere;
a surface modifying apparatus configured to modify surfaces of the first substrate and the second substrate in a depressurized atmosphere;
a load lock chamber configured to perform delivery of the first substrate and the second substrate between the load lock chamber and the substrate transfer device and between the load lock chamber and the surface modifying apparatus, and configured to switch an internal atmosphere of the load lock chamber between the atmospheric pressure atmosphere and the depressurized atmosphere;
a surface hydrophilizing apparatus configured to hydrophilize the modified surfaces of the first substrate and the second substrate; and
a bonding apparatus configured to bond the hydrophilized surfaces of the first substrate and the second substrate by an intermolecular force,
wherein the substrate transfer device transfers the first substrate and the second substrate to and from the load lock chamber, to and from the surface hydrophilizing apparatus, and to and from the bonding apparatus, and
wherein the load lock chamber sets the internal atmosphere to be the atmospheric pressure atmosphere when the first substrate and the second substrate are delivered between the load lock chamber and the substrate transfer device, and sets the internal atmosphere to be the depressurized atmosphere when the first substrate and the second substrate are delivered between the load lock chamber and the surface modifying apparatus.

US Pat. No. 10,340,245

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

Samsung Electro-Mechanics...

1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip and filling at least a portion of space between walls of the through-hole and side surfaces of the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip;
first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant; and
a component package including a wiring substrate and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate, the wiring substrate being disposed above the second interconnection member and connected to the second interconnection member through the first connection terminals,
wherein the first interconnection member and the second interconnection member each include a redistribution layer electrically connected to the connection pads of the semiconductor chip, and
the component package is disposed on a first surface side of the second interconnection member and the active surface of the semiconductor chip is disposed on a second surface side of the second interconnection member, the second surface being opposite the first surface,
wherein an electrical pathway at least traverses the connection pad, a first redistribution pattern of the redistribution layer of the second interconnection member, a first terminal of the first connection terminals, a wiring layer of the wiring substrate, a second terminal of the first connection terminals, a second redistribution pattern of the redistribution layer of the second interconnection member, the redistribution layer of the first interconnection member, and the second connection terminal in that sequence,
wherein the second terminal of the first connection terminals is spaced apart from the first terminal of the first connection terminals, and the second redistribution pattern of the second interconnection member is spaced apart from the first redistribution pattern of the second interconnection member.

US Pat. No. 10,340,244

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor device comprising:a low-density substrate;
a high-density patch positioned inside a cavity in the low-density substrate, the high-density patch comprising a base plate and a high-density redistribution structure, wherein the high-density redistribution structure comprises one or more high-density circuit traces on the base plate;
a first semiconductor die including high-density bumps and low-density bumps; and
a second semiconductor die including high-density bumps and low-density bumps,
wherein the high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the one or more high-density circuit traces of the high-density patch, and the low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

US Pat. No. 10,340,243

CIRCUIT SUBSTRATE AND METHOD FOR MANUFACTURING CIRCUIT SUBSTRATE

FUJI XEROX CO., LTD., To...

1. A circuit substrate comprising:a base material; and
a capacitor layer including:
a first metal layer on the base material;
a dielectric layer on the first metal layer; and
a second metal layer on the dielectric layer,
wherein the first metal layer includes a first electrode region on the base material, which is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit through the capacitor layer is to be connected, and
wherein the second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is to be connected.

US Pat. No. 10,340,241

CHIP-ON-CHIP STRUCTURE AND METHODS OF MANUFACTURE

INTERNATIONAL BUSINESS MA...

1. A method, comprising:placing a powder on a semiconductor substrate;
sintering the powder to form a plurality of pillars directly in contact with the semiconductor substrate;
repeating the placing and sintering steps until the plurality of pillars reach a predetermined height;
forming a solder cap on the plurality of pillars;
removing non-sintered powder by a cleaning process;
joining the semiconductor substrate to a board using the solder cap and a thermal reflow process;
joining a chip to the semiconductor substrate by a reflow process; andunderfilling empty spaces between the chip, the semiconductor substrate and the board, wherein:the semiconductor substrate is a wafer placed in a chuck and coated with a plurality of layers of the powder, followed by the laser sintering after each coating to form the pillars directly in contact with the wafer;
joining the chip to the wafer between the pillars;
dicing the wafer to form a plurality chips with the pillars;
bonding a chip without the pillars to a substrate of another chip of a plurality of chips between the pillars;
the chip without the pillars including plating of micro-bumps; and
wherein the board is an organic laminate and the organic laminate is bonded to the another chip by the pillars by a reflow of the solder cap at a reflow temperature of about 250° C. to about 260° C.

US Pat. No. 10,340,238

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:a first wiring structure including
a first insulation layer formed from a thermosetting insulative resin and including a reinforcement material,
a recess formed in a lower surface of the first insulation layer,
a first wiring layer with which the recess is filled, and
a via wiring including an upper end surface exposed from an upper surface of the first insulation layer, wherein the via wiring extends in a thickness-wise direction through the first insulation layer and is connected to the first wiring layer;
a protective insulation layer formed on the lower surface of the first insulation layer; and
a second wiring structure laminated on the upper surface of the first insulation layer, wherein the second wiring structure includes
at least one second insulation layer formed from an insulative resin of which main component is a photosensitive resin, and
two or more second wiring layers;
wherein the upper surface of the first insulation layer and the upper end surface of the via wiring are polished surfaces,
the first wiring layer includes a lower surface formed to be flush with the lower surface of the first insulation layer or recessed from the lower surface of the first insulation layer toward the second wiring structure,
the second wiring structure has a wiring density that is higher than a wiring density of the first wiring structure, and
the reinforcement material is located toward the second wiring structure from a thickness-wise center of the first insulation layer and is located at a thickness-wise center of a thickness from the lower surface of the first insulation layer to an upper surface of an uppermost one of the two or more second wiring layers.

US Pat. No. 10,340,237

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KOKUSAI ELECTRIC CORPORAT...

1. A method of manufacturing a semiconductor device, comprising:(a) loading a substrate into a process chamber, the substrate comprising a conductive film and an insulating film formed around the conductive film to expose the conductive film; and
(b) forming a protective film selectively on an upper surface of the insulating film without forming the protective film on the conductive film by supplying into the process chamber a process gas comprising a component reactive with a desorbed gas generated from the insulating film.

US Pat. No. 10,340,236

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a semiconductor substrate;
a top metal layer over the semiconductor substrate;
a first passivation layer over and in physical contact with the top metal layer;
a first redistribution layer over and in physical contact with the first passivation layer;
a first polymer layer over and in physical contact with the first redistribution layer;
an encapsulant in physical contact with the semiconductor substrate, the first passivation layer, and the first polymer layer, wherein the encapsulant contacts a first sidewall and a second sidewall of the first polymer layer, and wherein at least a portion of the first polymer layer extends above a top surface of the encapsulant; and
a first conductive via extending through the first polymer layer and in electrical connection with the first redistribution layer, the first conductive via being laterally separated from the encapsulant, wherein a top surface of the first conductive via extends above a top surface of the encapsulant.

US Pat. No. 10,340,231

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor package structure, comprising:a semiconductor die comprising an active surface, a back surface and a sidewall surface between the active surface and the back surface, wherein the active surface of the semiconductor die has a contact pad therein;
a molding layer covering the back surface and the sidewall surface of the semiconductor die; and
an inductor in the molding layer, wherein the sidewall surface of the semiconductor die faces toward the inductor, wherein a lower surface of the molding layer is coplanar with a lower surface of the inductor, and wherein an upper surface of the contact pad is coplanar with an upper surface of the inductor.

US Pat. No. 10,340,230

SEMICONDUCTOR CHIP

United Microelectronics C...

1. A semiconductor chip, comprising:at least one interlayer dielectric layer, disposed on a substrate;
a transmission pattern, disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip, wherein the transmission pattern is electrically connected to an external signal source;
a stress absorption structure, disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern, wherein the stress absorption structure is covered by the transmission pattern.

US Pat. No. 10,340,228

FABRICATION METHOD OF SEMICONDUCTOR PACKAGE

Siliconware Precision Ind...

1. A method for fabricating a semiconductor package, comprising the steps of:providing a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface;
disposing at least a semiconductor element on the first top surface of the circuit structure, wherein the semiconductor element is electrically connected to the circuit structure;
forming an encapsulant on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface;
thinning the encapsulant from the second top surface thereof; and
forming a strengthening layer on the second top surface of the encapsulant and forming an adhesive layer between the encapsulant and the strengthening layer, wherein the strengthening layer and the adhesive layer are free from being removed, and the strengthening layer is made of a semiconductor material.

US Pat. No. 10,340,227

METHOD FOR PROCESSING A DIE

Infineon Technologies AG,...

1. A die, comprising:a die body; and
at least one of a front side metallization structure on a front side of the die body and a back side metallization structure on a back side of the die body such that the die is configured to be planar at a die attach process temperature range or to have a positive radius of curvature at the die attach process temperature range, wherein the back side metallization structure is electrically conductive and comprises impurities configured to exert a compressive stress onto the die body that is greater than a compressive stress of the front side metallization structure at the die attach process temperature range.

US Pat. No. 10,340,226

INTERCONNECT CRACK ARRESTOR STRUCTURE AND METHODS

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first contact pad on a first semiconductor substrate;
a first crack stopper on the first contact pad, the first crack stopper comprising a first wire that is wire bonded to the first contact pad on the first semiconductor substrate, the first wire having a first portion directly bonded to the first contact pad, the first portion having non-parallel sidewalls comprising a ball or wedge shape at an interface with the first contact pad, the first wire having a second portion continuous with the first portion, the second portion having parallel sidewalls extending from the first portion, the second portion being narrower than the first portion;
a protective layer surrounding sides of the first wire; and
solder surrounding the first crack stopper.

US Pat. No. 10,340,225

METHODS AND MODULES RELATED TO SHIELDED LEAD FRAME PACKAGES

Skyworks Solutions, Inc.,...

1. A method for providing electro-magnetic interference shielding for a radio-frequency module, the method comprising:applying a metal-based covering over a portion of a lead-frame package, the lead-frame package having a plurality of pins with at least one pin exposed from overmold compound and in contact with the metal-based covering, the lead-frame package including an inner row and an outer row of pins on each side, and all the pins of all the outer rows of pins assigned to ground;
mounting the lead-frame package on a substrate; and
connecting the metal-based covering to a ground plane of the substrate.

US Pat. No. 10,340,224

MICROWAVE AND MILLIMETER WAVE PACKAGE

Mitsubishi Electric Corpo...

1. A microwave and millimeter wave package comprising:a conductor base plate having a semiconductor element fixed to an upper surface thereof;
a side wall provided on the conductor base plate to surround the semiconductor element, the side wall having a conductor portion electrically connected to the conductor base plate;
a dielectric cap disposed on the side wall to form an internal space together with the conductor base plate and the side wall;
a front-side metal film provided on an entire front-side of the dielectric cap;
a first back-side metal film provided on an inner surface of the dielectric cap such that a center of the first back-side metal film approximately coincides with a center of a surface of the dielectric cap which faces the conductor base plate; and
a plurality of vias provided to pass through the dielectric cap and achieve electrical connection between the front-side metal film and the first back-side metal film and electrical connection between the front-side metal film and the conductor portion of the side wall, wherein
the first back-side metal film has, in a plan view, any one of a rectangular shape, a circular shape, an oval shape, and a polygonal shape,
the first back-side metal film comprises an opening portion in the first back-side metal film, the opening portion having a shape approximately similar to the shape of the first back-side metal film and having a small area, centers of the opening portion and the first back-side metal film approximately coinciding with each other, and
a width of the first back-side metal film of the opening portion is in a range of 1/16 to 3/16 of the wavelength for the lowest-order cavity resonant frequency.

US Pat. No. 10,340,222

STAIR CONTACT STRUCTURE, MANUFACTURING METHOD OF STAIR CONTACT STRUCTURE, AND MEMORY STRUCTURE

MACRONIX INTERNATIONAL CO...

1. A stair contact structure adjacent to a memory array, comprising:a plurality of layers of stacking structures, wherein each stacking structure comprises a conductive layer and an insulating layer, and the conductive layers and the insulating layers are interlaced; and
a first etch stop layer penetrating through the stacking structures vertically and extending along a first horizontal direction, wherein the conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages, wherein a length along the first horizontal direction of one of the conductive layers of said each stacking structure is smaller than a length along the first horizontal direction of one of the insulating layers positioned on and directly contacting said one of the conductive layers of said each stacking structure;
wherein the stair contact structure and the memory array are disposed along a second horizontal direction vertical to the first horizontal direction.

US Pat. No. 10,340,221

STACKED FINFET ANTI-FUSE

International Business Ma...

1. A method of forming a semiconductor structure, said method comprising:providing a stacked fin structure on a surface of a first insulator layer, the stacked fin structure comprising a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion;
doping the first semiconductor fin portion and the second semiconductor fin portion;
removing the insulator fin portion;
growing a first highly doped epitaxial structure about the first semiconductor fin portion and a second highly doped epitaxial structure about the second semiconductor fin portion, wherein the first highly doped epitaxial structure has lower-most apex overlying and aligned with an upper-most apex of the second highly doped epitaxial structure, the lower-most apex separated from the upper-most portion by a gap; and
forming a second insulating layer about the first highly-doped epitaxial layer and the second highly-doped epitaxial layer, wherein the second insulator layer fills the gap.

US Pat. No. 10,340,220

COMPOUND LATERAL RESISTOR STRUCTURES FOR INTEGRATED CIRCUITRY

Intel Corporation, Santa...

17. A system on a chip (SOC), comprising:processor logic circuitry;
memory circuitry coupled to the processor logic circuitry;
RF circuitry coupled to the processor logic circuitry and including radio transmission circuitry and radio receiver circuitry; and
power management circuitry including an input to receive a DC power supply and an output coupled to at least one of the processor logic circuitry, memory circuitry, and RF circuitry, wherein at least one of the processor logic circuitry, memory circuitry, RF circuitry, or power management circuitry include both:
a resistor trace over a substrate, a length of the resistor trace comprising a first resistive material in contact a sidewall of a second resistive material;
a first dielectric material over the first resistive material, but not the second resistive material; and
a pair of resistor contacts coupled to opposite ends of the resistive trace and separated by the length; and
a transistor further comprising:
a gate stack over a semiconductor body, the gate stack including a gate electrode over a gate dielectric;
a semiconductor source and drain on opposite sides of the gate stack; and
source and drain contacts on the semiconductor source and drain, and separated from the gate stack by a spacer dielectric material that is also on a sidewall of the first dielectric.

US Pat. No. 10,340,218

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE COMPRISING PLURALITY OF THROUGH HOLES USING METAL HARD MASK

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure comprising:forming a first portion of a dielectric layer to conceal a conductive structure;
removing some of the first portion of the dielectric layer to expose a top surface of the conductive structure, wherein a top of the first portion of the dielectric layer is at or above the top surface of the conductive structure after removing some of the first portion of the dielectric layer;
forming a second portion of the dielectric layer over the first portion of the dielectric layer and over the top surface of the conductive structure;
forming a metal hard mask over the dielectric layer;
patterning the metal hard mask to form a patterned metal hard mask;
patterning the first portion of the dielectric layer and the second portion of the dielectric layer with the patterned metal hard mask to define a first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer; and
patterning the second portion of the dielectric layer with the patterned metal hard mask to define a second through hole extending through the second portion of the dielectric layer.

US Pat. No. 10,340,217

SEMICONDUCTOR DEVICE INCLUDING A CYLINDRICAL ELECTRODE INSERTED INTO A LOOPED PORTION OF AN ELECTRODE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor chip;
an electrode electrically connected to the semiconductor chip, the electrode including a looped portion;
a cylindrical electrode including a main portion having a screw thread formed therein and a narrow portion continuous with the main portion, the narrow portion having a smaller width than the main portion, the cylindrical electrode being electrically connected to the electrode by the narrow portion being inserted into the looped portion; and
a case for the semiconductor chip and the electrode, the case contacting the main portion and a top surface of the looped portion, while causing the screw thread and a connecting portion between the looped portion and the cylindrical electrode to be exposed.

US Pat. No. 10,340,215

CHIP ON FILM AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A chip on film comprising:a base material;
a plurality of mutually independent output pads extending in a first direction and disposed on a side of the base material;
a chip; and
a plurality of leads, in one-to-one correspondence with the output pads and extending in a second direction, wherein the leads are configured to connect corresponding output pads to the chip, the second direction is parallel to a plane where the output pads are located,
the output pads constitute at least one set of interdigitated electrode structures arranged in a direction perpendicular to the first direction,
the chip and the output pads are located on two sides of the base material, respectively, the leads comprise:
first leads disposed on the base material on a same side as the output pads, and
second leads disposed on the base material on a same side as the chip,
wherein, first ends of the first leads are connected with a part of output pads that constitute the interdigitated electrode structures, and second ends of the first leads are connected with the chip through first vias penetrating the base material,
first ends of the second leads are connected with another part of the output pads that constitute the interdigitated electrode structures through second vias penetrating the base material, and second ends of the second leads is connected with the chip.

US Pat. No. 10,340,214

CARRIER BASE MATERIAL-ADDED WIRING SUBSTRATE

SHINKO ELECTRIC INDUSTRIE...

1. A carrier base material-added wiring substrate comprising:a wiring substrate including
an insulation layer,
a wiring layer arranged on a lower surface of the insulation layer, and
a solder resist layer that covers the lower surface of the insulation layer and includes
an opening that exposes a portion of the wiring layer as an external connection terminal;
an adhesive layer including an opening that is in communication with the opening of the solder resist layer; and
a carrier base material that is adhered by the adhesive layer to the solder resist layer to form the carrier base material-added wiring substrate, wherein the carrier base material includes an opening that is in communication with the opening of the solder resist layer and the opening of the adhesive layer and exposes the external connection terminal,
wherein the opening of the carrier base material is tapered so that the diameter of the opening of the carrier base material decreases from a lower surface of the carrier base material toward an upper surface of the carrier base material, and the opening of the adhesive layer is tapered so that the diameter of the opening of the adhesive layer decreases from a lower surface of the adhesive layer toward an upper surface of the adhesive layer,
wherein each of the opening of the carrier base material and the opening of the adhesive layer has a diameter that is smaller than that of the opening of the solder resist layer, and
wherein the adhesive layer is a separation layer that is separable from the solder resist layer to remove the carrier base material and the adhesive layer from the carrier base material-added wiring substrate.

US Pat. No. 10,340,213

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor device comprising:a substrate comprising:
a first substrate side, a second substrate side opposite the first substrate side, and a plurality of perimeter substrate sides extending between the first substrate side and the second substrate side;
a central pattern exposed at the first substrate side;
a dielectric layer;
a plurality of conductive vias connected to the central pattern, extending through the dielectric layer, and exposed at the second substrate side; and
an edge pattern exposed at the perimeter substrate sides and completely extending around the substrate; and
a semiconductor die coupled to the first substrate side,
wherein:
the edge pattern comprises a plurality of conductive layers exposed at the perimeter substrate sides and positioned directly laterally from the dielectric layer in a direction parallel to the first and second substrate sides;
a first conductive layer of the plurality of conductive layers comprises a plurality of perimeter sides, and extends a first distance directly laterally from the dielectric layer; and
a second conductive layer of the plurality of conductive layers comprises a plurality of perimeter sides, each of which extends a second distance directly laterally from the dielectric layer and is coplanar with a respective one of the perimeter sides of the first conductive layer, wherein the second distance is different from the first distance.

US Pat. No. 10,340,211

SENSOR MODULE WITH BLADE INSERT

NXP B.V., San Jose, CA (...

1. A sensor module, comprising:a dual gauge lead frame, the lead frame including:
a die pad,
a plurality of lead fingers spaced around the die pad and extending generally perpendicularly thereto, wherein each of the lead fingers has a proximal end near to the die pad and a distal end farther from the die pad, and
two or more blade-type leads having proximal ends connected to the distal ends of two or more of the plurality of lead fingers, wherein the die pad and the plurality of lead fingers have a first thickness and the blade-type leads have a second thickness that is greater than the first thickness;
a first semiconductor die attached on a top surface of the die pad;
first electrical connections connecting electrodes on an active surface of the first semiconductor die to the proximal ends of respective ones of the plurality of lead fingers;
a plurality of passive devices, each passive device mounted on and connected across respective pairs of the plurality of lead fingers;
a mold compound covering the die pad, the first semiconductor die, the plurality of passive devices, the first electrical connections, and the proximal ends of the plurality of lead fingers and the two or more blade-type leads, wherein the mold compound forms a generally rectangular molded body.

US Pat. No. 10,340,209

MIXED IMPEDANCE LEADS FOR DIE PACKAGES AND METHOD OF MAKING THE SAME

1. A die package comprising:a die having a plurality of connection pads;
a die substrate supporting a plurality of connection elements;
a first lead connected to at least one connection pad and having a first metal core with a first core diameter, and a dielectric layer surrounding the first metal core having a first dielectric thickness; and
a second lead connected to at least one connection pad and having a second metal core with a second core diameter, and a dielectric layer surrounding the second metal core having a second dielectric thickness, with the first dielectric thickness differing from the second dielectric thickness,
wherein the first lead has a first impedance and the second lead has a second impedance different from said first impedance, and
wherein at least one of the dielectric layers includes multiple layers of different dielectric compositions including a vapor barrier layer deposited over a second dielectric layer and being thinner than the second dielectric layer.

US Pat. No. 10,340,207

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor package comprising:a die pad;
a semiconductor chip provided on the die pad;
a lead frame separated from the die pad, the lead frame being electrically connected to a terminal of the semiconductor chip, the lead frame including a first part and a second part disposed between the first part and the die pad, an upper surface of the first part being located below an upper surface of the second part, the first part having a first surface perpendicular to a first direction, the first direction being from the die pad toward the lead frame, a lower end of the first surface being located above a lower surface of the second part and below an upper surface of the die pad; and
an insulating part provided on the die pad, the semiconductor chip, and the second part, the insulating part sealing the semiconductor chip.

US Pat. No. 10,340,205

THROUGH SUBSTRATE VIAS WITH IMPROVED CONNECTIONS

Taiwan Semiconductor Manu...

1. A device comprising:a substrate;
an interconnect structure over the substrate, the interconnect structure comprising:
a plurality of low-k dielectric layers;
a plurality of metallization layers in the plurality of low-k dielectric layers and comprising metal pads, wherein the metal pads comprises copper; and
a dielectric layer over the plurality of metallization layers, wherein a k value of the dielectric layer is higher than k values of the plurality of low-k dielectric layers;
a through-substrate via (TSV) extending from a top surface of the dielectric layer to a bottom surface of the substrate;
a first deep conductive via extending from the top surface of the dielectric layer and terminating on a first metal pad in a first one of the plurality of metallization layers;
a second deep conductive via extending from the top surface of the dielectric layer and terminating on a second metal pad in a second one of the plurality of metallization layers different from the first one; and
a metal line over the dielectric layer and electrically coupling the TSV to the first and the second deep conductive vias.

US Pat. No. 10,340,204

SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including an integrated circuit and an electrical contact, the electrical contact electrically connected to the integrated circuit;
an insulation layer covering the substrate, the insulation layer including,
an interlayer dielectric layer on the substrate,
an intermetal dielectric layer on the interlayer dielectric layer, and
a plurality of metal lines electrically connected to the integrated circuit; and
a through electrode penetrating the substrate, the through electrode electrically connected to the integrated circuit,
wherein the plurality of metal lines includes:
a first metal line that is provided in the interlayer dielectric layer and electrically connected to the electrical contact; and
a plurality of second metal lines that are provided in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode,
wherein the through electrode includes a top surface higher in relation to the substrate than a top surface of the electrical contact,
wherein a top surface of the first metal line are coplanar with a top surface of the interlayer dielectric layer,
wherein the electrical contact penetrates the interlayer dielectric layer from the substrate and contacts a lower surface of the first metal line, and
wherein a width of the first metal line is greater than a width of a bottom surface of the second metal lines.

US Pat. No. 10,340,203

SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA AND METHOD FOR FABRICATING AND TESTING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor structure with a through silicon via, comprising:a substrate comprising a front side and a back side, wherein the front side is opposite to the back side;
a plurality of dielectric layers comprising an inner circuit disposed on the front side of the substrate, wherein the inner circuit is disposed within the plurality of dielectric layers, each of the plurality of dielectric layers directly contacts one of the plurality of dielectric layers;
a first through silicon via penetrating the substrate;
a second through silicon via penetrating the substrate;
a first bond pad disposed on the front side, on the topmost surface of the dielectric layers and electrically connecting to the inner circuit and the first through silicon via;
a first test pad disposed on the front side, directly contacting and on the topmost surface of the plurality of dielectric layers and connecting electrically to the first bond pad, wherein the first bond pad and the first test pad are made of a continuous metal layer, the first bond pad is directly contacted to the first test pad, and the first test pad has a first surface which is exposed and is tested by a first probe;
a second bond pad disposed on the back side of the substrate and electrically connecting to the second through silicon via; and
a second test pad disposed on and directly contacting the back side of the substrate and connecting electrically to the second bond pad, wherein the second test pad has a second surface which is exposed and is tested by a second probe, the second surface is opposite to the first surface, and the second test pad is the bottommost metal layer of the semiconductor structure with a through silicon via.

US Pat. No. 10,340,200

SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A semiconductor device comprising:a first semiconductor chip comprising an electrode pad on one surface of the first semiconductor chip;
a multilayer chip stack that is disposed on the one surface of the first semiconductor chip to be connected to the electrode pad;
a plurality of columnar spacers disposed on the one surface of the first semiconductor chip, the plurality of columnar spacers surrounding the multilayer chip stack and disposed outside the outer periphery of the multilayer chip stack; and
an underfill resin,
wherein:
the multilayer chip stack comprises a plurality of second semiconductor chips each of which comprises a connection terminal;
the connection terminal of one of the second semiconductor chips is directly connected to the electrode pad;
another one of the second semiconductor chips is mounted on the one of the second semiconductor chips;
a gap between the first semiconductor chip and the one of the second semiconductor chips and a gap between adjacent ones of the second semiconductor chips are filled with the underfill resin; and
a height of each of the plurality of columnar spacers is greater than a height of the connection terminal of each of the plurality of second semiconductor chips.

US Pat. No. 10,340,196

METHOD AND SYSTEM FOR SELECTION OF METROLOGY TARGETS FOR USE IN FOCUS AND DOSE APPLICATIONS

KLA-Tencor Corporation, ...

1. A method of selecting metrology targets for use in a focus and dose application comprising:providing a focus and exposure matrix wafer including a plurality of fields, each field including one or more metrology targets to a metrology tool;
measuring the one or more metrology targets within each of the plurality of fields of the focus and exposure matrix wafer with one or more detectors of the metrology tool to obtain one or more measurement results;
providing the one or more measurement results to a controller including one or more processors, wherein the one or more processors are communicatively coupled to the one or more detectors;
selecting a subset of fields of the plurality of fields of the focus and exposure matrix wafer with the one or more processors, wherein the subset of fields includes a number of fields less than the entirety of the plurality of fields;
performing a regression process on the one or more measurement results of the one or more metrology targets in the selected subset of fields of the plurality of fields of the focus and exposure matrix wafer to determine one or more dimension of interest (DOI) values for the one or more metrology targets in the selected subset of fields of the plurality of fields with the one or more processors;
calculating a focus sensitivity, a library precision, and a printability for the one or more metrology targets in the selected subset of fields of the plurality of fields based on the regression process performed on the selected subset of fields of the plurality of fields of the focus and dose exposure matrix wafer with the one or more processors, wherein the library precision is determined via a parameter sensitivity and noise model for the one or more metrology targets;
identifying a set of candidate metrology targets based on the focus sensitivity, the library precision, and the printability calculated for the one or more metrology targets in the selected subset of fields of the plurality of fields of the focus and exposure matrix wafer with the one or more processors, wherein the library precision defines a quality level of a library able to be generated from the set of candidate metrology targets; and
configuring one or more semiconductor device process tools to reduce selection time of a target for at least one of controlling or monitoring focus and dose, wherein the one or more semiconductor device process tools are configured based on the set of target candidates.

US Pat. No. 10,340,194

GUARD RINGS INCLUDING SEMICONDUCTOR FINS AND REGROWN REGIONS

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor substrate;
a guard ring comprising:
a first plurality of semiconductor fins aligned to a first ring, wherein the first ring encircles a portion of the semiconductor substrate;
a plurality of gate stacks on sidewalls and top surfaces of the first plurality of semiconductor fins;
a plurality of semiconductor regions, with each comprising a portion between two of the first plurality of semiconductor fins; and
a well region overlapped by the plurality of semiconductor regions and the first plurality of semiconductor fins, wherein the plurality of semiconductor regions and the well region are of a same conductivity type; and
a second plurality of semiconductor fins aligned to a second ring, with the plurality of gate stacks further extending on sidewalls and top surfaces of the second plurality of semiconductor fins, wherein the second ring encircles the first ring.