US Pat. No. 10,193,148

CARBON-SILICON COMPOSITE AND MANUFACTURING METHOD THEREOF

OCI COMPANY LTD., Seoul ...

11. A carbon-silicon composite comprising:silicon-carbon-polymer carbonized matrix structure particles, comprising:
a polymer matrix having a network structure consisting of knots and chains connecting the knots with a cross-linking point;
carbon particles dispersed in the polymer matrix; and
silicon dispersed in the silicon-carbon-polymer carbonized matrix structure particles, wherein the silicon is bound to the carbon particles; and
a first carbon body, wherein the first carbon body is carbonized, and the silicon-carbon-polymer carbonized matrix structure particles are captured and dispersed in the first carbon body;
wherein the carbon particles are connected to each other and to the first carbon body to form inner pores,
wherein at least a portion of the silicon is in the inner pores,
wherein the silicon-carbon-polymer carbonized matrix structure particle has a porosity higher than a porosity of the first carbon body.

US Pat. No. 10,193,147

LIQUID SILICON POUCH ANODE AND CELL

The United States of Amer...

1. An electrochemical cell comprising:a cathode pouch;
a membrane having a first side sealed against said cathode pouch and defining a cathode volume therebetween and a second side, said membrane allowing communication of lithium ions between the first and second sides;
a catholyte positioned in said cathode volume, said catholyte comprising a lithium bearing material and an electrolyte;
a cathode current collector positioned within said cathode volume in electrical communication with said catholyte for providing a positive electrical charge on discharge of the electrochemical cell;
an anode pouch sealed against said membrane second side and defining an anode volume therebetween wherein said anode volume is responsive to pressure changes therein;
an anolyte positioned in said anode volume, said anolyte comprising a silicon-based lithium ion insertion material, an electrolyte, and conductive particles; and
an anode current collector positioned within said anode volume in electrical communication with said anolyte for providing a negative electrical charge on discharge of the electrochemical cell.

US Pat. No. 10,193,145

CARBON-COATED ACTIVE PARTICLES AND PROCESSES FOR THEIR PREPARATION

HYDRO-QUEBEC, Montreal, ...

1. A process for producing carbon-coated particles, the process comprising the steps of:a. forming an emulsion by mixing particles, acrylonitrile monomers, and an aqueous solvent, said particles comprising an electrochemically active material;
b. polymerizing the acrylonitrile monomers in the mixture of step (a) by emulsion polymerization;
c. drying the particles from step (b) to form a nano-layer of poly(acrylonitrile) at the surface of the particles; and
d. thermally treating the dried particles of step (c) to form the carbon-coated particles, said carbon consisting in a nano-layer of carbon comprising fibers on the surface of the particles.

US Pat. No. 10,193,142

LITHIUM-ION BATTERY ANODE INCLUDING PRELOADED LITHIUM

CF Traverse LLC, San Fra...

1. A battery anode comprising:a substrate;
a plurality of support structures attached to the substrate;
an active layer configured to receive lithium from an electrolyte with nanoparticles interspersed within the active layer; and
an under-layer disposed between the active layer and the support structures, the under-layer including lithium;
wherein the under-layer contains active material catalyzers which are disposed in a concentration gradient in the under-layer.

US Pat. No. 10,193,140

POSITIVE ACTIVE MATERIAL FOR RECHARGEABLE LITHIUM BATTERY AND RECHARGEABLE LITHIUM BATTERY

Samsung SDI Co., Ltd., Y...

1. A positive electrode for a rechargeable lithium battery, comprising:a positive active material consisting of LiCoO2 or LiaCoGbO2 (0.90?a?1.8, 0.001?b?0.1, G is Al, Cr, Mn, Fe, Mg, La, Ce, Sr, V, or a combination thereof); and
activated carbon having an average particle diameter larger than an average particle diameter of the positive active material and in a range of about 122% to about 160% relative to 100% of the average particle diameter of the positive active material,
wherein the positive active material and activated carbon are present in a mixed ratio in a range of about 98:2 to about 94:6.

US Pat. No. 10,193,139

REDOX AND ION-ADSORBTION ELECTRODES AND ENERGY STORAGE DEVICES

The Regents of the Univer...

1. An energy storage device comprising:a first electrode comprising:
a layered double hydroxide;
a three-dimensional graphene based conductive scaffold; and
a first current collector;
a second electrode comprising:
a hydroxide; and
a second current collector;
a separator; and
an electrolyte;
wherein the energy storage device stores energy through both redox reactions and ion adsorption; and
wherein the layered double hydroxide comprises a metallic layered double hydroxide comprising a zinc-based layered double hydroxide, an iron-based layered double hydroxide, an aluminum-based layered double hydroxide, a chromium-based layered double hydroxide, an indium-based layered double hydroxide, a manganese-based layered double hydroxide, or any combination thereof.

US Pat. No. 10,193,137

LITHIUM-ION BATTERIES WITH NANOSTRUCTURED ELECTRODES

WASHINGTON STATE UNIVERSI...

1. A method to produce an anode suitable for a lithium-ion battery, the method comprising:preparing a surface of an anode substrate, the anode substrate being at least partially compliant and having a compliance of about 3.0×10?7 to 8×10?12 l/Pa, wherein preparing the surface of the anode substrate comprises polishing the anode substrate, treating the anode substrate with a basic solution, treating the anode substrate with an acidic solution, or combinations thereof;
forming a plurality of conductive nanostructures on the surface of the anode substrate via electrodeposition; and
controlling at least one operating condition of the electrodeposition based on a target profile for the plurality of conductive nanostructures formed on the surface of the anode substrate, the target profile including the conductive nanostructures forming a plurality of freestanding structures.

US Pat. No. 10,193,135

POSITIVE ELECTRODE ACTIVE MATERIALS WITH COMPOSITE COATINGS FOR HIGH ENERGY DENSITY SECONDARY BATTERIES AND CORRESPONDING PROCESSES

Zenlabs Energy, Inc., Fr...

1. A particulate material comprising a core of lithium cobalt oxide, a partial coating with domains of a lithium manganese nickel cobalt oxide, and a distinct inert stabilization nanocoating, and having from about 2 weight percent to about 19 weight percent lithium manganese nickel cobalt oxide evaluated according to weight of added metal during coating formation.

US Pat. No. 10,193,131

RECHARGEABLE BATTERY

Samsung SDI Co., Ltd., Y...

1. A rechargeable battery comprising:an electrode assembly;
a case accommodating the electrode assembly;
a cap plate covering the case and having a first surface facing the electrode assembly and a second surface opposite the first surface, the cap plate including an injection hole extending from the first surface to the second surface and being sealed by a ball, the second surface having a recess depressed toward the first surface, the injection hole being arranged in the recess; and
a terminal plate covering the injection hole and the ball, the terminal plate including a first region in the recess below the second surface of the cap plate.

US Pat. No. 10,193,130

RECHARGEABLE BATTERY PACK

Samsung SDI Co., Ltd., G...

1. A rechargeable battery pack including:a battery cell including an electrode terminal in a cap plate and configured to perform charging and discharging operations;
a protection element connected to the electrode terminal via a first connecting tab;
a protection management package connected to a second connecting tab of the protection element and connected to the cap plate via an electrode tab;
a molding portion fully enclosing the protection element and the protection management package; and
an adhesive member disposed between the molding portion and the battery cell to attach them, wherein the adhesive member is not enclosed by the molding portion and wherein the first connecting tab has a bending portion with a bend between the electrode terminal and the protection element so as to set a height difference.

US Pat. No. 10,193,128

SWITCHING DEVICE FOR A BATTERY, AND BATTERY COMPRISING SAID SWITCHING DEVICE

Robert Bosch GmbH, Stutt...

1. A switching device (1) for a battery (2), wherein the switching device (1) is configured to be operated by an acoustic resonance effect in order to interrupt an electrical line of the battery (2) to a device located outside of the battery, wherein the switching device (1) has at least one container (12) which is prestressed by a spring element (11) and is configured to be destroyed by acoustic resonance.

US Pat. No. 10,193,127

BATTERY TERMINAL UNIT WITH CURRENT SENSOR

YAZAKI CORPORATION, Mina...

1. A battery terminal unit with a current sensor, the battery terminal unit comprising:a bus bar for a battery terminal, the bus bar including:
an attachment part configured to attach to a battery post;
an extension part extended from the attachment part; and
a connection part which continues from the extension part and is configured to connect to a wire harness; and
a current sensor including a board having a magnetic detection element and a shield plate having a U shape so that both ends of the shield plate are connected to the board so as to define two opening portions oppositely opening,
wherein the extension part is inserted through the openings and extends inside the current sensor,
wherein the board is opposed to a surface of the extension part inside the current sensor,
wherein the attachment part, the extension part, and the connection part are integrally formed, and are configured in a unity member, and
wherein the connection part is connected to one end of the extension part at an opposite side to the attachment part and extends in a transverse direction substantially perpendicular to an overhang direction of the extension part, so that a part of the connection part configured to be connect to the wire harness is disposed on a position offset from the extension part in the transverse direction, and
wherein the connection part includes an extending portion which is bent from the one end of the extension part in a vertical direction perpendicular to both of the overhang direction and the transverse direction so as to be erected in the vertical direction.

US Pat. No. 10,193,125

ELECTRODE ASSEMBLY AND SECONDARY BATTERY INCLUDING THE SAME

Samsung SDI Co., Ltd., Y...

1. An electrode assembly, comprising:a jelly roll comprising a first electrode plate wound together with a second electrode plate, the second electrode plate having a different polarity from the first electrode plate,
wherein the first electrode plate includes a plurality of non-coated portions spaced apart from each other; and
a plurality of tabs attached to the plurality of non-coated portions, respectively,
wherein the plurality of non-coated portions includes a first non-coated portion having a first width, and a second non-coated portion having a second width different from the first width of the first non-coated portion, and
wherein the first non-coated portion is between a winding center of the jelly roll and the second non-coated portion and spaced apart from the winding center, and the second non-coated portion is between the first non-coated portion and an end of the first electrode plate opposite to the center of the jelly roll and spaced apart from the end of the first electrode plate.

US Pat. No. 10,193,124

BATTERY CONNECTING BODY AND POWER SUPPLY DEVICE

YAZAKI CORPORATION, Mina...

1. A battery connecting body comprising:a plurality of connecting members that each connect electrodes of adjacent ones of a plurality of batteries arranged such that the electrodes thereof are arranged on a straight line to electrically connect the plurality of batteries; and
a casing that houses the plurality of connecting members, wherein
the casing includes a plurality of connecting member housing portions that each house each of the connecting members and cover portions that each cover an opening of each of the connecting member housing portions, and
the cover portions are each retained by protruding portions inside of the cover portions inserted into the connecting members wherein at least one of the connecting members is a bus bar.

US Pat. No. 10,193,123

BATTERY PACK BUS BAR ASSEMBLY WITH ENLARGED INTERCONNECT MOUNTING PLATFORMS

ATIEVA, INC., Menlo Park...

1. A battery assembly, comprising:a plurality of batteries, each battery of said plurality of batteries comprising a first terminal at a first end portion of said battery and a second terminal at said first end portion of said battery, wherein said plurality of batteries are divided into a plurality of battery groups, wherein said batteries within each battery group are electrically connected in parallel, and wherein said battery groups of said plurality of battery groups are electrically connected in series; and
a plurality of non-overlapping bus bars configured in an alternating pattern with said plurality of battery groups, wherein said alternating pattern alternates a single bus bar of said plurality of non-overlapping bus bars with a single battery group of said plurality of battery groups, each single bus bar of said plurality of non-overlapping bus bars comprising:
a plurality of first coupling segments extending from a first edge of said single bus bar, said plurality of first coupling segments electrically connecting said single bus bar to a plurality of first interconnect mounting platforms, wherein each of said plurality of first interconnect mounting platforms is electrically connected to a first subset of said plurality of batteries via said first terminals of said first subset of said plurality of batteries;
a plurality of second coupling segments electrically connecting said plurality of first interconnect mounting platforms to a plurality of second interconnect mounting platforms, wherein each of said plurality of second interconnect mounting platforms is electrically connected to a second subset of said plurality of batteries via said first terminals of said second subset of said plurality of batteries;
a plurality of third coupling segments extending from a second edge of said single bus bar, said plurality of third coupling segments electrically connecting said single bus bar to a plurality of third interconnect mounting platforms, wherein each of said plurality of third interconnect mounting platforms is electrically connected to a third subset of said plurality of batteries via said second terminals of said third subset of said plurality of batteries; and
a plurality of fourth coupling segments electrically connecting said plurality of third interconnect mounting platforms to a plurality of fourth interconnect mounting platforms, wherein each of said plurality of fourth interconnect mounting platforms is electrically connected to a fourth subset of said plurality of batteries via said second terminals of said fourth subset of said plurality of batteries.

US Pat. No. 10,193,122

NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A non-aqueous electrolyte secondary battery comprising:a separator; and
an electrode,
the separator including a base material layer and a heat resistance layer arranged on a surface of the base material layer,
the heat resistance layer containing inorganic particles and a resin binder,
the electrode facing the heat resistance layer,
the heat resistance layer including, in a direction of thickness of the heat resistance layer, a central portion and a first end portion and a second end portion between which the central portion lies,
the first end portion including an interface with the electrode,
the second end portion including an interface with the base material layer,
a content of the resin binder in the first end portion being not lower than 8 mass % and not higher than 30 mass % based on a total content of the resin binder and the inorganic particles in the heat resistance layer being 100 mass %;
a content of the resin binder in the second end portion being not lower than 8 mass % and not higher than 30 mass % based on the total content of the resin binder and the inorganic particles in the heat resistance layer being 100 mass %; and
a content of the resin binder in the central portion being not lower than 2 mass % and not higher than 7 mass % based on the total content of the resin binder and the inorganic particles in the heat resistance layer being 100 mass %.

US Pat. No. 10,193,121

SEPARATOR FOR LITHIUM SECONDARY BATTERY, LITHIUM SECONDARY BATTERY USING THE SEPARATOR, AND METHOD OF MANUFACTURING THE LITHIUM SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

1. A separator for a lithium secondary battery, the separator comprising:a porous base, at least a portion of the porous base comprising at least one selected from polyethylene terephthalate, polybutylene terephthalate, polyester, polyacetal, polyamide, polycarbonate, polyimide, polyether ether ketone, polyether sulfone, polyphenylene oxide, polyphenylene sulfide, polyvinylidene fluoride, polyethylene oxide, polyacrylonitrile, a polyvinylidene fluoride-hexafluoropropylene copolymer, polyethylene, and polypropylene; and
a first coating layer directly on a surface of the portion of the porous base and a second coating layer on a surface of the porous base opposite to the first coating layer, the first coating layer and the second coating layer each comprising a (meth)acrylic acid ester-based polymer having a glass transition temperature of about 10° C. to about 60° C.,
wherein the (meth)acrylic acid ester-based polymer is a polymerization product of an ethylenically unsaturated carboxylic acid ester and a monomer that is copolymerizable with the ethylenically unsaturated carboxylic acid ester,
wherein the ethylenically unsaturated carboxylic acid ester is a mixture of 2-ethylhexyl acrylate, isobornyl acrylate, and hydroxyethyl acrylate, or a mixture of methyl acrylate, ethyl acrylate, and hydroxyethyl acrylate, and
the monomer that is copolymerizable with the ethylenically unsaturated carboxylic acid ester is a mixture of acrylonitrile, methacrylic acid, acrylic acid, and ethylene dimethacrylate.

US Pat. No. 10,193,120

METHOD FOR FORMING ADHESION LAYER FOR SECONDARY BATTERY

LG CHEM, LTD., Seoul (KR...

1. A method for forming an adhesion layer, comprising:preparing a mask having openings which are open vertically;
etching a photosensitive film through the mask to form grooves corresponding to the openings of the mask in the photosensitive film;
pouring polydimethylsiloxane onto the photosensitive film having the grooves, curing the polydimethylsiloxane, and separating the cured polydimethylsiloxane from the photosensitive film to manufacture a polydimethylsiloxane mold having a concavo-convex part;
coating a polymer binder slurry on the polydimethylsiloxane mold having the concavo-convex part; and
transferring only the polymer binder slurry directly from the polydimethylsiloxane mold onto a surface of a separator or an electrode of a secondary battery to form an adhesion layer having a cavity part on the surface of the separator or the electrode, the cavity part being open vertically.

US Pat. No. 10,193,119

COMPOSITION FOR NON-AQUEOUS SECONDARY BATTERY FUNCTIONAL LAYER, FUNCTIONAL LAYER FOR NON-AQUEOUS SECONDARY BATTERY, AND NON-AQUEOUS SECONDARY BATTERY

ZEON CORPORATION, Chiyod...

1. A composition for non-aqueous secondary battery functional layer, comprising:non-conductive inorganic particles; and
organic particles, wherein
a difference in density calculated by subtracting the organic particles' density from the non-conductive inorganic particles' density is 1.5 g/cm3 or more, and
the organic particles each have a core-shell structure having a core and a shell that partially covers an outer surface of the core, wherein the core is made of polymer having a degree of swelling in electrolysis solution of 5 times to 30 times, and the shell is made of polymer having a degree of swelling in electrolysis solution of greater than 1 time to 4 times,
wherein the degree of swelling of polymer in electrolysis solution is calculated by W1/W0, where W0 indicates a weight of a film fabricated using the polymer, and W1 indicates a weight of the film after immersing into an electrolysis solution at 60° C. for 72 hours, the electrolysis solution being obtained by dissolving LiPF6 into a mixture solvent of 68.5% by volume of ethylene carbonate, 30 vol % of diethyl carbonate, and 1.5 vol % of vinylene carbonate at a concentration of 1 mol/L.

US Pat. No. 10,193,118

HYDROXIDE-ION-CONDUCTIVE DENSE MEMBRANE AND COMPOSITE MATERIAL

NGK Insulators, Ltd., Na...

1. A separator for a zinc secondary battery comprising a composite material including a porous alumina substrate and a hydroxide-ion-conductive dense membrane disposed on at least one surface of the porous alumina substrate, the hydroxide-ion-conductive dense membrane consisting of a layered double hydroxide dense membrane and having a He permeability per unit area of 10 cm/min·atm or less,wherein the porous alumina substrate has a water-permeable structure and an average pore size of 0.001 ?m to 1.5 ?m, and
wherein the layered double hydroxide dense membrane is formed from a stock solution containing at least two cations that are different from one another.

US Pat. No. 10,193,115

BATTERY COVER

East Penn Manufacturing C...

1. A battery cover, comprising:a lower battery cover, and
an upper battery cover matable with the lower battery cover to form a labyrinth and a plurality of battery cover sides including a terminal side and an opposite side, the labyrinth defined by a plurality of walls formed by the lower battery cover and the upper battery cover and having
a plurality of labyrinth cell passageways each extending only between one of a plurality of cell openings and one of a plurality of mixing areas positioned on the terminal side,
a plurality of exhaust passageways extending along an entirety of the opposite side of the upper battery cover, and
a channel disposed between the plurality of mixing areas and the plurality of exhaust passageways, the channel connecting the plurality of mixing areas to the plurality of exhaust passageways by extending from a lower end of each of the plurality of mixing areas at the terminal side and splitting into the plurality of exhaust passageways, the plurality of labyrinth cell passageways each extending to a position directly adjacent one of the plurality of exhaust passageways at the opposite side before leading to the one of the plurality of mixing areas at the terminal side, each of the plurality of labyrinth cell passageways is separated only by one of the plurality of walls from one of the plurality of exhaust passageways at the position directly adjacent one of the plurality of exhaust passageways.

US Pat. No. 10,193,109

PRISMATIC ELECTROCHEMICAL CELL

Bosch Battery Systems LLC...

1. An electrochemical cell comprising:a rigid cell housing having the shape of a rectangular prism, the cell housing including
an elongated rectangular first end,
an elongated rectangular second end, and
a sidewall that connects the first end to the second end, the sidewall having the form of a tube that has a rectangular cross-sectional shape, the sidewall including a pair of major sides joined by a pair of minor sides, where each side of the pair of major sides is larger in area than each side of the pair of minor sides;
an electrode assembly disposed in the cell housing, the electrode assembly comprising positive electrode plates alternating with negative electrode plates and separated by at least one separator to form an electrode stack;
a terminal that protrudes through the cell housing, the terminal being electrically connected to the positive plates or the negative plates via a weld free, electrically conductive snap-fit connection, and
a connector disposed in the cell housing between the electrode assembly and the first end, the connector comprising an electrically conductive strip of material that is folded over on itself so as to provide a U shaped configuration that includes a first leg portion that faces a second leg portion,whereinthe electrode assembly defines a stack axis that extends parallel to a stacking direction of the positive electrode plates, the negative electrode plates and the at least one separator,
the stack axis extends in a direction that is normal to, and passes through, the first minor side and the second minor side,
the terminal is disposed on an outer surface of the cell housing first end,
the first leg portion is electrically connected to the terminal and the second leg portion is electrically connected to one of the positive electrode plates and the negative electrode plates, and
the connector is folded over on itself along a first connector fold line and along a second connector fold line so as to provide an S shaped configuration that includes the first leg portion that faces one side of the second leg portion and a third leg portion that faces an opposed side of the second leg portion, wherein the second leg portion is electrically connected to one of the positive electrode plates and the negative electrode plates via the third leg portion.

US Pat. No. 10,193,107

ELECTRIC STORAGE DEVICE AND ELECTRIC STORAGE APPARATUS PROVIDED WITH THE ELECTRIC STORAGE DEVICE

GS YUASA INTERNATIONAL LT...

4. An electric storage device, comprising:an electrode assembly comprising a positive electrode plate and a negative electrode plate that are insulated from each other;
a case constituted by a partition wall, the case housing the electrode assembly;
a rivet member comprising a first insert part provided on one end and a body part joined to the first insert part, the rivet member being fixed to the partition wall; and
a first conductive member comprising a first insert-receiving part through which the first insert part is inserted, the first conductive member being electrically connected to the rivet member,
wherein the body part has a larger width in a direction intersecting an insertion direction of the first insert part than the first insert-receiving part, and is in contact with the first conductive member,
wherein the body part has a higher Vickers hardness than a region of the first conductive member in contact with the body part,
wherein the first insert part comprises, at a distal end of the first insert part, a swaged part that is swaged while the first insert part is inserted through the first conductive member, and
wherein a peripheral region of the first insert-receiving part of the first conductive member includes a tapered portion that is compressed and deformed in the insertion direction, and sandwiched between the swaged part and the body part of the rivet member.

US Pat. No. 10,193,106

METHOD FOR MANUFACTURING OLED DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing an OLED device, comprising steps of:a. providing a substrate and manufacturing an anode and a buffer layer in sequence on the substrate;
b. subjecting the substrate with the anode and the buffer layer thereon to an acid treatment;
c. drying the substrate and manufacturing a liquid light emitting layer on the buffer layer;
d. providing a cover plate and manufacturing a cathode and an electron transport layer in sequence on the cover plate;
e. subjecting the cover plate with the cathode and the electron transport layer thereon to the acid treatment; and
f. bonding the cover plate and the substrate together by lamination to obtain the OLED device.

US Pat. No. 10,193,105

ULTRAVIOLET IRRADIATION DEVICE FOR PACKAGE OF LIGHT-EMITTING DIODE

WUHAN CHINA STAR OPTOELEC...

1. An ultraviolet irradiation device for package of a light-emitting diode, wherein the ultraviolet irradiation device comprises:a sealed shell, wherein the light-emitting diode to he packaged is arranged in the shell, and a UV mask that is movable in the shell is arranged below the light-emitting diode;
a UV lamp, which is arranged below the UV mask; and
to a sealed chamber which is in communication with the shell, wherein the chamber is arranged at a side of the shell, wherein a first rolling unit configured to deliver the light-emitting diode is arranged in the chamber, and a first gate and a second gate are respectively arranged at two ends of the chamber, and wherein the chamber is further in communication with an air exhaust unit and a first gas source respectively.

US Pat. No. 10,193,104

ORGANIC LIGHT-EMITTING DIODE STRUCTURE AND FABRICATION METHOD THEREOF, RELATED DISPLAY PANEL, AND RELATED DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting diode device (OLED) structure for compensating blue light emission, comprising:a substrate with a thin-film transistor (TFT) layer, the substrate being substantially transparent;
a first electrode layer on the substrate, the first electrode being substantially transparent;
a first light-emitting layer on the first electrode layer with one or more light-emitting portions for emitting light for compensating blue light;
a charge generation layer (CGL) with a reflective portion, the CGL being on the first light-emitting layer, the reflective portion of the CGL having a transmission rate for light emitted by the first light-emitting layer;
a second light-emitting layer on the CGL with one or more light-emitting portions for emitting the blue light; and
a second electrode layer with a reflectivity on the second light-emitting layer, wherein:
the OLED structure includes a microcavity structure having the CGL, the second electrode layer, and the second light-emitting layer;
the first light-emitting layer includes a green light-emitting portion for emitting green light and a red light-emitting portion for emitting red light; and
a portion of the green light and a portion of the red light transmit into the microcavity to be converted into a second portion of blue light.

US Pat. No. 10,193,103

ORGANIC LIGHT EMITTING DEVICE HAVING PROTRUSION FORMED OF TRANSPARENT MATERIAL AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. An organic light emitting device, comprising an array substrate and a package substrate, wherein on a side of the package substrate facing the array substrate, there is provided a protrusion formed of a first transparent material, a surface of the protrusion is covered with a transparent layer formed of a second transparent material, and a refractive index of the second transparent material is larger than a refractive index of the first transparent material;a recess is disposed between the protrusions covered with the transparent layer of the second transparent material, and a side face of the recess is covered with the transparent layer of the second transparent material having the refractive index larger than that of the first transparent material of the protrusion, so that a part of light irradiated to the side face is totally reflected and changed in optical paths;
wherein the array substrate comprises a pixel defining layer formed thereon, and the transparent layer is directly contacted with the pixel defining layer.

US Pat. No. 10,193,102

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a substrate;
a plurality of pixels above the substrate, each of the pixels including a light emitting element;
a display region including the plurality of pixels;
a thin film transistor which each of the plurality of pixels includes;
a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element;
a sealing film including a second inorganic insulating material and covering the light emitting element; and
at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film,
wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.

US Pat. No. 10,193,101

ELECTRONIC DEVICE

SHARP KABUSHIKI KAISHA, ...

1. An electronic device comprising:a flexible substrate, a device portion supported on the flexible substrate, and a driver circuit portion;
a first flexible tube having a water vapor transmission rate of less than 10?3 g/(m2·24 h) and an oxygen transmission rate of less than 10?2 ml/(m2·24 h·MPa); and
a second flexible tube provided on an inner side of the first flexible tube and having a water vapor transmission rate of less than 10?3 g/(m2·24 h) and an oxygen transmission rate of less than 10?2 ml/(m2·24 h·MPa), wherein:
a first seal structure at one end of the first flexible tube and the second flexible tube and a second seal structure at another end of the first flexible tube and the second flexible tube define a sealed space between the first flexible tube and the second flexible tube;
the sealed space is defined by an inner surface of the first flexible tube, an outer surface of the second flexible tube, an inner surface of the first seal structure, and an inner surface of the second seal structure;
a portion of the flexible substrate and the device portion are inside the sealed space; and
a remainder of the flexible substrate, other than the portion of the flexible substrate that is inside the sealed space, is outside the sealed space.

US Pat. No. 10,193,100

ARRAY SUBSTRATE, FABRICATING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising: a thin film transistor, an auxiliary electrode, and a transparent cathode which is electrically connected with the auxiliary electrode, wherein both the auxiliary electrode and an active layer of the thin film transistor are directly arranged on a gate insulating layer of the thin film transistor, the active layer comprises an oxide semiconductor, and the auxiliary electrode is an electric conductor comprising a modified oxide semiconductor,wherein the array substrate further comprises a first etch-stopping layer which is arranged on the auxiliary electrode, and a passivation layer which is arranged on the gate insulating layer and covers the first etch-stopping layer,
wherein a via hole is arranged in the passivation layer, a via hole is arranged in the first etch-stopping layer, and the transparent cathode is electrically connected with the auxiliary electrode through the via hole in the first etch-stopping layer and the via hole in the passivation layer.

US Pat. No. 10,193,099

TRANSFORMABLE DEVICE AND METHOD OF MANUFACTURING THE SAME

LG DISPLAY CO., LTD., Se...

1. A display device, comprising:a display panel; and a transformable device wherein the transformable device includes:
an electro-active layer;
a first electrode inside the electro-active layer; and
a second electrode inside the electro-active layer on the first electrode and at a distance from the first electrode,
wherein the electro-active layer includes impurities, and
wherein a concentration of the impurities in the electro-active layer increases closer to the first electrode and the second electrode.

US Pat. No. 10,193,098

LIGHT EMITTING DEVICE MANUFACTURING METHOD AND APPARATUS THEREOF

INT TECH CO., LTD., Hsin...

1. A method of manufacturing a light emitting device, comprising:providing a substrate;
forming a plurality of photosensitive bumps over the substrate;
forming a photosensitive layer over the plurality of photosensitive bumps;
patterning the photosensitive layer to form a recess through the photosensitive layer to expose a surface;
disposing an organic emissive layer on the surface;
removing the patterned photosensitive layer; and
forming a buffer layer between the photosensitive layer and the plurality of photosensitive bumps.

US Pat. No. 10,193,096

ORGANIC LIGHT-EMITTING DIODE ARRAY SUBSTRATE AND DISPLAY APPARATUS

BOE Technology Group Co.,...

1. An organic light-emitting diode (OLED) array substrate, comprising a plurality of OLEDs,wherein each of the OLEDs comprises: an anode, a light-emitting layer configured for emitting light of a color, and a cathode which are provided in this order,
wherein a forming material of the light-emitting layer of each of the OLEDs comprises a host material and a guest material which is doped in the host material, and light-emitting layers of the OLEDs are configured for emitting light of a plurality of colors,
wherein each of the OLEDs further comprises an exciton barrier layer which is provided between the anode and the light-emitting layer and in contact with the light-emitting layer, and a forming material of the exciton barrier layer comprises a host material of one light-emitting layer that has a maximum highest occupied molecular orbital energy level amongst the host materials of all of the light-emitting layers of the OLEDs, and
wherein the light-emitting layers of the OLEDs comprise a red light-emitting layer, a green light-emitting layer and a blue light-emitting layer; the forming material of the exciton barrier layer comprises a host material of the blue light-emitting layer; and
HOMO energy levels of the host materials of the blue light-emitting layer, green light-emitting layer and red light-emitting layer gradually decrease, and LUMO energy levels of the host materials of the blue light-emitting layer, green light-emitting layer and red light-emitting layer gradually increase.

US Pat. No. 10,193,095

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:first and second guide plates facing each other;
a pair of first guide rails disposed in the first and second guide plates, respectively;
a pair of second guide rails disposed in the first and second guide plates, respectively;
a first supporting plate disposed between the first guide rails and the second guide rails at the first guide plate and the first and second guide rails at the second guide plate, wherein the first supporting plate has opposite end portions fixed to a first position of the first and second guide plates;
a second supporting plate configured to have opposite end portions coupled to the pair of first guide rails;
a third supporting plate configured to have opposite end portions coupled to the pair of second guide rails; and
a display panel supported by at least one of the first to third supporting plates,
wherein the pair of first guide rails are respectively formed to extend from the first position to a second position, and
the pair of second guide rails are respectively formed to extend from the first position to a third position, wherein the first position is disposed between the second position and the third position.

US Pat. No. 10,193,093

RADIATION DETECTOR

Kabushiki Kaisha Toshiba,...

1. A radiation detector, comprising:a first conductive layer;
a second conductive layer; and
an intermediate layer provided between the first conductive layer and the second conductive layer, the intermediate layer comprising an organic semiconductor region and a plurality of particles which comprise zinc selenide, the organic semiconductor region comprising a portion provided around the particles, a diameter being not less than 1 nanometer and not more than 20 nanometers for at least a portion of the particles, a first bandgap energy of the plurality of particles being larger than a second bandgap energy of the organic semiconductor region.

US Pat. No. 10,193,091

SCHOTTKY DIODE INCLUDING AN INSULATING SUBSTRATE AND A SCHOTTKY DIODE UNIT

Tsinghua University, Bei...

1. A Schottky diode comprising:a first electrode, wherein the first electrode comprises a first metal layer and a second metal layer, the first metal layer covers the second metal layer, one end of the second metal layer is extended with respect to the first metal layer to form a step structure in the first electrode;
a second electrode located apart from the first electrode, wherein the second electrode comprises a third metal layer and a fourth metal layer, the third metal layer covers the fourth metal layer, one end of the third metal layer protrudes with respect to the fourth metal layer to form an inverted step structure in the second electrode; and
a semiconductor structure comprising a first end and a second end, wherein the first end of the semiconductor structure is sandwiched by the first metal layer and the second metal layer, the second end of the semiconductor structure is sandwiched by the third metal layer and the fourth metal layer, a portion of the semiconductor structure between the first end and the second end is defined as a middle portion, the step structure of the first electrode and the inverted step structure of the second electrode are both located between the first end and the second end of the semiconductor structure, and near the middle portion of the semiconductor structure, the semiconductor structure is a carbon nanotube structure.

US Pat. No. 10,193,085

DELAYED FLUORESCENCE COMPOUND, AND ORGANIC LIGHT EMITTING DIODE AND DISPLAY DEVICE USING THE SAME

LG Display Co., Ltd., Se...

1. A delayed fluorescence compound of Formula 1:
wherein n is 1 or 0, wherein L2 is selected from Formula 2, X2 is selected from Formula 3, and Y is selected from Formula 4:

wherein each of R5 and R6 in the Formula 2 is independently selected from hydrogen or C1 alkyl through C10 alkyl.

US Pat. No. 10,193,075

ANILINE DERIVATIVE AND USE THEREOF

NISSAN CHEMICAL INDUSTRIE...

1. An aniline compound characterized by having formula (1)
wherein R1 to R5 are each independently a hydrogen atom, a halogen atom, a nitro group, a cyano group, or an alkyl group of 1 to 20 carbon atoms, alkenyl group of 2 to 20 carbon atoms, alkynyl group of 2 to 20 carbon atoms, aryl group of 6 to 20 carbon atoms or heteroaryl group of 2 to 20 carbon atoms which may be substituted with a halogen atom;
each Ph1 is independently a group of formula (P1)

(R6 to R9 being each independently a hydrogen atom, a halogen atom, a nitro group, a cyano group, or an alkyl group of 1 to 20 carbon atoms, alkenyl group of 2 to 20 carbon atoms, alkynyl group of 2 to 20 carbon atoms, aryl group of 6 to 20 carbon atoms or heteroaryl group of 2 to 20 carbon atoms which may be substituted with a halogen atom);
each Ar1 is independently a group having any of formulas (A1) to (A14);

and m is an integer from 3 to 5.

US Pat. No. 10,193,072

PYRENE-BASED COMPOUND AND ORGANIC LIGHT-EMITTING DIODE COMPRISING THE SAME

Samsung Display Co., Ltd....

1. A pyrene-based compound represented by Formula 1;or a pyrene-based compound being one of Compounds 5, 7, 15, 17, 36, 37, and 45 below:


wherein, in Formula 1,
L1 and L2 are each independently selected from
a phenylene group, a pentalenylene group, an indenylene group, a naphthylene group, an azulenylene group, a heptalenylene group, an indacenylene group, an acenaphthylene group, a fluorenylene group, a spiro-fluorenylene group, a phenalenylene group, a phenanthrenylene group, an anthrylene group, a fluoranthenylene group, a triphenylenylene group, a pyrenylene group, a chrysenylene group, a naphthacenylene group, a picenylene group, a perylenylene group, a pentaphenylene group, a hexacenylene group, a pyrrolylene group, an imidazolylene group, a pyrazolylene group, a pyridinylene group, a pyrazinylene group, a pyrimidinylene group, a pyridazinylene group, an isoindolylene group, an indolylene group, an indazolylene group, a purinylene group, a quinolinylene group, a benzoquinolinylene group, a phthalazinylene group, a naphthyridinylene group, a quinoxalinylene group, a quinazolinylene group, a cinnolinylene group, a phenanthridinylene group, an acridinylene group, a phenanthrolinylene group, a phenazinylene group, a benzooxazolylene group, a furanylene group, a benzofuranylene group, a thiophenylene group, a benzothiophenylene group, a thiazolylene group, an isothiazolylene group, a benzothiazolylene group, an isoxazolylene group, an oxazolylene group, a tetrazolylene group, a triazinylene group, a benzooxazolylene group, a benzocarbazolylene group, and a dibenzosilolylene group; each optionally substituted with at least one selected from
a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group,
a C1-C20 alkyl group and a C1-C20 alkoxy group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, and a phosphoric acid group or a salt thereof,
a C6-C20 aryl group, and
a C6-C20 aryl group each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, and an isoquinolinyl group;
R1 is one of the groups represented by Formulae 4-1(3), 4-2(1), 4-4(2), 4-4(3), 4-6(1), and 4-6(2):

wherein, in Formulae 4-1(3), 4-2(1), 4-4(2), 4-4(3), 4-6(1), and 4-6(2), Z11 and Z21 and Z21 to Z26 are each independently selected from
a hydrogen atom, a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group,
a C1-C20 alkyl group and a C1-C20 alkoxy group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, and a phosphoric acid group or a salt thereof,
a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, and an isoquinolinyl group,
a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a guinolinyl group, and an isoguinolinyl group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, and an isoquinolinyl group, and
—Si(Q13)(Q14)(Q15) (where Q13 to Q15 are each independently a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, or an isoquinolinyl group);
R2 is selected from
a hydrogen atom, a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group,
a C1-C20 alkyl group and a C1-C20 alkoxy group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, and a phosphoric acid group or a salt thereof,
a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, an isoquinolinyl group, a quinoxalinyl group,
a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, an isoquinolinyl group, a quinoxalinyl group, a dibenzopuranyl group, and a dibenzothiophenyl group, each substituted with at least one of a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, and an isoquinolinyl group, and
?Si(Q3)(Q4)(Q5),
wherein Q3 to Q5 are each independently a C1-C20 alkyl group, a alkoxy group, a phenyl group, a naphthyl group, an anthryl group, a fluorenyl group, a dimethylfluorenyl group, a diphenylfluorenyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridatinyl group, a triatinyl group, a quinolinyl group, or an isoquinolinyl group;
a1 and b1 are each independently an integer from 1 to 5; and
a2 and b2 are each independently an integer from 0 to 5.

US Pat. No. 10,193,062

MGO INSERTION INTO FREE LAYER FOR MAGNETIC MEMORY APPLICATIONS

Headway Technologies, Inc...

29. A method of forming a magnetic element exhibiting interfacial perpendicular anisotropy at a first interface between a composite free layer and a first oxide layer or a first non-magnetic metal or alloy (NM1) layer, at a second interface between the composite free layer and a second oxide layer or a second non-magnetic metal or alloy (NM2) layer, and at a plurality of interfaces where the composite free layer contacts a plurality of metal oxide regions in two metal layers each having a non-stoichiometric oxidation state that are formed within the composite free layer, comprising:(a) providing the first oxide layer or the NM1 layer on a substrate;
(b) depositing a first free layer (FL1) on the first oxide layer or the NM1 layer;
(c) depositing a first metal layer (M) or a first alloy (MQ) layer on FL1 where M is a first metal and Q is a second metal;
(d) depositing a second free layer (FL2) on the first M layer or first MQ layer;
(e) depositing a second metal layer (M2) or a second alloy layer (M2Q2) on the FL2;
(f) depositing a third free layer (FL3) on the M2 layer or M2Q2 layer to give the composite free layer comprising a FL1/M/FL2/M2/FL3, FL1/M/FL2/M2Q2/FL3, FL1/MQ/FL2/M2Q2/FL3, or FL1/MQ/FL2/M2/FL3 stack of layers;
(g) depositing the second oxide layer or the NM2 layer on a top surface of the composite free layer that faces away from the first oxide or NM1 layer; and
(h) performing an annealing step such that during one or more of steps (f), (g), and (h) a plurality of M and/or Q metal atoms in the M, M2, MQ, and M2Q2 layers scavenge oxygen from one or more layers in the magnetic element, and react with the scavenged oxygen to form a plurality of metal oxide regions on the M or MQ layer that interface with portions of the FL1 and the FL2, and a plurality of metal oxide regions on the M2 or M2Q2 layer that interfaces with portions of the FL2 and the FL3 thereby enhancing perpendicular magnetic anisotropy (PMA) in the composite free layer.

US Pat. No. 10,193,012

TRANSFERRING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS OF MICRO-LED

Goertek, Inc., Shandong ...

1. A method for transferring micro-LED, comprising:transferring at least one micro-LED from an original substrate to a support body;
transferring the at least one micro-LED from the support body to a backup substrate; and
transferring the at least one micro-LED from the backup substrate to a receiving substrate, wherein:
the original substrate is laser-transparent;
the support body is transparent;
transferring the at least one micro-LED from the original substrate to the support body comprises:
mounting the original substrate onto the support body, wherein micro-LEDs are formed on the original substrate, the support body has light-release adhesive on a surface of the support body, and the micro-LEDs are adhered to the support body via the light-release adhesive,
irradiating the original substrate with a laser from the original substrate side, to selectively lift-off the at least one micro-LED from the original substrate, and
irradiating light from the support body side, to release un-lifted-off micro-LEDs; and
transferring the at least one micro-LED from the support body to the backup substrate comprises:
bonding the support body with the at least one micro-LED to the backup substrate, and
fully irradiating light from the support body side, to release the at least one micro-LED.

US Pat. No. 10,193,007

SOLAR CELL MODULE AND METHOD FOR MANUFACTURING SAME

KANEKA CORPORATION, Osak...

1. A solar cell module comprising:a solar cell;
and a wiring member, wherein
the solar cell includes a photoelectric conversion section, a collecting electrode provided on a light-receiving side of the photoelectric conversion section, and a back electrode provided on a back side of the photoelectric conversion section,
the collecting electrode includes a plurality of finger electrodes each extending in a first direction, and a bus bar electrode extending in a second direction;
the bus bar electrode includes a first collecting electrode and a second collecting electrode stacked in this order from a photoelectric conversion section side, the second collecting electrode covering an entire length of the first collecting electrode,
the back electrode includes a first back electrode and a second back electrode stacked in this order from the photoelectric conversion section side,
the second collecting electrode and the second back electrode each have two or more layers,
a surface roughness Ral of the first collecting electrode and a surface roughness Ra2 of the second collecting electrode are configured to satisfy Ral>Ra2 and Ra2=1.0 pm to 10.0 ?m,
at least an outermost part of the second collecting electrode and at least an outermost part of the second back electrode are mainly composed of same electroconductive material,
the wiring member is composed of a core material and a conductor that covers a surface of the core material
the bus bar electrode of the solar cell and the conductor of the wiring member are electrically connected to each other, and
the solar cell is electrically connected to another solar cell via the wiring member.

US Pat. No. 10,192,998

ANALOG FLOATING-GATE ATMOMETER

TEXAS INSTRUMENTS INCORPO...

1. A method of measuring evaporation rate, comprising:applying a drain-to-source voltage to a floating-gate transistor in an integrated circuit;
capacitively coupling a voltage to a floating-gate electrode in the floating-gate transistor, to establish a gate-to-source voltage at that transistor;
then dispensing moisture at a surface of the integrated circuit at which an electrode in electrical contact with the floating-gate electrode and at least one reference electrode are exposed;
then monitoring current conducted by the floating-gate transistor to measure an elapsed time at which the current stabilizes; and
determining an evaporation rate responsive to the measured elapsed time.

US Pat. No. 10,192,995

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first insulator comprising a first region and a second region thinner than the first region;
a second insulator on and in contact with the first region of the first insulator;
a third insulator on and in contact with the second region of the first insulator;
a semiconductor over the second insulator;
a fourth insulator over the semiconductor; and
a first conductor overlapping the semiconductor with the fourth insulator interposed therebetween,
wherein the third insulator comprises fluorine,
wherein the amount of hydrogen released from the third insulator when converted into hydrogen molecules is less than or equal to 6×1014 molecules/cm2 in thermal desorption spectroscopy analysis at a surface temperature of a film of higher than or equal to 100° C. and lower than or equal to 700° C., and
wherein the third insulator does not overlap with the semiconductor.

US Pat. No. 10,192,994

OXIDE SEMICONDUCTOR FILM INCLUDING INDIUM, TUNGSTEN AND ZINC AND THIN FILM TRANSISTOR DEVICE

Sumitomo Electric Industr...

1. An oxide semiconductor film composed of nanocrystalline oxide or amorphous oxide, whereinthe oxide semiconductor film includes indium, tungsten and zinc,
a content rate of tungsten to a total of indium, tungsten and zinc in the oxide semiconductor film is higher than 0.5 atomic % and equal to or lower than 5 atomic %, and
an electric resistivity of the oxide semiconductor film is equal to or higher than 10?1 ?cm; wherein
an atomic ratio of zinc to tungsten (Zn/W ratio) in the oxide semiconductor film is equal to or higher than 3 and equal to or lower than 30.

US Pat. No. 10,192,993

THIN FILM TRANSFER, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor (TFT), comprising a substrate, a poly-silicon (p-Si) active layer arranged on the substrate, a first amorphous silicon (a-Si) layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate, and a buffer layer arranged on a surface of the substrate at a side adjacent to the first a-Si layer, wherein an orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate, a groove is formed in the buffer layer, and the first a-Si layer is arranged in the groove.

US Pat. No. 10,192,988

FLAT STI SURFACE FOR GATE OXIDE UNIFORMITY IN FIN FET DEVICES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
a fin structure having a top surface with substantially rounded corners, wherein upper portions of the fin structures have a surface profile including a top surface of the fin structure having corners with a radius of curvature R, where 0.1 W an isolation region formed over the substrate and in contact with at least a sidewall of the fin structure, the isolation region having a top surface with a substantially flat step height (?H?) based on a thermal hydrogen treatment, the substantially flat step height being defined by a downward slope from the sidewalls of the fin structure toward the top surface of the isolation region, the substantially flat step height (?H?) being defined by 0.1H1

US Pat. No. 10,192,987

FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A fin-type field effect transistor, comprising:a substrate having fins and insulators disposed between the fins, wherein at least one fin of the fins comprises a stop layer embedded within the at least one fin, and the stop layer is located below top surfaces of the insulators;
at least one gate stack, disposed on the fins and on the insulators; and
strained material portions, disposed on the at least one fin and disposed on two opposite sides of the at least one gate stack.

US Pat. No. 10,192,985

FINFET WITH DOPED ISOLATION INSULATING LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming one or more fins over a substrate;
forming a mask layer over the one or more fins;
forming an isolation insulating layer over the one or more fins so that top surfaces of the one or more fins and mask layer are buried inside the isolation insulating layer, and the isolation insulating layer contacts side surfaces of the one or more fins and mask layer;
introducing an oxygen reactive dopant into the isolation insulating layer;
annealing the isolation insulating layer containing the dopant and oxidizing the dopant; and
removing a portion of the doped isolation insulating layer so as to expose a portion of the one or more fins.

US Pat. No. 10,192,981

SWITCHING DEVICE WITH CHARGE DISTRIBUTION STRUCTURE

POWER INTEGRATIONS, INC.,...

1. A semiconductor device, comprising:a substrate;
a first active layer disposed over the substrate;
a second active layer disposed on the first active layer such that a lateral conductive channel arises between the first active layer and the second active layer;
a source, gate and drain contacts disposed over the second active layer; and
a conductive charge distribution structure disposed over the second active layer between the gate and drain contacts, said conductive charge distribution structure being coupled only capacitively to the gate contact, said conductive charge distribution structure including a plurality of components of said conductive charge distribution structure, a first charge distribution structure component of said conductive charge distribution structure being only capacitively coupled to the gate contact and a second charge distribution structure component of said conductive charge distribution structure being only capacitively coupled to the first charge distribution structure component, each of the first and second charge distribution structure components including a first elongate member formed in a first portion and a second elongate member formed in a second portion such that each of the first and second charge distribution structure components of the capacitively-coupled charge distribution structure matches its potential with that of corresponding portion of the lateral conductive channel beneath the first and second charge distribution structure components, respectively;
wherein the length of the lateral conductive channel is less than twenty five microns.

US Pat. No. 10,192,972

SEMICONDUCTOR FERROELECTRIC STORAGE TRANSISTOR AND METHOD FOR MANUFACTURING SAME

NATIONAL INSTITUTE OF ADV...

17. A semiconductor ferroelectric memory transistor comprising a semiconductor body which has a source region and a drain region on which an insulator and a gate electrode conductor are stacked in that order, whereinthe insulator comprises a ferroelectric insulator comprising an oxide of strontium, calcium, bismuth, and tantalum, and the oxide of strontium, calcium, bismuth, and tantalum is represented by Sr-Ca-Bi-Ta-O.

US Pat. No. 10,192,965

SEMICONDUCTOR DEVICE INCLUDING FIRST AND SECOND GATE ELECTRODES AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor substrate;
a first gate electrode formed on a main surface of the semiconductor substrate;
a first gate insulating film formed between the first gate electrode and the semiconductor substrate;
a second gate electrode formed on the semiconductor substrate and adjacent to the first gate electrode; and
a second gate insulating film formed between the second gate electrode and the semiconductor substrate and between the second gate electrode and the first gate electrode and having a charge accumulating portion therein,
wherein the semiconductor substrate includes a first region, a second region, and a third region on the main surface side,
the second region is arranged closer to a first side than the first region in a first direction in a plan view,
the third region is arranged between the first region and the second region,
the first gate electrode is formed on a first upper surface of the first region,
the second gate electrode is formed on a second upper surface of the second region,
the second upper surface is lower than the first upper surface,
the third region has a first connection surface connecting the first upper surface and the second upper surface,
the second gate insulating film is formed on the first connection surface and the second upper surface,
a first end of the first connection surface is connected to the second upper surface,
a second end of the first connection surface which is on the opposite side to the first end is connected to the first upper surface,
the first end is arranged closer to the first side than the second end in the first direction, and is arranged lower than the second end, and
the first connection surface has a constant slope between the first end and the second end wherein the semiconductor substrate includes a fourth region on the main surface side, the fourth region is arranged closer to the opposite side to the first side than the first region in the first direction in a plan view, a third upper surface of the fourth region is lower than the first upper surface, and the second upper surface is lower than the third upper surface.

US Pat. No. 10,192,964

COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

FUJITSU LIMITED, Kawasak...

1. A compound semiconductor device comprising:a carrier transit layer;
a carrier supply layer over the carrier transit layer;
a source electrode and a drain electrode above the carrier supply layer;
a gate electrode above the carrier supply layer between the source electrode and the drain electrode; and
a first insulating film, a second insulating film, and a third insulating film above the carrier supply layer between the gate electrode and the drain electrode, wherein
the gate electrode includes a portion above the third insulating film,
a first concentration of electron traps in the first insulating film is higher than a second concentration of electron traps in the second insulating film,
a third concentration of electron traps in the third insulating film is higher than the second concentration of the electron traps in the second insulating film, and
the third insulating film has a lamer size than the first insulating film in planar view.

US Pat. No. 10,192,963

COMPOSITE GATE DIELECTRIC LAYER APPLIED TO GROUP III-V SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

INSTITUTE OF MICROELECTRO...

1. A composite gate dielectric layer for a Group III-V substrate, comprising:an AlxY2-xO3 interface passivation layer formed on the group III-V substrate by thermally treating an Al2Om passivation layer formed on the group III-V substrate and a Y2On strengthening layer formed on the Al2Om passivation layer in situ to mix the Al2Om passivation layer and the Y2On strengthening layer; and
a high-k dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2?x?1.9.

US Pat. No. 10,192,961

SILICON CARBIDE SEMICONDUCTOR DEVICE

Sumitomo Electric Industr...

1. A silicon carbide semiconductor device comprising:a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface; and
a gate insulating film provided on the first main surface,
the silicon carbide substrate including
a first body region being in contact with the gate insulating film at the first main surface and having a first conductivity type,
a second body region being in contact with the gate insulating film at the first main surface and having the first conductivity type, and
a JFET region provided between the first body region and the second body region and having a second conductivity type different from the first conductivity type,
the JFET region having both a first impurity capable of providing the first conductivity type and a second impurity capable of providing the second conductivity type,
a concentration of the second impurity being higher than a concentration of the first impurity,
the first conductivity type being p type and the second conductivity type being n type, and
the concentration of the first impurity increases from the second main surface toward the first main surface.

US Pat. No. 10,192,960

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Sumitomo Electric Industr...

1. A silicon carbide semiconductor device comprising:a silicon carbide layer having a first main surface and a second main surface opposite to said first main surface; and
a metal region,
said silicon carbide layer including
a drift region that constitutes said first main surface and that has a first conductivity type,
a body region that is provided on said drift region and that has a second conductivity type different from said first conductivity type, and
a source region that is provided on said body region to be separated from said drift region, that constitutes said second main surface, and that has the first conductivity type,
said silicon carbide layer being provided with a trench including a first side wall portion and a first bottom surface, said first side wall portion extending from said second main surface to said drift region through said source region and said body region, said first bottom surface being in said drift region,
said silicon carbide layer including a second conductivity type region that is embedded in said drift region to face said first bottom surface and that has said second conductivity type,
said second conductivity type region being separated from said body region,
said second conductivity type region being electrically connected to said source region,
said metal region being in contact with said source region,
said source region and said second conductivity type region being electrically connected to each other via said metal region,
said silicon carbide layer being provided with a stepped portion including a second bottom surface and a second side wall portion, said second bottom surface being between said first main surface and said second main surface, said second side wall portion connecting said second bottom surface and said second main surface to each other,
said metal region being in contact with said source region in said second main surface and is in contact with said second bottom surface,
said second conductivity type region being arranged in a plane, and
said metal region being directly in contact with said second conductivity type region.

US Pat. No. 10,192,958

CELLULAR LAYOUT FOR SEMICONDUCTOR DEVICES

GENERAL ELECTRIC COMPANY,...

1. A system, comprising:a rectangular semiconductor device cell disposed at a surface of a silicon carbide (SiC) semiconductor layer, wherein the semiconductor device cell comprises:
a drift region having a first conductivity type;
a well region having a second conductivity type disposed adjacent to the drift region;
a source region having the first conductivity type disposed adjacent to the well region and surrounded by the well region;
a rectangular channel region having the second conductivity type disposed around and adjacent to the source region and proximal to the surface;
a body contact region having the second conductivity type disposed over a portion of the well region, wherein the body contact region is disposed substantially in the center of a plane of the source region defined by the surface; and
a segmented source and body contact (SSBC) disposed over a portion of the surface, wherein the SSBC comprises:
a body contact portion disposed over the body contact region substantially in the center of the semiconductor device cell; and
at least one source contact portion disposed adjacent to the body contact region and over a portion of the source region, wherein the at least one source contact portion does not completely surround the body contact portion of the SSBC, wherein the semiconductor device cell includes only one SSBC.

US Pat. No. 10,192,954

JUNCTIONLESS NANOWIRE TRANSISTOR AND MANUFACTURING METHOD FOR THE SAME

Wuhan China Star Optoelec...

1. A junctionless nanowire transistor, comprising:an active layer, a barrier layer, a source region, a source electrode, a drain region, a drain electrode, a gate electrode, first insulation medium and at least two channel nanowires;
wherein, the source region and the drain region are disposed on the active layer; the at least two channel nanowires are disposed above the active layer in a stacked arrangement, and two terminals of each of the at least two channel nanowires are respectively connected with the source region and the drain region; the barrier layer is located at a side of the active layer away from the source region and the drain region; the source electrode and the drain electrode are respectively disposed on the source region and the drain region; the first insulation medium is disposed between the at least two channel nanowires and the gate electrode;
the source region, the drain region and the at least two channel nanowires uses a same doping material; and
the source electrode, the drain electrode and the gate electrode are manufactured by a same material; and
the junctionless nanowire transistor further comprises a second insulation medium having a first part, a second part and a third part, wherein the first part of the second insulation medium is disposed on the active layer and surrounds bottoms of the source region, the drain region and the gate electrode so as to expose tops of the source region and the drain region, the second part and the third part of the second insulation medium are disposed at two sides of the gate electrode.

US Pat. No. 10,192,953

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE

Sumitomo Electric Industr...

1. A silicon carbide semiconductor device comprising:a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to said first main surface;
an epitaxial layer formed on said first main surface, said epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which said silicon carbide substrate is located;
a trench which is formed in said epitaxial layer and includes side walls intersecting with said third main surface and a bottom portion connected to said side walls; and
an embedded region, which is formed in said trench and has a second conductivity type different from said first conductivity type, said trench being filled with said embedded region;
an opening of said trench being wider than said bottom portion, and said epitaxial layer adjacent to said embedded region and said embedded region constituting a superjunction structure, said silicon carbide semiconductor device further comprising:
an impurity region formed on said embedded region and having said second conductivity type;
a first electrode provided on said impurity region; and
a second electrode in contact with said second main surface.

US Pat. No. 10,192,948

AMOLED DISPLAY DEVICE AND ARRAY SUBSTRATE THEREOF

SHENZHEN CHINA STAR OPTOE...

1. An array substrate of an AMOLED display device, comprising a baseplate, a surface-shaped power line, a point-shaped power line, and a plurality of insulating layers arranged between the surface-shaped power line and the point-shaped power line,wherein the surface-shaped power line and the point-shaped power line are configured to provide a positive polarity power source to a light-emitting diode; and
wherein the surface-shaped power line is formed on the baseplate, the point-shaped power line is formed on the plurality of insulating layers, and the surface-shaped power line and the point-shaped power line are electrically connected to each other through a via hole;
further comprising a metal lead wire formed on an edge area thereof, wherein the metal lead wire is used for leading a power source signal to the surface-shaped power line;
wherein the metal lead wire and the point-shaped power line are arranged in a same layer, and the metal lead wire and the surface-shaped power line are electrically connected to each other through a via hole.

US Pat. No. 10,192,939

DISPLAY DEVICE AND FABRICATION METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising:a thin film transistor array and an organic light emitting diode (OLED) pixel array on a base substrate;
an encapsulation film encapsulating the thin film transistor array and the OLED pixel array;
a protection film over the encapsulation film, the protection film including a first retardation film;
a touch film on the protection film, the touch film including a second retardation film; and
a polarizer film on the touch film,
wherein each of the first and second retardation films includes a ?? retardation film.

US Pat. No. 10,192,937

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate including a display area and a non-display area;
a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels which displays a different color from a color of the first pixel column; and
data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column,
wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines,
in the non-display area, the sub lines connected to the first pixel column are connected with one another through at least one first contact hole, the sub lines connected to the second pixel column are connected with one another through at least one second contact hole, and the sub lines connected to the second pixel column are connected through the at least one second contact hole having a larger area than an area of the at least one first contact hole, through which the sub lines connected to the first pixel column are connected with one another, and
wherein a resistance of the data line connected to the first pixel column is provided to be relatively larger than a resistance of the sub lines connected to the second pixel column.

US Pat. No. 10,192,934

LIGHT-EMITTING DEVICE HAVING LIGHT EMISSION BY A SINGLET EXCITON AND A TRIPLET EXCITON

Semiconductor Energy Labo...

1. An active matrix type light emitting device comprising a pixel portion comprising:a first pixel which emits red light comprising:
a first EL element comprising a hole injecting layer and a light emitting layer between a first electrode and a second electrode;
a first current controlling TFT electrically connected to the first electrode, wherein the first current controlling TFT is configured to control a current flowing in the first EL element;
a first switching TFT configured to control a signal to be input to a gate electrode of the first current controlling TFT; and
a first capacitor electrically connected to the gate electrode of the first current controlling TFT, wherein the first capacitor is configured to maintain a voltage applied to the gate electrode of the first current controlling TFT;
a second pixel which emits green light comprising:
a second EL element comprising a hole injecting layer and a light emitting layer between a third electrode and a fourth electrode;
a second current controlling TFT electrically connected to the third electrode, wherein the second current controlling TFT is configured to control a current flowing in the second EL element;
a second switching TFT configured to control a signal to be input to a gate electrode of the second current controlling TFT; and
a second capacitor electrically connected to the gate electrode of the second current controlling TFT, wherein the second capacitor is configured to maintain a voltage applied to the gate electrode of the second current controlling TFT;
a third pixel which emits blue light comprising:
a third EL element comprising a hole injecting layer and a light emitting layer between a fifth electrode and a sixth electrode;
a third current controlling TFT electrically connected to the fifth electrode, wherein the third current controlling TFT is configured to control a current flowing in the third EL element;
a third switching TFT configured to control a signal to be input to a gate electrode of the third current controlling TFT; and
a third capacitor electrically connected to the gate electrode of the third current controlling TFT, wherein the third capacitor is configured to maintain a voltage applied to the gate electrode of the third current controlling TFT;
an insulating film over the first current controlling TFT, the second current controlling TFT, and the third current controlling TFT,
wherein the insulating film comprises a first opening, a second opening, and a third opening,
wherein the first electrode overlaps with the first opening,
wherein the third electrode overlaps with the second opening,
wherein the fifth electrode overlaps with the third opening,
wherein an upper surface of the insulating film is provided over an upper surface of the first electrode, an upper surface of the third electrode, and an upper surface of the fifth electrode,
wherein the hole injecting layer included in the first EL element, the hole injecting layer included in the second EL element, and the hole injecting layer included in the third EL element are provided as a common layer,
wherein the second electrode, the fourth electrode, and the sixth electrode are provided as a common layer,
wherein the first EL element included in the first pixel which emits red light is configured to emit light by a triplet exciton,
wherein the third EL element included in the third pixel which emits blue light is configured to emit light by a singlet exciton, and
wherein an operation voltage of the first EL element, an operation voltage of the second EL element, and an operation voltage of the third EL element are in a range of 10 V or less.

US Pat. No. 10,192,929

THREE-DIMENSIONAL MEMORY DEVICES HAVING THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory structures vertically extending through the alternating stack, wherein each of the memory structures includes memory elements located at levels of the electrically conductive layers;
conductive structures located between the substrate and the alternating stack; and
conductive via structures, wherein each conductive via structure contacts a top surface of a respective one of the electrically conductive layers and a top surface of a respective one of the conductive structures, and is electrically insulated from a respective subset of the electrically conductive layers that is located between the respective one of the electrically conductive layers and the conductive structures,
wherein each conductive via structure comprises an upper conductive via portion located directly on, and over, the top surface of the respective one of the electrically conductive layers, and a lower conductive via portion located between a horizontal plane including the top surface of the respective one of the electrically conductive layers and a horizontal plane including the top surface of the respective one of the conductive structures; and
wherein:
each upper conductive via portion is laterally surrounded by a respective upper insulating spacer;
each lower conductive via portion is laterally surrounded by a respective lower insulating spacer; and
the upper and lower insulating spacers comprise a same dielectric material.

US Pat. No. 10,192,923

PHOTODIODE ARRAY

HAMAMATSU PHOTONICS K.K.,...

1. A photodiode array comprising:avalanche photodiodes;
an insulating layer provided at a light incident side of a semiconductor substrate, covering the avalanche photodiodes; and
quenching resistors respectively connected to the avalanche photodiodes, each quenching resistor being provided on the insulating layer and arranged to cover an edge of a semiconductor region that forms one side of each avalanche photodiode,
wherein each of the quenching resistors includes:
an upper surface,
a lower surface, and
side surfaces extending along a surface of the insulating layer in a plan view, a strip of the quenching resistor defined by the side surfaces and forming a ring-like strip shape in the plan view.

US Pat. No. 10,192,918

IMAGE SENSOR INCLUDING DUAL ISOLATION AND METHOD OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:providing a mask over a substrate, wherein the substrate has a pixel area and a periphery area;
patterning a first opening in the pixel area and a second opening in the periphery area;
etching the mask via the first opening and the second opening;
protecting an entirety of the periphery area;
etching the substrate via the first opening to form a first STI structure having a first depth;
protecting the pixel area;
etching the substrate via the second opening to form a second STI structure having a second depth deeper than the first depth;
depositing an oxide layer in the first and the second STI structures;
removing the mask and an entirety of the oxide layer located above a top surface of the substrate, wherein after removal a surface of the oxide layer is coplanar with the top surface of the substrate;
forming at least one photo detector comprising one or more first NMOS devices in the pixel area, with the proviso that the pixel area does not contain any PMOS devices; and
forming second NMOS devices and PMOS devices in the periphery area.

US Pat. No. 10,192,907

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

10. An array substrate, comprising:a base substrate; and
a first conductive pattern, a second conductive pattern, and an insulating pattern disposed on the base substrate, the insulating pattern at least covering an upper surface of the first conductive pattern, wherein
the first conductive pattern comprises a first crystalline transparent conductive pattern and a first metallic pattern, the first crystalline transparent conductive pattern is closer to the base substrate than the first metallic pattern; and the second conductive pattern comprises a second crystalline transparent conductive pattern.

US Pat. No. 10,192,906

TOUCH DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of a touch display substrate, comprising steps of:forming a touch signal line on a base substrate through patterning process;
depositing a photoresist layer and forming a first thickness photoresist layer, a second thickness photoresist layer, and a photoresist layer opening area through patterning process, the touch signal line being located in the photoresist layer opening area;
depositing a first insulating layer on the photoresist layer, the first insulating layer comprising a first area and a second area, wherein the first area is located on the first thickness photoresist layer, the second area is located on the second thickness photoresist layer and the photoresist layer opening area, the first area and the second area of the first insulating layer are disconnected;
removing the photoresist layer and the first insulating layer located on the photoresist layer; and
depositing a second insulating layer.

US Pat. No. 10,192,905

ARRAY SUBSTRATES AND THE MANUFACTURING METHODS THEREOF, AND DISPLAY DEVICES

Shenzhen China Star Optoe...

1. A manufacturing method of array substrates, the method adopting four masking processes to obtain the array substrate and at least one pixel electrode within the array substrate, wherein a second masking process to form an active layer, a source electrode, and a drain electrode comprising:forming a semiconductor thin-film layer, N+ doping thin-film layer, a metal thin-film layer, and a photo-resistor layer on a gate insulation layer in sequence;
applying a gray-tone-mask process to expose and develop the photo-resistor layer to obtain a first photo-resistor mask;
under protection of the first photo-resistor mask, applying a first wet etching process to etch a portion of the metal thin-film layer that is not covered by the first photo-resistor mask;
under the protection of the first photo-resistor mask, applying a first dry etching process to etch portions of the semiconductor thin-film layer and the N+ doping thin-film layer that are not covered by the first photo-resistor mask to obtain the active layer;
applying a plasma ashing process to the first photo-resistor mask to obtain a second photo-resistor mask, and the metal thin-film layer is exposed by a central area of the second photo-resistor mask;
under the protection of the second photo-resistor mask, applying a second wet etching process to etch away a portion of the metal thin-film layer that is not covered by the second photo-resistor mask to obtain the source electrode and the drain electrode; and
peeling off the second photo-resistor mask, applying a second dry etching process to etch away the portion of the N+ doping thin-film layer between the source electrode and the drain electrode to obtain the N+ contact layer respectively between the source electrode and the active layer and between the drain electrode and the active layer.

US Pat. No. 10,192,904

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE

BOE Technology Group Co.,...

1. A manufacturing method of an array substrate, comprising:forming, on a base substrate and via one patterning process, a transparent conductive pattern layer, a pattern layer including a pixel electrode, and a pattern layer including a gate electrode and a gate line, the transparent conductive pattern lying in a same level as the pixel electrode;
on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, through one patterning process or two patterning processes, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer, wherein the etch stop layer comprises a first portion which is, along a gate line direction, between a second via hole and a third via hole that are located on two sided of the gate electrode; wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode; and
on the substrate with the etch stop layer formed thereon, through one patterning process, forming a pattern layer including a source electrode, a drain electrode and a data line, wherein, the source electrode and the drain electrode each contact with the metal oxide semiconductor active layer, and the drain electrode and the pixel electrode are electrically connected through the first via hole.

US Pat. No. 10,192,903

METHOD FOR MANUFACTURING TFT SUBSTRATE

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing a TFT substrate, comprising:step 101: providing a substrate and depositing a buffer layer on the substrate, wherein the substrate includes a drive TFT region and a display TFT region;
step 102: depositing a first amorphous silicon layer on the buffer layer, and performing excimer laser annealing on the first amorphous silicon layer so as to convert the first amorphous silicon layer into a first polysilicon layer through crystallization;
patterning the first polysilicon layer, to obtain a first active layer that is located in the drive TFT region;
step 103: depositing a gate insulating layer on the first active layer and the buffer layer;
depositing and patterning a first metal layer on the gate insulating layer, to form a first gate electrode at a position corresponding to position of the first active layer and form a second gate electrode at a position corresponding to position where the first active layer is not arranged;
step 104: implanting ions into the gate insulating layer taking the first gate electrode and the second gate electrode as a shading layer;
step 105: depositing an interlayer insulating layer on the gate insulating layer, the first gate electrode and the second gate electrode, depositing a second amorphous silicon layer on the interlayer insulating layer, implanting ions into the second amorphous silicon layer, and performing solid phase crystallization on the second amorphous silicon layer so as to convert the second amorphous silicon layer into a second polysilicon layer;
patterning the second polysilicon layer to form a second active layer at a position corresponding to the second gate electrode;
wherein the second amorphous silicon layer is implanted with boron (B) ions;
step 106: forming a first via hole and a second via hole in the gate insulating layer and the interlayer insulating layer corresponding to the first active layer, and forming a third via hole in the interlayer insulating layer corresponding to the second gate electrode;
step 107: depositing a source-drain electrode layer, patterning the source-drain electrode layer, and forming a channel on a surface of the second active layer at the same time;
step 108: depositing a passivation layer and patterning the passivation layer, depositing a flat layer on the passivation layer, and forming a fourth via hole in the flat layer at a position thereof in the display TFT region, the fourth via hole extending to a surface of the source-drain electrode layer; and
step 109: depositing an anode electrode on the flat layer, the anode electrode being in contact with the source-drain electrode layer through a fourth via hole, depositing a pixel definition layer, and defining a pattern, so that the TFT substrate is manufactured.

US Pat. No. 10,192,902

LTPS ARRAY SUBSTRATE

Shenzhen China Star Optoe...

1. A low temperature poly-silicon (LTPS) array substrate, comprising:a substrate;
a source electrode and a drain electrode, which are arranged on the substrate;
a poly-silicon layer, which is arranged on the substrate including the source electrode and the drain electrode, wherein the poly-silicon layer partially covers the source electrode and the drain electrode;
an insulating layer, which is arranged on the poly-silicon layer and the source and drain electrodes, wherein the insulating layer is formed through passivation of a part of the poly-silicon layer that covers the substrate including the source electrode and the drain electrode;
a gate electrode, which is arranged on the insulating layer between the source electrode and the drain electrode, wherein the source and drain electrodes, the poly-silicon layer, and the gate electrode collectively form a thin-film transistor (TFT);
a planar layer, which is arranged on the substrate including the gate electrode, wherein the planar layer is formed with a contact hole extending therethrough to expose a surface of the drain electrode;
a common electrode, which is arranged on the planar layer except the TFT of the LTPS array substrate;
a passivation layer, which is arranged on the planar layer and the common electrode layer, such that the passivation layer does not cover the contact hole;
a pixel electrode, which is arranged on the passivation layer, wherein the pixel electrode is electrically connected with the drain electrode through the contact hole;
wherein the poly-silicon layer has a first region that is stacked atop and covers an inner part of each of the source electrode and the drain electrode and a portion of the substrate that is between the source electrode and the drain electrode and a second region that is integrally extended from the first region and is partly stacked atop and covers an outer part of each of the source electrode and the drain electrode; and
wherein the first region of the poly-silicon has a thickness that is greater than a thickness of the second region of the poly-silicon and the first region of the poly-silicon has a lower part in direct contact with the inner parts of the source electrode and the drain electrode and the portion of substrate between the source electrode and the drain electrode and an upper part that forms a first portion of the insulating layer; and the second region of the poly-silicon, in the entirety thereof, forms a second portion of the insulating layer that integrally extends from the first portion of the insulating layer, such that the insulating layer is integrally combined with the lower part of the poly-silicon layer and is extended to cover the source electrode and the drain electrode.

US Pat. No. 10,192,901

ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode (OLED) display comprising:a substrate;
a transistor on the substrate; and
an organic light emitting diode (OLED) connected to the transistor,
wherein the transistor includes:
a semiconductor member on the substrate,
an insulating member on the semiconductor member,
a source member and a drain member disposed on the semiconductor member and respectively disposed at opposite sides of the insulating member, and
a gate electrode on the insulating member,
wherein each of the source member and the drain member includes a plurality of layers having different impurity doping concentrations.

US Pat. No. 10,192,899

DISPLAY AND MANUFACTURE METHOD THEREOF

AU OPTRONICS CORPORATION,...

1. A display, comprising:a first substrate;
a second substrate;
a plurality of pixels, disposed between the first substrate and the second substrate;
a seal disposed between the first substrate the second substrate; and
a photo-catalyst layer, disposed above a surface of the second substrate facing the first substrate or above a surface of the first substrate facing the second substrate, wherein the photo-catalyst layer and the plurality of pixels are located at two opposite sides of the seal respectively;
wherein each of the plurality of pixels comprises a transistor, and each of the transistors comprises a gate electrode, a source electrode, and an active layer, wherein the photo-catalyst layer and the gate electrode, or the photo-catalyst layer and the source electrode are belonging to a same first film layer.

US Pat. No. 10,192,898

DISPLAY DEVICE INCLUDING HYBRID TYPES OF TRANSISTORS

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate;
a first gate electrode and a second gate electrode disposed on the substrate, wherein the first gate electrode is formed by a first conducting layer, and the second gate electrode is formed by stacking the first conducting layer and a second conducting layer on the substrate;
a gate insulating layer disposed on the substrate, the first gate electrode and the second gate electrode;
a first active layer disposed on the gate insulating layer and corresponding to the first gate electrode, wherein the first active layer comprises a polysilicon layer;
a first insulating layer disposed on the first active layer and the gate insulating layer, and the first insulating layer comprising a first bottom insulating layer and a first top insulating layer;
a second active layer disposed on the first insulating layer and corresponding to the second gate electrode, wherein the second active layer comprises a metal oxide layer;
a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, wherein the first source electrode and the first drain electrode are disposed on the first insulating layer and electrically connect to the first active layer, and the second source electrode and the second drain electrode are disposed on the second active layer and electrically connect to the second active layer; and
a fourth conducting layer, wherein the fourth conducting layer partially covers at least one of the second source electrode and the second drain electrode,
wherein, the first gate electrode, the gate insulating layer, the first active layer, the first insulating layer, the first source electrode, and the first drain electrode form a first transistor, the second gate electrode, the gate insulating layer, the first insulating layer, the second active layer, the second source electrode, and the second drain electrode form a second transistor; and
a display medium layer disposed on the substrate.

US Pat. No. 10,192,897

ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE

HON HAI PRECISION INDUSTR...

1. An array substrate comprising:a substrate;
a first TFT formed on the substrate, the first TFT comprising a first channel layer formed on the substrate, a first gate insulator layer formed on the substrate and covering the first channel layer, a first gate electrode formed on the first gate insulator layer, a first dielectric layer formed on the first gate insulator layer and covering the first gate electrode, a second dielectric layer formed on the first dielectric layer, and a first source electrode and a first drain electrode formed on the second dielectric layer; the first source electrode and the first drain electrode electrically coupled to the first channel layer;
a second TFT formed on the substrate, the second TFT comprising a second gate insulator layer formed on the substrate, a second gate electrode formed on the second gate insulator layer, a third dielectric layer formed on the second gate insulator layer and covering the second gate electrode, a second channel layer formed on the third dielectric layer, and a second source electrode and a second drain electrode formed on the third dielectric layer; the second source electrode and the second drain electrode electrically coupled to the second channel layer; and
a third TFT formed on the substrate, the third TFT comprising a third gate insulator layer formed on the substrate, a third gate electrode formed on the third gate insulator layer, a fourth dielectric layer formed on the second gate insulator layer and covering the third gate electrode, a third channel layer formed on the fourth dielectric layer, and a third source electrode and a third drain electrode formed on the fourth dielectric layer; the third source electrode and the third drain electrode electrically coupled to the third channel layer;
wherein the first channel layer is made of a semiconducting material containing polycrystalline silicon; the second channel layer and the third channel layer are made of a semiconducting material containing metal oxide; the third dielectric layer is positioned between the second gate electrode and the second channel layer, and is in direct contact with the second gate electrode and the second channel layer; the fourth dielectric layer is positioned between the third gate electrode and the third channel layer, and is in direct contact with the third gate electrode and the third channel layer; the first dielectric layer is made of silicon nitride; the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are made of silicon oxide.

US Pat. No. 10,192,896

DISPLAY DEVICE WITH OVERLAPPING PADS SPACED APART FROM AN INSULATING LAYER

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate including a display area to display an image and a non-display area provided on at least one side of the display area;
a plurality of pixels disposed on the substrate and provided in an area corresponding to the display area;
a first insulating layer having an opening in a first area of the non-display area;
a second insulating layer filling the opening of the first insulating layer, wherein the second insulating layer contacts the substrate in the opening of the first insulating layer;
first lines provided on the substrate and connected to the plurality of pixels; and
second tines provided on the first and second insulating layers, and connected to the first lines,
wherein an area in which the first lines overlap with the second lines is spaced apart from an edge of the second insulating layer when viewed in a plan view.

US Pat. No. 10,192,895

DISPLAY DEVICE

JAPAN DISPLAY INC., Mina...

1. A display device comprising:a transparent substrate;
a plurality of thin film transistors provided in the transparent substrate;
a source electrode and a drain electrode formed above or below a semiconductor layer via an insulating film;
a first contact hole for connecting the semiconductor layer and the source electrode, a second contact hole for connecting the semiconductor layer and the drain electrode; and
a first light shielding film and a second light shielding film provided between the plurality of thin film transistors and the transparent substrate,
wherein each thin film transistor includes:
a semiconductor layer; and
a first gate electrode and a second gate electrode formed above or below the semiconductor layer via an insulating film,
the first light shielding film overlaps with the semiconductor layer in a plan view from a part of the first gate electrode to the first contact hole, and the second light shielding film overlaps with the semiconductor layer in a plan view from a part of the second gate electrode to the second contact hole,
wherein the semiconductor layer includes, in a plan view:
a source region formed in a first portion of the semiconductor layer which is positioned on an opposite side to the second gate electrode across the first gate electrode when seen in a plan view,
a drain region formed in a second portion of the semiconductor layer which is positioned on an opposite side to the first gate electrode across the second gate electrode when seen in a plan view,
a first semiconductor region formed in a third portion which is positioned between the first gate electrode and the source region, and
a second semiconductor region formed in a fourth portion which is positioned between the second gate electrode and the drain region,
the first light shielding film includes a first end portion on the source electrode side and a second end portion on the drain electrode side, and the second light shielding film includes a third end portion on the source electrode side and a fourth end portion on the drain electrode side,
a distance from the first end portion of the first light shielding film to an overlapping region with the first semiconductor region is L1 in the plan view, and an interlayer distance from the first light shielding film to the semiconductor layer is H1, the distance L1 is formed to be equal to or greater than the interlayer distance H1,
a distance from the fourth end portion of the second light shielding film to an overlapping region with the second semiconductor region is L2 in the plan view, and an interlayer distance from the second light shielding film to the semiconductor layer is H1, the distance L2 is formed to be equal to or greater than the interlayer distance H1.

US Pat. No. 10,192,894

THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor comprising, successively from the bottom up, a gate, a first common electrode located in a same layer as the gate, a gate insulating layer, an active layer, a pixel electrode, a source-drain electrode layer and a passivation layer located above the layer where the gate is located, and a second common electrode located on the passivation layer, wherein,the thin film transistor further comprises at least one connection electrode located in a same layer as the pixel electrode, wherein at least two via holes are provided between the first common electrode and the second common electrode so as to connect the first common electrode and the second common electrode through the connection electrode.

US Pat. No. 10,192,893

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, in a peripheral region outside a display region, comprising a plurality of signal lines, a plurality of connecting lines above the signal lines, and a driving module, the connecting lines being configured for connecting the signal lines and the driving module, to transmit signals from the signal lines to the driving module, wherein, each of the signal lines comprises a first electrode line layer and a second electrode line layer above the first electrode line layer,wherein, a first insulating layer is arranged between the first electrode line layer and the second electrode line layer, a second insulating layer is arranged above the second electrode line layer,
wherein, at least one of the signal lines is insulated from and intersected with the at least one of the connecting lines in a plan view of the array substrate; the second electrode line layer of the at least one of the signal lines is discontinuous at an intersection of the at least one of the signal lines and the at least one of the connecting lines in the plan view of the array substrate; and the second electrode line layer of at least one of the signal lines is not overlapped with the at least one of the connecting lines in the plan view of the array substrate.

US Pat. No. 10,192,892

ACTIVE MATRIX BACKPLANE FORMED USING THIN FILM OPTOCOUPLERS

Palo Alto Research Center...

1. A device comprising:a backplane, comprising:
multiple output terminals arranged on an output surface of the backplane;
an optocoupler active matrix array, comprising:
thin film solid state optical switches coupled respectively between an input terminal of the backplane and the output terminals, the optical switches and the output terminals arranged in an array; and
storage capacitors coupled respectively to the output terminals; and
a pixelated light source configured to provide pixelated light that controls the optical switches.

US Pat. No. 10,192,891

THIN FILM TRANSISTOR AND DISPLAY DEVICE COMPRISING THE SAME

JOLED INC., Tokyo (JP)

1. A thin film transistor comprising:an oxide semiconductor layer provided above an insulating substrate and including a source region, a drain region and a channel region between the source region and the drain region;
a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region;
a gate electrode provided on the first insulating film;
a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal;
a second protective film provided on the first protective film; and
a third protective film provided on the second protective film, as an insulating film containing a metal, wherein the first protective film directly contacts sidewalls and a top surface of the gate electrode, wherein the third protective film is thicker than the first protective film.

US Pat. No. 10,192,888

METALLIZED JUNCTION FINFET STRUCTURES

International Business Ma...

1. A FinFET structure comprising:a substrate;
a plurality of vertically extending, parallel semiconductor fins mounted to the substrate;
a plurality of parallel gate structures on and extending perpendicularly with respect to the semiconductor fins;
a plurality of first sidewall spacers on the gate structures;
a plurality of pairs of unmerged epitaxial source/drain structures, each pair of unmerged epitaxial source/drain structures including a first portion extending laterally from first and second sidewall surfaces of one of the semiconductor fins and operatively associated with the one of the semiconductor fins and a second portion integral with the first portion;
a plurality of parallel, vertically oriented, fin-shaped cavities between each pair of source/drain structures in each second portion thereof, each of the fin-shaped cavities being in linear alignment, respectively with each of the semiconductor fins and extending perpendicularly with respect to the plurality of gate structures, and
a metal silicide layer adjoining the source/drain structures and filling the plurality of fin-shaped cavities, the second portion of each pair of unmerged epitaxial source/drain structures extending laterally from one of the fin-shaped cavities and adjoining the metal silicide layer filling the one of the fin-shaped cavities.

US Pat. No. 10,192,885

SEMICONDUCTOR ON INSULATOR (SOI) BLOCK WITH A GUARD RING

NXP USA, Inc., Austin, T...

1. A method for forming a semiconductor device, comprising:delineating a portion of a bulk substrate having a first conductivity type as a first semiconductor on insulator (SOI) block;
forming a first doped well of the first conductivity type in the first SOI block;
forming a second doped well of a second conductivity type in the first SOI block;
forming a first guard ring of the first conductivity type around at least a portion of a periphery of and laterally spaced apart from the first SOI block such that the first guard ring and the first SOI block do not touch;
forming a first electronic device directly over the first doped well;
forming a first electrically conductive trace between the first guard ring and a first current electrode of the first electronic device to electrically connect the first guard ring and the first current electrode of the first electronic device.

US Pat. No. 10,192,884

BUTTED BODY CONTACT FOR SOI TRANSISTOR

pSemi Corporation, San D...

1. A semiconductor structure comprising:a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type;
a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type;
a first drain region adjacent to the first body region having a second conductivity type;
a first source region adjacent to the first body region having the second conductivity type;
a second source region adjacent to the second body region having the second conductivity type;
a second drain region adjacent to the second body region having the second conductivity type,
the first source region and the second drain region defining a first common source/drain region having the second conductivity type;
a first non-conductive isolation region configured to form an interruption in the second body region to divide the second body region in two separate second body regions;
at least one first body contact region of the first conductivity type formed within the first common source/drain region separate from the first and the second body regions and abutting the first non-conductive isolation region; and
at least one first body tab of the first conductivity type extending across the first common source/drain region in contact with the first body region and the at least one first body contact region,
wherein the first non-conductive isolation region, the at least one first body contact region and the at least one first body tab define a first butted body tie structure.

US Pat. No. 10,192,883

VERTICAL MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A memory device, comprising:a first region including a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a protective layer disposed in the first insulating layer; and
a second region including a second substrate disposed on the first insulating layer, wherein the second substrate includes a first impurity region, a channel region extending in a first direction substantially perpendicular to an upper surface of the second substrate, and a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, wherein the protective layer is disposed below the first impurity regions, and includes a plurality of regions separated from each other.

US Pat. No. 10,192,882

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a stacked body including a plurality of conductive layers stacked with an insulator interposed;
a columnar portion extending through the stacked body in a stacking direction of the stacked body; and
a first air gap extending through the stacked body in the stacking direction,
the insulator including
an insulating layer provided at a periphery of a side surface of the columnar portion, and
a second air gap communicating with the first air gap and being provided between the insulating layer and the first air gap,
the insulating layer having a protrusion at an end adjacent to the second air gap.

US Pat. No. 10,192,880

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:gate stacked structures surrounding channel layers;
a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, wherein the first concave portions are arranged in a first direction crossing a lengthwise direction of the channel layer; and
a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.

US Pat. No. 10,192,879

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device having a memory cell of a nonvolatile memory, comprising:a semiconductor substrate;
a first gate electrode formed over the semiconductor substrate via a first gate insulating film; and
a second gate electrode formed over the semiconductor substrate via a multi-layer insulating film, and adjacent to the first gate electrode via the multi-layer insulating film,
wherein the multi-layer insulating film includes a first insulating film, a second insulating film over the first insulating film, and a third insulating film over the second insulating film,
wherein the second insulating film has a charge storing function,
wherein the second gate electrode has a lower surface facing the semiconductor substrate, a first side surface adjacent to the first gate electrode via the multi-layer insulating film, and a second side surface opposite to the first side surface, and
wherein a fourth insulating film is formed between the lower surface of the second gate electrode and the semiconductor substrate and is in contact with the first, second and third insulating films such that the fourth insulating film is located closer to a first end portion of the second side surface of the second gate electrode than to a second end portion of the first side surface of the second gate electrode.

US Pat. No. 10,192,878

THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED MULTI-LEVEL DRAIN SELECT GATE ELECTRODES

SANDISK TECHNOLOGIES LLC,...

12. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;
a first conductive connector spacer connected to each of first strip portions of two or more uppermost layers among the electrically conductive layers; and
a second conductive connector spacer connected to each of second strip portions of the two or more uppermost layers among the electrically conductive layers,
wherein each of the first and second conductive connector spacers includes an alternating sequence of conductive non-concave sidewall portions and conductive concave sidewall portions.

US Pat. No. 10,192,877

THREE-DIMENSIONAL MEMORY DEVICE WITH LEVEL-SHIFTED STAIRCASE STRUCTURES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stack is composed of, from bottom to top, a first contiguous subset of layers within the alternating stack and a second contiguous subset of layers;
a mesa structure located over the substrate;
memory stack structures extending through the alternating stack in a memory array region, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
a first terrace region located above the mesa structure at a first side of the memory array region, and including first stepped surfaces of the first contiguous subset;
a second terrace region located at a second side of the memory array region, and including second stepped surfaces of the second contiguous subset;
first contact via structures contacting respective electrically conductive layers within the first contiguous subset in the first terrace region;
second contact via structures contacting respective electrically conductive layers within the second contiguous subset in the second terrace region;
a first retro-stepped dielectric material portion contacting the first stepped surfaces;
a second retro-stepped dielectric material portion contacting the second stepped surfaces, wherein the second retro-stepped dielectric material portion has a greater maximum height than the first retro-stepped dielectric material portion;
a contact level dielectric material layer overlying the alternating stack;
a first support pillar structure located in the first terrace region and extending through the contact level dielectric material layer and the first retro-stepped dielectric material portion, not extending through any layer within the second contiguous subset, and directly contacting a horizontal portion of an electrically conductive layer within the first contiguous subset, a horizontal portion of an insulating layer within the first contiguous subset, and a vertically extending portion of another electrically conductive layer within the first contiguous subset, wherein the vertically extending portion extends vertically over a vertical extent of multiple electrically conductive layers within the memory array region; and
a second support pillar structure located in the second terrace region and extending through the contact level dielectric material layer and the second retro-stepped dielectric material portion, and directly contacting a respective horizontal portion of each electrically conductive layer within the first contiguous subset and a horizontal portion of at least one electrically conductive layer within the second contiguous subset and does not directly contact any vertically extending portion of the electrically conductive layers within an entirety of the alternating stack.

US Pat. No. 10,192,876

TRANSISTOR, MEMORY, AND MANUFACTURING METHOD OF TRANSISTOR

Toshiba Memory Corporatio...

1. A transistor comprising:a gate electrode;
a gate insulating layer provided on the gate electrode;
an oxide semiconductor layer provided on the gate insulating layer;
an oxygen supply layer provided on the oxide semiconductor layer;
a first oxygen barrier layer including a first portion, the first portion provided on the oxygen supply layer;
a source electrode provided to include a source extending portion that extends through the oxygen supply layer and the first portion in a stacking direction of the layers, and connected to the oxide semiconductor layer; and
a drain electrode spaced apart from the source electrode, provided to include a drain extending portion that extends through the oxygen supply layer and the first portion in the stacking direction, and connected to the oxide semiconductor layer,
wherein the first oxygen barrier layer further includes a second portion between the oxygen supply layer and a side of the source extending portion, and a third portion between the oxygen supply layer and a side of the drain extending portion.

US Pat. No. 10,192,875

NON-VOLATILE MEMORY WITH PROTECTIVE STRESS GATE

eMemory Technology Inc., ...

1. A non-volatile memory, comprising:a substrate;
a floating gate transistor, a select transistor and a stress-releasing transistor, disposed on the substrate and coupled in series with each other, wherein the stress-releasing transistor is located between the floating gate transistor and the select transistor, and
the stress-releasing transistor has a stress release ratio represented by formula (1):
the stress release ratio=a channel length of the stress-releasing transistor/a gate dielectric layer thickness of the stress-releasing transistor  (1)
wherein a lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed,
an upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed, and
the channel length under a stress-releasing gate of the stress-releasing transistor is smaller than a minimum channel length of a design rule of an input/output device; and
a first capacitor and a second capacitor, wherein the first capacitor, the second capacitor and the floating gate transistor are disposed in separation and are coupled to each other.

US Pat. No. 10,192,873

MEMORY CELL, AN ARRAY OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR WITH THE ARRAY COMPRISING ROWS OF ACCESS LINES AND COLUMNS OF DIGIT LINES, A 2T-1C MEMORY CELL, AND METHODS OF FORMING AN ARRAY OF CAPACITORS AND ACCESS TRANSISTORS

Micron Technology, Inc., ...

1. A memory cell having a total of only two transistors and a total of only one capacitor, comprising:a capacitor comprising a laterally-outer electrode having an upwardly-open container shape;
a laterally-inner electrode;
a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode;
a lower vertical transistor having an upper source/drain region thereof electrically coupled to the laterally-outer electrode having the upwardly-open container shape; and
an upper vertical transistor having a lower source/drain region thereof electrically coupled to the laterally-inner electrode.

US Pat. No. 10,192,872

MEMORY DEVICE HAVING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first region in electrical contact with said floating body region; and
a back-bias region configured to maintain a charge in said floating body region;
wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity;
wherein said back bias region is commonly connected to at least two of said memory cells,
wherein said back bias region has a lower band gap than a band gap of said floating body region; and
a control circuit configured to provide electrical signals to said back bias region.

US Pat. No. 10,192,871

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor; and
a first circuit,
wherein the transistor includes a first gate and a second gate,
wherein the first gate and the second gate overlap with each other with a semiconductor layer positioned therebetween,
wherein the first circuit includes a temperature sensor and a comparator,
wherein the temperature sensor is configured to obtain temperature information, and
wherein the first circuit is configured to apply, to the second gate, a voltage depending on the temperature information.

US Pat. No. 10,192,870

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a semiconductor substrate of a first conductivity type;
a first semiconductor region of a second conductivity type, selectively provided in one main surface of the semiconductor substrate;
an isolating structure formed by a pn junction of the semiconductor substrate and the first semiconductor region, the isolating structure isolating regions of differing potentials;
a semiconductor element having: a second semiconductor region of the second conductivity type, selectively provided in the one main surface of the semiconductor substrate so as to be separated from the first semiconductor region and electrically connected to an electrode of a minimum potential through a first resistor; a third semiconductor region of the second conductivity type selectively provided inside the first semiconductor region and having a higher impurity concentration than the first semiconductor region; a gate insulating film provided along the semiconductor substrate between the first semiconductor region and the second semiconductor region; and a gate electrode provided along the gate insulating film, the semiconductor element converting a signal referenced to the minimum potential into a signal referenced to a potential differing from the minimum potential; and
a fourth semiconductor region of the first conductivity type selectively provided in the one main surface of the semiconductor substrate so as to be separated from the second semiconductor region at a prescribed distance and electrically connected to the electrode of the minimum potential, the fourth semiconductor region having a higher impurity concentration than the semiconductor substrate,
wherein the second semiconductor region is electrically connected to the fourth semiconductor region through a second resistor, and
wherein the second resistor comprises a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region.

US Pat. No. 10,192,869

REDUCTION OF NEGATIVE BIAS TEMPERATURE INSTABILITY

INTERNATIONAL BUSINESS MA...

1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:an n-channel field effect transistor (nFET), the nFET comprising a high-k dielectric layer on an interlayer, an nFET work function setting metal on the high-k dielectric layer, a cap layer on the nFET work function setting metal, and a pFET work function setting metal on the cap layer, wherein the interlayer is silicon dioxide (SiO2); and
a p-channel field effect transistor (pFET), the pFET comprising the high-k dielectric layer directly on the interlayer, the cap layer directly on the high-k dielectric layer, and the pFET work function setting metal directly on the cap layer, wherein the cap layer is aluminum-based and the pFET work function setting metal is a nitride and metal atoms from the cap layer do not intermix with the interlayer.

US Pat. No. 10,192,863

SERIES CONNECTED ESD PROTECTION CIRCUIT

Texas Instruments Incorpo...

1. An electrostatic discharge (ESD) protection circuit, comprising:a substrate;
an n-type buried layer formed below a surface of the substrate;
a first terminal formed on the surface of the substrate;
a second terminal formed on the surface of the substrate;
a first ESD protection device having a first current path connecting between the first terminal and the n-type buried layer, the first ESD protection device including a first NPN bipolar transistor having a collector positioned in the n-type buried layer; and
a second ESD protection device having a second current path connecting between the second terminal and the n-type buried layer, the second current path arranged in series with the first current path, the second ESD protection device including a second NPN bipolar transistor having an emitter positioned in the n-type buried layer,
wherein the first NPN bipolar transistor has a first base that is electrically isolated from a second base of the second NPN transistor.

US Pat. No. 10,192,862

SEMICONDUCTOR DEVICE

Murata Manufacturing Co.,...

1. A semiconductor device comprising:an amplifier circuit including a semiconductor element formed on a substrate;
a protection circuit including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit; and
a pad conductive layer at least partially including a pad for connecting to a circuit outside the substrate, wherein
the pad conductive layer and the protection circuit at least partially overlap each other in plan view, and
at least one of the protection diodes includes a substantially U-shaped electrode in plan view.

US Pat. No. 10,192,861

OPC METHOD FOR A SHALLOW ION IMPLANTING LAYER

SHANGHAI HUALI MICROELECT...

1. An OPC method for a shallow ion implanting layer, providing a shallow ion implanting original layout and other layers corresponding to the shallow ion implanting original layout include an active area layer, a contact hole layer and a poly-silicon layer, wherein the active area layer includes an active region pattern, the contact hole layer includes a contact hole pattern and the poly-silicon layer includes a ploy-silicon pattern; wherein the method comprising the following steps of:S01: selecting a valid device region in an implanting active region of the shallow ion implanting original layout; wherein a portion other than an active region pattern in an active area layer is a STI region, the shallow ion implanting original layout includes a shallow ion implanting region and a non-shallow ion implanting region, and a portion overlapped between the shallow ion implanting region and the active region pattern in the active area layer is the implanting active region; a portion to remain the implanting active region which touches to the contact hole pattern in the contact hole layer is a valid device region, and anther portion to remain the implanting active region which does not touch to the contact hole pattern in the contact hole layer is a non-device invalid region;
S02: selecting a region in the valid device region which is contacted with a poly-silicon pattern in a poly-silicon layer, as a poly-silicon contacting region, and selecting a region in the valid device region which is not contacted with the poly-silicon pattern in the poly-silicon layer, as a non poly-silicon contacting region;
S03: extending the length and width of the poly-silicon contacting region and the non poly-silicon contacting region, to form a new poly-silicon contacting region and a new non poly-silicon contacting region; wherein the new poly-silicon contacting region and the new non poly-silicon contacting region are located in any region except the active region pattern touching with the contact hole pattern in the non-shallow ion implanting region;
S04: combining one gap portion or more gap portions which an interval between any two new poly-silicon contacting regions and/or new non poly-silicon contacting regions after extending is smaller than or equal to G, with the poly-silicon contacting regions and the non poly-silicon contacting regions after extending, to form a correction target layer, wherein G is an interval safe value determined according to the actual process capability;
S05: performing a model-based OPC correction on the correction target layer, and to obtain a mask layer.

US Pat. No. 10,192,860

ENGINEERING CHANGE ORDER (ECO) CELL, LAYOUT THEREOF AND INTEGRATED CIRCUIT INCLUDING THE ECO CELL

Samsung Electronics Co., ...

1. An integrated circuit (IC) comprising:an integrated circuit substrate;
a plurality of standard cells on said integrated circuit substrate; and
at least one engineering change order (ECO) base cell on the integrated circuit substrate;
wherein the ECO base cell has a layout that is generated based on a layout of a functional cell corresponding to a first circuit including a plurality of logic gates having different logic configurations relative to each other;
wherein the layout of the ECO base cell includes a plurality of spaced-apart and dissimilar regions that are each associated with a respective one of the plurality of logic gates, with each of the plurality of dissimilar regions comprising a plurality of spaced-apart active regions and a plurality of gate lines overlapping the plurality of spaced-apart active regions; and
wherein the plurality of gate lines are disposed asymmetrically on said integrated circuit substrate so that the gate lines within at least two of the plurality of dissimilar regions lack symmetry relative to each other and relative to an axis extending between the at least two of the plurality of dissimilar regions.

US Pat. No. 10,192,859

INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:a substrate having a semiconducting surface; and
a structure formed in and on the semiconducting surface, the structure including a first block of standard cells, and at least a second block,
the first and second blocks arranged in a horizontal row, and at least partially aligned in height, such that at least a portion of a first vertical block boundary of the first block is adjacent to and aligned with at least a portion of a second vertical block boundary of the second block, thereby defining a region of alignment between the first and second blocks,
the first block including a first base level extending across a portion but not all of the first vertical block boundary to form a first vertical base-level boundary at least partially within the region of alignment,
the second block including a second base level extending across a portion but not all of the second vertical block boundary to form a second vertical base-level boundary at least partially within the region of alignment;
the first and second blocks placed on the semiconducting surface such that the blocks are separated by a protective separation strip between the blocks;
the first block including a first DWD1 dimension between its first vertical block boundary, and the second vertical base-level boundary of the second base level,
the second block including a second DWD1 dimension between its second vertical block boundary, and the first vertical base-level boundary of the first base level,
the separation strip having a uniform width dimension DWD1 between a vertical block boundary and a vertical base-level boundary,
the DWD1 dimension defined such that a minimum separation exists between the first and second vertical base-level boundaries corresponding to the protective separation strip.

US Pat. No. 10,192,858

LIGHT EMITTING STRUCTURE

Apple Inc., Cupertino, C...

1. A display comprising:a substrate;
a first bottom electrode line on the substrate;
a passivation layer over the display substrate;
a first plurality of vertical semiconductor-based light emitting diodes (LEDs) coupled with the first bottom electrode line and embedded within the passivation layer such that the passivation layer laterally surrounds a quantum well within each of the first plurality of vertical semiconductor-based LEDs;
a second plurality of vertical semiconductor-based LEDs embedded within the passivation layer such that the passivation layer laterally surrounds a quantum well within each of the second plurality of vertical semiconductor-based LEDs, wherein the second plurality of vertical semiconductor-based LEDs and the first plurality of vertical semiconductor-based LEDs share a same vertical semiconductor-based LED; and
a first top electrode line in electrical contact with the second plurality of vertical semiconductor-based LEDs.

US Pat. No. 10,192,857

DIRECT BANDGAP SEMICONDUCTOR BONDED TO SILICON PHOTONICS

Hewlett Packard Enterpris...

1. A method comprising:receiving an assembly comprising a silicon photonics (SiP) wafer bonded to a complementary metal-oxide-semiconductor (CMOS) wafer, wherein the SiP wafer includes photonics circuitry and the CMOS wafer includes electronic circuitry; and
after receiving the assembly:
bonding a direct bandgap (DBG) semiconductor structure to the SiP wafer such that the SiP wafer is disposed between the CMOS wafer and the DBG semiconductor structure;
optically coupling the direct bandgap (DBG) semiconductor structure to the photonics circuitry; and
electrically connecting the DBG semiconductor structure to the electronic circuitry of the CMOS wafer.

US Pat. No. 10,192,856

OPTICAL NAVIGATION MODULE CAPABLE OF PERFORMING LATERAL DETECTION AND ADJUSTING TRACKING DISTANCE

PIXART IMAGING INC., Hsi...

1. An optical navigation module, comprising:an optical package comprising
an image sensor, the image sensor having a sensor surface;
a light emitting chip configured to emit illumination light in a direction normal to the sensor surface; and
a reflective structure covering on the optical package and comprising:
a detection plane perpendicular to the sensor surface;
a detection opening located at the detection plane and penetrating from an outer surface of the detection plane to an inner surface of the detection plane;
a first reflective portion configured to reflect incident light coming from the detection opening to impinge on the sensor surface, wherein the incident light parallel to the sensor surface is reflected by the first reflective portion to be perpendicular to the sensor surface, wherein the first reflective portion has
a first end for reflecting the incident light coming from the detection opening to impinge on the sensor surface, and
a second end connected to the detection opening; and
a second reflective portion, which is separated from the first reflective portion, and configured to reflect the illumination light, emitted in the normal line direction by the light emitting chip, to be parallel to the sensor surface to go out the reflective structure from the same detection opening, wherein the second reflective portion has
a first end for reflecting the illumination light, emitted by the light emitting chip, to be parallel to the sensor surface, and
a second end connected to the detection opening, wherein
the first reflective portion extends in a first direction from the first end of the first reflective portion to the second end of the first reflective portion,
the second reflective portion extends in a second direction from the first end of the second reflective portion to the second end of the second reflective portion, and
the first direction is not parallel to the second direction.

US Pat. No. 10,192,853

METHOD FOR PREPARING A SEMICONDUCTOR APPARATUS

NANYA TECHNOLOGY CORPORAT...

1. A method for preparing a semiconductor apparatus, comprising:preparing a first semiconductor die, wherein the first semiconductor die comprises a substrate, a circuit portion disposed on the substrate, a first chip selection terminal disposed in the circuit portion above or below the substrate, a first upper terminal, and a first lower terminal electrically connected to the first chip selection terminals;
preparing a second semiconductor die, wherein the second semiconductor die comprises a second chip selection chip terminal and a second lower terminal electrically connected to the second chip selection terminal, wherein the second chip selection terminal is electrically connected to the first upper terminal of the first semiconductor die via the second lower terminal; and
attaching the second semiconductor die to the first semiconductor die in a horizontally shifted manner;
wherein the first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

US Pat. No. 10,192,852

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a semiconductor substrate;
a dielectric material over the substrate;
a conductive trace extending at least partially through the dielectric material; and
a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—
a conductive member coupled to the conductive trace, and
a conductive bond material bonded to the conductive member,
wherein all of the redundant electrical connectors are coupled to the conductive trace.

US Pat. No. 10,192,842

PACKAGE FOR ENVIRONMENTAL PARAMETER SENSORS AND METHOD FOR MANUFACTURING A PACKAGE FOR ENVIRONMENTAL PARAMETER SENSORS

ams International AG, Ra...

1. A method of manufacturing a sensor package comprising:providing an integrated circuit chip which carries at least one sensor element on a first surface;
bonding the first surface of the integrated circuit chip to a first surface of an intermediate carrier using an adhesive, the intermediate carrier comprising solder bond pads on a second surface of the intermediate carrier opposite the first surface; and
soldering the solder bond pads to tracks of a circuit board,
wherein the intermediate carrier has an opening beneath the at least one sensor element, the opening extending through the intermediate carrier,
wherein the at least one sensor element is exposed to the environment through the opening,
wherein the bonding comprises bonding the bumps to the first surface of the intermediate carrier,
wherein the adhesive is an anisotropic conductive glue,
wherein the use of soldering is avoided by the adhesive bonding of the integrated circuit chip,
wherein the sensor package comprises a shield formed by the intermediate carrier, the shield configured and arranged to protect a sensor area of the at least one sensor element from pollution during the soldering when the sensor package is soldered to the circuit board, and
wherein the outer shape defined by the outer edge of the intermediate carrier is within 0.5 mm of the outer edge of the shape of the chip and/or is within 0.4 mm and/or is within 0.3 mm.

US Pat. No. 10,192,841

SEMICONDUCTOR PACKAGE AND METHOD FOR PREPARING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor package, comprising:a first device having a first upper surface and a first side, wherein the first upper surface and the first side form a first corner of the first device; and
a bump structure disposed over the first upper surface, wherein the bump structure extends laterally across the first side of the first device;
wherein the first device comprises a missing corner, and the bump structure fills the missing corner.

US Pat. No. 10,192,839

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

International Business Ma...

1. A method of fabricating a pillar-type connection, the method comprising:forming a first conductive layer;
forming a second conductive layer on the first conductive layer to define a conductive pillar that includes a top surface defining a recess aligned with a hollow core of the first conductive layer; and
forming a conductive via that terminates at a top surface of the first conductive layer.

US Pat. No. 10,192,831

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package module comprising:a core member having first and second through-holes spaced apart from each other and one or more slits;
a semiconductor chip disposed in the first through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
one or more first passive components disposed in the second through-hole;
an encapsulant encapsulating at least portions of each of the core member, the inactive surface of the semiconductor chip, and the one or more first passive components;
a connection member disposed on the core member, the active surface of the semiconductor chip, and the one or more first passive components and including redistribution layers electrically connected to the connection pads and the one or more first passive component; and
first metal layers filling the one or more slits,
wherein at least one of the one or more slits is formed between the first and second through-holes.

US Pat. No. 10,192,829

LOW-TEMPERATURE DIFFUSION DOPING OF COPPER INTERCONNECTS INDEPENDENT OF SEED LAYER COMPOSITION

International Business Ma...

1. An interconnect structure, comprising:at least one trench patterned in a dielectric material;
a barrier layer lining the trench;
a metal liner on the barrier layer;
a copper (Cu) interconnect doping layer on the metal liner; and
a Cu interconnect in the trench such that the Cu interconnect doping layer is present between the metal liner and the Cu interconnect, wherein the Cu interconnect doping layer fully surrounds the Cu interconnect whereby the Cu interconnect doping layer is continuous along all bottom, sidewall and top surfaces of the Cu interconnect.

US Pat. No. 10,192,813

HARD MACRO HAVING BLOCKAGE SITES, INTEGRATED CIRCUIT INCLUDING SAME AND METHOD OF ROUTING THROUGH A HARD MACRO

QUALCOMM Incorporated, S...

1. A hard macro having a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro from the top to the bottom and including an array of blockage sites extending through the hard macro, wherein the plurality of vias are formed in at least some of the array of blockage sites and wherein at least one via is configured to connect a first element to a second element, the first element in a first layer different from a layer that includes the hard macro, the first element positioned in a first direction from a line that passes through the at least one via, the second element in a second layer different from the layer that includes the hard macro, the second element positioned in a second direction from the line that passes through the at least one via, and wherein, between the top and the bottom of the hard macro, the line is entirely contained within the hard macro.

US Pat. No. 10,192,807

POWER SEMICONDUCTOR MODULE, FLOW PATH MEMBER, AND POWER-SEMICONDUCTOR-MODULE STRUCTURE

FUJI ELECTRIC CO., LTD., ...

1. A power semiconductor module comprising:a metal base plate including a first surface and a second surface opposite to the first surface;
a multi-layer substrate including a third surface and a fourth surface opposite to the third surface, the fourth surface being joined to the first surface;
a semiconductor element mounted on the third surface;
a resin case disposed on the first surface of the metal base plate, the resin case surrounding the multi-layer substrate and the semiconductor element; and
a cooling case including
a bottom wall,
a side wall formed around the bottom wall and having one end of the side wall being joined to the second surface of the metal base plate to form a space enclosed by the metal base plate, the bottom wall, and the side wall for circulating a coolant,
an inlet portion having an inlet opening for introducing the coolant to the cooling case and an outlet portion having an outlet opening for discharging the coolant from the cooling case, the inlet portion and the outlet portion being connected to either the bottom wall or the side wall and disposed along a peripheral edge of the second surface of the metal base plate,
a first flange disposed at an inlet opening side of the inlet portion and having a main surface opposite to the inlet portion, the main surface of the first flange being parallel to a first surface of the metal base plate, and
a second flange disposed at an outlet opening side of the outlet portion and having a main surface opposite to the outlet portion, the main surface of the second flange being parallel to the first surface.

US Pat. No. 10,192,806

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:an insulating substrate including a metal plate, an insulating resin plate laminated on the metal plate, and circuit plates laminated on the insulating resin plate and including one circuit plate having a circuit pattern and an adhering pattern, which are selectively formed on the insulating resin plate;
a semiconductor element fixed to the circuit pattern of the insulating substrate with a bonding material;
a wiring member having an end connected to the one circuit plate of the insulating substrate;
a housing accommodating the insulating substrate, the semiconductor element, and the wiring member; and
a sealing material sealing the insulating substrate, the semiconductor element, and the wiring member accommodated in the housing,
wherein the adhering pattern is an opening, in a plan view, disposed in the one circuit plate, and arranged between the semiconductor element fixed to the one circuit plate and the end of the wiring member fixed to the one circuit plate,
the sealing material bonds the insulating resin plate through the opening to increase a bond between the sealing material and the insulating resin plate, and
one of the circuit plates having the adhering pattern is bonded to the insulating resin plate by the sealing material through the opening as the adhering pattern.

US Pat. No. 10,192,801

SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE IN SUBSTRATE FOR IPD AND BASEBAND CIRCUIT SEPARATED BY HIGH-RESISTIVITY MOLDING COMPOUND

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a semiconductor substrate;
a first semiconductor die disposed over a first surface of the semiconductor substrate;
a capacitor formed over the first surface of the semiconductor substrate and laterally offset from the first semiconductor die, the capacitor including,
(a) a first conductive layer formed over the first surface of the semiconductor substrate,
(b) an insulating layer formed over the first conductive layer, and
(c) a second conductive layer formed over the insulating layer;
an encapsulant deposited around the first semiconductor die and over the capacitor;
a vertical interconnect structure formed through the encapsulant; and
a third conductive layer formed over a surface of the encapsulant opposite the capacitor, wherein the third conductive layer is in physical contact with the vertical interconnect structure and a portion of the third conductive layer is wound to form an inductor.

US Pat. No. 10,192,799

METHOD AND APPARATUS TO MODEL AND MONITOR TIME DEPENDENT DIELECTRIC BREAKDOWN IN MULTI-FIELD PLATE GALLIUM NITRIDE DEVICES

TEXAS INSTRUMENTS INCORPO...

13. A test method comprising:providing a first set of test structures TS0 through TSN for a gallium nitride (GaN) transistor that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSX of the first set of test structures comprising:
a GaN substrate,
a dielectric material overlying the GaN substrate,
a respective source contact abutting the GaN substrate,
a respective drain contact abutting the GaN substrate,
a respective gate overlying the substrate and lying between the source contact and the drain contact,
X respective field plates corresponding to X field plates of the N field plates of the GaN transistor that are nearest to the GaN substrate, and
a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate;
for each test structure TSX, the test method comprising:
applying a stress voltage to the drain contact of test structure TSX until a dielectric breakdown condition is detected; and
recording the time-to-failure of test structure TSX at the stress voltage.

US Pat. No. 10,192,790

SRAM DEVICES AND FABRICATION METHODS THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a static random-access memory (SRAM) device, comprising:providing a base substrate including a pull up (PU) transistor region and a pull down (PD) transistor region adjacent to the PU transistor region;
forming a gate dielectric layer on a portion of the base substrate in the PU transistor region and the PD transistor region;
forming a first work function (WF) layer using a P-type WF material on the gate dielectric layer;
removing a portion of the first WF layer formed in the PD transistor region;
forming a second WF layer using a P-type WF material on a remaining portion of the first WF layer in the PU transistor region and on the gate dielectric layer in the PD transistor region;
removing a portion of the second WF layer formed in the PD transistor region;
forming a third WF layer using an N-type WF material on a top surface and a sidewall surface of a remaining portion of the second WF layer in the PU transistor region, a sidewall surface of the remaining portion of the first WF layer in the PU transistor region, and the gate dielectric layer in the PD transistor region; and
forming a gate electrode layer on the third WF layer.

US Pat. No. 10,192,769

THERMOSETTING ADHESIVE SHEET AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

DEXERIALS CORPORATION, T...

1. A thermosetting adhesive sheet to be applied to a grinding-side surface of a semiconductor wafer when dicing the semiconductor wafer comprising:a polymer containing an elastomer;
a (meth)acrylate containing more than 95 wt % of a polyfunctional (meth)acrylate with respect to total (meth)acrylate content;
an organic peroxide having a one-minute half-life temperature of 130° C. or lower; and
a transparent filler,
wherein the transparent filler is contained at 50 to 150 pts. mass with respect to 25 pts. mass of the polymer.

US Pat. No. 10,192,767

CERAMIC ELECTROSTATIC CHUCK INCLUDING EMBEDDED FARADAY CAGE FOR RF DELIVERY AND ASSOCIATED METHODS FOR OPERATION, MONITORING, AND CONTROL

Lam Research Corporation,...

1. A substrate support system, comprising:a ceramic assembly having a top surface and a bottom surface, the top surface including an area configured to support a substrate;
at least one clamp electrode positioned within the ceramic assembly;
a primary radiofrequency (RF) power delivery electrode positioned within the ceramic assembly at a location vertically below the at least one clamp electrode;
a lower support structure formed of an electrically conductive material, the ceramic assembly secured to the lower support structure such that an outer peripheral region of the bottom surface of the ceramic assembly is supported by the lower support structure, the lower support structure including a hollow interior region exposed to a portion the bottom surface of the ceramic assembly; and
a plurality of electrical connections established between the lower support structure and the primary RF power delivery electrode, each of the plurality of electrical connections extending through a respective portion of the ceramic assembly.

US Pat. No. 10,192,766

ELECTROSTATIC CHUCK DEVICE

SUMITOMO OSAKA CEMENT CO....

1. An electrostatic chuck device comprising, in the following order:an electrostatic chuck section having one principal surface serving as a placing surface on which a plate-shaped sample is placed, and having a built-in electrostatic attracting internal electrode;
a first adhesion layer;
a sheet material;
a second adhesion layer; and
a temperature adjusting base section which adjusts a temperature of the electrostatic chuck section to a desired temperature,
wherein the first adhesion layer includes a joining layer having a layer thickness in a range of 1 nm to 500 nm, and a silicone adhesive layer having a thickness in a range of 2 ?m to 30 ?m, and
the second adhesion layer includes a joining layer having a layer thickness in a range of 1 nm to 500 nm, and a silicone adhesive layer having a thickness in a range of 2 ?m to 30 ?m.

US Pat. No. 10,192,750

PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method for processing a workpiece that includes a silicon-containing etching target layer, an organic film provided on the etching target layer, an antireflective film provided on the organic film, and a first mask provided on the antireflective film, using a plasma processing apparatus that includes a processing container, the plasma processing method comprising:generating a first plasma in the processing container;
etching the antireflective film using the first plasma generated in the processing container and the first mask to form a second mask from the antireflective film;
etching the organic film using the first plasma generated in the processing container and the second mask to form a third mask from the organic film;
generating a second plasma of a mixed gas including a first gas and a second gas in the processing container; and
etching the etching target layer using the second plasma generated in the processing container and the third mask,
wherein the plasma processing apparatus further includes an upper electrode,
the upper electrode is provided above a placing table that supports the workpiece in the processing container,
an electrode plate of the upper electrode contains silicon,
the first gas is oxygen gas, and
after generating the second plasma of the mixed gas and before etching the etching target layer using the second plasma, a silicon oxide film is formed on a surface of the electrode plate by colliding oxygen ions contained in the second plasma of the first gas with the electrode plate.

US Pat. No. 10,192,742

SOFT LANDING NANOLAMINATES FOR ADVANCED PATTERNING

Novellus Systems, Inc., ...

1. A method of processing a substrate, the method comprising:depositing a core layer;
depositing a nanolaminate layer on the core layer; and
depositing a metal nitride or metal oxide layer on the nanolaminate layer,
wherein the nanolaminate layer comprises a stack comprising two or more sublayers, and
wherein the nanolaminate layer comprises silicon oxide or titanium oxide.

US Pat. No. 10,192,741

DEVICE SUBSTRATE, METHOD OF MANUFACTURING DEVICE SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method of manufacturing a device substrate, the method comprising:forming a mask film on an entire surface of a device substrate in which a multilayer film is disposed on a substrate;
removing a portion of the mask film on a bevel region that is provided as a region from a peripheral edge portion of a patterning region to an end portion of the device substrate, the patterning region being provided as the region on which a resist is to be applied during an imprint process of the device substrate; and
planarizing an upper surface of the mask film positioned on the patterning region,
wherein the planarizing of the upper surface of the mask film includes
dropping the resist onto the mask film,
placing a blank template including no rugged patterns, with respect to the mask film through the resist, such that there is a predetermined distance between the blank template and the mask film, and curing the resist, and
etching back an entire surface of the device substrate by use of dry etching.

US Pat. No. 10,192,738

METHODS OF PRODUCING SEED CRYSTAL SUBSTRATES AND GROUP 13 ELEMENT NITRIDE CRYSTALS, AND SEED CRYSTAL SUBSTRATES

NGK INSULATORS, LTD., Na...

1. A method of producing a seed crystal substrate, the method comprising the steps of:providing a seed crystal layer comprising a nitride of a group 13 element on a supporting body; and
irradiating a laser light from a side of said supporting body to provide an altered portion along an interface between said supporting body and said seed crystal layer, said altered portion comprising said nitride of said group 13 element and comprising a portion with dislocation defects introduced therein or an amorphous portion,
wherein the laser light is irradiated at an optical energy such that voids are not generated along the interface between the supporting body and seed crystal layer.

US Pat. No. 10,192,737

METHOD FOR HETEROEPITAXIAL GROWTH OF III METAL-FACE POLARITY III-NITRIDES ON SUBSTRATES WITH DIAMOND CRYSTAL STRUCTURE AND III-NITRIDE SEMICONDUCTORS

Foundation for Research a...

1. A method of heteroepitaxial growth of III-Nitride semiconductors on a substrate achieving (0001) orientation and metal-face polarity for a first nucleation layer and subsequent layers, comprising the following steps:utilizing a nitrogen plasma source for molecular beam epitaxy to deposit an Al-face polarity (0001) AlN nucleation layer less than 5 nm in deposited layer thickness to minimize degradation of the epitaxial growth of the AlN layer and inversion of its polarity;
depositing said AlN layer on a substrate independent of the crystalline surface orientation of said substrate, said substrate being polycrystalline diamond; and
by the cooperation between said utilizing the nitrogen plasma source for epitaxy and said depositing of said AlN layer less than 5 nm in thickness, subsequently overgrowing on said AlN layer one or more additional III-Nitride compound layers while preserving said (0001) orientation and III metal-face polarity; and
between the steps of depositing of said AlN layer and overgrowing of said AlN layer by a III-nitride compound layer, interrupting the depositing of said AlN layer and exposing said MN layer to active nitrogen species produced by the nitrogen plasma source.

US Pat. No. 10,192,735

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS

KOKUSAI ELECTRIC CORPORAT...

1. A manufacturing method of a semiconductor device comprising:(a) generating hydrogen radicals and oxygen radicals by plasma excitation of a mixed gas of hydrogen gas and oxygen gas or a mixed gas of hydrogen gas and oxygen-containing gas, and oxidizing a silicon surface of a substrate on which the silicon surface and a metal surface are exposed by exposing the surface of the substrate to the hydrogen radicals and the oxygen radicals to obtain the substrate on which the metal surface and an oxidized silicon surface are formed; and
(b) after performing (a), continuing the generation of the hydrogen radicals and stopping the generation of the oxygen radicals, by plasma excitation of hydrogen gas without oxygen gas and oxygen-containing gas, and exposing the surface of the substrate to a reducing atmosphere created with the hydrogen radicals,
wherein the oxygen radicals generated in (a) is remained in (b) in a space where the substrate is exposed.

US Pat. No. 10,192,733

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND CHEMICAL LIQUID

TOSHIBA MEMORY CORPORATIO...

1. A method of manufacturing a semiconductor device comprising:attaching, by a liquid treatment, a first liquid to a surface of a semiconductor substrate having a fine pattern formed therein;
substituting the first liquid attached to the surface of the semiconductor substrate with a solution, the solution comprising a precipitating material dissolved in a second liquid;
vaporizing the second liquid and precipitating the precipitating material to the surface of the semiconductor substrate; and
removing the precipitating material by transforming the precipitating material from solid to gas by depressurization and/or heating,
the precipitating material comprising at least one material selected from a group consisting of:
materials represented by chemical formulae A1, A2, A3, and A4 indicated in FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D where X1, X2, and X3 in the chemical formulae A1, A2, A3, and A4 each independently represent either of a hydroxy group (—OH), a carboxyl group (—COOH), an amino group (—NH2), an amide group (—CONH2), a nitro group (—NO2), and a methylester group (—COO—CH3), and
materials represented by chemical formulae B1, B2, B3, B4, and B5 indicated in FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, and FIG. 6E where X1, X2, X3, and X4 in the chemical formulae B 1, B2, B3, B4 and B5 each independently represent either of a hydroxy group (—OH), a carboxyl group (—COOH), an amino group (—NH2), an amide group (—CONH2), a nitro group (—NO2), a methylester group (—COO—CH3), a methoxy group (—OCH3), an ethoxy group (—OCH2CH3), and a propoxy group (—OCH2CH2CH3),
in the materials represented by chemical formulae A1, A4, B1, B3, and B5, a group bonded to one of adjacent bonding sites is a carboxyl group and one or more groups bonded to the other of the adjacent bonding sites include a carboxyl group, a hydroxyl group, or an amino group.

US Pat. No. 10,192,732

CONTAMINANT REMOVAL IN ULTRA-THIN SEMICONDUCTOR DEVICE FABRICATION

TEXAS INSTRUMENTS INCORPO...

1. A method of fabricating a semiconductor device, the method comprising:forming topside circuitry for an integrated circuit (IC) on a topside of a semiconductor substrate of the semiconductor device, the topside circuitry having a topside metal structure and a topside passivation structure;
applying a topside protection material to protect the topside circuitry;
grinding a backside of the semiconductor substrate to a selected thickness;
removing the topside protection material;
after removal of the topside protection material, applying a chemical solution cleaning process to remove contaminants from the backside of the semiconductor substrate;
applying a deionized (DI) water cleaning process to the semiconductor substrate after the chemical cleaning process; and
forming a backside metallization (BSM) layer over the backside of the semiconductor substrate,
wherein the topside metal structure comprises a gold (Au) metal structure and the topside passivation structure comprises a polyimide passivation structure, and further wherein the chemical solution cleaning process comprises exposing the semiconductor device to a solution of a mixture having ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) in a ratio of one part of NH4OH to two parts of H2O2, and the mixture is diluted in water in a ratio of one part of the mixture to eight parts of water.

US Pat. No. 10,192,731

LIQUID PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A liquid processing method for performing a liquid processing on a substrate disposed inside a processing container, and then, drying the substrate, the method comprising:a processing liquid supplying step of performing a liquid processing by supplying a processing liquid to a center portion of the substrate inside the processing container;
a low humidity gas supplying step of supplying a low humidity gas for lowering a humidity inside the processing container, into the processing container during a time period when the processing liquid is supplied to the substrate; and
a drying step of removing the processing liquid on the substrate and drying the substrate,
wherein the drying step is started after a humidity measurement value obtained by measuring the humidity inside the processing container becomes equal to or less than a preset humidity target value.

US Pat. No. 10,192,729

APPARATUS AND METHOD FOR STATIC GAS MASS SPECTROMETRY

Thermo Fisher Scientific ...

1. A method of static gas mass spectrometry comprising the steps of:introducing a sample gas comprising two or more isotopes to be analyzed into a static vacuum mass spectrometer at a time, t0;
operating an electron impact ionization source of the mass spectrometer with a first electron energy below the ionization potential of the sample gas for a first period of time that is following t0 until a time t1, wherein the first time period from t0 to t1 is set based on a previous determination of an equilibration period taken for the isotopes of the sample gas to equilibrate in the mass spectrometer; and
operating the electron impact ionization source with a second electron energy at least as high as the ionization potential of the sample gas for a second period of time that is after time t1;
wherein isotope ratio measurements are taken by the spectrometer during the second period but not during the first period.

US Pat. No. 10,192,728

MASS SPECTROMETER AND METHOD APPLIED THEREBY FOR REDUCING ION LOSS AND SUCCEEDING STAGE VACUUM LOAD

SHIMADZU CORPORATION, Ky...

1. A mass spectrometer, comprising:an ion source, located in a first gas pressure region and providing ions;
a vacuum chamber, having an inlet and an outlet and located in a second gas pressure region having a gas pressure lower than that of said first gas pressure region; wherein ions in said first gas pressure region are allowed to pass through said inlet of said vacuum chamber and enter said vacuum chamber located in said second gas pressure region along with a gas flow generated by a pressure difference, and exit said vacuum chamber from said outlet of said vacuum chamber;
an ion guiding device, arranged in said vacuum chamber and located at a succeeding stage of said vacuum chamber inlet but a preceding stage of said vacuum chamber outlet; and
a hollow tubular lens, arranged in said vacuum chamber and located at said succeeding stage of said vacuum chamber inlet but said preceding stage of said ion guiding device;
wherein said tubular lens is an aerodynamic lens whose central axis is parallel to a direction of said gas flow entering said vacuum chamber from said inlet of said vacuum chamber, said gas flow produces a Mach disc as a result of a free expanded jet after entering said vacuum chamber, and the inlet of said tubular lens is located at the upstream part of said Mach disc.

US Pat. No. 10,192,727

ELECTRODYNAMIC MASS ANALYSIS

Varian Semiconductor Equi...

1. An electrodynamic mass analysis system, comprising:an ion source;
an electrode assembly to extract a pulse of ions from the ion source; and
a deflector to receive the pulse of ions after the ions travel a predetermined distance from the electrode assembly, the deflector comprising two curved electrodes disposed on opposite sides of a path of the ions;
a plate having a resolving aperture disposed at an output end of the deflector;
wherein the deflector deflects the ions in accordance with an arrival time, such that only ions arriving during a predetermined time interval are guided through the deflector, and exit the deflector through the resolving aperture.

US Pat. No. 10,192,726

RAPID INLINE PREPARATION OF A DILUTED SAMPLE

ELEMENTAL SCIENTIFIC, INC...

1. A spectrometry analysis system including an inline dilution environment, comprising:a dilution apparatus including
a first valve assembly configured to prepare a first sample by accepting at least one of the first sample, a diluent, a carrier, or an internal standard, where the first valve assembly includes a first sample loop within the first valve assembly, and where the first sample loop prepares the first sample within the first valve assembly;
a second valve assembly configured to prepare the first sample by accepting the first sample from the first valve assembly, where the second valve assembly is coupled to the first valve assembly, where the second valve assembly includes a second sample loop within the second valve assembly, where the second sample loop isolates the first sample for injection into a torch assembly, and where the first valve assembly accepts and prepares a second sample while the first sample is isolated in the second sample loop; and
the torch assembly coupled to the dilution apparatus, where the second sample loop isolates and dilutes the first sample for injection into a torch assembly, and where the second valve assembly is coupled with the first valve assembly and the torch assembly;
wherein the dilution apparatus is configured to perform multiple injections of the prepared first sample to an analysis device.

US Pat. No. 10,192,725

ATMOSPHERIC INTERFACE FOR ELECTRICALLY GROUNDED ELECTROSPRAY

Waters Technologies Corpo...

1. An interface comprising:a front cone and an end piece;
a first ceramic tube having an inner bore extending from the front cone to the end piece, said inner bore comprising an entrance orifice and an exit orifice, and wherein the first ceramic tube is fabricated from a first ceramic material that is electrically resistive and thermally conductive; and
a high voltage DC power supply electrically connected at a first polarity to the front cone and to a front electrode in electrical and thermal contact with the front cone, and at a second polarity to the end piece.

US Pat. No. 10,192,724

MS/MS MASS SPECTROMETRIC METHOD AND MS/MS MASS SPECTROMETER

SHIMADZU CORPORATION, Ky...

1. An MS/MS mass spectrometer including an ionizing unit for ionizing a target component in a sample, a first mass separating unit for selecting, as a precursor ion, an ion having a specific mass-to-charge ratio from multivalent ions, the multivalent ion having a valence of two or more out of ions originated from the target component, a dissociation operation unit for dissociating the precursor ion selected by the first mass separating unit, a second mass separating unit for selecting a product ion having a specific mass-to-charge ratio from product ions generated through the dissociation, and a detecting unit for detecting the ion selected by the second mass separating unit, the MS/MS mass spectrometer comprising:a) a first inputting unit for allowing a user to input and set a mass mLoss of a fragment eliminated from the precursor ion through the dissociation;
b) a second inputting unit for allowing the user to input and set at least two of three parameters of a valence zLoss of the fragment, a valence zPrec of the precursor ion and a valence zprod of the product ion, the valence zLoss of the fragment being a valence of the fragment eliminated from the precursor ion through the dissociation when the dissociation is based on dissociation operation other than electron capture dissociation or a valence of a fragment before neutralized that captures an electron to be neutralized and eliminated when the dissociation is based on the electron capture dissociation;
c) a lack information calculating unit for calculating, when one of the three parameters zLoss, zPrec and zProd is not input, the one uninput parameter zLoss, zPrec or zProd from the parameters input by the second inputting unit using relation, zPrec=zProd+zLoss; and
d) a controlling unit for individually controlling operations of the first mass separating unit and the second mass separating unit in performing MS/MS analysis such that a mass-to-charge ratio MProd of the product ion selected by the second mass separating unit with respect to a mass-to-charge ratio MPrec of the precursor ion selected by the first mass separating unit satisfies relation, MProd=(MPrec×zPrec?mLoss)/zProd.

US Pat. No. 10,192,723

SOFT IONIZATION BASED ON CONDITIONED GLOW DISCHARGE FOR QUANTITATIVE ANALYSIS

LECO Corporation, St. Jo...

12. An ion source for a mass spectrometry apparatus, comprising:reactor chamber defining a sampling conditioning channel;
a glow discharge chamber residing adjacent to the reactor chamber;
a tubular electrode extruding into an interior of the glow discharge chamber, wherein the tubular electrode receives a voltage;
a sample nozzle residing at an outlet end of the reactor chamber;
a capillary for sample introduction, wherein the capillary passes through the glow discharge chamber, protrudes through the tubular electrode, and at least partially passes through the reactor chamber; and
a mechanical fluid pump residing in a location to allow evacuation of gas, wherein the mechanical fluid pump evacuates the gas from the glow discharge chamber past the sampling nozzle.

US Pat. No. 10,192,721

HIGH-FREQUENCY POWER SOURCE

DAIHEN Corporation, Osak...

1. A radio-frequency power source comprising:a radio-frequency signal generator that produces radio-frequency signals having a variable phase difference between them;
at least two amplifiers configured to amplify the radio-frequency signals, respectively;
a voltage supplier configured to supply DC voltage to the at least two amplifiers;
a radio-frequency combiner that combines amplified radio-frequency signals outputted from the at least two amplifiers by a predetermined ratio depending on the phase difference, and that outputs to a load;
an output controller that causes the radio-frequency signal generator to change the phase difference, thereby controlling radio-frequency power outputted from the radio-frequency combiner,
wherein the output controller performs control so that the phase difference changes so as to make the radio-frequency power outputted from the radio-frequency combiner into a desired waveform, while causing the radio-frequency signal generator to continue producing the radio-frequency signals when the DC voltage supplied from the voltage supplier remains constant.

US Pat. No. 10,192,719

PLASMA PROCESSING METHOD

Tokyo Electron Limited, ...

1. A plasma processing method comprising:a step of loading a substrate into a chamber where a plasma process is to be executed;
a step of mounting the substrate on a mounting table;
a first step of applying a bias power to the mounting table for a predetermined time period,
stopping the bias power after the predetermined time period, the bias power having a frequency that is lower than a frequency of excitation power for plasma excitation;
a second step of applying the bias power to the mounting table on which the substrate is mounted before applying an excitation power for plasma excitation;
a step of applying a DC voltage to an electrostatic chuck and electrostatically attracting the substrate that is mounted on the mounting table;
a step of supplying etching gas in the chamber; and
a step of applying the excitation power for the plasma excitation,
wherein the first step of applying the bias power and the second step of applying the bias power are performed on an identical substrate as one cycle before the DC voltage is applied on the electrostatic chuck so as to electrostatically attract the substrate by the electrostatic chuck,
wherein the first and second steps of applying the bias power are performed before supplying the etching gas, and
wherein the bias power of the first and the second steps are the same bias power and applied by one high frequency power source.

US Pat. No. 10,192,717

CONDITIONING REMOTE PLASMA SOURCE FOR ENHANCED PERFORMANCE HAVING REPEATABLE ETCH AND DEPOSITION RATES

APPLIED MATERIALS, INC., ...

10. The method of claim 9, wherein the passivation time of the interior wall surface of the remote plasma source and the processing time for performing a series of processes on N number of substrates are at a ratio of about 1:5 to about 1:30.

US Pat. No. 10,192,716

MULTI-BEAM DARK FIELD IMAGING

KLA-Tencor Corporation, ...

1. An apparatus, comprising:an electron source;
at least one optical device configured to produce a plurality of primary beam lets utilizing electrons provided by the electron source, the at least one optical device further configured to deliver the plurality of primary beam lets toward a target; and
an array of multi-channel detectors configured to receive a plurality of image beam lets emitted by the target in response to the plurality of primary beamlets, the array of multi-channel detectors further configured to render an array of dark field images to form a contiguous dark field image, wherein each multi-channel detector of the array of detectors comprises a set of detector elements.

US Pat. No. 10,192,715

MEASUREMENT OF THE ELECTRIC CURRENT PROFILE OF PARTICLE CLUSTERS IN GASES AND IN A VACUUM

1. A Faraday detector to measure the electric current profile of clusters of electrically charged particles, comprising:a detector electrode having structural elements in a bipolar arrangement of two groups, where neighboring structural elements have opposite polarities and structural elements with the same polarity are electrically connected, and bordering a gas-filled or evacuated space;
at least one voltage supply which is connected with the two groups of structural elements and supplies the two groups of structural elements simultaneously with different electric potentials such that charged particles originating from the space are substantially all deflected onto one of the two groups of structural elements having one polarity; and
a set of measurement electronics which is configured to separately measure current profiles at the structural elements of both polarities and to generate a differential signal by subtracting the current profiles to leave only a particle current profile.

US Pat. No. 10,192,714

ELECTRON MICROSCOPE SAMPLE HOLDER FOR FORMING A GAS OR LIQUID CELL WITH TWO SEMICONDUCTOR DEVICES

Protochips, Inc., Morris...

1. A sample holder for an electron microscope, said sample holder comprising:a sample holder body that defines:
a first pocket for positioning of a first microelectronic device therein; and
a second pocket for positioning of a second microelectronic device therein, the second pocket being above the first pocket within the sample holder,
wherein a first seal is positioned between the first pocket and the first microelectronic device when the first microelectronic device is installed within the first pocket, wherein the first seal surrounds a hole defined in the sample holder body for allowing passage of an electron beam, and
wherein a second seal is engaged with the second pocket such that fluids are sealed between the first seal and the second seal when the second microelectronic device is installed within the second pocket,
wherein the second pocket defines a perimeter that is larger than a perimeter of the first pocket and the first pocket and the second pocket are in fluid communication,
wherein at least one electrical contact extends from the second pocket for electrically coupling to the second microelectronic device when the second microelectronic device is installed within the second pocket; and
a lid for covering a portion of the sample holder body.

US Pat. No. 10,192,712

CHARGED PARTICLE BEAM WRITING APPARATUS, METHOD OF ADJUSTING BEAM INCIDENT ANGLE TO TARGET OBJECT SURFACE, AND CHARGED PARTICLE BEAM WRITING METHOD

NuFlare Technology, Inc.,...

1. A method of adjusting a beam incident angle to a target object surface comprising:applying, using a blanking deflector arranged backward of an electron lens with respect to a direction of an optical axis, a voltage for beam-on to the blanking deflector, converging, using the electron lens and a magnet coil arranged in a center height position of the blanking deflector, a charged particle beam by varying a voltage to be applied to the electron lens while supplying, to the magnet coil, a current for a deflection amount smaller than a deflection amount for performing deflection to make a beam-off state by the blanking deflector, and measuring a positional deviation amount of an irradiation position of the charged particle beam irradiating a target object, for each voltage to be applied to the electron lens;
determining whether the positional deviation amount is within an allowable value, for the each voltage to be applied to the electron lens; and
when the positional deviation amount is determined to be greater than an allowable value, the each voltage to be applied to the electron lens are adjusted so that the positional deviation amount is within the allowable value.

US Pat. No. 10,192,711

FLUID INJECTOR FOR X-RAY TUBES AND METHOD TO PROVIDE A LIQUID ANODE BY LIQUID METAL INJECTION

Siemens Aktiengesellschaf...

1. A fluid injector for x-ray tubes to provide a liquid anode by liquid metal injection, comprising:a device which injects fluid from an opening in a chamber of the device as a fluid jet generated by an arrangement for changing a volume within the chamber;
a pipe connected to the chamber of the device; and
a reservoir for storing the anode material, said reservoir being fluidically connected by the pipe with the chamber of the device;
wherein the pipe comprises a part formed in a fluid flow direction with a shape to block fluid flow from the chamber to the reservoir during injection.

US Pat. No. 10,192,708

ELECTRON EMITTER SOURCE

OREGON PHYSICS, LLC, Bea...

1. An electron emitter comprising:a wehnelt
an anode spaced downstream from said wehnelt;
a co-axial aperture formed through said wehnelt and said anode; and
an emitter extending into said co-axial aperture so that a terminal surface of said emitter is positioned between said wehnelt and said anode, said emitter having a cylindrical base formed of a high work function material having a hole formed through said terminal surface and extending into a body of the cylindrical base, said emitter further including a structure formed of a low work function material embedded within said hole and having an exposed emissive area,
wherein said emitter is heated and biased to a negative voltage relative to the anode.

US Pat. No. 10,192,707

FUSE ASSEMBLY WITH REPLACEABLE CASING

1. A fuse assembly comprising:a casing having two slots defined through a first end thereof, the casing having a room defined therein which communicates with the two slots, two protrusions extending from an inside of the room, the casing having two insertion recesses defined through the first end thereof, each of the insertion recesses having a positioning member formed in an inside surface thereof;
a conductive member located in the casing and having a first end extending through a second end of the casing, the conductive member including two blades which are located with a gap formed therebetween, a fuse connected between the two blades, each of the two blades having a hole, the two protrusions engaged with the two holes of the two blades;
a cap having an open bottom which is detachably mounted to the first end of the casing, two arms respectively extending from two ends of the cap and each arm having a hook end, the two arms inserted into the two insertion recesses and the two hook ends being detachably hooked to the two positioning members, and
a light member connected to the cap and having a bulb and a leg portion which is electrically connected to the bulb, the leg portion being electrically connected to a second end of the conductive member.

US Pat. No. 10,192,706

UNDERMOLDED AND OVERMOLDED FUSE JOINTS

SHOALS TECHNOLOGIES GROUP...

1. A fuse joint including:A) a fuse;
B) a first wire segment having two ends and a middle portion there between, said middle portion attached directly to said fuse at a first connection point;
C) a second wire segment attached directly to said fuse at a second connection point, said second wire segment having two ends and a middle portion there between;
D) an undermolding surrounding said fuse; and
E) an overmolding surrounding said undermolding.

US Pat. No. 10,192,703

BYPASS SWITCH COMPRISING A PLUNGER, A FIRST CONTACT DEVICE AND A SECOND CONTACT DEVICE

ABB SCHWEIZ AG, Baden (C...

1. A bypass switch for providing a bypass path between a first terminal and a second terminal, the bypass switch comprising:a first contact device;
a second contact device; and
a plunger being moveable from an initial state, via a first state, to a second state, wherein in the initial state the first terminal and second terminal are conductively separated; in the first state a movement of the plunger causes the first contact device to close a first conductive connection between the first terminal and the second terminal; and in the second state the plunger mechanically forces the second contact device to close a second conductive connection between the first terminal and the second terminal, AND
wherein the plunger comprises a front section and a back section, wherein the front section is detachably connected to the back section, and wherein, in the first state, it is the back section which causes the first contact device to close the first conductive connection.

US Pat. No. 10,192,702

ELECTROMAGNETIC RELAY AND RELAY DEVICE

PANASONIC INTELLECTUAL PR...

1. An electromagnetic relay, comprising:a contact point including a fixed contact and a movable contact;
a driver including a coil and is configured to bring the movable contact into contact with the fixed contact and to separate the movable contact from the fixed contact;
a base having an opening and including a first wall section surrounding an accommodation space in which the contact point and the driver are accommodated;
a cover covering the opening of the base; and
at least one connection terminal configured to electrically connect the coil to an external connection body, wherein
the first wall section of the base has a through hole communicating with an interior and an exterior of the accommodation space,
the at least one connection terminal includes:
a first terminal section accommodated in the base and electrically connected to the coil; and
a second terminal section protruding outside the base through the through hole and electrically connected to the external connection body,
the cover includes a second wall section disposed to leave a space from the first wall section having the through hole, and the second terminal section lies in the space, and
the space in which the second terminal section lies is sealed with a sealant.

US Pat. No. 10,192,701

SWITCH ACTUATION APPARATUS AND METHOD

GM Global Technology Oper...

1. An actuation apparatus comprising:a steering wheel armature including a base member;
wherein a module includes an air bag assembly;
the base member having a base defining a base axis and a base face;
wherein the steering wheel armature is rotatable about a rotation axis;
wherein the rotation axis and the base axis are non-coincident;
a plurality of base magnetic elements mounted to the base face and distributed around the base axis;
the module having a module face; and
a plurality of module magnetic elements mounted to the module face;
wherein the module is movably tethered to the base member;
wherein each of the base magnetic elements is aligned with a respective one of the module magnetic elements to form a paired magnet set such that the plurality of module magnetic elements and the plurality of base magnetic elements form a plurality of paired magnet sets; and
wherein the base magnetic element and the module magnetic element of each paired magnet set are oriented such that a repulsive magnetic force is generated between the base magnetic element and the module magnetic element of each paired magnetic set.

US Pat. No. 10,192,700

AIR CIRCUIT BREAKER HAVING AN IMPROVED ELECTRIC ARC QUENCHING CHAMBER

SCHNEIDER ELECTRIC INDUST...

1. An air circuit breaker, comprising:two separable electrical contacts connected to electric current input and output terminals; and
a chamber for quenching an electric arc, to extinguish the electric arc formed during the separation of the electrical contacts, said quenching chamber comprising a stack of splitter plates that are spaced apart from one another, and lateral walls placed on either side of the stack, the splitter plates being fixed to the lateral walls, each lateral wall including a thermosetting-resin impregnated polyamide fabric and being devoid of glass fibres,
wherein the quenching chamber furthermore includes protective elements made of crosslinked polyamide, said protective elements being placed inside the quenching chamber, along the lateral walls on either side of the stack, in junction zones between the lateral walls and the splitter plates, the protective elements covering corners of the splitter plates which corners are adjacent to the lateral walls, so as to separate these corners of the splitter plates from the electrical contacts, and
wherein each protective element comprises seats and a plurality of fingers, the seats being bounded by the fingers, one corner of the splitter plate of the stack being received inside each seat, and each pair of fingers in the plurality of fingers having one of the splitter plates disposed therebetween,
wherein the protective elements extend substantially parallel to the stack, from a lower end of the stack to a lower edge of an upper arcing horn situated above the stack, such that are there splitter plates included in the stack of splitter plates which are not covered by the protective elements.

US Pat. No. 10,192,699

POWER SEAT OPERATION DEVICE AND POWER SEAT

NHK Spring Co., Ltd., Yo...

1. A power seat operation device comprising:a dial that is rotatably installed at a side face of a power seat provided with a plurality of moving mechanisms, one of the plurality of moving mechanisms being selected by rotational operation of the dial, and an interior and an exterior of the dial being in communication through an opening formed at a peripheral outer side of the dial;
a switch that is attached inside the dial, the switch actuating the selected moving mechanism;
a knob that is installed inside the dial at a seat width direction outer side of the switch, that is rotatably supported by the dial, that includes an operation portion inserted through the opening so as to project outside the dial, and that is capable of operating the switch by operation of the operation portion; and
a channel that is formed inside the dial by the dial and the knob, the channel being partitioned from the switch, and, in cases in which liquid has infiltrated into the dial through the opening in a state in which the opening is positioned at an upper side of the switch, the channel letting the liquid flow downward to a lower side of the switch so as to discharge the liquid to outside the dial.

US Pat. No. 10,192,698

INPUT DEVICE WITH ADJUSTABLE FORCE LEVEL

PRIMAX ELECTRONICS LTD., ...

1. An input device with an adjustable force level, comprising:a circuit board comprising a switch; and
a key structure located over the circuit board, and comprising:
a key body comprising a keycap and a triggering element, wherein the triggering element is connected with the keycap;
a casing located under the keycap and assembled with the circuit board, wherein the triggering element is inserted into an inner portion of the casing; and
a pressure-adjustable elastic receptacle partially or completely accommodated within the casing and contacted with the key body, wherein the pressure-adjustable elastic receptacle comprises a pressure-adjusting opening, and a pressure within the pressure-adjustable elastic receptacle is set through the pressure-adjusting opening, wherein when the key body is pressed down, a resisting force to resist the key body is provided by the pressure-adjustable elastic receptacle according to the pressure within the pressure-adjustable elastic receptacle,
wherein when the key structure is pressed down to a triggered position by a user, the switch of the circuit board is triggered by the triggering element.

US Pat. No. 10,192,696

LIGHT-EMITTING ASSEMBLY FOR KEYBOARD

APPLE INC., Cupertino, C...

1. A keyboard assembly, comprising:a switch housing defining a switch opening and a light source recess formed in a sidewall of the switch opening;
a tactile dome positioned at least partially within the switch opening;
a keycap positioned above the switch housing and configured to move toward the tactile dome when pressed; and
a light-emitting assembly positioned within the light source recess of the switch housing, and comprising:
a light source;
a luminescent structure at least partially enclosing the light source and defining a front face of the light-emitting assembly;
an opaque material defining a rear face of the light-emitting assembly, the rear face being positioned opposite the front face;
a first sidewall defining a first side face of the light-emitting assembly; and
a second sidewall opposite the first sidewall and defining a second side face of the light-emitting assembly, wherein the switch housing is configured to receive light from each of the front face, the first side face, and the second side face and to guide the received light toward the keycap, wherein the opaque material is configured to prevent light from passing through it.

US Pat. No. 10,192,695

KEYSWITCH ASSEMBLY AND MANUFACTURING METHOD THEREOF

GETAC TECHNOLOGY CORPORAT...

1. A keyswitch assembly corresponding to a single key on a keyboard, comprising:a display unit comprising a plurality of display regions each capable of being individually switched between a light-on and a light-off state;
a carrier for carrying the display unit;
a plurality of contact pads on the carrier, the contact pads being electrically connected to the display regions;
a light-shielding layer positioned corresponding to the display regions, the light-shielding layer comprising a plurality of transparent patterns, the transparent patterns positioned respectively corresponding to the display regions; and
a transparent keycap positioned on the display unit;
wherein the light-shielding layer comprises a layer of light-shielding material in which the transparent patterns are formed, wherein the transparent patterns permit light emitted from the corresponding display regions to pass through.

US Pat. No. 10,192,694

INTERLOCKING CONTROL DEVICE OF MULTIPLE-UNIT TRAIN SAFETY CIRCUIT

CRRC QINGDAO SIFANG CO., ...

1. An interlocking control device for a multiple-unit safety circuit, comprising:a protective grounding switch control branch which comprises: a pantograph rising pneumatic circuit cut-off valve, a protective grounding switch turn-off pneumatic circuit cut-off valve and a protective grounding switch turn-off solenoid valve which are connected in series, wherein
when high-voltage equipment of a multiple-unit train is under inspection and maintenance or is powered by an external power supply, a protective grounding switch is turned on, a cock of the pantograph rising pneumatic circuit cut-off valve and a cock of the protective grounding switch turn-off pneumatic circuit cut-off valve are rotated to open a cover of a key box, the protective grounding switch control branch is disconnected, the protective grounding switch turn-off solenoid valve connected in series in the protective grounding switch control branch is powered off to maintain the protective grounding switch in an on state; and
the cover of the key box is mechanically locked by means of the pantograph rising pneumatic circuit cut-off valve and the protective grounding switch turn-off pneumatic circuit cut-off valve.

US Pat. No. 10,192,692

EXPLOSION-PROOF CROSS-TYPE LIMIT SWITCH

1. An explosion-proof limit switch (10) comprising:a housing (12);
a gear mechanism (24) arranged in said housing (12), said gear mechanism including a gear mechanism cover plate (38), a gear mechanism base plate (48) and at least one intermediate plate (42) arranged between the gear mechanism cover plate (38) and the gear mechanism base plate (48);
said intermediate plate (42) having at least one cutout (44) in which a first gearwheel (54) is arranged and at least one second cutout (46) in which a second gearwheel (58) is arranged;
said first gearwheel (54) having a first plug-through opening (56) and said second gearwheel (58) having a second plug-through opening (60);
a shaft (20) having an actuating lever (18) arranged outside the housing (12) and being rotatably supported in a first bearing arrangement (22) connected to the housing (12) and extending through the first plug-through opening (56) of the first gearwheel (54) in order to couple with the first gearwheel (54) in a torque transmitting manner and to radially support said first gearwheel (54); and
a rotary switch (30) arranged in the housing (12) and having a switch shaft (138) that is rotatably supported in a second bearing arrangement (106, 134) and extends through the second plug-through opening (60) of the second gearwheel (58) in order to couple with the second gearwheel (58) in a torque transmitting manner and to radially support said second gearwheel (58).

US Pat. No. 10,192,691

ELECTRICITY STORAGE UNIT

Panasonic Intellectual Pr...

1. An electricity storage unit comprising:an electricity storage device;
a holder for holding the electricity storage device;
a control board that is formed with a wiring electrically connected with the electricity storage device;
a case having a tubular side wall part and a bottom surface part closing one end of the side wall part, the case being formed with an opening at another end of the side wall part; and
a cover for covering the opening, wherein:
the electricity storage device, the holder, and the control board are housed inside the case,
the holder is fixed to the control board, and
a rear end of the holder is supported inside the case by abutting the rear end to an inner surface of the bottom surface part, the rear end facing the bottom surface part.

US Pat. No. 10,192,690

TITANIUM OXIDE-BASED SUPERCAPACITOR ELECTRODE MATERIAL AND METHOD OF MANUFACTURING SAME

SHANGHAI INSTITUTE OF CER...

1. A titanium oxide-based supercapacitor electrode material, comprising a conductive titanium oxide as an active substance, wherein the conductive titanium oxide is selected from the group consisting of titanium sub-oxide, reduced titanium dioxide, and doped reduced titanium dioxide, a whole or a surface of the titanium sub-oxide, the reduced titanium dioxide, or the doped reduced titanium dioxide having amorphous layers comprising defect structures and activated Ti3+; and the titanium oxide-based supercapacitor electrode material has a density of charge carrier higher than 1018 cm?3, and a specific capacitance in a range of 20 F/g˜1,740 F/g, under a charge-discharge current of 1 A/g; and the titanium sub-oxide, the reduced titanium dioxide, or the doped reduced titanium dioxide is prepared by a step of performing a high surface reduction treatment on titanium dioxide to obtain the titanium sub-oxide or the reduced titanium dioxide, or by a step of performing the high surface reduction treatment and a doping treatment on titanium dioxide to obtain the doped reduced titanium dioxide; wherein the high surface reduction treatment is performed at 200˜500° C. for 2˜12 hours.

US Pat. No. 10,192,689

SELF-ASSEMBLY OF PEROVSKITE FOR FABRICATION OF TRANSPARENT DEVICES

YISSUM RESEARCH DEVELOPME...

1. A patterned perovskite material, comprising a plurality of continuous intersecting perovskite line patterns, defining confined regions enclosed by walls of said intersecting line patterns, wherein the confined regions are perovskite-free voids.

US Pat. No. 10,192,687

CAPACITOR ASSEMBLY HAVING A NON-SYMMETRICAL ELECTRODE STRUCTURE AND CAPACITOR SEAT STRUCTURE THEREOF

APAQ TECHNOLOGY CO., LTD....

1. A capacitor assembly having a non-symmetrical electrode structure, comprising:a capacitor seat structure including a capacitor seat, a first electrode layer and a second electrode layer, wherein the first electrode layer and the second electrode layer are disposed on a bottom side of the capacitor seat and separated from each other, and the capacitor seat has a first through hole, a first groove communicated with the first through hole, a second through hole separated from the first through hole, and a second groove communicated with the second through hole; and
a capacitor package structure disposed on the capacitor seat structure, wherein the capacitor package structure includes a wound capacitor, a package casing for enclosing the wound capacitor, a first conductive pin electrically contacting the wound capacitor and partially exposed from the package casing, and a second conductive pin electrically contacting the wound capacitor and partially exposed from the package casing;
wherein the first electrode layer is partially received inside the first groove, and the first conductive pin has a first through portion passing through the first through hole and a first bending portion disposed inside the first groove and electrically contacting the first electrode layer;
wherein the second electrode layer is partially received inside the second groove, and the second conductive pin has a second through portion passing through the second through hole and a second bending portion disposed inside the second groove and electrically contacting the second electrode layer;
wherein the first electrode layer and the second electrode layer have the same or different surface areas; and
wherein the capacitor seat is a non-symmetrical electrode structure body, a first surface area of the first electrode layer is larger than a second surface area of the second electrode layer, and the second electrode layer is closer to a geometric center of the capacitor seat than the first electrode layer is.

US Pat. No. 10,192,686

MULTILAYER ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component comprising:a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, one ends of the first and second internal electrodes being exposed through the third and fourth surfaces, respectively;
first and second external electrodes including, respectively, first and second band portions disposed on the first surface of the capacitor body to be spaced apart from each other and first and second connected portions, respectively extending from the first and second band portions to the third and fourth surfaces of the capacitor body;
first and second connection terminals formed of insulators and disposed on the first and second band portions, respectively; and
first and second insulating portions disposed on at least some circumferential surfaces of the first and second connection terminals, respectively,
wherein the first connection terminal includes a first conductive pattern formed on a surface thereof facing the first band portion, a second conductive pattern formed on a surface thereof opposing the surface on which the first conductive pattern is formed, a first cut portion formed in some circumferential surfaces thereof connecting the first and second conductive patterns to each other, and a first connection pattern formed on the first cut portion to electrically connect the first and second conductive patterns to each other, and
the second connection terminal includes a third conductive pattern formed on a surface thereof facing the second band portion, a fourth conductive pattern formed on a surface thereof opposing the surface on which the third conductive pattern is formed, a second cut portion formed in some circumferential surfaces thereof connecting the third and fourth conductive patterns to each other, and a second connection pattern formed on the second cut portion to electrically connect the third and fourth conductive patterns to each other.

US Pat. No. 10,192,685

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body including a plurality of first and second internal electrodes alternately disposed therein and a dielectric layer interposed therebetween, the capacitor body having a first surface and a second surface opposing each other, a third surface and a fourth surface opposing each other and connected to the first and second surfaces, and a fifth surface and a sixth surface opposing each other and connected to the first to fourth surfaces;
a plurality of external electrodes connected to the plurality of first and second internal electrodes;
an insulating layer disposed on the first surface of the capacitor body;
a first terminal electrode and a second terminal electrode disposed on the insulating layer and spaced apart from each other in a direction in which the third and fourth surfaces are connected to each other; and
a connecting member electrically connecting the first and second terminal electrodes and the plurality of external electrodes to each other.

US Pat. No. 10,192,684

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body including dielectric layers and a plurality of first and second internal electrodes alternately disposed therein, having the dielectric layers interposed therebetween, and having a first surface and a second surface opposing each other in a first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction, and a fifth surface and a sixth surface connected to the first surface and the second surface, connected to the third surface and the fourth surface, and opposing each other in a third direction, the plurality of first and second internal electrodes being exposed through at least the third surface and the fourth surface, respectively;
a first external electrode and a second external electrode including first and second connection portions disposed on the third surface and the fourth surface of the capacitor body and electrically connected to exposed portions of the plurality of first and second internal electrodes, and first and second band portions extending from the first and second connection portions to portions of the first surface and the second surface of the capacitor body and to portions of the fifth surface and the sixth surface of the capacitor body, respectively;
a first conductive resin layer including a first portion covering a portion of the first band portion and disposed on the first surface of the capacitor body, and a second portion extending from the first surface onto one of the surfaces of the capacitor body other than the first surface;
a second conductive resin layer including a third portion covering a portion of the second band portion and disposed on the first surface of the capacitor body, and a fourth portion extending from the first surface onto one of the surfaces of the capacitor body other than the first surface;
an insulating layer disposed on the first surface of the capacitor body; and
a first terminal electrode and a second terminal electrode disposed to be spaced apart from each other in the second direction, covering portions of the insulating layer disposed on the first surface of the capacitor body, and connected to the first and second external electrodes, respectively.

US Pat. No. 10,192,683

MULTILAYER CAPACITOR AND BOARD HAVING THE MULTILAYER CAPACITOR MOUNTED THEREON

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor, comprising:a capacitor body including dielectric layers and a plurality of first internal electrodes and second internal electrodes, the plurality of first internal electrodes and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, the capacitor body further having a first surface and a second surface opposing each other, a third surface and a fourth surface each connected to each of the first surface and the second surface and the third surface and the fourth surface opposing each other, and a fifth surface and a sixth surface each connected to each of the first surface and the second surface, each of the fifth surface and the sixth surface connected to each of the third surface and the fourth surface, and the fifth surface and the sixth surface opposing each other, the first internal electrodes and the second internal electrodes being exposed through at least the third surface and the fourth surface, respectively;
an insulating layer disposed on the first surface of the capacitor body;
a buffer layer at least partially covering the insulating layer;
a first terminal electrode and a second terminal electrode extended from the third surface and the fourth surface of the capacitor body to the buffer layer, respectively, and spaced apart from each other; and
a first external electrode and a second external electrode disposed on the third surface and the fourth surface of the capacitor body, respectively, so that on a same side of the capacitor body at least a portion of at least one of the insulating layer or the buffer layer is arranged between at least one of the first external electrode or the second external electrode and at least one of the first terminal electrode or the second terminal electrode, respectively.

US Pat. No. 10,192,682

COMPOSITE ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A composite electronic component comprising:a multilayer capacitor;
an electrostatic discharge (ESD) protecting element; and
first to fourth conductive resin layers,
wherein the multilayer capacitor includes:
a capacitor body including dielectric layers and a plurality of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, each of the first internal electrodes extending from the third surface to the fourth surface and being exposed through the third and fourth surfaces, and each of the second internal electrodes extending from the fifth surface to the sixth surface and being exposed through the fifth and sixth surfaces;
first and second external electrodes extending from the third and fourth surfaces of the capacitor body to portions of the first surface of the capacitor body, respectively, and connected to exposed portions of the first internal electrodes; and
third and fourth external electrodes extending from the fifth and sixth surfaces of the capacitor body to portions of the first surface of the capacitor body, respectively, and connected to exposed portions of the second internal electrodes,
the ESD protecting element includes:
first and second lead electrodes disposed on the first surface of the capacitor body to be connected to the first and second external electrodes, respectively;
a third lead electrode disposed on the first surface of the capacitor body to connect the third and fourth external electrodes to each other, the first and second lead electrodes being spaced apart from the third lead electrode;
a discharge portion disposed on the first surface of the capacitor body and covering the first to third lead electrodes; and
a protective layer disposed to cover the discharge portion, and
the first to fourth conductive resin layers are formed on the first to fourth external electrodes, respectively, and extend to portions of a first surface of the protective layer, respectively.

US Pat. No. 10,192,681

METHOD OF MANUFACTURING A CRYOGENIC COIL ASSEMBLY

Gedex Systems Inc., Miss...

1. A method of manufacturing a cryogenic coil assembly, the method comprising:a) securing a wire lead of a wire within a lead channel of a substrate, wherein a plurality of radial channels and the lead channel are formed in a substantially circular region of the substrate,
b) clamping the substrate to a backing plate, wherein a gap is defined between the substrate and the backing plate to accommodate the wire, wherein the backing plate is adapted to resist adherence to a chemical bonding agent;
c) removably securing a mandrel to the backing plate and substrate, wherein the mandrel locates in a hole defined in a center of the circular region of the substrate;
d) turning the mandrel, substrate, and backing plate to wind the wire into a spiral coil, wherein the wire passes through a bath before being wound into the coil, wherein the bath contains the chemical bonding agent; and
e) permitting the chemical agent to cure;
wherein the chemical agent seeps into the radial channels prior to being cured, such that the chemical bonding agent, when cured, is present within the radial channels.

US Pat. No. 10,192,679

METHOD OF MANUFACTURING RARE EARTH MAGNET

TOYOTA JIDOSHA KABUSHIKI ...

1. A method of manufacturing a rare earth magnet comprising:preparing a powder by preparing a rapidly-solidified ribbon by liquid solidification, and by crushing the rapidly-solidified ribbon to obtain a crushed powder, the rapidly-solidified ribbon being a plurality of fine crystal grains, the powder including a RE-Fe—B main phase and a grain boundary phase of a RE-X alloy present around the main phase, RE representing at least one of Nd and Pr, and X representing a metal element;
manufacturing a sintered compact including by press-forming the powder; and
manufacturing a rare earth magnet by performing hot deformation processing on the sintered compact to impart anisotropy to the sintered compact, wherein
a nitrogen content in the powder is adjusted to be at least 1,000 ppm and less than 3,000 ppm by performing at least one of the preparation of the powder and the manufacturing of the sintered compact in a nitrogen atmosphere,
wherein a grain size of the crushed powder is adjusted to be in a range of 75 ?m to 300 ?m,
an average grain size of the main phase constituting the sintered compact is adjusted to be 300 nm or less, and
a content ratio of RE in the RE-Fe—B main phase is 29 mass % to 32 mass %.

US Pat. No. 10,192,677

METHOD AND APPARATUS FOR LEAKAGE MONITORING FOR OIL-IMMERSED ELECTRICAL TRANSFORMERS

ABB Inc., Cary, NC (US)

1. A method of monitoring for oil leakage from an oil-immersed electrical transformer comprising:measuring, using at least a top-oil temperature sensor, a top-oil temperature of an oil of the oil-immersed electrical transformer;
measuring, using at least a temperature sensor, an ambient temperature;
measuring, using at least a current sensor, a winding current of at least one winding of the oil-immersed electrical transformer;
communicating, using a communication interface that is configured for interfacing with the top-oil temperature sensor, the temperature sensor, and the current sensor, online measurements comprising the ambient temperature measurement, the top-oil temperature measurement, and the winding current measurement;
determining, by a processing circuit, characteristic values for first and second parameters of a transformer top-oil temperature model, wherein the first parameter represents a top-oil temperature rise over ambient temperature and the second parameter represents an oil time constant, and wherein the characteristic values for the first and second parameters comprises at least one of pre-configured factory values and collected historical measurements;
estimating, by the processing circuit and using at least the determined characteristic values for the first and second parameters with the transformer top-oil temperature model, a top-oil temperature;
comparing, by the processing circuit, the estimated top-oil temperature to the on-line measurements;
fitting, by the processing circuit and in response to the comparison of the estimated top-oil temperature to the on-line measurements and in an iterative optimization process, the first and second parameters to obtain fitted characteristic values for the first and second parameters;
estimating, by the processing circuit, a transformer oil thermal capacitance as a function of the fitted characteristic values and correspondingly estimating a transformer oil weight as a function of the estimated transformer oil thermal capacitance;
generating, by the processing circuit, alarm signaling, based on comparing the estimated transformer oil weight to a characteristic transformer oil weight, the characteristic transformer oil weight being calculated from at least the characteristic values for the first and second parameters and
generating, by the processing circuit, a maintenance diagnostic of the oil-immersed electrical transformer based on the generated alarm signaling, the maintenance diagnostic implemented by the oil-immersed electrical transformer to detect a loss of oil from the oil-immersed electrical transformer.

US Pat. No. 10,192,674

COIL COMPONENT HAVING TERMINAL ELECTRODES WITH HIGH MOUNTING STRENGTH, AND ELECTRONIC DEVICE INCLUDING THE COIL COMPONENT

TAIYO YUDEN CO., LTD., T...

1. A coil component comprising an air-core coil embedded in a magnetic body constituted by resin and metal magnetic grains, and having terminal electrodes electrically connected to both ends of the coil, wherein:both ends of the coil are exposed on a surface of the magnetic body;
the terminal electrodes are formed across the surface of the magnetic body and ends of the coil, and constituted by an underlying layer formed with metal material and a cover layer placed on an outer side of the underlying layer; and
the underlying layer is in contact with the resin and metal parts of the metal magnetic grains where the underlying layer is in contact with the magnetic body,
wherein a magnetic body surface on a side where either terminal electrode is connected to the end of the coil contains less resin than a magnetic body surface on a side where no terminal electrode is connected to the end of the coil.

US Pat. No. 10,192,673

INDUCTOR

SAMSUNG ELECTRO-MECHANICS...

1. An inductor comprising:a body comprising a magnetic material and having an upper surface, a lower surface, and side surfaces connecting the upper surface and the lower surface; and
a coil part disposed in the body and including a support member comprising an insulating resin, the coil part comprising first and second coil patterns respectively formed on an upper surface and a lower surface of the support member, wherein
1.15?b/a?1.45, where a is a length from a central plane between the upper surface and the lower surface of the support member to an upper surface of the body, and b is a length from the central plane of the support member to the lower surface of the body.

US Pat. No. 10,192,672

COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A coil component, comprising:a substrate; and
a coil pattern disposed on the substrate,
wherein the coil pattern includes a vertical region having a side surface perpendicular with respect to the substrate and a tapered region connected to the vertical region and having a side surface inclined with respect to the substrate,
in a cross section of the coil pattern, a minimum width of the tapered region is less than a minimum width of upper and lower surfaces of the coil pattern,
the vertical region and the tapered region form a trapezoidal shape and are made of the same material, and
wherein a spacing between coil pattern turns is between 0.15 and 0.45 times a width of a cross sectional shape of the coil pattern.

US Pat. No. 10,192,671

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component, comprising:a multilayer body including a plurality of insulator layers stacked together;
a plurality of inner conductors including at least a first inner conductor, a second inner conductor, a third inner conductor and a fourth inner conductor formed between the insulator layers and extended to a side surface of the multilayer body; and
a plurality of outer electrodes formed on both side surfaces of the multilayer body, the outer electrodes including at least a first outer electrode connected to the first inner conductor, a second outer electrode connected to the second inner conductor, a third outer electrode connected to the third inner conductor and a fourth outer electrode connected to the fourth inner conductor,
wherein each of the outer electrodes is formed on a single side surface so as not to extend over two side surfaces of the multilayer body, and
wherein the first outer electrodes and the second outer electrode are facing each other, and the first outer electrode and the second outer electrode differ in length in a direction in which the insulator layers are stacked.