US Pat. No. 10,511,210

DEVICE FOR THE THERMAL MANAGEMENT OF AN ELECTRIC POWER TRAIN

Nissan Motor Co., Ltd., ...

1. A device for the thermal management of an electric power train of an electric or hybrid motor vehicle, comprising a main housing accommodating at least an electric motor comprising a cooling circuit and a mechanical speed reducer coupled to the motor and comprising a lubrication circuit capable of being connected to the cooling circuit of the motor, wherein the main housing comprises an oil sump, common to the cooling circuit and to the lubrication circuit, arranged in a lower part of the main housing, and a partition for the separation of the main housing into two parts, in which there are arranged respectively, on the one hand, the motor and its cooling circuit, and, on the other hand, the speed reducer and its lubrication circuit, the oil sump comprising an oil overflow passage through the separating partition and, beneath the oil overflow passage, an oil channel extending through the separating partition between the two parts, the oil channel including one end discharging the oil sump on the speed reducer side provided with a valve for regulating the flow of oil between the two parts, controlled by the temperature of the oil, and one opposite free end, discharging into the oil sump on the motor side, the controlled valve being adapted to close the passage of oil in the oil channel between the two parts when the temperature of the oil on the speed reducer side reaches a predefined temperature threshold, so that the oil stored on the motor side and the oil stored on the speed reducer side do not mix when the temperature threshold is reached.

US Pat. No. 10,511,209

ENGINE GENERATOR

Honda Motor Co., Ltd., T...

1. An engine generator, comprising:a general-purpose engine;
a generator unit configured to be driven by the engine to generate electric power and to be able to operate as an engine starter motor during engine starting;
a case configured to house the engine and the generator unit;
a battery pack including a battery and configured to be detachably attached to the case;
an inverter unit configured to be connected to the generator unit;
a power supply circuit including a terminal part coming into contact with a terminal of the battery and configured to interconnect the battery included in the battery pack attached to the case and the inverter unit and to supply power of the battery through the inverter unit to the generator unit; and
a cover supported on a surface of the case in a manner slidable along the surface to cover the terminal part, wherein
the battery pack includes a projection configured to push an end of the cover along the surface so as to expose the terminal part along with an attachment of the battery pack to the case,
the cover is supported slidably in a vertical direction, and
the projection is provided lower than the terminal of the battery so as to abut on an upper face of the cover along with the attachment of the battery pack to the case.

US Pat. No. 10,511,207

COMPACT ELECTRIC MACHINE WITH COMBINED ROTOR CARRIER AND CLUTCH HOUSING

BorgWarner Inc., Auburn ...

1. An electric machine comprising:a stator assembly;
a rotor positioned within the stator assembly;
a rotor carrier wherein the rotor is mounted on an outer surface of the rotor carrier, the rotor carrier including a hub portion, a radial portion extending from the hub portion, a first cylindrical portion extending from the radial portion, and a second cylindrical portion extending from the first cylindrical portion, wherein the hub portion, the radial portion, the first cylindrical portion and the second cylindrical portion are an integrally formed unitary component;
an engine disconnect clutch positioned within the rotor carrier and engaging an inner surface of the first cylindrical portion; and
a transmission clutch positioned within the rotor carrier and engaging an inner surface of the second cylindrical portion; and
wherein the radial portion of the rotor carrier includes an inner radial wall and an outer radial wall with an axial connecting wall extending between the inner radial wall and the outer radial wall.

US Pat. No. 10,511,205

DEVICE FOR ATTACHING/DETACHING IDLER HORN FOR ACTUATOR MODULE

ROBOTIS CO., LTD., Seoul...

1. A device for attaching and detaching an idler horn of an actuator module, which allows a motor, a reduction gear, and a control circuit to be included therein, the device comprising:a ring-shaped elastic switch configured to surround an inner side end of a cylindrical hollow portion provided in one surface of a housing which constitutes an outer surface of the actuator module, the ring-shaped elastic switch comprising a protrusion installed to protrude inward in the cylindrical hollow portion and a trigger ring installed to protrude outward in the cylindrical hollow portion; and
a ring-shaped cover member configured to fix the ring-shaped elastic switch and coupled to an inner side surface of the housing,
wherein the ring-shaped cover member is configured to cover an entire surface of the ring-shaped elastic switch except the trigger ring protruding outward,
wherein the ring-shaped elastic switch is selectively attached to and detached from the idler horn using an elastic force.

US Pat. No. 10,511,203

MOTOR STATOR STRUCTURE

Asia Vital Components Co....

1. A motor stator structure comprising:a main body having multiple magnetic poles and a shaft hole, the magnetic poles outward extending from the main body, each magnetic pole having a free end outward extending from the main body and a connection end opposite to the free end, the connection ends being connected with the main body, the shaft hole passing through the main body between two ends thereof; and
multiple stopper plates respectively correspondingly assembled with the free ends of the magnetic poles;
wherein a width of the free end is larger than a width of the connection end.

US Pat. No. 10,511,192

WIRELESS POWER RECEIVER

Samsung Electronics Co., ...

1. An electronic device comprising:a housing;
a rectifier configured to rectify power provided through a first port and a second port of a power receiving circuit; and
the power receiving circuit disposed within the housing and including a conductive pattern for wirelessly receiving the power, the conductive pattern comprising:
a main coil,
a first sub-coil, wherein a first end of the first sub-coil is connected to a first end of the main coil and a second end of the first sub-coil is connected to the first port, and
a second sub-coil, wherein a first end of the second sub-coil is connected to a second end of the main coil and a second end of the second sub-coil is connected to the second port.

US Pat. No. 10,511,186

AUTOMATIC TRANSFER POWER SUPPLY WITH RELAY PROTECTION

Amazon Technologies, Inc....

1. An automatic transfer power supply unit, comprising:a switched-mode power supply circuit having a semiconductor switch operated by a switch controller;
a first relay having a first metal armature and a first relay controller, the first relay selectively electrically coupling the switched-mode power supply circuit with a first source of electric power;
a second relay having a second metal armature and a second relay controller, the second relay selectively electrically coupling the switched-mode power supply circuit with a second source of electric power that is independent of the first source of electric power; and
a source transfer controller electronically coupled with the switch controller, the first relay controller, and the second relay controller, the source transfer controller configured to:
receive a source transfer signal indicating that the automatic transfer power supply unit is to transfer from the first source of electric power to the second source of electric power;
responsive to receiving the source transfer signal, send a suspend operation signal to the switch controller to cause the switch controller to operate the semiconductor switch to prevent the switched-mode power supply circuit from drawing electric current through the first relay or through the second relay during a first time interval;
after sending the suspend operation signal, causing the first relay to open and the second relay to close during the first time interval; and
send a resume operation signal to the switch controller element to cause the switch controller element to operate the semiconductor switch such that the switched-mode power supply circuit draws electric current through the second relay during a second time interval that is after the first time interval.

US Pat. No. 10,511,180

SYSTEMS AND METHODS FOR REUSE OF BATTERY PACK-SIDE CURRENT AND VOLTAGE SENSING

QUALCOMM Incorporated, S...

1. A battery pack comprising:a battery cell;
a protection circuit comprising a first field effect transistor (FET) and a second FET arranged back-to-back;
a current mirror directly coupled to a source of the first FET and a source of the second FET, the current mirror configured to provide information about current flowing to the battery cell;
a voltage sense circuit; and
a battery connector configured to couple to a power bus and convey information from the voltage sense circuit and the information about the current flowing to the battery cell to a remote power management integrated circuit (PMIC) across the power bus.

US Pat. No. 10,511,171

CHARGING/DISCHARGING DEVICE AND CHARGE/DISCHARGE CONTROL METHOD FOR CONTROLLING CHARGE OR DISCHARGE OF AN ELECTRICITY STORAGE UNIT

HONDA MOTOR CO., LTD., T...

1. A charging/discharging device comprising:an electricity storage unit provided to a transport equipment;
a power conversion unit that performs conversion of power exchanged between the electricity storage unit and an external power system;
a reception unit that receives an instruction transmitted from a server device that decides a time at which discharge of the electricity storage unit to the power system or charge of the electricity storage unit by power supplied from the power system is performed, the instruction including the time at which the discharge or the charge is performed; and
a control unit that starts up or stops based on the time indicated by the instruction received in the reception unit and controls an operation of the power conversion unit,
wherein the time, at which the discharge or the charge is performed, is decided based on a result, which is obtained when the server device performs power demand and supply prediction in the power system through time-series analysis of a power amount supplied from a power supplier to the power system and a power amount supplied from the power system to a power consumer, and a minimum trading unit of a power amount managed by the server device when power is exchanged with the power system, the time being indicated by the instruction.

US Pat. No. 10,511,157

ARC DETECTION IN ELECTRIC METER SYSTEMS

1. A system to detect electrical arcing conditions between an electrical meter and a meter socket in a utility box capable of providing a metered utility to a premises, the system comprising:the electrical meter configured to transmit utility electrical signals from a utility side of the meter socket to a premises side of the meter socket, the electrical meter having a disconnect circuit capable of interrupting the transmission of the utility electrical signals;
a measurement circuit capable of producing a set of measurement values of the utility electrical signals transmitted by the electrical meter; and
a processor capable of communicating with the measurement circuit and the disconnect circuit;
wherein the processor is capable of:
receiving the set of measurement values,
comparing one of the values of the set of measurement values to a threshold,
determining, based on the one of the values being within a first range from the threshold, that a potential arcing condition is present,
in response to determining that the potential arcing condition is present, providing an indication of the potential arcing condition to a communication subsystem and instructing the communication subsystem to transmit the indication of the potential arcing condition to a central system,
determining, based on the one of the values being outside of the first range and within a second range from the threshold, that an existing arcing condition is present, and
in response to determining that the existing arcing condition is present, providing a disconnect signal to the disconnect circuit,
wherein the disconnect circuit is configured to receive the disconnect signal and disconnect the premises from the utility electrical signals.

US Pat. No. 10,511,148

TUNABLE LASER DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A tunable laser device comprising:an active layer configured to generate first light by a first source;
a first reflective layer and a second reflective layer spaced apart from each other and having the active layer disposed between the first reflective layer and the second reflective layer to form a resonance cavity; and
a variable refractive index unit disposed in the resonance cavity and having a refractive index being variable according to a second source, the second source being different from the first source;
a spacer in the resonance cavity, the spacer being disposed on each side of the active layer and the variable refractive index unit, respectively,
wherein a wavelength of second light resonated in the resonance cavity among the first light generated in the active layer varies according to the refractive index of the variable refractive index unit.

US Pat. No. 10,511,125

CONNECTOR HAVING A LEVER

Tyco Electronics Japan G....

1. A connector, comprising:a wire cover having a cover lock and a cover biasing member, the cover biasing member having a leading edge portion at a distal end and a projection projecting upward; and
a lever pivotally attached to the wire cover and rotatable between an unmated position and a mated position having a lever hook and a lever biasing member, the lever biasing member having a portion close to a distal end thereof, when the lever is in the mated position, the portion abuts on the projection and the lever hook engages with the cover lock and the cover lock locking the lever in the mated position and the cover biasing member biasing the lever toward the unmated position when the lever is in the mated position.

US Pat. No. 10,511,090

WIRELESS TELECOMMUNICATION ANTENNA MOUNT AND CONTROL SYSTEM

Sentenia Systems, Inc., ...

1. An antenna mount for use with a telecommunication antenna having at least one AISG antenna control unit (ACU), said antenna mount comprising:a structure interface mounted to an installation structure;
an antenna interface mounted to said antenna, said antenna interface being rotatably connected to said structure interface through a pivot having a vertical axis and being rotatably movable about said vertical axis through a range of azimuth angle positions;
a mount azimuth control unit (MACU) having a motor mechanically interconnected with said structure interface and said antenna interface, an AISG compatible motor controller, a male bidirectional AISG port and a female bidirectional AISG port, said motor being controllable to drive rotatable movement of said antenna through said range of azimuth angle positions,
wherein the ACU and MACU are serially interconnected through said bidirectional AISG ports to an AISG control interface for serial remote control of both the ACU and MACU,
said mount further comprising a mechanical downtilt assembly mechanically interconnected between said antenna interface and said antenna, said mechanical downtilt assembly comprising a lower hinge connector connected between a lower portion of said antenna interface and a lower portion of said antenna, said lower hinge connector being pivotable about a horizontal axis, said mechanical downtilt assembly further comprising an upper downtilt bracket connected between an upper portion of said antenna interface and an upper portion of said antenna, said upper downtilt bracket being configured to pivot said antenna about said lower hinge connector through a range of tilt angle positions.

US Pat. No. 10,511,080

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package comprising:a core member including a plurality of insulating layers and a plurality of wiring layers and having a blind cavity penetrating through a portion of the plurality of insulating layers;
a semiconductor chip disposed in the blind cavity and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the core member and the active surface of the semiconductor chip and filling at least portions of the blind cavity; and
a connection member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer connected to the connection pads,
wherein the plurality of wiring layers include antenna patterns and ground patterns,
the antenna patterns and the ground patterns are disposed on different levels, and
the antenna patterns are connected to the connection pads through the redistribution layer.

US Pat. No. 10,511,070

COOLING PLATE FOR WEIGHT LIGHTENING, BATTERY MODULE COMPRISING THE SAME AND METHOD FOR MANUFACTURING THE SAME

LG CHEM, LTD., Seoul (KR...

1. A cooling plate interposed between a cooling unit that is in thermal contact with battery cells on at least one surface of a stack of battery cells and the battery cells, the cooling plate comprising a metal plating layer on the surface of a substrate made of a synthetic resin.

US Pat. No. 10,511,066

BATTERY PACK COOLING SYSTEM

Nissan Motor Co., Ltd., ...

1. A battery pack cooling system comprising:a battery pack case;
a plurality cell modules disposed in an internal space of the battery pack case so as to form a cooling passage that cools the cell modules by cooling air flowing in the cooling passage, the cell modules including a first cell, a second cell module and a third cell module, the cooling passage including a cooling air inlet passage, a cooling air exhaust passage, and a plurality of cooling branch passages disposed to connect the cooling air inlet passage and the cooling air exhaust passage in parallel, the first cell module being disposed in a first cooling branch passage of the plurality of cooling branch passages, the second cell module being disposed in a second cooling branch passage of the plurality of cooling branch passages, and the third cell module disposed in a third cooling branch passage of the plurality of cooling branch passages, the first cooling branch passage, the second cooling branch passage, and the third cooling branch passage being arranged in parallel from an upstream side to a downstream side of the flow of the cooling air;
a first minimum temperature sensor disposed in an upstream position of the first cell module to measure a lowest temperature region in the first cell module;
a second minimum temperature sensor disposed in an upstream position in the third cell module to measure a lowest temperature region in the third cell module;
a first maximum temperature sensor disposed in a downstream position of the second cell module to measure a highest temperature region in the second cell module;
a second maximum temperature sensor disposed in a downstream position of the first cell module to measure a highest temperature region in the first cell module;
a controller comprising a diagnostic unit configured to perform rationality diagnosis based on temperature information from the first minimum temperature sensor, the second minimum temperature sensor, the first maximum temperature sensor and the second maximum temperature sensor using at least one of:
a difference between temperature change gradients from the first minimum temperature sensor and the second minimum temperature sensor in which a lowest temperature in the first cell module and a lowest temperature in the third cell module can be compared, and
a difference between temperature change gradients from the second maximum temperature sensor and the first maximum temperature sensor in which a highest temperature in the first cell module and the highest temperature in the second cell module can be compared.

US Pat. No. 10,511,065

BATTERY POWERED SURGICAL INSTRUMENT WITH DUAL POWER UTILIZATION CIRCUITS FOR DUAL MODES

Ethicon LLC, Guaynabo, P...

1. A battery pack of a surgical instrument, the battery pack comprising:(a) a battery;
(b) a high range monitoring circuit, wherein the high range monitoring circuit is configured to be activated when an electrical current discharged from the battery exceeds a predetermined threshold value, wherein the high range monitoring circuit is further configured to assess the electrical current discharged from the battery at a first acquisition rate; and
(c) a low range monitoring circuit, wherein the low range monitoring circuit is configured to be activated when the electrical current discharged from the battery is below the predetermined threshold value, wherein the low range monitoring circuit is further configured to assess the electrical current discharged from the battery at a second acquisition rate;
wherein the battery is configured to conserve power when the low range monitoring circuit is activated; and
wherein the low range monitoring circuit is configured to decrease the second acquisition rate when the low range monitoring circuit remains activated for a predetermined duration;
wherein the first acquisition rate is greater than the second acquisition rate.

US Pat. No. 10,511,063

NEGATIVE ELECTRODE PLATE, ENERGY STORAGE DEVICE, METHOD FOR MANUFACTURING NEGATIVE ELECTRODE PLATE, AND METHOD FOR MANUFACTURING ENERGY STORAGE DEVICE

GS YUASA INTERNATIONAL LT...

1. A negative electrode plate in an electrode assembly of an energy storage device, the negative electrode plate comprising:a base material layer;
an active material layer formed on the base material layer in a state where the active material layer is exposed partially, a peripheral edge portion of the negative electrode plate including:
a layer-non-formed portion that is disposed on a first side of the negative electrode plate, which is connected to a current collector of the energy storage device and on which the active material layer is not formed; and
a layer-non-exposed portion that is disposed on a second side of the negative electrode plate, which differs from the first side and on which the active material layer is not exposed; and
a covering material which covers a portion of the base material layer in the layer-non-exposed portion and is adhered or joined to the base material layer.

US Pat. No. 10,511,053

SOLID ELECTROLYTE HAVING MAGNESIUM ION CONDUCTIVITY AND MAGNESIUM SECONDARY BATTERY USING THE SAME

PANASONIC INTELLECTUAL PR...

8. A secondary battery comprising:a positive electrode containing a positive electrode active material;
a negative electrode containing a negative electrode active material; and
the solid electrolyte according to claim 1.

US Pat. No. 10,511,035

RECIRCULATION ARRANGEMENT AND METHOD FOR A HIGH TEMPERATURE CELL SYSTEM

CONVION OY, Espoo (FI)

1. A recirculation arrangement for a high temperature fuel cell system or electrolysis cell system, each cell in the system having an anode, a cathode, and an electrolyte between the anode and the cathode, the recirculation arrangement comprising:at least one ejector for recirculating a fraction of gas exhausted from the anode and for accomplishing a desired flow rate of the recirculated flow, the ejector having at least one nozzle;
means for providing at least one primary feedstock fluid to said nozzle of the ejector, which nozzle has a convergent-divergent flow channel through which the at least one primary feedstock fluid will expand from an initial higher pressure to a lower pressure;
means for providing at least one supplementary fluid to said nozzle of the ejector, the supplementary fluid constituting a majority of a total flow supplied to the nozzle at startup of the system;
means for regulating a respective ratio of at least part of the fluids of the ejector to maintain a desired motive flow and pressure at the nozzle of said ejector in order to accomplish the desired recirculated flow rate; and
means for cutting off the supplementary fluid when a level of system loading is such that the primary feedstock fluid alone maintains the desired motive flow and pressure at an ejector inlet,
wherein the at least one ejector comprises a supersonic ejector,
wherein in the supersonic ejector, motive flow expands in a series of supersonic shocks assisting in mixture of the supplementary fluid with the at least one primary feedstock fluid, the at least one supplementary fluid is water,
wherein an oxygen to-carbon ratio of a mixture of primary and supplementary fluids supplied to the nozzle of the ejector is above a carbon forming threshold when fuel cells are not loaded, and
wherein the flow in said nozzle reaches speed of sound whenever at least one primary feedstock is supplied.

US Pat. No. 10,511,034

GASKET FOR FUEL BATTERY

NOK Corporation, (JP)

1. A gasket for a fuel battery provided in a fuel battery cell in which an intermediate part including an MEA is interposed between a first separator and a second separator, the gasket for the fuel battery comprising:a first gasket main body attached to the first separator;
a second gasket main body attached to the second separator;
wherein the first and second gasket main bodies contact the intermediate part at positions where the first and second gasket main bodies overlap each other in a plan view;
wherein the first and second gasket main bodies each include a pair of bank portions that are unitary with and formed on opposing sides of the respective gasket main body and configured for fixed size stop according to a gasket thickness,
wherein the bank portions for fixed size stop are supported by convex portions which are defined by pressed three-dimensional hollow shapes formed in the first and second separators;
wherein the convex portions are buried in the bank portions for fixed size stop.

US Pat. No. 10,511,015

ELECTRODE FOR ELECTROCHEMICAL DEVICE, METHOD FOR PREPARING THE SAME, AND ELECTROCHEMICAL DEVICE COMPRISING THE SAME

LG CHEM, LTD., Seoul (KR...

1. An electrode for an electrochemical device comprisinga metal electrode, and
a coating layer positioned on the surface of the metal electrode,
wherein the coating layer comprises a two-dimensional semiconductor material, and metal phosphide converted from a part of the two-dimensional semiconductor material, and
wherein the two-dimensional semiconductor material is phosphorene in the form of a monolayer film.

US Pat. No. 10,511,014

BATTERY MODULE AND BATTERY PACK

Kabushiki Kaisha Toshiba,...

1. A battery module comprising five nonaqueous electrolyte batteries electrically connected in series, each of the five nonaqueous electrolyte batteries comprising:a positive electrode;
a negative electrode; and
a nonaqueous electrolyte,
wherein the negative electrode comprises an active material comprising a titanium composite oxide comprising Na and a metal element M in its crystal structure, the metal element M being at least one selected from the group consisting of Zr, Sn, V, Nb, Ta, Mo, W, Fe, Co, Mn, and Al, and
the crystal structure of the titanium composite oxide has symmetry belonging to a space group Cmca or Fmmm.

US Pat. No. 10,511,012

PROTECTIVE COATINGS FOR CONVERSION MATERIAL CATHODES

QuantumScape Corporation,...

1. An energy storage device comprising:a. an anode,
b. an electrolyte, and
c. a cathode comprising:
a plurality of coated electrochemically active material particles, each electrochemically active material particle comprising:
a core comprising a conversion material, and
a coating surrounding the core comprising the conversion material,
wherein the coating selectively isolates the conversion material from the electrolyte,
wherein the electrochemically active material particles have a capacity that is greater than 300 mAh/g;
wherein the coating has a median coating coverage surrounding the core comprising the conversion material that is at least 90% of the surface area of the core comprising the conversion material; and
wherein the core comprising the conversion material comprises conversion material in the charged state;
wherein the conversion material comprises a fluoride of a metal; and wherein the metal is iron, manganese, nickel, copper, or cobalt; wherein the coating surrounding the core comprises lithium oxides, lithium halides, lithium alloys, or combinations thereof.

US Pat. No. 10,511,007

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SANYO Electric Co., Ltd.,...

1. A nonaqueous electrolyte secondary battery, comprising:a flat power generating element including
a positive electrode plate,
negative electrode plate, and
a separator that electrically isolates the positive electrode plate and the negative electrode plate from each other;
an outer package, inside of which the power generating element is disposed;
a sealing body that closes an opening of the outer package;
a positive electrode collector electrically connected to the positive electrode plate;
a negative electrode collector electrically connected to the negative electrode plate; and
nonaqueous electrolyte,
wherein at least one of the collectors between the positive electrode collector and the negative electrode collector includes a first-side base portion disposed near the sealing body, and a first-side lead portion disposed so as to be connected to one end portion of the first-side base portion and to extend towards the power generating element,
wherein the first-side lead portion includes a first-side power generating element joining portion joined to a lateral side of the power generating element, and a first-side inclined portion inclined with respect to a thickness direction of the power generating element from the first-side power generating element joining portion towards an outer side in the thickness direction, and
wherein a sum of a weight of the power generating element and a weight of the nonaqueous electrolyte contained in the power generating element is within a range of 200 g or more to 500 g or less, and
a value of d×cos ? is in a range of 4.6 mm or more to 10.8 mm or less,
where ? is, in the one of the collectors, an angle of inclination of the first-side inclined portion with respect to the thickness direction in a case in which the first-side inclined portion is inclined in the thickness direction from a portion facing a lateral surface of the power generating element in the thickness direction, and d is a length of the first-side inclined portion in a longitudinal direction, and
wherein the one of the collectors is a positive electrode collector, and
wherein the positive electrode collector is formed of aluminum or an aluminum alloy, a Young's Modulus is in a range of 65 G Pa or more to 75 G Pa or less, a geometrical moment of inertia of the first-side lead portion is in a range of 1.4×10?12 m4 or more to 6.2×10?12 m4 or less.

US Pat. No. 10,510,999

CELL COVER FOR SECONDARY BATTERY HAVING BOTTOM SURFACE CONFORMING TO A COOLING PLATE, AND BATTERY MODULE COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A battery module, comprising:a cell cover for a secondary battery, which accommodates at least one secondary battery in an internal space; and
a cooling plate,
wherein the cell cover comprises:
a first side plate and a second side plate facing each other to form opposite side surfaces of the internal space;
a top plate forming a top surface of the internal space and connecting upper edges of the first side plate and the second side plate; and
a first bottom plate extending from a lower edge of the first side plate and a second bottom plate extending from a lower edge of the second side plate to face the first bottom plate, the first bottom plate and the second bottom plate forming a bottom surface of the internal space,
wherein a top surface of the cooling plate comprises a groove, the first bottom plate and the second bottom plate of the cell cover contacting the groove,
wherein the lower edge of the first side plate and the lower edge of the second side plate are in a first plane, and
wherein the first bottom plate and the second bottom plate are inclined downwardly at an angle with respect to the first plane.

US Pat. No. 10,510,984

TRANSPARENT DISPLAY DEVICES AND METHODS OF MANUFACTURING TRANSPARENT DISPLAY DEVICES

Samsung Display Co., Ltd....

1. A transparent organic light emitting display device comprising:a transparent base substrate;
a semiconductor device disposed on the transparent base substrate;
a display structure electrically connected to the semiconductor device; and
a protection layer including an adhesion film containing a blue dye and a protection film disposed on the adhesion film, the protection film containing the blue dye;
wherein the blue dye is distributed in at least one of the adhesion film and the protection film to overlap the entire transparent base substrate, and
wherein the transparent base substrate is a colored polymer substrate having a yellow color.

US Pat. No. 10,510,980

DISPLAY MODULE

Samsung Display Co., Ltd....

1. A display module comprising:a flat window member comprising a display area and a bezel area;
a display panel configured to produce an image, and comprising a display part for producing the image and overlapping the display area, and an edge part overlapping the bezel area and bent from the display part to extend away from the flat window member;
a dummy member on the display panel, and comprising:
a flat part overlapping the display part; and
a bending part overlapping the edge part; and
a protective frame accommodating the display panel and coupled to the flat window member,
wherein the edge part is bent in accordance with a first curvature from the display part, and
wherein the bending part is bent in accordance with the first curvature from the flat part.

US Pat. No. 10,510,979

COMPOSITE TRANSPARENT ELECTRODE, OLED AND METHOD FOR MANUFACTURING THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting diode, comprising a first electrode, a second electrode, and an organic light-emitting functional layer located between the first electrode and the second electrode, wherein the second electrode is a composite transparent electrode, the composite transparent electrode comprising:a metal layer;
a transparent conducting oxide layer, wherein the transparent conducting oxide layer is located on a side of the metal layer away from the organic light-emitting functional layer; and
a transparent cover layer located between the metal layer and the transparent conducting oxide layer,
wherein the metal layer is electrically connected to the transparent conducting oxide layer;
wherein the transparent cover layer has at least one first through-hole, through which the metal layer is electrically connected to the transparent conducting oxide layer;
wherein the at least one first through-hole comprises a material of the transparent conducting oxide layer therein; and
wherein the at least one first through-hole is a bar-shaped structure.

US Pat. No. 10,510,974

EMISSIVE DEVICES FOR DISPLAYS

Intel Corporation, Santa...

1. An emissive laser device comprising:an emission layer between a hole transport layer and an electron transport layer;
a first metasurface mirror adjacent to the electron transport layer; and
a second metasurface mirror adjacent to the hole transport layer, the first and second metasurface mirrors to sustain one or more resonant optical modes.

US Pat. No. 10,510,973

COLOR-STABLE ORGANIC LIGHT EMITTING DIODE STACK

Universal Display Corpora...

1. An organic light emitting device, comprising:an anode, and a hole-transport layer;
a hybrid blue emissive stack that includes a fluorescent blue dopant and a phosphorescent blue dopant, the hybrid blue emissive stack disposed over the hole-transport layer, and the hole-transport layer positioned between the anode and the hybrid blue emissive stack;
a charge-generation layer disposed over the hybrid blue emissive stack;
an emissive stack disposed over the charge-generation layer, the emissive stack includes N emissive layers, and N is an integer of at least 3, wherein at least one middle emissive layer in the emissive stack other than the first and the Nth emissive layers emits light in a different color region than the first and the Nth emissive layers, and the difference between the emission peak of the first emissive layer and the emission peak of the Nth emissive layer in the emissive stack is less than about 10 nm;
wherein at least one of the middle emissive layers has a thickness that is ten times a thickness of the first emissive layer; and
wherein the different color region is represented by a peak emission greater than about 10 nm;
an electron-transport layer disposed over the emissive stack; and
a cathode disposed over the electron-transport layer.

US Pat. No. 10,510,969

DISPLAY DEVICE HAVING A PIXEL INCLUDING SEMICONDUCTOR LAYERS HAVING DIFFERENT SEMICONDUCTOR MATERIALS

Japan Display Inc., Toky...

1. A display device including a plurality of pixels arranged on a surface of a substrate, each of the plurality of pixels comprising:a light-emitting element;
a driving transistor;
a selecting transistor; and
a retention capacitor, wherein
the driving transistor has a bottom-gate structure, and includes a semiconductor layer containing a first semiconductor material,
the selecting transistor includes a semiconductor layer containing a second semiconductor material different from the first semiconductor material,
the retention capacitor has a first electrode and a second electrode,
the first electrode doubles as a gate of the driving transistor,
the second electrode is disposed at a lower layer than the first electrode with an insulating layer interposed therebetween and contains the second semiconductor material, and
the selecting transistor has a gate disposed at the same layer as the gate of the driving transistor.

US Pat. No. 10,510,968

ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

UNIVERSAL DISPLAY CORPORA...

1. A compound having the formula Ir(LA)n(LB)3-n, having the structure:
wherein A1, A2, A6, A7, and A8 are carbon;
wherein A5 is nitrogen;
wherein X is O;
wherein R1, R2, R3, and R4 independently represent mono-, di-, tri-, tetra-substitution, or no substitution;
wherein any adjacent substitutions in R1, R2, R3, and R4 are optionally linked together to form a ring;
wherein R1, R2, R3, and R4 are independently selected from the group consisting of hydrogen, deuterium, alkyl, cycloalkyl, and combinations thereof; and
wherein n is an integer from 1 to 3.

US Pat. No. 10,510,966

ORGANIC LIGHT-EMITTING DEVICE

SAMSUNG ELECTRONICS CO., ...

1. An organic light-emitting device comprising:a first electrode;
a second electrode facing the first electrode; and
an organic layer disposed between the first electrode and the second electrode,
wherein the organic layer comprises an emission layer,
wherein the emission layer comprises a host and a dopant,
wherein the dopant comprises a condensed cyclic compound represented by Formula 1, and
wherein an amount of the dopant is smaller than that of the host:

wherein, in Formula 1, Ar1 is a group represented by Formula 1A, and Ar2 is a group represented by Formula 1B,
in Formula 1A, ring A1 is a group represented by Formula 2A, and ring A2 is a group represented by Formula 2B,
in Formulae 1A, 1B, 2A, and 2B,
X1 is C(R1) or N, X2 is C(R2) or N, X3 is C(R3) or N, X4 is C(R4) or N, X5 is C(R5) or N, X6 is C(R6) or N, X7 is C(R7) or N, and X8 is C(R8) or N,
X11 is selected from S, N[(L11)a11-(R11)b11], Si[(L11)a11-(R11)b11][(L12)a12-(R12)b12], and Ge[(L11)a11-(R11)b11][(L12)a12-(R12)b12],
X21 is C(R21) or N, X22 is C(R22) or N, X23 is C(R23) or N, X24 is C(R24) or N, and X25 is C(R25) or N,
X26 is C(R26), N, or a binding site to Ar1, X27 is C(R27), N, or a binding site to Ar1 X28 is C(R28), N, or a binding site to Ar1, X29 is C(R29), N, or a binding site to Ar1, and X30 is C(R30), N, or a binding site to Ar1,
at least one selected from X21 to X30 is N, and at least one selected from X26 to X30 is a binding site to Ar1,
L11 and L12 are each independently selected from a substituted or unsubstituted C3-C10 cycloalkylene group, a substituted or unsubstituted C1-C10 heterocycloalkylene group, a substituted or unsubstituted C3-C10 cycloalkenylene group, a substituted or unsubstituted C1-C10 heterocycloalkenylene group, a substituted or unsubstituted C6-C60 arylene group, a substituted or unsubstituted C1-C60 heteroarylene group, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group,
a11 and a12 are each independently an integer selected from 0 to 3,
R1 to R12 and R21 to R30 are each independently hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C7-C60 arylalkyl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted C1-C60 heteroaryloxy group, a substituted or unsubstituted C1-C60 heteroarylthio group, a substituted or unsubstituted C2-C60 heteroarylalkyl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —Si(Q1)(Q2)(Q3), —N(Q4)(Q5), and —B(Q6)(Q7),
b11 and b12 are each independently an integer selected from 1 to 3,
the number of a cyano group(s) included in the condensed cyclic compound represented by Formula 1 is 1 or greater, provided that Ar1 comprises at least one cyano group,
* indicates a binding site to a neighboring atom,
at least one substituent selected from the substituted C3-C10 cycloalkylene group, the substituted C1-C10 heterocycloalkylene group, the substituted C3-C10 cycloalkenylene group, the substituted C1-C10 heterocycloalkenylene group, the substituted C6-C60 arylene group, the substituted C1-C60 heteroarylene group, the substituted divalent non-aromatic condensed polycyclic group, the substituted divalent non-aromatic condensed heteropolycyclic group, the substituted C1-C60 alkyl group, the substituted C2-C60 alkenyl group, the substituted C2-C60 alkynyl group, the substituted C1-C60 alkoxy group, the substituted C3-C10 cycloalkyl group, the substituted C1-C10 heterocycloalkyl group, the substituted C3-C10 cycloalkenyl group, the substituted C1-C10 heterocycloalkenyl group, the substituted C6-C60 aryl group, the substituted C6-C60 aryloxy group, the substituted C6-C60 arylthio group, the substituted C7-C60 arylalkyl group, the substituted C1-C60 heteroaryl group, the substituted C1-C60 heteroaryloxy group, the substituted C1-C60 heteroarylthio group, the substituted C2-C60 heteroarylalkyl group, the substituted monovalent non-aromatic condensed polycyclic group, and the substituted monovalent non-aromatic condensed heteropolycyclic group is selected from:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C7-C60 arylalkyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryloxy group, a C1-C60 heteroarylthio group, a C2-C60 heteroarylalkyl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q11)(Q12)(Q13), —N(Q14)(Q15), and —B(Q16)(Q17);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C7-C60 arylalkyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryloxy group, a C1-C60 heteroarylthio group, a C2-C60 heteroarylalkyl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C7-C60 arylalkyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryloxy group, a C1-C60 heteroarylthio group, a C2-C60 heteroarylalkyl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one selected from deuterium, —F, —CI, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C7-C60 arylalkyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryloxy group, a C1-C60 heteroarylthio group, a C2-C60 heteroarylalkyl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q21)(Q22)(Q23), —N(Q24)(Q25), and —B(Q26)(Q27); and
—Si(Q31)(Q32)(Q33), —N(Q34)(Q35), and —B(Q36)(Q37), and
Q1 to Q7, Q11 to Q17, Q21 to Q27, and Q31 to Q37 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C7-C60 arylalkyl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted C1-C60 heteroaryloxy group, a substituted or unsubstituted C1-C60 heteroarylthio group, a substituted or unsubstituted C2-C60 heteroarylalkyl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,510,962

COMPOUND AND ORGANIC ELECTRONIC DEVICE USING THE SAME

SHANGHAI NICHEM FINE CHEM...

14. An organic electronic device, comprising a first electrode, a second electrode, and an organic layer disposed between the first electrode and the second electrode, wherein the organic layer comprises the compound as claimed in claim 1.

US Pat. No. 10,510,958

MASK FRAME, MASK AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A mask frame, comprising:a loop shaped frame body comprising an outer boundary and an inner boundary of the mask frame, the inner boundary defining a space for receiving a mask body;
wherein the mask frame comprises a forced side and a non-forced side, the forced side being subjected to a pulling force of the mask body, the non-forced side being free from the force of the mask body; and
wherein a width between the outer boundary of the forced side of the mask frame and the inner boundary corresponding to the outer boundary decreases gradually in a direction from a middle position on the forced side toward the non-forced side, and
wherein:
at least a section of the forced side is arc-shaped, and in the arc-shaped section, the width between the outer boundary of the forced side and the corresponding inner boundary is set to be proportional to deformation amounts of a hypothetical reference forced side under the same pulling force, wherein the hypothetical reference forced side has a constant width equal to a minimum width between the outer boundary and the corresponding inner boundary of the forced side of the mask, or
the forced side comprises a plurality of sections which have a constant width respectively, and the width between the outer boundary of each of the plurality of sections and the corresponding inner boundary is set to be proportional to deformation amounts at a position of the hypothetical reference forced side corresponding to a middle position of each of the plurality of sections under the same pulling force.

US Pat. No. 10,510,945

MAGNETOELASTICALLY ACTUATED MEMS DEVICE AND METHODS FOR ITS MANUFACTURE

1. An apparatus, comprising:a substrate; and
a microscale cantilever arm supported at a standoff distance from the substrate;
wherein said arm comprises a laminar magnetic actuator configured to bend the arm when subjected to a magnetic field; and wherein:
the laminar magnetic actuator comprises a film of magnetostrictive material;
the laminar magnetic actuator is a magnetic bimorph comprising a structural layer of copper underlying and adjacent to the film of magnetostrictive material;
the copper structural layer has a thickness in the range 0.5-20 ?m; and
the film of magnetostrictive material has a thickness in the range 0.5-5 ?m.

US Pat. No. 10,510,929

LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE

LG INNOTEK CO., LTD., Se...

1. A light emitting device comprising:a light emitting structure including a first conductivity type semiconductor layer, an active layer on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer on the active layer;
a transmissive electrode layer including a metal oxide layer on the second conductivity type semiconductor layer;
an insulating layer on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer;
a first electrode on the first conductivity type semiconductor;
a second electrode on the second conductivity type semiconductor layer, wherein the first electrode includes a first portion and a second portion, and wherein the first portion of the first electrode contacts the first conductivity type semiconductor layer and has an area of 10% to 95% of a top surface of the first electrode.

US Pat. No. 10,510,924

MULTI-HETEROJUNCTION NANOPARTICLES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME

The Board of Trustees of ...

1. A semiconducting nanoparticle comprising:a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and
two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and
where the first semiconductor and the second semiconductor are chemically different from each other, and the first endcaps contact the first end and the second end tangentially.

US Pat. No. 10,510,923

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. A method of manufacturing a display device, comprising:a first transferring step of transferring a plurality of LEDs disposed on a wafer onto a plurality of donors; and
a second transferring step of transferring the plurality of LEDs transferred onto the plurality of donors onto a display panel,
wherein in the second transferring step, an area where one of the plurality of donors overlaps the display panel partially overlaps an area where the other one of the plurality of donors overlaps the display panel,
wherein a plurality of first LEDs among the plurality of LEDs disposed on the wafer and a plurality of second LEDs among the plurality of LEDs disposed on the wafer are disposed in different rows or different columns on the wafer.

US Pat. No. 10,510,917

PORTABLE ELECTRONIC DEVICE, IMAGE-CAPTURING MODULE THEREOF AND CARRIER ASSEMBLY THEREOF

AZUREWAVE TECHNOLOGIES, I...

1. An image-capturing module, comprising:a circuit substrate having a top surface and a bottom surface;
an image-sensing chip electrically connected to the circuit substrate, wherein the image-sensing chip has an image-sensing area;
at least one electronic component disposed on the bottom surface of the circuit substrate and electrically connected to the circuit substrate;
a dispensing package disposed on the bottom surface of the circuit substrate to cover the at least one electronic component;
a lens assembly including a holder structure disposed on the top surface of the circuit substrate and a lens structure being held by the holder structure and corresponding to the image-sensing area; and
a filter element disposed on the image-sensing chip, and the filter element disposed in a through opening formed between the top surface and the bottom surface of the circuit substrate.

US Pat. No. 10,510,916

COMPONENT FOR DETECTING UV RADIATION AND METHOD FOR PRODUCING A COMPONENT

OSRAM OPTO SEMICONDUCTORS...

1. A component for detecting ultraviolet radiation comprising:a semiconductor body comprising a first semiconductor layer of a first charge carrier type, a second semiconductor layer of a second charge carrier type and an intermediate active layer located therebetween,
wherein the semiconductor body is based on AlmGa1-n-mInnN with 0?n?1, 0?m?1 and n+m<1,
wherein the first semiconductor layer is n-doped,
wherein the second semiconductor layer is p-doped,
wherein the active layer is formed with respect to its material composition in such a way that during operation of the component, arriving ultraviolet radiation is absorbed by the active layer for generating charge carrier pairs,
wherein the active layer is relaxed with respect to its lattice constant, and
wherein the first semiconductor layer is strained with respect to its lattice constant.

US Pat. No. 10,510,913

LIGHT REDIRECTING FILM USEFUL WITH SOLAR MODULES

3M INNOVATIVE PROPERTIES ...

1. A light redirecting film article comprising a light redirecting film having a length and a width, the length being longer than the width, wherein the light redirecting film defines an X-Y plane, wherein the length of the light redirecting film defines a longitudinal axis in the X direction, the light redirecting film comprising:a base layer;
an ordered arrangement of a plurality of microstructures projecting from the base layer;wherein each of the microstructures projects from the base layer in a Z direction,wherein the microstructures have an elongated shape that extends in the X-Y plane,wherein the elongated shape of each of the microstructures defines a primary axis for each of the microstructures in the X-Y plane;wherein the primary axis of a majority of the microstructures is oblique with respect to the longitudinal axis;wherein the longitudinal axis and the primary axis of at least one microstructure define a bias angle in the X-Y plane; andwherein the bias angle is within the range of 20 to 70 degrees or the range of ?20 to ?70 degrees; anda reflective layer over the microstructures opposite the base layer.

US Pat. No. 10,510,910

IMAGE SENSOR WITH AN ABSORPTION ENHANCEMENT SEMICONDUCTOR LAYER

Taiwan Semiconductor Manu...

1. An image sensor comprising:a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked, wherein the absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers, and wherein the absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer;
a plurality of protrusions defined by the back-side semiconductor layer; and
a photodetector defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.

US Pat. No. 10,510,908

SOLAR CELL PANEL

LG ELECTRONICS INC., Seo...

1. A solar cell panel comprising:a plurality of solar cells comprising at least a first solar cell and a second solar cell; and
a plurality of leads to connect the first solar cell and the second solar cell,
wherein each of the first solar cell and the second solar cell comprises:
a semiconductor substrate;
a first passivation layer on a front surface of the semiconductor substrate;
a second passivation layer on a back surface of the semiconductor substrate;
a first conductivity type region on the first passivation layer at the front surface of the semiconductor substrate;
a second conductivity type region on the second passivation layer at the back surface of the semiconductor substrate;
a first electrode electrically connected to the first conductivity type region, the first electrode comprising a first metal electrode layer including a plurality of finger lines in a first direction and a plurality of first bus bars in a second direction crossing the first direction; and
a second electrode electrically connected to the second conductivity type region, the second electrode comprising a second metal electrode layer including a plurality of second bus bars in the second direction,
wherein the plurality of leads have a diameter or width of 100 to 500 ?m, and comprise 6 or more leads arranged at one surface side of the first or second solar cell,
wherein each of the plurality of leads comprises a core layer having a circular, oval or round shape and a solder layer coated on the entire outer surface of the core layer,
wherein the plurality of leads are connected to the plurality of first bus bars of the first solar cell and the plurality of second bus bars of the second solar cell by the solder layer, respectively,
wherein the solder layer includes a portion adjacent to the first or second electrode, and
wherein a width of the portion gradually increases toward the first or second electrode.

US Pat. No. 10,510,904

SEMICONDUCTOR DEVICE WITH BACKSIDE N-TYPE LAYER AT ACTIVE REGION/TERMINATION REGION BOUNDARY AND EXTENDING INTO ACTION REGION

Mitsubishi Electric Corpo...

1. A semiconductor device wherein a terminal region is disposed outside an active region, comprising:an n type drift layer having a front surface and a rear surface facing each other;
a p type anode layer formed on the front surface of the n type drift layer in the active region, an end portion of the p type anode layer along a horizontal direction coinciding with an end portion of the of the active region;
an n type buffer layer formed on the rear surface of the n type drift layer;
an n type cathode layer and a p type cathode layer formed side by side on a rear surface of the n type buffer layer;
an n type layer formed on the rear surface of the n type buffer layer in a boundary region between the active region and the terminal region side by side with the n type cathode layer and the p type cathode layer; and
a cathode electrode formed in the active region and forming an ohmic contact with the n type cathode layer and the p type cathode layer, wherein
a region at the front surface directly adjacent to the end portion of the p type anode layer is an n type region,
an extending distance of the n type layer to the active region side with the end portion of the active region as a starting point is represented by WGR1,
WGR1 satisfies 100 ?m?WGR1?500 ?m,
the n type layer is extended to the terminal region side, and
the p type cathode layer is continuously provided in the terminal region and located adjacent to an end portion on the terminal region side of the n type layer.

US Pat. No. 10,510,896

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:forming an insulating structure over a substrate, wherein the substrate has a semiconductor fin separated from the insulating structure;
depositing a high-K dielectric layer over the semiconductor fin and a sidewall of the insulating structure facing the semiconductor fin;
etching a first portion of the high-K dielectric layer that extends substantially along the sidewall of the insulating structure, wherein a second portion of the high-K dielectric layer remains over the semiconductor fin; and
depositing a gate electrode over the second portion of the high-K dielectric layer.

US Pat. No. 10,510,893

METHOD FOR FABRICATING FINFET ISOLATION STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device, the method comprising:forming a stop layer on a semiconductor substrate;
forming a semiconductor fin on the stop layer;
forming two cells adjacent to each other on the semiconductor fin;
forming a gate conductor on a top of the semiconductor fin at a common boundary that is shared by the two cells;
forming a gate spacer peripherally enclosing the gate conductor;
forming an epitaxial layer at each of both sides of the gate conductor;
etching the gate conductor and the semiconductor fin to form a gap extending from the top of the semiconductor fin to the stop layer, thereby dividing the semiconductor fin into two portions of the semiconductor fin, and forming the epitaxial layer at one side of each of the two portions of the semiconductor fin; and
filling the gap with a dielectric filler.

US Pat. No. 10,510,892

FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES

International Business Ma...

1. A semiconductor device, comprising:one or more fins, each fin comprising:
a top channel portion formed from a channel material;
a middle portion, and
a bottom substrate portion formed from a same material as an underlying substrate, each of the top channel portion and the middle portion having a different width than the bottom substrate portion;
an isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins;
an oxide layer formed between the bottom substrate portion of each fin and the isolation layer, wherein a space extending to a depth below the top surface of the middle portion and above a bottom end of the bottom substrate portion exists between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer; and
a gate dielectric, protruding into the space and in contact with the middle portion, formed over the one or more fins and comprising a portion formed from a material different from the oxide layer.

US Pat. No. 10,510,889

P-TYPE STRAINED CHANNEL IN A FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate having an n-doped well feature;
an epitaxial silicon germanium fin formed over the n-doped well feature, the epitaxial silicon germanium fin having a lower part and an upper part, wherein the lower part has a lower germanium content than the upper part;
a channel in the epitaxial silicon germanium fin; and
lightly doped source-drain regions formed from the epitaxial silicon germanium fin, the lightly doped source-drain regions extending into the epitaxial silicon germanium fin, the lightly doped source-drain regions comprising a diffusion region having a dopant concentration decreasing from an interface between epitaxial source/drain regions and the epitaxial silicon germanium fin toward the channel, the lightly doped source-drain regions comprising an upper doped region over the diffusion region, the upper doped region having a uniform dopant concentration.

US Pat. No. 10,510,888

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming an alloy semiconductor material layer comprising a first element and a second element on a semiconductor substrate;
forming a mask on the alloy semiconductor material layer to provide a masked portion and an unmasked portion of the alloy semiconductor material layer; and
irradiating the unmasked portion of the alloy semiconductor material layer not covered by the mask with radiation from a radiation source to transform the alloy semiconductor material layer so that a surface region of the unmasked portion of the alloy semiconductor material layer has a higher concentration of the second element than an internal region of the unmasked portion of the alloy semiconductor material layer, wherein the surface region surrounds the internal region.

US Pat. No. 10,510,881

METHOD OF PRODUCING A SYMMETRIC LDMOS TRANSISTOR

ams AG, Unterpremstaette...

1. A method of producing a symmetric LDMOS transistor, comprising:forming a well of a first type of conductivity in a semiconductor substrate;
forming wells of a second type of conductivity in the well of the first type of conductivity, the wells of the second type of conductivity being arranged at a distance from one another;
performing an implantation of dopants forming a doped region of the second type of conductivity in the well of the first type of conductivity, the doped region of the second type of conductivity being arranged between the wells of the second type of conductivity at a distance from the wells of the second type of conductivity;
applying source/drain contacts to the wells of the second type of conductivity and arranging a gate dielectric and a gate electrode above regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity, the gate electrode being provided with a gap above the doped region of the second type of conductivity;
forming a body contact region between the wells of the second type of conductivity, the body contact region comprising a series of contact islands arranged on a straight line at the same distance from the wells of the second type of conductivity; and
interconnecting separated portions of the doped region using an interconnecting doped region of the second type of conductivity, the interconnecting doped region being disposed between two contact islands of the series of contact islands.

US Pat. No. 10,510,876

QUANTUM DOPING METHOD AND USE IN FABRICATION OF NANOSCALE ELECTRONIC DEVICES

1. A semiconductor device comprisinga substrate formed of a semiconductor material having a crystallographic orientation selected from the group consisting of <100>, <110>, and <111>, the substrate having a surface layer of atoms with a fixed number of unterminated bonds equal to an atomic surface density defined by the selected crystallographic orientation;
a single atomic layer of atoms of a dopant material attached to the surface layer in a self-limiting process that terminates the fixed number of unterminated bonds and creates a layer of dopant atoms of the same atomic surface density and having the same fixed number of unterminated bonds as the substrate surface layer; and
a plurality of N atomic layers of the semiconductor material disposed over the single atomic layer of atoms of dopant material, the value of N selected to create a specific volume dopant density equal to 1/N*(the atomic surface density divided by a known lattice spacing associated with the selected crystallographic orientation).

US Pat. No. 10,510,867

FINFETS AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a fin protruding from a substrate;
a gate structure disposed on sidewalls and a top surface of the fin;
a spacer layer on sidewalls of the gate structure;
a source/drain region on the fin adjacent the gate structure;
an etch stop layer on sidewalls of the spacer layer and on the source/drain region, wherein a first portion of the etch stop layer on the sidewall of the spacer layer has a smaller density than a second portion of the etch stop layer on the source/drain region; and
an interlayer dielectric layer (ILD) over the etch stop layer.

US Pat. No. 10,510,862

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a semiconductor layer;
a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion in a direction along a surface of the semiconductor layer, and a spacer provided between the first portion and the second portion; and
a first insulating layer provided between the semiconductor layer and the gate electrode, the first insulating layer including a first region containing at least one of a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing at least one of a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region,
wherein the first region is positioned between the first portion and the semiconductor layer,
the second region is positioned between the second portion and the semiconductor layer,
the boundary region is positioned between the spacer and the semiconductor layer, and
the boundary region has a chemical composition different from a chemical composition of the spacer.

US Pat. No. 10,510,860

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:forming a gate structure over a channel layer and an isolation insulating layer;
forming a first sidewall spacer layer on a side surface of the gate structure;
forming a sacrificial layer so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer;
forming a space between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer;
after the first sidewall spacer layer is removed, forming an air gap between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure;
removing the sacrificial layer; and
forming an interlayer dielectric layer.

US Pat. No. 10,510,857

THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor comprising:a substrate;
a source electrode on the substrate;
a first insulation pattern on the source electrode;
a drain electrode on the first insulation pattern; and
an active layer with one part on the first insulation pattern;
wherein the drain electrode and the one part of the active layer on the first insulation pattern are in an identical layer; and
wherein the source electrode is sandwiched between the substrate and the first insulation pattern;
wherein an orthographic projection of the first insulation pattern at the substrate is within an orthographic projection of the source electrode at the substrate;
wherein the drain electrode is on a top surface of the first insulation pattern; and the one part of the active layer is on the top surface of the first insulation pattern; wherein the drain electrode and the one part of the active layer on the top surface of the first insulation pattern are in an identical layer; and the top surface of the first insulation pattern is substantially parallel to a top surface of the substrate.

US Pat. No. 10,510,855

TRANSISTOR LAYOUT TO REDUCE KINK EFFECT

Taiwan Semiconductor Manu...

1. An integrated chip, comprising:a substrate having interior surfaces that define a trench within an upper surface of the substrate;
an isolation structure comprising one or more dielectric materials within the trench and having sidewalls that define an opening exposing the upper surface of the substrate;
a source region disposed within the upper surface of the substrate and having a first width extending along a first direction;
a drain region disposed within the upper surface of the substrate and having a second width extending along the first direction; and
a gate structure extending over a region of the upper surface that is between the source region and the drain region, wherein the region of the upper surface has a third width that extends along the first direction and that is larger than the first width and the second width.

US Pat. No. 10,510,848

SUB-FIN SIDEWALL PASSIVATION IN REPLACEMENT CHANNEL FINFETS

Intel Corporation, Santa...

1. An integrated circuit including at least one transistor, the integrated circuit comprising:a substrate;
a semiconductor region including material different from the substrate, the semiconductor region being on a portion of the substrate and under a gate stack, wherein the semiconductor region includes a first portion laterally between portions of the gate stack, and a second portion not laterally between portions of the gate stack;
a first dielectric region and a second dielectric region, the second portion of the semiconductor region being laterally between the first and second dielectric regions, wherein the first and second dielectric regions include a first dielectric material, wherein both a first surface of the first dielectric region facing the gate stack and an opposite second surface of the first dielectric region include the first dielectric material;
a first dielectric layer laterally between the second portion of the semiconductor region and the first dielectric region, and not laterally between the first portion of the semiconductor region and the gate stack; and
a second dielectric layer laterally between the second portion of the semiconductor region and the second dielectric region, and not laterally between the first portion of the semiconductor region and the gate stack,
wherein the first and second dielectric layers include a second dielectric material different from the first dielectric material, and wherein a section of the first dielectric layer is between the first dielectric region and the substrate, the section of the first dielectric layer in direct contact with the first dielectric region.

US Pat. No. 10,510,847

TRANSISTOR WITH SOURCE FIELD PLATES UNDER GATE RUNNER LAYERS

Texas Instruments Incorpo...

1. A device, comprising:a semiconductor substrate having a channel region;
a source contact layer contacting the a surface of the semiconductor substrate;
a gate layer above the channel region;
a source field plate defining an opening for accessing the gate layer; and
a gate runner layer above the source field plate, the gate runner layer accessing the gate layer through the opening.

US Pat. No. 10,510,846

SEMICONDUCTOR DEVICE WITH NEEDLE-SHAPED FIELD PLATE STRUCTURES IN A TRANSISTOR CELL REGION AND IN AN INNER TERMINATION REGION

Infineon Technologies Aus...

1. A semiconductor device, comprising:a semiconductor portion comprising a first surface, a second surface opposite the first surface and a drift structure of a first conductivity type disposed between the first and second surfaces;
a transistor cell region comprising needle-shaped first field plate structures extending from the first surface into the semiconductor portion, and body regions of a second conductivity type opposite the first conductivity type surrounding the first field plate structures in a horizontal plane; and
an inner termination region surrounding the transistor cell region and comprising needle-shaped second field plate structures extending from the first surface into the semiconductor portion, the inner termination region being devoid of regions of the second conductivity type that are spaced from the second surface of the semiconductor portion.

US Pat. No. 10,510,841

METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE

SHINDENGEN ELECTRIC MANUF...

1. A method of manufacturing a silicon carbide semiconductor device comprising:an epitaxial layer of a first conductive type;
a first semiconductor region of a first conductive type formed on a surface of the epitaxial layer of the first conductive type, and having higher impurity concentration than that of the epitaxial layer of the first conductive type;
a body region of a second conductive type formed at a position deeper than that of the first semiconductor region of the first conductive type;
a channel region of a second conductive type formed such that
the channel region of the second conductive type
penetrates the first semiconductor region of the first conductive type from a surface of the epitaxial layer of the first conductive type,
reaches the body region of the second conductive type, and
defines
a first part of the first semiconductor region of the first conductive type formed entirely on the body region of the second conductive type and
a second part of the first semiconductor region of the first conductive type formed partially on the body region of the second conductive type, wherein
the first part of the first semiconductor region of the first conductive type and the channel region of the second conductive type define a first boundary surface, and
the second part of the first semiconductor region of the first conductive type and the channel region of the second conductive type define a second boundary surface,
the channel region of the second conductive type having lower impurity concentration than that of the body region of the second conductive type;
a second semiconductor region of a first conductive type formed toward the body region of the second conductive type from the surface of the epitaxial layer of the first conductive type, the second semiconductor region of the first conductive type having higher impurity concentration than that of the first semiconductor region of the first conductive type;
a body contact region of a second conductive type formed such that the body contact region of the second conductive type penetrates the first semiconductor region of the first conductive type from the surface of the epitaxial layer of the first conductive type and reaches the body region of the second conductive type, the body contact region of the second conductive type having higher impurity concentration than that of the body region of the second conductive type; and
a gate electrode formed on at least the channel region of the second conductive type with a gate insulating film interposed therebetween, wherein
the channel region of the second conductive type and the second semiconductor region of the first conductive type are formed at a planar position where the first part of the first semiconductor region of the first conductive type
remains between the channel region of the second conductive type and the second semiconductor region of the first conductive type, and
separates the channel region of the second conductive type from the second semiconductor region of the first conductive type, and
the second boundary surface is positioned on the body region of the second conductive type as viewed in a plan view, wherein the method comprising the steps of:
preparing a silicon carbide semiconductor substrate provided with the epitaxial layer of the first conductive type;
forming the body region of the second conductive type on the surface of the epitaxial layer of the first conductive type such that a depth where a maximum concentration of an impurity of a second conductive type is deeper than a depth position of a bottom surface of the channel region;
forming the first semiconductor region of the first conductive type on a surface of the body region of the second conductive type;
forming the channel region of the second conductive type, the second semiconductor region of the first conductive type and a body contact region of a second conductive type in the first semiconductor region of the first conductive type, the body contact region of the second conductive type penetrating the first semiconductor region of the first conductive type from the surface of the epitaxial layer of the first conductive type and reaches the body region of the second conductive type; and
forming the gate electrode on at least the channel region of the second conductive type with a gate insulating film interposed therebetween, wherein
in the step of forming the channel region of the second conductive type, the second semiconductor region of the first conductive type and the body contact region of the second conductive type, the channel region of the second conductive type, the second semiconductor region of the first conductive type and the body contact region of the second conductive type are formed at a planar position where the first part of the first semiconductor region of the first conductive type remains between the channel region of the second conductive type and the second semiconductor region of the first conductive type, and
the second boundary surface is positioned on the body region of the second conductive type as viewed in a plan view.

US Pat. No. 10,510,838

HIGH SURFACE DOPANT CONCENTRATION FORMATION PROCESSES AND STRUCTURES FORMED THEREBY

Taiwan Semiconductor Manu...

1. A method comprising:forming a source/drain region in an active area on a substrate, the source/drain region having a first dopant concentration;
forming a dielectric layer over the active area and the source/drain region;
after forming the dielectric layer, replacing a dummy gate stack in the dielectric layer with a metal gate stack;
depositing a second dielectric layer over the dielectric layer and the metal gate stack;
forming an opening through the dielectric layer and the second dielectric layer, the opening exposing at least a portion of an upper surface of the source/drain region;
forming a surface dopant region in the source/drain region at the upper surface of the source/drain region, forming the surface dopant region comprising plasma doping the source/drain region through the opening in the dielectric layer and the second dielectric layer, the surface dopant region comprising a second dopant concentration proximate the upper surface of the source/drain region; and
forming a conductive feature in the opening to the surface dopant region in the source/drain region.

US Pat. No. 10,510,830

N-TYPE POLYSILICON CRYSTAL, MANUFACTURING METHOD THEREOF, AND N-TYPE POLYSILICON WAFER

Sino-American Silicon Pro...

1. An N-type polysilicon crystal, wherein:a resistivity of the N-type polysilicon crystal has a slope when graphed, of which a horizontal axis is referred to as a solidification fraction and a vertical axis is referred to as the resistivity presented by a unit of Ohm-cm (?·cm), and the slope of resistivity is between 0 to ?1.8 at a first solidification fraction value between 0.25 to 0.8; and
a defect area percentage of the N-type polysilicon crystal has a slope when graphed, of which the horizontal axis is referred to as the solidification fraction and the vertical axis is referred to as the defect area percentage (%), and the slope of defect area percentage is less than 2.5 at a second solidification fraction value between 0.4 to 0.8.

US Pat. No. 10,510,820

DISPLAY DEVICE AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A display device comprising:a pixel unit in which a plurality of pixel circuits each of which includes a light emitting element and a driving circuit configured to drive the light emitting element are arranged in a matrix form,
wherein, in a diffusion layer in which transistors included in the driving circuits of the pixel circuits are formed, an electricity supply region that is an active area for supplying an electric potential to a well is provided between mutually adjacent ones of the pixel circuits.

US Pat. No. 10,510,814

OLED DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An OLED display panel, comprising:a substrate;
a plurality of OLED light-emitting devices arranged on a side of the substrate;
a signal routing and a control device correspondingly connected with the OLED light-emitting devices;
an image sensor arranged on the other side or the same side of the substrate; and
a light shielding layer arranged between the image sensor and a film layer where the OLED light-emitting devices are located, the light shielding layer comprising at least one pinhole imaging region;
wherein an orthographic projection position of the pinhole imaging region on the substrate is arranged at a gap position between the OLED light-emitting devices, and is staggered from orthographic projection positions of light shielding parts in the signal routing and the control device on the substrate;
the image sensor is configured to acquire an image formed after an object above the OLED display panel passes through the pinhole imaging region;
the signal routing comprises a data line arranged between the film layer where the OLED light-emitting devices are located and the substrate;
the light shielding layer is arranged between the film layer where the OLED light-emitting devices are located and a film layer where the data line is located; and
the light shielding layer further comprises: a connecting through hole configured to connect a drain electrode in the film layer where the data line is located, or a pattern comprising the drain electrode with an anode in the OLED light-emitting device.

US Pat. No. 10,510,811

COLOR FILTER AND WHITE ORGANIC LIGHT-EMITTING DIODE DISPLAY APPARATUS

SHENZHEN CHINA STAR OPTOE...

10. A WOLED display apparatus, comprising a display panel and a color filter disposed on the display panel;wherein the display panel is a WOLED display pane;
wherein the color filter comprises a red pixel section, a green pixel section, a blue pixel section and a white pixel section, a red photoresist is disposed in the red pixel section, a green photoresist is disposed in the green pixel section, and a blue photoresist is disposed in the blue pixel section;
wherein the white pixel section includes a first sub-section, and a red photoresist, a green photoresist or a blue photoresist is disposed in the first sub-section; and
wherein the white pixel section further includes a second sub-section, there is a red photoresists, a green photoresist or a blue photoresist disposed in the second sub-section, and a color of the photoresist in the second sub-section is different from that of the photoresist in the first sub-section.

US Pat. No. 10,510,806

LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:an EL layer between an anode and a cathode,
wherein the EL layer has a structure where a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer are stacked in this order from the anode side,
wherein light emitted from the first light-emitting layer and light emitted from the third light-emitting layer have the same color,
wherein a wavelength of each of the light emitted from the first light-emitting layer and the light emitted from the third light-emitting layer is longer than a wavelength of light emitted from the second light-emitting layer, and
wherein emission spectra of the light emitted from the first light-emitting layer and the light emitted from the third light-emitting layer each have a half width of greater than or equal to 5 nm and less than or equal to 120 nm and a peak wavelength at greater than or equal to 620 nm and less than or equal to 680 nm.

US Pat. No. 10,510,802

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first conductive wiring;
at least one first dielectric layer over the first conductive wiring;
at least one second dielectric layer comprises a first layer and a second layer over the at least one first dielectric layer;
a second conductive wiring over the at least one second dielectric layer;
a conductive via electrically connected to the first conductive wiring and the second conductive wiring,
wherein a dielectric constant of the at least one second dielectric layer is higher than a dielectric constant of the at least one first dielectric layer, the dielectric constant of the at least one first dielectric layer is within a range of about 3.5 to about 4.5, the dielectric constant of the at least one second dielectric layer is within a range of about 4 to about 7; and
a memory device comprising:
a first conductive structure under the at least one first dielectric layer;
a second conductive structure over the at least one second dielectric layer; and
a memory cell between the first conductive structure and the second conductive structure, and through the at least one first dielectric layer and the at least one second dielectric layer, wherein the memory cell comprises:
a bottom electrode via over the first conductive structure;
a bottom electrode over and electrically connected to the bottom electrode via;
a top electrode over the bottom electrode
a top electrode via over the top electrode; and
a magnetic tunnel junction (MTJ) between the top electrode and the bottom electrode,
wherein the at least one first dielectric layer is below the bottom electrode and surrounds edges of the bottom electrode via,
wherein the second layer of the at least one second dielectric layer surrounds the entire sidewalls of the top electrode via,
wherein the first layer of the at least one second dielectric layer surrounds sidewalls of the bottom electrode, sidewalls of the MTJ and sidewalls of the top electrode,
wherein both the first layer and the second layer of the at least one second dielectric layer surround the sidewalls of the conductive via.

US Pat. No. 10,510,795

SEMICONDUCTOR IMAGE SENSOR

Taiwan Semiconductor Manu...

1. An image sensor integrated chip, comprising:an image sensing element arranged within a substrate;
a first dielectric disposed in one or more trenches within a first side of the substrate, wherein the one or more trenches laterally surround the image sensing element; and
wherein the substrate includes a recessed portion arranged along the first side of the substrate and defined by second sidewalls of the substrate directly over the image sensing element, the second sidewalls of the substrate are angled to meet at a point disposed along a horizontal plane that intersects the first dielectric within the one or more trenches.

US Pat. No. 10,510,794

SEMICONDUCTOR IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

1. A back side illumination (BSI) image sensor comprising:a substrate comprising a front side and a back side opposite to the front side;
a pixel sensor in the substrate;
a logic device disposed over the front side of the substrate;
an isolation structure surrounding the pixel sensor in the substrate;
a dielectric layer over the pixel sensor on the front side of the substrate; and
a plurality of conductive structures disposed in the dielectric layer and arranged to align with the isolation structure,
wherein at least one of the conductive structures is entirely overlapped by the isolation structure in a direction normal to the substrate, and the at least one of the conductive structures is separated from the logic device,
wherein the isolation structure further comprises an insulating material portion and a conductive coating, and sidewalls of the insulating material portion are lined with the conductive coating.

US Pat. No. 10,510,768

3D MEMORY DEVICE WITH U-SHAPED MEMORY CELL STRINGS

Trinandable S.r.l., Mila...

1. A 3D memory device comprising:a substrate;
a plurality of U-shaped memory cells strings each including a buried string portion formed in the substrate, a first, bit line-side string portion or pillar and a second, source line-side string portion or pillar, wherein the buried string portion is connected to a first end of the first string portion and to a first end of the second string portion, each one of the U-shaped memory cells strings including a stack of memory cells along the first string portion and a stack of memory cells along the second string portion;
bit line selectors arranged at a second end of the first string portions opposed to the first end, for the selective connection to respective bit lines;
source line selectors arranged at a second end of the second string portions opposed to the first end, for the selective connection to respective source lines;
first groups of first string portions, wherein in each first group the first string portions are aligned along a first direction to form a respective first row of first string portions;
second groups of second string portions, wherein in each second group the second string portions are aligned along the first direction to form a respective second row of second string portions;
wherein the first rows of first string portions and the second rows of second string portions follow one another, alternately or in pairs, along a second direction transversal to the first direction;
wherein first rows of first string portions and/or second rows of second string portions consecutive along said second direction are spaced apart from each other a respective distance;
the 3D memory device comprising a respective slit between a first row of first string portions and a second row of second string portions being consecutive along said second direction and spaced apart a distance equal to or less than a minimum distance allowed by a resolution of the manufacturing technology, wherein said slit extends in a third direction, orthogonal to said first and second directions, from said second end down to the substrate, said slit interrupting layers forming the bit line selectors and the source line selectors and control gates of the memory cells of the memory cells stacks formed along the first and second string portions; and
wherein said slit has dimension, along said second direction, less than, equal to or higher than said minimum distance, and walls of the slit lying in planes parallel to said first and third directions delimit the first and second string portions.

US Pat. No. 10,510,732

POP DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A package-on-package (PoP) device, comprising:a first package structure, comprising:
a die;
a through integrated fan-out via (TIV) aside the die;
an encapsulant encapsulating sidewalls of the die and sidewalls of the TIV; and
a film over the TIV and the encapsulant, and aside the die; and
a second package structure, connected to the first package structure through a connector,
wherein the connector penetrates through the film to electrically connect to the TIV,
wherein the film is surrounded by the encapsulant, and a top surface of the film is coplanar with a top surface of the encapsulant.

US Pat. No. 10,510,716

PACKAGED SEMICONDUCTOR DEVICES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

15. A device comprising:a friction-reducing mask coating;
a first molding compound over the friction-reducing mask coating;
an integrated circuit die extending into the first molding compound;
an adhesive film between the integrated circuit die and the friction-reducing mask coating;
an interconnect structure over the integrated circuit die and the first molding compound;
a second molding compound over the interconnect structure; and
a heat spreader abutting the friction-reducing mask coating, the friction-reducing mask coating being interposed between the heat spreader and the integrated circuit die.

US Pat. No. 10,510,715

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

16. A semiconductor structure, comprising:a first die including a first edge, a first corner over the first edge and a second corner opposite to the first corner;
a second die disposed over the first die and including a second edge, a third corner over the second edge and a fourth corner opposite to the third corner; and
a dielectric material surrounding the first die and the second die,wherein the first corner is vertically aligned with the third corner, the fourth corner protrudes laterally away from the first die, the second die is rotated about the first corner or about the third corner in relation to the first die from a top view, and the first die and the second die have different shapes or different dimensions.

US Pat. No. 10,510,712

METHODS FOR CONTROLLING WARPAGE IN PACKAGING

Taiwan Semiconductor Manu...

1. A method comprising:placing a plurality of dummy dies in a peripheral region of a carrier, the peripheral region of the carrier being free of device dies;
placing a plurality of device dies in a central region of the carrier, the central region being surrounded by the peripheral region and being free of dummy dies;
molding the plurality of dummy dies and the plurality of device dies in a molding composite to form a composite wafer;
forming electrical connections to respective device dies; and
singulating the composite wafer into a plurality of packages, wherein each of the plurality of packages includes two or more device dies.

US Pat. No. 10,510,700

SEMICONDUCTOR DEVICE

Rohm Co., Ltd., Kyoto (J...

1. A semiconductor device comprising:a semiconductor chip including:
an electrode pad portion on a face of a substrate;
a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;
a barrier metal layer on the electrode pad portion;
a second protection layer covering a region on the first protection layer and a region on the electrode par portion; and
a plurality of bump electrodes on the barrier metal layer;
a circuit board on which the semiconductor chip is mounted, the circuit board having, formed on a first face thereof facing the semiconductor chip, a connection pad portion connected to the bump electrodes;
a plurality of electrode terminals formed on a second face of the circuit board facing away from the semiconductor chip, the electrode terminals being electrically connected to the connection pad portion; and
a resin member filling a gap between the semiconductor chip and the circuit board,
wherein the barrier metal layer has a circumferential end part thereof formed inward of the first opening in the first protection layer as seen in a plan view,
wherein the electrode pad portion is rectangular as seen in a plan view;
wherein
a peripheral part of the barrier metal layer lies on the second protection layer, and
an upper surface and a lower surface of the barrier metal layer have a curved shape extending along the second protection layer so that a center point of a curvature of the curved shape as seen in a sectional view is located on a substrate side of the curved shape, and
wherein
the second protection layer is formed of polyimide,
the second protection layer has a second opening through which the top face of the electrode pad portion is exposed and which has an opening width smaller than the first opening,
a thickness of the second protection layer as seen in a sectional view increases gradually from a rim part of the second opening to the peripheral part of the barrier metal layer,
wherein
the bump electrodes are arrayed on a third face of the semiconductor chip facing the circuit board,
the electrode terminals are arrayed on the second face of the circuit board, and
an interval between adjacent ones of the electrode terminals on the second face is larger than an interval between adjacent ones of the bump electrodes on the third face, and
wherein the resin member covers the third face of the semiconductor chip and a part of a side face of the semiconductor chip neighboring the third face.

US Pat. No. 10,510,687

PACKAGING DEVICES AND METHODS FOR SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a semiconductor device bonded to a surface of a packaging substrate, wherein the semiconductor device comprises:
an interposer;
a first die bonded to a surface of the interposer;
a second die bonded to the surface of the interposer; and
a first stress isolation structure (SIS) attached to the surface of the interposer, the first SIS being interposed between the first die and the second die;
a second SIS bonded to the surface of the packaging substrate; and
a cover coupled to the packaging substrate, wherein the cover and the packaging substrate define an enclosed space, and wherein the semiconductor device and the second SIS are disposed in the enclosed space.

US Pat. No. 10,510,685

DISHING PREVENTION COLUMNS FOR BIPOLAR JUNCTION TRANSISTORS

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) comprising:a first IC region comprising,
an emitter region disposed within a semiconductor substrate;
a ring-shaped base region disposed within the semiconductor substrate and laterally surrounding the emitter region;
a ring-shaped collector region disposed within the semiconductor substrate and laterally surrounding the ring-shaped base region;
a pre-metal dielectric layer disposed over an upper surface of the semiconductor substrate, and separating the upper surface of the semiconductor substrate from a lowermost metal interconnect layer; and
a plurality of dishing prevention columns arranged over the emitter region and within the pre-metal dielectric layer, wherein the plurality of dishing prevention columns each comprise a dummy gate that is conductive and electrically floating; a second IC region comprising,
a semiconductor device having a pair of source/drain regions disposed within the semiconductor substrate, wherein the source/drain regions are spaced apart; and
a gate stack disposed over the semiconductor substrate and arranged between the source/drain regions, wherein the gate stack comprises a first gate oxide layer separating a gate electrode from the semiconductor substrate, and wherein a sidewall spacer is disposed on sidewalls of the gate stack and sidewalls of each of the dishing prevention columns of the plurality of dishing prevention columns.

US Pat. No. 10,510,617

CMOS VFET CONTACTS WITH TRENCH SOLID AND LIQUID PHASE EPITAXY

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming an n-type field effect transistor (NFET) on a substrate, the NFET comprising a p type semiconductor fin vertically extending from an n-type bottom source or drain region disposed on the substrate;
forming a p-type field effect transistor (PFET) on the substrate, the PFET comprising an n-type semiconductor fin vertically extending from a p-type bottom source or drain region disposed on the substrate;
forming the NFET comprises forming a first gate around a channel region of the p-type semiconductor fin; and
forming the PFET comprises forming a second gate around a channel region of the n-type semiconductor fin;
wherein the first gate and the second gate each comprises a dipole layer;
wherein the NFET and PFET each comprises a threshold voltage of about 150 mV to about 250 mV;
wherein a difference between the threshold voltages of the NFET and PFET is less than about 50 mV;
forming a top spacer on the first gate adjacent to sidewalls of the p-type semiconductor fin.

US Pat. No. 10,510,606

PROTECTED CHIP-SCALE PACKAGE (CSP) PAD STRUCTURE

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) package comprising:an IC die comprising a circuit, a first pad, a second pad, and a passivation layer, wherein the passivation layer covers the second pad and defines an opening overlying the first pad, wherein the first pad is electrically floating and has a top surface that is damaged, wherein the second pad is electrically coupled to the circuit and has a top surface substantially free of damage, and wherein the first pad, the second pad, and the passivation layer partially define a common sidewall of the IC die; and
an external link extending from a bottom of the IC die, along the common sidewall, to lateral contact with the second pad.

US Pat. No. 10,510,593

CONTACT OPENINGS AND METHODS FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:performing a first implantation on a portion of a first layer to form a first implanted region, wherein the first implanted region comprises:
a first portion overlapping a portion of a first gate stack;
a second portion overlapping a portion of a second gate stack; and
a third portion connecting the first portion of the first implanted region to the second portion of the first implanted region;
removing un-implanted portions of the first layer, wherein the first implanted region remains after the removing;
performing a first etching on a second layer underlying the first layer, wherein the first implanted region is used as a portion of a first etching mask in the first etching; and
removing the first implanted region.

US Pat. No. 10,510,583

METHOD OF MANUFACTURING SILICON GERMANIUM-ON-INSULATOR

GlobalWafers Co., Ltd., ...

1. A multilayer structure comprising:a silicon-on-insulator substrate comprising (i) a single crystal semiconductor handle layer comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle layer and the other of which is a back surface of the single crystal semiconductor handle layer, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle layer, a central plane between and parallel to the front surface and the back surface of the single crystal semiconductor handle layer, a central axis perpendicular to the central plane, and a bulk region between the front and back surfaces of the single crystal semiconductor handle layer, (ii) a dielectric layer in interfacial contact with the front surface of the single crystal semiconductor handle layer, and (ii) a silicon layer in interfacial contact with the dielectric layer, wherein the silicon layer has a thickness between about 0.5 nanometer and about 4 nanometers, as measured along the central axis, and further wherein the silicon layer comprises a hydride-terminated surface;
a first silicon germanium layer in interfacial contact with the hydride-terminated surface of the silicon layer, wherein the first silicon germanium comprises silicon and germanium and has a formula of SixGe1?x, wherein x is between about 0.2 and about 0.8, molar ratio; and
a second silicon germanium layer in interfacial contact with the first silicon germanium layer, wherein the second silicon germanium layer comprises silicon and germanium and has a formula SiyGe1?y, wherein y is between about 0.3 and about 0.9, molar ratio.

US Pat. No. 10,510,572

SEMICONDUCTOR PROCESSING STATION

Taiwan Semiconductor Manu...

1. A semiconductor processing station, comprising:a platform comprising an intake/outtake port and a plurality of processing modules;
a load port comprising:
a load chamber communicating with the intake/outtake port and having a load opening at its top end for receiving a transport carrier within the load chamber;
a movable cover disposed at the load opening and configured to seal the load opening; and
a carrier transfer module configured to transfer the transport carrier to the intake/outtake port; and
a carrier transport track having a bottom side configured to open the load chamber.

US Pat. No. 10,510,532

METHOD FOR MANUFACTURING GALLIUM NITRIDE SUBSTRATE USING THE MULTI ION IMPLANTATION

Industry-University Coope...

1. A method of fabricating a gallium nitride substrate, the method comprising:forming a bonding oxide film on a first gallium nitride, said first gallium nitride substrate having a bow;
performing a first ion implantation at least once by irradiating ions at an acceleration voltage of 10 keV to 200 keV with about 7 degrees slope from a perpendicular axis with regard to a surface of the first gallium nitride substrate, on which the bonding oxide film is formed, to form a damaged layer, thereby releasing the bow of the first gallium nitride;
performing a second ion implantation by irradiating ions at about 7 degrees slope from a perpendicular axis with regard to the surface of the first gallium nitride, on which the bonding oxide film is formed, to form a blister layer;
bonding the bonding oxide film of the first gallium nitride to a temporary substrate;
separating the first gallium nitride using the blister layer to form a seed layer; and
allowing growth of a second gallium nitride on the seed layer to form bulk gallium nitride,
wherein the thickness of the damaged layer is 200-500 nm and ?bow of the first gallium nitride is a 20-60 ?m, wherein said ?bow being a bow difference between an initial first gallium nitride and a bowing-released first gallium nitride after the first ion implantation.

US Pat. No. 10,510,518

METHODS OF DRY STRIPPING BORON-CARBON FILMS

APPLIED MATERIALS, INC., ...

1. A method for stripping a film from a substrate, comprising:positioning a substrate having a boron-carbon film thereon in a chamber;
generating a water vapor in the chamber via in situ steam generation;
generating a water vapor plasma from at least the water vapor and an additional gas to form oxygen ions or radicals and hydrogen ions or radicals in the chamber,
wherein the additional gas comprises a fluorine-containing gas or a chlorine-containing gas; and
removing the boron-carbon film from the substrate by exposing the film to the oxygen ions or radicals and the hydrogen ions or radicals, wherein a flow rate of the additional gas into the chamber is reduced as a thickness of the boron-carbon film is reduced.

US Pat. No. 10,510,497

REMOVABLE ELECTRIC CURRENT SWITCHING ELEMENT AND ELECTRICAL SWITCHGEAR FOR SWITCHING AN ELECTRIC CURRENT COMPRISING SUCH A REMOVABLE SWITCHING ELEMENT

Schneider Electric Indust...

1. A removable electric current switching element, comprising:a housing provided with a first bottom plate and a second bottom plate which are opposite one another;
fixed electrical contacts, which are rigidly connected to the first bottom plate;
electrically mobile contacts movable with respect to the fixed electrical contacts, said mobile contacts being borne by a movable contact holder movable in translation with respect to the second bottom plate;
the housing comprising insulating walls which extend around the electrically mobile contacts from the second bottom plate and along a direction perpendicular to the second bottom plate;
wherein the housing further includes protection walls which at least partially cover inner faces of the insulating walls, said protection walls being formed as a single piece with the second bottom plate, and
wherein the protection walls include folded-over edges which surround the ends of the insulating walls along the direction perpendicular to the second bottom plate such that the protection wall at least partially covers the inner faces of the insulating walls and covers a portion of outer faces of the insulating walls.

US Pat. No. 10,510,496

MULTILAYER CERAMIC CAPACITOR AND METHOD FOR MAKING MULTILAYER CERAMIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A method for making a multilayer ceramic capacitor, the method comprising:a step of applying a conductive paste containing Cu powder to a first surface of a multilayer body that includes a plurality of ceramic layers and a plurality of inner conductor layers arranged in a stacking direction, the inner conductor layers being exposed at the first surface; and
a step of baking the conductive paste on the first surface; wherein
the Cu powder has an average particle diameter of about 0.5 ?m or more and about 2.0 ?m or less; and
in the step of baking the conductive paste, water is added to a baking atmosphere while a peak temperature is maintained.

US Pat. No. 10,510,492

MULTILAYER CERAMIC CAPACITOR WITH LOW ACOUSTIC NOISE

APPLE INC., Cupertino, C...

1. A system comprising a capacitor device coupled to electrical circuitry, wherein the capacitor device comprises:a first ceramic sheet;
a second ceramic sheet;
a rigid dielectric disposed between the first ceramic sheet and the second ceramic sheet;
a main capacitor that comprises a first electrode disposed in the first ceramic sheet, a second electrode disposed in the second ceramic sheet, and a first portion of the rigid dielectric, wherein the main capacitor is configured to receive a first electric signal, and wherein the first electrode is coupled to a first termination of the capacitor device and the second electrode is coupled to a second termination of the capacitor device; and
a vise capacitor that comprises a third electrode disposed in the first ceramic sheet, the second electrode, and a second portion of the rigid dielectric, wherein the third electrode is coupled to a third termination of the capacitor device and the vise capacitor is configured to receive a second electrical signal that decreases a deformation of the rigid dielectric caused by the first electric signal; and
wherein the electrical circuitry is configured to provide the first electrical signal to the main capacitor via the first terminal and the second terminal, and the second electrical signal to the vise capacitor via the second terminal and the third terminal, and wherein the second electrical signal is based on the first electrical signal.

US Pat. No. 10,510,483

PRODUCTION METHOD FOR R-T-B SINTERED MAGNET

HITACHI METALS, LTD., To...

1. A method for producing a sintered R-T-B based magnet, comprising:a step of providing a sintered R-T-B based magnet, where R is one or more rare-earth elements, T is one or more transition metal elements, and B is boron or is boron and carbon;
a step of applying onto a surface of the sintered R-T-B based magnet a layer of an RLM alloy powder (where RL is Nd and/or Pr; M is one or more elements selected from the group consisting of Cu, Fe, Ga, Co, Ni and Al), the layer of the RLM powder being at least one particle thick or greater, and then applying a layer of an RH compound powder (where RH is Dy and/or Tb; and an RH compound of the RH compound powder is at least one selected from the group consisting of an RH fluoride, an RH oxide, and an RH oxyfluoride) to the layer of the RLM powder; and
a step of performing a heat treatment at a sintering temperature of the sintered R-T-B based magnet or lower, wherein
the RLM alloy powder contains RL in an amount of 50 at % or more, and a melting point of the RLM alloy powder is equal to or less than a temperature of the heat treatment; and
the heat treatment is performed while the RLM alloy powder and the RH compound powder are present on the surface of the sintered R-T-B based magnet at a mass ratio of RLM alloy powder: RH compound powder=9.6:0.4 to 5:5.

US Pat. No. 10,510,482

PRIMARY SIDED-ARRANGEMENT OF PRIMARY WINDING STRUCTURES, A METHOD OF MANUFACTURING THE PRIMARY-SIDED ARRANGEMENT, A SYSTEM FOR INDUCTIVE POWER TRANSFER AND A METHOD FOR INDUCTIVELY SUPPLYING POWER TO A VEHICLE

Bombardier Primove GmbH, ...

1. A primary-sided arrangement of primary winding structures of a system for inductive power transfer, comprising:at least three phase lines; and
at least one winding structure per phase line;
wherein each winding structure comprises at least one subwinding structure;
wherein the winding structures extend along a longitudinal axis of the primary-sided arrangement;
wherein:
a pitch between corresponding subwinding structures of the winding structures varies along the longitudinal axis;
a length of subwinding structures of the winding structures varies along the longitudinal axis; or
a pitch between corresponding subwinding structures of the winding structures varies along the longitudinal axis and a length of subwinding structures of the winding structures varies along the longitudinal axis.

US Pat. No. 10,510,473

SWITCHGEAR

MITSUBISHI ELECTRIC CORPO...

1. A switchgear comprising:a closing coil that drives a movable element to the close contact side of said switchgear in an electromagnetic operating device;
a closing capacitor that supplies electrical energy to said closing coil;
a closing control section which is connected between said closing coil and said closing capacitor, and performs control of charging said closing capacitor and of energizing said closing coil;
an opening coil that drives said movable element to the open contact side of said switchgear in said electromagnetic operating device;
an opening capacitor that supplies electrical energy to said opening coil;
an opening control section which is connected between said opening coil and said opening capacitor, and performs control of charging said opening capacitor and of energizing said opening coil;
a first interlock circuit that energizes said opening control section;
a second opening coil that drives said movable element to the open contact side of said switchgear in said electromagnetic operating device;
a second opening capacitor that supplies electrical energy to said second opening coil;
a second opening control section which is connected between said second opening coil and said second opening capacitor, and performs control of charging said second opening capacitor and of energizing said second opening coil; and
a second interlock circuit that energizes said second opening control section,
wherein either said opening coil or said second opening coil is enabled to drive said movable element to the open contact side of said switchgear, and
wherein reception, by said closing control section, of a command to activate the closing coil is blocked on the basis of a signal showing that said second opening control section is energizing said second opening coil.

US Pat. No. 10,510,468

LAN CABLE

Hitachi Metals, Ltd., To...

1. A LAN cable comprising:a sheath;
an electrical wire accommodated in the sheath and comprising a conductor and an insulating body covering the conductor; and
an intermediate layer having a mass reduction rate at 500° C. of less than or equal to 10% by mass and a mass reduction rate at 600° C. of less than or equal to 50% by mass, and located between the sheath and the electrical wire,
wherein the insulating body comprises polyethylene having a dielectric constant of smaller than or equal to 2.5,
wherein the sheath comprises a polyolefin-based polymer and a flame retardant,
wherein a content of the flame retardant in the sheath is greater than or equal to 150 parts by mass with respect to 100 parts by mass of the polyolefin-based polymer,
wherein the intermediate layer comprises polyimide, and
wherein the electrical wire is arranged at a center of the LAN cable and is coated with an aluminum laminate PET tape, a copper braid, the intermediate layer, and the sheath in this order radially outward.

US Pat. No. 10,510,466

ELECTROMAGNETIC AND ANTI-BALLISTIC SHIELDED CABLE

Marmon Utility LLC, Milf...

1. A cable comprising:a. one or more conductors surrounded by an inner synthetic strength member, wherein the one or more conductors and the inner synthetic strength member define a plurality of interstitial spaces filled with an extended polymer compound and located between the one or more conductors;
b. a continuous metallic sheath surrounding the inner synthetic strength member and the one or more conductors, wherein the extended polymer compound provides energy absorbing homogeneous foamed layers of various polymers to the cable; and
c. an outer synthetic strength layer surrounding the metallic sheath, the inner synthetic strength member and the outer synthetic strength layer made of an anti-ballistic material, wherein the cable with the layering of the continuous metallic sheath, the energy absorbing inner synthetic strength member and outer synthetic strength layer, and the energy absorbing homogeneous foamed layers of various polymers provide electromagnetic shielding without joints, seams, or cracks.

US Pat. No. 10,510,461

CONDUCTIVE FILM AND PRODUCTION METHOD THEREOF

LG Chem, Ltd., (KR)

1. A method of manufacturing a double-sided conductive film, wherein the double-sided conductive film comprises an intermediate base layer consisting of a plastic film; and two conductive base layers attached to both sides of the intermediate base layer,the method comprising:
thermally treating the intermediate base layer by maintaining the intermediate base layer on both sides of which layers of an uncrosslinked pressure-sensitive adhesive composition are formed, at 50 to 200° C., wherein each of the layers of the uncrosslinked pressure-sensitive adhesive composition is directly formed on a surface of the intermediate base layer,
then attaching the conductive base layers to the both sides of the intermediate base layer to have a room temperature peel strength of 1,000 gf/inch or more with respect to the intermediate base layer, wherein the room temperature peel strength is measured at a peeling rate of 0.3 m/min and a peeling angle of 180 degrees,
wherein each of the conductive base layers includes a conductive layer and a base layer, wherein the conductive layer is formed on one side of the base layer and the base layer is attached to the intermediate base layer, and
wherein the base layer of each of the conductive base layers is a plastic film.

US Pat. No. 10,510,454

MAIN PUMP SHAFT SEAL WATER INJECTION SYSTEM OF A NUCLEAR POWER STATION

China Nuclear Power Engin...

1. A main pump shaft seal water injection system of a nuclear power plant, comprising: a jet pump, a high pressure cooler, a hydrocyclone, valves and a main connection pipeline arranged outside of a main pump, an auxiliary pump and an internal flow path arranged in the main pump, inner and outer flow paths of the main pump are connected with a shaft seal water injection hole and a high temperature water drainage hole on the main connection pipeline, the main connection pipeline is connected between an upper filling water pipeline of a RCV and a shaft seal water injection hole of a main flange, the jet pump, the high pressure cooler and the hydrocyclone are sequentially arranged on the main connection pipeline, further comprising a bypass pipeline connected in parallel with the jet pump, the high pressure cooler and the hydrocyclone, the main connection pipeline is provided with a normally open main pipeline isolating valve at each end of a parallel section connected in parallel with the bypass pipeline, the bypass pipeline allows low temperature upper filling water in the RCV system to bypass the jet pump, the high pressure cooler and the hydrocyclone, and enter the shaft seal water injection hole of the main flange directly.

US Pat. No. 10,510,448

METHOD FOR PROVIDING DIAGNOSIS AID INFORMATION BY USING MEDICAL IMAGES, AND SYSTEM THEREFOR

Samsung Life Public Welfa...

1. A system for providing diagnosis-aiding information using medical images of a patient, the system comprising:a computer-implemented image receiving unit configured to receive a first medical image acquired in a first energy band and a second medical image acquired in a second energy band; and
a computer-implemented analysis- and diagnosis-aiding information providing unit configured to provide diagnosis-aiding information generated by analyzing the first medical image acquired in the first energy band and the second medical image acquired in the second energy band,
wherein the computer-implemented analysis- and diagnosis-aiding information providing unit is configured to provide the diagnosis-aiding information by:
measuring first Hounsfield unit (HU) values in a first region of interest (ROI) of the first medical image acquired in the first energy band and measuring second HU values in a second ROI of the second medical image acquired in the second energy band;
calculating an HU value ratio of the first HU values of the first ROI to the second HU values of the second ROI; and
identifying at least one of a viable tumor portion (VTP), necrotic tumor portion (NTP), Lipiodol-retaining tumor portion (LTP), liver portion, and blood vessel portion based on a comparison of the HU value ratio to a predetermined value,
wherein the computer-implemented analysis- and diagnosis-aiding information providing unit is further configured to identify the VTP responsive to the HU value ratio being between 1.54 to 2.4.

US Pat. No. 10,510,444

CARE PLAN ADMINISTRATION

Preventice Solutions, Inc...

1. A method for administering a care plan, comprising:receiving, at a care plan management system, the care plan specifying a plurality of observation metrics to monitor biometric data collected from a patient;
receiving, at the care plan management system, biometric data measured by at least one monitoring device, wherein the at least one monitoring device has limited computational resources relative to the care plan management system, wherein the biometric data comprises a plurality of detected events, wherein a first event of the plurality of detected events is initially classified as a first type of event by the at least one monitoring device, and wherein the initial classification is based on the at least one monitoring device determining that at least a portion of the biometric data matches a first preconfigured data pattern corresponding to the first type of event;
maintaining an event queue at the care plan management system storing a plurality of previously detected events in a determined order, each previously detected event having a previously determined priority, further comprising:
determining, at the care plan management system, a relative priority of the first event based on the initial classification of the first event by the at least one monitoring device; and
inserting the first event into the event queue at a position determined based on the relative priority of the first event and the order in which the first event was received, wherein the first event is placed into the event queue at a position in front of an event in the queue with a relatively lower priority level;
processing the plurality of detected events, at the care plan management system, in the event queue in the queued order, wherein the queued order is based on the respective position of each event within the event queue;
upon processing the first event, re-classifying, at the care plan management system, the first event as a sub-classification of the first type of event based on determining that at least a portion of the biometric data matches a second preconfigured data pattern, wherein the reclassification at the care plan management system is more computationally intensive than the initial classification at the at least one monitoring device; and
upon determining that the sub-classification of the first type of event satisfies at least one threshold value specified in the care plan, initiating at least one treatment plan specified in the care plan and corresponding to the satisfied at least one threshold value.

US Pat. No. 10,510,442

CABINET FOR DISPENSING ITEMS

Peacock Law P.C., Albuqu...

1. A method of regulating, controlling and distributing products inside of a store comprising:providing a kiosk having a user interface for receiving identification information from a user;
prompting the user to request access to a prescribed regulated product;
the kiosk directing communications between a user and a healthcare professional authorized to write prescriptions;
delivering a quantity of the regulated product to the user; and
configuring the kiosk to also function as a self-checkout register for non-regulated store products.

US Pat. No. 10,510,433

ELECTROMAGNETIC RADIATION SHIELDING TILE HAVING ELECTROMAGNETIC SHIELDING FABRIC AND METAL PORTIONS

Shield Your Body LLC, La...

1. An electromagnetic shielding tile comprising:a protective layer formed from a hypoallergenic fabric having a first surface and a second surface, the second surface to be exposed to an environment;
a first electromagnetic shielding fabric having a first surface bonded to the first surface of the protective layer and a second surface, the first electromagnetic shielding fabric formed from a first metal thread and a first fabric thread, the first metal thread is a PU-silver-copper thread;
a first mu metal layer having a first surface bonded to the second surface of the first electromagnetic shielding fabric and a second surface;
a first microwave absorbing layer having a first surface bonded to the second surface of the first mu metal layer, the first microwave absorbing layer including a magnetic material;
a second electromagnetic shielding fabric having a first surface bonded to the second surface of the first microwave absorbing layer and a second surface, the second electromagnetic shielding fabric formed from a second metal thread and a second fabric thread, the first metal thread including silver and copper;
a second mu metal layer having a first surface bonded to the second surface of the second electromagnetic shielding fabric and a second surface;
a second microwave absorbing layer having a first surface bonded to the second surface of the second mu metal layer and a second surface, the second microwave absorbing layer including a magnetic material; and
an adhesive layer having a first surface and a second surface, the first surface of the adhesive bonded to the second surface of the second microwave absorbing layer, the second surface of the adhesive configured to bond the electromagnetic shielding tile to an article.

US Pat. No. 10,510,430

METHOD, FLASH MEMORY CONTROLLER, MEMORY DEVICE FOR ACCESSING 3D FLASH MEMORY HAVING MULTIPLE MEMORY CHIPS

Silicon Motion, Inc., Hs...

1. A method for accessing a flash memory module being a 3D flash memory module including a plurality of flash memory chips, each flash memory chip including a plurality of blocks which include a plurality of multiple-level cell blocks, each block including a plurality of data pages and including a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, floating transistors on each bit line forming at least one page among the plurality of data pages; and the method comprises:configuring and planning the flash memory chips so that the flash memory chips include at least one super block; and
allocating a buffer memory space for storing multiple sets of temporary parity check codes generated by an encoding procedure during programming data into the at least one super block;
wherein each flash memory chip of the 3D NAND-type flash memory module has a plurality of 3D stacked planes; all word lines disposed on a same 3D stacked plane are classified into a same word line set, and word lines on different 3D stacked planes are respectively classified into different word line sets; all word line sets on the different 3D stacked planes are classified into a group of multiple odd word line sets and a group of multiple even word line sets; and, at least one set of parity check codes is generated for data disposed on particular word lines associated with a same order respectively comprised within different non-adjacent word line sets, the different non-adjacent word line sets being the multiple odd word line sets or the multiple even word line sets, the different non-adjacent word line sets comprising odd and even word lines of a first word line set and odd and even word lines of a second word line set that is not adjacent to the first word line set.

US Pat. No. 10,510,429

MEMORY DEVICE PERFORMING TEST ON MEMORY CELL ARRAY AND METHOD OF OPERATING THE SAME

Samsung Electronics Co., ...

1. A memory device, comprising:a memory cell array connected to a bit line, first word lines, and second word lines, the memory cell array including a first memory cell and second memory cells, the first memory cell being connected between one of the first word lines and the bit line, and the second memory cells being connected between a respective one of the second word lines and the bit line;
a first word line driver configured to drive the first word lines;
a second word line driver configured to drive the second word lines; and
a test manager configured to,
control the second word line driver in a test mode to drive N second word lines of the second word lines to change a capacitance of the bit line by connecting a cell capacitor included in each of the second memory cells associated with the N second word lines to the bit line connected to the first memory cell such that the capacitance of the bit line connected to the first memory cell increases, N being an integer greater than or equal to one, and
control, after the capacitance of the bit line connected to the first memory cell is changed, the first word line driver such that the first word lines are driven to test the first word lines.

US Pat. No. 10,510,428

SHIFT REGISTER CIRCUITRY AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUITRY AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A shift register circuitry, comprising an input circuit and a plurality of output circuits coupled to the input circuit;wherein the input circuit is coupled to an input signal terminal, and is configured to, under the control of a voltage at the input signal terminal, cause the plurality of output circuits to operate; and
wherein each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the respective clock signal terminal to the respective output signal terminal so as to output a driving signal at the respective output signal terminal;
wherein the shift register circuitry at least further comprises a pull-down control circuit a first pull-down circuit, and a second pull-down circuit;
wherein the plurality of output circuits comprise at least a first output circuit and a second output circuit;
wherein the input circuit is coupled to the input signal terminal, a first voltage terminal, a first pull-up point, and a second pull-up point, and is configured to couple the first voltage terminal to the first pull-up point and the second pull-up point, under the control of the voltage at the input signal terminal;
wherein the first output circuit is coupled to a first clock signal terminal and a first output signal terminal, and is configured to couple the first clock signal terminal to the first output signal terminal, under the control of a voltage at the first pull-up point;
wherein the second output circuit is coupled to a second clock signal terminal and a second output signal terminal and is configured to couple the second clock signal terminal to the second output signal terminal, under the control of a voltage at the second pull-up point;
wherein the pull-down control circuit is coupled to a third voltage terminal, a third clock signal terminal, the first pull-up point, the second pull-up point, and a pull-down point, and is configured to selectively couple the pull-down point to one of the third voltage terminal and the third clock signal terminal, under the control of voltages at the third clock signal terminal, the first pull-up point and the second pull-up point;
wherein the first pull-down circuit is coupled to the pull-down point, the third voltage terminal, the first pull-up point, and the first output signal terminal, and is configured to couple the first pull-up point and the first output signal terminal to the third voltage terminal, under the control of a voltage at the pull-down point; and
wherein the second pull-down circuit is coupled to the pull-down point, the third voltage terminal, the second pull-up point, and the second output signal terminal, and is configured to couple the second pull-up point and the second output signal terminal to the third voltage terminal, under the control of the voltage at the pull-down point.

US Pat. No. 10,510,427

HIGH RELIABLE OTP MEMORY WITH LOW READING VOLTAGE

SICHUAN KILOWAY ELECTRONI...

1. A high reliable, low reading voltage OTP memory, comprising: a first MOS transistor, a second MOS transistor and an anti-fuse element; whereina gate of the first MOS transistor is connected to a second line WS, a first end of the first MOS transistor is connected to a first line WP across through the anti-fuse element, and a second end of the first MOS transistor is connected to a third line BL;
a first end of the second MOS transistor is connected to a fourth line BR, a second end of the second MOS transistor is connected to the third line BL;
the high reliable, low reading voltage OTP memory further comprises a voltage-limit device having one control end and two connection ends; the control end of the voltage-limit device is connected to a control line WB, a first connection end of the voltage-limit device is connected to the anti-fuse element and the first end of the first MOS transistor, and a second connection end of the voltage-limit device is connected to a gate of the second MOS transistor.

US Pat. No. 10,510,422

MEMORY DEVICES WITH READ LEVEL CALIBRATION

Micron Technology, Inc., ...

1. A memory device comprising:a controller; and
a main memory operably coupled to the controller, wherein the main memory includes:
a memory region having a plurality of memory cells, and
calibration circuitry operably coupled to the memory region and configured to:
measure, for a portion of the memory region, a performance characteristic for each of a plurality of read level test signals, wherein the performance characteristic comprises a number of memory cells outputting a predetermined data state in response to the corresponding read level test signal;
determine a read level offset value corresponding to an extrapolated level between two of the plurality of read level test signals based at least in part on differences between the number of memory cells outputting the predetermined data state for adjacent read level test signals, and
output the read level offset value to the controller.

US Pat. No. 10,510,421

SEMICONDUCTOR STORAGE DEVICE AND READOUT METHOD THEREOF

Winbond Electronics Corp....

1. A semiconductor storage device, comprising:a memory cell array;
a page buffer/sense circuit, comprising:
a sensing node, comprising an N-type metal oxide semiconductor (NMOS) capacitor, and sensing data readout from a selected page of the memory cell array;
a latch circuit, comprising a latch node coupled to the sensing node, and holding data sensed by the sensing node; and
a selective charging circuit, comprising a floating node coupled to the sensing node, and performing selective charging to the sensing node based on a potential of the latch node; and
a controller, configured to control a readout operation or a program operation on the memory cell array, and control to perform pre-charging to the floating node before performing the selective charging to the sensing node.

US Pat. No. 10,510,420

RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES

Micron Technology, Inc., ...

1. A memory device comprising:a memory array including a plurality of access lines and data lines; and
a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines, wherein each pulse of the consecutive pulses comprises:
a first voltage; and
a second voltage, wherein the first voltage is greater in magnitude than the second voltage, and wherein the first voltage is applied for a shorter duration than the second voltage,
wherein the circuit is configured to provide the consecutive pulses to the selected one of the plurality of access lines during an operation.

US Pat. No. 10,510,416

METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION

ARM Ltd., Cambridge (GB)...

1. A method, comprising:applying a first programming signal to terminals of a non-volatile memory element, the non-volatile memory element to be capable of being placed in a high impedance or insulative state and two or more low impedance or conductive states, to place the non-volatile memory element in a first particular low impedance or conductive state of the two or more low impedance or conductive states, wherein the non-volatile memory element to comprise a material formed between terminals of the non-volatile memory element, and wherein the two or more low impedance or conductive states to be distinguishable based, at least in part, on a density of and/or concentration of electrons in the material;
measuring and/or detecting a first current in the non-volatile memory element responsive to application of a read signal to terminals of the non-volatile memory element; and
determining that the non-volatile memory element is in the particular impedance state from among the two or more low impedance or conductive states based, at least in part, on the measured and/or detected current in the non-volatile memory element.

US Pat. No. 10,510,411

RRAM ARRAY WITH CURRENT LIMITING ELEMENT

Taiwan Semiconductor Manu...

1. An integrated chip, comprising:a plurality of resistive random access memory (RRAM) devices respectively comprising a first electrode and a second electrode;
a bit-line decoder connected to the first electrode of the plurality of RRAM devices by a plurality of bit-lines; and
a current limiting element connected to the second electrode of the plurality of RRAM devices by way of a plurality of access transistors, wherein the current limiting element is configured to concurrently limit currents on the plurality of bit-lines.

US Pat. No. 10,510,410

METHOD FOR PROGRAMMING RESISTIVE MEMORY CELL WITH AC PERTURBATION AC SIGNAL AND NONVOLATILE MEMORY DEVICE THEREOF

Taiwan Semiconductor Manu...

1. A non-volatile memory device, comprising:a resistive memory cell; and
a write and read circuit, coupled to the resistive memory cell, and configured to combine a perturbation AC signal with a first writing signal, so as to generate a second writing signal having a same period as the first writing signal and apply the second writing signal to the resistive memory cell to program the resistive memory cell.

US Pat. No. 10,510,403

MEMORY READ STABILITY ENHANCEMENT WITH SHORT SEGMENTED BIT LINE ARCHITECTURE

Taiwan Semiconductor Manu...

1. A semiconductor memory device comprising:an array of semiconductor memory cells arranged in rows and columns, the array including first and second segments of non-overlapping memory cells which span multiple columns of the array;
a first bit line extending over the first segment of memory cells;
a second bit line extending over the second segment of memory cells;
a switch arranged between the first and second segments of memory cells and being configured to selectively couple the first bit line in series with the second bit line;
a first write circuit coupled to the first bit line, and configured to apply a bias to the first bit line to write data to the first segment of memory cells; and
a second write circuit separate from the first write circuit and coupled to the second bit line, the second write circuit configured to apply a bias to the second bit line to write data to the second segment of memory cells.

US Pat. No. 10,510,400

SEMICONDUCTOR STORAGE DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a word line;
a pair of bit lines;
a static type memory cell coupled to the word line and the pair of bit lines;
a write driver circuit which transmits data to the pair of bit lines according to write data; and
a write assist circuit which drives one of the pair of bit lines to a level of a negative voltage, the one of the pair of bit lines corresponding to a low potential side of the pair of bit lines according to the write data,
wherein the write assist circuit comprises:
a first signal wiring; and
a second signal wiring coupled to the bit line on the low potential side and operable to generate the negative voltage based on a first coupling capacitance between the first signal wiring and the second signal wiring, and
wherein the bit line on the low potential side is a wiring different from the second signal wiring.

US Pat. No. 10,510,396

METHOD AND APPARATUS FOR INTERRUPTING MEMORY BANK REFRESH

Apple Inc., Cupertino, C...

1. An integrated circuit comprising:a memory controller having an interface suitable for coupling to a dynamic random access memory (DRAM) having a plurality of banks, wherein the memory controller includes a state machine configured to:
send a refresh command to the DRAM to initiate a per-bank refresh, the per-bank refresh comprising successively refreshing single ones of the plurality of banks;
responsive to receiving an indication of a high-priority transaction during performing of the per-bank refresh, determining if a number of banks refreshed is at least a threshold value; and
responsive to determining that the number of banks refreshed is less than the threshold value, aborting the per-bank refresh.

US Pat. No. 10,510,392

INTEGRATED CIRCUITS HAVING MEMORY CELLS WITH SHARED BIT LINES AND SHARED SOURCE LINES

GLOBALFOUNDRIES, INC., G...

1. An integrated circuit comprising:a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line and wherein a first bit cell in the selected column is coupled to a word line;
a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line and wherein a first bit cell in the first column is coupled to the word line; and
a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line and wherein a first bit cell in the second column is coupled to the word line;
wherein each bit cell includes a magneto-resistive random access memory (MRAM) device;
wherein a first MRAM device in the selected column is longitudinally adjacent a second MRAM device in the selected column; and
wherein a single diffusion break isolates the first MRAM device in the selected column from the second MRAM device in the selected column.

US Pat. No. 10,510,391

MAGNETIC EXCHANGE COUPLED MTJ FREE LAYER HAVING LOW SWITCHING CURRENT AND HIGH DATA RETENTION

INTERNATIONAL BUSINESS MA...

1. A method of forming a magnetic tunnel junction (MTJ) storage element comprising:forming a reference layer having a fixed magnetization direction;
forming a tunnel barrier layer; and
forming a composite free layer on an opposite side of the tunnel barrier layer from the reference layer;
where forming the composite free layer comprises forming a first region, a second region and a third region;
where forming the first region comprises configuring the first region to include a first predetermined magnetic moment and a first non-fixed magnetization direction;
where forming the second region comprises configuring the second region to include a second predetermined magnetic moment and a second non-fixed magnetization direction, where the second predetermined magnetic moment is higher than the first predetermined magnetic moment;
configuring the first region, the second region, and the third region such that the direction of the first non-fixed magnetization direction changing initiates the change in the direction of the second non-fixed magnetization direction;
where forming the first region further comprises configuring the first region to include a first predetermined activation energy;
where forming the second region further comprises configuring the second region to include a second predetermined activation energy that is higher than the first predetermined activation energy;
where forming the third region comprises configuring the third region to magnetically couple the first region and the second region.

US Pat. No. 10,510,381

DATA TRANSFER BETWEEN SUBARRAYS IN MEMORY

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells; and
a controller coupled to the array of memory cells and configured to:
direct movement of data from first portion of memory cells in a row of a first subarray to a first sensing circuitry; and
direct movement of a complement of the data from the first sensing circuitry to a particular row of memory cells in a second subarray, wherein each memory cell of the particular row of memory cells is coupled to an adjacent memory cell of the particular row of memory cells;
direct movement of the complement of the data from memory cells in the particular row of memory cells in the second subarray to adjacent memory cells in the particular row of memory cells in the second subarray; and
direct movement of the complement of the data from the adjacent memory cells in the particular row of memory cells of the second subarray to a second sensing circuitry.

US Pat. No. 10,510,372

MECHANICAL RETENTION AND RETRIEVAL FOR TAPE STORAGE CARTRIDGE

Amazon Technologies, Inc....

1. A system, comprising:a tape cartridge comprising a rectangular body defined by a first lateral side wall and a second lateral side wall, the tape cartridge further comprising a first notch in the first lateral side wall and a second notch in the second lateral side wall;
a tape library rack comprising a plurality of partitions including a first lateral partition and a second lateral partition spaced apart from one another to define there between a slot sized for receiving the tape cartridge;
a first hook coupled with the first lateral partition and comprising a first sloped extension releasably engaged in the first notch of the tape cartridge;
a second hook coupled with the second lateral partition and comprising a second sloped extension releasably engaged in the second notch of the tape cartridge;
a gripper comprising a first arm, a second arm, a driver, and a pincher, wherein the first arm and the second arm are spaced to engage the first notch and the second notch of the tape cartridge and the first hook and the second hook of the tape library rack, the first arm comprising a first ramped surface and the second arm comprising a second ramped surface, the gripper selectively movable by the driver toward the slot to cause the first ramped surface of the first arm to engage and travel along the first sloped extension of the first hook so as to displace the first hook out of engagement from the first notch of the tape cartridge and to cause the second ramped surface of the second arm to engage and travel along the second sloped extension of the second hook so as to displace the second hook out of engagement from the second notch of the tape cartridge, wherein the first arm and the second arm are selectively engageable respectively in the first notch and the second notch of the tape cartridge by the pincher for gripping the tape cartridge for moving the tape cartridge relative to the slot by movement of the gripper.

US Pat. No. 10,510,364

DEVICES INCLUDING A NEAR FIELD TRANSDUCER (NFT) WITH NANOPARTICLES

Seagate Technology LLC, ...

1. A device comprising:a near field transducer (NFT) comprising a crystalline plasmonic material having crystal grains and grain boundaries; and nanoparticles disposed in the crystal grains, in the grain boundaries, on the grain boundaries, or some combination thereof,
wherein the nanoparticles comprise:
oxides of, lanthanum (La), barium (Ba), strontium (Sr), erbium (Er), hafnium (Hf), germanium (Ge), or combinations thereof;
nitrides of zirconium (Zr), niobium (Nb), or combinations thereof; or
carbides of silicon (Si), aluminum (Al), boron (B), zirconium (Zr), tungsten (W), titanium (Ti), niobium (Nb), or combinations thereof.

US Pat. No. 10,510,357

RESAMPLING OF AN AUDIO SIGNAL BY INTERPOLATION FOR LOW-DELAY ENCODING/DECODING

ORANGE, Paris (FR)

1. A method comprising:receiving an audio frequency signal for resampling from a non-transitory computer-readable memory of a FIR type resampling filter; and
resampling the audio frequency signal by an audio frequency signal coder or decoder device, the resampling comprising performing an interpolation method of order higher than one, and obtaining interpolated samples by a computation of a weighted average of possible interpolation values computed over a plurality of intervals covering a temporal location of the sample to be interpolated, the interpolated samples complementing a signal decoded according to a restricted predictive decoding mode in a transition frame between a predictive decoding and a transform decoding prior to an act of combination between samples decoded according to the restricted predictive decoding and the samples decoded according to a transform decoding in the transition frame.

US Pat. No. 10,510,355

TIME-ALIGNMENT OF QMF BASED PROCESSING DATA

Dolby International AB, ...

1. An audio decoder comprising:a waveform processing path configured to generate a plurality of waveform subband signals from waveform data obtained from an access unit of a data stream of an audio signal;
a metadata processing path configured to generate decoded metadata from metadata obtained from the access unit, the metadata processing path comprising a metadata delay unit configured to delay the decoded metadata by an integer multiple of a frame length N of the reconstructed frame of the audio signal, wherein the integer multiple is greater than zero and the delay is greater than a delay introduced by the waveform processing path; and
a metadata application and synthesis unit configured to generate a reconstructed frame of the audio signal from the plurality of waveform subband signals and from the decoded metadata, wherein at least one of the waveform processing path or the metadata processing path comprises at least one delay unit configured to time-align the plurality of waveform subband signals and the decoded metadata.

US Pat. No. 10,510,352

DETECTING REPLAY ATTACKS IN VOICE-BASED AUTHENTICATION

Amazon Technologies, Inc....

1. A method, comprising:receiving, via at least one of one or more computing devices, audio captured via an audio input device at a first geographic location;
verifying, via at least one of the one or more computing devices, that the audio includes a voice authentication factor spoken by a user;
receiving, via at least one of the one or more computing devices, information indicating that the user is physically present at a second geographic location instead of the first geographic location when the audio was captured; and
performing, via at least one of the one or more computing devices, at least one action in response to receiving the information, the at least one action comprising at least one of: causing a notification of authentication failure to be played by a speaker, requesting that the user provide another authentication factor, sending a notification to an administrator, blacklisting a network address, disabling access to an account associated with the user, storing the audio in a data store, or causing a honeypot mode to be entered by the one or more computing devices.

US Pat. No. 10,510,349

CONTEXT-BASED SMARTPHONE SENSOR LOGIC

Digimarc Corporation, Be...

20. A method employing a portable device including a processor, memory and plural sensors that include at least a microphone or a camera, the method comprising the acts:(a) applying a classification procedure to received audio and/or visual information, sensed by the microphone and/or camera, to determine a type of said information from among plural possible types;
(b) determining a scenario type, based at least in part on (i) a number of people sensed as being present with a user of the device, or (ii) an identity of one or more people sensed as being present with said user, together with one or more of: (i) time of day, (ii) day of week, (iii) location, (iv) calendar data, (v) clock alarm status, (vi) motion sensor data, (vii) orientation sensor data, and (viii) information from a social networking service; and
(c) based on a combination of (i) the determined type of the received audio and/or visual information, and (ii) the determined type of scenario, selecting a group of one or more recognition technologies from a set of available recognition technologies, and applying the selected group of one or more recognition technologies to the received audio and/or visual information;
at a first time, act (c) comprising applying a first group of recognition technologies to the received audio and/or visual information, in accordance with a first combination of (i) information type, and (ii) scenario type;
at a second time, act (c) comprising applying a second group of recognition technologies to the received audio and/or visual information, in accordance with a second combination of (i) information type, and (ii) scenario type; and
at a third time, act (c) comprising applying a third group of recognition technologies to the received audio and/or visual information, in accordance with a third combination of (i) information type, and (ii) scenario type;
wherein:
said first, second and third groups of recognition technologies are different;
said first, second and third combinations are different; and
at one of said first, second or third times, act (c) includes selecting and applying a group of two or more recognition technologies to the received audio and/or visual information, at least one of said two or more recognition technologies being a watermark-, fingerprint-, barcode-based, or optical character-recognition technology.

US Pat. No. 10,510,343

SPEECH RECOGNITION METHODS, DEVICES, AND SYSTEMS

ADEMCO INC., Golden Vall...

1. A system for speech recognition, the system comprising:a number of microphones configured to capture sound in an area;
a digital signal processor configured to segregate the sound into a first signal and a second signal, wherein the first signal corresponds to a first portion of the area and the second signal corresponds to a second portion of the area; and
a single automatic speech recognition engine having one or more processing components configured to receive the first signal and the second signal, first process the first signal through all of the one or more processing components and then process the second signal through all of the one or more processing components to recognize a speech command in the sound, and responsive to recognizing the speech command, adjust operation of the single automatic speech recognition engine or another device.

US Pat. No. 10,510,310

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a first gate driver circuit;
a second gate driver circuit;
a pixel portion between the first gate driver circuit and the second gate driver circuit; and
a gate line electrically connected to the first gate driver circuit and the second gate driver circuit,
wherein the first gate driver circuit comprises first to eighth transistors,
wherein the second gate driver circuit comprises ninth to sixteenth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the gate line,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the gate line,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring,
wherein a gate of the fourth transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the third transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein a gate of the fifth transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the third transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the second wiring,
wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a fourth wiring,
wherein a gate of the seventh transistor is electrically connected to the fourth wiring,
wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the second wiring,
wherein a gate of the eighth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate line,
wherein the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate line,
wherein the other of the source and the drain of the tenth transistor is electrically connected to a seventh wiring,
wherein one of a source and a drain of the eleventh transistor is electrically connected to a gate of the tenth transistor,
wherein the other of the source and the drain of the eleventh transistor is electrically connected to an eighth wiring,
wherein one of a source and a drain of the twelfth transistor is electrically connected to the gate of the tenth transistor,
wherein the other of the source and the drain of the twelfth transistor is electrically connected to the seventh wiring,
wherein a gate of the twelfth transistor is electrically connected to a gate of the ninth transistor,
wherein one of a source and a drain of the thirteenth transistor is electrically connected to a gate of the eleventh transistor,
wherein the other of the source and the drain of the thirteenth transistor is electrically connected to the eighth wiring,
wherein a gate of the thirteenth transistor is electrically connected to the eighth wiring,
wherein one of a source and a drain of the fourteenth transistor is electrically connected to the gate of the eleventh transistor,
wherein the other of the source and the drain of the fourteenth transistor is electrically connected to the seventh wiring,
wherein a gate of the fourteenth transistor is electrically connected to the gate of the ninth transistor,
wherein one of a source and a drain of the fifteenth transistor is electrically connected to the gate of the ninth transistor,
wherein the other of the source and the drain of the fifteenth transistor is electrically connected to a ninth wiring,
wherein a gate of the fifteenth transistor is electrically connected to the ninth wiring,
wherein one of a source and a drain of the sixteenth transistor is electrically connected to the gate of the ninth transistor,
wherein the other of the source and the drain of the sixteenth transistor is electrically connected to the seventh wiring, and
wherein a gate of the sixteenth transistor is electrically connected to a tenth wiring.

US Pat. No. 10,510,302

ELECTROLUMINESCENT DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An electroluminescent display device, comprising:a substrate
a scan signal line along a first direction on the substrate;
a data line and a power line along a second direction crossing the first direction;
a switching thin film transistor (TFT) connected to the scan signal line and the data line;
a driving TFT connected to the switching TFT and the power line; and
an emitting diode connected to the driving TFT,
wherein the driving TFT includes a two-gate overlap structure including a second gate electrode over a first gate electrode, the second gate electrode comprising a source terminal of the driving TFT, whereby the first and second gate electrodes are configured to act as a first capacitor,
wherein the power line has a first portion directly extending from the power line over the two-gate overlap structure, whereby the first portion of the power line and the second gate electrode are configure to act as a second capacitor, and
wherein the first portion of the power line is disposed over the second gate electrode and overlaps the first gate electrode in a plane view.

US Pat. No. 10,510,300

ORGANIC LIGHT EMITTING DISPLAY

Samsung Display Co., Ltd....

1. An organic light emitting display comprising:a plurality of sub pixels comprising a blue sub pixel, a red sub pixel and a green sub pixel;
a first power source line coupled to at least one of the plurality of sub pixels; and
a second power source line coupled to at least one of other sub pixels different from the at least one of the sub pixels coupled to the first power source line,
wherein the first power source line has a larger width than the second power source line, and
wherein a distance between sub pixels adjacent to the first power source line from among the plurality of sub pixels is greater than a distance between sub pixels adjacent to the second power source line from among the plurality of sub pixels.

US Pat. No. 10,510,296

PIXEL DRIVING CIRCUIT AND PIXEL DRIVING METHOD, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel driving circuit, comprising a driving control circuit, a first driving circuit and a second driving circuit, whereinthe driving control circuit is connected to a data line, a first scanning line, a second scanning line, a first voltage signal terminal, and is connected to the first driving circuit via a first node, is connected to the second driving circuit via a second node, and is configured to control one of the first driving circuit and the second driving circuit to be turned on under the condition the first scanning line outputs an effective voltage signal, and control the other of the first driving circuit and the second driving circuit to be turned on under the condition the second scanning line outputs an effective voltage signal;
the first driving circuit is connected to the driving control circuit, a second voltage signal terminal and a light emitting circuit, and is configured to drive the light emitting circuit to emit light under control of the driving control circuit;
the second driving circuit is connected to the driving control circuit, the second voltage signal terminal and the light emitting circuit, and is configured to drive the light emitting circuit to emit light under control of the driving control circuit; and
the driving control circuit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor, wherein
a control terminal of the first transistor is coupled to the first scanning line, a first terminal of the first transistor is coupled to the data line, and a second terminal of the first transistor is coupled to the first node;
a control terminal of the second transistor is coupled to the second scanning line, a first terminal of the second transistor is coupled to the data line, and a second terminal of the second transistor is coupled to the second node;
a control terminal of the third transistor coupled to the second scanning line, a first terminal of the third transistor is coupled to the first voltage signal terminal, and a second terminal of the third transistor is coupled to the first node;
a control terminal of the fourth transistor is coupled to the first scanning line, a first terminal of the fourth transistor is coupled to the first voltage signal terminal, and a second terminal of the fourth transistor is coupled to the second node;
a first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to a second terminal of the second capacitor; and
a first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the second terminal of the first capacitor.

US Pat. No. 10,510,285

DISPLAY DEVICE AND DRIVE METHOD THEREFOR

SHARP KABUSHIKI KAISHA, ...

1. An active-matrix type display device comprising:a display unit including n pieces of scanning lines, wherein n is an integer equal to or more than two, m pieces of data lines, wherein m is an integer equal to or more than two and (m×n) pieces of pixel circuits arranged two-dimensionally;
a scanning line drive circuit configured to drive the scanning lines;
a data line drive circuit configured to drive the data lines; and
a measurement circuit including a plurality of measurement units and configured to measure a current or a voltage with respect to the pixel circuit, wherein
the measurement unit is connected to the data line,
the data lines and the measurement units are classified into first and second groups,
each of the first and second groups includes one or p pieces of adjacently arranged data lines, wherein p is an integer equal to or more than two,
the measurement circuit is configured to perform, at a same timing, a main measurement for measuring the current or the voltage via the data line with respect to the pixel circuit with supplying a measurement signal to a part of the measurement units and a dummy measurement for measuring a current or a voltage via the data line with supplying a dummy signal to at least a part of remaining measurement units, the dummy signal being a signal with which a value to be measured is approximately zero, and perform a calculation on a result of the main measurement and a result of the dummy measurement, and
the measurement circuit is configured to perform the main measurement using the measurement unit in the first group and the dummy measurement using the measurement unit in the second group at a same timing in a first period, and perform the main measurement using the measurement unit in the second group and the dummy measurement using the measurement unit in the first group at a same timing in a second period.

US Pat. No. 10,510,254

METHOD AND SYSTEM FOR PROCESSING CROSSWIND LOAD DATA FOR A MOTOR VEHICLE

FORD GLOBAL TECHNOLOGIES,...

1. A method for operating a motor vehicle, comprising:ascertaining a travel path of the vehicle across a roadway section situated ahead in a direction of travel, the travel path being defined by a running condition of the vehicle, a virtual map having local wind conditions, a current location of the vehicle on the virtual map, and instantaneous environment data;
ascertaining a time and location that the vehicle enters a lateral wind shadow of a second vehicle traveling ahead of the vehicle within the travel path, and a time and location that the vehicle exits the lateral wind shadow, the lateral wind shadow being based on the running condition and the environment data; and
actuating at least one device configured to influence the running condition based on the travel path and the times and locations of the later wind shadow entry and exit.

US Pat. No. 10,510,247

METHOD AND DEVICE FOR DETECTING WHETHER OBJECT VIOLATES TRAFFIC SIGNAL

BOE TECHNOLOGY GROUP CO.,...

1. A method for detecting whether an object violates a traffic signal, comprising:acquiring, by a terminal moving along with the object, a current signal state of the traffic signal in a moving direction of the object through a network, the terminal being paired with the object;
determining, by the terminal, a current position of the object according to beacons surrounding an intersection where the object is in response to the current signal state of the traffic signal being no passing; and
detecting, by the terminal, whether the object violates a traffic signal according to the current position of the object;
wherein the step of the terminal determining a current position of the object according to beacons surrounding the intersection where the object is, comprises:
determining, by the terminal, beacons surrounding the intersection wirelessly, in response to the current signal state of the traffic signal being no passing;
determining, by the terminal, a distance from each beacon according the received signal strength of each determined beacon; and
determining, by the terminal, the current position of the object according to the distance from each beacon.

US Pat. No. 10,510,204

APPARATUS FOR THE PREPARATION AND DISPENSING OF BAKERY FOOD PRODUCTS, IN PARTICULAR PIZZAS

1. An apparatus for the preparation and dispensing of bakery food products, in particular pizzas, comprising:a magazine (2) containing a plurality of food products (P) having a storage compartment (3) for storing said products (P) in a respective semi-cooked condition;
said magazine comprising a chamber (5) internally defining said storage compartment (3) and having at least one opening (6) for connecting said loading station with said compartment (3), and a carousel (8) arranged inside said compartment (3) and rotatable about a respective longitudinal axis (X);
said carousel (8) having a plurality of retaining members (9) for retaining at least one frozen food product (P), which are arranged along a substantially circular path defined by said carousel (8) and motor means (10) associated with said carousel in order to rotate it under a plurality of operating conditions in which at least one retaining member (9) is arranged in the area of said opening (6);
each retaining member (9) comprising a plurality of gripping elements (11) mutually overlapped and movable along a closed loop path in a direction parallel to said longitudinal axis (X) of the carousel (8);
each gripping element (11) presenting two adjacent portions (12) defining a support surface (13) for a respective food product (P), said retaining member (9) further presenting a pair of motorised belts (14) for conveying said portions (12) for moving the gripping elements (11) along the closed loop path;
said apparatus further comprising:
cooling means (4) arranged inside the magazine (2) to keep the compartment (3) of said food products (P) at a predetermined freezing temperature;
a supply line (15) for supplying said food products (P) extending between a product loading station arranged in the area of the magazine (2) and a dispensing station for dispensing the food products (P);
said supply line comprising a first oven (16) arranged downstream of the loading station and configured to thaw the food products (P) leaving the magazine (2), and a second oven (17) interposed between said first oven and said dispensing station and configured to cook the thawed food product at a given temperature depending on the type of the product (P) itself; and
packaging means (21), located in the area of said dispensing station to arrange each product (P) leaving the supply line (15) inside a respective package (C).

US Pat. No. 10,510,183

GRAPHICS PROCESSING ENHANCEMENT BY TRACKING OBJECT AND/OR PRIMITIVE IDENTIFIERS

SONY INTERACTIVE ENTERTAI...

1. A method of rendering graphics with a processor, the method comprising:setting up a plurality of objects in a scene in virtual space, each said object being defined by a set of vertices;
assigning a unique object identifier to each of the objects;
issuing one or more draw calls to draw the objects;
setting up a plurality of primitives from the vertices, each said primitive being defined by a set of one or more of the vertices and each said primitive belonging to one or more of the objects;
performing geometry shading to generate one or more output primitives from the plurality of primitives, wherein performing the geometry shading includes generating a primitive identifier for one or more primitives generated by the geometry shading by incrementing a primitive identifier for each input primitive by a maximum amount of geometric amplification of output primitives supported by an object with which the input primitives are associated;
rasterizing each of the primitives for a plurality of pixels;
writing one or more of the object identifiers to at least one ID buffer, such that each pixel of the plurality of pixels is associated with an object identifier in the ID buffer;
processing the pixels for each of the rasterized primitives to determine corresponding depth and color values for the plurality of pixels; and
determining a set of display pixels for an output frame using the depth and color values for the plurality of pixels and the object identifiers in the ID buffer.

US Pat. No. 10,510,177

DATA PROCESSING DEVICE

Inria Institute National ...

1. A device for processing data, includinga memory for receiving three-dimensional surface data, projection data and pattern data,
a sorter configured to select, for one input voxel, voxels surrounding the input voxel that correspond to the three-dimensional surface data,
an estimator configured to calculate a similarity value between a first voxel associated with first projection data and a second voxel associated with second projection data by calculating the projection of the three-dimensional surface data associated with the first voxel and the three-dimensional surface data associated with the second voxel respectively on a first surface defined by the first projection data and on a second surface defined by the second projection data on which the pattern data are applied, and by calculating a value derived from the difference between the projection of the first voxel on the first surface and the second surface on the one hand, and the difference between the projection of the second voxel on the first surface and the second surface on the other,
a selector configured to determine, for a given voxel and from a set of projection data, those projection data of said set which indicate the best similarity with neighboring voxels of the given voxel, from a value derived from the similarity values obtained by repeatedly calling the estimator with on the one hand the given voxel as the first voxel and the projection data of the set as the first projection data and on the other hand with at least some of the voxels derived from calling the sorter with the first voxel as the second voxel, and projection data which are associated therewith as second projection data, and to associate with the given voxel the determined projection data,
a propagator configured to define, from a voxel of a given resolution and projection data which are associated therewith, a plurality of voxels of higher resolution than the given resolution, and to associate with at least some of this plurality of voxels the projection data associated with the voxel of given resolution,
a driver arranged for calling the propagator with three-dimensional surface data, a voxel and associated projection data, and for calling the selector with at least some of the resulting plurality of voxels with which projection data are associated as a given voxel, as well as with a set of projection data including on the one hand the projection data associated with the resulting plurality of voxel data, and on the other hand a non-zero quantity of other projection data, the driver being further arranged for repeating the call of the propagator with at least some of the voxels associated with the projection data determined by the selector, as well the call of the selector on at least some of the resulting plurality of voxels until reaching a chosen resolution.

US Pat. No. 10,510,171

VISUALIZATION OF ANATOMICAL CAVITIES

Biosense Webster (Israel)...

1. A system for performing a procedure in a nasal cavity and/or sinus, comprising:(a) a magnetic tracking system;
(b) an intrabody tool having one or more magnetic sensors;
(c) a display;
(d) a memory configured to store an image slice and a three-dimensional model of a patient anatomy, wherein the image slice is a two-dimensional image, and wherein a plane location from which the patient anatomy is shown in the image slice is present within the three-dimensional model;
(e) a processor, configured:
(i) to identify a portion of the image slice that corresponds to an anatomical cavity,
(ii) to identify a wall of the three-dimensional model that corresponds to the anatomical cavity, from the same plane location as that of the image slice,
(iii) to create a modified image slice by overlaying the wall on the anatomical cavity of the image slice,
(iv) to overlay an icon that represents the intrabody tool on a portion of the modified image slice that corresponds to a location of the intrabody tool within the anatomical cavity, and
(v) to display the modified image slice on the display.

US Pat. No. 10,510,150

SEARCHING TREES: LIVE TIME-LAPSE CELL-CYCLE PROGRESSION MODELING AND ANALYSIS

International Business Ma...

1. A method of tracking a cell through a plurality of images comprising:selecting at least one cell in at least one image obtained at a first time;
generating a track of the at least one cell through a plurality of images, including the at least one image, obtained at different times using a forward tracking and a backward tracking, wherein generating the track comprises distinguishing, using information generated for the at least one cell by the forward tracking, between a visually occluded cell in at least one of the plurality of images and a mitosis event detected by the backward tracking; and
generating a cell tree lineage of the at least one cell using the track.

US Pat. No. 10,510,144

SYSTEM AND METHOD FOR DETECTION OF SUSPICIOUS TISSUE REGIONS IN AN ENDOSCOPIC PROCEDURE

MAGENTIQ EYE LTD., (IL)

1. An image processing system connected to the video output of an endoscopy device during an endoscopic procedure, comprising:at least one processor; and
at least one memory communicatively coupled to the at least one processor comprising computer-readable instructions that when executed by the at least one processor cause the image processing and machine learning system to implement a method of detecting in real-time suspicious regions in endoscopic video images produced by the endoscopy device, the method comprising performing the following steps on a plurality of successive video frames:(i) removing from each frame peripheral regions outside the visual feed of the endoscope camera;(ii) identifying and removing lumen regions in a frame by finding low intensity, convex regions in the frame, wherein the intensity is below 0.1 on an intensity scale between 0 and 1;(iii) identifying and removing feces regions in a frame;(iv) identifying and removing occurrences in a frame of the endoscope internal side of the tip at peripheral parts of the frame;(v) identifying areas with liquids in each frame or portion of frame;(vi) identifying, and removing surgical tools in each frame or portion of frame;(vii) identifying and removing blurry regions in each frame or portion of frame;(viii) applying on each of said video frames or portion of said frames two of the following conventional detectors that are not based on a supervised learning algorithm, said conventional detectors being adapted to detect if the video frame or portion of said frame contain suspicious regions: color analysis; texture/edges/kernel-based extraction analysis; shading analysis; 3-dimensional (3D) image analysis; or any combination thereof, wherein the determination to identify an area as a suspicious region takes into account the identification of that region in a predetermined number of successive frames; and(ix) applying on each of said video frames or portions of said frames one of the following models of supervised machine learning-based detectors in order to classify which features and image regions are related to suspicious regions: applying a Support Vector Machine (SVM) based process; applying a Decision Trees-based process; applying a deep machine-learning-based networks process comprising one or more models of Convolutional Neural Network (CNN), Regional CNN (RCNN), and Long-Short Term Memory Recurrent CNN (LSTM Recurrent CNN), wherein each model receives as input color channels of original frames or images resulting from the processing of said conventional algorithms or three successive frames; or any combination thereof, wherein the determination to identify an area as a suspicious region takes into account the identification of that region in a predetermined number of successive frames;(x) receiving the results of (viii) and (ix) and reaching a final decision about the suspicious region existence in the frame according to one or more predetermined rules; and(xi) identifying one or more video frames as containing a suspicious area.

US Pat. No. 10,510,130

MOBILE DEVICE TASK MANAGEMENT AND QUEUE FOR MEDICAL TRIAGE

Charu Software Solutions,...

1. A computer-assisted method of routing a medical triage request, the method comprising:registering a medical triage request application residing on a user's mobile electronic device, the registration including:
receiving an association request from the mobile electronic device at a verification server, the association request including a provider code uniquely associated with the mobile electronic device wherein the verification server includes:
a preloaded provider code database;
a medical triage request patient database including a plurality of patient entries, each patient entry corresponding to each of a plurality of managed patients within a medical practice management system; and
a unique device identification database;
verifying the provider code from the association request against the preloaded provider code database to confirm the user is authorized to register the medical triage request application; and
sending to the medical triage request application on the mobile electronic device an association confirmation message code in response to the confirmation that the user is authorized to register the medical triage request application; and
authorizing a medical triage request received from the mobile electronic device the authorization including:
receiving a medical triage request and a unique device identifier code at the verification server from the user through the registered medical triage request application residing on the mobile electronic device, the registered medical triage request application verifying the user information prior to submitting the medical triage request;
comparing the received medical triage request and the unique device identifier code to the plurality of patient entries within the medical triage request patient database, the comparison indicating that the user associated with the medical triage request application residing on the mobile electronic device is authorized to submit the medical triage request and identifying a patient type associated with the user; and
when the comparison identifies a match between the unique device identifier code and the plurality of entries within the medical triage request patient database and the user has been verified as being authorized to submit the medical triage request, routing the medical triage request based on the patient type to a triage software application system for fulfilling the medical triage request.

US Pat. No. 10,510,085

TIME AND LOCATION AWARE CUSTOMER RELATIONSHIP MANAGEMENT

SUGARCRM INC., Cupertino...

1. A method for time and location aware customer relationship management (CRM), the method comprising:establishing a communicative connection between a CRM application executing in memory of a host computing system and a mobile computing device of an end user of the CRM application over a computer communications network;
storing one or more contacts of the CRM application in memory of the host computing system wherein each of the contacts comprise one or more related data records for each of the contacts;
obtaining a location for the mobile computing device from global positioning satellite (GPS) data for the mobile computing device and obtaining a current time in the mobile computing device;
forwarding the location and the current time to the CRM application;
responsive to identifying a meeting in the CRM application that is scheduled proximate to the obtained time, retrieving a related meeting data record for the meeting from the CRM application wherein the related meeting data record comprises directions from the location of the mobile computing device to a location of the meeting and displaying the related meeting data record in the mobile computing device in a user interface for the CRM application; and,
responsive to identifying a contact in the CRM application from the one or more contacts of the CRM application that is proximate to the obtained location, retrieving a related data record for the contact from the CRM application wherein the related data record for the contact comprises a name of the contact, an address of the contact, a listing of key employees of the contact, a listing of key products of the contact and a history of interactions with the contact, additionally retrieving data extrinsic to the CRM application from over the Internet wherein the extrinsic data comprises a portion of a web site provided by the contact that is unrelated to the location of the contact and unrelated to the location of the mobile computing device, and displaying the related data record and the extrinsic data in the mobile computing device of the end user of the CRM application in the user interface for the CRM application.

US Pat. No. 10,510,079

SMALL SAMPLE BASED TRAINING AND LARGE POPULATION APPLICATION FOR COMPLIANCE DETERMINATION AND ENFORCEMENT PLATFORM

Coinbase, Inc., San Fran...

1. A compliance determination and enforcement platform comprising:a processor;
a computer-readable medium connected to the processor; and
a set of computer readable code on the computer-readable medium, including:
a data store;
a plurality of user accounts stored in the data store;
a transaction processor that is executable by the processor to process transactions for the respective user accounts;
a compliance reference score stored in the data store;
a plurality of factors stored in association with each account;
a training system comprising:
a training set selector that is executable by the processor to select a training set of the user accounts, the training set being a subset of the user accounts, and
a training set flagging module that is executable by the processor to:
flag select ones of the user accounts in the training set that fail compliance to indicate non-compliant accounts, and
identify at least one factor of a user account flagged by the training set flagging module as a fail parameter,
the training system being executable by the processor to generate reference data based on at least one fail parameter;
the reference data;
a trained compliance score model, wherein the trained compliance score model is a model that is trained by factors generated by the transaction processor;
a factor entering module that is executable by the processor to enter at least one factor from each user account into the trained compliance score model, wherein the trained compliance score model is executable by the processor to determine a compliance score for each one of the accounts, wherein the respective compliance score for the respective account is based on the at least one factor associated with the respective account, and the reference data generated by the training system;
a comparator that is executable by the processor to compare the compliance score for each account with the compliance reference score to determine a subset of the accounts that fail compliance and a subset of the accounts that meet compliance;
a flagging unit that is executable by the processor to flag the user accounts that fail compliance to indicate non-compliant accounts;
a corrective action system that is executable by the processor to perform a corrective action only for the accounts that are flagged as non-compliant accounts and to provide a user interface that displays a compliance score for each of the plurality of accounts and receives user input identifying a selected flagged account; and
a model modifier unit that is executable by the processor to modify, automatically and without human input, the compliance score model based on the compliance score,
wherein the training set flagging module is executable by the processor to flag select ones of the user accounts in the training set that fail compliance based on the user input received via the user interface provided by the corrective action system.

US Pat. No. 10,510,076

METHOD AND SYSTEM FOR UNIFICATION OF WEARABLE ACTIVITY DATA AND TRANSACTION DATA

MASTERCARD INTERNATIONAL ...

1. A method for distributing content based on wearable computing device activity data and transaction behavior, comprising:storing, in an activity database of a processing server, a plurality of activity profiles, wherein each activity profile is a structured data set including data related to activity of a wearable computing device including at least a device identifier and one or more activity data entries;
storing, in a transaction database of the processing server, a plurality of transaction data entries, wherein each transaction data entry is a structured data set including data related to an electronic transaction including at least a primary account number and additional transaction data;
receiving, by a receiving device of the processing server, a data signal superimposed with pairing data, wherein the pairing data includes at least a specific device identifier and a specific primary account number;
executing, by a querying module of the processing server, a first query on the activity database to identify a specific activity profile where the included device identifier corresponds to the specific device identifier;
executing, by the querying module of the processing server, a second query on the transaction database to identify one or more transaction data entries where the included primary account number corresponds to the specific primary account number;
updating, by an updating module of the processing server, the identified specific activity profile to include at least the specific primary account number;
storing, in a content database of the processing server, a plurality of content profiles, wherein each content profile is a structured data set that includes at least a content data file, trigger data, and at least one transaction behavior;
receiving, by the receiving device of the processing server, a data signal superimposed with an activity notification from a mobile communication device, wherein the activity notification includes at least the specific device identifier and specific trigger data associated with activity data corresponding to a wearable computing device interfaced with the mobile communication device;
identifying, by an analytic module of the processing server, one or more transaction behaviors based on at least the additional transaction data included in at least one of the identified one or more transaction data entries;
executing, by the querying module of the processing server, a third query on the content database to identify a specific content profile where the included trigger data corresponds to the specific trigger data and where the included at least one transaction behavior is included in the identified one or more transaction behaviors; and
electronically transmitting, by a transmitting device of the processing server, a data signal superimposed with at least the content data file identified by the third query in the identified specific content profile to the mobile communication device, wherein the content data file includes an advertisement or offer targeted to a user associated with the activity data corresponding to the wearable device based on the specific trigger data and at least one transaction behavior.

US Pat. No. 10,510,043

COMPUTER METHOD AND APPARATUS FOR TARGETING ADVERTISING

Skyword Inc., Boston, MA...

1. A method of real time customization of a web page at a host computer site hosting a computer-based social network of users, the method comprising:(i) obtaining demographic information of a subject end-user of the host computer site provided by the subject end-user, said obtaining being by one or more computer servers of the host computer site;
(ii) forecasting further demographic information of the subject end-user based on relationships of the subject end-user with other users of the host computer site and based on respective demographic information of the other users of the host computer site, said forecasting resulting in forecasted further demographic information including age or gender of the subject end-user, said forecasting being by the one or more computer servers and being automatically implemented;
(iii) recording, by the one or more computer servers, classification keywords of authored works read, written or published by the subject end-user, and recording indications of corresponding frequency or recency of use by the subject end-user of the recorded classification keywords of said authored works, the classification keywords being keywords used by users at the host computer site to categorize authored works,
wherein users include registered users of the host site and non-registered users of the host site, and authored works include works originated at the host site and works originated elsewhere;
(iv) automatically generating and maintaining, by the one or more computer servers, a profile of the subject end-user by combining the recorded classification keywords of the subject end-user, the obtained demographic information provided by the subject end-user, and the forecasted further demographic information of the subject end-user, said combining considering the recorded indications of corresponding frequency or recency of use by the subject end user of the recorded classification keywords in forming the profile of the subject end-user, the host computer site supporting the generated and maintained profile with a set of tables;
(v) indexing a plurality of paid third-party advertisements, each advertisement having respective keywords associated therewith, said indexing being by the one or more computer servers;
(vi) filtering the indexed advertisements based on the generated and maintained profile of the subject end-user as supported by the tables to generate a plurality of filtered advertisements, said filtering being by the one or more computer servers;
(vii) for each filtered advertisement in the plurality of filtered advertisements, assigning a priority to the filtered advertisements as a function of a rules-based score, the rules-based score being based on at least the generated and maintained profile of the subject end-user, said assigning being by the one or more computer servers assigning a different priority to different filtered advertisements;
(viii) in response to user selection of a web page, customizing the web page in real time with a highest priority filtered advertisement of the plurality of filtered advertisements, said customizing being by the one or more computer servers; and
(ix) delivering the customized web page to the subject end-user such that the highest priority filtered advertisement is displayed with the customized webpage by the one or more computer servers.

US Pat. No. 10,510,032

AUTOMATED CONFIGURATION DATA COLLECTION FOR BUSINESS APPLICATIONS USING FEEDBACK

International Business Ma...

1. A non-transitory computer-readable recordable storage medium storing code executed by a processor causing the processor to perform an automated data collection method comprising:collecting, by a configuration collector manager, a default set of configuration data of an information technology infrastructure, including configuration properties, from a plurality of data sources forming the information technology infrastructure, wherein each of the data sources has a score and wherein the data sources provide the default set of configuration data responsive to a command received from the configuration collector manager;
creating, by a model discovery component, a business application model using the default set of configuration data collected by the configuration collector manager, wherein the business application model comprises a set of unique elements of the information technology infrastructure and relationships therebetween;
mapping the data sources providing the default set of configuration data to the unique elements of the information technology infrastructure;
collecting, from a business application model analysis user interface, activity, including edits and confirmations, associated with the business application model and records associating a plurality of editors with the activity;
analyzing, by a feedback analyzer component, the activity associated with the business application model and the records associating the editors with the activity, wherein the analysis comprises:
identifying a first group of the editors using the records associating the editors with the activity;
mapping the activity of the first group to the data sources;
increasing the score of each of the data sources mapped to the activity associated with the first group of the editors;
decreasing the score of each of the data sources not mapped to the activity associated with the first group of the editors; and
prioritizing the configuration properties based on the scores of the data sources; and
scanning, periodically by the configuration collector manager, the information technology infrastructure to collect additional configuration data according to the prioritized configuration properties, wherein a frequency of the scanning of any one of the plurality of data sources forming the information technology infrastructure is individually adjusted according to the prioritized configuration properties, and wherein the collection of the additional configuration data is performed using an instruction of the configuration collector manager to the data sources overriding the command to collect the default set of configuration data.

US Pat. No. 10,510,023

OBTAINING SERVICES FROM PRODUCT PROVIDERS

Onriva, Inc., Foster Cit...

1. A machine-implemented method comprising:determining, by a platform, a lowest price among offered prices of an air flight selling by agents and by individual airlines,
wherein each agent of the agents represents multiple airlines,
wherein the platform is configured to communicate with the agents using a first protocol,
wherein the platform is configured to communicate with the individual airlines using a second protocol,
wherein the second protocol is different from the first protocol,
wherein the first protocol comprises New Distribution Capability (NDC) protocol or Global Distribution Systems (GDS) protocol, and
wherein the second protocol comprises Internet protocol or Application Program Interface (API) protocol; and
negotiating with one of the individual airlines to obtain a matched price,
wherein the negotiation occurs after obtaining the offered prices,
wherein the matched price is compatible with the lowest price,
wherein the matched price is to be offered to customers when the customers contact the platform about the air flight.

US Pat. No. 10,509,975

METHOD AND DEVICE FOR ESTIMATING A DIRECTION OF A VIEW OF A VEHICLE OCCUPANT, METHOD AND DEVICE FOR DETERMINING A HEAD MOVEMENT GAIN PARAMETER SPECIFIC FOR A VEHICLE OCCUPANT, AND METHOD AND DEVICE FOR ESTIMATING THE DIRECTION OF VIEW OF A VEHICLE OCCUPAN

Robert Bosch GmbH, Stutt...

1. A method for estimating a direction of view of an occupant of a vehicle, the method including the following steps:ascertaining a head fixation position of a head of the vehicle occupant, which terminates a current head movement of the head, using sensor data concerning an angular speed of the current head movement; and
combining the head fixation position and a head movement gain parameter to estimate the direction of view of the vehicle occupant, the head movement gain parameter being a function of a head movement pattern individual for a vehicle occupant during a visual fixing of an object.

US Pat. No. 10,509,967

OCCUPANCY DETECTION

KONINKLIJKE PHILIPS N.V.,...

1. Apparatus for detecting when a subject has exited an item of furniture, the apparatus comprising:a camera adapted to be arranged, when in use, beneath the underside of an item of furniture, wherein the item of furniture has an upper side for supporting a subject and the underside is opposite to the upper side, and wherein the camera is arranged to capture sequential images that do not include the upper side of the item of furniture, the images having a foreground corresponding to a region beneath the underside of the item of furniture and a background corresponding to a region adjacent the item of furniture; and
a processing unit arranged to:
receive the images from the camera;
detect, for each received image, an edge corresponding to an edge of the item of furniture;
detect, in the received images, the appearance of a feature contiguous with the edge;
monitor how the detected feature changes over a time period;
determine whether a change to the detected feature over the time period satisfies at least one predefined criterion for a subject exit event; and
output a signal based on the determining.

US Pat. No. 10,509,941

OPTICAL ASSEMBLY AND FINGERPRINT IMAGING SYSTEM

SHANGHAI OXI TECHNOLOGY C...

1. An optical fingerprint imaging system comprising:a sensor and a light source;
wherein the sensor comprises a substrate and a photosensitive layer, the substrate has a first surface and a second surface which is opposite to and lower than the first surface, and the photosensitive layer is in contact with the first surface of the substrate; and
wherein the light source is disposed at a position lower than the first surface and higher than the second surface, and light emitted from the light source is adapted to be guided by the substrate to the first surface of the substrate.

US Pat. No. 10,509,923

TOUCH SCREEN SECURITY PROTECTION STRUCTURE AND DISPLAY DEVICE

PAX COMPUTER TECHNOLOGY (...

1. A touch screen security protection structure, comprising:a touch screen, a display screen, and a circuit board which are sequentially stacked;
wherein the touch screen is connected with a first signal ribbon cable, the display screen is connected with a second signal ribbon cable, the first signal ribbon cable and the second signal ribbon cable are respectively connected with the circuit board via zebra stripes, the first signal ribbon cable and the second signal ribbon cable are provided with protection winding wires that are loaded with anti-tampering detection signals, and the protection winding wires are electrically connected with the zebra stripes via contacts, wherein a protection wall is arranged in a circumferential direction of the zebra stripes, and wherein the protection wall is provided with the protection winding wires.

US Pat. No. 10,509,918

ONE-TIME OBFUSCATION FOR POLYNOMIAL-SIZE ORDERED BINARY DECISION DIAGRAMS (POBDDS)

HRL Laboratories, LLC, M...

1. A system for protecting sensitive information, the system comprising:one or more processors and a non-transitory memory having instructions encoded thereon such that when the instructions are executed, the one or more processors perform operations of:
transforming a software executable readable code represented as a polynomial-size ordered binary decision diagram (POBDD) having sensitive information embedded therein into an obfuscated code that is hardcoded in POBDD form, wherein transforming the software executable readable code comprises a cryptographic obfuscation process that hides a mapping between an input query and a corresponding output decision bit, wherein the cryptographic obfuscation process guarantees protection of the sensitive information;
evaluating the input query on the obfuscated code via an evaluation process; and
revealing the sensitive information embedded in the software executable readable code only if the input query is a correct input,
wherein the input query is a sequence of secret strings, having a length, corresponding to an input x, and wherein an output of the evaluation process is the output decision bit providing an instruction regarding a next operation to perform.

US Pat. No. 10,509,907

METHODS AND SYSTEMS FOR SECURE AND RELIABLE IDENTITY-BASED COMPUTING

Advanced Elemental Techno...

1. A secure, tamper resistant identity system for device and device corresponding stakeholder assiduous identification and authentication, such system comprising:one or more computing arrangements, including at least one processor, for use in providing one or more standardized at least one of resources and specifications, that at least in part enable forming and validating device stakeholder biometric, and device, bound identifying attribute information sets,
wherein such one or more computing arrangements are employed to provide such one or more standardized at least one of resources and specifications, that at least in part, enable using a secure identity information processing and memory arrangement, producing device unique one or more identifier attribute information sets, wherein such identifier attribute information sets include one or more device identifier attributes that are securely at least one of embedded in, otherwise incorporated in, and otherwise securely bound to, their respective device resource corresponding information sets, such at least one of embedded in, otherwise incorporated in, and otherwise securely bound to, attribute information sets including respective devices' at least one of one or more private keys for respective digital certificates, and symmetric keys,
wherein such digital certificates are signed by, and/or symmetric keys are enabled by, their devices' respective manufacturers, and
wherein each device identifier attribute information set includes commercial value chain device corresponding stakeholder at least one of creator, manufacturer, distributor, retailer, and installer, identity information,
wherein such one or more computing arrangements are employed to provide such one or more standardized at least one of resources and specifications, that at least in part, enable using a human biometric identification arrangement comprising, at least in part, at least one of secure electromagnetic and ultrasound, sensor set for biometric identification of device stakeholder identity information sets,
wherein device stakeholders comprise at least one of one or more manufacturers, providers, distributors, retailers, installers, and at least one of users and owners, wherein at least one of stakeholder biometric attribute information sets and information sets respectively derived therefrom, are at least one of securely included in, and securely associated with, respective, corresponding device information sets to form device stakeholder biometric, and device, bound identifying attribute information sets, and
wherein such one or more computing arrangements are employed to provide such one or more standardized at least one of resources and specifications, that at least in part, enable device validation, employing an at least in part hardware tamper resistant processing and memory arrangement, in support of validating such stakeholder biometric, and device, bound identifying attribute information sets, and wherein a determination as to whether to use one or more devices is based, at least in part, on validating the authenticity of device respective at least one of such stakeholder biometric attribute information sets, and such bound identifying attribute information sets.

US Pat. No. 10,509,882

SYSTEMS AND METHODS FOR CELL ABUTMENT

Taiwan Semiconductor Manu...

1. A method for cell placement, the method comprising:placing a plurality of cells selected from a cell library in a cell-based chip layout to produce a first cell placement;
determining whether the first cell placement satisfies design demands;
rearranging a first cell from among the plurality of cells to abut the first cell with a second cell from among the plurality of cells when the first cell placement fails to satisfy the design demands, wherein the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined;
generating the cell-based chip layout based on the second cell placement; and
outputting the cell-based chip layout to a machine readable storage medium, wherein the outputted cell-based chip layout is used to manufacture a set of masks used in chip fabrication processes.

US Pat. No. 10,509,846

ACCELERATOR FOR PROCESSING DATA

Intel Corporation, Santa...

1. An apparatus for accelerating processing of one or more processors, the apparatus comprising:at least one processing element having a multiplier that receives row data sets and column data sets while operating in a first mode;
at least one row multiplexer and at least one row memory device coupled to the at least one processing element for selecting a row data set received by the multiplier based on matching a row data set index with a column data set index while operating in a second mode; and
at least one column multiplexer and at least one column memory device coupled to the at least one processing element for selecting a column data set received by the multiplier based on matching a column data set index with a row data set index while operating in the second mode.

US Pat. No. 10,509,829

CONTEXTUAL SEARCH USING NATURAL LANGUAGE

MICROSOFT TECHNOLOGY LICE...

1. A method performed on a device of a plurality of devices associated with a device user for facilitating a search for content using contextual references, comprising:monitoring user interactions with the device of the plurality of devices;
identifying content exposed by the device based on the monitored user interactions;
using the identified content from the monitored user interactions, determining contextual reference tags for respective pieces of content, the contextual reference tags indicating that the respective pieces of content were exposed on the device of the plurality of devices;
applying and associating the determined contextual reference tags to the respective pieces of content, the contextual reference tags including an identification of specific devices on which the respective pieces of content were exposed;
exposing a user interface supporting natural language inputs for the search from the device user;
receiving the natural language inputs from the device user through the user interface, wherein the natural language inputs include an identification of a device on which the device user accessed content;
parsing the received natural language inputs for contextual references, the contextual references including the identified device and one or more of time, date, event, location, schedule, activity, or contact;
performing the search for content using the contextual reference tags and the received contextual references; and
providing results of the search, the search results identifying content matching at least one or more of the parsed contextual references for the identified device.

US Pat. No. 10,509,821

DATA CAPTURE AND IDENTIFICATION SYSTEM AND PROCESS

NANT HOLDINGS IP, LLC, C...

1. A mobile system that performs object recognition, comprising:at least one data capture device;
a computer system programmed to:
store reference characteristics corresponding to a plurality of target objects and object information associated with each of the plurality of target objects;
receive, from the at least one data capture device, digital data of a scene captured by the at least one data capture device, the digital data comprising at least one of image data and position data related to a digital representation of at least one real-world object within the scene;
derive salient characteristics for the at least one real-world object based on the digital representation including the position data;
identify the at least one real-world object as at least one target object among the plurality of target objects based on the derived salient characteristics and the stored reference characteristics;
retrieve the object information associated with the identified at least one target object; and
execute a software process based on the object information.

US Pat. No. 10,509,800

VISUALLY INTERACTIVE IDENTIFICATION OF A COHORT OF DATA OBJECTS SIMILAR TO A QUERY BASED ON DOMAIN KNOWLEDGE

Hewlett-Packard Developme...

1. A computer system comprising:a memory storing a database; and
a computer processor communicatively coupled to the memory and configured to:
access a plurality of data objects in the database, each data object comprising a plurality of numerical components, wherein each component represents a data feature of a plurality of data features;
identify, for each data feature, a feature distribution of the numerical components associated with the data feature;
select a sub-plurality of data features of a query object, wherein a given data feature is selected if the component representing the given data feature is a peak for the feature distribution of the given data feature;
determine, for the query object and a data object, a similarity measure based on the sub-plurality of the data features, the similarity measure indicative of data features common to the query object and the data object;
provide, via an interactive graphical user interface, an interactive visual representation of a distance histogram representing the feature distributions of the plurality of data features;
iteratively process, based on the interactive distance histogram, selection of a sub-plurality of the data features, the selection based on domain knowledge; and
identify, based on the similarity measures, a cohort of data objects similar to the query object.

US Pat. No. 10,509,796

APPARATUS FOR VISUALIZING DATA AND METHOD FOR USING THE SAME

ELECTRONICS AND TELECOMMU...

1. An apparatus for visualizing data, comprising:a behavior information collection unit for executing an application from which information is to be collected and collecting behavior information from a process of the executed application;
a behavior feature extraction unit for extracting behavior features in an order in which the behavior information is called;
a behavior sequence generation unit for generating a behavior sequence by arranging the behavior features in chronological order; and
a behavior sequence visualization unit for visualizing the behavior sequence as a 3D sequence object.

US Pat. No. 10,509,779

SELF-CLEANING TOKEN VAULT

Visa International Servic...

1. A method comprising performing by a computer system:receiving, over a first network communications channel, a plurality of token generation request messages from one or more token requestors;
causing a plurality of tokens to be generated and stored in a token vault managed by the computer system, wherein a first token is generated in response to a first token generation request message from a first token requestor, wherein the first token is stored in the token vault after being generated, wherein a copy of the first token is sent to and stored on a device of the first token requestor;
associating a first expiration threshold and a first level flag having a first level value with the first token,
wherein a level flag has one of a plurality of level values, wherein a level value indicates a respective set of one or more modifiable rules for managing an associated token in the token vault;
storing the first level flag having the first level value and the first expiration threshold in association with the first token as a first entry at the token vault;
managing the plurality of tokens stored in the token vault using the level values of the level flags corresponding to the tokens, wherein the managing includes:
identifying that the first token has not expired based on a first set of one or more modifiable rules corresponding to the first level value of the first level flag, wherein applying the first set of one or more modifiable rules results in a store action for the first level value of the first token;
receiving, over the first network communications channel, an instruction to modify the first set of one or more modifiable rules corresponding to the first level value of the first level flag from the first token requestor;
modifying the first set of one or more modifiable rules into a modified first set of one or more modifiable rules based on the instruction, wherein applying the modified first set of one or more modifiable rules results in a delete action for the first token; and
after modifying:
identifying that the first token has expired based on the modified first set of one or more modifiable rules corresponding to the first level value of the first level flag; and
automatically removing the first token from the token vault in response to identifying that the first token has expired and based on the first level value of the first level flag, thereby removing all elements of the first entry associated with the first token from the token vault.

US Pat. No. 10,509,778

REAL-TIME TRANSACTIONALLY CONSISTENT CHANGE NOTIFICATIONS

Google LLC, Mountain Vie...

1. A method comprising:executing, by data processing hardware, an initial instance of a change log process for a distributed system, each instance of the change log process configured to store, in at least one change log cache of memory hardware in communication with the data processing hardware, a transaction history of transactions executed on the distributed system, wherein the at least one change log cache is non-durable and shardable in the memory hardware;
receiving, at the data processing hardware, transaction requests for executing corresponding transactions on the distributed system;
determining, by the data processing hardware, a change log load based on a number of the received transaction requests;
when the change log load satisfies a threshold load, executing, by the data processing hardware, at least one subsequent instance of the change log process;
after executing the at least one subsequent instance of the change log process, determining, by the data processing hardware, whether the change log load of the change log process, based on the number of received transaction requests, dissatisfies the threshold load;
determining, by the data processing hardware, whether multiple instances of the change log process are executing; and
when multiple instances of the change log process are executing and when the change log load of the change log process dissatisfies the threshold load:
ceasing, by the data processing hardware, execution of the at least one subsequent instance of the change log process; and
merging, by the data processing hardware, the transaction history of the initial instance of the change log process and the transaction history of the at least one subsequent instance of the change log process.

US Pat. No. 10,509,774

SECURE CONTAINERIZED USER SPECIFIC ISOLATED DATA STORAGE

Red Hat, Inc., Raleigh, ...

1. A system of instantiating secure databases, the system comprising:a memory;
a database schema provider;
a schema compatible with a plurality of databases;
a plurality of accounts, including a first account and a different second account; and
one or more processors communicatively coupled to the memory wherein the one or more processors:
instantiate a first isolated guest, including a first account specific database of the plurality of databases on the first isolated guest, wherein the first isolated guest includes at least a first lower storage layer that is write-protected and a first upper storage layer;
add the schema to the first account specific database, wherein the schema is write-protected;
receive a first database command from the first account directly or from a first application the first account is accessing;
authenticate the first account with the first isolated guest by using first login credentials of the first account and first stored account data of the first account;
save a first change to the first account specific database in the first upper storage layer based on executing the first database command;
instantiate a second isolated guest, including a second account specific database of the plurality of databases on the second isolated guest, wherein the second isolated guest includes at least a second lower storage layer that is write-protected and a second upper storage layer;
add the schema to the second account specific database, wherein the schema is write-protected;
receive a second database command from the second account directly or from a second application the second account is accessing;
authenticate the second account with the second isolated guest by using second login credentials of the second account and second stored account data of the second account; and
save a second change to the second account specific database in the second upper storage layer based on executing the second database command.

US Pat. No. 10,509,773

DBFS WITH FLASHBACK ARCHIVE

ORACLE INTERNATIONAL CORP...

1. A method comprising:accessing a plurality of files stored in a database table through an application programming interface (API) that supports access primitives, said access primitives including creating a file, opening a file, and reading a file,
wherein said database table is stored in a database managed by a database server,
wherein said files include a particular file;
in response to executing database transactions that make changes to the particular file, storing undo records in an undo tablespace in the database, said undo records recording information usable to undo said changes;
archiving said undo records into a historical data tablespace in the database;
receiving a file operation request to perform on the particular file;
in response to receiving said file operation request:
generating a particular database query that conforms to SQL (“Structure Query Language”) to generate a set of version identifiers for the particular file, the particular database query being executable on the historical data tablespace with respect to a point in time in the past, said point in time being specified by a session context variable or as a parameter specified by the particular database query; and
executing the particular database query thereby generating said set of version identifiers of the particular file, each version identifier of said set of version identifiers identifying a respective version of said particular file.

US Pat. No. 10,509,772

EFFICIENT LOCKING OF LARGE DATA COLLECTIONS

Google LLC, Mountain Vie...

1. A computer-implemented method for updating a database that includes a plurality of database columns that each include a plurality of entries, each entry storing a respective field and value, the method comprising:associating exactly one lock of a plurality of locks with each entry of the plurality of entries, wherein each lock is associated with one or more entries and each entry is associated with exactly one lock, wherein the database has a distribution of memory accesses in which some entries are updated more frequently than other entries, and wherein memory accesses made according to the distribution to the values of entries are uniformly distributed over the locks;
associating a respective update aggregation rule to each lock of the plurality of locks; and for each lock:
accumulating a plurality of updates to the database entries associated with the lock until the update aggregation rule associated with the lock is satisfied, wherein application of the accumulated updates to the database entries associated with the lock is delayed until the update aggregation rule associated with the lock is satisfied, and then
acquiring the lock and updating the database by applying the accumulated plurality of updates to the entries associated with the lock,
wherein the update aggregation rules comprise a first rule that is satisfied when (i) a predefined number of updates have been made to database entries associated with the lock, (ii) a predefined number of updates have been made to values associated with a particular feature associated with the lock, (iii) a predetermined amount of time has passed, or (iv) a generated random number satisfies a condition of being greater than or less than a predetermined threshold value.

US Pat. No. 10,509,770

HEURISTIC INTERFACE FOR ENABLING A COMPUTER DEVICE TO UTILIZE DATA PROPERTY-BASED DATA PLACEMENT INSIDE A NONVOLATILE MEMORY DEVICE

Samsung Electronics Co., ...

1. A method for providing an interface for enabling a computer device to utilize data property-based data placement inside a nonvolatile memory device, the method comprising:executing a software component at an operating system level in the computer device that monitors update statistics of data item modifications into the nonvolatile memory device, including one or more of update frequencies for at least a portion of the data items, accumulated update and delete frequencies specific to each file type, and an origin of* the data item;
storing, by the software component, the update statistics for the data items and data item types in a database; and
intercepting all operations, including create, write, and update performed by applications to the data items, and automatically assigning a data property identifier to each of the data items based on current update statistics in the database, such that the data items and assigned data property identifiers are transmitted over a memory channel to the nonvolatile memory device for storage, the software component assigning the data property identifiers to the data items based on one or more data properties indicating data similarity, including at least one of data type, data size, logical block address (LBA) ranges, LBA access patterns, and a physical data source.

US Pat. No. 10,509,758

EMULATED SWITCH WITH HOT-PLUGGING

Amazon Technologies, Inc....

1. A Peripheral Component Interconnect (PCI)-based peripheral device, comprising:an integrated circuit configured to execute an emulation module;
a memory including a plurality of emulation configurations; and
a management circuit configured to:
configure the emulation module to include an emulated PCI switch, wherein configuring the emulation module includes using a PCI switch configuration from the plurality of emulation configurations, wherein the emulated PCI switch includes an emulated upstream bridge and a plurality of emulated downstream bridges;
receive a request from a host device for a new PCI endpoint device;
select an emulation configuration from the plurality of emulation configurations that corresponds to the new PCI endpoint device;
instruct the emulation module to generate the new PCI endpoint device, wherein the emulation module generates the new PCI endpoint device using the selected emulation configuration, and wherein the emulation module attaches the new PCI endpoint device to a particular downstream bridge from the plurality of emulated downstream bridges
initiate a PCI hot-plug procedure for adding the new PCI endpoint device, wherein initiating the PCI hot-plug procedure includes sending an interrupt to the host device;
receive a request for information about the new PCI endpoint device from the host device;
direct the request for information to the emulated upstream bridge;
receive a response from the emulated upstream bridge, wherein the response includes a unique identifier for the new PCI endpoint device, wherein the unique identifier corresponds in part to the particular downstream bridge; and
transmit the response to the host device.

US Pat. No. 10,509,748

MEMORY SHARING FOR APPLICATION OFFLOAD FROM HOST PROCESSOR TO INTEGRATED SENSOR HUB

Intel Corporation, Santa...

1. A processor-implemented method for memory sharing, the method comprising:allocating, by a host processor, a shared region of a first memory, the shared region to be accessed by the host processor and by an integrated sensor hub (ISH) that includes a second processor, in connection with the execution of a shared application on the host processor and the second processor, the shared application being a location, mapping, and/or navigation application;
storing, by the host processor, a location database in the shared region, wherein the location database is divided into a plurality of segments, each segment associated with a geographic location defined by index values;
transferring, by the second processor, one or more of the plurality of segments between the shared region and a second memory associated with the second processor, wherein the transferring comprises one or more direct memory access (DMA) transfers; and
executing, by the second processor, a portion of the shared application based on the one or more of the plurality of segments stored in the second memory.

US Pat. No. 10,509,741

CALIBRATION PROTOCOL FOR COMMAND AND ADDRESS BUS VOLTAGE REFERENCE IN LOW-SWING SINGLE-ENDED SIGNALING

Rambus Inc., Sunnyvale, ...

1. A memory device comprising:a command and address (CA) pin; and
a receiver coupled to the CA pin, wherein the receiver is to:
receive a first signal using a first reference voltage level, the first signal having a first voltage swing and a first signaling frequency;
subsequent to receiving the first signal, receive a command to calibrate a reference voltage level of the receiver and derive a second reference voltage level that is lower than the first reference voltage level, the receiver to receive a second signal, having a second voltage swing and a second signaling frequency, using the second reference voltage level, wherein the second signaling frequency is higher relative to the first signaling frequency, and wherein a magnitude of the second voltage swing is lower than a magnitude of the first voltage swing; and
wherein the receiver, in response to the command, is to receive signals of a calibration pattern used to derive the second reference voltage level.

US Pat. No. 10,509,739

OPTIMIZED READ IO FOR MIX READ/WRITE SCENARIO BY CHUNKING WRITE IOS

EMC IP Holding Company LL...

1. A computer-implemented method to prioritize input/output request transactions for a storage system, the method comprising:receiving a plurality of input/output (IO) request transactions at the storage system having a plurality of storage devices;
for each of the plurality of IO request transactions, determining a plurality of child IO requests required to complete the IO request transaction;
tagging the IO request transaction and the associated child IO requests with a unique tag identifier;
for each of the child IO requests that is a write IO request, determining an optimal write IO request size by analyzing IO sequences on an IO bus having mixed read and write IO requests at a fixed point in time to determine an optimal write IO request size for that fixed point in time so that the optimal write IO request size can be applied to a subsequent write IO request;
segmenting the write IO request into a plurality of sub-IO write requests, each having an the optimal write IO request size; and
interleaving sub-IO write requests with read IO requests for servicing to avoid impact in performance to the read IO requests for a mixed IO workload.

US Pat. No. 10,509,689

METHOD FOR PROCESSING APPLICATION AND TERMINAL

BEIJING KINGSOFT INTERNET...

1. A method for processing an application, comprising:detecting an increase in a temperature of a central processing unit (CPU) over time using a temperature sensor;
searching for an application with a first CPU occupancy rate exceeding a corresponding normal numerical range if it is detected that a second CPU occupancy rate is also in an increase state, wherein it is determined that the application is an application that causes a temperature increase of the CPU; and
stopping the application that causes the temperature increase of the CPU;
wherein before searching for the application with the first CPU occupancy rate exceeding the corresponding normal numerical range, the method further comprises:
acquiring data of consuming a system resource by each of a plurality of applications and reporting the data to a server for each of a plurality of scenarios;
calculating a normal numerical range of consuming the system resource by each application in each scenario based on the data; and
receiving the normal numerical range of consuming the system resource by each application in each scenario from the server.

US Pat. No. 10,509,678

MANAGEMENT SYSTEM FOR MANAGING COMPUTER SYSTEM

Hitachi, Ltd., Tokyo (JP...

1. A management method of a computer system that includes multiple resources of multiple resource types, the method comprising:collecting metric time series data of each of the resources;
storing the metric time series data of each of the resources in a storage resource;
receiving a selection of at least one of the resources;
determining two or more of the multiple resources that are base point resources and two or more respective related resources which are related to the base point resources based on multiple pieces of resource information stored in advance in the storage resource, related information of the multiple resources stored in advance in the storage resource, and the selected at least one of the resources;
obtaining the metric time series data in a predetermined time range of the base point resources and the related resources of the base point resource from the storage resource;
collectively performing display of a graph matrix which includes a plurality of two-dimensional orthogonal coordinate system graphs arranged in a plurality of columns and a plurality of rows and which separately display the obtained metric time series data of each of the respective base point resources and the obtained metric time series data of each of the related resources of each of the respective base point resources, and a horizontal axis is a time axis and a vertical axis is a metric value axis in each of the plurality of two-dimensional orthogonal coordinate system graphs,
wherein each of the columns corresponds to a respective one of the base point resources and the related resources which are related to the respective one of the base point resources, and each of the rows corresponds to a same respective type of the obtained metric time series data.

US Pat. No. 10,509,665

FAST-BOOTING APPLICATION IMAGE

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:parsing source code of an application to determine a variation point in the source code;
causing a computer system instance to perform at least some of an executable portion of the application; and
copying, after partial but incomplete performance of the executable portion, an image of the computer system instance usable to instantiate another computer system instance to continue performance of the executable portion from a point in performance at which the image was copied, wherein the partial but incomplete performance of the executable portion is based at least in part on the variation point.

US Pat. No. 10,509,662

VIRTUAL DEVICES IN A RELIABLE DISTRIBUTED COMPUTING SYSTEM

Scale Computing, Indiana...

1. A method, in a fault-tolerant distributed computing system including one or more virtual machines, each particular virtual machine having one or more user applications with access to one or more virtual storage devices, of providing degrees of reliability associated with each virtual storage device in the fault-tolerant distributed computing system, each degree of reliability being selected by a user application for a portion of an associated virtual storage device, the method including steps of:emulating the virtual storage devices using one or more real storage devices, the real storage devices being subject to potential failure, and the virtual storage devices being maintained at the defined degrees of reliability;
receiving and responding to messages from the user applications executing at virtual machines, the messages from a selected user application including setting metadata defining a degree of reliability associated with said portion of a virtual storage device for that virtual machine;
maintaining metadata indicating a first and second failure group, each failure group indicating at least a portion of a real storage device, the metadata including which cross-products of failure groups and virtual storage devices are assigned for use by real storage devices, each virtual storage device disposed to be maintained across more than one failure group; and
maintaining those portions of the virtual storage devices at associated portions of those real storage devices, wherein no two or more portions of each virtual storage device is assigned to the same one of first set of failure groups and to the same one of the second set of failure groups.

US Pat. No. 10,509,657

FORCED DEVICE REINITIALIZATION WITHOUT MANDATORY RESTART

NCR Corporation, Atlanta...

1. A method comprising:experiencing, by a first device, an unexpected device reset;
receiving, by the first device, a first data communication;
responding, by the first device, to the first data communication with a second data communication identifying a state of the first device as a reset state;
receiving, by the first device in response to the second data communication, a third data communication including data to alter the state of the first device from the reset state to a programmed state;
implementing the data of the third data communication to place the first device in the programmed state; and
wherein the first device is not a plug-and-play device.

US Pat. No. 10,509,650

SELF-LEARNING AUTOMATED TECHNIQUES FOR DETECTING THE USAGE OF SOFTWARE PACKAGES

International Business Ma...

1. A method for detecting a usage of a software package installed on a computer system, the method comprising:determining at least one first file system path related to a specific software package;
determining a second file system path associated with a computing process running on the computer system;
detecting that the specific software package is used on the computer system based on comparing the first file system path with the second file system path;
determining that a further computing process running on the computer system cannot be detected by comparing a third file system path associated with the further computing process and the at least one first file system path with each other, and
identifying a software package used on the computer system based on behavioral signature matching.

US Pat. No. 10,509,643

DATA PROCESSING WITH A PLANE COMPUTER

1. A system comprising:a first line of code or data;
a first plane, wherein said first plane being configured to receive said first line of code or data;
a first processor, in which said first processor is running a first operating configuration, wherein said first processor is configured to, at least read and execute or process said first line of code or data;
a second line of code differing from said first line of code or data;
a second plane, wherein said second plane being configured to receive said second line of code or data;
a second processor, in which said second processor is running a second operating configuration different from said first operating configuration, wherein said second processor is configured to, at least read and execute or process said second line of code separately and simultaneously or in parallel from said first line of code or data;
a third line of code differing from said first and second line of code or data;
a third plane, wherein said third plane being configured to receive said third line of code or data; and
a third processor, in which said third processor is running a third operating configuration different from said first and second operating configuration, wherein said third processor is configured to, at least read and execute or process said third line of code separately and simultaneously from said first and second line of code or data, wherein said processing of said first, second, and third lines of code or data separately and simultaneously or in parallel with separate processors is configured to prevent an external source from reading or hacking said lines of code or data, and wherein said processing of said first, second, and third lines of code or data separately and simultaneously with separate processors running a first, second, and third operating configuration, is configured to further prevent or alleviate a hacking of said system since each processor is running different operating configurations in addition to running different lines of code or data separately.

US Pat. No. 10,509,633

BASE EDITOR COMPONENT IN A WEB APPLICATION BUILDER FRAMEWORK

salesforce.com, inc., Sa...

1. A system comprising:a database system implemented using a server system comprising one or more hardware processors, the database system configurable to cause:
providing for interaction with a database identifying a plurality of web application builder components configured to be used to build components of a web application and further configured to be reusable within a server-hosted web application builder framework, each of the web application builder components comprising a respective one or more attributes;
processing a first user request to add to or modify one or more attributes of a first one of the web application builder components;
retrieving, in response to the first user request, a metadata model associated with the first web application builder component, the metadata model comprising one or more nodes corresponding to the one or more attributes of the first web application builder component;
providing user interface data to a client device, the user interface data capable of being processed to cause display of a user interface comprising one or more user interface elements for displaying and modifying the metadata model;
modifying the metadata model by adding or editing one or more nodes with respect to the metadata model based on user input received from the client device and associated with the user interface;
storing the modified metadata model in one or more server databases; and
providing web application builder data to the client device, the web application builder data capable of being processed to cause display of the web application builder framework for constructing web application builders, the web application builder framework implementing at least the first web application builder component with the modified metadata model.

US Pat. No. 10,509,630

RANDOM NUMBER GENERATION APPARATUS, RANDOM NUMBER GENERATION METHOD AND PROGRAM

NIPPON TELEGRAPH AND TELE...

1. A random number generation apparatus for generating a random number on a factor ring which is used for electronic cryptography system, the random number generation apparatus comprises a processing circuitry and a memory that stores a program, and when the processing circuitry executes the program, the processing circuitry is configured to implement:a storage;
a binary random number generating unit generating a first sequence that comprises values of digits of a uniform random number represented by a binary number as elements and stores the first sequence in the storage;
a random number acquiring unit obtaining, from the storage, the first sequence;
a mask generator receiving an input of Mersenne prime numbers and generating a second sequence that comprises values of digits of one or more Mersenne numbers represented by one or more binary numbers and a zero value as elements; and
a logical product arithmetic unit obtaining a third sequence that is results of elementwise logical product operation between the first sequence and the second sequence being received from the mask generator,
wherein
the first sequence comprises a first subsequence; a second subsequence comprised in the second sequence indicates any of the Mersenne numbers; the third sequence comprises a third subsequence that is results of elementwise logical product operation between the first subsequence and the second subsequence; and the processes of the random number acquiring unit and the logical product arithmetic unit are executed again when the second subsequence matches the third subsequence, otherwise the logical product arithmetic unit outputs the third sequence including the random number on the factor ring.

US Pat. No. 10,509,629

CONTROL DEVICE

Kabushiki Kaisha Toshiba,...

1. A control device comprising:a first circuit to perform proportional control and integral control, on the basis of a difference between an indicating value input from an outside and a feedback value output from a controlled object in accordance with the indicating value;
a second circuit to extract change in manipulated variable input to the controlled object in accordance with the indicating value and to generate and output a reverse bias value that causes reverse change to the extracted change; and
an adder to add an output value of the first circuit to the reverse bias value, and to output an addition value obtained by the addition as the manipulated variable.