US Pat. No. 10,170,936

WIRELESS POWER RECEIVER AND POWER SUPPLY APPARATUS USING THE SAME

Samsung Electro-Mechanics...

1. A wireless power receiver of a wearable device, the wireless power receiver comprising:a core part disposed in the wearable device to be adjacent to a surface of an internal part of the wearable device;
a magnetic sheet disposed in the wearable device between the core part and the surface of the internal part;
a receiving coil disposed in the wearable device and wound around the core part; and
a power circuit configured to provide power received from the receiving coil to the wearable device.

US Pat. No. 10,170,934

ELECTROMAGNETIC-COUPLING-MODULE-ATTACHED ARTICLE

MURATA MANUFACTURING CO.,...

1. An article comprising:a metal portion including at least one main surface; and
a power supply circuit including a coil-shaped electrode; wherein
the coil-shaped electrode of the power supply circuit is disposed adjacent to the at least one main surface of the metal portion such that a portion of the coil-shaped electrode overlaps the at least one main surface of the metal portion and another portion of the coil-shaped electrode does not overlap the at least one main surface of the metal portion when viewed in a direction perpendicular to the at least one main surface of the metal portion;
the coil-shaped electrode is disposed on only one side of the at least one main surface of the metal portion;
the coil-shaped electrode of the power supply circuit is magnetically coupled to the at least one main surface of the metal portion; and
the metal portion is configured to perform at least one of transmitting a power supplied from the power supply circuit, and receiving a power and supplying the power to the power supply circuit.

US Pat. No. 10,170,933

NON-CONTACT TYPE POWER SUPPLYING APPARATUS AND NON-CONTACT TYPE POWER SUPPLYING METHOD

Samsung Electro-Mechanics...

1. A non-contact type power supplying apparatus comprising:a first transmitting coil configured to output a detection signal through the first transmitting coil, wherein the detection signal is a plurality of discrete pulses;
a second output comprising a second transmitting coil and configured to output a wake-up signal through the second transmitting coil or transmit power through the second transmitting coil using a non-contact type method, wherein the wake-up signal is a plurality of discrete pulses; and
a controller configured to determine whether or not a first object has approached by using a variation of an impedance of the first transmitting coil, control the second output to output the wake-up signal, determining whether or not an approached first object is a first power receiving apparatus by using a first response signal outputted from the approached first object in response to the wake-up signal, control the second output to transmit power to the first power receiving apparatus when the approached first object is determined to be the first power receiving apparatus, determine whether or not a second object has approached by using a variation of the impedance of the first transmitting coil while the second output transmits the power to the first power receiving apparatus, and control the second output to stop the transmission of the power and output the wake-up signal when it is determined that the second object has approached,
wherein the amplitude of either one or both of the detection signal pulses and the wake-up single pulses varies sequentially from a low level to a high level, and
wherein the first output outputs the detection signal while the second output transmits the power to the first power receiving apparatus.

US Pat. No. 10,170,931

ELECTRIC POWER CONTROL SYSTEM

NEC Corporation, Tokyo (...

1. An electric power control system connected to an electric power supplying unit for supplying electric power and a load unit for accepting supply of electric power and consuming the electric power, the electric power control system comprising:a supplied energy acquiring unit for acquiring a supplied energy, the supplied energy being an amount of electric power supplied from the electric power supplying unit;
a consumed energy acquiring unit for acquiring a consumed energy, the consumed energy being an amount of electric power consumed by the load unit; and
an electric power supply and demand controlling unit for, depending on a total supplied energy and a total consumed energy, transmitting and receiving electric power to and from another device to change the total supplied energy, the total supplied energy being a total of the acquired supplied energy, and the total consumed energy being a total of the acquired consumed energy,
wherein the electric power supply and demand controlling unit calculates an electric power supply and demand difference representing a difference between the total supplied energy and the total consumed energy, and transmits and receives electric power to and from another device to change the total supplied energy, thereby executing control so that the electric power supply and demand difference falls within a predetermined range set in advance,
the system further comprising a plurality of electric power supply and demand controlling units, the electric power supply and demand controlling units each belonging to any of groups determined in advance, and the electric power supply and demand controlling units each targeting the electric power supplying unit and/or the load unit set to belong to its group for control of electric power supply and demand,
wherein the electric power supply and demand controlling units each transmit and receive electric power to and from another device placed outside its group to change the total supplied energy in its group, thereby making the electric power supply and demand difference in its group fall within a predetermined range set in advance,
wherein the electric power supply and demand controlling units each transmit and receive electric power to and from another of the electric power supply and demand controlling units and make the electric power supply and demand difference in its group fall within a predetermined range set in advance, the other electric power supply and demand controlling unit belonging to another of the groups, and
wherein the electric power supplying unit includes an electric power system which supplies a predetermined energy of electric power and a generator which generates and supplies electric power; and
the electric power supply and demand controlling unit belonging to each of a plurality of distribution substations to which different electric power supplying units and/or different load units belong, respectively, transmits and receives electric power to and from another of the electric power supply and demand controlling units and thereby executes control so that a sum of supplied energy in the plurality of distribution substations becomes minimum, the other electric power supply and demand controlling unit belonging to another of the distribution substations.

US Pat. No. 10,170,930

ELECTRICAL POWER RESTORATION SYSTEM FOR A CIRCUIT ASSEMBLY AND METHOD

Runway Energy, LLC, San ...

1. An electrical power restoration system for a circuit assembly having a circuit breaker, an electrical load and a circuit conditioner, the circuit conditioner being configured to condition electrical current flowing through the circuit assembly, the electrical power restoration system comprising:a circuit controller that is positioned along the circuit assembly between the circuit breaker and the electrical load, the circuit controller being electrically connected to the circuit conditioner, the circuit controller selectively controlling activation of the circuit conditioner;
a first hot conductor that selectively conducts AC power from the circuit breaker to the circuit controller; and
a second hot conductor that conducts AC power from the circuit controller to the electrical load only when the first hot conductor conducts AC power from the circuit breaker to the circuit controller.

US Pat. No. 10,170,921

METHODS AND SYSTEMS FOR EFFICIENT BATTERY CHARGING AND USAGE

POWERPLUG LTD., Tel Aviv...

1. A method for charging a battery associated with a device, wherein the device is configured to draw power from either one of a battery or an external power source, the method comprising the following operations performed by one or more processors:receiving a signal from an external information service, the signal including power rate data reflecting a value at which power is purchasable at a particular time;
determining a usage threshold that reflects a minimum battery level in which a device draws power from the battery and a charge threshold that reflects a maximum battery level to which the device charges the battery from power drawn from the external power source corresponding to the power rate data and a device class of the device; and
enabling the device to draw power from the battery as a function of whether a charge level associated with the battery exceeds the usage threshold, and enabling the device to charge the battery with power drawn from the external power source as a function of whether the charge level is below the charge threshold and whether the external power source is available.

US Pat. No. 10,170,920

SYSTEM AND METHOD FOR ENERGY MANAGEMENT WITHIN A GROUP OF DEVICES

Symbol Technologies, LLC,...

9. A system, comprising:a group of charging stations each of which includes a docking connection, wherein each charging station in the group comprises:
a processor for identifying the docking connection;
a transceiver, responsive to identifying the docking connection, configured to transmit information to other charging stations in the group and receive at least one set of information transmitted from another charging station in the group, wherein each charging station generates a list using the information transmitted by the charging station and the at least one set of information received by the charging station; and
a ranking component configured to at least one of filter, sort, and rank entries in the list, wherein each entry in the list is associated with a charging station with a docking connection and in the group of charging stations,
wherein each charging station in the group is configured to determine that an entry in the list that is associated with the charging station is ranked at a predefined position in the list and provide an indication of the predefined position.

US Pat. No. 10,170,915

ENERGY MANAGEMENT SYSTEM, ENERGY MANAGEMENT METHOD AND COMPUTER PROGRAM

SUMITOMO ELECTRIC INDUSTR...

1. A non-transitory computer readable storage medium storing a computer program for causing a computer to operate as an energy management system for managing an operation state of an electric power device including a storage battery connected to a power grid, the computer program comprising:a first step of acquiring static parameters to be used in controlling the electric power device; and
a second step of controlling the electric power device based on the acquired static parameters, wherein
the static parameters acquired in the first step are commonly used irrespective of whether the storage battery is circulation type or non-circulation type, and the static parameters are at least five types of parameters including:
a storage battery capacity, being an energy capacity of the storage battery that can be delivered from a fully charged state;
dischargeable power, being a limit value of power that the storage battery can discharge;
chargeable power, being a limit value of power that the storage battery can be charged;
discharge efficiency, being a proportion of output power relative to stored power when the storage battery discharges; and
charge efficiency, being a proportion of stored power relative to input power when the storage battery is charged.

US Pat. No. 10,170,914

VOLTAGE SOURCE CONVERTER (VSC) CONTROL SYSTEM WITH ACTIVE DAMPING

ABB SCHWEIZ AG, Baden (C...

1. A Voltage Source Converter control system for active damping of a resonance oscillation in a Voltage Source Converter (VSC), the resonance oscillation having a frequency which is above a synchronous frequency but less than two times said synchronous frequency, the control system comprising:a first Phase-Locked Loop (PLL) having a first PLL controller; and
a second PLL having a second PLL controller, the second PLL controller having a gain which is lower than a gain of the first PLL controller,
wherein the control system is arranged such that an imaginary part of an active damping signal is obtainable from the second PLL; and
wherein the second PLL is configured for having a closed-loop bandwidth which is less than the frequency of the resonance oscillation to be dampened in a synchronous dq frame.

US Pat. No. 10,170,912

DYNAMIC HYBRID CONTROL

Kongsberg Maritime AS, K...

1. A system for controlling a power plant in a marine vessel, the power plant comprising;at least one switchboard including at least one switching device, and at least one consumer; and
at least one power generator supplying electrical energy to the at least one switchboard; and
at least one energy storage device coupled to the switchboard capable of storing excess energy from the switchboard, and capable of sourcing the stored energy through the switchboard to the at least one consumer;
wherein the at least one power generator, the at least one energy storage device, and the at least one consumer are coupled to a Dynamic Hybrid Control (DHC) unit, the control unit controlling the flow of energy on the at least one switchboard;
the DHC unit further comprising;
measurement means for monitoring predetermined power plant and vessel related parameters; and
computational means for computing and predicting power and energy requirements in the power plant for varying time spans into the future, based upon data including, the parameters monitored by the measurement means, pre-determined models, and expected energy flow trends related to the at least one power generator, the at least one energy storage element, and the at least one consumer,
wherein the system utilizes the power and energy requirements predicted by the computational means for pre-planning and allocating of power and energy between the at least one power generator, the at least one energy storage element and the at least one consumer for minimizing transients, including voltage, frequency variations in the power plant and load variations on the at least one power generator due to the transients; and,
wherein the system transmits feedforward signals for functions including, the prediction, the pre-planning and the allocation; the feedforward signals including,
power demand;
adapting energy storage devices for handling the transients;
adapting set-point of the at least one power generator; and setting load limitation on the at least one consumer.

US Pat. No. 10,170,905

ELECTRONIC SWITCHING AND PROTECTION CIRCUIT WITH WAKEUP FUNCTION

INFINEON TECHNOLOGIES AG,...

1. An electronic circuit, comprising:an electronic switch comprising a load path; and
a control circuit configured to drive the electronic switch,
wherein the control circuit is configured to operate in one of a first operation mode and a second operation mode based at least on a level of a load current of the electronic switch,
wherein in the first operation mode the control circuit is configured to generate a first protection signal based on a current-time-characteristic of the load current and drive the electronic switch based on the first protection signal, and
wherein the control circuit is configured to generate a status signal such that the status signal has a wakeup pulse when the operation mode changes from the second operation mode to the first operation mode and, after the wakeup pulse, a signal level representing a level of the load current.

US Pat. No. 10,170,901

STACKED BUS ASSEMBLY WITH STEPPED PROFILE

Eaton Intelligent Power L...

1. A bus bar assembly, the bus bar assembly comprising:a stack of bus bars configured to be attached to a surface and insulated from one another, wherein the bus bars have aligned longitudinal centerlines and respective different widths in a direction perpendicular to the longitudinal centerlines and parallel to the surface that decrease along a direction perpendicular to the surface, wherein the stack of bus bars comprises:
a first bus bar having a first width;
a second bus bar overlying the first bus bar and having a second width less than the first width; and
a third bus bar overlying the second bus bar and having a third width less than the second width.

US Pat. No. 10,170,900

ELECTRICAL CONNECTION BOX

AutoNetworks Technologies...

1. An electrical connection box comprising:a bus bar;
a case to which the bus bar is fixed;
a terminal that is connected to the bus bar;
a fixing member that fixes a connection portion at which the terminal and the bus bar are connected to each other; and
a base member that holds the fixing member, the base member disposed on a portion of the case and underneath the connection portion;
wherein the fixing member and the base member are disposed at a position at which the fixing member and the base member overlap the connection portion of the bus bar, and when the connection portion at which the terminal and the bus bar are connected to each other is fixed, the base member moves in a direction in which the base member comes into contact with the bus bar, wherein an under surface of the base member is spaced apart and free from the portion of the case.

US Pat. No. 10,170,899

METHOD FOR CONNECTING AT LEAST TWO ELECTRIC CABLES AND CONNECTION DEVICE, KIT, ELECTRIC MACHINE AND ASSOCIATED VEHICLE

1. A connecting device including electric cables connected to an electric machine of a vehicle, said connecting device comprising:at least two contact elements;
a housing having a first housing wall provided with at least two first openings for allowing passage of the cables in a first direction and in a straight line within the housing to meet the contact elements for electrical connection therewith in one-to-one correspondence, and a second housing wall provided with at least two second openings for allowing passage of the cables in a second direction oriented in a straight line within the housing;
wherein only one of the cables directly meets one of the contact elements for electrical connection therewith, while a conductor bar electrically connects the other one of the cables to the other one of the contact elements; and
an isolating support provided in the housing,
said conductor bar being placed on the isolating support and on the other one of the contact elements and one side of the conductor bar connected with the other one of the contact elements, and the other one of the cables being attached to the conductor bar to establish electrical contact via the conductor bar,
wherein the electric cables are connected to the electric machine of the vehicle.

US Pat. No. 10,170,891

ALGAINP-BASED SEMICONDUCTOR LASER

USHIO OPTO SEMICONDUCTORS...

1. A semiconductor laser chip comprising:an n-type cladding layer having a composition of (AlxnGa1-xn)0.5In0.5P where 0.9 a p-type cladding layer having a composition of (AlxpGa1-xp)0.5In0.5P where 0.92 an active layer provided between the n-type cladding layer and the p-type cladding layer,
wherein the Al composition ratio xp of the p-type cladding layer and the Al composition ratio xn of the n-type cladding layer satisfies a relationship of xn wherein a difference between the Al composition ratio xp of the p-type cladding layer and the Al composition ratio xn of the n-type cladding layer satisfies a relationship of 0.03<=xp?xn<=0.06.

US Pat. No. 10,170,878

JUNCTION BOX WITH AN INTEGRATED CONNECTION CIRCUIT

1. A junction box with an integrated connection circuit comprising:a junction box configured to accept external wiring with a common, neutral and a ground;
said junction box is an adjustable electrical box;
said junction box connects said external wiring to an internal circuit;
said internal circuit is an internal distribution receptacle;
said internal distribution receptacle is positionable within said adjustable electrical box to provide spacing for said external wiring within said adjustable electrical box and behind said internal distribution receptacle;
said adjustable electrical box has two independent racks integrated into opposing sides of said adjustable electrical box;
said internal distribution receptacle has two independent springs that are configured to engage into said two independent racks whereby said internal distribution receptacle is prevented from moving further into or out of said adjustable electrical box;
said junction box having at least two mechanical securing locations that are configured to secure a user interface device to said junction box;
said user interface device is a switch or an outlet, and
said user interface device electrically connects to at least said common and said neutral.

US Pat. No. 10,170,877

CONNECTING DEVICE, ASSEMBLY THEREOF AND ASSEMBLY METHOD THEREFOR

JACKSAVIOR IP B.V., (NL)...

1. Connecting device for insertion into a connection jack, said connecting device comprising:a substantially elongated inserting member that is extending in a longitudinal direction and that is insertable into the connection jack of an electronic device, said inserting member further comprising a transverse direction extending transverse thereto, said inserting member further comprising an outer surface with at least two electrically conductive parts with insulating material arranged there between;
wherein the inserting member is configured to, by means of compression, clamping at least two wire ends between an inner wall of the least one of the at least two electrically conductive parts and an outer wall of an insulation member, mechanically and electrically connect the at least two electrically conductive parts with the at least two wire ends of a connection cable within a space enclosed by the outer surface of the inserting member, wherein the at least two wire ends of the connection cable extend directly from the connection cable into the inserting member without any electrical connection between exiting the connection cable and entering the inserting member, and all of the electrical connections between wires extending from the connection cable and the at least two electrically conductive parts take place within the inserting member; and
the inserting member is configured such that wires of the connection cable branch out in different directions inside the space enclosed by the outer surface of the inserting member.

US Pat. No. 10,170,859

INTERFACE APPARATUS, INTERFACE UNIT, PROBE APPARATUS, AND CONNECTION METHOD

TOKYO ELECTRON LIMITED, ...

1. An interface apparatus comprising:a connector configured to be connected to an external connector; and
a support part configured to support the connector,
wherein the support part includes:
a base member;
a holder configured to be connected to the base member, having a hollow section defined therein, and configured to hold the connector;
a pushing member interposed between the base member and the holder, and configured to push the holder toward the external connector; and
a coupling member configured to be fixed to the base member and configured to be inserted into the hollow section of the holder with a clearance applied between the coupling member and the hollow section,
wherein the coupling member is engaged with an inner wall of the hollow section in a state in which the holder is separated from the base member at a first interval by virtue of a pushing force of the pushing member, whereby the holder is fixed to the base member, and
the coupling member is separated from the inner wall of the hollow section when the base member and the holder are separated from each other at a second interval smaller than the first interval, against the pushing force, whereby the holder is freely movable relative to the base member.

US Pat. No. 10,170,858

LEVER-TYPE CONNECTOR

SUMITOMO WIRING SYSTEMS, ...

1. A lever-type connector, comprising:a housing; and
a lever mounted on the housing movably to an initial position, a first connection position and a second connection position more distant from the initial than the first connection position;
wherein:
the lever includes a deflecting portion deflectable in a moving direction of the lever;
the housing includes a projecting portion configured to start contacting the deflecting portion halfway through a movement of the lever from the initial position to the first connection position and deflect the deflecting portion until the second connection position is reached and a lever lock portion configured to hold the lever in a movable state between the first connection position and the second connection position; and
the lever includes a receiving portion configured to contact not the lever lock portion, but the projecting portion when the second connection position is reached.

US Pat. No. 10,170,857

ELECTRICAL CONNECTION DEVICE

Molex, LLC, Lisle, IL (U...

1. An electrical connection device, comprising:a receptacle connector comprising a receptacle body, a front guide-positional limiting portion, a rear guide-positional limiting portion and a first latching member, the receptacle body comprising a base, a front wall and a rear wall which extend upwardly from the base and two side walls respectively positioned on left and right sides, the base, the front wall and the rear wall cooperating to define a plug receiving space, the two side walls each being formed with a side opening communicating with the plug receiving space, the front guide-positional limiting portion comprising the front wall and a guide groove positioned to the front wall and extending along an inserting direction, the rear guide-positional limiting portion comprising the rear wall and at least one rear guide-positional limiting piece formed to the rear wall, the first latching member being provided to the front guide-positional limiting portion; and
a plug connector removably mating with the receptacle connector along the inserting direction and comprising a plug body and a second latching member, the plug body having a front wall, a rear wall, two side walls respectively positioned on left and right sides, the rear wall of the plug body being recessed to form a recessed portion, the recessed portion being formed with a guide recessed groove into which the rear guide-positional limiting piece of the receptacle connector extends, the second latching member being provided to the front wall of the plug body,
when the plug connector mates with the receptacle connector, the plug body being inserted into the plug receiving space of the receptacle body and limited between the front wall of the front guide-positional limiting portion and the rear wall of the rear guide-positional limiting portion, the second latching member of the plug connector being latched to the first latching member of the receptacle connector and limited by the front guide-positional limiting portion, the rear guide-positional limiting piece of the receptacle body extending into the guide recessed groove and the rear wall engaging with the recessed portion of the plug body, the rear wall of the plug connector being generally flush with the rear wall of the receptacle connector, the two side walls of the plug body being respectively exposed to the two side openings of the receptacle body and generally flush with the two side walls of the receptacle body.

US Pat. No. 10,170,852

METHOD FOR MANUFACTURING PLUG-TYPE CONTACTS, PLUG-TYPE CONTACT AND COMPONENT ASSEMBLY COMPRISING AT LEAST ONE PLUG-TYPE CONTACT

1. A component assembly comprising at least one contact receptacle and at least one plug-type contact for producing an electric connection, with a flat connecting body and two curved limbs having two flat sides adjoining the connecting body, wherein the connecting body and the limbs are configured as a single flat piece, wherein each limb has a press-in region and an end region with a contact portion, wherein the two limbs define a substantially almond-shaped inner contour, and wherein the contact portions of the two limbs face each other and touch in a defined manner at least in sections, wherein the plug-type contact is received in the contact receptacle by being prestressed;wherein the limbs have an attachment region for attachment to the flat connecting body,
wherein the limbs have a concave constriction at a transition between the press-in region and the attachment region, said constriction being formed by curved portions of the limbs, wherein end regions of the limbs which face the connecting body furthermore have an inner rounding which merges into an inner space defined between the limbs, and wherein the concave constriction of the limbs defines a narrow point between the inner space and the inner rounding, wherein the curved portions of the limbs are configured to touch each other at the narrow point when received in the contact receptacle, and wherein the inner space is larger than the inner rounding.

US Pat. No. 10,170,851

CONNECTOR WITH A WIRELESS COUPLER

Hewlett-Packard Developme...

1. An apparatus, comprising:a housing;
an electronic connector coupled to a back side of the housing, wherein the electronic connector is to communicate with a circuit board of an electronic device;
a pin located on a front side of the housing and in communication with the electronic connector;
a first alignment magnet on a first end of the housing;
a second alignment magnet on a second end of the housing located opposite the first end;
a first wireless transceiver chip that contacts the first alignment magnet; and
a second wireless transceiver chip that contacts the second alignment magnet.

US Pat. No. 10,170,850

ADJUSTING AN OPENING OF A CARD EDGE CONNECTOR USING A SET OF ELECTROACTIVE POLYMERS

International Business Ma...

1. An apparatus to dynamically adjust, in a card edge connector, an opening configured to receive a printed-circuit card, the apparatus comprising:the card edge connector having a first position and a second position;
a set of contacts configured to connect with a set of edges of the printed-circuit card in the second position at both a first contact location and a second contact location, wherein a first distance between the first and the second contact locations in the first position exceeds a second distance between the first and the second contact locations in the second position; and
a set of electroactive polymers configured to change thickness in response to voltages applied to electrodes positioned adjacent to opposing faces of the set of electroactive polymers, the change of thickness adjusting the set of contacts between the first position and the second position, the set of electroactive polymers including an electroactive polymer configured to control a single contact of the set of contacts.

US Pat. No. 10,170,849

CONNECTOR AND CONNECTOR ASSEMBLY WITH SLIDABLE LATCH

Molex, LLC, Lisle, IL (U...

1. A connector assembly, comprising:a first connector including: a first housing having two first wall parts extending in a longitudinal direction and opposing in a short direction, two second wall parts positioned on end parts of the two first wall parts and opposing in the longitudinal direction, and a recessed part formed on an inner side of the first wall parts and second wall parts; and a first terminal retained on the first wall parts; and
a second connector including: a second terminal for connecting to the first terminal, and a second housing retaining the second terminal, the second connector being mated to an inner side of the recessed part of the first housing; wherein:
the first connector includes: a slider supported by at least one of the two second wall parts and that can slide in the longitudinal direction; and a first metal fitting attached to at least one second wall part,
the slider can slide between a locking position where the slider locks the second connector mated to the inner side of the recessed part and a lock releasing position where the slider is separated from the second connector to an outer side in the longitudinal direction such that locking of the second connector is released,
the first metal fitting has an engaging part,
the slider has a first engageable part to which the engaging part is engaged,
at least one of the engaging part and first engageable part can elastically deform, and
movement of the slider from the locking position to the lock releasing position is restricted by engagement between the engaging part and the first engageable part, and sliding between the locking position and lock releasing position is permitted by at least one of the aforementioned parts.

US Pat. No. 10,170,843

PARABOLIC DEPLOYABLE ANTENNA

CALIFORNIA INSTITUTE OF T...

1. A deployable antenna comprising:a container;
a deployment mechanism attached to the container;
a hub within the container, configured to deploy along a longitudinal axis of the container upon activation of the deployment mechanism;
a plurality of root ribs attached to the hub and configured to rotate away from the longitudinal axis upon deployment;
a plurality of tip ribs, each tip rib attached to a corresponding root rib by a rotating hinge, the plurality of tip ribs configured to rotate away from the longitudinal axis upon deployment;
a mesh attached to the plurality of root and tip ribs;
a horn attached to the hub, the horn extending along the longitudinal axis and located centrally to the mesh;
a sub-reflector attached to the horn and configured to extend away from the horn along the longitudinal axis upon deployment; and
a waveguide attached to the hub, the waveguide being configured to fit within the horn before deployment and to remain in its pre-deployment location while the hub and the horn are extended away along the longitudinal axis upon deployment,
wherein:
the mesh, horn, root ribs, tip ribs and sub-reflector are configured to operate between 2 and 50 GHz,
and
the deployable antenna is a Cassegrain antenna optimized to operate at 35.75 GHz with a bandwidth of 20 MHz.

US Pat. No. 10,170,840

APPARATUS AND METHODS FOR SENDING OR RECEIVING ELECTROMAGNETIC SIGNALS

13. A device, comprising:a generator that facilitates generation of a first electromagnetic wave;
a core; and
a waveguide that facilitates guiding the first electromagnetic wave towards the core,
wherein the core comprises a first region, a second region, and a third region,
wherein the core comprises an interface in the first region,
wherein the interface comprises a tapered structure,
wherein the first electromagnetic wave induces at the interface a second electromagnetic wave,
wherein the waveguide is configured to confine the second electromagnetic wave at least in part within the core in the first region,
wherein the second region of the core has a tapered structure and is configured to reduce a radiation loss of the second electromagnetic wave as the second electromagnetic wave propagates into the second region, and
wherein the third region of the core is configured to reduce a propagation loss of the second electromagnetic wave as the second electromagnetic wave propagates into the third region.

US Pat. No. 10,170,830

DISPLAY DEVICE, PROJECTOR, AND COMMUNICATION DEVICE

Seiko Epson Corporation, ...

1. A display device comprising:a communication unit which wirelessly receives image data from an external device; and
a display unit which displays an image based on the image data received by the communication unit;
wherein the communication unit includes
a first communication unit which has a first array antenna, the first communication unit receives wireless radio waves of a first frequency in a millimeter wave band via the first array antenna, and
a second communication unit which has a second array antenna, the second communication unit receives wireless radio waves of a second frequency in a millimeter wave band that is different from the first frequency via the second array antenna, and
a plane including the second array antenna is tilted at an angle of 10 degrees or more and 30 degrees or less to a plane including the first array antenna.

US Pat. No. 10,170,829

SELF-COMPLEMENTARY MULTILAYER ARRAY ANTENNA

THALES, Courbevoie (FR)

1. A multilayer antenna array comprising:a radiating structure formed from an array of radiating elements forming self-complementary patterns, each radiating element including:
a plurality of electrical supply points distributed around a perimeter of the respective radiating element; and
four particular points distributed around the perimeter of the respective radiating element between consecutive electrical supply points of the plurality of electrical supply points;
a ground plane;
a dielectric layer that separates said radiating structure from said ground plane; and
an array of metallized vias passing through said dielectric layer between the radiating structure and the ground plane, each via being positioned facing a respective one of the four particular points of each radiating element.

US Pat. No. 10,170,826

TFT SUBSTRATE, SCANNING ANTENNA USING SAME, AND METHOD FOR MANUFACTURING TFT SUBSTRATE

SHARP KABUSHIKI KAISHA, ...

1. A TFT substrate comprising a dielectric substrate and a plurality of antenna element regions arranged on the dielectric substrate, the TFT substrate comprising a transmitting/receiving region including the plurality of antenna element regions therein, and a non-transmitting/receiving region located outside of the transmitting/receiving region,each of the plurality of antenna element regions comprising:
a thin film transistor supported on the dielectric substrate, the thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer located between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer;
a first insulating layer covering the thin film transistor and having a first opening which exposes the drain electrode of the thin film transistor; and
a patch electrode formed on the first insulating layer and in the first opening, and electrically connected to the drain electrode of the thin film transistor,
wherein the patch electrode includes a metal layer, and a thickness of the metal layer is greater than a thickness of the source electrode and the drain electrode of the thin film transistor.

US Pat. No. 10,170,818

PLATFORM ASSEMBLIES FOR RADIO TRANSMISSION TOWERS

Kenwood Telecom Corporati...

1. A platform assembly comprising:first, second, and third platform structures, each platform structure respectively including a radial beam and a grating supported by the radial beam, the radial beam constructed to connect to and extend substantially horizontally away in a radial direction from a vertical support structure and to support a weight of a human, each platform structure respectively defining at least four mounting locations arranged in three intersecting vertical mounting planes, including a first front mounting location spaced apart from a second front mounting location defined in substantially co-planar relationship in a front vertical mounting plane of the three intersecting vertical mounting planes, at least one first side mounting location substantially defined in a first side vertical mounting plane of the three intersecting vertical mounting planes, and at least one second side mounting location substantially defined in a second side vertical mounting plane of the three intersecting vertical mounting planes, wherein the front vertical mounting plane is perpendicular to the radial direction of the radial beam and is located radially outward from the entire radial beam, wherein the first front mounting location and the second front mounting location are spaced apart at a sufficient distance to provide for proper antenna function when antennas are mounted adjacent the first front mounting location and second front mounting location, and
wherein the first, second, and third platform structures are connected together such that the respective front vertical mounting planes, the respective first side vertical mounting planes, and the respective second side vertical mounting planes of the first, second, and third platform structures are substantially hexagonally arranged whereby the first side vertical mounting plane of each of the first, second, and third platform structures is substantially coplanar with an adjacent second side vertical mounting plane of a directly adjacent platform structure of the first, second, and third platform structures.

US Pat. No. 10,170,817

SUPERCONDUCTING AIRBRIDGE CROSSOVER USING SUPERCONDUCTING SACRIFICIAL MATERIAL

INTERNATIONAL BUSINESS MA...

1. A method of forming a superconducting airbridge on a structure, the method comprising:forming a first ground plane, a resonator, and a second ground plane on a substrate;
forming a first lift-off pattern of a first lift-off resist and a first photoresist, the first photoresist being deposited on the first lift-off resist;
depositing a superconducting sacrificial layer while using the first lift-off pattern;
removing the first lift-off pattern;
forming a cross-over lift-off pattern of a second lift-off resist and a second photoresist, the second photoresist being deposited on the second lift-off resist;
depositing a cross-over superconducting material to be formed as the superconducting airbridge while using the cross-over lift-off pattern;
removing the cross-over lift-off pattern; and
forming the superconducting airbridge connecting the first ground plane and the second ground plane by removing the superconducting sacrificial layer underneath the cross-over superconducting material, wherein the superconducting airbridge crosses over the resonator.

US Pat. No. 10,170,788

VARIABLE LAYER THICKNESS IN CURVED BATTERY CELL

MICROSOFT TECHNOLOGY LICE...

1. A battery, comprising:an anode arranged on an anode substrate, the anode substrate being curved with a first arc length;
a cathode arranged on a cathode substrate, the cathode substrate being curved with a second arc length; and
a separator between the anode and the cathode,
wherein the first arc length differs from the second arc length to define tapered edges of the battery, and
wherein a thickness of the anode differs from a thickness of the cathode.

US Pat. No. 10,170,769

METHOD OF HYDROPHOBIC TREATMENT OF A CARBON SUBSTRATE

1. A method of treating a carbon substrate, comprising the following successive steps of:impregnating the carbon substrate with an aqueous solution containing an amorphous fluorinated copolymer of tetrafluoroethylene and perfluoromethoxy dioxole; and
drying the impregnated carbon substrate at a pressure lower than the atmospheric pressure to obtain a treated carbon substrate impregnated with the fluorinated copolymer, wherein the method is free of sintering after drying.

US Pat. No. 10,170,766

CATHODE FOR LITHIUM-SULFUR BATTERY AND MANUFACTURING METHOD THEREFOR

LG CHEM, LTD., Seoul (KR...

1. A cathode for a lithium-sulfur battery, comprising:a cathode active part comprising a sulfur-carbon composite; and
a cathode coating layer provided on at least one portion of a surface of the cathode active part and consisting of an amphiphilic polymer comprising polyvinyl pyrrolidone (PVP), said amphiphilic polymer including a hydrophilic portion and a hydrophobic portion,
wherein the cathode coating layer comprises pores and the pores have an average diameter of 1 nm to 10 ?m,
wherein the cathode coating layer has a porosity of 50 to 95% based on a total volume of the cathode coating layer, and
wherein the cathode coating layer has a thickness of 10 nm to 1 ?m.

US Pat. No. 10,170,765

ELECTRONICALLY CONDUCTIVE POLYMER BINDER FOR LITHIUM-ION BATTERY ELECTRODE

The Regents of the Univer...

1. A polymeric composition with repeating units of the formula:
wherein: R1 is selected from the group consisting of: naphthalene, anthracene, pyrene, fluorene, fluorenone and oligophenylene, R2 is (OCH2CH2)mCH3 where m=0-1000, R3 is selected from the group consisting of: H, OH, alkyloxide, alkanol, ethyleneoxide, carbonate and trialkylamine, a+b+c=1 where 0

US Pat. No. 10,170,753

NANO-SILICON COMPOSITE NEGATIVE ELECTRODE MATERIAL USED FOR LITHIUM ION BATTERY, PROCESS FOR PREPARING THE SAME AND LITHIUM ION BATTERY

Shenzhen BTR New Energy M...

1. A nano-silicon composite negative electrode material, comprising;a graphite matrix composed of hollowed graphite;
a nano-silicon material chemical-vapor deposited inside the graphite matrix;
an amorphous carbon coating layer; and
a nano-conductive material coating layer on the surface of the graphite matrix,
wherein the nano-conductive material coating layer comprises a material selected from the group consisting of carbon nanotubes, graphene, conductive graphite, carbon fibers, nano graphite, conductive carbon black, and combinations thereof, and
wherein the nano-conductive material coating layer is included at from 0.1 wt. % to 10.0 wt. % in the negative electrode material.

US Pat. No. 10,170,751

COMPOSITE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERIES AND METHOD FOR PRODUCING SAME

CONNEXX SYSTEMS CORPORATI...

1. A method for producing a composite active material for lithium secondary batteries comprising:a mixing step of mixing an expanded graphite or a flaky graphite having a specific surface area of 30 m2/g or more and a battery active material capable of combining with lithium ions, to obtain a mixture; and
a spheroidization step of subjecting the mixture to a spheroidization treatment, to produce a generally spherical composite active material for lithium secondary batteries, the composite active material containing graphite and a battery active material capable of combining with lithium ions.

US Pat. No. 10,170,748

STABILIZED ANODE FOR LITHIUM BATTERY AND METHOD FOR ITS MANUFACTURE

Ovonic Battery Company, I...

1. A method of manufacturing an anode for a lithium battery, said method comprising the steps of:providing an anode member comprising a body of carbon having at least one electrochemically active surface which, when said anode is incorporated in a lithium battery, will provide an interface with an electrolyte of said battery;
coating a layer of a Group IV element or Group IV element-containing substance onto said at least one electrochemically active surface, said Group IV element or Group IV element containing substance comprising silicon, germanium, tin, or lead;
disposing said anode in a lithium battery cell comprising a cathode which is spaced apart from said anode, and a volume of electrolyte disposed between said cathode and said anode; and
operating said lithium battery cell in a charging mode so that lithium is intercalated into said carbon wherein said at least one electrochemically active surface of said anode member having said Group IV element or Group IV element-containing substance disposed thereupon interacts with said electrolyte so as to form a nonhomogeneous solid electrolyte interface layer comprising subregions, the subregions comprising the group IV element and carbon from the body of carbon.

US Pat. No. 10,170,745

SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

14. A secondary battery comprising:an electrode assembly comprising first and second non-coating portions;
a first current collector connected to the first non-coating portion, and a second current collector connected to the second non-coating portion;
a cap assembly comprising a first terminal connection member connected to a portion of the first current collector, and a second terminal connection member connected to a portion of the second current collector; and
a sealing member between the first current collector and the first terminal connection member,
wherein a terminal connection member of the first and second terminal connection members comprises a fuse,
wherein the first terminal connection member comprises:
a first area on an upper portion of the cap assembly; and
a second area on a lower portion of the cap assembly,
wherein the first terminal connection member has a fastening hole between the first area and the second area,
wherein the sealing member comprises a protrusion having a second hole, and a second depression is formed at a position on the first current collector corresponding to the second hole,
wherein the second hole is aligned with the second depression, and the second area passes through the second hole and is connected to the first current collector in the second depression, the protrusion of the sealing member being inserted into and coupled to the fastening hole.

US Pat. No. 10,170,742

BATTERY PACK HAVING ELECTRIC INSULATING PACK CASE

LG CHEM, LTD., Seoul (KR...

1. A battery pack comprising:a plate-shaped battery cell having electrode terminals, including an anode terminal and a cathode terminal formed at an upper end thereof, the upper end of the battery cell further including a sealed surplus portion, wherein the battery cell is formed to have a planar quadrangular structure;
a protection circuit module (PCM) including electrode terminal joint parts bent towards the electrode terminals and being directly and electrically connected to the electrode terminals to control operation of the battery pack, the PCM being adhesively attached to the sealed surplus portion of the battery cell via an insulating double-sided adhesive tape; and
a pack case applied to the sealed surplus portion of the battery cell, the PCM, and opposite sides of the battery cell in a thermally molten state and solidified, the pack case being configured to have a structure to cover the sealed surplus portion of the battery cell, the PCM, and the opposite sides of the battery cell in a state in which a top and a bottom of the battery cell are open, wherein each of the opposite sides of the battery cell are adjacent to the upper end of the battery cell,
wherein the electrode terminals extend outward from an upper end of the pack case at a first surface,
wherein a lower end of the battery cell, opposite to the upper end of the battery cell, is open, and
wherein the pack case is provided with a through hole at a second surface of the upper end thereof through which a side portion of the PCM received in the pack case is exposed outward, wherein the first surface is different from the second surface.

US Pat. No. 10,170,740

BATTERY AND BATTERY PACK WITH A BOLT AS AN ELECTRODE TERMINAL

TOYOTA JIDOSHA KABUSHIKI ...

1. A battery comprising:a flat case that has a top plate being an elongated rectangular shape;
a power generating element that is housed in the case;
an insulating plate arranged above the top plate;
a terminal bolt that is arranged above the insulating plate such that a top surface of a bolt head faces the insulating plate; and
a connecting terminal plate that is electrically connected to the power generating element and insulated from the top plate, plate, and that fits loosely over the terminal bolt with the bolt head sandwiched between the connecting terminal plate and the insulating plate, wherein
the bolt head has a regular N-sided polygon shape having an even number of apexes;
the insulating plate includes a pair of rotation stopping walls, including a first rotation stopping wall and a second rotation stopping wall, that stop rotation of the bolt head with respect to the insulating plate and that are respectively provided on each side of the bolt head in a short direction of the top plate,
a wall thickness of the first rotation stopping wall at a first abutting location, where the bolt head abuts the first rotation stopping wall when the bolt head is rotated in a tightening direction of a nut that screws onto the terminal bolt and the bolt head is stopped from further rotating by the first rotation stopping wall, is greater than a wall thickness of the first rotation stopping wall at a second abutting location, where the bolt head abuts the first rotation stopping wall when the bolt head is rotated in a loosening direction of the nut and the bolt head is stopped from further rotating by the first rotation stopping wall, and
a wall thickness of the second rotation stopping wall at a third abutting location, where the bolt head abuts the second rotation stopping wall when the bolt head is rotated in a tightening direction of the nut that screws onto the terminal bolt and the bolt head is stopped from further rotating by the second rotation stopping wall, is greater than a wall thickness of the second rotation stopping wall at a fourth abutting location, where the bolt head abuts the second rotation stopping wall when the bolt head is rotated in a loosening direction of the nut and the bolt head is stopped from further rotating by the second rotation stopping wall.

US Pat. No. 10,170,736

BATTERY CASE

Samsung SDI Co., Ltd., G...

1. A battery case, comprising:a front case comprising i) a first surface configured to face a front end portion of a battery module that is placed in a bottom surface of the battery case, and ii) a first flange portion configured to extend toward the battery module from a periphery of the first surface, the first flange portion having an opening formed in an upper surface thereof;
a top case comprising i) a second surface facing the opening of the first flange portion and a top of the battery module, and ii) a second flange portion configured to extend toward the top of the battery module from a periphery of the second surface, the second flange portion having one side connected to the first flange portion along edge portions of the opening; and
an attaching/detaching mechanism, configured to be attached and detached from the front case, wherein the attaching/detaching mechanism comprises i) an elastic member configured to be positioned between the first surface of the front case and the front end portion of the battery module, ii) a plurality of cover members respectively at least partially surrounding opposing ends of the elastic member, iii) an extending member extending upwardly from one area of each cover member, and iv) a plurality of press members respectively formed toward the opposing ends of the elastic member from end portions of the extending member, and wherein the number of the cover members is the same as the number of the press members.

US Pat. No. 10,170,724

LIGHT EMITTING APPARATUS AND METHOD OF FABRICATING THE SAME

Semiconductor Energy Labo...

1. A light emitting apparatus comprising:a transistor in a drive circuit portion;
a semiconductor layer;
a gate electrode over the semiconductor layer;
a first insulating film over the gate electrode;
a first electrode over the first insulating film, the first electrode being electrically connected to the semiconductor layer;
a connection wiring over the first insulating film;
an insulating substance over and in contact with a top surface of the first electrode, and a top surface of the connection wiring;
an electroluminescent layer over the first electrode and the insulating substance;
a second electrode over the electroluminescent layer; and
a flexible printed circuit,
wherein the flexible printed circuit is electrically connected to the second electrode through the connection wiring, and
wherein the second electrode is in contact with the connection wiring at a connection portion between the electroluminescent layer and a channel forming region of the transistor.

US Pat. No. 10,170,722

ORGANIC LIGHT-EMITTING DEVICE HAVING LOW WORK FUNCTION METAL HALIDE COMPOUND IN HOLE INJECTION LAYER

SAMSUNG DISPLAY CO., LTD....

13. An organic light-emitting device, comprising:an anode;
a cathode facing the anode; and
an organic layer between the anode and the cathode and including an emission layer, the organic layer including:
a hole transport region between the anode and the emission layer, the hole transport region including a hole injection layer, and
an electron transport region between the emission layer and the cathode, the electron transport region including an electron injection layer,
wherein:
the hole injection layer includes
LiCl, NaCl, KCl, RbCl, CsCl, BeCl2, MgCl2, CaCl2, SrCl2, BaCl2, YbCl, YbCl2, YbCl3, SmCl3,
LiBr, NaBr, KBr, RbBr, CsBr, BeBr2, MgBr2, CaBr2, SrBr2, BaBr2, YbBr, YbBr2, YbBr3, SmBr3,
LiI, NaI, KI, RbI, CsI, BeI2, MgI2, CaI2, SrI2, BaI2, YbI, YbI2, YbI3, or SmI3, and
the hole injection layer directly contacts the anode.

US Pat. No. 10,170,721

ORGANIC LIGHT EMITTING DISPLAY DEVICE HAVING HOLE TRANSPORT LAYERS WITH DIFFERENT THICKNESS

LG Display Co., Ltd., Se...

1. An organic light emitting display device comprising:a first emission part between a first electrode and a second electrode, the first emission part including a first hole transport layer and a first emission layer;
a second emission part on the first emission part, the second emission part including a second hole transport layer and a second emission layer;
a third emission part on the second emission part, the third emission part including a third hole transport layer and a third emission layer,
wherein a thickness of the second hole transport layer is greater than a thickness of the first hole transport layer.

US Pat. No. 10,170,717

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, DISPLAY SUBSTRATE, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising a source electrode pattern and a drain electrode pattern arranged on a same layer, wherein the thin film transistor further comprises:a heat dissipation layer arranged between the source electrode pattern and the drain electrode pattern,
wherein the heat dissipation layer is made of a polymer carbon nanotube composite material.

US Pat. No. 10,170,713

DISPLAY DEVICE AND MANUFACTURING METHOD THEREFOR

Japan Display Inc., Mina...

1. A display device comprising:a substrate having a front surface and a back surface;
a display circuit layer laminated on the front surface, the display circuit layer including a first area and a second area that are aligned in a first direction and apart from each other, the display circuit layer including a middle area positioned between the first area and the second area and having a narrower width in a second direction orthogonal to the first direction than widths of the first area and the second area in the second direction, the display circuit layer having at least one hollow located in the middle area and recessed in the second direction;
a first film overlapped with the first area and stuck to the display circuit layer;
a resin layer provided on the display circuit layer, ranging from the middle area to the second area, and being adjacent to the first film;
a second film overlapped with the first area and stuck to the back surface of the substrate; and
a third film positioned apart from the second film, overlapped with the second area, and stuck to the back surface of the substrate,
wherein the display circuit layer includes a light emitting element, a thin film transistor, and an inorganic insulating layer, and
the inorganic insulating layer is positioned at an edge of the hollow.

US Pat. No. 10,170,711

DISPLAY WITH VIAS TO ACCESS DRIVER CIRCUITRY

Apple Inc., Cupertino, C...

1. A display, comprising:a substrate;
metal pads having opposing first and second surfaces;
a polymer layer covering the substrate and the first surface of the metal pads, wherein vias in the polymer layer contact the first surface of metal pads;
a thin-film transistor layer on the polymer layer, wherein metal traces in the thin-film transistor layer are coupled to the vias and provide signals to pixels configured to be controlled by transistors in the thin-film transistor layer; and
bonding material on the second surfaces of the metal pads.

US Pat. No. 10,170,710

ORGANOMETALLIC COMPLEX, LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:an EL layer between a pair of electrodes,
wherein the EL layer comprises a light-emitting layer, and
wherein the light-emitting layer comprises an organometallic complex represented by a formula (G1-1),

wherein M represents Pt or Pd, and each of R1 to R16 independently represents any one of hydrogen, an alkyl group having 1 to 6 carbon atoms, and a substituted or unsubstituted aryl group having 6 to 13 carbon atoms,
wherein a ring A represents a triazole ring, and
wherein the light-emitting element emits green light.

US Pat. No. 10,170,706

AMINE-BASED COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. An amine-based compound represented by Formula 1A below:wherein in

L1 and L2 are each independently selected from:
a phenylene group, a naphthylene group, a fluorenylene group, a spiro-fluorenylene group, a phenanthrenylene group, an anthracenylene group, a fluoranthenylene group, a triphenylenylene group, a pyrenylene group, a chrysenylene group, a pyridinylene group, a pyrazinylene group, a pyrimidinylene group, a pyridazinylene group, an isoindolylene group, an indolylene group, a quinolinylene group, a benzoquinolinylene group, a quinoxalinylene group, a quinazolinylene group, a cinnolinylene group, a carbazolylene group, and a triazinylene group; and
a phenylene group, a naphthylene group, a fluorenylene group, a spiro-fluorenylene group, a phenanthrenylene group, an anthracenylene group, a fluoranthenylene group, a triphenylenylene group, a pyrenylene group, a chrysenylene group, a pyridinylene group, a pyrazinylene group, a pyrimidinylene group, a pyridazinylene group, an isoindolylene group, an indolylene group, a quinolinylene group, a benzoquinolinylene group, a quinoxalinylene group, a quinazolinylene group, a cinnolinylene group, a carbazolylene group, and a triazinylene group, each substituted with at least one selected from a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, a quinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, and a triazinyl group;
a and b are each independently 0 or 1;
Ar1 and Ar2 are each independently selected from:
a phenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, a quinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, and a triazinyl group; and
a phenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, a quinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, and a triazinyl group, each substituted with at least one selected from a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, a quinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, and a triazinyl group;
R1 and R2 are each independently selected from:
a C1-C20 alkyl group;
a C1-C20 alkyl group substituted with at least one selected from a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a phenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, a quinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, and a triazinyl group;
a phenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, a quinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, and a triazinyl group; and
a phenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, a quinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, and a triazinyl group, each substituted with at least one selected from a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, a quinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, and a triazinyl group;
R3, R4 and R11 to R21 are each independently selected from a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, and a C1-C20 alkyl group; and
p and q are each independently 0, 1, or 2,
wherein
at least one of Ar1, Ar2, R1 to R4, and R11 to R21 is selected from:
a naphthyl group;
a naphthyl group substituted with at least one selected from a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, a quinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, and a triazinyl group; and
a phenyl group, an anthracenyl group, and a fluorenyl group, each substituted with at least one naphthyl group.

US Pat. No. 10,170,701

CONTROLLED DEPOSITION OF MATERIALS USING A DIFFERENTIAL PRESSURE REGIME

Universal Display Corpora...

1. A deposition device for depositing a material onto a substrate, comprising:a delivery device comprising a first aperture in fluid communication with a delivery gas and a source of organic material to be deposited on a substrate, the first aperture configured to create a higher pressure regime in a first microenvironment below the first aperture; and
a second aperture, disposed adjacent to the first aperture, and configured to create a lower pressure regime in a second microenvironment below the second aperture;
wherein the delivery device creates a higher pressure regime in a third microenvironment adjacent to the second aperture.

US Pat. No. 10,170,699

RRAM CELL BOTTOM ELECTRODE FORMATION

Taiwan Semiconductor Manu...

16. A method of forming a resistive random access memory (RRAM) cell, comprising:performing a physical vapor deposition (PVD) process to form a lower portion of a bottom electrode layer;
performing a first plasma enhanced atomic layer deposition (PEALD) process to form an upper portion of the bottom electrode layer over the lower portion of the bottom electrode layer;
performing a second PEALD process, in-situ with the first PEALD process, to form a dielectric data storage layer having a variable resistance over the upper portion of the bottom electrode layer; and
forming a top electrode layer over the dielectric data storage layer.

US Pat. No. 10,170,697

CRYOGENIC PATTERNING OF MAGNETIC TUNNEL JUNCTIONS

INTERNATIONAL BUSINESS MA...

8. A method for fabricating a magnetic tunnel junction, comprising:sequentially depositing a first magnetic layer, an insulating layer, and a second magnetic layer onto a substrate, the substrate comprising a first electrode;
depositing a sacrificial layer onto second magnetic layer;
forming an opening in the sacrificial layer;
conformally depositing a liner layer onto the substrate;
removing a portion of the liner layer on a top surface of the sacrificial layer;
depositing a conductive material into the opening;
selectively removing remaining portions of the liner layer and the sacrificial layer from the substrate; and
anisotropically etching the first magnetic layer, the insulating layer, and the second magnetic layer using the conductive material as a hard mask to form the magnetic tunnel junction on at least a portion of the first electrode, wherein anisotropically etching comprises cooling the substrate to a temperature between 0° C. and ?200° C. and exposing the first magnetic layer, the insulating layer, and the second magnetic layer to reactive plasma.

US Pat. No. 10,170,693

MAGNETORESISTIVE DEVICE AND METHOD OF FORMING THE SAME

Agency for Science, Techn...

1. A magnetoresistive device comprising:a free magnetic layer structure having a variable magnetization orientation;
a fixed magnetic layer structure having a fixed magnetization orientation;
a compensating magnetic layer having a magnetization orientation aligned at least substantially antiparallel to the fixed magnetization orientation of the fixed magnetic layer structure; and
a tilting magnetic layer structure configured to provide an interlayer exchange biasing field to tilt, at equilibrium, the fixed magnetization orientation relative to the variable magnetization orientation to be along a tilting axis that is at least substantially non-parallel to at least one of a first easy axis of the fixed magnetization orientation and a second easy axis of the variable magnetization orientation,
wherein the tilting magnetic layer structure is interlayer exchange coupled to the compensating magnetic layer via a non-magnetic spacer layer therebetween such that the interlayer exchange biasing field tilts, at equilibrium, the fixed magnetization orientation of the fixed magnetic layer structure to be along the tilting axis.

US Pat. No. 10,170,687

SPIN TORQUE MAJORITY GATE DEVICE

IMEC vzw, Leuven (BE)

1. A majority gate device, comprising:a plurality of input zones;
an output zone; and
a magnetic tunneling junction (MTJ) formed in each of the input zones and the output zone, the MTJ comprising a non-magnetic layer interposed between a free layer stack and a hard layer, the free layer stack comprising:
a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, and
a magnetic layer formed directly on and in physical contact with the bulk PMA layer,
wherein the non-magnetic layer is formed on the magnetic layer,
wherein each of the bulk PMA layer and the seed layer serves as a common layer for each of the input zones and the output zone.

US Pat. No. 10,170,685

PIEZOELECTRIC MEMS MICROPHONE

The Regents of The Univer...

1. A packaged microphone comprising:a microphone comprising:
a substrate; and
a transducing element having a transducer acoustic compliance, the transducing element comprising a first electrode layer, a piezoelectric layer deposited over the first electrode layer, and a second electrode layer deposited over the piezoelectric material, wherein the first electrode layer is patterned on the substrate, the piezoelectric layer is patterned on the first electrode layer, and the second electrode layer is patterned on the piezoelectric layer; and
a casing mounted to the microphone and having a back wall, wherein a space between the back wall and the transducing element at least partially defines a back cavity having a back cavity acoustic compliance, the casing dimensioned to achieve a predetermined ratio between the transducer and back cavity acoustic compliances.

US Pat. No. 10,170,678

THERMOMECHANICAL CYCLE FOR THERMAL AND/OR MECHANICAL ENERGY CONVERSION USING PIEZOELECTRIC MATERIALS

The Regents of the Univer...

1. A method for generating electrical energy, comprising:(a) increasing an electric field applied to a piezoelectric component from EL to EH, maintaining a temperature of the piezoelectric component at TC, and maintaining a mechanical stress applied to the piezoelectric component at ?L;
(b) increasing the mechanical stress applied to the piezoelectric component from ?L to ?H, increasing the temperature of the piezoelectric component from TC to TH, and maintaining the electric field applied to the piezoelectric component at EH;
(c) decreasing the electric field applied to the piezoelectric component from EH to EL, maintaining the temperature of the piezoelectric component at TH, and maintaining the mechanical stress applied to the piezoelectric component at ?H;
(d) decreasing the mechanical stress applied to the piezoelectric component from ?H to ?L, decreasing the temperature of the piezoelectric component from TH to TC, and maintaining the electric field applied to the piezoelectric component at EL; and
repeatedly cycling through operations (a)-(d).

US Pat. No. 10,170,673

LED PACKAGE STRUCTURE AND MULTILAYER CIRCUIT BOARD

LITE-ON OPTOTECHNOLOGY (C...

1. An LED package structure, comprising:a multilayer circuit board, comprising:
a conductive layer having a first surface and a second surface opposite to the first surface, a mounting region of the conductive layer being arranged on the first surface;
a first resin layer disposed on the first surface and having a first opening, the first opening exposing the mounting region of the conductive layer; and
a first circuit layer disposed on the first resin layer and having a first electrode and a second electrode separated from the first electrode, the first electrode having a second opening, the second opening exposing the mounting region of the conductive layer;
an LED chip passing through the second opening of the first circuit layer and the first opening of the first resin layer to mount on the mounting region of the conductive layer, the LED chip being electrically connected to the second electrode of the first circuit layer by wire bonding; and
a cover disposed on the first resin layer and covering the LED chip and the first circuit layer.

US Pat. No. 10,170,668

SOLID STATE LIGHTING DEVICES WITH IMPROVED CURRENT SPREADING AND LIGHT EXTRACTION AND ASSOCIATED METHODS

Micron Technology, Inc., ...

1. A solid state lighting (SSL) device, comprising:a solid state emitter (SSE) having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials, wherein the second semiconductor material has an emission surface;
a first contact on the first semiconductor material;
a second contact on the second semiconductor material and opposite to the first contact, the second contact having a plurality of interconnected conductive fingers; and
an insulative feature extending from the first contact at least partially into the first semiconductor material, the insulative feature having a plurality of interconnected insulative fingers, wherein the insulative feature comprises a transparent dielectric material having a backside;
the SSL device further comprises a reflective material at the backside of the transparent dielectric material;
each conductive finger is superimposed over a corresponding insulative fingers;
the SSE comprises non-contact areas outboard the area beneath the second contact; and
the insulative feature is configured to: (a) eliminate a direct current path orthogonal to the emission surface between the first and second contacts and (b) increase current spreading in the non-contact areas.

US Pat. No. 10,170,667

SEMICONDUCTOR OPTICAL DEVICE

Sony Corporation, Tokyo ...

1. A semiconductor optical device having a multilayer structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type,wherein a first electrode is formed on the first compound semiconductor layer through a contact layer,
wherein the contact layer has a thickness of four or less atomic layers, and
wherein when an interface between the contact layer and the first compound semiconductor layer is an xy-plane, a lattice constant along an x-axis of crystals constituting an interface layer which is a part of the first compound semiconductor layer in contact with the contact layer is x1, a lattice constant along a z-axis is z1, a length along the x-axis in one unit of crystals constituting the contact layer is xc?, and a length along the z-axis is zc?,
(zc?/xc?)>(z1/x1)is satisfied.

US Pat. No. 10,170,664

SURFACE MOUNT EMISSIVE ELEMENTS

eLux, Inc., Vancouver, W...

1. A surface mount light emitting diode (SMLED) comprising:a top surface;
a bottom comprising a globally flat planar surface;
a first electrical contact formed exclusively on the top surface and configured as a ring;
a second electrical contact formed exclusively on the top surface within a first electrical contact ring perimeter;
a single post connected to and extending from the bottom surface
a first semiconductor layer, with a dopant selected from a first group consisting of an n-dopant or a p-dopant;
a second semiconductor layer, with the unselected dopant from the first group;
a multiple quantum well (MQW) layer interposed between the first semiconductor layer and the second semiconductor layer;
wherein the first semiconductor layer and MQW layer are a stack underlying the first electrical contact, in the shape of a ring; and,
wherein the second semiconductor layer has a disk shape with a center portion underlying the second electrical contact.

US Pat. No. 10,170,662

METHOD FOR MANUFACTURING CIRCUIT BOARD, METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE, AND LIGHT-EMITTING DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a circuit board comprising:a first process;
a second process;
a third process;
a fourth process; and
a fifth process,
wherein the first process comprises a step of providing a circuit and an electrode on a first surface of a first substrate,
wherein the second process comprises a step of providing a reflective layer on the first surface side of the first substrate or a second surface side of a second substrate,
wherein the third process comprises a step of attaching the first surface and the second surface to each other with a bonding layer therebetween to face each other so that the reflective layer overlaps with the electrode and the reflective layer surrounds part of the electrode,
wherein the fourth process comprises a step of irradiating at least part of the reflective layer with laser light from a side opposite to the electrode such that a periphery of a region of the first substrate is irradiated with laser light or a periphery of a region of the second substrate is irradiated with laser light, and
wherein the fifth process comprises a step of removing at least the region of the first substrate or at least the region of the second substrate by pulling the region of the first substrate or the region of the second substrate.

US Pat. No. 10,170,661

INTEGRATED PHOTODETECTOR WAVEGUIDE STRUCTURE WITH ALIGNMENT TOLERANCE

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming a waveguide structure; and
forming a photodetector fully landed on the waveguide structure,
wherein the forming the photodetector comprises:
forming a dielectric material directly on a planar top surface of the waveguide structure;
forming a polycrystalline material directly on a top surface of the dielectric material;
forming an upper hardmask material directly on a top surface and sidewalls of the polycrystalline material, wherein the upper hardmask material and the dielectric material are a same material which form an encapsulating material directly contacting a lower surface, the top surface and the sidewalls of polycrystalline material and which fully encapsulates and fully seals the photodetector; and
crystallizing the polycrystalline material through an annealing process,
wherein the upper hardmask material and the dielectric material are both oxide material or nitride material directly on a bottom surface, the top surface and the sidewalls of the polycrystalline material.

US Pat. No. 10,170,657

SOLAR CELL HAVING AN EMITTER REGION WITH WIDE BANDGAP SEMICONDUCTOR MATERIAL

SunPower Corporation, Sa...

1. A solar cell, comprising:a single crystalline silicon substrate;
a doped amorphous silicon layer disposed directly on a thin oxide layer disposed on a surface of the single crystalline silicon substrate, wherein the doped amorphous silicon layer is an emitter region sufficiently thin to minimize optical absorption, and wherein the doped amorphous silicon layer is doped throughout an entirety of the doped amorphous silicon layer; and
a conductive contact disposed directly on, and conductively coupled to, the doped amorphous silicon layer, wherein the conductive contact has a metallic material in direct contact with the doped amorphous silicon layer.

US Pat. No. 10,170,652

METAMORPHIC SOLAR CELL HAVING IMPROVED CURRENT GENERATION

THE BOEING COMPANY, Chic...

1. A lattice mismatched metamorphic semiconductor device having at least one subcell, the at least one subcell comprising:a base layer;
an emitter layer in electrical connectivity with the base layer, wherein the base layer and emitter layer form a p-n junction in a photovoltaic cell or other optoelectronic device;
a low bandgap absorber region disposed in either or both of the base layer and emitter layer, wherein the low bandgap absorber region has a higher photogeneration and a lower bandgap than surrounding semiconductor layers;
wherein the low bandgap absorber region forms tensile and compressive regions having alternating smaller and larger lattice constants than that of an average lattice constant of the lattice mismatched metamorphic semiconductor device;
wherein the low bandgap absorber region does not form a quantum well,
wherein the subcell further comprises one or more small-lattice-constant strain-compensation regions adjacent to the low bandgap absorber region, wherein a lattice constant of the one or more strain compensation regions is less than the lattice constant of the low bandgap absorber region, wherein strain in the low bandgap absorber region is balanced by strain in the opposite direction by the strain compensation regions, the strain compensation regions having a larger bandgap than the low bandgap absorber region,
wherein the low bandgap absorber region comprises: a 1-dimensional geometric configuration comprising one or more of a linear feature, a curved line, a plurality of discontinuous line-like features, or combinations thereof and wherein the strain compensation regions having a larger bandgap than the low bandgap absorber region encapsulating the 1-dimensional geometric configurations.

US Pat. No. 10,170,645

ORGANIC VEHICLE FOR ELECTROCONDUCTIVE PASTE

1. An electroconductive paste for use in solar cell technology comprising:about 60-90 wt % of metallic particles comprising silver, based upon total weight of the electroconductive paste;
about 1-10 wt % glass frit, based upon total weight of the electroconductive paste; and
about 1-20 wt % of an organic vehicle, based upon total weight of the electroconductive paste, the organic vehicle comprising:
about 1-10 wt % of a polyvinyl pyrrolidone (PVP) binder, based upon total weight of the organic vehicle,
about 1-20 wt % of a surfactant, based upon total weight of the organic vehicle,
about 50-70 wt % of an organic solvent comprising terpineol, based upon total weight of the organic vehicle, and
about 1-10 wt % ethyl cellulose, based upon total weight of the organic vehicle,
wherein the electroconductive paste is suitable for screen printing onto a substrate.

US Pat. No. 10,170,642

SOLAR CELLS WITH IMPROVED LIFETIME, PASSIVATION AND/OR EFFICIENCY

SunPower Corporation, Sa...

1. A solar cell, the solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, the solar cell comprising:a dielectric region over a silicon substrate, wherein a portion of the silicon substrate has a dopant concentration of approximately less than or equal to 2×1018 cm?3, wherein the first emitter region is a N-type doped polysilicon region;
a first emitter region having metal impurities formed over the dielectric region; and
a first metal contact formed over the first emitter region;
a second emitter region having metal impurities formed over the dielectric emitter region, wherein the second emitter region is formed at least partially over the first emitter region, and wherein the first and second emitter regions are formed on a same side of the solar cell; and
a second metal contact formed over the second emitter region, wherein the second emitter region is a P-type doped polysilicon region.

US Pat. No. 10,170,640

FINFET TRANSISTOR GATE AND EPITAXY FORMATION

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a semiconductor fin on a substrate;
forming a buffer layer on a surface of the substrate and adjacent to the semiconductor fin;
forming a semiconducting layer on the buffer layer to define a fin height of the semiconductor fin; and
replacing the buffer layer with a dielectric layer.

US Pat. No. 10,170,639

3D MEMORY

Micron Technology, Inc., ...

1. A vertical memory comprising:a stack of memory cells, each cell of the stack extending between two respective vertically spaced dielectric tiers, each cell comprising:
a control gate having a vertical surface;
a charge storage structure having a vertical surface facing the vertical surface of the control gate;
a barrier film between the charge storage structure and the control gate, the barrier film having a first vertical surface facing the vertical surface of the control gate and a second vertical surface opposite the first vertical surface and facing the vertical surface of the charge storage structure, wherein the barrier film is situated entirely within a horizontal dimension between the vertical surface of the control gate and the vertical surface of the charge storage structure;
a first dielectric extending between the first vertical surface of the barrier film and the charge storage structure; and
a second dielectric extending between the first vertical surface of the barrier film and the control gate, wherein at least one of the first dielectric and the second dielectric further extends between the charge storage structure and the two respective vertically spaced dielectric tiers, and wherein at least one of the first dielectric and the second dielectric further extends between the barrier film and the two respective vertically spaced dielectric tiers.

US Pat. No. 10,170,635

SEMICONDUCTOR DEVICE, DISPLAY DEVICE, DISPLAY APPARATUS, AND SYSTEM

RICOH COMPANY, LTD., Tok...

1. A semiconductor device comprising:a base;
a gate electrode to which a gate voltage is applied;
a source electrode and a drain electrode through which an electric current is generated according to the gate voltage being applied to the gate electrode;
a semiconductor layer made of an oxide semiconductor;
a gate insulating layer inserted between the gate electrode and the semiconductor layer, wherein
the semiconductor layer includes a channel-forming region and a non-channel-forming region, each having
an insulating-layer-facing face facing the gate insulating layer, and
a base-facing face facing the base layer and opposite to the insulating-layer-facing face,
the channel-forming region is in contact with the source electrode and the drain electrode, and
the non-channel-forming region is in contact with the source electrode and the drain electrode.

US Pat. No. 10,170,634

WIRE-LAST GATE-ALL-AROUND NANOWIRE FET

INTERNATIONAL BUSINESS MA...

1. A nanowire field effect transistor (FET) device comprising:a first source/drain region and a second source/drain region, each on an upper surface of a bulk semiconductor substrate, the bulk semiconductor substrate including a single layer of semiconductor material extending from a base to the upper surface, the single layer excluding an insulator layer between the base and the upper surface;
a gate region interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate;
a plurality of nanowires only in the gate region, the nanowires suspended above the semiconductor substrate and defining gate channels of the nanowire FET device; and
a gate structure including a gate electrode in the gate region and sidewalls spacers on sidewalls of the gate electrode that directly contact the upper surface of the bulk semiconductor substrate, the gate electrode formed directly on the upper surface of the bulk semiconductor substrate and contacting an entire surface of each nanowire.

US Pat. No. 10,170,632

SEMICONDUCTOR DEVICE INCLUDING OXIDE SEMICONDUCTOR LAYER

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor including a first oxide semiconductor layer; and
a second transistor including a second oxide semiconductor layer,
wherein the second transistor includes a first gate electrode below the second oxide semiconductor layer and a second gate electrode above the second oxide semiconductor layer,
wherein the second oxide semiconductor layer includes a first region and a second region,
wherein the second region overlaps with a source or a drain electrode of the second transistor,
wherein a thickness of the first region is smaller than a thickness of the second region, and
wherein the first transistor is electrically connected to a pixel electrode, and the pixel electrode is formed using the same material as the second gate electrode.

US Pat. No. 10,170,630

MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

Semiconductor Energy Labo...

1. A manufacturing method of a semiconductor device comprising:forming a transistor comprises a gate electrode;
forming a cylindrical semiconductor consisting of an oxide semiconductor on and in contact with the gate electrode;
forming a gate insulating film covering a side surface and a top surface of the cylindrical semiconductor; and
forming a first conductor covering the side surface of the cylindrical semiconductor with the gate insulating film therebetween.

US Pat. No. 10,170,626

TRANSISTOR PANEL HAVING A GOOD INSULATION PROPERTY AND A MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A transistor panel, comprising:a channel region including a first oxide of a first metal;
a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source region and the drain region, and wherein the channel region is connected to the source region and the drain region;
an insulation layer disposed on the channel region;
an upper electrode disposed on the insulation layer;
an interlayer insulation layer disposed on the upper electrode, the source region and the drain region; and
a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source region and the drain region, wherein the first portion of the barrier layer contacts each of the source region and the drain region,
wherein the upper electrode and the barrier layer each comprise a second metal, and
the barrier layer does not overlap the upper electrode in a direction perpendicular to a top surface of the upper electrode.

US Pat. No. 10,170,623

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor device, comprising:providing a plurality of mandrels on a substrate, each of the mandrels spaced from each other on a planar surface of the substrate;
removing a portion of the mandrels and a portion of the substrate to form a trench across the mandrels, the trench having a bottom surface lower than the planar surface;
forming a plurality of spacers not sealing the whole trench formed on the planar surface of the substrate, the spacers only covering sidewalls of the mandrels and the trench;
after completely removing the mandrels, using the spacers as a mask to form a plurality of fin shaped structures on the substrate and a plurality of shallow trenches surrounding the fin shaped structures; and
removing a portion of the spacers to form a spacing layer on the sidewalls of the trench, wherein the spacing layer has a top surface being lower than a top surface of the fin shaped structures.

US Pat. No. 10,170,619

VERTICAL SCHOTTKY CONTACT FET

International Business Ma...

1. A semiconductor structure comprising:a vertical field effect transistor located above a substrate, said vertical field effect transistor comprising:
a bottom Schottky contact source/drain structure located directly on a surface of said substrate, said bottom Schottky contact source/drain structure comprises a base portion and a vertically extending portion;
a semiconductor channel region extending vertically upwards from a surface of said base portion of said bottom Schottky contact source/drain structure;
a top Schottky contact source/drain structure located on a topmost surface of said semiconductor channel region; and
a gate structure located on each side of said semiconductor channel region, wherein said vertically extending portion of said bottom Schottky contact source/drain structure has a topmost surface that is coplanar with a topmost surface of said top Schottky contact source/drain structure.

US Pat. No. 10,170,617

VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

GLOBALFOUNDRIES, Grand C...

1. A structure, comprising:a vertical fin structure composed of semiconductor material and having a lower dopant region at a lower portion of the vertical fin structure, an upper dopant region at an upper portion of the vertical fin structure and a channel region between the lower dopant region and the upper dopant region;
a recessed portion in the semiconductor material adjacent to the lower dopant region at a lower portion of the vertical fin structure;
shallow trench isolation structures formed in the semiconductor material, adjacent to the recessed portion; and
doped semiconductor material in the recessed portion in the semiconductor material on sides of the vertical fin structure at the lower portion and adjacent to the shallow trench isolation structures, the lower dopant region being composed of the doped semiconductor material at the lower portion,
wherein the doped semiconductor material comprises a tri-layer of material within the recessed portion, with a higher doped semiconductor material in a lower portion and upper portion of the recessed portion, and a lower doped semiconductor material sandwiched therebetween.

US Pat. No. 10,170,602

SEMICONDUCTOR DEVICE WITH MULTIPLE HBTS HAVING DIFFERENT EMITTER BALLAST RESISTANCES

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a first no-contact HBT and a second no-contact HBT formed over a substrate, wherein the first no-contact HBT comprises a first lower cap over a first emitter, a first middle cap over the first lower cap, a first ballast resistor layer over the first middle cap, and a first upper cap over the first ballast resistor layer at a top portion of the first no-contact HBT, and the second no-contact HBT comprises a second lower cap over a second emitter, a second middle cap over the second lower cap, a second ballast resistor layer over the second middle cap, and a second upper cap over the second ballast resistor layer at a top portion of the second no-contact HBT;
removing the second upper cap and the second ballast resistor layer from the second no-contact HBT to form a second etched HBT; and
providing a first emitter contact to the first no-contact HBT to form a first HBT, wherein the first emitter contact is formed over the first upper cap, and providing a second emitter contact to the second etched HBT to form a second HBT, wherein the second emitter contact is formed over the second middle cap.

US Pat. No. 10,170,583

FORMING A GATE CONTACT IN THE ACTIVE AREA

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:patterning a fin in a substrate;
forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall;
removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer, the spacer having a first spacer portion and a second spacer portion;
recessing the gate and depositing a dielectric cap over the gate;
forming a source/drain contact over at least one of the source/drain regions, the source/drain contact contacting the spacer and the dielectric spacer;
forming a via contact over the source/drain contact; and
removing the dielectric cap and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion, the second gate contact portion being wider than the first gate contact portion;
wherein the first spacer portion and the second spacer portion comprise different materials, the first spacer portion lines sidewalls of the gate and extends to a height that is over the gate, and directly contacts the first gate contact portion and the source/drain contact, and the second spacer portion is arranged directly on top of the first spacer portion, directly beneath an overhanging portion of the second gate contact portion, and directly in contact with the source/drain contact.

US Pat. No. 10,170,574

HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

INTERNATIONAL BUSINESS MA...

1. A method of forming contacts to an electrical device comprising:providing a first via to a first semiconductor device comprising at least one of a silicon and germanium containing source and drain region and providing a second via to a second semiconductor device comprising at least one of a silicon containing source and drain region;
forming a material stack in the first and second via, the first material stack comprising a first metal layer and a second metal layer;
converting the second metal layer of the first material stack within the second via to a second metal oxide;
removing the second metal oxide with an etch that is selective to the first metal layer; and
converting the first metal layer present in the second via to first metal oxide with an oxidation anneal, wherein during said oxidation anneal the second metal layer in the first via alloys with the first metal layer and silicon from the silicon and germanium containing source and drain region to provide a binary metal semiconductor alloy.

US Pat. No. 10,170,565

IMAGING DEVICE, METHOD FOR DRIVING IMAGING DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. An imaging device comprising:a photoelectric conversion element;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor; and
a first capacitor,
wherein one terminal of the photoelectric conversion element is directly connected to one of a source electrode and a drain electrode of the first transistor,
wherein the other terminal of the photoelectric conversion element is directly connected to a first power supply line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the sixth transistor,
wherein the other of the source electrode and the drain electrode of the first transistor is directly connected to one terminal of the first capacitor,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the other terminal of the first capacitor,
wherein the one of the source electrode and the drain electrode of the third transistor is electrically connected to a gate electrode of the fourth transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is directly connected to one of a source electrode and a drain electrode of the fifth transistor,
wherein the gate electrode of the fourth transistor is directly connected to the other terminal of the first capacitor,
wherein the other of the source electrode and the drain electrode of the fifth transistor is directly connected to a second power supply line, and
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor.

US Pat. No. 10,170,564

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate, the manufacturing method of a semiconductor device comprising:forming an n-type gallium nitride layer on a gallium nitride monocrystalline substrate having a threading dislocation density of less than 1E+7 cm?2; and
forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, the impurities including at least one element selected from among magnesium, beryllium, calcium and zinc, wherein
at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.

US Pat. No. 10,170,563

GALLIUM NITRIDE SEMICONDUCTOR DEVICE WITH IMPROVED TERMINATION SCHEME

Alpha and Omega Semicondu...

1. A gallium nitride based semiconductor power device comprising:a top gallium nitride layer comprises a plurality of guard rings disposed in a peripheral area of the top gallium nitride layer wherein the guard rings comprise a plurality of trenches having substantially a same depth opened in an upper portion of the top gallium nitride layer filled with a P-doped gallium-based epitaxial layer therein and wherein the guard rings surrounding a first electrode of the semiconductor power device comprises a metal layer covering over a middle portion of a top surface of the top gallium nitride layer; and
a heavily doped bottom gallium nitride epitaxial layer extending beyond an outer edge of the top gallium nitride layer wherein an extended portion of the bottom gallium nitride epitaxial layer having an exposed top surface not covered by the top gallium nitride layer and wherein a second electrode of the semiconductor power device is disposed directly on the exposed top surface of the extended portion of the bottom gallium nitride layer.

US Pat. No. 10,170,562

SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device, comprising:a first conductive-type SiC semiconductor layer having a front surface and a rear surface;
an anode electrode having a multi-layered structure being in contact with the front surface of the SiC semiconductor layer; and
a cathode electrode formed on the rear surface of the SiC semiconductor layer, wherein
a Schottky junction is formed between the anode electrode and the front surface of the SiC semiconductor layer,
fine recesses are formed only in a SiC semiconductor layer side of a Schottky junction portion between the anode electrode and the front surface of the SiC semiconductor layer,
a part of the anode electrode is embedded in the fine recesses, and
the fine recesses have a depth not greater than 20 nm and are irregularly arranged on the SiC semiconductor layer.

US Pat. No. 10,170,561

DIAMOND SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A diamond semiconductor device comprising:a first diamond semiconductor layer of a first conductivity type having a main surface;
a second diamond semiconductor layer of an i-type or a second conductivity type provided on the main surface of the first diamond semiconductor layer, and having a first side surface with a plane orientation of a {111};
a third diamond semiconductor layer of the first conductivity type provided on the first side surface; and
a fourth diamond semiconductor layer of the second conductivity type provided on the main surface of the first diamond semiconductor layer and on a side surface of the second diamond semiconductor layer, at a side opposite to a side of the third diamond semiconductor layer.

US Pat. No. 10,170,557

THYRISTOR WITH IMPROVED PLASMA SPREADING

ABB Schweiz AG, Baden (C...

1. A thyristor device comprising:a semiconductor wafer having a first main side and a second main side opposite to the first main side;
a first electrode layer, which is arranged on the first main side;
a second electrode layer, which is arranged on the first main side and which is electrically separated from the first electrode layer;
a third electrode layer, which is arranged on the second main side;
wherein the semiconductor wafer includes the following layers;
a first emitter layer of a first conductivity type, the first emitter layer being in electrical contact with the first electrode layer;
a first base layer of a second conductivity type different from the first conductivity type, wherein the first base layer is in electrical contact with the second electrode layer, and wherein the first base layer and the first emitter layer form a first, p-n junction;
a second base layer of the first conductivity type, the second base layer and the fist base layer forming a second p-n junction;
a second emitter layer of the second conductivity type, wherein the second emitter layer is in electrical contact with the third electrode layer, and
wherein the second emitter layer and the second base layer form a third p-n junction.
wherein the thyristor device comprises a plurality of discrete emitter shorts, each emitter short penetrating through the first emitter layer to electrically connect the first base layer with the first electrode layer,
wherein in an orthogonal projection onto a plane parallel to the first main side, a contact area covered by an electrical contact of the first electrode layer with the first emitter layer and the emitter shorts includes areas in the shape of lanes in which no emitter shorts are arranged,
wherein the width of the lanes is at least two times the average distance between centers of emitter shorts next to each other in the contact area,
the lanes are curved, and in the orthogonal projection onto the plane parallel to the first main side, the lanes extend from an edge of the contact area adjacent to the second electrode layer in a direction away from the second electrode layer.

US Pat. No. 10,170,555

INTERMETALLIC DOPING FILM WITH DIFFUSION IN SOURCE/DRAIN

Taiwan Semiconductor Manu...

1. A method comprising:etching a substrate to form a first semiconductor strip;
forming a first dummy gate structure over a first channel region of the first semiconductor strip, the first dummy gate structure being perpendicular to the first semiconductor strip;
etching a first recess in the first semiconductor strip on a first side of the first dummy gate structure;
etching a second recess in the first semiconductor strip on a second side of the first dummy gate structure;
forming a first intermetallic doping film in the first recess and the second recess;
diffusing a first dopant of the first intermetallic doping film into the first semiconductor strip proximate the first recess and into the first semiconductor strip proximate the second recess;
epitaxially growing a source/drain region in the first recess; and
epitaxially growing a source/drain region in the second recess.

US Pat. No. 10,170,552

CO-INTEGRATION OF SILICON AND SILICON-GERMANIUM CHANNELS FOR NANOSHEET DEVICES

INTERNATIONAL BUSINESS MA...

1. A method for forming nanosheet semiconductor devices, comprising:forming a first stack in a first device region comprising layers of a first channel material and layers of a sacrificial material;
forming a second stack in a second device region comprising layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material; and
etching away the sacrificial material using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner, wherein the liner protects the second channel material from the wet etch.

US Pat. No. 10,170,546

FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR

STMicroelectronics, Inc.,...

1. A device, comprising:a substrate;
a fin suspended over the substrate, the fin including a channel region, the fin having a first surface that faces the substrate;
a source region;
a drain region;
an insulating layer between the substrate and the fin, the source region, and the drain region, the insulating layer extending between and in contact with the substrate and the channel region of the fin, the first surface of the fin being between a surface of the insulating layer and the substrate; and
a gate overlying the channel region of the fin.

US Pat. No. 10,170,545

MEMORY ARRAYS

Micron Technology, Inc., ...

1. A memory array, comprising:a semiconductor substrate;
a trench extending into the substrate and proximate a transistor, the trench comprising an upper portion over a lower portion;
a liner along an interior wall of the lower and upper portions of the trench, the liner comprising a transition configuration between the lower and upper portions of the trench, the transition configuration comprising a curved configuration and the liner comprising the only transition configuration for the lower and upper portions of the trench; and
an electrically insulative material in the lower and upper portions of the trench.

US Pat. No. 10,170,541

SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF ELECTRODES AND SUPPORTERS

Samsung Electronics Co., ...

1. A semiconductor device comprising:a plurality of electrode structures on a substrate, the plurality of electrode structures having side surfaces; and
an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures, respectively, the upper supporter group including a plurality of upper supporters, at least some of the plurality of upper supporters each having an upper surface and a lower surface, the at least some of the plurality of upper supporters having a thickness between the upper surface and the lower surface, respectively,
wherein a first one of the upper surface and the lower surface has a curved profile, and a second one of the upper surface and lower surface has a flat profile, and
at least some of the plurality of upper supporters have the thickness that decreases towards the plurality of electrode structures.

US Pat. No. 10,170,539

STACKED CAPACITOR WITH ENHANCED CAPACITANCE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a first conductive layer over the semiconductor substrate;
a second conductive layer over the first conductive layer;
a dielectric layer between the first conductive layer and the second conductive layer;
a cap layer over the second conductive layer;
a first contact via through the cap layer, the second conductive layer and the dielectric layer, and electrically connected to the first conductive layer, wherein a bottom of the first contact via stops at an upper surface of the first conductive layer; and
a second contact via through the cap layer, and electrically connected to the second conductive layer, wherein a bottom of the second contact via stops at an upper surface of the second conductive layer.

US Pat. No. 10,170,534

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate;
a plurality of display elements in a display area of the substrate, wherein each of the plurality of display elements includes a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode;
a drive circuit on an outer side of the display area and including a thin film transistor;
a first insulating layer on the drive circuit;
a first power supply line layer on the first insulating layer and overlapping the drive circuit;
a second insulating layer on the first power supply line layer; and
a connection electrode layer on the second insulating layer, wherein the connection electrode layer electrically connects the first power supply line layer to the opposite electrode.

US Pat. No. 10,170,533

DISPLAY DEVICE, METHOD FOR DRIVING THE SAME, AND ELECTRONIC APPARATUS

SONY CORPORATION, Tokyo ...

1. A display device comprising:a pixel array unit having pixels arranged in a matrix, at least one of the pixels having an electro-optical element, a first capacitor, a second capacitor, a first transistor configured to supply a data signal from a data line to the first capacitor, and a second transistor configured to flow a drive current to the electro-optical element;
a data signal line extending in a first direction; and
a scan line extending in a second direction perpendicular to the first direction,
wherein,
the first capacitor has a first electrode and a second electrode overlapped with the first electrode partly,
the second capacitor has a third electrode and a fourth electrode overlapped with the third electrode partly,
the first electrode is disposed in a first layer,
the fourth electrode is disposed in a second layer which is different from the first layer, and the second layer is disposed over the first layer,
the first electrode is electrically connected to a control terminal of the second transistor,
the second electrode is electrically connected to a first current terminal of the second transistor,
the third electrode is electrically connected to an anode electrode of the electro-optical element, and
the second electrode and the third electrode are electrically connected.

US Pat. No. 10,170,532

EL DISPLAY PANEL, POWER SUPPLY LINE DRIVE APPARATUS, AND ELECTRONIC DEVICE

Sony Corporation, Tokyo ...

1. An electroluminescence display device comprising:a plurality of pixel circuits arranged in a matrix form having a column and a row; and
a peripheral circuit configured to drive the pixel circuits,
wherein the pixel circuits includes:
a first pixel circuit configured to drive a first electroluminescence element, and
a second pixel circuit adjacent to the first pixel circuit along a column direction and configured to drive a second electroluminescence element,
wherein the peripheral circuits includes:
a first buffer circuit including a first transistor and a second transistor serially connected between a first node and a second node, and configured to alternatively output a high potential and a low potential, to the first pixel circuit via a first extraction wire,
a second buffer circuit including a third transistor and a fourth transistor serially connected between a third node and a fourth node, and configured to alternatively output a high potential and a low potential, to the second pixel circuit via a second extraction wire,
a first line connected to the first node of the first buffer circuit and the third node the second buffer circuit, and
a second line connected to the second node of the first buffer circuit and the fourth node the second buffer circuit,
wherein the first line and the second line is disposed on an input side of first buffer circuit.

US Pat. No. 10,170,531

ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING REACTION BLOCKING MEMBER ON COMMON VOLTAGE LINE

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode display comprising:a substrate divided into a pixel area, and a peripheral area enclosing the pixel area;
an organic light emitting diode which is in the pixel area, and comprises a first electrode, an organic emission layer and a second electrode;
a switching element which is in the pixel area, and controls the organic light emitting diode;
a protective layer covering the switching element;
a pixel defining layer which defines the pixel area in which the organic light emitting diode is disposed;
a common voltage line which is in the peripheral area, and transmits a common voltage to the second electrode; and
a reaction blocking part which is in the peripheral area and overlaps the common voltage line, the reaction blocking part comprising a same material as the first electrode,
wherein in the peripheral area:
a side surface of the common voltage line which is furthest from the pixel area is exposed by each of the protective layer and the pixel defining layer, and
the reaction blocking part which comprises the same material as the first electrode overlaps an entirety of the exposed side surface of the common voltage line which is furthest from the pixel area.

US Pat. No. 10,170,529

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising the steps of:preparing a processed member, the processed member comprising:
an organic resin layer over a substrate; and
an element layer comprising a transistor over the organic resin layer;
irradiating the organic resin layer with a linear beam through the substrate by using a first apparatus, the first apparatus comprising:
a laser oscillator configured to emit a laser light;
an optical device configured to extend the laser light; and
a lens configured to condense the laser light into the linear beam; and
separating the organic resin layer from the substrate by using a separation apparatus after irradiating the organic resin layer with the linear beam,
wherein the separation apparatus comprises a roller, and
wherein the organic resin layer and the element layer are rolled up by the roller at the step of separating the organic resin layer from the substrate.

US Pat. No. 10,170,525

ORGANIC LIGHT EMITTING DISPLAY DEVICE

Samsung Display Co., Ltd....

1. An organic light emitting display (OLED) device, comprising:a substrate including a sub-pixel region and a transparent region;
a gate insulation layer on the substrate;
a planarization layer in the sub-pixel region on the gate insulation layer, the planarization layer exposing-the transparent region;
a boundary pattern which covers a boundary of the sub-pixel region and the transparent region, the boundary pattern including:
a first boundary extension extending in a direction from the boundary of the sub-pixel region and the transparent region into the sub-pixel region, the first boundary extension extending onto the sidewall of the planarization layer, and
a second boundary extension extending in a direction from the boundary of the sub-pixel region and the transparent region into the transparent region, the second boundary extension extending onto an upper surface of the gate insulation layer that is located in transparent region on the substrate;
a pixel defining layer on the planarization layer, the pixel defining layer exposing the transparent region and exposing at least a portion of an upper surface of the boundary pattern in the transparent region; and
a sub-pixel structure on the planarization layer.

US Pat. No. 10,170,519

MAGNETORESISTIVE ELEMENT AND MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A magnetoresistive element comprising:a first metal layer having a body-centered cubic structure;
a second metal layer having a hexagonal close-packed structure on the first metal layer;
a metal nitride layer on the second metal layer;
a first magnetic layer on the metal nitride layer;
an insulating layer on the first magnetic layer; and
a second magnetic layer on the insulating layer.

US Pat. No. 10,170,515

IMPLANTATION PROCESS FOR SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other;
performing a first implantation process on the substrate from the first surface to form a first shallow implantation region in the substrate adjacent to the first surface;
forming a device on the first surface adjacent to the first shallow implantation region;
performing a thinning process on the second surface of the substrate; and
performing a second implantation process on the substrate from the second surface to form a first deep implantation region and a second deep implantation region in the substrate adjacent to the second surface, wherein the first deep implantation region is formed to adjoin the first shallow implantation region, the second implantation process is performed such that at least a portion of the second deep implantation region is separated from the first deep implantation region, and the second deep implantation region is formed to peripherally surround the first deep implantation region.

US Pat. No. 10,170,514

IMAGE SENSOR

CMOSIS BVBA, Antwerp (BE...

1. An image sensor comprising an array of pixels and control logic which is arranged to control operation of the pixels, each of the pixels comprising:a pinned photodiode;
a first sense node;
a second sense node;
a transfer gate connected between the pinned photodiode and the first sense node;
a first reset transistor connected between a voltage reference line and the second sense node;
a second reset transistor connected between the first sense node and the second sense node; and
a buffer amplifier having an input connected to the first sense node;the image sensor further comprising:a first reset control line connected between the control logic and the first reset transistor in each of a plurality of pixels of the array;
a second reset control line connected between the control logic and the second reset transistor in each of the plurality of pixels of the array;
wherein the control logic is arranged to selectively operate the pixels in a low conversion gain mode and in a high conversion gain mode and in each of the conversion gain modes the control logic is arranged to operate one of the first reset control line and the second reset control line to continuously switch on one of the first reset transistor and the second reset transistor during a readout period of an operational cycle of the pixels and;wherein, in each of the conversion gain modes the control logic is arranged to operate the first reset control line and the second reset control line such that the first reset transistor and the second reset transistor are switched on during a non-readout period of the operational cycle of the pixels;wherein for the low conversion gain mode;
the second reset transistor is switched on during a readout period, and the first reset control line is operated to switch on the first reset transistor to reset the first sense node and
for the high conversion pain mode;
the first reset transistor is switched on during a readout period, and the second reset control line is operated to switch on the second reset transistor to reset the first sense node.

US Pat. No. 10,170,504

MANUFACTURING METHOD OF TFT ARRAY SUBSTRATE, TFT ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A TFT array substrate, comprising a thin film transistor and a pixel electrode formed on a base substrate, the pixel electrode being electrically connected with a drain electrode of the thin film transistor,wherein
the array substrate further comprises a light-shielding pattern provided above the thin film transistor;
the array substrate further comprises: a passivation layer provided between the thin film transistor and the pixel electrode, and a passivation layer via hole penetrating the passivation layer;
the array substrate further comprises a light-shielding conductive metal layer formed of a same material as the light-shielding pattern, and an entirety of the light-shielding conductive metal layer is provided in the passivation layer via hole; and
the pixel electrode is electrically connected with the drain electrode of the thin film transistor through the light-shielding conductive metal layer.

US Pat. No. 10,170,502

TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A transistor array panel comprising:a substrate;
a buffer layer positioned on the substrate;
a semiconductor layer positioned on the buffer layer;
an intermediate insulating layer positioned on the semiconductor layer;
an upper conductive layer positioned on the intermediate insulating layer;
a lower conductive layer positioned between the substrate and the buffer layer,
wherein the semiconductor layer includes a first contact hole,
wherein the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole,
wherein the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole,
wherein the buffer layer comprises a third contact hole positioned over and exposing the lower conductive layer,
wherein the intermediate insulating layer comprises a fourth contact hole positioned in an overlapping relationship with the third contact hole,
wherein the lower conductive layer comprises a different material from a material of the semiconductor layer, and
wherein the upper conductive layer is in contact with an upper surface of the buffer layer in the fourth contact hole, and is in contact with an upper surface of the lower conductive layer in the third contact hole.

US Pat. No. 10,170,501

DISPLAY PANEL

INNOLUX CORPORATION, Mia...

1. A display panel, comprising:a substrate comprising a display region and a non-display region adjacent to the display region; and
a thin film transistor disposed on the non-display region of the substrate, wherein the thin film transistor comprises:
a semiconductor layer disposed over the substrate;
a first insulating layer disposed over the semiconductor layer;
a first metal layer disposed over the first insulating layer, and the first metal layer comprises a first branch portion and a second branch portion, wherein the first branch portion and the second branch portion are electrically connected to each other;
a second insulating layer disposed over the first insulating layer;
a plurality of first via holes and a plurality of second via holes penetrating through the first insulating layer and the second insulating layer, wherein the first branch portion and the second branch portion are disposed between the plurality of first via holes and the second via holes; and
a second metal layer disposed over the second insulating layer, wherein the second metal layer comprises a first portion electrically connected to the semiconductor layer through the plurality of first via holes and a second portion electrically connected to the semiconductor layer through the plurality of second via holes,
wherein a minimum distance between one of the first via holes and the first branch portion is a first distance, and a minimum distance between one of the second via holes and the second branch portion is a second distance, and the second distance is different from the first distance,
wherein the first metal layer serves as a gate electrode of the thin film transistor and the second metal layer serves as a source/drain electrode of the thin film transistor.

US Pat. No. 10,170,500

TRANSISTOR, LIQUID CRYSTAL DISPLAY DEVICE, AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display device comprising:a transistor comprising a gate electrode, a source electrode, a drain electrode, and a semiconductor layer;
a first wiring electrically connected to the gate electrode, the first wiring extending in a first direction;
a second wiring electrically connected to the source electrode, the second wiring extending in a second direction and intersecting the first wiring;
a pixel electrode electrically connected to the drain electrode; and
a capacitor wiring having a first part extending in parallel with the first direction, and second and third parts each extending in parallel with the second direction,
wherein the pixel electrode has a first edge portion overlapping with the first part of the capacitor wiring, a second edge portion overlapping with the second part of the capacitor wiring, and a third edge portion overlapping with the third part of the capacitor wiring,
wherein the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, and
wherein the semiconductor layer overlaps with an entirety of the pixel electrode.

US Pat. No. 10,170,499

FINFET DEVICE WITH ABRUPT JUNCTIONS

International Business Ma...

1. A method of forming a FinFET device comprising:providing a plurality of semiconductor fins on a surface of an insulator layer;
forming a plurality of gate structures orientated perpendicular to and straddling each semiconductor fin of said plurality of semiconductor fins;
providing a dielectric spacer on vertical sidewalls of each gate structure;
removing, entirely by an anisotropic etch, an entirety of each semiconductor fin and a portion of said insulator layer, not protected by said gate structures and said dielectric spacers, wherein said removing provides semiconductor fin portions located on pedestal insulator portions of said insulator layer;
forming a source-side doped semiconductor material portion on one exposed vertical sidewall of each semiconductor fin portion and a drain-side doped semiconductor portion on another exposed vertical sidewall of each semiconductor fin portion; and
diffusing, by annealing, a dopant from said source-side doped semiconductor material portion into each semiconductor fin portion to form a source region along an entirety of said one exposed vertical sidewall of each semiconductor fin portion, and a dopant from said drain-side doped semiconductor material portion into each semiconductor fin portion to form a drain region along an entirety of said another exposed vertical sidewall of each semiconductor fin portion, said source region and said drain region are laterally separated from each other by a channel region of said semiconductor fin portion, and wherein a first junction between the source region and the channel region has a first dopant concentration gradient of less than 6 nm per decade, and a second junction between the drain region and the channel region has a second dopant concentration gradient of less than 6 nm per decade.

US Pat. No. 10,170,497

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE AND METHOD FOR OPERATING AN ELECTRONIC DEVICE

1. A method for manufacturing an electronic device, the method comprising:providing a carrier comprising a hollow chamber structure within the carrier;
forming a first trench structure extending from a surface of the carrier to the hollow chamber structure such that an electrically isolated region is formed over the hollow chamber structure; and
forming at least one second trench structure extending from the surface of the carrier into a second region of the carrier, the second region of the carrier being laterally adjacent to the electrically isolated region, the second trench structure being at least a part of an electronic component provided in the second region of the carrier.

US Pat. No. 10,170,496

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a cell structure comprising alternately stacked first conductive patterns and first interlayer insulating layers enclosing a channel layer;
a source coupling structure physically separated from the cell structure by a slit and comprising alternately stacked second conductive patterns and second interlayer insulating layers; and
a source discharge transistor coupled to the source coupling structure.

US Pat. No. 10,170,495

STACKED MEMORY DEVICE, OPTICAL PROXIMITY CORRECTION (OPC) VERIFYING METHOD, METHOD OF DESIGNING LAYOUT OF STACKED MEMORY DEVICE, AND METHOD OF MANUFACTURING STACKED MEMORY DEVICE

Samsung Electronics Co., ...

1. A method of manufacturing a stacked memory device, the method comprising:designing a layout of the stacked memory device, the layout including a first pattern;
calculating value of shift of the first pattern according to a first location of the first pattern in the layout;
obtaining a difference value between the first location of the first pattern and a second location of a second pattern formed through a first optical proximity correction (OPC) with respect to the first pattern;
determining, by a processor that executes software instructions, whether a second OPC is to be performed, based on the value of shift and the difference value;
when the processor determines that the second OPC is to be performed, forming a third pattern through the second OPC;
forming a mask, based on the second pattern or third pattern formed through the second OPC; and
forming the stacked memory device through a lithographic process using the mask.

US Pat. No. 10,170,494

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A stacked semiconductor memory device comprising:a stacked body comprising:
a plurality of underlying metal films comprising:
a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %,
a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or
a tungsten film;
a plurality of metal films provided on the underlying metal films and in contact with the underlying metal films, the metal films containing at least one of tungsten and molybdenum, and having a main orientation of (100) or (111); and
a plurality of insulator films,
wherein
the underlying metal films are provided between a lower surface of the metal films and the insulator films, and the underlying metal films are not provided on an upper surface of the metal-films, and
at least one of the plurality of insulator films contacts at least one of the plurality of underlying metal films and at least one the plurality of metal films.

US Pat. No. 10,170,489

HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:first, second, third, and fourth high-voltage transistors arranged on a main surface of a semiconductor substrate, the first and second high-voltage transistors being adjacent each other in a gate-width direction, the third and fourth high-voltage transistors being adjacent each other in the gate-width direction, the first and third high-voltage transistors being adjacent each other in a gate-length direction, the second and fourth high-voltage transistors being adjacent each other in the gate-length direction, and each of the transistors having a gate electrode, and a gate electrode contact formed on the gate electrode; and
a conductive line provided on a portion of an element isolation region, the conductive line positioned between the first and third transistors and between the second and fourth transistors,
wherein the gate electrode contact is formed on a fringe portion formed by extending an end portion of the gate electrode onto the element isolation region in the gate-width direction.

US Pat. No. 10,170,475

SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON REGION

INTERNATIONAL BUSINESS MA...

1. A method of forming a transistor on a silicon substrate, the method comprising:forming a gate stack structure on an epitaxial silicon region disposed on a silicon substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and
growing a raised epitaxial source and drain from the silicon substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure.

US Pat. No. 10,170,472

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

16. An integrated circuit device, comprising:a substrate comprising adjacent first and second substrate regions;
active fins protruding from the substrate in the first and second substrate regions and extending parallel to one another in a first direction;
first and second gate electrodes extending co-linearly in a second direction that intersects the first direction, wherein the first and second gate electrodes are electrically isolated and extend on first and second active fins of the active fins in the first substrate region to define first and second transistors, respectively;
first and second wordlines extending in parallel on the first and second substrate regions; and
first and second wordline contacts connecting the first and second gate electrodes to the first and second wordlines, respectively,
wherein the first and second transistors in the first substrate region are between the first and second wordline contacts.

US Pat. No. 10,170,466

DEVICE HAVING AN ACTIVE CHANNEL REGION

HEWLETT-PACKARD DEVELOPME...

1. A transistor comprising:a substrate;
a drain in the substrate;
a source in the substrate;
a channel between the drain and the source, the channel surrounding the drain and having a channel length to width ratio; and
a gate over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

US Pat. No. 10,170,461

ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

Taiwan Semiconductor Manu...

1. A method of testing a semiconductor device, the semiconductor device comprising:a semiconductor substrate;
a interconnect structure disposed over the semiconductor substrate;
a first conductive pad disposed over the interconnect structure;
a second conductive pad disposed over the interconnect structure and spaced apart from the first conductive pad;
a third conductive pad disposed over the interconnect structure and spaced apart from the first and second conductive pads;
a fourth conductive pad disposed over the interconnect structure and spaced apart from the first, second, and third conductive pads;
a first ESD protection element, including a first fuse, electrically coupled between the first and second conductive pads;
a second ESD protection element, including a second fuse, electrically coupled between the third and fourth conductive pads;
a first device under test (DUT) electrically coupled between the first and third conductive pads; and
a second DUT electrically coupled between the second and fourth conductive pads;
the method comprising:
subjecting the semiconductor device to an electrostatic discharge (ESD) prone environment during manufacturing or testing of the semiconductor device;
after subjecting the semiconductor device to the ESD prone environment, blowing away the first fuse and blowing away the second fuse; and
after blowing away the first and second fuses, conducting an electro-migration test by applying electrical stress to the first DUT or to the second DUT.

US Pat. No. 10,170,453

ARRANGEMENT AND METHOD FOR GENERATING MIXED LIGHT

OSRAM OPTO SEMICONDUCTORS...

1. An arrangement for generating mixed light, comprising:a first device;
a second device; and
a third device,
the first device having a first semiconductor chip for generating a first primary radiation in the blue spectral range and having a first conversion element for generating a first secondary radiation from the first primary radiation, wherein a first total radiation exiting the first device has a first chromaticity coordinate, which lies within a color quadrilateral having the corner points (0.300, 0.425), (0.308, 0.439), (0.388, 0.407) and (0.370, 0.390) or (0.322, 0.482), (0.330, 0.500), (0.384, 0.450) and (0.375, 0.432) or (0.335, 0.345), (0.335, 0.365), (0.355, 0.365) and (0.355, 0.345),
the second device having a second semiconductor chip for generating a second primary radiation in the blue spectral range and having a second conversion element for generating a second secondary radiation from the second primary radiation, wherein a second total radiation exiting the second device has a second chromaticity coordinate, which lies within a color quadrilateral having the corner points (0.325, 0.225), (0.350, 0.225), (0.350, 0.275) and (0.325, 0.275) or (0.350, 0.325), (0.365, 0.325), (0.350, 0.340) and (0.365, 0.340) or (0.445, 0.309), (0.457, 0.318), (0.425, 0.325) and (0.439, 0.337), and
the third device having a third semiconductor chip for generating a third primary radiation in the blue spectral range and having a third conversion element for generating a third secondary radiation from the third primary radiation, wherein a third total radiation exiting the third device has a third chromaticity coordinate, which lies within a color quadrilateral having the corner points (0.475, 0.400), (0.425, 0.400), (0.425, 0.440) and (0.475, 0.440) or (0.515, 0.420), (0.495, 0.420), (0.515, 0.450) and (0.495, 0.450) or (0.425, 0.465), (0.425, 0.475), (0.440, 0.475) and (0.440, 0.465).

US Pat. No. 10,170,428

CAVITY GENERATION FOR EMBEDDED INTERCONNECT BRIDGES UTILIZING TEMPORARY STRUCTURES

Intel Corporation, Santa...

1. A method comprising:fabricating a package substrate;
placing at least one temporary structure in a first location on the package substrate;
subsequent to placing the at least one temporary structure in the first location on the package substrate, applying a first dielectric material to the package substrate, to surround at least a portion of the at least one temporary structure;
subsequent to applying the first dielectric material to the package substrate, removing the at least one temporary structure from the package substrate to generate a cavity in the package substrate, wherein a portion of the first dielectric material remains over the cavity subsequent to removing the temporary structure;
removing the portion of the first dielectric material from over the cavity;
subsequent to removing the portion of the first dielectric material from over the cavity, bonding an interconnect bridge in the cavity, the interconnect bridge including a plurality of interconnections;
applying a second dielectric material to the package substrate; and
installing a plurality of contacts to a surface of the package substrate, the plurality of contacts being coupled with the interconnect bridge.

US Pat. No. 10,170,420

PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:a semiconductor substrate;
a first interconnect layer over the semiconductor substrate, the first interconnect layer comprising: a first dielectric material having a conductive body embedded therein, the conductive body comprising a first sidewall, a second sidewall, and a bottom surface, and a spacer element having a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body; and
a second interconnect layer overlying the first interconnect layer comprising a second dielectric material having at least one via therein, the at least one via filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer;
wherein a height of the spacer element is greater than a height of the conductive body.

US Pat. No. 10,170,417

SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a dielectric layer on the substrate and comprising a recess feature therein;
a metal layer in the recess feature, wherein the metal layer has an oxygen content less than about 0.1 atomic percent; and
a tungsten layer in the recess feature and in contact with the metal layer.

US Pat. No. 10,170,405

WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:an insulating layer; and
a wiring layer buried in the insulating layer at a first surface of the insulating layer,
the wiring layer including a first portion and a second portion, the first portion being narrower and thinner than the second portion, the first portion including a first surface exposed at the first surface of the insulating layer, the second portion including a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer, the opening being open at a second surface of the insulating layer opposite to the first surface thereof,
wherein the wiring layer includes a first surface exposed at the first surface of the insulating layer, a second surface opposite to the first surface of the wiring layer, and a side surface, and
wherein a surface roughness of the second surface of the wiring layer and the side surface of the wiring layer is greater than a surface roughness of the first surface of the wiring layer.

US Pat. No. 10,170,396

THROUGH VIA STRUCTURE EXTENDING TO METALLIZATION LAYER

Taiwan Semiconductor Manu...

1. A method of forming an integrated circuit, comprising:forming an intermetal dielectric layer over a substrate;
forming a metal via and a metal line in the intermetal dielectric layer using a dual-damascene process, the metal line formed in a metal one layer (M1);
after forming the intermetal dielectric layer, removing portions of the intermetal dielectric layer to form an opening through the intermetal dielectric layer;
after removing portions of the intermetal dielectric layer, filling the opening with a conductive material to form a through via (TV), the through via extending through the intermetal dielectric layer and at least a portion of the substrate, the through via having a top surface co-planar with a top surface of the metal line; and
after forming the through via, forming one or more dielectric layers over the through via.

US Pat. No. 10,170,390

THERMALLY ENHANCED SEMICONDUCTOR PACKAGE HAVING FIELD EFFECT TRANSISTORS WITH BACK-GATE FEATURE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a first buried oxide (BOX) layer;
a non-silicon thermal conductive component, wherein the first BOX layer resides over the non-silicon thermal conductive component;
a first epitaxial layer over the first BOX layer;
a second BOX layer over the first epitaxial layer;
a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain;
a gate dielectric aligned over the channel; and
a front-gate structure over the gate dielectric, wherein
a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel; and
a field effect transistor (FET) is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

US Pat. No. 10,170,371

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS

International Business Ma...

1. A fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, comprising:a plurality of vertical fins within a perimeter of a fin pattern region on a substrate;
a step formed in the substrate surrounding the plurality of vertical fins;
a doped region within the perimeter of the fin pattern region below the plurality of vertical fins, wherein the depth of the doped region is less than the height of the step;
a dielectric layer on the step and at least a portion of the plurality of vertical fins; and
a gate dielectric layer on at least a portion of the sidewalls of the plurality of vertical fins and on the dielectric layer, wherein the gate dielectric layer extends over at least a portion of the step.

US Pat. No. 10,170,370

CONTACT RESISTANCE CONTROL IN EPITAXIAL STRUCTURES OF FINFET

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:fin regions on a substrate;
shallow trench isolation (STI) regions between the fin regions;
a replacement gate structure over the fin regions and the STI regions;
a merged epitaxial region; and
a capping layer, on the merged epitaxial region, with a top surface having a vertical dimension between a highest point and a lowest point less than about 5 nm.

US Pat. No. 10,170,341

RELEASE FILM AS ISOLATION FILM IN PACKAGE

Taiwan Semiconductor Manu...

1. A method comprising:forming a release film over a carrier;
attaching a device over the release film through a die-attach film;
encapsulating the device in an encapsulating material;
performing a planarization on the encapsulating material to expose the device;
forming redistribution lines to electrically couple to the device;
detaching the device and the encapsulating material from the carrier while the die-attach film remains attached to the device;
after the detaching of the device and the encapsulating material from the carrier, removing the die-attach film to expose a back surface of the device; and
applying a thermal conductive material on the back surface of the device.

US Pat. No. 10,170,336

METHODS FOR ANISOTROPIC CONTROL OF SELECTIVE SILICON REMOVAL

Applied Materials, Inc., ...

1. A method of etching, the method comprising:flowing a gas through a plasma to form plasma effluents;
reacting plasma effluents with a first layer defining a first feature, wherein:
the first feature comprises a first sidewall, a second sidewall, and a first bottom,
the first sidewall, the second sidewall, and the bottom comprise the first layer, and
the first layer is characterized by a first thickness on the first sidewall;
forming a second layer from the reaction of the plasma effluents with the first layer to define a third feature, wherein:
the third feature comprises a third sidewall, a fourth sidewall, and a second bottom,
the first layer is replaced by the second layer,
the third sidewall, the fourth sidewall, and the second bottom comprise the second layer,
the first sidewall is replaced by the third sidewall,
the second layer is characterized by a second thickness on the third sidewall, and
the second thickness is greater than or equal to the first thickness; and
removing the second layer to expose a third layer, the third layer defining a second feature.

US Pat. No. 10,170,331

STACKED NANOWIRES

International Business Ma...

1. A method of forming silicon germanium (SiGe) nanowires, the method comprising the steps of:forming a stack of alternating silicon (Si) and SiGe layers on a wafer;
patterning fins in the stack;
selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape, wherein the SiGe layers in the fins are selectively thinned using an anisotropic wet etching process, and wherein the anisotropic wet etching process results in a v-shaped notching of the SiGe layers in the fin stack;
burying the fins in an oxide material; and
annealing the fins under conditions sufficient to diffuse germanium (Ge) from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires.

US Pat. No. 10,170,319

FORMING A CONTACT FOR A TALL FIN TRANSISTOR

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:forming a recessed fin in a substrate, a top surface of the recessed fin being flush with a top surface of the substrate, and the recessed fin having a uniform height along an entire length of the recessed fin;
performing an epitaxial growth process over the recessed fin to form a discrete source/drain over the recessed fin, the discrete source/drain having a width that is wider than a width of the recessed fin; and
disposing a conductive metal around the source/drain.

US Pat. No. 10,170,318

SELF-ALIGNED CONTACT AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

15. A device comprising:a gate stack over a semiconductor structure, the semiconductor structure having a first source/drain region, a second source/drain region, and a channel region interposed between the first source/drain region and the second source/drain region, the gate stack being over the channel region;
a gate mask over the gate stack, the gate mask comprising:
a first dielectric layer over the gate stack, the first dielectric layer having a first Cl content;
a second dielectric layer over the first dielectric layer, the second dielectric layer having a second Cl content, the first Cl content being different from the second Cl content; and
a third dielectric layer over the second dielectric layer, a first portion of the third dielectric layer having a lower etch rate than a second portion of the third dielectric layer; and
a capping layer over the gate mask.

US Pat. No. 10,170,314

PULSED LASER ANNEAL PROCESS FOR TRANSISTOR WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN

Intel Corporation, Santa...

1. A transistor, comprising:a semiconductor substrate including a channel region disposed below a gate stack; and
semiconductor source/drain regions coupled to the channel region and disposed on opposite ends of the channel region with the gate stack disposed there between, wherein the semiconductor source/drain regions comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth, the super-activated dopant region having a higher activated dopant concentration than the activated dopant region, wherein the melt depth is substantially the same along the entirety of the semiconductor source/drain regions, and wherein the higher activated dopant concentration is a constant over the super-activated dopant region while the activated dopant concentration is not a constant over activated dopant region.

US Pat. No. 10,170,313

SYSTEMS AND METHODS FOR A TUNABLE ELECTROMAGNETIC FIELD APPARATUS TO IMPROVE DOPING UNIFORMITY

Taiwan Semiconductor Manu...

8. A dopant tool comprising:a chamber sized to contain a wafer;
a plasma generator to accelerate particles toward a wafer support structure; and
an electromagnetic structure disposed between the plasma generator and the wafer support structure, the electromagnetic structure encircling the wafer support structure, wherein the electromagnetic structure comprises a plurality of electromagnetic elements whose positions are movable independently of each other.

US Pat. No. 10,170,310

METHOD OF FORMING PATTERNED STRUCTURE

UNITED MICROELECTRONICS C...

1. A method of forming a patterned structure, comprising:forming a dielectric layer and a material layer on a substrate sequentially;
forming a hard mask layer on the material layer, wherein the material of the hard mask layer is identical to the material of the dielectric layer;
forming a first patterned mask on the hard mask layer and performing a first etching process using the first patterned mask as a mask for forming at least one first opening in the hard mask layer, wherein the first opening exposes at least a part of the material layer;
removing the first patterned mask after the first etching process;
forming a second patterned mask on the hard mask layer and performing a second etching process using the second patterned mask as a mask after the first etching process for forming at least one second opening in the hard mask layer, wherein the second opening exposes at least a part of the material layer, and the second opening partially overlaps the first opening;
performing a third etching process to the material layer with the hard mask layer having the first opening and the second opening as a mask for removing the material layer exposed by the first opening and the second opening; and
performing a fourth etching process to the dielectric layer and the hard mask layer after the third etching process for removing the hard mask layer and forming a trench in the dielectric layer.

US Pat. No. 10,170,308

FABRICATING SEMICONDUCTOR DEVICES BY CROSS-LINKING AND REMOVING PORTIONS OF DEPOSITED HSQ

International Business Ma...

1. A method of manufacturing a semiconductor device, comprising:forming a hydrogen silesquioxane (HSQ) layer on a semiconductor substrate;
forming a cap layer on the HSQ layer;
cross-linking a portion of the HSQ layer under the cap layer;
removing another portion of the HSQ layer which was not cross-linked;
forming a dielectric layer on the substrate, wherein the dielectric layer is positioned between the HSQ layer and the semiconductor substrate;
forming at least one opening exposing a portion of the semiconductor substrate through the cap layer, HSQ layer and dielectric layer; and
epitaxially growing a III-V semiconductor material from the exposed portion of the semiconductor substrate, wherein the III-V semiconductor material occupies a vacant area left by the removal of the other portion of the HSQ layer was not cross-linked;
wherein the removing comprises introducing a developer through the at least one opening to remove the other portion of the HSQ layer which was not cross-linked.

US Pat. No. 10,170,302

SUPERLATTICE LATERAL BIPOLAR JUNCTION TRANSISTOR

International Business Ma...

1. A method for forming a bipolar junction transistor, comprising:patterning an extrinsic base on a superlattice stack including a plurality of alternating layers of semiconductor material on a substrate;
etching an intrinsic base in the superlattice stack; and
growing a collector and emitter adjacent to the intrinsic base on opposite sides of the intrinsic base.

US Pat. No. 10,170,301

ADHESION OF POLYMERS ON SILICON SUBSTRATES

INTERNATIONAL BUSINESS MA...

1. A method for adhering a polymer to a surface of a substrate, the method comprising:forming a substrate;
forming a modified surface of the substrate, where the modified surface comprises X—H terminations;
forming a polymer on the modified surface of the substrate, the polymer comprising a self-crosslinkable organic planarization layer (OPL) comprising hydroxyl, alkene, or alkyne functional group functional groups; and
chemically bonding the polymer to the modified surface of the substrate.

US Pat. No. 10,170,295

FLUX RESIDUE CLEANING SYSTEM AND METHOD

Taiwan Semiconductor Manu...

11. A method comprising:softening an outer region of a flux residue formed around conductive connectors interposed between a wafer and a die by immersing the wafer and the die in a first chemical, the wafer having a first side, the die being disposed on the first side of the wafer;
after the softening the outer region of the flux residue, removing the outer region of the flux residue to expose an inner region of the flux residue by discharging a first chemical spray in a first spray chamber, the first chemical spray impinging on the flux residue, the removing the outer region of the flux residue comprising rotating the wafer during the impinging the first chemical spray upon the wafer in the first spray chamber;
after the removing the outer region of the flux residue, softening the inner region of the flux residue formed around conductive connectors interposed between the wafer and the die by immersing the wafer and the die in a second chemical, the second chemical comprising a surfactant; and
after the softening the inner region of the flux residue, removing the inner region of the flux residue by discharging a second chemical spray in a second spray chamber, the first chemical spray or the second chemical spray or both comprising deionized water.

US Pat. No. 10,170,282

INSULATED SEMICONDUCTOR FACEPLATE DESIGNS

Applied Materials, Inc., ...

1. A semiconductor processing chamber faceplate comprising:a conductive plate defining a plurality of apertures; and
a plurality of inserts, wherein each aperture of the plurality of apertures contains an insert of the plurality of inserts, wherein each insert of the plurality of inserts defines at least two channels there through, wherein each channel of the at least two channels independently extends vertically from a first end of an associated insert to a second end of the associated insert, wherein each channel of the at least two channels is radially offset from a central axis through the insert defining the at least two channels, and wherein the at least two channels are radially offset from one another about the central axis;
a plurality of first o-rings positioned within annular channels at least partially defined by the conductive plate within the plurality of aperture;
wherein a portion of each first o-ring of the plurality of first o-rings is seated within a first annular groove defined along a region of a corresponding insert between a top and bottom of the corresponding insert.

US Pat. No. 10,170,278

INDUCTIVELY COUPLED PLASMA SOURCE

APPLIED MATERIALS, INC., ...

1. An inductively coupled plasma apparatus, comprising:a bottom wall comprising a hub having a plurality of radially outwardly directed spokes and a ring having a corresponding plurality of radially inwardly directed spokes, wherein each radially inwardly directed spoke lies along a common radius as a corresponding one of the plurality of radially outwardly directed spokes, wherein the hub and the ring are each electrically conductive, and wherein the hub has a central opening aligned with a central axis of the inductively coupled plasma apparatus;
a plurality of capacitors, one each disposed between and coupling respective ends of each radially outwardly directed spoke and corresponding radially inwardly directed spoke;
a top wall spaced apart from and above the bottom wall, wherein the top wall has a central opening aligned with the central axis, and wherein the top wall is electrically conductive;
a sidewall electrically connecting the ring to the top wall; and
a tube electrically connecting the hub to the top wall, the tube having a central opening aligned with the central axis.

US Pat. No. 10,170,273

CHARGED PARTICLE BEAM DEVICE, AND METHOD OF MANUFACTURING COMPONENT FOR CHARGED PARTICLE BEAM DEVICE

Hitachi High-Technologies...

1. A charged particle beam device comprising:an optical device that adjusts a charged particle beam emitted from a charged particle source; and
a vacuum container for forming a vacuum atmosphere in a path where the charged particle beam passes;
a first anode for extracting charged particles from the charged particle source;
a second anode for accelerating charged particles extracted by the first anode;
an insulator arranged between the first anode and the second anode; and
a vacuum pump that locally evacuates a peripheral portion of the charged particle source;
wherein the insulator is formed of vanadium-containing glass.

US Pat. No. 10,170,265

LEAKAGE CURRENT PROTECTION DEVICE

Chengli Li, Suzhou (CN)

1. A leakage current protection device, comprising:a top cover, a base, and an electrical and mechanical assembly disposed therein, the electrical and mechanical assembly comprising:
a circuit board;
one or more moving contact plates, for electrically connecting and disconnecting a load circuit;
an auxiliary switch, for electrically connecting and disconnecting an auxiliary circuit;
a reset shaft, wherein an upper portion of the reset shaft is configured to be connected to a reset button, a lower portion of the reset shaft includes a hook, a bottom end of the reset shaft is set against one end of a reset spring, and another end of the reset spring is set against the base;
a disconnect mechanism, wherein an upper portion of the disconnect mechanism has a hook which is configured to be engageable in a vertical direction with the hook of the reset shaft;
a trip coil and a trip plunger disposed in the trip coil, which are disposed on a side of the disconnect mechanism and controlled by electrical circuitry on the circuit board,
wherein the disconnect mechanism is driven by the trip plunger to move horizontally to cause the hook of the reset shaft and the hook of the disconnect mechanism to disengage from each other,
wherein the disconnect mechanism further includes a pushing end disposed at its top, and one or more lifting levers, wherein the pushing end of the disconnect mechanism controls the auxiliary switch and the one or more lifting levers control the one or more moving contact plates.

US Pat. No. 10,170,262

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHODS OF MANUFACTURE AND DESIGN STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A MEMS structure, comprising:fixed actuator electrodes and a contact point;
a MEMS beam over the fixed actuator electrodes and the contact point; and
an array of actuator bumps in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from contacting an actuator portion of the fixed actuator electrodes, wherein the array of actuator bumps are in direct contact with and extending from at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes, and the array of actuator bumps are composed of a dielectric material.

US Pat. No. 10,170,258

METHOD FOR CONTROLLING A CHANGE OF OPERATING STATE OF AN ELECTROMECHANICAL COMPONENT AND CORRESPONDING DEVICE

STMicroelectronics (Rouss...

1. A method for controlling an electromechanical component, the method comprising:transitioning the electromechanical component from a first operating state to a second operating state by:
charging a capacitor coupled to a first terminal of an inductive element of the electromechanical component, and
after charging the capacitor, generating a first current from a power supply while simultaneously generating a second current by partially discharging the capacitor, the first current and the second current forming a third current flowing through the inductive element from the first terminal of the inductive element to a second terminal of the inductive element;
maintaining the electromechanically component in the second operating state by preventing current from flowing through the inductive element;
transitioning the electromechanical component from the second operating state to the first operating state by:
discharging the capacitor, and
after discharging the capacitor, generating a fourth current from the power supply, the fourth current flowing through the inductive element from the second terminal of the inductive element to the first terminal of the inductive element; and
maintaining the electromechanically component in the first operating state by preventing current from flowing through the inductive element.

US Pat. No. 10,170,254

KEY STRUCTURE

PRIMAX ELECTRONICS LTD., ...

1. A key structure, comprising:a flexible key cap, exposed out of the key structure, and configured to be pressed to deform;
a conducting plate, fixed on an inner surface of the flexible key cap and in contact with a plurality of inner sidewalls of the flexible key cap;
a switch circuit board, disposed below the conducting plate, and configured to be triggered due to deformation of the flexible key cap, so as to generate a key signal; and
an elastic element, disposed between the conducting plate and the switch circuit board, and configured to be pushed by the conducting plate to press the switch circuit board, wherein when the flexible key cap is pressed and receives a pressing force, the conducting plate twists due to the flexible key cap that deforms and pushes the plurality of inner sidewalls of the flexible key cap, so as to conduct the pressing force to a corner of the flexible key cap,
wherein the flexible key cap comprises:
a plurality of oblique pyramids, wherein each of the oblique pyramids corresponds to the inner sidewall of the key cap and extends out of the corresponding inner sidewall of the key cap, and the oblique pyramid is disposed on the corresponding inner sidewall of the key cap and is approximate to the corner of the flexible key cap; and
a fixing column, disposed on an inner surface of the key cap and extending out of the inner surface of the key cap.

US Pat. No. 10,170,253

KEY SCISSOR-TYPE CONNECTING ELEMENT WITH AN ELASTIC CONTACT PART

PRIMAX ELECTRONICS LTD., ...

1. A key structure, comprising:a base plate comprising a first open-type hook, a second open-type hook and a bulge;
a keycap disposed over the base plate and movable relative to the base plate; and
a scissors-type connecting element connected with the keycap, the first open-type hook and the second open-type hook, wherein while the scissors-type connecting element is swung, the keycap is moved relative to the base plate, wherein the scissors-type connecting element comprises:
a first frame having a first end connected with the keycap and a second end connected with the first open-type hook, wherein the first frame comprises a first base post and an elastic contact part, wherein the first base post is located at a second end of the first frame and connected with the first open-type hook, the elastic contact part is located at the second end of the first frame and arranged beside the first base post, and the elastic contact part is contacted with the bulge to prevent detachment of the first base post from the first open-type hook, wherein the first frame further comprises a first keycap post, which is located at a first end of the first frame and connected with a movable hook of the keycap, wherein while the keycap is moved relative to the base plate, the first keycap post is slid within the movable hooks; and
a second frame combined with the first frame, wherein a first end of the second frame is connected with the second open-type hook, and a second end of the second frame is connected with the keycap.

US Pat. No. 10,170,249

MULTI-LAYER CAPACITOR PACKAGE

International Business Ma...

1. A substrate assembly comprising:a first ceramic layer;
a first layer of one or more electrodes connected to the first ceramic layer;
a first high dielectric constant layer connected to the first layer of one or more electrodes,
wherein a quantity of ceramic particles in the first high dielectric constant layer is adjusted to control a dielectric constant of the first high dielectric constant layer,
wherein the ceramic particles are selected from the group consisting of strontium titanate and barium titanate,
wherein the first high dielectric constant layer has a thickness ranging from 1 ?m to 10 ?m;
a second layer of one or more electrodes connected to the first high dielectric constant layer;
a second high dielectric constant layer connected to the first layer of one or more electrodes;
a third layer of one or more electrodes connected to the second high dielectric constant layer;
a second ceramic layer connected to the third layer of one or more electrodes;
two or more holes, wherein each of the two or more holes is formed through at least one ceramic layer, at least one layer of one or more electrodes, and at least one high dielectric constant layer;
electrically conductive structures formed in the two or more holes,
wherein each of the electrically conductive structures is physically connected to at least one of the electrodes, thereby forming at least three sets,
wherein each of the sets is physically separated from at least one of the other sets; and an electrically conductive surface pad at a termination of the two or more holes.

US Pat. No. 10,170,234

COIL DEVICE CAPABLE OF PERFORMING A WIRE CONNECTION

TDK CORPORATION, Tokyo (...

1. A coil device comprising:a magnetic core having a winding core wound by a wire to form a coil;
a first flange and a second flange having a substantially planar shape and integrally formed at both ends in the winding axis direction of the winding core; and
a terminal electrode attached on an outer end surface of the first flange formed at an end in a winding axis direction of the winding core, wherein the terminal electrode comprises:
an attachment piece contacted with the outer end surface of the first flange;
a wire connection rising piece integrally risen from one end in a longitudinal direction of the attachment piece along a side surface in a first axis direction of the first flange; and
a connection piece formed integrally with an upper end side of the wire connection rising piece and having a welded ball connected to a lead part of the wire by laser welding, and wherein
a laser shielding member is arranged between the welded ball and the magnetic core,
the side surface in the first axis direction of the first flange includes:
a rising piece facing plane facing the wire connection rising piece in such a manner as to be contactable with the wire connection rising piece to position the connection piece; and
a terminal space concave part caved inside from the rising piece facing plane to form a space between the terminal space concave part and the wire connection rising piece,
the shielding member is formed integrally with the wire connection rising piece of the terminal electrode,
the shielding member is held in space between the welded ball and the terminal space concave part of the magnetic core,
the first flange has notches dented more largely than the second flange so that an outer shape size of the first flange is smaller than that of the second flange,
the rising piece facing plane and the terminal space concave part are formed on the notches, and
the wire connection rising piece is located inside the notches.

US Pat. No. 10,170,230

POWER SUPPLY APPARATUS

PANASONIC INTELLECTUAL PR...

1. An electric supply apparatus configured to contactlessly supply electric power using electromagnetic induction to an electric reception section provided in a vehicle, the electric supply apparatus comprising:an electric supply coil having a ring-shape and a hollow portion, and configured to supply electric power to the electric reception section;
a first cover covering the hollow portion of the electric supply coil, said first cover configured to face the electric reception section; and
a second cover covering the hollow portion of the electric supply coil, said second cover configured to face the electric reception section and being placed between the first cover and the electric supply coil, wherein
a part of the second cover is distinct from the first cover,
at least the part of the second cover covering the hollow portion of the electric supply coil and being between the first cover and the electric supply coil, has higher heat resistant properties than the first cover covering the hollow portion of the electric supply coil.

US Pat. No. 10,170,229

CHIP ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A chip electronic component comprising:an insulating substrate;
a first coil part disposed on one surface of the insulating substrate;
a second coil part disposed on the other surface of the insulating substrate opposing the one surface of the insulating substrate;
a via connecting the first and second internal coil parts to each other while penetrating through the insulating substrate;
first and second via pads disposed on the one surface and the other surface of the insulating substrate, respectively, so as to cover the via; and
a first dummy pattern disposed in a region of the one surface of the insulating substrate adjacent to the first via pad, and a second dummy pattern disposed in a region of the other surface of the insulating substrate adjacent to the second via pad,
wherein the first and second dummy patterns are physically and electrically separated from each other,
portions of the first and second via pads facing the first and second dummy patterns, respectively, are formed to have a curved surface, and
the first and second dummy patterns are formed to have a curved shape, depending on a shape of the first and second via pads, respectively.

US Pat. No. 10,170,227

ELECTOMAGNETIC DRIVER

DENSO CORPORATION, Kariy...

1. An electromagnetic driver comprising:a stationary core;
a movable core located to face the stationary core with a variable gap relative to the stationary core, the movable core being configured to be reciprocable relative to the stationary core;
a spring configured to urge the movable core to be away from the stationary core; and
a coil configured to generate magnetic flux when energized,
wherein the stationary core comprises:
a main magnetic circuit through which a first component of the magnetic flux flows,
the main magnetic circuit being configured such that:
first pulling force generated based on the first component of the magnetic flux flowing through the main magnetic path pulls the movable core in a reciprocation direction of the movable core; and
the first pulling force increases with a reduction of a dimension of the gap; and
an auxiliary magnetic circuit through which a second component of the magnetic flux flows,
the auxiliary magnetic circuit being configured such that:
second pulling force generated based on the second component of the magnetic flux flowing through the auxiliary magnetic path pulls the movable core in the reciprocation direction of the movable core; and
the second pulling force with the dimension of the gap being within a first range is changed to be higher than the second pulling force with the dimension of the gap being within a second range, the second range being smaller than the first range.

US Pat. No. 10,170,221

FENCE STANDARD

GALLAGHER GROUP LIMITED, ...

1. A fence standard, comprising:an elongate shaft; and
a wire support made of electrically non-conductive material, comprising:
an elongate support member including a first end and a second end, and a longitudinal axis between the first end and the second end; and
an open ended loop made of a length of material bending around to double onto or cross over itself and result in overlapping opposing sections having a gap therebetween to permit passage of a wire into the center of the loop in use, wherein one of the opposing sections includes an end of the loop, and the end of the loop lies within an outer periphery of the other opposing section of the loop,
wherein the length of material forming the open ended loop extends from the first end of the elongate support member in a first direction away from the longitudinal axis before bending around above the first end, and
wherein the elongate support member includes a guide surface facing away from the first direction, the guide surface leading outwardly from the longitudinal axis along a direction from the second end to the first end,
wherein the wire support is connected to the shaft by the elongate support member.

US Pat. No. 10,170,218

IGNITION SUPPRESSION CIRCUITING TECHNOLOGY

ISCT LLC, Madisonville, ...

1. A cable system comprising:a cable, said cable having a sheath with an axial pathway running a length of said cable between a first end of said cable and a second end of said cable;
said cable having one or a plurality of electrically conductive wires running through said axial pathway of said sheath for said length of said cable;
said cable having a fluid conduit engaged with or within said sheath and running said length of said cable, said fluid conduit having a sidewall surrounding an axial passage thereof;
wherein said length of said cable is engageable to communicate electricity through said conductive wires between said first end and said second end of said cable and to concurrently communicate a fire suppressant within said fluid conduit, between said first end of said cable and said second end of said cable;
said electrically conductive wires and said fluid conduit at one end of said cable, engageable with a junction box;
a suppressant chamber configured for attachment with said junction box;
said suppressant chamber having a connection for sealed engagement of said axial passage of said fluid conduit, with an internal cavity of said suppressant chamber;
said internal cavity forming a reservoir of a fire suppressant communicated through said axial passage of said fluid conduit from a fire suppressant supply;
said electrically conductive wires having an insulation coating circumferentially engaged thereon, said insulation having a first melting temperature; and
said suppressant chamber being formed of material having a second melting temperature, said first melting temperature exceeding said second melting temperature, whereby said suppressant chamber melts and causes an emission of said fire suppressant from within said internal cavity, only when a temperature of said conductive wires within said junction box or an interior of said junction box, exceeds said second melting temperature.

US Pat. No. 10,170,202

MEMORY SYSTEM

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:a semiconductor storage device including a plurality of blocks; and
a controller configured to
(i) instruct the semiconductor storage device to perform a read operation on data written to a block of the semiconductor storage device to determine whether or not to designate the block as a partial bad block if, after instructing the semiconductor storage device to perform a write operation on the block to write the data, status information read from the semiconductor storage device indicates that the write operation failed, and
(ii) designate the block as a partial bad block if read data that is returned from the semiconductor storage device in response to the instruction to perform the read operation has errors that are correctable, and as a bad block if read data that is returned from the semiconductor storage device in response to the instruction to perform the read operation has errors that are not correctable,
wherein the controller is configured to manage a partial bad block differently from a bad block,
wherein the controller is configured to instruct the semiconductor storage device to increase a threshold number of errors for determining that the write operation failed prior to a subsequent write operation on the block designated as a partial bad block, and
wherein the controller, after the subsequent write operation on the block designated as a partial bad block, sends a command for decreasing the threshold number of errors to the semiconductor storage device.

US Pat. No. 10,170,182

RESISTANCE CHANGE MEMORY DEVICE CONFIGURED FOR STATE EVALUATION BASED ON REFERENCE CELLS

IMEC vzw, Leuven (BE)

1. A memory device comprising:a plurality of memory cells arranged in an array, wherein each memory cell comprises a memory element configured to be switched between at least two resistance states; and
a plurality of word lines and a plurality of bit lines crossing each other, wherein each of the memory cells is formed at a crossing between one of the word lines and one of the bit lines,
wherein the memory cells are configured to be connected to a source line,
wherein each bit line has a bit line capacitance and is configured to store a charge associated with a state of a selected memory element,
wherein at least two memory cells electrically connected between one of the word lines and at least two different bit lines are configured as reference cells, wherein one of the reference cells is in a high resistance state and the other of the reference cells is in a low resistance state, and
wherein the at least two different bit lines electrically connected to the reference cells are interconnected by an equalizing switch configured to equalize charges associated with bit line capacitances of the at least two bit lines; and
a memory controller configured to select any of the word lines as a reference word line, such that different ones of the word lines can be used as reference word lines at different times.

US Pat. No. 10,170,179

DATA STORAGE DEVICE AND OPERATING METHOD FOR DATA STORAGE DEVICE

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:a flash memory, including K dies, wherein each die contains N planes, each plane contains a plurality of blocks, each block contains a plurality of pages, each word line is shared by M pages within the same block, and each of K, N and M is an integer greater than 1; and
a controller, writing a first patch of data that contains L pages issued by a host to L pages of a first die of the K dies, wherein L is a product of N and M, the L pages of the first die are provided by N planes of the first die with each plane of the first die using one block to provide M pages sharing the same word line, and the L pages contained in the first patch of data are written to the N planes of the first die in an interleaved way.

US Pat. No. 10,170,157

METHOD AND APPARATUS FOR FINDING AND USING VIDEO PORTIONS THAT ARE RELEVANT TO ADJACENT STILL IMAGES

Apple Inc., Cupertino, C...

1. A method of producing an enhanced image comprising:capturing a first plurality of images, wherein the first plurality of images comprises:
a snapshot image, wherein the snapshot image is captured in response to receiving a snapshot indication through a user interface;
a pre-capture image sequence, wherein the pre-capture image sequence comprises a plurality of images captured prior to capturing the snapshot image, and wherein the snapshot indication is received after capturing at least one of the plurality of images of the pre-capture image sequence; and
a post-capture image sequence, wherein the post-capture image sequence comprises a plurality of images captured after capturing the snapshot image;
obtaining motion information for each of the first plurality of images;
determining, for each image of the pre-capture image sequence and the post-capture image sequence, whether the motion information of a respective image meets a first motion criterion, wherein the first motion criterion comprises a comparison between the motion information of the respective image and the motion information of the snapshot image;
identifying a first subset of images from among the pre-capture image sequence that meet the first motion criterion;
identifying a second subset of images from among the post-capture image sequence that meet the first motion criterion; and
creating an enhanced image comprising the snapshot image, the first subset of images, and the second subset of images.

US Pat. No. 10,170,154

SYMMETRICALLY MIRRORED VIDEO SEGMENT

Virtual Dreamware, LLC, ...

1. A method for producing a symmetrically mirrored video segment comprising:selecting a video segment;
dividing said video segment into two equal segments;
reducing said two equal segments with an aspect ratio equation that when converted creates a symmetrical mirrored video segment;
adding an audio soundtrack to said symmetrical mirrored video segment;
playing said symmetrical mirrored video segment on a viewing device.

US Pat. No. 10,170,144

MAGNETIC TAPE DEVICE AND HEAD TRACKING SERVO METHOD

FUJIFILM Corporation, To...

1. A magnetic tape device comprising:a magnetic tape; and
a servo head,
wherein the servo head is a magnetic head including a tunnel magnetoresistance effect type element as a servo pattern reading element,
the magnetic tape includes a non-magnetic support, and a magnetic layer including ferromagnetic powder, a binding agent, and fatty acid ester on the non-magnetic support,
the magnetic layer includes a servo pattern,
a center line average surface roughness Ra measured regarding a surface of the magnetic layer is equal to or smaller than 2.0 nm,
a full width at half maximum of spacing distribution measured by optical interferometry regarding the surface of the magnetic layer before performing a vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 7.0 nm,
a full width at half maximum of spacing distribution measured by optical interferometry regarding the surface of the magnetic layer after performing the vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 7.0 nm,
a difference Safter?Sbefore between a spacing Safter measured by optical interferometry regarding the surface of the magnetic layer after performing the vacuum heating with respect to the magnetic tape and a spacing Sbefore measured by optical interferometry regarding the surface of the magnetic layer before performing the vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 8.0 nm, and
a ratio Sdc/Sac of an average area Sdc of a magnetic cluster of the magnetic tape in a DC demagnetization state and an average area Sac of a magnetic cluster of the magnetic tape in an AC demagnetization state measured with a magnetic force microscope is 0.80 to 1.30.

US Pat. No. 10,170,142

SYSTEM AND METHOD FOR COMPENSATING FOR RADIAL INCOHERENCE ASSOCIATED WITH READING SERVO SECTORS

Marvell International Ltd...

1. A system for compensating radial incoherence while reading servo data from a rotating storage medium, the system comprising:an equalizer to (i) receive a digital signal comprising a bit sequence of the servo data read from the rotating storage medium, and (ii) equalize the digital signal via a plurality of filters, wherein at least some of the plurality of filters are to phase rotate the digital signal to generate a plurality of phase rotated signals;
a Viterbi detector to operate based on a trellis state machine, wherein the trellis state machine comprises a plurality of main branches, wherein each of the plurality of main branches comprises a plurality of sub-branches, wherein each of the plurality of main branches is to receive the plurality of phase rotated signals respectively at corresponding ones of the plurality of sub-branches, and wherein the Viterbi detector is to (i) determine branch metrics for each of the sub-branches, (ii) determine a minimum branch metric among all the branch metrics of the plurality of sub-branches for each of the plurality of main branches, and (iii) process the minimum branch metric as a representative of a corresponding branch using an add-compare-select process of the Viterbi detector to determine a most likely received bit sequence; and
a servo control module to adjust a location of a read/write head of the rotating storage medium based on the most likely received bit sequence.

US Pat. No. 10,170,138

TAPE APPARATUS HAVING AN ARRAY OF WRITE TRANSDUCERS EACH HAVING AT LEAST THREE LAYERS OF COILS

International Business Ma...

1. A magnetic recording tape writing apparatus, comprising:an array of write transducers extending along a common tape bearing surface, each of the write transducers having:
a lower pole having a lower pole tip;
a lower coil layer above the lower pole;
an intermediate coil layer above the lower coil layer;
an upper coil layer above the intermediate coil layer;
an upper pole above the upper coil layer, the upper pole having an upper pole tip, the upper coil layer having multiple coil turns positioned between the upper pole and the intermediate coil layer, wherein the multiple coil turns are in a common plane of deposition, the intermediate coil layer having a plurality of turns in a second common plane of deposition, wherein the intermediate coil layer has more coil turns than the upper coil layer;
a nonmagnetic write gap between the pole tips, a plane of deposition of the write gap extending between the intermediate coil layer and the upper coil layer; and
a layer positioned between the write gap and the upper pole tip, the layer having a higher magnetic moment than the upper pole,
wherein a width of each coil, measured along a respective plane of deposition thereof in a track width direction, is less than 44 microns.

US Pat. No. 10,170,135

AUDIO GAIT DETECTION AND IDENTIFICATION

Intel Corporation, Santa...

1. An audio gait detection system comprising:network interface circuitry to receive audio input data from a plurality of microphone devices dispersed within a home;
a processor coupled to the network interface circuitry;
one or more memory devices coupled to the processor, the one or more memory devices including instructions, which when executed by the processor, cause the system to:
pre-process the audio input data to combine and strengthen an audio gait signal;
detect a sound of one or more footsteps from the audio gait signal; and
identify a person associated with the one or more footsteps using a set of trained footstep identification (ID) classifiers, wherein each trained footstep ID classifier is to be mapped to the gait of the person in the home based on a particular combination of personal profile, footwear, and floor surface within the home.

US Pat. No. 10,170,133

ACOUSTIC ENHANCEMENT BY LEVERAGING METADATA TO MITIGATE THE IMPACT OF NOISY ENVIRONMENTS

1. A system, comprising:a memory that stores instructions;
a processor that executes the instructions to perform operations, the operations comprising:
determining that an audio stream includes an interference signal if a first portion of the audio stream correlates with metadata that identifies the interference signal;
cancelling, if the audio stream is determined to include the interference signal, the interference signal from the audio stream, wherein the interference signal is cancelled from the audio stream based on a pattern of usage of an interfering device that outputted the interference signal; and
transmitting, after cancelling the interference signal, a remaining portion of the audio stream to an intended destination.

US Pat. No. 10,170,132

ECHO-CANCELLING DEVICE AND ECHO-CANCELLING METHOD

AVERMEDIA TECHNOLOGIES, I...

1. An echo-cancelling device, which is electrically and externally connected to an electronic device, wherein an output signal and an external reference signal are generated by the electronic device according to a first sound signal, and an output audio is generated by the electronic device according to the output signal, comprising:an audio input-output (I/O) terminal selected from a universal serial bus (USB) terminal, a high definition multimedia interface (HDMI) terminal, a Thunderbolt terminal, an IEEE 1394 terminal or a PCI Express terminal, being electrically and externally connected to the electronic device to receive the external reference signal from the electronic device;
an audio-receiving module receives an input audio and the output audio, and generates an analog input signal with the input audio and the output audio;
an analog-to-digital (A/D) converter is electrically connected to the audio-receiving module to receive the analog input signal and generates a digital input signal according to the analog input signal; and
a processor is electrically connected to the A/D converter and the audio I/O terminal to receive the external reference signal via the audio I/O terminal and receive the digital input signal from the A/D converter so as to cancel the output audio and generate a second sound signal, which is transmitted to the electronic device via the audio I/O terminal.

US Pat. No. 10,170,129

APPARATUS FOR ENCODING A SPEECH SIGNAL EMPLOYING ACELP IN THE AUTOCORRELATION DOMAIN

Fraunhofer-Gesellschaft z...

1. An apparatus for encoding a speech signal by determining a codebook vector of a speech coding algorithm for encoding the speech signal, wherein the apparatus comprises:a matrix determiner for determining an autocorrelation matrix R, and
a codebook vector determiner for determining the codebook vector of the speech coding algorithm for encoding the speech signal depending on the autocorrelation matrix R,
wherein the matrix determiner is configured to determine the autocorrelation matrix R by determining vector coefficients of a vector r, wherein the autocorrelation matrix R comprises a plurality of rows and a plurality of columns, wherein the vector r indicates one of the columns or one of the rows of the autocorrelation matrix R, wherein
R(i,j)=r(|i?j|),
wherein R(i, j) indicates the coefficients of the autocorrelation matrix R, wherein i is a first index indicating one of a plurality of rows of the autocorrelation matrix R, and wherein j is a second index indicating one of the plurality of columns of the autocorrelation matrix R,
wherein the codebook vector determiner is configured to determine the codebook vector of the speech coding algorithm for encoding the speech signal by applying the formula

wherein R is the autocorrelation matrix, wherein R is a Hermitian Toeplitz matrix, and wherein ê is one of the codebook vectors of the speech coding algorithm for encoding the speech signal, wherein f(ê) is a normalized correlation, and wherein dT is defined according to

wherein e is an original, unquantized residual signal,
wherein T indicates a transpose of a vector, and
wherein at least one of the matrix determiner and the codebook vector determiner comprises a hardware implementation.

US Pat. No. 10,170,126

EFFECTIVE ATTENUATION OF PRE-ECHOES IN A DIGITAL AUDIO SIGNAL

ORANGE, Paris (FR)

1. A method comprising:processing attenuation of pre-echo in a digital decoded audio signal by a processing device, wherein the processing comprises:
receiving at an input of the processing device a decoded signal in a communication network from a decoder device that has decoded the digital audio signal according to a transform decoding into the decoded signal, without the processing device receiving auxiliary information regarding the digital audio signal for attenuation of the pre-echo;
decomposition of the decoded signal into at least two sub-signals according to a predetermined decomposition frequency criterion, the decomposition being performed by a first low-pass filtering in the form of a finite impulse response filtering with zero transfer function phase:
c(n)z?1+(1?2c(n))+c(n)z
with c(n) being a coefficient lying between 0 and 0.25, to obtain a first sub-signal, a second sub-signal being obtained by subtraction of the first sub-signal from the decoded signal;
computation of respective attenuation factors per sub-signal and per sample of a previously determined pre-echo zone;
attenuation of pre-echo in the pre-echo zone of each of the sub-signals by application of the respective attenuation factors to the sub-signals;
producing an attenuated, processed digital audio signal by combining the attenuated sub-signals, in which the pre-echo attenuation has been performed; and
outputting the attenuated, processed digital audio signal on an output of the processing device so that the processed digital audio signal can be played.

US Pat. No. 10,170,124

VOICE-CONTROLLED COMPUTER SYSTEM

MASTERCARD INTERNATIONAL ...

1. A voice-controlled computer system comprising:a headset with a heads up display (HUD),
wherein when the system requires a user to verbally enter an alphanumeric security code, the system is configured to display on the HUD, to the user, a first plurality of different pairs of alphanumeric characters, from which the user may verbally select, each pair of the plurality of different pairs of alphanumeric characters including a first character and an associated, randomly generated second character,
wherein the first character of each pair of the plurality of different pairs of alphanumeric characters is a character of the alphanumeric security code to be entered,
wherein the system is configured to:
receive a verbal entry of the associated second character of a pair of the first plurality of different pairs of alphanumeric characters displayed on the HUD,
upon successful recognition of the verbal entry of the associated second character of the pair of the first plurality of different pairs of alphanumeric characters, change the display on the HUD such that a second plurality of different pairs of alphanumeric characters, from which the user may verbally select, is displayed thereon, said second plurality of different pairs differing from said first plurality of different pairs, and
decipher the verbal entry of the associated second character of the pair of the first plurality of different pairs as equivalent to entry of the first character of the pair of the first plurality of different pairs.

US Pat. No. 10,170,123

INTELLIGENT ASSISTANT FOR HOME AUTOMATION

Apple Inc., Cupertino, C...

1. A method for controlling electronic devices using a virtual assistant on a user device having a memory and at least one processor, the method comprising: at the user device:receiving, an audio input comprising user speech;
transmitting data corresponding to the audio input to one or more servers;
receiving, from the one or more servers:
an identification of a first electronic device determined by the one or more servers based on the data corresponding to the audio input; and
a first command to be performed by the first electronic device determined by the one or more servers based on the data corresponding to the audio input;
transmitting the first command to the first electronic device;
receiving, after transmitting the first command to the first electronic device, a second audio input;
transmitting a state query to the first electronic device in accordance with the second audio input;
receiving, from the first electronic device, a current state of the first electronic device; and
transmitting the current state of the first electronic device to the one or more servers to be stored as at least a portion of a configuration, wherein the configuration defines a plurality of states of a plurality of corresponding electronic devices to use in response to a command that references the configuration.

US Pat. No. 10,170,120

CALL MANAGEMENT SYSTEM AND ITS SPEECH RECOGNITION CONTROL METHOD

1. A call management system for recording a call from an external line, performing speech-recognition, speech-to-text converting the call, and displaying text, comprising:a speech recognition server that performs speech recognition on recording data of call data including audio data, and outputs text data,
wherein the speech recognition server includes:
one or more processors which are configured to execute a speech recognition engine that performs speech recognition on the audio data and speech-to-text converts the data; and
a memory configured to store a mode control table that holds a speech recognition mode for each call,
wherein the speech recognition engine includes:
a mode management unit that designates a speech recognition mode for a decoder; and
an output analysis unit that analyzes recognition result data that is speech-to-text converted by the speech recognition,
wherein the output analysis unit designates the speech recognition mode for the mode management unit based on the result of analysis of the recognition result data that is speech-to-text converted by the speech recognition,
wherein the mode management unit rewrites the speech recognition mode held in the mode control table based on the designation with the output analysis unit for each call, and designates the speech recognition mode for the decoder based on the speech recognition mode held in the mode control table for each call,
wherein, in a first mode of the speech recognition, the decoder reduces the number of language models to be referred to, and reduces the number of candidates to be presented as an intermediate result, and
wherein, in a second mode of the speech recognition, the decoder increases the number of language models to be referred to, and increases the number of candidates to be presented as the intermediate result.

US Pat. No. 10,170,118

TELEPHONY SYSTEM WITH A BACKGROUND RECAPILATION FEATURE

1. A telephony system comprising:a processor; and
a memory, wherein the memory stores instructions that, when executed by the processor, cause the processor to:
establish a telephony session between a first communication appliance and a second communication appliance;
record a conversation of the telephony session in response to establishing the telephony session;
receive a request from at least one of the first communication appliance, the second communication appliance, or a third communication appliance not already participating in the telephony session, wherein the request is for the third communication appliance to join the telephony session;
in response to receiving the request:
extend the telephony session to the third communication appliance;
stop recording the telephony session; and
automatically transcribe the recorded conversation into a text transcript, wherein the instructions that cause the processor to automatically transcribe include instructions that cause the processor to wait to receive the request before initiating the transcription; and
provide the text transcript of the conversation to the third communication appliance in response to the extending of the telephony session to the third communication appliance for causing display of the text transcript on a display device associated with the third communication appliance, wherein the text transcript comprises at least a portion of the conversation prior to the extending of the telephony session to the third communication appliance.

US Pat. No. 10,170,116

MAINTAINING CONTEXT FOR VOICE PROCESSES

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:receiving audio data from a first device;
determining that the audio data corresponds to an interaction associated with a first process;
sending, to a second device associated with the first process, a first request to operate the first process based on the interaction;
determining to halt a session associated with the first process at a first time;
determining that the first process is capable of using progress data to represent a current status of the first process;
determining first progress data corresponding to the first process, wherein the first progress data includes information about a first status of the first process at the first time;
associating the first progress data with an identity of the first process in a user profile associated with the first device; and
halting the session associated with the first process.

US Pat. No. 10,170,112

DETECTING AND SUPPRESSING VOICE QUERIES

Google LLC, Mountain Vie...

1. A computer-implemented method, comprising:receiving, by a system of one or more computers and from a plurality of client devices, a plurality of voice query processing requests, each voice query processing request referencing a respective voice query;
identifying, by the system, that a value that is based on a number of voice query processing requests received by the system during a specified time interval satisfies one or more criteria;
in response to identifying that the value that is based on the number of voice query processing requests received by the system during the specified time interval satisfies the one or more criteria, analyzing at least some of the voice query processing requests to determine a set of voice query processing requests that each reference a common voice query, including:
(i) for each analyzed voice query processing request, generating an electronic fingerprint for the respective voice query referenced by the voice query processing request, wherein the electronic fingerprint models acoustic features of the respective voice query, and
(ii) determining matches among the electronic fingerprints for the respective voice queries referenced by the analyzed voice query processing requests based on comparison of the acoustic features of at least some of the electronic fingerprints; and
suppressing performance of operations indicated by the common voice query in one or more voice query processing requests subsequently received by the system.

US Pat. No. 10,170,106

PARAMETER COLLECTION AND AUTOMATIC DIALOG GENERATION IN DIALOG SYSTEMS

GOOGLE LLC, Mountain Vie...

1. A method for intent parameter collection, the method comprising:receiving a speech input of a user, the speech input of the user provided via a dialog system interface of a client device;
processing the speech input, using an automatic speech recognizer, to identify at least one predetermined intent keyword;
identifying a dialog system intent associated with the speech input based on the at least one predetermined intent keyword being previously defined, via a platform interface, as a trigger for the dialog system intent, the dialog system intent having required intent parameters previously defined via the platform interface as required, and having optional intent parameters previously defined via the platform interface as optional;
extracting, from the speech input, first optional data for a first optional intent parameter of the optional intent parameters,
wherein no optional data for a second optional intent parameter, of the optional intent parameters, is extracted from the speech input;
determining whether data for all required intent parameters of the dialog system are available without initiating a parameter collection dialog associated with the dialog system intent;
based on the determination:
selectively initiating performance of an action, based on the data for all the required intent parameters and based on the first optional data, without initiating a parameter collection dialog, when the data for all the required intent parameters are available without initiating the parameter collection dialog;
selectively initiating a parameter collection dialog associated with the dialog system intent, the parameter collection dialog being operable to collect data, for the required intent parameters not otherwise available to the dialog system, but not for the optional intent parameters, until data for all of the required intent parameters are determined, wherein when the parameter collection dialog is initiated, the method further comprises:
identifying a prompt defined for a given missing required intent parameter, the given missing intent parameter being one of one or more missing required intent parameters of the required intent parameters for which data is not available, and the prompt being previously defined for the given missing required intent parameter via the platform interface,
causing the prompt to be presented via the dialog system interface of the client device,
receiving an additional speech input of the user in response to the prompt, the additional speech input of the user provided via the dialog system interface of the client device,
processing the additional speech input to determine data for at least the given missing required intent parameter from the additional speech input,
after the processing, determining whether data for all of the missing required intent parameters are determined, and
based on the determination, selectively providing one or more additional prompts and processing one or more responsive additional speech inputs until data for all of the missing required intent parameters are determined; and
based on the dialog system intent, the data for all the required intent parameters, and the first optional data for the first optional intent parameter: generating an action instruction, wherein the action instruction, when executed, causes a server or the client device to implement the action based on the data for all the required intent parameters and the first optional data for the first optional intent parameter.

US Pat. No. 10,170,105

METHOD AND APPARATUS FOR EVALUATING TRIGGER PHRASE ENROLLMENT

Google Technology Holding...

1. A computer-implemented method comprising:during a trigger phrase enrollment process:
prompting, by a speech recognition-enabled electronic device, a user of the speech recognition-enabled electronic device to speak a trigger phrase;
receiving, at the speech recognition-enabled electronic device, a first audio signal corresponding to the user speaking the trigger phrase;
determining, by the speech recognition-enabled electronic device, a first number of frames in the first audio signal that have a measure of noise variability of background noise exceeding a noise variability threshold;
determining, by the speech recognition-enabled electronic device, a second number of frames in the first audio signal that have voice activity; and
when the first number of frames in the first audio signal is less than a threshold value and when the second number of frames in the first audio signal is within a frame count threshold range, training, by the speech recognition-enabled electronic device, a trigger phrase model with the first audio signal corresponding to the user speaking the trigger phrase, the trigger phrase model configured to detect the trigger phrase in a spoken utterance; and
after the trigger phrase enrollment process:
receiving, at the speech recognition-enabled electronic device and while the speech recognition-enabled electronic device is in a sleep mode, a second audio signal including an utterance of the trigger phrase spoken by the user; and
detecting, by the speech recognition-enabled electronic device and using the trigger phrase model trained during the trigger phrase enrollment process, the utterance of the trigger phrase in the second audio signal, the trigger phrase when detected in the second audio signal causing the speech recognition-enabled electronic device to wake from the sleep mode, the sleep mode comprising a power-saving mode of operation in which one or more parts of the speech recognition-enabled electronic device are in a low-power state or powered off.

US Pat. No. 10,170,104

ELECTRONIC DEVICE, METHOD AND TRAINING METHOD FOR NATURAL LANGUAGE PROCESSING

SONY CORPORATION, Tokyo ...

1. An electronic device for natural language processing, comprising:a processor configured to:
for each of words obtained by segmenting a sentence in a training data set, determine attention parameters representing correlation between the word and each of other words in the sentence, wherein the words are represented by respective word vectors;
for each of the words, determine a context vector based on a sum of the word vectors of the other words in the sentence that are weighted based on the corresponding attention parameters; and
determine parameters of a trained neural network by training a neural network, based on label information of the sentence in the training data set, the word vectors, and context vectors for the words, the trained neural network being configured by the determined parameters to perform sentence classification on another sentence.

US Pat. No. 10,170,101

SENSOR BASED TEXT-TO-SPEECH EMOTIONAL CONVEYANCE

International Business Ma...

1. A method for assigning phonetic data to a textual message for synthesis of an audio version of the textual message, the method comprising the steps of:receiving, from a user of a mobile device, a plurality of vocal samples;
determining a first set of phonetic data from the plurality of vocal samples based, at least in part, on:
segmenting each vocal sample in the plurality of vocal samples into a plurality of phonetic units; and
identifying a plurality of acoustic parameters corresponding to each of the plurality of phonetic units;
indexing a first set of phonetic units derived from the plurality of phonetic units based, at least in part, on:
identifying a correlation between acoustic parameters corresponding to phonetic units segmented from the plurality of vocal samples and a first emotional state of the user during a period of time in which each of the vocal samples are generated;
determining, based on physical characteristics associated with the user of the mobile device, the first emotional state of the user during a period of time which the textual message is generated via the mobile device;
comparing the first emotional state of the user with a context of the textual message;
determining, based on the comparison, that the first emotional state of the user matches the context of the textual message;
assigning, in response to determining that the first emotional state of the user matches the context of the textual message, acoustic parameters associated with those phonetic units in the first set of phonetic units that correspond to phonetic transcriptions of the textual message, wherein: the acoustic parameters are predicted to convey, to a listener, the first emotional state of the user; and
synthesizing, via speech synthesizer software, an audio version of the textual message based, at least in part, on the acoustic parameters.

US Pat. No. 10,170,100

SENSOR BASED TEXT-TO-SPEECH EMOTIONAL CONVEYANCE

International Business Ma...

1. A computer program product for assigning phonetic data to a textual message for synthesis of an audio version of the textual message, the computer program product comprising one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising instructions to:receive, from a user of a mobile device, a plurality of vocal samples;
determine a first set of phonetic data from the plurality of vocal samples based, at least in part, on instructions to:
segment each vocal sample in the plurality of vocal samples into a plurality of phonetic units; and
identify a plurality of acoustic parameters corresponding to each of the plurality of phonetic units;
index a first set of phonetic units derived from the plurality of phonetic units based, at least in part, on instructions to:
identify a correlation between acoustic parameters corresponding to phonetic units segmented from the plurality of vocal samples and a first emotional state of the user during a period of time in which each of the vocal samples are generated;
determine, based on physical characteristics associated with the user of the mobile device, the first emotional state of the user during a period of time which the textual message is generated via the mobile device;
compare the first emotional state of the user with a context of the textual message;
determine, based on the comparison, that the first emotional state of the user matches the context of the textual message;
assign, in response to determining that the first emotional state of the user matches the context of the textual message, acoustic parameters associated with those phonetic units in the first set of phonetic units that correspond to phonetic transcriptions of the textual message, wherein: the acoustic parameters are predicted to convey, to a listener, the first emotional state of the user; and
synthesize, via speech synthesizer software, an audio version of the textual message based, at least in part, on the acoustic parameters.