US Pat. No. 10,193,754

SYSTEM AND METHOD FOR SUPPORTING CONNECTORS IN A MULTITENANT APPLICATION SERVER ENVIRONMENT

ORACLE INTERNATIONAL CORP...

1. A system for supporting use of connectors in a multitenant application server environment, comprising:one or more computers, including an application server that enables deployment and execution of software applications, wherein the application server is associated with a domain configuration that is used at runtime to define a domain for execution of the software applications, and a plurality of partitions,
wherein each of the plurality of partitions is associated with a partition configuration, and wherein each partition provides a subdivision of the domain and includes one or more resource groups of a plurality of resource groups, wherein the one or more resource groups are defined by one or more resource group templates;
one or more deployed partition-level resource adapters, each of the one or more deployed partition-level resource adapters being deployed in a resource group of a partition of the plurality of partitions;
a connector container, wherein the connector container determines a partition scope of the one or more deployed partition-level resource adapters, wherein the partition scope is used to identify a partition identification (partition ID), based on a component invocation context, of a partition of the plurality of partitions within which a partition-level resource adapter is deployed; and
a partition classloader, the partition classloader deploying the one or more deployed partition-level resource adapters, the one or more deployed partition-level resource adapters being an instantiated version of a deployable resource adapter;
wherein, based upon the identified partition ID of partition of the plurality of partitions within which the partition-level resource adapter is deployed, access to the partition-level resource adapter is restricted to applications and resources within the partition associated with the identified partition ID.

US Pat. No. 10,193,751

SYSTEM, METHOD AND APPARATUS FOR CONFIGURING A NODE IN A SENSOR NETWORK

Senseware, Inc., Vienna,...

1. A method, comprising:receiving, by a sensor data control system, a request to change a configuration of a wireless node in a wireless sensor network at a monitored location, the wireless node supporting one or more sensors at the monitored location;
transmitting, by the sensor data control system, a configuration message for delivery to the wireless node, the configuration message including configuration information that enables the wireless node to change at least one configuration setting used by the wireless node in controlling a delivery of sensor data from the one or more sensors to the sensor data control system;
generating, by the sensor data control system, a first configuration hash value using a hash function having an input based on the at least one configuration setting identified by the request;
receiving, by the sensor data control system from a gateway device at the monitored location, a status message associated with the wireless node at the monitored location, the status message including a second configuration hash value generated by the wireless node using the hash function and having an input based on current configuration settings of the wireless node;
comparing, by the sensor data control system, the first configuration hash value to the second configuration hash value; and when the comparison indicates that the first configuration hash value is different from the second configuration hash value, retransmitting, by the sensor data control system to the gateway device, the configuration message based on the request to effect a change in the current configuration settings of the wireless node.

US Pat. No. 10,193,750

MANAGING VIRTUAL PORT CHANNEL SWITCH PEERS FROM SOFTWARE-DEFINED NETWORK CONTROLLER

CISCO TECHNOLOGY, INC., ...

1. A computer-implemented method for configuring a virtual port channel (VPC) domain comprising:determining that a first switch and a second switch are connected in a pair of switch peers in the VPC domain via a shared VPC-peerlink;
determining, by the first switch, that the first switch is in a primary role;
determining a first unique identifier for the first switch, a first VPC portchannel number for the first switch, and a first orphan port number for the first switch;
receiving, from the second switch via the VPC-peerlink, a second unique identifier for the second switch, a second VPC portchannel number for the second switch, and a second orphan port number for the second switch;
associating the second VPC portchannel number for the second switch and the first VPC portchannel number for the first switch with a unified VPC portchannel number;
creating a first unique orphan port number for the first switch and a second unique orphan port number for the second switch;
sending, to a controller along with a request for port configuration data, the unified VPC portchannel number and the first unique orphan port number and the second unique orphan port number; and
receiving, by the first switch from the controller, the port configuration data in the form of VLAN address configuration data.

US Pat. No. 10,193,749

MANAGED FORWARDING ELEMENT EXECUTING IN PUBLIC CLOUD DATA COMPUTE NODE WITHOUT OVERLAY NETWORK

NICIRA, INC., Palo Alto,...

1. A method for a network controller that manages a logical network implemented in a public datacenter comprising forwarding elements to which the network controller does not have access, the method comprising:identifying a data compute node, that operates on a host machine in the public datacenter, to attach to the logical network, the data compute node having a network interface with a network address provided by a management system of the public datacenter, wherein the data compute node executes (i) a workload application and (ii) a managed forwarding element comprising a first bridge that connects via an internal port to the workload application and a second bridge that connects to the network interface of the data compute node; and
distributing configuration data for configuring the managed forwarding element, wherein, based on the configuration data, the managed forwarding element receives data packets sent to and from the workload application on the data compute node and performs network security processing on the data packets with the first bridge without performing logical forwarding operations, wherein the data packets sent by the workload application have the provided network address as a source address when received by the managed forwarding element and are not encapsulated by the managed forwarding element before being transmitted from the data compute node.

US Pat. No. 10,193,747

FAULT DETECTION METHOD AND DEVICE

HUAWEI DEVICE CO., LTD., ...

1. A method for fault detection, comprising:receiving, by a terminal device, a touch control operation performed by a user on a preset fault detection key;
determining, by the terminal device, a fault detection instruction according to the touch control operation;
determining, by the terminal device, a service type of a to-be-detected fault according to the fault detection instruction, wherein the to-be-detected fault is a type of fault that the fault detection instruction designates for detection, and the service type of the to-be-detected fault is that of a service that is configured to process information that is of a same type as the type of the to-be-detected fault;
determining, by the terminal device, fault detection content according to the service type, wherein the fault detection content includes operational information associated with successful operation of the service that is configured to process the information that is of the same type as the type of the to-be-detected fault;
analyzing, by the terminal device, the fault detection content including the operational information to obtain a detection result; and
presenting, by the terminal device, the detection result.

US Pat. No. 10,193,746

DEADLOCK AVOIDANCE USING MODIFIED ETHERNET CONNECTIVITY FAULT MANAGEMENT SIGNALING

Juniper Networks, Inc., ...

1. A first maintenance endpoint (MEP) device, comprising:a memory; and
one or more processors to:
identify that a first interface of the first MEP device is associated with a connectivity failure;
provide, to a second MEP device, a first continuity check message (CCM), that includes a MEP identifier of the first MEP device, based on identifying that the first interface of the first MEP device is associated with the connectivity failure,
the first CCM to cause the second MEP device to invoke an action profile,
the second MEP device to designate a second interface of the second MEP device as being offline based on the action profile;
receive, from the second MEP device, a second CCM, that includes the MEP identifier of the first MEP device and information indicating that the second interface of the second MEP device is offline, based on the second MEP device designating the second interface of the second MEP device as being offline; and
execute a rule to avoid a deadlock situation based on the second CCM including the MEP identifier of the first MEP device.

US Pat. No. 10,193,745

RADIO INTERRUPT

Hewlett Packard Enterpris...

1. An apparatus, comprising:a first processing resource connected via an interface to a second processing resource, the first processing resource to execute instructions to:
receive an interrupt generated by a radio coupled to the second processing resource;
increment a counter in response to receiving the interrupt during a configurable time interval;
determine that the counter has not been incremented during a threshold number of configurable time intervals, wherein a duration of a threshold time interval included in the threshold number of configurable time intervals is configurable; and
reboot the first processing resource and the second processing resource in response to the determination that the counter has not been incremented during the threshold number of configurable time intervals.

US Pat. No. 10,193,744

MASS RESTORATION OF ENTERPRISE BUSINESS SERVICES FOLLOWING SERVICE DISRUPTION

INTUIT INC., Mountain Vi...

1. A computer-implemented method for restoring a plurality of services of an application in a computer network following a service disruption, the method comprising:identifying, via a processor, one or more servers hosting at least one of the services;
identifying at least a first dependency between the at least one of the services and another one of the plurality of services;
generating a run list comprising one or more scripts for restoring the plurality of services in one or more successive phases, wherein each successive phase is determined based on the at least a first dependency, wherein each script is associated with one of the plurality of services and comprises instructions for one of starting, stopping, or restarting the service; and
based on the run list:
saving data of a downstream dependent service in a temporary restoration directory, wherein the downstream dependent service depends on the at least one of the services;
stopping the downstream dependent service;
restarting the at least one of the services;
restarting the downstream dependent service; and
loading the data of the downstream dependent service saved in the temporary restoration directory into the downstream dependent service.

US Pat. No. 10,193,738

METHOD FOR SERVICE CONTENT DISTRIBUTION UNDER HETEROGENEOUS NETWORK AND SERVICE MANAGEMENT PLATFORM

1. A method for service content distribution under a heterogeneous network, comprising:storing and maintaining, by a joint radio resource management server of a service management platform, context information of a network and a terminal, wherein the context information of the network comprises: a network description, a general resource of the network and context information of a stream, and the context information of the terminal comprises: context information of the terminal about communication, computation, service presentation; and
making a request, by an edge server of the service management platform, to the joint radio resource management server for an index of the context information when receiving a service request from an initiator terminal;
transmitting, by the joint radio resource management server, the index of the context information to the edge server after receiving the request from the edge server;
comparing, by the edge server, the service request with the index of the context information to select a cooperative network and a cooperative terminal in the cooperative network for service content distribution, and performing the service content distribution according to the cooperative network and the cooperative terminal in the cooperative network, so that the edge server transmits requested service content to the initiator terminal of the service request through the selected cooperative network and the cooperative terminal in the cooperative network;
wherein performing the service content distribution according to the cooperative network and the cooperative terminal in the cooperative network comprises:
performing, by the edge server of the service management platform, comparative analysis on information in the service request and an index of service data information buffered by the edge server of the service management platform itself, judging whether the requested service content has been stored in the edge server of the service management platform according to the comparative analysis, when the requested service content has been stored in the edge server of the service management platform, distributing corresponding stored service content to the cooperative network and the cooperative terminal in the cooperative network, and when the requested service content has not been stored in the edge server of the service management platform, making a request to service content providing equipment for corresponding service content and distributing acquired service content to the cooperative network and the cooperative terminal in the cooperative network;
the method further comprises: when multiple cooperative networks and cooperative terminals are selected, performing, by the edge server of the service management platform, service stream segmentation on service content when the service content is distributed, and transmitting service sub-streams obtained by the service stream segmentation to corresponding cooperative networks and cooperative terminals respectively.

US Pat. No. 10,193,736

CODING AND MODULATION APPARATUS USING NON-UNIFORM CONSTELLATION AND DIFFERENT PHY MODES

SONY CORPORATION, Tokyo ...

wherein the bit labeling indicated in groups A and B may alternatively be inverted for one or more bit labels.

US Pat. No. 10,193,734

METHOD FOR TRANSCEIVING SIGNAL IN A WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR THE SAME

LG ELECTRONICS INC., Seo...

1. A method for transceiving a signal in a wireless communication system supporting narrow-band (NB)-LTE, which is performed a terminal, the method performed by a terminal and comprising:receiving, from a base station, a narrow band synchronization signal;
acquiring time synchronization and frequency synchronization with the base station based on the narrow band synchronization signal and detecting an identifier of the base station; and
receiving, from the base station, broadcast information based on the detected identifier of the base station,
wherein the narrow band synchronization signal and the broadcast information are received through a narrow band (NB),
wherein the narrow band has a system bandwidth of 180 kHz and includes 12 subcarriers disposed at an interval of 15 kHz,
wherein the narrow band synchronization signal includes a narrow band primary synchronization signal and a narrow band secondary synchronization signal,
wherein the narrow band primary synchronization signal and the narrow band secondary synchronization signal are transmitted in different subframes, and
wherein the broadcast information is transmitted in a first subframe of a radio frame.

US Pat. No. 10,193,733

WIRELESS COMMUNICATION SYSTEM TO COMMUNICATE USING DIFFERENT BEAMWIDTHS

Intel Corporation, Santa...

1. A communication system to communicate in a wireless network via a wireless frequency band, the system comprising:an input to receive intermediate frequency signals;
radio frequency (RF) filter circuitry coupled to the input to receive the intermediate frequency signals therefrom, the RF filter circuitry including a mixer and a filter;
a frequency synthesizer coupled to the mixer; and
an amplifier coupled to the filter;
wherein:
the frequency synthesizer is to provide a carrier frequency to the mixer;
the mixer is to combine the intermediate frequency signals with the carrier frequency from the frequency synthesizer to generate combined carrier signals;
the filter is to filter the combined carrier signals to generate filtered carrier signals;
the amplifier is to amplify the filtered carrier signals to generate signals to be wirelessly transmitted by one or more antennas; and
the signals to be wirelessly transmitted include:
first signals corresponding to a first beamwidth when transmitted by the one or more antennas, the first signals to include first control signals comprising first beamforming control information to facilitate an initial beamforming for wireless communication via the wireless frequency band, the first control signals to include control signals to facilitate one or more of carrier frequency offset estimation, timing synchronization, and signal detection; and
second signals corresponding to a second beamwidth when transmitted by the one or more antennas, the second signals to include second control signals comprising second beamforming control information to facilitate a fine beamforming to supplement the initial beamforming, the first beamwidth to comprise a wider beamwidth than the second beamwidth.

US Pat. No. 10,193,727

SELECTIVE MUTING OF TRANSMISSION OF REFERENCE SIGNALS TO REDUCE INTERFERENCE IN A WIRELESS NETWORK

Sprint Spectrum L.P., Ov...

1. A method operable in a wireless communication network including a first base station configured for serving user equipment devices (UEs) within a first coverage area of the first base station, the method comprising:for a given transmission time interval (TTI) during which a plurality of downlink resource blocks (RBs) are scheduled to be transmitted to one or more UEs being served by the first base station, making a selection for a first subset of RBs of the plurality of a particular transmission mode (TM) for which a particular type of downlink reference signal is not required to be transmitted, wherein each of the scheduled RBs of the plurality is allocated one of a plurality of distinct groups of sub-carrier frequencies of a carrier band during the given TTI, and the particular type of downlink reference signal is scheduled to be transmitted on respective specific sub-carriers of all RBs of the plurality by default;
making a determination that for a second subset of RBs of the plurality, no condition exists that requires transmission of the particular type of downlink reference signal;
determining a third subset of RBs of the plurality as an overlap of the first and second subsets; and
muting transmission of the particular type of downlink reference signal on any of the sub-carriers of any of the third subset of RBs of the plurality during transmission in the TTI by the first base station of the plurality of downlink RBs.

US Pat. No. 10,193,725

APPARATUS AND METHOD FOR SENDING AND RECEIVING BROADCAST SIGNALS

LG ELECTRONICS INC., Seo...

1. A broadcast signal transmitter, comprising:a Forward Error Correction (FEC) encoder configured to perform error correction processing on Physical Layer Pipe (PLP);
a time interleaver configured to perform time-interleaving on the PLP data;
a framer configured to generate a signal frame comprising the PLP data;
a frequency interleaver configured to perform frequency-interleaving on the signal frame; and
a waveform generator configured to generate a transmission signal comprising the signal frame,
wherein the signal frame comprises a bootstrap, a preamble, and at least one subframe,
wherein the bootstrap comprises first information for indicating system bandwidth, second information for emergency alert wake up, and third information for indicating structure of the preamble,
wherein the preamble comprises at least one preamble symbol,
wherein the at least preamble symbol carries Layer 1 (L1) signaling data for the signal frame,
wherein a first preamble symbol of the at least one preamble symbol comprises fourth information,
wherein the fourth information indicates a number of at least one remaining preamble symbol other than the first preamble symbol,
wherein the first preamble symbol of the at least one preamble symbol has a minimum number of carriers (NoCs),
wherein the first preamble symbol comprises fifth information related to an NoC of the at least one remaining preamble symbol when the preamble comprises a plurality of preamble symbols, and
wherein the first preamble symbol is a foremost preamble symbol among the plurality of preamble symbols.

US Pat. No. 10,193,723

APPARATUS FOR TRANSMITTING AND RECEIVING A SIGNAL AND METHOD OF TRANSMITTING AND RECEIVING A SIGNAL

LG ELECTRONICS INC., Seo...

1. A method of transmitting a broadcast signal, the method comprising:first encoding signaling data;
padding the first-encoded signaling data with zero bits, the zero bits filling information bits required for second encoding;
second encoding the padded signaling data by appending parity bits; and
puncturing a portion of the appended parity bits from the second-encoded signaling data and removing the padded zero bits to generate forward error correction (FEC)-encoded signaling data that is punctured and has zero bits removed;
mapping the FEC-encoded signaling data into signaling symbols that include channel bonding information;
third encoding data according to at least one code rate;
mapping the third-encoded data onto constellations according to a symbol mapping method that includes Non-uniform QAM (Quadrature amplitude modulation);
building a signal frame based on a preamble symbol including the FEC-encoded signaling data and data symbols including the third-encoded data;
modulating the signal frame according to an OFDM (Orthogonal Frequency Division Multiplexing) scheme; and
transmitting the broadcast signal carrying the modulated signal frame.

US Pat. No. 10,193,719

SIGNAL PROCESSING METHOD, NETWORK EQUIPMENT, SYSTEM AND COMPUTER STORAGE MEDIUM

1. A signal processing method, applied to a sender network device and comprising:generating a first reference signal based on a frequency-domain density of the first reference signal and an energy value of the first reference signal on a time-frequency resource;
determining a time-frequency resource location of a target channel, the target channel being configured to carry information of a Licensed Assisted Access (LAA) system; and
generating a Clear Channel Assessment (CCA) signal based on the time-frequency resource location of the target channel and the first reference signal, mapping the CCA signal to the target channel, and sending the CCA signal to a receiver network device through the target channel to enable the receiver network device to determine whether the target channel is applicable to the LAA system according to the CCA signal.

US Pat. No. 10,193,718

METHOD FOR DATA MODULATION IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR THE SAME

ELECTRONICS AND TELECOMMU...

1. A data modulation apparatus comprising:a single-to-differential (S2D) conversion part including a first amplifier operating based on a carrier wave signal and two transformers receiving an output signal of the first amplifier;
a first switch part transferring status of input data to the first amplifier based on the input data;
a differential amplification part receiving output signals of the S2D conversion part and amplifying the output signals of the S2D conversion part;
a differential-to-signal (D2S) conversion part receiving output signals of the differential amplification part and performing modulation on the output signals of the differential amplification part by converting the output signals of the differential amplification part to a single signal; and
a second switch part transferring the output signals of the differential amplification part to the D2S conversion part based on the input data,
wherein the first switch part and the second switch part are alternately turned on and off, and
the two transformers include a first transformer connected to a first inductor of the first amplifier and a second transformer connected to a second inductor of the first amplifier, wherein the first inductor and the second inductor are connected in parallel with the first amplifier.

US Pat. No. 10,193,717

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first coupler;
an encoding circuit which executes differential Manchester encoding on digital data based on a clock inputted thereto via the first coupler, and which outputs an encoded data;
a second coupler; and
a demodulating circuit which demodulates the encoded data inputted thereto via the second coupler, wherein
the demodulating circuit includes
a first sampling circuit which samples the encoded data based on a sampling frequency set to be two times higher than that of the encoded data, and which outputs first sample data,
a second sampling circuit which samples the encoded data at a timing earlier than that in the first sampling circuit based on the sampling frequency, and which outputs second sample data,
a determination circuit which determines whether or not the first sample data and the second sample data match each other, and
a selection circuit which selects first phase data obtained by even-numbered sampling or second phase data obtained by odd-numbered sampling from the first sample data, on the basis of determination data generated at the determination circuit.

US Pat. No. 10,193,715

TRANSMISSION APPARATUS, RECEPTION APPARATUS, AND COMMUNICATION SYSTEM

Mitsubishi Electric Corpo...

1. A reception apparatus to receive a transmitted signal, which is obtained by converting a transmission signal including N (N is an integer equal to or larger than 2) symbols to a frequency domain signal having a first bandwidth, performing band limitation on the transmission signal converted to the frequency domain signal to obtain a frequency domain signal having a second bandwidth narrower than the first bandwidth, and converting the band-limited transmission signal to a time domain signal, the transmission signal converted to the time domain signal being transmitted at a set transmission interval, wherein the reception apparatus comprising:a receiver to perform sampling of a received signal, which is obtained by receiving the transmitted signal;
a time-frequency converter to convert the sampled received signal to a frequency domain signal;
an equalizer to perform frequency domain equalization processing based on the received signal converted to the frequency domain signal;
a frequency-time converter to convert the received signal that has undergone the frequency-domain equalization processing to a time domain signal; and
a demodulator to perform interference removal processing and demodulation based on the received signal converted to the time domain signal, repeatedly for a preset number of times,
wherein the receiver sets a sampling interval for sampling the received signal to a value obtained by multiplying the transmission interval by a value obtained by dividing the second bandwidth by the first bandwidth.

US Pat. No. 10,193,713

METHOD FOR SENDING AND RECEIVING SIGNAL, AND CORRESPONDING DEVICE AND SYSTEM

Huawei Technologies Co., ...

1. A method, comprising:performing, by a transmitter, constellation mapping on a data stream to obtain a mapped signal;
performing, by the transmitter, pre-filtering on the mapped signal to convert the mapped signal into a first filtered signal, wherein the pre-filtering is finite impulse response filtering, a bandwidth of the first filtered signal is less than a bandwidth of the mapped signal, and the first filtered signal is a baud rate signal;
performing, by the transmitter, waveform forming according to the first filtered signal to obtain a shaped signal;
performing, by the transmitter, digital-to-analog conversion on the shaped signal to obtain an analog signal;
sending, by the transmitter, the analog signal;
performing, by a receiver, analog-to-digital conversion on the analog signal to obtain a digital signal;
performing, by the receiver, equalization and phase retrieval on the digital signal to obtain an equalized and retrieved signal;
performing, by the receiver, post-filtering on the equalized and retrieved signal to convert the equalized and retrieved signal into a second filtered signal, wherein the post-filtering is finite impulse response filtering, and a bandwidth of the equalized and retrieved signal is greater than a bandwidth of the second filtered signal, wherein the post-filtering filters noise and introduces intersymbol interference (ISI) corresponding to ISI introduced by the transmitter; and
performing, by the receiver, sequence detection on the second filtered signal to obtain a sequence signal, wherein a relation for implementing the pre-filtering is D(k)=W0C(k)+W1C(k?1)+ . . . +WN-1C(k?N+1), wherein k is a time sequence number, D(k) is the first filtered signal, C(k) is the mapped signal, 0?i?N?1, N?1 is a maximum delay amount based on a time unit, Wi is an ith filter coefficient, and C(k?i) is a signal obtained by delaying C(k) by i time units.

US Pat. No. 10,193,712

MOBILE TERMINAL DEVICE AND METHOD FOR PROCESSING SIGNALS

Intel IP Corporation, Sa...

9. A receiver for a mobile radio communication device comprising:one or more lower receive branches, comprising:
a second equalizer configured to equalize a receive radio signal to generate a second equalized receive radio signal;
a second filter configured to filter a second re-synthesized transmit signal to generate a second subtraction signal; and
a second subtractor configured to subtract the second subtraction signal from the second equalized receive radio signal to generate a second subtracted equalized radio receive signal;
wherein the one or more lower receive branches is either a lowest branch or an intermediate branch between the highest branch and the lowest branch; and
a re-synthesizer configured to re-synthesize a transmit signal from the second subtracted equalized receive radio signal;
a highest receive branch comprising:
a first equalizer configured to equalize the receive radio signal to generate a first equalized receive radio signal;
a first filter configured to filter the re-synthesized transmit signal to generate a first subtraction signal; and
a first subtractor configured to subtract the first subtraction signal from the first equalized receive radio signal.

US Pat. No. 10,193,711

TIMING BASED ARBITRATION METHODS AND APPARATUSES FOR CALIBRATING IMPEDANCES OF A SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. A system comprising:a resistor; and
a plurality of chips,
wherein each chip of the plurality of chips comprises:
a terminal coupled to the resistor; and
a calibration circuit configured to determine whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chips, and
wherein the timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.

US Pat. No. 10,193,709

METHOD FOR PROCESSING REQUEST MESSAGES IN WIRELESS COMMUNICATION SYSTEM, AND DEVICE FOR SAME

LG ELECTRONICS INC., Seo...

1. A method for processing request messages between heterogeneous systems in a wireless communication system, the method being performed by a gateway device and comprising:receiving an advertisement message about a service of a first node from the first node belonging to a first system;
when the advertisement message includes an indicator indicating that the service is shared with a second system, generating resources which represent the shared service and a resource for access control for the generated resources;
receiving a request message for retrieving information on resources corresponding to at least one service shared with the second system, which have been generated in the gateway device from a second node of the second system;
transmitting the information on the resources corresponding to the at least one service to the second node when the second node has an access right for the retrieving information on the resources corresponding to the at least one service;
receiving, from the second node, a request message for generating a resource corresponding to a service to be called selected from the information on the resources corresponding to the at least one service, as a child resource of the generated resources;
checking an access right for generation of the child resource; and
generating the child resource when the second node has an access right for generation of the child resource.

US Pat. No. 10,193,708

MULTI-DOMAIN INTERCONNECT

NICIRA, INC., Palo Alto,...

1. A network system comprising:a first set of machines executing on a first set of host computers in a first physical domain and a second set of machines executing on a second set of host computers in a second physical domain, the first set of machines connected by a first logical forwarding element and the second set of machines connected by a second logical forwarding element, wherein the first and second logical forwarding elements are logically connected;
within each physical domain, a plurality of edge forwarding elements executing on the respective sets of host computers, each edge forwarding element for (i) coupling to the respective sets of machines and (ii) forwarding network data to and from the set of machines according to logical forwarding rules of the respective logical forwarding element of the set of machines;
within the first physical domain, an interior forwarding element executing on a first particular host computer, the interior forwarding element for coupling to a set of the edge forwarding elements of the first physical domain in order to receive network data for forwarding from the set of edge forwarding elements according to the logical forwarding rules of the first logical forwarding element when the edge forwarding elements do not recognize a destination location for the network data; and
within the first physical domain, a first interconnection forwarding element executing on a second particular host computer, the interconnection forwarding element for coupling to (i) the interior forwarding element, (ii) the set of edge forwarding elements, and (iii) a second interconnection forwarding element located in the second physical domain through an external network,
wherein when an edge forwarding element in the first physical domain receives network data with a destination address corresponding to a machine in the second domain connected to the second logical forwarding element, the edge forwarding element forwards said network data to the first interconnection forwarding element based on the logical connection between the first and second logical forwarding elements.

US Pat. No. 10,193,707

PACKET TRANSMISSION METHOD AND APPARATUS

Huawei Technologies Co., ...

1. A packet transmission method, wherein the method comprises:receiving, by a first Network Virtualization Edge (NVE) device, a first packet, wherein the first packet comprises a first source address and a first destination address, the first source address is an address of a first virtual machine, and the first destination address is an address of a second virtual machine, wherein the first virtual machine is virtualized by a first physical server and the second virtual machine is virtualized by a second physical server;
obtaining, by the first NVE device, an active-active access configuration information list, wherein the active-active access configuration information list comprises a first entry and a second entry, wherein the first entry comprises an identifier of a first active-active group, a virtual network instance, and an identifier of the first NVE device, and the second entry comprises an identifier of a second active-active group, the virtual network instance, and identifiers of at least two NVE devices that belong to the second active-active group;
obtaining, by the first NVE device, the virtual network instance according to the first entry and the identifier of the first NVE device;
searching, by the first NVE device, for at least one active-active group corresponding to the virtual network instance, wherein the at least one active-active group comprises the second active-active group; and selecting a second NVE device from the at least two NVE devices belonging to the second active-active group; and
encapsulating, by the first NVE device, the first packet by using an identifier of the second NVE device and the virtual network instance, and sending the encapsulated first packet to the second NVE device.

US Pat. No. 10,193,699

PROBABILISTIC CLASSIFIERS FOR CERTIFICATES

MICROSOFT TECHNOLOGY LICE...

9. A method comprising:receiving, by a computing device and from a trusted entity, one or more classifiers, the one or more classifiers are previously trained by the trusted entity and used to determine a probability that a received certificate by the computing device is being used improperly;
receiving, by the computing device and from an unverified entity, a request to communicate via a secure channel;
receiving a certificate from the unverified entity;
selecting a classifier of the received one or more classifiers based at least in part on one or more properties of the certificate;
using the classifier to:
determine that the certificate is valid;
determine a probability that the certificate is being used improperly;
stored the certificate based at least in part on a sampling percentage associated with the probability that the valid certificate is being used improperly; and
determining an action based at least in part on the probability that the certificate is being used improperly, the action relating to communication with the unverified entity via the secure channel;
performing the action;
send, to the trusted entity, the stored certificate to update classifier training data; and
receive, from the trusted entity, one or more updated classifiers, the one or more updated classifiers are trained by the trusted entity with the updated classifier training data and used to determine the probability that the received certificate by the computing device is being used improperly.

US Pat. No. 10,193,698

AVOIDING INTERDICTED CERTIFICATE CACHE POISONING FOR SECURE SOCKETS LAYER FORWARD PROXY

Juniper Networks, Inc., ...

1. A method, comprising:receiving, by a device, a message associated with establishing a secure session, the message including a first certificate chain associated with a server device, the first certificate chain including a plurality of certificates;
providing, by the device, information associated with each of the plurality of certificates included in the first certificate chain as an input to a cryptographic hash function;
receiving, by the device, a first certificate fingerprint as an output of the cryptographic hash function;
determining, by the device, that the device stores or has access to a certificate cache entry associated with the first certificate chain;
identifying, by the device and based on determining that the device stores or has access to the certificate cache entry, a second certificate fingerprint associated with the certificate cache entry, the second certificate fingerprint being based on a second certificate chain that has been validated;
determining, by the device, whether the first certificate fingerprint matches the second certificate fingerprint; and
identifying and providing, by the device, a stored interdicted certificate associated with the second certificate chain or the second certificate fingerprint based on determining that the first certificate fingerprint matches the second certificate fingerprint; orgenerating and providing, by the device, a generated interdicted certificate, associated with the first certificate chain, based on determining that the first certificate fingerprint does not match the second certificate fingerprint.

US Pat. No. 10,193,694

METHOD AND APPARATUS FOR SECURELY CONFIGURING PARAMETERS OF A SYSTEM-ON-A-CHIP (SOC)

Marvell International Ltd...

1. A method comprising:receiving, by a system-on-a-chip (SOC) from a host, a public key of a public/private key pair;
generating a first hash value of the public key;
authenticating the first hash value;
in response to authenticating the first hash value, transmitting, by the SOC, a first nonce to the host;
receiving a signed nonce from the host, the signed nonce being signed using a private key of the public/private key pair;
decrypting, using the received public key, the signed nonce to generate a second nonce;
based on the first nonce and the second nonce, authenticating the host;
in response to authenticating the host, receiving, from the host, a command to configure one or more parameters of the SOC; and
configuring the one or more parameters of the SOC.

US Pat. No. 10,193,693

INFORMATION PROCESSING DEVICE AND VERSION SWITCHING METHOD OF TRUSTED PLATFORM MODULE

Kabushiki Kaisha Toshiba,...

1. An information processing device comprising:a hardware processor;
a nonvolatile memory configured to store a system program;
a first trusted platform module; and
a second trusted platform module which is a version newer than the first trusted platform module,
wherein the system program causes the hardware processor to perform functions of:
determining whether a boot mode of the information processing device is set to a first mode or a second mode based on a setting value indicative of the boot mode, wherein the first mode is a mode for booting an operating system from a storage device initialized by a master boot record (MBR) and the second mode is a mode for booting an operating system from a storage device initialized by a GUID partition table (GPT); and
enabling the first or second trusted platform module based on a result of determination of the boot mode such that the first trusted platform module is enabled when the boot mode is the first mode, and the second trusted platform module is enabled when the boot mode is the second mode,
wherein the system program causes the hardware processor to further perform functions of:
determining whether an operating system which is previously booted is a first type operating system supporting the second trusted platform module based on information related to the operating system which is previously booted; and
enabling the first or second trusted platform module based on a result of determination of the type of the operating system which is previously booted such that the second trusted platform module is enabled when the operating system which is previously booted is the first type operating system, and the first trusted platform module is enabled when the operating system which is previously booted is not the first type operating system.

US Pat. No. 10,193,692

IDENTIFICATION TOKEN

NOKIA TECHNOLOGIES OY, E...

1. An apparatus comprising at least one processor and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following:obtain one or more tokens for processing incoming communication items to a first user in a predetermined manner based on information regarding type or origin of the incoming communication items, wherein a token is associated with one or more identifiers characterizing one or more communication items accompanying the token, the one or more identifiers comprising user identifiers of one or more second users that are being assigned the token,
encrypt the one or more tokens to create respective one or more encrypted tokens,
provide the one or more encrypted tokens to the one or more second users for subsequent use in communication to the first user to enable the first user to process the incoming communication items in accordance with the one or more identifiers,
verify an originator of the incoming communication items accompanied by the one or more encrypted tokens is the same as indicated by the one or more identifiers associated with the one or more communication items by comparing the one or more identifiers associated with the one or more encrypted tokens with the one or more identifiers associated with the one or more communication items, and
in response to determining the one or more identifiers of the one or more encrypted tokens do not match the one or more identifiers associated with the one or more communication items that are indicative of the originator of the incoming communication items, verify the originator of the incoming communication items by verifying that the incoming communication items accompanied by the one or more encrypted tokens further include a valid encryption key.

US Pat. No. 10,193,691

INFORMATION PROCESSING DEVICE, SERVER DEVICE, INFORMATION PROCESSING SYSTEM, MOVING OBJECT, AND INFORMATION PROCESSING METHOD

Kabushiki Kaisha Toshiba,...

1. An information processing system comprising:an information processing device having:
one or more processors configured to:
convert a first encryption key to be used for generation of a master key to be shared with a server device by using a second conversion rule to generate a third encryption key to be a new master key, the second conversion rule being different from a first conversion rule used for generation of a second encryption key that is the master key currently used for encrypted communication with the server device,
generate a ciphertext so that the server device derives the third encryption key on a basis of the second encryption key and the third encryption key, and
transmit the ciphertext to the server device, wherein the server device has:
one or more processors configured to:
receive, from the information processing device, the ciphertext for deriving the third encryption key being the new master key to be shared with the information processing device, the ciphertext being generated on a basis of the third encryption key and the second encryption key, the third encryption key being generated by converting the first encryption key used for generating the master key to be shared with the information processing device by using the second conversion rule different from the first conversion rule used for generation of the second encryption key, the second encryption key being the master key currently used for encrypted communication with the information processing device,
decrypt the ciphertext by using the second encryption key to obtain the third encryption key, and
update the third encryption key as the second encryption key to be shared with the information processing device.

US Pat. No. 10,193,689

STORING ACCESS INFORMATION IN A DISPERSED STORAGE NETWORK

International Business Ma...

1. A method comprises:encoding, in accordance with a share encoding function, an access information packet to produce a first encoded share and a second encoded share;
obtaining a set of personalized authenticating values regarding user access of a user device to the access information packet, wherein each of at least some of the personalized authenticating values of the set of personalized authenticating values is unique;
generating a first hidden password from the set of personalized authenticating values based on a first function;
generating a second hidden password from the set of personalized authenticating values based on a second function;
generating a first encryption key from the first hidden password and a first random number;
generating a second encryption key from the second hidden password and a second random number;
encrypting the first encoded share with the first encryption key to produce a first encrypted encoded share;
encrypting the second encoded share using the second encryption key to produce a second encrypted encoded share;
sending the first encrypted encoded share and the first random number to a first dispersed storage (DS) processing unit, wherein the first DS processing unit generates a first encoded data slice based on the first encrypted encoded share and the first random number; and
sending the second encrypted encoded share and the second random number to a second DS processing unit, wherein the second DS processing unit generates a second encoded data slice based on the second encrypted encoded share and the second random number.

US Pat. No. 10,193,688

FLEXIBLE ETHERNET ENCRYPTION SYSTEMS AND METHODS

Ciena Corporation, Hanov...

1. A method for Physical Coding Sublayer (PCS) encryption implemented by a first network element communicatively coupled to a second network element, the method comprising:utilizing an encryption messaging channel in Flexible Ethernet (FlexE) overhead of a FlexE signal to establish an authenticated session and to establish one or more encryption keys with a second network element;
encrypting a signal, based on the one or more encryption keys, wherein the encryption is applied to a 64b/66b bit stream associated with the FlexE signal at one or more of a FlexE client layer and a FlexE shim layer; and
transmitting the encrypted signal to the second network element.

US Pat. No. 10,193,685

RECEPTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

SOCIONEXT INC., Yokohama...

1. A reception circuit comprising:a determination circuit including:
a first number of first comparator circuits configured to perform determination of a level of a first data piece of a received signal based on a first clock signal among a plurality of clock signals having different phases and to output first determination signals, and
the first number of second comparator circuits configured to perform determination of a level of a second data piece of the received signal based on a second clock signal which is different from the first clock signal among the plurality of clock signals and to output second determination signals, the second data piece being subsequent to the first data piece,
the determination circuit being configured to perform determination of the level of the first data piece and the level of the second data piece by using the first number of the first comparator circuits and the first number of the second comparator circuits, respectively, when the received signal is a first signal which is a multi-valued signal and configured to perform determination of the level of the first data piece and the level of the second data piece by using a second number of the first comparator circuits and the second number of the second comparator circuits, respectively, the second number being two or more and smaller than the first number, when the received signal is a second signal, a number of possible values of the second signal being smaller than a number of possible values of the first signal;
a timing aligner circuit configured to align timing of the first determination signals and the second determination signals with one of the plurality of clock signals and to output first timing-aligned determination signals corresponding to the first determination signals and second timing-aligned determination signals corresponding to the second determination signals; and
a logic circuit configured to generate digital signals based on the first and second timing-aligned determination signals, the logic circuit being configured to operate as a decoder which decodes the first and second timing-aligned determination signals and generates the digital signals when the received signal is the first signal, and configured to operate as a selector which selects one of the first timing-aligned determination signals and one of the second timing-aligned determination signals and generates the digital signals when the received signal is the second signal.

US Pat. No. 10,193,684

METHOD AND APPARATUS FOR SIGNAL PROCESSING

Huawei Technologies Co., ...

1. An apparatus comprising:a bus;
a processor connected to the bus;
a receiver connected to the processor over the bus, wherein the receiver is configured to acquire a digital baseband reference signal, a self-interference reference signal, and a frequency-domain baseband signal; and
a non-transitory computer readable storage medium storing a program for execution by the processor, the program including instructions to:
obtain a basic reference signal and an image reference signal according to the digital baseband reference signal acquired by the receiver, wherein the image reference signal is an image signal of the basic reference signal;
estimate an estimated value of a first comprehensive response and an estimated value of a second comprehensive response according to the basic reference signal obtained by the processor, the image reference signal obtained by the processor, and the self-interference reference signal acquired by the receiver;
calculate a self-interference signal according to the estimated value of the first comprehensive response estimated by the processor, the estimated value of the second comprehensive response estimated by the processor, the basic reference signal obtained by the processor, and the image reference signal obtained by the processor, so that the apparatus is configured to perform self-interference cancellation on the frequency-domain baseband signal acquired by the receiver, wherein the basic reference signal comprises a basic frequency-domain reference signal, the image reference signal comprises an image frequency-domain reference signal, the first comprehensive response comprises a first comprehensive frequency-domain response, the second comprehensive response comprises a second comprehensive frequency-domain response, and the self-interference reference signal comprises a frequency-domain self-interference reference signal; and
estimate an estimated value ?1(f) of H1(f) and an estimated value ?2(f) of H2(f) according to a first formula:
Z(f)=H1(f)S(f)+H2(f)S*(?f)wherein S(f) is the basic frequency-domain reference signal obtained by the processor, S*(?f) is the image frequency-domain reference signal obtained by the processor, Z(f) is the frequency-domain self-interference reference signal acquired by the receiver, H1(f) is a first comprehensive frequency-domain response, ?1(f) is the estimated value of the first comprehensive frequency-domain response, H1(f), H2(f) is the second comprehensive frequency-domain response, and ?2(f) is the estimated value of the second comprehensive frequency-domain response H2(f).

US Pat. No. 10,193,683

METHODS AND DEVICES FOR SELF-INTERFERENCE CANCELATION

INTEL CORPORATION, Santa...

3. A communication circuit arrangement comprising:a kernel generation circuit configured to process an input signal for an amplifier to obtain a plurality of kernel signals that approximate non-linear components of a response of the amplifier;
a signal path circuit configured to separately apply a kernel dimension filter and a delay tap dimension filter to the plurality of kernel signals to obtain an estimated interference signal, where the kernel dimension filter approximates the response of the amplifier over the plurality of kernel signals;
a cancelation circuit configured to subtract the estimated interference signal from a received signal to obtain a clean signal; and
a filter update circuit configured to alternate between updating the kernel dimension filter and the delay tap dimension filter using the clean signal by:
selecting between the kernel dimension filter and the delay tap dimension filter to identify a current filter to update and a fixed filter to hold constant, and
updating the current filter based on the input signal and the clean signal.

US Pat. No. 10,193,680

APPARATUS AND METHOD FOR ESTIMATING CHANNEL

Apple Inc., Cupertino, C...

1. A method for transmitting a reference signal, comprising:configuring first initialization value generation information associated with a first value of scrambling code identity (SCID) (nSCID) information and second initialization value generation information associated with a second value of the SCID (nSCID) information, wherein the first initialization value generation information and the second initialization value generation information comprise respective cell identity (cell ID) information, wherein the respective cell ID information is selected based on the SCID (nSCID) information;
transmitting, to a user equipment (UE), the first initialization value generation information and the second initialization value generation information through a higher layer signaling;
transmitting, to the UE, the SCID (nSCID) information as selection indication information;
generating a reference signal for the UE based on one of a first initialization value and a second initialization value selected by the SCID (nSCID) information, the first initialization value being determined based on the first initialization value generation information and the second initialization value being determined based on the second initialization value generation information; and
transmitting the generated reference signal to the UE.

US Pat. No. 10,193,679

REFERENCE SIGNAL RECEPTION AND CQI COMPUTATION METHOD AND WIRELESS COMMUNICATION APPARATUS

Sun Patent Trust, New Yo...

1. A communication apparatus comprising: a receiver, which, in operation, receives a first reference signal that is mapped in a subframe and transmitted to the communication apparatus compliant with a first communication system, and receives a second reference signal that is mapped in all subframes and transmitted to the communication apparatus and another communication apparatus compliant with a second communication system; and circuitry, which, in operation, computes a channel quality indicator (CQI) based on the received first reference signal and the received second reference signal, wherein the first reference signal is mapped with an interval, which is the same as (i) an interval of retransmissions in a Hybrid automatic repeat request (HARQ) process or a number of HARQ processes, (ii) an integer multiple of an interval of retransmissions in a HARQ process or an integer multiple of a number of HARQ processes, or (iii) 1/N of an interval of retransmissions in a HARQ process or 1/N of a number of HARQ processes, where N is a positive integer.

US Pat. No. 10,193,677

METHOD FOR RECEIVING DOWNLINK SIGNAL BY MEANS OF UNLICENSED BAND IN WIRELESS COMMUNICATION SYSTEM AND DEVICE FOR SAME

LG ELECTRONICS INC., Seo...

1. A method of receiving a downlink signal by a user equipment (UE) from an eNB in a wireless communication system, the method comprising:receiving information on a second reference signal being QCL (Quasi Co-Location) with a first reference signal for demodulating the downlink signal from the eNB;
determining quasi-continuity of the second reference signal according to average density of the second reference signal existing within a window for determining quasi-continuity; and
receiving the downlink signal from the eNB based on whether or not the second reference signal is quasi-continuous.

US Pat. No. 10,193,675

METHOD AND DEVICE FOR NOTIFYING REFERENCE SIGNAL CONFIGURATION INFORMATION

HUAWEI TECHNOLOGIES CO., ...

1. A method, comprising:determining, by a base station, channel state information-reference signal (CSI-RS) configuration codes; and
sending, by the base station, the CSI-RS configuration codes to a terminal device; wherein the CSI-RS configuration codes comprise a first code, a second code, and a third code, the first code indicates a quantity of antenna ports of the base station for transmitting a channel state information-reference signal (CSI-RS), and a CSI-RS pattern, the second code indicates a CSI-RS period and a offset corresponding to the CSI-RS period, and the third code indicates a data muting resource.

US Pat. No. 10,193,672

MOBILE COMMUNICATION SYSTEM

Mitsubishi Electric Corpo...

2. A base station that performs radio communication with user equipment in response to a control by a radio network controller, whereinsaid radio network controller indicates a low-frequency resource that is a radio resource for transmitting to said user equipment a reference signal less frequently than normal to said base station, the reference signal being transmitted to measure power,
the base station designates, in addition to the low-frequency resource indicated by said radio network controller, a low-frequency resource that is a radio resource for transmitting said reference signal to said user equipment less frequently than normal, and
said base station transmits said reference signal to said user equipment less frequently than normal in the low-frequency resource indicated by said radio network controller and the low-frequency resource additionally designated by said base station itself.

US Pat. No. 10,193,671

SYSTEM AND METHOD FOR TRANSMISSION SYMBOL ARRANGEMENT FOR REDUCING MUTUAL INTERFERENCE

Huawei Technologies Co., ...

1. A method for operating a transmitting device, the method comprising:transmitting, by the transmitting device, a pilot signal associated with the transmitting device in a plurality of tones of a first transmission symbol in accordance with a spreading pattern in frequency domain associated with the transmitting device, without transmitting the pilot signal in a remainder of the tones in the first transmission symbol; and
transmitting, by the transmitting device, data to a receiving device in the plurality of tones of a second transmission symbol in accordance with the spreading pattern in the frequency domain, without transmitting the data or the pilot signal in a remainder of the tones in the second transmission symbol.

US Pat. No. 10,193,670

METHODS AND SYSTEMS FOR COMMUNICATION

1. A communication network, comprising:a central node configured to allocate bandwidth at which data is transferred to and from initial network nodes over a communication channel according to an initial frequency band plan, the initial frequency band plan comprising:
a number of dedicated frequencies associated with the respective initial network nodes; and
a common frequency band on which the central node and initial network nodes communicate, wherein communication over the common frequency band includes a number of time windows that are respectively and uniquely associated with the number of initial network nodes; andwherein the central node is further configured to reallocate the bandwidth according to a modified frequency band plan to account for a subsequent network node requesting access to the communication network,wherein frequencies of the common frequency band are interspersed with the dedicated frequencies, orwherein the frequencies of the common frequency band are all above the dedicated frequencies.

US Pat. No. 10,193,669

NIB COMP TRANSMISSION METHOD AND DEVICE IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for performing a Coordinated Multi-Point (CoMP) transmission at a first eNodeB in wireless communication system, the method comprising:receiving, by the first eNodeB from a second eNodeB, CoMP information including a CoMP hypothesis set and a benefit metric associated with the CoMP hypothesis set; and
performing, by the first eNodeB, the CoMP transmission based on the CoMP information,
wherein a CoMP hypothesis included in the CoMP hypothesis set is hypothetical physical resource block (PRB)-specific resource allocation information,
wherein the benefit metric quantifies a benefit assuming that the CoMP hypothesis is applied,
wherein the benefit metric has a value that is one of a value within a specific range or is a predefined value outside of the specific range, and
wherein, when the benefit metric has the predefined value, a benefit of the CoMP hypothesis is unknown.

US Pat. No. 10,193,667

METHOD FOR PERFORMING COMP OPERATION IN WIRELESS COMMUNICATION SYSTEM AND AN APPARATUS FOR SUPPORTING THE SAME

LG Electronics Inc., Seo...

1. A method of performing an inter-eNB Coordinated Multi-Point (CoMP) operation in a wireless communication system, the method comprising:receiving, by a first eNB, a first LOAD INFORMATION message from a second eNB requesting that the first eNB start the CoMP operation;
sending, by the first eNB, a second LOAD INFORMATION message to the second eNB requesting a Benefit Metric Information Element (IE);
receiving, by the first eNB, a third LOAD INFORMATION message from the second eNB, including the Benefit Metric IE;
coordinating, by the first eNB, resources for the CoMP operation; and
sending, by the first eNB, a fourth LOAD INFORMATION message to the second eNB, including results of the resource coordination,
wherein the first LOAD INFORMATION message includes an Invoke Indication IE, and the Invoke Indication IE includes CoMP Initiation IE for requesting the start of the CoMP operation.

US Pat. No. 10,193,665

REFERENCE SIGNAL FOR 3D MIMO IN WIRELESS COMMUNICATION SYSTEMS

TEXAS INSTRUMENTS INCORPO...

1. A method for providing channel state information (CSI) feedback between a base station and a user device, comprising:obtaining, at the user device, a first measurement using a first channel state information reference signal (CSI-RS) sub-resource;
obtaining, at the user device, a second measurement using a second CSI-RS sub-resource;
deriving a single CSI-process based on the first and the second measurements;
reporting said CSI-process to the base station; and
receiving a message from the base station configuring the first and second CSI-RS sub-resources corresponding to said single CSI-process to be reported by the user device.

US Pat. No. 10,193,664

ENHANCED RETRY COUNT FOR UPLINK MULTI-USER TRANSMISSION

Intel IP Corporation, Sa...

1. A device, the device comprising memory and processing circuitry configured to:identify a trigger frame received from a first device on a wireless communication channel;
determine a quality of service counter associated with an access category;
cause to send a frame to the first device based at least in part on the trigger frame;
determine an error condition associated with the frame; and
refrain from incrementing the quality of service counter based on the error condition.

US Pat. No. 10,193,661

COMMUNICATION DEVICE, NON-TRANSITORY COMPUTER READABLE MEDIUM AND WIRELESS COMMUNICATION SYSTEM

KABUSHIKI KAISHA TOSHIBA,...

1. A communication device comprising:processing circuitry configured to calculate a function having as an argument each of identifiers of other first communication devices and set bits corresponding to values of the function to first values to generate first data; and
a communicator configured to transmit a first message including the first data to the other first communication devices,
wherein
the communicator waits to receive second messages from the other first communication devices until a predetermined timing, and the processing circuitry specifies second messages which have been received until the predetermined timing and generates the first data by using the function and identifiers of other first communication devices from which the specified second messages have been received, wherein the first data is acknowledgment information indicating the specified second message have successfully been received,
or
the communicator waits to receive second messages from the other first communication devices until a predetermined timing and the processing circuitry specifies second messages which have not been received until the predetermined timing, and generates the first data by using the function and identifiers of communication devices from which the second messages have not been received, wherein the first data is non-acknowledgment information indicating the specified second messages have not successfully been received.

US Pat. No. 10,193,658

APPARATUS AND A METHOD FOR A REGENERATIVE NETWORK NODE BETWEEN A FIRST AND A SECOND LINK PORTION

Alcatel Lucent, Boulogne...

1. An apparatus for a regenerative network node between a first and a second link portion, comprising:an input configured to receive, from the first link portion, a signal impaired by the first link portion, the signal including a data packet with a Forward Error Correction (FEC) encoded payload portion and a header portion;
a signal regeneration unit configured to mitigate signal impairments of the first link portion to provide a regenerated FEC encoded payload portion;
a processing unit configured to
extract destination information given in the data packet's header,
if the extracted destination information indicates that the data packet's destination is the regenerative network node,
forward the data packet's regenerated FEC encoded payload portion to a decoding unit of the regenerative network node,
else,
forward the data packet's regenerated FEC encoded payload portion to the second link portion; and
a reduction unit configured to reduce a number of bits representing the data packet's regenerated FEC encoded payload portion, if the data packet's regenerated FEC encoded payload portion is forwarded to the second link portion.

US Pat. No. 10,193,656

SYSTEMS AND METHODS FOR ADAPTIVE DOWNLINK CONTROL INFORMATION SET FOR WIRELESS TRANSMISSIONS

HUAWEI TECHNOLOGIES CO., ...

1. A method for performing blind detection, the method comprising:identifying, by a user equipment (UE), a search space in a control channel, the control channel carrying signaling using at least some control formats in a set of control formats defined for the control channel;
determining, by the UE, a subset of control formats to search for in the search space based at least on a sub-carrier spacing configuration assigned to the UE, at least two sub-carrier spacing configurations being associated with different subsets of control formats, and the subset of control formats excluding one or more control formats in the set of control formats defined for the control channel;
searching, by the UE, for the subset of control formats in the search space without searching for the one or more control formats excluded from the subset of control formats; and
transmitting or receiving, by the UE, a data signal in accordance with control information detected in the search space.

US Pat. No. 10,193,655

METHOD AND APPARATUS FOR SCHEDULING MULTIMEDIA STREAMS OVER A WIRELESS BROADCAST CHANNEL

FUTUREWEI TECHNOLOGIES, I...

1. A method of broadcasting data, the method comprising:receiving a plurality of broadcast data streams, a first broadcast data stream including data processed with a first modulation and coding scheme, and a second broadcast data stream including the same data processed with a second modulation and coding scheme;
assigning the broadcast data streams into a plurality of frames, each frame being assigned to only one broadcast data stream, each frame carrying data from only its assigned broadcast data stream, index information carried by each frame of other frames assigned to the broadcast data streams being limited, per broadcast stream, to a sole instance of index information of only a single next frame carrying data from that same broadcast data stream, and the index information varying from frame-to-frame; and
causing the frames to be broadcast wirelessly.

US Pat. No. 10,193,653

POLARIZATION MULTIPLEXING OPTICAL TRANSMISSION CIRCUIT AND POLARIZATION MULTIPLEXING OPTICAL TRANSMISSION AND RECEPTION CIRCUIT

Nippon Telegraph and Tele...

1. A polarization multiplexing optical transmission circuit, comprising:a first optical power splitter for branching an optical power of continuous light outputted from a light source;
a first polarization optical modulation circuit at a side of a path having a higher loss connected to a first output of the first optical power splitter;
a second optical power splitter connected to a second output of the first optical power splitter; and
a second polarization optical modulation circuit at a side of a path having a lower loss connected to one output of the second optical power splitter.

US Pat. No. 10,193,652

METHOD AND MASTER DEVICE FOR CONTROLLING ACCESS TO OUT-OF-BAND COMMUNICATION CHANNEL IN OPTICAL COMMUNICATIONS NETWORK

MITSUBISHI ELECTRIC CORPO...

1. A method for controlling access to an out-of-band communication channel in an optical communications network comprising a master device and slave devices connected to the master device via optical fiber, the optical communications network being adapted to enable in-band communications, the out-of-band communication channel being intended to enable transmissions of signalling signals with respect to the in-band communications, collisions occurring in the out-of-band communication channel when plural slave devices access the out-of-band communication channel by using respective carrier wavelengths that match each other, characterized in that the master device performs:processing signalling signals transmitted by said slave devices without access restriction to the out-of-band communication channel;
and upon detecting a collision between signalling signals transmitted by slave devices concurrently accessing the out-of-band communication channel:
initiating a temporary time-slotted access to the out-of-band communication channel, so as to restrict access to the out-of-band communication channel, using a predetermined rule of time slot distribution among slave devices likely to concurrently access the out-of-band communication channel using carrier wavelengths substantially identical as those having involved the detected collision.

US Pat. No. 10,193,651

OPTICAL NETWORK CONTROLLER AND OPTICAL NETWORK CONTROL METHOD

NEC CORPORATION, Tokyo (...

1. An optical network controller, comprising:a computer-readable memory storing program instructions;
at least one processor configured to execute the program instructions stored in the memory to implement:
an optical wavelength region setting unit configured to set a wavelength region in an optical transmission line between a plurality of optical nodes composing an optical network using wavelength division multiplexing system dividing the wavelength region into consecutive regions of a first wavelength region and a second wavelength region;
an optical path setting unit configured to set a first optical path in the first wavelength region and a second optical path in the second wavelength region, the second optical path differing from the first optical path in a route; and
a controller configured to instruct the plurality of optical nodes on a central wavelength and a usable band of signal light for the optical node to transmit based on a setting by the optical path setting unit, wherein the controller instructs the plurality of optical nodes to change the central wavelength and the usable band so as to rearrange the second optical path in the second wavelength region, keeping a placement of the first optical path in the first wavelength region constant.

US Pat. No. 10,193,648

MITIGATING PACKET INTERFERENCE

Facebook, Inc., Menlo Pa...

1. A method, comprising;receiving, by a sector, data to be transmitted over a specific wireless link of a wireless network;
configuring a packet for transmission over the specific wireless link, wherein the packet includes a preamble, and the data, comprising:
identifying a reference sequence based on the specific wireless link, comprising:
selecting a subset of codes from available codes;
grouping links of the wireless network into a plurality of groups based on connectivity of the links between sectors of nodes of the wireless network;
assigning at least one code of the subset of codes to the first group and at least one other code of the subset of codes to the second group;
characterizing interference between at least one link of a first group of the plurality of groups and at least one link of a second group of the plurality of groups, wherein at least one of the first group or the second group includes the specific wireless link; and
wherein assigning at least one code of the subset of codes to the first group and at least one other code of the subset of codes to the second group is based on the characterizing of the interference;
configuring the sector with the reference sequence, wherein the reference sequence comprises one of the subset of codes of the first group or one of the subset of codes of the second group based on which of the first group or the second group includes the specific wireless link;
inserting the reference sequence into at least a portion of the preamble;
transmitting, by the sector, the configured packet over the specific wireless link.

US Pat. No. 10,193,647

GENERATING INTERFERENCE PATTERN FOR CONTROLLING INTER-CELL INTERFERENCE AND METHOD FOR SIGNALING THEREFOR

LG ELECTRONICS INC., Seo...

1. A method of transmitting, by a base station supported by a reference cell, a demodulation pilot signal for controlling inter-cell interference, the method comprising:determining a pattern length of a first interference pattern and a cyclic shift offset,
wherein the first interference pattern is included in an interference pattern set and is allocated to a first time resource of a predetermined reference resource, and
wherein the cyclic shift offset is used for distinguishing each interference pattern in the interference pattern set;
generating a cell-specific sequence related with a demodulation pilot signal in which a cyclic shift offset for the first interference pattern is applied,
wherein a pattern of the demodulation pilot signal is determined based on the pattern length of the first interference pattern and a number of frequency domain resources that are used for the demodulation pilot signal;
transmitting the demodulation pilot signal based on the cell-specific sequence through a resource allocated according to the pattern of the demodulation pilot signal,
wherein the demodulation pilot signal is used for signaling the first interference pattern.

US Pat. No. 10,193,646

BANDWIDTH EXTENSION FOR TRUE SINGLE-PHASE CLOCKED MULTIPLEXER

BAE Systems Information a...

1. A true single-phase clocked (TSPC) multiplexer (MUX) for outputting one of a plurality of input signals in synchronization with a first clock signal and as selected by at least one select signal, the MUX comprising:a plurality of first transistors electrically connected to a first power source for supplying a first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level;
a plurality of second transistors electrically connected to a second power source for supplying the second voltage level and configured to turn on in response to a gate voltage of the first voltage level;
a first node between ones of the first transistors and having a voltage level configured to take on each of the first voltage level, the second voltage level, and a first floated voltage level, the first floated voltage level being between and different from the first and second voltage levels, the first node voltage level depending at any given time on the input signals, the select signal, and the first clock signal;
a second node between ones of the second transistors and having a voltage level configured to take on each of the first voltage level, the second voltage level, and a second floated voltage level, the second floated voltage level being between and different from the first and second voltage levels, the second node voltage level depending at any given time on the input signals, the select signal, and the first clock signal;
a third node electrically connected to the first node by one of the first transistors and to the second node by one of the second transistors; and
a pre-charge transistor to electrically connect the third node to the first power source.

US Pat. No. 10,193,641

METHOD AND APPARATUS FOR ESTIMATING AN EXPECTED RECEPTION QUALITY

Volkswagen AG, Wolfsburg...

6. A device for estimating a quality of reception to be expected in a reception time interval for a Car to X communication, the device comprising:a receiving device for acquiring data packets and a memory, wherein at least one empirically determined variable is deposited in the memory for reception patterns of data packets in a first time interval,
wherein the at least one empirically determined variable specifies or provides data to determine a probability that a data packet or a number (n) of data packets will be received successfully in a subsequent second time interval, wherein the device is designed so that, for the first time interval before the reception time interval, the reception pattern is determined and the associated probability for the reception time interval is read out of the memory,
wherein a warning message is generated based on the determined probability and a functionality of a driver assistance function is changed based on the determined probability.

US Pat. No. 10,193,640

OFFSET-COMPENSATED LOSS OF SIGNAL DETECTION METHODS AND SYSTEMS

INPHI CORPORATION, Santa...

1. A loss-of-signal detection device comprising:a first terminal configured to receive a first input signal, the first input signal being characterized by a first frequency;
a first hysteresis voltage source configured to apply a first predetermined hysteresis voltage to the first input signal to provide a first adjusted signal;
a bias voltage source being configured to provide a bias voltage;
a first transistor comprising a first gate and a first source, the first adjusted signal being coupled to the first gate;
a second transistor comprising a second gate, a second source, and a first drain, the second gate being coupled to the bias voltage, the second source being coupled to the first source; and
an output module comprising a switch network and a latch, the switch network being configured to generate an intermediate signal using a strength indicator signal received from the first drain of the second transistor and an offset associated at least with the first transistor, the latch being configured to generate a loss-of-signal indicator based on the intermediate signal at a second frequency, the second frequency being lower than the first frequency;
wherein the switch network operates in a first phase and a second phase, the switching network being configured to determine a common offset voltage during the first phase, the switching network being configure to generate the intermediate signal during the second phase, the intermediate signal is based on a difference between the strength indicator signal and the common offset voltage.

US Pat. No. 10,193,639

OVER THE AIR MEASUREMENT MODULE

1. An over the air measurement module, comprising:an antenna, adapted to receive a first measuring signal from a device under test or adapted to transmit a second measuring signal to the device under test,
a mixer, directly connected to said antenna, adapted to reduce or increase a frequency of the received first measuring signal, resulting in a frequency reduced or increased first measuring signal, or adapted to increase or reduce a frequency of a frequency reduced or increased second measuring signal, resulting in the second measuring signal, and
a first connector, connected to said mixer, adapted to input a local oscillator signal into the mixer for frequency conversion,
wherein at least 50% of the surfaces of the over the air measurement module facing the main radiation direction of the antenna are angled away from a normal of the main radiation direction of the antenna by at least 30°,
wherein the antenna is a planar antenna, and
wherein a main radiation direction of the antenna is in the plane of the planar antenna.

US Pat. No. 10,193,637

METHOD AND SYSTEM OF NETWORK SWITCH OPTIMIZATION

The United States of Amer...

1. A method for determining a network configuration for delivery of entangled photons to a plurality of users such that any user of the plurality of users may share one of a pair of entangled photons with any other user; the network comprising a plurality of inputs; a plurality of switches, and a plurality of outputs operatively connected to the plurality of inputs by a plurality of optical fibers;the plurality of switches, each having a first switch input and a second switch input and a first switch output and a second switch output and being switchable between two states, a first state in which the first switch input is connected to the first switch output and the second switch input is connected to the second switch output and a second state in which the first switch input is connected to the second switch output and the second switch input is connected to the first switch output; the method comprising:
determining the minimum number of switches necessary to deliver entangled photon pairs from a predetermined number of sources to a predetermined number of users,
minimizing the loss experienced by an entangled photon passing through the plurality of switches by minimizing the number of switches that any one photon passes through by selecting only nondominated switch configurations;
determining the minimum number of equivalent network switch configurations and eliminating all but one of the equivalent network switch configurations; and
selecting an optimum network configuration by which the plurality of inputs and the plurality of outputs are operatively interconnected so as to enable the delivery of one photon of the pair of entangled photons to each of the plurality of output ports using a minimum number of switches in any route connecting each of the plurality of outputs to the plurality of inputs.

US Pat. No. 10,193,634

OPTICAL DRIVER CIRCUITS

Hewlett Packard Enterpris...

18. An optical driver circuit, comprising:a level controller to pre-emphasize rising and falling edges of a modulation signal output to an optical transmitter;
an equalization controller to remove the pre-emphasis from the modulation signal output using an inverted delayed modulation signal;
an edge rate controller to control a rise and fall time of the modulation signal output;
wherein the level controller, the equalization controller, and the edge rate controller each include a plurality of negative-AND (NAND) gate p-channel metal-oxide-semiconductor field-effect transistor (PMOS) circuits and a plurality of negative-OR (NOR) gate n-channel metal-oxide-semiconductor field-effect transistor (NMOS) circuits; and
a pre-driver circuit to:
generate a main modulation signal and an inverted main modulation signal;
provide the main modulation signal as input to the plurality of NAND gate PMOS circuits and the plurality of NOR gate NMOS circuits included in the edge rate controller; and
provide the inverted main modulation signal as input to the plurality of NAND gate PMOS circuits and the plurality of NOR gate NMOS circuits included in the level controller.

US Pat. No. 10,193,632

OPTICAL DEVICES INCLUDING A HIGH CONTRAST GRATING LENS

Hewlett Packard Enterpris...

6. An optical communication device, comprising:a transparent substrate;
a vertical-cavity surface emitting laser VCSEL integrated at a first side of the transparent substrate to emit a modulated laser light into the transparent substrate, the laser light being modulated for transmitting information;
an optical waveguide to implement optical communications to a remote device via transmission of the modulated laser light; and
a HCG lens integrated at a second side of the transparent substrate to:
receive the modulated laser light from the transparent substrate, and
transmit and refract the modulated laser light into an optical input of the optical waveguide;
wherein the HCG lens includes a HCG layer and a separation layer interposed between the HCG layer and the substrate to enhance resonant optical effects that the HCG layer causes on the laser light impinging thereon.

US Pat. No. 10,193,630

STATION-SIDE DEVICE AND OPTICAL TRANSMISSION SYSTEM

NIPPON TELEGRAPH AND TELE...

1. A station-side device used in an optical transmission system that includes N (N is an integer of not less than 2) optical splitters and the station-side device that is configured to perform transfer processing of frames between a plurality of subscriber-side devices connected to the station-side device via the optical splitters and a host device, comprising:N optical transceivers connected to the optical splitters in a one-to-one correspondence and configured to perform opto-electric conversion of upstream frames from the subscriber-side devices connected to the corresponding optical splitters to the host device and perform electro-optic conversion of downstream frames from the host device to the subscriber-side devices;
a PON control circuit configured to exchange the upstream frames and the downstream frames with the host device and time-divisionally allocate a communication band for upstream frame transmission to the subscriber-side devices such that the upstream frames are transmitted from the respective subscriber-side devices at different times;
a selection and distribution circuit configured to select the optical transceivers corresponding to the upstream frame that time-divisionally arrives such that the upstream frames opto-electrically converted by the optical transceivers are transferred to the PON control circuit, and distribute the downstream frames from the PON control circuit to the optical transceivers; and
a power supply control circuit configured to stop power supply to at least one of the optical transceivers that are not used to transfer the frame of the optical transceivers and the selection and distribution circuit which is not used to transfer the frames,
wherein the power supply control circuit includes N first power switches provided in correspondence with the respective optical transceivers and configured to control power supply to the optical transceivers based on operation statuses of the optical transceivers, and N second power switches provided in correspondence with the respective optical transceivers and configured to control power supply to circuit portions corresponding to the optical transceivers in the selection and distribution circuit based on the operation statuses of the optical transceivers and/or upstream band allocation statuses representing arrival time periods of the upstream frames that arrive time-divisionally.

US Pat. No. 10,193,629

OPTICAL-SIGNAL PROCESSING APPARATUS, OPTICAL TRANSMISSION METHOD, RECEIVER, AND OPTICAL NETWORK SYSTEM

FUJITSU LIMITED, Kawasak...

1. An optical network system comprising:a nonlinear optical medium through which a first optical carrier having a first wavelength and a second optical carrier having a second wavelength propagate in opposite directions, the nonlinear optical medium configured to connect a first terminal and a second terminal and the first optical carrier propagating from the first terminal to the second terminal and the second optical carrier propagating from the second terminal to the first terminal;
the first terminal including:
an optical modulator which generates a modulated light based on a combined signal generated by combining a baseband signal with an RF (radio frequency) signal, multiplexes the modulated light on the first optical carrier and transmits the modulated light to the second terminal via the nonlinear optical medium, the RF signal being generated by modulating a carrier signal with an information;
the second terminal splits the modulated light from the first optical carrier and receives the RF signal or the baseband signal, multiplexes modulated data signals on the second optical carrier and transmits the modulated data signals to the first terminal via the nonlinear optical medium,
wherein the first terminal splits the modulated data signals from the second optical carrier and receives the modulated data signals.

US Pat. No. 10,193,627

DETECTION OF VISIBLE LIGHT COMMUNICATION SOURCES OVER A HIGH DYNAMIC RANGE

FORD GLOBAL TECHNOLOGIES,...

1. A visible light communication (VLC) method, comprising:capturing frames of a scene with a camera;
assembling an enhanced dynamic range image sequence from the frames;
detecting at least one VLC source in the enhanced sequence occupying a respective subwindow;
optimizing an exposure at the subwindow according to a brightness of the respective VLC source;
capturing a plurality of subwindow images using the optimized exposure; and
decoding VLC data visible in the subwindow images.

US Pat. No. 10,193,626

AUTO-DISCOVERY OF NEIGHBOR RELATIONSHIPS AND LIGHTING INSTALLATION SELF-MAPPING VIA VISUAL LIGHT COMMUNICATION

ABL IP HOLDING LLC, Cony...

4. A method comprising steps of:triggering a general illumination lighting device to modulate a visual light output from a general illumination source of the lighting device to repeat transmission of a packet of predetermined data a number of times,
the predetermined data of the repeatedly transmitted packet including an identification of the lighting device;
receiving, from another general illumination lighting device, a report of number of visual light receptions of the transmitted packet by the other general illumination lighting device; and
identifying the other general illumination lighting device as a neighbor of the general illumination lighting device based on detection of a predetermined relationship between the number of times of transmission and the number of visual receptions of the packet of predetermined data.

US Pat. No. 10,193,624

VISIBLE LIGHT COMMUNICATION DEVICE, METHOD AND SYSTEM

INDUSTRIAL TECHNOLOGY RES...

1. A visible light communication (VLC) device for performing VLC by a visible light source, the VLC device comprising:a processing circuit; and
a current driving circuit, coupled to the processing circuit and the visible light source, wherein the current driving circuit being controlled by the processing circuit to drive the visible light source,
wherein
in searching a central frequency of the visible light source, the processing circuit is configured to:
send a plurality of central frequency training packets to the current driving circuit, the central frequency training packets including a plurality of candidate central frequencies; and
based on a first decoding result on the central frequency training packets, select one among the candidate central frequencies to set as the central frequency of the visible light source; and
in searching a bandwidth of the visible light source, the processing circuit is configured to:
send a plurality of bandwidth training packets to the current driving circuit, the bandwidth training packets including the central frequency of the visible light source and a plurality of candidate bandwidth; and
based on a second decoding result on the bandwidth training packets, select one among the candidate bandwidth to set as the bandwidth of the visible light source.

US Pat. No. 10,193,622

ARTIFICIAL LIGHT SOURCE BASED MESSAGING PLATFORM

COOPER TECHNOLOGIES COMPA...

1. A non-transitory computer-readable medium comprising a plurality of instructions, which, when executed by a processor, cause the processor to perform operations comprising:detecting, using a light sensor coupled to the processor, a modulated light from an artificial light source in an area,
wherein the modulated light is representative of data associated with the artificial light source, and
wherein the artificial light source is associated with a first group of artificial light sources in the area, each artificial light source of the first group of artificial light sources being associated with each other;
decoding the modulated light to retrieve the data associated with the artificial light source; and
visually presenting, via a display coupled to the processor, a first visual identifier overlaid over the first group of artificial light sources in the area and a second visual identifier overlaid over a second group of artificial light sources in the area to visually distinguish the first group of artificial light sources from the second group of artificial light sources in the area.

US Pat. No. 10,193,621

LOCATION MEASUREMENT APPARATUS, LIGHT MODULATION CONVERTER, AND LIGHT VARIATION LOCATION MEASUREMENT METHOD

FUJITSU LIMITED, Kawasak...

1. A location-measurement apparatus that is disposed on one terminal of an optical transmission line, the location-measurement apparatus comprising:a light source that causes continuous oscillation light to enter one terminal of the optical transmission line, the continuous oscillation light being to propagate a light variation of a first physical amount generated on the optical transmission line to another terminal of the optical transmission line;
a photodetector that detects, on the one terminal of the optical transmission line, light turned back from a light modulation converter provided on the another terminal of the optical transmission line, wherein the light modulation converter obtains the turned-back light by converting the light variation of the first physical amount into a light variation of a second physical amount; and
a processor that calculates a light-variation location generated on the optical transmission line by comparing time variations in the light variation of the first physical amount and the light variation of the second physical amount in the light detected by the photodetector.

US Pat. No. 10,193,620

NONLINEAR SPATIALLY RESOLVED INTERFEROMETER FOR CHARACTERIZING OPTICAL PROPERTIES OF DEPLOYED TELECOMMUNICATION CABLES

Ciena Corporation, Hanov...

1. A method for measuring physical properties of optical signals as a function of wavelength and as a function of location in an optical link, the method comprising:generating a first modulated optical carrier at a first wavelength, the first modulated optical carrier carrying pump pulses;
generating a second modulated optical carrier at a second wavelength that differs from the first wavelength, the second modulated optical carrier carrying pilot pulses and carrying probe pulses;
transmitting the first modulated optical carrier and the second modulated optical carrier on an optical fiber over the optical link, the optical link comprising multiple spans connected by one or more optical amplifiers, such that a probe pulse of the probe pulses is spatially overlapped in the optical fiber with a pump pulse of the pump pulses within at least one interaction region in the optical link;
performing a measurement on the probe pulse beyond an end of the optical fiber to measure optical properties of the probe pulse relative to a coherent reference, wherein the coherent reference includes a component of at least one of the pilot pulses, the component being coherent to the probe pulse; and
calculating physical properties of the pump pulse from the measurement on the probe pulse,
wherein the pilot pulses are arranged to be not spatially overlapped in the optical fiber with any of the pump pulses, or the pilot pulses are arranged so that any interaction between the pilot pulses and any of the pump pulses introduces a negligible error or a deterministic-yet-correctable error in measurement of the optical properties.

US Pat. No. 10,193,619

MODE DIVISION MULTIPLEXED PASSIVE OPTICAL NETWORK

9. A method of compensating for crosstalk in a mode division multiplexing passive optical network, the method comprising:inputting a plurality of downlink reference signals to a multiplexer, each of the plurality of downlink reference signals being in a different one of a plurality of modes;transmitting the plurality of downlink reference signals as a mode multiplexed signal along an optical fibre;receiving the mode multiplexed signal at a demultiplexer;
outputting a plurality of received downlink reference signals from the demultiplexer, each of the received plurality of downlink reference signals being in a different one of a plurality of modes;
coupling the received plurality of downlink reference signals into an uplink reference signal,
transmitting the uplink reference signal in a quasi-single mode transmission along the optical fibre,
adapting a plurality of optical signals input to the multiplexer based on the uplink reference signal to pre-compensate for crosstalk.

US Pat. No. 10,193,615

APPARATUS AND METHOD FOR COMMUNICATIONS MANAGEMENT

BAE Systems Plc, London ...

1. Apparatus for management of communications resources of a moving platform comprising an on-board communications system configured to effect wireless data communication between said moving platform and another node, said communications resources comprising a plurality of wireless communications links and a plurality of antennas associated therewith, the apparatus comprising an antenna analysis and selection module residing with said communications system and configured to:receive, during a mission from one or more systems/subsystems and/or functions of said moving platform, attribute data representative of said emissions control criteria, said attribute data comprising (i) location data representative of a specified emissions control region, and (ii) position and/or attitude and/or velocity data representative of an adversary node defining an emissions control region;
determine, using said attribute data and based on said emissions control criteria, suitability of one or more on-board antennas and/or portions of aperture antenna for supporting said communications requirement;
for each of a plurality of antennas/portions of aperture antenna determined to be suitable for supporting said communications requirement based on said emissions control criteria, determine a quality metric, said quality metric being indicative of a respective performance criterion; and
select one or more of said suitable antennas/portion of aperture antenna having a highest performance criterion, for facilitating said communications requirement.

US Pat. No. 10,193,613

PING PONG BEAMFORMING

Intel IP Corporation, Sa...

1. One or more non-transitory, computer-readable media having one or more instructions, the one or more instructions comprising instructions that, when executed, cause a first device to:perform a ping-pong beamforming process, wherein the instructions that, when executed, cause the first device to perform the ping-pong beamforming process comprise instructions that, when executed, cause the first device to:
send a first training signal using a first weight vector to a second device;
receive, from the second device, a second training signal sent using a second weight vector;
estimate, based on the second training signal, an indexed signal, wherein an estimate of the indexed signal comprises a product of the second weight vector and a channel;
determine a third weight vector based on a complex conjugate of the estimate of the indexed signal; andnormalize the third weight vector; andperform a first iteration of the ping-pong beamforming process using a transmission protocol to exchange one or more messages with the second device, the transmission protocol comprising a plurality of time slots, and an individual time slot selected from the plurality of time slots dedicated to one transmission direction and comprising a training period followed by a data period, wherein the first iteration of the ping-pong beamforming process comprises the send, the receive, the estimate, the determine, and the normalize.

US Pat. No. 10,193,610

ENHANCING MU-MIMO TO GROUP CLIENTS ACROSS MULTIPLE BSSIDS FOR A PHYSICAL RADIO

Hewlett Packard Enterpris...

1. A method comprising:determining, by a network device, a first plurality of client devices associated with an access point (AP) corresponding to a first basic service set (BSS) that uniquely identifies a first wireless local area network (WLAN), wherein traffic flows between each of the first plurality of client devices and the AP comprise similar frame sizes and similar inter-arrival times;
transmitting, by the network device, sounding frames to the first plurality of client devices associated with the AP;
receiving, by the network device, a plurality of feedback frames, each feedback frame indicating how the sounding frames were received by each of the first plurality of client devices;
grouping, by the network device, the first plurality of client devices into a single multi-user multiple input multiple output (MU-MIMO) group for beamforming based on the received plurality of feedback frames;
simultaneously transmitting, by the network device, the traffic flows to the first plurality of client devices in the MU-MIMO group.

US Pat. No. 10,193,609

METHOD FOR FEEDING BACK CHANNEL STATE INFORMATION, BASE STATION AND USER EQUIPMENT

China Academy of Telecomm...

1. A method for feeding back Channel State Information (CSI), comprising steps of:dividing a plurality of antenna ports into a plurality of groups of antenna ports;
configuring for each group of antenna ports a same intra-group codebook set consisting of a plurality of intra-group precoding matrices, allocating for each group of antenna ports a plurality of different reference signals corresponding to a same reference resource, and configuring for each antenna port in each group of antenna ports a precoded reference signal acquired after a precoding operation using the intra-group precoding matrices, a number of the reference resources corresponding to a number of the intra-group precoding matrices in the intra-group codebook set, and a number of the reference signals corresponding to each reference resource corresponding to a number of groups of inter-group antenna ports;
transmitting the precoded reference signal to a User Equipment (UE) via each antenna port; and
receiving the CSI fed back by the UE based on measurement on the reference signal.

US Pat. No. 10,193,608

METHOD FOR TRANSMITTING/RECEIVING CHANNEL STATE INFORMATION IN WIRELESS COMMUNICATION SYSTEM AND DEVICE THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for transmitting, by a user equipment (UE), channel state information (CSI) in a wireless communication system, the method comprising:determining CSI for a serving cell of an unlicensed band; and
transmitting the CSI at a periodic CSI reporting instance within a reserved resource period (RRP) which is a time period occupied to transmit and receive data in the serving cell,
wherein another CSI prior to an initial rank indication (RI) reporting instance within the RRP is dropped or transmitted through an out of range (OOR) message.

US Pat. No. 10,193,605

BEAMFORMING CODEWORD EXCHANGE BETWEEN BASE STATIONS

Comcast Cable Communicati...

1. A first base station configured to communicate with a wireless device, the first base station comprising:one or more processors; and
memory storing instructions that, when executed by the one or more processors, cause the first base station to:
receive, from a second base station, at least one message comprising a plurality of downlink beamforming information elements for a downlink cell, wherein each downlink beamforming information element of the plurality of downlink beamforming information elements is associated with a respective resource block of a plurality of resource blocks in the downlink cell and indicates a parameter for beamforming for the respective resource block;
select, for at least one resource block of the plurality of resource blocks, a first beamforming codeword based at least in part on at least one first downlink beamforming information element of the plurality of downlink beamforming information elements, wherein the at least one first downlink beamforming information element is associated with the at least one resource block; and
transmit, to the wireless device, signals on the at least one resource block employing the first beamforming codeword.

US Pat. No. 10,193,604

DEVICE, NETWORK, AND METHOD FOR RECEIVING DATA TRANSMISSION UNDER SCHEDULING DECODING DELAY IN MMWAVE COMMUNICATION

Futurewei Technologies, I...

1. A method for receiving a millimeter wave (mmWave) communication, comprising the operations of:receiving, at a user equipment (UE), a control transmission portion of the mmWave communication;
assigning scheduling restrictions to an earlier portion of the control transmission portion of the mmWave communication;
performing demodulation and decoding of the earlier portion of the control transmission portion;
prior to completion of the demodulation and decoding of the earlier portion of the control transmission portion, receiving, an earlier portion of a data transmission portion of the mmWave communication, the earlier portion of the data transmission portion of the mmWave communication corresponding to the earlier portion of the control transmission portion of the mmWave communication;
performing beamforming of the earlier portion of the data transmission portion of the mmWave communication using default parameters;
performing demodulation and decoding of a later portion of the control transmission portion; and
performing beamforming of the later portion of the data transmission portion of the mmWave communication using parameters obtained during the performing of demodulation and decoding of the later portion of the control transmission portion.

US Pat. No. 10,193,597

ELECTRONIC DEVICE HAVING SLOTS FOR HANDLING NEAR-FIELD COMMUNICATIONS AND NON-NEAR-FIELD COMMUNICATIONS

Apple Inc., Cupertino, C...

1. An electronic device, comprising:a housing having a peripheral conductive wall;
a dielectric-filled gap in the peripheral conductive wall that divides the peripheral conductive wall into first and second segments;
an antenna ground separated from the peripheral conductive wall by a slot;
a non-near-field communications antenna having an antenna feed coupled between the first segment and the antenna ground across the slot;
a near-field communications antenna having a first antenna feed terminal coupled to the first segment and a second antenna feed terminal coupled to the second segment;
a transmission line coupled to the first and second antenna feed terminals; and
near-field communications transceiver circuitry coupled to the transmission line, wherein the near-field communications transceiver circuitry is configured to convey near-field communications signals using the near-field communications antenna.

US Pat. No. 10,193,596

MAGNETIC COUPLING DEVICE WITH REFLECTIVE PLATE AND METHODS FOR USE THEREWITH

1. A coupling device comprising:a receiving portion, that receives, from a transmitting device, a radio frequency signal conveying data;
an electromagnetic coupler, that electromagnetically couples the radio frequency signal to a transmission medium as a guided electromagnetic wave that is guided by a surface of the transmission medium; and
a dielectric portion that secures the transmission medium adjacent to the electromagnetic coupler and provides a spacing between the electromagnetic coupler and a reflective plate that reduces electromagnetic emissions from the electromagnetic coupler, wherein the spacing corresponds to substantially one-half of a wavelength of the radio frequency signal.

US Pat. No. 10,193,593

SIGNAL PROCESSING DEVICE, COMMUNICATION SYSTEM, AND SIGNAL PROCESSING METHOD

NEC CORPORATION, Minato-...

1. A signal processing device comprising:an electrical signal generation unit generating an electrical signal on the basis of an optical signal which is polarization-multiplexed and multi-value-modulated and which is transmitted through an optical transmission path; and
a compensation unit performing a compensation process on the electrical signal,
wherein the compensation unit includes:
a Fourier transform unit performing Fourier transform on the electrical signal;
an equalization processing unit performing an equalization process on the electrical signal having undergone the Fourier transform in a frequency domain;
an inverse Fourier transform unit performing inverse Fourier transform on the electrical signal having undergone the equalization process; and
an equalization coefficient setting unit setting an equalization coefficient matrix W(f) used for the equalization process, and
wherein the equalization coefficient setting unit sets the equalization coefficient matrix W(f) on the basis of the following equation:
W(f)=H(f)H(f)(H(f)HH(f)+(1/Es)×???1
such that H(f)=G(f)×C(f), HH is a Hermitian transposed matrix of a matrix H, Es is power of the optical signal, and ? is a diagonal matrix with N rows and N columns defined on the basis of colored noise, and
G(f) is a diagonal matrix set on the basis of a band limit condition during generation of the optical signal, and C(f) is a diagonal matrix set on the basis of wavelength dispersion incurred in the optical transmission path.

US Pat. No. 10,193,592

TECHNIQUES FOR DETECTING AND CANCELLING INTERFERENCE IN WIRELESS COMMUNICATIONS

QUALCOMM Incorporated, S...

1. A method for cancelling interference in wireless communications, comprising:performing an energy level detection of a received signal to determine an allocation size and position corresponding to an interfering device in the received signal;
determining an interference demodulation reference signal (DM-RS) and cyclic shift of the interfering device in the received signal;
determining, based at least in part on the allocation size and position and the interference DM-RS and cyclic shift, whether to apply successive interference cancellation on the received signal to cancel interference from the interfering device; and
applying the successive interference cancellation on the received signal based on determining to apply the successive interference cancellation.

US Pat. No. 10,193,591

METHODS AND DEVICES FOR CONTROLLING RECEIVE CONFIGURATIONS IN WIRELESS COMMUNICATIONS

Intel Deutschland GmbH, ...

1. A circuit, comprising:a first receiver configured to demodulate a first down-converted signal, which is generated by a first radio frequency (RF) stage;
a second receiver configured to demodulate a second down-converted signal, which is generated by a second radio frequency (RF) stage; and
a controller configured to control the first RF stage and the second RF stage and the first receiver and the second receiver to alternate between a first receive configuration, in which the first down-converted signal and the second down-converted signal are both received from a first radio network, and a second receive configuration, in which the first down-converted signal is received from the first radio network and the second down-converted signal is received from a second radio network.

US Pat. No. 10,193,588

HEAD PROTECTION DEVICE, COMMUNICATION UNIT, CONNECTION UNIT AND SYSTEM COMPRISING HEAD PROTECTION DEVICE, COMMUNICATION UNIT AND CONNECTION UNIT

1. A head protection device comprising a communication unit, wherein the communication unit comprises:a communication interface configured to transmit a first communication signal and to receive a second communication signal, the communication signals being digital electrical signals; and
a signal processor with an interface configured to send the first communication signal, an interface configured to detect a microphone signal, an interface configured to detect a second communication signal and an interface configured to send an ear speaker signal and the signal processor is configured such that the first communication signal is sent as a function of the microphone signal, and that the ear speaker signal is sent as a function of the second communication signal, wherein:
the signal processor further comprises a data interface incorporated into the communication interface;
the signal processor is configured to receive parameter data via the data interface;
the signal processor is configured to adapt a digital signal processing of the microphone signal for sending the first communication signal as a function of the parameter data, the signal processor adapts the digital signal processing of the microphone signal to the sending of the first communication signal such that an adaptation of the frequency response of the first communication signal is made;
the communication interface is located in an external area of the communication unit; and
the communication interface is an electrical contact unit configured to mechanically and electrically connect to a connection unit.

US Pat. No. 10,193,587

MOBILE PHONE AND COMMUNICATION METHOD THEREOF

ZTE CORPORATION, Shenzhe...

1. A mobile phone, comprising a mobile phone body and a mobile phone accessory, wherein the mobile phone accessory comprises a mobile phone card configured to communicate with an external communication device, a storage module configured to store user data and a second communication module configured to establish wireless communication with the mobile phone body; and the mobile phone body comprises:a first communication module configured to perform data interaction with the second communication module and establish wireless communication between the mobile phone body and the mobile phone accessory;
a mobile phone card information reading module configured to read information of the mobile phone card in the mobile phone accessory;
a basic communication module configured to communicate with an external communication device according to the information of the mobile phone card; and
a data transmission control module configured to send an operation instruction to the storage module, to store the user data stored in the storage module to a local memory or update user data in the local memory to the storage module.

US Pat. No. 10,193,586

DIRECT CONVERSION RECEIVER WITH CORRECTION FOR SECOND ORDER DISTORTION IN RF MIXER

TEXAS INSTRUMENTS INCORPO...

1. A receiver comprising:a clock generator to provide a first clock signal and a second clock signal;
a first node;
a second node;
a zero-intermediate frequency (zero-IF) mixer coupled to the first and second nodes, clocked by the first and second clock signals, and comprising a first transimpedance amplifier and a second transimpedance amplifier to provide a direct-conversion voltage;
a current injector, coupled to the first and second nodes, configurable to inject into the first and second nodes a common mode current or a differential mode current; and
a controller, coupled to the zero-IF mixer and the current injector, to adjust at least one of the first and second transimpedance amplifiers based on the direct-conversion voltage when the current injector is to inject the common mode current.

US Pat. No. 10,193,584

ADJUSTING AN ANTENNA CONFIGURATION OF A TERMINAL DEVICE IN A CELLULAR COMMUNICATION SYSTEM

Sony Mobile Communication...

1. A method for adjusting an antenna configuration of a terminal device in a cellular communication system, the cellular communication system comprising a base station and the terminal device. the terminal device being a portable user equipment and comprising a plurality of antenna elements, the method comprising:providing, in the terminal device, a plurality of preset antenna configurations, each antenna configuration of the plurality of preset antenna configurations defining phase information and amplitude information for each of the plurality of antenna elements, the phase information and the amplitude information used in combining signals respectively received by the antenna elements,
determining a reception characteristic of a signal transmission sent from the base station and received at the plurality of antenna elements,
comparing the determined reception characteristic with a threshold value,
in response to the determined reception characteristic is greater than the threshold value, adjusting the antenna configuration according to a channel sounding procedure, and
in response to the determined reception characteristic is less than the threshold value, adjusting the antenna configuration by:
performing consecutively for each preset antenna configuration of the plurality of preset antenna configurations:
applying the antenna configuration to the plurality of antenna elements, and
determining a reception characteristic of a signal transmission sent from the base station and received at the plurality of antenna elements with the applied antenna configuration,
selecting one antenna configuration of the plurality of preset antenna configurations based on the plurality of reception characteristics determined for the plurality of preset antenna configurations, and
applying the selected antenna configuration to the plurality of antenna elements for further signal transmissions.

US Pat. No. 10,193,579

STORAGE CONTROL DEVICE, STORAGE SYSTEM, AND STORAGE CONTROL METHOD

Toshiba Memory Corporatio...

1. A storage control device comprising:a controller that receives a request to write a data item and determines whether or not a wear degree of a target region in a storage device is less than a threshold value, the target region being a region to which the data item is written;
a compression condition determiner that determines, based on the wear degree, a compression condition out of a plurality of compression conditions including lossy compression, the compression conditions indicating how to compress the data item;
a first error correction encoder that adds an error correction code to the data item when the wear degree is less than the threshold value to generate a first encoded data item; and
a compressor that generates a compressed data item of the first encoded data item based on the compression condition,
wherein the compression condition determiner determines the compression condition that performs lossy compression capable of correcting the error and has a shortest code length of the compressed data item.

US Pat. No. 10,193,578

FLEXIBLE POLAR ENCODERS AND DECODERS

1. A method of encoding data comprising:inputting data to a first non-systematic polar encoder having a first pipeline defining a first input and a first output, and capable of encoding a polar code of length nmax;
extracting, via at least one first multiplexer of size log nmax×1, a first polar code of length n modifying the first encoded output to set frozen bits to a known value to obtain a modified first encoded output;
inputting the modified first encoded output to a second non-systematic polar encoder having a second pipeline defining a second input and a second output, and capable of encoding a polar code of length nmax; and
extracting, via at least one second multiplexer of size log nmax×1, a second polar code of length n

US Pat. No. 10,193,577

STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION

Micron Technology, Inc., ...

1. A method, comprising:receiving a codeword with an error correction circuit;
iteratively error correcting the codeword with the error correction circuit including:
parity checking the codeword on a layer-by-layer basis; and
updating the codeword after each layer;
stopping the iterative error correction in response to a parity check being correct for a particular layer of a particular iteration within a threshold number of units of data without error correcting a next layer of the particular iteration, wherein the threshold number of units of data is at least one; and
selecting the threshold number based on a characteristic of an apparatus, the apparatus including the error correction circuit, selected from the group of characteristics including: a temporal age of the apparatus, a number of program/erase cycles of the apparatus, a storage density of the apparatus, a retention rate of the apparatus, and a physical location within the apparatus where the codeword is stored.

US Pat. No. 10,193,576

MEMORY SYSTEM AND MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:a memory cell array configured to store data, a first parity generated in association with the data based on a first error correction code (ECC) scheme, and a second parity generated in association with the data and the first parity based on a second error correction code (ECC) scheme;
a first ECC control circuit configured to execute a first error correction using the first ECC scheme and the first parity during a read operation on the memory cell array;
a second ECC control circuit configured to execute a second error correction using the second ECC scheme and the second parity during a scrub operation on the memory cell array; and
a register in which a range of addresses is registered within which an error uncorrectable by the first error correction with the first ECC control circuit has occurred,
wherein the first ECC scheme and the second ECC scheme have error correction capabilities of different levels, and
wherein the second ECC control circuit executes the second error correction so as to give priority to the range indicated by the registered addresses.

US Pat. No. 10,193,575

DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN DIGITAL BROADCASTING SYSTEM

LG ELECTRONICS INC., Seo...

1. An apparatus for receiving a broadcast signal, the apparatus comprising:a tuner to receive the broadcast signal, wherein the broadcast signal includes a first region and a second region, wherein the first region is concatenated with the second region, wherein the broadcast signal includes known data, signaling information, and service data;
a signaling decoder to decode the signaling information for signaling the service data, wherein the signaling information includes a first field indicating a number of subframes in a frame;
a deinterleaver to deinterleave the service data; and
a decoder to decode the deinterleaved service data,
wherein the broadcast signal further includes fast service acquisition information between a physical layer and an upper layer,
wherein the signaling information further includes a second field for the fast service acquisition information,
wherein the service data includes a data packet which includes a header and a payload,
wherein the header of the data packet includes a pointer field which represents start position information of the payload, and
wherein the header of the data packet further includes a field which is related with stuffing bytes which fills a portion in front of the payload in the data packet.

US Pat. No. 10,193,574

EFFICIENT SYNDROME CALCULATION IN PROCESSING A GLDPC CODE

APPLE INC., Cupertino, C...

1. An apparatus, comprising:an interface, which is configured to receive input data to be processed in accordance with a Generalized Low-Density Parity-Check (GLDPC) code defined by a parity-check-matrix comprising multiple sub-matrices, wherein each of the sub-matrices comprises N block-rows and N block-columns of block matrices, wherein the sub-matrices comprise main diagonals and secondary diagonals, and wherein each of the main diagonals and each of the secondary diagonals comprises N respective block matrices;
a main processing module, which is configured to calculate N first partial syndromes based on the input data and on the block matrices of the main diagonals of the sub-matrices;
a secondary processing module, which is configured to calculate N second partial syndromes based on the input data and on the block matrices of the secondary diagonals of the sub-matrices; and
combiner circuitry, which is configured to produce N syndromes by respectively combining the N first partial syndromes with the N second partial syndromes, and to encode or decode the input data, based on the N syndromes, in accordance with the GLDPC code.

US Pat. No. 10,193,573

METHOD AND DATA PROCESSING DEVICE FOR DETERMINING AN ERROR VECTOR IN A DATA WORD

Infineon Technologies AG,...

1. A method of increasing data word correctability of a corrupted data word beyond a threshold of half a minimum distance of a code minus one using linear recursion syndrome determination, the method comprising:receiving the data word, wherein n is a length of the received data word, and k is a dimension of the code as determined by n=2k?1;
determining a syndrome, the syndrome comprising a first 2k?1?k sequence elements of the received data word and a second 2k?1?k elements derived according to a linear recursion formula;
successively generating code words by selecting each of a first 2k?1?k elements to be either 0 or 1 calculating a next n?2k?1?k elements using a linear recursion formula; forming, for each code word generated, a sum of the syndrome supplemented with zeros to the data word length and the code word, and checking, for the code word, whether the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among each of the sum of the syndrome supplemented with zeros; and
determining the error vector as the sum of the syndrome and the code word for which the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words; and
correcting the data word using the error vector,
wherein the minimum distance of the code is a smallest Hamming distance between two code words.

US Pat. No. 10,193,569

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method, for a flash memory device, the decoding method comprising:executing at least one first iteration decoding procedure of a low density parity code (LDPC) on a first codeword according to a first clock signal by a correcting circuit;
generating, by a memory control circuit unit, a control parameter for adjusting a first frequency of the first clock signal to a second frequency of a second clock signal according to a first iteration count of the at least one first iteration decoding procedure in order to reduce a power consumption for decoding and maintain a decoding efficiency;
outputting, by the memory control circuit unit, the second clock signal to the correcting circuit according to the control parameter;
executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit;
outputting, by the memory control circuit unit, another clock signal to an adding circuit for outputting a valid codeword to a host system, wherein the another clock signal inputted to the adding circuit has a preset frequency which is different from the first frequency of the first clock signal or the second frequency of the second clock signal inputted to the correcting circuit for executing the at least one first iteration decoding procedure of the LDPC or the at least one second iteration decoding procedure of the LDPC;
correcting the second codeword, by the adding circuit, according to the another clock signal and error index information output by the correcting circuit,
wherein the error index information includes an error bit index, the error bit index is used to correct one or more data bits in the second codeword to generate the valid codeword; and
outputting, by the adding circuit, the valid codeword to the host system.

US Pat. No. 10,193,568

OPTICAL COHERENT RECEIVER WITH FORWARD ERROR CORRECTION

Alcatel Lucent, Boulogne...

1. An optical coherent receiver comprising a number of decoding blocks, each decoding block being configured to implement an iteration of a forward error correction iterative message-passing decoding algorithm, said number of decoding blocks being distributed into at least two parallel chains of cascaded decoding blocks, wherein said optical coherent receiver also comprises at least one intermediate circuit interposed between said two parallel chains, wherein said optical coherent receiver is switchable between:a first operating mode, in which said intermediate circuit is inactive and each one of said two parallel chains separately implements said forward error correction message-passing decoding algorithm on a respective client channel; and
a second operating mode, in which said intermediate circuit is active and said two parallel chains jointly implement said forward error correction message-passing decoding algorithm on a same client channel by cooperating through said intermediate circuit.

US Pat. No. 10,193,566

ENCODING/DECODING SYSTEM FOR PARALLEL DATA

NIPPON TELEGRAPH AND TELE...

1. A parallel data encoding/decoding system which performs parallel data transmission from an encoder to a decoder using a plurality of lanes, the number of the plurality of lanes being R, R being an integer that is larger than or equal to 2,wherein the encoder generates a code vector M having R elements, each element of the code vector M is a symbol to be transmitted in parallel using the plurality of lanes, the code vector M being denoted M={m0, m1, m2, . . . mR?1|mi?GF(2n)}, m0, m1, m2, . . . mR?1 being the elements of the code vector M, GF(2n) being an n-order extension field of a Galois field, the number of the elements being equal to the number of the plurality of lanes, and the state vector U having R elements, each element in the state vector U is a code indicating to the decoder whether each of the corresponding elements of the code vector M is valid or invalid, the state vector U being denoted as U=(u0, u1, u2, . . . uR?1|ui?{0, 1}), u0, u1, u2, . . . uR?1 being the elements of the state vector U,
calculates products {m0u0, m1u1, m2u2, . . . , mR?1uR?1|mi?M, ui?U} of the elements of the code vector M and the elements of the state vector U,
generates a transmission vector Y by encoding the calculated products using a maximum distance separable (2R, R) block code with which erasure of R symbols is capable of being corrected,
transmits the transmission vector Y through the plurality of lanes, and
transmits the state vector U through the plurality of lanes or a path separate from the plurality of lanes,
the encoder comprises an MDS encoding computer that performs the encoding of the calculated products using the maximum distance separable (MDS) block code, and
the decoder decodes a subset Msub of the code vector M, the subset Msub being constituted of a valid element of the code vector M, using a received reception vector Y?, the received state vector U, and an erasure vector E indicating whether each element of the transmission vector Y has been erased in a transmission/reception section.

US Pat. No. 10,193,564

ANALOG-TO-DIGITAL CONVERTER

TEXAS INSTRUMENTS INCORPO...

1. A system, comprising:a multiplex circuit having: a plurality of inputs to receive a respective plurality of analog signals, including a first input to receive a first analog signal; and an output to provide an output signal, multiplexed from among the received analog signals; and
an analog-to-digital converter (ADC) to convert the output signal, relative to a reference voltage, into a corresponding digital value, wherein: if the output signal is the first analog signal, then the reference voltage is a fixed voltage; and if the output signal is other than the first analog signal, then the reference voltage is a variable voltage of the first analog signal.

US Pat. No. 10,193,563

SEMICONDUCTOR DEVICE, WIRELESS SENSOR, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a sample-and-hold circuit including a transistor including an oxide semiconductor containing indium and oxide in a channel formation region and a capacitor;
a comparator electrically connected to one of a source and a drain of the transistor and the capacitor;
a successive approximation register electrically connected to the comparator;
a digital-analog converter circuit electrically connected to the successive approximation register and the comparator; and
a timing controller electrically connected to a gate of the transistor, the successive approximation register, and the digital-analog converter circuit,
wherein the other of the source and the drain of the transistor is electrically connected to an input terminal of the sample-and-hold circuit.

US Pat. No. 10,193,562

DIGITAL PHASE LOCKED LOOP CIRCUIT ADJUSTING DIGITAL GAIN TO MAINTAIN LOOP BANDWIDTH UNIFORMLY

Samsung Electronics Co., ...

1. A digital phase locked loop circuit comprising:a phase frequency detector configured to,
generate a first detection value associated with order between a first phase of a reference signal and a second phase of a fed-back signal, and
generate a second detection value based on the first detection value in response to the reference signal;
a bandwidth calibrator configured to,
amplify a signal level of the second detection value by a gain value, to generate an amplified detection value, and
adjust the gain value based on the first detection value;
a digital loop filter configured to generate a digital code based on the amplified detection value; and
a digital controlled oscillator configured to generate an output signal which has a frequency corresponding to the digital code, wherein
the fed-back signal is generated based on the output signal and is fed back to the phase frequency detector.

US Pat. No. 10,193,559

CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Seiko Epson Corporation, ...

1. A circuit device comprising:a delay locked loop (DLL) circuit, which has a plurality of delay elements, and to which a first clock signal generated using a first resonator and having a first clock frequency is input; and
an adjustment circuit, to which delayed clock signals from the delay elements of the DLL circuit, and a second clock signal generated using a second resonator and having a second clock frequency lower than the first clock frequency are input, and which adjusts delay amounts of the delay elements of the DLL circuit using a frequency difference between the first clock frequency and the second clock frequency.

US Pat. No. 10,193,558

CLOCK SIGNAL AND SUPPLY VOLTAGE VARIATION TRACKING

Micron Technology, Inc., ...

1. An apparatus comprising:a first tracking enablement circuit configured to enable a delay-locked loop tracking circuit based on a variation in a voltage output of a voltage source, a variation in a frequency of an input clock signal, or combinations thereof; and
a second tracking enablement circuit configured to enable a duty cycle correction circuit based on a variation in a duty cycle of the input clock signal.

US Pat. No. 10,193,556

METHOD AND APPARATUS FOR CONFIGURABLE CONTROL OF AN ELECTRONIC DEVICE

SKYWORKS SOLUTIONS, INC.,...

1. A configurable controller for establishing operational states of a device having a plurality of functional operating units, the configurable controller comprising:an input configured to receive an identifier of a desired operational state of the device;
a plurality of control outputs, each of the control outputs configured to couple to one or more of the plurality of functional operating units each having two or more operational states; and
a plurality of reference inputs each configured to receive a reference signal, at least one reference signal being mapped, based on the identifier, to at least one control output to provide a control signal that places each functional operating unit in a selected state of its two or more operational states to achieve the desired operational state of the device.

US Pat. No. 10,193,555

METHODS AND DEVICES FOR A MEMORY INTERFACE RECEIVER

Cadence Design Systems, I...

1. A receiver apparatus for receiving data from a memory device, the apparatus comprising:a first resistor wherein a first terminal of the first resistor is connected to a first receiver input of the memory receiver apparatus;
a first N-type metal oxide semiconductor (NMOS) field effect transistor (FET) wherein a drain terminal of the first NMOS FET is connected to a second terminal of the first resistor and a gate terminal of the first NMOS FET is connected to the drain terminal of the first NMOS FET;
a second NMOS FET wherein a gate terminal of the second NMOS FET is connected to the gate terminal of the first NMOS FET;
a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET; and
a complementary metal oxide semiconductor (CMOS) inverter wherein an input terminal of the CMOS inverter is connected to an output terminal of the trans-impedance amplifier;
wherein the first NMOS FET and the second NMOS FET are low voltage devices; and
wherein the first resistor is configured to shield the first NMOS FET and the second NMOS FET from input/output (I/O) voltage levels.

US Pat. No. 10,193,553

PROCESSING CIRCUIT CAPABLE OF DYNAMICALLY MODIFYING ITS PRECISION

1. A circuit comprising:a processing circuit comprising a plurality of circuit domains, each circuit domain comprising a plurality of transistors and being configured to apply one or more corresponding transistor biasing voltages to said transistors; and
a control circuit configured to determine, based on at least a selected accuracy setting of the processing circuit, the level of said one or more transistor biasing voltages to be applied in each of said circuit domains, the control circuit being further configured to cause said transistor biasing voltages to be applied to the circuit domains.

US Pat. No. 10,193,548

BIASING SCHEME FOR HIGH VOLTAGE CIRCUITS USING LOW VOLTAGE DEVICES

Intel Corporation, Santa...

1. An apparatus comprising:an integrated circuit including a first node to receive a supply voltage and a second node to receive ground potential; and
a transmitter located in the integrated circuit, the transmitter including a buffer to transmit a signal, the buffer including:
an output stage including a first pair of transistors coupled between the first node and an output node, and a second pair of transistors coupled between the output node and the second node;
the first pair of transistors including a first transistor and a second transistor, the first transistor including a first non-gate terminal directly coupled to a first non-gate terminal of the second transistor, the second transistor including a second non-gate terminal coupled to the output node;
the second pair of transistors including a first transistor and a second transistor, the first transistor of the second pair of transistors including first non-gate terminal directly coupled to a first non-gate terminal of the second transistor of the second pair of transistors, and the second transistor of the second pair of transistors including a second non-gate terminal directly coupled to the second non-gate terminal of the second transistor of the first pair of transistors; and
a bias stage to provide a first bias voltage to a gate of the second transistor in the second pair of transistors and a second bias voltage to a gate of the second transistor in the first pair of transistors, wherein a value of each of the first and second bias voltages is greater than zero, and the value of the second bias voltage is a value of the supply voltage minus the value of the first bias voltage.

US Pat. No. 10,193,544

MINIMIZING RINGING IN WIDE BAND GAP SEMICONDUCTOR DEVICES

Ford Global Technologies,...

1. A power conversion circuit, comprising:first and second semiconductor switches; and
a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch, wherein, during the period, a gate voltage of the second switch is steady or substantially steady.

US Pat. No. 10,193,543

ELECTRONIC DEVICE AND METHOD OF CONTROLLING SWITCHING ELEMENTS

CANON KABUSHIKI KAISHA, ...

1. An electronic device comprising:a first switching element connected between a power source and one end of a power inductor;
a second switching element connected between the one end of the power inductor and ground;
a detection unit that detects a current flowing to the second switching element and generates a current detection signal from the detected current; and
a control unit that gradually decreases an on-resistance of the first switching element when the first switching element is changed from an off-state to an on-state,
wherein the control unit controls a fall time of a gate voltage of the first switching element when the control unit gradually decreases the on-resistance of the first switching element,
wherein the control unit determines a driving mode corresponding to the fall time of the gate voltage of the first switching element, based on the current detection signal generated by the detection unit,
wherein the control unit causes a selector to select a resistor corresponding to the driving mode from among resistors,
wherein the control unit supplies a driving signal to a gate of the first switching element via the resistor selected by the selector, and
wherein the control unit includes the selector and the resistors.

US Pat. No. 10,193,542

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device for driving a high-side switching device and a low-side switching device ON and OFF in a complementary manner, the high-side switching device and the low-side switching device being totem pole-connected with a node therebetween to be connected to a load to drive the load, the semiconductor device comprising:a high-side driver circuit and a low-side driver circuit which respectively switch the high-side switching device and the low-side switching device ON and OFF in a complementary manner;
a bootstrap capacitor connected to a power supply that supplies driving power to the low-side driver circuit via a diode such that the bootstrap capacitor is charged when the low-side switching device is ON, and a resulting charge voltage is boosted and applied to the high-side driver circuit when the low-side switching device is OFF;
a supplementary bootstrap capacitor connected in parallel to the bootstrap capacitor via a switch circuit such that the supplementary bootstrap capacitor is charged by an intermediate voltage at an intermediate node between the high-side and low-side driver circuits that is to be connected to said node between the high-side switching device and the low-side switching device when the high-side switching device is ON;
a Zener diode that is connected to said intermediate node and that regulates a charging voltage of the supplementary bootstrap capacitor; and
a control circuit that controls the switch circuit so as to apply a charge voltage of the supplementary bootstrap capacitor to the high-side driver circuit when the charge voltage of the bootstrap capacitor decreases to less than a prescribed voltage while the high-side switching device is ON.

US Pat. No. 10,193,541

TRANSFORMERLESS SWITCHING REGULATOR WITH CONTROLLABLE BOOST FACTOR

Siemens Medical Solutions...

1. A switching regulator system comprising:a controller;
a boost converter comprising an inductor and a first transistor responsive to a control signal from the controller, the first transistor connected with the inductor such that the inductor connects to ground through the first transistor;
a charge pump having an input connected with an output of the boost converter;
a diode connected between the inductor and the input of the charge pump, the diode connected to prevent current from the charge pump entering the first transistor; and
a second transistor responsive to the control signal, the second transistor connected to the input of the charge pump.

US Pat. No. 10,193,540

LOW-POWER DECISION THRESHOLD CONTROL FOR HIGH-SPEED SIGNALING

XILINX, INC., San Jose, ...

1. An apparatus for decision threshold control, comprising:an alternating current coupler (“ac-coupler”) circuit configured as a high-pass circuit path for a first frequency range;
a buffer amplifier circuit coupled in parallel with the ac-coupler circuit and configured as a low-pass circuit path for a second frequency range; and
an offset injection circuit coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.

US Pat. No. 10,193,539

HIGH SPEED DATA SYNCHRONIZATION

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:an internal clock generation circuit configured to generate first to fourth internal clock signals from first to fourth division clock signals; and
a data input and output (I/O) circuit configured to output input data as output data in synchronization with the first to fourth internal clock signals,
wherein the first internal clock signal is generated after the fourth internal clock signal is generated, the second internal clock signal is generated after the first internal clock signal is generated, the third internal clock signal is generated after the second internal clock signal is generated, and the fourth internal clock signal is generated after the third internal clock signal is generated.

US Pat. No. 10,193,538

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first circuit block that is connected between a first power supply voltage line and a first reference voltage line;
a second circuit block that is connected between a second power supply voltage line and a second reference voltage line and transmits and receives signals with the first circuit block;
a resistor circuit that is connected between the second power supply voltage line and the second circuit block; and
a first clamp circuit that is connected between a line connected between the resistor circuit and the second circuit block and the first reference voltage line and clamps a potential difference between the line connected between the resistor circuit and the second circuit block and the first reference voltage line.

US Pat. No. 10,193,537

RANDOM DATA GENERATION CIRCUIT, MEMORY STORAGE DEVICE AND RANDOM DATA GENERATION METHOD

PHISON ELECTRONICS CORP.,...

1. A random data generation circuit, comprising:a phase difference detection circuit, configured to sample a first clock signal and a second clock signal based on a plurality of sampling clock signals, so as to detect a phase difference between the first clock signal and the second clock signal and output phase difference information; and
a random data output circuit, coupled to the phase difference detection circuit and configured to output random data according to the phase difference information.

US Pat. No. 10,193,535

OSCILLATION CIRCUIT, BOOSTER CIRCUIT, AND SEMICONDUCTOR DEVICE

ABLIC INC., Chiba (JP)

1. An oscillation circuit, comprising:a ring oscillator circuit in which odd stages of inverter circuits, each of which includes a PMOS transistor and an NMOS transistor that are connected to each other in series, are cascade connected such that the inverter circuits are connected to form a ring;
a first constant current element formed of a PMOS transistor configured to cause a predetermined current to flow to the inverter circuits;
a second constant current element formed of an NMOS transistor configured to cause a predetermined current to flow to the inverter circuits; and
a power supply circuit configured to generate a first bias voltage, a second bias voltage, and a second power supply voltage from a first power supply voltage,
the second power supply voltage being a constant voltage when the first power supply voltage is at a predetermined voltage or higher,
the PMOS transistor in each of the inverter circuits including a source connected to a drain of the PMOS transistor, which is the first constant current element, and a substrate to which the first power supply voltage is input,
the NMOS transistor in each of the inverter circuits including a source connected to a drain of the NMOS transistor, which is the second constant current element, and a substrate to which a ground voltage is input,
the PMOS transistor, which is the first constant current element, including a gate to which the first bias voltage is input, and a source and a substrate to which the second power supply voltage is input,
the NMOS transistor, which is the second constant current element, including a gate to which the second bias voltage is input, and a source and a substrate to which the ground voltage is input.

US Pat. No. 10,193,533

METHODS AND SYSTEMS FOR EVENT-DRIVEN RECURSIVE CONTINUOUS-TIME DIGITAL SIGNAL PROCESSING

The Trustees of Columbia ...

1. A continuous-time digital signal processor comprising:an event-grouping block, configured to receive a first input timing signal, a second input timing signal, and to generate an intermediate timing signal;
a first time delay block, configured to receive the intermediate timing signal and generate an output timing signal;
a second time delay block, configured to receive the output timing signal and generate the second input timing signal;
a two-channel memory configured to receive a first data input and a second data input and to generate a first intermediate data signal and a second intermediate data signal;
an arithmetic operation block, configured to receive the first intermediate data signal, the second intermediate data signal and to generate an output data signal, the arithmetic operation block comprising:
a scalar block configured to receive the second intermediate data signal and generate a scaled version of the second intermediate data signal; and
an adder configured to receive the first intermediate data signal and the scaled version of the second intermediate data signal, and generate the output data signal; and
a first-in-first-out (FIFO) memory configured to receive the output data signal and to generate the second input data signal.

US Pat. No. 10,193,529

ELASTIC WAVE DEVICE

Murata Manufacturing Co.,...

1. An elastic wave device comprising:a first signal terminal;
a second signal terminal;
a first interdigital transducer (IDT) electrode and a second IDT electrode that are adjacent to or in a vicinity of each other in or substantially in a direction of propagation of elastic waves; and
at least one bridging capacitance; wherein
each of the first IDT electrode and the second IDT electrode includes a pair of comb-shaped electrodes, each of the comb-shaped electrodes including a busbar electrode extending in or substantially in the direction of propagation of elastic waves and a plurality of electrode fingers connected to the busbar electrode and extending in or substantially in a direction that crosses the direction of propagation of elastic waves;
one of the pair of comb-shaped electrodes in the first IDT electrode is a first comb-shaped electrode directly electrically connected to the first signal terminal, and one of the pair of comb-shaped electrodes in the second IDT electrode is a second comb-shaped electrode electrically connected to the second signal terminal;
the bridging capacitance is arranged in a region outside a region sandwiched between the electrode fingers that are adjacent to or in a vicinity of each other in or substantially in the direction of propagation of elastic waves and includes a pair of comb-shaped electrodes opposed to each other at a predetermined interval; and
a first one of the pair of comb-shaped electrodes in the bridging capacitance is a first comb-shaped electrode directly electrically connected to the first comb-shaped electrode of the first IDT electrode, and a second one of the pair of comb-shaped electrodes is a second comb-shaped electrode electrically connected to either one of the pair of comb-shaped electrodes in the second IDT electrode.

US Pat. No. 10,193,528

ACOUSTIC WAVE DEVICE AND ACOUSTIC WAVE MODULE

KYOCERA Corporation, Kyo...

1. An acoustic wave device, comprising:a piezoelectric substrate;
an excitation electrode on the piezoelectric substrate;
an electrode pad arranged on the piezoelectric substrate and electrically connected with the excitation electrode; and
a cover arranged on the piezoelectric substrate so that a oscillation space is arranged between the cover and the excitation electrode, wherein
the cover, in an internal portion, comprises a via conductor electrically connected to the electrode pad and its surface facing the piezoelectric substrate is curved so as to approach the excitation electrode side,
the cover is an organic substrate including fibers extending in the surface direction, and
a portion of the fibers is buried in the via conductor.

US Pat. No. 10,193,527

BRANCHING FILTER

TDK CORPORATION, Tokyo (...

9. A branching filter comprising:a common port;
a first signal port;
a second signal port;
a low-pass filter provided between the common port and the first signal port, and configured to selectively pass a signal of a frequency within a first passband not higher than a first cut-off frequency, the low-pass filter including:
a first LC resonant circuit; and
a first acoustic wave resonator provided in a shunt circuit connecting a path leading from the first LC resonant circuit to the first signal port to a ground, the first acoustic wave resonator having a resonant frequency higher than the first cut-off frequency; and
a high-pass filter provided between the common port and the second signal port, and configured to selectively pass a signal of a frequency within a second passband not lower than a second cut-off frequency higher than the first cut-off frequency, the high-pass filter including:
a second LC resonant circuit; and
a second acoustic wave resonator provided in a path leading from the second LC resonant circuit to the second signal port, the second acoustic wave resonator having an anti-resonant frequency lower than the second cut-off frequency.

US Pat. No. 10,193,522

SINGLE PORT WIDE BAND IMPEDANCE MATCHING CIRCUIT WITH NARROW BAND HARMONIC BYPASS, WIRELESS COMMUNICATION DEVICE, AND METHOD FOR PROVIDING ANTENNA MATCHING

Motorola Mobility LLC, C...

15. A wireless communication device comprising:one or more transceivers;
a single signal port coupled to the one or more transceivers, the single signal port including a wide band signal;
an impedance matching circuit including a narrow band harmonic bypass, the narrow band harmonic bypass being configured to produce a short at a predetermined frequency, which corresponds to a harmonic of a lower frequency signal included as part of the wide band signal received at the single signal port;
an antenna port coupled to the single signal port via the impedance matching circuit; and
an antenna coupled to the antenna port.

US Pat. No. 10,193,521

ADJUSTABLE IMPEDANCE MATCHING NETWORK

Infineon Technologies AG,...

1. An impedance matching network comprising:a first port;
a second port; and
an adaptive matching network connected between the first port and the second port,
wherein the adaptive matching network comprises at least two stages,
wherein the adaptive matching network comprises a series inductance with an intermediate tap and a capacitive element connected to the intermediate tap,
wherein the series inductance comprises a first inductance associated with a first stage of the at least two stages and a second inductance associated with a second stage,
wherein the first inductance and the second inductance form a transmission line transformer,
wherein the series inductance is located in a first inductor path of a series branch of the adaptive matching network, and
wherein the first inductance and the second inductance are inductively coupled.

US Pat. No. 10,193,520

DIGITAL SWITCHED ATTENUATOR

SKYWORKS SOLUTIONS, INC.,...

1. An attenuation cell for use in a switched attenuator, the attenuation cell comprising:an attenuation path having an input, a first switch, a resistive network, a second switch, and an output, the resistive network electrically disposed between the first switch and the second switch and configured to provide a desired attenuation from the input to the output;
a bypass path in parallel with the attenuation path and having a bypass switch disposed between the input and the output; and
a shunt switch including at least four series-connected switching elements, the shunt switch being coupled between the resistive network and a reference node to selectively connect the resistive network to the reference node.

US Pat. No. 10,193,518

RADIO-FREQUENCY (RF) COMPONENT

MURATA MANUFACTURING CO.,...

1. A radio-frequency component comprising:a first substrate including one or more first wiring electrodes, and a plurality of stacked insulating layers;
a column-shaped spacer member placed on a first main face of the first substrate;
a second substrate including a second wiring electrode, and a plurality of stacked insulating layers, the second substrate being spaced from the first substrate by being stacked on the column-shaped spacer member; and
an inductor component mounted on the first main face of the first substrate,
wherein a first no-electrode-forming area where the one or more first wiring electrodes are not formed is set to a range overlapping with the inductor component in a plan view of at least one of the plurality of stacked insulating layers of the first substrate, and
wherein a second no-electrode-forming area where the second wiring electrode is not formed is set to a range overlapping with the inductor component in a plan view of at least one of the plurality of stacked insulating layers of the second substrate.

US Pat. No. 10,193,517

VARIABLE FILTER CIRCUIT AND RADIO COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. A variable filter circuit comprising:a first series arm including a first resonator connected in series between a first input/output terminal and a node;
a second series arm including a second resonator connected in series between a second input/output terminal and the node; and
a parallel arm connected between the node and a ground connection terminal,
wherein the parallel arm includes a first inductor connected in series between the node and the ground connection terminal, and
at least one of the first and second series arms includes a variable capacitor connected in parallel to the first or second resonator,
wherein each of the first and second series arms includes first and second parallel inductors respectively connected in parallel to the first and second resonators and first and second series inductors respectively connected in series to circuits in which the first and second resonators and the first and second parallel inductors are respectively connected in parallel.

US Pat. No. 10,193,516

COMMON MODE FILTER

TDK CORPORATION, Tokyo (...

1. A common mode filter comprising:a core including a winding core part extending in an axial direction, a first flange part provided at one end of the winding core part in the axial direction, and a second flange part provided at other end of the winding core part in the axial direction;
first and second terminal electrodes provided on the first flange part;
third and fourth terminal electrodes provided on the second flange part;
a first wire wound around the winding core part and having one end connected to the first terminal electrode and other end connected to the third terminal electrode; and
a second wire wound around the winding core part and having one end connected to the second terminal electrode and other end connected to the fourth terminal electrode,
wherein the winding core part includes a first winding region, a second winding region, and a third winding region positioned between the first and second winding regions in the axial direction, and
wherein the first and second wires are bifilar-wound in the first and second winding regions and layer-wound in the third winding region.

US Pat. No. 10,193,515

CONTINUOUS TIME LINEAR EQUALIZER WITH TWO ADAPTIVE ZERO FREQUENCY LOCATIONS

INPHI CORPORATION, Santa...

1. A linear equalizer device comprising:a first input transistor comprising a first gate terminal a first drain terminal and a first source terminal, the first gate terminal being configured to receive a first input signal;
a second input transistor comprising a second gate terminal a second drain terminal and a second source terminal, the second gate terminal being configured to receive a second input signal;
a first compensation circuit coupled to the first drain terminal; and
a high-frequency zero circuit comprising at least a pair of source resistors and a pair of source capacitors;
wherein:
the pair of source resistors comprises a first source resistor coupled to the first source terminal and a second source resistor coupled to the first source resistor and the second source terminal, a first terminal being positioned between the first source resistor and the second source resistor;
the pair of source capacitors comprises a first source capacitor coupled to the first source terminal and a second source capacitor coupled to the second source terminal, a second terminal being positioned between the first source capacitor and the second source capacitor and coupled to the first terminal.

US Pat. No. 10,193,514

SELECTABLE PROGRAMMABLE GAIN OR OPERATIONAL AMPLIFIER

MICROCHIP TECHNOLOGY INCO...

1. A configurable amplifier, comprising:a differential input stage;
a first output block;
a second output block;
a plurality of switches coupled to the differential input stage, the first output block and the second output block;
at least one configuration line controlling a switching position of said plurality of switches;
wherein
when a logic state on said configuration line defines a programmable gain amplifier setting, the plurality of switches are controlled such that the differential input stage and the first output block are coupled together as a programmable gain amplifier and comprises a feedback loop, wherein at least one switch of said plurality of switches changes a feedback resistance of the feedback loop, and
when another logic state of said configuration line defines an operational amplifier setting, the plurality of switches are controlled such that the differential input stage and the second output block are coupled together as an operational amplifier without a feedback loop.

US Pat. No. 10,193,513

OPTICAL AMPLIFIER BASED ON ELECTRO-OPTIC EFFECT FOR ELECTRICAL SIGNALS AND ITS APPLICATION AS SEMICONDUCTOR RADIATION DETECTOR PREAMPLIFIER

1. An electrical signal amplification system comprising:an electrical signal amplifier for amplifying an electrical signal, the electrical signal amplifier having
an electro-optic (EO) medium for receiving the electrical signal, wherein applying the electrical signal to the EO medium causes a change to an effective index of refraction;
a device for measuring a light phase change for measuring the change to the effective index of refraction; and
a photodetector;
wherein the photodetector converts the change to the effective index of refraction into an amplified electrical current output signal.

US Pat. No. 10,193,512

PHASE-SHIFTING POWER DIVIDER/COMBINER ASSEMBLIES AND SYSTEMS

Werlatone, Inc., Brewste...

1. A power divider/combiner assembly comprising:a divider network for dividing a received divider-network input signal into N divider-network output signals, where N is an integer greater than seven, the divider network including at least one divider and at least one of each of first, second, and third divider phase-shift circuits, each divider having a divider input and a plurality of divider outputs and being configured to divide a divider input signal on the divider input into a divider output signal on each of the plurality of divider outputs, each divider phase-shift circuit being configured to produce a respective non-zero phase shift between divider output signals on an associated pair of divider outputs of an associated divider of the at least one divider, each first divider phase-shift circuit producing a first phase shift, each second divider phase-shift circuit producing a second phase shift that is more than the first phase shift, and each third divider phase-shift circuit producing a third phase shift that is more than the second phase shift;
N amplifiers, each amplifier amplifying one of the N divider-network output signals into a respective amplified signal; and
a combiner network for combining the N amplified signals into a combiner-network output signal, the combiner network including at least one combiner and at least one of each of first, second, and third combiner phase-shift circuits, with each combiner having a plurality of combiner inputs and a combiner output and being configured to combine combiner input signals on the plurality of combiner inputs into a combiner output signal on the combiner output, each combiner phase-shift circuit being configured to produce a respective non-zero phase shift between combiner input signals on an associated pair of combiner inputs of an associated combiner of the at least one combiner, each first combiner phase-shift circuit producing the first phase shift, each second combiner phase-shift circuit producing the second phase shift, and each third combiner phase-shift circuit producing the third phase shift.

US Pat. No. 10,193,511

MONOLITHIC MICROWAVE INTEGRATED CIRCUIT HAVING AN OVERLAY TRANSFORMER AND LOW IMPEDANCE TRANSMISSION LINES

BAE Systems Information a...

1. A monolithic microwave integrated circuit (MMIC) power amplifier comprising:a substrate;
an input port supported by the substrate and an output port supported by the substrate, wherein the input port is indirectly electrically coupled to the output port; a first overlay transformer supported by the substrate and electrically intermediate the input port and the output port for transforming impedance from a higher input impedance to a lower output impedance; and
a first artificial low impedance transmission line supported by the substrate that is electrically intermediate the input port and the output port, and in electrical communication with the first overlay transformer, wherein the first artificial low impedance transmission line is coupled with at least one shunt capacitor and at least one high impedance transmission line configured as an inductor to provide artificial low impedance to electrical signals flowing through the first low impedance transmission line from the input port to the output port.

US Pat. No. 10,193,508

MULTI-BRANCH OUTPHASING SYSTEM AND METHOD

TEXAS INSTRUMENTS INCORPO...

1. A multi-level, multi-branch outphasing amplifier comprising:a first branch group circuit including:
a first branch circuit including a first activation circuit and a first power amplifier, the first activation circuit coupled to receive an RF first input signal and a first control signal, the first activation circuit configured to selectively enable and disable the RF first input signal from being transmitted to the first power amplifier responsive to the first control signal; and
a second branch circuit including a second activation circuit an a second power amplifier, the second activation circuit coupled to receive the RF first input signal and a second control signal, the second activation circuit configured to selectively enable and disable the RF first input signal from being transmitted to the second power amplifier responsive to the second control signal;
a second branch group circuit including:
a third branch circuit including a third activation circuit and a third power amplifier, the third activation circuit coupled to receive an RF second input signal and a third control signal, the third activation circuit configured to selectively enable and disable the RF second input signal from being transmitted to the third power amplifier responsive to the third control signal;
a fourth branch circuit including a fourth activation circuit and a fourth power amplifier, the fourth activation circuit coupled to receive the RF second input signal and a fourth control signal, the fourth activation circuit configured to selectively enable and disable the RF second input signal from being transmitted to the fourth power amplifier responsive to the fourth control signal; and
combiner circuitry for combining output signals of the first, second, third and fourth power amplifiers and producing an output signal across a load;
wherein a single constant-value voltage supply supplies power to the first branch group circuit and to the second branch group circuit, and
wherein a number of enabled RF input signals in the first branch group circuit and a number of enabled RF input signals in the second branch group circuit is selected to be the same or different depending on a power demand of the load or on a backoff load current.

US Pat. No. 10,193,507

CURRENT SWITCHING CIRCUIT

Analog Devices Global, H...

1. A current switching circuit with current boosting for operation across a wider range of frequencies, the current switching circuit comprising:a differential current switching circuit comprising:
a first transistor configured to receive a switching signal and to provide an output current to an output node;
a second transistor configured to receive an inverted switching signal, the first transistor and the second transistor coupled to each other at a tail node; and
a first current source configured to provide an input current to the tail node; and
a third transistor coupled to the tail node, wherein the third transistor is configured to provide a boost current from a second current source to the tail node while the first transistor is off.

US Pat. No. 10,193,504

SOLDER BUMP PLACEMENT FOR THERMAL MANAGEMENT IN FLIP CHIP AMPLIFIERS

SKYWORKS SOLUTIONS, INC.,...

1. An amplifier comprising:a transistor array formed over a silicon substrate;
a plurality of first resistors formed over the silicon substrate, a first end of a resistor of the plurality of first resistors in communication with an emitter of a transistor of the transistor array; and
a metal pillar formed over the silicon substrate, a footprint defined by a periphery of the metal pillar being adjacent to a footprint defined by a periphery of the transistor array, the footprint defined by the periphery of the metal pillar overlapping a footprint defined by a periphery of the plurality of first resistors, a second end of the resistor of the plurality of first resistors in communication with the metal pillar, the silicon substrate, the metal pillar, the plurality of first resistors, and the transistor array being arranged with respect to each other such that heat generated during operation of the transistor is transferred through the silicon substrate to the metal pillar.

US Pat. No. 10,193,501

DISTRIBUTED POLE-ZERO COMPENSATION FOR AN AMPLIFIER

TEXAS INSTRUMENTS INCORPO...

1. An amplifier comprising:an amplifier input and an amplifier output;
a first amplification stage having an input and an output, the input of the first amplification stage being coupled to the amplifier input;
a second amplification stage having an input and an output, the input of the second amplification stage being coupled to the output of the first amplification stage;
a third amplification stage having an input and an output, the input of the third amplification stage being coupled to the output of the second amplification stage and the output of the third amplification stage being coupled to the amplifier output;
a first feedback capacitor coupled between the amplifier output and at least one of: the input of the second amplification stage and the input of the third amplification stage; and
a compensation network coupled to the amplifier output, the compensation network comprising at least one RC network, wherein the at least one RC network is a plurality of RC networks providing staggered at least one half pole roll off with approximately a forty five degree phase margin per RC network.

US Pat. No. 10,193,498

METHOD AND SYSTEM FOR BOOSTING THE SUPPLY OF POWER AMPLIFIER

1. A system for boosting the power supply of a RF power amplifier in high peak to average power ratio applications, wherein the power amplifier is coupled to receive and amplify a digital data stream of a baseband signal, which is supplied as an RF input signal to the power amplifier to generate an RF output signal, the system comprising:a. a first circuit for controlling a boost event in open-loop with the digital data stream, wherein a timing of the boost event can be adjusted according to delays in the digital data stream; and
b. a second circuit for adjusting the timing of the boost event in such a way that the signal which controls the second circuit is a result of a comparison between a digital representation of the RF input signal and/or a digital representation of the power supply, and the digital baseband signal, wherein the comparison represents a substantial matching of the delays in the paths of the RF input signal and the power supply; and
wherein the boost event is delivered through a plurality of capacitors configured as a charge-pump, and a shape of the boost is generated by capacitive coupling from a single DC voltage.

US Pat. No. 10,193,497

ENHANCED BROADBAND OPERATION OF AN ACTIVE MIXER

QUALCOMM Incorporated, S...

1. An apparatus for wireless communication, comprising:an active mixer configured to convert between radio frequency signals and intermediate frequency signals based at least in part on an alternating current local oscillator signal, wherein a direct current generated within the active mixer is dependent in part on a bias voltage and the alternating current local oscillator signal; and
a mixer biasing circuit configured to generate the bias voltage for the active mixer, a magnitude of the bias voltage depending at least in part on an amplitude of the alternating current local oscillator signal, the mixer biasing circuit comprising a feedback loop configured to inversely control the magnitude of the bias voltage with respect to the amplitude of the alternating current local oscillator signal.

US Pat. No. 10,193,496

PHOTOVOLTAIC COMBINER BOX MONITORING SYSTEM

BOE TECHNOLOGY GROUP CO.,...

1. A photovoltaic combiner box monitoring system, comprising a current sampling circuit, a microprocessor and a communication circuit, whereinthe current sampling circuit is connected with the microprocessor, and configured to sample at least one channel of current signals and input the sampled currents to the microprocessor, the current sampling circuit comprises at least one sampling branch, and each sampling branch comprises a connector and a line selector; the connector is connected with the line selector, and configured to sample a plurality of channels of current signals and input each channel of current signals to one of current input ports of the line selector by means of a port of the connector; and the line selector is connected with the microprocessor, and configured to output current signals that are inputted to respective current input ports of the line selector to the microprocessor in time division manner according to control signals output from the microprocessor; and
the microprocessor is connected with the communication circuit, and configured to send the current signals sampled by the current sampling circuit via the communication circuit.

US Pat. No. 10,193,494

VEHICLE GLASS ROOF SYSTEMS

FORD GLOBAL TECHNOLOGIES,...

1. A glass roof system, comprising:a first glass layer;
a second glass layer;
a photovoltaic module;
a switching film powered by the photovoltaic module, wherein the switching film is positioned between the first glass layer and the second glass layer and is positioned axially between a first solar cell and a second solar cell of the photovoltaic module; and
a control module configured to selectively control the switching film based on a passenger cabin temperature.

US Pat. No. 10,193,493

MULTI-SURFACE SOLAR CELL PACKAGING FOR SELF-POWERED ELECTRONIC DEVICES

Intel Corporation, Santa...

20. A method, comprising:collecting solar energy from a first solar cell mounted on a bendable substrate over a first surface of an electronic device, the bendable substrate to physically mount to the first surface;
collecting solar energy from a second solar cell mounted on the bendable substrate over a second surface of the electronic device, the bendable substrate to physically mount to the second surface; and
transferring the solar energy from the first and second solar cells via the bendable substrate to an electrical contact of the first surface of the electronic device, wherein the second surface of the electronic device lacks an electrical contact.

US Pat. No. 10,193,491

ROOFTOP HEAT REFLECTOR SYSTEM

1. A reflector system for reflecting solar radiation away from a roof, said system comprising:a plurality of brackets, wherein each of said plurality of brackets has a first end, a second end, and a first length that extends between said first end and said second end, wherein said second end of each of said plurality of brackets contacts said roof causing said first end of each of said plurality of brackets to extend away from said roof by said first length;
a plurality of flags, wherein each of said plurality of flags has a base, a second length, and exterior surfaces along said second length that are reflective to solar radiation, wherein said second length of each of said plurality of flags is longer than said first length of each of said plurality of brackets;
a common ribbon having a top edge and a bottom edge, wherein said base of each of said plurality of flags are coupled to said ribbon so that said second length of each of said plurality of flags hang away from said bottom edge of said ribbon;
wherein said ribbon attaches to said first end of each of said plurality of brackets therein supporting said ribbon away from said roof, wherein said plurality of flags hang from said ribbon and are suspended between said ribbon and said roof.

US Pat. No. 10,193,490

MOTOR DRIVE DEVICE

NTN CORPORATION, Osaka (...

1. A motor drive device comprising:an electric motor;
a speed reducer configured to reduce a speed of rotation of the electric motor and transmit so reduced rotation to a wheel;
a lubricating oil supply mechanism configured to supply a lubricating oil to the speed reducer; and
a control device configured to control the electric motor, wherein
a lubricating oil temperature sensor configured to detect a temperature of the lubricating oil is provided in a lubricating oil passage in the speed reducer, a coil temperature sensor configured to detect a temperature of a motor coil is provided in a stator of the electric motor, and a rotation speed detection sensor configured to detect a rotation speed of the electric motor is provided, and
the control device includes
an abnormality detector configured to detect an abnormality in the lubricating oil temperature sensor, and
a lubricating oil temperature estimator configured to estimate the temperature of the lubricating oil on the basis of a determined relationship using the temperature detected by the coil temperature sensor and the rotation speed detected by the rotation speed detection sensor, when the abnormality detector detects the abnormality in the lubricating oil temperature sensor.

US Pat. No. 10,193,489

METHOD AND APPARATUS FOR ACOUSTIC SIGNAL GENERATION

GM Global Technology Oper...

1. A motor drive system for controlling operation of a multi-phase electric machine, comprising:an inverter including a plurality of paired power transistors that are electrically connected to the electric machine, wherein the inverter is electrically connected to a DC power source via a high-voltage electrical power bus; and
a motor controller including a first controller and an acoustic signal generator, wherein the first controller is disposed to control the paired power transistors of the inverter to effect operation of the multi-phase electric machine;
wherein the first controller is disposed to determine an initial output voltage based upon a torque command;
wherein the acoustic signal generator is disposed to generate a sound injection voltage, including a sound pattern generator that is disposed to generate an instantaneous audio signal and a rotational transformation element that is disposed to generate the sound injection voltage based upon the instantaneous audio signal, and wherein the instantaneous audio signal is adjusted by a first gain factor associated with a torque-based gain derating and a second gain factor associated with a speed-based gain derating;
wherein the motor controller is disposed to combine the initial output voltage and the sound injection voltage; and
wherein the motor controller is disposed to generate commands to control the paired power transistors of the inverter, wherein the commands are determined based upon the initial output voltage and the sound injection voltage.

US Pat. No. 10,193,486

PARALLELED MULTIPHASE INVERTER CONTROL FOR ELECTRIC MACHINE

APPLE INC., Cupertino, C...

1. A method, comprising:controlling a first inverter and a second inverter, the first inverter having a first plurality of switch pairs and the second inverter having a second plurality of switch pairs, wherein the first plurality of switch pairs and the second plurality of switch pairs are operated in a pulse width modulation sequence to produce a plurality of outputs;
pairing output of each switch pair of the first inverter with output of a respective switch pair of the second inverter to produce a plurality of paired outputs that are each associated with one phase to supply multiphase power;
measuring current for the switch pairs of each paired output using a current sensor shared by the switch pairs of the respective paired output; and
controlling operation of switches for each paired output to be about 180 degrees out of phase and with equal duty cycle based on the measured current for each paired output.

US Pat. No. 10,193,485

METHOD AND APPARATUS FOR CONTROL OF SWITCHED RELUCTANCE MOTORS

1. A short pitched switched reluctance motor control apparatus for controlling current in a first phase winding and a second phase winding of a short pitched switched reluctance motor, wherein the apparatus comprises:a first voltage provider configured to be coupled to the first phase winding and operable to selectively apply voltage to the first phase winding to drive current in the first phase winding in a first direction and in a second direction opposite to the first direction;
a second voltage provider configured to be coupled to the second phase winding and operable to selectively apply voltage to the second phase winding to drive current in the second phase winding in a first direction and in a second direction opposite to the first direction; and
a controller configured to control the first voltage provider and the second voltage provider to control the timing of the currents in the first phase winding and the second phase winding to drive the motor.

US Pat. No. 10,193,484

CONTROLLED MOTION SYSTEM

Rockwell Automation, Inc....

1. A controlled motion system comprising:a first track section;
a second track section;
a plurality of movers movable along the first and second track sections; and
a control system coupled to the first and second track sections, and configured to control movement of the plurality of movers together and not independently on the first track section and independently on the second track section;
wherein the first and second track sections comprise a plurality of linear motor circuits configured to drive movement of the movers under the control of the control system.

US Pat. No. 10,193,483

METHOD AND DEVICE FOR THE CYCLIC DIGITAL TRANSMISSION OF A POSITION VALUE OF A MOVING OBJECT WITH INERTIAL MASS

1. A method for closed-loop control of a drive, comprising:recurrently detecting a position value over time; and
transmitting associated information to a control device;
wherein the position value includes at least two values, including a partial-angle value, a fine-angle value, and/or digital values, a first value being denotable with a whole number, and a position-value range being assigned to each number, each position range including a first value being assigned mutually separate sub-ranges of the position range, each of these sub-ranges including a second value denotable as a whole number, the second value being transmitted prior in time to the first value;
wherein:
(i) after a newly detected second value has been transmitted, a model value is determined for the first value from the newly detected and a previously transmitted second value, and the position value determined is used by a control device to determine an updated value of a manipulated variable of the control device; and
(ii) after the newly detected second value has been transmitted, the newly detected first value is transmitted, and the model value determined is compared to the newly detected first value, and an action is carried out if they do not agree,
wherein the action includes communication and/or display of warning information, bringing the drive to rest, and/or transferring the drive into a safe state;
wherein the manipulated variable includes a voltage space vector and/or a stator-voltage space vector of an electric motor of the drive.

US Pat. No. 10,193,482

METHOD FOR REDUCING THE NOISE OF AN ELECTRIC MOTOR

1. A method for reducing noise of a motor fed by a converter, said method comprising:changing a magnetic flux in the motor for reducing a fundamental oscillation and a harmonic oscillation of the magnetic flux; and
changing a duty cycle and/or a pulse frequency of the converter so as to change a harmonic oscillation of the magnetic flux, wherein the magnetic flux in the motor is changed as a function of a load torque on the motor.

US Pat. No. 10,193,481

WIND TURBINE PROVIDING GRID SUPPORT

1. A wind turbine for connection to an electrical grid, the wind turbine comprising:a rotor with blades coupled to an electrical generator; and
a controller configured to:
increase, in response to an event, an electrical output power from the wind turbine for a duration of an overproduction period using kinetic energy stored in the rotor thereby decreasing a rotational speed of the rotor, wherein the event indicates a need to increase the electrical output power from the wind turbine to the electrical grid to support the stability of the electrical grid, and
after increasing the electrical output power and before the rotational speed of the rotor reaches a predetermined minimum value, accelerate the rotor for a duration of a recovery period to a previous rotational speed while outputting at least a predetermined minimum electrical power to the electrical grid, wherein the controller is configured to control the wind turbine such that the predetermined minimum electrical power output to the electrical grid during the recovery period is at least 80% of an electrical operating power which was supplied to the electrical grid during a normal operation period prior to the overproduction period.

US Pat. No. 10,193,480

PROPORTIONAL INTEGRAL REGULATING LOOP FOR DIGITAL REGULATOR DEVICE FOR MOTOR VEHICLE EXCITATION ROTARY ELECTRICAL MACHINE

Valeo Equipements Electri...

1. A proportional integral regulating loop (10) for a digital regulator device (2) for a motor vehicle excitation rotary electrical machine (1) configured to function as a generator which provides an output voltage (Ub+) adjusted by an excitation current (Ie), said digital regulator device (2) comprising a control device (11) for controlling said excitation current (Ie) and said regulating loop (10), said regulating loop (10) comprising:at an input, a measuring device (35) for measurement by sampling of said output voltage (Ub+) generating a measurement signal (Um);
an error calculation system (13) generating an error signal (e) equal to a difference between said measurement signal (Um) and a set point (U0);
a processing system (14, 15, 16, 17, 18, 20) for processing of said error signal (e) generating a regulating signal (Ysat), said processing system comprising in parallel a first amplifier (14), an integrator (15) and an anti-saturation system (23); and
at an output, a generation system (38) for generation of a control signal (PWM) controlling said control device (11) according to said regulating signal (Ysat),
said anti-saturation system (23) comprising a saturation detector (24) generating a disconnection signal (Cmd) controlling a switch (25) which disconnects said integrator (15, 29) of said error calculation system (13) in the case of detection of a state of saturation (SM) of said regulating signal (Ysat).

US Pat. No. 10,193,479

DEVICE FOR CONTROLLING A REGULATOR OF A MOTOR VEHICLE ALTERNATOR, AND ALTERNATOR COMPRISING THE CORRESPONDING REGULATOR

Valeo Equipements Electri...

1. Device (1, 2) for controlling a regulator of a motor vehicle alternator, of the type comprising firstly a control circuit (1) which generates a command (KEY_ON) for activation of said regulator, by taking to a first voltage higher than a predetermined high reference voltage a single-wire two-way communication line (6) which is connected to, secondly, a circuit (2) for detection of a state (KEY_DETECT) of said activation command (KEY_ON), said detection circuit (2) comprising means (7, 9) for generation of a fault signal from a flag (LAMP_ON) which indicates a fault of said alternator, by connection of said communication line (6) to a ground by at least one semiconductor switching element (7), by this means taking said communication line (6) to a second voltage lower than a predetermined fault voltage lower than said high reference voltage, and said control circuit (1) comprising means (4) for detection of said fault signal, wherein said control circuit (1) also transmits a pulse width modulated set signal with a maximum which is higher than said high reference voltage, and a minimum which is lower than a predetermined low reference voltage higher than said fault voltage, a duty cycle of said set signal being representative of a set voltage (V0) of said regulator.

US Pat. No. 10,193,475

SENSORLESS CONTROL OF SWITCHED RELUCTANCE MACHINES FOR LOW SPEEDS AND STANDSTILL

Caterpillar Inc., Deerfi...

1. A method for determining rotor position of a sensorless control of a switched reluctance (SR) machine having a rotor and a stator at standstill or low speed, comprising:injecting a test pulse into one or more idle phases of the SR machine;
determining a decoupled flux value based at least partially on a total flux value corresponding to the test pulse and a mutual flux value; and
determining the rotor position based at least partially on the decoupled flux value, wherein the test pulse being injected is based at least partially on a measured phase current and rotor position feedback.

US Pat. No. 10,193,473

ACTUATOR

Canon Kabushiki Kaisha, ...

1. An actuator comprising:a vibrator including a vibration plate and a piezoelectric device that generates a vibration in the vibration plate; and
a holding member that holds the vibration plate,
wherein the vibration plate includes a center portion and a fixing portion connected to the center portion, the center portion configured to have a first surface on a first side on which the piezoelectric device is fixed and a contact portion for contacting a friction member on a second side opposite to the first side so that the vibration by the piezoelectric device causes relative movement between the friction member and the vibration plate,
wherein the first surface is a polished surface, and
wherein the holding member holds the fixing portion at a location between a first plane including the first surface of the center portion and a second plane including the contact portion of the center portion.

US Pat. No. 10,193,472

SINGLE FRICTION SURFACE TRIBOELECTRIC MICROGENERATOR AND METHOD OF MANUFACTURING THE SAME

PEKING UNIVERSITY, Beiji...

1. A single friction surface microgenerator, comprising an insulating substrate having an upper surface and a lower surface, with a surface-friction-structured layer on the upper surface and a first induction electrode and a second induction electrode on the lower surface; wherein the first induction electrode is located to correspond to the surface-friction-structured layer that is used as a friction surface while the second induction electrode is located peripherially of the first induction electrode and insulatedly spaced from the first induction electrode, the second induction electrode surrounds the first induction electrode in a ring shape, and the surface-friction-structured layer has a number of micro/nano array structures or is a smooth surface.

US Pat. No. 10,193,459

HIGH STATIC GAIN BI-DIRECTIONAL DC-DC RESONANT CONVERTER

Huawei Technologies Co., ...

1. A bi-directional DC-DC converter comprising:a first terminal circuit;
a second terminal circuit;
a transformer circuit;
a first high voltage side coupled to the first terminal circuit, wherein the first high voltage side comprises a resonant tank circuit coupled between a first bridge circuit of the first high voltage side and a high voltage side of the transformer circuit, wherein the resonant tank circuit comprises:
a) a first branch comprising a first capacitor Cr1 and a first inductor Lr1 coupled in series;
b) a second branch comprising a second inductor Lr2 and a second capacitor Cr2 coupled in series; and
c) a third branch comprising a third capacitor Cr3 and a third inductor Lr3 coupled in series;
wherein the first, second and third branches are coupled to a common node, the second branch is coupled between the common node and a first terminal of the high voltage side of the transformer circuit and the third branch is coupled between the common node and a second terminal of the high voltage side of the transformer circuit; and
a second low voltage side coupled to the second terminal circuit, wherein the first high voltage side and the second low voltage side are coupled to each other via the transformer circuit.

US Pat. No. 10,193,455

RESONANT CAPACITOR STABILIZER IN RESONANT CONVERTERS

Semiconductor Components ...

1. A resonant converter for resonant capacitance stabilization during start-up, the resonant converter comprising:an oscillator configured to generate a first clock signal to drive a first driver for a first power switch, and a second clock signal to drive a second driver for a second power switch during switching operations; and
a resonant capacitor stabilizer configured to control the second driver to periodically activate the second power switch to discharge a resonant capacitor of a resonant network during initialization of the switching operations of the resonant converter,
the resonant capacitor stabilizer configured to activate the second power switch for a first duration and activate the second power switch for a second duration such that the second power switch is deactivated during a period of time between the first duration and the second duration.

US Pat. No. 10,193,453

HIGH SIDE SIGNAL INTERFACE IN A POWER CONVERTER

Power Integrations, Inc.,...

1. A controller for use in a power converter, the controller comprising:a high side signal interface circuit coupled to generate a drive signal in response to an ON signal and an OFF signal generated by a control circuit of the controller to control switching of a high side switch coupled to a half bridge node of the power converter, wherein the high side signal interface circuit comprises:
a common mode cancellation circuit coupled to receive the ON signal and the OFF signal, wherein the common mode cancellation circuit is coupled to generate a fourth current signal representative of the OFF signal referenced to a bypass voltage during an initial state, wherein the common mode cancellation circuit is coupled to generate a first current signal in response to the ON signal being pulled to a lower value relative to the OFF signal to turn ON the high side switch, and wherein the common mode cancellation circuit is coupled to generate a common mode rejection signal in response to the first current signal and the fourth current signal; and
a first current hysteresis comparator coupled to receive the first current signal, the fourth current signal, the common mode rejection signal, and a drive signal, wherein the first current hysteresis comparator is coupled to generate a first output signal in response to the first current signal, the fourth current signal, the common mode rejection signal, and the drive signal, wherein the drive signal is coupled to be generated in response to the first output signal in a presence of a common mode voltage caused by slewing at the half bridge node.

US Pat. No. 10,193,448

METHOD OF FORMING A POWER SUPPLY CONTROL CIRCUIT AND STRUCTURE THEREFOR

SEMICONDUCTOR COMPONENTS ...

1. A circuit for a power supply control system comprising:a control circuit configured to operate a power switch at a frequency having a period to control a current through an inductor and through the power switch to provide an output voltage to a load wherein the control circuit operates the power switch at a frequency having a period;
a first switch having a first terminal, a second terminal, and a control terminal, the first terminal of the first switch configured to be coupled to a first terminal of the inductor and to a first terminal of a boost capacitor, the second terminal of the first switch configured to be coupled to a first terminal of a power source;
a second switch having a first terminal, a second terminal, and a control terminal, the first terminal of the second switch configured to be coupled to a second terminal of the boost capacitor, the second terminal of the second switch configured to be coupled to a second terminal of the power source, wherein the control circuit operates the first and second switches at the frequency and enables the first and second switches for substantially a first portion of the period; and
a third switch having a first terminal, a second terminal, and a control terminal, the first terminal of the third switch coupled to the first terminal of the second switch, the second terminal of the third switch coupled to the first terminal of the first switch, wherein the control circuit operates the third switch at the frequency and operates the third switch with a substantially opposite phase to the first switch.

US Pat. No. 10,193,447

DC TOPOLOGY CIRCUIT WORKABLE WITH VARIOUS LOADS THROUGH INCLUSION OF SUBTRACTOR

SHENZHEN CHINA STAR OPTOE...

1. A DC topology circuit, comprising a control chip, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first inductor, a first capacitor, and a second capacitor;the control chip comprises a control module and a subtractor; a first input terminal of the subtractor is inputted with an input voltage, a second input terminal of the subtractor is connected with a load-rated voltage and an output terminal of the subtractor is electrically connected with the control module;
a gate electrode of the first field effect transistor is inputted with a first control signal, a drain electrode of the first field effect transistor is connected with the input voltage, and a source electrode of the first field effect transistor is electrically connected to one terminal of the first inductor; a gate electrode of the second field effect transistor is inputted with a second control signal, a drain electrode of the second field effect transistor is connected the terminal of the first inductor, and a source electrode of the second field effect transistor is grounded; a gate electrode of the third field effect transistor is inputted with a third control signal, a drain electrode of the third field effect transistor is electrically connected to one other terminal of the first inductor, and the source electrode of the third field effect transistor is grounded; a gate electrode of the fourth field effect transistor is inputted with a fourth control signal, the drain electrode of the fourth field effect transistor outputs a output voltage, and the source electrode of the fourth field effect transistor is electrically connected with the other terminal of the first inductor; one terminal of the first capacitor is electrically connected with the terminal of the first inductor and one other terminal of the first capacitor is electrically connected to a first bootstrap pin of the control chip; one terminal of the second capacitor is electrically connected to the other terminal of the first inductor and one other terminal of the second capacitor is electrically connected with a second bootstrap pin of the control chip;
the first control signal, the second control signal, the third control signal, and the fourth control signal are all provided by the control module;
wherein the subtractor subtracts the input voltage and the load-rated voltage and outputs an operation result to the control module; the control module adjusts the first control signal, the second control signal, the third control signal, and the fourth control signal, to correspondingly control on/off of the first field effect transistor, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor.

US Pat. No. 10,193,440

SWITCH NETWORK OF A MULTILEVEL POWER CONVERTER ARCHITECTURE

WISCONSIN ALUMNI RESEARCH...

1. A power converter comprising:a capacitive divider including a first end providing a first converter terminal and a second end providing a second converter terminal attachable to a ground reference, the capacitive divider further including a plurality of capacitors connected in series between the first end and the second end;
a multilevel switch network including a plurality of levels, each level including at least one level switch, wherein each level switch comprises
a switch terminal;
two throw terminals;
a single-pole, double-throw switch (SPDT) having a pole and two throws, wherein each throw of the two throws is connected to a respective throw terminal of the two throw terminals, wherein the pole is electrically controllable to move between the two throws;
an inductor connected between the pole and the switch terminal; and
a capacitor connected between the two throw terminals;
wherein a number of level switches in successive levels of the plurality of levels decreases from a first level to a last level,
wherein the last level has a single level switch, wherein the switch terminal of the single level switch provides a third converter terminal and the two throw terminals of the single level switch are each connected to the switch terminal of the level switch of a previous level relative to the last level,
wherein each level switch of the first level is connected across a different capacitor of the capacitive divider to provide a switchable connection between the pole of a respective SPDT switch and each side of a respective different capacitor,
wherein each level switch of each remaining level includes a throw terminal of the two throw terminals connected to the switch terminal of a different level switch of the previous level relative to a current level;
and
at least one switch signal generator controlling a switching of the SPDT switches of the multilevel switch network to provide a power transformation between the first converter terminal and the third converter terminal.

US Pat. No. 10,193,439

POWER FACTOR CORRECTION CIRCUIT, CONTROL METHOD AND CONTROLLER

Silergy Semiconductor Tec...

1. A power factor correction circuit, comprising:a) a power meter configured to measure total harmonic distortion (THD) at an input port;
b) a switching-type regulator that is controllable by a switching control signal in order to adjust a power factor of an input signal thereof; and
c) a controller configured to generate said switching control signal to control said switching-type regulator to perform power factor correction, wherein said controller minimizes said THD by adjusting a current reference signal according to a measured THD, and said current reference signal represents an expected inductor current of said switching-type regulator.

US Pat. No. 10,193,437

BRIDGELESS AC-DC CONVERTER WITH POWER FACTOR CORRECTION AND METHOD THEREFOR

SEMICONDUCTOR COMPONENTS ...

1. A bridgeless AC-DC converter, comprising:a totem pole network having a first input adapted to be coupled to a second terminal of an AC voltage source, a second input adapted to be coupled to a first terminal of said AC voltage source through an inductor, an output terminal for providing an output voltage, and a return terminal;
an output capacitor having a first terminal coupled to said output terminal, and a second terminal coupled to a bulk ground terminal;
a sense element coupled between said return terminal and said bulk ground terminal; and
a controller circuit coupled to said return terminal of said totem pole network, wherein said controller circuit modulates an on time of an active switch in said totem pole network on a cycle-by-cycle basis by shortening said on time corresponding to an amount of time a current sense signal derived from a current through said sense element exceeds a current limit threshold.

US Pat. No. 10,193,435

START-UP CIRCUIT TO DISCHARGE EMI FILTER FOR POWER SAVING OF POWER SUPPLIES

SEMICONDUCTOR COMPONENTS ...

1. A discharge circuit for an EMI filter having an X-capacitor, comprising:a monitor circuit configured to be coupled to the EMI filter to receive a rectified signal having a waveform that is correlated to a waveform of a power source that is filtered by the EMI filter;
a high voltage switch transistor configured to receive the rectified signal and form a sample signal having a waveform that that is correlated to the rectified signal, the high voltage switch transistor configured to charge a supply voltage;
when the power source is shut down over a period of time, a discharging path is provided to conduct a discharge current from the EMI filter through the high voltage switch transistor for discharging a stored voltage of the X-capacitor, wherein the discharging path is cut off when the power source is in an active state.

US Pat. No. 10,193,433

RAILWAY VEHICLE CONTROL APPARATUS

MITSUBISHI ELECTRIC CORPO...

1. A railway vehicle control apparatus comprising:a first power conversion device comprising a primary circuit and a secondary circuit, each including a switching element, each to operate as a power conversion circuit when the switching element is activated, and each to operate as a rectifier circuit when the switching element is deactivated, the first power conversion device performing bidirectional power conversions between a primary side and a secondary side; and
a controller to perform control to deactivate, when one of either the switching element of the primary circuit or the switching element of the secondary circuit is activated, the other switching element;
wherein, while an alternating current generator is stopped that is disposed on the primary side of the first power conversion device and driven by an internal combustion engine to output alternating current power, the controller activates the switching element of the secondary circuit and deactivates the switching element of the primary circuit such that the first power conversion device converts electric power input from the secondary side to supply electric power for causing the alternating current generator to operate; and
wherein, during operation of the alternating current generator, the controller activates the switching element of the primary circuit and deactivates the switching element of the secondary circuit such that the first power conversion device converts electric power supplied from the alternating current generator to output the converted electric power to the secondary side;
the railway vehicle control apparatus further comprising:
a second power conversion device, a primary side thereof being connected to the alternating current generator, to perform bidirectional power conversions between the primary side and a secondary side;
a smoothing capacitor connected to secondary side terminals of the second power conversion device and connected to terminals of the primary side of the first power conversion device; and
an inverter connected in parallel with the smoothing capacitor between the secondary side terminals of the second power conversion device;
wherein the controller further controls the second power conversion device;
wherein, while the alternating current generator is stopped: (i) the controller, in response to a start command of the internal combustion engine, activates the switching element of the secondary circuit, and deactivates the switching element of the primary circuit such that the first power conversion device converts electric power stored in an electric power storage device connected to the secondary side terminals of the first power conversion device to charge the smoothing capacitor; (ii) thereafter the controller controls the second power conversion device such that the second power conversion device converts electric power stored in the smoothing capacitor to supply electric power for causing the alternating current generator to operate; (iii) the internal combustion engine is started by a torque output by the alternating current generator to which electric power from the second power conversion device is supplied and (iv) when starting operation of the internal combustion engine is completed, the controller deactivates the switching element of the primary circuit and the switching element of the secondary circuit; and
wherein while the alternating current generator is operated: (i) the controller controls the second power conversion device such that the second power conversion device converts the electric power supplied from the alternating current generator to charge the smoothing capacitor; and (ii) thereafter, when the voltage of the smoothing capacitor is greater than or equal to a threshold and the inverter is in a state of capable of being activated, the controller activates the switching element of the primary circuit and deactivates the switching element of the secondary circuit such that the first power conversion device converts the electric power supplied to the secondary side terminals of the second power conversion device to charge the electric power storage device.

US Pat. No. 10,193,398

WIRELESS POWER TRANSFER AND RECEIVE METHOD, APPARATUS AND SYSTEM

LG ELECTRONICS INC., Seo...

1. A wireless power transmitter for transferring power to a wireless power receiver in a wireless manner, the wireless power transmitter comprising:a power transmission control unit configured to detect the wireless power receiver; and
a power conversion unit configured to transfer the power to the wireless power receiver;
wherein the wireless power transmitter is configured to:
receive at least one of an identification packet or a configuration packet transmitted in a first mode from the wireless power receiver;
determine, based on the configuration packet, whether or not the wireless power receiver supports a second mode different from the first mode; and
communicate with the wireless power receiver in at least one of the first mode or the second mode when the wireless power receiver supports the second mode,
wherein the first mode is used for communication between one wireless power transmitter and one wireless power receiver, and the second mode is used for communication between one wireless power transmitter and a plurality of wireless power receivers, and
wherein the configuration packet comprises operation mode information indicating a communication execution mode supported by the wireless power receiver.

US Pat. No. 10,193,375

CLOSED LOOP CURRENT CONTROL IN A WIRELESS POWER SYSTEM

MediaTek Inc., Hsin-Chu ...

1. A wireless power transmitter, comprising:a first controller configured to set a target coil current value based, at least in part, on a voltage value reported by a wireless power receiver;
an amplifier configured to generate a transmitter coil current based, at least in part, on a supply voltage received by the amplifier; and
a second controller configured to adjust the supply voltage received by the amplifier based, at least in part, on a comparison of a value of the transmitter coil current to the target coil current value.

US Pat. No. 10,193,374

MULTIFUNCTION BATTERY CHARGING AND HAPTIC DEVICE

Intel Corporation, Santa...

1. An electronic device comprising:a processor;
a memory device comprising instructions to be executed by the processor;
a battery to provide electrical power to the processor and the memory device;
a multifunction charger comprising an enclosure, a first conductive winding fixedly disposed on an inner wall of the enclosure, and a magnetic core suspended within the enclosure by a spring; and
control circuitry configured to activate one of a plurality of available operating modes of the multifunction charger, wherein the plurality of operating modes of the multifunction charger comprises a wireless charging mode and a haptic feedback mode, wherein, to activate wireless charging mode, the control circuitry is to conductively couple the first conductive winding to a battery charging circuit.

US Pat. No. 10,193,372

OPERATING AN INDUCTIVE ENERGY TRANSFER SYSTEM

Apple Inc., Cupertino, C...

1. A method for operating an inductive energy transfer system that includes a transmitter device and a receiver device, the receiver device including a touch sensing device, the method comprising:detecting if an input surface of the touch sensing device is touched while the transmitter device is transferring energy inductively to the receiver device; and
if the input surface is touched, the transmitter device transferring energy inductively only during a first time period and the touch sensing device obtaining touch samples only during a different second time period.

US Pat. No. 10,193,363

HYBRID COUPLING FOR A SMART BATTERY SYSTEM

Bren-Tronics, Inc., Comm...

1. A smart battery system comprising:a battery housing containing a first battery, a second battery, and first and second memory locations for storing data about said first and second batteries respectively; and
a single hybrid coupling having a mating jack comprising
(i) a power coupling including two pairs of D.C. battery conductors disposed in a first circular configuration within said mating jack for electrically connecting an external device to said first and second batteries; and
(ii) a data coupling providing two system management buses for communicating data between the external device and said first and second memory locations respectively, wherein said data coupling has two pairs of digital bus conductors disposed in a second circular configuration within said mating jack, wherein said second circular configuration is concentric with said first circular configuration,wherein said power coupling and said data coupling terminate in contacts that are arranged in the jack starting from the 12:00 position and moving clockwise as follows:a first battery conductor of said first pair of D.C. battery conductors;
a first digital bus clock data conductor of said first pair of digital bus conductors;
an additional battery-type conductor;
a first digital bus data conductor of said first pair of digital bus conductors;
a first battery conductor of said second pair of D.C. battery conductors;
an additional data-type conductor;
a second battery conductor of said first pair of D.C. battery conductors;
a second digital bus clock data conductor of said second pair of digital bus conductors;
a second battery conductor of said second pair of D.C. battery conductors; and
a second digital bus data conductor of said second pair of digital bus conductors, andwherein the external device comprises a charger, and further comprising a further battery-type conductor in the center of the jack, and wherein said additional data-type conductor provides a charge enable signal and said further battery-type conductor provides a charge enable return signal.

US Pat. No. 10,193,323

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor switching element having a sense terminal and capable of outputting from the sense terminal a sense current given at a predetermined shunt ratio to a main current;
a sense resistor having one end connected to the sense terminal, having the other end configured to be connected to a ground, and receiving a current from the sense terminal to generate a sense voltage;
a correction voltage generation circuit which generates a correction voltage;
a voltage dividing circuit including a first resistor which receives the sense voltage at its one end and a second resistor which receives at its one end the correction voltage from the correction voltage generation circuit, and whose other end is connected to the other end of the first resistor, the voltage dividing circuit outputting from the point of connection between the first and second resistors a corrected sense voltage obtained by correcting the sense voltage with the correction voltage;
an overcurrent protection circuit to which the corrected sense voltage is input, and which outputs a halt signal when the corrected sense voltage is higher than a threshold voltage;
a drive circuit which stops driving of the semiconductor switching element upon receiving the halt signal from the overcurrent protection circuit; and
a correction voltage switching element which connects the correction voltage generation circuit and the one end of the second resistor,
wherein the correction voltage switching element is turned on from an off state after a lapse of a predetermined time period from a moment at which the semiconductor switching element is turned on, and with the correction voltage switching element turned on, the correction voltage generation circuit is connected to the one end of the second resistor.

US Pat. No. 10,193,321

FILLER ASSEMBLY FOR CABLE GLAND

1. A filler assembly for filling a cable gland with curable liquid material, the assembly comprising:(a) a dispenser apparatus for a curable liquid material, the apparatus comprising:
a body defining at least one first chamber accommodating a first component of a curable liquid material, and at least one second chamber accommodating a second component of said curable liquid material, wherein mixing of said first and second components initiates curing of said curable liquid material; and
at least one dispenser device adapted to dispense said mixed curable liquid material therefrom between a plurality of said cores of said cable; and
(b) at least one flexible barrier member capable of having at least one respective aperture therethrough configured to be adapted to stretch to engage a plurality of cores of a cable while in use to provide a barrier to passage of said curable liquid material along said cores.

US Pat. No. 10,193,301

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device, the method comprising:providing a wafer including a conductive first substrate, a laser element structure on an upper side of the first substrate, and an upper surface electrode on an upper surface of the laser element structure;
bonding the wafer to a second substrate at an upper surface electrode side of the wafer;
removing a portion of the first substrate to reduce a thickness of the wafer;
forming a lower surface electrode on a lower surface of the first substrate at which the removing of the portion of the first substrate has been performed;
singulating the wafer to obtain a laser element; and
mounting the laser element on a submount such that the lower surface electrode faces the submount.

US Pat. No. 10,193,289

PLUG-IN POWER SOURCE ADAPTING SEAT

Rich Brand Industries Lim...

1. A plug-in power source adapting seat composed of a main body, an adapting barrel, a positive pole clip, a negative pole clip and a joining body, wherein:the main body is integrally formed by a cylinder like portion and a disc like portion, the cylinder like portion has a straight-type external surface, the top surface of the cylinder like portion is opened, an inside of the cylinder like portion is disposed with a positive pole clip slot and a negative pole clip slot, an outward appearance of the cylinder like portion is formed with a shield ring at a small distance away from a bottom of the cylinder like portion, the bottom is circularly disposed with a plurality of slots, a circumference wall is disposed with a notch; the disc like portion is formed at the bottom of the cylinder like portion and formed with an expanded area, the bottom of the disc like portion is formed with a set of inserting troughs, the set of inserting troughs inwardly passing through and respectively piercing through the positive pole clip slot and the negative pole clip slot inside the cylinder like portion;
the adapting barrel is formed by a conductive material and has a cylinder shape, a circumference wall of the adapting barrel is formed with a screwing strip as a spiral shape, a bottom of the screwing strip is a vertical wall, the vertical wall is circularly disposed with a plurality of concave bodies, a top surface of the adapting barrel is formed with an opening and is embedded with an insulation body, the insulation body has a joining groove vertically penetrating;
a sheet body of the positive pole clip is formed with an extension and a bending, the positive pole clip obliquely protrudes to form a fasten piece, and a bottom of the positive pole clip is formed into a clamp line end;
a sheet body of the negative pole clip is formed with an extension and a bending, the negative pole clip obliquely protrudes to form a fasten piece, and a bottom of the negative pole clip is formed into a clamp line end; and
the joining body is formed by a conductive material to have a top cover showing an arc shape and a joining lever downwardly stretching, the top cover covers the opening of the adapting barrel, and an external diameter of the joining lever equals an inner diameter of the joining groove;
in assembling, the positive pole clip is downwardly accommodated into the positive pole clip slot from a top opening of the main body so that the clamp line end of the positive pole clip aligns with one of the set of inserting troughs, with the fasten piece of the positive pole clip and the positive pole clip slop achieving fastening and positioning; the negative pole clip is downwardly accommodated into the negative pole clip slot so that the clamp line end of the negative pole clip aligns with another of the set of inserting troughs, the fasten piece of the negative pole clip and the negative pole clip slot achieves fastening and positioning, after positioning the negative pole clip, a top section of the negative pole clip stretches from the notch of the cylinder like portion; the adapting barrel downwardly fits the cylinder like portion to enable the screwing strip of the adapting barrel to exist on the straight-type external surface of the cylinder like portion, the vertical wall is downwardly and vertically disposed from the shield ring of the cylinder like portion, the plurality of concave bodies of the adapting barrel is fastened into a corresponding slot of the cylinder like portion one on one so that the adapting barrel and the cylinder like portion achieve a combination, in the process, the top section of the negative pole clip achieves electric conductance together with the adapting barrel, at the same time, a top section of the positive pole clip enters the joining groove of the insulation body at a top end of the adapting barrel, the joining lever of the joining body pierces through the joining groove of the insulation body from an outside, the joining lever is in contact with the top section of the positive pole clip, the joining lever and the joining groove performing a packing motion, achieve an electric conductance together with the top section of the positive pole clip, and at the same time, the top cover completely covers the opening of the adapting barrel.

US Pat. No. 10,193,283

BUSWAY STAB ASSEMBLIES AND RELATED SYSTEMS AND METHODS

Eaton Intelligent Power L...

1. A plug-in device for use with a busway system comprising a busway housing defining a longitudinal axis, the plug-in device comprising:a stab base housing having first and second opposite sides;
one or more stab conductors extending out of and away from the stab base housing at the first side of the stab base housing;
one or more stab conductors extending out of and away from the stab base housing at the second side of the stab base housing; and
a ground conductor at an upper portion of the stab base housing;
wherein the stab base housing is configured to be received through an opening at a bottom portion of the busway housing and positioned in a first position with each stab conductor extending away from the stab base housing in a direction substantially parallel to the longitudinal axis of the busway housing and with the ground conductor contacting a top wall of the busway housing;
wherein the stab base housing is configured to be rotated from the first position to a second position with each stab conductor extending away from the stab base housing in a direction substantially perpendicular to the longitudinal axis of the busway housing and with the ground conductor contacting the top wall of the busway housing;
wherein:
an enclosure is coupled to a lower portion of the stab base housing;
a cable extends from each stab conductor and from the ground conductor to outside the stab base housing at the lower portion thereof; and
each cable is electrically connected to one or more components in the enclosure.

US Pat. No. 10,193,281

ELECTRICAL CONNECTOR ASSEMBLY HAVING A SHIELD ASSEMBLY

TE CONNECTIVITY CORPORATI...

1. A connector assembly for terminating a cable having a cable shield that is electrically conductive, the connector assembly comprising:a backshell that is electrically conductive comprising a body that extends from a mating end to a cable end along a mating axis of the connector assembly, the backshell configured to provide shielding for an electrical connector configured to be received in the backshell at the mating end, the cable end comprising a cable channel that extends through the body and is configured to hold an end segment of the cable therein;
a shield assembly comprising a clamp system, wherein the clamp system is electrically conductive and held within the cable end of the body of the backshell, the clamp system comprising a front clamping member and a rear clamping member, the cable shield of the cable configured to terminate to the front clamping member and to the rear clamping member of the clamp system between the front clamping member and the rear clamping member; and
an electromagnetic interference (EMI) gasket, wherein the EMI gasket is electrically coupled to the backshell and held within the cable end of the body of the backshell, the EMI gasket comprising a backshell interface and a clamp interface, wherein the backshell interface is configured to engage the backshell and the clamp interface is configured to engage an exterior surface of at least one of the front clamping member or the rear clamping member of the clamp system.