US Pat. No. 10,483,110

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:an n-type oxide semiconductor layer;
a first electrode joined to a first main surface of the n-type oxide semiconductor layer; and
a second electrode provided on the first main surface of the n-type oxide semiconductor layer or on a second main surface that is a surface on a rear side of the first main surface,
wherein current flows between the first electrode and the second electrode via the n-type oxide semiconductor layer provided between the first electrode and the second electrode,
the semiconductor device further comprising:
a p-type oxide semiconductor layer provided adjacent to a junction between the first electrode and the n-type oxide semiconductor layer; and
a nitride layer provided between the p-type oxide semiconductor layer and the n-type oxide semiconductor layer.

US Pat. No. 10,483,109

SELF-ALIGNED SPACER FORMATION

Tokyo Electron Limited, ...

1. A substrate processing method, comprising:forming a sacrificial film over a substrate;
creating a pattern in the sacrificial film;
conformally depositing a first spacer layer over the patterned sacrificial film;
removing horizontal portions of the first spacer layer while substantially leaving vertical portions of the first spacer layer; and
thereafter, performing a gas phase exposure, thereby selectively depositing a second spacer layer on the first spacer layer and not on the patterned sacrificial film, wherein the first spacer layer comprises a metal-containing layer that catalyzes the selective deposition of the second spacer layer on the first spacer layer.

US Pat. No. 10,483,108

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:patterning a middle layer and a bottom layer to expose a spacer material located over a hard mask, wherein prior to the patterning the middle layer and the bottom layer are located on a first side of the spacer layer and a semiconductor substrate is located on a second side of the spacer layer opposite the first side; and
applying an etchant to be in physical contact with both the middle layer and the spacer material, wherein the etchant comprises an inhibitor which inhibits an etch rate of the spacer material.

US Pat. No. 10,483,106

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device including a transistor, the method comprising the steps of:forming an oxide semiconductor layer over an insulating layer;
preforming a first heat treatment on the oxide semiconductor layer under an inert atmosphere at a first temperature equal to or higher than 400° C.;
forming an oxide insulating layer over and in contact with a first part of the oxide semiconductor layer after the first heat treatment; and
performing a second heat treatment heating the oxide insulating layer at a second temperature equal to or higher than 150° C. and lower than 350° C.,
wherein the first part of the oxide semiconductor layer is included in a channel formation region of the transistor.

US Pat. No. 10,483,104

METHOD FOR PRODUCING STACKED ELECTRODE AND METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A method for producing a stacked electrode, comprising:preparing a multi-layered graphene film directly on an insulating substrate;
applying a dispersion liquid of metal nanowires directly onto the multi-layered graphene film;
removing a solvent from the dispersion liquid to prepare a metal wiring on the multi-layered graphene film;
pressing the metal wiring to prepare a metal wiring on the multi-layered graphene filing and to strengthen the connection between the multi-layered graphene film and the metal nanowires;
forming a polymer directly on the multi-layered graphene film and the metal wiring to fill asperities of the metal nanowires, wherein the polymer covers the multi-layered graphene film and the metal wiring to obtain a stacked member including the insulating substrate, the multi-layered graphene film, the metal wire, and the polymer; and
cleaving a side of the stacked member where the multi-layered graphene and the insulating substrate are in direct contact and obtaining the stacked electrode including the multi-layered graphene film, the metal wire, and the polymer.

US Pat. No. 10,483,103

METHOD FOR MANUFACTURING A SEMICONDUCTOR MATERIAL INCLUDING A SEMI-POLAR III-NITRIDE LAYER

CENTRE NATIONAL DE LA REC...

1. Method for manufacturing a semiconductor material including a semi-polar III-nitride layer from a starting substrate including a plurality of grooves periodically spaced apart by a distance L2, each groove including a first inclined flank of crystallographic orientation C (0001) and a second inclined flank of different crystallographic orientation, a first inclined flank of a groove and a second inclined flank of an adjacent groove forming a crenelation having a top overhung by a mask cap,the method comprising the phases consisting in:forming first III-nitride crystals on the first inclined flanks of the grooves, the growth parameters of the first III-nitride crystals being adapted to favor lateral growth of said first III-nitride crystals:
the growth firstly inducing triangular cavities formed between the substrate and two adjacent first III-nitride crystals, a triangular cavity having a base, two walls and a vertex, the base corresponding to the substrate, a wall corresponding to a first III-nitride crystal, another wall corresponding to said adjacent first III-nitride crystal, and the vertex corresponding to a beginning of intersection between said two adjacent first III-nitride crystals, a presence of the mask cap avoiding parasitic growth on the area covered by the mask,
and then inducing an overlapping between adjacent first III-nitride crystals, forming extended cavities situated above the triangular cavities, starting from the vertex of the triangular cavities and in line with the overlapping areas between the first III-nitride crystals in meeting planes between the first III-nitride crystals, at an intersection between two adjacent overlapping first III-nitride crystals;
forming a two-dimensional III-nitride layer on III-nitride crystals formed beforehand.

US Pat. No. 10,483,102

SURFACE MODIFICATION TO IMPROVE AMORPHOUS SILICON GAPFILL

APPLIED MATERIALS, INC., ...

1. A method for manufacturing a semiconductor device, comprising:positioning a substrate in a processing volume of a processing chamber, the substrate having at least one feature formed in a surface of the substrate, wherein the at least one feature is defined by sidewalls and a bottom surface;
pretreating the surface of the substrate, the pretreating comprising:
forming a plasma of a pretreatment gas mixture; and
exposing the surface of the substrate to radicalized species of the pretreatment gas mixture to form an oxynitride-terminated silicon layer or a nitride-terminated silicon layer on the surface of the substrate; and
depositing a flowable silicon film on the pretreated surface of the substrate to fill the at least one feature with flowable silicon film, wherein the flowable silicon film comprises amorphous silicon.

US Pat. No. 10,483,101

GLASS-BASED ARTICLE WITH ENGINEERED STRESS DISTRIBUTION AND METHOD OF MAKING SAME

Corning Incorporated, Co...

1. A glass-based article comprising:a first surface having an edge,
wherein a maximum optical retardation of the first surface is at the edge and the maximum optical retardation is less than or equal to about 40 nm, and
wherein the optical retardation decreases from the edge toward a central region of the first surface, the central region having a boundary defined by a distance from the edge toward a center point of the first surface, wherein the distance is ½ of the shortest distance from the edge to the center point.

US Pat. No. 10,483,098

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A method of manufacturing a display apparatus, the method comprising:preparing a substrate having a display portion on an upper surface of the substrate;
attaching a protection film having an opening to a lower surface of the substrate so that the protection film overlaps the display portion;
attaching a support film to the lower surface so that the support film is disposed within the opening of the protection film, wherein the support film is spaced apart from the protection film before the support film is attached to the lower surface;
attaching a driving circuit chip to the upper surface so that the driving circuit chip is spaced apart from the display portion and the opening;
removing at least a part of the support film; and
bending the substrate along a longitudinal direction of the opening.

US Pat. No. 10,483,097

METHOD FOR CLEANING, PASSIVATION AND FUNCTIONALIZATION OF SI—GE SEMICONDUCTOR SURFACES

The Regents of the Univer...

1. A method for in-situ dry cleaning of a SiGe semiconductor surface, comprising:ex-situ, degreasing the Ge containing semiconductor surface;
ex-situ, removing organic contaminants;
dosing the SiGe surface with HF (aq), or with NH4F (g) generated via NH3+NF3 or via NF3 with H2 or H2O;
in-situ dosing the SiGe surface with atomic H to remove carbon contamination;
in-situ passivating with H2O2 (g); and
in-situ nucleating with trimethylaluminum (TMA).

US Pat. No. 10,483,096

DEVICE AND METHOD FOR ANALYSIS OF BIOFLUIDS BY ION GENERATION USING WETTED POROUS MATERIAL

Indiana University Resear...

1. A mass spectrometry cartridge comprising:a sample holder;
a base;
a solid phase extraction column, wherein the solid phase extraction column is disposed within the sample holder; and
a first absorbent unit, wherein the first absorbent unit is configured for use with a mass spectrometer.

US Pat. No. 10,483,095

METHOD OF EXTRACTING AND ACCELERATING IONS

AGC FLAT GLASS NORTH AMER...

1. A method of extracting and accelerating ions comprising:(i) providing a ion source comprising:
a chamber;
a first hollow cathode having a first hollow cathode cavity and a first plasma exit orifice and a second hollow cathode having a second hollow cathode cavity and a second plasma exit orifice, the first and second hollow cathodes being disposed adjacently in the chamber;
a first ion accelerator between and in communication with the first plasma exit orifice and the chamber, wherein the first ion accelerator forms a first ion acceleration cavity; and
a second ion accelerator between and in communication with the second plasma orifice and the chamber, wherein the second ion accelerator forms a second ion acceleration cavity;
wherein a width of the first ion acceleration cavity is larger than a width of the first plasma exit orifice, and a width of the second ion acceleration cavity is larger than a width of the second plasma exit orifice;
(ii) generating a plasma within the first hollow cathode and the second hollow cathode, wherein the first hollow cathode and the second hollow cathode are configured to alternatively function as electrode and counter-electrode; and
(iii) extracting and accelerating ions from the first hollow cathode and the second hollow cathode through the first ion acceleration cavity and the second ion acceleration cavity;
wherein each of the first ion acceleration cavity and the second ion acceleration cavity are sufficient to enable the extraction and acceleration of ions without the presence of magnetic fields.

US Pat. No. 10,483,094

PLASMA DEVICE DRIVEN BY MULTIPLE-PHASE ALTERNATING OR PULSED ELECTRICAL CURRENT

AGC FLAT GLASS NORTH AMER...

1. A plasma source comprising:at least three electrodes, including a first electrode, a second electrode, and a third electrode, the at least three electrodes being arranged linearly such that a first distance between the first electrode and the second electrode is smaller than a second distance between the first electrode and the third electrode; and
a source of power capable of producing multiple output waves, including a first output wave, a second output wave, and a third output wave, wherein the first output wave and the second output wave are out of phase, the second output wave and the third output wave are out of phase, and the first output wave and the third output wave are out of phase;
wherein each electrode is electrically connected to the source of power such that the first electrode is electrically connected to the first output wave, the second electrode is electrically connected to the second output wave, and the third electrode is electrically connected to the third output wave;
wherein electrical current flows between the at least three electrodes that are out of electrical phase;
wherein each electrode alternately serves as anode and cathode when powered by the multiple output waves, and
wherein the plasma source is capable of generating a plasma between the electrodes, including a first plasma directly between the first electrode and the second electrode, a second plasma directly between the second electrode and the third electrode, and a third plasma directly between the first electrode and the third electrode.

US Pat. No. 10,483,092

BAFFLE PLATE AND SHOWERHEAD ASSEMBLIES AND CORRESPONDING MANUFACTURING METHOD

LAM RESEARCH CORPORATION,...

1. A baffle plate assembly comprising:a baffle plate having an outer diameter and configured to receive gases from a stem of a showerhead assembly and distribute the gases through a showerhead of the showerhead assembly of a substrate processing system;
a ring having an inner diameter and configured to be disposed in a ring channel of the showerhead assembly, wherein the inner diameter is greater than the outer diameter of the baffle plate; and
a plurality of support members extending from the baffle plate to the ring,
wherein the ring and the plurality of support members are configured to hold the baffle plate in a position between a top plate and a bottom plate of the showerhead.

US Pat. No. 10,483,089

HIGH VOLTAGE RESISTIVE OUTPUT STAGE CIRCUIT

Eagle Harbor Technologies...

13. A high voltage, high frequency switching circuit comprising:a high voltage switching power supply that produces pulses having a voltage greater than 1 kV and with frequencies greater than 10 kHz;
an output; and
a resistive output stage electrically coupled to, and in parallel with the output of the high voltage switching power supply, the resistive output stage comprising at least one resistor that discharges a load coupled with the output,
wherein the output can produce a high voltage pulse having a voltage greater than 1 kV and with frequencies greater than 10 kHz and with a pulse fall time less than about 400 ns.

US Pat. No. 10,483,085

USE OF ION BEAM ETCHING TO GENERATE GATE-ALL-AROUND STRUCTURE

Lam Research Corporation,...

1. A method of forming channels or nanowires for a gate-all-around device or other electronic device, the method comprising:(a) providing a substrate on a substrate holder in a reaction chamber, the substrate comprising a patterned mask layer over semiconductor material, wherein the patterned mask layer comprises a plurality of linear mask portions oriented substantially parallel to one another;
(b) orienting the substrate with respect to an ion trajectory in a first orientation and directing ions toward the substrate in a first direction, the plurality of linear mask portions protecting a plurality of first shadowed regions, wherein the ions impact the substrate at a first incidence angle to thereby etch the semiconductor material to form a first set of trenches between adjacent first shadowed regions;
(c) orienting the substrate with respect to the ion trajectory in a second orientation and directing the ions toward the substrate in a second direction, the plurality of linear mask portions protecting a plurality of second shadowed regions, wherein the ions impact the substrate at a second incidence angle to thereby etch the semiconductor material to form a second set of trenches between adjacent second shadowed regions;
(d) repeating (b)-(c) to further etch the first and second sets of trenches, wherein the first and second set of trenches intersect with one another, wherein the first shadowed regions and second shadowed regions intersect with one another, and wherein the channels or nanowires are formed in a direction parallel to the plurality of linear mask portions, in areas where the first and second shadowed regions intersect with one another.

US Pat. No. 10,483,083

SCANNING ELECTRON MICROSCOPE AND IMAGE PROCESSING APPARATUS

HITACHI, LTD., Tokyo (JP...

1. A scanning electron microscope (SEM) comprising:a sample stage for mounting a sample;
a detector for detecting an electron emitted from the sample;
an SEM control section for controlling a distance between the sample stage and the detector;
a memory, which stores:
a material database storing a plurality of datasets comprising information associated with a material, information of a crystal structure of the material, and information of an electron emitted from the material; and
a first relationship between the information of electron emitted from the material, the distance, and a signal detected by the detector.

US Pat. No. 10,483,082

EVALUATION METHOD, CORRECTION METHOD, RECORDING MEDIUM AND ELECTRON BEAM LITHOGRAPHY SYSTEM

NuFlare Technology, Inc.,...

1. An evaluation method to evaluate a precision of an aperture formed with multiple openings, the method comprising:forming a first evaluation pattern based on first evaluation data using multiple electron beams generated by an electron beam that has passed through the aperture;
dividing the aperture into multiple regions, each of the regions including a subset of the multiple openings that is less than all the multiple openings in the aperture, and defining the multiple divided regions;
forming a second evaluation pattern based on second evaluation data using a third evaluation pattern formed by multiple electron beams that have passed through a first divided region among the multiple divided regions;
comparing the first evaluation pattern with the second evaluation pattern; and
evaluating the precision of the aperture based on the comparison result between the first evaluation pattern and the second evaluation pattern.

US Pat. No. 10,483,081

SELF DIRECTED METROLOGY AND PATTERN CLASSIFICATION

KLA-Tencor Corp., Milpit...

1. A system configured to determine one or more parameters of a process to be performed on a specimen, comprising:a measurement subsystem comprising at least an energy source and a detector, wherein the energy source is configured to generate energy that is directed to the specimen, and wherein the detector is configured to detect energy from the specimen and to generate output responsive to the detected energy; and
one or more computer subsystems configured for:
determining an area of a defect detected on the specimen;
correlating the area of the defect with information for a design for the specimen;
determining a spatial relationship between the area of the defect and the information for the design based on results of said correlating; and
automatically generating a region of interest, in which one or more measurements are performed for the specimen, based on the spatial relationship, wherein the one or more measurements are performed in the region of interest by the measurement subsystem during a process performed on the specimen by the measurement subsystem.

US Pat. No. 10,483,078

ANODE STACK

Oxford Instruments X-ray ...

1. An anode stack for cooling and electrically insulating an anode of an X-ray device, the anode stack comprising:a conductor member and a dielectric member, the conductor member having a main body and a peripheral portion,
wherein the dielectric member overlies the main body of the conductor member,
wherein the main body of the conductor member is arranged to couple with the dielectric member at one surface of the conductor member, and with an end of the anode at an opposing surface of the conductor member, and
wherein the peripheral portion of the conductor member comprises an annular region that surrounds at least a part of the dielectric member and which is spaced therefrom.

US Pat. No. 10,483,077

X-RAY SOURCES HAVING REDUCED ELECTRON SCATTERING

Rapiscan Systems, Inc., ...

1. An anode for an X-ray tube having at least two channels, the anode comprising:a first channel extending through the anode, wherein the first channel comprises:
a first target defined by a first plane;
a first electron aperture, comprising a first material, through which electrons from a first source of electrons pass to strike said first target, wherein said first electron aperture comprises side walls, each of said side walls having a surface, and a central axis and wherein each of the side walls face each other and define a first pathway through which the electrons travel; and
a first collimating aperture through which X-rays produced at the first target pass out of the anode as a first collimated beam, wherein said first collimating aperture comprises side walls, each of said side walls having a surface, and a central axis;
a second channel extending through the anode, wherein the second channel comprises:
a second target defined by a second plane;
a second electron aperture through which electrons from a second source of electrons pass to strike the second target, wherein the second electron aperture comprises side walls, each of said side walls having a surface, and a central axis and wherein each of the side walls face each other and define a second pathway through which the electrons travel; and
a second collimating aperture through which X-rays produced at the second target pass out of the anode as a second collimated beam, wherein the second collimating aperture comprises side walls, each of said side walls having a surface, and a central axis, wherein the first electron aperture is separate from the second electron aperture and the first collimating aperture is separate from the second collimating aperture.

US Pat. No. 10,483,075

SLOW WAVE CIRCUIT AND TRAVELING WAVE TUBE

NEC NETWORK AND SENSOR SY...

1. A slow wave circuit comprising:a meandering waveguide of a folded structure comprising an opposing meandering groove formed in a flat surface of opposing components; and
a beam hole formed between the opposing groove of the opposing components and that pierces the meandering waveguide, wherein
a sectional shape of the beam hole in a direction orthogonal to a longitudinal direction thereof is a polygon having a larger number of sides as compared with a quadrilateral.

US Pat. No. 10,483,073

FABRICATION OF VACUUM ELECTRONIC COMPONENTS WITH SELF-ALIGNED DOUBLE PATTERNING LITHOGRAPHY

Elwha LLC, Bellevue, WA ...

1. A method of fabricating a component of a vacuum electronic device, the method comprising:fabricating a component of a vacuum electronic device on or in a substrate, comprising:
disposing a first material on or in the substrate;
removing a portion of the first material to form one or more structures of the first material, each of the one or more structures protruding from the substrate and having a first surface and a second surface;
disposing a second material onto the first and second surfaces of the one or more structures of the first material;
removing a portion of the second material from the first surface of the one or more structures to form one or more sidewall structures of the second material, the one or more sidewall structures being disposed on the second surface of the one or more structures of the first material;
removing a second portion of the one or more structures of the first material to form a fabricated structure comprising the substrate and one or more sidewall structures protruding from the substrate; and
disposing a third material onto the one or more sidewall structures, wherein the third material is suspended by the one or more support structures.

US Pat. No. 10,483,072

INTERRUPTER DEVICE FOR INTERRUPTING A DIRECT CURRENT

1. An interrupter device for interrupting a direct current between a direct current source and an electrical device, the interrupter device comprising:a semiconductor switch;
a mechanical switch that has a first fixed contact, a second fixed contact, and a contact bridge that is adapted to be moved between a first position and a second position, wherein in the first position, the first fixed contact and the second fixed contact are electrically contacted via the contact bridge, and in the second position, the contact bridge is spaced apart from the first fixed contact and the second fixed contact and the second fixed contact is galvanically isolated from the contact bridge, wherein when the contact bridge is in the second position, the first fixed contact is galvanically isolated from the second fixed contact,
wherein the contact bridge and the first fixed contact are electrically contacted to the semiconductor switch, which blocks a current when the contact bridge is in the first position, and
wherein a control input of the semiconductor switch is connected to the mechanical switch such that an arc voltage generated as a result of an arc across the mechanical switch connects the semiconductor switch so as to conduct the current when the contact bridge is moved into the second position.

US Pat. No. 10,483,070

FUSES AND METHODS OF FORMING FUSES

LITTELFUSE, INC., Chicag...

11. A method of forming a fuse, comprising;connecting a leadframe to a base, the leadframe including a first terminal having a first end and a second end and a second terminal having a first end and a second end, the second ends connected by a bridge, and the base including a first aperture and a second aperture to receive the respective first and second terminals;
bonding a plurality of wires at each of the first end of the first terminal and the first end of the second terminal;
attaching a cover to the base, the cover including a cavity such that the first end of the first terminal and the first end of the second terminal are enclosed by the cover; and
wherein the bridge has one or more protrusions disposed between the first and second terminals and extending from the bridge, the plurality of wires being bonded to each of the one or more protrusions therebetween.

US Pat. No. 10,483,067

OVERLOAD PROTECTION DEVICE FOR COMPRESSOR MOTOR

MICRO CONTACT SOLUTION CO...

1. An overload protection device for a compressor motor, the overload protection device comprising:a base formed of an insulative material and comprising an inner space;
a conductive terminal comprising an input terminal, an output terminal, and an intermediate terminal;
an overload protection means placed in the inner space of the base; and
a cover configured to cover the base,
wherein the input terminal and the output terminal are at least partially embedded in the base and at least partially exposed inside the inner space, and
the intermediate terminal is placed between the input terminal and the output terminal, the intermediate terminal being at least partially embedded in the base and at least partially exposed inside the inner space,
wherein the overload protection means comprises:
a resistance heating element capable of conducting electricity and having a predetermined electrical resistance value;
a movable arm comprising a material having electrical conductivity and elastic resilience, the movable arm being placed above the resistance heating element and having a predetermined length, the movable arm extending in a length direction thereof; and
a bimetal placed between the resistance heating element and the movable arm, the bimetal deforming in shape at a predetermined operating temperature and returning to an original shape thereof at a predetermined return temperature,
wherein the resistance heating element is electrically connected to the output terminal at one end thereof and electrically connected to the intermediate terminal at the other end thereof, the resistance heating element generating heat when conducting electricity,
wherein a lengthwise end of the movable arm forms a fixed contact that is fixed to and electrically connected to the intermediate terminal, and the other lengthwise end of the movable arm forms a movable contact configured to make contact with the input terminal and vary in position, such that the movable arm electrically connects the input terminal and the intermediate terminal,
wherein electrical connection between the movable contact and the input terminal is broken and made in such a manner that when the bimetal deforms in shape at a temperature equal to or higher than the operating temperature, the movable contact is spaced apart from the input terminal, and when the bimetal returns to the original shape thereof at a temperature equal to or lower than the return temperature, the movable contact and the input terminal come into contact with each other;
wherein the bimetal comprises a first bimetal and a second bimetal placed on the first bimetal,
wherein the first bimetal is shaped like a disc curved downward in a concave dish shape and deforms and snaps at a first operating temperature in an upwardly protruding curved shape,
wherein the second bimetal has a downwardly curved concave dish shape and deforms and snaps at a second operating temperature in an upwardly protruding curved shape,
wherein the second operating temperature is higher than the first operating temperature.

US Pat. No. 10,483,065

MOLDED-CASE CIRCUIT BREAKER FOR DC

LSIS CO., LTD., Anyang-s...

1. A molded-case circuit breaker for DC that contains a plurality of interruption units within an outer casing, the DC circuit breaker comprising a two-unit connecting heater that connects fixed contacts of adjacent interruption units, the two-unit connecting heater being placed within the outer casing,wherein the adjacent interruption units are connected to each other as a series circuit,
wherein the two-unit connecting heater is formed in a U-shape, and comprises:
a pair of head portions respectively connected to the fixed contacts of the adjacent interruption units;
a pair of body portions extending downward from the head portions; and
a leg portion connecting the pair of body portions, and
wherein one of the pair of body portions has a tripping mechanism that detects an over-current in a circuit and interrupts the circuit,
wherein a trip portion case for receiving the two-unit connecting heater and the tripping mechanism is placed within the outer casing, and
wherein the trip portion case has a partition for insulation between the interruption units, and a cut groove is formed on a part of the partition to insert the leg portion.

US Pat. No. 10,483,064

ELECTROMAGNETIC DEVICE, AND ELECTROMAGNETIC RELAY USING SAME

Panasonic Intellectual Pr...

1. An electromagnetic device comprising:an excitation coil;
a stator surrounded by the excitation coil, the stator having a first end;
a movable element surrounded by the excitation coil and configured to, when current is flown in the excitation coil, be attracted to the stator by magnetic flux generated at the excitation coil to move in a first direction from a first position to a second position, wherein the movable element is in contact with the first end of the stator when the movable element moves to the second position;
a yoke having a first end and a second end, and forming a part of a magnetic path for the magnetic flux generated at the excitation coil, wherein the first end of the yoke is magnetically combined with the stator, the second end of the yoke is positioned on a side of the first position of the movable element, and the excitation coil is disposed between the first end of the yoke and the second end of the yoke; and
a yoke extension connected to the second end of the yoke and extending from the second end of the yoke to the first end of the stator, the yoke extension being magnetically combined with the yoke, the stator, and the movable element,
and
wherein the yoke extension surrounds entirety of the movable element positioned between the first position and the second position and surrounds the first end of the stator.

US Pat. No. 10,483,063

PROTECTIVE RELAY WITH EASY WITHDRAWAL

LSIS CO., LTD., Anyang-s...

1. A protective relay comprising:an inner casing including:
a back casing having a receiving space defined therein for accommodating a component therein;
a front casing having a display and a plurality of buttons, wherein the front casing is coupled to the back casing;
a front frame disposed along an edge of the inner casing;
a handle having a lever structure, wherein the handle is pivotably coupled to the front casing, defines a portion of the front frame, and has a 90 degrees-pivoted U shape, wherein both ends thereof are pivotably coupled to the front casing; and
a pair of pivotable frames respectively coupled to an inner side of the handle so as to face each other; and
an outer casing constructed for detachably receiving the inner casing therein, wherein the outer casing includes a pair of support brackets respectively mounted on both opposite sides of an open end of the outer casing for detachably supporting the handle, wherein each of the support brackets includes a handle support protruding toward the inner casing,
wherein when the inner casing is separated from the outer casing, the handle pivots at a state where a portion thereof is in contact with the support brackets, thereby pushing the inner casing out of the outer casing,
wherein each of the pivotable frames has a distal end having a V shaped portion, wherein the distal end is pivotably coupled to the handle support,
wherein each of the pivotable frames has a pivoting point at the distal end, and
wherein when the pivotable frames are pivoted around the pivoting point together with a pivoting of the handle, the distal end of the pivotable frames is inserted or separated into or from the support brackets.

US Pat. No. 10,483,062

ELECTRIC WIRE PROTECTION DEVICE

AutoNetworks Technologies...

1. An electric wire protection device comprising:a pyrotechnic cutoff switch, provided partway along an electric wire connecting a load to a vehicle-mounted power supply connected to a reference potential, the pyrotechnic cutoff switch including a conductive part that conducts current between the vehicle-mounted power supply and the load, a cutting blade that cuts the conductive part, a drive part that propels the cutting blade in a direction that cuts the conductive part using the explosive power of gunpowder, and two terminals that input and output current that drives the drive part;
a conductive wire, one end of the conductive wire being connected to the electric wire and another end of the conductive wire being connected to one of the terminals;
a diode, an anode of the diode being connected to the reference potential and a cathode of the diode being connected to the other of the terminals;
a switch, one end of the switch being connected to the other of the terminals and another end of the switch being connected to the reference potential;
a control unit that opens and closes the switch;
a current detecting unit that detects current flowing in the electric wire; and
a temperature detecting unit that detects a surrounding temperature,
wherein the control unit:
includes a temperature calculating unit that calculates a temperature of the electric wire on the basis of the value of the current detected by the current detecting unit and the surrounding temperature detected by the temperature detecting unit; and
a comparing unit that compares the temperature calculated by the temperature calculating unit with a threshold, and wherein the control unit closes the switch in the case where the temperature is greater than or equal to the threshold;
a timer unit that measures a time for which current flows in the electric wire;
a remaining lifespan calculating unit that calculates a remaining lifespan of the electric wire on the basis of the temperature calculated by the temperature calculating unit and the time measured by the timer unit; and
a remaining lifespan communicating unit that communicates information based on a length of the remaining lifespan calculated by the remaining lifespan calculating unit.

US Pat. No. 10,483,060

SURGICAL TOOL WITH AMBIDEXTROUS SAFETY SWITCH

Stryker Corporation, Kal...

1. A powered surgical tool, the powered surgical tool including:a tool body;
an energy applicator that extends forward from the tool body, the energy applicator adapted to receive energy from a power generating unit and apply the energy to tissue to which the energy applicator is applied; and
a switch assembly attached to the tool body for controlling the actuation of the power generating unit, the switch assembly including:
a switch that is moveably mounted to the tool body;
a sensor configured to generate a signal representative of the position of the switch relative to the sensor;
two arms that are pivotally mounted to said switch such that said arms extend outwardly from opposed sides of the switch and each arm is capable of moving from a safety state to a run state; and
a member attached to at least one of said arms such that when said arm is in the safety state, the member engages a fixed surface to prevent movement of said switch and, when said arm is in the run state, the member is spaced from the fixed surface so that said member does not impede movement of the switch and
wherein, said switch assembly is further constructed so that each said arm includes a base that is pivotally mounted to said switch and the bases of said arms are formed with components that engage each other, so that the pivoting of either one of the arm bases from the arm run state to the arm safety state, results in the simultaneous pivoting of the other arm base from the arm run state to the arm safety state, and the pivoting of either arm base from the arm safety state to the arm run state results in the simultaneous pivoting of the other arm base from the arm safety state to the arm run state.

US Pat. No. 10,483,058

SAFETY SWITCH ACCESS ARRANGEMENT

Eaton Intelligent Power L...

1. An apparatus comprising:a cabinet;
a circuit interrupting device installed in the cabinet, the circuit interrupting device having an actuator configured for rotation about a switching axis to switch the circuit interrupting device between ON and OFF conditions;
a front access hub supported for rotation about an axis orthogonal to the switching axis;
a handle coupled to the front access hub to rotate the front access hub about the orthogonal axis;
a first link coupled to the front access hub to project radially from the orthogonal axis, and to move pivotally about the orthogonal axis upon rotation of the front access hub;
a second link coupled to the actuator to project radially from the actuator, and to rotate the actuator about the switching axis upon movement of the second link pivotally about the switching axis; and
a third link coupled between the first and second links to transmit pivotal movement between the first and second links;
wherein the third link is coupled between the first and second links to move in opposite directions between the first and second links upon movement of the first and second links pivotally about the orthogonal axis and the switching axis; and
the third link has a first elongated slot with opposite ends, the second link projects through the first elongated slot, and the opposite ends of the first elongated slot are movable against the second link to move the second link pivotally about the switching axis.

US Pat. No. 10,483,054

MONO OR BIDIRECTIONAL CONTACTOR

Telarc S.r.l., Milan (IT...

1. A mono- or bi-directional contactor device for applications involving switching of a power supply for high current and/or voltage electrical loads, comprisinga containing and protective casing made of synthetic plastic insulating material, said casing having a bottom wall from which there extends an actuator portion, said actuator portion comprising a coil and auxiliary contacts,
an intermediate portion for housing fixed and movable contact poles, and
an upper arc chute portion for dissipating an electric arc;
said casing having a flat parallelepiped form, the bottom wall of the casing extending at 90° with respect to a side wall of the casing, said side wall being on a shorter side of said flat parallelepiped form;
a support plate for the contactor being connected to an outer surface of the bottom wall or to an outer surface of said side wall, so as to support the casing as a vertical extension from a horizontal plane or as a horizontal projection from a vertical plane, and
wherein said arc chute portion occupies a quadrant of the parallelepiped form which is situated at a top and/or side with respect to said bottom wall and/or said side wall.

US Pat. No. 10,483,051

CONTACT SLIDE UNIT FOR A SWITCHING UNIT

1. A contact slide unit for a switching unit, the contact slide unit comprising:a contact slide;
a moving contact piece guided within the contact slide, wherein the moving contact piece has a top side and a bottom side, and wherein the contact slide is positioned on the top side of the moving contact piece; and
a contact load spring,
wherein one side of the moving contact piece is acted on by the contact load spring, and
wherein the moving contact piece is mounted in a turn gap between two turns of the contact load spring such that a first part of the contact load spring is positioned above the top side of the moving contact piece, a second part of the contact load spring is positioned below the bottom side of the moving contact piece, and the turn gap is positioned between the first part and the second part of the contact load spring.

US Pat. No. 10,483,050

METHOD FOR MAKING STRETCHABLE CAPACITOR ELECTRODE-CONDUCTOR STRUCTURE

Tsinhua University, Beij...

1. A method of making a stretchable capacitor electrode-conductor structure comprising:step (S1), providing an elastic substrate, and pre-stretching the elastic substrate along a first direction and a second direction to obtain a pre-stretched elastic substrate;
step (S2), laying a carbon nanotube active material composite layer on a surface of the pre-stretched elastic substrate, the step (S2) comprising:
step (S21), laying a first carbon nanotube film structure on the surface of the pre-stretched elastic substrate, and the first carbon nanotube film structure directly contacting with the pre-stretched elastic substrate and comprising a plurality of first super-aligned carbon nanotube films stacked with each other, each of the plurality of first super-aligned carbon nanotube films comprising a plurality of first carbon nanotubes substantially parallel with each other;
step (S22), covering a first mask on a surface of the first carbon nanotube film structure away from the pre-stretched elastic substrate;
step (S23), adding an electrode active material through the first mask to the surface of the first carbon nanotube film structure away from the pre-stretched elastic substrate, to form a first active material layer on a part of the surface of the first carbon nanotube film structure;
step (S24), removing the first mask; and
step (S25), laying a second carbon nanotube film structure on a surface of the first active material layer away from the pre-elastic substrate, and the second carbon nanotube film structure directly contacting with the first active material layer and comprising a plurality of second super-aligned carbon nanotube films stacked with each other, each of the plurality of second super-aligned carbon nanotube films comprising a plurality of second carbon nanotubes substantially parallel with each other;
step (S3), releasing the pre-stretching of the elastic substrate to restore deformations of the elastic substrate, and forming a plurality of wrinkles on a surface of the carbon nanotube active material composite layer; and
step (S4), processing the carbon nanotube active material composite layer to obtain a capacitor electrode and a conductor structure, and the capacitor electrode and the conductor structure being formed by an integrated molding.

US Pat. No. 10,483,047

ELECTROCHEMICAL REACTION DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A method of using an electrochemical reactor, comprising:preparing an electrochemical reactor, the electrochemical reactor having
a tank including a first room and a second room,
a first electrode disposed in the first room and configured to reduce a first substance,
a second electrode disposed in the second room and configured to oxidize a second substance,
a first pipe connected to the first room, and
a second pipe connected to the first room and disposed above the first pipe;
supplying a first liquid into the first room and the first pipe and a second liquid into the first room and the second pipe to form a first electrolytic solution, and supplying a second electrolytic solution into the second room, the first liquid containing water and forming a first liquid phase in the first electrolytic solution, the second liquid containing an organic solvent and forming a second liquid phase in the first electrolytic solution, the second electrolytic solution containing the second substance, and at least one liquid selected from the group consisting of the first and second liquids further containing the first substance;
applying a voltage between the first and second electrodes to reduce the first substance and thus form a reduction product and to oxidize the second substance and thus form a oxidization product; and
recovering the reduction product with the second liquid through the second pipe, and recovering the oxidization product.

US Pat. No. 10,483,046

ORGANOMETALLIC HALIDE PEROVSKITE SINGLE CRYSTALS HAVING LOW DEFECT DENSITY AND METHODS OF PREPARATION THEREOF

KING ABDULLAH UNIVERSITY ...

1. A method of making a single crystal, comprising:providing a first reservoir including a first liquid, wherein the first liquid includes a first precursor and an organic cation precursor dissolved in a first liquid solvent;
providing a second reservoir including a second liquid, wherein the second liquid is a non-solvent;
wherein the first reservoir and second reservoir are separated by a boundary so that the first liquid and the second liquid do not contact one another, wherein the first reservoir and the second reservoir are in a closed system;
allowing for vapor diffusion of the second liquid into the first liquid so that the solubility of the first precursor and organic cation precursor gradually decreases; and
precipitating out an organometallic halide perovskite single crystal in the first reservoir.

US Pat. No. 10,483,044

MATERIAL FOR ELECTRODE OF POWER STORAGE DEVICE, POWER STORAGE DEVICE, AND ELECTRICAL APPLIANCE

Semiconductor Energy Labo...

1. A material for an electrode of a power storage device comprising:a granular active material comprising a carbon atom; and
a film having a structure over the granular active material,
wherein the structure comprises a plurality of bonds between the carbon atom and one of a silicon atom and a metal atom through an oxygen atom, and
wherein the film partly covers a surface of the granular active material so that the surface of the granular active material has a first region which is covered with the film, and a second region which is not covered with the film.

US Pat. No. 10,483,042

METHOD OF MANUFACTURING A CAPACITIVE ELECTRICAL DEVICE

ABB Schweiz AG, Baden (C...

1. A method of manufacturing a capacitive electrical device, wherein the method comprises:a) bonding a first electrical insulation film with a second electrical insulation film to obtain a single electrical insulation film that has a larger surface area than any of the first electrical insulation film and the second electrical insulation film has alone,
b) providing a conductive layer onto the single electrical insulation film, and
c) winding the single electrical insulation film and the conductive layer around a shaft concurrently to obtain a layer of the single electrical insulation film and a layer of the conductive layer wound onto the shaft for forming the capacitive electrical device,the first electrical insulation film and the second electrical insulation film being bonded to form the single electrical insulation film prior to them being wound around the shaft.

US Pat. No. 10,483,039

CONDUCTIVE PASTE FOR EXTERNAL ELECTRODE AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT INCLUDING THE CONDUCTIVE PASTE FOR EXTERNAL ELECTRODE

MURATA MANUFACTURING CO.,...

1. A conductive paste for an external electrode, the conductive paste comprising:a conductive metal powder;
a glass frit having an average particle diameter D50 of not more than 0.8 ?m and having a flat shape with an average flatness of 1.5 to 5.5; and
a binder resin.

US Pat. No. 10,483,038

MULTILAYER CERAMIC CAPACITOR AND MANUFACTURING METHOD OF MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a multilayer structure in which each of dielectric layers and each of internal electrode layers are alternately stacked, a main component of the dielectric layers being ceramic, a main component of the internal electrode layers being a metal,
wherein:
at least one of the internal electrode layers includes grains of which a main component is ceramic; and
an area ratio of a total area of the grains to a total area of the at least one of the internal electrode layers in a cross section of the at least one of the internal electrode layers in a stacking direction of the dielectric layers and the internal electrode layers is 12% or more.

US Pat. No. 10,483,037

METHOD OF MANUFACTURING A MAGNETICALLY GRADED MATERIAL

ROLLS-ROYCE plc, London ...

1. A method of manufacturing a magnetically graded material, the method comprising:in an additive layer manufacture process:
depositing a powder or wire material to a substrate; and
applying a directed energy source comprising one of a laser and an electron beam to first and second regions of the powder or wire material to thereby join the first and second regions to form a joined material; wherein
the energy source is directed to the first region while the first region is provided with a shield gas comprising an inert shield gas such that the material of the first region comprises a magnetic phase,
the shield gas is changed to comprise a nitrogen containing shield gas when the energy source is directed to the second region such that the second region is provided with the nitrogen containing shield gas to thereby impart an non-magnetic phase to the second region, and the inert shield gas is substantially free of nitrogen.

US Pat. No. 10,483,034

MANUFACTURING METHOD OF COIL-EMBEDDED INDUCTOR USING SOFT MAGNETIC MOLDING SOLUTION AND COIL-EMBEDDED INDUCTOR MANUFACTURED BY USING THE SAME

CHANG SUNG CO., LTD., Ch...

1. A manufacturing method of a coil-embedded inductor having a structure in which a part of a coil is embedded in a magnetic core, the manufacturing method comprising:(I) preparing an organic vehicle;
(II) preparing a soft magnetic molding solution having a density of 5.5 to 6.5 g/cc by mix-milling a soft magnetic powder with the organic vehicle;
(III) positioning and fixing a part of the coil in a case; and
(IV) forming the magnetic core by injecting and curing the soft magnetic molding solution into the case,
wherein the soft magnetic molding solution in step (II) is formed with a composition ratio of 94 to 98 wt % of the soft magnetic powder and 2 to 6 wt % of the organic vehicle,
wherein the soft magnetic powder is formed by mixing three or more soft magnetic powders having different average particle diameters, and
wherein the soft magnetic powder is formed by mixing a first soft magnetic powder having an average particle diameter of 2 to 5 ?m, a second soft magnetic powder having an average particle diameter of 10 to 20 ?m, and a third soft magnetic powder having an average particle diameter of 50 to 150 ?m.

US Pat. No. 10,483,031

CIRCUIT ARRANGEMENT FOR REDUCING A MAGNETIC UNIDIRECTIONAL FLUX COMPONENT IN THE CORE OF A TRANSFORMER

Siemens Aktiengesellschaf...

1. A circuit arrangement for reducing a magnetic unidirectional flux component in a core (13) of a transformer, comprising:a measuring device which provides a sensor signal corresponding to the magnetic unidirectional flux component;
a compensation coil which is magnetically coupled to the core of the transformer;
a semiconductor switching device which is electrically arranged in a current path in series with the compensation coil to feed a current into the compensation coil, such that current is directed opposite to the magnetic unidirectional flux component, the semiconductor switching device being controlled via a control signal provided by a controller;
an inductive voltage divider comprising:
a first impedance component arranged in a current circuit in series with the compensation coil and the semiconductor switching device, said first impedance component being connected in parallel with a parallel resonant circuit;
a second impedance component which is arranged in parallel with the semiconductor switching device.

US Pat. No. 10,483,029

CORE MEMBER, REACTOR, AND METHOD FOR MANUFACTURING CORE MEMBER

AutoNetworks Technologies...

1. A core member obtained by molding a mixture containing soft magnetic powder and a resin, the core member comprising:a base portion and a pair of projecting portions spaced apart from each other and projecting from the base portion;
an installation surface disposed on a bottom portion of the base portion, the installation surface facing an object on which the core member is to be installed and an interlinkage surface disposed on an end of each of the projecting portions, the interlinkage surface being intersected by a magnetic flux excited by a coil; and
wherein the installation surface and the interlinkage surface has a higher density than the base portion and the pair of projecting portions.

US Pat. No. 10,483,024

COIL ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component, comprising:a substrate;
a coil pattern disposed on at least one surface of the substrate;
a body filling at least a core area of the coil pattern and containing a magnetic material; and
a magnetic flux controller disposed at an outer surface of the body and corresponding to the core area, the magnetic flux controller containing a magnetic material which has a permittivity value higher than that of the magnetic material of the body,
wherein the magnetic flux controller has a surface area smaller than that of the core area such that the magnetic flux controller is disposed at the outer surface of the body partly, and
wherein when viewing the coil electronic component from a side in a width-length direction thereof, a width of the magnetic flux controller is smaller than that of the core area.

US Pat. No. 10,483,023

RESISTOR CALIBRATION

Futurewei Technologies, I...

1. An electrical circuit, comprising:a configurable resistor;
a reference resistor;
a current source circuit coupled to provide a current to the configurable resistor and the reference resistor;
an Analog-to-Digital Converter (ADC) coupled to the configurable resistor and the reference resistor, the ADC configured to convert voltages from the configurable resistor and the reference resistor to digital values;
a calculation circuit coupled to receive digital values from the ADC, the calculation circuit configured to calculate an adjustment for the configurable resistor from a digital reference value obtained from a reference resistor voltage and two or more digital values obtained from two or more voltages corresponding to two or more configurations of the configurable resistor; and
a sequencer configured to adjust the configurable resistor based on the adjustment calculated by the calculation circuit.

US Pat. No. 10,483,021

CABLE WITH A CARBONIZED INSULATOR AND METHOD FOR PRODUCING SUCH A CABLE

LEONI Kabel GmbH, Nuremb...

5. A method for producing a cable, comprising:surrounding an inner conductor with an insulating material;
partially carbonizing a surface of the insulating material at least intermittently, and forming a structure on the surface; and
surrounding the insulating material with an outer conductor.

US Pat. No. 10,483,020

TWISTED PAIR DATA COMMUNICATION CABLE WITH INDIVIDUALLY SHIELED PAIRS USING DISCONTINUOUS SHIELDING TAPE

NEXANS, Courbevoie (FR)

1. A LAN cable comprising:four twisted pairs of insulated conductors;
a jacket surrounding said twisted pairs; and
at least two discontinuous shield tapes each having a plurality of separated metal segments,
wherein said discontinuous shielding tapes are folded and arranged between said four twisted pairs in a partially overlapping manner, separating each of said four pairs from one another.

US Pat. No. 10,483,019

ULTRA-FLEXIBLE INDOOR ACCOMPANYING PHOTOELECTRIC COMPOSITE CABLE

JIANGSU ETERN COMPANY LIM...

1. An indoor accompanying photoelectric composite cable, comprising:power transmission components,
optical fiber transmission components; and
structural strengthening components,
wherein the power transmission components include a cable core and an insulating material wrapped around the cable core, the cable core being a non-flammable flame-retardant material,
wherein the power transmission components, optical fiber transmission components; and structural strengthening components are covered by a flame-retardant outer protective layer,
wherein the power transmission components comprise a cable core which is a soft conductor and an insulating material layer wrapped around the cable core, the optical fiber transmission components comprise a tight tube optical fiber, and the power transmission components and the optical fiber transmission components are arranged in parallel inside the flame-retardant outer protective layer,
wherein the structural strengthening components comprise multiple strands of high elastic tensile steel wires,
wherein the power transmission components and the structural strengthening components are two different components separated by the flame-retardant outer protective layer and the power transmission components are disposed at an inside of the structural strengthening components,
wherein a plurality of stress grooves are formed between the power transmission components and the optical fiber transmission components, and between the optical fiber transmission components, and
wherein the tight tube optical fiber consists of, in sequence from inside to outside: a fiber core, a high-strength aramid fiber layer for improving flexibility of the photoelectric composite cable, and a tight-buffered coating layer, the high-strength aramid fiber layer being wrapped around the fiber core, and the tight-buffered coating layer being wrapped outside the high-strength aramid fiber layer.

US Pat. No. 10,483,018

TRANSMISSION CABLE AND POWER SUPPLY DEVICE HAVING TRANSMISSION CABLE

CHICONY POWER TECHNOLOGY ...

1. A transmission cable, comprising:a cable body, having a first end and a second end, the cable body comprising a power supply wire and a signal wire;
a return control circuit, located at the second end, and configured to selectively electrically connect the power supply wire to the signal wire; and
a determining circuit, located at the first end, and configured to determine a return voltage of the signal wire and output a first signal when the return voltage is less than a threshold.

US Pat. No. 10,483,015

FLEX FLAT CABLE STRUCTURE AND FLEX FLAT CABLE ELECTRICAL CONNECTOR FIX STRUCTURE

ENERGY FULL ELECTRONICS C...

1. A flex flat cable (FFC) electrical connector fix structure, comprising:an electrical connector, comprising:
a housing;
a spacer, assembled onto the housing, and comprising a plurality of containing recesses;
a printed circuit board (PCB), comprising a plurality of conductive portions and a plurality of connecting portions, and the plurality of conductive portions being electrically connected to the plurality of corresponding connecting portions respectively;
a plurality of terminals, one end of the plurality of terminals passing through the containing recess and being connected to the plurality of connecting portions; and
a shell, assembled onto the housing; and
an FFC structure, comprising:
a plurality of metallic transmission wires, arranged parallel, comprising one or more power wires and a plurality of signal wires; the power wire being configured to transmit power; the plurality of signal wires being configured to transmit a data signal;
a plurality of first insulating jackets, and each of the plurality of first insulating jackets encloses one of the plurality of metallic transmission wires;
a second insulating jacket, surrounding the plurality of first insulating jackets; an embossment pattern being arranged directly on an external surface of the second insulating jacket; the embossment pattern comprising a plurality of meander lines in a top-view direction and in an extending direction for the plurality of metallic transmission wires; the plurality of meander lines being not arranged parallel; and
a third insulating jacket, enclosing the plurality of first insulating jackets without any gap and being enclosed by the second insulating jacket,
wherein all of the conductive portions are on one surface of the and the plurality of metallic transmission wires are connected to the plurality of conductive portions, and
wherein the second insulating jacket and the third insulating jacket are made of different materials.

US Pat. No. 10,483,014

ROLLED COPPER FOIL, METHOD OF MANUFACTURING A ROLLED COPPER FOIL, FLEXIBLE FLAT CABLE, AND METHOD OF MANUFACTURING A FLEXIBLE FLAT CABLE

FURUKAWA ELECTRIC CO., LT...

1. A rolled copper foil comprising one of copper and a copper alloy, the rolled copper foil having a rolled surface and two side surfaces adjacent to the rolled surface, each of the side surfaces being a non-sheared surface, whereinthe rolled copper foil has a width of 0.300 mm to 2.000 mm and a thickness of 0.010 mm to 0.200 mm,
an area ratio A of crystal grains oriented at a deviation angle of less than or equal to 13° from Cube orientation being greater than or equal to 6%,
at two end regions each corresponding to 10%-width in a transverse direction, an area ratio B of crystal grains oriented at a deviation angle of less than or equal to 13° from Cube orientation is greater than or equal to 15%,
wherein the rolled copper foil has a flex life cycle of 500,000 cycles or more,
the rolled copper foil is hard copper in which stress is accumulated due to plastic working, and
the rolled copper foil is formed by subjecting a planar wire rod to a finish rolling process so that a thickness reduction ratio Z is 50% or less.

US Pat. No. 10,483,013

INSULATED WIRE EXCELLENT IN BENDING RESISTANCE, AS WELL AS COIL AND ELECTRIC OR ELECTRONIC EQUIPMENT USING THE SAME

FURUKAWA ELECTRIC CO., LT...

1. An insulated wire having an insulating coat layer comprising a thermoplastic resin on an outer peripheral surface of a conductor having a rectangular cross-sectional shape and also having a long side, a short side, and a corner portion having a curvature radius Rc,wherein a thickness t1 (?m) of the insulating coat layer covered on a surface which is continuing in an axial direction of the conductor, and which layer includes a long side of a transverse section of the conductor, a thickness t2 (?m) of the insulating coat layer covered on the surface which is continuing in the axial direction of the conductor, and which layer includes a short side of the transverse section of the conductor, and a corner portion thickness t3 (?m) of the insulating coat layer satisfy formula (1):
t3/{(t1+t2)/2}?1.2  Formula (1)
wherein the t1 (?m) and t2 (?m) are each independently 20 ?m or more and 50 ?m or less, and
wherein a ratio of a cross-sectional area Sc (mm2) of the conductor to a cross-sectional area Sw (mm2) of the insulated wire satisfies formula (2):
1.0>Sc/Sw?0.8.  Formula (2)

US Pat. No. 10,483,012

PROCESS FOR FORMING A NANOCOMPOSITE FILM

King Fahd University of P...

1. A process for forming a nanocomposite film, comprising:sonicating a solution of a conductive nanofiller to form a stable dispersion of nanofiller,
mixing the stable dispersion of nanofiller with a solution comprising a polymer and a polysaccharide to form a reaction mixture, and
casting the reaction mixture and drying to form the nanocomposite film, wherein during the casting the mixture separates into a polymer phase containing a majority of the polymer, a conductive nanofiller phase containing a majority of the conductive nanofiller, and a polysaccharide phase containing a majority of the polysaccharide,
wherein the nanocomposite film comprises:
a polymer layer comprising the polymer,
a conductive nanofiller layer comprising the conductive nanofiller,
a polysaccharide layer comprising the polysaccharide,
wherein a surface of the polysaccharide layer has a first resistivity and a surface of the polymer layer has a second resistivity,
wherein the conductive nanofiller layer is sandwiched between and in continuous contact with the polymer layer and the polysaccharide layer; and
wherein the second resistivity is less than or equal to the first resistivity.

US Pat. No. 10,483,010

REDUCTION OF SURFACE AND EMBEDDED SUBSTRATE CHARGE BY CONTROLLED EXPOSURE TO VACUUM ULTRAVIOLET (VUV) LIGHT IN LOW-OXYGEN ENVIRONMENT

LAM RESEARCH AG, Villach...

1. A system for reducing surface and embedded charge in a substrate, comprising:a substrate support configured to support a substrate;
a vacuum ultraviolet (VUV) assembly, of a processing chamber, that is arranged adjacent to the substrate support and that includes a housing and a VUV lamp that is connected to the housing and that generates and directs ultraviolet (UV) light at the substrate,
wherein the housing includes:
a first inlet to receive an oxygen-reducing purge gas;
a first fluid channel in fluid communication with the first inlet,
wherein the first fluid channel has an annular shape; and
a first outlet in fluid communication with the first fluid channel; and
a movement device configured to move the VUV assembly during exposure of the substrate to the UV light to reduce surface and embedded charge in the substrate,
wherein the first outlet directs the oxygen-reducing purge gas into a gap between the VUV lamp and the substrate, and
wherein the first outlet comprises one of:
a plurality of spaced nozzles passing from the first fluid channel through a substrate-facing surface of the housing; and
an annular slot passing from the first fluid channel through the substrate-facing surface of the housing.

US Pat. No. 10,483,006

LEARNING BASED METHODS FOR PERSONALIZED ASSESSMENT, LONG-TERM PREDICTION AND MANAGEMENT OF ATHEROSCLEROSIS

Siemens Healthcare GmbH, ...

1. A computer-implemented method for providing a personalized evaluation of assessment of atherosclerotic plaques for a patient, the method comprising:acquiring patient data comprising non-invasive patient data, medical images of the patient, and blood biomarkers;
extracting features of interest from the patient data;
training one or more machine learning models using a database of synthetic data comprising one or more of in silico anatomical models and in vitro anatomical models; and
applying the one or more machine learning models to the features of interest to predict a plurality of measures of interest related to atherosclerotic plaque, wherein the plurality of measures of interest related to atherosclerotic plaque include a risk of cardiovascular event, plaque composition, plaque evolution, effect of a drug treatment, in-stent restenosis, lesions requiring sealing, indication of a future screening data, and effect of a device for therapy, wherein the risk of cardiovascular event includes coronary circulation, cerebral circulation, and peripheral circulation,
wherein the one or more machine learning models are trained using a process comprising:
performing fluid solid growth (FSG) computations for the in silico anatomical models or flow experiments for the in vitro anatomical models to yield output data;
extracting measures of interest from the output data;
extracting geometric features and plaque-related features from the database of synthetic data; and
training the one or more machine learning models to predict measures of interest related to atherosclerotic plaque using the measures of interest from the output data, the geometric features, and the plaque-related features.

US Pat. No. 10,483,005

SYSTEM AND METHOD FOR CHARACTERIZATION OF ELECTRICAL PROPERTIES OF THE HEART FROM MEDICAL IMAGES AND BODY SURFACE POTENTIALS

Siemens Healthcare GmbH, ...

1. A method for estimating patient-specific cardiac electrical properties from medical image data and non-invasive body surface potential measurements of a patient, comprising:generating a volumetric patient-specific anatomical heart model and a patient-specific anatomical torso model from medical image data of a patient and an electrical coupling model between the patient-specific anatomical heart model and the patient-specific anatomical torso model;
estimating extra-cellular potentials on an epicardial surface of the patient-specific anatomical heart model from measured body surface potentials on a torso of the patient based on the electrical coupling model between the patient-specific anatomical heart model and the patient-specific anatomical torso model and estimating transmembrane potentials on the epicardial surface of the patient-specific anatomical heart model from the estimated extra-cellular potentials; and
estimating spatially varying patient-specific cardiac electrical parameters for the patient by:
initializing one or more cardiac electrical parameters of a computational cardiac electrophysiology model over the volumetric patient-specific anatomical heart model from the estimated transmembrane potentials on the epicardial surface of the patient-specific anatomical heart model;
simulating cardiac electrophysiology over time at a plurality of nodes in the volumetric patient-specific anatomical heart model using the computational cardiac electrophysiology model, and
adjusting the one or more cardiac electrical parameters of the computational cardiac electrophysiology model over the volumetric patient-specific anatomical heart model based on the estimated transmembrane potentials on the epicardial surface of the patient-specific anatomical heart model, and simulated transmembrane potentials on the epicardial surface of the patient-specific anatomical heart model resulting from simulating the cardiac electrophysiology.

US Pat. No. 10,483,004

MODEL-BASED TEETH RECONSTRUCTION

DISNEY ENTERPRISES, INC.,...

1. A method for reconstructing a three-dimensional (3D) model of teeth of an object from one or more images of the object, the method being performed by a computer system and comprising:receiving, by the computer system, sample data of teeth rows of different sample subjects;
receiving, by the computer system, tooth templates comprising individual template teeth;
mapping, by the computer system, individual teeth in the teeth rows of the different sample subjects to the individual template teeth;
for each of the individual template teeth, obtaining, by the computer system, a teeth statistical model, the statistical model encoding a deviation in shape and pose for each of the individual template teeth, wherein the teeth statistical model includes information regarding a rigid transformation and an anisotropic scaling factor for the teeth rows, the anisotropic scaling factor comprising different properties depending on a direction of measurement for the teeth rows;
training, by the computer system, each teeth statistical model using the sample data of the teeth rows of the different sample subjects based on the mapping between the individual teeth in the teeth rows of the different sample subjects and the individual template teeth, wherein the training comprises: evaluating the teeth statistics model to provide an instance of a teeth row that represents either an upper or a lower teeth for a sample subject;
acquiring, by the computer system, teeth information from the one or more images of the object; and
reconstructing, by the computer system, a 3D model of teeth of the object by fitting parameters of the trained teeth statistical model to the teeth information acquired from the one or more images of the object.

US Pat. No. 10,483,003

DYNAMICALLY DETERMINING RISK OF CLINICAL CONDITION

Cerner Innovation, Inc., ...

1. One or more computer-readable hardware devices having computer-executable instructions embodied thereon that when executed by at least a processor, facilitate at least an apparatus to:receive a portion of patient health data for a patient, the portion of patient health data including a first set of clinical concepts encoded in a first nomenclature associated with a healthcare entity;
convert the first set of clinical concepts encoded in the first clinical nomenclature to a second set of clinical concepts encoded in a second nomenclature;
determine, from the second set of clinical concepts encoded in the second nomenclature, a current state of the patient;
accessing a library of clinical condition programs that are encoded in the second nomenclature to construct a clinical condition computer program routine for the patient based on the determined current state of the patient;
use the clinical condition computer program routine to determine a set of risk factors specifically associated with a combination of at least two concurrent clinical conditions, the set of risk factors having one or more clinical concepts encoded in the second nomenclature;
convert the one or more clinical concepts associated with the set of risk factors encoded in the second nomenclature to respective one or more clinical concepts encoded in the first nomenclature; and
cause for display the set of risk factors having the respective one or more clinical concepts encoded in the first nomenclature to a healthcare provider of the patient.

US Pat. No. 10,483,001

INTERACTIVE DISPLAY FOR USE IN OPERATING ROOMS

Compview Medical, Beaver...

1. An interactive method of displaying information in an operating room in connection with a scheduled surgical procedure, the method comprising:receiving information about a plurality of categories of personnel that have been pre-selected as required for the scheduled surgical procedure;
displaying each of the categories that have been pre-selected as required for the scheduled surgical procedure on a display screen;
receiving data via a reader from one or more badges associated with one or more respective persons to establish the presence of the one or more persons in the operating room, the data containing identifying information relating to the one or more persons;
processing the data received via the reader from the one or more badges of persons in the operating room; and
displaying the identifying information from the data on the one or more badges on display device along with the pre-selected plurality of categories of personnel required for the surgical procedure, the identifying information including at least a name of the one or more persons established as being present in the operating room and a role assigned to the one or more persons for the surgical procedure;
associating the identifying information and preselected categories together on the display screen to indicate whether all preselected categories of personnel are represented by one or more respective persons that have established their presence in the operating room;
identifying the departure from the operating room of the one or more persons that had been previously established as present in the operating room;
removing the departed one or more persons from the display of the identifying information such that the display screen accurately reflects all of the persons that are in the operating room;
displaying on the display device a first count of foreign objects that have been opened and are available for use during the surgical procedure;
displaying on the display device a second count of the foreign objects from the first count that have actually been used during the surgical procedure; and
entering information about the foreign objects on a touchscreen device to determine the first and second counts displayed on the display device, the touchscreen device including a pre-determined listing of foreign objects from which the first and second counts can be selected,
wherein the display device is visually accessible within the operating room, the display device comprising a display screen that is sufficiently large for observation by multiple viewers within the operating room.

US Pat. No. 10,483,000

MEDICINE ADMINISTERING SYSTEM INCLUDING INJECTION PEN AND COMPANION DEVICE

Companion Medical, Inc., ...

1. A system for administering a medicine to a patient, comprising:an injection pen device comprising:
a housing including a main body structured to include a chamber to encase a cartridge containing medicine upon loading of the cartridge in the chamber;
a dose setting and dispensing mechanism to set and dispense a particular dose of the medicine from the cartridge, the dose setting and dispensing mechanism including a dose knob, a shaft, and a plunger, wherein the dose knob is rotatable to cause the shaft to move to a position proportional to a set dose of the medicine, and wherein the dose knob is operable to move translationally to cause the shaft to drive the plunger to dispense the medicine from the cartridge;
a sensor to detect a dispensed dose, and
an electronics unit in communication with the sensor unit, the electronics unit including a processor and a non-transitory memory to process the detected dispensed dose and time data associated with a dispensing event to generate dose data, a power source to provide electrical power to the electronics unit, and a transmitter; and
a mobile communication device including a software application program product stored in a memory of the mobile communication device and including instructions operable to cause the mobile communication device to process one or more of the dose data corresponding to one or more dispensing events to form a dose dispensing sequence such that the dispensing events of the dose dispensing sequence all occur in temporal proximity of one another that span less than a predetermined temporal threshold, and the last dispensing event in the dose dispensing sequence is identified as the injection event and one or more of the dispensing events other than the last dispensing events in the dose dispensing sequence are identified as the priming events regardless of relative sizes of the dispensing events,
wherein the transmitter of the injection pen device is operable to wirelessly transmit the dose data to the mobile communication device.

US Pat. No. 10,482,999

SYSTEMS AND METHODS FOR EFFICIENT HANDLING OF MEDICAL DOCUMENTATION

APIXIO, INC., San Mateo,...

1. In a health information management system, a computerized method for processing medical records, comprising:receiving at least one medical record;
processing the at least one medical record by indexing and semantic meta-tagging to alter the at least one medical record format, embedding information in metadata;
providing the processed at least one medical record to an analytics layer of a data storage architecture;
generating, using a processor, a condition based upon at least one medical record of the processed at least one medical record, wherein the condition includes a first confidence value;
determining admissibility of each medical record by confirming that an encounter associated with the medical record was face-to-face, signed, and by an admissible specialist, wherein the confirming the encounter is face-to-face includes contextual analysis of confirmation statements, presence of a procedure that requires patient attendance, and metadata, and wherein the confirming the medical record is signed includes an image recognition algorithm, and wherein the confirming the admissible specialist includes cross referencing the condition against a physician performing the diagnosis responsive to a table of allowable diagnoses for the specialty of the physician;
contacting the physician, a healthcare provider or insurance company when the medical record is inadmissible with a suggestion for correction;
scheduling an examination of the patient to correct the inadmissible record; and
generating a MEAT determination for each medical record, wherein the MEAT determination includes a second confidence value, and further wherein the MEAT determination includes identifying a monitor component, and evaluation component, an assessment component and a treatment component.

US Pat. No. 10,482,996

SYSTEMS AND METHODS FOR DETERMINING RELATIVE GEOCHEMICAL DATA

Schlumberger Technology C...

1. A method for determining relative geochemical data, comprising:receiving measurement data that was measured by a downhole logging tool, wherein the measurement data represents relative yields of a plurality of chemical elements in a rock formation;
determining first absolute yields of at least a portion of the plurality of chemical elements in a first chemical compound in the rock formation;
determining second absolute yields of at least a portion of the plurality of chemical elements in a second chemical compound in the rock formation;
determining, using a processor, a volume of the first chemical compound, a volume of the second chemical compound, and a sum of yields of the plurality of chemical elements using the first and second absolute yields and the relative yields, wherein determining the sum of yields of the plurality of chemical elements further comprises:
determining a denominator based on the relative yield of a first chemical element in the plurality of chemical elements;
determining a numerator based on a product of the absolute yield of the first chemical element in the first chemical compound and the volume of the first chemical compound; and
determining the sum of yields based on the numerator divided by the denominator; and
producing a geochemical log model that displays the volume of the first chemical compound, the volume of the second chemical compound, and the sum of the yields of the plurality of chemical elements.

US Pat. No. 10,482,992

GENOME BROWSER

CERES, INC., Thousand Oa...

1. A computer-implemented method for displaying and analyzing sequenced genome data, the method comprising:obtaining, by a computing system, genomic data for a plurality of organisms;
generating, by the computing system and based at least on the genomic data for the plurality of organisms, a browser plate component displaying a first graphical representation of the genomic data, the first graphical representation comprising a plurality of vertical parallel tracks that are arranged to show one or more features of the genomic data for different ones of the plurality of organisms, wherein the plurality of vertical parallel tracks includes a first track that shows a first particular feature of a first organism, a second track that shows the first particular feature of a second organism, and a third track that shows the first particular feature of a third organism; and
upon an identification, by the computing system, that the first organism is designated as a reference organism, reconfiguring, by the computing system and in response to identifying that the first organism is designated as the reference organism, the browser plate component to display a second graphical representation of the plurality of vertical parallel tracks in the second graphical representation of the genomic data so that the first track that shows the first particular feature of the first organism is shown in a reference position of the graphical representation, the second and third tracks are shown in respective positions proximate to the reference position, and the first particular features of the second and third tracks are each shown relative to the first particular features of the first track, wherein reconfiguring the browser plate component comprises rearranging each vertical parallel track in accordance with a rank corresponding to a similarity score between each vertical parallel track and the first track.

US Pat. No. 10,482,987

MAGNETIC WALL UTILIZATION SPIN MOSFET AND MAGNETIC WALL UTILIZATION ANALOG MEMORY

TDK CORPORATION, Tokyo (...

1. A magnetic wall utilization spin MOSFET comprising:a magnetic wall driving layer comprising a magnetic wall, a first region, a second region, and a third region located between the first region and the second region;
a channel layer;
a magnetization free layer provided at a first end portion of a first surface of the channel layer, and arranged so as to be in contact with the third region of the magnetic wall driving layer;
a magnetization fixed layer provided at a second end portion opposite to the first end portion; and
a gate electrode provided between the first end portion and the second end portion of the channel layer through a gate insulating layer; and
a readout electrode layer provided at a position overlapping the magnetization free layer in plan view on a fourth surface of the magnetic wall driving layer opposite to a third surface of the magnetic wall driving layer on which the magnetization free layer is provided in the third region of the magnetic wall drive layer, the fourth surface being provided in the third region of the magnetic wall drive layer.

US Pat. No. 10,482,986

ADAPTIVE ERASE FAIL BIT CRITERIA

Western Digital Technolog...

1. An apparatus, comprising:a group of non-volatile memory cells;
an erase circuit configured to perform an erase operation on the group;
a counting circuit configured to determine whether a first fail bit count for the group with respect to a first erase verify level for the erase operation exceeds an allowed fail bit count;
the counting circuit further configured to determine a second fail bit count for the group with respect to a second erase verify level that is a higher magnitude reference voltage than the first erase verify level responsive to the first fail bit count being above the allowed fail bit count; and
a response circuit configured to increase the allowed fail bit count for the erase verify level to at least the second fail bit count responsive to the second fail bit count being between a first number and a second number.

US Pat. No. 10,482,985

DYNAMIC ERASE LOOP DEPENDENT BIAS VOLTAGE

SanDisk Technologies LLC,...

1. An apparatus comprising:a monitor circuit configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold;
a bias circuit configured to adjust a voltage applied to one or more buffer word lines of the erase block in response to the erase loop count for the data word lines satisfying the threshold; and
an erase circuit configured to perform one or more subsequent erase loops of the erase operation for the data word lines with the adjusted voltage applied to the one or more buffer word lines.

US Pat. No. 10,482,984

RAMP DOWN SENSING BETWEEN PROGRAM VOLTAGE AND VERIFY VOLTAGE IN MEMORY DEVICE

SanDisk Technologies LLC,...

1. An apparatus, comprising:a set of memory cells connected to a selected word line;
a voltage driver configured to, in a program operation, apply a program voltage to the selected word line followed by ramping down a voltage of the selected word line; and
sense circuits configured to perform repeated sensing of the set of memory cells during the ramping down of the voltage of the selected word line.

US Pat. No. 10,482,981

PREVENTING REFRESH OF VOLTAGES OF DUMMY MEMORY CELLS TO REDUCE THRESHOLD VOLTAGE DOWNSHIFT FOR SELECT GATE TRANSISTORS

SanDisk Technologies LLC,...

1. An apparatus, comprising:a set of connected memory cells comprising a data memory cell adjacent to one or more dummy memory cells, the data memory cell comprising a control gate and the one or more dummy memory cells comprising a dummy memory cell positioned adjacent to a select gate transistor; and
a refresh circuit configured to repeatedly increase a voltage at the control gate to keep the voltage at the control gate higher than a voltage of a control gate of the dummy memory cell positioned adjacent to the select gate transistor.

US Pat. No. 10,482,980

SEMICONDUCTOR DEVICE HAVING RING OSCILLATOR AND METHOD OF ARRANGING RING OSCILLATOR

SK hynix Inc., Gyeonggi-...

1. A ring oscillator comprising:first to fourth current-controlled delay circuits configured to allow a delay time to be changed depending on a magnitude of sink current; and
a current control circuit configured to control the magnitude of the sink current,
wherein the current control circuit is arranged at a center of a square, and
wherein the first to fourth current-controlled delay circuits are arranged symmetrically to each other about the square.

US Pat. No. 10,482,977

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMEORY CORPORATI...

1. A semiconductor memory device, comprising:a first pad to which a first voltage is supplied;
a second pad to which a second voltage different from the first voltage is supplied; and
a power supply protection circuit including:
a first transistor including a first end electrically connected to the first pad and a second end electrically connected to a first node,
a second transistor including a first end electrically connected to the second pad and a second end electrically connected to the first node,
a third transistor including a first end electrically connected to the second pad, a second end electrically connected to the first node, and a gate electrically connected to a second node, and having a size different from that of the second transistor,
a fourth transistor including a first end electrically connected to the first pad, a second end electrically connected to the second node, and a gate electrically connected to the first node, and
a fifth transistor including a first end electrically connected to the second pad, a second end electrically connected to the second node, and a gate electrically connected to the first node.

US Pat. No. 10,482,976

MEMORY DEVICE PERFORMING UV-ASSISTED ERASE OPERATION

SK hynix Inc., Gyeonggi-...

1. A nonvolatile memory device, comprising:a plurality of word lines that are stacked;
a pillar structure that penetrates through the word lines in a vertical direction; and
a voltage supplier suitable for supplying a plurality of biases that are required according to an operation mode, to the word lines and the pillar structure,
wherein the pillar structure includes:
a vertical channel region disposed in a core; and
a laser diode structure disposed between the word lines and the vertical channel region to surround a periphery of the vertical channel region.

US Pat. No. 10,482,975

FLASH MEMORY CELL WITH DUAL ERASE MODES FOR INCREASED CELL ENDURANCE

MICROCHIP TECHNOLOGY INCO...

1. A method, comprising:providing a memory cell including a floating gate and a pair of program/erase nodes over the floating gate; and
selectively alternate between the pair of program/erase nodes after every N erase functions, wherein N is greater than 1, to perform a series of erase functions in the memory cell.

US Pat. No. 10,482,974

OPERATION OF A MEMORY DEVICE DURING PROGRAMMING

Micron Technology, Inc., ...

1. A method of operating a memory, comprising:applying a first voltage level to a first data line and to a second data line while applying a second voltage level, lower than the first voltage level, to a first select gate connected between the first data line and a first string of series-connected memory cells and to a second select gate connected between the second data line and a second string of series-connected memory cells;
applying a third voltage level, lower than the first voltage level, to the first data line while continuing to apply the first voltage level to the second data line and while continuing to apply a voltage level lower than the first voltage level to the first select gate and to the second select gate;
applying a fourth voltage level, higher than the third voltage level, to the first select gate while continuing to apply a voltage level lower than the first voltage level to the second select gate;
applying a fifth voltage level, higher than the first voltage level, to a first access line and to a second access line while continuing to apply the fourth voltage level to the first select gate and while continuing to apply a voltage level lower than the first voltage level to the second select gate, wherein the first access line and the second access line are each coupled to a respective memory cell of the first string of series-connected memory cells and to a respective memory cell of the second string of series-connected memory cells; and
applying a sixth voltage level, higher than the fifth voltage level, to the first access line while continuing to apply the fifth voltage level to the second access line.

US Pat. No. 10,482,971

SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS

SK hynix Inc., Icheon-si...

1. A semiconductor memory apparatus comprising:a memory cell; and
a current supply circuit configured to perform a write operation by changing an amount of current flowing through the memory cell, perform a reset write operation without limiting a voltage level across the memory cell, and limit the voltage level across the memory cell to a level of a clamping voltage in a set write operation.

US Pat. No. 10,482,970

SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory system comprising:a first semiconductor memory device; and
a signal line connected to the first semiconductor memory device,
wherein the first semiconductor memory device outputs a signal according to existence of a peak current to the signal line, and
wherein when the peak current is larger than a reference current, the first semiconductor memory device is in a waiting state that does not transfer to an operating state using the current larger than the reference current.

US Pat. No. 10,482,967

LAYOUT STRUCTURE OF LOCAL X-DECODER

Wuhan Xinxin Semiconducto...

1. A two-sided memory array comprising a central Flash memory cell array, wherein each side of the memory array comprises:four local x-decoders, each local x-decoder comprising:
a first pair of cascode transistors coupled between a voltage supply and ground, comprising a first PMOS and a first NMOS, wherein a first voltage is coupled to a gate of the first PMOS and a gate of the first NMOS, and a first signal is coupled to a drain of the first PMOS and a source of the first NMOS;
a second pair of cascode transistors comprising a second PMOS and a second NMOS, wherein a drain of the second NMOS is coupled to ground, a source of the second PMOS is coupled to a second signal, a drain of the second PMOS is coupled to a word line, and the first signal is coupled to a gate of the second PMOS;
a third PMOS, having a source coupled to the first signal and a drain coupled to ground; and
a third pair of cascode transistors comprising a third NMOS and a fourth NMOS, wherein a source of the third NMOS is coupled to the second signal, a gate of the third NMOS is coupled to a third signal, and a drain of the fourth NMOS is coupled to the word line;
wherein all transistors in each local x-decoder are disposed vertically, and P-channels and N-channels of the four local x-decoders on each side of the memory array are disposed in an order corresponding to P-channels of a first local x-decoder, P-channels of a second local x-decoder, P-channels of a third local x-decoder, P-channels of a fourth local x-decoder, N-channels of the fourth local x-decoder, N-channels of the third local x-decoder, N-channels of the second local x-decoder and N-channels of the first local x-decoder.

US Pat. No. 10,482,966

BLOCK DECODER OF NONVOLATILE MEMORY AND LEVEL SHIFTER

WINBOND ELECTRONICS CORP....

15. A level shifter, comprising:a first transistor, wherein the first transistor has a control terminal coupled to a first control node, a first terminal coupled to an output node, and a second terminal coupled to a first supply voltage;
a second transistor, wherein the second transistor has a control terminal coupled to a second control node, a first terminal coupled to a ground voltage, and a second terminal coupled to the output node;
a third transistor, wherein the third transistor has a control terminal coupled to the output node, a first terminal coupled to a first node, and a second terminal coupled to a second supply voltage; and
a fourth transistor, wherein the fourth transistor has a control terminal coupled to the second control node, a first terminal coupled to the first node, and a second terminal coupled to the output node.

US Pat. No. 10,482,965

MEMORY START VOLTAGE MANAGEMENT

Micron Technology, Inc., ...

1. A system, comprising:a memory device storing a set of start voltage values, wherein the set of start voltage values each represent voltage levels used to initially store charges in performing operations to corresponding one or more memory locations of the memory device; and
a processing device, operatively coupled to the memory device, to:
determine whether a quantity of start voltage values in the set of start voltage values stored in the memory device meets a threshold;
modify the set of start voltage values stored in the memory device to remove one or more start voltage values from the set in response to a determination that the quantity of start voltage values in the set meets the threshold, wherein the one or more start voltage values are removed based on:
tracking an oldest entry within a memory-block list, wherein the oldest entry represents one of the start voltage values corresponding to one of the memory locations having longest delay since last access or charging operation and or that was accessed first, and
deleting the oldest entry; and
add a new start voltage value to the modified set of start voltage values.

US Pat. No. 10,482,964

THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A three-dimensional (3D) semiconductor memory device comprising:a substrate comprising a cell array region and a connection region;
an electrode structure extending from the cell array region onto the connection region in a first direction, the electrode structure comprising a lower stack structure comprising a plurality of lower electrodes vertically stacked on the substrate and a plurality of intermediate stack structures vertically stacked on the lower stack structure to comprise a first stair step structure in the first direction;
an upper stack structure comprising a plurality of upper electrodes vertically stacked on the electrode structure; and
an upper dummy stack structure comprising a plurality of upper dummy electrodes which are horizontally spaced apart from the upper stack structure and are vertically stacked on the electrode structure,
wherein each of the plurality of intermediate stack structures comprises a plurality of intermediate electrodes vertically stacked to comprise a second stair step structure extending in a second direction that is substantially perpendicular to the first direction.

US Pat. No. 10,482,963

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a stacked body including a first stacked region; and
a first structure body,
the first stacked region including
a first selection gate electrode,
a second selection gate electrode separated from the first selection gate electrode in a first direction,
a plurality of first electrodes arranged in the first direction and provided between the first selection gate electrode and the second selection gate electrode,
a plurality of second electrodes arranged in the first direction and provided between the second selection gate electrode and the first electrodes, and
a plurality of third electrodes arranged in the first direction and provided between the first electrodes and the second electrodes,
a first spacing between two mutually-adjacent first electrodes of the first electrodes being wider than a third spacing between two mutually-adjacent third electrodes of the third electrodes,
a second spacing between two mutually-adjacent second electrodes of the second electrodes being wider than the third spacing,
the first structure body including
a first semiconductor body extending in the first direction,
a first outer film provided between the first semiconductor body and the first stacked region,
a first inner film provided between the first semiconductor body and the first outer film, and
a first intermediate film provided between the first outer film and the first inner film.

US Pat. No. 10,482,962

TCAM DEVICE AND OPERATING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A ternary content addressable memory (TCAM) device comprising:a plurality of memory cells, each of the plurality of memory cells comprising:
a data storage circuit comprising a first resistor and a second resistor connected in series to divide a search voltage corresponding to search data, and configured to store cell data;
a limiter circuit configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage; and
a discharge circuit configured to discharge a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.

US Pat. No. 10,482,960

DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES

Intel Corporation, Santa...

1. A memory device, comprising:an array of memory cells; and
circuitry configured to:
apply a set demarcation bias voltage (Vdms) to a plurality of cells and detect the presence or absence of a resulting transient snapback current;
after applying the set demarcation bias voltage (Vdms) to the plurality of cells, receive at least a portion of data comprising set bits and reset bits;
identify an array location to write data comprising set bits and reset bits;
map the set bits and the reset bits of the data to corresponding cells of the array location;
apply a reset demarcation bias voltage (Vdmr) to reset bit-mapped cells and detect the presence or absence of a resulting transient snapback current, wherein Vdmr has a higher voltage than Vdms;
apply a set pulse to set bit-mapped cells in which the transient snapback current is absent; and
apply a reset pulse to reset bit-mapped cells in which the transient snapback current is present.

US Pat. No. 10,482,959

ELECTRONIC DEVICE WITH A REFERENCE RESISTANCE ADJUSTMENT BLOCK

SK hynix Inc., Icheon-si...

1. An electronic device including a semiconductor memory, the semiconductor memory comprising:one or more resistive storage cells each structured to exhibit different resistance values for storing data;
a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series;
a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and structured to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and
a reference resistance adjustment block coupled to the reference resistance block and structured to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block, and
wherein a bias voltage having a fixed voltage level is supplied to the first reference resistance transistor as the first gate voltage during an operation to determine data stored in the selected resistive storage cell and an adjustment voltage having a varying voltage level adjusted depending on a temperature is supplied to the second reference resistance transistor as the second gate voltage.

US Pat. No. 10,482,958

RRAM-BASED MONOTONIC COUNTER

Taiwan Semiconductor Manu...

1. A circuit, comprising:a memory array having a plurality of memory cells;
a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state;
a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state; and
an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.

US Pat. No. 10,482,957

RESISTIVE RAM MEMORY CELL

STMICROELECTRONICS (ROUSS...

16. A memory, comprising:a silicon on insulator substrate that includes a semiconductor layer on a buried insulating layer;
first and second memory cells each including:
a selection transistor having a gate, source, and drain, at least one of the source and drain being a conductive zone formed in the substrate layer; and
a resistive RAM memory element positioned along a sidewall of the gate of the selection transistor and directly contacting the conductive zone, in which the first and second memory elements are located side by side; and
an insulating region extending between the conductive zone of the first memory cell and the conductive zone of the second memory cell, the insulating region including a portion of the buried insulating layer.

US Pat. No. 10,482,956

APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS

Micron Technology, Inc., ...

1. A method, comprising:applying a first bias across a memory cell during a selection phase of an access operation, the first bias having a first polarity;
removing the first bias, wherein a current flowing through the memory cell falls below a minimum hold current based at least in part on the removing the first bias; and
applying a second bias across the memory cell during an access phase of the access operation, the second bias lower in magnitude than the first bias and having a second polarity.

US Pat. No. 10,482,955

STORAGE ARRAY, AND STORAGE CHIP AND METHOD FOR STORING LOGICAL RELATIONSHIP OF OBJECTS

SHANGHAI INSTITUTE OF MIC...

1. A storage array, characterized in that the storage array at least comprises:first leading-out wires and second leading-out wires which have the same quantity and are respectively located in a line direction and a column direction; the first leading-out wires and the second leading-out wires being respectively numbered; a storage unit being connected between each first leading-out wire and each second leading-out wire having different serial numbers; and a controllable switch being connected between each first leading-out wire and each second leading-out wire having a same serial number, wherein,
the storage unit comprises a variable-resistance two-terminal device and a gating diode which are connected in series, and the gating diode is forwardly conducted from the first leading-out wire to the second leading-out wire and is reversely cut off from the second leading-out wire to the first leading-out wire; and
the controllable switch is switched between a bidirectional cut-off state and a unidirectional conducted state from the second leading-out wire to the first leading-out wire.

US Pat. No. 10,482,953

MULTI-STATE MEMORY DEVICE AND METHOD FOR ADJUSTING MEMORY STATE CHARACTERISTICS OF THE SAME

MACRONIX INTERNATIONAL CO...

1. A multi-state memory device, comprising:memory cells each comprising a memory element and a controlling element connected to the memory element in series or in parallel, wherein the memory cells are connected in series or in parallel, the controlling elements of the memory cells have a characteristic value, the memory elements have identical structures;
when one of the memory elements receives a first signal and a second signal respectively, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.

US Pat. No. 10,482,952

INTEGRATED CIRCUIT WITH SEPARATE SUPPLY VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM LOGIC CIRCUIT SUPPLY VOLTAGE

Apple Inc., Cupertino, C...

1. An integrated circuit comprising:a logic circuit in a first voltage domain, the first voltage domain corresponding to a first power supply voltage having a first power supply voltage value during use;
a memory circuit in a second voltage domain corresponding to a second power supply voltage having a second power supply voltage value different from the first power supply voltage value for at least some operation during use, the memory circuit comprising a plurality of memory cells, wherein the logic circuit accesses data in the memory circuit; and
an interface circuit between the first voltage domain and the second voltage domain, wherein the interface circuit converts one or more inputs to the memory circuit from the logic circuit from the first voltage domain to the second voltage domain.

US Pat. No. 10,482,951

1T1D DRAM CELL AND ACCESS METHOD AND ASSOCIATED DEVICE FOR DRAM

1. An access device applied to a Dynamic Random-Access Memory cell, a circuit of said memory cell comprises a data transmission node and a transmission control node, said data transmission node is applied for writing and reading data, said transmission control node is applied for controlling data input and output; wherein said access device comprises a trigger and a transistor, said trigger comprises a signal input connective point, said transistor comprises a data rewrite connective point and a control input connective point said signal input connective point connects or couples to said data rewrite connective point, said data transmission node connects or couples to said signal input connective point and said data rewrite connective point, said trigger outputs an inverted signal which inverts said signal input connective point and connects to said control input connective point; while the cell read operation, when said trigger detected that the variation of said data transmission node is over the trigger level then turns on said transistor, otherwise continue cuts off said transistor; and the rewrite operation of said memory cell is said transistor be turned on.

US Pat. No. 10,482,948

APPARATUSES AND METHODS FOR DATA MOVEMENT

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory device, comprising:
a plurality of subarrays of memory cells;
respective sensing circuitry stripes coupled to the plurality of subarrays, the respective sensing circuitry stripes each including a sense amplifier stripe and a corresponding compute component stripe;
a latch stripe comprising a plurality of latches selectably coupled to respective columns of the memory cells and configured to store first data values moved, in parallel, from a first sensing circuitry stripe of a first subarray to the latch stripe; and
a controller configured to direct:
movement of the first data values from the first sensing circuitry stripe to the latch stripe; and
movement of the first values from the latch stripe to a selected second subarray via a second sensing circuitry stripe corresponding thereto; and
while the first data values are being moved to the selected second subarray, performance of a logical operation between second and third data values stored in a third subarray using a third sensing circuitry stripe corresponding thereto.

US Pat. No. 10,482,947

INTEGRATED ERROR CHECKING AND CORRECTION (ECC) IN BYTE MODE MEMORY DEVICES

Intel Corporation, Santa...

1. A memory device package, comprising:an input/output (I/O) interface having N connectors to couple to a channel having fewer than N signal lines;
a first memory die with a first N-bit interface;
a second memory die with a second N-bit interface; and
circuitry to selectively apply column address select (CAS) signals to the first and second memory dies to selectively couple N/2 interface bits of the first memory die to N/2 of the N connectors and at least one of the interface bits of the second memory die to at least one of the N connectors, to provide a channel having fewer than N bits spread between the first and second memory dies, the channel to include N/2 data (DQ) signal lines and at least one error checking and correction (ECC) signal line.

US Pat. No. 10,482,944

SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:an initial buffer signal generation circuit configured to include an initial buffer circuit which is activated if an initialization operation terminates and configured to generate an initial buffer signal from an external control signal in response to a first reference voltage signal; and
a buffer signal generation circuit configured to include a buffer circuit which is activated in response to the initial buffer signal and configured to generate a buffer signal from the external control signal in response to a second reference voltage signal;
wherein the initial buffer signal has a first logic level if the external control signal has a level which is greater than or equal to a level of the first reference voltage signal, and wherein the initial buffer signal has a second logic level if the external control signal has a level which is less than the level of the first reference voltage signal.

US Pat. No. 10,482,943

SYSTEMS AND METHODS FOR IMPROVED ERROR CORRECTION IN A REFRESHABLE MEMORY

Qualcomm Incorporated, S...

1. A method for implementing error correction control (ECC) on a computing device, the method comprising:defining a parity region and a user data region of a refreshable memory device, the memory device coupled to a system on a chip (SoC), the parity region having a size which is smaller than the user data region, the parity region storing ECC parity bits without user payload data (UPD), the user data region storing user payload data without ECC parity bits;
determining with the SoC a first refresh rate for the user data region of the memory device;
determining with the SoC a second refresh rate for the parity region of the memory device, the second refresh rate being greater than the first refresh rate and being based on at least one of: a ratio to the first refresh rate, and calibration data;
generating with the SoC parity data for a write operation of the user payload data (UPD) to the user data region of the memory device;
refreshing the user data region of the memory device at the first refresh rate;
refreshing the parity region of the memory device at the second refresh rate; and
determining that a change in the second refresh rate for the parity region is needed based on at least one of: a time interval, a pre-determined number of writes to the parity region or user data region, error detection in the parity region, and a change in type of error correction.

US Pat. No. 10,482,941

MAGNETIC MEMORY DEVICE

Toshiba Memory Corporatio...

1. A magnetic memory device, comprising:a first memory portion including
a first magnetic portion including a first portion and a second portion,
a first magnetic layer, and
a first nonmagnetic layer provided between the second portion and the first magnetic layer;
a first conductive portion electrically connected to the first portion;
a first interconnection electrically connected to the first magnetic layer; and
a controller electrically connected to the first conductive portion and the first interconnection,
the controller being configured to apply a first pulse between the first conductive portion and the first interconnection in a first write operation, the first pulse having a first pulse height and a first pulse length,
the controller being configured to apply a second pulse between the first conductive portion and the first interconnection in a first shift operation, the second pulse having a second pulse height and a second pulse length,
an absolute value of the second pulse height being less than an absolute value of the first pulse height,
the second pulse length being longer than the first pulse length.

US Pat. No. 10,482,940

COMPUTATIONAL ACCURACY IN A CROSSBAR ARRAY

HEWLETT PACKARD ENTERPRIS...

1. A system, comprising:a crossbar array, comprising a plurality of memory elements at junctions, usable in performance of computations;
a calculate engine to calculate ideal conductance of memory elements at a plurality of junctions of the crossbar array;
a determine engine to determine conductance of the memory elements at the plurality of junctions of the crossbar array; and
an adjust engine to adjust conductance of at least one memory element to improve computational accuracy by reduction of a difference between the ideal conductance and the determined conductance of the at least one memory element, wherein the adjusting of the conductance of the at least one memory element is based on an input of a number of actual crossbar parameters comprising a number of models of signal output variation in crossbar arrays.

US Pat. No. 10,482,938

WORD-LINE TIMING CONTROL IN A SEMICONDUCTOR MEMORY DEVICE AND A MEMORY SYSTEM INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of operating a semiconductor memory device including a memory cell array having a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the method comprising:enabling a first word-line of the plurality of word-lines in response to a first command received from a memory controller, the first word-line being selected in response to an access address received from the memory controller;
generating an interval signal having a first pulse width if the first command corresponds to an active command; and
counting the generated interval signal to determine whether a reference time interval has elapsed, and disabling the first word-line upon determining the reference time interval has elapsed,
wherein a first bit-line of a bit-line pair coupled to at least one memory cell coupled to the first word-line is charged with an internal voltage and a second bit-line of the bit-line pair is discharged to a ground voltage in an enable interval during which the first word-line is enabled, and
wherein voltage levels of the first and second bit-lines are maintained at the internal voltage and the ground voltage, respectively, during a disable interval during which the first word-line is disabled.

US Pat. No. 10,482,937

MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME

Samsung Electronics Co., ...

1. A memory device comprising:an interface configured to receive a data signal and a strobe signal from an external device, the strobe signal corresponding to the data signal;
a strobe buffer configured to receive the strobe signal from the interface;
a phase detection unit configured to detect a phase difference between the data signal output from the interface and the strobe signal output from the strobe buffer;
a phase adjust unit configured to adjust a phase of the strobe signal output from the strobe buffer based on the phase difference; and
a sampling unit configured to sample the data signal output from the interface based on the strobe signal output from the phase adjust unit.

US Pat. No. 10,482,936

SIGNAL TRAINING FOR PREVENTION OF METASTABILITY DUE TO CLOCKING INDETERMINACY

Micron Technology, Inc., ...

1. A memory device comprising:a delay element configured to receive a command signal;
a latch configured to receive the command signal from the delay element and to output the command signal based on a clock signal, wherein the delay element is configured to match a latency of the command signal to a latency of the clock signal;
a command decoder configured to receive the command signal, wherein the command decoder is configured to provide a write command signal when the received command signal comprises a write operation; and
circuitry configured to receive the write command signal and a data strobe signal, and to output an internal write control signal.

US Pat. No. 10,482,935

NONVOLATILE MEMORY INCLUDING DUTY CORRECTION CIRCUIT AND STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY

Samsung Electronics Co., ...

1. A nonvolatile memory comprising:a first memory chip;
a second memory chip;
a clock pin, which is commonly connected to the first and second memory chips, configured to receive an external clock signal during a training period; and
an input/output pin commonly connected to the first and second memory chips,
wherein the first memory chip includes,
a first duty correction circuit (DCC) configured to perform a first duty correction operation on a first internal clock signal based on the external clock signal, and
a first output buffer connected between an output terminal of the first DCC and the input/output pin,
wherein the second memory chip includes,
a second DCC configured to perform a second duty correction operation on a second internal clock signal based on the external clock signal, and
a second output buffer connected between an output terminal of the second DCC and the input/output pin, and
wherein, during the training period, the first DCC is configured to perform the first duty correction operation in parallel with the second DCC performing the second duty correction operation.

US Pat. No. 10,482,934

MEMORY CONTROLLER ARCHITECTURE WITH IMPROVED MEMORY SCHEDULING EFFICIENCY

Altera Corporation, San ...

1. A method comprising:receiving, via a memory controller circuit, a memory command to access a memory, wherein the memory command is configured to transmit from user interface circuitry configured to receive the memory command from user logic of field programmable gate array (FPGA) circuitry, and wherein the memory controller circuit comprises a plurality of column address arbiters configured to arbitrate between read and write memory access requests configured as memory commands;
determining, via the memory controller circuit, a priority associated with the memory command;
ordering, via the memory controller circuit, the memory command to transmit through logic circuitry comprising a plurality of finite state machine circuits configured to queue the memory command among a plurality of memory commands, wherein the logic circuitry is parallel to additional logic circuitry;
determining, via the memory controller circuit, to issue the memory command based on the priority and a queue of the memory command;
transmitting, via the memory controller circuit, the memory command to physical layer circuitry to access the memory; and
transmitting, via the memory controller circuit, a feedback signal associated with the memory command transmitted to the physical layer circuitry, wherein the plurality of finite state machine circuits are configured to use the feedback signal in queuing operations.

US Pat. No. 10,482,932

VOLTAGE REFERENCE COMPUTATIONS FOR MEMORY DECISION FEEDBACK EQUALIZERS

Micron Technology, Inc., ...

1. A device, comprising:a voltage reference generator configured to produce one or more distortion correction factors; and
a selection circuit configured to:
receive the one or more distortion correction factors from the voltage reference generator;
select a distortion correction factor of the one or more distortion correction factors as a selected distortion correction factor; and
transmit the selected distortion correction factor such that the selected distortion correction factor is used to offset an interference associated with a data stream on a distorted bit.

US Pat. No. 10,482,931

REVERSED BIAS COMPENSATION FOR SENSE AMPLIFIER OPERATION

Micron Technology, Inc., ...

17. A memory device comprising:first and second data lines, wherein the first data line is coupled to a memory cell;
a flip-flop comprising:
a first transistor comprising a first source terminal coupled to the first data line, a first gate terminal coupled to a first output of a biasing circuit and a first drain terminal coupled to a first common source line; and
a second transistor comprising a second source terminal coupled to the second data line, a second gate terminal coupled to a second output of the biasing circuit and a second drain terminal coupled to the first common source line; and
reversed bias compensation circuitry comprising the biasing circuit, a pre-charge circuitry, wherein the reversed bias compensation circuitry is configured to:
pre-charge and equalize the first data line and the second data line to a pre-charge voltage using the pre-charge circuitry;
during a compensation phase, connect the first gate terminal and the second gate terminal to a first voltage higher than the pre-charge voltage using the biasing circuit; and
during a readout phase, connect the first gate terminal to the second data line and the second gate terminal to the first data line and connect the memory cell to the first data line; and
wherein the compensation phase is configured to generate a first voltage difference between the first data line and the second data line that is proportional to a difference ?Vth between a first gate-source threshold voltage of the first transistor and a second gate-source threshold voltage of the second transistor.

US Pat. No. 10,482,930

MEMORY CHIP WITH REDUCED POWER CONSUMPTION, BUFFER CHIP MODULE CONTROLLING THE SAME AND MEMORY MODULE INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. A memory chip, comprising:a chip select (CS) buffer configured to receive a chip select signal;a chip identification (CID) buffer configured to receive a chip identification signal; anda command (CMD) buffer configured to receive a command signal,wherein the chip identification signal is input after a time has elapsed since the chip select signal is activated and before the command signal is input and the CID buffer is activated when the chip identification signal is input, andwherein the command signal is input after a time has elapsed since the identification signal is input and the CMD buffer is activated when the command signal is input.

US Pat. No. 10,482,929

NON-VOLATIVE (NV) MEMORY (NVM) MATRIX CIRCUITS EMPLOYING NVM MATRIX CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS

QUALCOMM Incorporated, S...

1. A non-volatile (NV) memory (NVM) matrix circuit, comprising:a plurality of word lines configured to receive an input vector represented by an input voltage on each word line among the plurality of word lines;
a plurality of bit lines, each bit line among the plurality of bit lines configured to receive a corresponding line voltage;
a plurality of source lines;
a plurality of NVM storage string circuits, each NVM storage string circuit among the plurality of NVM storage string circuits configured to be electrically coupled between a corresponding bit line among the plurality of bit lines and a corresponding source line among the plurality of source lines each comprising a plurality of NVM bit cell circuits;
each NVM bit cell circuit among the plurality of NVM bit cell circuits having a resistance representing a stored memory state in the NVM bit cell circuit to form a data vector for the corresponding NVM storage string circuit;
each NVM bit cell circuit among the plurality of NVM bit cell circuits in the NVM storage string circuit, comprising:
a gate node coupled to a corresponding word line among the plurality of word lines; and
each NVM bit cell circuit configured to couple its resistance to the source line in response to the input voltage applied to the corresponding word line coupled to the gate node; and
a plurality of access transistors, each access transistor among the plurality of access transistors coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line;
each access transistor among the plurality of access transistors comprising an access gate node coupled to an access line; and
each access transistor among the plurality of access transistors configured to electrically couple the corresponding bit line to the corresponding NVM storage string circuit in response to an access voltage applied to the access gate node;
wherein an NVM storage string circuit among the plurality of NVM storage string circuits is configured to generate a respective current flowing through a source line among the plurality of source lines coupled to the NVM storage string circuit to a respective output node based on the line voltage applied to the bit line coupled to the NVM storage string circuit and the resistances applied by each of the plurality of NVM bit cell circuits of the NVM storage string circuit in response to a read activation voltage being applied to the gate nodes of each of the plurality of NVM bit cell circuits.

US Pat. No. 10,482,928

RECIRCULATION FILTER FOR AN ELECTRONIC ENCLOSURE

Donaldson Company, Inc., ...

1. A filter assembly comprising:a first sheet of filter media having a first perimeter region;
a second sheet of filter media having a second perimeter region, wherein the first perimeter region and the second perimeter region are bonded in a rim region; and
a plurality of adsorbent beads disposed between the first sheet of filter media and the second sheet of filter media, wherein a substantial portion of the plurality of adsorbent beads are unbonded and the plurality of adsorbent beads define an adsorbent face area having an adsorbent density of greater than 600 g/m2.

US Pat. No. 10,482,927

WATERPROOF MODULE AND SEAL MEMBER THEREOF

ETAC TECHNOLOGY CORPORATI...

1. A module, comprising:a housing having an opening, wherein the opening penetrates through an outer surface of the housing;
an inserting element adapted to enter and exit the housing through the opening; and
a seal member comprising a connecting portion and a resilient portion, wherein the resilient portion surrounds and extends away from a periphery of the connecting portion, the connecting portion is fixed to the inserting element, the connecting portion is proportioned to fit in the opening, and the resilient portion and the connecting portion are proportioned and arranged such that when the inserting element is moved from an ejected position to a retracted position, the connecting portion at least partially enters into the opening, the resilient portion is pressed against the outer surface of the housing at a periphery of the opening, the resilient portion is deformed at a junction of the resilient portion and the connecting portion so as to bend away from the inserting element, and a waterproof seal is created between the resilient portion and the outer surface of the housing.

US Pat. No. 10,482,926

INFORMATION PROCESSING APPARATUS

FUJITSU LIMITED, Kawasak...

1. An information processing apparatus comprising:a casing which includes a side plate on each of left and right sides; and
a processing apparatus to be mounted in the casing,
the processing apparatus includes:
a board on which an arithmetic processing device and a storage device are mounted;
a rail which is provided on each of the left and right sides of the board and extends in the horizontal direction to make the board slidable;
a locking portion which locks the board to the casing;
a detection portion which detects that the board is taken out first when the board is taken out from the casing by that locking by the locking portion is released and the board slides against the rails; and
a locking mechanism provided so as to be separated physically from the locking portion and configured to lock the board to the casing when the board is further taken out from the casing after the board is taken out first,
the processing apparatus migrates a virtual machine which operates by using the arithmetic processing device and the storage device to another processing apparatus while the board is locked to the casing by the locking mechanism.

US Pat. No. 10,482,925

FRAME SELECTION OF VIDEO DATA

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:receiving sampled video data associated with first video data that has a first frame rate, wherein the sampled video data has a second frame rate lower than the first frame rate;
determining, by at least one device, a plurality of image features, wherein a first image feature of the plurality of image features corresponds to a first video frame in the sampled video data;
determining transition points in the sample video data using the plurality of image features, wherein a first transition point of the transition points corresponds to an end of a first series of contiguous video frames and a beginning of a second series of contiguous video frames;
selecting a first portion of the sampled video data based on the first transition point;
determining that the first video frame is included in the first portion;
determining a second image feature that corresponds to the first video frame;
determining, based on the second image feature, a first image quality score that corresponds to the first video frame; and
storing the first image quality score in an annotation database.

US Pat. No. 10,482,923

RECORDING MEDIUM, PLAYBACK DEVICE, AND PLAYBACK METHOD

PANASONIC INTELLECTUAL PR...

1. A non-transitory computer-readable medium, in which are recordeda base video stream that is encoded video information,
an enhanced video stream that is encoded video information, for enhancing luminance of the base video stream by being played synchronously with the base video stream, and
a management information file in which is described a playback path of the base video stream,
wherein a playback path of the enhanced video stream is further described in the management information file so that the enhanced video stream is played synchronously with the base video stream,
wherein the base video stream includes High Dynamic Range (HDR), and
wherein the enhanced video stream, by being played synchronously with the base video stream, realizes a higher luminance than the base video stream.

US Pat. No. 10,482,922

DATA RECORDING METHOD AND APPARATUS

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:in a pass of a magnetic tape through a tape drive,
writing first data to a location on a first data track of the magnetic tape, the first data track partially overlapping a portion of an adjacent data track on the magnetic tape;
verifying that the first data is correctly written to the magnetic tape by reading second data from the location on the first data track and verifying that the first data matches the second data; and
verifying that data on a non-overlapped portion of the adjacent track is recoverable by reading third data from the non-overlapped portion of the adjacent data track.

US Pat. No. 10,482,921

ERROR DETECTION CODE HOLD PATTERN SYNCHRONIZATION

Micron Technology, Inc., ...

1. A method, comprising:detecting a first scenario, comprising an initialization phase of a memory device, an impending end of an error correction checksum data delivery burst, or both;
upon detection of the first scenario:
asserting an error detection code (EDC) hold reset; and
de-asserting the EDC hold reset synchronous to a rising edge of a command clock (CK_t clock), such that when transmission of an EDC hold pattern from data path circuitry timed to a data path clock (WCK_t) having a WCK_t frequency different than a CK_t frequency of the CK_t clock is triggered based upon a falling edge of the EDC hold reset, the transmission is synchronous to the rising edge of the CK_t clock.

US Pat. No. 10,482,918

CHANGING BIT SPACING FOR SELECTED SYMBOLS WRITTEN TO A MAGNETIC RECORDING MEDIUM

Seagate Technology LLC, ...

1. A method, comprising:writing a plurality of different symbols to a magnetic recording medium at a nominal bit timing;
determining a first set of the symbols that result in a relatively high error when read back;
upon writing subsequent to the determining of the first set of symbols, identifying one symbol of the first, set of symbols within a data segment ready to be mitten to the magnetic recording medium; and
writing the data segment with increased bit spacing relative to the nominal bit timing in response to identifying that the one symbol of the first set of symbols is within the data segment.

US Pat. No. 10,482,917

EFFICIENT JUST-IN-TIME TRANSCODING BY PARAMETER EXTRACTION

ARRIS Enterprises LLC, S...

1. A method for performing video encoding for storage comprising:providing super-encoding to compute an efficient compressed stream for storage for a single layer first resolution video; and
computing metadata that reduces the computational load for subsequent Just In Time (JIT) transcoding the stored first resolution video as part of the super-encoding to a single layer second resolution video and storing the metadata with the compressed stream,
wherein the metadata targets the largest computational load of transcoding.

US Pat. No. 10,482,912

MICROWAVE-ASSISTED MAGNETIC RECORDING APPARATUS AND METHOD

Seagate Technology LLC, ...

1. An apparatus, comprising:a magnetic recording medium having a recording surface comprising a plurality of recording layers each having a different ferromagnetic resonant frequency; and
a recording head arrangement configured for microwave-assisted magnetic recording (MAMR) and writing user data to a first recording layer of the plurality of recording layers, the recording head arrangement comprising:
a write pole configured to generate a write magnetic field; and
a write-assist arrangement proximate the write pole, the write-assist arrangement configured to generate a radiofrequency assist magnetic field at a frequency that corresponds to a first ferromagnetic resonant frequency of the first recording layer.

US Pat. No. 10,482,909

DUAL STAGE ACTUATED SUSPENSION HAVING SHEAR-MODE PZT ACTUATORS FOR ROTATING GIMBAL TONGUE

Magnecomp Corporation, M...

1. A flexure comprising:a proximal end and a distal end, the distal end is opposite the proximal end;
a gimbal tongue at the distal end of the flexure, the gimbal tongue configured to receive a head slider for writing data to, and reading data from, a moving data medium containing a plurality of data tracks thereon;
first and second flexible outrigger arms extending on respective lateral sides of the flexure from a relatively fixed portion of the flexure adjacent to the proximal end, and extending to the gimbal tongue; and
a first shear-mode piezoelectric device mounted at a distal end of the first flexible outrigger arm opposite of the relatively fixed portion of the flexure, the first shear-mode piezoelectric device having a top surface, a bottom surface, and two electrodes, the top surface moving in a linear shear direction relative to the bottom surface when an actuation voltage is applied across the electrodes; and
a mechanical coupling that, in response to the piezoelectric device being activated, couples the shear movement of the piezoelectric device to rotational movement of the head slider.

US Pat. No. 10,482,908

PERFORMANCE MONITORING OF A NEAR-FIELD TRANSDUCER OF A HEAT-ASSISTED MAGNETIC RECORDING SLIDER

Seagate Technology LLC, ...

1. A method, comprising:moving a slider configured for heat-assisted magnetic recording relative to and spaced apart from a magnetic recording medium, the slider comprising a writer, a writer heater, a thermal sensor, and a near-field transducer (NFT), the sensor situated on the slider so as to be substantially insensitive to heat conducted from the NFT to the sensor;
measuring, while the NFT generates heat when writing to the medium, back-heating from the medium not confounded by heat from the NFT using the thermal sensor; and
generating an output signal indicative of NFT performance degradation in response to the back-heating measurements.

US Pat. No. 10,482,904

CONTEXT DRIVEN DEVICE ARBITRATION

Amazon Technologies, Inc....

1. A system comprising:one or more processors;
computer-readable media storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
receiving, from a first speech interface device, a first audio signal representing a speech utterance of a user captured by a first microphone associated with the first speech interface device;
receiving, from the first speech interface device, first metadata associated with the first speech interface device, wherein the first metadata indicates a first device state of the first speech interface device;
receiving, from a second speech interface device, a second audio signal representing the speech utterance of the user captured by a second microphone associated with the second speech interface device;
receiving, from the second speech interface device, second metadata associated with the second speech interface device, wherein the second metadata indicates a second device state of the second speech interface device;
determining, from the first device state and the second device state, a first confidence score for the first speech interface device, wherein the first confidence score represents a first likelihood that the first speech interface device perform an action responsive to the speech utterance;
determining, from the first device state and the second device state, a second confidence score for the second speech interface device, wherein the second confidence score represents a second likelihood that the second speech interface device perform the action responsive to the speech utterance;
determining, based at least in part on one of the first confidence score or the second confidence score, that the first speech interface device is to perform the action responsive to the speech utterance;
generating response data representing the action responsive to the speech utterance; and
sending, to the first speech interface device, the response data.

US Pat. No. 10,482,903

METHOD, DEVICE AND APPARATUS FOR SELECTIVELY INTERACTING WITH MULTI-DEVICES, AND COMPUTER-READABLE MEDIUM

BAIDU ONLINE NETWORK TECH...

1. A method for selectively interacting with multi-devices, comprising:receiving voice information from a plurality of terminal devices, wherein the voice information from the plurality of terminal devices comprises an identical wake-up word;
performing voice recognition on the received voice information;
calculating an energy value of the wake-up word in the voice information from the plurality of terminal devices; and
comparing the energy values of the wake-up word, and transmitting feedback information to the terminal devices according to an energy comparison result and a voice recognition result,
wherein before the receiving voice information from a plurality of terminal devices, the method further comprises: calibrating recording performances of the plurality of terminal devices, wherein the calibrating comprises:
transmitting a play request for a standard speech to the plurality of terminal devices, wherein the standard speech is played and recorded by the plurality of terminal devices; and
receiving recordings uploaded by the plurality of terminal devices, acquiring the recording performances of the respective terminal devices based on the received recordings, and setting recording performance coefficients for the respective terminal devices.

US Pat. No. 10,482,902

METHOD AND SYSTEM TO EVALUATE AND QUANTIFY USER-EXPERIENCE (UX) FEEDBACK

Martin Benjamin Seider, ...

1. A computer-implemented method to evaluate and quantify user-experience (UX) feedback in response to a user-interface presentation (e.g., a themed ringtone), the method comprising:generating, by a processor of a computing device, via one or more speakers of, or connected to, the computing device, a multimedia output of a plurality of selectable multimedia outputs accessible from the computing device, wherein the multimedia output comprises an audio output associated with a stored audio file, and wherein the multimedia output is generated upon receipt of an electronic communication or notification at the computing device;
recording, by the processor, via one or more microphones of, or connected to, the computing device, an audio stream as part of a user-experience (UX) feedback to the user-interface presentation, wherein the audio stream is recorded immediately following, and/or during, the audio output being generated, and wherein the audio stream is recorded as an audio file or as a cached data;
determining, by the processor, a spectrum profile of each, or a substantial portion, of a plurality of audio segments of the recorded audio file or the cached data; and
determining, by the processor, a matrix comprising the plurality of spectrum profiles for each of the plurality of audio segments and providing the matrix to a machine learning operation configured to analyze the user-experience (UX) feedback, wherein the matrix is used as an input for the machine learning operation configured with weights specific to the multimedia output to evaluate and quantify user-experience (UX) feedback of the multimedia output.

US Pat. No. 10,482,901

SYSTEM AND METHOD FOR BEEP DETECTION AND INTERPRETATION

Alarm.com Incorporated, ...

1. A monitoring system for monitoring a property, the monitoring system comprising:one or more processors; and
one or more storage devices, the one or more storage devices storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
obtaining, by the monitoring system, sound data of audio sounds detected by a microphone that is located at the property;
determining, by the monitoring system, whether the sound data includes data representing one or more audio tones generated by a device;
based on determining that the obtained sound data includes one or more audio tones generated by a device, generating, by the monitoring system, an audio fingerprint of the sound data;
generating, by the monitoring system, a query that includes the generated audio fingerprint as a search parameter;
obtaining, by the monitoring system and in response to the generated query, (i) a device identifier of the device that generated the one or more audio tones and (ii) a state of the device that generated the one or more audio tones; and
performing, by the monitoring system, one or more operations based on at least one of the device identifier and the state of the device that generated the one or more audio tones.

US Pat. No. 10,482,900

ORGANIZATION OF SIGNAL SEGMENTS SUPPORTING SENSED FEATURES

Microsoft Technology Lice...

1. A computing system for performing a method for managing sensed signals used to sense features of physical entities over time, the system comprising:one or more processors;
one or more computer-readable media having thereon computer-executable instructions that, when executed by the one or more processors, cause the computing system to perform the method for managing sensed signals used to sense features of physical entities over time, the method comprising:
creating a computer-navigable graph of a plurality of sensed features of a plurality of sensed physical entities over a plurality of times, the sensed features determined from analysis of sensor signals observed of the plurality of sensed physical entities; and
for at least one of the sensed features of at least one of the sensed plurality of entities, associating within the computer-navigable graph a signal segment with the at least one sensed feature such that computer-navigation to the sensed feature also allows for computer-navigation to the signal segment, wherein the associated signal segment is a particular signal segment of the at least one sensed entity which had been analyzed to determine the at least one sensed feature.

US Pat. No. 10,482,898

SYSTEM FOR ROBOT TO ELIMINATE OWN SOUND SOURCE

YUTOU TECHNOLOGY (HANGZHO...

1. A system for robot to eliminate own sound source, comprising:a pickup unit, for collecting digital signals mixed with left and right channels and outputting;
a sound card drive unit, connecting to said pickup unit, for mixing the received reference signals of sound source of the robot itself with the digital signals mixed with left and right channels to form mixed speech signals and outputting;
a signal separation unit, connecting to said sound card drive unit, for separating the mixed speech signals into the digital signals mixed with left and right channels and the reference signals, and judging whether interference signals existing in the digital signals mixed with left and right channels, and acquiring playing semaphores and outputting the digital signals mixed with left and right channels and the reference signals and the playing semaphores; when the system plays music, the playing semaphores are set to True, when the systems don't play music, the playing semaphores are set to False;
a sound source elimination unit, connecting to said signal separation unit, for receiving reference signals, playing semaphores and digital signals mixed with left and right channels, and eliminating interference signals in the digital signals mixed with left and right channels according to the semaphores, and outputting; and
a recognition unit, connecting to said sound source elimination unit, for recognizing digital signals mixed with left and right channels.

US Pat. No. 10,482,897

BIOLOGICAL SOUND ANALYZING APPARATUS, BIOLOGICAL SOUND ANALYZING METHOD, COMPUTER PROGRAM, AND RECORDING MEDIUM

PIONEER CORPORATION, Tok...

1. A biological sound analyzing apparatus comprising:a sensor configured to obtain first biological sound information, which indicates a change in biological sounds with time;
a processor configured to generate second biological sound information by performing a first process of enhancing first noise information, which indicates noise included in the biological sounds, on the first biological sound information;
a calculator configured to calculate correlation information, which indicates a correlation in adjacent periods of the second biological sound information; and
a display device configured to output second noise information, which indicates continuous noise included in the biological sounds, on the basis of the correlation coefficient.

US Pat. No. 10,482,896

MULTI-BAND NOISE REDUCTION SYSTEM AND METHODOLOGY FOR DIGITAL AUDIO SIGNALS

Retune DSP ApS, Kongens ...

1. A hearing instrument comprising:a microphone arrangement for picking-up acoustic signals from the surrounding environment and generating one or more microphone signals in response; and
a multi-band noise reduction system for digital audio signals comprising:
a signal input for receipt of a digital audio input signal originating from the one or more microphone signals, an analysis filter bank configured for dividing the digital audio input signal into a plurality of sub-band signals Yk(n),
a noise estimator configured for determining respective sub-band noise estimates ?k2(n) of the plurality of sub-band signals Yk(n),
a first signal-to-noise ratio estimator configured for determining respective first signal-to-noise ratio estimates ?k0(n) of the plurality of sub-band signals based on the respective sub-band noise estimation signals and the respective sub-band signals Yk(n),
a second signal-to-noise ratio estimator configured for filtering the plurality of first signal-to-noise ratio estimates ?k0(n) of the plurality of sub-band signals Yk(n) with respective time-varying low-pass filters to produce respective second signal-to-noise ratio estimates ?k(n) of the plurality of sub-band signals Yk(n) wherein a low-pass cut-off frequency of each of the time-varying low-pass filters is adaptable in accordance with the first signal-to-noise ratio estimate of the sub-band signal or the second signal-to-noise ratio estimate of the sub-band signal,
a gain calculator configured for applying respective time-varying gains Gk (n) to the plurality of sub-band signals Yk(n) based on the respective second signal-to-noise ratio estimates ?k(n) and respective sub-band gain laws to produce a plurality of noise compensated sub-band signals, and
a synthesis filter bank configured to combine the plurality of noise compensated sub-band signals into a noise reduced digital audio output signal at a signal output.

US Pat. No. 10,482,893

SOUND PROCESSING METHOD AND SOUND PROCESSING APPARATUS

YAMAHA CORPORATION, Hama...

1. A sound processing method comprising:supplying an acoustic signal;
improving a sound quality of the supplied acoustic signal by:
applying a nonlinear filter to a temporal sequence of original spectral envelope of the supplied acoustic signal to smooth fine temporal perturbation of the original spectral envelope without smoothing out a larger temporal change of the original spectral envelope; and
adjusting the supplied acoustic signal having the original spectral envelope using a temporal sequence of spectral envelope smoothed by the nonlinear filter to generate an acoustic signal having the spectral envelope in which the fine temporal perturbation has been smoothed; and
outputting the acoustic signal having the spectral envelope in which the fine temporal perturbation has been smoothed.

US Pat. No. 10,482,890

DETERMINING MEDIA DEVICE ACTIVATION BASED ON FREQUENCY RESPONSE ANALYSIS

The Nielsen Company (US),...

1. A meter to monitor a media device, the meter comprising:a microphone to sense audio;
a device activation detector to:
reuse first frequency values of the sensed audio to determine a first frequency response of the sensed audio, the first frequency values having been determined to perform watermark detection during a first monitoring time interval;
compare the first frequency response to a reference frequency response to determine whether the media device was active during the first monitoring time interval; and
control operation of the meter based on the determination of whether the media device was active during the first monitoring time interval; and
a data reporter to output a device activity determination indicating whether the media device was active during the first monitoring time interval.

US Pat. No. 10,482,889

AUDIO SIGNAL PROCESSING APPARATUSES AND METHODS

HUAWEI TECHNOLOGIES CO., ...

1. An audio signal downmixing apparatus (105) for processing an input audio signal including a plurality of input channels (113), comprising:an auxiliary downmix matrix determiner (107) configured to determine an auxiliary downmix matrix (DW) by:
computing a plurality of eigenvectors of a covariance matrix (COV) defined by the plurality of input channels (113) of the input audio signal;
determining for at least one eigenvector of the plurality of eigenvectors of the covariance matrix (COV) a subspace angle between the at least one eigenvector and a vector defined by a column of a primary downmix matrix (DU);
selecting at least one eigenvector from the plurality of eigenvectors based on the subspace angle and a preset threshold angle ?MIN; and
defining at least one column of the auxiliary downmix matrix (DW) by the at least one selected eigenvector; and
a processor (109) configured to process the input audio signal into an output audio signal including a plurality of primary output channels (123) and at least one auxiliary output channel (125) using a downmix matrix (D), wherein the downmix matrix (D) includes the primary downmix matrix (DU) for providing the plurality of primary output channels (123) and the auxiliary downmix matrix (DW) for providing the at least one auxiliary output channel (125).

US Pat. No. 10,482,885

SPEAKER BASED ANAPHORA RESOLUTION

Amazon Technologies, Inc....

1. A computer-implemented method comprising:receiving, at a first time and from a first speech-controlled device, first input audio data corresponding to a first utterance;
processing the first input audio data to determine that the first utterance was spoken by a first speaker;
performing automatic speech recognition on the first input audio data to obtain first text data;
processing the first text data to determine that the first text data includes a name of a first person;
storing association data associating between a first speaker identifier (ID) associated with the first speaker, a first device ID associated with the first speech-controlled device, and a first entity ID associated with the first person;
receiving, at a second time after the first time and from a second speech-controlled device, second input audio data corresponding to a second utterance;
processing the second input audio data to determine that the second utterance was spoken by the first speaker;
associating the second input audio data with the first speaker ID;
performing automatic speech recognition on the second input audio data to obtain second text data;
determining that the second text data includes a pronoun that refers to an entity that is not named in the second text data;
identifying the association data using the first speaker ID;
determining that the association data associates the first speaker ID and the first entity ID;
determining a length of time between the first time and the second time;
determining, based on the length of time, a score corresponding to a likelihood of the pronoun referring to the first person;
determining the score is within a threshold;
in response to determining that the score is within the threshold, associating the first entity ID with the pronoun; and
causing a command to be executed using the first entity ID and the second text data, wherein the pronoun is replaced by the name of the first person in the second text data.

US Pat. No. 10,482,884

OUTCOME-ORIENTED DIALOGS ON A SPEECH RECOGNITION PLATFORM

Amazon Technologies, Inc....

1. A system comprising:one or more processors; and
one or more computer-readable media storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
receiving first audio data representing a request;
determining, based at least in part on the first audio data, first intent data representing a first intent associated with the request, the first intent associated with one or more slots;
determining, based at least in part on the first audio data, second intent data representing a second intent associated with the request;
determining a first number of values associated with the first intent;
determining a second number of values associated with the second intent;
selecting the first intent based at least in part on the first number of values being more favorable than the second number of values;
determining that a slot of the one or more slots is unfilled;
generating, based at least in part on the slot being unfilled, second audio data representing a query for additional information;
sending the second audio data to a device to output audio corresponding to the second audio data;
receiving third audio data representing a response to the query; and
associating a value with the slot based at least in part on the third audio data.

US Pat. No. 10,482,880

COMMAND AND CONTROL OF DEVICES AND APPLICATIONS BY VOICE USING A COMMUNICATION BASE SYSTEM

CenturyLink Intellectual ...

13. A device control system comprising;a first device;
a second device; and
a base station storing computer executable instructions for wirelessly controlling the second device using voice-commands that, when executed, cause the base station to:
establish a wireless communication path directly between the first device and the base station;
establish a second wireless communication path between the base station and the second device;
receive a communication from the first device;
identify, with a command processing module, during the communication from the first device, a speech pattern as including a voice-command by detecting an address word, wherein the address word is associated with the base station and is unassociated with the voice-command;
determine a second device operation corresponding to the voice-command; and
communicate a command corresponding to the second device operation to the second device.

US Pat. No. 10,482,879

WAKE-ON-VOICE METHOD AND DEVICE

BAIDU ONLINE NETWORK TECH...

1. A wake-on-voice method, comprising:obtaining a voice inputted by a user;
processing data frames of the voice with a frame skipping strategy and performing a voice activity detection on the data frames through a time-domain energy algorithm;
extracting an acoustic feature of the voice and performing a voice recognition on the acoustic feature according to a preset recognition network and an acoustic model; and
performing an operation corresponding to the voice if the voice is a preset wake-up word in the preset recognition network;
stopping the voice recognition according to a preset refusal strategy via:
judging whether a weighted sum of a voice length obtained by the voice activity detection and a number of junk words is greater than a fourth preset threshold, and
determining that wake-up is failed and stopping the voice recognition, when the weighted sum is greater than the fourth preset threshold,
determining junk words by a cluster algorithm based on edit distance, comprising:
connecting all syllables in parallel to form a candidate recognition network;
performing a recognition on a preset voice training set according to the candidate recognition network and obtaining recognized results, wherein a number of the recognized results is greater than a first preset threshold;
selecting a plurality of syllables from all the syllables to form a candidate set of syllables according to the recognized results, wherein a number of recognized results corresponding to any syllable included in the candidate set is greater than that of recognized results corresponding to each syllable not included in the candidate set;
obtaining a first syllable from the number of recognized results, the first syllable corresponding to a largest number of recognized results from the candidate set, saving the first syllable into a junk word set and removing the first syllable from the candidate set;
(i) computing an edit distance between a syllable last saved into the junk word set and from each remaining syllable of the candidate set respectively, (ii) saving a syllable Bk into the junk word set, the syllable Bk having a maximum edit distance between the syllable Bk and the first syllable, and (iii) removing the syllable Bk from the candidate set, and
iteratively for each remaining syllable in the candidate set, repeating the acts of (i) computing, (ii) saving, and (iii) removing until a number of syllables in the junk word set satisfies a second preset threshold; and
configuring the syllables in the junk word set as the junk words of the candidate recognition network.

US Pat. No. 10,482,877

REMOTE SENSOR VOICE RECOGNITION

Hewlett-Packard Developme...

1. A computing device comprising:a processor; and
a non-transitory computer readable medium coupled to the processor and comprising instructions that when executed by the processor cause the processor to:
establish a bi-directional wireless communication link between the computing device and a remote sensor comprising a speaker and a microphone, the remote sensor separate from the computing device;
transmit a first audio signal to the remote sensor for playback on the speaker;
receive a second audio signal from the microphone in the remote sensor;
process the second audio signal to generate a processed audio signal;
send the processed audio signal to a voice recognition routine to recognize a voice command within the processed audio signal; and
initiate an automation command controlling the first audio signal transmitted to the remote sensor for playback on the speaker, based on the recognized voice command,
wherein the processor is to process the second audio signal to generate the processed audio signal by:
detecting the first audio signal within the second audio signal;
determining a time delay between the first audio signal as transmitted to the remote sensor and the first audio signal as detected within the second audio signal;
time-shifting the first audio signal as detected within the second audio signal according to the determined time delay; and
subtracting the time-shifted first audio signal as detected within the second audio signal from the second audio signal,
and wherein the computing device is to both transmit the first audio signal to the remote sensor and receive back the second audio signal from the remote sensor.

US Pat. No. 10,482,876

HIERARCHICAL SPEECH RECOGNITION DECODER

Interactions LLC, Frankl...

1. A computer-implemented method, comprising:receiving, over a computer network, an utterance of a user, the utterance having been accepted from the user at a client device as spoken input;
storing the utterance, the storing comprising identifying a plurality of sub-expressions by applying a parameterized statistical model that determines likely n-grams of literal word tokens and concept placeholders included in the utterance and storing each of the sub-expressions in the data structure as either: a set of literal word tokens representing the sub-expression, or a concept placeholder representing the sub-expression and providing an indication of a language sub-model;
determining likely textual representations of the sub-expressions stored as concept placeholders by applying the indicated language sub-models to the sub-expressions;
generating a user-specific textual interpretation of the utterance, the textual interpretation being a combination of the literal word tokens and the determined likely textual representations of the sub-expressions.

US Pat. No. 10,482,874

HIERARCHICAL BELIEF STATES FOR DIGITAL ASSISTANTS

Apple Inc., Cupertino, C...

1. An electronic device, comprising:one or more processors;
a memory; and
one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for:
receiving a user utterance of a dialogue;
parsing one or more text representations of the user utterance to determine a plurality of semantic interpretations for the user utterance, the plurality of semantic interpretations including more than two concepts or properties, wherein the parsing includes determining that a first concept or property and a second concept or property in the more than two concepts or properties have a joint semantic relationship;
determining, based on the plurality of semantic interpretations, a belief state for the dialogue, the belief state comprising a plurality of dialogue slots representing the more than two concepts or properties, wherein each dialogue slot of the plurality of dialogue slots includes a respective marginal certainty for a respective concept or property represented by the respective dialogue slot, and wherein a first dialogue slot of the plurality of dialogue slots further includes a joint certainty for the first concept or property and the second concept or property based on the determined joint semantic relationship;
determining a plurality of candidate policy actions from the determined belief state;
selecting, based on the marginal certainty of each dialogue slot of the plurality of dialogue slots and the joint certainty, a policy action from the plurality of candidate policy actions; and
performing the selected policy action, including outputting results of the policy action for presentation.

US Pat. No. 10,482,873

ASYNCHRONOUS OPTIMIZATION FOR SEQUENCE TRAINING OF NEURAL NETWORKS

Google LLC, Mountain Vie...

1. A method performed by one or more computing devices, the method comprising:obtaining multiple copies of a neural network of a speech model;
asynchronously obtaining parameter values for the multiple copies of the neural network such that different copies of the neural network have different sets of parameter values;
after obtaining the parameter values such that different copies of the neural network have different sets of parameter values, training the multiple copies of the neural network in parallel using different subsets of a set of training data, wherein training each copy of the neural network adjusts the parameter values for the copy of the neural network to generate adjusted parameter values; and
updating the neural network of the speech model based on the adjusted parameter values generated for each of the multiple copies of the neural network.

US Pat. No. 10,482,872

SPEECH RECOGNITION APPARATUS AND SPEECH RECOGNITION METHOD

Olympus Corporation, Tok...

1. A speech recognition apparatus comprising:a microphone configured to acquire an audio stream in which speech vocalized by a person is recorded;
a camera configured to acquire an image data in which at least a mouth of the person is captured;
an operation element configured to recognize speech including a consonant vocalized by the person based on the audio stream, estimate the consonant vocalized by the person based on a mouth shape of the person in the image data, and specify the consonant based on the estimated consonant and the speech-recognized consonant,
wherein the operation element specifies a consonant vocalization frame which is a frame in which it is estimated that the person in the image data has vocalized a consonant before a vowel based on a timing when the vowel is detected, and estimates the consonant vocalized by the person based on the mouth shape of the person in the consonant vocalization frame and a mouth shape model that indicates a change in mouth shape for each consonant.

US Pat. No. 10,482,870

SOUND-PROCESSING APPARATUS AND SOUND-PROCESSING METHOD

NANJING HORIZON ROBOTICS ...

1. A sound-processing apparatus comprising:at least one pair of sound transducers, each pair of sound transducers including
a. a first sound transducer for receiving an audio source signal and outputting a first sound signal according to the audio source signal; and
b. a second sound transducer for receiving the audio source signal and outputting a second sound signal according to the audio source signal,
c. the second sound signal having an opposite phase from the first sound signal, and difference between an amplitude of the second sound signal and an amplitude of the first sound signal being less than or equal to an amplitude threshold value; and
a sound acquisition device for acquiring a sound signal, path-characteristic difference between an amplitude-frequency characteristic of a first sound path from the first sound transducer to the sound acquisition device and an amplitude-frequency characteristic of a second sound path from the second sound transducer to the sound acquisition device being less than or equal to a first characteristic threshold value.

US Pat. No. 10,482,865

VIBRATION DAMPED SOUND SHIELD

THE HONG KONG UNIVERSITY ...

1. An acoustic/vibrational energy absorption metamaterial comprising:a substantially air impermeable flexible sheet (203); and
a plurality of dampers (101) fixed to the flexible sheet, at least a subset of the dampers comprising:
an enclosed planar frame (103);
an flexible, membrane (105) attached to said frame; and
at least one rigid or semi-rigid mass or platelet (107) having an asymmetrical shape when taken in a plan view facing the thin sheet and fixedly attached to said flexible membrane by an asymmetrical hinge attachment so as to induce a flapping motion about the hinge attachment, the masses or platelets providing a restoring force exerting by the flexible membrane upon displacement of the dampers on the sheet, wherein at least a subset of the dampers present plural resonant modes with tunable resonant frequencies.

US Pat. No. 10,482,864

PORTABLE ACOUSTICAL BLOCKING SYSTEM

L.J. AVALON LLC, Tampa, ...

1. A portable acoustical blocking system for use with a support, comprising:a sheet of acoustical blocking material having a first and a second side and bound by material edge;
said sheet of acoustical blocking material having a thickness of approximately one-eighth of an inch and a density of greater than one pound per square foot;
a flexible reinforcing tape permanently affixed to said first side of said sheet of acoustical blocking material adjacent to said material edge;
a plurality of hangers secured to said sheet of acoustical blocking material and extending through said reinforcing tape and said sheet of acoustical blocking material for hanging said sheet of acoustical blocking material from the support for inhibiting the flow of acoustic energy between said first and second sides of the acoustical blocking material; and
said sheet of acoustical blocking material and said reinforcing tape being flexible for enabling the entire portable acoustical blocking system including said sheet of acoustical blocking material and reinforcing tape to be rolled as a single unit for transportation.

US Pat. No. 10,482,863

METHODS AND APPARATUS TO EXTRACT A PITCH-INDEPENDENT TIMBRE ATTRIBUTE FROM A MEDIA SIGNAL

THE NIELSEN COMPANY (US),...

1. An apparatus comprising:an interface to receive a media signal;
a timbre database to store reference pitch-less timbre spectrums; and
one or more processors to:
compare a pitch-less timbre spectrum of the media signal to the reference pitch-less timbre spectrums; and
classify the media signal based on data corresponding to a reference pitch-less timbre spectrum of the reference pitch-less timbre spectrums that matches the pitch-less timbre spectrum, the classification corresponding to at least one of an instrument or a genre.

US Pat. No. 10,482,862

COMPUTER IMPLEMENTED METHOD FOR PROVIDING AUGMENTED REALITY (AR) FUNCTION REGARDING MUSIC TRACK

YOUSICIAN OY, Helsinki (...

1. A computer implemented method for providing an augmented reality (AR) function, comprising:receiving input information of a music track and an instrument;
determining attribute information of the music track based on the received input information, the attribute information comprising data for a user to play the music track with the instrument;
receiving real time content of audiovisual (AV) input signals using at least one capturing device;
the real time content comprising visual information that corresponds to a view regarding at least one user limb and the instrument comprising a plurality of user operable elements;
generating augmented reality (AR) instruction information based on the attribute information of the music track, the augmented reality (AR) instruction information comprising a plurality of layers;
generating augmented reality (AR) visual information by applying the augmented reality (AR) instruction information to the visual information so that a first layer of the augmented reality (AR) instruction information is applied above at least a portion of the visual information; and
causing a display of the generated augmented reality visual information.

US Pat. No. 10,482,861

REACTION FORCE GENERATOR AND KEYBOARD DEVICE OF ELECTRONIC MUSICAL INSTRUMENT

YAMAHA CORPORATION, Hama...

1. A reaction force generator that is disposed on a base surface comprising:an elastic structure; and
a dome that is made of an elastic member, and includes a portion bulging toward the base surface and includes at least an after stroke portion and a click generating portion,
wherein:
a reaction force is generated by elastic deformation of the elastic structure and the dome in a pressing process in which the elastic structure is pressed, and the after stroke portion and the click generating portion are both inclined with respect to the direction of pressing in the dome,
the click generating portion has one end connected to the after stroke portion, and a degree of inclination of a thick portion between both ends of the click generating portion with respect to the direction of pressing is larger than a degree of inclination of the after stroke portion with respect to the direction of pressing,
the dome starts to deform once a distal end portion of the dome comes into contact with the base surface after the elastic structure starts to deform in the pressing process,
the click generating portion undergoes buckling in the pressing process to cause a sudden decrease in a reaction force and generate a click feeling, the click generating portion causing a sudden increase in an amount of deformation prior to the after stroke portion, and
the amount of deformation of the after stroke portion increases rapidly after the click generating portion undergoes buckling.

US Pat. No. 10,482,860

KEYBOARD INSTRUMENT AND METHOD

CASIO COMPUTER CO., LTD.,...

1. A keyboard instrument comprising:a keyboard that includes a first key specifying a first pitch, a second key specifying a second pitch and a third key specifying a third pitch, when operated, wherein
the first key is associated with first section data corresponding to a first section among a plurality of sections in a piece of music, the first section data includes at least two notes and corresponds to a first period from a first timing to a second timing of the piece of music,
the second key is associated with second section data corresponding to a second section following the first section among the plurality of sections in the piece of music, the second section data includes at least two notes and corresponds to a second period from the second timing to a third timing of the piece of music, and
the third key is not associated with any section data corresponding to any section among the plurality of sections in the piece of music, and
at least one processor electrically connected to the keyboard, wherein the at least one processor is configured to:
display at least one identifier such that the first key and the second key are distinguishable from the third key;
output the first section data as a musical sound when the first key is operated; and
output the second section data as a musical sound when the second key is operated.

US Pat. No. 10,482,858

GENERATION AND TRANSMISSION OF MUSICAL PERFORMANCE DATA

ROLAND VS LLC, Snohomish...

1. A method of capturing musical performance data, the method comprising:generating, by a musical input device comprising a processor, a first command encoding a first musical event;
generating, by the musical input device, a first message corresponding to the first command, wherein the first message encodes a first acoustic attribute type of the first musical event and a first acoustic attribute value, wherein the first acoustic attribute value specifies a first value of the first acoustic attribute type;
generating, by the musical input device, a second message corresponding to the first command, wherein the second message encodes a second acoustic attribute type of the first musical event and a second acoustic attribute value, wherein the second acoustic attribute value specifies a second value of the second acoustic attribute type;
generating, by the musical input device, timestamp data denoting a time of an occurrence of the first musical event, the timestamp data corresponding to the first message and the second message; and
sending the timestamp data, the first command, the first message, and the second message to a computing device.

US Pat. No. 10,482,857

MEDIA-MEDIA AUGMENTATION SYSTEM AND METHOD OF COMPOSING A MEDIA PRODUCT

MASHTRAXX LIMITED, Warwi...

1. A media-content augmentation system comprising:a database containing a multiplicity of media files and associated metadata, each media file or part thereof mapped to at least one contextual theme defined by beginning and end timings;
a processing system coupled to the database and responsive to said metadata; and
an input coupled to the processing system, the input in the form of temporally-varying events data;
wherein the processing system is arranged:
to resolve the input into one or more of a plurality of categorized contextual themes;
to correlate said categorized contextual themes with metadata associated with selected media files or part thereof relevant to the one or more of the plurality of categorized contextual themes, and thereafter
to splice or fade together selected media files or part thereof to reflect said events as the input varies with time, thereby to generate, as an output, a media product in which transitions between media files or parts thereof are aligned with the temporally-varying events and wherein said temporarily-varying events take the form of one of:
a beginning and an end in the case of a sustained feature for the contextual theme, wherein the sustained features is one of a form function and a hit point over time; and
a specific point in time for a hit point.

US Pat. No. 10,482,854

HYBRID SNARE DRUM STICK

Freer Precussion LLC, Cl...

1. A drum stick for use by a percussionist comprising a first end section that includes a first threaded portion, a second end section that includes a second threaded portion, and a middle section interposed between and connected to the first end section and to the second end section, wherein the middle section is connected to the first threaded portion of the first end section and to the second threaded portion of the second end section by a threaded connection, wherein the first end section and the second end section are fabricated from a wood laminate material, and wherein the middle section is formed from a woven carbon material.

US Pat. No. 10,482,853

PAD RING RETAINER

1. A pad for a tonehole cover of a woodwind instrument comprising:a pad material;
a pad ring retainer, the pad ring retainer having a vertical wall surrounding a vertical edge of the pad material; and
wherein the pad ring retainer comprises a lower side with an inward taper extending inwardly from the vertical wall, the pad material abutting and being supported by the inward taper, the taper compressing the pad material.

US Pat. No. 10,482,851

KEY UNIT AND KEYBOARD INSTRUMENT

CASIO COMPUTER CO., LTD.,...

1. A keyboard instrument comprising:a plurality of key blocks, each key block including:
a plurality of key main bodies, each key main body having a top surface, and an area of the top surface abutting a first edge side of the key main body in a longitudinal direction being pressable by a user;
a plurality of connecting sections, respectively corresponding to the plurality of key main bodies, each connecting section being provided on a top surface side abutting a second edge side of the key main body in the longitudinal direction, and the connecting section being deformed in response to its respective key main body being pressed by the user; and
a supporting section which supports the plurality of key main bodies as one key block through the plurality of connecting sections; and
an instrument case which houses the plurality of key blocks,
wherein the supporting sections included in the plurality of key blocks are piled up in a direction intersecting with the longitudinal direction in the instrument case, and
wherein the plurality of connecting sections included in one key block and the plurality of connecting sections included in another key block overlap each other in the instrument case.

US Pat. No. 10,482,850

METHOD AND VIRTUAL REALITY DEVICE FOR IMPROVING IMAGE QUALITY

VIA ALLIANCE SEMICONDUCTO...

1. A method for improving image quality, comprising:receiving an image data and sensing information;
dividing the image data into areas corresponding to different resolutions according to first parameter information, wherein the different resolutions correspond to different frequencies;
rendering the areas in a single pass according to the sensing information and the different frequencies and outputting a rendered image data with the different resolutions; and
resolving the rendered image data with the different resolutions into a final output image data with a first resolution according to second parameter information,
wherein the method further comprising:
receiving time information from a time sensor;
estimating a finish time of a current frame according to the time information;
determining whether the finish time is before a video-synchronizing signal (Vsync); and
generating an instruction signal to adjust the resolution when the finish time cannot be before the Vsync.

US Pat. No. 10,482,849

APPARATUS AND METHOD FOR COMPOSITING IMAGE IN A PORTABLE TERMINAL

Samsung Electronics Co., ...

1. An apparatus for compositing images in a portable terminal, the apparatus comprising:a first camera;
a second camera;
a display; and
a processor configured to:
control the display to display a first image and a second image, wherein the first image and the second image are respectively obtained from the first camera and the second camera;
identify, in the displayed first image, a first touch input for selecting a first portion of the first image;
identify, in the displayed second image, a second touch input for selecting a second portion of the second image;
determine that the first portion and the second portion can be composed together by comparing shapes of the first portion and the second portion;
based on a determination that the first portion and the second portion have different shapes, adjust the first portion and the second portion so that the first portion and the second portion have the same shape; and
composite, in response to identifying the first touch input and the second touch input or in response to adjusting the first portion and the second portion, the first portion of the first image on the second portion of the second image such that a background of the second portion of the second image is a background of the first portion of the first image; and
display the composited image.

US Pat. No. 10,482,847

DRIVING METHOD AND DRIVING APPARATUS FOR DISPLAY PANEL, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A driving method for a display panel, the display panel having a first resolution, the driving method comprising:converting RGB signals of an input image having a second resolution into YUV signals corresponding to an output image, a resolution of the output image being not smaller than the second resolution;
converting the YUV signals into RGB signals corresponding to the output image;
converting the RGB signals corresponding to the output image into driving signals for driving the display panel; and
outputting the driving signals to the display panel,
wherein the converting the RGB signals of the input image having the second resolution into the YUV signals corresponding to the output image comprises:
segmenting the input image into N sub-image, N being a positive integer; and
converting RGB signals of each of the sub-images into a group of YUV signals, to obtain N groups of YUV signals,
wherein, in a case where the input image cannot be segmented into N sub-images having a same resolution, the segmenting the input image into N sub-images comprises:
segmenting the input image into N initial sub-images, the N initial sub-images including K first initial sub-images having a third resolution and (N-K) second initial sub-images having a fourth resolution, the third resolution being smaller than the fourth resolution, K being a positive integer and smaller than N; and
inserting a predetermined number of blank pixels at a predetermined position of the first initial sub-images, an amount of the blank pixels being equal to a difference between the fourth resolution and the third resolution.

US Pat. No. 10,482,846

DISPLAY DEVICE HAVING PROCESSOR THAT CONTROLS COMMUNICATION WITH EXTERNAL DEVICE, CONTROL METHOD FOR DISPLAY DEVICE, AND DISPLAY SYSTEM

SEIKO EPSON CORPORATION, ...

1. A display device comprising:a communication line configured to perform communication with an external display device;
a display configured to display an image corresponding to image information; and
a processor configured to cause the communication line to transmit first information to the external display device and, when waiting to receive second information from the external display device via the communication line after causing the communication line to transmit the first information to the external display device, prohibit the display from displaying the image for a first period and thereafter cause the display to display the image,
wherein the processor starts preparation for displaying the image according to power-on of the display device and, after the preparation is completed, causes the communication line to transmit the first information to the external display device, and
wherein, when the communication line has not received the second information for a second period after the processor prohibits the display section from displaying the image according to the transmission of the first information, the processor causes the display to display the image; when the communication line receives the second information before the second period elapses, the processor prohibits the display from displaying the image for the first period and thereafter causes the display to display the image; and, when the second information reaches the communication line after the second period elapses, the processor causes the display to maintain the display of the image.

US Pat. No. 10,482,844

METHOD TO IMPROVE DISPLAY PERFORMANCE AT EDGES OF CIRCULAR DISPLAY SCREEN

SHANGHAI TIANMA AM-OLED C...

1. A method for improving display performance at edges of a circular display screen, comprising:determining an edge area and a central area of the circular display screen, the edge area surrouding the central area;
along a direction from a geometric center of the circular display screen to the edge area of the circular display screen, dividing the edge area into n display regions each having a different luminance-level, where n is a positive integer larger than 1; and
according to luminance of pixels in the central area and the luminance-level of each of the n display regions, adjusting luminance of pixels in each of the n display regions to corresponding target luminance, wherein:
the pixels in each of the n display regions have different corresponding target luminance,
the pixels in a same display region have same corresponding target luminance, and
along the direction from the geometric center to the edge area of the circular display screen, the corresponding target luminance of each of the pixels in different display regions sequentially decreases and ratios between the corresponding target luminance of the pixels in the n display regions and the luminance of the pixels in the central area form an arithmetic sequence, and the arithmetic sequence has a common ratio of approximately ½.

US Pat. No. 10,482,840

DATA VOLTAGE ADJUSTING METHOD OF LIQUID CRYSTAL DISPLAY PANEL AND DEVICE

Shenzhen China Star Optoe...

1. A data voltage adjusting method of a liquid crystal display panel, comprising steps of:obtaining a total variation amount of data voltages on all data lines in the liquid crystal display panel;
calculating a maximum variation amount of the data voltages corresponding to a horizontal crosstalk index of the liquid crystal display panel, wherein the horizontal crosstalk index of the liquid crystal display panel presents a predetermined level of crosstalk exhibited on the liquid crystal display panel and the maximum variation amount of the data voltages indicates a variation amount of the data voltages of the data lines that causes the predetermined level of crosstalk on the liquid crystal display panel;
determining whether an absolute value of the total variation amount of the data voltages is larger than an absolute value of the maximum variation amount of the data voltages corresponding to the horizontal crosstalk index;
if yes, implementing a data voltage adjustment to data lines with data voltages having variations in the liquid crystal display panel according to the total variation amount of the data voltages;
wherein the step of obtaining the total variation amount of the data voltages on all the data lines in the liquid crystal display panel comprises:
obtaining a sum of positive variation amounts of the data voltages on all the data lines in the liquid crystal display panel;
obtaining a sum of negative variation amounts of the data voltages on all the data lines in the liquid crystal display panel;
calculating the total variation amount of the data voltages on all the data lines in the liquid crystal display panel according to the sum of the positive variation amounts of the data voltages and the sum of the negative variation amount of the data voltages by adding up the two sums.

US Pat. No. 10,482,839

LIQUID CRYSTAL DISPLAY APPARATUS WITH REDUCED HORIZONTAL CROSSTALK

LG Display Co., Ltd., Se...

1. A liquid crystal display apparatus, comprising:a liquid crystal display (LCD) panel including a plurality of sub-pixels configured to be operated by a gate signal provided from a gate driver via a gate line and an image signal provided from a data driver via a data line;
a driving circuit board, including:
a gamma voltage generator configured to supply gamma reference voltages for expressing gray levels to the data driver;
a power supply unit configured to supply a first high operating voltage (VDD) signal excluding a common voltage (Vcom) to the gamma voltage generator and a second VDD signal to the data driver; and
a horizontal crosstalk compensation circuit configured to filter a ripple of the first VDD signal supplied from the power supply unit on the driving circuit board such that voltage of the first VDD signal is stabilized to thereby reduce a level of crosstalk between the sub-pixels adjacent to one another; and
a flexible circuit board connecting the driving circuit board with the LCD panel,
wherein the data driver is on the flexible circuit board, and the gamma voltage generator supplies the gamma reference voltages to the flexible circuit board having the data driver thereon.

US Pat. No. 10,482,838

ACTIVE-MATRIX DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME

SHARP KABUSHIKI KAISHA, ...

1. An active-matrix display device comprising:a display portion including a plurality of data signal lines, a plurality of scanning signal lines crossing the data signal lines, and a plurality of pixel forming portions arranged in a matrix along the data signal lines and the scanning signal lines, at least two of the scanning signal lines being different in time constant from each other;
a scanning signal line driver circuit configured to generate a plurality of scanning signals respectively provided to the scanning signal lines;
a scanning clock generation circuit configured to generate a scanning clock signal to be provided to the scanning signal line driver circuit; and
a waveform control circuit configured to control a waveform of the scanning clock signal, the waveform control circuit being provided inside or outside the scanning clock generation circuit, wherein,
each of the pixel forming portions includes:
a capacitive electrode serving as one of electrodes that form predetermined capacitance; and
a field-effect transistor serving as a pixel switching element and having a first conduction terminal connected to one of the data signal lines, a second conduction terminal connected to the capacitive electrode, and a control terminal connected to one of the scanning signal lines,
the scanning signal line driver circuit includes:
a shift register configured to sequentially transfer an inputted start pulse and having stages corresponding in number to the scanning signal lines; and
a plurality of analog switches respectively connected to the scanning signal lines and being respectively turned on or off by output signals from the stages of the shift register that correspond to the scanning signal lines to which the analog switches are connected,
the scanning signal line driver circuit applies a plurality of signals respectively to the scanning signal lines as the scanning signals, the plurality of signals being obtained by sampling the scanning clock signal by the analog switches, and
the waveform control circuit controls the waveform of the scanning clock signal such that a time period taken for a voltage of the scanning clock signal to change from an on-voltage for rendering the pixel switching element in ON-state to an off-voltage for rendering the pixel switching element in OFF-state, at a fall or rise of a pulse included in the scanning clock signal, increases as the scanning signal line to which a scanning signal including the pulse is to be applied decreases in time constant.

US Pat. No. 10,482,837

LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING LIQUID CRYSTAL DISPLAY

Mitsubishi Electric Corpo...

1. A liquid crystal display, comprising:a plurality of scanning lines and a plurality of signal lines arranged in a matrix pattern on a substrate;
a pixel being formed at a crossing portion of each of the plurality of scanning lines and each of the plurality of signal lines, and comprising a thin film transistor that is connected to each of the plurality of scanning lines and each of the plurality of signal lines;
a plurality of first nonlinear resistance elements formed respectively in the plurality of scanning lines, each of the plurality of first nonlinear resistance elements being connected to one of the plurality of scanning lines at one end thereof and being connected to a first short ring line at another end thereof; and
a plurality of second nonlinear resistance elements formed respectively in the plurality of signal lines, each of the plurality of second nonlinear resistance elements being connected to one of the plurality of signal lines at one end thereof and being connected to a second short ring line at another end thereof, wherein
a voltage is applied to the plurality of first nonlinear resistance elements and the plurality of second nonlinear resistance elements independently of each of the plurality of scanning lines and each of the plurality of signal lines; and
the first short ring line and the second short ring line are electrically isolated from one another to permit application of respective voltages different from one another through the plurality of first nonlinear resistance elements and the plurality of second nonlinear resistance elements.

US Pat. No. 10,482,832

DISPLAY APPARATUS AND A METHOD OF DRIVING THE SAME

SAMSUNG DISPLAY CO., LTD....

19. A display apparatus comprising:a display panel configured to display an image, and comprising a gate line and a data line;
a gate driving part configured to output a gate signal to the gate line;
a data driving part configured to output a data signal to the data line; and
a timing controlling part,
wherein the timing controlling part comprises:
a pattern detecting part configured to receive first image data, detect patterns in the first image data, and output pattern detection data;
a lookup table configured to store parameters corresponding to a plurality of display areas in the display panel; and
a micro controlling part configured to receive the first image data, generate second image data and transition time control data using the first image data, the pattern detection data, and the lookup table, and output the second image data and the transition time control data to the data driving part, and
wherein the transition time control data is used to control a transition time and a slew of the data signal.

US Pat. No. 10,482,831

DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus, comprising:a plurality of pixels arranged in rows and columns, wherein each pixel column extends in a first direction and each pixel row extends in a second direction crossing the first direction;
a first data line extending in the first direction and configured to transfer a data voltage to pixels included in at least two pixel columns;
a second data line adjacent to the first data line;
a first pixel row includes a first pixel and a second pixel, the first and second pixels being disposed between the first data line and the second data line;
a second pixel row includes a third pixel and a fourth pixel, the third and fourth pixels being disposed between the first data line and the second data line, and the second pixel row is adjacent to the first pixel row, wherein the second pixel is disposed adjacent to the second data line and connected to the first data line, and the third pixel is disposed adjacent to the first data line and connected to the first data line;
for each pixel row, a first gate line extending in the second direction and disposed at a first side of the pixel row; and
a second gate line extending in the second direction and disposed at a second side of the pixel row, wherein the first and second sides of the pixel row are opposite to each other,
wherein, in a pair of adjacent pixel columns, pixels, which are connected to the first gate line of their respective pixel row, are arranged in a zigzag arrangement in the first direction.

US Pat. No. 10,482,829

DISPLAY DEVICE AND FABRICATING METHOD THEREOF

Samsung Display Co., Ltd....

1. A display device, comprising:a substrate including a first pixel area and a second pixel area spaced apart from each other, a first non-pixel area disposed adjacent to the first pixel area at a periphery of the first pixel area, and a second non-pixel area disposed adjacent to the second pixel area at a periphery of the second pixel area and opposite to the first non-pixel area with the first and the second pixel areas interposed therebetween;
first scan lines and first pixels connected to the first scan lines and disposed in the first pixel area;
second scan lines spaced apart from the first scan lines and second pixels connected to the second scan lines and disposed in the second pixel area;
a first scan driver disposed in the first non-pixel area and connected to the first scan lines;
a second scan driver disposed in the second non-pixel area and connected to the second scan lines;
a plurality of first wires disposed in the first non-pixel area and connected to the first scan driver;
a plurality of second wires disposed in the second non-pixel area and connected to the second scan driver;
first scan pads connected to the plurality of first wires and second scan pads connected to the plurality of second wires; and
a plurality of connecting wires connecting the first wires and the second wires, the plurality of connecting wires disposed adjacent to the first and second scan pads,
wherein the first pixels are not connected to the second scan lines and the second pixels are not connected to the first scan lines.

US Pat. No. 10,482,828

METHOD AND APPARATUS FOR CONTROLLING BACKLIGHT BRIGHTNESS, AND LIQUID CRYSTAL DISPLAY DEVICE

Hisense Electric Co., Ltd...

1. A method for controlling backlight brightness, comprising:determining, in an image to be displayed, an image block corresponding to a backlight partition of a plurality of backlight partitions, and determining an initial backlight value for the backlight partition according to grayscale values of pixels in the image block;
determining brightness distribution information for pixels in the image block according to grayscale values of the pixels in the image block;
determining that a backlight adjusting curve corresponding to the image block is of a reverse S-shaped curve type when the brightness distribution information indicates that number of pixels in the image block having grayscale values smaller than a first grayscale value is greater than a first threshold value, wherein the backlight adjusting curve of the reverse S-shaped curve type is configured to increase the initial backlight value to a target backlight value for the backlight partition corresponding to the image block when the initial backlight value is smaller than a first initial backlight value, and to decrease the initial backlight value to the target backlight value for the backlight partition corresponding to the image block when the initial backlight value is greater than a second initial backlight value;
determining that the backlight adjusting curve corresponding to the image block is of a S-shaped curve type when the brightness distribution information indicates that number of pixels in the image block having grayscale values greater than a second grayscale value is greater than a second threshold value, wherein the backlight adjusting curve of the S-shaped curve type is configured to increase the initial backlight value to the target backlight value for the backlight partition corresponding to the image block when the initial backlight value is greater than a third initial backlight value, and to decrease the initial backlight value to the target backlight value for the backlight partition corresponding to the image block when the initial backlight value is smaller than a fourth initial backlight value; and
determining a backlight adjusting factor for the backlight partition corresponding to the image block according to the initial backlight value of the backlight partition corresponding to the image block and the backlight adjusting curve corresponding to the image block, and determining the target backlight value for the backlight partition corresponding to the image block according to the initial backlight value for the backlight partition and the backlight adjusting factor.

US Pat. No. 10,482,826

GOA DRIVING CIRCUITS AND DISPLAY DEVICES

Shenzhen China Star Optoe...

1. A gate driver on array (GOA) driving circuit, comprising:N number of cascaded-connected GOA units, wherein N is a natural number not smaller than four, wherein the GOA unit at the i-th level comprises a first transistor, a second transistor; a third transistor, a first capacitor, and a first pull-down maintain unit, wherein 1?i?a and a is a natural number smaller than or equal to N/2;
a source and a gate of the first transistor receives turn-on signals, and a drain of the first transistor respectively connects to the first pull-down maintain unit and a node at the i-th level;
a source of the second transistor receives the turn-on signals, a gate of the second transistor receives second clock signals, and a drain of the second transistor connects to the node at the i-th level;
a source of the third transistor receives first clock signals, a gate of the third transistor connects to the node at the i-th level, and a drain of the third transistor respectively connects to the other end of the first capacitor and a gate signal output end at the i-th level;
one end of the first capacitor connects to the node at the i-th level, and the other end of the first capacitor connects to the first pull-down maintain unit, the first pull-down maintain unit connects to a direct-current low voltage end;
the GOA unit at the j-th level comprises a fourth transistor, a fifth transistor, a second capacitor, and a second pull-down maintain unit, wherein a+1?j?N;
a source of the fourth transistor connects to a gate signal output end in the (j?a)-th level, a gate of the fourth transistor receives the second clock signals, a drain of the fourth transistor respectively connects to second pull-down maintain unit and the node at the j-th level Q(j); a source of the fifth transistor receives the first clock signals, a gate of the fifth transistor connects to the node at the j-th level Q(j), and a drain of the fifth transistor respectively connects to the other end of the second capacitor and the gate signal output end at the j-th level; and one end of the second capacitor connects to the node in the j-th level, and the other end of the second capacitor connects to the second pull-down maintain unit, and the second pull-down maintain unit connects to a turn-off voltage; and
wherein the second clock signals and the first clock signals are two different clock signals in one clock signals set;
the clock signals set comprises M number of clock signals, wherein M is a positive integer, wherein a period of each of the clock signals is 8H, and a high level duration of each of the clock signals is 3.2H, a rising edge of the (m+1)-th clock signals is delayed by a time delay of the rising edge of the m-th clock signals, wherein m is a positive integer in a range from 1 to M, and m is not equal to three, the rising edge of the third clock signals is delayed by 1.2H of the rising edge of the second clock signals.

US Pat. No. 10,482,824

DIGITAL-TO-ANALOG CONVERTER, DATA DRIVER AND DISPLAY APPARATUS INCLUDING THE SAME

DB HiTek Co., Ltd., Buch...

1. A digital-to-analog converter, comprising:a voltage generator configured to generate a plurality of voltage groups, each of the plurality of voltage groups having a plurality of reference voltages; and
a decoder having an output node configured to output one of the pluralities of reference voltages from any of the plurality of voltage groups,
wherein the decoder includes:
switch blocks that correspond to the plurality of voltage groups; and
first to (m?1)-th connection transistors between a first connection node and an m-th connection node, m being a natural number greater than 1,
each of the switch blocks includes transistors that are turned on or off by or in response to a control signal,
the first connection node is directly connected to a first transistor in a first one of the switch blocks and to a second transistor in a second one of the switch blocks,
the m-th connection node is directly connected to two neighboring (m?1)-th connection transistors,
each of the (m?1)-th connection transistors is between an (m?1)-th connection node and the m-th connection node,
a first voltage group corresponding to the first transistor is higher than a second voltage group corresponding to the second transistor,
a size of the first transistor is greater than a size of the second transistor,
one of the (m?1)-th connection transistors has a same size as a size of a third transistor of the first one of the switch blocks, and
the first switch block receives reference voltages equal to or higher than a voltage of the (m?1)-th connection node to which the one of the (m?1)-th connection transistors is connected.

US Pat. No. 10,482,822

DISPLAYS WITH MULTIPLE SCANNING MODES

Apple Inc., Cupertino, C...

1. A display comprising:an array of pixels formed in an active area of the display, wherein the array of pixels comprises rows and columns of pixels;
display driver circuitry formed in an inactive area of the display, wherein the display driver circuitry is configured to provide image data to the pixels; and
gate driver circuitry formed in the inactive area of the display, wherein the gate driver circuitry comprises an emission driver and a scan driver, wherein the emission driver comprises a first portion that is associated with a first portion of the array of pixels, wherein the scan driver comprises a first portion that is associated with the first portion of the array of pixels, wherein the first portion of the emission driver is disabled while operating in a partial scanning mode to prevent the first portion of the array of pixels from emitting light, wherein the first portion of the scan driver scans the pixels in the first portion of the array of pixels while operating in the partial scanning mode, wherein the emission driver comprises a second portion associated with a second portion of the array of pixels, wherein the scan driver comprises a second portion associated with the second portion of the array of pixels, wherein the second portion of the emission driver is configured to receive a first control pulse at the beginning of each frame while operating in the partial scanning mode and wherein the second portion of the scan driver is configured to receive a second control pulse at the beginning of each frame while operating in the partial scanning mode.

US Pat. No. 10,482,819

DEVICE WITH OLED MATRIX OF ACTIVE PIXELS WITH CATHODE VOLTAGE REGULATION, AND CORRESPONDING METHOD

STMicroelectronics Intern...

1. A device, comprising:a matrix of active pixels, each active pixel comprising:
a control circuit coupled to an anode side terminal; and
an OLED diode having an anode coupled to the control circuit and a cathode coupled to a cathode supply line;
at least one dummy pixel comprising:
a dummy control circuit; and
a dummy OLED diode having an anode coupled to the dummy control circuit and a cathode coupled to the cathode supply line;
wherein the dummy OLED diode has substantially similar operating characteristics as the OLED diode, and the dummy control circuit has substantially similar operating characteristics as the control circuit;
a current source;
a switch having a first terminal coupled to the current source and a second terminal coupled to the anode side terminal;
wherein the dummy control circuit is coupled between the second terminal of the switch and the anode of the dummy OLED diode; and
regulation circuitry coupled between the anode side terminal and the cathode supply line.

US Pat. No. 10,482,817

DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME

Samsung Display Co., Ltd....

1. A display device, comprising:pixels configured to emit light of various intensity in accordance with driving signals;
data lines to communicate the driving signals to the pixels;
scan lines to communicate scan signals to select one or more of pixels to receive the driving signals; and
a power supply to supply at least one driving voltage to the pixels;
wherein at least one of the pixels comprises:
a switching transistor having a first electrode connected to one of the data lines and a second electrode connected to a first node, and a gate electrode connected to one of the scan lines,
a driving transistor connected between the power supply and an organic light emitting diode,
a storage capacitor having a first terminal connected to the first node and a second terminal connected to a gate electrode of the driving transistor,
a first transistor connected between the first node and a first electrode of the driving transistor, and
a second transistor having a gate electrode connected to the scan line, the scan line being connected to the switching transistor.

US Pat. No. 10,482,816

METHOD FOR DRIVING DISPLAY ELEMENT, DISPLAY DEVICE, AND ELECTRONIC DEVICE

SONY CORPORATION, Tokyo ...

1. A method for driving a display element, the method comprising:in driving the display element including an n-channel drive transistor in which a voltage is applied to one source/drain region and a light-emitting unit is connected to another source/drain region, and a capacitor connected between a gate electrode of the n-channel drive transistor and the other source/drain region,
performing threshold voltage cancellation processing that applies a drive voltage to the one source/drain region in a state where a reference voltage is applied to the gate electrode of the n-channel drive transistor, to bring a potential of the other source/drain region closer to a potential obtained by subtracting a threshold voltage of the n-channel drive transistor from the reference voltage;
subsequently, setting the gate electrode of the n-channel drive transistor in a floating state, and changing a potential of the gate electrode in the floating state via a parasitic capacitance and causing a current to flow via the n-channel drive transistor to increase a voltage between the other source/drain region and the gate electrode, and then applying the reference voltage to the gate electrode of the n-channel drive transistor;
afterwards, performing write processing that applies a video signal voltage to the gate electrode of the n-channel drive transistor; and
subsequently, setting the gate electrode of the n-channel drive transistor in the floating state to cause the light-emitting unit to emit light.

US Pat. No. 10,482,815

PIXEL DRIVING CIRCUIT AND DISPLAY PANEL

Shenzhen China Star Optoe...

1. A pixel driving circuit, comprising a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, a charge-voltage terminal, a reset-voltage-signal terminal, a data-voltage-signal terminal, and a driving-voltage-signal terminal; wherein the driving transistor comprises a gate terminal, a source terminal, and a drain terminal;the first switch is disposed between the gate terminal and the drain terminal, the gate terminal is connected with the reset-voltage-signal terminal via the second switch; the source terminal is respectively connected with the driving-voltage-signal terminal and the data-voltage-signal terminal via the third switch and the fourth switch;
the first capacitor is connected between the gate terminal and the charge-voltage terminal; the charge-voltage terminal is connected with a control terminal of the first switch, the second capacitor is connected between the gate terminal and the driving-voltage-signal terminal;
the pixel driving circuit further comprising:
a first control-signal terminal, wherein the first control-signal terminal is connected with the charge-voltage terminal, the control terminal of the first switch, a control terminal of the third switch, and a control terminal of the fourth switch, so as to control on/off of the first switch, the third switch, and the fourth switch;
a second control-signal terminal, wherein the second control-signal terminal is connected with a control terminal of the second switch, so as to control on/off of the second switch;
a fifth switch, a light-emitting diode and a negative voltage-signal terminal; wherein the light-emitting diode comprises a positive terminal and a negative terminal; the fifth switch is connected between the drain terminal and the positive terminal, so as to control on/off of the driving transistor and the light-emitting diode, and the negative terminal is connected with the negative voltage-signal terminal;
a third control-signal terminal, wherein the third control-signal terminal is connected with a control terminal of the fifth switch, so as to control on/off of the fifth switch;
wherein when the first control-signal terminal and the third control-signal terminal are loaded with a high-level signal, and the second control-signal terminal is loaded with a low-level signal, the potential of the charge-voltage terminal is at a high level, the second switch and the third switch are turned on, and the first switch, the fourth switch, and the fifth switch are turned off; and the gate terminal is connected with the reset-voltage-signal terminal via the second switch, the source terminal is connected with the driving-voltage-signal terminal via the third switch, so as to reset a potential of the gate terminal and a potential of the source terminal.

US Pat. No. 10,482,810

INTEGRATED FOLDED OLED DISPLAY IN AN INFORMATION HANDLING SYSTEM PORTABLE HOUSING FOR DISABLING PIXELS BASED UPON ANTENNA ACTIVITY

Dell Products L.P., Roun...

1. A portable information handling system comprising:a housing;
a processor disposed in the housing and operable to execute instructions to process information;
a memory disposed in the housing and interfaced with the processor, the memory operable to store the information;
a graphics processor operable to selectively send visual information to present visual images at pixels of a display and to selectively turn off presentation of visual images at the pixels by withholding visual information from presentation at the pixels;
an OLED display integrated in the housing and interfaced with the graphics processor, the OLED display operable to present the information as visual images and having control wires interfaced with pixels to communicate signals to the pixels that generate the visual images;
plural antenna wires integrated with the OLED display at plural locations, the plural antenna wires aligned to pass across the display with the control wires; and
a radio interfaced with the plural antenna wires, the radio having a multiple input multiple output (MIMO) controller operable to communicate wireless signals from the plural antenna wires in a MIMO configuration;
wherein the graphics processor selects less than all pixels of the display at which to disable the presentation of visual information based upon activity at the antenna wires, the disabled visual information associated with control wires that are proximate to but separate from the antenna wires to reduce signal interference between the control wires and the antenna wires.

US Pat. No. 10,482,807

INTERFACE DEVICES AND LIQUID CRYSTAL DEVICES WITH THE SAME

Shenzhen China Star Optoe...

1. An interface device for high resolution liquid crystal device (LCD), comprising:a first connector configured to receive low voltage differential signals (LVDS) provided for a left-half active area of the LCD, a second connector configured to receive the LVDS provided for a right-half active area of the LCD, and a third connector configured to receive operational voltage signals and control signals provided for the LCD;
wherein the left-half active area comprises N number of left active areas along a direction from left to right in sequence, and each of the left active areas correspond to one left-positive-negative-pole-pin pair, the first connector comprises N number of left-positive-negative-pole-pin pairs, each of the left-positive-negative-pole-pin pairs comprises a first-left grounding pin, a left-positive-pole-pin and a left-negative-pole-pin, and the first-left grounding pin directly followed by the left-positive-pole-pin directly followed by the left-negative-pole-pin, each of the left-positive-pole-pins is configured to receive the positive LVDS provided for the corresponding left active area, and each of the left-negative-pole-pins is configured to receive the negative LVDS provided for the corresponding left active area; and
wherein the first connector further comprises at least one no-load (NC) pin before the N number of left-positive-negative-pole-pin pairs, and a second-left grounding pin after the N number of left-positive-negative-pole-pin pairs.

US Pat. No. 10,482,806

SPATIOTEMPORAL DITHERING TECHNIQUES FOR ELECTRONIC DISPLAYS

Apple Inc., Cupertino, C...

1. A method of operating a display, comprising:providing positive polarity data signals and negative polarity data signals via a processor to a plurality of pixels of the display during a first frame period, wherein the first frame period corresponds a first spatiotemporal rotation phase;
driving a first subset of pixels of the plurality of pixels to a first intensity level and a second subset of pixels of the plurality of pixels to a second intensity level during the first frame period;
providing the positive polarity data signals and the negative polarity data signals to the plurality of pixels of the display during a second frame period, wherein the second frame period corresponds a second spatiotemporal rotation phase;
counting a first number of frames using the first spatiotemporal rotation phase during a unit time and a second number of frames using the second spatiotemporal rotation phase during the unit time; and
driving a third subset of pixels to the second intensity level and a fourth subset of pixels to the first intensity level during the second frame period, wherein the third subset of pixels comprises first rotated pixels that are rotated from the first subset of pixels within quadrants of the plurality of pixels, and the fourth subset of pixels comprises second rotated pixels that are rotated from the second subset of pixels within quadrants of the plurality of pixels, a spatiotemporal rotation phase sequence provided to the display comprises the first spatiotemporal rotation phase and the second spatiotemporal rotation phase, and wherein the processor is configured to replace one of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase of the spatiotemporal rotation phase sequence with another spatiotemporal rotation phase during the first frame period or the second frame period, wherein replacing one of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase comprises replacing one of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase of the spatiotemporal rotation phase sequence each time a measured pixel charge value reaches a pixel charge threshold value and based at least in part on the first number or the second number.

US Pat. No. 10,482,803

DISPLAY DRIVER INTEGRATED CIRCUIT

Samsung Electronics Co., ...

1. A display driver integrated circuit comprising:a source driver configured to receive a power voltage from a power management integrated circuit; and
a logic circuit configured to receive display data from an application processor, to perform an analysis on the display data, and to control a voltage level of the power management integrated circuit based on the analysis,
wherein the logic circuit is configured to set the voltage level of the power management integrated circuit to one of at least three different voltages by comparing the analysis with a first reference value and a second reference value,
wherein the display data comprises image data in units of frames,
the image data in units of frames comprises a plurality of horizontal lines,
each of the plurality of horizontal lines includes a plurality of pixel bits, and
the logic circuit is configured to control the power management integrated circuit by comparing each pixel bit of a first horizontal line with each pixel bit of a second horizontal line adjacent to the first horizontal line, summing compared results, and controlling the voltage level of the power voltage based on a summed result,
wherein the first horizontal line and the second horizontal line extend a length of the image data.