US Pat. No. 10,461,173

METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR FORMING SOURCE AND DRAIN REGIONS IN A VERTICAL FIELD EFFECT TRANSISTOR

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a fin above a semiconductor substrate;
forming a structure on a middle portion of each sidewall of the fin, whereby a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; and
forming a first epitaxial region on at least the top of the fin for forming a top source/drain (S/D) region, and a second epitaxial region on the lower portion of each sidewall and on the semiconductor substrate for forming a bottom S/D region, such that the bottom S/D region comprises an elevated subregion on the lower portion of each sidewall of each fin, wherein the elevated subregion is vertically aligned with the top S/D region.

US Pat. No. 10,461,170

METHOD OF FORMING MOSFET STRUCTURE

Taiwan Semiconductor Manu...

1. A method comprising:providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer;
providing a gate layer adjacent to the epitaxial layer and the cap layer;
providing a dielectric layer above the cap layer and the gate layer;
forming a trench above the cap layer by patterning a portion of the dielectric layer above the cap layer, wherein sidewalls of the trench comprise the gate layer and the dielectric layer above the gate layer;
filling the trench with a protection layer; and
removing the protection layer.

US Pat. No. 10,461,169

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a metal gate electrode structure and an insulating layer over a semiconductor substrate, wherein the insulating layer surrounds the metal gate electrode structure; and
nitrifying a first top portion of the metal gate electrode structure to transform the first top portion into a metal nitride layer while nitrifying a second top portion of the insulating layer to transform the second top portion of the insulating layer to a dielectric nitride layer.

US Pat. No. 10,461,166

ELECTRICAL CONTACT

National University of Si...

1. An electrical contact comprising:(a) a top electrode comprising a non-Newtonian liquid metal alloy; and
(b) a bottom electrode comprising a self-assembled monolayer of molecules (SAM) formed on a metal substrate,
wherein the surface of the SAM layer of the bottom electrode contacting the top electrode is a template-stripped non-patterned surface and the electrical contact has no edge effect;
and the surface of the liquid metal alloy contacting the SAM layer is contained in a polymer insulator and the area of the electrical contact between the liquid metal alloy surface and the SAM layer is determined by modulating the diameter of the liquid metal alloy surface contacting the SAM layer, the diameter being between 15 ?m and 55 ?m.

US Pat. No. 10,461,165

SEMICONDUCTOR DEVICE AND METHOD OF FORMATION

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, comprising:forming a first tube material over a first channel material, the first channel material over a dielectric layer;
forming a second channel material over the first tube material such that the second channel material is in contact with the first channel material;
removing at least some of the dielectric layer from under the first channel material to form a first gate opening;
forming a gate in the first gate opening under the first channel material and around the second channel material; and
performing an annealing operation to form a dielectric tube from the first tube material and to form a channel from the first channel material and the second channel material, wherein the channel surrounds the dielectric tube to enclose an outer perimeter of the dielectric tube.

US Pat. No. 10,461,159

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, the method comprising the steps of:(a) forming a second nitride semiconductor layer on a first nitride semiconductor layer;
(b) forming a third nitride semiconductor layer on the second nitride semiconductor layer;
(c) forming a fourth mesa-type nitride semiconductor layer on the third nitride semiconductor layer;
(d) forming a gate insulating film on the fourth mesa-type nitride semiconductor layer; and
(e) forming a gate electrode on the gate insulating film;
wherein the second nitride semiconductor layer has an electron affinity equal to or larger than electron affinity of the first nitride semiconductor layer,
wherein the third nitride semiconductor layer has an electron affinity smaller than the electron affinity of the first nitride semiconductor layer,
wherein the fourth nitride semiconductor layer has an electron affinity equal to or smaller than the electron affinity of the second nitride semiconductor layer, and
wherein the step (d) includes the steps of:
(d1) forming a first film including a first insulator on the fourth mesa-type nitride semiconductor layer by a sputtering process using a target including the first insulator; and
(d2) forming a second film including a second insulator on the first film by a CVD process.

US Pat. No. 10,461,157

FLAT GATE COMMUTATED THYRISTOR

ABB Schweiz AG, Baden (C...

1. A turn-off power semiconductor device comprising:a semiconductor wafer having a first main side and a second main side opposite to the first main side;
a plurality of thyristor cells, each of the plurality of thyristor cells comprising in the order from the first main side to the second main side:
(a) a cathode region of a first conductivity type;
(b) a base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region;
(c) a drift layer of the first conductivity type forming a second p-n junction with the base layer; and
(d) an anode layer of the second conductivity type separated from the base layer by the drift layer,
wherein each thyristor cell comprises: a gate electrode which is arranged lateral to the cathode region and forms an ohmic contact with the base layer; a cathode electrode arranged on the first main side and forming an ohmic contact with the cathode region; and an anode electrode arranged on the second main side and forming an ohmic contact with the anode layer,
wherein interfaces between the cathode regions and the cathode electrodes and interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar, and
wherein the base layer includes a gate well region extending from its contact with the gate electrode to a depth (dW) which is at least half of a depth (dC) of the cathode region,
wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 ?m from the cathode region, and
the base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein a ratio between the density of first conductivity type impurities and the net doping concentration in the compensated region is at least 0.4.

US Pat. No. 10,461,154

BOTTOM ISOLATION FOR NANOSHEET TRANSISTORS ON BULK SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A method of forming nanosheets comprising:providing at least two stacks of semiconductor material layers on a supporting bulk semiconductor substrate, wherein the at least two stacks of semiconductor material layers includes a sacrificial semiconductor layer of a first composition, and a nanosheet semiconductor layer of a second composition, and removing the sacrificial semiconductor layer to provide nanosheets composed of the nanosheet semiconductor layer;
forming a first undercut region filled with a first dielectric material extending from an opening into the supporting bulk semiconductor substrate underlying the semiconductor material layers of the at least two stacks of semiconductor material layers; and
forming a second undercut region into the supporting bulk semiconductor substrate filled with a second dielectric material from a side of the at least two stacks of semiconductor material layers that is opposite a side of the at least two stacks of semiconductor material layers at which the first undercut region is positioned, wherein the first and second dielectric materials provide an isolation region.

US Pat. No. 10,461,153

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor memory device comprising;a substrate including active regions;
word lines in the substrate, each of the word lines extending in a first direction parallel to an upper surface of the substrate;
bit line structures connected to the active regions, respectively, each of the bit line structures extending in a second direction crossing the first direction; and
spacer structures on sidewalls of respective ones of the bit line structures,
each of the spacer structures including a first spacer, a second spacer, and a third spacer,
the second spacer being disposed between the first spacer and the third spacer,
the second spacer including a void, and
a height of the second spacer being greater than a height of the void with respect to the upper surface of the substrate,
the second spacer filling a bottom portion of a gap region defined by the first spacer and the third spacer;
contact plugs between each of the bit line structures, the contact plugs being connected to the active regions, respectively;
connection pads on the contact plugs, respectively; and
a separation layer between each of the connection pads, wherein
a lowermost surface of the separation layer is higher than an uppermost surface of the second spacer with respect to the upper surface of the substrate,
an upper surface of the third spacer is lower than an upper surface of the first spacer with respect to the upper surface of the substrate,
an upper surface of the second spacer is lower than the upper surface of the third spacer with respect to the upper surface of the substrate, and
each of the spacer structures further includes a fourth spacer on a sidewall of the first spacer and on the upper surface of the second spacer.

US Pat. No. 10,461,152

RADIO FREQUENCY SWITCHES WITH AIR GAP STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising a substrate with at least one trench structure extending from a surface of the substrate to at least one airgap structure formed in a well region of the substrate and under at least one gate structure having a channel extending continuously into the well region, the at least one airgap devoid of a lining and which extends within the substrate to a junction formed by a source/drain region in the substrate of the at least one gate structure, and the at least one trench is capped with insulator material which seals the at least one airgap structure to prevent moisture from entering into the at least one airgap structure.

US Pat. No. 10,461,145

METHOD FOR FABRICATING MAGNETIC CORE

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a magnetic core, comprising:depositing a magnetic layer on a dielectric layer;
forming a first photoresist layer on the magnetic layer and patterning the first photoresist layer;
etching the magnetic layer through the patterned first photoresist layer, wherein a first section of the magnetic layer exposed by the patterned first photoresist layer remains on the dielectric layer after etching the magnetic layer;
removing the patterned first photoresist layer;
forming a second photoresist layer on the magnetic layer and patterning the second photoresist layer such that the patterned second photoresist layer has a curve portion;
etching the magnetic layer through the patterned second photoresist layer such that the curve portion of the patterned second photoresist layer suspends without support above the magnetic layer; and
removing the patterned second photoresist layer.

US Pat. No. 10,461,139

LIGHT EMITTING DEVICE MANUFACTURING METHOD AND APPARATUS THEREOF

INT TECH CO., LTD., Hsin...

1. A method of manufacturing a light emitting device, comprising:providing a substrate;
forming a plurality of photosensitive bumps over the substrate;
forming a photosensitive layer over the plurality of photosensitive bumps;
forming a buffer layer between the photosensitive layer and the plurality of photosensitive bumps;
patterning the photosensitive layer to form a recess through the photosensitive layer to expose a surface;
disposing an organic emissive layer on the surface,
forming a metal containing layer over the organic emissive layer, and
removing the patterned photosensitive layer.

US Pat. No. 10,461,135

FLEXIBLE DISPLAY PANEL AND FABRICATION METHOD THEREOF, AND FLEXIBLE DISPLAY DEVICE

Shanghai Tianma Micro-Ele...

11. A flexible display device including a flexible display panel, wherein the flexible display panel comprises:a stacked structure having a plurality of layers comprising a flexible substrate, a light-emitting device layer, and a polarizing layer stacked in a preset order;
at least one upper-side resistive force-sensitive electrode disposed on a layer above a neutral plane of the stacked structure; and
at least one lower-side resistive force-sensitive electrode disposed on a layer below the neutral plane, wherein:
each upper-side resistive force-sensitive electrode includes a first resistive force-sensitive electrode and a second resistive force-sensitive electrode,
each lower-side resistive force-sensitive electrode includes a third resistive force-sensitive electrode and a fourth resistive force-sensitive electrode,
the first resistive force-sensitive electrode, the second resistive force-sensitive electrode, the third resistive force-sensitive electrode, and the fourth resistive force-sensitive electrode are electrically connected to form a bridge circuit,
the bridge circuit further includes a positive terminal, a negative terminal, a first voltage terminal, and a second voltage terminal,
one end of the first resistive force-sensitive electrode being electrically connected to one end of the third resistive force-sensitive electrode,
one end of the second resistive force-sensitive electrode being electrically connected to one end of the fourth resistive force-sensitive electrode,
another end of the first resistive force-sensitive electrode being electrically connected to another end of the fourth resistive force-sensitive electrode,
another end of the third resistive force-sensitive electrode being electrically connected to another end of the second resistive force-sensitive electrode,
a connection node between the first resistive force-sensitive electrode and the third resistive force-sensitive electrode is connected to one of the positive terminal and the negative terminal,
a connection node between the second resistive force-sensitive electrode and the fourth resistive force-sensitive electrode is connected to the other one of the positive terminal and the negative terminal,
a connection node between the first resistive force-sensitive electrode and the fourth resistive force-sensitive electrode is connected to the first voltage terminal, and
a connection node between the third resistive force-sensitive electrode and the second resistive force-sensitive electrode is connected to the second voltage terminal.

US Pat. No. 10,461,133

LIGHT EMITTING DISPLAY DEVICE INCLUDING AN INFRARED RAY LIGHT EMITTING DIODE

Samsung Display Co., Ltd....

1. A light emitting display device comprising:a first electrode on a substrate;
a second electrode overlapping the first electrode;
a red emission layer, a green emission layer, a blue emission layer, and an infrared ray emission layer between the first electrode and the second electrode and emitting light of different wavelengths from each other;
a green resonance auxiliary layer between the green emission layer and the first electrode; and
a blocking layer between the green resonance auxiliary layer and the green emission layer,
wherein the infrared ray emission layer and the green resonance auxiliary layer comprise the same material,
the green emission layer comprises a green light emitting dopant, and
a Lowest Unoccupied Molecular Orbital (LUMO) energy of the blocking layer is larger than a LUMO energy of the green light emitting dopant.

US Pat. No. 10,461,130

IMAGE DEVICE INCLUDING PHOTOELECTRIC CONVERSION LAYER

PANASONIC INTELLECTUAL PR...

1. An imaging device comprising unit pixels, each unit pixel including:a photoelectric conversion unit including
a first electrode including a first conducting material,
a second electrode facing the first electrode,
a photoelectric conversion layer between the first and second electrodes, the photoelectric conversion layer including a first photoelectric conversion material, and
an electron-blocking layer between the first electrode and the photoelectric conversion layer, the electron-blocking layer including an electron-blocking material; and
a signal detection circuit electrically connected to the first electrode, wherein
the electron-blocking material has an ionization potential higher than both a work function of the first conducting material and an ionization potential of the first photoelectric conversion material,
the photoelectric conversion unit is adapted to be applied with a voltage between the first electrode and the second electrode, and the photoelectric conversion unit has a characteristic, responsive to the voltage within a range from a first voltage to a second voltage, showing that a density of current passing between the first electrode and the second electrode when light is incident on the photoelectric conversion layer becomes substantially equal to that when no light is incident on the photoelectric conversion layer, and
a difference between the first voltage and the second voltage is 0.5 V or more.

US Pat. No. 10,461,129

DEVICE FOR DETECTING ELECTROMAGNETIC RADIATION CONSISTING OF ORGANIC MATERIALS

ISORG, Grenoble (FR)

1. An electromagnetic radiation detection device comprising: at least one row of photoresistors, each photoresistor comprising an active portion comprising organic semiconductor materials; emitters of the electromagnetic radiation; and a waveguide; wherein the waveguide comprises at least one surface intended to be in contact with at least one object, the photoresistors being distributed along an edge of said surface, the emitters being located along said edge.

US Pat. No. 10,461,108

IMAGING DEVICE

Hitachi, Ltd., Tokyo (JP...

1. An imaging device comprising:a modulator with a first pantoscopic grating pattern, the modulator configured to modulate light intensity by passage through the first pantoscopic grating pattern;
an image sensor configured to convert light passing through the modulator, to image data, and output the image data; and
an image processor configured to conduct image processing of restoring an image with the use of the image data output from the image sensor,
wherein the first pantoscopic grating pattern is configured to comprise multiple basic patterns, and
each of the basic patterns has the shape of a concentric circle, and
wherein the modulator comprises a first polarization plate and a second polarization plate,
the first polarization plate is disposed closer to a surface configured to serve as an input face of the modulator,
the second polarization plate is disposed closer to a rear surface configured to serve as an output face of the modulator, and
the first polarization plate and the second polarization plate have polarizing axes determined on the basis of an arrangement of the basic patterns.

US Pat. No. 10,461,106

IMAGING ELEMENT AND CAMERA SYSTEM

Sony Corporation, Tokyo ...

1. An imaging element comprising:a plurality of photoelectric conversion sections that are arrayed on a substrate to receive light incident through a dual-pass filter having transmission bands for visible light and a predetermined range of near-infrared light,
wherein the photoelectric conversion sections include a visible light photoelectric conversion section and a near-infrared light photoelectric conversion section, and the visible light photoelectric conversion section includes a red light photoelectric conversion section, a green light photoelectric conversion section, and a blue light photoelectric conversion section,
wherein a near-infrared absorption filter is selectively disposed on a light incident surface of the photoelectric conversion sections in correspondence with the visible light photoelectric conversion section, and
wherein at least a part of the near-infrared absorption filter is embedded into an opening in a light-shielding layer separating neighboring photoelectric conversion sections.

US Pat. No. 10,461,105

PHOTODIODE ARRAY

ams AG, Unterpremstaette...

1. A photodiode array, comprising:A first photodiode comprising a first set of spatially separate and electrically interconnected photodiode segments,
A second photodiode comprising a second set of spatially separate and electrically interconnected photodiode segments,
A first group of photodiode segments comprising photodiode segments from the first and/or second set of photodiode segments, wherein the photodiode segments from the first group of photodiode segments are radially arranged around a common center of symmetry in a common first distance with respect to the common center of symmetry, and
A second group of photodiode segments comprising photodiode segments from the first and/or second set of photodiode segments, wherein photodiode segments from the second group of photodiode segments are radially arranged around the common center of symmetry in a second common distance with respect to the common center of symmetry, wherein the first distance is different from the second distance, and wherein
Each photodiode has an area matched counterpart photodiode forming a matched pair of photodiodes,
The matched counterpart photodiodes comprise a matched set of spatially separate and electrically interconnected photodiode segments, and
Each group of photodiode segments comprises the corresponding matched set of photodiode segments.

US Pat. No. 10,461,102

DISPLAY DEVICE, TRANSFLECTIVE ARRAY SUBSTRATE, AND MANUFACTURING METHOD THEREOF

Shenzhen China Star Optoe...

1. A manufacturing method of a transflective array substrate, wherein the transflective array substrate comprises a plurality of pixel cells, each of the pixel cells comprises a reflective area, and the manufacturing method comprises:arranging a plurality of scanning lines, a plurality of data lines intersecting with the scanning lines, and a plurality of TFTs, wherein the TFT is surrounded by the scanning lines and the data lines, the TFT is configured within the pixel cell, and the TFT electrically connects to the scanning line and the data line respectively;
arranging a photoresist layer above the TFT corresponding to each of the pixel cells;
arranging at least one pixel electrode above the photoresist layer corresponding to each of the pixel cells, wherein the TFT electrically connects to the pixel electrode;
arranging a reflective layer within the reflective area, wherein the reflective layer is configured above the photoresist layer, so as to prevent ambient light beams from being filtered by the photoresist layer when the ambient light beams enter the reflective area;
wherein step of arranging a plurality of the scanning lines, a plurality of the data lines intersecting with the scanning lines, and a plurality of the TFTs further comprises:
depositing a gate metal layer on a glass substrate;
forming the scanning lines and a gate of the TFT by conducting an exposure process, a development process, a wet-etching process, and a peeling-off process on the gate metal layer, wherein the gate electrically connects to the scanning line;
depositing a source-drain metal layer above the scanning line and the gate;
forming the data lines, and a source and a drain of the TFT by conducting the exposure process, the development process, the wet-etching process, a dry-etching process, and the peeling-off process on the source-drain metal layer, wherein the source electrically connects to the data line, and the drain electrically connects to the pixel electrode;
wherein, before the step of depositing the source-drain metal layer above the scanning line and the gate, the manufacturing method further comprises:
depositing a gate insulation layer above the scanning line and the gate to form a first insulation layer;
depositing an N-doped amorphous silicon layer on the first insulation layer;
forming a semiconductor layer by conducting the exposure process, the development process, the dry-etching process, and the peeling-off process on the N-doped amorphous silicon layer;
before the step of arranging the photoresist layer above the TFT corresponding to each of the pixel cells, the manufacturing method further comprises:
depositing a photoresist insulation layer on the data line, and the source and the drain of the TFT to form a second insulation layer;
before the step of arranging at least one pixel electrode above the photoresist layer corresponding to each of the pixel cells, the manufacturing method further comprises:
depositing a flat layer on the photoresist layer to form a third insulation layer;
forming a through hole by conducting a through-hole etching process on the third insulation layer, wherein the through hole penetrates the third insulation layer, the photoresist layer, and a second insulation layer, the drain is exposed by the through hole;
the step of arranging the pixel electrode above the photoresist layer corresponding to each of the pixel cells further comprises:
depositing a first conductive material layer on the third insulation layer;
forming the pixel electrode by conducting the exposure process, the development process, the wet-etching process, and the peeling-off process on the first conductive material layer, wherein the pixel electrode electrically connects to the drain via the through hole;
before the step of arranging the reflective layer, the manufacturing method further comprises:
depositing an electrode insulation layer on the pixel electrode to form a fourth insulation layer.

US Pat. No. 10,461,101

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:an oxide semiconductor layer over a first insulating film;
the oxide semiconductor layer comprising a first region and a second region;
a transistor over an insulating surface, the transistor including:
a source electrode layer and a drain electrode layer;
a second insulating film over the first region; and
a gate electrode layer over the first region with the second insulating film therebetween;
a transparent conductive film overlapping with the second region;
a dielectric between the second region and the transparent conductive film; and
a capacitor comprising
the second region;
the transparent conductive film; and
the dielectric serving as a dielectric of the capacitor,
wherein the dielectric is in direct contact with a side edge surface of the second insulating film, a first electrode of the capacitor, and a second electrode of the capacitor.

US Pat. No. 10,461,096

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display apparatus comprising:a substrate having a central area and a peripheral area disposed adjacent to the central area, the central area comprising a display area;
at least one semiconductive layer or one conductive layer in the display area;
a first insulating layer disposed in the peripheral area of the substrate, the first insulating layer covering at least one of the at least one semiconductive layer or the one conductive layer;
at least one pattern corresponding to a region of the first insulating layer;
a cover layer on the first insulating layer and covering the at least one pattern in the peripheral area, the cover layer comprising an insulating material; and
an encapsulating layer on the display area, at least one layer of the encapsulating layer is spaced apart from the cover layer.

US Pat. No. 10,461,095

FERROELECTRIC NON-VOLATILE MEMORY

SanDisk Technologies LLC,...

1. A non-volatile storage element comprising:a control gate;
a blocking layer comprising a ferroelectric material;
a charge storage region; and
a tunneling layer,
wherein the blocking layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer, and
wherein the blocking layer comprises doped hafnium oxide including crystal grains that may be switched between a first polarization state to a second polarization state.

US Pat. No. 10,461,092

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a stacked body including:
a first stacked unit and a second stacked unit stacked above the first stacked unit, each of the first and second stacked units including a plurality of electrode layers alternately stacked with a plurality of first insulating layers therebetween, and
an intermediate insulating layer provided above the first stacked unit and below the second stacked unit; and
a columnar member piercing the stacked body in a stacking direction of the stacked body, the columnar member including an intermediate columnar part inside the intermediate insulating layer; wherein
a diameter of the intermediate columnar part in a first direction perpendicular to the stacking direction is broadened downwardly to a predetermined depth in a diameter broadening portion of the columnar member, a sidewall of the diameter broadening portion of the columnar member having a curved shape in a cross section along the stacking direction, the diameter of the intermediate columnar part being broadened downwardly on both sides of the diameter broadening portion in the first direction, and wherein
the predetermined depth does not reach any electrode layers functioning as word lines in the first stacked unit, memory cells being provided at intersections of the word lines and the columnar member.

US Pat. No. 10,461,087

STRUCTURE AND METHOD FOR FINFET SRAM

TAIWAN SEMICONDUCTOR MANU...

1. A method for semiconductor fabrication, comprising:forming mandrel patterns over a substrate using a first mask that defines the mandrel patterns, wherein the first mask includes at least four first patterns that are spaced from each other in a first direction, wherein each of the first patterns extends lengthwise in a second direction orthogonal to the first direction;
forming spacers on sidewalls of the mandrel patterns;
removing the mandrel patterns;
etching the substrate using the spacers as an etch mask, thereby forming fin lines in the substrate; and
performing a fin cut process using a second mask to remove selective ones of the fin lines, wherein the second mask includes at least four second patterns, each being an elongated shape extending lengthwise in the second direction, wherein the second patterns are spaced from each other in the first direction, and each of the second patterns covers a side of one of the first patterns when the first and second masks are superimposed, the side extending in the second direction.

US Pat. No. 10,461,084

COMPACT SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED NUMBER OF CONTACTS, METHODS OF OPERATING AND METHODS OF MAKING

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises:
a floating body region for storing charge indicating a state of said semiconductor memory cell; and
a back-bias region;
wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels;
wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;
wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and
a control circuitry configured to apply said voltage to said back-bias region.

US Pat. No. 10,461,080

METHOD FOR MANUFACTURING A FINFET DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:etching a semiconductor substrate of a wafer to form at least one fin;
forming an insulation structure around the fin;
recessing the fin;
epitaxially growing an epitaxial channel structure over the recessed fin;
removing a portion of the epitaxial channel structure over a top surface of the insulation structure;
performing a non-contact-type cleaning operation to clean a top surface of the wafer after removing said portion of the epitaxial channel structure;
cleaning the top surface of the wafer using hydrogen fluoride after removing said portion of the epitaxial channel structure; and
recessing the insulation structure such that the epitaxial channel structure protrudes from the recessed insulation structure.

US Pat. No. 10,461,066

STRUCTURE AND METHOD FOR HYBRID OPTICAL PACKAGE WITH GLASS TOP COVER

Maxim Integrated Products...

1. An optical package, comprising:a package substrate comprising at least one of: at least one die attach pad, at least one vent hole configured to prevent pop-corning of the panel level substrate or at least one pedestal;
an application specific integrated circuit (ASIC) die disposed on the package substrate, the application specific integrated circuit die including a detector;
at least one non-optical sensor die disposed on the package substrate;
a pre-molded polymer panel unit cell disposed on and coupled to the package substrate using a first adhesive film element, the pre-molded polymer panel unit cell including multiple sidewalls that form an outer perimeter and a middle sidewall that defines two cavities, the ASIC die disposed in a first cavity and the at least one non-optical sensor die disposed in a second cavity, the middle sidewall configured to restrict cross talk between the application specific integrated circuit die and the at least one non-optical sensor die, the middle sidewall further comprising a shelf-structure; and
an individual glass cover disposed on the pre-molded polymer panel unit cell, where the glass cover is transparent to an electro-magnetic spectral region detected by the ASIC die and the at least one non-optical sensor die, the individual glass cover adhesively bonded directly to the pre-molded polymer panel unit cell using a second adhesive film element, the individual glass cover adhesively bonded directly to the shelf-structure using a third adhesive film element.

US Pat. No. 10,461,065

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device, the method comprising:mounting a plurality of light emitting elements on a collective substrate;
arranging at least one light transmissive member for each light emitting device on an upper surface of each of the plurality of light emitting elements;
arranging a first protruding member that surrounds the plurality of light emitting elements on an upper surface of the collective substrate;
arranging a second protruding member between the plurality of light emitting elements on the upper surface of the collective substrate;
after the arranging the first protruding member and the second protruding member, forming a cover member that covers an upper end of the second protruding member, the light emitting elements, and a lateral surface of the light transmissive member in a region surrounded by the first protruding member; and
singulating the light emitting devices by dividing the cover member, the second protruding member, and the collective substrate at a portion including the second protruding member;
wherein an upper end of the second protruding member is located in the region surrounded by the first protruding member so as to be lower than an upper end of the first protruding member but higher than the upper surface of each of the light emitting elements, and
wherein the second protruding member is harder than the cover member.

US Pat. No. 10,461,060

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH REDISTRIBUTION LAYERS

Taiwan Semiconductor Manu...

1. A chip package, comprising:a semiconductor die;
a protective layer surrounding the semiconductor die;
an interface between the semiconductor die and the protective layer; and
a conductive layer over the protective layer and the semiconductor die, wherein the conductive layer has a first portion and a second portion, the first portion is closer to an inner portion of the semiconductor die than the second portion, the first portion is in direct contact with the second portion, the second portion extends across the interface, and in a top view of the conductive layer, the second portion has a line width greater than that of the first portion.

US Pat. No. 10,461,059

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH IMPROVED THERMAL PERFORMANCE AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A semiconductor die assembly, comprising:a thermally conductive casing;
a package substrate comprising a plurality of first raised bond pads that each have a first vertical height, wherein the package substrate and the thermally conductive casing together define an enclosure;
an interposer having a front side surface and an opposing back side surface, the back side surface attached to the thermally conductive casing within the enclosure and the front side surface comprising a plurality of second raised bond pads that each have a second vertical height;
a stack of semiconductor dies having a stack height disposed between the front side surface of the interposer and the package substrate within the enclosure; and
a plurality of conductive members interposed between the plurality of first raised bond pads and the plurality of second raised bond pads, wherein each conductive member of the plurality of conductive members include a solder bump having a third vertical height, and wherein a sum of the first, second, and third vertical heights is about equal to or greater than the stack height of the stack of semiconductor dies.

US Pat. No. 10,461,057

DUAL-INTERFACE IC CARD MODULE

NXP B.V., Eindhoven (NL)...

1. A dual-interface integrated circuit card module, the module comprising:a substrate having first and second opposing surfaces;
a contact pad on the first surface of the substrate;
an integrated circuit on the second surface of the substrate, the integrated circuit having electrical connections to the contact pad through the substrate; and
a pair of antenna pads for providing electrical contact, disposed in recesses in the second surface of the substrate and electrically connected to corresponding antenna connections on the integrated circuit,
wherein the recesses pass through the substrate, the antenna pads being attached to a back surface of the contact pad with a non-conductive material, the non-conductive material in contact with the antenna pads and the contact pad, and the non-conductive material providing an insulating layer between the antenna pads and the contact pad.

US Pat. No. 10,461,054

ANISOTROPIC CONDUCTIVE FILM AND PRODUCTION METHOD OF THE SAME

DEXERIALS CORPORATION, T...

1. An anisotropic conductive film in which conductive particles are dispersed in an insulating resin layer, the anisotropic conductive film comprising:a first conductive particle layer in which conductive particles are dispersed at a predetermined depth in a film thickness of the anisotropic conductive film; and
a second conductive particle layer in which conductive particles are dispersed at a depth that is different from that of the first conductive particle layer, wherein
in each of the conductive particle layers, a closest distance between the adjacent conductive particles is 2 times or more an average particle diameter of the conductive particles.

US Pat. No. 10,461,052

COPPER STRUCTURES WITH INTERMETALLIC COATING FOR INTEGRATED CIRCUIT CHIPS

Monolithic Power Systems,...

1. An integrated circuit (IC) chip comprising:a substrate comprising an integrated circuit;
a metal pad disposed on the substrate and electrically connects to the integrated circuit;
a redistribution layer that electrically connects to the metal pad;
a copper pillar that is disposed on and electrically connects to the redistribution layer;
a solder bump that is disposed on and electrically connects to the copper pillar; and
a tin-copper intermetallic coating that is formed on a surface of the copper pillar and the redistribution layer.

US Pat. No. 10,461,050

BONDING PAD STRUCTURE OF A SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor chip;
a metal electrode formed on a surface of the semiconductor chip; and
metal wiring connected to the metal electrode via a bonding part,
wherein an outer peripheral of the metal wiring is covered with a metal layer consisting of a metal or an alloy different from a constituent metal of the metal electrode,
the bonding part has an alloy region harder than the metal wiring, and
the metal layer is formed on an upper surface and a lower surface of at least the metal wiring, and a part of the lower surface contacts the bonding part.

US Pat. No. 10,461,049

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
an aluminum electrode provided on the semiconductor substrate;
a metallic film for a solder joint provided on the aluminum electrode; and
an organic protective film provided on the aluminum electrode and apart from the metallic film,
wherein an interval between the organic protective film and the metallic film is equal to or greater than half of a thickness of the organic protective film.

US Pat. No. 10,461,047

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a substrate having an insulating layer disposed thereon, the substrate having a perimeter;
a metallization structure disposed on the insulating layer, the metallization structure comprising conductive routing disposed in a dielectric material stack, wherein an uppermost layer of the metallization structure comprises first and second pluralities of conductive pads thereon;
a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing;
a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring; and
a metal-free region of the dielectric material stack surrounding the second metal guard ring, the metal-free region disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

US Pat. No. 10,461,045

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A power semiconductor device comprising:an insulating substrate having a metal layer which is formed on an upper surface of said insulating substrate;
a semiconductor element and a main electrode each bonded to an upper surface of said metal layer;
a metal ware connecting said metal layer and said semiconductor element;
a metal member bonded to a lower surface side of said insulating substrate;
a case member surrounding said insulating substrate and affixed to said metal member; and
a sealing resin filled in a region surrounded by said metal member and said case member, said sealing resin having a resin strength equal to or higher than 0.12 MPa at room temperature, a microcrystallization temperature equal to or lower than ?55° C. and a needle penetration of 30 to 50 after storage at 175° C. for 1000 hours, said sealing resin sealing said insulating substrate, said metal layer, said semiconductor element, said metal wire, and said main electrode.

US Pat. No. 10,461,043

METHOD OF MANUFACTURING AN ELECTROMAGNETIC SHIELD

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a precursor package having a plurality of integrated circuit (IC) modules, wherein:
an inter-module area is horizontally in between two adjacent IC modules of the plurality of IC modules; and
each of the plurality of IC modules comprises a module substrate and at least one electronic component that is attached to a top surface of the module substrate and encapsulated by a mold compound, wherein the module substrate comprises a ground plane formed within the module substrate, and a plurality of first input/output (I/O) contacts formed at a bottom surface of the module substrate;
placing the precursor package onto a chemical resistant tape, such that the plurality of first I/O contacts of each module substrate are sealed and against the chemical resistant tape;
performing a sweller process on the precursor package, which resides over the chemical resistant tape;
performing a desmear process on the precursor package, which resides over the chemical resistant tape;
removing the chemical resistant tape to expose the plurality of first I/O contacts;
singulating the precursor package at each inter-module area to form a plurality of individual IC modules, each of which comprises the module substrate;
placing the individual IC modules onto a top surface of a carrier tape, such that the plurality of first I/O contacts of each individual IC module are sealed and against the carrier tape; and
applying a shielding structure completely over a top surface and side surfaces of each of the plurality of individual IC modules to form a plurality of shielded IC modules, wherein the shielding structure is electrically coupled to the ground plane within the corresponding module substrate.

US Pat. No. 10,461,039

MARK, METHOD FOR FORMING SAME, AND EXPOSURE APPARATUS

NIKON CORPORATION, Tokyo...

1. A method for producing a device comprising:forming a pre-pattern on a mark formation area of a substrate;
applying a polymer layer containing a block copolymer to the pre-pattern;
allowing the polymer layer, applied to the pre-pattern, to form a self-assembled area;
selectively removing a portion of the self-assembled area;
forming an alignment mark by using the self-assembled area from which the portion of the self-assembled area has been removed;
illuminating the alignment mark formed on the substrate with an illumination light;
detecting the alignment mark by receiving a light from the alignment mark with a detector; and
changing a polarization state of the illumination light.

US Pat. No. 10,461,038

METHODS OF ALIGNMENT MARKING SEMICONDUCTOR WAFERS, AND SEMICONDUCTOR PACKAGES HAVING PORTIONS OF ALIGNMENT MARKINGS

Micron Technology, Inc., ...

1. A method for alignment marking a semiconductor wafer, comprising:defining die locations associated with the semiconductor wafer, and defining alignment mark locations between the die locations;
forming first alignment marks within the alignment mark locations at a first level of processing associated with the semiconductor wafer; the first alignment marks comprising first segments extending primarily along a first direction, and comprising second segments extending primarily along a second direction substantially orthogonal to the first direction;
forming second alignment marks within the alignment mark locations at a second level of processing associated with the semiconductor wafer; the second level of processing being subsequent to the first level of processing; the second alignment marks comprising third segments extending primarily along the first direction, and comprising fourth segments extending primarily along the second direction; and
forming a texture within the alignment mark locations, the texture having a pattern other than lines extending along either the first or second direction.

US Pat. No. 10,461,028

SEMICONDUCTOR DEVICE INCLUDING A VERTICAL ONE-TIME PROGRAMMABLE FUSE THAT INCLUDES A CONDUCTIVE LAYER AND A RESISTIVE MATERIAL AND A METHOD OF MAKING THE SAME

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a substrate;
forming a first insulating layer over the substrate;
forming a first opening through the first insulating layer;
forming a first conductive layer along a sidewall of the first opening; and
depositing a resistive material within the first opening over the first conductive layer, wherein:
the resistive material has a resistivity 10 times or greater than the first conductive layer, and
the first conductive layer and resistive material form a vertical one-time-programmable (OTP) fuse with electrically conductive properties associated with the fuse along the sidewall of the first opening.

US Pat. No. 10,461,027

SEMICONDUCTOR DEVICE INCLUDING VIA PLUG AND METHOD OF FORMING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a lower insulating layer on a substrate;
a conductive pattern in the lower insulating layer;
a middle insulating layer on the lower insulating layer and the conductive pattern;
a via control region in the middle insulating layer, the via control region having a lower etch rate than the middle insulating layer;
an upper insulating layer on the middle insulating layer and the via control region; and
a via plug passing through the via control region and connected to the conductive pattern.

US Pat. No. 10,461,022

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first die including a first surface and a second surface opposite to the first surface;
a molding surrounding the first die;
a via extended through the molding;
an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed below the first surface of the first die and the molding, and the conductive member is disposed within the dielectric layer;
a second die disposed over the molding and including a third surface facing the first die, a fourth surface opposite to the third surface and a sidewall between the third surface and the fourth surface;
a connector disposed between the second die and the via and being in contact with the third surface of the second die and the via; and
an underfill surrounding the connector and being in contact with a portion of the second surface of the first die,wherein the second die is electrically connected to the via, and the underfill covers a portion of the sidewall of the second die and exposes entirely the fourth surface of the second die.

US Pat. No. 10,461,014

HEAT SPREADING DEVICE AND METHOD

Taiwan Semiconductor Manu...

19. A method comprising:attaching a die stack to an interposer, the die stack comprising active devices, the interposer comprising interconnect structures, the interconnect structures of the interposer being electrically coupled to the active devices of the die stack after the attaching the die stack to the interposer;
encapsulating the die stack with an encapsulant;
forming a dummy through substrate via (TSV) in the die stack;
plating dummy metallization on the dummy TSV, the die stack, and the encapsulant;
forming a conductive feature on the dummy metallization, wherein the dummy TSV, the dummy metallization, and the conductive feature are electrically isolated from the active devices of the die stack and the interconnect structures of the interposer;
dispensing a thermal interface material around the conductive feature and on the dummy metallization; and
attaching a heat spreader to the die stack with the thermal interface material, the thermal interface material, the dummy metallization, and the conductive feature thermally coupling the heat spreader to the dummy TSV.

US Pat. No. 10,461,011

MICROELECTRONICS PACKAGE WITH AN INTEGRATED HEAT SPREADER HAVING INDENTATIONS

Intel Corporation, Santa...

13. A method of manufacturing a microelectronics package, the method comprising:attaching a first die, a second die, and a third die to a substrate;
forming a first indentation in a first surface of an integrated heat spreader;
forming a second indentation in the integrated heat spreader; and
attaching the integrated heat spreader to the first die, the second die, and the third die such that:
the first indentation is located in between the first die and the second die, and
the second indentation is located in between the third die and the first die and the second die.

US Pat. No. 10,461,010

POWER MODULE, POWER SEMICONDUCTOR DEVICE AND POWER MODULE MANUFACTURING METHOD

MITSUBISHI ELECTRIC CORPO...

1. A power module which comprises a power element, a metal base for dissipating heat from the power element, a lead frame electrically connected to electrodes of the power element, and a resin enclosure that encapsulates the power element so that one surface of the metal base and a part of the lead frame are exposed from the enclosure,said resin enclosure comprising:
a body portion in which the power element and a part of the lead frame are placed, and at a bottom surface of which said one surface of the metal base is exposed; and
a rib portion which is placed on the bottom surface of the body portion so as to surround an outer periphery of the metal base, and is formed to protrude from the bottom surface of the body portion in a direction perpendicular to the bottom surface, the rib portion extending lower than said one surface of the metal base;
wherein the rib portion has a depression at its end overhanging from the bottom surface.

US Pat. No. 10,461,009

3DIC PACKAGING WITH HOT SPOT THERMAL MANAGEMENT FEATURES

Taiwan Semiconductor Manu...

1. A package comprising:a die stack comprising:
a plurality of first dies; and
a second die bonded to the plurality of first dies, wherein a first portion of the second die is disposed directly under the plurality of first dies, and wherein a second portion of the second die extends laterally past sidewalls of the plurality of first dies; and
a package substrate, wherein the die stack is bonded to a top surface of the package substrate by a plurality of conductive connectors, and wherein the package substrate comprises:
a conductive line extending continuously from the plurality of conductive connectors to a thermal interface material (TIM) at the top surface of the package substrate; and
a solder resist, wherein the solder resist covers a first portion of the conductive line and does not cover a second portion of the conductive line, and wherein the TIM extends through the solder resist to contact the second portion of the conductive line.

US Pat. No. 10,461,008

ELECTRONIC COMPONENT PACKAGE HAVING STRESS ALLEVIATION STRUCTURE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer;
a semiconductor chip disposed on the wiring part;
a frame disposed on the wiring part, having upper and lower surfaces opposing each other, and including a component disposition region defined by an inner wall of the frame surrounding the semiconductor chip; and
an encapsulant filling at least a portion of the component disposition region,
wherein a portion of the inner wall of the frame has first and second protrusions, made of an insulating material and disposed on opposite sides of the semiconductor chip, protruding toward the semiconductor chip,
each of the first and second protrusions has an upper surface, a lower surface opposing the upper surface, and an end surface connecting the upper and lower surfaces of a respective one of the first and second protrusions and opposing the inner wall of the frame, the semiconductor chip disposed between the end surfaces of the first and second protrusions,
the upper surface of the frame and the upper surface of each of the first and second protrusions have a first step, and the lower surface of the frame and the lower surface of each of the first and second protrusions have a second step,
the encapsulant extends continuously from the upper surface of the frame to the second step and passes the first step, a space between the first protrusion and the semiconductor chip, and a space between the second protrusion and the semiconductor chip, and
no electrically conductive pattern is disposed directly on the upper surface or the lower surface of each of the first and second protrusions to be electrically connected to the semiconductor chip.

US Pat. No. 10,461,005

SEMICONDUCTOR PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a dielectric layer having a first surface and a second surface opposite to the first surface; and
a conductive post disposed in the dielectric layer, the conductive post comprising a first portion and a second portion disposed above the first portion, the second portion of the conductive post being recessed from the second surface of the dielectric layer,
wherein the second surface of the dielectric layer has an arithmetic average surface roughness (Ra) value, and wherein the Ra value is greater than approximately 450 nanometers (nm).

US Pat. No. 10,460,998

METHOD FOR INSPECTING SUBSTRATE, SUBSTRATE INSPECTION APPARATUS, EXPOSURE SYSTEM, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Nikon Corporation, Tokyo...

1. A method for inspecting a substrate comprising:irradiating infrared light of a plurality of different wavelengths onto a first surface or a second surface opposite to the first surface, of the substrate in which a pattern having a periodicity and extending from the first surface to an inside of the substrate is formed in the first surface, each of the plurality of different wavelengths of the infrared light having a permeability to permeate the substrate to a respective predetermined depth;
detecting, with respect to each of the wavelengths, a diffracted light diffracted by the pattern of the substrate, or a polarization component of light transmitted through the substrate; and
inspecting the substrate up as far as the predetermined depths based on detection results of the wavelengths regarding the diffracted light diffracted by the pattern of the substrate, or the polarization component of the light transmitted through the substrate,
wherein at least one of an incidence angle of the infrared light with respect to the substrate and an exit angle of the diffracted light or the transmitted light with respect to the substrate is changed in accordance with the plurality of different wavelengths.

US Pat. No. 10,460,996

FIN FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a fin field effect transistor (FinFET), comprising:providing a plurality of discrete fins on a semiconductor substrate;
forming a dummy gate across a length portion of the fins and covering portions of top and sidewall surfaces of the fins;
forming an interlayer dielectric layer, covering the dummy gate and the fins;
forming an opening in the interlayer dielectric layer by removing the dummy gate;
forming a gate dielectric layer in the opening and on the interlayer dielectric layer;
forming a barrier layer on the gate dielectric layer;
removing a portion of the gate dielectric layer on the interlayer dielectric layer and a portion of the barrier layer on the interlayer dielectric layer;
performing an annealing treatment after removing the portion of the gate dielectric layer on the interlayer dielectric layer and the portion of the barrier layer on the interlayer dielectric layer;
removing a remaining portion of the barrier layer in the opening after performing the annealing treatment; and
forming a metal gate in the opening.

US Pat. No. 10,460,995

METHOD OF MANUFACTURE OF A FINFET DEVICE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:depositing a first dummy gate stack and a second dummy gate stack, wherein the first dummy gate stack has a first channel length and the second dummy gate stack has a second channel length different from the first channel length;
depositing an interlayer dielectric around the first dummy gate stack and the second dummy gate stack;
planarizing the first dummy gate stack, the second dummy gate stack and the interlayer dielectric;
after planarizing the first dummy gate stack, implanting ions into the interlayer dielectric to form an implanted region;
after implanting ions into the interlayer dielectric, removing the first dummy gate stack and the second dummy gate stack to form a first opening and a second opening, wherein the removing the first dummy gate stack and the second dummy gate stack reduces a height of the interlayer dielectric; and
filling the first opening and the second opening with a conductive material.

US Pat. No. 10,460,991

RESIN PACKAGE SUBSTRATE PROCESSING METHOD

DISCO CORPORATION, Tokyo...

1. A resin package substrate processing method for processing a resin package substrate including a mold resin in which a filler having a plurality of filler particles is mixed, said resin package substrate processing method comprising:a fixing step of fixing said resin package substrate through an expandable adhesive tape to an annular frame having an inside opening in the condition where said resin package substrate is positioned in said inside opening of said annular frame;
a dividing step of applying a laser beam having an absorption wavelength to said mold resin of said resin package substrate, to said mold resin after performing said fixing step, thereby forming a plurality of division grooves and dividing said resin package substrate into a plurality of chips;
an interchip distance increasing step of expanding said adhesive tape after performing said dividing step, thereby increasing the distance between any adjacent ones of said chips to a distance greater than or equal to a maximum diameter of said filler particles caught between said adjacent chips; and
a cleaning step of supplying a cleaning liquid to said resin package substrate after performing said interchip distance increasing step, thereby removing said filler particles caught between said adjacent chips,
whereby when each chip is picked up from said adhesive tape, falling of said filler particles from each chip is prevented.

US Pat. No. 10,460,990

SEMICONDUCTOR VIA STRUCTURE WITH LOWER ELECTRICAL RESISTANCE

INTERNATIONAL BUSINESS MA...

12. A semiconductor device comprising:a first conductive line including a first conductive material;
a second conductive line including a second conductive material;
a via including opposing tapered sidewalls each having a lower end contacting the first conductive material and an upper end contact the second conductive material, a distance between the lower end of the tapered sidewalls being less than a distance between the upper end of tapered sidewalls, the via connecting the first conductive line and the second conductive line, wherein the via includes a via material disposed between the tapered sidewalls such that the via material includes a via material top surface extending between the upper end of the tapered sidewalls and a via material bottom surface, wherein the via material bottom surface has a first contact area extending between the lower end of the tapered sidewalls that is in direct physical contact with the first conductive line, wherein the via material top surface is convex and has a second contact area that is greater than the first contact area;
a first liner material coating inner surfaces of the via side walls; and
a second liner material coating the via material top surface,
wherein the via material top surface directly contacts a bottom surface of the second liner material.

US Pat. No. 10,460,983

METHOD FOR MANUFACTURING A BONDED SOI WAFER

SHIN-ETSU HANDOTAI CO.,LT...

1. A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, comprising, in sequential order, the steps of:depositing a polycrystalline silicon layer on the bonding surface side of the base wafer,
polishing a surface of the polycrystalline silicon layer,
forming the insulator film on the bonding surface of the bond wafer,
forming an ion-implanted layer in the bond wafer,
bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and
thinning the bonded bond wafer by delaminating along the ion-implanted layer in the bond wafer to form an SOI layer; wherein,
as the base wafer, a silicon single crystal wafer having a resistivity of 100 ?·cm or more is used,
the step for depositing the polycrystalline silicon layer further comprises a stage for previously forming an oxide film on the surface of the base wafer on which the polycrystalline silicon layer is deposited,
the polycrystalline silicon layer is deposited by a method consisting of two growth stages, a first growth performed at a first temperature of 900° C. or more and 1010° C. or less, and a second growth performed at a second temperature of 1100° C. or more to deposit the polycrystalline silicon layer thicker than in the first growth,
deposition of the polycrystalline silicon layer is performed using trichlorosilane as a source gas at atmospheric pressure in the first growth and the second growth,
the oxide film is formed by wet cleaning,
the oxide film has a thickness of 0.3 nm or more and 10 nm or less, and
the polycrystalline silicon layer has a thickness of 2 ?m or more when the base wafer and the bond wafer are bonded.

US Pat. No. 10,460,982

FORMATION OF SEMICONDUCTOR DEVICES WITH DUAL TRENCH ISOLATIONS

International Business Ma...

1. A method for fabricating a semiconductor device with dual trench isolations, comprising:forming a deep trench located between a first region associated with a first array of transistors and a second region associated with a second array of transistors;
forming a first shallow trench located between transistors within the first array and a second shallow trench located between transistors within the second array; and
forming, by a single dielectric material fill process, a deep trench isolation (DTI) region in the deep trench, a first shallow trench isolation (STI) region in the first shallow trench, and a second STI region in the second shallow trench.

US Pat. No. 10,460,976

SUBSTRATE TRANSFER DEVICE AND SUBSTRATE TRANSFER METHOD

TOKYO ELECTRON LIMITED, ...

1. A substrate transfer device, comprising:at least one first supporting portion and at least one second supporting portion configured to support a substrate from below the substrate;
an elevating mechanism configured to elevate the at least one second supporting portion up and down between a first position higher than a height of the at least one first supporting portion, which is maintained fixed, and a second position lower than the height of the at least one first supporting portion;
a control unit configured to control the elevating mechanism; and
a detecting unit configured to detect an external surface of the at least one second supporting portion,
wherein the control unit determines whether the at least one second supporting portion is in a required elevation state based on a detection result of the detecting unit,
the detecting unit includes a light projecting unit configured to irradiate light, and a light receiving unit configured to receive the light irradiated from the light projecting unit, and
the control unit controls the detecting unit to overlap an optical axis of the light with the at least one second supporting portion.

US Pat. No. 10,460,972

METHOD OF DETACHING SEMICONDUCTOR MATERIAL FROM A CARRIER AND DEVICE FOR PERFORMING THE METHOD

Infineon Technologies AG,...

1. A method of detaching semiconductor material from a carrier, the method comprising:providing a carrier having attached thereto a layer of semiconductor material, wherein the layer comprises an edge portion;
deflecting the carrier in an area of the carrier, on which the edge portion of the layer of semiconductor material is attached, in a direction having an angle greater than zero with respect to a surface of the layer of semiconductor material; and
guiding an air stream onto the edge portion of the layer of semiconductor material, wherein the air stream impacts on a deflected portion of the carrier, thereby removing only the edge portion of the semiconductor material from the carrier.

US Pat. No. 10,460,970

ELECTROSTATIC CHUCK

NGK Insulators, Ltd., Na...

1. An electrostatic chuck comprising:a dielectric layer including an oriented alumina sintered body having a degree of c-plane orientation of 5% or more, the degree of c-plane orientation being determined by a Lotgering method using an X-ray diffraction profile obtained by the irradiation of an X-ray in the 2? range of 20° to 70°;
a ceramic layer integrated with a surface disposed opposite a wafer placement surface of the dielectric layer; and
an electrostatic electrode between the dielectric layer and the ceramic layer,
wherein a proportion by volume of pores having a diameter of 0.2 ?m or more with respect to the volume of the oriented alumina sintered body is 130 ppm or less by volume.

US Pat. No. 10,460,969

BIPOLAR ELECTROSTATIC CHUCK AND METHOD FOR USING THE SAME

Applied Materials, Inc., ...

1. An electrostatic chuck comprising:a chuck body; and
a plurality of independently replaceable electrostatic chuck assemblies mounted in an array across the chuck body to define a substrate support surface suitable for supporting a large area substrate, at least a first electrostatic chuck assembly of the plurality of electrostatic chuck assemblies operable independent of an operation of a second electrostatic chuck assembly of the plurality of electrostatic chuck assemblies, wherein the first electrostatic chuck assembly is laterally spaced apart from the second electrostatic chuck assembly to form a gap therebetween, and wherein the chuck body comprises:
a port aligned with and configured to flow gas into the gap defined between the first and second electrostatic chuck assemblies.

US Pat. No. 10,460,967

OVERHEAD TRANSPORT VEHICLE SYSTEM AND TEACHING METHOD FOR OVERHEAD TRANSPORT VEHICLE

MURATA MACHINERY, LTD., ...

1. An overhead transport vehicle system comprising:a plurality of overhead transport vehicles each including:
a winding drum to wind a hoisting material, attached to a lift stage to transfer goods, by lap winding; and
a controller that controls an amount of rotation of the winding drum to control a height of the lift stage;
a storage that stores the amount of rotation of the winding drum corresponding to an overall length of the hoisting material, unique to each of the plurality of overhead transport vehicles; and
a calculator that calculates the amount of rotation of the winding drum, corresponding to a corresponding one of a plurality of transfer heights, for each of the plurality of overhead transport vehicles, from the amount of rotation unique to each of the plurality of overhead transports vehicle stored in the storage.

US Pat. No. 10,460,965

SUSCEPTOR

MARUWA CO., LTD., Owaria...

1. A susceptor having an upper surface on which a wafer is placed and a lower surface arranged on a side opposite to the upper surface, and configured to be rotated about a spindle which extends in a vertical direction, wherein:a bearing formed of a recessed section receiving the spindle is formed on the lower surface,
the bearing has a shape where the bearing is tip-narrowed toward the upper surface from the lower surface, and
a gap is formed in a side wall of the bearing such that the gap projects toward the outside of the bearing from a fitting surface between the bearing and the spindle in a horizontal direction perpendicular to the vertical direction,
wherein the fitting surface between the bearing and the spindle accounts for 80% or more of an area of a portion of a side surface of the spindle inserted into the bearing,
wherein a distal end portion of the spindle has a tapered shape, and
wherein the spindle engages the bearing at a downstream end of the distal end portion of the spindle where a size of the spindle agrees with a size of the bearing,
wherein the spindle is made of metal having higher thermal conductivity than a material of the susceptor.

US Pat. No. 10,460,964

SUBSTRATE LIQUID PROCESSING APPARATUS AND METHOD, AND COMPUTER-READABLE STORAGE MEDIUM STORED WITH SUBSTRATE LIQUID PROCESSING PROGRAM

Tokyo Electron Limited, ...

1. A substrate liquid processing apparatus comprising:a liquid processing chamber of which a top is opened, and configured to process a substrate with a processing liquid;
a processing liquid supply source connected to the liquid processing chamber through a processing liquid supply path provided with a first flow rate controller, and configured to supply the processing liquid to the liquid processing chamber through the processing liquid supply path;
a diluent supply source connected to the liquid processing chamber through a diluent supply path provided with a second flow rate controller, and configured to supply a diluent for diluting the processing liquid to the liquid processing chamber through the diluent supply path;
a controller configured to control the first flow rate controller and the second flow rate controller;
a concentration sensor connected to the controller, and provided on a circulation path of which both ends are connected with the liquid processing chamber, the concentration sensor being configured to detect a concentration of the processing liquid;
an atmospheric pressure sensor connected to the controller and configured to detect an atmospheric pressure,
wherein the controller is programmed to:
identify a set atmospheric pressure and a set concentration of the processing liquid, respectively;
detect the concentration of the processing liquid and the atmospheric pressure using the concentration sensor and the atmospheric pressure sensor, respectively;
when the detected atmospheric pressure is not equal to the set atmospheric pressure, correct the set concentration of the processing liquid according to the detected atmospheric pressure; and
when the detected concentration of the processing liquid is not equal to the set concentration of the processing liquid, control the second flow rate controller of the diluent supply path such that an amount of the diluent supplied from the diluent supply source to the liquid processing chamber is adjusted, thereby allowing the detected concentration of the processing liquid to become the set concentration of the processing liquid.

US Pat. No. 10,460,962

SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus, comprising:a holding plate provided with a first through hole and configured to hold a substrate;
a rotation driving unit configured to rotate the holding plate;
a lift pin provided above the holding plate and configured to support the substrate from below;
a liquid supply unit provided to pass through the first through hole and configured to supply a liquid to a rear surface of the substrate held by the holding plate; and
an elevating device configured to move the lift pin and the liquid supply unit up and down between at a neighboring position where the lift pin and the liquid supply unit are adjacent to the holding plate and the substrate is held and at a distanced position where the lift pin and the liquid supply unit are distanced upwards from the holding plate and the substrate is carried out,
wherein the elevating device comprises a first lifting member configured to move the lift pin to the distanced position,
the first lifting member is in a disconnected state with respect to the lift pin when the lift pin and the liquid supply unit are located at the neighboring position, and
when the lift pin and the liquid supply unit are moved from the neighboring position to the distanced position, the first lifting member is turned from the disconnected state to a connected state where the first lifting member is connected to the lift pin, and the elevating device raises only the lift pin without raising the liquid supply unit for a time during which the first lifting member is moved up to a preset position, where the lift pin comes into contact with the rear surface of the substrate, while being connected to the lift pin, and raises the lift pin and the liquid supply unit for a time during which the first lifting member is raised from the preset position to the distanced position.

US Pat. No. 10,460,959

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A manufacturing method of a package structure, comprising:providing a carrier;
bonding a semiconductor chip on the carrier, wherein the semiconductor chip comprises a plurality of conductive pads exposed at an active surface of the semiconductor chip;
forming an insulating material layer over the carrier and encapsulating the semiconductor chip after the semiconductor chip is bonded on the carrier, wherein the insulating material layer comprises a first surface and a second surface opposite to the first surface, a thickness of the insulating material layer is greater than a thickness of the semiconductor chip, and the plurality of conductive pads are covered by the insulating material layer;
patterning the first surface of the insulating material layer to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer;
forming a plurality of conductive posts in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip, and the plurality of conductive posts extend onto the first surface of the insulating layer;
forming a plurality of conductive vias in the second openings, wherein the plurality of conductive vias extend onto the first surface of the insulating layer;
forming a redistribution layer over the first surface of the insulating material layer, wherein the redistribution layer is electrically connected to the plurality of conductive posts and the plurality of conductive vias;
de-bonding the carrier; and
forming a plurality of conductive terminals on the second surface of the insulating material layer, wherein the plurality of conductive terminals is electrically connected to the redistribution layer through the plurality of conductive vias.

US Pat. No. 10,460,958

METHOD OF MANUFACTURING EMBEDDED PACKAGING WITH PREFORMED VIAS

Invensas Corporation, Sa...

1. A method of forming a microelectronic assembly, comprising:forming a structure including a microelectronic element having a front surface, edge surfaces bounding the front surface, and contacts at the front surface, and substantially rigid metal posts extending in a first direction, the posts disposed between at least one of the edge surfaces and a corresponding edge of the structure, each metal post having a sidewall separating first and second end surfaces of such metal post from one another, the sidewalls of the metal posts having a root mean square (rms) surface roughness of less than about 1 micron; and then,
forming an encapsulation having a thickness extending in the first direction between first and second surfaces of the encapsulation, the encapsulation contacting at least the edge surfaces of the microelectronic element and the sidewalls of the metal posts, wherein the metal posts extend at least partly through the thickness, and the encapsulation electrically insulates adjacent metal posts from one another;
depositing an insulation layer overlying the first surface of the encapsulation and having a thickness extending away from the first surface of the encapsulation;
forming connection elements directly adjacent and extending away from the first end surfaces of the metal posts and through the thickness of the insulation layer, wherein at least some connection elements have cross sections smaller than respective cross sections of the metal posts from which the connection elements extend;
depositing an electrically conductive redistribution structure on the insulation layer, the redistribution structure electrically connecting at least some metal posts with the contacts of the microelectronic element; and
forming terminals at a first side of the microelectronic assembly adjacent to the first surface of the encapsulation, wherein at least some of the at least some connection elements electrically connect at least some of the first end surfaces with corresponding terminals.

US Pat. No. 10,460,955

METHODOLOGY FOR ANNEALING GROUP III-NITRIDE SEMICONDUCTOR DEVICE STRUCTURES USING NOVEL WEIGHTED COVER SYSTEMS

The United States of Amer...

1. A method for preventing the escape of nitrogen from a Group-III nitride semiconductor covered with an annealing cap during annealing, the method comprising:covering the annealing cap on the Group-III nitride semiconductor with a weighted cover system comprising a protective cover placed on top of the capped Group-III nitride semiconductor; and
annealing the Group-III nitride semiconductor while covered with the weighted cover system at a temperate in excess of 1250° C. for at least 30 minutes,
wherein the weighted cover system provides a sufficient force for preventing the escape of nitrogen from the capped Group-III nitride semiconductor and delamination of the annealing cap from the Group-III nitride semiconductor during said annealing; and
wherein the protective cover has sufficient flexibility and sufficient force applied to permit it to conform to the bow or warpage of the capped semiconductor and to maintain intimate contact with the capped semiconductor surface during the annealing.

US Pat. No. 10,460,952

STRESS RELIEVING SEMICONDUCTOR LAYER

Sensor Electronic Technol...

1. A structure comprising:a substrate;
a nucleation layer located on the substrate, wherein the nucleation layer is formed of a plurality of nucleation islands; and
a cavity containing layer located over the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

US Pat. No. 10,460,948

STRESS ASSISTED WET AND DRY EPITAXIAL LIFT OFF

International Business Ma...

1. A method, comprising:providing a sacrificial release layer on a base substrate;
forming a device layer on the sacrificial release layer;
depositing a metal stressor layer on the device layer;
creating a curvature in the device layer and causing the device layer to bend away from the base substrate at a first edge of the device layer such that the device layer remains in contact with the sacrificial release layer at least at a second opposing edge of the device layer;
etching the sacrificial release layer from an end surface thereof as the device layer is caused to bend away from the first edge and as the sacrificial release layer is exposed; and
releasing the device layer and the metal stressor layer from the base substrate.

US Pat. No. 10,460,931

SEMICONDUCTOR TRANSISTOR HAVING SUPERLATTICE STRUCTURES

Robert Bosch GmbH, Stutt...

1. A transistor, comprising:a substrate of a first doping type;
an epitaxy layer of the first doping type above the substrate;
a channel layer of a second doping type, which differs from the first doping type, above the epitaxy layer;
a plurality of trenches in the channel layer, which have a gate electrode situated within the trenches and are bordered by a source terminal of the first doping type above the channel layer;
a plurality of shielding areas of the second doping type situated below the gate electrode;
wherein the shielding areas form together an interconnection of shielding areas below the trenches and several of the shielding areas are jointly guided to terminals for contacting the shielding areas,
wherein a grid is made up of first cells, which are formed from the channel terminal of the second doping type for contacting the channel layer and a source terminal bordering the channel terminal, the first cells being bordered by trenches, the grid having gaps into which second cells are inserted, which have the terminals for the shielding areas for contacting the interconnection of the shielding areas.

US Pat. No. 10,460,930

SELECTIVE GROWTH OF SIO2 ON DIELECTRIC SURFACES IN THE PRESENCE OF COPPER

Lam Research Corporation,...

1. A method of selectively depositing silicon oxide on a dielectric material relative to copper on a substrate, the method comprising:(a) providing the substrate comprising the dielectric material and exposed copper metal surface;
(b) prior to depositing the silicon oxide, exposing the substrate to a copper-blocking reagent to selectively adsorb onto the exposed copper metal surface;
(c) exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto the dielectric material;
(d) exposing the substrate to an oxidizing plasma generated in an environment comprising a weak oxidant to convert the adsorbed silicon-containing precursors to silicon oxide; and
(e) exposing the substrate to a reducing agent to reduce the exposed copper metal surface.

US Pat. No. 10,460,925

METHOD FOR PROCESSING SEMICONDUCTOR DEVICE

United Microelectronics C...

1. A method for processing a semiconductor device, wherein the semiconductor device comprises a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure, the method comprising:removing the nitride spacer on the protruding structure, wherein a portion of the epitaxial layer under the nitride spacer is further exposed;
performing a dilute hydrofluoric acid (DHF) cleaning process over the substrate after removing the nitride spacer, wherein a top surficial portion of the epitaxial layer is removed; and
performing a standard clean (SC) process over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

US Pat. No. 10,460,924

PROCESS FOR PRODUCING A GALLIUM ARSENIDE SUBSTRATE WHICH INCLUDES MARANGONI DRYING

FREIBERGER COMPOUND MATER...

1. A process for producing a surface-treated gallium arsenide substrate, the process comprising the following sequence of steps:a) oxidation treatment of at least one surface of a gallium arsenide substrate in dry condition by means of UV radiation and/or ozone gas;
b-i) contacting the at least one surface of the gallium arsenide substrate with an alkaline aqueous solution;
b-ii) contacting the at least one surface of the gallium arsenide substrate with water;
b-iii) contacting the at least one surface of the gallium arsenide substrate with an acidic aqueous solution comprising ozone as an oxidizing agent, wherein the ozone concentration in the acidic aqueous solution is between 10 ppm and 100 ppm;
b-iv) contacting the at least one surface of the gallium arsenide substrate with water, wherein the water at least initially contains a pH value modifying additive comprising NH3 in an amount to make the water sufficiently basic to remove oxides or prevent oxide formation on the at least one surface; and
c) Marangoni drying of the gallium arsenide substrate.

US Pat. No. 10,460,918

FORMING ION PUMP HAVING SILICON MANIFOLD

COLDQUANTA, INC, Boulder...

1. An ion-pump formation process comprising:forming a silicon manifold by forming a Penning-trap aperture and a flow aperture in a block of monocrystalline silicon, the Penning trap aperture being formed between a first pair of faces of the silicon block, the flow aperture being formed between a second pair of faces of the silicon block;
coating walls of the Penning-trap aperture and the flow aperture with conductive material, the resulting coated wall of the Penning-trap aperture defining a wall anode;
positioning cathodes so that the wall anode is located between the cathodes; and
hermetically sealing a volume including the cathode aperture and the cathodes.

US Pat. No. 10,460,914

FERRITE CAGE RF ISOLATOR FOR POWER CIRCUITRY

LAM RESEARCH CORPORATION,...

1. Apparatus for providing isolated power to a component of a plasma processing chamber that also is subject to a plurality of RF signals, the plurality of RF signals including at least a first RF signal having a first RF frequency, the apparatus comprising:first and second coils; and
a ferrite cage that surrounds said first and second coils, said ferrite cage comprising:
a first dielectric disc supporting said first coil;
a second dielectric disc supporting said second coil;
first and second pluralities of ferrite pieces disposed on a side of said first dielectric disc facing away from said second dielectric disc;
third and fourth pluralities of ferrite pieces disposed on a side of said second dielectric disc facing away from said first dielectric disc;
the first through fourth pluralities of ferrite pieces being arranged such that the first and second dielectric discs and the first and second coils are inside the first through fourth pluralities of ferrite pieces;
a fifth plurality of ferrite pieces to connect respective ones of the first and second pluralities of ferrite pieces to the third and fourth pluralities of ferrite pieces;
said fifth plurality of ferrite pieces to separate said first and second dielectric discs so that the first and second coils are spaced apart by a predetermined distance; and
said first coil to receive an input voltage signal and said second coil to provide an isolated power signal.

US Pat. No. 10,460,908

MULTI CHARGED PARTICLE BEAM WRITING APPARATUS AND MULTI CHARGED PARTICLE BEAM WRITING METHOD

NuFlare Technology, Inc.,...

1. A multiple charged particle beam writing apparatus comprising:an emission source configured to emit a charged particle beam;
a shaping aperture array substrate configured to form multiple charged particle beams by being irradiated with the charged particle beam;
a combination setting circuitry configured to set, for each of a plurality of design grids being irradiation positions in design of the multiple charged particle beams, a plurality of combinations each composed of three beams whose actual irradiation positions surround a design grid concerned in the plurality of design grids, by using four or more beams whose actual irradiation positions are close to the design grid concerned;
a first distribution coefficient calculation circuitry configured to calculate, for each of the plurality of combinations, a first distribution coefficient for each of the three beams configuring a combination concerned in the plurality of combinations, for distributing a dose to irradiate the design grid concerned to the three beams configuring the combination concerned such that a position of a gravity center of each distributed dose coincides with a position of the design grid concerned and a sum of the each distributed dose coincides with the dose to irradiate the design grid concerned, where at least one the first distribution coefficient is calculated for the each of the four or more beams;
a second distribution coefficient calculation circuitry configured to calculate, for each of the four or more beams, a second distribution coefficient of the each of the four or more beams relating to the design grid concerned by dividing a total value of the at least one the first distribution coefficient corresponding to a beam concerned in the four or more beams by a number of the plurality of combinations; and
a writing mechanism configured to write a pattern on a target object with the multiple charged particle beams in which the dose to irradiate each of the plurality of design grids has been distributed to each corresponding one of the four or more beams.

US Pat. No. 10,460,905

BACKSCATTERED ELECTRONS (BSE) IMAGING USING MULTI-BEAM TOOLS

KLA-Tencor Corporation, ...

1. An apparatus, comprising:an electron source;
a beamlet control mechanism configured to produce a plurality of beamlets utilizing electrons provided by the electron source, the beamlet control mechanism further configured to deliver one of the plurality of beamlets toward a target at a time-instance, wherein the beamlet control mechanism comprises at least one of an aperture plate, an aperture array, or one or more blanking devices; and
a detector configured to produce an image of the target at least partially based on electrons backscattered out of the target, wherein the detector is further configured to receive electrons backscattered out of the target for two or more beamlets delivered toward the target at two or more time-instances, wherein the detector is further configured to produce the image of the target at least partially based on a sum of the received backscattered electrons.

US Pat. No. 10,460,901

COOLING SPIRAL GROOVE BEARING ASSEMBLY

General Electric Company,...

1. A bearing assembly comprising:a shell;
a shaft defining a bore therein and rotatably disposed within the shell; and
a cooling tube disposed within the bore of the shaft, the cooling tube including at least one turbulence-inducing feature.

US Pat. No. 10,460,894

GAS CIRCUIT BREAKER

MITSUBISHI ELECTRIC CORPO...

1. A gas circuit breaker comprising:a first tank filled with an insulating gas;
a fixed contact provided inside the first tank;
a movable contact provided inside the first tank and movable between a position in contact with the fixed contact and a position separated from the fixed contact;
a nozzle that ejects the insulating gas toward the fixed contact when the movable contact moves in a first direction, the first direction being a direction in which the movable contact moves from the position in contact with the fixed contact to the position separated from the fixed contact;
a cylindrical body, provided inside the first tank, that guides the gas ejected from the nozzle in a second direction, the second direction being a direction opposite to the first direction; and
a second tank connected to the first tank in the second direction, wherein
the second tank has a cylindrical shape centering on an axis extending in a direction perpendicular to the first direction as a central axis,
the first tank includes an opening formed on one end side thereof along an axis extending in the first direction, said opening being separated from the cylindrical body, and
the insulating gas elected from the nozzle is elected in the first tank and flows into the second tank via the opening.

US Pat. No. 10,460,891

KEYBOARD DEVICE AND ELECTRONIC APPARATUS

NEC PERSONAL COMPUTERS, L...

1. A keyboard device comprising:a first sheet-like member;
a membrane sheet disposed on an upper surface of the first sheet-like member;
a second sheet-like member disposed on an upper surface of the membrane sheet and supports the membrane sheet between the first sheet-like member and the second sheet-like member while being movable in an in-plane direction;
a connection member connecting the first sheet-like member and the second sheet-like member;
a plurality of key tops vertically movable and supported by a guide mechanism on an upper surface side of the second sheet-like member and brings the membrane sheet into contact with the second sheet-like member or separates the contact from the second sheet-like member;
a frame member partitioning adjacent key tops and having a lower surface to which the upper surface of the second sheet-like member is bonded and fixed; and
a support between the first sheet-like member and the second sheet-like member and regulates an interval between the first sheet-like member and the second sheet-like member to a dimension larger than a plate thickness of the membrane sheet.

US Pat. No. 10,460,880

CAPACITORS HAVING ENGINEERED ELECTRODES WITH VERY HIGH ENERGY DENSITY AND ASSOCIATED METHOD

GranBlueTech, L.L.C., Bu...

1. An apparatus comprising:a capacitor that includes:
an anode; and
a cathode,
wherein the cathode has a surface facing the anode that is covered by a first dielectric film having a dielectric constant of at least ten,
wherein the anode has a surface facing the cathode that includes a refractory material,
wherein the cathode is formed by a process that includes photolithography,
wherein the capacitor maintains a vacuum in a region that separates the surface of the anode that includes a refractory material and the first dielectric coating on the cathode, and
wherein the cathode surface maintains an operational emission current of less than one ampere per square meter.

US Pat. No. 10,460,873

ENHANCING DIELECTRIC CONSTANTS OF ELASTOMER SHEETS

Facebook Technologies, LL...

1. A method comprising:receiving an uncured elastomer;
depositing dielectric ceramic particulates having a value of a dielectric constant satisfying one or more conditions onto the uncured elastomer;
receiving an additional uncured elastomer;
layering the additional uncured elastomer onto the dielectric ceramic particulates deposited onto the uncured elastomer;
depositing additional dielectric ceramic particulates having an additional value of an additional dielectric constant satisfying the one or more conditions;
curing the uncured elastomer and the additional uncured elastomer for an interval of time and at a specified temperature within a mold having an anode and a cathode; and
for at least a portion of the interval of time during the curing while a temperature within the mold is within a threshold amount of a Curie temperature of the dielectric ceramic particulates or of the additional dielectric ceramic particulates, applying an electric field by applying a voltage to the anode and to the cathode of the mold including the uncured elastomer and the additional uncured elastomer such that a cured elastomer and the uncured elastomer have different dielectric constants.

US Pat. No. 10,460,869

MULTI-SERIES CONTINUOUS-FLOW MAGNETOELECTRIC COUPLING PROCESSING SYSTEM AND APPLICATIONS THEREOF

Jiangnan University, Wux...

1. A multi-series continuous-flow magnetoelectric coupling processing system, comprising:more than two stages of induction units, wherein each stage of the induction unit comprises:
a closed iron core,
a primary coil, wound around one side of the closed iron core, and
a secondary coil, wound around an opposite side of the closed iron core and arranged in an induction voltage chamber, wherein the secondary coil comprises an insulation pipe for circulation of a feed liquid, and two ends of the insulation pipe are exposed from the induction voltage chamber and respectively act as a feeding hole and a discharge hole;
a high frequency power supply, in connection with the primary coils of the more than two stages of the induction units and providing excitation voltage for each of the primary coils; and
a feed liquid container, in series connection with the insulation pipes of the more than two stages of the induction units to form a feed liquid circulation loop.

US Pat. No. 10,460,867

UPRIGHT COMPOSITE COMMON MODE COIL ASSEMBLY

Yujing Technology Co., Lt...

1. An upright composite common mode coil assembly comprising:a coil carrier including two bobbins, a group of coils being wounded around the outer circumference of each of the bobbins; and
a seat including:
a base having a back plate on a surface thereof, hollow portions formed at an upper position and a lower position of the back plate, a wire slot provided at either side of the back plate, and an indentation extending from one end of each of the wire slots;
a bottom portion extending vertically from a side of the base closer to the indentations, a recessed portion formed at each of the corners of the bottom portion, and a pin inserted into each of the recessed portions;
a top portion extending vertically from another side of the base and including a flat top face; and
a separating portion extending from another surface of the base and being tapered to form a curved surface, and the separating portion forming a receiving slot with the top portion and another receiving slot with the bottom portion,
wherein some of the recessed portions are in communication with the indentations, while the rest of the recessed portions respectively form notches with adjacent regions of the bottom portion;
wherein one bobbin of the coil carrier is received in each of the receiving slots of the seat, and wires of a group of the coils are guided into some of the recessed portions through the wire slots and the indentations, and wires of another group of the coils are guided into the other recessed portions through the notches, so that the wires of the coils do not protrude out of the seat and are neatly soldered on the pins; and
wherein a wing portion extends from a side of each indentation, and a concaved portion is formed between each indentation and its corresponding wing portion.

US Pat. No. 10,460,862

MAGNESIUM DIBORIDE SUPERCONDUCTING THIN-FILM WIRE AND METHOD FOR PRODUCING SAME

HITACHI, LTD., Tokyo (JP...

1. A magnesium diboride superconducting thin-film wire, comprising:a long substrate;
a magnesium diboride thin film formed on the long substrate, wherein the magnesium diboride thin film includes magnesium diboride columnar crystal grains; and
a transition metal element layer formed on the magnesium diboride thin film, wherein the transition metal layer is diffused into grain boundaries of the magnesium diboride columnar crystal grains;
wherein:
the magnesium diboride thin film has a microtexture such that the magnesium diboride columnar crystal grains stand densely together on a surface of the long substrate, and
the transition metal element layer is formed from a predetermined transition metal element that has a body-centered cubic lattice structure.

US Pat. No. 10,460,861

HIGH SPEED ROTOR CONNECTION ASSEMBLY

HAMILTON SUNDSTRAND CORPO...

1. A resistor pack assembly comprising:a positive rail having a circular face;
a negative rail having an inner circular face and an outer circular face located radially outward from the inner circular face;
an insulator ring having a first circular face and a second circular face opposite the first circular face, the second circular face contacts the outer circular face of the negative rail;
a first DC bus bar electrically connected to the insulator ring;
a second DC bus bar electrically connected to the negative rail; and
a cylindrical suppression resistor having a first flat surface and a second flat surface opposite the first flat surface, the cylindrical suppression resistor is located radially inward of the insulator and axially between the positive rail and the negative rail, wherein the first flat surface contacts the circular face of the positive rail and the second flat surface contacts the inner circular face of the negative rail.

US Pat. No. 10,460,849

LIGHTWEIGHT, HIGH-CONDUCTIVITY, HEAT-RESISTANT, AND IRON-CONTAINING ALUMINUM WIRE, AND PREPARATION PROCESS THEREOF

CENTRAL SOUTH UNIVERSITY,...

1. A lightweight, high-conductivity, heat-resistant, and iron-containing aluminum wire comprising the following components in percentage by weight:B 0.04-0.10 wt. %;
Zr 0.10-0.15 wt. %;
Fe 0.10-0.20 wt. %;
La 0.05-0.30 wt. %; and
inevitable titanium, vanadium, chromium, and manganese with a total content less than 0.01 wt. %, and aluminum as the remaining.

US Pat. No. 10,460,838

AUTOMATED ANATOMICALLY-BASED REPORTING OF MEDICAL IMAGES VIA IMAGE ANNOTATION

INTERNATIONAL BUSINESS MA...

1. Non-transitory computer-readable medium including instructions that, when executed by an electronic processor, cause the electronic processor to perform a set of functions, the set of functions comprising:receiving a first annotation for a medical image;
automatically determining a location within an electronic structured report associated with the first annotation based on a predetermined mapping;
automatically populating the location of the electronic structured report based on the first annotation with medical data associated with the annotation; and
updating the first annotation displayed within the medical image to display the first annotation in a first manner different from a second manner used to display a second annotation within the medical image not mapped to any location within the electronic structured report.

US Pat. No. 10,460,825

SORTING NON-VOLATILE MEMORIES

International Business Ma...

1. A method, executed by one or more processors, for sorting non-volatile random access memories (NVRAMS), the method comprising:testing, via the one or more processors, a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS;
determining, via the one or more processors, a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data;
physically separating, via the one or more processors, the plurality of NVRAMS into routing groups based on the trend in the failure metric as a function of testing cycles; and
physically routing, via the one or more processors, the routing groups within a manufacturing environment.

US Pat. No. 10,460,816

SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS

Sandisk Technologies LLC,...

1. An apparatus, comprising:a memory structure, comprising:
a plurality of memory cells, and
a write circuit to apply a single programming pulse to a group of memory cells in response to a command; and
command processing logic configured to complete the command in response to the single programming pulse and mark the group for background verification.

US Pat. No. 10,460,815

DECODING METHOD OF SELECTING OPTIMIZED READ VOLTAGE SET BASED ON GRAY CODE COUNT DEVIATION SUMMATIONS, AND STORAGE CONTROLLER USING THE SAME

Shenzhen EpoStar Electron...

1. A decoding method for a storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of word lines, each of the word lines comprises a plurality of memory cells, each of the memory cells is programmed to store a bit value corresponding to one of a plurality of different Gray codes, a total number of the Gray codes is N, N is a first predetermined positive integer greater than 2, and the method comprises:choosing a target word line of the word lines, wherein a plurality of target memory cells of the target word line are programmed;
reading the target memory cells by respectively using a plurality of different X read voltage sets to obtain X Gray code count deviation summations, wherein X is a second predetermined positive integer, the X read voltage sets and the corresponding X Gray code count deviation summations are ordered based on a first predetermined order, each of the X read voltage sets has N?1 read voltages ordered based on a second predetermined order, and an ith Gray code count deviation summation in the X Gray code count deviation summations corresponds to an ith read voltage set of the X read voltage sets, wherein i is 1 to X based on the first predetermined order; and
choosing one of the X read voltage sets as an optimized read voltage set based on the X Gray code count deviation summations.

US Pat. No. 10,460,807

INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES

Conversant Intellectual P...

1. A flash memory device comprising:a memory cell array comprising a first string and a second string, each of the first and the second string comprising a plurality of erasable memory cells, each memory cell of the first string being connected to a respective word line of a first set of word lines, and each memory cell of the second string being connected to a respective word line out of a second set of word lines;
a first string select line, a first ground select line and a first local erase line each being connected to the first string;
a second string select line, a second ground select line and a second local erase line each being connected to the second string, the first and second string select line, the first and second ground select line, the first and second local erase line and each word line of the first and second sets of word lines running in a first direction;
a first pass block circuit comprising a first group of transistors located at an edge outside of the memory cell array, the first group of transistors comprising a first erase voltage pass transistor; and
a second pass block circuit comprising a second group of transistors located at one of the edge or another edge outside of the memory cell array, the second group of transistors comprising a second erase voltage pass transistor,
the first local erase line being coupled to the first erase voltage pass transistor and at least one of the first string select line being coupled to a first string select signal pass transistor of the first group of transistors, the first ground select line being coupled to a first ground select signal pass transistor of the first group of transistors, and a word line of the first set of word lines being coupled to a first word line pass transistor of the first group of transistors; and
the second local erase line being coupled to the second erase voltage pass transistor and at least one of the second string select line being coupled to a second string select signal pass transistor of the second group of transistors, the second ground select line being coupled to a second ground select signal pass transistor of the second group of transistors, and a word line of the second set of word lines being coupled to a second word line pass transistor of the second group of transistors,
wherein the first word line pass transistor is coupled to one of the first set of word lines, and the second word line pass transistor is coupled to one of the second set of word lines,
wherein the gate electrode of the first word line pass transistor and the gate electrode of the first erase voltage pass transistor are electrically in direct connection to each other,
wherein the gate electrode of the second word line pass transistor and the gate electrode of the second erase voltage pass transistor are electrically in direct connection to each other.

US Pat. No. 10,460,805

SEMICONDUCTOR CIRCUIT, METHOD OF DRIVING SEMICONDUCTOR CIRCUIT, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A semiconductor circuit, comprising:a first circuit that is able to generate, on a basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node;
a second circuit that is able to generate, on a basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node;
a first transistor that couples the first node to a third node when in an on state;
a second transistor that supplies a first direct-current voltage to the third node when in an on state;
a third transistor that includes a drain or a source to be coupled to the third node and that includes a gate coupled to the first node or the second node; and
a first storage element that includes a first terminal coupled to the third node and is able to take a first resistance state or a second resistance state,
the first circuit and the second circuit being configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.

US Pat. No. 10,460,804

VOLTAGE-CONTROLLED RESISTIVE DEVICES

Massachusetts Institute o...

1. A memristive element comprising:a conductive material layer disposed in a x-y plane, the conductive material layer being configured to reversibly uptake an amount of at least one ionic species;
a first electrode coupled proximate to a first end of the conductive material layer;
a second electrode coupled proximate to a second end of the conductive material layer, opposite to the first end;
a gate dielectric layer disposed over the conductive material layer, the gate dielectric layer being configured to supply to, or receive from, the conductive material layer, an amount of the at least one ionic species; and
a gate electrode layer disposed over, and in electrical communication with, the gate dielectric material layer;
an inert metal underlayer disposed in electrical communication with the conductive material layer and coupled to the first electrode and the second electrode to shunt a portion of a current flowing between the first electrode and the second electrode;
the gate electrode layer, the gate dielectric layer, and the conductive material layer being configured such that:
a first potential difference applied in a first direction between the gate electrode layer and the conductive material layer modifies a proportionate amount of the at least one ionic species in a portion of the conductive material layer to generate a first memristive state comprising a first lateral resistive state between the first electrode and the second electrode;
a second potential difference applied in a second direction between the gate electrode layer and the conductive material layer modifies a proportionate amount of the at least one ionic species in a portion of the conductive material layer to generate a second memristive state comprising a second lateral resistive state between the first electrode and the second electrode that is different from the first lateral resistive state; and
the memristive element persists in the first memristive state or the second memristive state in response to discontinuance of the first potential difference or the second potential difference, respectively.

US Pat. No. 10,460,793

SEMICONDUCTOR MEMORY DEVICE HAVING CLOCK GENERATION SCHEME BASED ON COMMAND

Samsung Electronics Co., ...

1. A semiconductor memory device comprising:a command decoder configured to decode a command for writing data at a memory cell or reading data from a memory cell;
an internal data clock generating circuit configured to adjust phase of a data clock with a system clock in response to the command, wherein a frequency of the system clock is lower than a frequency of the data clock; and
a pattern generator configured to generate an error detect code (EDC) hold pattern, used for a clock data recovery operation, in response to the command and to output the EDC hold pattern to an external device through EDC hold pattern pins.

US Pat. No. 10,460,792

SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) AND MEMORY CONTROLLER DEVICE MOUNTED IN SINGLE SYSTEM IN PACKAGE (SIP)

Renesas Electronics Corpo...

1. An electronic device comprising:a first semiconductor memory device having a plurality of data terminals including a first data terminal and a second data terminal, and configured to store data input from the plurality of the data terminals;
a semiconductor device comprising a controller and configured to access the data stored in the first semiconductor memory device; and
a wiring substrate on which the semiconductor device and the first semiconductor memory device are mounted,
wherein the wiring substrate comprise:
a build-up layer comprising a first wiring layer, a second wiring layer and, simultaneously, a plurality of ground planes forming respective layers of the wiring substrate;
a first data wiring electrically connecting the semiconductor device with the first data terminal through the first wiring layer; and
a second data wiring electrically connecting the semiconductor device with the second data terminal through the second wiring layer,
wherein the first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer,
wherein the first data terminal is located farther from the semiconductor device than the second data terminal, and
wherein the semiconductor device and the first semiconductor memory device are mounted on the wiring substrate in a thickness direction of the wiring substrate; and
wherein the first wiring layer is arranged closer to the semiconductor device than the second wiring layer in the thickness direction of the wiring substrate.

US Pat. No. 10,460,786

SYSTEMS AND METHODS FOR REDUCING WRITE ERROR RATE IN MAGNETOELECTRIC RANDOM ACCESS MEMORY THROUGH PULSE SHARPENING AND REVERSE PULSE SCHEMES

Inston, Inc., Santa Moni...

1. A method for a writing mechanism for a magnetoelectric random access memory cell, the method comprising:applying a voltage of a given polarity for a period of time across a magnetoelectric junction bit of the magnetoelectric random access memory cell, wherein:
the magnetoelectric junction bit comprises:
a ferromagnetic free layer,
a ferromagnetic fixed layer, and
a dielectric layer interposed between the ferromagnetic free layer and the ferromagnetic fixed layer;
application of the voltage of the given polarity across the magnetoelectric junction bit reduces the perpendicular magnetic anisotropy and magnetic coercivity of the ferromagnetic free layer through a voltage controlled magnetic anisotropy effect;
the magnetization of the ferromagnetic free layer changes direction in response to the application of the voltage of the given polarity; and
applying a voltage of a polarity opposite the given polarity across the magnetoelectric junction bit at the end of the application of the voltage of the given polarity.

US Pat. No. 10,460,780

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) EMPLOYING AN INTEGRATED PHYSICALLY UNCLONABLE FUNCTION (PUF) MEMORY

QUALCOMM Incorporated, S...

1. A memory access circuit for controlling a physically unclonable function (PUF) operation accessing magneto-resistive magnetic random access memory (MRAM) bit cells in an MRAM array comprising an MRAM data array comprising at least one MRAM bit cell row circuit of data MRAM bit cells and an MRAM PUF array comprising at least one MRAM bit cell row circuit of PUF MRAM bit cells, the memory access circuit comprising:a write driver circuit configured to generate a reference write signal to program at least one PUF MRAM bit cell in at least one MRAM bit cell column circuit to a reference memory state, in response to a PUF write operation selecting an MRAM bit cell row circuit to be written in the MRAM PUF array;
a reference write driver circuit configured to generate a second reference write signal to program at least one reference MRAM bit cell in at least one reference MRAM bit cell column circuit to the reference memory state, in response to the PUF write operation selecting the MRAM bit cell row circuit to be written in the MRAM PUF array;
a data output circuit configured to, in response to a PUF read operation selecting an MRAM bit cell row circuit of PUF MRAM bit cells to be read:
receive a PUF data signal representing a resistance of the at least one PUF MRAM bit cell in the at least one MRAM bit cell column circuit for the selected MRAM bit cell row circuit for the PUF read operation;
receive a reference signal representing a resistance of the at least one reference MRAM bit cell in the at least one reference MRAM bit cell column circuit for the selected MRAM bit cell row circuit for the PUF read operation;
compare the PUF data signal to the reference signal; and
generate a PUF output based on a difference between the PUF data signal and the reference signal.

US Pat. No. 10,460,779

MRAM REFERENCE CELL WITH SHAPE ANISOTROPY TO ESTABLISH A WELL-DEFINED MAGNETIZATION ORIENTATION BETWEEN A REFERENCE LAYER AND A STORAGE LAYER

CROCUS TECHNOLOGY INC., ...

1. An apparatus, comprising:a reference magnetic tunnel junction to produce a reference signal, the reference magnetic tunnel junction with a high aspect ratio including a reference layer in an annealed state to establish permanent magnetization along a minor axis and a storage layer with magnetization along a major axis, wherein the storage layer magnetization is substantially perpendicular to the magnetization along the minor axis, the magnetization orientation between the minor axis and the major axis being maintained by shape anisotropy caused by the high aspect ratio.

US Pat. No. 10,460,772

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device comprising:a control circuit connected to a bus;
a first circuit operating under control of the control circuit;
a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus;
a switch element connected between the first circuit and a power supply; and
a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.

US Pat. No. 10,460,768

BASE UNIT AND DISK DRIVE APPARATUS

NIDEC CORPORATION, Kyoto...

1. A base unit for use in a disk drive apparatus in which a gas with a density lower than that of air is sealed in a housing space defined by a base member and a cover fixed to each other, the base unit comprising:the base member that supports a motor rotatable about a central axis extending in a vertical direction; and
a connector electrically connected to a wire in the housing space; wherein the base member includes:
a recessed portion extending in radial directions and recessed upward from a lower surface of the base member; and
a hole extending through the recessed portion in the vertical direction;
the recessed portion includes a recessed portion loop-shaped surface defining a loop-shaped surface in the radial direction;
the connector is located on a lower side of the recessed portion to cover the hole;
an adhesive is located between the connector and the recessed portion; and
a minimum value of a gap distance in the radial direction between an outer end of the connector and an inner end of the recessed portion in which the outer end of the connector and the inner end of the recessed portion are opposed to each other with the adhesive therebetween is greater than a minimum value of a gap in the vertical direction distance between an upper surface of the connector and the recessed portion loop-shaped surface, in which the upper surface of the connector and the recessed portion loop-shaped surface are opposed to each other with the adhesive therebetween; wherein
the adhesive includes a filler; and
the adhesive extends all the way around the hole.

US Pat. No. 10,460,763

GENERATING AUDIO LOOPS FROM AN AUDIO TRACK

Adobe Inc., San Jose, CA...

1. In a digital media environment comprising pre-recorded electronic audio tracks, a computer-implemented method of generating audio loops, comprising:identifying, by at least one processor of a client device, a plurality of portions of an audio track, wherein each portion of the plurality of portions is a possible audio loop comprising a common beginning beat, and each portion of the plurality of portions comprises a different number of beats;
determining, by the at least one processor, a score for each portion of the plurality of portions of the audio track by determining a similarity of an audio profile of the beginning beat and an audio profile of an ending beat of each portion;
selecting a portion of the audio track from the plurality of portions of the audio track based on the determined score for each portion; and
generating, by the at least one processor, an audio loop using the selected portion of the audio track.

US Pat. No. 10,460,757

MANAGEMENT OF HEAD AND MEDIA DIMENSIONAL STABILITY

International Business Ma...

1. A method for characterizing a magnetic recording tape of a tape cartridge, the method comprising:measuring, using a magnetic head having servo readers of known pitch, a servo band difference at various locations along a length of a magnetic recording tape of a tape cartridge; and
storing the servo band difference measurements and/or derivatives thereof in association with the tape cartridge.

US Pat. No. 10,460,750

PLATING BASED PRE-DEFINED SIDE SHIELD AND APPLICATION IN MAGNETIC HEAD

SanDisk Technologies LLC,...

1. A magnetic recording head having an air bearing surface (ABS), comprising:a main pole;
a side shield laterally spaced from the main pole by a first side gap and a second side gap;
an electrically conductive non-magnetic gap material layer disposed between the main pole and the side shield in the first side gap; and
a dielectric non-magnetic gap material matrix and a conformal dielectric spacer layer disposed between the main pole and the side shield in the second side gap.

US Pat. No. 10,460,748

CONVERSATIONAL INTERFACE DETERMINING LEXICAL PERSONALITY SCORE FOR RESPONSE GENERATION WITH SYNONYM REPLACEMENT

The Toronto-Dominion Bank...

16. A computerized method performed by one or more processors, the method comprising:receiving, via a communications module, a first signal including a conversational input received via interactions with a conversational interface;
analyzing the received conversational input via a natural language processing engine to determine an intent of the received conversational input and a lexical personality score of the received conversational input, the determined intent and the determined lexical personality score based on characteristics included within the received conversational input, wherein the determined lexical personality score includes at least a first score representing a formality score and a second score representing a politeness score of the received conversational input, wherein the formality score and the politeness score represent respective measures determined based on the characteristics included within the received conversational input;
determining a set of response content responsive to the determined intent of the received conversational input, the determined set of response content including a set of initial tokens representing an initial response to the received conversational input, wherein the initial response to the received conversational input corresponds to a default lexical personality score;
identifying a set of synonym tokens associated with at least some of the set of initial tokens, wherein each of the set of synonym tokens are associated with at least a corresponding formality score and a politeness score;
determining, from the identified set of synonym tokens, at least one synonym token associated with a lexical personality score similar to the determined formality score and politeness score of the received conversational input;
replacing at least one token from the set of initial tokens included in the determined set of response content with the at least one determined synonym token corresponding to the determined formality score and politeness score of the received conversational input to generate a modified version of the set of response content; and
transmitting, in response to the received first signal and via the communications module, a second signal including the modified version of the set of response content to a device associated with the received conversational input.

US Pat. No. 10,460,747

FREQUENCY BASED AUDIO ANALYSIS USING NEURAL NETWORKS

Google LLC, Mountain Vie...

1. A method for training a neural network that includes a plurality of neural network layers on training data,wherein the neural network is configured to receive linear scale frequency domain features of an audio sample and to process the frequency domain features to generate a neural network output for the audio sample,
wherein the neural network comprises (i) an input convolutional layer that is configured to map linear scale frequency domain features to logarithmic scaled frequency domain features, wherein the mapping from linear scale frequency domain features to logarithmic scaled frequency domain features is defined by one or more convolutional layer filters of the input convolutional layer, and (ii) one or more other neural network layers having respective layer parameters that are configured to process the logarithmic scaled frequency domain features to generate the neural network output, and
wherein the method comprises:
obtaining training data comprising, for each of a plurality of training audio samples, linear scale frequency domain features of the training audio sample and a known output for the training audio sample; and
training the neural network on the training data to adjust the values of the parameters of the other neural network layers and to adjust the one or more convolutional layer filters that define the mapping from linear scale frequency domain features to logarithmic scaled frequency domain features to determine an optimal logarithmic convolutional mapping of linear scale frequency domain features to logarithmic-scaled frequency domain features.

US Pat. No. 10,460,746

SYSTEM, METHOD, AND DEVICE FOR REAL-TIME LANGUAGE DETECTION AND REAL-TIME LANGUAGE HEAT-MAP DATA STRUCTURE CREATION AND/OR MODIFICATION

MOTOROLA SOLUTIONS, INC.,...

1. A method of real-time language detection and language heat map data structure modification, the method comprising:receiving, at an electronic computing device from a first electronic audio source, first audio content;
identifying, by the electronic computing device, a first geographic location of the first audio content as one of a location of the first electronic audio source and a sound localization process calculated as a function of the location of the first electronic audio source;
determining, by the electronic computing device, that the first audio content includes first speech audio;
identifying, by the electronic computing device from the first audio content, a first language in which the first speech audio is spoken and creating a first association between the first geographic location and the first language;
accessing, by the electronic computing device, a real-time language heat-map data structure including at least a second association between the first geographical location and a second language different from the first language;
modifying, by the electronic computing device based on the first audio content, the real-time language heat-map data structure to include the created first association;
taking a further action, by the electronic computing device, as a function of the modified real-time language heat-map data structure comprising at least one of: (i) electronically displaying at least a modified portion of the modified real-time language heat-map data structure at an electronic display coupled to the electronic computing device, (ii) transmitting at least the modified portion of the modified real-time language heat-map data structure to another electronic computing device for further processing, (iii) electronically transmitting a dispatch instruction to a user having a skill or a need in the first language to the first geographic location, and (iv) electronically transmitting a notification to a user having a skill or a need in the first language including identifying the first geographic location and the first language;
identifying a time and/or date associated with receipt of the first audio content; and
modifying a historical language heat-map data structure associated with the time and/or date to include the first association, wherein the historical language heat-map data structure includes a plurality of associations across sequential times and/or dates that track a particular language cluster as it moves across a geographic region.

US Pat. No. 10,460,737

METHODS, APPARATUS AND SYSTEMS FOR ENCODING AND DECODING OF MULTI-CHANNEL AUDIO DATA

Dolby Laboratories Licens...

1. A method for decoding an encoded bitstream of multi-channel audio data and associated metadata, the method comprising:decoding the encoded bitstream of multi-channel audio data into multi-channel audio data;
detecting that the multi-channel audio data includes a first Ambisonics format;
transforming the first Ambisonics format of the multi-channel audio data to a second Ambisonics format representation of the multi-channel audio data, wherein the transforming maps the first Ambisonics format of the multi-channel audio data into the second Ambisonics format representation of the multi-channel audio data; and
wherein the detecting is based on at least part of the associated metadata that indicates existence of the first Ambisonics format of the multi-channel audio data.

US Pat. No. 10,460,732

SYSTEM AND METHOD TO INSERT VISUAL SUBTITLES IN VIDEOS

Tata Consultancy Services...

1. A computer implemented system for creation of visually subtitled videos, wherein said system comprises:a memory storing instructions and coupled to the processor, wherein the processor is configured to execute the instructions to perform operations to:
segment an audio signal with at least one speaker in a video frame from an input video signal and a music segment from the input video signal;
map a plurality of recognized phones from the segmented audio signal to at least one viseme using a language model;
determine a likelihood score of the recognized phones;
determine a viseme based language model score (VLM) for the at least one mapped viseme;
compute a total viseme score for the at least one mapped viseme by determining a sum of the likelihood score and the VLM score when more than one phone maps to the same viseme or determining a product of the likelihood score and VLM score when one phone maps to a single viseme;
determine a most relevant viseme from the segmented audio signal by comparing the total viseme score and selecting a viseme with the highest total score;
generate a speaker representation sequence of the segmented audio signal; and
integrate the segmented audio signal and viseme sequence to generate visual subtitles.

US Pat. No. 10,460,724

DISCOVERING WINDOWS IN TEMPORAL PREDICATES

INTERNATIONAL BUSINESS MA...

1. A method for event processing by discovering windows in temporal predicates, comprising:separating a predicate that specifies a set of events into a temporal part and a non-temporal part, the set of events being used to reduce required computational resources for the discovering windows in temporal predicates by forming an aggregation that is incrementally maintained as events are added to and removed from the set of events;
comparing the temporal part of the predicate against a predicate of a known window type;
determining whether the temporal part of the predicate matches the predicate of the known window type; and
replacing (i) the non-temporal part of the predicate by a filter, and (ii) the temporal part of the predicate by an instance of the known window type, responsive to the temporal part of the temporal predicate matching the predicate of the known window type,
wherein the set of events is specified by first filtering the set of events by the filter replacing the non-temporal part of the predicate, with any remaining events being tracked in the instance of the known window type that replaced the temporal part of the predicate,
wherein the instance is parameterized with substitutions used to match the temporal part of the predicate to the predicate of the known window type, and
wherein a window of the known window type is associated with one or more buckets that are pre-aggregated at a bucket-level upon event arrival.

US Pat. No. 10,460,721

DIALOGUE ACT ESTIMATION METHOD, DIALOGUE ACT ESTIMATION APPARATUS, AND STORAGE MEDIUM

PANASONIC INTELLECTUAL PR...

1. A dialogue act estimation method, in a dialogue act estimation system, comprising:acquiring sounds by a microphone in a terminal;
determining, by a processor in the terminal, whether the acquired sounds are uttered sentences of one or more speakers or noise;
outputting the uttered sentences to communication transmitter only when the processor determines that the acquired sounds are uttered sentences of the one or more speakers and are not noise;
converting the uttered sentences of the one or more speakers to one or more formatted communication signals when the processor determines that the acquired sounds are uttered sentences of the one or more speakers;
transmitting the one or more formatted communication signals from the terminal over a communication network to a server;
receiving the one or more formatted communication signals by the server;
converting the received one or more formatted communication signals by a processor in the server to the uttered sentences of the one or more speakers;
acquiring first training data by the server from the converted uttered sentences of the one or more speakers indicating, in a mutually associated manner, text data of a first sentence that can be a current uttered sentence, text data of a second sentence that can be an uttered sentence immediately previous to the first sentence, first speaker change information indicating whether a speaker of the first sentence is the same as a speaker of the second sentence, and dialogue act information indicating a class of the first sentence;
learning an association between the current uttered sentence and the dialogue act information by applying the first training data to a model;
storing a result of the learning as learning result information in a memory in the server;
acquiring dialogue data including text data of a third sentence of a current uttered sentence uttered by a user, text data of a fourth sentence of an uttered sentence immediately previous to the third sentence, and second speaker change information indicating whether the speaker of the third sentence is the same as a speaker of the fourth sentence;
estimating a dialogue act to which the third sentence is classified by applying the dialogue data to the model based on the learning result information; and
generating a correct response to the uttered sentences of the one or more speakers,
wherein the model includes
a first model that outputs a first feature vector based on the text data of the first sentence, the text data of the second sentence, the first speaker identification information, the second speaker identification information, and a first weight parameter, and
a second model that outputs a second feature vector based on the text data of the first sentence, the text data of the second sentence, the first speaker change information, and a second weight parameter,
wherein the first model determines the first feature vector from the first sentence and the second sentence according to a first RNN-LSTM (Recurrent Neural Network-Long Short Term Memory) having the first weight parameter dependent on the first speaker identification information and the second speaker identification information, and
wherein the second model determines the second feature vector from the first sentence and the second sentence according to a second RNN-LSTM having the second weight parameter dependent on first speaker change information.

US Pat. No. 10,460,715

ACOUSTIC FLOOR UNDERLAY SYSTEM

Zephyros, Inc., Romeo, M...

1. A flooring assembly comprising:a) at least one first lofted, lapped, or airlaid bulk absorber layer for acoustic absorption and compression resistance;
b) at least one impedance layer for one or more of acoustic impedance, compression resistance, and stiffness;
c) at least one second lofted, lapped, or airlaid bulk absorber layer for acoustic absorption and compression resistance; and
d) one or more fibrous air-flow resistive layers.

US Pat. No. 10,460,714

BROADBAND ACOUSTIC ABSORBERS

United States of America ...

1. An apparatus, comprising:acoustic absorber panels located on a plurality of sides of a body to be acoustically dampened, wherein each acoustic absorber panel comprises:
at least one cubic retainer, wherein the cubic retainer is open to a surrounding gaseous environment and capable of receiving sound waves to be acoustically dampened, the cubic retainer comprising:
at least one solid side; and
at least one perforated side permitting sound waves in the surrounding gaseous environment to enter the cubic retainer; and
an acoustic absorber layer disposed within the cubic retainer and comprised of a plurality of reeds, wherein:
the plurality of reeds each comprise a first end, a second end, and a length disposed between the first end and the second end;
the plurality of reeds are natural reeds, synthetic reeds, or a combination of natural and synthetic reeds;
the plurality of reeds are fixed at one end, wherein the length of each of the reeds is substantially perpendicular to the sound waves entering the cubic retainer; and
the plurality of reeds are each open on at least one end to the surrounding gaseous environment;
wherein sound waves entering the cubic retainer are acoustically dampened by the acoustic absorber layer.

US Pat. No. 10,460,710

MUSICAL INSTRUMENTS INCLUDING KEYBOARD GUITARS

1. A musical instrument, comprising:a body;
an elongated neck coupled to the body, wherein the body and the elongated neck define an electric guitar shape, wherein the elongated neck has a length that is greater than or equal to a length of the body, and wherein the body includes a middle portion that is narrower than opposite end portions of the body;
a plurality of neck keys disposed on the elongated neck;
a plurality of body keys disposed on the body; and
an output for transmitting an electrical signal generated by the musical instrument;
wherein activation of each neck key generates an electrical signal at the output representing a pitch associated with a musical note corresponding to the activated neck key, wherein activation of each body key generates an electrical signal at the output representing a pitch associated with a musical note corresponding to the activated body key, and wherein the plurality of body keys and the plurality of neck keys are tuned in a continuous chromatic scale that spans the plurality of body keys and the plurality of neck keys.

US Pat. No. 10,460,699

TRANSITIONING BETWEEN VIDEO PRIORITY AND GRAPHICS PRIORITY

Dolby Laboratories Licens...

1. In a video receiver, a method for blending graphics data with a processor, the method comprising:receiving input video data and input dynamic metadata for the input video data, wherein the input video data is at a video dynamic range;
receiving input graphics data and input static metadata, wherein the input graphics data is at a graphics dynamic range;
receiving display identification data from a target display to which the video receiver is linked over a video interface;
receiving a blending priority map characterizing a per-pixel priority of output pixels in an image generated based on blending the input video data and the input graphics data;
blending the input video data and the input graphics data to generate blended video data; and
sending the blended video data to the target display for rendering the blended video data at a target dynamic range;
wherein blending the input video data and the input graphics data to generate blended video data comprises computing:
output(i)=a(i)*Rgraphics(i)+(1?a(i))*Rvideo(i),
wherein output(i) denotes an output pixel; Rvideo(i) denotes an input video pixel mapped to the target dynamic range based on a video tone-mapping function; Rgraphics(i) denotes an input graphics pixel mapped to the target dynamic range based on a graphics tone-mapping function, and a(i) denotes a blending value based on the blending priority map; i denotes a pixel index.

US Pat. No. 10,460,695

ELECTROCHROMIC DISPLAY DEVICE HAVING A PLURALITY OF SUB-FRAMES

ELECTRONICS AND TELECOMMU...

1. An electrochromic display device comprising:a display panel comprising a plurality of pixels configured to display an image on a basis of a unit frame defined as first to third sub-frames;
a timing controller configured to output a data signal and an off signal; and
a data driving circuit configured to provide, to the pixels, a data voltage generated based on the data signal during the second sub-frame and provide, to the pixels, an off voltage generated based on the off signal during the third sub-frame,
wherein each of the pixels comprises an electrochromic element, and
a power supply voltage is delivered to the electrochromic element in response to the data voltage during the second sub-frame, and the power supply voltage provided to the electrochromic element is blocked in response to the off voltage during the third sub-frame.

US Pat. No. 10,460,691

DISPLAY DEVICE WITH STABILIZATION

Samsung Display Co., Ltd....

1. A display device configured to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, the display device comprising:a gate driving circuit comprising a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages comprising a clock terminal configured to receive a clock signal,
wherein a clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, the clock signal being greater than a stabilization voltage lower than the second clock voltage during the frame intervals, and the clock signal is changed to the stabilization voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval,
wherein the ith stage comprises:
a first output unit configured to be turned on/off according to a voltage of a Q-node and output a gate signal including a gate-on signal and a gate-off signal from the clock signal to a gate output terminal of the ith stage;
a control unit configured to control the voltage of the Q-node; and
a first pull-down unit configured to provide a first low signal to the gate output terminal after the gate-on signal is outputted from the first output unit, and
wherein the ith stage further comprises a second output unit configured to be turned on/off according to a potential of the Q-node and output a carry signal including a carry-on signal and a carry-off signal from the clock signal to a carry output terminal of the ith stage.

US Pat. No. 10,460,688

LIQUID CRYSTAL DISPLAY PANEL AND DISPLAY DEVICE HAVING LIQUID CRYSTAL DISPLAY PANEL

Wuhan China Star Optoelec...

1. A liquid crystal display panel, wherein the liquid crystal display panel comprises:a plurality of data line pairs, each set of data line pair comprising a first data line and a second data line which are located side by side;
a plurality of scan lines, comprising a first scan line and a second scan line which are perpendicular with the plurality of data line pairs and alternatively arranged;
a pixel unit array, comprising a plurality of pixel units, which are respectively located in regions formed by arrangement of the plurality of data line pairs and the plurality of scan lines, and each row of pixel units being coupled to a first scan line and a second scan line;
wherein a scan drive signal received by the first scan line and the second scan line scan the two rows of pixel units coupled to each other at the same time, and the first scan line and the second scan line are respectively coupled to at least two pixel units in a single row of the pixel unit, and drives the pixel units coupled to each data line in time division to charge the pixel units coupled to the same data line in time division;
wherein the first data line and the second data line transmit data signals with positive polarity or negative polarity to the coupled pixel units, and the polarities of the entire column of the pixel unit array are inverted, and the pixel units are coupled to the first data line or the second data line which can provide corresponding polarity signals according to self polarities to make the first data line or the second data line be coupled to a plurality of pixel units of the same row at the same time
wherein in the pixel unit, the polarities of the pixels of the entire column are reversed in order of positive, negative, negative, positive, negative, positive, positive, negative.

US Pat. No. 10,460,678

DISPLAY DEVICE AND METHOD OF DRIVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a display portion including a plurality of pixels;
a light emitting diode array including a plurality of light emitting diodes and configured to emit light toward the display portion;
a monitoring circuit configured to generate a monitoring signal corresponding to a forward voltage of a first light emitting diode of the plurality of light emitting diodes;
a backlight controller configured to control the amount of current flowing to the light emitting diode array; and
a first luminance compensation circuit configured to increase the amount of current flowing to the light emitting diode array in response to the monitoring signal,
wherein the backlight controller comprises:
a first transistor connected between the light emitting diode array and a ground;
a first amplifier including an output terminal connected to a gate electrode of the first transistor;
a second transistor including a gate electrode connected to a first node, and connected between a power voltage and the first amplifier;
a second amplifier including a first input terminal to which a backlight control signal is input; and
a third transistor including a gate electrode connected to an output terminal of the second amplifier, and connected between the first node and the ground.

US Pat. No. 10,460,671

SCANNING DRIVING CIRCUIT AND DISPLAY APPARATUS

Shenzhen China Star Optoe...

1. A scanning driving circuit, comprising: a first voltage terminal; a second voltage terminal; a scanning signal output terminal for outputting a high level scanning signal or a low level scanning signal;a pull-up circuit for receiving a clock signal of a current stage and controlling the scanning signal output terminal to output of a high level scanning signal according to the clock signal of the current stage;
a transmission circuit, connected to the pull-up circuit for outputting a high level stage transmission signal of a current stage; a pull-up control circuit, connected to the transmission circuit and receiving a stage transmission signal of a previous stage for charging the pull-up control signal point to pull up the potential of the pull-up control signal point to a high level;
a pull-down maintenance circuit connected to the pull-up control circuit, the first voltage terminal and the second voltage terminal and receiving a high voltage direct current voltage, for maintaining the low level of the pull-up control signal point, and the low level of the scanning signal outputted from the scanning signal output terminal;
a bootstrap circuit for raising the potential of the pull-up control signal point;
a pull-down circuit connected to the transmission circuit, the pull-down maintenance circuit, and the first voltage terminal, for receiving a stage transmission signal of a next stage and controlling the scanning signal output terminal to output the low level scanning signal in accordance with the stage transmission signal of the next stage;
wherein the pull-up circuit comprises a first controllable switch, a first terminal of the first controllable switch receiving the clock signal of the current stage, a control terminal of the first controllable switch is connected to the transmission circuit and the pull-down circuit, a second terminal of the first controllable switch is connected to the transmission circuit and the scanning signal output terminal; and
wherein when the scanning driving circuit is not operated, the second voltage terminal is controlled to be at high potential, and when the scanning driving circuit is operated, the second voltage terminal becomes a low potential, and the low potential is the same with the first voltage terminal; and
wherein the pull-down maintenance circuit comprises fourth to ninth controllable switches, a control terminal of the fourth controllable switch is connected to a control terminal of the fifth controllable switch, a first terminal of the fourth controllable switch is connected to the pull-up control circuit, a second terminal of the fourth controllable switch is connected to the first voltage terminal, a first terminal of the fifth controllable switch is connected to the scanning signal output terminal, a second terminal of the fifth controllable switch is connected to the first voltage terminal, a second terminal of the sixth controllable switch is connected to a first terminal of the seventh controllable switch and the control terminal of the fifth controllable switch, a first terminal of the sixth controllable switch is connected to a first terminal of the eighth controllable switch and a control terminal of the eighth controllable switch and to receive the high voltage direct current voltage, a control terminal of the sixth controllable switch is connected to the second terminal of the eighth controllable switch and a first terminal of the ninth controllable switch, a control terminal of the seventh controllable switch is connected to a control terminal of the ninth controllable switch and the pull-up control circuit, a second terminal of the seventh controllable switch and a second terminal of the ninth controllable switch are both connected to the second voltage terminal.

US Pat. No. 10,460,662

ELECTROLUMINESCENT DISPLAY AND METHOD OF SENSING ELECTRICAL CHARACTERISTICS OF ELECTROLUMINESCENT DISPLAY

LG Display Co., Ltd., Se...

1. An electroluminescent display comprising:a display panel including a plurality of pixels, a plurality of gate lines, and a plurality of data lines; and
a driver integrated circuit connected to the data line through a channel terminal,
wherein the driver integrated circuit includes:
a data voltage generator configured to generate a data voltage to be supplied to the pixel;
a first switch connected between the channel terminal and the data voltage generator;
a sensor configured to sense electrical characteristics of the pixel; and
a second switch connected between the channel terminal and the sensor,
wherein each pixel includes:
a driving thin film transistor (TFT) including a control electrode connected to a first node, a first electrode connected to a high potential driving power, and a second electrode connected to a second node;
an organic light emitting diode (OLED) connected between the second node and a low potential driving power;
a first switching TFT including a control electrode connected to a first gate line supplied with a first gate signal, a first electrode connected to the data line, and a second electrode connected to the first node;
a second switching TFT including a control electrode connected to a second gate line supplied with a second gate signal, a first electrode connected to the data line, and a second electrode connected to the second node; and
a storage capacitor connected between the high potential driving power and the first node,
wherein during a degradation tracking period following a first programming period, the first and second switches are turned off, and the first and second switching TFTs are turned on.

US Pat. No. 10,460,660

AMOLED DISPLAYS WITH MULTIPLE READOUT CIRCUITS

Ingis Innovation Inc., W...

1. A system for determining the operational voltage VOLED of a light-emitting device in a pixel in an array of pixels in a display, the pixel including a storage capacitor coupled to a drive transistor for supplying current to said light-emitting device as a function of a programming of the storage capacitor, the system comprising:a controller adapted to:
vary a first programming of the storage capacitor and measure a first current supplied to said light-emitting device via said drive transistor, until reaching a final first programming of the storage capacitor when the first current equals a predetermined current, wherein one of the first current and the predetermined current is a function of the operational voltage VOLED of said light-emitting device; and
extract the value of the operational voltage VOLED of said light-emitting device with use of the final first programming of the storage capacitor.

US Pat. No. 10,460,652

SCAN DRIVER CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE CIRCUIT

Wuhan China Star Optoelec...

1. A scanning driving circuit, the scanning driving circuit comprising a plurality of cascaded scanning driving unit, each scanning driving unit comprising:a forward and reverse scanning circuit for receiving a previous level scanning signal and a first clock signal and outputting a first control signal to control the scanning driving circuit performing forward scanning, or for receiving a next level scanning signal and a second clock signal and outputting a second control signal to control the scanning driving circuit performing reverse scanning;
an input circuit connected to the forward and reverse scanning circuit, for receiving a third clock signal and receiving the first and the second control signal from the forward and reverse scanning circuit, and according to the third clock signal, the first and the second control signal to perform charging to the pull-up control signal point and the pull-down control signal point; and
an output circuit connected to the input circuit for performing a process to a received third or the fourth control signal and a data received from the input circuit, generating a scanning driving signal with two-valued high electrical level and outputting to the current level scanning line to drive a pixel unit;
wherein the third control signal comprises a fourth clock signal, the fourth control signal comprises the fourth clock signal;
the forward and reverse scanning circuit comprises a first controllable switch and a second controllable switch, the control terminal of the first controllable switch receives the first clock signal, a first terminal of the controllable switch receives the previous level scanning signal, a second terminal of the first controllable switch is connected to the first terminal of the second controllable switch and the input circuit, a control terminal of the second controllable switch receives the second clock signal, a second terminal of the second controllable switch receives the next level scanning signal;
the input circuit comprises a third to seventh controllable switches, a first capacitor and a second capacitor, a control terminal of the third controllable switch is connected to turn-on voltage terminal signal, a first terminal of the third controllable switch is connected to a control terminal of the fourth controllable switch, the second terminal of the first controllable switch and the first terminal of the second controllable switch, a second terminal of the third controllable switch is connected to a first terminal of the fifth controllable switch and the output circuit, a second terminal of the fifth controllable switch is connected to a second terminal of the fourth controllable switch, a second terminal of the sixth controllable switch and a second terminal of the seventh controllable switch receive the turn-off voltage terminal signal, a control terminal of the fifth controllable switch is connected to a first terminal of the fourth controllable switch and a control terminal of the sixth controllable switch, a first terminal of the sixth controllable switch is connected to a first terminal of the seventh controllable switch and the output circuit, a control terminal of the seventh controllable switch receives the third clock signal, a first terminal of the first capacitor is connected to the control terminal of the fifth controllable switch, a second terminal of the first capacitor is connected to the output circuit, the second capacitor is connected between the control terminal and the second terminal of the sixth controllable switch;
the output circuit comprises eighth-twelfth controllable switches and a third capacitor, a control terminal of the eighth controllable switch is connected to the second terminal of the third controllable switch, the first terminal of the fifth controllable switch and a control terminal of the twelfth controllable switch, a first terminal of the eighth controllable switch is connected to a second terminal of the ninth controllable switch, a second terminal of the eighth controllable switch is connected to the first terminal of the sixth and seventh controllable switches, a second terminal of the twelfth controllable switch and the current level scanning line, a control terminal of the ninth controllable switch receives the reset signal, a first terminal of the ninth controllable switch is connected to a control and a first terminals of the tenth controllable switch, a first terminal of the eleventh controllable switch and a second terminal of the first capacitor receive the fourth clock signal, a second terminal of the tenth controllable switch is connected to the control terminal of the eleventh controllable switch, a second terminal of the eleventh controllable switch is connected to a first terminal of the twelfth controllable switch, the third capacitor is connected between the control and the second terminals of the eighth controllable switch.

US Pat. No. 10,460,649

AUTOMATICALLY SELECTING A SET OF PARAMETER VALUES THAT PROVIDE A HIGHER LINK SCORE

Dell Products L.P., Roun...

1. A method comprising:selecting, by a display controller of a display device, a first set of parameter values from multiple sets of parameter values;
configuring, by the display controller, a video input of the display device based at least in part on the first set of parameter values;
receiving, by the display controller, a request to initiate link training from a video source that is connected to the video input;
initiating, by the display controller, the link training;
generating, by the display controller, a current link score after the link training is successfully completed, wherein the link score comprises a sixteen-bit value that includes one or more error flags and one or more quality measurements ordered from a most significant bit (MSB) to a least significant bit (LSB) in order of significance;
determining, by the display controller, that the current link score is greater than a stored link score;
setting a value of the stored link score to be the current link score;
storing the first set of parameter values to create a stored set of parameter values;
determining, by the display controller, that each set of parameter values from the multiple sets of parameter values has been selected; and
configuring, by the display controller, the video input of the display device based at least in part on the stored set of parameter values.

US Pat. No. 10,460,646

DISPLAY SYSTEM, DISPLAY DEVICE, ELECTRONIC APPARATUS, AND IMAGE SIGNAL TRANSMISSION METHOD FOR DISPLAYING AN ORIGINAL IMAGE BASED ON COMBINING DIVIDED IMAGE SIGNALS

NEC DISPLAY SOLUTIONS, LT...

16. An image signal transmission method that is carried out in a display system that includes a display device and an electronic apparatus that is electrically connected by a connector to said display device, said method comprising:said electronic apparatus receiving or generating an original image signal that indicates an original image that is to be displayed and supplying a plurality of divided image signals that each indicate a respective image of a plurality of partial images obtained by dividing said original image; and
said display device displaying said original image on a basis of a combined image signal realized by combining said plurality of divided image signals that are supplied from said electronic apparatus,
wherein said electronic apparatus supplies a first divided image signal that indicates a first partial image of two partial images obtained by dividing said original image either vertically or horizontally, and a second divided image signal that indicates a second partial image of the two partial images,
wherein said display device combines said first and second divided image signals to supply a combined image signal that indicates said original image,
wherein said display device comprises:
a first memory into which is written first data that indicates said first partial image that is indicated by said first divided image signal;
a second memory into which is written second data that indicates said second partial image that is indicated by said second divided image signal;
a first memory input circuit that reads said first data from said first memory;
a second memory input circuit that reads said second data from said second memory, wherein said first and second memory input circuits use a same clock signal to perform reading of said first and second data from said first and second memories;
a first signal receiver circuit that receives said first divided image signal from said electronic apparatus and supplies as output each of said first data, a first clock signal, and a first Data Enable signal;
a second signal receiver circuit that receives said second divided image signal from said electronic apparatus and supplies as output each of said second data, a second clock signal of a same frequency as said first clock signal, and a second Data Enable signal;
a first memory input circuit that, at a write timing indicated by said first Data Enable signal, writes said first data to said first memory in synchronization with said first clock signal;
a second memory input circuit that, at a write timing indicated by said second Data Enable signal, writes said second data to said second memory in synchronization with said second clock signal; and
a clock generation circuit that supplies a third clock signal of a same frequency as said first or second clock signal, and
wherein each of said first and second memory input circuits uses, of said first and said second Data Enable signals, the Data Enable signal having the later timing or a Data Enable signal having a later timing than both said first and second Data Enable signal to read data on the basis of said third clock signal from, of said first and second memories, a corresponding memory at a read timing that is indicated by the Data Enable signal.

US Pat. No. 10,460,638

INTERMITTENT DISPLAY ISSUE MONITORING SYSTEM

HONEYWELL INTERNATIONAL I...

1. A system to detect intermittent failures of a display system comprising a display and a display processing system, comprising:a sensor system configured to capture a light level of the display, the sensor system comprising:
a light sensor configured to output a voltage representative of the light level received by the light sensor;
a filter coupled to an output of the light sensor, the filter configured to filter the output voltage at a frequency corresponding to a flicker of a light bulb;
a programmable gain amplifier coupled to an output of the filter, the programmable gain amplifier configured to amplify the filtered output voltage and transmit the filtered output voltage to the processor; and
an offset adjustment circuit coupled between the programmable gain amplifier and the processor, the offset adjustment circuit configured adjust a gain of the programmable gain amplifier to center the amplified filtered output voltage around an input voltage range of the processor; and
a processor communicatively coupled to the sensor system and the display processing system, the processor configured to:
transmit instructions to generate a static image for a predetermined amount of time to the display processing system, the instructions causing the display processing system to generate the static image on the display for the predetermined amount of time;
determine, when the display is displaying the static image, a baseline light level of the display based upon data received from the sensor system;
validate an existence of an intermittent display error when the light level of the display is greater than the baseline light level by a first predetermined amount or when the light level of the display is less than the baseline light level by a second predetermined amount at least once over the predetermined amount of time;
determine, when the existence of the intermittent display error is validated, a recurrence rate based upon instances when the light level of the display is greater than the baseline light level by the first predetermined amount or when the light level of the display is less than the baseline light level by the second predetermined amount and the predetermined amount of time; and
associate, when the existence of the intermittent display error is validated, an error type with each instance that the light level of the display is greater than the baseline light level by the first predetermined amount or when the light level of the display is less than the baseline light level by the second predetermined amount.

US Pat. No. 10,460,636

CONTROL OF SELECTIVE ACTUATION OF A LIGHT FILTER ARRAY

Nokia Technologies Oy, E...

1. A method comprising:in a standard display mode, causing display of a graphical element at a position on a see through display that comprises a light projection display that overlays a light filtration array such that the light projection display projects the graphical element at the position on the see through display and the light filtration array filters at least a portion of ambient light at the position on the see through display;
transitioning from the standard display mode to a low power display mode that configures the see through display to consume less power than the see through display consumes in the standard display mode;
causing termination of display of the graphical element on the see through display based, at least in part, on the low power display mode;
determining that an event has occurred, wherein the event is unrelated to a view of a viewer of the see through display;
generating a notification that signifies the event;
causing actuation of the light filtration array such that a plurality of light filtration cells of the light filtration array are selectively actuated in a pattern that depicts the notification based, at least in part, on the low power display mode.

US Pat. No. 10,460,635

DEPLOYABLE TAPE ESTABLISHING VISIBILITY IN FIELD ENVIRONMENTS

1. A portable signaling assembly comprising:a composite strip with a broad and flat profile, said composite strip comprising:
an elongate reflective strip formed of a metalized film having a first planar surface and a second planar surface opposed the first planar surface, said elongate strip having a first end configured with a first attachment mechanism and a second end opposite the first end configured with a second attachment mechanism;
a first attachment point configured in the first end;
a second attachment point configured in the second end; and
an elongate reinforcing strip longitudinally affixed to the elongate reflective strip configured so as to reinforce the elongate reflective strip against longitudinal loads;
a first swivel member attached to the first attachment point;
a second swivel member attached to the second attachment point;
a first stretchable member attached to the first swivel member; and
a second stretchable member attached to the second swivel member;
wherein the portable signaling assembly is configured so that when the composite strip is held taut in air by the first and second stretchable members the composite strip freely twists and rotates along a line formed between the first and second attachment points when a breeze contacts the broad and flat profile to create a visual signaling display as a result of twisting and rotation of the elongated reflective strip in which the elongated reflected strip is twisted at least once through one hundred and eighty degrees so that the first planar surface and the second planar surface are visible from a single vantage point.

US Pat. No. 10,460,631

PRIVACY LABEL

1. A privacy label comprising:a liner sheet, said liner sheet comprising a first surface and a second surface opposite said first surface;
a label sheet, said label sheet comprising a top surface, an underside surface opposite said top surface, and one or more edges defining a boundary of said label sheet, said top surface adapted for printing indicia thereon, said label sheet comprising a line of weakness defining a first segment and a second segment in said label sheet, said first segment and said second segment together defining an area for printing said indicia thereon, said first segment being, separable from said second segment along said line of weakness, said underside surface of said, label sheet comprising a first adhesive, wherein a portion of said underside surface of said label sheet is releasably bonded to said first surface of said liner sheet;
an intermediate sheet between said liner sheet and said label sheet, said intermediate sheet being smaller in size than both said liner sheet and said label sheet, said intermediate sheet comprising an upper surface and a lower surface opposite said upper surface, said lower surface of said intermediate sheet comprising a second adhesive, wherein said upper surface of said intermediate sheet is releasably bonded to said underside surface of said label sheet in a position underlying at least all of said second segment of said label sheet, and wherein said lower surface of said intermediate sheet is releasably bonded to said first surface of said liner sheet, wherein said label sheet and said intermediate sheet may be simultaneously separated from said liner sheet, with said intermediate sheet remaining adhered to said underside surface of said second segment of said label sheet and said first adhesive and said second adhesive being exposed;
wherein when said label sheet and said intermediate sheet together are separated from said liner sheet and adhered to a surface of an object, said lower surface of said intermediate sheet and said underside surface of said first segment of said label sheet are permanently adhered to said surface of said object, and said underside surface of said second segment of said label sheet is removable from said intermediate sheet.

US Pat. No. 10,460,630

BABY BOTTLE-ADAPTABLE REUSABLE LABEL

1. A baby bottle-adaptable reusable label, the label comprising:a resilient sleeve comprising a resilient material,
the sleeve being defined by an inner wall and an outer wall, the outer wall being oppositely disposed to the inner wall,
the outer wall operable to enable marking and erasing of a removable identifying indicia, the outer wall comprising a pre-printed permanent identifying indicia,
the sleeve further being defined by a pair of peripheral edges running around the walls, the peripheral edges forming four notches, wherein each of the peripheral edges has a thickness;
wherein each of the at least one notch has an inwardly-extended gripping surface for allowing the thumbs to rest thereon; and
wherein each of the notches has a square shape, and each of the notches is arranged on an opposite side of the sleeve.

US Pat. No. 10,460,623

TOOL SIMULATION SYSTEM, SIMULATION WORKPIECE, AND METHOD OF OPERATION

1. A simulator system for use in simulating fabrication or construction, comprising:a simulation tool comprising a magnet mounted in fixed relation to a working end of the simulation tool;
a simulation workpiece comprising a substrate having a visible alignment indicator provided thereon, and at least one tool path indicator; and
a sensor device, comprising:
a visible alignment indicator on an exterior of the sensor device;
at least one magnetic sensor, memory, and a microprocessor in communication with the at least one magnetic sensor and the memory, configured to detect a magnetic field from the simulation tool and to determine a path travelled by the simulation tool with respect to the sensor device, while the visible alignment indicator of the sensor device is maintained in physical alignment with the visible alignment indicator of the simulation workpiece.

US Pat. No. 10,460,622

ASSISTED PROGRAMMING USING AN INTERCONNECTABLE BLOCK SYSTEM

1. An interconnectable block based system comprising:a plurality of interconnectable blocks; and
a processing unit, coupled to the plurality of interconnectable blocks, configured to:
determine a programming language construct, or a portion thereof, based on a sequence in which the plurality of interconnectable blocks are connected to each other,
execute the programming language construct, or the portion thereof, to generate an output, and
transmit the output to an output device, wherein the output device is at least an electroacoustic transducer device or an electroluminescent device, wherein the output device is coupled to the interconnectable block based system;
wherein at least one interconnectable block has at least one pinhole that can accommodate another electroluminescent device to indicate a particular state of the at least one interconnectable block.

US Pat. No. 10,460,621

ADVANCED DEVICE FOR WELDING TRAINING, BASED ON AUGMENTED REALITY SIMULATION, WHICH CAN BE UPDATED REMOTELY

Seabery Soluciones, S.L.,...

7. An apparatus, comprising:a welding mask including a set of confocal cameras operably coupled to video glasses, the video glasses configured to display, to a wearer of the welding mask during use, a three-dimensional mixed-reality setting including real images captured by the set of confocal cameras and at least one virtual element, the set of confocal cameras configured to recognize:
a first marker having a first predetermined pattern disposed on a removable tip of a welding torch, the removable tip replaceable with each tip from a set of further tips each having an associated pattern different from the first predetermined pattern; and
a second marker having a second predetermined pattern associated with a workpiece, and the welding mask configured to permit interaction between the welding torch, the workpiece and the at least one virtual element within the three-dimensional mixed-reality setting in response to the first predetermined pattern and the second predetermined pattern being recognized.

US Pat. No. 10,460,620

DEVICE FOR LINKING BODILY MOVEMENT TO LEARNING BEHAVIOUR AND METHOD WHEREBY SUCH A DEVICE IS APPLIED

I3-TECHNOLOGIES, NAAMLOZE...

1. A method for linking seat movement to learning behavior, the method comprising:providing an arrangement of a plurality of objects that are cube-shaped seating units in an arbitrary pattern around the central teaching module that is wirelessly connected to a digital module in each cube-shaped seating unit, the digital module being configured to detect movements of the respective cube-shaped seating unit caused by the pupils to answer questions or assignments;
transmitting, by the digital module in the respective cube-shaped seating unit, the position or the movement of the respective cube-shaped seating unit wirelessly to the central teaching module when the pupils give an answer to an assignment by moving the respective cube-shaped seating unit; and
sending an individual wireless signal by the central teaching module to each cube-shaped seating unit related to the movement that is made with the respective cube-shaped seating unit, the individual wireless signal including an identification of the cube-shaped seating unit for which the individual wireless signal is intended, evaluating an individually-provided answer from the cube-shaped seating unit to which the individual wireless signal is sent as to whether the answer was right or wrong or providing another evaluation of the answer, and providing an individual light signal on each cube-shaped seating unit from which the pupil can read at the respective cube-shaped seating unit whether the answer was right or wrong, or an indication of the other evaluation of the answer,
wherein each of the cube-shaped seating units is equipped with one or more of movement detectors and orientation detectors that are connected to the digital module of the respective cube-shaped seating unit to detect the movement and the position of the respective cube-shaped seating unit, and
the method further comprises transmitting, by the movement detectors and the orientation detectors, the movements and the positions caused by the pupil to answer questions or assignments to the digital module of the respective cube-shaped seating unit.

US Pat. No. 10,460,619

METHOD AND SYSTEM OF CUSTOMIZING SCRIPTURE STUDY

1. A method of customizing scripture study via a graphical user interface comprising:providing a graphical user interface having at least two distinct areas comprising an interactive area and a display area, wherein the interactive area comprises text entry, selectable passages, and links to study resources;
saving and outputting information after implementing the following steps:
(a) specifying a range of scripture which includes:
(i) selecting a plurality of passages varying from a small assortment of passages to a complete canon of scripture;
(ii) selecting a passage format of verse, chapter, or book;
(b) randomly generating by a computer processor a study passage which includes;
(i) assigning a reference number to each passage;
(ii) using dice to randomly generate a reference number;
(iii) matching dice reference number using a reference table;
(c) said computer processor optimizes the study of the random study passage by linking to various resources such as a commentary, lexicon, study guide, timeline, concordance, original language helps, maps, and a memorization tool;
(d) storing in a database said study passage including said reference table with said matched dice reference number;
(e) transmitting over a network a study report including said reference table with said matched dice reference number.

US Pat. No. 10,460,611

DYNAMIC NAVIGATION OF UAVS USING THREE DIMENSIONAL NETWORK COVERAGE INFORMATION

Verizon Patent and Licens...

1. A method comprising:maintaining, by one or more computing devices, a three-dimensional network coverage map that includes, for each of a plurality of locations, an indication of wireless signal strength for a wireless network, each of the plurality of locations being three-dimensional locations that are defined as including a height value at which unmanned aerial vehicles (UAVs) are likely to fly, the indications of the wireless signal strengths being obtained using:
signal strength estimation techniques based on locations of base stations, orientations of antennas respectively associated with the base stations, and geographic topology around the base stations, and
measuring devices to measure wireless signal strengths at various altitudes;
determining, by the one or more computing devices, a flight path, for a UAV, based on the three-dimensional network coverage map, the determined flight path indicating three-dimensional altitudes at which the UAV should fly to optimize connectivity to the cellular wireless network when the UAV is traversing the flight path; and
transmitting, by the one or more computing devices, the determined flight path to an entity associated with navigation of the UAV.

US Pat. No. 10,460,607

PREDICTIVE MULTIMODAL LAND TRANSPORTATION SUPERVISION

ALSTOM TRANSPORT TECHNOLO...

1. A supervision infrastructure for a multimodal land transportation network that groups together a plurality of monomodal land transportation networks, wherein each monomodal land transportation network is equipped with an individual operating system, the supervision infrastructure comprising:a plurality of local supervision modules, each local supervision module being associated with a transfer station providing an interconnection between at least two of the monomodal land transportation networks, and wherein each local supervision module is configured to:
perform a real-time traffic synthesis of traffic at the associated transfer station,
execute continuously a plurality of operating rules by using operating data from the real-time traffic synthesis to generate at least one setpoint, and
send the at least one setpoint to at least one operating system of at least one monomodal land transportation network from among the monomodal land transportation networks interconnected to the associated transfer station, and
a global supervision module configured to send, to each of said local supervision modules, the plurality of operating rules that the local supervision module must execute, wherein the plurality of operating rules sent to one local supervision module differs from the plurality of operating rules sent to another local supervision module.

US Pat. No. 10,460,597

SYSTEM AND METHOD OF CONTROLLING EXTERNAL APPARATUS CONNECTED WITH DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method of controlling external devices, the method comprising:receiving, from a server, first identification information of a plurality of external devices and first capability information regarding capabilities that the plurality of external devices are able to perform;
receiving, from an electronic device distinct from the plurality of external devices, a single user voice command input by a user to the electronic device;
obtaining a user intent regarding the received single user voice command based on the received single user voice command;
identifying at least two external devices, from among the plurality of external devices, based on the obtained user intent regarding the single user voice command and the first identification information of the plurality of external devices;
generating control information for control commands controlling the identified at least two external devices, based on the obtained user intent regarding the single user voice command, second capability information of the identified at least two external devices, and second identification information of the identified at least two external devices; and
outputting the generated control information for the control commands controlling the identified at least two external devices.

US Pat. No. 10,460,590

METHOD AND SYSTEM FOR MOBILE DURESS ALARM

TYCO INTEGRATED SECURITY,...

1. A method for responding to potential security events comprising:specifying one or more arming events, expiration actions, and disarming actions for a user;
a mobile application executing on a mobile computing device of the user detecting the specified arming events for the user, starting recording event data including recording audio and video data by the mobile computing device in response to detecting the specified arming events for the user,
buffering the recorded event data including the audio and video data recorded by the mobile computing device,
executing the specified disarming actions for the user in response to determining that the mobile application was disarmed by the user within a predetermined time period including stopping recording the audio and video data and deleting the recorded audio and video data; and
executing the specified expiration actions for the user in response to determining that the mobile application was not disarmed by the user within the predetermined time period including sending the recorded audio and video data to the monitoring center and streaming recorded audio and video data to the monitoring center.

US Pat. No. 10,460,583

GPS MONITORING SYSTEM AND ASSOCIATED USE THEREOF

1. A GPS monitoring system comprising:a child wristband including a first GPS transceiver;
an adult wristband including a second GPS transceiver in continuous communication with said first GPS transceiver;
a portable electronic device in communication with each said child wristband and said adult wristband; and
at least one communications network in communication with each said child wristband, adult wristband, and said portable electronic device;
wherein said portable electronic device includes
a display screen,
a processor in communication with each said first GPS transceiver and second GPS transceiver and said display screen, and
a memory communicatively coupled to said processor and including software instructions, when executed by said processor, that monitors whether a real-time location of said child wristband relative to a real-time location of said adult wristband is within an authorized maximum distance at an authorized geographic location during an authorized time period;
wherein each of said child wristband and said adult wristband are portable;
wherein said software instructions comprise the steps of:
receiving said authorized time period, at said portable electronic device, during which said child wristband and said adult wristband are desired to be monitored;
receiving said authorized maximum distance limit, at said portable electronic device, in which said child wristband is permitted to travel away from said adult wristband; and
receiving said authorized geographic zone, at said portable electronic device, in which said authorized time period and said authorized maximum distance limit are desired to be monitored;
wherein said software instructions further comprise the step of:
receiving a real-time operating parameter signal from each said child wristband and said adult wristband, each said real-time operating parameter signal being bifurcated into first and second channels each including
a first data stream defining a real-time transmission occurrence of said real-time operating signals, and
a second data stream defining a real-time location of said child wristband and said adult wristband;
wherein each said real-time operating parameter signal is true when
said real-time transmission occurrence is within said authorized time period; and
a real-time distance between said child wristband and said adult wristband is greater than said maximum distance limit as well as within said authorized geographic zone;
wherein each said real-time operating parameter signal is false when
said real-time transmission occurrence is not within said authorized time period; or
said real-time distance between said child wristband and said adult wristband is less than said maximum distance limit or not within said authorized geographic zone;
wherein said software instructions further comprise the step of:
if said real-time transmission occurrence is true, generating and transmitting a first alert signal to each said child wristband and said adult wristband as well as generating and graphically displaying, on said portable electronic device, a directional arrow identifying said real-time location of said child wristband relative to a real-time location of said adult wristband;
wherein said software instructions further comprise the step of:
if said real-time transmission occurrence is false, requesting said adult wristband to verify if said adult wristband wishes to know said real-time location of said child wristband.

US Pat. No. 10,460,579

TAMPER DETECTION SYSTEM

United States of America ...

1. A system for detecting tampering, comprising:an item of value;
a luminescent layer enclosing the item of value, wherein the luminescent layer emits a light beam during the tampering to access the item of value;
an optical detector for detecting the light beam emitted during the tampering; and
an alarm activated in response to the optical detector detecting the light beam emitted during the tampering, the alarm providing a real-time alert of the tampering to a remote user.

US Pat. No. 10,460,572

METHODS AND SYSTEM FOR PROCESSING CUSTOMERS THROUGH A POINT-OF-SALE SYSTEM HAVING A MULTIPLE-ITEM PRICE SCANNING APPARATUS

NCR Corporation, Atlanta...

1. A system for processing customers of a retail establishment through a point-of-sale system at which multiple items can be simultaneously scanned for purchase, the system comprising:a conveyance path to transport items for purchase from the retail establishment, a multiple-item scanner to substantially simultaneously price scan multiple items grouped together on the conveyance path as the conveyance path transports the multiple items thereby,
a diverter configured to be controlled by a processor of the system, the diverter situated at an end of the conveyance path and on direction of the processor diverts a grouping of the items onto a particular one of a plurality of linear conveyance paths, each of the linear conveyance paths sloping downward to the particular one of a plurality of separate item collection areas,
the plurality of separate item collection areas coupled to the conveyance path, each of the plurality of item collection areas configured to selectively and linearly receive items from a particular linear conveyance path after price scanning by the multiple-item scanner, wherein the plurality of separate item collection areas includes four separate item collection areas arranged and situated in a circle around an end portion of the conveyance path,
a plurality of customer payment interfaces each positioned at a different one of the plurality of item collection areas and each configured to process customer payment for purchase of items routed only to the one of the plurality of item collection areas at which that customer payment station is positioned;
a plurality of weigh scales to weigh select ones of the items, each weigh scale positioned proximate to a particular customer payment interface and each weigh scale a peripheral device of the particular customer payment interface to which that weigh scale is positioned proximate to;
a plurality of customer displays, each customer display situated adjacent to each entrance of each of the linear conveyance paths; and
firmware and software configured to allow a local server to control and process information on the local server for transactions of the customers at the point-of-sale device that would otherwise be processed on the point-of-sale system, the point-of-sale system configured to operate as a thin-client device interfaced to the local server, wherein the firmware and software further configured to display customer-assignment information on each customer display indicating assignments between the customers and the item collection areas at the entrances of each of the linear conveyance paths.

US Pat. No. 10,460,569

SMART BIN LOTTERY TICKET DISPENSER WITH INTEGRATED CONTROLLER

Scientific Games Internat...

1. A lottery ticket dispenser array, comprising:an external frame;
a plurality of separate bins contained within the frame, each bin defined by a housing having a front side that is exposed to and faces a purchaser in operational use of the dispenser array, an opposite back side exposed to a user of the dispenser array, and an internal space for receipt of a supply of interconnected lottery tickets, wherein each lottery ticket contains a code printed thereon;
each bin having an electronic drive mechanism that dispenses the lottery tickets therefrom;
a controller in communication with each of the drive mechanisms to initiate a dispense sequence upon receipt of a ticket dispense command from the controller;
the controller configured externally on the frame and variably positional on the frame between different physical and operational positions on the frame such that the controller is presented to the user as an interface with the dispenser array and variably positionable by the user to the different operational positions on the frame; and
wherein the controller is slidable along a bottom member, top member, or side member of the frame between the different operational positions.

US Pat. No. 10,460,568

SPECIALIZED SLOT MACHINE FOR CONDUCTING A WAGERING TOURNAMENT GAME USING REAL TIME OR LIVE ACTION EVENT CONTENT

1. A specialized slot machine comprising:a data processor;
a network interface, in data communication with the data processor, for communication on a data network; and
a gaming system, executable by the data processor, to:
prompt a plurality of users at a plurality of geographically distributed user platforms to each submit a wager for entry as players into a real time live action wagering tournament game;
divide the plurality of players of the real time live action wagering tournament game into player groups, the player groups each having a pre-determined quantity of players, the players in each player group competing with other players of a same player group to advance through a pre-determined number of rounds to a main tournament, the players in each player group only playing against other members of the same player group during a given round;
obtain a set of real time or live event content via the data network while the plurality of players are playing the real time live action wagering tournament game, the gaming system using the network interface to establish a data connection with a network resource located at a remote venue at which a live event is occurring, the real time or live event content being generated at the remote venue by the network resource based on activity at the live event;
partition the set of real time or live event content into a plurality of content categories;
generate a raw score for each of the content categories based on real time information obtained via the data network;
receive from the players in each player group a bid corresponding to at least one of the content categories;
receive from the players in each player group credits corresponding to the bid via a value input mechanism of a handheld device, the value input mechanism including a reader or a touch key interface to enable a player to authorize access to a central account of the player and authorize transfer of credits of the player from the central account to the specialized slot machine, the value input mechanism including a ticket reader, a barcode scanner, or a QR code scanner for reading information stored on a credit ticket, a card, or other tangible portable credit storage device;
score each of the players in each player group based on their bids and the raw score of the content category corresponding to their bids;
rank each of the players in each player group based on their score; and
enable a pre-determined quantity of highest ranked players from each player group to advance to a next round.

US Pat. No. 10,460,566

SYSTEM AND METHOD FOR PEER-TO-PEER WIRELESS GAMING

CFPH, LLC, New York, NY ...

1. A method comprising:receiving, by at least one processor, a request from a first device via a network interface, the request identifying a selected gaming activity, a maximum number of players for the gaming activity, and a betting limit for the gaming activity;
searching, by the at least one processor, profile information of users stored in a database that are potential participants in the gaming activity;
transmitting, by the at least one processor, a list of users to the first device via the network interface;
receiving, by the at least one processor, from the first device via the network interface, a selection of a second user from the list of users;
determining, by the at least one processor, whether the first device and a second device are in a location that permits the gaming activity;
in response to determining that the first device and the second device are in a location that permits the gaming activity, determining, by the at least one processor, a distance between the first device and the second device;
determining, by the at least one processor, whether a distance requirement has been violated, in which the distance requirement comprises a minimum distance that must be maintained between the first device and the second device when providing the gaming activity;
based at least in part on determining that the distance requirement has been violated, disabling, by the at least one processor, the gaming activity at the first device and the second device;
based at least in part on determining that the distance requirement has not been violated, enabling, by the at least one processor, the gaming activity at the first device and the second device and communicating, by the at least processor, an invitation from the first device to the second device via the network interface, wherein the first device and the second device exchange location information and display the location information on respective screens;
receiving, by the at least one processor, an acceptance of the invitation from the second device via the network interface;
responsive to receiving the acceptance of the invitation from the second device, transmitting, by the at least one processor, data indicative of the gaming activity to the first device and the second device via the network interface; and
in response to determining that the first device and the second device are not in a location that permits the gaming activity, preventing, by the at least one processor, data indicative of the gaming activity from being transmitted to the second device via the network interface.

US Pat. No. 10,460,560

METHODS AND ARCHITECTURE FOR CASHLESS SYSTEM SECURITY

IGT, Las Vegas, NV (US)

1. A gaming system comprising:at least one input device;
at least one display device;
at least one processor; and
at least one memory device which stores a plurality of instructions, which when executed by the at least one processor, cause the at least one processor to operate with the at least one display device and the at least one input device to:
(a) wirelessly receive information from a mobile device, wherein:
(i) said mobile device is in one of an online state and an offline state,
(ii) the offline state corresponds to at least one transaction performed when the mobile device is authenticated by the at least one processor,
(iii) the online state corresponds to at least one transaction performed when the mobile device is authenticated by the at least one processor and by a remote host, and
(iv) the received mobile device information relates to any unacknowledged transactions that were performed when the mobile device was operating in the offline state,
(b) responsive to receiving from the mobile device information relating to a first unacknowledged transaction, send the information relating to the first unacknowledged transaction to the remote host,
(c) receive a transaction acknowledgment from the remote host for the first unacknowledged transaction, and
(d) send the transaction acknowledgment to the mobile device and enable a play of wager-based game.

US Pat. No. 10,460,559

SYSTEM AND METHOD OF CONDUCTING GAMES OF CHANCE WITH ENHANCED PAYOUTS BASED ON CASH IN AMOUNT

1. A method of conducting a player loyalty program to award a player of a game on an electronic gaming machine, the electronic gaming machine being operatively associated with a display, a memory unit and a processor, the method comprising the steps of:said processor accepting an initial investment from a player to participate in said game on said electronic gaming machine, the electronic gaming machine being configured to use a first payout schedule and a second payout schedule to determine payouts from instances of play of a game of chance, the first and second payout schedules being stored in the memory unit operatively associated with the electronic gaming machine and the first payout schedule having a greater overall payout percentage than the second payout schedule, wherein any payout is distributed to a player account stored in the memory unit of the electronic gaming machine;
said processor operatively associated with the electronic gaming machine facilitating the crediting said player's account stored in the memory unit operatively associated with said electronic gaming machine an amount equivalent to said initial investment, wherein said crediting of the player's account is stored in the memory unit;
said processor operatively associated with the electronic gaming machine facilitating the counting of a number of times the first payout schedule is used to determine a payout of none or one or more credits for crediting to said player's account stored in the memory unit operatively associated with said electronic gaming machine from instances of play of the game; and
responsive to said processor operatively associated with the electronic gaming machine facilitating the determination of the counted number of times said first payout schedule is used to determine a payout to said player's account being equal to or greater than a first threshold value, said processor operatively associated with the electronic gaming machine facilitating the assigning an award for display on the display operatively associated with the electronic gaming machine; and
responsive to said processor operatively associated with the electronic gaming machine facilitating the determination of the counted number of times said first payout schedule is used to determine a payout to said player's account stored in the memory unit being less than said first threshold value, said processor using one of the first and second payout schedules stored in the memory unit to determine a payout amount to be credited to said player's account stored in the memory unit from an instance of play of the game on the electronic gaming machine.

US Pat. No. 10,460,555

TABLE GAME PLAY USING PORTABLE ELECTRONIC DEVICES

Fresh Idea Global Limited...

1. A gaming system, comprising:a system server located remotely from and in communication with a plurality of electronic gaming tables, the system server being adapted to facilitate providing gaming data from multiple table games at different gaming tables from the plurality of electronic gaming tables to a player located remotely from all of the plurality of electronic gaming tables, with the player using a portable electronic device adapted to function as a player terminal for any of the plurality of electronic gaming tables; and
at least one server communication interface coupled to the system server and adapted to facilitate the routing of game data from the multiple table games from the different gaming tables to the portable electronic device,
wherein each of the plurality of electronic gaming tables includes at least:
a physical surface adapted for the play of a table game that includes a live dealer and the use of one or more physical game components, the live dealer manipulates the one or more physical game components that provide random game data for the table game,
a table controller adapted to control a plurality of gaming table functions, and
a table communication interface coupled to the table controller and adapted to facilitate routing of data between the table controller and the system server, and
wherein the multiple table games are able to be different games operated by different live dealers at the different gaming tables,
wherein the plurality of electronic gaming tables are adapted to provide live table games involving wager based games,
wherein said gaming system is adapted to facilitate play, by the player using the portable electronic device, in the live table games with respect to other players that can also be playing the live table games, and
wherein play of the live table game by the player is independent of play of the live table games with respect to other players such that the player is permitted to play the live table games at his or her own pace and is not required to concurrently play the live table game with the other players.

US Pat. No. 10,460,553

METHODS OF USER AND MACHINE INTERACTION AND APPARATUS FOR FACILITATING USER INTERACTION

Takara Gaming Solutions L...

1. A method of interaction involving a machine and a player or a plurality of players, the method comprising:the machine selecting a plurality of information bearing devices from a deck comprising a predetermined plurality of available information bearing devices to form a hand of playing devices upon a player making an initiation request to the machine, wherein each playing device is an information bearing device selected from the predetermined plurality of available information bearing devices by the machine;
the machine sending the playing devices to an electronic display apparatus representing the player, and displaying the playing devices on a display screen of the electronic display apparatus, wherein the playing devices are distributed in a distribution matrix which is formed on a first display region of the display screen;
the machine moving a scoring combination out of an allocated position on the distribution matrix into a second display region of the display screen which is outside the first display region, wherein the scoring combination comprises a playing device or a plurality of playing devices and carries a predetermined score value;
the machine maintaining a first counter and incrementing the first counter by a value corresponding to the predetermined score value; and
the machine moving the scoring combination back to the allocated position.

US Pat. No. 10,460,547

TWO-WAY EXCHANGE VENDING

Tricopian, LLC, Carlsbad...

1. A vending system comprising:a vending unit for vending and receiving products, the vending unit comprising a communication module and a unique identifier; and
a central computer, remote from the vending unit, the central computer comprising:
a processor;
a database associating the unique identifier with product information for products available at the vending unit; and
a communication unit, the central computer being in communication with the vending unit;
wherein the central computer is configured to receive the unique identifier indicative of the vending unit from a user vending interface running on a user interface device, the user interface device being located remotely from the vending unit;
wherein the central computer is configured to identify the vending unit into which a received product is deposited based on the unique identifier received from the user vending interface, and
wherein the central computer is configured to determine from the database the identity of products available at the vending unit in response to receiving the unique identifier from the user vending interface and to communicate an option for completing a transaction at the vending unit to the user vending interface.

US Pat. No. 10,460,541

REMOTELY UNLOCKABLE ELECTRICAL PANEL

A.G. STACKER INC., Weyer...

1. A system comprising:a first electrical panel having a high voltage compartment and a low voltage compartment and a first door shiftable between an open position allowing access to the high voltage compartment and a closed position preventing access to the high voltage compartment;
a first lock shiftable between a locked position locking the first door and an unlocked position unlocking the first door;
a first actuator configured to shift the first lock from the locked position to the unlocked position in response to a receipt of an unlock signal;
a main disconnect switch outside the first electrical panel shiftable between an ON position for connecting a source of electric current to the first electrical panel and an OFF position for disconnecting the source of electric current from the first electrical panel;
a sensor configured to detect a position of the main disconnect switch and to send the unlock signal to the first actuator in response to a detection that the main disconnect switch is in the OFF position;
a second electrical panel having a high voltage compartment and a low voltage compartment and a second door shiftable between an open position allowing access to the high voltage compartment of the second electrical panel and a closed position preventing access to the high voltage compartment of the second electrical panel;
a second lock shiftable between a locked position locking the second door and an unlocked position unlocking the second door; and
a second actuator in communication with the sensor and configured to shift the second lock from the locked position to the unlocked position in response to the receipt of the unlock signal.

US Pat. No. 10,460,538

SCANNERLESS VENUE ENTRY AND LOCATION TECHNIQUES

Flash Seats, LLC, Clevel...

1. An attendee device, comprising:a processor-readable, non-transitory memory that stores computer executable components; and
a processor that executes the following computer executable components stored in the memory:
a communication component that receives ticket data indicative of a privilege to enter a venue;
a first component configured to detect receipt of an audio signal from a venue beacon;
a redemption component that, in response to detection of the audio signal from the venue beacon:
performs a self-validation procedure in which the attendee device validates the ticket data, and
in response to the ticket data being validated, generates at least a portion of verification data that is representative of an indication the ticket data was self-validated;
a presentation component that instructs the attendee device to present the verification data.

US Pat. No. 10,460,535

METHOD AND SYSTEM FOR DISPLAYING AN INITIAL LOSS REPORT INCLUDING REPAIR INFORMATION

STATE MUTUAL AUTOMOBILE I...

1. A method for displaying an initial loss report for a damaged vehicle, the method executed by one or more processors programmed to perform the method, the method comprising:receiving, by one or more processors, sensor data from a vehicle connected to a plurality of sensors including a plurality of: vehicle part position data from spatial sensors disposed within the vehicle, vehicle image data from an image capturing device disposed within the vehicle, vehicle acceleration data from an accelerometer disposed within the vehicle, vehicle velocity data from a positioning device disposed within the vehicle, or vehicle direction data from the positioning device and an indication of a crash for the vehicle;
analyzing, by the one or more processors, the sensor data to determine an extent of damage to the vehicle;
in response to determining the extent of the damage to the vehicle, automatically determining, by the one or more processors, a treatment complexity level based on the extent of the damage to the vehicle, the treatment complexity level representing a degree of difficulty associated with treating the vehicle;
causing, by the one or more processors, indications of one or more treatment facilities capable of performing treatment for the vehicle at the determined treatment complexity level to be displayed on a user interface;
receiving, by the one or more processors, a selection of one of the one or more displayed treatment facilities; and
transmitting, by the one more processors, information associated with transporting the vehicle to the selected treatment facility.

US Pat. No. 10,460,530

LOCALIZATION OF TRANSACTION OF TAGS

Conduent Business Service...

1. A method for validation of a trip on a vehicle traveling on a route of a transportation network, the vehicle including an automated ticketing validation device, the vehicle carrying a plurality of passengers with respective mobile communication devices, the route including a plurality of spaced stationary beacons, the method comprising:receiving, by an automated vehicle location component, signals from one of the plurality of spaced stationary beacons on the route, the beacon signals including localization data for the respective beacon, the localization data including a beacon identifier;
receiving, by a receiver component or transceiver of the automatic ticketing validation device, which the vehicle transports, a passenger identifier from a respective one of the mobile communication device of one of the plurality of passengers on the vehicle via short range communication;
generating, by a processor of the automatic ticketing validation device, encrypted transaction data based on the passenger identifier, localization data and a timestamp;
transmitting, by an emitter component or the transceiver of the automatic ticketing validation device, the encrypted transaction data to at least one of the mobile communication devices; and
by a server:
receiving the encrypted transaction data from the at least one of the mobile communication devices,
decrypting the encrypted transaction data,
extracting the localization data, the passenger identifier, and the timestamp from the decrypted transaction data,
retrieving a location of the beacon from memory, based on the beacon identifier, and
performing a transaction based on the location and passenger identifier.

US Pat. No. 10,460,528

FIGURE DRAWING APPARATUS, CONTROL METHOD OF FIGURE DRAWING APPARATUS, AND RECORDING MEDIUM

CASIO COMPUTER CO., LTD.,...

1. A control method of a figure drawing apparatus comprising a processor, the control method performed by the processor comprising:a process in which, when drawing one or more arbitrary shapes formed by connecting a plurality of points included in a plane to be drawn and thereby drawing the plane to be drawn within a drawing area of a display screen of a display device, if a predetermined first combination of two or more points of the plurality of points of one arbitrary shape among the one or more arbitrary shapes is not located within the drawing area, the one arbitrary shape is not drawn within the drawing area of the display screen by the display device;
a process in which one or more triangles are specified as the one or more arbitrary shapes, vertices of each of the one or more triangles being a center point of a circle or an ellipse as the plane to be drawn and two neighboring different points on an arc of the circle or the ellipse; and
a process in which, when the center point among three vertices of one triangle among the one or more triangles is located outside the drawing area and the two points on the arc is located within the drawing area, the one triangle is displayed within the drawing area of the display screen.

US Pat. No. 10,460,524

ROLL TURNING AND TAP TURNING FOR VIRTUAL REALITY ENVIRONMENTS

Microsoft Technology Lice...

1. A computing device comprising:a processing unit; and
memory;
the computing device configured to perform operations for turning in a virtual environment, the operations comprising:
receiving, from a user via an analog input control, a first movement of the analog input control to a border region of the analog input control;
determining a point where the first movement reaches the border region;
in response to the first movement of the analog input control, activating a roll turn mode, wherein activation of the roll turn mode does not result in any turning of an element in the virtual environment regardless of the point where the first movement reaches the border region;
while in the roll turn mode:
receiving a second movement of the analog input control along the border region of the analog input control;
determining a turning amount corresponding to the second movement; and
turning the element in the virtual environment by the determined turning amount;
wherein any turning of the element in the virtual environment only begins after receiving the second movement.

US Pat. No. 10,460,523

AUGMENTED REALITY SYSTEM FOR ELECTROMAGNETIC BURIED ASSET LOCATION

1. A system for calculating and visualizing a position of a buried asset during a location procedure in a target area, the system comprising:1) an electromagnetic locate device (ELD) including one or more electromagnetic antennas configured for sensing an electromagnetic (EM) field emanating from the buried asset at a target area, wherein each electromagnetic antenna produces a vector field data at each periodic point in space; and
2) an augmented reality system comprising a camera, a display, inertial sensors for measuring motion and distance moved, and one or more processors configured for:
a) reading camera data from the camera of a target area in which the system is situated, and reading sensor data from the inertial sensors;
b) calculating motion of the electromagnetic antennas and distance moved by the electromagnetic antennas based on the sensor data and the camera data;
c) generating a 3D model representing the electromagnetic antennas and the target area in which the system is situated, based on the camera data, and the motion and distance moved that was calculated;
d) calculating vector field values for the EM field at multiple different points in space based on the vector field data from the electromagnetic antennas;
e) placing each vector field value that was calculated in the 3D model representing the electromagnetic antennas and the target area in which the system is situated, based on the camera data, and the motion and distance moved that was calculated, thereby generating a 3D vector field representing the EM field emanating from the buried asset;
f) calculating a position of the buried asset based on the 3D vector field and the 3D model, and creating an object in the 3D model that represents the position of the buried asset; and
g) rendering video of the target area in the display, and overlaying onto said video a graphic representation of the position of the buried asset, based on the 3D model.

US Pat. No. 10,460,513

COMBINED WORLD-SPACE PIPELINE SHADER STAGES

Advanced Micro Devices, I...

17. A computer system for executing a shader program for a combined shader stage of a graphics processing pipeline, the computer system comprising:a processor executing a device driver for controlling an accelerated processing device (APD); and
the APD, comprising:
a plurality of shader engines including registers and local data store memory; and
a scheduler configured to:
receive a combined shader program for the combined shader stage from the device driver, wherein the combined shader stage includes one of a combined vertex shader and hull shader stage and a combined vertex shader and geometry shader stage, the combined shader program including instructions from a vertex shader program and either a hull shader program or a geometry shader program;
for a first primitive for which tessellation is disabled and geometry shading is enabled, configure the graphics processing pipeline in a vertex shader/geometry shader configuration, in which a vertex shader stage and stages for tessellation, including the combined vertex and hull shader stage, are bypassed;
for a second primitive, for which tessellation is enabled, configure the graphics pipeline in a vertex/hull shader configuration, in which the vertex shader stage is bypassed, and in which the combined vertex shader and geometry shader stage does not process the second primitive; and
reserve resources for a number of wavefronts to execute the combined shader program in the plurality of shader engines, the number of wavefronts being the greater of a number of wavefronts to execute instructions from the vertex shader program and instructions from the hull shader program or geometry shader program; and
spawn the number of wavefronts to execute the combined shader program in the plurality of shader engines.

US Pat. No. 10,460,509

PARAMETERIZING 3D SCENES FOR VOLUMETRIC VIEWING

Dolby Laboratories Licens...

1. A method for selecting sampled views of multiview images, comprising:determining a target view to a 3D scene depicted by a multiview image, the multiview image comprising a plurality of sampled views at a plurality of sampled view positions distributed throughout a viewing volume, each sampled view in the plurality of sampled views of the multiview image comprising a wide-field-of-view (WFOV) image and a WFOV depth map corresponding to the WFOV image, each sampled view of the multiview image in the plurality of sampled views of the multiview image corresponding to a respective sampled view position in the plurality of sampled view positions;
using the target view to select, from the plurality of sampled views of the multiview image, a set of sampled views, each sampled view in the plurality of sampled views corresponding to a respective viewpoint to the 3D scene;
causing a display image to be rendered on a display of a wearable device of a user, the display image being generated based on one or more portions of the WFOV image and one or more portions of the WFOV depth map for each such sampled view in the set of sampled views.

US Pat. No. 10,460,508

VISUALIZATION WITH ANATOMICAL INTELLIGENCE

Siemens Healthcare GmbH, ...

1. A computer-implemented method of visualization, comprising:(i) receiving magnetic resonance image data;
(ii) automatically localizing at least one bone structure of interest in the image data that appears only in a first number of slices in the image data;
(iii) highlighting and flattening the localized bone structure of interest by reformatting the image data into reformatted image data by
estimating a cylindrical shape of the localized bone structure of interest based on landmarks associated with the localized bone structure of interest,
resampling voxels on a surface of the cylindrical shape from the image data, and
mapping the resampled voxels on the cylindrical shape to corresponding points on a visualization plane to flatten the localized bone structure of interest, and
wherein the bone structure of interest appears only in a second number of slices of the reformatted image data, wherein the second number of slices is less than the first number of slices; and
(iv) rendering the reformatted image data for display via a display device.

US Pat. No. 10,460,507

RENDERING A 3-D SCENE USING NORMAL OFFSET SMOOTHING

Imagination Technologies ...

1. A computer-implemented method of rendering an image of a 3-D scene using a ray tracing system, comprising:identifying an intersection at an intersection point between a primary ray and a planar primitive located in the 3-D scene;
emitting a secondary ray in response to identifying said intersection, wherein the secondary ray has an origin determined as an offset from the intersection point of the primary ray with the primitive, the origin being offset from the intersection point such that the origin of the secondary ray: (i) lies on an implicit curved surface associated with the planar primitive, and (ii) does not lie on the planar primitive,
tracing the secondary ray to identify an intersection involving the secondary ray; and
using the results of the tracing of the secondary ray in rendering the image of the 3-D scene.

US Pat. No. 10,460,506

METHOD AND APPARATUS FOR GENERATING ACCELERATION STRUCTURE

SAMSUNG ELECTRONICS CO., ...

1. A method for generating an acceleration structure used for ray tracing by at least one processor, the method comprising:generating a linear code, the linear code representing a position of each of a plurality of primitives included in a three-dimensional (3D) space;
arranging the plurality of primitives according to the generated linear code;
determining a rate of change of a size of a generated bounding box while sequentially inputting the plurality of arranged primitives into the generated bounding box;
selecting one of the plurality of arranged primitives based on the rate of change of the size of the generated bounding box; and
classifying the plurality of arranged primitives into a plurality of determined bounding boxes according to the selected primitive.

US Pat. No. 10,460,504

PERFORMING A TEXTURE LEVEL-OF-DETAIL APPROXIMATION

NVIDIA CORPORATION, Sant...

1. A method comprising:identifying a scene to be rendered;
projecting a ray passing through a pixel of a screen space, resulting in a first hit point at a geometry element within the scene;
determining a footprint angle of the pixel;
determining a curvature measure for the geometry element at the first hit point within the scene;
computing a texture level of detail (LOD) approximation for a component of the scene, utilizing the footprint angle of the pixel and the curvature measure for the geometry element; and
performing, utilizing a hardware processor, one or more rendering operations for the scene, utilizing the texture LOD approximation.

US Pat. No. 10,460,498

CONSTRAINT EVALUATION IN DIRECTED ACYCLIC GRAPHS

DreamWorks Animation L.L....

1. An electronic device, including:one or more processors; and
memory storing one or more programs for evaluating a constraint system for use in rendering three-dimensional (3D) graphics, wherein the one or more programs are configured to be executed by the one or more processors, the one or more programs including instructions for:
accessing a first directed acyclic graph (DAG) representing a first virtual 3D object;
accessing a second DAG representing a second virtual 3D object;
receiving a constraint relationship request, the constraint relationship request identifying the first DAG as a constraint parent and the second DAG as a constraint child;
verifying whether the first DAG is compatible for constraining to the second DAG;
connecting, in response to the first DAG and second DAG being compatible for constraining, an output of the first DAG to an input of the second DAG; and
in accordance with a determination that an output value of the first DAG does not affect an evaluation of the second DAG, rendering a first image depicting at least a portion of the first virtual 3D object and at least a portion of the second virtual 3D object.

US Pat. No. 10,460,496

INFORMATION DISPLAY BY OVERLAY ON AN OBJECT

1. A method for display in a computer system, the method comprising:detecting an object in a field-of-view (FOV) using at least one sensor coupled to the computer system;
determining a shape of the object using a processor of the computer system;
creating an overlay element having the shape of the object and a changeable characteristic comprising a transparency or a fill amount;
obtaining a series of values of a parameter over a period of time, wherein the parameter is related to a temperature of the object, a pressure in the object, a hazard level of the object, an expected time remaining to an action by the object, or a fuel level of the object;
rendering multiple representations of the overlay element with the changeable characteristic changed based on the series of values of the parameter; and
serially presenting the multiple representations of the overlay element over the period of time on a display of the computer system to at least partially occlude the object.

US Pat. No. 10,460,490

METHOD, TERMINAL, AND COMPUTER STORAGE MEDIUM FOR PROCESSING PICTURES IN BATCHES ACCORDING TO PRESET RULES

Tencent Technology (Shenz...

1. An information processing method, applied to a terminal, the method comprising:receiving a first operation;
in response to the first operation, selecting a plurality of pictures from a local information base or an information base pulled and obtained by a background server, and displaying the selected plurality of pictures on a user interface of the terminal;
receiving to-be-added first target information comprises:
receiving first information which is non-text information selected from the local information base or the information base obtained by pulled and obtained by the background server; or, receiving a combination of the first information and second information, wherein the second information is text input by a user in real time,
receiving a second operation;
in response to the second operation, partitioning the to-be-added first target information into a plurality of items of second target information, and overlaying the plurality of items of second target information on the plurality of pictures simultaneously according to a preset rule, wherein the preset rule being configured to represent an arrangement rule and/or attribute of the plurality of pictures and the plurality of items of second target information overlaid on the plurality of pictures; and
displaying the plurality of pictures, with the plurality of items of second target information being displayed as multiple partial information split on the plurality of pictures.

US Pat. No. 10,460,483

TOOL FOR CREATING AND EDITING ARCS

Adobe Inc., San Jose, CA...

1. In a digital media environment to facilitate digital illustration creation using a computing device, a method comprising:receiving, by the computing device, a first user input specifying a drawing path in a drawing canvas;
displaying, by the computing device, the drawing path in the drawing canvas as a plurality of segments, the plurality of segments including an arc segment;
receiving, by the computing device, a second user input via the drawing canvas to resize the displayed drawing path;
resizing, by the computing device responsive to the second user input, the plurality of segments of the drawing path proportionally, the resizing including scaling the arc segment based on arc radius and arc length; and
displaying, by the computing device, the resized plurality of segments of the drawing path in the drawing canvas.

US Pat. No. 10,460,480

RECONSTRUCTING PET IMAGE

Shenyang Neusoft Medical ...

1. A method of reconstructing a Positron Emission Computed Tomography (PET) image, the method comprising:for each of coincidence events comprising at least one true coincidence event and at least one scattering coincidence event,
determining an emission path of the coincidence event according to photon information of the coincidence event, wherein the photon information of the coincidence event comprises time data, position data, and angle data of each of two photons involved in the coincidence event;
determining an annihilation position of the coincidence event according to the emission path of the coincidence event and the time data of each of the two photons involved in the coincidence event; and
reconstructing the PET image according to the annihilation position, the emission path and the photon information of each of the coincidence events.

US Pat. No. 10,460,478

SYSTEM COMPRISING PROVIDING MEANS FOR PROVIDING DATA TO A USER

1. A system for emitting light, comprisinga computer for receiving data, electing one or more parameters associated with the data, and assessing at least one characteristic of the one or more parameters; and
a lighting system connected to the computer and comprising one or more light sources, the lighting system configured to emit light of different characteristics;
wherein the computer determines a characteristic of the light based on an assessed result on the characteristic of the one or more parameters and controls the lighting system to operate in a mood lighting mode where the lighting system emits the light with the determined characteristic based on the assessed result on the characteristic of the one or more parameters,
wherein the computer controls the lighting system to emit colorless light to a location in a standard mode when the mood lighting mode is deactivated,
wherein at least one of the one or more parameters is divided into at least one sub-parameter, the at least one sub-parameter defining an additional condition to the at least one of the one or more parameters, the additional condition being related to at least one of a region, employee, office or timeframe, and
wherein the characteristic of the light is changed depending on an assessed result on a characteristic of the at least one sub-parameter.

US Pat. No. 10,460,477

SYSTEM AND METHOD FOR INTERACTIVELY VISUALIZING RULES AND EXCEPTIONS

TATA CONSULTANCY SERVICES...

1. A method for visualizing a rule and one or more exceptions for the rule, wherein the rule and the one or more exceptions are derived from a data set, and wherein the method comprises:receiving, by a processor, the rule, the one or more exceptions, and a plurality of data attributes associated with the rule and the one or more exceptions, wherein the plurality of data-attributes comprises a list of antecedents, a list of consequents, a rule syntax, an exception syntax, a support associated with the rule, a confidence associated with the rule, a support associated with each exception of the one or more exceptions, a lift, and a confidence associated with each exception of the one or more exceptions, wherein the lift corresponds to a ratio of the confidence and the support of the consequent, wherein the rules with lift differ significantly from unit lift is considered unexpected than those with near unit lift, and wherein the support associated with the rule, the confidence associated with the rule, the support associated with each exception, and the confidence associated with each exception are statistics associated with the rule and each exception respectively; and
visualizing, by the processor, the rule, and the one or more exceptions by:
representing the rule and the one or more exceptions with a first graphical element and a plurality of second graphical elements respectively, wherein the plurality of second graphical elements are represented within the first graphical element, and wherein the first graphical element and the plurality of second graphical elements have a plurality of visual attributes comprising a shape, a size, a transparency, a color opacity and a color;
mapping, by the processor, the plurality of data-attributes with the plurality of visual attributes, wherein the color opacity of the first graphical element and the plurality of second graphical elements is mapped with the confidence associated with the rule and the confidence associated with each exception of the one or more exceptions, wherein the plurality of data-attributes are categorized as nominal and quantitative, wherein if the data-attribute is in nominal category, then the data-attribute is represented by visual attribute of color, shape and texture, wherein if the data-attribute is in quantitative category, then the data-attribute is represented by visual attribute of length, position, area, angle, and volume;
computing, by the processor, positioning of the first graphical element and the plurality of second graphical elements, wherein the size of the first graphical element and the plurality of second graphical elements are proportional to the support associated with the rule and the support associated with each exception of the one or more exceptions;
generating visualization of the rules and the support associated with each exception of the one or more exceptions based on the computed positioning, wherein the visualization generated is used for developing rule hierarchies and updating the visualization based on user interaction; and
connecting at least one section of a second graphical element with at least one section of other second graphical element by an edge, wherein the at least one section of the second graphical element and the at least one section of the other second graphical element is connected based on having similar antecedents, and wherein a width of the edge represents a degree of overlap of the antecedents,
wherein the one or more exceptions associated with the rules are represented using visual encoding that is used for visualizing the rules, and the visual encoding representing the exceptions are contained within the visual encoding representing the rules.

US Pat. No. 10,460,471

CAMERA POSE ESTIMATING METHOD AND SYSTEM

KABUSHIKI KAISHA TOSHIBA,...

1. A camera pose estimation method for determining the translation and rotation between a first camera pose and a second camera pose,the method comprising:
extracting features from a first image captured at the first pose and a second image captured at the second pose, the extracted features comprising location, scale information and a descriptor, the descriptor comprising information that allows a feature from the first image to be matched with a feature from the second image;
matching features between the first image and the second image to produce matched features;
determining a depth ratio of matched features from the scale information, wherein the depth ratio is the ratio of the depth of a matched feature from the first pose to the depth of the matched feature from the second pose;
selecting n matched features, where at least one of the matched features is selected with both the depth ratio and location information; and
calculating the translation and rotation between the first camera pose and the second camera pose using the selected matched features with depth ratio derived from the scale information.

US Pat. No. 10,460,467

OBJECT RECOGNITION PROCESSING APPARATUS, OBJECT RECOGNITION PROCESSING METHOD, AND AUTONOMOUS DRIVING SYSTEM

Mitsubishi Electric Corpo...

1. An object recognition processing apparatus comprising:a processor for executing a program; and
a storage device in which the program is stored, wherein the processor executes the program to:
receive a first detection information signal from a first object detection unit and a second detection information signal from a second object detection unit that is different from the first object detection unit;
determine whether or not both the first detection information signal and the second detection information signal have object identification information;
determine whether first object identification information in the first detection information signal is different from second object identification information in the second detection information signal if both the first detection information signal and the second detection information signal have object identification information;
based on the first object identification information being determined to not be different from the second object identification information, set an object motion difference threshold to a first value;
based on one of the first detection information signal and the second detection information signal having object identification information, or none of the first detection information signal and the second detection information signal having object identification information, set the object motion difference threshold to a second value that is less than the first value;
determine whether a difference between first position or speed information of the first detection information signal and second position or speed information of the second detection information signal is equal to or less than the object motion difference threshold; and
based on the difference between the first position or speed information and the second position or speed information being determined to be equal to or less than the object motion difference threshold:
fuse the first and second detection information signals into one fused signal for a same object; and
recognize the same object existing around the vehicle on the basis of the fused signal for the same object.

US Pat. No. 10,460,466

LINE-OF-SIGHT MEASUREMENT SYSTEM, LINE-OF-SIGHT MEASUREMENT METHOD AND PROGRAM THEREOF

TOPPAN PRINTING CO., LTD....

1. A system for measuring a line-of-sight of an observer, comprising:a user imaging sensor which is wearable by an observer of an object in a display space and captures a field view image in front of the observer;
a user measurement sensor, which is wearable by the observer and obtains line-of-sight measurement data indicating a line-of-sight direction of the observer relative to a coordinate system of the field view image; and
processing circuitry configured to obtain, from the line-of-sight measurement data, a gaze point of the observer based on a coordinate position in a coordinate system of the user measurement sensor at which 3D shape data of the display space, including the object, intersects with a vector, corresponding to the line-of-sight direction of the observer, generated based on correlating the coordinate system of the field view image and the coordinate system of the user measurement sensor,
wherein the correlating the coordinate system of the field view image and the coordinate system of the user measurement sensor includes applying coordinate conversion of a line-of-sight direction vector from a camera coordinate system to a global coordinate system with a camera coordinate conversion matrix, where a coordinate value in the camera coordinate system represented by (x, y, z) is rotated to conform to the global coordinate system represented by (x?, y?, z?).

US Pat. No. 10,460,464

DEVICE, METHOD, AND MEDIUM FOR PACKING RECOMMENDATIONS BASED ON CONTAINER VOLUME AND CONTEXTUAL INFORMATION

Amazon Technologies, Inc....

1. A device, comprising:an image capture device for capturing image data;
a display for displaying content; and
one or more computer hardware processors in communication with the image capture device and the display, the one or more computer hardware processors configured to at least:
recognize, based on application of one or more computer-based object recognition techniques to image data obtained via the image capture device, a container to be packed with one or more items;
identify, based on computer-based analysis of the image data, context data for a packing operation associated with the container;
based at least in part on automated analysis of the obtained image data and the identified context data,
determine an item packing recommendation for the container, wherein the automated analysis of the obtained image data comprises computer-based analysis of the obtained image data; and
instruct presentation of the item packing recommendation via the display.