US Pat. No. 10,192,858

LIGHT EMITTING STRUCTURE

Apple Inc., Cupertino, C...

1. A display comprising:a substrate;
a first bottom electrode line on the substrate;
a passivation layer over the display substrate;
a first plurality of vertical semiconductor-based light emitting diodes (LEDs) coupled with the first bottom electrode line and embedded within the passivation layer such that the passivation layer laterally surrounds a quantum well within each of the first plurality of vertical semiconductor-based LEDs;
a second plurality of vertical semiconductor-based LEDs embedded within the passivation layer such that the passivation layer laterally surrounds a quantum well within each of the second plurality of vertical semiconductor-based LEDs, wherein the second plurality of vertical semiconductor-based LEDs and the first plurality of vertical semiconductor-based LEDs share a same vertical semiconductor-based LED; and
a first top electrode line in electrical contact with the second plurality of vertical semiconductor-based LEDs.

US Pat. No. 10,192,854

LIGHT EMITTER COMPONENTS AND RELATED METHODS

Cree, Inc., Durham, NC (...

1. A light emitter component comprising:a submount comprising ceramic;
a reflective material disposed on portions of the submount, wherein the reflective material comprises a reflective surface; and
a plurality of light emitter chips disposed on the reflective surface of the reflective material and in contact with one or more electrical traces on the submount, wherein the reflective surface extends below each of the plurality of light emitter chips and between each of the one or more electrical traces, wherein each light emitter chip comprises a sapphire substrate, an epi area disposed over the sapphire substrate, and first and second electrical contacts that face the reflective surface;
wherein a ratio of a combined epi area of the plurality of light emitter chips to a surface area of the reflective surface not covered by the plurality of light emitter chips is at least 0.4 or more, and
wherein a ratio of a combined planar surface area of the plurality of light emitter chips to a planar surface area of the reflective surface not covered by the plurality of light emitter chips is at least approximately 0.25 or more.

US Pat. No. 10,192,851

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device comprising:(a) providing a wiring substrate including:
an upper surface,
a lower surface opposite to the upper surface,
a first device region provided on the lower surface,
a second device region provided on the lower surface and also provided next to the first device region,
a dicing region provided between the first device region and the second device region
a peripheral region provided on the lower surface and also provided around the first device region, the second device region and the dicing region,
a target mark provided in the peripheral region and also not located on an extended line of the dicing region,
a plurality of first bump lands provided in a matrix, in the first device region,
a plurality of second bump lands provided in a matrix, in the second device region, and
a first insulating film formed over the lower surface such that the first insulating film exposes the plurality of first bump lands and the plurality of second bump lands,
wherein the plurality of first bump lands has a first outermost peripheral land row arranged on the outermost peripheral row of the plurality of first bump lands, which is closest to the dicing region,
wherein the plurality of second bump lands has a second outermost peripheral land row arranged on the outermost peripheral row of the plurality of second bump lands, which is closest to the dicing region,
wherein the target mark is comprised of a first pattern formed between the extended line of the dicing region and an extended line of the first outermost peripheral land row in plan view, and a second pattern formed between the extended line of the dicing region and an extended line of the second outermost peripheral land row in plan view, the first pattern and the second pattern being spaced apart from each other,
wherein a first feeder line and a second feeder line are connected to the first pattern and the second pattern, respectively,
wherein each of the first feeder line and the second feeder line has a first portion exposed from the first insulating film, and a second portion covered with the first insulating film,
wherein the first pattern, the second pattern, the first feeder line and the second feeder line are comprised of a conductive member, and
wherein a first plating film is formed on a surface of each of the first pattern exposed from the first insulating film and the second pattern exposed from the first insulating film by using the first feeder line and the second feeder line, respectively;
(b) after (a), mounting a first semiconductor chip and a second semiconductor chip on the upper surface of the wiring substrate;
(c) after (b), sealing the first semiconductor chip and the second semiconductor chip with resin;
(d) after (c), forming a plurality of first external terminals and a plurality of second external terminals on the plurality of first bump lands and the plurality of second bump lands, respectively; and
(e) after (d), identifying the dicing region on the basis of the target mark, and cutting the wiring substrate along the dicing region,
wherein, in (e), the dicing region of the wiring substrate and a first region of the peripheral region of the wiring substrate are cut off by using a rotating cutting blade,
wherein the first region is located between the first pattern and the second pattern in plan view, and
wherein the first pattern, the second pattern, the first feeder line and the second feeder line are not formed in the first region.

US Pat. No. 10,192,850

BONDING PROCESS WITH INHIBITED OXIDE FORMATION

SiTime Corporation, Sant...

1. A method of forming a wafer-to-wafer bond, the method comprising:forming, on a first wafer, a first contact from a first conductive material subject to surface oxidation when exposed to air;
disposing a layer of oxide-inhibiting material over a bonding surface of the first contact;
forming, on a second wafer, a second contact from a second conductive material that, upon heating while in physical contact with the first conductive material, will form a eutectic bond;
positioning the first and second wafers relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material; and
after positioning the first and second wafers relative to one another, heating the first and second contacts and the layer of oxide-inhibiting material to a first temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond;
the method further comprising, prior to positioning the first and second wafers relative to one another such that the bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material, heating the first contact and the layer of oxide-inhibiting material to a second temperature that alloys the oxide-inhibiting material with the first conductive material.

US Pat. No. 10,192,849

SEMICONDUCTOR MODULES WITH SEMICONDUCTOR DIES BONDED TO A METAL FOIL

Infineon Technologies AG,...

1. A method of manufacturing semiconductor modules, the method comprising:providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer;
attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil;
encasing the semiconductor dies attached to the metal foil in an electrically insulating material;
structuring the metal layer and the metal foil after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer; and
dividing the electrically insulating material along the surface regions devoid of the metal foil and the metal layer to form individual modules,
wherein structuring the metal layer and the metal foil comprises:
masking the metal layer so that regions of the metal layer are exposed;
removing the exposed regions of the metal layer so that regions of the metal foil are exposed; and
removing the exposed regions of the metal foil using the remaining metal layer as a mask.

US Pat. No. 10,192,848

PACKAGE ASSEMBLY

Taiwan Semiconductor Manu...

1. A package assembly, comprising:a bump on a first substrate;
a molding compound on the first substrate and contacting sidewalls of the bump;
a no-flow underfill layer on a conductive region of a second substrate, wherein the no-flow underfill layer and the conductive region contact the bump; and
a mask layer arranged on the second substrate and laterally surrounding the no-flow underfill layer, wherein the no-flow underfill layer contacts the second substrate between the conductive region and the mask layer, wherein the no-flow underfill layer physically contacts sidewalls and an upper surface of the mask layer facing the first substrate, and wherein the upper surface of the mask layer continuously extends from directly below the no-flow underfill layer to a non-zero distance laterally past an outermost edge of the no-flow underfill layer.

US Pat. No. 10,192,846

METHOD OF INSERTING AN ELECTRONIC COMPONENT INTO A SLOT IN A CIRCUIT BOARD

Infineon Technologies Aus...

1. A method, comprising:inserting an electronic component comprising a power semiconductor device embedded in a dielectric core layer into a slot in a side face of a circuit board, wherein the inserting the electronic component causes one or more electrically conductive contacts on one or more surfaces of the electronic component to electrically couple with one or more corresponding electrical contacts arranged on one or more surfaces of the slot,
exerting pressure on the contact of the slot to electrically couple the one or more electrical contacts arranged on one or more surfaces of the slot to the one or more electrically conductive contacts of the electronic component, wherein the exerting the pressure comprises exerting pressure on a surface of the circuit board defining the slot by applying one or more fixation elements.

US Pat. No. 10,192,845

ELECTRONIC DEVICE AND MOUNTING STRUCTURE OF THE SAME

ROHM CO., LTD., Kyoto (J...

1. An electronic device comprising:a first electronic element; a second electronic element spaced apart from and electrically connected to the first electronic element; a main electrode on which the first electronic element and the second electronic element are disposed;
an insulating joining part directly interposed between the first electronic element and the main electrode;
a plurality of insulating spacers mixed in the joining part and each directly contacting the main electrode and the first electronic element; a joining layer interposed between the second electronic element and the main electrode, the joining layer being made of an electroconductive material comprising silver (Ag); and; and
a sealing resin covering the first electronic element, the second electronic element and the main electrode.

US Pat. No. 10,192,844

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip, a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant, the first interconnection member and the second interconnection member including, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip: and
a component package including a wiring substrate disposed above the second interconnection member and connected to the second interconnection member through the first connection terminals and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate,
wherein the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer.

US Pat. No. 10,192,840

BALL PAD WITH A PLURALITY OF LOBES

Intel Corporation, Santa...

1. An electronic assembly comprising:a substrate that includes a conductive trace embedded within the substrate, wherein the conductive trace is exposed to an upper exterior surface of the substrate; and
a ball pad mounted on the upper exterior surface of the substrate, wherein the ball pad engages the conductive trace and includes a plurality of lobes projecting distally from a center of the ball pad, wherein each lobe in the plurality of lobes includes two sides that form an edge with the two sides extending from the edge at an acute angle, wherein one of the two sides in each lobe forms a planar surface with a side of another lobe and the other of the two sides forms a separate planar surface with a side of a different lobe.

US Pat. No. 10,192,839

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

International Business Ma...

1. A method of fabricating a pillar-type connection, the method comprising:forming a first conductive layer;
forming a second conductive layer on the first conductive layer to define a conductive pillar that includes a top surface defining a recess aligned with a hollow core of the first conductive layer; and
forming a conductive via that terminates at a top surface of the first conductive layer.

US Pat. No. 10,192,838

FABRICATION METHOD OF PACKAGING SUBSTRATE

Siliconware Precision Ind...

1. A fabrication method of a packaging substrate, comprising:providing a base body having at least a conductive pad on a surface thereof and a dielectric layer formed on the surface of the base body and at least a first opening formed in the dielectric layer for exposing the conductive pad;
forming at least a second opening in the dielectric layer around a periphery of the first opening, wherein the second opening is spaced apart from the first opening, and the second opening is free from being located directly above the conductive pad;
after forming the second opening in the dielectric layer around the periphery of the first opening, forming a metal layer on the dielectric layer and the conductive pad, allowing the metal layer to extend to only a part of a sidewall of the second opening without covering an entire surface of the second opening; and
forming at least a solder bump on the metal layer.

US Pat. No. 10,192,837

MULTI-VIA REDISTRIBUTION LAYER FOR INTEGRATED CIRCUITS HAVING SOLDER BALLS

NXP B.V., San Jose, CA (...

1. An article of manufacture comprising an integrated circuit (IC), the IC comprising:a top metal conducting layer;
a passivation layer on top of the top metal conducting layer, wherein the passivation layer comprises openings to the top conducting layer;
a redistribution layer on top of the passivation layer, wherein material of the redistribution layer fills the openings in the passivation layer to form via structures electrically connecting the redistribution layer to the top metal conducting layer; and
a solder ball placed on top of the redistribution layer that has a footprint that spans a first plurality of the via structures of the redistribution layer such that electricity can flow vertically between the solder ball and the top metal conducting layer through the redistribution layer and the first plurality of the via structures,
wherein there is no under-bump metallization (UBM) layer under the solder ball other than the redistribution layer, and
wherein the solder ball is in direct contact with the redistribution layer, and the footprint of the solder ball is vertically aligned with the first plurality of the via structures over the top metal conducting layer.

US Pat. No. 10,192,835

SUBSTRATE DESIGNED TO PROVIDE EMI SHIELDING

Apple Inc., Cupertino, C...

1. A package comprising:a package substrate including a top surface and a bottom surface;
a die bonded to the package substrate top surface;
a plurality of ground pads at a periphery of the package substrate top surface;
a plurality of electrically conductive wire bonds on the plurality of ground pads such that more than one electrically conductive wire bond is bonded to a corresponding ground pad;
a molding compound that encapsulates the die and the electrically conductive wire bonds on the package substrate top surface, the molding compound including top and side surfaces, wherein a corresponding plurality of surfaces of the plurality of electrically conductive wire bonds are exposed at a side surface of the molding compound; and
an electrically conductive shield layer on the top and side surfaces of the molding compound, and in physical contact with the plurality of surfaces of the exposed electrically conductive wire bonds.

US Pat. No. 10,192,834

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

Siliconware Precision Ind...

1. A semiconductor package, comprising:a substrate;
a first semiconductor element disposed on the substrate and having a first conductive pad and a second conductive pad, wherein the second conductive pad is electrically connected to the first conductive pad by a first bonding wire and grounded to the substrate;
a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad, wherein the first semiconductor element is disposed between the conductive layer and the substrate, and the conductive layer is in direct contact with the first conductive pad and encapsulates the first conductive pad and a portion of the first bonding wire;
a second semiconductor element disposed on the conductive layer; and
an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.

US Pat. No. 10,192,833

INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES

Taiwan Semiconductor Manu...

1. An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising:a substrate body having opposed first and second surfaces;
a plurality of conductive layers disposed in a dielectric material on said substrate body, wherein a first one of said plurality of conductive layers includes a first lead and a second of said plurality of conductive layers includes a second lead, wherein said first lead is shielded from said second lead by a shield including portions of a first interposed conductive layer and a second interposed conductive layer of said plurality of conductive layers coupled by a via such that an entirety of a longitudinal width of each of the first interposed conductive layer and the second interposed conductive layer of the shield is contained within a boundary of a first coupling via and a second coupling via;
said first lead extending along a longitudinal direction of said interposer and said shield extending continuously along a transverse direction of said interposer, wherein said shield extends across at least a majority of a transverse width of said interposer between said first and second leads; and
wherein said plurality of conductive layers are formed of metal materials or semiconductor materials;wherein said shield forms a continuous member of said metal materials or semiconductor materials, and there is no dielectric path from said first lead to said second lead through said shield.

US Pat. No. 10,192,832

ALIGNMENT MARK STRUCTURE WITH DUMMY PATTERN

United Microelectronics C...

1. An alignment mark structure, comprising:a substrate;
an alignment mark disposed on the substrate;
dummy patterns disposed on the substrate and located adjacent to the alignment mark;
a first passivation layer covering a top surface of the dummy patterns; and
a second passivation layer covering the first passivation layer, wherein
a size of the dummy patterns is smaller than a size of the alignment mark,
a metal layer of the alignment mark and a metal layer of the dummy patterns are derived from the same metal layer, and
the second passivation layer directly contacts and covers entire top surface of the alignment mark, and the first passivation layer does not cover any of the top surface of the alignment mark.

US Pat. No. 10,192,829

LOW-TEMPERATURE DIFFUSION DOPING OF COPPER INTERCONNECTS INDEPENDENT OF SEED LAYER COMPOSITION

International Business Ma...

1. An interconnect structure, comprising:at least one trench patterned in a dielectric material;
a barrier layer lining the trench;
a metal liner on the barrier layer;
a copper (Cu) interconnect doping layer on the metal liner; and
a Cu interconnect in the trench such that the Cu interconnect doping layer is present between the metal liner and the Cu interconnect, wherein the Cu interconnect doping layer fully surrounds the Cu interconnect whereby the Cu interconnect doping layer is continuous along all bottom, sidewall and top surfaces of the Cu interconnect.

US Pat. No. 10,192,826

CONDUCTIVE LAYOUT STRUCTURE INCLUDING HIGH RESISTIVE LAYER

UNITED MICROELECTRONICS C...

1. A layout structure comprising a conductive structure comprising:a dielectric layer formed on a substrate; and
the conductive structure formed in the dielectric layer, the conductive structure further comprising:
a barrier layer;
a metal layer formed within the barrier layer;
a first nucleation layer sandwiched in between the barrier layer and the metal layer; and
a high resistive layer sandwiched in between the first nucleation layer and the metal layer.

US Pat. No. 10,192,824

EDGE STRUCTURE FOR MULTIPLE LAYERS OF DEVICES, AND METHOD FOR FABRICATING THE SAME

MACRONIX International Co...

1. An edge structure for multiple layers of devices, wherein the multiple layers of devices comprises a plurality of unit layers being stacked, comprising:a first stair structure at a first direction of the multiple layers of devices where contacts for the devices are to be formed, including first edge portions of the unit layers at the first direction, wherein borders of the first edge portions gradually retreat with increase of a level height thereof, and an elevation angle from the border of the first edge portion of the bottom unit layer to the border of the first edge portion of the top unit layer is a first angle (?1); and
a second stair structure, including second edge portions of the unit layers at a second direction, wherein variation of border position of the second edge portion with increase of the level height is irregular, and an elevation angle from the border of the second edge portion of the bottom unit layer to the border of the second edge portion of the top unit layer is a second angle (?2) that is larger than the first angle ?1,
wherein a number of the unit layers is 16 or more,
the first direction is orthogonal with the second direction, and
the second stair structure has a first part and a second part above the first part, wherein
in the first part, variation of border position of the second edge portion with increase of the level height is regular,
in the second part, borders of the second edge portions of a corresponding part of the unit layers are aligned with each other, and
a height of the second part is over a half of a total height of the second stair structure.

US Pat. No. 10,192,823

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including a first region and a second region;
a transistor comprising a gate electrode and first and second dopant regions that are disposed on the first region of the substrate;
first, second, and third contact plugs electrically connected to the first dopant region, the second dopant region, and the gate electrode, respectively; and
a fuse structure disposed on the second region of the substrate, the fuse structure comprising: first and second fuse contact plugs having a same height as the first and second contact plugs; and a connection pattern having a same height as the third contact plug,
wherein the connection pattern is connected between the first and second fuse contact plugs,
wherein top surfaces of the first and second contact plugs are substantially coplanar with a top surface of the third contact plug, and
wherein the top surface of the third contact plug is substantially coplanar with a top surface of the connection pattern.

US Pat. No. 10,192,818

ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE

NSK LTD., Tokyo (JP)

1. An electronic part mounting heat-dissipating substrate which comprises: a conductor plate which is formed on lead frames of wiring pattern shapes to mount an electronic part; and an insulating member which is provided between said lead frames of said wiring pattern shapes on said conductor plate; in which a plate surface of a part arrangement surface of said conductor plate and a plate surface of a part arrangement surface-side of said insulating member are formed in an identical vertical plane, and a plate surface of a back surface of said part arrangement surface of said conductor plate and a plate surface of a back surface of said part arrangement surface-side of said insulating member are formed in an identical vertical plane,wherein said lead frames of said wiring pattern shapes have different thicknesses of at least two types or more, a thickness of the lead frames being measured in a direction parallel to the mounting direction of the electronic part, and a thick lead frame is used for a large current signal and a thin lead frame is used for a small current signal,
wherein said plate surface of said back surface of said part arrangement surface of said lead frames of said wiring pattern shapes and said plate surface of said back surface of said part arrangement surface-side of said insulating member are formed in an identical vertical plane to meet said plate surface of said back surface of said part arrangement surface of a thickest lead frame among said lead frames,
wherein said lead frames having different thicknesses are configured so that different wiring patterns are formed for said respective different thicknesses so as not to mutually cross and overlap and said lead frames having different thicknesses form an electronic circuit by mounting said electronic part,
wherein wiring widths of thin lead frames are smaller than wiring widths of thick lead frames, and said thin lead frames are arranged between said thick lead frames when said electronic part arrangement surface is seen from an upper side, and
wherein both side surfaces of said lead frames are formed with a plane vertical to said plate surface from a top surface of said electronic part arrangement surface to a back surface thereof.

US Pat. No. 10,192,817

ELECTROSTATIC DISCHARGE PROTECTION ELEMENT

REALTEK SEMICONDUCTOR COR...

1. An electrostatic discharge (ESD) protection element of a semiconductor device, the ESD protection element leading out an electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge, comprising:an input/output (I/O) pad connected between the I/O terminal and the internal circuit;
a first conductor connected to the I/O pad;
a second conductor connected to a ground terminal; and
a gap structure disposed between the first conductor and the second conductor and configured to establish a path from the I/O pad to the first conductor, the second conductor and to the ground terminal for conducting the electrostatic discharge current;
wherein the first conductor, the second conductor and the gap structure are disposed in a same layer of the semiconductor device with a substantially same thickness.

US Pat. No. 10,192,815

WIRING BOARD AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring board comprising:a first insulating layer;
a first wiring layer formed on a lower surface of the first insulating layer;
a first through hole which penetrates the first insulating layer in a thickness direction of the first insulating layer;
a first via wiring comprising:
a filling portion formed to fill the first through hole and connected to the first wiring layer; and
a protruding portion protruding upward from an upper surface of the first insulating layer;
a second wiring layer comprising a land, wherein the land comprises:
an outer circumferential portion covering the upper surface of the first insulating layer; and
a central portion formed integrally with the outer circumferential portion to cover a side surface and an upper surface of the protruding portion and protruding upward from an upper surface of the outer circumferential portion,
a second insulating layer formed on the upper surface of the first insulating layer to cover the second wiring layer;
a second through hole which penetrates the second insulating layer in the thickness direction to expose a side surface and an upper surface of the central portion;
a second via wiring formed to fill the second through hole to cover the side surface and the upper surface of the central portion; and
a third wiring layer formed on an upper surface of the second insulating layer and connected to the second via wiring,
wherein
the filling portion comprises:
a first metal film covering an inner side surface of the first through hole, the first metal film including an upper end surface that is planar with the upper surface of the first insulating layer;
a second metal film covering the first metal film; and
a metal layer covering the second metal film,
the protruding portion comprises:
the metal layer protruding upward from the upper surface of the first insulating layer; and
the second metal film covering a side surface and an upper surface of the metal layer exposed from the upper surface of the first insulating layer, and
the first via wiring has a step at a boundary between the protruding portion and the filling portion, the step formed along the upper end surface of the first metal film and a side surface and an upper surface of the second metal film, the side surface and the upper surface of the second metal film being exposed from the first metal film.

US Pat. No. 10,192,812

POLYMER LAYER ON METAL CORE FOR PLURALITY OF BUMPS CONNECTED TO CONDUCTIVE PADS

Samsung Display Co., Ltd....

1. A semiconductor chip, comprising:a substrate;
one or more conductive pads disposed on the substrate; and
one or more bumps electrically connected to the one or more conductive pads,
wherein the one or more bumps comprise a metal core, a polymer layer disposed over side and upper surfaces of the metal core, and a conductive coating layer disposed over side and upper surfaces of the polymer layer and electrically connected to the one or more conductive pads.

US Pat. No. 10,192,811

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A power semiconductor device comprising:a metallic lead frame that includes a mounting surface and a dissipating surface opposite to the mounting surface, and including a P-potential electrode, intermediate potential electrodes, and an N-potential electrode that are electrically independent;
power semiconductor chips and a current detection resistor that are disposed on the mounting surface of the metallic lead frame via conductive joining members;
a wiring member that connects an electrode of one of the power semiconductor chips to a portion of the metallic lead frame; and
a resin that covers a portion of the mounting surface of the metallic lead frame, the power semiconductor chips, the current detection resistor and the wiring member,
wherein the P-potential electrode and the N-potential electrode are disposed on a centerline of the metallic lead frame, and
the metallic lead frame, the power semiconductor chips, the wiring member and the current detection resistor are disposed in symmetry with respect to the centerline.

US Pat. No. 10,192,810

UNDERFILL MATERIAL FLOW CONTROL FOR REDUCED DIE-TO-DIE SPACING IN SEMICONDUCTOR PACKAGES

Intel Corporation, Santa...

1. A semiconductor apparatus, comprising:first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies laterally adjacent to one another and separated by a spacing;
a barrier structure disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die; and
an underfill material layer in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die, wherein the underfill material layer is disposed on and over an uppermost surface of the barrier structure at a location of a highest point of the uppermost surface of the barrier structure above the common semiconductor package substrate but is not on a portion of the uppermost surface of the barrier structure underneath the first semiconductor die.

US Pat. No. 10,192,807

POWER SEMICONDUCTOR MODULE, FLOW PATH MEMBER, AND POWER-SEMICONDUCTOR-MODULE STRUCTURE

FUJI ELECTRIC CO., LTD., ...

1. A power semiconductor module comprising:a metal base plate including a first surface and a second surface opposite to the first surface;
a multi-layer substrate including a third surface and a fourth surface opposite to the third surface, the fourth surface being joined to the first surface;
a semiconductor element mounted on the third surface;
a resin case disposed on the first surface of the metal base plate, the resin case surrounding the multi-layer substrate and the semiconductor element; and
a cooling case including
a bottom wall,
a side wall formed around the bottom wall and having one end of the side wall being joined to the second surface of the metal base plate to form a space enclosed by the metal base plate, the bottom wall, and the side wall for circulating a coolant,
an inlet portion having an inlet opening for introducing the coolant to the cooling case and an outlet portion having an outlet opening for discharging the coolant from the cooling case, the inlet portion and the outlet portion being connected to either the bottom wall or the side wall and disposed along a peripheral edge of the second surface of the metal base plate,
a first flange disposed at an inlet opening side of the inlet portion and having a main surface opposite to the inlet portion, the main surface of the first flange being parallel to a first surface of the metal base plate, and
a second flange disposed at an outlet opening side of the outlet portion and having a main surface opposite to the outlet portion, the main surface of the second flange being parallel to the first surface.

US Pat. No. 10,192,806

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:an insulating substrate including a metal plate, an insulating resin plate laminated on the metal plate, and circuit plates laminated on the insulating resin plate and including one circuit plate having a circuit pattern and an adhering pattern, which are selectively formed on the insulating resin plate;
a semiconductor element fixed to the circuit pattern of the insulating substrate with a bonding material;
a wiring member having an end connected to the one circuit plate of the insulating substrate;
a housing accommodating the insulating substrate, the semiconductor element, and the wiring member; and
a sealing material sealing the insulating substrate, the semiconductor element, and the wiring member accommodated in the housing,
wherein the adhering pattern is an opening, in a plan view, disposed in the one circuit plate, and arranged between the semiconductor element fixed to the one circuit plate and the end of the wiring member fixed to the one circuit plate,
the sealing material bonds the insulating resin plate through the opening to increase a bond between the sealing material and the insulating resin plate, and
one of the circuit plates having the adhering pattern is bonded to the insulating resin plate by the sealing material through the opening as the adhering pattern.

US Pat. No. 10,192,804

BUMP-ON-TRACE PACKAGING STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a first package component;
a first metal trace and a second metal trace on a top surface of the first package component, the first metal trace having a first thickness with respect to the top surface of the first package component and the second metal trace having a second thickness with respect to the top surface of the first package component, the first thickness and the second thickness being substantially equal;
a dielectric mask layer covering a top surface of the first package component and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace in a cross sectional view, the dielectric mask layer not exposing the second metal trace in the cross sectional view, wherein a first side surface of the second metal trace forms a first interface with the dielectric mask layer in the cross sectional view, wherein a second side surface of the second metal trace opposite the first side surface forms a second interface with the dielectric mask layer in the cross sectional view, the first interface and the second interface each extending continuously from a topmost surface of the second metal trace to a bottommost surface of the second metal trace, and the dielectric mask layer has constantly sloped sidewall surfaces defining the opening, the dielectric mask layer being a photodefinable layer;
a second package component; and
an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, the solder bump being in contact with a top surface and a side surface of the first metal trace in the opening of the dielectric mask layer, the constantly sloped sidewall surfaces of the dielectric mask layer being in contact with the side surface of the first metal trace at a first point, the solder bump being in contact with the side surface of the first metal trace at a second point, the first point being higher than the second point, an entirety of the side surface of the first metal trace being perpendicular to the top surface of the first metal trace, the side surface of the first metal trace extending continuously from a topmost surface of the first metal trace to a bottommost surface of the first metal trace, a continuous portion of the side surface of the first metal trace extending continuously from the first point to the second point being not in contact with the dielectric mask layer and not in contact with the solder bump, the second point being above a bottommost surface of the first metal trace.

US Pat. No. 10,192,800

SEMICONDUCTOR DEVICE

ABB Schweiz AG, Baden (C...

1. A semiconductor device, comprising:two electrodes with opposite faces;
a semiconductor wafer sandwiched between the two electrodes;
an outer insulating ring attached to the two electrodes and surrounding the semiconductor wafer;
a middle insulating ring inside the outer insulating ring and surrounding the semiconductor wafer, whereby the middle insulating ring is made of a plastics material;
an inner insulating ring inside the middle insulating ring, whereby the inner insulating ring is made of ceramics and/or glass material;
wherein either the middle insulating ring or the inner insulating ring has a tongue and the other thereof has a groove such that the tongue fits into the groove for their rotational alignment and
wherein the middle insulating ring and the inner insulating ring have a radial opening for receiving a gate connection of the semiconductor device.

US Pat. No. 10,192,799

METHOD AND APPARATUS TO MODEL AND MONITOR TIME DEPENDENT DIELECTRIC BREAKDOWN IN MULTI-FIELD PLATE GALLIUM NITRIDE DEVICES

TEXAS INSTRUMENTS INCORPO...

13. A test method comprising:providing a first set of test structures TS0 through TSN for a gallium nitride (GaN) transistor that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSX of the first set of test structures comprising:
a GaN substrate,
a dielectric material overlying the GaN substrate,
a respective source contact abutting the GaN substrate,
a respective drain contact abutting the GaN substrate,
a respective gate overlying the substrate and lying between the source contact and the drain contact,
X respective field plates corresponding to X field plates of the N field plates of the GaN transistor that are nearest to the GaN substrate, and
a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate;
for each test structure TSX, the test method comprising:
applying a stress voltage to the drain contact of test structure TSX until a dielectric breakdown condition is detected; and
recording the time-to-failure of test structure TSX at the stress voltage.

US Pat. No. 10,192,798

INTEGRATED CIRCUIT DIE HAVING A SPLIT SOLDER PAD

EM Microelectronic-Marin ...

1. An electronic system, comprising:an integrated circuit die having:
at least two bond pads, and
a redistribution layer having:
at least one solder pad comprising a first and second portion being separated from each other to provide a separation space between the first and second portion and being configured to provide an electrical connection between each of the first and second portion by a solder ball disposed on the at least one solder pad, and to electrically isolate the first and second portion in an absence of the solder ball on the at least one solder pad, and
at least two redistribution wires, each connecting a different one of the first and second portion to a different one of the at least two bond pads, a second bond pad of the at least two bond pads being connected via a second redistribution wire of the at least two redistribution wires to a second portion of the first and second portion of the at least one solder pad being dedicated to testing the integrated circuit die; and
a grounded printed circuit board track,
wherein the solder ball is disposed between the at least one solder pad and the grounded printed circuit board track, and
wherein no redistribution wires traverse the separation space between the first and second portion.

US Pat. No. 10,192,797

SEMICONDUCTOR DEVICE AND ELECTRICAL CONTACT STRUCTURE THEREOF

Mitsubishi Electric Corpo...

1. A semiconductor device having a semiconductor element region, in which a semiconductor element is formed, and a terminal region provided in an outer peripheral part of said semiconductor element, the semiconductor device comprising:a plurality of electrodes formed on a surface of said semiconductor element;
a protective layer having opening parts respectively provided vertically over the semiconductor element at each electrode such that a portion of each said electrode is exposed at the opening parts, and vertically over and covering the other portions of said electrodes excluding said portion of said electrodes exposed at said opening part, said protective layer being insulative; and
a conductive layer formed so as to cover said protective layer and said opening parts and directly connected to said electrodes at said opening parts, wherein
said electrodes have substantially the same electric potential, and
said conductive layer is formed across said electrodes, wherein said protective layer has a plurality of said opening parts for each said electrode.

US Pat. No. 10,192,796

SEMICONDUCTOR DEVICE AND METHOD OF FORMING DUAL-SIDED INTERCONNECT STRUCTURES IN FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a substrate;
a vertical interconnect structure formed in contact with a first surface of the substrate, wherein the substrate includes an opening extending from a second surface of the substrate opposite the first surface of the substrate to the vertical interconnect structure;
a semiconductor die disposed over the first surface of the substrate;
an encapsulant deposited over the first surface of the substrate, a side surface of the substrate, and around the semiconductor die, including a surface of the encapsulant outside the substrate coplanar with the second surface of the substrate; and
a first interconnect structure formed over the encapsulant opposite the substrate and coupled to the semiconductor die.

US Pat. No. 10,192,795

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a power transistor that passes a current from a high-potential terminal to a low-potential terminal, the power transistor comprising a gate electrode insulated from a channel region of the power transistor by an insulating film; and
a temperature sensing diode that senses a variation in temperature due to heating of the power transistor,
wherein the low-potential terminal of the power transistor and a cathode of the temperature sensing diode are directly electrically connected to each other so as to have a same potential.

US Pat. No. 10,192,793

PATTERN FORMATION METHOD, IMPRINT DEVICE, AND COMPUTER-READABLE NON-VOLATILE STORAGE MEDIUM STORING DROP RECIPE ADJUSTMENT PROGRAM

Toshiba Memory Corporatio...

1. A pattern formation method comprising:forming a first imprint pattern for a prepared sample;
measuring residual film thickness distribution of the first imprint pattern;
calculating change rate of the residual film thickness of the first imprint pattern with respect to drop density of a resist material at the time of formation of the first imprint pattern;
forming a first etching pattern using the first imprint pattern as a mask;
measuring dimension distribution of the first etching pattern;
calculating a correction coefficient based on the residual film thickness distribution of the first imprint pattern and the dimension distribution of the first etching pattern;
correcting the residual film thickness of the first imprint pattern based on the correction coefficient to reduce a variation in size of the first etching pattern;
calculating a first drop density of an imprint material based on the change rate of the residual film thickness of the first imprint pattern with respect to drop density to obtain the corrected residual film thickness;
dropping the imprint material onto an etching material based on the first drop density;
pressing a template against the dropped imprint material to form the second imprint pattern with the corrected residual film thickness on the etching material;
etching the etching material using the second imprint pattern as a mask to form a second etching pattern;
determining whether dimension distribution of the second etching pattern falls within a specification;
calculating, when the dimension distribution of the second etching pattern does not fall within the specification, an additional residual film thickness to compensate for insufficient adjustment of the dimension of the second etching pattern; and
calculating a second drop density of the imprint material to obtain the additional residual film thickness.

US Pat. No. 10,192,790

SRAM DEVICES AND FABRICATION METHODS THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a static random-access memory (SRAM) device, comprising:providing a base substrate including a pull up (PU) transistor region and a pull down (PD) transistor region adjacent to the PU transistor region;
forming a gate dielectric layer on a portion of the base substrate in the PU transistor region and the PD transistor region;
forming a first work function (WF) layer using a P-type WF material on the gate dielectric layer;
removing a portion of the first WF layer formed in the PD transistor region;
forming a second WF layer using a P-type WF material on a remaining portion of the first WF layer in the PU transistor region and on the gate dielectric layer in the PD transistor region;
removing a portion of the second WF layer formed in the PD transistor region;
forming a third WF layer using an N-type WF material on a top surface and a sidewall surface of a remaining portion of the second WF layer in the PU transistor region, a sidewall surface of the remaining portion of the first WF layer in the PU transistor region, and the gate dielectric layer in the PD transistor region; and
forming a gate electrode layer on the third WF layer.

US Pat. No. 10,192,785

DEVICES AND METHODS RELATED TO FABRICATION OF SHIELDED MODULES

Skyworks Solutions, Inc.,...

1. A method for preparing a carrier assembly for processing of packaged modules, the method comprising:providing a plate having a first side and a second side, and defining a plurality of openings, such that each opening extends through the plate between the first side and the second side; and
implementing an adhesive layer on the first side of the plate, such that the adhesive layer defines a plurality of openings arranged to substantially match the openings of the plate, each opening of the adhesive layer dimensioned such that the adhesive layer is capable of providing an adhesive engagement between a perimeter portion of an underside of a package and a perimeter portion about the corresponding opening of the adhesive layer, and such that the underside of the package not in engagement with the adhesive layer is exposed through the respective opening on the second side of the plate.

US Pat. No. 10,192,783

GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a gate electrode above a substrate, the gate electrode having a bottom surface, a first portion of the gate electrode bottom surface over a single crystalline region of the substrate and a second portion of the gate electrode bottom surface over a trench isolation layer of the substrate;
a source region or drain region in the single crystalline region of the substrate at a side of the gate electrode;
a dielectric sidewall spacer laterally adjacent the side of the gate electrode;
a gate etch stop layer over the gate electrode;
a trench contact structure on the source region or drain region, laterally adjacent the dielectric sidewall spacer; and
a single conductive via structure over and in contact with the trench contact structure, over the dielectric sidewall spacer, and over and in direct contact with the gate electrode, the conductive via structure in an opening in the gate etch stop layer, the opening exposing a portion of but not all of the gate electrode.

US Pat. No. 10,192,781

INTERCONNECT STRUCTURES INCORPORATING AIR GAP SPACERS

International Business Ma...

1. A process for manufacturing a dual damascene article of manufacture comprising a trench and a conductive metal column, said trench and said conductive metal column extending down into and contiguous with a via, said trench and said conductive metal column and said via having a common axis, wherein said trench and said via further comprise a sidewall air gap adjacent the side walls of said trench, said via, and said conductive metal column, said sidewall air-gap extending down to said via to a depth below a line fixed by the bottom of said trench, and continues downward in said via for a distance of from about 1 Angstrom below said line to the full depth of said via, said air gap being on opposite sides of said trench and said via, said process comprising forming said trench and said via of said dual damascene article of manufacture, coating the side wall of said trench and the side wall of said via with a dielectric material said dielectric material being on opposite sides of said trench and said via, damaging said dielectric material to form a damaged dielectric material on said side wall of said trench and said side wall of said via, metallizing said trench and said via having said damaged dielectric material to form a conductive metal column in said trench and a conductive metal column in said via and separately forming a metallization liner material in said trench and said via whereby said metallization liner is on opposite sides of said conductive metal column and contiguous with and interposed between said conductive metal column and said dielectric material, and removing said damaged dielectric material to form a sidewall air-gap adjacent said side wall, wherein said air gap is contiguous with said metallization liner and said metallization liner is contiguous with said conductive metal column, and further comprising providing a perforated pinched off cap operatively associated with said article, said perforated pinched off cap comprising a first cap layer patterned with a patterning layer that defines a narrower gap or narrower gaps extending from the top surface of said first cap layer to the bottom surface of said first cap layer, with said narrower gap or narrower gaps extending through said bottom surface of said first cap layer and being positioned over and projecting into said sidewall air-gap, and sealing only said narrower gap or narrower gaps, and further providing a second non-perforated cap layer operatively associated with and extending over said top surface of said first cap layer.

US Pat. No. 10,192,775

METHODS FOR GAPFILL IN HIGH ASPECT RATIO STRUCTURES

APPLIED MATERIALS, INC., ...

1. A processing method comprising:providing a substrate surface having an opening formed by at least one feature, the at least one feature, the at least one feature extending a depth from the substrate surface to a bottom surface, the at least one feature having a width defined by a first sidewall and a second sidewall;
forming a first quantity of a film on the substrate surface and the first sidewall, second sidewall and bottom surface of the at least one feature in a first deposition sequence, the first quantity of the film having a seam located within the width of the at least one feature wherein a bottom of the seam being at a first distance from the bottom surface of the at least one feature; and
reducing a height of the first quantity of the film to less than the first distance to remove at least some of the first quantity of the film and to completely remove the seam.

US Pat. No. 10,192,774

TEMPERATURE CONTROL DEVICE FOR PROCESSING TARGET OBJECT AND METHOD OF SELECTIVELY ETCHING NITRIDE FILM FROM MULTILAYER FILM

TOKYO ELECTRON LIMITED, ...

6. A method of selectively etching a nitride film from a processing target object, which has a multilayer film in which an oxide film and the nitride film are alternately stacked on top of each other, by using a temperature control device comprising a moving stage allowed to be heated and configured to mount a processing target object on a top surface thereof; a cooling body allowed to be cooled and fixed at a position under the moving stage; a shaft, having one end connected to the moving stage; the other end positioned under the cooling body; a first flange provided at the other end; and a second flange provided between the first flange and the cooling body, extended between the one end and the other end; a driving plate, provided between the first flange and the second flange, having a top surface facing the second flange and a bottom surface opposite to the top surface; an elastic body provided between the bottom surface of the driving plate and the first flange; and a driving unit configured to move the driving plate up and down, the method comprising:placing the processing target object on the top surface of the moving stage;
bringing the moving stage into contact with the cooling body by moving the driving plate downwards;
adjusting a contact thermal resistance between the moving stage and the cooling body by adjusting an amount of a downward movement of the driving plate;
etching the nitride film selectively from the multilayer film by plasma of a processing gas containing fluorine and hydrogen after the bringing of the moving stage into contact with the cooling body;
spacing the moving stage apart from the cooling body by moving the driving plate upwards after the etching of the nitride film; and
removing a reaction product, which is generated in the etching of the nitride film, by heating the moving stage after the spacing of the moving stage apart from the cooling body.

US Pat. No. 10,192,772

SUBSTRATE TABLE AND LITHOGRAPHIC APPARATUS

ASML Netherlands B.V., V...

1. A substrate table to support a substrate, the substrate table comprising:a main body;
burls extending from the main body and having first upper ends, the first upper ends defining a support surface to support the substrate; and
support pins having second upper ends, the support pins being movable between a retracted position, in which the second upper ends are arranged below the support surface, and an extended position, in which the second upper ends extend above the support surface,
wherein at least some of the support pins are arranged to support the substrate in the extended position,
wherein the support pins are arranged to be switched to a first stiffness mode and a second stiffness mode,
wherein, in the first stiffness mode, the at least some of the support pins have a first stiffness in a direction parallel to the support surface,
wherein, in the second stiffness mode, the at least some of the support pins have a second stiffness in the direction parallel to the support surface,
wherein the first stiffness is different from the second stiffness.

US Pat. No. 10,192,771

SUBSTRATE HOLDING/ROTATING DEVICE, SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME, AND SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate holding/rotating device comprising:a rotary table;
a rotation driving unit that rotates the rotary table around a rotational axis aligned with a vertical direction; and
a plurality of movable pins that supports a substrate horizontally, each of the movable pins having a support portion movable between an open position that is far apart from the rotational axis and a hold position that has approached the rotational axis, the plurality of movable pins being arranged to rotate around the rotational axis together with the rotary table,
the plurality of movable pins including a first movable pin group including at least three movable pins, and a second movable pin group including at least three movable pins other than the movable pins belonging to the first movable pin group,
the substrate holding/rotating device further comprising:
an urging unit that urges the support portion of each of the movable pins to one of the open position and the hold position;
first driving magnets, mounted in correspondence to the respective movable pins of the first movable pin group, having magnetic pole directions orthogonal to the rotational axis and mutually equal with respect to the rotational axis;
second driving magnets, mounted in correspondence to the respective movable pins of the second movable pin group, having magnetic pole directions orthogonal to the rotational axis and opposite those of the first driving magnets with respect to the rotational axis;
a first moving magnet, arranged in a non-rotating state, having a magnetic pole direction such as to apply a repulsive force or an attractive force to the first driving magnets along directions orthogonal to the rotational axis, and, by the repulsive force or the attractive force, urging the support portions of the first movable pin group to the other of the open position and the hold position;
a second moving magnet, arranged in a non-rotating state, having a magnetic pole direction such as to apply a repulsive force or an attractive force to the second driving magnets along directions orthogonal to the rotational axis, and, by the repulsive force or the attractive force, urging the support portions of the second movable pin group to the other of the open position and the hold position;
a first relative movement unit that makes the first moving magnet and the rotary table move relatively between a first position, at which the first moving magnet applies the repulsive force or the attractive force to the first driving magnets, and a second position, at which the first moving magnet does not apply the repulsive force or the attractive force to the first driving magnets; and
a second relative movement unit that makes the second moving magnet and the rotary table move relatively between a third position, at which the second moving magnet applies the repulsive force or the attractive force to the second driving magnets, and a fourth position, at which the second moving magnet does not apply the repulsive force or the attractive force to the second driving magnets, independently of the relative movement of the first moving magnet and the rotary table.

US Pat. No. 10,192,770

SPRING-LOADED PINS FOR SUSCEPTOR ASSEMBLY AND PROCESSING METHODS USING SAME

Applied Materials, Inc., ...

1. A susceptor assembly, comprising:a susceptor having a susceptor body and a top surface with at least one recess therein sized to enclose a wafer during processing, each recess having a bottom surface with at least three flared openings; and
at least three lift pins positioned within each recess, each lift pin positioned within one of the at least three flared openings in the bottom surface of the recess, each lift pin comprising a sleeve having an elongate body with a flared top end, bottom, sides and an elongate axis, the sleeve movable within the recess along the elongate axis so that the flared top end of the sleeve can extend above the bottom surface of the recess, a spring within the elongate body of the sleeve adjacent the bottom of the sleeve and a pin positioned within the elongate sleeve in contact with the spring, the pin having a flared top portion and movable along the elongate axis of the sleeve so that a top surface of the pin can extend above the flared top end of the sleeve.

US Pat. No. 10,192,769

THERMOSETTING ADHESIVE SHEET AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

DEXERIALS CORPORATION, T...

1. A thermosetting adhesive sheet to be applied to a grinding-side surface of a semiconductor wafer when dicing the semiconductor wafer comprising:a polymer containing an elastomer;
a (meth)acrylate containing more than 95 wt % of a polyfunctional (meth)acrylate with respect to total (meth)acrylate content;
an organic peroxide having a one-minute half-life temperature of 130° C. or lower; and
a transparent filler,
wherein the transparent filler is contained at 50 to 150 pts. mass with respect to 25 pts. mass of the polymer.

US Pat. No. 10,192,767

CERAMIC ELECTROSTATIC CHUCK INCLUDING EMBEDDED FARADAY CAGE FOR RF DELIVERY AND ASSOCIATED METHODS FOR OPERATION, MONITORING, AND CONTROL

Lam Research Corporation,...

1. A substrate support system, comprising:a ceramic assembly having a top surface and a bottom surface, the top surface including an area configured to support a substrate;
at least one clamp electrode positioned within the ceramic assembly;
a primary radiofrequency (RF) power delivery electrode positioned within the ceramic assembly at a location vertically below the at least one clamp electrode;
a lower support structure formed of an electrically conductive material, the ceramic assembly secured to the lower support structure such that an outer peripheral region of the bottom surface of the ceramic assembly is supported by the lower support structure, the lower support structure including a hollow interior region exposed to a portion the bottom surface of the ceramic assembly; and
a plurality of electrical connections established between the lower support structure and the primary RF power delivery electrode, each of the plurality of electrical connections extending through a respective portion of the ceramic assembly.

US Pat. No. 10,192,765

SUBSTRATE PROCESSING SYSTEMS, APPARATUS, AND METHODS WITH FACTORY INTERFACE ENVIRONMENTAL CONTROLS

Applied Materials, Inc., ...

1. A method of processing substrates within an electronic device processing system, comprising:providing a factory interface including a factory interface chamber, one or more substrate carriers docked to the factory interface, each of the one or more substrate carriers having a substrate carrier door, one or more carrier purge chambers within the factory interface chamber, and one or more load lock chambers coupled to the factory interface;
sealing a carrier purge housing to the factory interface chamber, the carrier purge housing having a carrier purge chamber located therein, the sealing covering a substrate carrier door and isolating the carrier purge chamber from the factory interface chamber;
monitoring one or more environmental conditions in the carrier purge chamber;
setting one or more environmental conditions in the carrier purge chamber in response to the monitoring;
opening the substrate carrier door by attaching a door opener to the substrate carrier door, the door opener being attached to a rack and pinion, the rack located within the carrier purge chamber, the pinion being attached to a motor at least partially located external to the carrier purge chamber; and
unsealing the carrier purge housing from the factory interface.

US Pat. No. 10,192,763

METHODOLOGY FOR CHAMBER PERFORMANCE MATCHING FOR SEMICONDUCTOR EQUIPMENT

Applied Materials, Inc., ...

1. A method for calibrating a plasma processing chamber for semiconductor manufacturing process, comprising:performing a first predetermined plasma process in a plasma processing chamber;
maintaining a desired gas pressure in the plasma processing chamber;
collecting a first set of signals transmitted from a first group of sensors disposed in the plasma processing chamber to a controller while performing the predetermined process;
analyzing the collected first set of signals;
comparing the collected first set of signals with database stored in the controller of the plasma processing chamber to check sensor responses from the first group of sensors;
calibrating sensors based on the collected first set of signals when a mismatch sensor response is found;
subsequently performing a first series of plasma processes including at least two processes in the processing chamber, wherein the first series of processes comprises multiple processes including the process parameters set in the first predetermined process, 20% above and below of the process parameters set in the first predetermined process, and 10% above and below of the process parameters set in the first predetermined process; and
collecting a second set of signals transmitted from the sensors to the controller while performing the series of plasma processes in the plasma processing chamber.

US Pat. No. 10,192,762

SYSTEMS AND METHODS FOR DETECTING THE EXISTENCE OF ONE OR MORE ENVIRONMENTAL CONDITIONS WITHIN A SUBSTRATE PROCESSING SYSTEM

APPLIED MATERIALS, INC., ...

1. A method for operating a substrate processing cluster tool, comprising:positioning a substrate storage cassette at least partially within a factory interface of the substrate processing cluster tool, the substrate storage cassette defining an interior volume dimensioned and arranged to receive one or more substrates;
sensing, with a plurality of sensors, at least one condition including temperature within the substrate storage cassette, an elapsed time between termination of a first process involving the substrate storage cassette and initiation of a second process involving the substrate storage cassette, a concentration of one or more airborne contaminants within at least one of the substrate storage cassette or the factory interface, or a humidity within the substrate storage cassette; and
responsive to a sensed condition generating an alert and performing a corrective operation involving the substrate storage cassette.

US Pat. No. 10,192,759

IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING

LAM RESEARCH CORPORATION,...

1. A semiconductor processing tool, comprising:one or more process chambers;
one or more gas inlets into the one or more process chambers and associated flow-control hardware;
a low frequency radio frequency (LFRF) generator;
a high frequency radio frequency (HFRF) generator; and
a controller having at least one processor and a memory, wherein
the at least one processor and the memory are communicatively connected with one another,
the at least one processor is at least operatively connected with the flow-control hardware, the LFRF generator, and the HFRF generator, and
the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow-control hardware, the HFRF generator, and the LFRF generator to:
etch a semiconductor substrate to transfer a pattern from an overlying photoresist to a core amorphous carbon layer on the semiconductor substrate;
deposit a conformal film over the patterned core amorphous carbon layer on the semiconductor substrate;
deposit a gap-fill amorphous carbon layer over the conformal film;
planarize the semiconductor substrate with a process that etches both the conformal film and the gap-fill amorphous carbon layer to remove the conformal film overlying the core amorphous carbon layer without removing the conformal film deposited between the core amorphous carbon layer and the gap-fill amorphous carbon layer; and
selectively etch the conformal film to form a mask.

US Pat. No. 10,192,758

SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus that processes a substrate with a processing liquid and dries the substrate, the substrate processing apparatus comprising:a substrate rotating device configured to rotate the substrate;
a processing liquid discharging unit configured to discharge the processing liquid toward the substrate;
a substitution liquid discharging unit configured to discharge a substitution liquid, which is substituted with the processing liquid on the substrate, toward the substrate while relatively moving with respect to the substrate to form a liquid film of the substitution liquid on the substrate; and
an inert gas discharging unit configured to:
discharge a first inert gas, from a first inert gas discharge nozzle provided vertically downward, vertically downward from above a central portion of the substrate toward a central portion of the liquid film of the substitution liquid formed on the substrate to form an interface where the liquid film of the substitution liquid is thicker at a peripheral portion side of the substrate than at a central portion side thereof and to increase an area confined by the interface uniformly from the central portion of the substrate toward a peripheral portion thereof, and then
push the interface from the central portion of the substrate toward the peripheral portion thereof by discharging a second inert gas, from a second inert gas discharge nozzle provided to be inclined downward, toward a peripheral portion of the substrate in an inclined direction from above the substrate while moving the second inert gas discharge nozzle relatively with respect to the substrate in a direction different from a direction in which the substitution liquid discharging unit is moved.

US Pat. No. 10,192,757

SUBSTRATE CLEANING APPARATUS AND SUBSTRATE CLEANING METHOD

EBARA CORPORATION, Tokyo...

1. A substrate cleaning apparatus, comprising:a substrate holder configured to hold a substrate and rotate the substrate about a rotational axis;
a roll cleaning tool configured to be placed in sliding contact with the substrate to thereby clean the substrate; and
a cleaning-tool rotating device coupled to the roll cleaning tool;
a vertically-moving device coupled to the cleaning-tool rotating device, the vertically-moving device being configured to change a vertical position of the roll cleaning tool toward the substrate held by the substrate holder and keep the vertical position of the roll cleaning tool while cleaning the substrate;
a cleaning-liquid supply nozzle configured to supply cleaning liquid onto a first region of the substrate;
a fluid supply nozzle arranged in parallel with a longitudinal direction of the roll cleaning tool as viewed from an extending direction of the rotational axis, the fluid supply nozzle being configured to supply fluid, which is constituted by pure water or chemical liquid, onto a second region of the substrate, the cleaning-liquid supply nozzle being located at one side of the roll cleaning tool, while the fluid supply nozzle being located at an opposite side of the roll cleaning tool beside the roll cleaning tool, the fluid supply nozzle being located at a position to form a flow of the fluid along the longitudinal direction of the roll cleaning tool at the second region located at an opposite side of the substrate from the first region across the roll cleaning tool.

US Pat. No. 10,192,755

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
a plurality of wiring layers formed over the semiconductor substrate;
a pad electrode formed in the uppermost layer of the wiring layers;
a first protective film having an opening over the pad electrode;
a first redistribution line formed over the first protective film and having an upper surface, a side surface and a lower surface, the first redistribution line coupled electrically to the pad electrode through the opening;
a sidewall barrier film comprised of an insulating film formed on the side surface of the first redistribution line; and
a cap metallic film covering the upper surface of the first redistribution line and having an overlapping part with sidewall barrier film,
wherein the cap metallic film covers the side surface of the first redistribution line, and
wherein the cap metallic film and the sidewall barrier film are overlapped with each other at the side surface of the first redistribution line.

US Pat. No. 10,192,752

SELF-ASSEMBLED MONOLAYER BLOCKING WITH INTERMITTENT AIR-WATER EXPOSURE

Applied Materials, Inc., ...

14. A method of processing a substrate, comprising:exposing a substrate to a self-assembled monolayer (“SAM”) molecule for a first period of time to achieve selective deposition of a SAM on a first material in a first processing chamber, wherein the substrate comprises an exposed first material and an exposed second material;
transferring the substrate to a second processing chamber;
exposing the substrate to a hydroxyl moiety formed from water vapor in the second processing chamber for a second period of time;
repeating the exposing the substrate to a SAM molecule in the first processing chamber and the exposing the substrate to the hydroxyl moiety formed from water vapor in the second processing chamber in a time ratio of the first period of time to the second period of time between about 1:1 and about 100:1, respectively, and wherein a first repetition occurs for a first total time and a subsequent repetition occurs for a second total time that is less than the first total time;
after performing the repeating, exposing the substrate to the SAM molecule in the first processing chamber;
selectively depositing a third material on the exposed second material; and
removing the SAM from the first material.

US Pat. No. 10,192,751

SYSTEMS AND METHODS FOR ULTRAHIGH SELECTIVE NITRIDE ETCH

LAM RESEARCH CORPORATION,...

1. A method for selectively etching a silicon nitride layer on a substrate, comprising:arranging the substrate on a substrate support of a substrate processing chamber,
wherein the substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper chamber region and the lower chamber region, and
wherein the gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region;
supplying an etch gas mixture to the upper chamber region;
striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil, wherein the etch gas mixture etches silicon nitride, promotes silicon dioxide passivation and promotes polysilicon passivation;
selectively etching the silicon nitride layer on the substrate;
extinguishing the inductively coupled plasma after a predetermined period; and
after the selectively etching, dry cleaning the substrate by supplying a dry clean gas mixture to the substrate processing chamber and striking plasma in the substrate processing chamber for another predetermined period.

US Pat. No. 10,192,750

PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method for processing a workpiece that includes a silicon-containing etching target layer, an organic film provided on the etching target layer, an antireflective film provided on the organic film, and a first mask provided on the antireflective film, using a plasma processing apparatus that includes a processing container, the plasma processing method comprising:generating a first plasma in the processing container;
etching the antireflective film using the first plasma generated in the processing container and the first mask to form a second mask from the antireflective film;
etching the organic film using the first plasma generated in the processing container and the second mask to form a third mask from the organic film;
generating a second plasma of a mixed gas including a first gas and a second gas in the processing container; and
etching the etching target layer using the second plasma generated in the processing container and the third mask,
wherein the plasma processing apparatus further includes an upper electrode,
the upper electrode is provided above a placing table that supports the workpiece in the processing container,
an electrode plate of the upper electrode contains silicon,
the first gas is oxygen gas, and
after generating the second plasma of the mixed gas and before etching the etching target layer using the second plasma, a silicon oxide film is formed on a surface of the electrode plate by colliding oxygen ions contained in the second plasma of the first gas with the electrode plate.

US Pat. No. 10,192,747

MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE AND METHOD OF MANUFACTURING THEREOF

Cypress Semiconductor Cor...

1. The method of fabricating a semiconductor device, comprising:forming, on a substrate, a first gate stack having a first gate conductor layer and a first gate dielectric structure between the first gate conductor layer and the substrate;
forming an inter-gate dielectric structure at a sidewall of the first gate conductor;
forming, adjacent to the inter-gate dielectric structure, a second gate stack having a second gate conductor layer and a second gate dielectric structure between the second gate conductor layer and the substrate; and
performing a wet etch to clean the first and second gate stacks prior to forming a dielectric layer to encapsulate at least the first and second gate stacks, and the inter-gate,
wherein the inter-gate dielectric structure includes four or more layers of two or more different dielectric films disposed in an alternating manner, and having significantly different wet etch rates against a same etchant, wherein each of the four or more layers includes a width in an approximate range of 30 ? or less, and wherein the inter-gate dielectric structure is substantially un-etched by the wet etch in a direction perpendicular to the substrate.

US Pat. No. 10,192,744

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

Semiconductor Manufacturi...

1. A semiconductor device comprising:a first substrate, wherein a through hole extends through the first substrate;
a second substrate, which overlaps the first substrate;
a first conductor, which is configured to electrically connect two elements associated with the first substrate, wherein the through hole is positioned between two opposite edges of the first conductor;
a second conductor, which is positioned on the first substrate and is electrically connected to the first conductor;
a third conductor, which is configured to electrically connect two elements associated with the second substrate;
a fourth conductor which is positioned on the second substrate and is electrically connected to the third conductor; and
a fifth conductor, which directly contacts each of the second conductor and the fourth conductor and is positioned between the second conductor and the fourth conductor.

US Pat. No. 10,192,743

METHOD OF ANISOTROPIC EXTRACTION OF SILICON NITRIDE MANDREL FOR FABRICATION OF SELF-ALIGNED BLOCK STRUCTURES

TOKYO ELECTRON LIMITED, ...

1. A method of preparing a self-aligned block (SAB) structure, comprising:providing a substrate having raised features defined by a first material containing silicon nitride and a second material containing silicon oxide formed on side walls of the first material, and a third material containing an organic material covering some of the raised features and exposing some raised features according to a block pattern formed in the third material;
forming a first chemical mixture by plasma-excitation of a first process gas containing H and optionally a noble gas;
exposing the first, second, and third materials on the substrate to the first chemical mixture;
thereafter, forming a second chemical mixture by plasma-excitation of a second process gas containing N, F, O, and optionally a noble element; and
exposing the first, second, and third materials on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second and third materials.

US Pat. No. 10,192,741

DEVICE SUBSTRATE, METHOD OF MANUFACTURING DEVICE SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method of manufacturing a device substrate, the method comprising:forming a mask film on an entire surface of a device substrate in which a multilayer film is disposed on a substrate;
removing a portion of the mask film on a bevel region that is provided as a region from a peripheral edge portion of a patterning region to an end portion of the device substrate, the patterning region being provided as the region on which a resist is to be applied during an imprint process of the device substrate; and
planarizing an upper surface of the mask film positioned on the patterning region,
wherein the planarizing of the upper surface of the mask film includes
dropping the resist onto the mask film,
placing a blank template including no rugged patterns, with respect to the mask film through the resist, such that there is a predetermined distance between the blank template and the mask film, and curing the resist, and
etching back an entire surface of the device substrate by use of dry etching.

US Pat. No. 10,192,740

HIGH THROUGHPUT SEMICONDUCTOR DEPOSITION SYSTEM

Alliance for Sustainable ...

1. A method of performing hydride vapor phase epitaxy (HVPE) deposition, the method comprising:providing at least one first source material and at least one first carrier gas flow to a first HVPE mixing zone coupled to a first deposition zone;
providing at least one second source material and at least one second carrier gas flow to a second HVPE mixing zone coupled to a second deposition zone;
heating the first deposition zone to a first temperature;
heating the first HVPE mixing zone to a second temperature;
heating the second deposition zone to a third temperature, wherein the third temperature is different from the first temperature;
heating the second HVPE mixing zone to a fourth temperature;
outputting, from the first HVPE mixing zone into the first deposition zone, first reactant gases produced from the at least one first source material and the at least one first carrier gas flow;
outputting, from the second HVPE mixing zone into the second deposition zone, second reactant gases produced from the at least one second source material and the at least one second carrier gas flow;
placing a substrate into the first deposition zone to grow a first layer from the first reactant gases; and
placing the substrate into the second deposition zone to grow a second layer from the second reactant gases,
wherein the heating of the first deposition zone to the first temperature and the heating of the second deposition zone to the third temperature are performed concurrently.

US Pat. No. 10,192,737

METHOD FOR HETEROEPITAXIAL GROWTH OF III METAL-FACE POLARITY III-NITRIDES ON SUBSTRATES WITH DIAMOND CRYSTAL STRUCTURE AND III-NITRIDE SEMICONDUCTORS

Foundation for Research a...

1. A method of heteroepitaxial growth of III-Nitride semiconductors on a substrate achieving (0001) orientation and metal-face polarity for a first nucleation layer and subsequent layers, comprising the following steps:utilizing a nitrogen plasma source for molecular beam epitaxy to deposit an Al-face polarity (0001) AlN nucleation layer less than 5 nm in deposited layer thickness to minimize degradation of the epitaxial growth of the AlN layer and inversion of its polarity;
depositing said AlN layer on a substrate independent of the crystalline surface orientation of said substrate, said substrate being polycrystalline diamond; and
by the cooperation between said utilizing the nitrogen plasma source for epitaxy and said depositing of said AlN layer less than 5 nm in thickness, subsequently overgrowing on said AlN layer one or more additional III-Nitride compound layers while preserving said (0001) orientation and III metal-face polarity; and
between the steps of depositing of said AlN layer and overgrowing of said AlN layer by a III-nitride compound layer, interrupting the depositing of said AlN layer and exposing said MN layer to active nitrogen species produced by the nitrogen plasma source.

US Pat. No. 10,192,733

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND CHEMICAL LIQUID

TOSHIBA MEMORY CORPORATIO...

1. A method of manufacturing a semiconductor device comprising:attaching, by a liquid treatment, a first liquid to a surface of a semiconductor substrate having a fine pattern formed therein;
substituting the first liquid attached to the surface of the semiconductor substrate with a solution, the solution comprising a precipitating material dissolved in a second liquid;
vaporizing the second liquid and precipitating the precipitating material to the surface of the semiconductor substrate; and
removing the precipitating material by transforming the precipitating material from solid to gas by depressurization and/or heating,
the precipitating material comprising at least one material selected from a group consisting of:
materials represented by chemical formulae A1, A2, A3, and A4 indicated in FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D where X1, X2, and X3 in the chemical formulae A1, A2, A3, and A4 each independently represent either of a hydroxy group (—OH), a carboxyl group (—COOH), an amino group (—NH2), an amide group (—CONH2), a nitro group (—NO2), and a methylester group (—COO—CH3), and
materials represented by chemical formulae B1, B2, B3, B4, and B5 indicated in FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, and FIG. 6E where X1, X2, X3, and X4 in the chemical formulae B 1, B2, B3, B4 and B5 each independently represent either of a hydroxy group (—OH), a carboxyl group (—COOH), an amino group (—NH2), an amide group (—CONH2), a nitro group (—NO2), a methylester group (—COO—CH3), a methoxy group (—OCH3), an ethoxy group (—OCH2CH3), and a propoxy group (—OCH2CH2CH3),
in the materials represented by chemical formulae A1, A4, B1, B3, and B5, a group bonded to one of adjacent bonding sites is a carboxyl group and one or more groups bonded to the other of the adjacent bonding sites include a carboxyl group, a hydroxyl group, or an amino group.

US Pat. No. 10,192,732

CONTAMINANT REMOVAL IN ULTRA-THIN SEMICONDUCTOR DEVICE FABRICATION

TEXAS INSTRUMENTS INCORPO...

1. A method of fabricating a semiconductor device, the method comprising:forming topside circuitry for an integrated circuit (IC) on a topside of a semiconductor substrate of the semiconductor device, the topside circuitry having a topside metal structure and a topside passivation structure;
applying a topside protection material to protect the topside circuitry;
grinding a backside of the semiconductor substrate to a selected thickness;
removing the topside protection material;
after removal of the topside protection material, applying a chemical solution cleaning process to remove contaminants from the backside of the semiconductor substrate;
applying a deionized (DI) water cleaning process to the semiconductor substrate after the chemical cleaning process; and
forming a backside metallization (BSM) layer over the backside of the semiconductor substrate,
wherein the topside metal structure comprises a gold (Au) metal structure and the topside passivation structure comprises a polyimide passivation structure, and further wherein the chemical solution cleaning process comprises exposing the semiconductor device to a solution of a mixture having ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) in a ratio of one part of NH4OH to two parts of H2O2, and the mixture is diluted in water in a ratio of one part of the mixture to eight parts of water.

US Pat. No. 10,192,731

LIQUID PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A liquid processing method for performing a liquid processing on a substrate disposed inside a processing container, and then, drying the substrate, the method comprising:a processing liquid supplying step of performing a liquid processing by supplying a processing liquid to a center portion of the substrate inside the processing container;
a low humidity gas supplying step of supplying a low humidity gas for lowering a humidity inside the processing container, into the processing container during a time period when the processing liquid is supplied to the substrate; and
a drying step of removing the processing liquid on the substrate and drying the substrate,
wherein the drying step is started after a humidity measurement value obtained by measuring the humidity inside the processing container becomes equal to or less than a preset humidity target value.

US Pat. No. 10,192,728

MASS SPECTROMETER AND METHOD APPLIED THEREBY FOR REDUCING ION LOSS AND SUCCEEDING STAGE VACUUM LOAD

SHIMADZU CORPORATION, Ky...

1. A mass spectrometer, comprising:an ion source, located in a first gas pressure region and providing ions;
a vacuum chamber, having an inlet and an outlet and located in a second gas pressure region having a gas pressure lower than that of said first gas pressure region; wherein ions in said first gas pressure region are allowed to pass through said inlet of said vacuum chamber and enter said vacuum chamber located in said second gas pressure region along with a gas flow generated by a pressure difference, and exit said vacuum chamber from said outlet of said vacuum chamber;
an ion guiding device, arranged in said vacuum chamber and located at a succeeding stage of said vacuum chamber inlet but a preceding stage of said vacuum chamber outlet; and
a hollow tubular lens, arranged in said vacuum chamber and located at said succeeding stage of said vacuum chamber inlet but said preceding stage of said ion guiding device;
wherein said tubular lens is an aerodynamic lens whose central axis is parallel to a direction of said gas flow entering said vacuum chamber from said inlet of said vacuum chamber, said gas flow produces a Mach disc as a result of a free expanded jet after entering said vacuum chamber, and the inlet of said tubular lens is located at the upstream part of said Mach disc.

US Pat. No. 10,192,724

MS/MS MASS SPECTROMETRIC METHOD AND MS/MS MASS SPECTROMETER

SHIMADZU CORPORATION, Ky...

1. An MS/MS mass spectrometer including an ionizing unit for ionizing a target component in a sample, a first mass separating unit for selecting, as a precursor ion, an ion having a specific mass-to-charge ratio from multivalent ions, the multivalent ion having a valence of two or more out of ions originated from the target component, a dissociation operation unit for dissociating the precursor ion selected by the first mass separating unit, a second mass separating unit for selecting a product ion having a specific mass-to-charge ratio from product ions generated through the dissociation, and a detecting unit for detecting the ion selected by the second mass separating unit, the MS/MS mass spectrometer comprising:a) a first inputting unit for allowing a user to input and set a mass mLoss of a fragment eliminated from the precursor ion through the dissociation;
b) a second inputting unit for allowing the user to input and set at least two of three parameters of a valence zLoss of the fragment, a valence zPrec of the precursor ion and a valence zprod of the product ion, the valence zLoss of the fragment being a valence of the fragment eliminated from the precursor ion through the dissociation when the dissociation is based on dissociation operation other than electron capture dissociation or a valence of a fragment before neutralized that captures an electron to be neutralized and eliminated when the dissociation is based on the electron capture dissociation;
c) a lack information calculating unit for calculating, when one of the three parameters zLoss, zPrec and zProd is not input, the one uninput parameter zLoss, zPrec or zProd from the parameters input by the second inputting unit using relation, zPrec=zProd+zLoss; and
d) a controlling unit for individually controlling operations of the first mass separating unit and the second mass separating unit in performing MS/MS analysis such that a mass-to-charge ratio MProd of the product ion selected by the second mass separating unit with respect to a mass-to-charge ratio MPrec of the precursor ion selected by the first mass separating unit satisfies relation, MProd=(MPrec×zPrec?mLoss)/zProd.

US Pat. No. 10,192,719

PLASMA PROCESSING METHOD

Tokyo Electron Limited, ...

1. A plasma processing method comprising:a step of loading a substrate into a chamber where a plasma process is to be executed;
a step of mounting the substrate on a mounting table;
a first step of applying a bias power to the mounting table for a predetermined time period,
stopping the bias power after the predetermined time period, the bias power having a frequency that is lower than a frequency of excitation power for plasma excitation;
a second step of applying the bias power to the mounting table on which the substrate is mounted before applying an excitation power for plasma excitation;
a step of applying a DC voltage to an electrostatic chuck and electrostatically attracting the substrate that is mounted on the mounting table;
a step of supplying etching gas in the chamber; and
a step of applying the excitation power for the plasma excitation,
wherein the first step of applying the bias power and the second step of applying the bias power are performed on an identical substrate as one cycle before the DC voltage is applied on the electrostatic chuck so as to electrostatically attract the substrate by the electrostatic chuck,
wherein the first and second steps of applying the bias power are performed before supplying the etching gas, and
wherein the bias power of the first and the second steps are the same bias power and applied by one high frequency power source.

US Pat. No. 10,192,717

CONDITIONING REMOTE PLASMA SOURCE FOR ENHANCED PERFORMANCE HAVING REPEATABLE ETCH AND DEPOSITION RATES

APPLIED MATERIALS, INC., ...

10. The method of claim 9, wherein the passivation time of the interior wall surface of the remote plasma source and the processing time for performing a series of processes on N number of substrates are at a ratio of about 1:5 to about 1:30.

US Pat. No. 10,192,716

MULTI-BEAM DARK FIELD IMAGING

KLA-Tencor Corporation, ...

1. An apparatus, comprising:an electron source;
at least one optical device configured to produce a plurality of primary beam lets utilizing electrons provided by the electron source, the at least one optical device further configured to deliver the plurality of primary beam lets toward a target; and
an array of multi-channel detectors configured to receive a plurality of image beam lets emitted by the target in response to the plurality of primary beamlets, the array of multi-channel detectors further configured to render an array of dark field images to form a contiguous dark field image, wherein each multi-channel detector of the array of detectors comprises a set of detector elements.

US Pat. No. 10,192,712

CHARGED PARTICLE BEAM WRITING APPARATUS, METHOD OF ADJUSTING BEAM INCIDENT ANGLE TO TARGET OBJECT SURFACE, AND CHARGED PARTICLE BEAM WRITING METHOD

NuFlare Technology, Inc.,...

1. A method of adjusting a beam incident angle to a target object surface comprising:applying, using a blanking deflector arranged backward of an electron lens with respect to a direction of an optical axis, a voltage for beam-on to the blanking deflector, converging, using the electron lens and a magnet coil arranged in a center height position of the blanking deflector, a charged particle beam by varying a voltage to be applied to the electron lens while supplying, to the magnet coil, a current for a deflection amount smaller than a deflection amount for performing deflection to make a beam-off state by the blanking deflector, and measuring a positional deviation amount of an irradiation position of the charged particle beam irradiating a target object, for each voltage to be applied to the electron lens;
determining whether the positional deviation amount is within an allowable value, for the each voltage to be applied to the electron lens; and
when the positional deviation amount is determined to be greater than an allowable value, the each voltage to be applied to the electron lens are adjusted so that the positional deviation amount is within the allowable value.

US Pat. No. 10,192,711

FLUID INJECTOR FOR X-RAY TUBES AND METHOD TO PROVIDE A LIQUID ANODE BY LIQUID METAL INJECTION

Siemens Aktiengesellschaf...

1. A fluid injector for x-ray tubes to provide a liquid anode by liquid metal injection, comprising:a device which injects fluid from an opening in a chamber of the device as a fluid jet generated by an arrangement for changing a volume within the chamber;
a pipe connected to the chamber of the device; and
a reservoir for storing the anode material, said reservoir being fluidically connected by the pipe with the chamber of the device;
wherein the pipe comprises a part formed in a fluid flow direction with a shape to block fluid flow from the chamber to the reservoir during injection.

US Pat. No. 10,192,707

FUSE ASSEMBLY WITH REPLACEABLE CASING

1. A fuse assembly comprising:a casing having two slots defined through a first end thereof, the casing having a room defined therein which communicates with the two slots, two protrusions extending from an inside of the room, the casing having two insertion recesses defined through the first end thereof, each of the insertion recesses having a positioning member formed in an inside surface thereof;
a conductive member located in the casing and having a first end extending through a second end of the casing, the conductive member including two blades which are located with a gap formed therebetween, a fuse connected between the two blades, each of the two blades having a hole, the two protrusions engaged with the two holes of the two blades;
a cap having an open bottom which is detachably mounted to the first end of the casing, two arms respectively extending from two ends of the cap and each arm having a hook end, the two arms inserted into the two insertion recesses and the two hook ends being detachably hooked to the two positioning members, and
a light member connected to the cap and having a bulb and a leg portion which is electrically connected to the bulb, the leg portion being electrically connected to a second end of the conductive member.

US Pat. No. 10,192,703

BYPASS SWITCH COMPRISING A PLUNGER, A FIRST CONTACT DEVICE AND A SECOND CONTACT DEVICE

ABB SCHWEIZ AG, Baden (C...

1. A bypass switch for providing a bypass path between a first terminal and a second terminal, the bypass switch comprising:a first contact device;
a second contact device; and
a plunger being moveable from an initial state, via a first state, to a second state, wherein in the initial state the first terminal and second terminal are conductively separated; in the first state a movement of the plunger causes the first contact device to close a first conductive connection between the first terminal and the second terminal; and in the second state the plunger mechanically forces the second contact device to close a second conductive connection between the first terminal and the second terminal, AND
wherein the plunger comprises a front section and a back section, wherein the front section is detachably connected to the back section, and wherein, in the first state, it is the back section which causes the first contact device to close the first conductive connection.

US Pat. No. 10,192,702

ELECTROMAGNETIC RELAY AND RELAY DEVICE

PANASONIC INTELLECTUAL PR...

1. An electromagnetic relay, comprising:a contact point including a fixed contact and a movable contact;
a driver including a coil and is configured to bring the movable contact into contact with the fixed contact and to separate the movable contact from the fixed contact;
a base having an opening and including a first wall section surrounding an accommodation space in which the contact point and the driver are accommodated;
a cover covering the opening of the base; and
at least one connection terminal configured to electrically connect the coil to an external connection body, wherein
the first wall section of the base has a through hole communicating with an interior and an exterior of the accommodation space,
the at least one connection terminal includes:
a first terminal section accommodated in the base and electrically connected to the coil; and
a second terminal section protruding outside the base through the through hole and electrically connected to the external connection body,
the cover includes a second wall section disposed to leave a space from the first wall section having the through hole, and the second terminal section lies in the space, and
the space in which the second terminal section lies is sealed with a sealant.

US Pat. No. 10,192,701

SWITCH ACTUATION APPARATUS AND METHOD

GM Global Technology Oper...

1. An actuation apparatus comprising:a steering wheel armature including a base member;
wherein a module includes an air bag assembly;
the base member having a base defining a base axis and a base face;
wherein the steering wheel armature is rotatable about a rotation axis;
wherein the rotation axis and the base axis are non-coincident;
a plurality of base magnetic elements mounted to the base face and distributed around the base axis;
the module having a module face; and
a plurality of module magnetic elements mounted to the module face;
wherein the module is movably tethered to the base member;
wherein each of the base magnetic elements is aligned with a respective one of the module magnetic elements to form a paired magnet set such that the plurality of module magnetic elements and the plurality of base magnetic elements form a plurality of paired magnet sets; and
wherein the base magnetic element and the module magnetic element of each paired magnet set are oriented such that a repulsive magnetic force is generated between the base magnetic element and the module magnetic element of each paired magnetic set.

US Pat. No. 10,192,700

AIR CIRCUIT BREAKER HAVING AN IMPROVED ELECTRIC ARC QUENCHING CHAMBER

SCHNEIDER ELECTRIC INDUST...

1. An air circuit breaker, comprising:two separable electrical contacts connected to electric current input and output terminals; and
a chamber for quenching an electric arc, to extinguish the electric arc formed during the separation of the electrical contacts, said quenching chamber comprising a stack of splitter plates that are spaced apart from one another, and lateral walls placed on either side of the stack, the splitter plates being fixed to the lateral walls, each lateral wall including a thermosetting-resin impregnated polyamide fabric and being devoid of glass fibres,
wherein the quenching chamber furthermore includes protective elements made of crosslinked polyamide, said protective elements being placed inside the quenching chamber, along the lateral walls on either side of the stack, in junction zones between the lateral walls and the splitter plates, the protective elements covering corners of the splitter plates which corners are adjacent to the lateral walls, so as to separate these corners of the splitter plates from the electrical contacts, and
wherein each protective element comprises seats and a plurality of fingers, the seats being bounded by the fingers, one corner of the splitter plate of the stack being received inside each seat, and each pair of fingers in the plurality of fingers having one of the splitter plates disposed therebetween,
wherein the protective elements extend substantially parallel to the stack, from a lower end of the stack to a lower edge of an upper arcing horn situated above the stack, such that are there splitter plates included in the stack of splitter plates which are not covered by the protective elements.

US Pat. No. 10,192,699

POWER SEAT OPERATION DEVICE AND POWER SEAT

NHK Spring Co., Ltd., Yo...

1. A power seat operation device comprising:a dial that is rotatably installed at a side face of a power seat provided with a plurality of moving mechanisms, one of the plurality of moving mechanisms being selected by rotational operation of the dial, and an interior and an exterior of the dial being in communication through an opening formed at a peripheral outer side of the dial;
a switch that is attached inside the dial, the switch actuating the selected moving mechanism;
a knob that is installed inside the dial at a seat width direction outer side of the switch, that is rotatably supported by the dial, that includes an operation portion inserted through the opening so as to project outside the dial, and that is capable of operating the switch by operation of the operation portion; and
a channel that is formed inside the dial by the dial and the knob, the channel being partitioned from the switch, and, in cases in which liquid has infiltrated into the dial through the opening in a state in which the opening is positioned at an upper side of the switch, the channel letting the liquid flow downward to a lower side of the switch so as to discharge the liquid to outside the dial.

US Pat. No. 10,192,696

LIGHT-EMITTING ASSEMBLY FOR KEYBOARD

APPLE INC., Cupertino, C...

1. A keyboard assembly, comprising:a switch housing defining a switch opening and a light source recess formed in a sidewall of the switch opening;
a tactile dome positioned at least partially within the switch opening;
a keycap positioned above the switch housing and configured to move toward the tactile dome when pressed; and
a light-emitting assembly positioned within the light source recess of the switch housing, and comprising:
a light source;
a luminescent structure at least partially enclosing the light source and defining a front face of the light-emitting assembly;
an opaque material defining a rear face of the light-emitting assembly, the rear face being positioned opposite the front face;
a first sidewall defining a first side face of the light-emitting assembly; and
a second sidewall opposite the first sidewall and defining a second side face of the light-emitting assembly, wherein the switch housing is configured to receive light from each of the front face, the first side face, and the second side face and to guide the received light toward the keycap, wherein the opaque material is configured to prevent light from passing through it.

US Pat. No. 10,192,692

EXPLOSION-PROOF CROSS-TYPE LIMIT SWITCH

1. An explosion-proof limit switch (10) comprising:a housing (12);
a gear mechanism (24) arranged in said housing (12), said gear mechanism including a gear mechanism cover plate (38), a gear mechanism base plate (48) and at least one intermediate plate (42) arranged between the gear mechanism cover plate (38) and the gear mechanism base plate (48);
said intermediate plate (42) having at least one cutout (44) in which a first gearwheel (54) is arranged and at least one second cutout (46) in which a second gearwheel (58) is arranged;
said first gearwheel (54) having a first plug-through opening (56) and said second gearwheel (58) having a second plug-through opening (60);
a shaft (20) having an actuating lever (18) arranged outside the housing (12) and being rotatably supported in a first bearing arrangement (22) connected to the housing (12) and extending through the first plug-through opening (56) of the first gearwheel (54) in order to couple with the first gearwheel (54) in a torque transmitting manner and to radially support said first gearwheel (54); and
a rotary switch (30) arranged in the housing (12) and having a switch shaft (138) that is rotatably supported in a second bearing arrangement (106, 134) and extends through the second plug-through opening (60) of the second gearwheel (58) in order to couple with the second gearwheel (58) in a torque transmitting manner and to radially support said second gearwheel (58).

US Pat. No. 10,192,691

ELECTRICITY STORAGE UNIT

Panasonic Intellectual Pr...

1. An electricity storage unit comprising:an electricity storage device;
a holder for holding the electricity storage device;
a control board that is formed with a wiring electrically connected with the electricity storage device;
a case having a tubular side wall part and a bottom surface part closing one end of the side wall part, the case being formed with an opening at another end of the side wall part; and
a cover for covering the opening, wherein:
the electricity storage device, the holder, and the control board are housed inside the case,
the holder is fixed to the control board, and
a rear end of the holder is supported inside the case by abutting the rear end to an inner surface of the bottom surface part, the rear end facing the bottom surface part.

US Pat. No. 10,192,690

TITANIUM OXIDE-BASED SUPERCAPACITOR ELECTRODE MATERIAL AND METHOD OF MANUFACTURING SAME

SHANGHAI INSTITUTE OF CER...

1. A titanium oxide-based supercapacitor electrode material, comprising a conductive titanium oxide as an active substance, wherein the conductive titanium oxide is selected from the group consisting of titanium sub-oxide, reduced titanium dioxide, and doped reduced titanium dioxide, a whole or a surface of the titanium sub-oxide, the reduced titanium dioxide, or the doped reduced titanium dioxide having amorphous layers comprising defect structures and activated Ti3+; and the titanium oxide-based supercapacitor electrode material has a density of charge carrier higher than 1018 cm?3, and a specific capacitance in a range of 20 F/g˜1,740 F/g, under a charge-discharge current of 1 A/g; and the titanium sub-oxide, the reduced titanium dioxide, or the doped reduced titanium dioxide is prepared by a step of performing a high surface reduction treatment on titanium dioxide to obtain the titanium sub-oxide or the reduced titanium dioxide, or by a step of performing the high surface reduction treatment and a doping treatment on titanium dioxide to obtain the doped reduced titanium dioxide; wherein the high surface reduction treatment is performed at 200˜500° C. for 2˜12 hours.

US Pat. No. 10,192,686

MULTILAYER ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component comprising:a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, one ends of the first and second internal electrodes being exposed through the third and fourth surfaces, respectively;
first and second external electrodes including, respectively, first and second band portions disposed on the first surface of the capacitor body to be spaced apart from each other and first and second connected portions, respectively extending from the first and second band portions to the third and fourth surfaces of the capacitor body;
first and second connection terminals formed of insulators and disposed on the first and second band portions, respectively; and
first and second insulating portions disposed on at least some circumferential surfaces of the first and second connection terminals, respectively,
wherein the first connection terminal includes a first conductive pattern formed on a surface thereof facing the first band portion, a second conductive pattern formed on a surface thereof opposing the surface on which the first conductive pattern is formed, a first cut portion formed in some circumferential surfaces thereof connecting the first and second conductive patterns to each other, and a first connection pattern formed on the first cut portion to electrically connect the first and second conductive patterns to each other, and
the second connection terminal includes a third conductive pattern formed on a surface thereof facing the second band portion, a fourth conductive pattern formed on a surface thereof opposing the surface on which the third conductive pattern is formed, a second cut portion formed in some circumferential surfaces thereof connecting the third and fourth conductive patterns to each other, and a second connection pattern formed on the second cut portion to electrically connect the third and fourth conductive patterns to each other.

US Pat. No. 10,192,684

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body including dielectric layers and a plurality of first and second internal electrodes alternately disposed therein, having the dielectric layers interposed therebetween, and having a first surface and a second surface opposing each other in a first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction, and a fifth surface and a sixth surface connected to the first surface and the second surface, connected to the third surface and the fourth surface, and opposing each other in a third direction, the plurality of first and second internal electrodes being exposed through at least the third surface and the fourth surface, respectively;
a first external electrode and a second external electrode including first and second connection portions disposed on the third surface and the fourth surface of the capacitor body and electrically connected to exposed portions of the plurality of first and second internal electrodes, and first and second band portions extending from the first and second connection portions to portions of the first surface and the second surface of the capacitor body and to portions of the fifth surface and the sixth surface of the capacitor body, respectively;
a first conductive resin layer including a first portion covering a portion of the first band portion and disposed on the first surface of the capacitor body, and a second portion extending from the first surface onto one of the surfaces of the capacitor body other than the first surface;
a second conductive resin layer including a third portion covering a portion of the second band portion and disposed on the first surface of the capacitor body, and a fourth portion extending from the first surface onto one of the surfaces of the capacitor body other than the first surface;
an insulating layer disposed on the first surface of the capacitor body; and
a first terminal electrode and a second terminal electrode disposed to be spaced apart from each other in the second direction, covering portions of the insulating layer disposed on the first surface of the capacitor body, and connected to the first and second external electrodes, respectively.

US Pat. No. 10,192,682

COMPOSITE ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A composite electronic component comprising:a multilayer capacitor;
an electrostatic discharge (ESD) protecting element; and
first to fourth conductive resin layers,
wherein the multilayer capacitor includes:
a capacitor body including dielectric layers and a plurality of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, each of the first internal electrodes extending from the third surface to the fourth surface and being exposed through the third and fourth surfaces, and each of the second internal electrodes extending from the fifth surface to the sixth surface and being exposed through the fifth and sixth surfaces;
first and second external electrodes extending from the third and fourth surfaces of the capacitor body to portions of the first surface of the capacitor body, respectively, and connected to exposed portions of the first internal electrodes; and
third and fourth external electrodes extending from the fifth and sixth surfaces of the capacitor body to portions of the first surface of the capacitor body, respectively, and connected to exposed portions of the second internal electrodes,
the ESD protecting element includes:
first and second lead electrodes disposed on the first surface of the capacitor body to be connected to the first and second external electrodes, respectively;
a third lead electrode disposed on the first surface of the capacitor body to connect the third and fourth external electrodes to each other, the first and second lead electrodes being spaced apart from the third lead electrode;
a discharge portion disposed on the first surface of the capacitor body and covering the first to third lead electrodes; and
a protective layer disposed to cover the discharge portion, and
the first to fourth conductive resin layers are formed on the first to fourth external electrodes, respectively, and extend to portions of a first surface of the protective layer, respectively.

US Pat. No. 10,192,674

COIL COMPONENT HAVING TERMINAL ELECTRODES WITH HIGH MOUNTING STRENGTH, AND ELECTRONIC DEVICE INCLUDING THE COIL COMPONENT

TAIYO YUDEN CO., LTD., T...

1. A coil component comprising an air-core coil embedded in a magnetic body constituted by resin and metal magnetic grains, and having terminal electrodes electrically connected to both ends of the coil, wherein:both ends of the coil are exposed on a surface of the magnetic body;
the terminal electrodes are formed across the surface of the magnetic body and ends of the coil, and constituted by an underlying layer formed with metal material and a cover layer placed on an outer side of the underlying layer; and
the underlying layer is in contact with the resin and metal parts of the metal magnetic grains where the underlying layer is in contact with the magnetic body,
wherein a magnetic body surface on a side where either terminal electrode is connected to the end of the coil contains less resin than a magnetic body surface on a side where no terminal electrode is connected to the end of the coil.

US Pat. No. 10,192,673

INDUCTOR

SAMSUNG ELECTRO-MECHANICS...

1. An inductor comprising:a body comprising a magnetic material and having an upper surface, a lower surface, and side surfaces connecting the upper surface and the lower surface; and
a coil part disposed in the body and including a support member comprising an insulating resin, the coil part comprising first and second coil patterns respectively formed on an upper surface and a lower surface of the support member, wherein
1.15?b/a?1.45, where a is a length from a central plane between the upper surface and the lower surface of the support member to an upper surface of the body, and b is a length from the central plane of the support member to the lower surface of the body.

US Pat. No. 10,192,672

COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A coil component, comprising:a substrate; and
a coil pattern disposed on the substrate,
wherein the coil pattern includes a vertical region having a side surface perpendicular with respect to the substrate and a tapered region connected to the vertical region and having a side surface inclined with respect to the substrate,
in a cross section of the coil pattern, a minimum width of the tapered region is less than a minimum width of upper and lower surfaces of the coil pattern,
the vertical region and the tapered region form a trapezoidal shape and are made of the same material, and
wherein a spacing between coil pattern turns is between 0.15 and 0.45 times a width of a cross sectional shape of the coil pattern.

US Pat. No. 10,192,671

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component, comprising:a multilayer body including a plurality of insulator layers stacked together;
a plurality of inner conductors including at least a first inner conductor, a second inner conductor, a third inner conductor and a fourth inner conductor formed between the insulator layers and extended to a side surface of the multilayer body; and
a plurality of outer electrodes formed on both side surfaces of the multilayer body, the outer electrodes including at least a first outer electrode connected to the first inner conductor, a second outer electrode connected to the second inner conductor, a third outer electrode connected to the third inner conductor and a fourth outer electrode connected to the fourth inner conductor,
wherein each of the outer electrodes is formed on a single side surface so as not to extend over two side surfaces of the multilayer body, and
wherein the first outer electrodes and the second outer electrode are facing each other, and the first outer electrode and the second outer electrode differ in length in a direction in which the insulator layers are stacked.

US Pat. No. 10,192,668

COIL COMPONENT

Murata Manufacturing Co.,...

1. A coil component comprising:a drum-shaped core including a winding core portion and first and second flange portions provided at respective end portions of the winding core portion along a predetermined direction that is a length direction of the winding core portion;
each of the first and second flange portions having an inner end surface that faces a side of the winding core portion and positions the corresponding end portion of the winding core portion, an outer end surface that faces an outer side opposite to the inner end surface, a bottom surface that couples the inner end surface with the outer end surface and faces a side of a mount substrate at mounting, and a top surface opposite to the bottom surface;
a plate-shaped core bridged between the first and second flange portions while one principal surface of the plate-shaped core contacts the top surface of each of the first and second flange portions;
at least one first terminal electrode provided on the bottom surface of the first flange portion;
at least one second terminal electrode provided on the bottom surface of the second flange portion; and
at least one wire wound around the winding core portion and connected between the first and second terminal electrodes,
wherein, for dimensions measured along the predetermined direction, a dimension of each of the top surfaces of the first and second flange portions is equal to or larger than a dimension of the winding core portion.

US Pat. No. 10,192,667

ENCLOSURE SYSTEM AND METHOD FOR FACILITATING INSTALLATION OF ELECTRICAL EQUIPMENT

Hubbell Incorporated, Sh...

8. A method for installing a transformer:providing an enclosure for electrical equipment, the enclosure including a frame;
coupling a first member to the frame;
coupling the transformer to a first plate;
placing the first plate into the enclosure such that it is at least partially supported by the first member; and
fastening the first plate to the frame by manipulating a fastener that is coupled to the first plate and received through a hole in the frame, wherein fastening the first plate to the frame lifts the first plate from the first member.

US Pat. No. 10,192,666

MAGNETIC DEVICE FOR LOCKING A GEAR SELECTOR LEVER OF A VEHICLE IN A PREDETERMINED POSITION, METHOD FOR PRODUCING A MAGNETIC DEVICE, AND METHOD FOR OPERATING A MAGNETIC DEVICE

ZF Friedrichshafen AG, F...

1. A magnetic device for locking a gear shift lever of a vehicle in a predetermined position, the magnetic device comprising:a coil;
a tie component, which is movably supported in the coil;
a spring disposed outside the coil, wherein the spring is designed to push at least a portion of the tie component out of the coil;
a switch element which is designed to interact with a positioning element and the tie component disposed on a movement track in order to detect a position of the magnetic device in the movement track.

US Pat. No. 10,192,664

EXCITING DEVICE FOR ELECTROMAGNETIC CONNECTION DEVICE

OGURA CLUTCH CO., LTD., ...

1. An exciting device for an electromagnetic connection device, comprising:a yoke including an annular groove and a first through hole formed in a bottom wall serving as a bottom of the annular groove;
an exciting coil stored in the annular groove;
a terminal housing including a convex portion fitted in the first through hole and a concave portion located on an opposite side of the annular groove with respect to the convex portion, the convex portion including a second through hole extending in a direction parallel to a center line of the first through hole; and
an external connecting terminal buried in the terminal housing in a state in which a portion of the external connecting terminal is exposed in the concave portion, the external connecting terminal including a coil extraction hole formed in the portion exposed in the concave portion and continuing to the second through hole, and the exciting coil including an extraction end soldered to the external connecting terminal in a state in which the extraction end is passed through the second through hole and the coil extraction hole.

US Pat. No. 10,192,663

COIL FOR A SWITCHING DEVICE WITH A HIGH-FREQUENCY POWER

1. A coil system comprising a coil and several windings,wherein a first winding of the coil provides a first winding diameter and a first winding spacing;
wherein a last winding of the coil provides a second winding diameter and a second winding spacing;
wherein the first winding diameter is larger than the second winding diameter;
wherein the first winding spacing is smaller than the second winding spacing;
wherein the coil system further comprises a coil former filling an interior cavity of the coil;
wherein the coil former provides four recesses extending along its longitudinal axis, separated by webs, which are 90° offset relative to one another with reference to the coil former;
wherein the coil former comprises synthetic material,
wherein the coil former provides a relative permittivity that is no greater than about 1.2;
wherein the windings of the coil are guided in a guide groove of the coil former; and
wherein a wire thickness of the coil is larger than a depth of the guide groove.

US Pat. No. 10,192,662

METHOD FOR PRODUCING GRAIN-ORIENTED ELECTRICAL STEEL SHEET

JFE Steel Corporation, T...

1. A method for producing a grain-oriented electrical steel sheet by comprising a series of steps of hot rolling a raw steel material comprising C: 0.002-0.10 mass %, Si: 2.0-8.0 mass %, Mn: 0.005-1.0 mass % and the remainder being Fe and inevitable impurities to obtain a hot rolled sheet, subjecting the hot rolled steel sheet to a hot band annealing as required and further to one cold rolling or two or more cold rollings including an intermediate annealing therebetween to obtain a cold rolled sheet having a final sheet thickness, subjecting the cold rolled sheet to primary recrystallization annealing combined with decarburization annealing, applying an annealing separator to the steel sheet surface and then subjecting to final annealing, characterized in that rapid heating is performed at a rate of not less than 50° C./s in a region of 200-700° C. in the heating process of the primary recrystallization annealing, and the steel sheet is held at any temperature of 250-600° C. in the region of 200-700° C. for 1-5 seconds, while a soaking process of the primary recrystallization annealing is controlled to a temperature range of 750-900° C., a time of 90-180 seconds and PH2O/PH2 in an atmosphere of 0.25-0.40, where PH2O means a partial water vapor pressure of the atmosphere and PH2 means a partial hydrogen pressure of the atmosphere.

US Pat. No. 10,192,657

GROMMET AND WIRE HARNESS

Sumitomo Wiring Systems, ...

1. A grommet that is to be attached to a group of electrical wires and mounted to a vehicle body panel so as to block an opening in the vehicle body panel, the grommet comprising:a first cylindrical portion through which the group of electrical wires is inserted;
a second cylindrical portion that is formed shorter in an axial direction than the first cylindrical portion and surrounds the first cylindrical portion;
a seat portion that is constituted by an annular rubber elastic body that surrounds the second cylindrical portion and is capable of constriction in diameter, the seat portion having an annular unevenness portion capable of fitting around an edge portion of the opening in the vehicle body panel; and
an annular connection portion that elastically connects the first cylindrical portion and the seat portion,
wherein the seat portion has an approximately elliptical shape,
the connection portion has an inclined annular wall portion that forms an inclined annular surface that is inclined in the axial direction between the first cylindrical portion and the seat portion, the inclined annular wall portion supporting a base end portion of the second cylindrical portion, and
a plurality of rib portions are integrally provided on the inclined annular wall portion and the second cylindrical portion, the plurality of rib portions extending from an axially intermediate portion of the second cylindrical portion to the inclined annular wall portion on two sides in a major axis direction of the approximately elliptical shape, and projecting from the second cylindrical portion to a seat portion side.

US Pat. No. 10,192,653

TWISTED STRING-SHAPED ELECTRIC CABLE FOR UNDERWATER PURPOSE

Panasonic Intellectual Pr...

1. An electric cable comprising:at least one electric wire; and
a plurality of string-shaped bodies each extending in a longitudinal direction of the electric cable and twisting with one another around the at least one electric wire being a core, wherein the plurality of string-shaped bodies has a connection part twisting with one another excluding the at least one electric wire, and
wherein the connection part is connected to a frame of an underwater robot.

US Pat. No. 10,192,651

TRANSFER MATERIAL, METHOD OF MANUFACTURING TRANSFER MATERIAL, LAMINATED BODY, METHOD OF MANUFACTURING LAMINATED BODY, METHOD OF MANUFACTURING CAPACITANCE-TYPE INPUT DEVICE, AND METHOD OF MANUFACTURING IMAGE DISPLAY DEVICE

FUJIFILM CORPORATION, To...

1. A transfer material comprising, in this order, a temporary support body, a first resin layer, and a second resin layer,the first resin layer not being water soluble,
the second resin layer including a water soluble polymer,
the second resin layer including a compound that has a heteroaromatic ring including a nitrogen atom as a ring member, and
a content of the compound that has a heteroaromatic ring including a nitrogen atom as a ring member in the second resin layer being 3.0% by mass or greater with respect to a total solid content of the second resin layer.

US Pat. No. 10,192,650

PHOTOSENSITIVE CONDUCTIVE PASTE, METHOD OF PRODUCING MULTILAYER ELECTRONIC COMPONENT USING THE SAME, AND MULTILAYER ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A photosensitive conductive paste comprising:(a) a conductive powder in an amount of 70.3 to 85.6 mass % with respect to a total amount of the photosensitive conductive paste;
(b) a photosensitive resin composition containing an alkali-soluble polymer, a photosensitive monomer, a photopolymerization initiator, and a solvent; and
(c) a glass frit,
wherein a mass ratio of the glass frit to the conductive powder is 0.020 to 0.054,
the glass frit has a softening point that is equal to or above a temperature at which sintering of the conductive powder starts, and
the softening point of the glass frit is 657° C. or higher.

US Pat. No. 10,192,647

PACKAGE COMPRISING IMPROVED MEANS OF DAMPENING IMPACT BETWEEN AN ASSEMBLY CONTAINING RADIOACTIVE MATERIALS AND THE COVER OF THE PACKAGING

TN INTERNATIONAL, Montig...

1. A package comprising:a packaging for storing and/or transporting radioactive materials;
an assembly containing radioactive materials housed in a cavity of the packaging extending along a longitudinal axis of the packaging and being closed by a cover crossed by said longitudinal axis; and
a system for dampening impact of the assembly against the cover, the system comprising at least one plastically deformable dampening device and a loading device,
wherein one of the loading device and deformable dampening device is mounted moveable on the cover in a plane orthogonal to the longitudinal axis of the packaging, and has means of self-centring relatively to the other of the loading device and the deformable dampening device which is provided on said assembly containing the radioactive materials, and
wherein the deformable dampening device is arranged between the assembly and the cover along the longitudinal axis of the packaging.

US Pat. No. 10,192,646

RADIATION SHIELDING SYSTEM

General Electric Company,...

1. A radiation shielding system for an x-ray detector array comprising active components and passive components, the radiation shielding system comprising:a first radiation shield comprising a plurality of shielding pads configured to be positioned over active components of the digital detector array and a plurality of interstices between the shielding pads and configured to be positioned over passive components of the x-ray detector array,
wherein the plurality of shielding pads have a greater thickness than a thickness of the plurality of interstices.

US Pat. No. 10,192,640

FRACTIONAL FLOW RESERVE DECISION SUPPORT SYSTEM

Siemens Healthcare GmbH, ...

1. A method for fractional flow reserve (FFR) decision support using a computed tomography (CT)-based clinical decision support system, the method comprising:scanning a patient with a CT system, the scanning providing coronary CT data representing a heart of the patient;
acquiring non-invasive patient data and biochemical measurements;
extracting values from the non-invasive patient data and the biochemical measurements for features of an input vector of a machine-learnt predictor of the CT-based clinical decision support system from the coronary CT data;
generating, by the machine-learnt predictor of the CT-based clinical decision support system based on the values for the features of the input vector, a clinical decision of whether to perform CT-FFR for the patient; and
transmitting the clinical decision.

US Pat. No. 10,192,638

METHODS AND SYSTEMS FOR MANAGING PATIENT TREATMENT COMPLIANCE

WellDoc, Inc., Columbia,...

1. A computer-implemented method, comprising:receiving, over a network, application features for generating an application including instructions for using a treatment plan;
programmatically generating the application for a user to use on an electronic device by using the received application features;
receiving an activation code from the user to use the application, wherein the activation code is acquired by the user after the user receives authorization from a medical professional to use the application;
after receiving the activation code:
processing the activation code to determine if the user is authorized to use the application;
after determining that the user is authorized, authorizing the user to use and activate the application;
receiving input data from the user; and
using the input data from the user to evaluate user compliance with the treatment plan.

US Pat. No. 10,192,636

BAGGAGE SYSTEM, RFID CHIP, SERVER AND METHOD FOR CAPTURING BAGGAGE DATA

Brain Trust Innovations I...

1. A baggage system comprising:a belt loader reader device configured to communicate with a radio-frequency identification (RFID) tag associated with a baggage item, wherein the belt loader reader device comprises:
an RFID antenna;
a power transmission subsystem including a power source and an antenna arranged to wirelessly transmit power from the power source to the RFID tag;
a transceiver configured to receive first data from the RFID tag, the first data including identification information;
a controller operatively coupled to the transceiver; and
one or more memory sources operatively coupled to the controller, the one or more memory sources including instructions for configuring the controller to generate one or more messages indicative of the identification information to be sent by the transceiver to a server device via a network connection,
wherein the server device comprises:
a transceiver configured to receive the one or more messages from the belt loader reader device;
a controller operatively coupled to the transceiver; and
one or more memory sources operatively coupled to the controller, the one or more memory sources including instructions for configuring the controller to generate another message indicative of the identification information associated with the baggage item.

US Pat. No. 10,192,634

WIRE ORDER TESTING METHOD AND ASSOCIATED APPARATUS

MEDIATEK SINGAPORE PTE. L...

1. A wire order testing method for determining pin connection relationships between a memory device and an electronic device, the method comprising:testing the memory device with at least one test pattern to obtain at least one first data;
predicting at least one second data that is to be correspondingly obtained from testing of the memory device with the at least one test pattern according to mapping relationships between the test pattern and pins of the memory device; and
determining the pin connection relationships between the memory device and the electronic device according to the at least one first data and the at least one second data.

US Pat. No. 10,192,633

LOW COST INBUILT DETERMINISTIC TESTER FOR SOC TESTING

Intel Corporation, Santa...

6. A method of testing an integrated circuit, comprising:transitioning an auto-response module into a test mode, the auto-response module being fabricated on a chip and a signal path between the memory controller and memory ports at a chip boundary;
sending a read transaction from a transaction agent;
intercepting the read transaction in the auto-response module, wherein the auto-response module non-deterministically accumulates signatures of received transactions, the transactions comprising at least one of a write request and a read request; and
sending a deterministic response to the transaction agent based on a logical address of the read transaction.

US Pat. No. 10,192,632

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:a memory cell array including a plurality of memory cells coupled between a common source line and a bit line; and
a voltage generator applying operating voltages to word lines coupled to the memory cells or discharging potential levels of the word lines,
wherein during a program verify operation, the voltage generator applies a program verify voltage and a pass voltage as the operating voltages to the word lines, and subsequently applies a set voltage to the common source line during a period in which the memory cells are turned on.

US Pat. No. 10,192,629

SELF-LATCH SENSE TIMING IN A ONE-TIME-PROGRAMMABLE MEMORY ARCHITECTURE

TEXAS INSTRUMENTS INCORPO...

1. A method of reading data stored in a memory element of a memory device comprising:receiving a signal corresponding to the data stored in the memory element at an input of a sense amplifier;
outputting, at an output of the sense amplifier, a sensed output signal indicating a logic state of the data stored in the memory element in response to a sense amplifier enable signal;
operating a data latch having an input in a reset state in response to a latch signal indicating a first value to pass the sensed output signal of the sense amplifier to an output of the data latch, wherein the input of the data latch is coupled to the output of the sense amplifier to receive the sensed output signal; and
operating the data latch in a set state in response to the latch signal indicating a second value to store a data state of the sensed output signal and isolate the input of the data latch from the output of the sense amplifier;
wherein the latch signal is generated using a set-reset control circuit having an input to receive the sense amplifier enable signal and the generation of the latch signal is at least partially in response to the sense amplifier enable signal.

US Pat. No. 10,192,626

RESPONDING TO POWER LOSS

Micro Technology, Inc., ...

1. A method of operating a memory, comprising:obtaining information indicative of a data value stored in a particular memory cell of the memory;
programming additional data to the particular memory cell;
determining if a power loss to the memory is indicated while programming the additional data to the particular memory cell; and
if a power loss to the memory is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell;
wherein a resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.

US Pat. No. 10,192,624

NON-VOLATILE MEMORY DEVICE INCLUDING DECOUPLING CIRCUIT

Samsung Electronics Co., ...

1. A non-volatile memory device comprising:a memory cell array including a plurality of planes;
a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, the page buffer being configured to receive a bit line voltage control signal (BLSHF) via a first node;
a decoupling circuit connected to the first node, the decoupling circuit including at least one decoupling capacitor, the decoupling circuit being configured to execute charge sharing via the first node; and
a BLSHF generator connected to the first node;
wherein the BLSHF generator is configured to generate the BLSHF, and
the first node is between the decoupling circuit and the BLSHF generator.

US Pat. No. 10,192,623

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a memory unit; and
a control unit which controls the memory unit,
wherein the memory unit includes
a memory which is configured with a non-volatile memory device, and stores setting information necessary for rewriting,
a first control circuit which has a first register and a rewrite end flag, and
a power source circuit which generates a rewrite voltage,
wherein the control unit includes
a second control circuit which has a rewrite start flag,
a counter which measures a rewrite voltage application time based on the rewrite start flag and the rewrite end flag, and
a second register which stores a next rewrite voltage based on the rewrite voltage application time, and
wherein, when a command for rewriting the memory is received, the control unit reads the setting information necessary for rewriting from the memory, and writes it back to the first register.

US Pat. No. 10,192,622

SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE LINES

Cypress Semiconductor Cor...

1. A method for operating a memory device, comprising:providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, wherein the first and second memory cells are coupled to a common source line;
providing a second voltage to a second transistor of the first memory cell and a fourth transistor of the second memory cell; and
providing a third voltage to the first transistor of the first memory cell and the third transistor of the second memory cell.

US Pat. No. 10,192,621

FLASH MEMORY

Renesas Electronics Corpo...

1. A flash memory comprising:a memory cell array formed by a plurality of memory cells arranged in a matrix shape;
a plurality of word lines provided in each column of the memory cell array;
a first word line driver that outputs a first voltage group to each of the plurality of word lines; and
a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver, wherein the first word line driver includes:
a plurality of first level shifters, each level shifter provided to a corresponding word lines,
a plurality of inverters that drive outputs of the respective first level shifters, and
a plurality of first voltage relaxing transistors that relax voltages applied to a respective inverter, wherein:
the inverters are separately formed on a plurality of P wells provided individually in every unit of the memory cells targeted for memory data erasing at once,
the first word line driver includes:
a P well from the plurality of P wells, a plurality of second level shifters that supply a common potential to each source of an NMOS transistor of respective PMOS and NMOS transistors forming the respective inverters formed on the P well, and
a plurality of third level shifters that separately supply a potential to a plurality of N wells provided correspondingly to the plurality of P wells, wherein each of the first voltage relaxing transistors comprises an N channel type MOS transistor provided in an output stage of a respective inverter.

US Pat. No. 10,192,619

METHODS FOR PROGRAMMING 1-R RESISTIVE CHANGE ELEMENT ARRAYS

Nantero, Inc., Woburn, M...

1. A method for adjusting the resistive state of a single resistive change element within a resistive change element array, comprising:providing a resistive change element array, said resistive change element array comprising:
a plurality of word lines;
a plurality of bit lines; and
a plurality of resistive change elements, wherein each resistive change element has a first terminal and a second terminal and wherein said first terminal of each resistive change element is in electrical communication with a word line and said second terminal of each resistive change element is in electrical communication with a bit line;
floating all of said bit lines and all of said word lines within said resistive change element array;
selecting one of said plurality of resistive change elements;
driving the bit line in electrical communication with said selected resistive change element to a preselected voltage;
driving the word line in electrical communication with said selected resistive change element to ground;
discharging said bit line in electrical communication with said selected resistive change element through said selected resistive change element to provide a programming current through said selected resistive change element;
wherein said programming current adjusts the electrical resistance of said selected resistive change element from a first resistive state to a second resistive state.

US Pat. No. 10,192,616

OVONIC THRESHOLD SWITCH (OTS) DRIVER/SELECTOR USES UNSELECT BIAS TO PRE-CHARGE MEMORY CHIP CIRCUIT AND REDUCES UNACCEPTABLE FALSE SELECTS

WESTERN DIGITAL TECHNOLOG...

1. A memory device, comprising:a word line;
a bit line disposed perpendicular to the word line;
a memory element disposed between the word line and the bit line;
a select element coupled to the memory element, wherein the select element is disposed adjacent to the bit line wherein the select element is selected from the group consisting of an ovonic threshold switch (OTS), a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a Field Assisted Superlinear Threshold selector (FAST);
a wire that at least partly overlaps the word line, the wire coupled with a voltage source providing a predefined unselect bias voltage; and
a connecting element comprising an undoped polysilicon material disposed between the word line and the wire wherein the connecting element comprises a second memory element and a second select element, wherein the second select element is constructed from one of a RRAM and a MRAM material.

US Pat. No. 10,192,613

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first memory module;
a second memory module; and
a third memory module,
each of the memory modules having a memory cell array including a plurality of memory cells,
each of the memory modules having a first state to consume less electric power than in a second state, and
the first memory module having a greater number of memory cells than the second memory module;
a first control signal line coupled with the first memory module and the second memory module to transmit a control signal for controlling the first state and the second state to the first memory module and the second memory module;
a second control signal line coupled with the first memory module and the third memory module to transmit the control signal from the first memory module to the third memory module;
wherein a first wiring is disposed in the first memory module, and coupled between the first control signal line and the second control signal line for transmitting the control signal from the first control signal line to the second control signal line via the first wiring, and
wherein the first wiring is coupled with a first MOS transistor in the first memory module.

US Pat. No. 10,192,611

SENSING CIRCUIT, SET OF PRE-AMPLIFIERS, AND OPERATING METHOD THEREOF

NATIONAL TSING HUA UNIVER...

1. A set of pre-amplifiers of a sense amplifier, comprising:a first pre-amplifier, coupled to a first input terminal of the sense amplifier; and
a second pre-amplifier, coupled to a second input terminal of the sense amplifier;
wherein the first pre-amplifier and the second pre-amplifier respectively performs a discharging operation to discharge the first input terminal and the second input terminal of the sense amplifier after the first input terminal and the second input terminal of the sense amplifier are charged to a predetermined voltage; and
one of the first pre-amplifier and the second pre-amplifier amplifies a voltage difference between the first input terminal and the second input terminal of the sense amplifier by terminating the discharging operation of another of the first pre-amplifier and the second pre-amplifier;
wherein the first pre-amplifier comprises:
a first switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch is coupled to the predetermined voltage, the second terminal of the first switch is coupled to the first input terminal of the sense amplifier, and the control terminal of the first switch receives a pre-charge signal;
a second switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the first switch and the control terminal of the second switch is coupled to the second input terminal of the sense amplifier;
a third switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled to the second terminal of the second switch, the second terminal of the third switch is coupled to a ground, and a control terminal of the third switch receives an initializing signal; and
a first capacitor, having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the second terminal of the second switch.

US Pat. No. 10,192,608

APPARATUSES AND METHODS FOR DETECTION REFRESH STARVATION OF A MEMORY

Micron Technology, Inc., ...

1. An apparatus comprising:a plurality of memory cells; and
a control circuit configured to monitor refresh request commands and to perform an action that prevents unauthorized access to data stored at the plurality of memory cells in response to detection that timing of the refresh request commands has failed to meet a refresh timing limit.

US Pat. No. 10,192,606

CHARGE EXTRACTION FROM FERROELECTRIC MEMORY CELL USING SENSE CAPACITORS

MICRON TECHNOLOGY, INC., ...

1. A method of operating a ferroelectric memory cell, comprising:selecting the ferroelectric memory cell that is in electronic communication with a digit line;
activating a switching component that is in electronic communication with the digit line to virtually ground the digit line, wherein activating the switching component comprises applying a charging voltage to a capacitor when the switching component and the capacitor are connected in parallel;
virtually grounding the digit line; and
activating a sense amplifier that is in electronic communication with the digit line based at least in part on virtually grounding the digit line.

US Pat. No. 10,192,605

MEMORY CELLS AND SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC MATERIALS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a ferroelectric material comprising hafnium oxide, zirconium oxide, or a combination thereof, the ferroelectric material configured to exhibit asymmetric characteristics and configured to switch from a first polarization state to a second polarization state responsive to exposure to a first bias voltage and configured to change from the second polarization state to the first polarization state responsive to exposure to a negative bias voltage having a different magnitude than the positive bias voltage.

US Pat. No. 10,192,604

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device comprising:a cell array including a plurality of memory cells;
a sense amplifier reading data of the memory cell;
write drivers writing data to the memory cell;
a sub cell area including the cell array, the sense amplifier, and the write driver;
a memory area including a plurality of sub cell areas; and
a control circuit, when performing a first operation of supplying a first voltage to a selected sub cell area, supplying first write data to the sub cell area which performs the first operation, for selecting the sub cell area as a target of the first operation.

US Pat. No. 10,192,603

METHOD FOR CONTROLLING A SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method for controlling a semiconductor storage device which comprises:a cell array including a plurality of memory cells;
a sense amplifier reading data of the memory cell;
a write driver writing data to the memory cell;
a sub cell area including the cell array, the sense amplifier, and the write driver;
a memory area including a plurality of sub cell areas; and
a control circuit controlling the sense amplifier and the write driver,
the method comprising causing the control circuit to supply first write data to the sub cell area which performs a first operation of supplying a first voltage to a selected sub cell area.

US Pat. No. 10,192,596

APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME

Micron Technology, Inc., ...

1. An apparatus, comprising:an input-output control circuit;
a memory array configured to store data, the memory array further including signal lines for accessing memory of the memory array;
control logic coupled to the input-output control circuit and the memory array, the control logic configured to provide, in a first mode, internal control signals responsive to receiving a read command that controls activation of a charge pump circuit to develop a full pumped voltage prior to driving signal lines to a target signal line voltage based on the full pumped voltage, and
wherein the control logic is configured to provide, in a second mode, internal control signals prior to receiving a read command that controls the charge pump circuit to develop a ready pumped voltage that is less than the full pumped voltage, the control logic further configured to provide control signals to control the ready pumped voltage based on temperature compensation information of the memory array.

US Pat. No. 10,192,595

LEVEL SHIFTER AND OPERATION METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A level shifter, comprising:an input control unit suitable for outputting an output control signal according to a pulse width of a data signal and a pulse width of an input control signal; and
an output control unit suitable for controlling an output driving signal according to the output control signal.

US Pat. No. 10,192,594

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a booster circuit configured to boost an input voltage and generate a first boosted voltage;
a voltage hold circuit configured to hold a second boosted voltage having a smaller absolute value than the first boosted voltage;
a first output terminal configured to output the first boosted voltage as first output;
a second output terminal configured to output the second boosted voltage as second output;
a first switch that is placed between the first output terminal and the second output terminal; and
a control circuit configured to generate a switch signal for switching the first switch from close to open in response to an output voltage of the booster circuit reaching a hold voltage level set to the voltage hold circuit,
wherein during a first period when the switch signal indicates close of the first switch, the voltage hold circuit is further configured to increase or decrease a voltage value of the second boosted voltage to be output in accordance with the output voltage of the booster circuit, and during a second period at a point in time when the switch signal indicates open of the first switch, the second boosted voltage has a particular value, and the voltage hold circuit is further configured to maintain the particular voltage value of the second boosted voltage after the first switch is open,
wherein the voltage hold circuit includes:
a plurality of voltage hold circuits,
the first switch includes a plurality of first switches corresponding to the plurality of voltage hold circuits, and
the control circuit outputs the switch signal to a pair of the first switch and the voltage hold circuit to which the hold voltage level corresponding to a detected voltage value of the output voltage of the booster circuit is set each time the output voltage of the booster circuit reaches a plurality of hold voltage levels respectively set to the plurality of voltage hold circuits, and
wherein the control circuit includes:
a first resistor and a second resistor that are connected in series between a boost node at which the output voltage of the booster circuit is generated and a bias terminal through which a specified voltage is supplied,
a third resistor that is connected in series with the first resistor and the second resistor and includes a plurality of resistors connected in parallel,
a comparator configured to compare a detection target voltage generated at a connection node between the first resistor and the second resistor with a preset reference voltage, and
a detection voltage control circuit configured to enable any one of a plurality of switch signals in response that an output of the comparator becomes enabled, and
the detection voltage control circuit switches a resistor to be short-circuited among the plurality of resistors included in the third resistor at the same time as enabling any one of the plurality of switch signals.

US Pat. No. 10,192,593

RECEPTION CIRCUIT FOR REDUCING CURRENT AND ELECTRONIC APPARATUS INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. An electronic apparatus comprising:a system control circuit configured to generate a plurality of first control signals individually provided to a plurality of chips and a second control signal commonly and simultaneously provided to the plurality of chips; and
the plurality of chips each including a reception circuit configured to generate a reception control signal in response to the first control signal and selectively receive the second control signal in response to the reception control signal,
wherein the reception circuit comprises:
a controller configured to generate the reception control signal based on the first control signal;
a first buffer configured to receive the second control signal; and
a delay circuit configured to receive the second control signal from the first buffer in response to the reception control signal and provide the second control signal to other elements in the chips.

US Pat. No. 10,192,591

MEMORY DEVICES HAVING SPECIAL MODE ACCESS

Micron Technology, Inc., ...

1. A memory device comprising a register, a memory array, and a serial interface controller configured to receive and operate using a serial message to access the register that controls operation of the memory array by storing bits, the serial message having a format that comprises:a command field of the serial message configured to enable the serial interface controller to access the register;
a register address field of the serial message immediately following the command field indicating an address of the register; and
a data field of the serial message immediately following the register address field;
wherein the serial interface controller is configured to receive the serial message, wherein the command field of the serial message comprises a command that the serial interface controller is configured to interpret as enabling write access to a special mode enable register of the memory device, wherein the address of the register is configured to identify the special mode enable register, wherein the data field of the serial message comprises data to be written into the special mode enable register that is configured, when written into the special mode enable register, to cause the memory device to operate according to a special mode of operation, wherein the special mode of operation comprises a one time programmable (OTP) access mode, a parameter page access mode, or a block lock access mode, or any combination thereof.

US Pat. No. 10,192,587

MOVIE ADVERTISING PLAYBACK SYSTEMS AND METHODS

Open Text SA ULC, Halifa...

1. A method of video production, comprising:receiving, in playback of a video, a command from a viewer to advance the play of the video, wherein advancement of the play of the video skips a proxy advertisement in the video, the receiving performed by a video player device having a transcoder embodied in at least one physical unit;
responsive to the command from the viewer to advance the play of the video, determining a location in the video to resume playback of the video, the determining performed by the video player device;
moving the proxy advertisement to the location in the video determined by the video player device, the moving performed by the video player device, the proxy advertisement including an ad request;
sending the ad request to an advertisement server, the sending performed by the video player device;
receiving an advertisement from the advertisement server, the receiving performed by the video player device; and
delivering the advertisement received from the advertisement server to the location in the video indicated by the proxy advertisement, the delivering performed by the video player device, the video player device to play the advertisement at the location.

US Pat. No. 10,192,584

COGNITIVE DYNAMIC VIDEO SUMMARIZATION USING COGNITIVE ANALYSIS ENRICHED FEATURE SET

International Business Ma...

1. A method of providing a summary of a media production comprising:receiving the media production in computer-readable form, by executing first instructions in a computer system;
dividing the media production into original segments having respective time stamps indicating a time order of the original segments, by executing second instructions in the computer system;
conducting a cognitive analysis of each of the original segments to extract at least one cognitive feature associated with each original segment, by executing third instructions in the computer system;
grouping the original segments into multiple clusters based on the cognitive features by identifying one or more predominant features for each given cluster based on segments making up the given cluster, by executing fourth instructions in the computer system;
selecting a representative segment for each of the clusters based on one or more selection factors which include a distance of a given segment to a centroid of its corresponding cluster, an emotion level of the given segment, an audio uniqueness of the given segment, or a video uniqueness of the given segment wherein the representative segment for a given cluster corresponds to one of the original segments within the given cluster, by executing fifth instructions in the computer system; and
combining the representative segments in time order according to their time stamps to form a media summary, by executing sixth instructions in the computer system.

US Pat. No. 10,192,581

REPRODUCING DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A reproducing device capable of reproducing content from an optical information recording medium in which the content is recorded in a form of a pit group including one or more pits shorter than an optical system resolution limit of the reproducing device, comprising:an irradiation section for irradiating the optical information recording medium with reproduction light;
a conversion section for converting, into reproduction signal indicative of the content, light which reflected off the optical information recording medium;
a signal quality evaluating section for evaluating quality of the reproduction signal converted by the conversion section; and
a spherical aberration correcting section for correcting a spherical aberration caused by the irradiation section, by using a result of evaluation of the quality of the reproduction signal which quality has been evaluated by the signal quality evaluating section; wherein
the signal quality evaluating section is an i-MLSE (Integrated-Maximum Likelihood Sequence Estimation) detecting section for (a) detecting an i-MLSE which is an evaluation index for evaluating a signal characteristic of the reproduction signal and (b) evaluating quality of the reproduction signal,
the optical information recording medium has a BCA (Burst Cutting Area) recording region, and
the reproducing device further comprises a BCA reproduction control section for reproducing information recorded in the BCA recording region.

US Pat. No. 10,192,574

DEVICES INCLUDING A DIFFUSION BARRIER LAYER

Seagate Technology LLC, ...

1. A device having an air bearing surface (ABS), the device comprising:a write pole;
a near field transducer (NFT) comprising a peg and a disc, wherein the peg is at the ABS of the device;
a heat sink positioned adjacent the disc of the NFT;
a dielectric gap positioned adjacent the peg of the NFT at the ABS of the device;
a conformal diffusion barrier layer, wherein the conformal diffusion barrier layer forms at least one angle that is not greater than 135°; and
a peg coupler layer,
wherein the conformal diffusion barrier layer is positioned adjacent the write pole,
the peg coupler layer is positioned between the conformal diffusion barrier layer and the dielectric gap, the disc and the heat sink, and
the dielectric gap and the disc are positioned between the peg coupler layer and the heat sink and the peg.

US Pat. No. 10,192,573

DEVICES INCLUDING METAL LAYER

Seagate Technology LLC, ...

1. A device having an air bearing surface (ABS), the device comprising:a write pole;
a near field transducer (NFT) comprising a peg and a disc, wherein the peg is at the ABS of the device;
a metallic layer positioned over at least the peg of the NFT at the ABS, the metallic layer comprising: iridium (Ir), chromium (Cr), tin (Sn), platinum (Pt), or combinations thereof;
an adhesion layer comprising silicon (Si), chromium (Cr), titanium (Ti), tantalum (Ta), zirconium (Zr), niobium (Nb), neodymium (Nd), hafnium (Hf), nickel (Ni), or combinations thereof; and
an overcoat positioned over at least the metallic layer,
wherein the adhesion layer is positioned between at least the metallic layer and the overcoat layer.

US Pat. No. 10,192,572

MAGNETIC RECORDING HEAD WITH SPECIFIED THICKNESS AND SATURATION MAGNETIC FLUX DENSITY PRODUCTS FOR STO MAGNETIC LAYERS

Kabushiki Kaisha Toshiba,...

1. A magnetic recording and reproducing device, comprising:a magnetic recording head; and
a controller,
the magnetic recording head including:
a magnetic pole;
a shield;
a stacked body including
a first magnetic layer provided between the magnetic pole and the shield,
a second magnetic layer provided between the first magnetic layer and the shield, and
an intermediate layer provided between the first magnetic layer and the shield, the intermediate layer being non-magnetic; and
a first non-magnetic layer provided between the second magnetic layer and the shield, the first non-magnetic layer contacting the shield and the second magnetic layer,
the first magnetic layer having a first thickness and a first saturation magnetic flux density, the first thickness being along a first direction from the second magnetic layer toward the first magnetic layer,
the second magnetic layer having a second thickness along the first direction and a second saturation magnetic flux density, and
a second product of the second thickness and the second saturation magnetic flux density being larger than a first product of the first thickness and the first saturation magnetic flux density,
the controller is configured to flow a current in the stacked body from the second magnetic layer toward the first magnetic layer,
wherein
in a first state, a first magnetic pole magnetic field is generated from the magnetic pole, the first magnetic pole magnetic field having a component along the first direction,
in a second state, a second magnetic pole magnetic field is generated from the magnetic pole, the second magnetic pole magnetic field having a component along a second direction from the first magnetic layer toward the second magnetic layer, and
in the first state, magnetization of the first magnetic layer has a component along the second direction.

US Pat. No. 10,192,570

MAGNETIC DISK DEVICE AND WRITE METHOD

Kabushiki Kaisha Toshiba,...

1. A magnetic disk device comprising:a disk;
a head configured to write data on the disk; and
a controller configured to
generate a target trajectory of the head in a circumferential direction for writing to a plurality of sectors in a current track, wherein the target trajectory is based on an actual trajectory of the head for writing to a plurality of sectors in a previously written track that is adjacent to the current track;
determine that the previously written track is discontinuous between an initial sector of the previously written track and an end sector of the previously written track by a radial offset;
based on the radial offset, generate a corrected trajectory for writing the plurality of sectors in the current track; and
control a position of the head in a radial direction based on the corrected trajectory while writing to the plurality of sectors in the current track.

US Pat. No. 10,192,569

INFORMING A SUPPORT AGENT OF A PARALINGUISTIC EMOTION SIGNATURE OF A USER

INTUIT INC., Mountain Vi...

1. A computer-implemented method for assisting a support agent assigned to interact with a user during a support encounter, comprising:receiving, at a computing device, an audio stream comprising audio of a user interacting with an application;
evaluating the audio stream to identify a collection of paralinguistic information present in the audio stream, wherein the paralinguistic information comprises a set of descriptors characterizing acoustic aspects of the audio that are distinct from verbal content of the audio;
determining, from the paralinguistic information, one or more attribute measures associated with the user interacting with the application; and
upon receiving a request to initiate a support encounter:
generating, before a support agent assigned to handle the support encounter interacts with the user and based on evaluating at least one of the attribute measures with an uplift model, a set of activities for the support agent to use when interacting with the user that increases a likelihood of achieving a specified outcome for the support encounter;
providing information content on a support agent interface before the support agent interacts with the user, the information content comprising the one or more attribute measures determined from the paralinguistic information and the generated set of activities, wherein the one or more attribute measures comprises an emotional state of the user responsive to at least one content item provided by the application; and
generating, before the support agent interacts with the user, a mockup of the application on the support agent interface, the mockup comprising the at least one content item.

US Pat. No. 10,192,568

AUDIO SOURCE SEPARATION WITH LINEAR COMBINATION AND ORTHOGONALITY CHARACTERISTICS FOR SPATIAL PARAMETERS

Dolby Laboratories Licens...

1. A method of audio source separation from audio content, the method comprising:determining a spatial parameter of an audio source, wherein the determining comprises:
determining a power spectrum parameter of the audio source based on one of a linear combination characteristic of the audio source and an orthogonality characteristic of two or more audio sources to be separated in the audio content;
updating the power spectrum parameter based on the other of the linear combination characteristic and the orthogonality characteristic; and
determining the spatial parameter of the audio source based on the updated power spectrum parameter; and
separating the audio source from the audio content based on the spatial parameter.

US Pat. No. 10,192,565

CROSS PRODUCT ENHANCED HARMONIC TRANSPOSITION

Dolby International AB, ...

1. A system for decoding an audio signal, the system comprising:a core decoder for decoding a low frequency component of the audio signal;
an analysis filter bank for providing a plurality of analysis subband signals of the low frequency component of the audio signal;
a subband selection reception unit for receiving information associated with a fundamental frequency ? of the audio signal, and for selecting, in response to the information, a first analysis subband signal and a second analysis subband signal from the plurality of analysis subband signals;
a non-linear processing unit to generate a synthesis subband signal from the first analysis subband signal and the second analysis subband signal by modifying the phase of the first analysis subband signal and modifying the phase of the second analysis subband signal, and by combining the phase-modified first analysis subband signal and the phase-modified second analysis subband signal; and
a synthesis filter bank for generating a high frequency component of the audio signal from the synthesis subband signal;
wherein the information associated with the fundamental frequency ? of the audio signal is received in an encoded bit stream.

US Pat. No. 10,192,563

APPARATUS AND METHOD FOR SCREEN RELATED AUDIO OBJECT REMAPPING

Fraunhofer-Gesellschaft z...

1. An apparatus for generating loudspeaker signals, comprising:an object metadata processor, and
an object renderer,
wherein the object renderer is configured to receive an audio object,
wherein the object metadata processor is configured to receive metadata, comprising an indication on whether the audio object is screen-related, and further comprising a first position of the audio object,
wherein the object metadata processor is configured to calculate a second position of the audio object depending on the first position of the audio object and depending on a size of a screen if the audio object is indicated in the metadata as being screen-related,
wherein the object renderer is configured to generate the loudspeaker signals depending on the audio object and depending on position information,
wherein the object metadata processor is configured to feed the first position of the audio object as the position information into the object renderer if the audio object is indicated in the metadata as being not screen-related, and
wherein the object metadata processor is configured to feed the second position of the audio object as the position information into the object renderer if the audio object is indicated in the metadata as being screen-related.

US Pat. No. 10,192,562

CROSS PRODUCT ENHANCED SUBBAND BLOCK BASED HARMONIC TRANSPOSITION

Dolby International AB, ...

1. A system configured to generate a time stretched and/or frequency transposed signal from an input signal, the system comprising one or more processing elements that:derive a number Y?1 of analysis subband signals from the input signal, wherein each analysis subband signal comprises a plurality of complex-valued analysis samples, each having a phase and a magnitude;
generate a synthesis subband signal from the Y analysis subband signals using a subband transposition factor Q and a subband stretch factor S, at least one of Q and S being greater than one by:
forming Y frames of L input samples, each frame being extracted from said plurality of complex-valued analysis samples in an analysis subband signal and the frame length being L>1, wherein at least one of the L input samples is derived by interpolating two or more of the plurality of complex-valued analysis samples;
applying a block hop size of h samples to said plurality of analysis samples, prior to forming a subsequent frame of L input samples, thereby generating a sequence of frames of input samples;
generating, on the basis of Y corresponding frames of input samples formed by the block extractor, a frame of processed samples by determining a phase and magnitude for each processed sample of the frame, wherein, for at least one processed sample:
i) the phase of the processed sample is based on the respective phases of the corresponding input sample in each of the Y frames of input samples; and
ii) the magnitude of the processed sample is determined as a mean value of the magnitude of the corresponding input sample in a first frame of the Y frames of input samples and the magnitude of the corresponding input sample in a second frame of the Y frames of input samples; and
determining the synthesis subband signal by overlapping and adding the samples of a sequence of frames of processed samples; and
generate the time stretched and/or frequency transposed signal from the synthesis subband signal, wherein the system is operable at least for Y=2.

US Pat. No. 10,192,561

AUDIO PROCESSOR AND METHOD FOR PROCESSING AN AUDIO SIGNAL USING HORIZONTAL PHASE CORRECTION

Fraunhofer-Gesellschaft z...

1. An audio processor for processing an audio signal comprising:an audio signal phase measure calculator configured for calculating a phase measure of an audio signal for a time frame;
a target phase measure determiner for determining a target phase measure for said time frame;
a phase corrector configured for correcting phases of the audio signal for the time frame using the calculated phase measure and the target phase measure to achieve a processed audio signal,
wherein the phase corrector is configured for forming a vector of deviations, wherein a first element of the vector refers to a first deviation for the first subband of the plurality of subbands and a second element of the vector refers to a second deviation for the second subband of the plurality of subbands from a previous time frame to a current time frame, and wherein the phase corrector is configured to apply the vector of deviations to the phases of the audio signal, wherein the first element of the vector is applied to a phase of the audio signal in a first subband of a plurality of subbands of the audio signal and the second element of the vector is applied to a phase of the audio signal in a second subband of the plurality of subbands of the audio signal, or
wherein the target phase measure determiner is configured for achieving a fundamental frequency estimate for a time frame, for calculating a frequency estimate for each subband of the plurality of subbands of the time frame using the fundamental frequency for the time frame, for forming a vector of frequency estimates for each subband of the plurality of subbands, wherein the first element of the vector refers to a frequency estimate for a first subband and a second element of the vector refers to a frequency estimate for a second subband, and for calculating the frequency estimate using multiples of the fundamental frequency, wherein the frequency estimate of the current subband is that multiple of the fundamental frequency which is closest to the center of the subband, or wherein the frequency estimate of the current subband is a border frequency of the current subband if none of the multiples of the fundamental frequency are within the current subband.

US Pat. No. 10,192,560

ROBUST SPECTRAL ENCODING AND DECODING METHODS

Digimarc Corporation, Be...

1. A device for decoding a digital watermark embedded in an audio signal, wherein the digital watermark is embedded in the audio signal by adjusting signal values, the device comprising:a memory in which is stored blocks of the audio signal;
a processor in communication with the memory to obtain blocks of the audio signal, the processor configured with instructions to:
perform an initial synchronization of the digital watermark, distorted due to time scale change, by converting blocks of the audio to frequency domain data, pre-filtering the frequency domain data to produce first pre-filtered blocks, summing the first pre-filtered blocks to produce a first accumulated block, the first pre-filtered blocks being selected over a sufficiently long block of audio such that plural instances of watermark signal representing the same code at different time locations are accumulated, and correlating the first accumulated block with a pattern to detect a time scale of an embedded code signal; and
perform decoding of variable code data of the digital watermark at the detected time scale by correlating phase of the audio signal at the detected shift with a data signal pattern, wherein the processor is configured with instructions to decode the variable code data by correlating phase of the audio signal with a synchronization code signal to identify a start position of the variable code, and correlating phase of the audio signal with data code signals to detect data code signals encoded as the variable code data of the digital watermark.

US Pat. No. 10,192,558

ADAPTIVE GAIN-SHAPE RATE SHARING

Telefonaktiebolaget LM Er...

1. A method in an encoder for allocating bits to a gain adjustment quantizer and a shape quantizer to be used for encoding a gain shape vector for a received audio signal, the method comprising:determining a current bitrate and a value for a first signal property of the audio signal;
identifying a bit allocation for the gain adjustment quantizer and the shape quantizer for the determined current bitrate and the determined value for the first signal property, by using information from a table indicating a number of bits to be allocated to the gain adjustment quantizer and the shape quantizer for each of a plurality of combinations of bitrate and values for the first signal property; and
applying the identified bit allocation when encoding the gain shape vector.

US Pat. No. 10,192,555

DYNAMIC SPEECH RECOGNITION DATA EVALUATION

MICROSOFT TECHNOLOGY LICE...

1. A method of dynamically providing speech recognition data from a client computing device to a server computing device, the method comprising:receiving audio input at the client computing device;
processing the audio input to generate the speech recognition data;
determining a first estimated confidence level for a first identified portion of the speech recognition data comprising a first feature vector, wherein the first estimated confidence level exceeds a predetermined confidence threshold that corresponds to a valid result;
based on determining that the first estimated confidence level corresponds to the valid result, continuing to process the speech recognition data with the first identified portion;
determining a second estimated confidence level for a second identified portion of the speech recognition data comprising a second feature vector, wherein the second estimated confidence level also exceeds the predetermined confidence threshold that corresponds to the valid result;
identifying at least one statistically improbable characteristic associated with the second feature vector;
determining that the client computing device comprises a first feature extractor;
comparing the first feature extractor of the client computing device with a second feature extractor utilized by the server computing device;
based on comparing the first feature extractor of the client computing device with the second feature extractor utilized by the server computing device, determining that the second feature extractor of the server computing device is different from the first feature extractor;
based on (1) determining the second estimated confidence level corresponds to the valid result, (2) identifying the at least one statistically improbable characteristic, and (3) determining that the server computing device comprises the second feature extractor different from the first feature extractor, providing the second feature vector to the server computing device for an evaluation of the second feature vector by the second, different feature extractor.

US Pat. No. 10,192,550

CONVERSATIONAL SOFTWARE AGENT

Microsoft Technology Lice...

1. A computer system comprising:an input configured to receive voice input from a user;
an automatic speech recognition (ASR) system for identifying individual words in the voice input, the ASR system configured to generate in memory a set of one or more words it has identified in the voice input, and update the set each time it identifies a new word in the voice input by adding the new word to the set;
a speech detection module configured to detect speech activity in the voice input, prevent a speech inactivity interval from commencing until a grammatically complete sentence is detected in the voice input, cause the speech inactivity interval to commence when the grammatically complete sentence is detected in the speech input, and determine whether the ASR system has identified any more words in the voice input during the speech inactivity interval; and
a response module configured to generate a response for output based on the set of identified words, in response to the detection of an end of the speech inactivity interval, the response module configured to output the generated response after the speech inactivity interval has ended and only if the ASR system has not identified any more words in the voice input during the speech inactivity interval such that the generated response is not output if one or more words are identified in the voice input during the speech inactivity interval.

US Pat. No. 10,192,548

METHOD AND APPARATUS FOR EVALUATING TRIGGER PHRASE ENROLLMENT

Google Technology Holding...

1. A computer-implemented method comprising:during a trigger phrase enrollment process:
receiving, at a speech recognition-enabled electronic device, a first audio signal corresponding to a user of the speech recognition-enabled electronic device speaking a trigger phrase, the first audio signal comprising a first number of frames having a measure of noise variability of background noise exceeding a noise variability threshold;
when a count of the first number of frames in the first audio signal satisfies a frame number threshold, prompting, by the speech recognition-enabled electronic device, the user to speak the trigger phrase again;
receiving, by the speech recognition-enabled electronic device, a second audio signal corresponding to the user speaking the trigger phrase again, the second audio signal comprising a second number of frames having the measure of noise variability of background noise exceeding the noise variability threshold; and
when a count of the second number of frames in the second audio signal dissatisfies the frame number threshold, training, by the speech recognition-enabled electronic device, a trigger phrase model with the second audio signal corresponding to the user speaking the trigger phrase again; and
after the trigger phrase enrollment process:
receiving, at the speech recognition-enabled electronic device and while the speech recognition-enabled electronic device is in a sleep mode, a third audio signal including an utterance of the trigger phrase spoken by the user; and
detecting, by the speech recognition-enabled electronic device and using the trigger phrase model trained during the trigger phrase enrollment process, the utterance of the trigger phrase in the third audio signal, the trigger phrase when detected in the third audio signal causing the speech recognition-enabled electronic device to wake from the sleep mode, the sleep mode comprising a power-saving mode of operation in which one or more parts of the speech recognition-enabled electronic device are in a low-power state or powered off.

US Pat. No. 10,192,541

SYSTEMS AND METHODS FOR GENERATING SPEECH OF MULTIPLE STYLES FROM TEXT

Nuance Communications, In...

1. A method for use in a text-to-speech system comprising a computer-implemented linguistic analysis component operative to generate a phonetic transcription based upon input text, a speech base comprising speech unit recordings associated with a plurality of styles of speech, and at least one computer-implemented speech generation component operative to generate output speech from stored speech unit recordings based at least in part on the phonetic transcription, the method comprising acts of:(A) receiving, by the linguistic analysis component, input text produced by a text-producing application, wherein the text produced by a text-producing application comprises a speech style indication indicating a style of speech to be output by the text-to-speech system for an associated segment of the input text;
(B) generating, by the linguistic analysis component, a phonetic transcription based at least in part on the input text, the phonetic transcription specifying a first style of speech of the plurality of styles of speech to be output by the at least one speech generation component for the segment of the input text; and
(C) generating, by the at least one speech generation component, output speech based at least in part on the phonetic transcription generated in the act (B), wherein the generating comprises the at least one speech generation component selecting, from the speech unit recordings in the speech base, speech unit recordings associated with a second style of speech of the plurality of styles of speech, the second style of speech being different than the first style of speech, and concatenating the selected speech unit recordings to generate output speech in the first style.

US Pat. No. 10,192,534

PERCUSSION INSTRUMENT

YAMAHA CORPORATION, Shiz...

1. A percussion instrument comprising:a shell having a wall portion and at least one opening;
a head attached to the shell and overlying the at least one opening of the shell; and
a speaker provided inside of the shell and oriented to output sound having a main direction of propagation towards the wall portion of the shell according to an input signal.

US Pat. No. 10,192,533

CONTROLLER AND SYSTEM FOR VOICE GENERATION BASED ON CHARACTERS

Yamaha Corporation, Hama...

1. A manually-operable controller for a voice generation device including a processor, the voice generation device being configured to generate a voice on the basis of one or more designated characters in a pre-defined character string and a pitch designated by a pitch selector manual-operator, the manually-operable controller comprising:a character selector manual-operator located at a first position on the manually-operable controller and structurally dedicated to be operable by a user, during an outputting of an output voice from a sound output circuit, to designate in real time the one or more designated characters in the pre-defined character string; and
a voice control manual-operator located at a second position on the manually-operable controller and structurally dedicated to be operable by the user, during the generation of the generated voice, to control in real time a state of the voice generated on the basis of the one or more characters designated by the character selector manual-operator and the pitch designated by the pitch selector manual-operator,
wherein the character selector manual-operator includes a separation selector manual-operator for instructing that a voice of a character group, comprising one or more characters, included in the character string be separated into a plurality of syllables and that a voice of the separated syllables be generated at different timings.

US Pat. No. 10,192,532

TELESCOPING MUSICAL DRUM

18. A telescoping musical drum, comprising:at least two truncated, conical annular bodies, which can be extended into overlapping end-to-end positions, wherein the open-locking mechanism is accomplished via the increasingly tight friction fit created by extending such concentric conical bodies, working in combination with a ridge or ridges surrounding the lower or upper inner or outer edge of each of said annular bodies that may fit into a groove surrounding the corresponding lower inner or upper outer edge of said adjacent annular body.

US Pat. No. 10,192,530

MUSICAL INSTRUMENT PITCH CHANGER

1. A pitch changing apparatus, comprising:a bender lever pivotally secured to a musical instrument configured to move between unengaged and engaged positions;
a bender saddle secured to the musical instrument configured to vary the tension in a string on the musical instrument in response to movement of the bender lever between the unengaged and engaged positions, wherein the bender saddle further comprises a head with a cam portion and a bore therethrough, said bore configured to receive a string threaded through the bore and wrapped around a portion of the cam section;
a string mount configured to secure the bender saddle to a first selected string in a first bending configuration or to a second selected string in a second bending configuration; and
wherein the bender saddle is configured to move between the first selected string and the second selected string of the musical instrument.

US Pat. No. 10,192,529

ELECTRONIC APPARATUS, FRAMES PER SECOND DECISION METHOD, AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM THEREOF

MediaTek, Inc., Hsinchu ...

1. An electronic apparatus, comprising:a circuit, being configured to calculate a first movement value according to a plurality of first data corresponding to a first frame for display and a plurality of second data corresponding to a second frame for display, and calculate a first target Frames Per Second (FPS) for displaying a plurality of third frames according to the first movement value and a first number of frame time between the first frame and the second frame,
wherein the first movement value indicates a movement distance of one or more objects between the first frame and the second frame, and the first number of frame time indicates a time measurement between the first frame and the second frame, and
wherein the circuit calculates the first target FPS by dividing the first movement value by the first number of frame time, and wherein the greater the first target FPS, the faster the plurality of third frames are displayed.

US Pat. No. 10,192,525

SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR GENERATING ONE OR MORE VALUES FOR A SIGNAL PATCH USING NEIGHBORING PATCHES COLLECTED BASED ON A DISTANCE DYNAMICALLY COMPUTED FROM A NOISE DISTRIBUTION OF THE SIGNAL PATCH

NVIDIA CORPORATION, Sant...

1. A non-transitory computer readable medium storing code executable by a processor to perform a method comprising:identifying a reference patch from a signal;
determining a noise distribution in the reference patch;
computing a reference distance based on the noise distribution in the reference patch;
collecting from the signal neighbor patches closest to the computed reference distance from the reference patch, by
(a) ordering possible neighbor patches to the reference patch by distance, and collecting a predefined number (N) of the ordered neighbor patches that are closest to the reference distance from the reference patch, or
(b) determining a range for the reference distance, the range defined by a minimum distance from the reference patch that is a particular variance of the reference distance in a negative direction and a maximum distance from the reference patch that is the particular variance of the reference distance in a positive direction, and collecting all neighbor patches within the range;
processing the collected neighbor patches with the reference patch to generate one or more values for the reference patch.

US Pat. No. 10,192,522

MULTI-LAYERED DISPLAY DEVICE

YAZAKI CORPORATION, Mina...

1. A display device comprising:a first display surface configured to display vehicle information in a display area and include a segment bar which transmits light;
a second display surface configured to be disposed facing the first display surface and to transmit light, the second display surface including a drawing pattern drawn across an inside and an outside of the display area when seen from a direction in which the second display surface is stacked on the first display surface, and be able to switch to a displayed state in which the drawing pattern is displayed and a hidden state in which the drawing pattern is hidden;
a dial plate disposed between the first display surface and the second display surface; and
a circuit board, wherein
the circuit board includes a plurality of light sources facing a side of the second display surface in a direction substantially perpendicular to a depth direction in which the second display surface transmits light from a back face side to a front face side,
the light sources are configured to transmit light through the side of the second display surface in a direction substantially perpendicular to the depth direction,
the display area is an area exposed through an opening provided in the dial plate, the display device displays information by the first display surface and the second display surface, and
a part of the drawing pattern is disposed over the opening such that the part of the drawing pattern overlaps the first display surface in the direction and the part of the drawing pattern is superimposed on the segment bar and serves as an indication part indicated by the segment bar.

US Pat. No. 10,192,520

BACKLIGHT UNIT, DISPLAY PANEL AND DISPLAY DEVICE

SHANGHAI TIANMA MICRO-ELE...

1. A backlight unit, comprising:a light source having a plurality of light-emitting units that emit light in at least three different colors;
only one light guide plate having N preset regions, where N is a positive integer, and N>1; and
a backlight control unit controlling the light-emitting units to provide light to the preset regions in the only one light guide plate,
wherein:
the only one light guide plate has a light incidence side and a side surface opposite to the light incidence side, and the N preset regions continuously extend from the light incidence side to the side surface of the only one light guide plate;
all light-emitting units in the light source are disposed at the light incidence side of the only one light guide plate, and the light emitted from the plurality of light-emitting units enters the N preset regions from the light incidence side of the only one light guide plate;
in the light-emitting units corresponding to a same preset region in the N present regions, the light-emitting units with a same color are connected in series;
the light-emitting units corresponding to different preset regions in the N present regions are independent;
the light emitted by the light source spreads in the preset regions in a convergent way;
the backlight control unit acquires image data information corresponding to the N preset regions, and derives chrominance and luminance information of an image corresponding to each preset region, by calculating the image data information corresponding to each preset region, wherein the chrominance and luminance information of the image corresponding to each present region comprises a ratio of a red component, a green component and a blue component; and
the backlight control unit then, based on the chrominance and luminance information of each preset region, determines an electric current for each red light-emitting unit, each green light-emitting unit and each blue light-emitting unit of each preset region, according to the ratio of the red component, the green component and the blue component.

US Pat. No. 10,192,518

DISPLAY METHOD AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display method, comprising:converting three-channel data of each of pixels in a target image to be displayed to four-channel data;
calculating a color different between the four-channel data and the three-channel data for each of the pixels;
decreasing, for pixels whose color difference of which meets a preset adjustment condition, a ratio of a numerical value of a newly added channel in the four-channel data with respect to the three-channel data to obtain an adjusted four-channel data; and
displaying the target image by using the adjusted four-channel data for the pixels the four-channel data of which is adjusted and using the four-channel data for the pixels the four-channel data of which is not adjusted;
wherein deceasing the ratio of the numerical value of the newly added channel in the four-channel data with respect to the three-channel data to obtain the adjusted four-channel data so that coordinate points of the adjusted four-channel data and coordinate points of the three-channel data belong to same margin ranges in a chrominance coordinate system.

US Pat. No. 10,192,516

METHOD FOR WIRELESSLY TRANSMITTING CONTENT FROM A SOURCE DEVICE TO A SINK DEVICE

BlackBerry Limited, Wate...

1. A method for wirelessly transmitting content from a source device to a sink device, the source device comprising a processor, a graphics processing unit (GPU) coupled to the processor, and a wireless communication subsystem coupled to the processor, the method comprising:preparing, by the processor and/or GPU of the source device, a first set of display frames for the sink device from a set of source display frames in accordance with a selected transmission format, wherein the selected transmission format is one of screencasting, graphics processing unit (GPU) processing or GPU processing with media streaming;
wirelessly transmitting, by the wireless communication subsystem of the source device, the first set of display frames to the sink device;
determining, by the processor of the source device, whether predetermined performance criteria have been met; and
when the predetermined performance criteria have not been met and the selected transmission format is GPU processing or GPU processing with media streaming, changing the selected transmission format from GPU processing or GPU processing with media streaming to screencasting.

US Pat. No. 10,192,515

DISPLAY DEVICE AND DATA DRIVER

AU OPTRONICS CORPORATION,...

1. A data driver applicable to a display device, comprising:a first boost circuit, receiving a supply voltage value and generating a first boosted voltage at a first preset voltage value;
a first gate clock generation circuit, electrically coupled to the first boost circuit, receiving a plurality of timing signals and the first boosted voltage, and generating a first timing signal;
a first level shift circuit, receiving a first timing signal and generating a first gate timing signal; and
a data drive circuit, receiving the plurality of timing signals and generating a plurality of display data signals;
wherein the first boost circuit is electrically coupled to a second boost circuit of a second data driver, and the second booster circuit generates a second boosted voltage at the first preset voltage value.

US Pat. No. 10,192,512

GATE VOLTAGE GENERATION CIRCUIT, TRANSISTOR SUBSTRATE AND DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a gate voltage generation circuit for generating a gate voltage including a first voltage, a second voltage and a third voltage and supplying the gate voltage to a pixel transistor of the display device; and
a transistor substrate provided with the gate voltage generation circuit,
wherein the first voltage is a voltage for opening the pixel transistor,
the second voltage is lower than the first voltage and is a voltage for closing the pixel transistor,
the third voltage is an intermediate voltage between the first voltage and the second voltage,
the voltage rises by way of the intermediate voltage at the time of rising from the second voltage to the first voltage,
the transistor substrate comprises:
a plurality of source lines and a plurality of gate lines formed in a display region;
a pixel region formed by crossing the source lines and the gate lines;
a peripheral region outside the display region;
a gate selection circuit formed in the peripheral region and connected to the gate line of the pixel transistor;
a first transistor constituting the gate selection circuit;
a first source electrode and a first drain electrode constituting the first transistor;
a second transistor constituting the gate selection circuit;
a first gate electrode and a first channel opposed to the first gate electrode, which constitute the first transistor; and
a second gate electrode and a second channel opposed to the second gate electrode, which constitute the second transistor,
the pixel transistor is formed in the pixel region,
the gate voltage generation circuit is formed in the peripheral region,
the first source electrode is electrically connected to the gate voltage generation circuit and the first drain electrode is electrically connected to the gate line, and
a channel length of the first channel is shorter than a channel length of the second channel.

US Pat. No. 10,192,511

DISPLAY DRIVING CIRCUIT AND PIXEL STRUCTURE

WUHAN CHINA STAR OPTOELEC...

1. A display driving circuit, comprising:a first latch for latching a first data voltage;
a second latch for latching a second data voltage;
a logic control unit having two logic control ends, four voltage input ends and a voltage output end, wherein an output end of the first latch and an output end of the second latch are respectively connected with one of the logic control ends, the four voltage input ends are respectively connected with four different preset voltages, and the logic control unit is used for selecting to output one of the four preset voltages to a pixel electrode via the voltage output end based upon a first data voltage and a second data voltage input by the two logic control ends.

US Pat. No. 10,192,509

DISPLAY APPARATUS AND A METHOD OF OPERATING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus, comprising:a timing controller configured to generate a mode selection signal and output image data in response to input image data, the mode selection signal indicating a first operation mode or a second operation mode;
a first data driver configured to generate first through M-th data voltages and (M+1)-th through N-th data voltages in response to the mode selection signal and the output image data, and to apply the first through N-th data voltages to first through N-th data lines, respectively, where M is a natural number and N is a natural number greater than M; and
a display panel connected to the first through N-th data lines,
wherein, during a first duration of the first operation mode, each of a polarity pattern of the first through M-th data voltages and a polarity pattern of the (M+1)-th through N-th data voltages repeats a first polarity pattern,
wherein, during a first duration of the second operation mode, the polarity pattern of the first through M-th data voltages repeats the first polarity pattern, and the polarity pattern of the (M+1)-th through N-th data voltages repeats a second polarity pattern different from the first polarity pattern,
wherein the first data driver includes:
a digital-to-analog converter configured to generate the first through N-th data voltages in response to the mode selection signal, a polarity control signal and the output image data, wherein the mode selection signal and the polarity control signal are directly provided to the digital-to-analog converter; and
an output buffer configured to output the first through N-th data voltages to the first through N-th data lines.

US Pat. No. 10,192,503

ELECTROOPTIC DEVICE AND ELECTRONIC APPARATUS

SEIKO EPSON CORPORATION, ...

1. An electrooptic device comprising:a scan line;
a first data line and a second data line that intersect the scan line;
a scan line driving circuit that selects the scan line;
a data line driving circuit that supplies data signals to the first data line or the second data line during a period where the scan line is selected;
a first transistor that includes a gate electrode receiving gate signals for selecting the first data line, the first transistor having one end connected to the first data line and the other end connected to the data line driving circuit; and
a second transistor that includes a gate electrode receiving gate signals for selecting the second data line, the second transistor having one end connected to the second data line and the other end connected to the data line driving circuit,
wherein the gate electrode of the second transistor overlaps the first data line in plan view,
the first transistor includes a plurality of first sub-transistors,
the second transistor includes a plurality of second sub-transistors, and
an overlap between a gate electrode of one of the first sub-transistors and the second data line and an overlap between a gate electrode of one of the second sub-transistors and the first data line alternate in a direction in which the first data line and the second data line extend.

US Pat. No. 10,192,502

APPARATUS HAVING SPATIAL LIGHT MODULATOR AND CONVERTING UNIT CONVERTING INPUT VALUE TO CONTROL VALUE TO CONTROL SPATIAL LIGHT MODULATOR

HAMAMATSU PHOTONICS K.K.,...

1. An apparatus for modulating light, comprising:a spatial light modulator including a plurality of blocks, each of the blocks including a plurality of pixels, the spatial light modulator being configured to modulate input light in response to a drive voltage for each of the pixels;
an input value setting unit configured to set an input value for the each of the pixels;
a converting unit configured to convert the input value to a control value based on a plurality of different look-up tables, each of the look-up tables corresponding to a respective block of the plurality of blocks; and
a driving unit configured to drive each of the pixels in response to the drive voltage corresponding to the control value, wherein
each of the look-up tables is configured to store values for the corresponding block based on a phase modulation amount measured for each of the pixels,
when the phase modulation amount is measured for only one pixel in the block, the stored values are based on the phase modulation amount of the one pixel of the plurality of pixels in the block, and
when the phase modulation amount is measured for more than one pixel in the block, the stored values are based on an average of the phase modulation amount for each of the plurality of pixels in the block.

US Pat. No. 10,192,500

POLARITY REVERSION DRIVING METHOD AND APPARATUS OF LIQUID CRYSTAL DISPLAY, AND A LIQUID CRYSTAL DISPLAY

BOE TECHNOLOGY GROUP CO.,...

1. A polarity reversion driving apparatus of a liquid crystal display, comprising a time schedule controller, an inverter, a first logic controller, a second logic controller and a source driver, wherein,the time schedule controller is configured to transmit a first polarity reversion signal POL1 to the inverter and the first logic controller, and transmit a second polarity reversion signal POL2 to the first logic controller and the second logic controller;
the inverter is configured to invert the polarity of the received first polarity reversion signal to generate a third polarity reversion signal POL3, and transmit the third polarity reversion signal POL3 to the first logic controller;
the first logic controller is configured to get through the received first polarity reversion signal POL1 and the third polarity reversion signal POL3 to constitute a fourth polarity reversion signal POL4 according to a level of the received second polarity reversion signal POL2, and transmit the fourth polarity reversion signal POL4 to the second logic controller;
the second logic controller is configured to select and output the fourth polarity reversion signal POL4 or the second polarity reversion signal POL2 to the source driver according to a level of the control signal;
the source driver is configured to output image data signals with corresponding polarities according to a level of the fourth polarity reversion signal POL4 or a level of the second polarity reversion signal POL2;
wherein polarities of the fourth polarity reversion signal POL4 and the second polarity reversion signal POL2 are inverted for every two frames, and a polarity of the control signal is inverted for every frame.

US Pat. No. 10,192,499

DRIVING DEVICE FOR LIQUID CRYSTAL PANEL AND DRIVING METHOD FOR THE SAME FOR DETERMINING IF AMPLIFYING ORIGINAL DATA VOLTAGES IN A SCANNING DIRECTION

Wuhan China Star Optoelec...

1. A driving device for a liquid crystal panel, comprising:a scanning driver for applying a scanning voltage to pixels arranged as a matrix in a liquid crystal panel row by row; and
a data driver for receiving an image data and a polarity inversion signal, obtaining original data voltages to provide to the pixels in each column according to the image data, determining an amplification coefficient for the original data voltages to provide to the pixels in each column along a scanning direction according to the polarity inversion signal, and providing the original data voltages or amplified data voltages to the pixels in each column;
wherein, if the polarity inversion signal is inverted to a positive polarity from a negative polarity, the original data voltages provided to the pixels in each column along the scanning direction are amplified to produce the amplified data voltages;
wherein, the gain module further utilizes a following formula 1 to amplify the original data voltages to provide to the pixels in each column,
V0=Vi·(Y·U+X)pn  [formula 1]
wherein, Vi represents an original data voltage, Vo represents a data voltage after being amplified, (Y·U+X)pn represents an amplification coefficient, which is gradually increased along the scanning direction; U, X and n are reference coefficients, and each is a fixed value; Y represents a regulation coefficient; p represents a gain coefficient;
wherein, when the polarity inversion signal is inverted to a positive polarity from a negative polarity, the gain coefficient p is set as 1; when the polarity inversion signal is inverted to a negative polarity from a positive polarity, the gain coefficient p is set as 0.

US Pat. No. 10,192,495

DISPLAY APPARATUS WITH LIGHTING DEVICE, CONTROL METHOD FOR DISPLAY APPARATUS, AND STORAGE MEDIUM

CANON KABUSHIKI KAISHA, ...

1. A display apparatus comprising:a plurality of light-emitting units configured to emit light;
a display unit configured to display an image on a screen with transmitted light emitted based on an input image;
a first acquisition unit configured to acquire initial luminance values of the plurality of light-emitting units based on the luminance of each of a plurality of regions of the input image corresponding to each of the plurality of light-emitting units;
a first processing unit configured to acquire intermediate luminance values of the plurality of light-emitting units by correcting the initial luminance values, wherein the first processing unit increases an initial luminance value of a first target light-emitting unit among the plurality of light-emitting units that is greater than an initial luminance value of a first neighboring light-emitting unit neighboring the first target light-emitting unit, according to a difference of the initial luminance value of the first target light-emitting unit and the initial luminance value of the first neighboring light-emitting unit;
a second processing unit configured to acquire correct luminance values of the plurality of light-emitting units by correcting the intermediate luminance values, wherein the second processing unit increases an intermediate luminance value of a second target light-emitting unit among the plurality of light-emitting units that is smaller than an intermediate luminance value of a second neighboring light-emitting unit neighboring the second target light-emitting unit, according to a difference of the intermediate luminance value of the second target light-emitting unit and the intermediate luminance value of the second neighboring light-emitting unit, the second target light-emitting unit being same or different from the first target light-emitting unit; and
a control unit configured to control light emission of each of the plurality of light-emitting units according to the correct luminance value of each of the plurality of light-emitting units.

US Pat. No. 10,192,494

INDIVIDUAL CONTROL OF BACKLIGHT LIGHT-EMITTING DIODES

Facebook, Inc., Menlo Pa...

1. A method comprising:by a computing device of a user, dynamically identifying a first subregion and a second subregion of a display of the computing device, wherein the display is backlit by backlighting components, and wherein content of a structured document is associated with each subregion;
by the computing device, receiving a message, the message being associated with a messaging application running on the computing device of the user;
by the computing device, in response to receipt of the message, computing an affinity score between a source of the message and the user, the affinity score being computed based at least in part on interactions on a social-networking system between the source of the message and the user;
by the computing device, increasing light intensity of one or more backlighting components to emit a particular color light that backlight the first subregion comprising the message based on:
the content associated with the first subregion, wherein the content associated with the first subregion comprises the message received at the computing device,
the computed affinity score being above a preset threshold, and
a color associated with the user interface of the messaging application, wherein the particular color light is substantially the same as the color associated with the user interface; and
by the computing device, decreasing light intensity of one or more backlighting components that backlight the second subregion based on the content associated with the second subregion, wherein the increasing and the decreasing are concurrent.

US Pat. No. 10,192,493

DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A display device, comprising:a case;
a display panel on a first side of the case and capable of being in a transparent display state where a background scene is viewable through the display panel;
a panel light source on a second side of the case and that irradiates the display panel with colored light of a plurality of colors in a time division manner;
a rear side light source on a third side of the case or behind the display panel and that irradiates a rear surface side of the display panel, the rear side light source being capable of emitting colored light of a plurality of colors in a time division manner; and
a control circuit that controls emission timings of the colored light from the panel light source and from the rear side light source,
wherein the panel light source and the rear side light source are synchronized by the control circuit such that colored light of different colors are not emitted at a same timing.

US Pat. No. 10,192,490

PIXEL ARRAY AND DISPLAY CIRCUIT FOR VIRTUAL REALITY WITH TWO DISPLAY MODES

EVERDISPLAY OPTRONICS (SH...

1. A pixel array with two display modes, comprising a plurality of rows of pixel circuits, each of the pixel circuits comprising:a first transistor comprising a first end connected to a power supply terminal, a second end, and a control end accessing a first enable signal,
a second transistor comprising a first end connected to a display device, a second end connected to the second end of the first transistor, and a control end accessing the first enable signal;
a third transistor comprising a first end connected to the power supply terminal, a second end connected to the second end of the first transistor, and a control end connected to a second enable signal; and
a fourth transistor comprising a first end connected to the display device, a second end connected to the second end of the second transistor, and a control end accessing the second enable signal;
a fifth transistor comprising a first end connected to the second end of the second transistor, a second end connected to the second end of the first transistor, and a control end connected to the power supply terminal through a capacitor;
a sixth transistor comprising a first end connected to a cathode of the capacitor, a second end, and a control end accessing the first control signal, the capacitor comprising an anode connected to the power supply terminal;
a seventh transistor comprising a first end connected to a second terminal of the sixth transistor, a second end connected to an initial voltage power supply terminal, and a control end accessing the first control signal; and
an eighth transistor comprising a first end connected to the initial voltage supply terminal and a second end connected to the display device;
wherein the first transistor and the second transistor are transistors of the same channel type, and the third transistor and the fourth transistor are transistors of the same channel type, and
wherein the first enable signal drives the display devices in each row of the pixel circuits to light line by line, and the second enable signal which accesses each row of the pixel circuits is the same so that the second enable signal drives display devices in each row of the pixel circuits to be lit at the same time.

US Pat. No. 10,192,487

PIXEL CIRCUIT HAVING THRESHOLD VOLTAGE COMPENSATION, DRIVING METHOD THEREOF, ORGANIC ELECTROLUMINESCENT DISPLAY PANEL, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit, comprising a light emitting element, a driving control module, a resetting control module, a charging control module, a writing control module, and a light emitting control module, wherein:a first control terminal and a second control terminal of the resetting control module are connected to a reset signal terminal, an input terminal of the resetting control module is connected to a first level signal terminal, a first output terminal of the resetting control module is connected to a first node, and a second output terminal of the resetting control module is connected to an output terminal of the driving control module and an input terminal of the light emitting element; the resetting control module is configured to reset the first node and the light emitting element;
a control terminal of the charging control module is connected to the reset signal terminal, an input terminal of the charging control module is connected to an output terminal of the light emitting control module and a first input terminal of the driving control module, and an output terminal of the charging control module is connected to a second node; the charging control module is configured to charge the second node through the light emitting control module and discharge the second node through the driving control module and the resetting control module;
a control terminal of the writing control module is connected to a scan signal terminal, an input terminal of the writing control module is connected to a data signal terminal, and an output terminal of the writing control module is connected to the second node; the writing control module is configured to write a data signal to the second node;
a control terminal of the light emitting control module is connected to a light emitting signal terminal, and an input terminal of the light emitting control module is connected to a second level signal terminal; the light emitting control module is configured to control the driving control module to drive the light emitting element to emit light;
a second input terminal of the driving control module is connected to the first node, and a third input terminal of the driving control module is connected to the second node; and
an output terminal of the light emitting element is connected to a third level signal terminal,
wherein the driving control module comprises a driving transistor having a gate connected to the first node, a first electrode connected to the input terminal of the charging control module and the output terminal of the light emitting control module, a second electrode connected to the input terminal of the light emitting element and the second output terminal of the resetting control module without intervention of any transistor.

US Pat. No. 10,192,486

PIXEL CIRCUIT, A DRIVING METHOD FOR DRIVING THE PIXEL CIRCUIT, AND A DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit, comprising:a threshold compensation unit, connected to a first level terminal, a first scanning signal terminal, a first node, a second node and a third node, configured to pull a voltage of the first node and a voltage of the first level terminal to be uniform and pull a voltage of the third node and a voltage of the second node to be uniform under the control of the voltage of the first scanning signal terminal, and further configured to make the voltage of the first node and the voltage of the third node have an equipotential change and store the voltage of the first node and the voltage of the third node, so that the voltage of the first node is changed into a voltage sum obtained by adding the threshold voltage of the driving unit a voltage difference obtained by subtracting the voltage of the third level terminal from the voltage of the data signal terminal;
a driving unit, connected to the first node, the second node, a second level terminal, a fourth node and a third scanning signal terminal, and configured to output a driving current through the fourth node under the control of the voltage of the first node and a voltage of the third scanning signal terminal, or adjust the voltage of the second node into a voltage difference between the voltage of the first node and a threshold voltage of the driving unit under the control of the voltage of the first node;
a data writing unit, connected to a data signal terminal, a second scanning signal terminal and the third node, and configured to pull the voltage of the third node and the voltage of the data signal terminal to be uniform under the control of a voltage of a second scanning signal terminal;
a resetting unit, connected to the second scanning signal terminal, a third level terminal and the fourth node, and configured to pull a voltage of the fourth node and a voltage of a third level terminal to be uniform under the control of the voltage of the second scanning signal terminal;
an EL light-emitting unit, connected to the fourth node and a fourth level terminal, and configured to display gray scales through driving current input by the fourth node; and
a feedback unit, connected to the third node and the fourth node, and configured to store the voltage of the third node and the voltage of the fourth node and make the voltage of the third node and the voltage of the fourth node have an equipotential change.

US Pat. No. 10,192,485

PIXEL COMPENSATION CIRCUIT AND AMOLED DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel compensation circuit comprising:a capacitor;
a driving transistor;
a light emitting device;
a data signal writing circuit connected to a first end of the capacitor;
a high voltage writing circuit connected to the first end of the capacitor; and
a first reference voltage generation circuit connected to a second end of the capacitor, an anode of the light emitting device and a drain electrode of the driving transistor,
wherein a gate electrode of the driving transistor is connected to the second end of the capacitor, a source electrode of the driving transistor is connected to the high voltage writing circuit, and the drain electrode of the driving transistor is connected to the anode of the light emitting device; and
wherein a cathode of the light emitting device is connected to a common grounding electrode,
wherein the high voltage writing circuit comprises a high voltage signal terminal and a second transistor, and
wherein a control electrode of the second transistor is connected to a light emitting signal terminal, a source electrode of the second transistor is connected to the high voltage signal terminal, and a drain electrode of the second transistor is connected to the first end of the capacitor.

US Pat. No. 10,192,484

PIXEL CIRCUIT AND DRIVING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A pixel circuit comprising: a preset unit, a compensation unit, a data writing unit, a driving unit, an energy storage unit, and a light emitting unit,wherein the preset unit is connected to a first scanning signal terminal, a first node, a second node, a third node and a second electric level terminal, and is configured to connect the first node and the third node to the second electric level terminal, and to provide a first scanning signal from the first scanning signal terminal to the second node, based on the first scanning signal provided to the first scanning signal terminal,
wherein the compensation unit is connected to a second scanning signal terminal, the first node, the second node, the third node, a fourth node and the second electric level terminal, and is configured to connect the first node and the third node to the second electric level terminal, and to connect the fourth node to the second node, based on a second scanning signal provided to the second scanning signal terminal,
wherein the data writing unit is connected to a third scanning signal terminal, a data signal terminal and the first node, and is configured to connect the data signal terminal to the first node under the control of a signal of the third scanning signal terminal,
wherein the energy storage unit is connected to the first node and the second node, and is configured to store a voltage between the first node and the second node,
wherein the driving unit is connected to the second node, the third node and the fourth node, and is configured to output a driving signal to the third node based on a voltage between the second node and the fourth node,
wherein the light emitting unit comprises a light emission control unit and a light emitting component,
wherein the light emission control unit is connected to a control signal terminal, the third node, the fourth node, a first electric level terminal and the light emitting component, the light emitting component is connected to the light emission control unit and the second electric level terminal, the light emission control unit is configured to connect the first electric level terminal to the fourth node and to connect the third node to the light emitting component under the control of the signal of the control signal terminal, the light emitting component is configured to emit light based on the driving signal and a signal provided to the second electric level terminal, and
wherein the second electric level terminal is directly connected to a cathode of the light emitting component for providing said signal provided to the second electric level terminal to the cathode of the light emitting component.

US Pat. No. 10,192,482

PIXEL COMPENSATION CIRCUITS, SCANNING DRIVING CIRCUITS AND FLAT DISPLAY DEVICES

Shenzhen China Star Optoe...

1. A pixel compensation circuit, comprising:a first controllable transistor having a control end, a first end, and a second end, the control end of the first controllable transistor connects to a first scanning line, and the first end of the first controllable transistor connects to one data line to receive a data voltage via the data line;
a driving transistor having a control end, a first end, and a second end, the control end of the driving transistor directly connects to the second end of the first controllable transistor, and the first end of the driving transistor connects to a first voltage end;
a second controllable transistor having a control end, a first end, and a second end, the control end of the second controllable transistor connects to a second scanning line, and the first end of the second controllable transistor connects to the second end of the driving transistor;
an OLED having an anode and a cathode, the anode of the OLED directly connects to the second end of the second controllable transistor, and the cathode of the OLED is grounded;
a first capacitor having a first end and a second end, the first end of the first capacitor connects to the control end of the driving transistor, and the second end of the first capacitor connects to the first end of the second controllable transistor; and
a second capacitor includes a first end and a second end, the first end of the second capacitor connects to the first end of the second controllable transistor and the second end of the first capacitor, and the second end of the second capacitor connects to a second voltage end.