US Pat. No. 10,115,964

ADVANCED SI-C COMPOSITE ANODE ELECTRODE FOR HIGH ENERGY DENSITY AND LONGER CYCLE LIFE

PALO ALTO RESEARCH CENTER...

1. An electrode, comprising:a layer of alternating stripes of two different materials, wherein a first material is a graphite-containing material and a second material is a silicon-containing material, wherein the silicon-containing material resides in a three-dimensional graphite matrix.

US Pat. No. 10,115,962

HIGH CAPACITY CATHODE MATERIAL WITH STABILIZING NANOCOATINGS

ENVIA SYSTEMS, INC., New...

1. A positive electrode active material comprising a lithium metal oxide active composition coated with an amorphous aluminum zinc oxide coating composition approximately represented by the formula AlxZn1?(3x/2)O, where x is from about 0.15 to about 0.475, wherein the lithium metal oxide active composition can be approximately represented by a formula Li1+bNi?Mn?Co?A?O2, where b ranges from about 0.05 to about 0.3, ? ranges from 0 to about 0.4, ? range from about 0.2 to about 0.65, ? ranges from 0 to about 0.46, and ? ranges from 0 to about 0.15 with the proviso that both ? and ? are not zero, and where A is Mg, Sr, Ba, Cd, Zn, Al, Ga, B, Zr, Ti, Ca, Ce, Y, Nb, Cr, Fe, V, or combinations thereof.

US Pat. No. 10,115,961

METHOD FOR THE FABRICATION OF A THIN-FILM SOLID-STATE BATTERY WITH NI(OH)2 ELECTRODE, BATTERY CELL, AND BATTERY

IMEC VZW, Leuven (BE) Pa...

1. A method for fabricating a thin-film solid-state battery cell on a substrate comprising a first current collector layer, the method comprising:depositing above the first current collector layer a first electrode layer,
wherein the first electrode layer is a nanoporous composite layer comprising a plurality of pores having pore walls, and
wherein the first electrode layer comprises a mixture of a dielectric material and an active electrode material;
depositing above the first electrode layer a porous dielectric layer; and
depositing directly on the porous dielectric layer a second electrode layer,
wherein depositing the second electrode layer comprises depositing a porous Ni(OH)2 layer using an electrochemical deposition process.

US Pat. No. 10,115,958

MANUFACTURING METHOD OF ELECTRIC STORAGE DEVICE AND ELECTRIC STORAGE DEVICE

GS YUASA INTERNATIONAL LT...

1. An electric storage device, comprising:a case including an electrolyte solution pouring opening through which an electrolyte solution is to be poured into the case;
an electric storage element housed in the case;
an electrode terminal disposed on an outer side of the case; and
a current collector including at least a first attitude portion disposed in an attitude along a face in which the electrolyte solution pouring opening is formed, to block a view of the electric storage element from the electrolyte solution pouring opening, the current collector electrically connecting the electric storage element and the electrode terminal,
wherein the current collector includes a through hole, in a cross sectional view of the electric storage device, the through hole longitudinally extending in a direction orthogonal to the face in which the electrolyte solution pouring opening is formed, for flowing the electrolyte solution to the electric storage element in a direction parallel to the face in which the electrolyte solution pouring opening is formed,
wherein a first portion of the electric storage element is applied with an active material, and
wherein, in a plan view from a top surface of the electric storage device, the electrolyte solution pouring opening is located outside of the first portion of the electric storage element.

US Pat. No. 10,115,956

ELECTRICITY STORAGE DEVICE

KABUSHIKI KAISHA TOYOTA J...

1. An electricity storage device comprising:an electrode assembly, in which one or more first electrodes and one or more second electrodes, which are electrodes, are stacked alternately with one or more separators in between;
a case, which accommodates the electrode assembly;
a first terminal and a second terminal, which are exposed to an outside from a wall portion of the case, a part of each terminal protruding toward the electrode assembly, wherein
each first electrode has a first tab, which has a shape protruding from an end of the first electrode,
each second electrode has a second tab, which has a shape protruding from an end of the second electrode, and
the electrode assembly has an end face on which the first and second tabs are located, the end face facing the wall portion,
a circuit breaker, which is arranged between the second terminal and the electrode assembly and is joined to the second terminal;
a first conductor, which is joined to the first tabs and the first terminal; and
a second conductor, which is joined to the circuit breaker and the second tabs, wherein
the first conductor has a first bend portion, which is bent into a shape of a crank when viewed along a stacking direction of the electrodes,
the second conductor has a second bend portion, which is bent into a shape of a crank when viewed along a stacking direction of the electrodes,
a direction that is perpendicular to both the stacking direction of the electrodes and a direction along which the wall portion and the end face face each other is defined as a width direction of the electrode assembly,
a part of the first terminal and the first tabs are arranged along the width direction of the electrode assembly,
the circuit breaker and the second tabs are arranged along the width direction of the electrode assembly,
the first conductor includes
a terminal joint portion, which is joined to the first terminal, and
a first tab joint portion, which is arranged closer to the wall portion than the terminal joint portion and includes a first tab joint face joined to the first tabs and a first opposed face facing the wall portion,
the second conductor includes
a breaker joint portion, which is joined to the circuit breaker, and
a second tab joint portion, which is arranged closer to the wall portion than the breaker joint portion and includes a second tab joint face joined to the second tabs and a second opposed face facing the wall portion,
the breaker joint portion and the terminal joint portion are displaced from each other along the facing direction,
the first bend portion and the second bend portion are bent such that the first opposed face and the second opposed face approach each other along the facing direction, and
the second bend portion of the second conductor is narrower than the first bend portion of the first conductor in the stacking direction of the electrodes.

US Pat. No. 10,115,955

BATTERY TERMINAL ADAPTER

1. A battery terminal adapter for allowing a plurality of electrical wires to be connected to a single battery terminal, said battery terminal adapter comprising:a body side portion having a first end and a second end, said body side portion defining at least one wire-receiving hole therein;
a resiliently deformable first arm extending from said first end of said side portion, said first arm having a central portion and extending longitudinally from said side portion and an end portion opposite from said side portion;
a resiliently deformable second arm extending from said second end of said side portion opposing said first arm, said second arm having a central portion and extending longitudinally from said side portion and an end portion opposite from said side portion; and
a battery terminal receiving cavity defined by and delimited between said central portions of said first and said second arms; wherein
at least one of the end portion of the first arm and the end portion of the second arm extends from and forms an L-shaped arrangement with the corresponding central portion of the first arm and the central portion of the second arm, respectively, and defines at least one transversely-oriented wire-receiving hole and at least one respective fastener bore corresponding to each transversely-oriented wire-receiving hole of the at least one transversely-oriented wire-receiving hole, wherein the respective fastener bore is configured to allow insertion of a fastener therethrough to secure a wire within the corresponding transversely-oriented fastener bore; and further wherein
the battery terminal receiving cavity is electrically conductive with the at least one wire-receiving hole in the body side portion and with the at least one transversely-oriented wire-receiving hole.

US Pat. No. 10,115,954

BATTERY MODULE

SAMSUNG SDI CO., LTD., Y...

1. A battery module, comprising:a plurality of battery cells arranged in a first direction, each one of the plurality of battery cells having a terminal portion on an upper surface thereof;
a bus-bar holder positioned on the plurality of battery cells, the bus-bar holder having an opening exposing terminal portions of the plurality of battery cells;
a bus-bar including a bending portion protruding upward and a flat portion contacting the terminal portions of the plurality of battery cells, the bus-bar positioned in the opening of the bus-bar holder, the bus-bar being spaced apart from a circumference of the opening of the bus-bar holder by a predetermined interval, and the bus-bar electrically connecting terminal portions of adjacent battery cells among the plurality of battery cells;
a guide wall extending along the opening in the first direction, the guide wall extending upward above the opening; and
a fixing member on an inner side of the guide wall, the fixing member being at the bending portion of the bus-bar and pressing the bending portion toward the terminal portions of the plurality of battery cells; and
an insulating member between adjacent flat portions of adjacent bus-bars, wherein
the insulating member includes a gas exhausting portion, a height of the gas exhausting portion being lower than that of another area of the insulating member, the gas exhausting portion being between bending portions of the adjacent bus-bars and extending to parallel the bending portions of the adjacent bus-bars.

US Pat. No. 10,115,953

ENERGY STORAGE APPARATUS

GS YUASA INTERNATIONAL LT...

1. An energy storage apparatus, comprising:one or more energy storage devices;
a component on which bus bars are arranged, the component comprising an insulating material;
a wiring connection component for connecting a first wiring and a second wiring, the first wiring being connected to at least one of the one or more energy storage devices; and
an attachment portion to which the wiring connection component is detachably attached,
wherein the energy storage apparatus is disposed in an energy storage pack in which an other energy storage apparatus is disposed,
wherein the wiring connection component connects the first wiring, which is connected to the wiring connection component, and the second wiring, which is connected to the wiring connection component and to the other energy storage apparatus, and
wherein the wiring connection component includes:
a connector to which the first wiring is connected;
a connector holder for holding the connector; and
a main body to which the connector holder is detachably attached.

US Pat. No. 10,115,951

SWELLING TAPE FOR FILLING GAP

LG Chem, Ltd., (KR)

1. A swelling tape for filling a gap, comprising:a substrate layer that is deformed in a length direction upon contact with a fluid;
a pressure-sensitive adhesive layer formed in a direction parallel to the length direction of the substrate layer on one surface of the substrate layer, and satisfying Equation 1; and
a back-side coating layer present on a surface opposite to the surface of the substrate layer on which the pressure-sensitive adhesive layer is formed,
wherein the substrate layer has a shore A hardness according to ASTM D2240 of 70 A or more, or the substrate layer has a shore D hardness according to JIS K-7311 of 40 D or more, wherein the recited hardnesses are maintained after the substrate is in contact with the fluid,
wherein the back-side coating layer comprises at least one selected from the group consisting of a fluorine-based releasing agent, a silicon-based releasing agent, a releasing agent containing silicon and having a vinyl or acrylic group, and an amide-based releasing agent:
1.5?X2/X1?150  [Equation 1]
where X1 is a peeling strength of the pressure-sensitive adhesive layer measured at room temperature, and at a peeling rate of 5 mm/sec and a peeling angle of 180 degrees with respect to the surface opposite to the surface of the substrate layer on which the pressure-sensitive adhesive layer is formed, and X2 is a peeling strength measured with respect to glass at room temperature and at a peeling rate of 5 mm/sec and a peeling angle of 180 degrees,
wherein the X1 is 20 gf/25 mm or less.

US Pat. No. 10,115,949

LITHIUM SECONDARY BATTERY

Toyota Jidosha Kabushiki ...

1. A lithium secondary battery comprising:a positive electrode having a positive electrode active material layer;
a negative electrode having a negative electrode active material layer;
an organic porous material layer placed between the positive electrode active material layer and the negative electrode active material layer; and
an inorganic porous material layer placed between the organic porous material layer and the negative electrode active material layer;
wherein
the organic porous material layer is a porous resin sheet,
the positive electrode active material layer comprises a positive electrode active material capable of reversibly storing and releasing lithium, the positive electrode active material layer comprising, as the positive electrode active material, one or more species of lithium transition metal oxide having a layered structure selected from the group consisting of lithium nickel-based oxides, lithium cobalt-based oxides, lithium manganese-based oxides and lithium nickel cobalt manganese oxides,
the negative electrode active material layer comprises a negative electrode active material capable of reversibly storing and releasing lithium,
the negative electrode active material is a carbon material having a graphite structure at least partially, and
the inorganic porous material layer comprises:
an inorganic filler that does not store lithium at a potential higher than at least the lithium-storing potential of the negative electrode active material, and
a Li absorber that irreversibly stores lithium at a potential higher than the lithium-storing potential of the negative electrode active material, and wherein
the Li absorber comprises at least one species selected from carbon fluorides and manganese dioxide,
the inorganic filler comprises one, two or more species selected from alumina, magnesia and titania,
the Li absorber content in the inorganic porous material layer is 2 to 10 parts by mass relative to 100 parts by mass of the positive electrode active material and is 10 to 100 parts by mass relative to 100 parts by mass of the inorganic filler, and
the lithium secondary battery further comprises a non-aqueous electrolyte solution being a liquid phase at room temperature, wherein the non-aqueous electrolyte solution comprises:
a non-aqueous solvent, and
a lithium compound as a supporting electrolyte which is soluble in the solvent to supply lithium ions.

US Pat. No. 10,115,946

SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

1. A secondary battery comprising:an electrode assembly comprising:
a first electrode plate comprising a first electrode tab;
a second electrode plate comprising a second electrode tab; and
a separator between the first electrode plate and the second electrode plate;
a case comprising:
a body accommodating the electrode assembly;
a cap plate at an upper portion of the body; and
a bottom plate at a lower portion of the body;
an electrode terminal comprising:
a first electrode terminal electrically connected to the first electrode tab and extending through the cap plate; and
a second electrode terminal electrically connected to the second electrode tab via the case and on the cap plate; and
a first safety vent in the bottom plate,
wherein an exterior surface of the bottom plate defines first gas exhaust grooves in communication with the first safety vent, one of the first gas exhaust grooves extending from the first safety vent to an outer perimeter of the bottom plate.

US Pat. No. 10,115,945

HEARING AID BATTERY PACKAGING

SPECTRUM BRANDS, INC., M...

1. A battery package, comprising:a card;
a cover attached to the card, the cover including an opening and a door wherein the door is movable between an open position to provide access to the opening and a closed position in which the door closes the opening;
a tray positioned between the card and the cover, the tray including a plurality of receptacles;
a plurality of batteries, each battery positioned within one of the plurality of receptacles; and
a plurality of tabs, each tab removably attached to one of the batteries, wherein each tab is positioned between the cover and the battery to which the tab is attached;
wherein the tray is rotatable relative to the card and the cover to selectively align one of the receptacles with the opening in a battery removal position; and
wherein with the door in the open position, the tab attached to the battery in the receptacle in the battery removal position is accessible through the opening via an arc of access of at least 90 degrees.

US Pat. No. 10,115,944

BATTERY USED FOR UNMANNED AERIAL VEHICLE AND AN UNMANNED AERIAL VEHICLE

AUTEL ROBOTICS USA LLC, ...

1. A battery assembly configured to power a multi-rotor unmanned aerial vehicle having a battery compartment, comprising:a shell;
a battery body substantially disposed within the shell;
a clamp button, a first part of the clamp button being mounted directly or indirectly to the shell and a second part of the clamp button being configured to be detachably coupled to the battery compartment; and
a restorable elastic piece;
wherein a first end of the restorable elastic piece is disposed to the shell and a second end of the restorable elastic piece is fixed with the clamp button; and
wherein the battery assembly is capable of being removed from the battery compartment in a state where the clamp button is pressed down.

US Pat. No. 10,115,943

BATTERY PACKING MODULE AND BATTERY PACK

Korea Institute Of Energy...

1. A battery packing module comprising:a heat dissipation member having a plurality of insertion cylinders arranged in a lattice type and a through-hole formed between the insertion cylinders in a direction that is parallel to the longitudinal direction of the insertion cylinders, wherein the outer circumferential surfaces of adjacent insertion cylinders are connected to each other;
a plurality of cylindrical battery cells inserted into the insertion cylinders and configured to make contact with the inner circumferential surfaces of the insertion cylinders; and
packing plates coupled to the upper ends and lower ends of the battery cells, wherein the packing plates have a current flow hole formed therein through which electrodes of the battery cells are exposed and battery mounting recesses formed therein in which the battery cells are mounted,
wherein each of the packing plates has an insertion protrusion formed on one side thereof, which is inserted into the through-hole.

US Pat. No. 10,115,941

BATTERY HOUSING AND METHOD FOR INSTALLING A BATTERY

1. A battery housing for receiving a battery cooled by a liquid coolant, the battery housing comprising:a battery plate configured to cool the battery, the battery plate having a first end, a second end, a top surface, and a bottom surface, the battery plate comprising first and second cooling tubes fitted in the battery plate, wherein the first cooling tube enables flow of the coolant liquid in a first direction, and the second cooling tube enables flow of the coolant liquid in a second direction opposite the first direction;
first, second, third, and fourth side panels, wherein:
the first and the second side panels are opposite to each other;
the first side panel has a first elongated recess configured to receive the first end of the battery plate; and
the second side panel has a second elongated recess configured to receive the second end of the battery plate; and
first and second cover plates;
wherein:
the first end of the battery plate is inserted in the first elongated recess;
the second end of the battery plate is inserted in the second elongated recess;
the side panels are configured to connect together to form at least a four-sided housing and to hold the battery plate without the cover plates;
at least one of the top and bottom surfaces of the battery plate is configured to hold the battery; and
the first and second cover plates are connected respectively to a top and bottom of the at least four-sided housing, the connected cover plates being parallel to the top surface of the battery plate.

US Pat. No. 10,115,939

BATTERY COVER PLATE ASSEMBLY AND BATTERY HAVING THE SAME

BYD COMPANY LIMITED, She...

1. A battery cover plate assembly, comprising:a cover plate;
an insulation sheet comprising an insulation sheet body and a limitation portion, the insulation sheet body defining a first end and a second end, the limitation portion being disposed at the second end of the insulation sheet body and defining a limitation space with a lower surface of the insulation sheet body; and
a negative connection sheet comprising a riveting portion and a negative tab connection portion configured to connect to a negative tab and defining a limitation end,
wherein the insulation sheet is disposed between the cover plate and the negative connection sheet, and the riveting portion is connected to the insulation sheet and the cover plate via a rivet, and the limitation end is inserted into the limitation space; and
wherein the limitation space has a U-shape opened in a direction from the second end of the insulation sheet body toward the first end of the insulation sheet body, and
wherein a buffering gap is formed within the U-shape of the limitation space, and the buffering gap is between an end of the limitation end and an end of the limitation space.

US Pat. No. 10,115,938

BATTERY CASE HAVING ANTI-WRINKLE PATTERN

LG CHEM, LTD., Seoul (KR...

1. A battery case made of a laminate sheet, comprising:an outer coating layer made of a weather-resistant polymer;
an inner sealant layer made of a thermally bondable polymer; and
a barrier layer interposed between the outer coating layer and the inner sealant layer,
wherein a pattern is formed on at least one surface of the battery case,
wherein the outer coating layer entirely covers the barrier layer,
wherein the inner sealant layer includes a first surface adjacent the barrier layer and a second surface spaced from and opposite the first surface, the second surface being flat,
wherein the pattern comprises a plurality of grooves formed at the battery case such that the grooves are concave in a direction in which an electrode assembly is mounted in the battery case,
wherein the grooves are formed in all of the outer coating layer, the barrier layer, and the inner sealant layer of the battery, and
wherein the depth of the grooves gradually decreases from the outer coating layer to the inner sealant layer.

US Pat. No. 10,115,937

BATTERY INCLUDING BRANCHED CURRENT COLLECTOR SECTIONS

KABUSHIKI KAISHA TOSHIBA,...

1. A battery comprising:an electrode group in which a positive electrode and a negative electrode are wound into a flat form with a separator interposed therebetween, the positive electrode comprising a positive electrode current collector, and the negative electrode comprising a negative electrode current collector;
a positive electrode tab which is a section of the positive electrode current collector projected in a spiral form from one end face in a winding axis direction of the electrode group;
a negative electrode tab which is a section of the negative electrode current collector projected in a spiral form from another end face in the winding axis direction of the electrode group;
a case in which the electrode group is stored;
a lid provided to an opening in the case and comprising a positive electrode terminal and a negative electrode terminal;
a positive electrode lead comprising,
a connecting section of the positive electrode lead electrically connected to the positive electrode terminal, and
current collecting sections which are two sections branched from the connecting section, extending along a direction perpendicular to the winding axis direction and sandwiching the positive electrode tab, one of the two sections being electrically connected to the positive electrode tab, another section being electrically connected to the positive electrode tab;
a negative electrode lead comprising
a connecting section of the negative electrode lead electrically connected to the negative electrode terminal, and
current collecting sections which are two sections branched from the connecting section, extending along the direction perpendicular to the winding axis direction and sandwiching the negative electrode tab, one of the two sections being electrically connected to the negative electrode tab, another section being electrically connected to the negative electrode tab;
an insulating tape which is arranged on an outermost circumference of the electrode group;
a first insulating cover comprising a resin molded product having a shape which covers areas of the positive electrode lead and the positive electrode tab which are areas opposed to an inside surface of the case, the first insulating cover comprising an opening, a side plate covering an end face of the positive electrode tab, and a side plate curved into a U-shaped form to cover an outermost circumference of the positive electrode tab; and
a second insulating cover comprising a resin molded product having a shape which covers areas of the negative electrode lead and the negative electrode tab which are areas opposed to the inside surface of the case, the second insulating cover comprising an opening, a side plate covering an end face of the negative electrode tab, and a side plate curved into a U-shaped form to cover an outermost circumference of the negative electrode tab.

US Pat. No. 10,115,936

LEAD-ACID BATTERY

GS Yuasa International Lt...

1. A lead-acid battery comprising:a power generating element; and
a container accommodating the power generating element and including a bottom wall, outer walls and a corner at which the outer walls intersect, at least one of the outer walls including a first portion and a second portion that recesses inward from the first portion,
wherein a portion of the corner corresponding to the first portion includes a thick portion that is thickened inward within a range not inwardly beyond the second portion to be thicker than the outer wall and a portion of the corner corresponding to the second portion.

US Pat. No. 10,115,935

CORROSION RESISTANT TUBE FOR SECONDARY BATTERY AND SECONDARY BATTERY COMPRISING THE SAME

LG CHEM, LTD., Seoul (KR...

1. A secondary battery, comprising:(i) an electrode assembly comprising: a positive electrode, a negative electrode and a separator;
(ii) a metal can,
wherein the electrode assembly is built in the metal can; and
(iii) a corrosion resistant tube, consisting of one layer, said layer comprising:
a volatile corrosion inhibitor,
wherein the volatile corrosion inhibitor comprises NaNO2 and a polymer resin; and
a base resin, wherein the base resin is a single material selected from the group consisting of polyethylene terephthalate (PET), nylon and polybutylene terephthalate (PBT), or a mixture of two or more types among these;
wherein the corrosion resistant tube is coated on an outer circumference surface of the metal can,
wherein the volatile corrosion inhibitor is included in 2 to 10 parts by weight based on 100 parts by weight of the base resin.

US Pat. No. 10,115,934

BATTERY PACK

Samsung SDI Co., Ltd., Y...

1. A battery pack comprising: a can having an opening; an electrode assembly accommodated in the can; a cap plate closing the opening of the can, the cap plate comprising a protruding anchor portion; and an insulation plate comprising an anchor hole accommodating the anchor portion, wherein the anchor hole is a slot and is configured to guide movement of the anchor portion within the anchor hole when pressure is applied to the can and the cap plate.

US Pat. No. 10,115,933

ENERGY STORAGE APPARATUS

GS YUASA INTERNATIONAL LT...

1. An energy storage apparatus, comprising:an energy storage device and another energy storage device; and
a spacer located between the energy storage device and said another energy storage device,
wherein each of the energy storage device and said another energy storage device comprises a case body for accommodating an electrode assembly, the case body comprising a body part including an opening at at least a first end in a first direction, and a lid for closing the opening,
wherein the body part comprises:
a thick-walled part formed at at least one of the first end and a second end of the body part in the first direction; and
a thin-walled part thinner than the thick-walled part,
wherein the spacer comprises a pair of sealing parts disposed at an interval in the first direction and a base extending along the energy storage device and said another energy storage device,
wherein each of the sealing parts is in contact with the thin-walled part of the energy storage device,
wherein, in said each of the energy storage device and said another energy storage device, at least a part of a surface of the thick-walled part that faces the spacer is spaced apart from the spacer, and
wherein at least one of the pair of sealing parts includes a first contact part, contacting a surface of the energy storage device, and a second contact part, contacting a surface of said another energy storage device, the first contact part and the second contact part asymmetrically extending from the base with respect to the base.

US Pat. No. 10,115,932

METHOD OF DESIGNING ELECTROLUMINESCENT DEVICE, ELECTROLUMINESCENT DEVICE MANUFACTURED WITH THE DESIGN METHOD, AND METHOD OF MANUFACTURING ELECTROLUMINESCENT DEVICE WITH THE DESIGN METHOD

KONICA MINOLTA, INC., To...

1. A method of designing an electroluminescent device having an emissive layer between a first electrode and a second electrode, the first electrode being a transparent electrode, the emissive layer lying between a first functional layer and a second functional layer, the electroluminescent device having a first transparent member on a side of the first electrode opposite to a side where the emissive layer is provided, the method comprising:preparing a reference device including a construction of the electroluminescent device and a desired analyzed device including a construction of the electroluminescent device;
performing quantum optical analysis, electromagnetic analysis, and ray trace with thicknesses and complex relative permittivities of the first transparent member, the first electrode, the first functional layer, the second functional layer, the emissive layer, and the second electrode as well as a position of a light-emitting point in the emissive layer and a distribution of light-emitting points in the emissive layer being used as design variables;
calculating a “ratio of light extraction efficiency” between the reference device and the analyzed device by computing efficiency of light extraction from the emissive layer into the transparent member or air in both of the reference device and the analyzed device;
finding relation of the thickness and the complex relative permittivity of each of the layers with the “ratio of light extraction efficiency,” the layers forming the reference device and the analyzed device; and
obtaining the respective thicknesses and the respective complex relative permittivities of the first transparent member, the first electrode, the first functional layer, the second functional layer, the emissive layer, and the second electrode as the design variables, based on the relation and an electroluminescence spectrum in air or the first transparent member measured by feeding a current to the reference device.

US Pat. No. 10,115,930

COMBINED INTERNAL AND EXTERNAL EXTRACTION LAYERS FOR ENHANCED LIGHT OUTCOUPLING FOR ORGANIC LIGHT EMITTING DEVICE

Universal Display Corpora...

1. An organic light emitting device comprising:a substrate;
a transparent first electrode having a first index of refraction, disposed adjacent to the substrate;
a second electrode;
an organic emissive layer disposed between the transparent first electrode and the second electrode, the organic emissive layer having a second index of refraction;
layer disposed between the substrate and the transparent first electrode, comprising:
a first material having an index of refraction at least 0.01 greater than the second index of refraction, and
a non-planar interface between the first material and a material adjacent to the first material; and
an external extraction layer disposed adjacent to the substrate, wherein the external extraction layer outcouples light from the substrate and the substrate is disposed between the internal extraction layer and the external extraction layer;
wherein the internal extraction layer comprises at least on material having an index of refraction that is greater than the index of refraction of the substrate and less than the first index of refraction.

US Pat. No. 10,115,929

OLED DEVICE ENCAPSULATION STRUCTURES, OLED DEVICES, AND DISPLAY PANELS

Wuhan China Star Optoelec...

1. A package structure of organic light emitting diode (OLED) components, comprising:an OLED body and an encapsulation layer having an organic layer, a protecting layer, a blocking layer, and a stressed layer;
a first curved-surface area is formed on the organic layer, the protecting layer, the blocking layer, and the stressed layer are stacked on the organic layer in sequence, the protecting layer, the blocking layer, and the stressed layer are respectively formed with a second curved-surface area, the second curved-surface area is stacked on the first curved-surface area and is overlapped with the first curved-surface area, and the second curved-surface area and the first curved-surface area form a folded area of the encapsulation layer;
wherein the first curved-surface area comprises a plurality of periodic cones arranged in a matrix, and the cones are spaced apart from each other.

US Pat. No. 10,115,928

DISPLAY DEVICE WITH MICRO COVER LAYER AND MANUFACTURING METHOD FOR THE SAME

LG Display Co., Ltd., Se...

1. A flexible OLED display, comprising:a substrate including a display area and including a non-display area having a first routing area, a second routing area and a bend allowance area between the first and second routing areas;
a wire trace routed from the first routing area to the second routing area of the substrate;
a notched edge of the substrate corresponding to a routing direction of the wire trace;
a notched edge etched area and a stripe structure between the wire trace and the notched edge of the substrate; and
an organic layer that coats the notched edge etched area and the stripe structure in the bend allowance area.

US Pat. No. 10,115,927

DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising a base substrate comprising a plurality of display units, wherein each of the plurality of display units is provided with an anode, an organic light-emitting layer and a cathode, wherein anodes of different display units are separated from each other, and the display substrate further comprises:a plurality of cathode lines arranged between cathodes and the base substrate, and configured to be connected to driving Integrated Circuits (ICs); and
an insulating layer arranged between the cathode lines and the cathodes, wherein a plurality of cathode windows corresponding to the cathode lines are formed in the insulating layer,
wherein at least part of the plurality of cathode windows respectively corresponds to at least two display regions, a cathode at each of the display regions is connected to the respective cathode line via the cathode window corresponding to the display region.

US Pat. No. 10,115,926

LIGHT-EMITTING ELEMENT, LIGHTING DEVICE, LIGHT-EMITTING DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:an anode;
a first layer over the anode;
a second layer over the first layer;
a third layer over the second layer; and
a cathode over the third layer,
wherein the first layer comprises a first organic compound and a second organic compound,
wherein the second layer comprises a third organic compound and a fourth organic compound,
wherein the third layer comprises the first organic compound and a fifth organic compound,
wherein the first organic compound and the third organic compound have light emitting-property,
wherein the third organic compound comprises a material which emits phosphorescence,
wherein a color of light emitted from the first organic compound is blue, and
wherein a color of light emitted from the third organic compound is yellow.

US Pat. No. 10,115,925

ORGANIC OPTOELECTRONIC DEVICE AND DISPLAY APPARATUS

Samsung SDI Co., Ltd., Y...

1. An organic optoelectronic device, comprisingan anode and a cathode facing each other,
a light-emitting layer located between the anode and cathode,
a hole transport layer located between the anode and light-emitting layer,
an auxiliary hole transport layer located between the hole transport layer and light-emitting layer,
an electron transport layer located between the cathode and light-emitting layer, and
an auxiliary electron transport layer between the electron transport layer and light-emitting layer,
wherein the auxiliary electron transport layer includes at least one type of a first compound expressed by Chemical Formula 1, and
the auxiliary hole transport layer includes at least one type of a second compound expressed by Chemical Formula 2:

wherein, in Chemical Formula 1,
Z is independently N, C, or CRa,
at least one of Z is N,
R1 to R6 and Ra are independently hydrogen, deuterium, a substituted or unsubstituted C1 to C10 alkyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C3 to C30 heteroaryl group, or a combination thereof,
L1 to L6 are independently a single bond, a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted heteroarylene group, or a combination thereof, and
s1 to s6 are independently an integer ranging from 0 to 5,

wherein, in Chemical Formula 2,
R10 to R19 are independently hydrogen, deuterium, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C2 to C30 heteroaryl group, or a combination thereof, and
L7 is a substituted or unsubstituted C2 to C10 alkenylene group, a substituted or unsubstituted C6 to C30 arylene group, a substituted or unsubstituted C2 to C30 heteroaryl group, or a combination thereof, and
“substituted” refers replacement of at least one hydrogen by deuterium, a halogen, a hydroxy group, an amino group, a substituted or unsubstituted C1 to C30 amine group, a nitro group, a substituted or unsubstituted C1 to C40 silyl group, a C1 to C30 alkyl group, a C3 to C30 cycloalkyl group, a C2 to C30 heterocycloalkyl group, a C6 to C30 aryl group, a C2 to C30 heteroaryl group, a C1 to C20 alkoxy group, a fluoro group, a C1 to C10 trifluoroalkyl group, a fluorenyl group, or a cyano group.

US Pat. No. 10,115,924

ORGANIC LIGHT EMITTING DISPLAY APPARATUS

LG Display Co., Ltd., Se...

1. An organic light emitting display (OLED) apparatus comprising:a reflection-anode;
a transparent layer directly on the reflection-anode;
a first stack directly on the transparent layer, wherein the first stack includes an electron transport layer and at least one organic layer having light-emitting dopant of an arylamine-based compound for emitting blue light;
a first charge generation layer on the first stack, wherein the first charge generation layer includes a first N-type charge generation layer doped with alkali-based metal, and a first P-type charge generation layer;
a second stack on the first charge generation layer, wherein the second stack includes at least one organic layer having light-emitting dopant of an iridium-based compound for yellow-green light;
a second charge generation layer on the second stack, wherein the second charge generation layer includes a second N-type charge generation layer doped with alkali-based metal, and a second P-type charge generation layer;
a third stack on the second charge generation layer, wherein the third stack includes at least one organic layer having light-emitting dopant of the arylamine-based compound for emitting blue light; and
a transparent-cathode on the third stack;
wherein, T1 indicates a distance from a lower surface of the transparent layer to an interface between the first N-type charge generation layer and the first P-type charge generation layer, T2 indicates a distance from the interface between the first N-type charge generation layer and the first P-type charge generation layer to an interface between the second N-type charge generation layer and the second P-type charge generation layer, and T3 indicates a distance from the interface between the second N-type charge generation layer and the second P-type charge generation layer to an upper surface of the transparent-cathode, the T1, T2 and T3 satisfy a thickness ratio of T1:T2:T3 =16%:36%:48%,
wherein the light emitting device has a color reproduction ratio of 99% or more than 99%, and a color change value (?u?v?) of 0.05 or less than 0.05 within a viewing angle range from 0° to 60°.

US Pat. No. 10,115,923

DISPLAY PANEL WITH LUMINESCENT MATERIAL BLOCKS

SHENZHEN CHINA STAR OPTOE...

1. A display panel comprising:at least a display unit, the display unit being divided into a first region, a second region, a third region, a fourth region, and a fifth region, wherein the display unit comprises:
an anode layer comprising:
a first anode provided in the first region;
a second anode provided in the second region;
a third anode provided in the third region;
a fourth anode provided in the fourth region; and
a fifth anode provided in the fifth region;
a hole injection layer;
a hole transport layer;
a luminescent material layer including:
a first light-emitting section located in the first region, the first light-emitting section being formed solely by a portion located in the first region of a first luminescent material block;
a second light-emitting section located in the second region, the second light light-emitting section being formed by stacking a portion located in the second region of the first luminescent material block and a portion located in the second region of a second luminescent material block;
a third light-emitting section located in the third region, the third light-emitting section being a portion located in the third region of the second luminescent material block;
a fourth light-emitting section located in the fourth region, the fourth light-emitting section being formed by stacking a portion located in the fourth region of the second luminescent material block and a portion located in the fourth region of a third luminescent material block; and
a fifth light-emitting section located in the fifth region, the fifth light-emitting section being a portion located in the fifth region of the third luminescent material block;
an electron transporting layer;
an electron injection layer; and
a cathode layer;
the display unit further comprising a switching component, which includes
a first switch thin film transistor (TFT) connected to the first anode;
a second switch TFT connected to the second anode;
a third switch TFT connected to the third anode;
a fourth switch TFT connected to the fourth anode; and
a fifth switch TFT connected to the fifth anode;
wherein the first luminescent material block is located in the first region and second region, the second luminescent material is located in the second region, the third region, and the fourth region, as well as the third luminescent material is located in the fourth region and the fifth region.

US Pat. No. 10,115,922

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND LIGHTING APPARATUS FOR VEHICLES USING THE SAME

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising:a first organic layer on a first electrode;
a first emission layer on the first organic layer;
a second emission layer on the first emission layer
a second organic layer on the second emission layer; and
a second electrode on the second organic layer;
wherein a thickness of each of the first emission layer and the second emission layer is equal to or greater than a thickness of the first organic layer.

US Pat. No. 10,115,921

QUANTUM DOT LIGHT EMITTING ELEMENT, METHOD OF FABRICATING THE SAME, AND LIQUID-CRYSTAL DISPLAY

Shenzhen China Star Optoe...

1. A quantum dot light emitting element, comprising: a substrate, a cathode, an electron injection/electron transport layer, a quantum dot light emitting layer, a hole injection/hole transport layer, and an anode, wherein the cathode is arranged on the substrate; the cathode and the anode is arranged on the same side of the substrate; the cathode is opposite to the anode with some in-between space; the electron injection/electron transport layer, the quantum dot light emitting layer, and the hole injection/hole transport layer are inserted between the cathode and the anode; one side of the electron injection/electron transport layer is connected to the cathode; the quantum dot light emitting layer and the hole injection/hole transport layer are subsequently layered on a surface of the electron injection/electron transport layer away from the cathode; the hole injection/hole transport layer is away from a surface of the quantum dot light emitting layer and is connected to the anode; the cathode is used for supplying electrons; the anode is used for supplying holes; the electron injection/electron transport layer is used for transmitting the electrons to the quantum dot light emitting layer; the hole injection/hole transport layer is used for transmitting the holes to the quantum dot light emitting layer; the electrons and the holes recombine in the quantum dot light emitting layer for emitting light; and wherein the electron injection/electron transport layer comprises a water-alcohol soluble conjugated polymer (WACPs);wherein the WACPs comprises one of PFNBr (Bromine Polyfluorene) and PFNSO (Sulfo-Polyfluorene).

US Pat. No. 10,115,920

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting diode display device comprising:a common anode electrode disposed on red, green and blue sub-pixel regions as a single electrode and including a metal layer and a transparent conductive material layer on the metal layer;
a hole injection layer disposed on the common anode electrode;
a first hole transport layer disposed on the hole injection layer;
a second hole transport layer disposed on the first hole transport layer opposite to the red sub-pixel region;
a third hole transport layer disposed on the first hole transport layer opposite to the green sub-pixel region;
first, second and third organic emission layers arranged over the first hole transport layer opposite to the red, green and blue sub-pixel regions, respectively;
an electron transport layer disposed on the first, second and third organic emission layers;
a first cathode electrode on the electron transport layer corresponding to the red sub-pixel region;
a second cathode electrode on the electron transport layer corresponding to the green sub-pixel region; and
a third cathode electrode on the electron transport layer corresponding to the blue sub-pixel region,
wherein the second organic emission layer opposite to the green sub-pixel region is formed in a stacked structure including a green dopant host layer disposed between a first green hole type host layer and a second green hole type host layer used to transport holes,
wherein the first green hole type host layer of the second organic emission layer is interposed between the green dopant host layer and the third hole transport layer,
wherein the third organic emission layer opposite to the blue sub-pixel region is formed in a stacked structure including a blue dopant host layer disposed between a first blue hole type host layer and a second blue hole type host layer used to transport holes,
wherein the second blue hole type host layer of the third organic emission layer is interposed between the blue dopant host layer and the electron transport layer,
wherein the first, second and third organic emission layers are separate and discriminately formed from one another on the hole injection layer,
wherein a side of the stacked structure of the second organic emission layer contacts a side of the stacked structure of the third organic emission layer, and
wherein the first green hole type host layer of the stacked structure of the second organic emission layer is substantially coplanar with the second blue hole type host layer of the stacked structure of the third organic emission layer.

US Pat. No. 10,115,919

OPTOELECTRONIC DIODES AND ELECTRONIC DEVICES INCLUDING SAME

SAMSUNG ELECTRONICS CO., ...

1. An optoelectronic diode, comprising:a first electrode and a second electrode electrically connected to each other, the second electrode having a greater resistance than a resistance of the first electrode,
a third electrode proximate to at least one electrode of the first electrode and the second electrode,
a first active layer between a first two electrodes of the first electrode, the second electrode, and the third electrode, and
a second active layer between a second two electrodes of the first electrode, the second electrode, and the third electrode, the second active layer isolated from the first active layer.

US Pat. No. 10,115,918

DOPING ENGINEERED HOLE TRANSPORT LAYER FOR PEROVSKITE-BASED DEVICE

OKINAWA INSTITUTE OF SCIE...

7. A method of fabricating an optoelectronic device comprising:forming an active layer comprising organometal halide perovskite; and
forming by vacuum evaporation a hole transport layer (HTL) for use for transporting hole carriers, wherein the forming the HTL comprises:
forming a first sublayer adjacent to the active layer and comprising a hole transport material (HTM) doped with an n-dopant by co-evaporating the HTM and the n-dopant;
forming a second sublayer adjacent to the first sublayer and comprising the HTM that is undoped by evaporating the HTM; and
forming a third sublayer adjacent to the second sublayer and comprising the HTM doped with a p-dopant by co-evaporating the HTM and the p-dopant.

US Pat. No. 10,115,917

DOPANT-FREE POLYMERIC HOLE-TRANSPORTING MATERIALS FOR PEROVSKITE SOLAR CELL

Northwestern University, ...

1. A hybrid organic-inorganic perovskite photovoltaic device comprising a first electrode, a second electrode, a light-absorbing layer between the first and second electrodes that comprises a perovskite compound, and a hole-transporting material in contact with the perovskite compound, wherein the hole-transporting material comprises a copolymer comprising a benzo[1,2-d;4,5-d?]bistriazole-containing repeating unit and a benzo[1,2-b:4,5-b?]dithiophene-containing repeating unit.

US Pat. No. 10,115,916

AMBIPOLAR SYNAPTIC DEVICES

International Business Ma...

1. A method comprising:providing a synaptic device including a first structure for injecting both electrons and holes into a semiconductor layer and traps for trapping both electrons and holes;
receiving an electrical signal at the synaptic device, thereby causing the first structure to inject one of electrons and holes into the semiconductor layer, and
effecting net negative charge trapping or net positive charge trapping within the traps upon injection of the one of electrons and holes into the semiconductor layer,wherein the first structure includes a contact region adjoining the semiconductor layer and the semiconductor layer comprises an organic layer containing the traps, the contact region injecting one of the electrons and holes into the semiconductor layer.

US Pat. No. 10,115,915

ORGANIC THIN FILM TRANSISTOR AND METHOD FOR MAKING THE SAME

Tsinghua University, Bei...

1. A method for making an organic thin film transistor, comprising:S1: applying an interdigital electrode layer on a surface of an insulating substrate;
S2: forming an organic semiconductor layer on a surface of the interdigital electrode layer, wherein the forming the organic semiconductor layer comprises:
S21: providing an evaporating source, wherein the evaporating source comprises a carbon nanotube film structure and an organic semiconductor material, and the organic semiconductor material is located on a carbon nanotube film structure surface; and
S22: spacing the evaporating source from the interdigital electrode layer, and heating the carbon nanotube film structure to gasify the organic semiconductor material and form the organic semiconductor layer on an interdigital electrode layer surface;
S3: locating an insulating layer to cover the organic semiconductor layer; and
S4: forming a gate electrode on the insulating layer.

US Pat. No. 10,115,914

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:a display panel including a display area and a peripheral area outside the display area;
a wiring located in the peripheral area;
a first organic insulating film under the wiring and in contact with the wiring; and
a second organic insulating film on the wiring and in contact with the wiring,
wherein the display panel has a first surface which is an opposite side of the wiring from the second organic insulating film,
a distance between the first surface and the wiring includes a first distance at a first portion and a second distance at a second portion, the first and second portions being located in the peripheral area,
the second portion is between the first portion and the display area, and
the first distance is smaller than the second distance.

US Pat. No. 10,115,913

DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus, comprising:a substrate including a bending area between a first area and a second area and bent about a bending axis;
a display over an upper surface of the substrate in the first area; and
a protective film over a lower surface of the substrate, the protective film including a first protective film base over the lower surface of the substrate and corresponding to at least a part of the first area and a first adhesive layer between the substrate and the first protective film base,
wherein the first protective film base includes a first thick portion having a first thickness and a first thin portion having a second thickness less than the first thickness and closer to the bending area than the first thick portion, and
wherein, in the first adhesive layer, a thickness of a portion corresponding to the first thin portion is greater than a thickness of a portion corresponding to the first thick portion.

US Pat. No. 10,115,912

ORGANOMETALLIC COMPLEX, LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. An organometallic complex represented by a general formula (G1),
wherein each of R1 to R13 independently represents any of hydrogen, a substituted or unsubstituted alkyl group having 1 to 6 carbon atoms, and a substituted or unsubstituted phenyl group,
wherein A represents a five-membered heteroaromatic skeleton comprising two or three nitrogen atoms, and
wherein Q represents a sulfur atom.

US Pat. No. 10,115,910

ORGANIC ELECTROLUMINESCENT MATERIAL, ORGANIC ELECTROLUMINESCENT DEVICE AND QUANTUM DOT ELECTROLUMINESCENT UNIT

HANNSTAR DISPLAY (NANJING...

1. An organic electroluminescent material, comprising a structure of the following Formula (1),
wherein one of R2, R4 or R6, or two of R2, R4, R6, R9, or R13 are independent triazole derivatives, and the triazole derivatives have the structure of the following Formula (2),

the other substituents of R1 to R23 are independently selected from the group consisting of a hydrogen atom, a fluorine atom, a cyano group, an alkyl group, a cycloalkyl group, an alkoxy group, a thioalkyl group, a silyl group, and an alkenyl group.

US Pat. No. 10,115,909

ORGANIC ELECTROLUMINESCENT DEVICE, MANUFACTURING METHOD THEREOF AND ELECTRONIC EQUIPMENT

BOE TECHNOLOGY GROUP CO.,...

1. An organic electroluminescent device, comprising:an anode layer, a hole transport layer, a first light emitting layer, a second light emitting layer, an electron transport layer, and a cathode layer stacked in sequence;
wherein the first light emitting layer and the second light emitting layer are in direct contact with each other and comprise the same substrate material; and wherein at least one of the first light emitting layer and the second light emitting layer are doped such that a hole mobility of the first light emitting layer is equal to an electron mobility of the second light emitting layer.

US Pat. No. 10,115,908

IMIDAZOLE[4,5-F][1,10]PHENANTHROLINE DERIVATIVES, METHOD OF PREPARING THE SAME, AND USE THEREOF

BOE Technology Group Co.,...

1. An 11-(9H-carbazol-9-yl)-1H-imidazole[4,5-f][1,10]phenanthroline derivative conforming to a chemical structural formula of:
wherein X is independently selected from the group consisting of a Z-substituted heteroaryl ring and an unsubstituted heteroaryl ring, wherein Y is independently selected from the group consisting of a Z-substituted aryl ring, a Z-substituted heteroaryl ring, an unsubstituted aryl ring, and an unsubstituted heteroaryl ring, and wherein Z is independently selected from the group consisting of aryl, C1-4 alkoxy, amino, nitro, trifluoromethyl, cyano, halo atom, and C1-24 aliphatic hydrocarbyl.

US Pat. No. 10,115,907

COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A compound represented by any one selected from the following Formula 1, Formula 2, and Formula 3:
wherein, in Formula 1, X and Y are each independently S, O, or NR1,
wherein, in Formulae 2 and 3,
X and Y are each independently S, O, NR1, or CR2R3,
wherein, in Formulae 1, 2, and 3,
A to F are each independently hydrogen, deuterium, or a substituted or unsubstituted C6-C60 aryl moiety fused to a corresponding backbone, at least one of A or B being a substituted or unsubstituted C6-C60 aryl moiety fused to the corresponding backbone,
Ar1 to Ar4 and R1 to R3 are each independently a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, or a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group,
at least one substituent of the substituted C1-C60 alkyl group, substituted C6-C60 aryl group, substituted C2-C60 heteroaryl group, substituted monovalent non-aromatic condensed polycyclic group, and substituted monovalent non-aromatic condensed heteropolycyclic group is:
a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid or a salt thereof, a sulfonic acid or a salt thereof, a phosphoric acid or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, or a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, or a C1-C60 alkoxy group, each substituted with a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid or a salt thereof, a sulfonic acid or a salt thereof, a phosphoric acid or a salt thereof, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C2-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q11)(Q12), —Si(Q13)(Q14)(Q15), or —B(Q16)(Q17);
a C3-C10 cycloalkyl group, a C2-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, or a monovalent non-aromatic condensed heteropolycyclic group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C2-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, or a monovalent non-aromatic condensed heteropolycyclic group, each substituted with a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid or a salt thereof, a sulfonic acid or a salt thereof, a phosphoric acid or a salt thereof, a C2-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C2-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q21)(Q22), —Si(Q23)(Q24)(Q25), or —B(Q26)(Q27); or
—N(Q31)(Q32), —Si(Q33)(Q34)(Q35), or —B(Q36)(Q37),
wherein Q11 to Q17, Q21 to Q27, and Q31 to Q37 are each independently a hydrogen, a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid or a salt thereof, a sulfonic acid or a salt thereof, a phosphoric acid or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C2-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, or a monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,115,905

ORGANIC COMPOUND FOR ORGANIC ELECTROLUMINESCENCE DEVICE AND USING THE SAME

1. An organic compound with a general formula (I) as follows:wherein A represents a substituted or unsubstituted fused ring hydrocarbon unit with two to four rings, R1 to R3 are independently selected from the group consisting of a hydrogen atom, a halide, a substituted or unsubstituted alkyl group having 1 to 30 carbon atoms, a substituted or unsubstituted aryl group having 6 to 30 carbon atoms, and a substituted or unsubstituted aralkyl group having 6 to 30 carbon atoms.

US Pat. No. 10,115,904

TRANSPARENT RESIN COMPOSITION FOR ORGANIC ELECTROLUMINESCENT ELEMENT SEALING, RESIN SHEET FOR ORGANIC ELECTROLUMINESCENT ELEMENT SEALING, AND IMAGE DISPLAY DEVICE

FURUKAWA ELECTRIC CO., LT...

1. A transparent resin composition for organic electroluminescent element sealing, comprising:a thermoplastic resin comprising a hydride of a styrene-based A-B-A triblock body;
a tackifying resin which is at least one selected from the group consisting of a hydride of a C5-based petroleum resin, a hydride of a C9-based petroleum resin, and a hydride of a petroleum resin obtained by copolymerizing a C5-based petroleum resin and a C9-based petroleum resin; and
an organometallic compound comprising an ester bond and represented by Formula (1),
where R1, R2, R4, and R6 each represents an organic group comprising an alkyl group, an aryl group, a cycloalkyl group, or an acyl group each having a carbon number of 1 or more and 8 or less; R3 and R5 each represents an organic group comprising an alkyl group, an aryl group, an alkoxy group, a cycloalkyl group, or an acyl group each having a carbon number of 1 or more and 8 or less; M represents a trivalent metal atom; and R1 to R6 are identical organic groups or different organic groups,wherein
the transparent resin composition has a light transmittance of 85% or higher for light having a wavelength of 550 nm at a thickness of 0.1 mm, and
the transparent resin composition satisfies a relationship: AM/Y<162, where A (mg CH3ONa/g) represents an acid value of the transparent resin composition excluding the organometallic compound, M represents a weight average molecular weight of the organometallic compound, and Y represents a weight ratio of the organometallic compound with respect to 100 parts by weight of the resin components.

US Pat. No. 10,115,903

EMITTER HAVING A CONDENSED RING SYSTEM

Merck Patent GmbH, (DE)

1. An organic electroluminescent device comprising at least two electrodes and at least one emitting layer between the electrodes which comprises at least one bi- or tricyclic aromatic or heteroaromatic compound of thegeneral formulae (130) to (137):
where one or more H atoms of these compounds is replaced by one, two, three or four of a radical R1,
R1 is, identically or differently on each occurrence, D, F, N(R2)2, Si(R2)3, B(OR2)2, P(R2)2, S(?O)R2, a straight-chain alkoxy or thioalkoxy group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkoxy group having 3 to 40 C atoms, each of which is optionally substituted by one or more radicals R2, where one or more non-adjacent CH2 groups is optionally replaced by R2C?CR2, Si(R2)2, Ge(R2)2, Sn(R2)2, C?O, C?S, C?Se, C?NR2, P(?O)(R2), SO, SO2, NR2, O, S or CONR2 and where one or more H atoms is optionally replaced by D, F, Cl, or CN, or an uncondensed aromatic ring system having 6 to 18 aromatic ring atoms or an uncondensed heteroaromatic ring system having 5 to 18 aromatic ring atoms, each of which is optionally substituted by one or more radicals R2, or a condensed aromatic or heteroaromatic ring system having 8 to 12 aromatic ring atoms, which may in each case be substituted by one or more radicals R2, or a combination of two or more of these groups, two or more substituents R1 may also form a mono- or polycyclic aliphatic ring system with one another here;
R2 is, identically or differently on each occurrence, H, D, F, OH, N(R3)2, Si(R3)3, B(OR3)2, P(?O)(R3)2, P(R2)2, S(?O)R3, a straight-chain alkyl, alkoxy or thioalkoxy group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkoxy group having 3 to 40 C atoms, each of which is optionally substituted by one or more radicals R3, where one or more non-adjacent CH2 groups is optionally replaced by R3C?CR3, C?C, Si(R3)2, Ge(R3)2, Sn(R3)2, C=O, C?S, C?Se, C?NR3, P(?O)(R3), SO, SO2, NR3, O, S or CONR3 and where one or more H atoms is optionally replaced by D, F, Cl or CN, or an uncondensed aromatic ring system having 6 to 18 aromatic ring atoms or an uncondensed haeroaromatic ring system having 5 to 18 aromatic ring atoms, each of which be substituted by one or more radicals R3, or a condensed aromatic or heteroaromatic ring system having 8 to 12 aromatic ring atoms, which may in each case be substituted by one or more radicals R3, or a combination of two or more of these groups; two or more adjacent radicals R2 may form a mono- or polycyclic aliphatic ring system with one another here; and
R3 is, identically or differently on each occurrence, H, D, F, a straight-chain alkyl, alkoxy or thioalkoxy group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkoxy group having 3 to 40 C atoms, an uncondensed aromatic ring system having 6 to 18 aromatic ring atoms or a heteroaromatic ring system having 5 to 12 aromatic ring atoms, in which, in addition, one or more H atoms is optionally replaced by F; two or more substituents R3 may also form a mono- or polycyclic aliphatic ring system with one another here
wherein the compound of the formulae (130) to (137) is employed as UV light-emitting compound, and wherein the device emits radiation having a wavelength in the range from 280 nm to 380 nm.

US Pat. No. 10,115,902

AZINOTHIADIAZOLE COMPOUNDS AND RELATED SEMICONDUCTOR DEVICES

Flexterra, Inc., Skoke, ...

1. A semiconducting compound, the semiconducting compound being a polymer having a first repeating unit M1 comprising one or more divalent azino[1,2,3]thiadiazole moieties represented by formula (I):wherein:each W independently is selected from the group consisting of N, CH, and CR1, provided that at least one of the W is N; and
R1 is selected from the group consisting of halogen, —CN, NO2, R2, -L-R3, OH, OR2, OR3, NH2, NHR2, N(R2)2, NR2R3, N(R3)2, SH, SR2, SR3, S(O)2OH, —S(O)2OR2, —S(O)2OR3, C(O)H, C(O)R2, C(O)R3, C(O)OH, C(O)OR2, C(O)OR3, C(O)NH2, C(O)NHR2, C(O)N(R2)2, C(O)NR2R3, C(O)N(R3)2, SiH3, SiH(R2)2, SiH2(R2), and Si(R2)3, wherein L is selected from the group consisting of a divalent C1-40 alkyl group, a divalent C2-40 alkenyl group, a divalent C1-40 haloalkyl group, and a covalent bond; R2 is selected from the group consisting of a C1-40 alkyl group, a C2-40 alkenyl group, a C2-40 alkynyl group, and a C1-40 haloalkyl group; and R3 is selected from the group consisting of a C3-10 cycloalkyl group, a C6-14 aryl group, a C6-14 haloaryl group, a 3-12 membered cycloheteroalkyl group, and a 5-14 membered heteroaryl group, each of which optionally is substituted with 1-5 substituents independently selected from the group consisting of halogen, —CN, NO2, R2, OR2, and SR2,
wherein said polymer has a degree of polymerization (n) ranging from 3 to 1,000.

US Pat. No. 10,115,901

MASK ASSEMBLY, APPARATUS, AND METHOD OF MANUFACTURING DISPLAY DEVICE USING THE MASK ASSEMBLY

Samsung Display Co., Ltd....

1. A mask assembly, comprising:a mask substrate configured to deposit a deposition material on a first pixel disposed on a device substrate comprising the first pixel and a second pixel;
a molding layer stacked on the mask substrate and comprising a hole corresponding to a position of the second pixel disposed on the device substrate; and
a blocking plate detachably mounted in the hole and configured to block the second pixel from the deposition material by covering the second pixel when the blocking plate is detached from the hole.

US Pat. No. 10,115,900

SYSTEMS AND METHODS FOR THERMAL PROCESSING OF A SUBSTRATE

Kateeva, Inc., Newark, C...

1. A method for processing a substrate comprising:coating a liquid ink on a substrate, wherein the liquid ink is a formulation comprising a carrier liquid and a film-forming material;
positioning the substrate in a drying chamber of a drying module, wherein the drying chamber comprises
a substrate support apparatus for supporting the substrate,
a condensation plate positioned above the substrate support apparatus, wherein a surface of the condensation plate opposing the substrate is configured to provide at least two gap distances between the surface of the condensation plate opposing the substrate and the substrate, and
wherein a first gap distance of the at least two gap distances is positioned over a first area on the substrate, and a second gap distance of the at least two gap distances is positioned over a second area on the substrate;
applying a vacuum to the drying chamber; and
drying the substrate in the drying chamber;
wherein the method further comprises before or during drying the substrate, controlling the temperature of the substrate and the condensation plate; and
wherein the temperature of the condensation plate is controlled in a range of between about ?10° C. to about 15° C.

US Pat. No. 10,115,899

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NONVOLATILE MEMORY

SanDisk Technologies LLC,...

1. A method comprising:forming a word line above a substrate, the word line disposed in a first direction;
forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction;
forming a nonvolatile memory material between the word line and the bit line by selectively forming a conductive oxide material layer adjacent the word line, and forming a semiconductor material layer adjacent the bit line; and
forming a memory cell comprising the nonvolatile memory material at an intersection of the bit line and the word line.

US Pat. No. 10,115,898

MAGNETORESISTIVE TUNNEL JUNCTION

Taiwan Semiconductor Manu...

1. A method for forming a Magnetoresistive Tunnel Junction (MJT), the method comprising:disposing a magnetic, substantially circular reference layer on a first electrode;
disposing a resistive layer onto the reference layer;
disposing a magnetic, substantially circular free layer on the resistive layer, wherein the reference layer completely overlaps the free layer in a plan view, and wherein the reference layer is larger than the free layer in the plan view; and
disposing a second electrode so as to be connected to the free layer;
wherein the reference layer produces a first magnetic core in a first direction, and the free layer produces a second magnetic core in a second direction, wherein the second direction is different from the first direction.

US Pat. No. 10,115,897

RESISTIVE MEMORY CELL CONTAINING A MIDDLE ELECTRODE AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A resistive memory device comprising:an alternating stack of insulating layers and electrically conductive layers that extend along a first horizontal direction, wherein sidewalls of the electrically conductive layers are laterally recessed relative to sidewalls of the insulating layers to define laterally recessed regions;
discrete clam-shaped barrier material portions located within a respective one of the laterally recessed regions and vertically spaced apart by the insulating layers;
middle electrodes contacting a respective one of the discrete clam shaped barrier material portions, wherein each of the middle electrodes includes a protrusion portion located inside a respective one of the laterally recessed regions and embedded within a respective one of the discrete clam shaped barrier material portions, and further includes a vertically-extending portion located outside the laterally recessed regions and having a greater vertical extent than the protrusion portion;
a resistive memory material layer comprising a resistive material having at least two resistive states having different electrical resistivity and contacting the vertically-extending portion of each of the middle electrodes; and
a vertical conductive line contacting the resistive memory material layer.

US Pat. No. 10,115,896

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first bottom electrode having two edges opposite to each other, and an upper surface;
a second bottom electrode between the edges of the first bottom electrode and exposed from the upper surface of the first bottom electrode wherein a conductivity of the second bottom electrode is higher than a conductivity of the first bottom electrode;
a switching layer over the first bottom electrode and the second bottom electrode; and
a top electrode over the switching layer.

US Pat. No. 10,115,895

VERTICAL FIELD EFFECT TRANSISITORS HAVING A RECTANGULAR SURROUND GATE AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A semiconductor structure comprising a two-dimensional array of vertical field effect transistors, wherein the two-dimensional array of vertical field effect transistors comprises:a one-dimensional array of gate electrode rail pairs, wherein each of the gate electrode rail pairs comprises a pair of gate electrode rails that laterally extend along a first horizontal direction and spaced among one another along a second horizontal direction;
a two-dimensional array of tubular gate electrode portions, wherein each of the tubular gate electrode portions includes a pair of outer sidewalls that contact sidewalls of a respective pair of gate electrode rails;
a gate dielectric located inside each of the tubular gate electrode portions; and
a vertical semiconductor channel extending along a vertical direction and located inside each of the tubular gate electrode portions and laterally surrounded by the gate dielectric.

US Pat. No. 10,115,894

APPARATUS AND METHODS FOR ELECTRICAL SWITCHING

MASSACHUSETTS INSTITUTE O...

1. An apparatus for electrical switching, the apparatus comprising:a crystalline layer having a first side and a second side opposite the first side, the crystalline layer having at least one channel extending from the first side to the second side;
a first electrode disposed on the first side of the crystalline layer, the first electrode having a first solid solubility less than 1% in the crystalline layer; and
a second electrode disposed on the second side of the crystalline layer, the second electrode having a second solid solubility less than 1% in the crystalline layer,
wherein the first electrode comprises an active material to provide at least one metal ion migrating along the at least one channel in response to a first voltage applied across the first electrode and the second electrode.

US Pat. No. 10,115,893

DATA STORAGE DEVICES AND METHODS FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method for manufacturing a data storage device, the method comprising:forming a magnetic tunnel junction layer on a substrate;
irradiating a first ion beam on the magnetic tunnel junction layer at a first incident angle with respect to a top surface of the substrate and in situ in a first chamber to form a plurality of magnetic tunnel junction patterns from the magnetic tunnel junction layer, the plurality of magnetic tunnel junction patterns separated from each other;
irradiating a second ion beam on the magnetic tunnel junction patterns at a second incident angle with respect to the top surface of the substrate and in situ in the first chamber, subsequently to irradiating the first ion beam on the magnetic tunnel junction layer, the second incident angle smaller than the first incident angle; and
irradiating a third ion beam on the magnetic tunnel junction patterns at a third incident angle with respect to the top surface of the substrate and in situ in the first chamber, subsequently to irradiating the second ion beam on the magnetic tunnel junction patterns, the third incident angle greater than the first incident angle.

US Pat. No. 10,115,892

MULTILAYER STRUCTURE FOR REDUCING FILM ROUGHNESS IN MAGNETIC DEVICES

Headway Technologies, Inc...

1. A multilayer structure for reducing film roughness in a magnetic device, comprising:(a) a buffer layer that is one or more of Zr, ZrN, Nb, NbN, Mo, MoN, TiN, W, WN, and Ru, or one of more of the aforementioned materials with Ta or TaN that is formed on a substrate;
(b) a first smoothing layer (S1) with a first bond energy, and having a first surface with an “as deposited” first peak to peak roughness, the S1 is formed on the buffer layer; and
(c) a second smoothing layer (S2) that is non-crystalline or nano-crystalline with a second bond energy that is greater than the first bond energy such that deposition of the S2 results in resputtering of the S1 to give S1 with a second surface having a second peak to peak roughness less than the “as deposited” first peak to peak roughness, and the S2 formed on the second surface, the S2 has a third surface with the second peak to peak roughness.

US Pat. No. 10,115,891

MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A magnetoresistive memory device comprising:a plurality of bottom electrodes provided on a substrate;
a plurality of magnetoresistive elements each provided on a corresponding one of the plurality of bottom electrodes;
a plurality of contact plugs each provided on a corresponding one of the plurality of magnetoresistive elements;
an insulating film provided on sides of the plurality of bottom electrodes, the plurality of magnetoresistive elements and the plurality of contact plugs; and
a shift-adjustment layer provided on the plurality of contact plugs, the shift-adjustment layer extending on the insulating film to interconnect the plurality of contact plugs,
wherein the shift-adjustment layer has an artificial lattice of alternately laminated Co and Pt or an artificial lattice of alternately laminated Co and Pd, and the shift-adjustment layer suppresses a stray magnetic field in the plurality of magnetoresistive elements.

US Pat. No. 10,115,890

MAGNETIC THIN FILM AND APPLICATION DEVICE INCLUDING MAGNETIC THIN FILM

Fuji Electric Co., Ltd., ...

1. A magnetic thin film comprising an ordered alloy, wherein the ordered alloy comprises:at least one first element selected from the group consisting of Fe and Ni;
at least one second element selected from the group consisting of Pt, Pd, Au and Ir; and
a third element consisting of Sc, wherein the content of Sc is in a range from 1.2 at % to 3.8 at %”.

US Pat. No. 10,115,889

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

DENSO CORPORATION, Kariy...

9. A method for manufacturing semiconductor devices, the method comprising:bonding a semiconductor element to a first surface of a planar lead frame;
clamping a partial area of the lead frame to hold the lead frame and the semiconductor element in molding dies; and
covering at least a part of the lead frame and the semiconductor element with a resin member by resin molding which fills the molding dies with resin, wherein:
a thin-walled portion having a relative small thickness is previously formed on a shortest virtual line connecting a clamp area of the lead frame to an area where the semiconductor element is bonded,
through holes are previously formed at four corners of the lead frame around the semiconductor element, and
in the resin molding, another resin member is formed on a second surface of the lead frame so as to connect the resin member to the other resin member via the through holes.

US Pat. No. 10,115,888

METHOD FOR MANUFACTURING CRYSTAL FILM

Advanced Material Technol...

1. A method for manufacturing a crystal film, comprising the steps of:forming a Zr film on a substrate heated to 700° C. or more by a vapor deposition method using a vapor deposition material having a Zr single crystal;
forming a ZrO2 film on said Zr film on a substrate heated to 700° C. or more, by a vapor deposition method using said vapor deposition material having a Zr single crystal, and oxygen; and
forming a Y2O3 film on said ZrO2 film on a substrate heated to 700° C. or more, by a vapor deposition method using a vapor deposition material having Y, and oxygen.

US Pat. No. 10,115,887

FERROELECTRIC CERAMICS AND METHOD FOR MANUFACTURING THE SAME

ADVANCED MATERIAL TECHNOL...

1. Ferroelectric ceramics comprising:a Pt film formed on a stacked film;
a SrTiO3 film formed on said Pt film; and
a PZT film formed on said SrTiO3 film, wherein,
said stacked film is a film formed by repeating N times sequentially a first ZrO2 film and a Y2O3 film, and a second ZrO2 film is formed on said film formed repeatedly N times; and
said N is an integer of 1 or more.

US Pat. No. 10,115,886

TWIN ENGINEERING TO IMPROVE THE SWITCHABILITY AND ROTATABILITY OF POLARIZATIONS AND DOMAINS IN FERROELECTRIC AND PIEZOELECTRIC MATERIALS

The Hong Kong University ...

1. A method for forming deformation crystal twins in piezoelectric materials, the method comprising:obtaining crystalline piezoelectric material;
deforming the crystalline piezoelectric material using a load;
heating the deformed crystalline piezoelectric material in an oxidative atmosphere to a predetermined temperature for a predetermined time to form a plurality of deformation crystal twins in the crystalline piezoelectric material;
allowing the crystalline piezoelectric material to cool to room temperature;
removing the load that induces the deformation of the crystalline piezoelectric material,
wherein the deforming of the crystalline piezoelectric material is achieved by at least one of the following: compressing, stretching, shearing, torsion, and bending of the crystalline piezoelectric material, and
wherein the deforming of the crystalline piezoelectric material creates a shear plane that acts as a twin boundary, which separates the plurality of deformation crystal twins with non-uniform orientation.

US Pat. No. 10,115,885

FLUIDIC ASSEMBLY PROCESS USING PIEZOELECTRIC PLATES

eLux, Inc., Vancouver, W...

1. A method for fabricating a thin-film electronic device employing a piezoelectric plate, the method comprising:providing a plurality of piezoelectric plates, each piezoelectric plate having a polygon shape and comprising a piezoelectric layer, a first electrode overlying a first surface of the piezoelectric layer, and a second electrode overlying a second surface of the piezoelectric layer;
forming a piezoelectric plate suspension;
providing a substrate comprising a plurality of electronic devices, each electronic device including a top surface well;
flowing the piezoelectric plate suspension over the substrate; and,
in response to the piezoelectric plate suspension flow, capturing piezoelectric plates in the top surface wells.

US Pat. No. 10,115,883

DEVICE USING A PIEZOELECTRIC ELEMENT AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A device using a piezoelectric element comprising:a substrate having a cavity;
a movable film formation layer including a movable film disposed above the cavity and defining a top surface portion of the cavity; and
a piezoelectric element formed above the movable film,
the piezoelectric element including a lower electrode formed above the movable film, a piezoelectric film formed above the lower electrode, and an upper electrode formed above the piezoelectric film,
the upper electrode having, in a plan view of viewing from a direction normal to a major surface of the movable film, a peripheral edge that is receded further toward an interior of the cavity than the movable film;
a wiring having one end portion connected to an upper surface of the upper electrode and having another end portion led out to an outer side of a peripheral edge of the cavity in the plan view;
wherein the piezoelectric film has an active portion with an upper surface in contact with a lower surface of the upper electrode and an inactive portion extending along a lower surface of the wiring from a side portion of the active portion to an outer side of the peripheral edge of the cavity,
a hydrogen barrier film, having an opening at an upper surface center of the upper electrode and covering a peripheral edge portion of the upper surface of the upper electrode, entireties of side surfaces of the upper electrode and the piezoelectric film, and an upper surface of the inactive portion of the piezoelectric film; and
an insulating film, formed above the hydrogen barrier film and disposed between the hydrogen barrier film and the wiring;
wherein a contact hole, exposing a portion of the upper electrode is formed in the hydrogen barrier film and the insulating film and the one end portion of the wiring is connected to the upper electrode via the contact hole.

US Pat. No. 10,115,882

THERMOELECTRIC CONVERSION ELEMENT AND THERMOELECTRIC CONVERSION MODULE

FUJIFILM Corporation, Mi...

1. A thermoelectric conversion element comprising:a first substrate having a high thermal conduction portion which has a thermal conductivity higher than a thermal conductivity of other regions in at least a portion in a plane direction;
a thermoelectric conversion layer formed on the first substrate;
a pressure sensitive adhesive layer formed on the thermoelectric conversion layer;
a second substrate formed on the pressure sensitive adhesive layer, having a concave portion, which at least partially overlaps the high thermal conduction portion in the plane direction and is on the pressure sensitive adhesive layer side, and made of a metal material; and
an electrode pair connected to the thermoelectric conversion layer such that the thermoelectric conversion layer is interposed between the electrodes in the plane direction.

US Pat. No. 10,115,881

PORTABLE LIGHTING DEVICE WITH THERMOELECTRIC POWER SOURCE

DONGGUAN HEWANG ELECTRIC ...

1. A portable lighting device with thermoelectric power source, comprising:a thermoelectric power generation module, including a heat dissipation unit, a thermoelectric power generation chip set with hot and cold sides, a heat supply box and a combustion chamber, wherein said cold side of said thermoelectric power generation chip set is in close contact with said heat dissipation unit, said hot side of said thermoelectric power generation chip set is in close contact with said heat supply box, and said heat supply box has a bottom portion connected to said combustion chamber;
an adjustment rod;
a mounting top panel; and
a light emitting unit mounted onto a surface of said mounting top panel, wherein said mounting top panel and said thermoelectric power generation module are connected through said adjustment rod;
said thermoelectric power generation chip set in said cold side comprises a Bi2Te3—Bi2Se3 thermoelectric power generation sheet at a temperature range of 0˜300 degree Celsius, then a solid solution of PbTe, PbTe and SnTe or PbSe at a temperature range of 300˜600 degree Celsius after said Bi2Te3—Bi2Se3 thermoelectric power generation sheet, and a GeTe and/or AgSbTe2 thermoelectric power generation sheet, and in said hot side comprises a Ge—Si alloy and/or MnTe thermoelectric power generation sheet at a temperature above 600 degree Celsius.

US Pat. No. 10,115,880

SYSTEM AND METHOD FOR HARVESTING ENERGY DOWN-HOLE FROM AN ISOTHERMAL SEGMENT OF A WELLBORE

SAUDI ARABIAN OIL COMPANY...

1. A method of generating power in a wellbore extending through a subterranean formation, the method comprising:(i) producing a production fluid from the subterranean formation into the wellbore, wherein the production fluid is produced under pressure from a production zone of the subterranean formation containing a hydrocarbon containing fluid;
(ii) passing the production fluid through a vortex tube to generate a temperature differential between first and second outlets of the vortex tube, wherein the inlet of the vortex tube is in fluid communication with the production zone of the subterranean formation; and
(iii) converting the temperature differential into a voltage.

US Pat. No. 10,115,879

THERMOELECTRIC CONVERSION MATERIAL AND METHOD OF PRODUCTION THEREOF

Panasonic Corporation, O...

1. A thermoelectric conversion material comprising a skutterudite-type material represented by the following composition formula (I)InxGayM4Pn12  (I),wherein:x and y satisfy
0.04?x?0.11,
0.11?y?0.34, and
x M represents one or more elements selected from a group of elements including: Co, Rh, Ir, Fe, Ni, Pt, Pd, Ru, and Os, and
Pn represents one or more elements selected from a group of elements including: Sb, As, P, Te, Sn, Bi, Ge, Se, and Si.

US Pat. No. 10,115,878

OPTICAL SENSOR

Shinko Electric Industrie...

1. An optical sensor comprising:a flexible substrate;
a light emitting element;
a light receiving element;
a plurality of element mounting portions formed on an upper surface of the substrate, wherein each of the light emitting element and the light receiving element is mounted on one of the element mounting portions;
a plurality of element connection portions formed on the upper surface of the substrate, wherein each of the element connection portions is connected to one of the light emitting element and the light receiving element by a wire;
a plurality of through wirings respectively formed in a plurality of through holes extending through the substrate, wherein
each of the through wirings is bonded to one of the element mounting portions or one of the element connection portions, and
the through wirings include a heat radiation through wiring that is located immediately below the light emitting element and bonded to the element mounting portion on which the light emitting element is mounted;
a plurality of light shielding materials that are each frame-shaped, wherein each of the light emitting element and the light receiving element is surrounded by one of the light shielding materials; and
a plurality of encapsulation resins each arranged within a region surrounded by one of the light shielding materials, wherein each of the light emitting element and the light receiving element is encapsulated by one of the encapsulation resins.

US Pat. No. 10,115,877

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a semiconductor device, the method comprising:(a) providing a support, and a semiconductor light-emitting element disposed on the support, the semiconductor light-emitting element including:
a semiconductor structure, and
a first electrode and a second electrode that are disposed on the semiconductor structure;
(b) providing a base including a first interconnect terminal corresponding to the first electrode, and a second interconnect terminal corresponding to the second electrode;
(c) forming a first metal layer that is continuous and covers both a surface of the first electrode and a surface of the second electrode;
(d) forming a second metal layer that is continuous and covers both a surface of the first interconnect terminal and a surface of the second interconnect terminal;
(e) arranging the first and second electrodes to face the first and second interconnect terminals, respectively, and electrically connecting the first and second electrodes to the first and second interconnect terminals, respectively, by atomic diffusion joining, such that:
a first portion of the first and second metal layers is in a region between the first electrode and the first interconnect terminal,
a second portion of the first and second metal layers is in a region between the second electrode and the second interconnect terminal, and
a third portion of the first and second metal layers is in a region other than the first and second portions; and
(f) rendering electrically insulative or removing the third portion of the first and second metal layers.

US Pat. No. 10,115,876

LIGHT EMITTING DEVICE MOUNT, LEADFRAME, AND LIGHT EMITTING APPARATUS

NICHIA CORPORATION, Anan...

1. A light emitting device mount comprising:a positive lead terminal and a negative lead terminal, each of which includes
a first main surface,
a second main surface opposite to said first main surface in a thickness direction of each of said positive lead terminal and said negative lead terminal, and
an end surface which is provided between said first main surface and said second main surface, said end surface including
a first recessed surface area and
a second recessed surface area between said positive lead terminal and said negative lead terminal facing each other, said first recessed surface area extending from a first point of said first main surface in cross section, said second recessed surface area extending from a second point of said second main surface in cross section, said first point being arranged on an exterior side relative to said second point in cross section, said first recessed surface area and said second recessed surface area define a protruding portion protruding outwardly,
wherein at least one of said positive lead terminal and said negative lead terminal includes a middle area between said first and second recessed surface areas, forming an end surface of said protruding portion, that is arranged on an exterior side relative to said first point.

US Pat. No. 10,115,875

LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

NICHIA CORPORATION, Anan...

1. A light-emitting device comprising:a base member having a plurality of first recesses each defined by a bottom surface and lateral surfaces that are inner surfaces of a lateral wall separating adjacent first recesses of the plurality of first recesses;
at least one light-emitting element mounted in each of the plurality of first recesses; and
a plurality of light-transmissive members, each having a flat upper surface and covering one of the plurality of first recesses, wherein
the plurality of light-transmissive members are separated from each other by the lateral wall separating the adjacent first recesses; and
the upper surface of each of the plurality of light transmissive members is located higher than an uppermost portion of the lateral wall, wherein
the base member comprises a substrate and the lateral wall, and
in a cross-sectional view of each of the plurality of first recesses, a virtual line passing through an edge of an upper surface of the at least one light-emitting element and an edge of an upper surface of the lateral wall forms an angle of 0 to 5 degrees with respect to an upper surface of the substrate.

US Pat. No. 10,115,874

LIGHT-EMITTING DEVICE INCLUDING PHOTOLUMINESCENT LAYER

PANASONIC INTELLECTUAL PR...

1. A light-emitting device comprising:a photoluminescent layer that has a first surface perpendicular to a thickness direction thereof and emits light including first light in an infrared region, an area of the first surface being larger than a sectional area of the photoluminescent layer perpendicular to the first surface, the first light having a wavelength ?a in air; and
a light-transmissive layer located on the photoluminescent layer,
wherein at least one of the photoluminescent layer and the light-transmissive layer has a periodic structure having projections or recesses or both arranged perpendicular to the thickness direction of the photoluminescent layer,
at least one of the photoluminescent layer and the light-transmissive layer has a light emitting surface perpendicular to the thickness direction of the photoluminescent layer, the first light being emitted from the light emitting surface,
a refractive index nwav-a of the photoluminescent layer for the first light and a period pa of the periodic structure satisfy ?a/nwav-a a thickness of the photoluminescent layer, the refractive index nwav-a and the period pa are set to limit a directional angle of the first light emitted from the light emitting surface.

US Pat. No. 10,115,873

SURFACE-MODIFIED PHOSPHOR AND LIGHT EMITTING DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A surface-modified phosphor comprising:a phosphor matrix comprising
a compound represented by Chemical Formula 1
K2SiF6:Mn4+; and  Chemical Formula 1
a nano-sized phosphor disposed on the phosphor matrix,
wherein the phosphor matrix has a crack, and wherein the crack is filled with the nano-sized phosphor, and
wherein the nano-sized phosphor comprises at least a compound represented by any one of Chemical Formulas 2 and 3,
Li2TiO3:Mn4+, and  Chemical Formula 2
CaAlSiN:Eu2+.  Chemical Formula 3

US Pat. No. 10,115,871

OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING SAME

OSRAM OPTO SEMICONDUCTORS...

1. A method for producing a plurality of optoelectronic semiconductor components the method comprising:applying a plurality of semiconductor chips, which emit electromagnetic radiation of a first wavelength range from a radiation exit surface during operation, onto an auxiliary carrier;
applying a first conversion material into interstices between the semiconductor chips, wherein the first conversion material is suitable for converting electromagnetic radiation of the first wavelength range into electromagnetic radiation of a second wavelength range;
applying a second conversion material over the first conversion material, wherein the second conversion material is suitable for converting electromagnetic radiation of the first wavelength range into electromagnetic radiation of a second wavelength range or of a third wavelength range;
removing the auxiliary carrier; and
singulating the semiconductor components, wherein the first conversion material forms a first conversion layer on lateral flanks of the semiconductor chips and the second conversion material forms a second conversion layer on the radiation exit surface of the semiconductor chips,
wherein the first conversion material and the second conversion material are a first liquid resin and a second liquid resin into which phosphor particles have been introduced,
wherein the phosphor particles from the second liquid resin sediment into the first liquid resin,
wherein the first liquid resin and second liquid resin are cured before a singulation process, and
wherein, before applying the first conversion material, a reflective material is applied into the interstices between the semiconductor chips.

US Pat. No. 10,115,869

OPTOELECTRONIC SEMICONDUCTOR CHIP, OPTOELECTRONIC COMPONENT AND METHOD FOR SINGULATING SEMICONDUCTOR CHIPS

OSRAM Opto Semiconductors...

1. An optoelectronic semiconductor chip having a carrier and a semiconductor body comprising an active layer provided for generating electromagnetic radiation, whereinthe carrier comprises a first major surface facing towards the semiconductor body, a second major surface facing away from the semiconductor body and a side flank arranged between the first major surface and the second major surface,
the carrier comprises a structured region for enlarging a total surface area of the side flank, the structured region comprising singulating traces,
the structured region comprises a barrier groove, which is circumferential with respect to the carrier, on the side flank,
a lateral extent of the barrier groove is between 3 ?m and 60 ?m inclusive,
the barrier groove is spaced apart from the first major surface and from the second major surface, and
the optoelectronic semiconductor chip comprises one of the following additional features (i) and (ii), namely:
(i) the structured region further comprises on the side flank a plurality of indentations and a lateral extent of the barrier groove is at least twice and at the most ten times as large as a lateral extent of the indentations, or
(ii) the structured region comprises an indentation on the side flank, wherein a lateral width of the indentation is between 0.3 ?m and 6 ?m inclusive and the indentation has a vertical depth which is between 1 times and 5 times the lateral width of the indentation inclusive.

US Pat. No. 10,115,868

OPTOELECTRONIC SEMICONDUCTOR CHIP, OPTOELECTRONIC COMPONENT, AND METHOD OF PRODUCING SEMICONDUCTOR CHIPS

OSRAM Opto Semiconductors...

1. An optoelectronic component comprising an optoelectronic semiconductor chip and a housing body, said optoelectronic semiconductor chip comprising a carrier and a semiconductor body having an active layer that generates electromagnetic radiation during operation of the optoelectronic semiconductor chip, whereinthe semiconductor body is arranged on the carrier,
the semiconductor body has a first main surface facing away from the carrier and a second main surface facing the carrier,
a side surface of the optoelectronic semiconductor chip has an anchoring structure,
the second main surface is arranged between the first main surface and the anchoring structure,
the side surface has roughnesses,
the anchoring structure comprises a plurality of indentations formed in the carrier and spatially arranged apart from one another in a vertical direction, wherein a cross section of the indentations is at least three times larger than a cross section of the roughnesses of the side surface, and a depth of the indentations is at least three times larger than a depth of the roughnesses of the side surface, said depth of the indentation being a lateral extent of the indentation into the carrier, and
the housing body encloses the optoelectronic semiconductor chip in a lateral direction such that a material of the housing body engages into the anchoring structure, and the first main surface and a rear side of the optoelectronic semiconductor chip are free of the material of the housing body.

US Pat. No. 10,115,867

OPTOELECTRONIC SEMICONDUCTOR CHIP

OSRAM OPTO SEMICONDUCTORS...

1. An optoelectronic semiconductor chip comprising:a semiconductor body of semiconductor material;
a p-contact layer; and
an n-contact layer,
wherein:
the semiconductor body comprises an active layer intended for generating radiation,
the semiconductor body comprises a p-side and an n-side, between which the active layer is arranged,
the p-contact layer is capable of electrically contacting the p-side of the semiconductor body,
the n-contact layer is capable of electrically contacting the n-side of the semiconductor body,
the n-contact layer contains a TCO layer and a mirror layer,
the TCO layer is arranged between the n-side of the semiconductor body and the mirror layer, and
the n-contact layer is not in direct contact with the semiconductor body.

US Pat. No. 10,115,866

LIGHT EMITTING DEVICE AND PROJECTOR

Seiko Epson Corporation, ...

1. A light emitting device comprising:a laminated body having an active layer capable of producing light when current is injected thereinto and a first cladding layer and a second cladding layer that sandwich the active layer; and
a first electrode and a second electrode that inject current into the active layer,
wherein the second cladding layer has a ridge section thicker than another portion of the second cladding layer,
the active layer forms an optical waveguide that guides light,
the optical waveguide has a first light exiting surface and a second light exiting surface through which the light exits,
the optical waveguide extends in a direction inclined with respect to a normal to the first light exiting surface and a normal to the second light exiting surface,
the laminated body has a connection area that overlaps with the ridge section when viewed in a direction in which the active layer is laminated on the first cladding layer and is connected to the second electrode,
the ridge section has a first tapered section having a width that increases with distance from a center position that is equidistant from the first light exiting surface and the second light exiting surface toward the first light exiting surface when viewed from the laminated direction and a second tapered section having a width that increases from the center position toward the second light exiting surface when viewed from the laminated direction,
the connection area has a third tapered section having a width that increases from the center position toward the first light exiting surface when viewed from the laminated direction and a fourth tapered section having a width that increases from the center position toward the second light exiting surface when viewed from the laminated direction,
an angle of outer edges of the connection area that specify the width of the third tapered section with respect to a center line of the optical waveguide is greater than an angle of outer edges of the ridge section that specify the width of the first tapered section with respect to the center line when viewed from the laminated direction, and
an angle of outer edges of the connection area that specify the width of the fourth tapered section with respect to the center line is greater than an angle of outer edges of the ridge section that specify the width of the second tapered section with respect to the center line when viewed from the laminated direction.

US Pat. No. 10,115,865

HIGH-PERFORMANCE LED FABRICATION

Soraa, Inc., Fremont, CA...

1. An LED package comprising:a ceramic substrate having a substrate top surface;
a plurality of traces overlaying said substrate top surface;
a plurality of contacts, each contact being electrically connected to one of said traces;
a reflective material disposed over at least a portion of said traces, said reflective material not extending above said plurality of contacts; and
a flip-chip LED die having LED contacts said LED contacts contacting said plurality of contacts.

US Pat. No. 10,115,864

OPTOELECTRONIC DEVICE WITH LIGHT-EMITTING DIODES AND AN IMPROVED RADIATION PATTERN

Aledia, Grenoble (FR)

1. An optoelectronic device comprising:a support comprising a conductive layer;
an electrode,
wherein the conductive layer comprises a portion having a concave or convex shape, and the electrode has a concave or convex shape, respectively; and
at least one light-emitting diode disposed between the portion and the electrode, wherein:
the at least one light-emitting diode comprises at least one cylindrical, conical or tapered semiconductor element in contact with a surface of the portion;
an amplitude of a deflection of the surface between the at least one semiconductor element and the portion is smaller than or equal to 0.5 ?m; and
an amplitude of a deflection of the portion is greater than 1/20th of a chord of the portion.

US Pat. No. 10,115,863

STRAINED ALGAINP LAYERS FOR EFFICIENT ELECTRON AND HOLE BLOCKING IN LIGHT EMITTING DEVICES

Lumileds LLC, San Jose, ...

1. A light-emitting device, comprising:an electron blocking layer, wherein at least a portion of the electron blocking layer is arranged to have a tensile strain;
a hole blocking layer, wherein at least a portion of the hole blocking layer is arranged to have a compressive strain; and
an active layer disposed between the hole blocking layer and the electron blocking layer.

US Pat. No. 10,115,862

FLUIDIC ASSEMBLY TOP-CONTACT LED DISK

eLux Inc., Vancouver, WA...

1. A top-contact light emitting diode (LED) display, the display comprising:a transparent substrate with a top surface comprising a number of wells;
a top-contact LED formed in each of the number of wells, each LED comprising:
a lower disk comprising a material with a first dopant selected from a group consisting of: a p-dopant, and an n-dopant; the lower disk having a bottom surface and a top surface;
a multiple quantum well (MQW) disk overlying the lower disk top surface;
an upper disk comprising a material with a second dopant, wherein the second dopant is opposite the first dopant; the upper disk having a bottom surface overlying the MQW disk, a top surface and a first diameter;
an electrical insulator disk overlying the upper disk top surface, having a second diameter smaller than the first diameter such that at least a portion of a perimeter of the upper disk extending to an outer edge of the upper disk top surface remains uncovered by the electrical insulator disk; and, a via formed through the electrical insulator disk upper disk, and MQW disk, exposing a center contact region of the lower disk top surface.

US Pat. No. 10,115,861

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

XIAMEN SANAN OPTOELECTRON...

1. A light-emitting diode, comprising:an epitaxial-laminated layer, comprising from bottom to up:
an n-type ohmic contact layer;
a first n-type transition layer;
an n-type etching-stop layer;
a second n-type transition layer;
an n-type confinement layer;
an active layer;
a p-type confinement layer;
a p-type transition layer; and
a p-type window layer;
a p electrode over an upper surface of the p-type window layer;
a metal bonding layer over a bottom surface of the n-type ohmic contact layer, wherein: a portion corresponding to a position of the p electrode extends upwards and passes through the n-type ohmic contact layer and the first n-type transition layer, till the n-type etching-stop layer, thereby forming a current distribution adjustment structure such that injected current does not flow towards the epitaxial-laminated layer right below the p electrode; and
a conductive substrate located over a bottom surface of the metal bonding layer.

US Pat. No. 10,115,860

HIGH VOLTAGE MONOLITHIC LED CHIP

CREE, INC., Durham, NC (...

1. A monolithic LED chip, comprising:a plurality of active regions on a submount;
integral electrically conductive interconnect elements in electrical contact with said plurality of active regions and electrically connecting at least some active regions of said plurality of active regions in parallel or in series-parallel, wherein said interconnect elements are completely embedded within said submount; and
one or more integral insulating layers surrounding at least a portion of said interconnect elements and isolating said at least a portion of said interconnect elements from other elements of said monolithic LED chip.

US Pat. No. 10,115,859

NITRIDE BASED DEVICES INCLUDING A SYMMETRICAL QUANTUM WELL ACTIVE LAYER HAVING A CENTRAL LOW BANDGAP DELTA-LAYER

Lehigh University, Bethl...

1. A III-nitride based semiconductor device comprising:a substrate;
a first barrier layer comprising a GaN-based material formed over said substrate;
a second barrier layer comprising a GaN-based material disposed over said first barrier layer; and
an InGaN-delta-InN quantum well active layer positioned between said first and second barrier layers, said quantum well active layer comprising:
an inner quantum well delta layer of an InN material, said inner quantum well delta layer having a thickness of approximately 6 ? or less, said first nitride-based material having a first bandgap characteristic; and
a pair of outer quantum well layers, each of said pair of outer quantum well layers being of an InGaN material having an Indium content in the range of about 15% to 35%, said pair of outer quantum well layers sandwiching said inner quantum well delta layer, each of said pair of outer quantum well layers having a respective thickness greater than said thickness of said inner quantum well delta layer and measuring approximately 15 ? to 30 ?;
wherein said InGaN-delta-InN quantum well active layer emits light in a wavelength range of about 500 nm to about 750 nm when the semiconductor device is energized.

US Pat. No. 10,115,858

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

1. A method of fabricating a light emitting diode, the method comprising:providing a substrate;
forming an N-type layer over the substrate;
forming an active layer over the N-type layer;
forming an electronic blocking layer over the active layer; and
forming a P-type layer over the electronic blocking layer, wherein:
the P-type layer comprises a Mg-doped GaN material layer having a Mg impurity concentration of about 2×1019-2×1020 cm?3; and
the P-type layer has a thickness of less than or equal to about 250 ?, and has a surface density of V-type defects of less than or equal to about 5×106 cm?2.

US Pat. No. 10,115,857

METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT OF POLYGON SHAPE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a semiconductor element, comprising:providing a semiconductor wafer including a substrate, a semiconductor structure on the substrate, and electrodes;
forming a cleavage starting portion in the semiconductor wafer, without dividing the semiconductor structure; and
dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer before separating the semiconductor structure, thereby the semiconductor wafer is separated at the cleavage starting portion, wherein
the pressing member includes a tip portion to be pressed on the semiconductor wafer,
the tip portion has a spherical surface, and
each of the plurality of semiconductor elements has a shape of a polygon having five or more angles in a plan view.

US Pat. No. 10,115,856

SYSTEM AND METHOD FOR CURING CONDUCTIVE PASTE USING INDUCTION HEATING

Tesla, Inc., Palo Alto, ...

1. A system for curing conductive paste applied on a plurality photovoltaic structures, comprising:a wafer carrier for carrying the photovoltaic structures on a first side of the wafer carrier, wherein the wafer carrier includes a base and a strip carrier that is in direct contact with the photovoltaic structures; and
a heater positioned on the first side of the wafer carrier, wherein the heater includes an induction coil configured to operate near the photovoltaic structures, thereby providing localized induced heat for curing the conductive paste, and
two shields positioned on the first side of the wafer carrier and configured to shield a magnetic field caused by the induction coil from metallic parts of the photovoltaic structures other than the conductive paste, wherein a gap between the two shields allows the conductive paste to be exposed to the magnetic field produced by the induction coil.

US Pat. No. 10,115,854

METHOD FOR FORMING A VIRTUAL GERMANIUM SUBSTRATE USING A LASER

NewSouth Innovations Pty ...

1. A method for manufacturing a semiconductor device comprising the steps of:providing a substrate;
forming a germanium layer over the substrate, the germanium layer having a concentration of lattice defects;
depositing a dielectric layer onto the germanium layer; thereafter
exposing a region of the germanium layer to laser light through the dielectric layer; thereafter
removing the dielectric layer; and thereafter
forming at least one semiconductor device on a surface portion of the exposed region of the germanium layer comprising growing a plurality of layers comprising III-V compound materials on the formed germanium layer;
wherein the step of exposing the region of the germanium layer to laser light comprises: generating a continuous-wave laser beam and directing the continuous-wave laser beam towards a first edge of the germanium layer and laterally moving the laser beam along the length of the germanium layer from the first edge to a second edge.

US Pat. No. 10,115,853

ELECTRONIC POWER CELL MEMORY BACK-UP BATTERY

Colossus EPC Inc., Gilbe...

1. An electronic power cell memory back-up battery comprising:a light source, wherein the light source emits light in response to receiving light source input power;
a photovoltaic device, wherein the photovoltaic device outputs photovoltaic-generated electrical power in response to receiving light from the light source;
power modulation circuitry electrically coupled to the light source and photovoltaic device;
wherein a first portion of the photovoltaic-generated electrical power output by the photovoltaic device is the light source input power;
wherein the power modulation circuitry receives the light source input power, alters the light source input power to provide a periodic light source input power, and provides the periodic light source input power to the light source;
wherein a second portion of the photovoltaic-generated electrical power output by the photovoltaic device is a power source output power; and
wherein the light source comprises:
a light-emitting device, wherein the light emitting device emits light of a first peak wavelength in response to receiving light source input power; and
a light photon releaser (LPR) material, wherein the LPR material emits light of a second peak wavelength in response to receiving light of the first peak wavelength from the light-emitting device, wherein the LPR material comprises a compound doped with phosphorus, europium, and/or elements from the Lanthanide series; and
a block of optical coupling material, wherein the light-emitting device and the LPR material are embedded in the block of optical coupling material;
wherein the battery further comprises at least one mirror having an interior surface facing the light source and coated with LPR material, wherein the LPR material coating is in contact with the optical coupling material.

US Pat. No. 10,115,852

SOLAR CELL MODULE

Panasonic Intellectual Pr...

1. A solar cell module comprising:first and second solar cell strings, each of the first and second solar cell strings including solar cells arranged in an arrangement direction and wiring members electrically connecting the solar cells to one another;
a light diffusion sheet disposed between the first and second solar cell strings; and
a sealant member sealing the light diffusion sheet and the solar cells of the first and second solar cell strings,whereinthe first and second solar cell strings are disposed adjacent to each other and parallel to each other along the arrangement direction,
the light diffusion sheet is disposed on a front side as a light-receiving side with respect to the solar cells such that both side edge portions of the light diffusion sheet overlap side edge portions of the first and second solar cell strings and the light diffusion sheet does not overlap the wiring members of the first and second solar cell strings in a planar view of the solar cell module, and
the light diffusion sheet comprises:
a base material having a resin sheet; and
a metal film deposited on a front side of the base material, wherein the light diffusion sheet is in direct contact with a light-receiving surface of the solar cells of each of the first solar cell string and the second solar cell string and a side surface of the solar cells of each of the first solar cell string and the second solar cell string.

US Pat. No. 10,115,851

SOLAR CELL HAVING A DIELECTRIC REAR FACE COATING AND METHOD FOR PRODUCING SAME

Centrotherm Photovoltaics...

1. A method for production of a solar cell, comprising:arranging a solar cell substrate in a retaining device having at least one retaining collar, being brought to abut against the at least one retaining collar;
inserting the retaining device into a coating device and depositing a dielectric coating on the back side of the solar cell substrate;
applying a planar contact on at least parts of the dielectric coating;
when the planar contact is applied on at least some parts of the dielectric coating, leaving free those areas which have been shaded by the retaining collars during the deposition of the dielectric coating;
configuring the planar contact in such a way that its boundary line has at least one recess; and
configuring and arranging the planar contact in such a way that the at least one recess leaves at least part of those areas which have been shaded by the retaining collars during the deposition of the dielectric coating free from a covering with the planar contact.

US Pat. No. 10,115,850

ROOF INTEGRATED SOLAR PANEL SYSTEM WITH SIDE MOUNTED MICRO INVERTERS

Building Materials Invest...

1. A roof integrated solar power system for generating electrical power from sunlight, the solar power system comprising:a plurality of modules configured to be installed in overlapping courses on a roof, each module including:
a frame having a top surface with an exposure portion to be exposed to sunlight when the module is installed and a headlap portion to be covered by a module in a next higher course of modules when the power system is installed, the exposure portion having opposed ends;
a photovoltaic panel recess formed in the exposure portion of the frame, the photovoltaic panel recess having a first end adjacent one of the opposed ends of the frame and a second end spaced from the other one of the opposed ends of the frame;
a photovoltaic panel having ends, a forward edge, a rear edge, and a top surface and being mounted within the photovoltaic panel recess;
an electronics compartment recess formed in the exposure portion of the frame within the space between the second end of the photovoltaic panel recess and the other one of the opposed ends of the frame;
a micro-inverter and first wiring mounted within the electronics compartment recess; an access panel removably attached to the top of the frame covering the electronics compartment recess, the access panel having a forward edge aligned with the forward edge of the photovoltaic panel and a rear edge aligned with the rear edge of the photovoltaic panel when the access panel is attached to the top of the frame; and
a top surface of the access panel and the top surface of the photovoltaic panel being flush with the top surface of the frame.

US Pat. No. 10,115,849

SOLAR CELL AND METHOD OF FABRICATING THE SAME

LG INNOTEK CO., LTD., Se...

1. A method of fabricating a solar cell, the method comprising:forming a back electrode layer on a substrate;
forming a light absorbing layer on the back electrode layer;
forming a first buffer layer on the light absorbing layer;
forming a second buffer layer on the first buffer layer; and
forming a front electrode layer on the second buffer layer;
wherein the first buffer layer or the second buffer layer comprises at least one of zinc sulfide (ZnS), zinc oxide (ZnO), and zinc hydroxide (Zn(OH)2),
wherein in order to form the buffer layer, the substrate is dipped into the solution in which an ammonia water is dissolved
wherein the forming the first buffer layer, the concentration of the ammonia water is in the range of 1 M to 4 M,
wherein the forming the second buffer layer, the concentration of the ammonia water is in the range of 5 M to 7 M,
wherein a difference in the concentration of ammonia water between the steps of forming the first and second buffer layers is in the range of 3 M to 6 M,
wherein simultaneously with the forming the first buffer layer, the second buffer layer is formed by adjusting the concentration of the ammonia water of the solution,
wherein the second buffer layer is in direct physical contact with the front electrode layer,
wherein the first buffer layer or the second buffer layer has a thickness in a range of about 15 nm to about 50 nm.

US Pat. No. 10,115,848

METHOD OF TRANSFERRING THIN FILM

NATIONAL TSING HUA UNIVER...

1. A method of transferring a thin film, comprising:providing a first element structure, wherein the first element structure includes a first substrate and a functional film layer formed on the first substrate;
completely removing the first substrate, wherein steps of the completely removing the first substrate include conducting an etching step to erode the first substrate and conducting a grinding step to planarize the eroded first substrate, and wherein the etching step and the grinding step are separately and repeatedly conducted until the first substrate is completely removed; and
after completely removing the first substrate, attaching the functional film layer on a second substrate to form a second element structure without flipping the functional film layer;
wherein the first substrate is a soda glass substrate, the functional film layer is a solar cell layer, and the functional film layer includes a back electrode layer, a light absorbing layer, a buffer layer, and a transparent conductive layer, and wherein the light absorbing layer is disposed between the back electrode layer and the transparent conductive layer, and the buffer layer is disposed between the light absorbing layer and the transparent conductive layer.

US Pat. No. 10,115,847

CUPRIC OXIDE SEMICONDUCTORS

Trustees of Tufts College...

1. A cupric oxide semiconductor comprising a substrate and a cupric oxide film overlaying the substrate, wherein the cupric oxide film, containing polycrystalline cupric oxide, amorphous cupric oxide, or both, has an electrical resistivity of 10 to 105 ?·cm, a thickness of 50 to 10000 nm, a bulk density of 1 to 6.4 g/cm3, a surface area of 1 to 100 m2/g, a bandgap of 1.1 to 1.8 eV, and a capacitance of 50 to 100000 mF/g.

US Pat. No. 10,115,846

SOLAR CELL AND SOLAR CELL MANUFACTURING METHOD

Panasonic Intellectual Pr...

1. A solar cell comprising:a photoelectric conversion element including:
a light incident surface and a back surface opposed to the light incident surface; and
a side surface provided between the light incident surface and the back surface,
wherein the photoelectric conversion element has a plurality of sides; and
a light diffusion portion on an outer peripheral area of the light incident surface and the side surface,
the light diffusion portion having:
a lower side light diffusion portion in direct contact with the outer peripheral area of the light incident surface and the side surface on a lower side that is one of the plurality of sides; and
an upper side light diffusion portion in direct contact with the outer peripheral area of the light incident surface and the side surface on an upper side that is one of the plurality of sides and opposed to the lower side,
wherein a width of the lower side light diffusion portion on the side surface in a direction from the light incident surface toward the back surface is smaller than a width of the upper side light diffusion portion on the side surface in the direction from the light incident surface toward the back surface,
wherein a first corner portion constituted by a part of the light incident surface and a part of the side surface is exposed from the light diffusion portion, and
wherein the first corner portion is located along the lower side or the upper side.

US Pat. No. 10,115,845

COMPOSITION FOR FORMING SOLAR CELL ELECTRODES AND ELECTRODES FABRICATED USING THE SAME

SAMSUNG SDI CO., LTD., Y...

1. A composition for forming solar cell electrodes, the composition comprising a conductive powder, a glass frit, an organic vehicle, and a surface tension modifier having a surface tension of 40 to 60 mN/m, the composition for forming solar cell electrodes having a tackiness of 60% to 90% represented by the following Expression 1:
wherein, in Expression 1, A represents a minimum shear stress value of shear stress measured while detaching a pair of circular plates, from each other, which have a diameter of 25 mm and have been laminated in parallel to each other by a medium of the composition for forming solar cell electrodes, by applying an external force, and B represents a shear stress value at a point at which an instantaneous rate of change of shear stress with respect to a gap between the plates (d (shear stress)/d (gap)) is 0.05.

US Pat. No. 10,115,844

ELECTRODES COMPRISING NANOSTRUCTURED CARBON

SEERSTONE LLC, Provo, UT...

1. A method of producing a sintered object, comprising:mixing a mass of nanostructured carbon particles with at least one fluid containing a dissolved carbon source to produce a paste;
pyrolyzing the paste such that the dissolved carbon source forms residual solid carbon within a cohesive body of the nanostructured carbon particles; and
sintering the cohesive body of the nanostructured carbon particles with the residual solid carbon at a pressure from about 10 MPa to about 1000 MPa to form contacts between adjacent nanostructured carbon particles to provide an electrical path between at least two remote points of the cohesive body.

US Pat. No. 10,115,843

BROADBAND ANTIREFLECTION COATINGS UNDER COVERGLASS USING ION GUN ASSISTED EVAPORATION

THE BOEING COMPANY, Chic...

1. A method of forming an antireflective coating, comprising:depositing a first layer comprising titanium dioxide and having a first index of refraction within a range of about 2.3 to about 2.7 using ion beam-assisted deposition;
depositing an intermediate layer by e-beam evaporation comprising titanium dioxide on the first layer, the intermediate layer having an index of refraction and a density less than the first layer;
depositing a second layer on the intermediate layer by e-beam evaporation, the second layer having an index of refraction less than the intermediate layer and within a range of about 1.8 to about 2.1; and
depositing a third layer on the second layer, the third layer having an index of refraction within a range of about 1.6 to about 1.8.

US Pat. No. 10,115,842

SEMICONDUCTOR OPTICAL PACKAGE AND METHOD

STMICROELECTRONICS PTE LT...

1. A device, comprising:a first substrate;
a second semiconductor substrate having a first surface on the first substrate and a second surface opposite the first surface, the semiconductor substrate including a first optical device and a second optical device that receive light from the second surface;
a first sidewall on the first substrate;
a second sidewall on the first substrate, the second semiconductor substrate being between the first and second sidewall;
a transparent layer extending between the first and second sidewall and overlapping the second surface of the semiconductor substrate;
a first light protection coating on the transparent layer, the transparent layer being between the first light protection coating and the second surface of the semiconductor substrate;
a first opening in the first light protection coating; and
a second opening in the first light protection coating.

US Pat. No. 10,115,841

INTEGRATED PHOTOVOLTAIC PANEL CIRCUITRY

Solaredge Technologies Lt...

1. An apparatus comprising:a photovoltaic panel comprising a plurality of photovoltaic cells;
a casing that holds the photovoltaic cells; and
a converter circuit comprising first and second input terminals, the first input terminal directly connected to the casing by the first input terminal being bonded to the casing, and the second input terminal directly connected to the photovoltaic panel, and the converter circuit comprising first and second output terminals galvanically isolated from the first and second input terminals and electrically disconnected from the first and second input terminals, wherein the converter circuit converts first direct current (DC) power on the second input terminal to second DC power on the first output terminal, wherein the first output terminal of the converter circuit outputs power received by the converter circuit,
wherein the first and second input terminals of the converter circuit are integrated with the casing and the photovoltaic panel, respectively.

US Pat. No. 10,115,840

SOLAR CELL AND METHOD FOR PRODUCING THEREOF

SHIN-ETSU CHEMICAL CO., L...

1. A solar cell comprising:a semiconductor substrate of a first conductivity type comprising main surfaces that are opposite to each other wherein one of the main surfaces is a light-receiving surface, the other main surface is a backside, and the backside of the semiconductor substrate has a region of the first conductivity type and a region of a second conductivity type, being an opposite conductivity type to the first conductivity type;
a first finger electrode composed of a first contact portion joined to the region of the first conductivity type and a first current collector formed on the first contact portion;
a second finger electrode composed of a second contact portion joined to the region of the second conductivity type and a second current collector formed on the second contact portion;
a first bus bar electrode being in electrical contact with the first current collector;
a second bus bar electrode being in electrical contact with the second current collector;
a first insulator film disposed at least in the whole area just under the first bus bar electrode; and
a second insulator film disposed at least in the whole area just under the second bus bar electrode;
wherein the entire area of the first bus bar electrode is disposed on the first insulator film;
the entire area of the second bus bar electrode is disposed on the second insulator film;
the electrical contact between the first current collector and the first bus bar electrode is made on the first insulator film;
the electrical contact between the second current collector and the second bus bar electrode is made on the second insulator film;
the first contact portion is in a continuous line shape at least just under the second insulator film; and
the second contact portion is in a continuous line shape at least just under the first insulator film.

US Pat. No. 10,115,839

MODULE FABRICATION OF SOLAR CELLS WITH LOW RESISTIVITY ELECTRODES

Tesla, Inc., Palo Alto, ...

1. A solar module, comprising:a first solar cell having a first back-side emitter layer, and having only an area along one edge on a back-side surface covered by a first busbar; and
a second solar cell having only an area along one edge on a front-side surface covered by a second busbar;
wherein the first solar cell and second solar cell are coupled by overlapping the first busbar and second busbar.

US Pat. No. 10,115,838

PHOTOVOLTAIC STRUCTURES WITH INTERLOCKING BUSBARS

Tesla, Inc., Palo Alto, ...

1. A photovoltaic structure, comprising:a first metallic grid positioned on a first surface of the photovoltaic structure, wherein the first metallic grid includes a first set of discontinuous segments positioned near an edge of the photovoltaic structure; and
a second metallic grid positioned on a second surface of the photovoltaic structure, wherein the second metallic grid includes a second set of discontinuous segments positioned near an opposite edge of the photovoltaic structure;
wherein the first and the second sets of discontinuous segments have substantially complementary topology profiles such that, when the edge of the photovoltaic structure overlaps with an opposite edge of an adjacent photovoltaic structure with a same metallic-grid configuration, a respective segment on the first surface of the photovoltaic structure fits in a corresponding gap between two neighboring segments on the second surface of the adjacent photovoltaic structure, thereby facilitating interlocking of the segments between the two photovoltaic structures wherein, within each of the first and second metallic grids, the discontinuous segments are not directly coupled to one another by a metallic material except by segments of another grid when two photovoltaic structures are overlapped.

US Pat. No. 10,115,837

INTEGRATED CIRCUITS WITH SOLAR CELLS AND METHODS FOR PRODUCING THE SAME

Globalfoundries Singapore...

1. An integrated circuit comprising:a substrate comprising a handle layer, a buried insulator layer overlying the handle layer, and an active layer overlying the buried insulator layer, wherein the handle layer comprises monocrystalline silicon and the active layer comprises monocrystalline silicon;
a transistor overlying the buried insulator layer;
a solar cell within the handle layer such that the buried insulator layer is between the solar cell and the transistor, wherein the solar cell comprises a solar cell outer layer in electrical communication with a solar cell outer layer contact, a solar cell inner layer in electrical communication with a solar cell inner layer contact, and wherein the solar cell inner layer and the solar cell outer layer are monocrystalline silicon;
a deep bias well underlying the buried insulator layer and the transistor, wherein the deep bias well overlies the solar cell inner layer; and
a deep bias well contact in electrical communication with the deep bias well.

US Pat. No. 10,115,835

VARIABLE CAPACITOR BASED ON BURIED OXIDE PROCESS

QUALCOMM Incorporated, S...

1. A semiconductor variable capacitor comprising:a substrate;
a first conductive pad coupled to a first non-insulative region;
a second conductive pad coupled to a second non-insulative region, wherein the second non-insulative region is coupled to a first semiconductor region;
a first control region coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying a control voltage applied to the first control region; and
a first insulator region between the first semiconductor region and the substrate with respect to an axis perpendicular to the substrate, wherein at least a portion of the first non-insulative region is separated from the first semiconductor region by the first insulator region such that the first conductive pad is electrically isolated from the second conductive pad.

US Pat. No. 10,115,833

SELF-ALIGNED HETEROJUNCTION FIELD EFFECT TRANSISTOR

International Business Ma...

1. A junction field effect transistor comprising:an insulating carrier substrate;
a base semiconductor substrate formed on the insulating carrier substrate;
a gate region formed on the base semiconductor substrate wherein the gate region forms a junction with the base semiconductor substrate;
a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region;
a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region; and
a gate stack deposited on the gate region, a first source/drain stack deposited on the first source/drain region and a second source/drain stack deposited on the second source/drain region;
wherein at least a portion of the first source/drain stack and a portion of the second source/drain stack overlaps a top surface of the gate stack in the gate region.

US Pat. No. 10,115,825

STRUCTURE AND METHOD FOR FINFET DEVICE WITH ASYMMETRIC CONTACT

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a fin-type active region extruded from a semiconductor substrate;
a gate stack disposed on the fin-type active region;
a source/drain feature formed in the fin-type active region and disposed on a side of the gate stack;
an elongated contact feature landing on the source/drain feature; and
a dielectric material layer disposed on sidewalls of the elongated contact feature and free from ends of the elongated contact feature, wherein the sidewalls of the elongated contact feature are parallel with the gate stack.

US Pat. No. 10,115,816

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Hyundai Motor Company, S...

1. A semiconductor device, comprising:an n? type layer disposed on a first surface of an n+ type silicon carbide substrate;
a trench disposed within the n? type layer;
an n+ type region and a first p type region disposed at the n? type layer and at a lateral surface of the trench;
a plurality of second p type regions disposed at the n? type layer and are spaced apart from the first p type region;
a gate electrode that includes a first gate electrode disposed at the trench and a plurality of second gate electrodes that extend from the first gate electrode;
a source electrode disposed on the gate electrode and insulated from the gate electrode; and
a drain electrode disposed on a second surface of the n+ type silicon carbide substrate,
wherein the plurality of second p type regions are spaced apart from each other, and the source electrode contacts the plurality of second p type regions and the n? type layer disposed between the plurality of second p type regions,
wherein the semiconductor device comprises a MOSFET region and a diode region,
wherein the MOFET region comprises the n? type layer, the first p type region, the n+ type region, the first gate electrode, the second gate electrode, the source electrode, and the drain electrode,
wherein the diode region comprises the n? type layer, the first p type region, the second p type regions, the source electrode, and the drain electrode, and
wherein the plurality of second gate electrodes extend from the first gate electrode to an upper portion of the second p type region adjacent to the first p type region.

US Pat. No. 10,115,810

HETEROJUNCTION BIPOLAR TRANSISTOR WITH A THICKENED EXTRINSIC BASE

GLOBALFOUNDRIES Inc., Gr...

1. A method for forming a heterojunction bipolar transistor, the method comprising:epitaxially growing a first semiconductor layer on a top surface of a substrate;
epitaxially growing a second semiconductor layer on the first semiconductor layer;
amorphizing a first section of the second semiconductor layer;
doping a second section of the second semiconductor layer that has a lateral arrangement relative to the first section of the second semiconductor layer; and
etching the second semiconductor layer beneath the first section and selective to the first section and the second section of the second semiconductor layer to form an emitter beneath the first section and a first cavity that laterally separates the second section from the emitter.

US Pat. No. 10,115,803

FIELD-EFFECT TRANSISTOR AND METHOD FOR THE FABRICATION THEREOF

Fraunhofer-Gesellschaft z...

1. Field-effect transistor having at least one channel layer, said channel layer comprising a group-III-nitride compound semiconductor, wherein the field-effect transistor comprises at least one source electrode and at least one drain electrode, with the at least one source electrode and the at least one drain electrode each having at least one contact, with the at least one contact having a same or smaller depth than the channel layer;said source electrode and drain electrode comprising at least one doped region extending from the same surface into the at least one channel layer, wherein the depth of penetration of said doped region is selected from approximately 10 nm to approximately 200 nm, and a depth of penetration is equal or smaller than a channel depth, and the gradient of the dopant concentration at the lower interface between the channel layer and the doped region is smaller than 14 nm/decade.

US Pat. No. 10,115,801

VERTICAL TRANSISTOR GATED DIODE

International Business Ma...

1. A semiconductor structure comprising:a first doped semiconductor segment of a first conductivity type extending upwards from a doped bottom semiconductor layer located on a substrate;
a second doped semiconductor segment of a second conductivity type located on the first doped semiconductor segment, wherein the second conductivity type is opposite from the first conductivity type;
a doped top semiconductor region laterally surrounding a top portion of the second doped semiconductor segment;
a gate structure laterally surrounding the first doped semiconductor segment and the second doped semiconductor segment located between the doped bottom semiconductor layer and the doped top semiconductor region;
a top spacer located on the gate structure, wherein the top spacer laterally surrounding the second doped semiconductor segment;
a sidewall spacer atop the top spacer, wherein the sidewall spacer laterally surrounding the doped top semiconductor region; and
a first contact structure atop the second doped semiconductor segment and the doped top semiconductor region, wherein the first contact structure is laterally surrounded by the sidewall spacer.

US Pat. No. 10,115,798

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate;
a first electrode disposed on a surface of the semiconductor device and configured to be soldered to a conductive member; and
a second electrode disposed on the surface of the semiconductor device and configured to be wire-bonded to a conductive member,
wherein
the first electrode comprises a first metal layer, a second metal layer, and a third metal layer, the second metal layer being located between the first metal layer and the third metal layer, and a metallic material of the second metal layer being greater in tensile strength than a metallic material of each one of the first metal layer and the third metal layer, and
the second electrode comprises a layer constituted of a same metallic material as one of the first metal layer and the third metal layer, and does not comprise any layers constituted of a same metallic material as the second metal layer.

US Pat. No. 10,115,790

ELECTRONIC DEVICE INCLUDING AN INSULATING STRUCTURE

SEMICONDUCTOR COMPONENTS ...

1. A process of forming an electronic device comprising:patterning a substrate to define a trench and a first anchor having a proximal portion and a distal portion, wherein
the first anchor extends from a sidewall of the trench,
the sidewall is closer to the proximal portion than to the distal portion, and
the proximal portion has a width that is less than a width of the distal portion; and
forming an insulating structure within the trench and adjacent to the first anchor.

US Pat. No. 10,115,785

MEMORY CELLS AND DEVICES

Xerox Corporation, Norwa...

1. A memory cell comprising a flexible substrate layer and a layer comprising a crosslinked mixture of an acrylic polyol, an alkylene urea-glyoxal resin, and an acid catalyst, wherein said acrylic polyol possesses an OH equivalent weight of from about 300 to about 1,500, and a glass transition temperature of from about ?20° C. to about 90° C.

US Pat. No. 10,115,780

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate comprising a first display region having a first width in a first direction, a second display region having a second width smaller than the first width in the first direction, a peripheral region at a periphery of the first and second display regions, and a dummy region in the peripheral region;
a first pixel in the first display region;
a second pixel in the second display region;
a first control line connected to the first pixel, the first control line extending along the first direction in the first display region;
a second control line connected to the second pixel, the second control line extending along the first direction in the second display region; and
a dummy line connected to the second control line, the dummy line being in the dummy region,
wherein the second control line is at a first conductive layer on a first insulating layer, the first insulating layer is on the substrate, the dummy line is at a second conductive layer on a second insulating layer, and the second insulating layer is on the first conductive layer.

US Pat. No. 10,115,778

ELECTRO-OPTICAL APPARATUS, MANUFACTURING METHOD FOR ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC DEVICE

SEIKO EPSON CORPORATION, ...

1. A light-emitting device, the light-emitting device comprising:a light-reflective layer;
an opposing electrode;
a functional layer including a light-emitting layer, the functional layer being disposed between the light-reflective layer and the opposing electrode;
a first pixel electrode disposed between the light-reflective layer and the functional layer;
a second pixel electrode disposed between the light-reflective layer and the functional layer;
a third pixel electrode disposed between the light-reflective layer and the functional layer;
an insulating layer having a first insulating layer, a second insulating layer, and a third insulating layer,
wherein the first insulating layer is disposed between the first pixel electrode and the light-reflective layer,
wherein the first insulating layer and the third insulating layer are disposed between the second pixel electrode and the light-reflective layer,
wherein the first insulating layer, the second insulating layer, and the third insulating layer are disposed between the third pixel electrode and the light-reflective layer,
wherein the second insulating layer is disposed between the first insulating layer and the third insulating layer in a region that the third pixel electrode overlaps the light-reflective layer,
wherein the third insulating layer physically contacts the first insulating layer in a region that the second pixel electrode overlaps the light-reflective layer, and
wherein at least part of an edge of the second insulating layer is covered by the third insulating layer, and
wherein at least one of the first, second and third insulating layers is made of a material different from others of the first, second and third insulating layers.

US Pat. No. 10,115,776

ORGANIC LIGHT EMITTING DISPLAY DEVICES

Samsung Display Co., Ltd....

1. An electroluminescent device, comprising:a substrate;
a plurality of first electrodes located on the substrate to be spaced apart from each other;
a pixel defining layer disposed on the substrate to expose portions of the first electrodes;
an intermediate layer disposed on the pixel defining layer and the first electrodes;
an emitting layer disposed on the intermediate layer to overlap the first electrode;
a second electrode disposed on the emitting layer; and
wherein the intermediate layer has a first pattern overlapping the portion of the plurality of first electrodes exposed by the pixel defining layer, a second pattern being sloped to confine at least a portion of the emitting layer, and a third pattern overlapping a portion of the substrate between adjacent first electrodes that are spaced apart from each other;
wherein a charge from each first electrode advances to the emitting layer through the first pattern;
wherein at least one of the second and third patterns has a different property from a remaining portion of the intermediate layer;
wherein the different property is at least one selected from the group consisting of an electrical conductivity smaller than the first pattern, an electrical resistance greater than the first pattern, an ink-affinity smaller than the first pattern, and a surface energy smaller than the first pattern; and
wherein the at least one of the second and third patterns has a chemical element diffused from the pixel defining layer to be fixed in the at least one of the second and third patterns.

US Pat. No. 10,115,771

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a substrate;
a first wiring extending in a first direction;
a second wiring being provided between the substrate and the first wiring extending in the first direction, the second wiring being located away from the first wiring in a second direction crossing the first direction and perpendicular to the substrate;
a third wiring being provided between the first wiring and the second wiring, the third wiring extending in a third direction crossing the first and the second directions, the third direction being parallel to the substrate;
a first variable resistance element being provided between the first wiring and the third wiring;
a second variable resistance element being provided between the second wiring and the third wiring;
a first contact extending in the second direction, one end of the first contact being connected to the first wiring, and a length between the first contact and the third wiring in the first direction being a first length and a length between the first contact and the second wiring in the first direction being a second length shorter than the first length;
a second contact being located below the second wiring in the second direction, one end of the second contact being connected to the other end of the first contact, and the second contact extending in the second direction; and
a third contact being connected to the second wiring, the third contact extending in the second direction, and a length between the second contact and the third contact in the first direction being a third length longer than the second length.

US Pat. No. 10,115,769

RESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

MACRONIX INTERNATIONAL CO...

1. A resistive random access memory (ReRAM) device, comprising:a first dielectric layer disposed on a substrate and covering a gate oxide structure on the substrate, and the first dielectric layer comprising:
a first insulating layer disposed on the substrate; and
a stop layer disposed on the first insulating layer and directly contacting a top surface of the gate oxide structure, wherein the stop layer is a hydrogen controlled layer;
a first conductive connecting structure disposed on the substrate and penetrating the first dielectric layer; and
a ReRAM unit disposed on the first conductive connecting structure.

US Pat. No. 10,115,767

DUAL LIGHT EMISSION MEMBER, DISPLAY APPARATUS HAVING THE SAME AND LIGHTING APPARATUS HAVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a substrate comprising:
a first area at which an image is displayed in a first direction with light, and
a second area at which an image is displayed in a second direction opposite to the first direction with light, wherein a portion of the substrate at the second area is light-transmissive;
a first light-emitting member on the substrate and disposed in the first area of the substrate; and
a lens commonly disposed over the first area and the second area of the substrate so as to cover the first light-emitting member,
wherein
at the first area, the light with which the image is displayed in the first direction passes through the lens, and
at the second area, the light with which the image is displayed in the second direction opposite to the first direction passes through the substrate.

US Pat. No. 10,115,766

STRETCHABLE DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a plurality of light-emitting diodes;
a stretchable substrate comprising:
a flat portion including a flat surface; and
a plurality of protrusions protruding from the flat portion, wherein each of the protrusions is stretchable and has an inclined surface with respect to the flat surface, and at least some light-emitting diodes of the plurality of light-emitting diodes are disposed on the inclined surface, wherein an inclination angle of the inclined surface is variable with respect to extension or reduction of the stretchable substrate; and
a plurality of thin film transistors disposed inside the stretchable substrate and connected to the light-emitting diodes.

US Pat. No. 10,115,765

X-RAY FLAT-PANEL DETECTOR AND METHOD FOR PREPARING THE SAME, AND WHITE INSULATING MATERIAL

BOE TECHNOLOGY GROUP CO.,...

1. An X-ray flat-panel detector, comprising:a thin-film transistor substrate;
an insulating reflection layer, which is provided on the thin-film transistor substrate and has a diffuse reflection function, wherein the insulating reflection layer is provided with a contact hole through which a source electrode of the thin-film transistor substrate is exposed, the insulating reflection layer being made of a white insulating material containing, by weight percentage, 80%-98% of a resin matrix and 2%-20% of a light-beam diffuse reflection functional material powder;
a pixel electrode, which is provided on the insulating reflection layer, wherein the pixel electrode is electrically connected to the source electrode of the thin-film transistor substrate via the contact hole;
a photodiode, which covers the pixel electrode;
an electrode, which is provided on the photodiode; and
an X-ray conversion layer, which is provided on the electrode.

US Pat. No. 10,115,764

MULTI-BAND POSITION SENSITIVE IMAGING ARRAYS

RAYTHEON COMPANY, Waltha...

1. A light detection device, comprising:a first array of pixels formed from a first layer of semiconductor material having a bandgap corresponding to a first range of wavelengths, the first array of pixels disposed along a focal plane, each pixel of the first array of pixels configured as a position sensing pixel and to output one or more first signals in proportion to a position of photons incident thereon that are within the first range of wavelengths, the one or more first signals referenced to a ground common;
a first contact disposed on at least a portion of each pixel of the first array of pixels;
at least one barrier layer disposed on a surface of the first layer of semiconductor material;
a second array of pixels monolithically formed on the first array of pixels and formed from a second layer of semiconductor material disposed on a first portion of a surface of the at least one barrier layer, the second layer of semiconductor material having a bandgap corresponding to a second range of wavelengths different from the first range of wavelengths, the second array of pixels disposed along the focal plane, each pixel of the second array of pixels configured as an image sensing pixel and to generate one or more second signals in proportion to a number of photons incident thereon that are within the second range of wavelengths, the one or more second signals referenced to the ground common, wherein the pixels of the second array are sized to be smaller than the pixels of the first array;
a second contact disposed on at least a portion of each pixel of the second array of pixels; and
a third contact disposed on a second portion of the surface of the at least one barrier layer,
wherein the second array of pixels are formed on and disposed outwardly from the first array of pixels such that a plurality of pixels of the second array are associated with and spatially co-registered along the same axis of an optical path of incident photons with each pixel of the first array of pixels, the first and second arrays of pixels arranged along respective planes that are parallel to each other and to the focal plane and that are perpendicular to the optical path, such that the incident photons travel along the optical path from the first array of pixels to the second array of pixels.

US Pat. No. 10,115,758

ISOLATION STRUCTURE FOR REDUCING CROSSTALK BETWEEN PIXELS AND FABRICATION METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a semiconductor device, the method comprising:forming a first trench in a semiconductor substrate;
forming a dielectric layer covering the semiconductor substrate, wherein the dielectric layer has a trench portion located in the first trench of the semiconductor substrate;
forming a reflective material layer on the trench portion of the dielectric layer; and
etching the reflective material layer to form an isolation structure, wherein the isolation structure comprises a bottom portion in a second trench formed by the trench portion of the dielectric layer and a top portion located on the bottom portion of the isolation structure, wherein a top surface of the top portion of the isolation structure is in a position higher than a top surface of the semiconductor substrate.

US Pat. No. 10,115,755

SOLID-STATE IMAGE PICKUP DEVICE, IMAGE PICKUP SYSTEM USING SOLID-STATE IMAGE PICKUP DEVICE, AND METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE

Canon Kabushiki Kaisha, ...

1. A solid-state image pickup device comprising:a plurality of pixels, each of the plurality of pixels including:
a first transfer transistor configured to transfer carriers stored at a first semiconductor region of a first conductive type disposed in a substrate to a second semiconductor region of the first conductive type disposed in the substrate;
a second transfer transistor configured to transfer the carriers held at the second semiconductor region to a third semiconductor region of the first conductive type disposed in the substrate, and
an amplification transistor configured to output a signal based on a potential of the third semiconductor region; and
a metal film
including
a first bottom surface located above an upper surface of a gate electrode of the first transfer transistor,
a second bottom surface located above the first semiconductor region, and
a third bottom surface located above the second semiconductor region,
wherein
with respect to a distance in a direction perpendicular to a surface of the substrate, a first distance between the second bottom surface and the surface of the substrate and a second distance between the third bottom surface and the surface of the substrate are each smaller than a third distance between the upper surface of the gate electrode and the surface of the substrate.

US Pat. No. 10,115,753

IMAGE SENSOR INCLUDING PIXELS HAVING PLURAL PHOTOELECTRIC CONVERTERS CONFIGURED TO CONVERT LIGHT OF DIFFERENT WAVELENGTHS AND IMAGING APPARATUS INCLUDING THE SAME

Samsung Electronics Co., ...

1. An image sensor of a multi-layered sensor structure, the image sensor comprising:a plurality of sensing pixels, each of the plurality of sensing pixels including,
a micro lens configured to collect light,
a first photoelectric converter configured to convert the light of a first wavelength band into an electrical signal, and
a second photoelectric converter configured to convert the light of a second wavelength band into the electrical signal, the second photoelectric converter including a first photoelectric conversion device and a second photoelectric conversion device, the first photoelectric conversion device being spaced apart from the second photoelectric conversion device based on an optical axis of the micro lens, wherein the first photoelectric converter includes,
a first color selection layer configured to photoelectrically convert the light of the first wavelength band into the electrical signal, and
a first electrode and a second electrode spaced apart from the optical axis, the first electrode and the second electrode configured to output converted electrical signals.

US Pat. No. 10,115,746

MANUFACTURING METHOD FOR ACTIVE MATRIX SUBSTRATE, ACTIVE MATRIX SUBSTRATE AND DISPLAY APPARATUS

Sakai Display Products Co...

1. A method of manufacturing an active matrix substrate, the method comprising:forming, on a base substrate, a gate wiring and a source wiring which crosses the gate wiring above the gate wiring;
forming a thin film transistor near a region where the gate wiring and the source wiring face each other;
forming an interlayer dielectric film containing a spin-on-glass (SOG) material having photosensitivity in at least an area between the gate wiring and the source wiring in the region;
forming a hole in the interlayer dielectric film at a position overlapping only one of two outer edges along the longitudinal direction of the gate wiring formed on the base substrate so that a boundary viewed from above between the base substrate and the gate wiring is visually recognized through the hole; and
forming a semiconductor film after the interlayer dielectric film is formed,
wherein the method further comprises:
viewing the position of the boundary through the hole;
forming a film after the interlayer dielectric film is formed while adjusting a position of the film formed after the interlayer dielectric film based on the position of the boundary viewed through the hole.

US Pat. No. 10,115,744

ARRAY SUBSTRATE AND FABRICATION METHOD, DISPLAY PANEL, AND DISPLAY DEVICE

Shanghai Tianma AM-OLED C...

1. An array substrate, comprising: a substrate; a first functional layer configured on one side of the substrate; a first insulating layer configured on the first functional layer facing away from the substrate; a second functional layer configured on the first insulating layer facing away from the substrate; a second insulating layer configured on the second functional layer facing away from the substrate; a third functional layer configured on the second insulating layer facing away from the substrate; a third insulating layer configured on the third functional layer facing away from the substrate; a fourth functional layer configured on the third insulating layer facing away from the substrate; a plurality of through-holes configured to electrically connect different functional layers, wherein a depth of any through-holes does not exceed the thickness of two adjacent insulating layers; and a plurality of pixel driving circuits, wherein a pixel driving circuit comprises a first transistor, wherein a semiconductor layer of the first transistor is located in the first functional layer, a gate electrode of the first transistor is located in the second functional layer, and a source electrode and a drain electrode of the first transistor are both located in the fourth functional layer.

US Pat. No. 10,115,734

SEMICONDUCTOR DEVICE INCLUDING INTERLAYER SUPPORT PATTERNS ON A SUBSTRATE

Samsung Electronics Co., ...

1. A semiconductor device comprising:a stack of interlayer support patterns on a substrate;
a stack of horizontal conductive patterns on the substrate and disposed laterally of the stack of interlayer support patterns;
an interlayer insulating layer interposed between vertically adjacent ones of the interlayer support patterns in the stack of interlayer support patterns, extending between vertically adjacent ones of the horizontal conductive patterns in the stack of horizontal conductive patterns, and disposed parallel to a surface of the substrate, the interlayer insulating layer being in contact with the vertically adjacent ones of the interlayer support patterns;
a conductive structure extending in a direction perpendicular to said surface of the substrate;
first vertical structures each extending vertically through the vertically adjacent ones of the horizontal conductive patterns and the interlayer insulating layer extending between the vertically adjacent ones of the horizontal conductive patterns; and
second vertical structures each extending vertically through the vertically adjacent ones of the interlayer support patterns and the interlayer insulating layer extending between the vertically adjacent ones of the interlayer support patterns,
wherein each of the first vertical structures and each of the second vertical structures includes a channel semiconductor layer extending in a direction perpendicular to the substrate.

US Pat. No. 10,115,722

SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including a plurality of logic cells disposed along a first direction;
active patterns protruding from the substrate; and
a device isolation layer on the substrate, the device isolation layer including a first double diffusion break region that has a first width, as measured along the first direction, and is disposed between a pair of adjacent logic cells and a second double diffusion break region that has a second width, as measured along the first direction, greater than the first width and is disposed between another pair of adjacent logic cells,
wherein the active patterns comprise:
a plurality of pairs of first active patterns spaced apart from each other along the first direction with the first double diffusion break region interposed therebetween; and
a plurality of pairs of second active patterns spaced apart from each other along the first direction with the second double diffusion break region interposed therebetween,
wherein the first active patterns comprise first end portions that are adjacent to a side of the first double diffusion break region and are aligned along a second direction crossing the first direction, and
wherein the second active patterns comprise second end portions that are adjacent to a side of the second double diffusion break region, and wherein one of the second end portions is offset from another of the second end portions along the first direction.

US Pat. No. 10,115,721

PLANAR DEVICE ON FIN-BASED TRANSISTOR ARCHITECTURE

INTEL CORPORATION, Santa...

1. An integrated circuit comprising:a semiconductor substrate having a plurality of fins extending from a surface thereof;
a semiconductor body over a first sub-set of the plurality of fins and having a planar surface, wherein the semiconductor body merges the first sub-set of fins; and
a first planar transistor having a gate body over the planar surface of the semiconductor body.

US Pat. No. 10,115,713

OPTOELECTRONIC ASSEMBLY AND METHOD OF OPERATING AN OPTOELECTRONIC ASSEMBLY

OSRAM Opto Semiconductors...

1. An optoelectronic assembly comprising:a semiconductor chip comprising:at least one first component that emits a first electromagnetic radiation;
a first photosensitive component that controls the first component electrically connected in parallel with the first component and comprises a first radiation-sensitive region arranged in a beam path of the first electromagnetic radiation, wherein the first photosensitive component connected in parallel with the first component is an automatic control of the first component such that the photosensitive component connected in parallel with the first component results in the automatic control without needing to provide an associated open loop control, and the first component and the first photosensitive component are integrated into the semiconductor chip;
a first carrier on which the first component and the first photosensitive component are arranged, wherein on the first carrier a first contact region is configured, a second contact region electrically insulated from the first contact region is configured on the first carrier, the first component comprises a carrier layer and a functional layer deposited on the carrier layer, the carrier layer is configured in an electrically conductive manner, the first photosensitive component is arranged on the first component, a first electrical contact of the first component and a first electrical contact of the first photosensitive component are electrically coupled by a first contact pad, the first contact pad is electrically coupled to the first contact region by a first bond wire, a second electrical contact of the first component is arranged at a bottom side of the first component and is electrically and physically coupled to the second contact region, a second electrical contact of the first photosensitive component is physically connected to the electrically conductive carrier layer of the first component and is electrically coupled to the second contact region, and between the first component and the first photosensitive component and between the first contact pad and the carrier layer, an insulator is formed; and
at least a second component that emits a second electromagnetic radiation and comprises a second photosensitive component electrically connected in parallel with the second component and a second radiation-sensitive region, wherein the second radiation-sensitive region is arranged in the beam path of the second electromagnetic radiation, the second radiation-sensitive region of the second photosensitive component is arranged in the beam path of the first electromagnetic radiation, a second beam filter is arranged in the beam path between the first component and the second photosensitive component, the second beam filter blocking the first electromagnetic radiation, and the second photosensitive component is coated with a beam-filter material of the second beam filter, and
wherein the first radiation-sensitive region of the first photosensitive component is arranged outside of a beam path of the second electromagnetic radiation.

US Pat. No. 10,115,712

ELECTRONIC MODULE

Siliconware Precision Ind...

1. An electronic module, comprising:a first package having an encapsulant and an electronic element embedded in the encapsulant, wherein the encapsulant has opposite first and second surfaces, wherein a first circuit structure has a dielectric layer formed on the first surface of the encapsulant and at least a circuit layer formed on the dielectric layer for electrically connecting the electronic element; and
a second package disposed on the first circuit structure formed on the first surface of the encapsulant through a plurality of conductive elements, wherein the second package has an insulating layer having opposite third and fourth surfaces and an antenna structure formed on the third surface of the insulating layer and extending through the insulating layer, the insulating layer being bonded to the first surface of the encapsulant via the fourth surface thereof and the antenna structure being electrically connected to the circuit layer and the electronic element, wherein a metal layer is formed on the fourth surface of the insulating layer and electrically connected to the antenna structure and at least one of the conductive elements, and wherein the metal layer is free from being in contact with the first circuit structure.

US Pat. No. 10,115,710

PACKAGE INCLUDING A PLURALITY OF STACKED SEMICONDUCTOR DEVICES, AN INTERPOSER AND INTERFACE CONNECTIONS

1. A package, comprising:a first dynamic random access memory (DRAM) semiconductor device, a second DRAM semiconductor device, and a third DRAM semiconductor device stacked in a first direction above a first surface of an interposer;
a first wiring formed in the interposer providing an electrical connection essentially orthogonal to and between the first surface and a second surface, opposite the first surface, of the interposer;
a first external connection formed on the second surface of the interposer, the first wiring electrically connected at a central portion of the first external connection, the first external connection configured to receive a first power supply potential;
the first DRAM semiconductor device includes a first through via, the first through via providing an electrical connection between a first surface and a second surface of the first DRAM semiconductor device;
the second DRAM semiconductor device includes a second through via, the second through via providing an electrical connection between a first surface and a second surface of the second DRAM semiconductor device;
the third DRAM semiconductor device includes a third through via, the third through via providing an electrical connection between a first surface and a second surface of the third DRAM semiconductor device;
a first interface connection formed between the first DRAM semiconductor device and the second DRAM semiconductor device providing an electrical connection between the first and second through vias;
a second interface connection formed between the second DRAM semiconductor device and the third DRAM semiconductor device providing an electrical connection between the second and third through vias;
a third interface connection formed between the interposer and the first DRAM semiconductor device providing an electrical connection between the first wiring and the first through via, the first wiring providing an electrical connection between the third interface connection and the first external connection;
a second wiring formed in the interposer providing an electrical connection essentially orthogonal to and between the first surface and the second surface, opposite the first surface, of the interposer; and
a second external connection formed on the second surface of the interposer, the second wiring electrically connected at a central portion of the second external connection, the second external connection configured to receive a first data signal.

US Pat. No. 10,115,706

SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor chip comprising a plurality of input/output units, the semiconductor chip comprising:a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads comprise at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and
a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads comprise at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further comprise a third pad through which a signal is input and/or output,
wherein the at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units, and
wherein, when the plurality of additional pads comprise the first additional pad and the plurality of pads comprise the first pad, the first additional pad is electrically connected to the first pad through an internal interconnection underneath the surface.

US Pat. No. 10,115,702

SEMICONDUCTOR CHIP FOR SENSING TEMPERATURE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

Samsung Electronics Co., ...

1. A semiconductor system comprising:a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor; and
a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information, the second temperature sensor configured to generate a control signal based on the first temperature information and temperature measured by the second temperature sensor, the control signal adjusting an operation performed on the second chip, wherein
the second chip is a dynamic random access memory (DRAM) chip, and
the control signal is configured to determine a self-refresh interval of the DRAM chip.

US Pat. No. 10,115,701

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS BY BACKSIDE VIA REVEAL WITH CMP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a semiconductor wafer;
forming a plurality of openings in the semiconductor wafer;
forming a plurality of conductive vias in the plurality of openings in the semiconductor wafer, respectively;
removing a portion of the semiconductor wafer to leave a respective portion of each conductive via of the plurality of conductive vias extending above the semiconductor wafer;
forming a first insulating layer over the plurality of conductive vias and semiconductor wafer, wherein the first insulating layer includes a first planar top surface that extends uniformly across an entire surface of the semiconductor wafer;
planarizing the first insulating layer and the plurality of conductive vias together to form a second planar top surface of the first insulating layer, wherein the second planar top surface of the first insulating layer extends as a uniform plane to each respective conductive via of the plurality of conductive vias;
forming a conductive layer over the plurality of conductive vias and the second planar top surface of the first insulating layer, wherein a surface of the conductive layer opposite the semiconductor wafer is planar across an entire width of the conductive layer and the conductive layer extends outside a footprint of each respective opening of the plurality of openings in the semiconductor wafer to contact the second planar top surface of the first insulating layer, and wherein the second planar top surface of the first insulating layer is exposed between portions of the conductive layer;
singulating the semiconductor wafer into a plurality of semiconductor die, wherein a first semiconductor die of the plurality of semiconductor die includes a first conductive via of the plurality of conductive vias and a second semiconductor die of the plurality of semiconductor die includes a second conductive via of the plurality of conductive vias; and
disposing the first semiconductor die of the plurality of semiconductor die over the second semiconductor die of the plurality of semiconductor die, wherein a conductive bump is in direct physical contact with the first conductive via of the plurality of conductive vias of the first semiconductor die of the plurality of semiconductor die and a first portion of the conductive layer on the second semiconductor die of the plurality of semiconductor die.

US Pat. No. 10,115,700

POWER MODULE, ELECTRICAL POWER CONVERSION DEVICE, AND DRIVING DEVICE FOR VEHICLE

Hitachi, Ltd., Tokyo (JP...

1. A power module, comprising:a first switching device; and
a second switching device connected in parallel to the first switching device and having a threshold voltage higher than that of the first switching device,
the second switching device being mounted at a first location at which a temperature of the power module during operation is higher than a temperature of the power module at a second location at which the first switching device is mounted,
wherein each of the first switching device and the second switching device is an SiC-MOSFET.

US Pat. No. 10,115,699

METHOD FOR MANUFACTURING WIRE BONDING STRUCTURE, WIRE BONDING STRUCTURE, AND ELECTRONIC DEVICE

ROHM CO., LTD., Kyoto (J...

12. A wire bonding structure comprising:a first joining target having a first surface;
a second joining target; and
a wire joined to both the first joining target and the second joining target,
wherein the wire is made of Cu and has a circular cross-sectional shape with a diameter of 150 to 1000 ?m, the circular cross-sectional shape having a curvature depending on the diameter,
the wire includes a bonding part joined to the first joining target,
the bonding part has an outer circumferential surface and a joining surface joined to the first joining target,
the joining surface is withdrawn toward a central axis of the wire from the outer circumferential surface and elongated along the central axis,
in a cross-section perpendicular to the central axis of the wire, the bonding part comprises first, second and third arcs spaced apart from each other about the central axis,
the first arc is disposed opposite to the joining surface with respect to the central axis, and the second arc and the third arc are spaced apart from each other via the joining surface, and
each of the first, the second and the third arcs has a curvature that is equal to the curvature of the circular cross-sectional shape of the wire.

US Pat. No. 10,115,698

METHOD FOR DIRECT ADHESION VIA LOW-ROUGHNESS METAL LAYERS

1. A method for assembling a first substrate and a second substrate via metal bonding layers, comprising: depositing, onto a surface of each of the first and second substrates, a metal layer having a thickness which is controlled to limit surface roughness of the metal layer below a roughness threshold; exposing the metal layers to air; contacting the metal layers after the metal layers have been exposed to air, the surface roughness of the contacted metal layers being that obtained at an end of the depositing, and directly bonding the first and second substrates through the contacted metal layers; wherein the bonding is made without applying physical pressure to the assembly of the first and second substrates resulting from contacting the metal bonding layers.

US Pat. No. 10,115,697

COUPLING ELEMENT, INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATION THEREFOR

NXP USA, INC., Austin, T...

1. A coupling element for providing external coupling to a semiconductor die within an integrated circuit package; the coupling element comprising a flexible laminate structure comprising:a flexible, electrically insulating substrate layer;
a first conductive layer bonded to a first surface of the substrate layer, the first conductive layer comprising a first bonding area for bonding directly to a first respective bonding pad of the semiconductor die; and
a second conductive layer bonded to a second surface of the substrate layer, wherein:
the coupling element is arranged to be coupled to the semiconductor die such that the first and second conductive layers are electrically coupled to electrical contacts of the semiconductor die, the second conductive layer comprising a second bonding area for bonding directly to a second respective bonding pad of the semiconductor die; and
the coupling element is further arranged to extend through the integrated circuit package when electrically coupled to the semiconductor die, and for the first and second conductive layers to be further electrically coupled to at least one external component.

US Pat. No. 10,115,696

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

INNOLUX CORPORATION, Mia...

1. An electronic device, comprising:a first substrate;
an adhesion layer disposed on the first substrate and comprising a condensation product of silane or derivatives thereof;
an inorganic layer disposed on the adhesion layer; and
an active unit disposed on the inorganic layer;
wherein the silane or the derivatives thereof is represented by the following formula (I):

wherein each of R1, R2 and R3 is H.

US Pat. No. 10,115,695

SOLID-STATE IMAGING DEVICE

TOHOKU-MICROTEC CO., LTD,...

1. A solid-state imaging device comprising:a detector substrate having a first main-surface, on which a plurality of first lands are arranged in a matrix;
a signal-circuit substrate having a second main-surface, on which plurality of second lands are arranged so as to face the arrangement of the first lands; and
a plurality of tubular bumps, each of which having a flattened plane pattern, and is provided between each of the plurality of first lands and each of the plurality of second lands, the plurality of tubular bumps respectively having major-axis directions to define inclined angles, being arranged in the matrix such that the inclined angles differ depending on locations of the plurality of tubular bumps.

US Pat. No. 10,115,694

ELECTRONIC DEVICE, ELECTRONIC DEVICE FABRICATION METHOD, AND ELECTRONIC APPARATUS

FUJITSU LIMITED, Kawasak...

1. An electronic device fabrication method comprising:preparing an electronic part including:
a first substrate having first terminals over a first surface and having a concavity in a second surface opposite to the first surface;
a filler placed in the concavity; and
a flat plate placed over the second surface with the filler therebetween; and
making the first surface of the electronic part face a third surface of a second substrate having second terminals over the third surface and bonding the first terminals and the second terminals together,
the preparing the electronic part includes:
sucking and holding the first surface of the first substrate on a first sucking surface;
placing the filler in the concavity of the first substrate sucked and held; and
placing the flat plate over the second surface of the first substrate sucked and held with the filler therebetween.

US Pat. No. 10,115,693

SOLDER LAYER OF A SEMICONDUCTOR CHIP ARRANGED WITHIN RECESSES

LONGITUDE LICENSING LIMIT...

1. A semiconductor chip comprising:a semiconductor substrate;
a plurality of bump electrodes provided on one face side of said substrate;
a plurality of recesses provided on the other face side of said substrate;
a solder layer arranged within said recesses, wherein said recesses are formed so as to have a smaller aperture area from said other face side of said substrate towards said one face side thereof, and wherein the solder layer completely fills said recesses; and
a circuit forming layer disposed between the solder layer and the plurality of bump electrodes.

US Pat. No. 10,115,692

METHOD OF FORMING SOLDER BUMPS

International Business Ma...

1. A method of forming solder bumps, the method includes:preparing a substrate having a surface on which a plurality of electrode pads are formed;
forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads;
forming a conductive pillar in each of the openings of the resist layer;
forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer;
filling molten solder in each of the openings in which the conductive layers has been formed, wherein the conductive layers include metals having a same composition ratio as a composition ratio of metals of the molten solder; and
removing the resist layer.

US Pat. No. 10,115,691

MODULE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

CANON KABUSHIKI KAISHA, ...

1. A module, comprising:an electronic component having a first electrode;
a mounting board having a second electrode;
a solder-bump configured to connect the first electrode and the second electrode; and
a thermoplastic resin member configured to contact both the first electrode and the second electrode and cover the solder-bump, so as to form a space between the electronic component and the mounting board.

US Pat. No. 10,115,690

METHOD OF MANUFACTURING MICRO PINS AND ISOLATED CONDUCTIVE MICRO PIN

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing micro pins, the method comprising:forming a release layer over a substrate;
forming a pattern layer over the release layer, wherein the pattern layer has a plurality of openings spaced apart from each other and through the pattern layer;
forming a plurality of micro pins respectively in the openings;
removing the pattern layer and the release layer to obtain the micro pins; and
after removing the pattern layer and the release layer, rounding corners of the micro pins, wherein rounding the corners of the micro pins includes performing a ball mill process on the micro pins.

US Pat. No. 10,115,689

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a first semiconductor substrate having a first wiring electrode on a first surface thereof;
a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode;
a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface; and
a first bump comprising a bump diameter of 30 ?m or less connected to the first bump electrode,
wherein the width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer.

US Pat. No. 10,115,688

SOLDER METALLIZATION STACK AND METHODS OF FORMATION THEREOF

INFINEON TECHNOLOGIES AG,...

1. A method of forming a semiconductor device, the method comprising:forming active circuitry and devices at a first semiconductor surface of a semiconductor substrate having a first side and an opposite second side, the first side having the first semiconductor surface, the second side having a second semiconductor surface;
providing a contact metal layer under the second semiconductor surface of the semiconductor substrate, the contact metal layer comprising aluminum, the second semiconductor surface being opposite to the first semiconductor surface, the contact metal layer physically contacting and covering all of the second semiconductor surface of the semiconductor substrate, the contact metal layer being provided at the second side of the semiconductor substrate;
at the second side, forming a diffusion barrier layer under the contact metal layer, wherein the diffusion barrier layer covers all of the contact metal layer and is a different material than the contact metal layer;
at the second side, forming an inert layer under the diffusion barrier layer, wherein the inert layer comprises a different material than the diffusion barrier layer;
at the second side, forming a solder active layer under the inert layer, wherein the inert layer comprises a different material than the solder active layer; and
at the second side, forming a conductive capping layer under the solder active layer,
wherein the contact metal layer, the diffusion barrier layer, the inert layer, the solder active layer, and the conductive capping layer form a solder metallization stack and wherein each layer in the solder metallization stack is coterminous with the second semiconductor surface of the semiconductor substrate.

US Pat. No. 10,115,687

METHOD OF PATTERN PLACEMENT CORRECTION

APPLIED MATERIALS, INC., ...

1. A method for correcting a pattern placement on a substrate, the method comprising:detecting three reference points for a substrate;
detecting a plurality of sets of three die location points, each set indicative of an orientation of a die, the plurality of sets include a first set associated with a first die and a second set associated with a second die;
calculating a local transformation for an orientation of the first die and the second die on the substrate;
selecting three orientation points from the plurality of sets of three die location points wherein the orientation points are not members of the same set;
calculating a first global transformation of the substrate from the selected three points from the set of points; and
storing the first global transformation and the local transformation for the substrate.

US Pat. No. 10,115,679

TRENCH STRUCTURE AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A trench structure comprising:a top metal layer;
a silicon carbide (SiC) layer on the top metal layer;
a first passivation layer overlying the SiC layer; and
a second passivation layer overlying the first passivation layer,
wherein
a first sidewall of the trench structure, a second sidewall of the trench structure, and the top metal layer form a trench, and
at least one of the first sidewall or the second sidewall comprises:
a sidewall of the SiC layer; and
a sidewall of the second passivation layer,
wherein a portion of the second passivation layer is between the first passivation layer and the at least one of the first sidewall or the second sidewall.

US Pat. No. 10,115,676

INTEGRATED CIRCUIT AND METHOD OF MAKING AN INTEGRATED CIRCUIT

NXP B.V., Eindhoven (NL)...

1. An integrated circuit comprising:a semiconductor substrate; and
a metallization stack located on a major surface of the semiconductor substrate, the metallization stack comprising a plurality of metal layers including patterned metal features, wherein each metal layer of the metallization stack is separated by an intervening dielectric layer,
wherein the metallization stack forms a first grid including patterned metal features for supplying power and providing signal connections to components of the integrated circuit located in the semiconductor substrate, and
wherein the metallization stack also forms a second grid for securing the integrated circuit against electromagnetic attacks, wherein the second grid includes patterned metal features interspersed with the patterned metal features of the first grid in at least some of the metal layers of the metallization stack, and wherein the patterned metal features of the second grid are electrically connected to the first grid.

US Pat. No. 10,115,675

PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A PACKAGED SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A packaged semiconductor device, comprising:a first package structure having a first cut edge, wherein the first package structure comprises a die, a molding compound and at least one outer via, the die and the outer via are encapsulated by the molding compound, and the outer via penetrates the molding compound;
at least one outer conductive bump disposed on the first package structure and having a second cut edge;
a second package structure jointed onto the first package structure;
a sealing material disposed on the first package structure, surrounding the second package structure, and covering the outer conductive bump, wherein the sealing material has a third cut edge and the sealing material is in physical contact with the outer conductive bump; and
an electromagnetic interference (EMI) shielding layer disposed over the first cut edge, the second cut edge, and the third cut edge, and being in electrical contact with the outer conductive bump, wherein the EMI shielding layer is electrically connected with the outer via through the outer conductive bump.

US Pat. No. 10,115,674

SEMICONDUCTOR DEVICE INCLUDING ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING LAYER AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method for manufacturing a semiconductor device, comprising:providing a substrate having a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface;
providing a semiconductor chip on the first surface;
forming a resin portion that seals the semiconductor chip;
forming a conductive film on an upper surface of the resin portion and a side surface of the resin portion, the conductive film being electrically connectable to a ground potential source; and
forming a film stack including a first film that is a metal oxide film formed by depositing metal in an oxygen containing environment or a metal nitride film formed by depositing metal in a nitrogen containing environment, wherein
a lightness value of the film stack is less than a lightness value of the resin portion.

US Pat. No. 10,115,673

EMBEDDED SUBSTRATE PACKAGE STRUCTURE

1. An embedded substrate package structure, comprising: a first substrate being disposed with a plurality of first through holes, and having an upper surface and a lower surface disposed respectively with a first upper wire layer and a first lower wire layer, the first upper wire layer and the first lower wire layer being electrically connected by the plurality of first through holes;a first dielectric layer covering the first lower wire layer on the lower surface of the first substrate, and having a plurality of openings located at a position of the first lower wire layer to expose a portion of a surface of the first lower wire layer, and the exposed surface being disposed with a conductive bump;
a second dielectric layer covering the first upper wire layer on the upper surface of the first substrate, and having a plurality of openings located at a position of the first upper wire layer to expose a portion of a surface of the first upper wire layer, and the exposed surface being disposed with a conductive bump, and the conductive bump comprising a solder bump and an under-bump metallurgy;
a second substrate being disposed with at least a cavity and a plurality of second through holes, the at least a cavity being for accommodating a chip, and the second substrate having an upper surface and a lower surface disposed respectively with a second upper wire layer and a second lower wire layer;
a third dielectric layer covering the second lower wire layer on the lower surface of the second substrate, and having a plurality of openings located at a position of the second lower wire layer to expose a portion of a surface of the second lower wire layer, and the exposed surface being disposed with a conductive bump, and the conductive bump comprising a solder bump and an under-bump metallurgy;
a fourth dielectric layer covering the second upper wire layer and the chip, serving as a protective layer of the back of the chip, and having a plurality of openings located at a position of the second upper wire layer to expose a portion of a surface of the second upper wire layer, and the exposed surface being disposed with a conductive bump, and the conductive bump comprising a solder bump and an under-bump metallurgy; and
a fifth dielectric layer covering surroundings of the chip to fill gaps between the chip and the cavity and fixing the chip to inside of the cavity, wherein the second dielectric layer and the third dielectric layer respectively have a plurality of openings at positions of the cavity, inside of the plurality of openings being disposed with an under bump metallurgy or a solder bump, and a conductive bump or a solder bump is formed on a pad of the chip, the chip being disposed in the cavity and electrically connected to the first upper wire layer of the first substrate through the conductive bump or the solder bump.

US Pat. No. 10,115,646

SEMICONDUCTOR ARRANGEMENT, SEMICONDUCTOR SYSTEM AND METHOD OF FORMING A SEMICONDUCTOR ARRANGEMENT

INFINEON TECHNOLOGIES AG,...

1. A semiconductor arrangement, comprising:an electrically conductive plate having a top surface;
a plurality of power semiconductor devices arranged on the top surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices is electrically coupled to the electrically conductive plate;
a plurality of electrically conductive blocks, each electrically conductive block being electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and
encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the top surface of the electrically conductive plate is free from the encapsulation material.

US Pat. No. 10,115,645

REPACKAGED RECONDITIONED DIE METHOD AND ASSEMBLY

Global Circuit Innovation...

1. A method comprising:removing one or more existing ball bonds from an extracted die, the extracted die comprising a fully functional semiconductor die removed from a previous package;
reconditioning die pads of the extracted die to create a reconditioned die, reconditioning comprising applying a plurality of metallic layers to the die pads;
securing the reconditioned die within a cavity of a new package base;
providing a plurality of bond connections interconnecting the reconditioned die pads and package leads or downbonds of the new package base;
applying an encapsulating compound over the reconditioned die and the plurality of bond connections to create an assembled package base, the encapsulating compound configured to exhibit low thermal expansion; and
securing a lid to the new package base.

US Pat. No. 10,115,634

SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS AND METHOD OF MANUFACTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor component comprising:a semiconductor substrate having an opening;
a first dielectric liner having a first stress over an interior surface of the opening;
a second dielectric liner having a second stress over the first dielectric liner, wherein a direction of the first stress is opposite a direction of the second stress; and
a conductive material over the second dielectric liner.

US Pat. No. 10,115,627

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a base;
a memory cell region on the base comprising a first plurality of conductive layers including first and second portions, and a first plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers;
a first stacked body on the base comprising a second plurality of insulating layers and a second plurality of conductive layers fewer than the number of the first plurality of conductive layers, each of the conductive layers of the second plurality being connected to one of the conductive layers of the first portion of the first plurality, wherein an insulating layer of the second plurality of insulating layers extends between, and separates, each two adjacent conductive layers of the second plurality of conductive layers, an end portion of the first stacked body having a first stair portion having a first stair-like shape wherein a surface of each of the second plurality of conductive layers is exposed; and
a second stacked body on the base comprising a third plurality of insulating layers and a third plurality of conductive layers fewer in number than the first plurality of conductive layers, each of the conductive layers of the third plurality being connected to one of the conductive layers of the second portion of the first plurality, wherein an insulating layer of the third plurality of insulating layers extends between, and separates, each two adjacent conductive layers of the third plurality of conductive layers, an end portion of the second stacked body having a second stair portion having a second stair-like shape wherein a surface of each of the third plurality of conductive layers is exposed, the second stair portion spaced from the first stair portion by a first distance, wherein
the lowermost layer of the first stacked body is in contact with the base and the lowermost layer of the second stacked body is in contact with the base.

US Pat. No. 10,115,624

METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION

Taiwan Semiconductor Manu...

1. A method comprising:forming a plurality of fin elements extending from a substrate using a hardmask layer;
forming isolation features disposed between adjacent fin elements;
irradiating the isolation features using a first pulsed laser beam having a first pulse duration,
wherein prior to the irradiating the isolation features, the isolation features have a first etch rate in a first solution, and
wherein after the irradiating the isolation features, a top portion of the isolation features has a second etch rate less than the first etch rate in the first solution, and a bottom portion of the isolation features has the first etch rate;
after the irradiating the isolation features, removing the hardmask layer over the substrate by an etching process using the first solution;
forming a gate structure over the plurality of fin elements;
depositing an inter-level dielectric (ILD) layer over the gate structure; and
irradiating the ILD layer using a second pulsed laser beam having a second pulse duration different from the first pulse duration.

US Pat. No. 10,115,621

METHOD FOR IN-DIE OVERLAY CONTROL USING FEOL DUMMY FILL LAYER

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:providing parallel structures in a first layer on a substrate;
determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements;
forming overlay trenches with a first reticle, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures;
determining a trench center-of-gravity of an overlay trench by measuring a first distance from a first edge of the overlay trench to the structure with a critical dimension scanning electron microscope (CDSEM); and measuring a second distance from a second edge, opposing the first edge, of the overlay trench to the structure with the CDSEM;
determining a structure center-of-gravity of a structure exposed in the overlay trench;
determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity; and
upgrading the first reticle with a second reticle.

US Pat. No. 10,115,611

SUBSTRATE COOLING METHOD, SUBSTRATE TRANSFER METHOD, AND LOAD-LOCK MECHANISM

TOKYO ELECTRON LIMITED, ...

1. A substrate cooling method for, by using a load-lock mechanism for controlling a pressure therein between a first pressure and a second pressure in the case of transferring the substrate between a first module maintained at a first pressure close to an atmospheric pressure and a second module maintained at a second pressure in a vacuum state, cooling a high-temperature substrate transferred from the second module to the first module, the load-lock mechanism including a chamber accommodating a substrate, a cooling member disposed in the chamber and configured to cool the substrate disposed proximate to the cooling member, a gas exhaust unit configured to exhaust the chamber, and a purge gas inlet unit configured to introduce a purge gas into the chamber, the method comprising:maintaining a pressure in the chamber to the second pressure, allowing the chamber to communicate with the second module, and loading the high-temperature substrate into the chamber;
placing the substrate to a cooling position close to the cooling member;
exhausting the chamber to a third pressure at which a region between a surface of the cooling member and a backside of the substrate satisfies a molecular flow condition to obtain uniform temperature distribution of the substrate; and
after maintaining the third pressure in the chamber at the third pressure for a first duration, introducing a purge gas into the chamber to increase the pressure in the chamber to the first pressure, and cooling the substrate by using the cooling member.

US Pat. No. 10,115,608

METHOD AND APPARATUS FOR RAPID PUMP-DOWN OF A HIGH-VACUUM LOADLOCK

Novellus Systems, Inc., ...

1. An apparatus configured to be installed as part of a semiconductor processing tool, the semiconductor processing tool selected from the group consisting of: a semiconductor processing tool having one or more process chambers and a loadlock with a loadlock volume, and a semiconductor processing tool having one or more process chambers, a loadlock with a loadlock volume, and one or more transfer chambers, the apparatus comprising:a housing having internal surfaces defining a gas expansion volume, wherein the gas expansion volume is at least one and a half times larger than the loadlock volume;
a gas expansion volume valve, wherein:
the housing is configured to connect with the loadlock such that the gas expansion volume valve is interposed between the loadlock volume and the gas expansion volume when so connected,
the gas expansion volume is configured to be separate from the one or more process chambers and separate from any transfer chamber of the semiconductor processing tool,
the gas expansion volume valve is configured to be movable between an open state and a closed state,
the gas expansion volume valve permits fluidic communication between the loadlock volume and the gas expansion volume when in the open state and when the apparatus is connected with the loadlock, and
the gas expansion volume valve prevents fluidic communication between the loadlock volume and the gas expansion volume when in the closed state and when the apparatus is connected with the loadlock;
a first mechanism that comprises a high-vacuum pump configured to evacuate gas from the housing regardless of whether the gas expansion volume valve is in the open state or the closed state; and
a controller with at least one processor and a memory, the memory storing computer-executable instructions for controlling the at least one processor to:
a) control the gas expansion volume valve to enter the closed state;
b) cause the loadlock to be fluidically isolated from the one or more process chambers;
c) control a roughing pump to, after (a) and (b), evacuate gas from within the loadlock volume to reach a first lower-than-atmospheric pressure when the gas expansion volume valve is in the closed state;
d) control, after (a), the high-vacuum pump to evacuate gas from within the housing to reach a second lower-than-atmospheric pressure, wherein the second lower-than-atmospheric pressure is lower than the first lower-than-atmospheric pressure; and
e) control, after (c) and (d), the gas expansion valve to enter the open state thereby allowing gas in the gas expansion volume to mix with gas from the loadlock volume and reach equilibrium, wherein:
the first mechanism is fluidically connected with the gas expansion volume,
the first mechanism is configured to control gas pressure within the housing and to cause the pressure in the housing to be reducible to lower than 10E-3 Torr, and
the first mechanism is fluidically isolated from the loadlock volume when the gas expansion volume valve is in the closed state and when the apparatus is connected with the loadlock.

US Pat. No. 10,115,605

VACUUM ASSISTED SEALING PROCESSES AND SYSTEMS FOR INCREASING AIR CAVITY PACKAGE MANUFACTURING RATES

RJR Technologies, Inc., ...

1. A sealing process for air cavity electronic packages comprising the steps of:providing a base and a lid, at least one of the base and the lid having a mating surface coated with an adhesive;
maintaining an air gap between the base and the lid;
generating a vacuum around the base, the lid, and the adhesive;
mating the base and the lid together after the vacuum has been generated to create a mated package assembly with a vacuum therein; and
heating the mated package assembly to a curing temperature to cure the adhesive.

US Pat. No. 10,115,603

REMOVAL OF SURFACE PASSIVATION

ASM IP HOLDING B.V., Alm...

1. A method for removing at least a portion of a passivation film from a substrate surface comprising a first metal surface and a second dielectric surface, the method comprising:exposing the passivation film to a vapor phase organic reactant that is an alcohol, an aldehyde or has the formula R—COOH, where R is hydrogen or a C1 to C3 alkyl,
wherein the passivation film was formed by exposure of the first metal surface to a passivation agent comprising a hydrocarbon, and
wherein the passivation film is not exposed to a plasma during exposure of the passivation film to the vapor phase organic reactant, and
selectively depositing a material on the first metal surface relative to the second dielectric surface.

US Pat. No. 10,115,600

METHOD OF ETCHING SEMICONDUCTOR STRUCTURES WITH ETCH GAS

American Air Liquide, Inc...

1. A method of depositing an etch-resistant polymer layer on a substrate, the method comprising:introducing a vapor of a compound into a reaction chamber containing the substrate, the compound having a formula selected from the group consisting of: C2F4S2 (CAS 1717-50-6), F3CSH (CAS 1493-15-8), F3C—CF2—SH (CAS 1540-78-9), F3C—CH2—SH (CAS 1544-53-2), CHF2—CF2—SH (812-10-2), CF3—CF2—CH2—SH (CAS 677-57-6), F3C—CH(SH)—CF3 (CAS 1540-06-3), F3C—S—CF3 (CAS 371-78-8), F3C—S—CHF2 (CAS 371-72-2), F3C—CF2—S—CF2—CF3 (CAS 155953-22-3), F3C—CF2—CF2—S—CF2—CF2—CF3 (CAS 356-63-8), c(—S—CF2—CF2—CHF—CF2—) (CAS 1035804-79-5), c(—S—CF2—CHF—CHF—CF2—) (CAS 30835-84-8), c(—S—CF2—CF2—CF2—CF2—CF2—) (CAS 24345-52-6), c(—S—CFH—CF2—CF2—CFH—)(2 R, 5 R) (CAS 1507363-75-8), c(—S—CFH—CF2—CF2—CFH—)(2 R, 5 S) (CAS 1507363-76-9), and c(—S—CFH—CF2—CF2—CH2—) (CAS 1507363-77-0); and
plasma activating the compound to form the etch-resistant polymer layer on the substrate.

US Pat. No. 10,115,599

SPECTRALLY AND TEMPORALLY ENGINEERED PROCESSING USING PHOTOELECTROCHEMISTRY

The Board of Trustees of ...

1. A method for fabricating a photodetector integral with a parabolic reflector, the method comprising:a. photoelectroplating a top-contact metal-semiconductor-metal photodetector on a semiconductor wafer; and
b. defining a parabolic surface on the semiconductor wafer by
i. applying an etch solution to the surface of the semiconductor wafer;
ii. generating a spatial pattern of electron-hole pairs by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface of the semiconductor wafer; and
iii. applying an AC electrical potential across the interface of the semiconductor and the etch solution with any specified temporal profile of onset and duration relative to the temporal profile of the spatial pattern of illumination.