US Pat. No. 10,559,840

ION EXCHANGING MEMBRANE, METHOD FOR MANUFACTURING THE SAME AND ENERGY STORAGE SYSTEM COMPRISING THE SAME

KOLON INDUSTRIES, INC., ...

1. An ion exchanging membrane comprising: a porous support including a plurality of pores;a first ion conducting material located on one surface of the porous support; and
a second ion conducting material located on the other surface of the porous support,
wherein the first ion conducting material and the second ion conducting material are polymers including hydrophilic repeating units and hydrophobic repeating units,
the first ion conducting material and the second ion conducting material have different molar ratios of the hydrophilic repeating units and the hydrophobic repeating units,
the first ion conducting material has a molar ratio of the hydrophilic repeating unit to the hydrophobic repeating unit which is higher than the molar ratio of the hydrophilic repeating unit to the hydrophobic repeating unit of the second ion conducting material, and
a thickness ratio of the first ion conducting material and the second ion conducting material is 9:1 to 6:4.

US Pat. No. 10,559,839

SOLID OXIDE FUEL CELL DEVICE AND SYSTEM

1. A solid oxide fuel cell device comprising:an elongate substrate having a length between first and second ends that is at least five times greater than the width, opposing first and second sides along the length, a non-active end region adjacent the first end, and an active end region adjacent the second end;
a first multi-layer anode-cathode structure comprising a plurality of anodes in opposing relation with a plurality of cathodes within the elongate substrate in the active end region and an electrolyte disposed between each of the opposing anodes and cathodes for undergoing a fuel cell reaction when supplied with heat, fuel and oxidizer, wherein the non-active end region lacks the anodes and cathodes in opposing relation and extended length-wise away from the non-active end region without being heated to dissipate heat and to thereby remain at a lower temperature than the active end region when the active end region is supplied with heat;
at least one tab portion extending from each one of the plurality of anodes and cathodes within the active end region of the elongate substrate to one of the opposing first and second sides to form electrical pathways to a respective plurality of exposed anode and cathode surfaces in the active end region;
at least one first exterior metallization on one of the opposing first and second sides in contact with at least one exposed anode in the active end region and extending length-wise to the non-active end region for electrical connection at the lower temperature;
at least one second exterior metallization on one of the opposing first and second sides in contact with at least one exposed cathode in the active end region and extending length-wise to the non-active end region for electrical connection at the lower temperature; and
one or more third exterior metallizations on one or both of the opposing first and second sides, applied over at least one pair of adjacent exposed anode and cathode surfaces to electrically connect respective anodes and cathodes in series in the active end region.

US Pat. No. 10,559,837

FLUID CONTROL VALVE

NISSAN MOTOR CO., LTD., ...

1. A fluid control valve connected to a wet gas flow passage in order to control a flow of wet gas, comprising:an introduction passage for introducing the wet gas into the fluid control valve;
a filter that is formed in a tubular shape and has a hole in a tubular side face thereof such that water is suctioned up over the tubular side face;
a guiding passage disposed above the filter provided to extend upward from an upper portion of the filter;
a valve port disposed above the introduction passage and constituted by an upper portion open end of the guiding passage;
a discharge passage that discharges the wet gas that has passed through the filter from the fluid control valve through the valve port; and
a valve portion that opens and closes the valve port using a valve body,
wherein the filter is configured to be disposed in a lowermost point of the introduction passage.

US Pat. No. 10,559,836

METHOD AND ARRANGEMENT FOR DISTRIBUTING REACTANTS INTO A FUEL CELL OR INTO AN ELECTROLYZER CELL

ELCOGEN OY, Vantaa (FI)

1. A solid oxide fuel cell including a fuel flow guiding arrangement, the solid oxide fuel cell having a fuel side, an air side, and an electrolyte element between the fuel side and the air side, wherein the arrangement comprises:a flow field plate for each cell to arrange air flow on a first side of the flow field plate and fuel flow on a second side of flow field plate;
a flow distribution area on the flow field plate;
a flow outlet area on the flow field plate;
a side gas channel of the fuel cell located perpendicularly to a main flow direction of the fuel flow channel area for guiding fuel feed flow to the fuel distribution area, the flow distribution area being located outside of an electrochemically active electrolyte element area;
an air inflow and outflow to and from respectively, an electrolyte element in one of the same flow direction and opposite flow direction with the main fuel flow;
a flow adjusting structure for turning about 90° at least one of a fuel feed flow on the flow distribution area and fuel outlet flow on the flow outlet area, the flow adjusting structure including flow restriction orifices, each having a geometrical shape defining fuel flow volume of parallel fuel flow channels in order to equalize flow distribution on the electrolyte element, the flow adjusting structure being located outside of the electrochemically active electrolyte element area; and
the flow adjusting structure having at least partly an elliptical shape as said at least one geometrical shape, wherein the solid oxide fuel cell is configured to operate at a temperature range of 500°-1000° C.

US Pat. No. 10,559,835

RESIN-FRAMED MEMBRANE-ELECTRODE ASSEMBLY FOR FUEL CELL

HONDA MOTOR CO., LTD., T...

1. A resin-framed membrane-electrode assembly for a fuel cell, comprising:a stepped membrane-electrode assembly comprising:
a polymer electrolyte membrane having a first surface and a second surface which is opposite to the first surface and which has an outer perimeter surface portion;
a first electrode disposed on the first surface of the polymer electrolyte membrane; and
a second electrode disposed on the second surface of the polymer electrolyte membrane, the first electrode having planar dimensions larger than planar dimensions of the second electrode, the outer perimeter surface portion of the second surface of the polymer electrolyte membrane extending outward along the second surface from an end of the second electrode so as to be exposed from the second electrode; and
a resin frame member surrounding an outer perimeter of the polymer electrolyte membrane and comprising:
an inner perimeter base end; and
an inner protruding portion having a thickness and protruding from the inner perimeter base end toward a second electrode side, the inner protruding portion including a raised portion and a flat surface portion which extends from the raised portion toward the second electrode side to face the outer perimeter surface portion of the second surface of the polymer electrolyte membrane and on which an adhesive layer is provided so that the adhesive layer lies at least between the flat surface portion and the outer perimeter surface portion, the adhesive layer having a tapered shape in which a thickness of the adhesive layer increases from a tip of the inner protruding portion toward the inner perimeter base end, the flat surface portion extending from the raised portion to the tip.

US Pat. No. 10,559,834

SEPARATOR FOR FUEL CELL

Hyundai Motor Company, S...

3. A separator for a fuel cell having a plurality of channels, which are formed in a reaction surface in a direction of gravity and configured to allow reaction gas and generated water to flow therethrough,wherein the channels have a wave shape in the reaction surface, each of channels including alternately arranged curved portions and straight portions,
wherein each of the curved portions of the channels has a larger width than each of the straight portions, and
wherein a side wall of a land located adjacent to each of a reaction gas inflow region and a reaction gas exhaust region of each of the curved portions of the channels is inclined at an angle smaller than an angle at which a side wall of a land located adjacent to a middle region of each of the curved portions is inclined.

US Pat. No. 10,559,833

FUEL CELL STACK

Toyota Jidosha Kabushiki ...

1. A fuel cell stack comprising a plurality of stacked cells each having separators,wherein:
a base material of each of separators used for an end cell located at a positive-side end of the fuel cell stack and a base material of each of separators used for cells other than the end cell are different metallic materials, and
the base material of each of the separators used for the end cell is a material with higher corrosion resistance than the base material of each of the separators used for the cells other than the end cell.

US Pat. No. 10,559,832

CELL FOR STORING POWER, COMPRISING AT LEAST ONE MALE ELEMENT AND ONE FEMALE ELEMENT EQUIPPED WITH ELECTRICAL CONNECTION INTERFACES

1. A cell for storing power, configured to be integrated into an electrical module for assembling a power storage system, opposite the first surface, comprising:a non-conductive outer casing having a first surface and a second surface;
on one of the first and second surfaces, at least one male element, and on the other of the first and second surfaces, at least one female element, said at least one male element and at least one female element having shapes that allow for their fitting into one another in such a way that the cell is configured to be assembled to another cell of the same type, said at least one male element or said at least one female element of the cell being configured to respectively fit with at least one female element or at least one male element of the other cell of the same type,
wherein at least one male element of said at least one male element and at least one female element comprises at least one electrical connection interface having positive polarity and wherein at least one female element of said at least one male element and at least one female element comprises at least one electrical connection interface having negative polarity, or inversely, in such a way that the cell is configured to be electrically connected to the other cell of the same type,
said male element has a first outer layer projected from the one of the first and second surfaces and formed of a non-conductive material and first side layers connecting the outer surface to the one of the first and second surfaces each formed the non-conductive material, and
said at least one electrical connection interface of said male element being exposed only in a region of said male element beneath the first outer layer and between the first side layers, and
an electrical core comprising a negative electrode, a positive electrode and an electrolyte located between the negative electrode and the positive electrode, covered by a packaging configured in such a way as to not cover said at least one electrical connection interface having positive polarity and an electrical connection interface having negative polarity.

US Pat. No. 10,559,827

ELECTROCHEMICAL CELL HAVING SOLID IONICALLY CONDUCTING POLYMER MATERIAL

Ionic Materials, Inc., W...

1. An electrochemical cell for producing electrical energy via an electrochemical reaction comprising:an anode; and
a cathode;
wherein at least one of the anode and the cathode comprise a solid ionically conducting polymer material;
wherein the solid ionically conducting polymer material can ionically conduct hydroxyl ions, whereby the solid ionically conducting polymer material can conduct hydroxyl ions during said electrochemical reaction; and
wherein the solid ionically conducting polymer material has a crystallinity index of at least or greater that about 30%.

US Pat. No. 10,559,826

MULTIVALENT METAL ION BATTERY HAVING A CATHODE OF RECOMPRESSED GRAPHITE WORMS AND MANUFACTURING METHOD

Global Graphene Group, In...

1. A multivalent metal-ion battery comprising an anode, a cathode, a porous separator electronically separating said anode and said cathode, and an electrolyte in ionic contact with said anode and said cathode to support reversible deposition and dissolution of a multivalent metal, multivalent selected from Ni, Zn, Be, Mg, Ca, Ba, La, Ti, Ta, Zr, Nb, Mn, V, Co, Fe, Cd, Cr, Ga, In, or a combination thereof, at said anode, wherein said anode contains said multivalent metal or its alloy as an anode active material and said cathode comprises a cathode layer of an exfoliated graphite or carbon material having inter-flake pores from 2 nm to 10 ?m in pore size,the cathode layer comprises an active layer of recompressed exfoliated graphite or carbon material comprising a physical density of 0.5 to 1.8 g/cm3 and has a meso-scaled pores having a pore size of 2 nm to 50 nm.

US Pat. No. 10,559,825

POSITIVE ELECTRODE ACTIVE MATERIAL AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SANYO Electric Co., Ltd.,...

1. A positive electrode active material comprising a lithium transition metal oxide containing a halogen and a rare-earth compound attached to the surface of each particle of the lithium transition metal oxide,wherein the amount of the halogen present on the surface of the lithium transition metal oxide particle is 5 mass percent or less of the total amount of the halogen contained in the lithium transition metal oxide particle,
a rare-earth element in the rare-earth compound is one other than yttrium and scandium, and
wherein the lithium transition metal oxide containing the halogen comprises a lithium cobalt oxide, represented by the formula LiaCobAcBdOeXf (where A includes at least one selected from Al, Ti, Zr, Ni, and Mn; B includes at least one selected from Mg and Ca; a is 0.8 to 1.2; b is 0.75 to 1.0; c is 0 to 0.25; d is 0 to 0.03; e is 1.9 to 2.1; f is 0.0005 to 0.0035; and X is F).

US Pat. No. 10,559,824

POSITIVE ELECTRODE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY INCLUDING CORE CONTAINING LITHIUM COBALT OXIDE AND SHELL BEING DEFICIENT IN LITHIUM, AND METHOD OF PREPARING THE SAME

LG Chem, Ltd., (KR)

1. A positive electrode active material for a secondary battery, comprising:a core part including lithium cobalt oxide; and
a shell part that is located on a surface of the core part and includes lithium-deficient cobalt oxide which is deficient in lithium because a molar ratio of lithium to cobalt is 0.9 or less,
wherein a molar ratio of lithium:cobalt in the lithium-deficient cobalt oxide of the shell part is in the range of 0.7:1 to 0.9:1,
wherein the lithium cobalt oxide of the core part has a composition of the following Chemical Formula 1:
LiaCo1-bMbO2  (1)
wherein, in Chemical Formula 1, M is each independently one or more selected from the gro up consisting of Ti, Mg, Al, Zr, Ba, Ca, Ti, Ta, Nb, and Mo;
0.95?a?1.02; and
0?b?0.2, and
wherein the lithium-deficient cobalt oxide of the shell part has a composition of the following Chemical Formula 2:
LiaCo1-bMbO2  (2)
Wherein, in Chemical Formula 2, M is each independently one or more selected from the group consisting of Ti, Mg, Al, Zr, Ba, Ca, Ti, Ta, Nb, and Mo;
0.7?a?0.9; and
0?b?0.2.

US Pat. No. 10,559,823

MANGANESE NICKEL COMPOSITE HYDROXIDE AND METHOD FOR PRODUCING SAME, LITHIUM MANGANESE NICKEL COMPOSITE OXIDE AND METHOD FOR PRODUCING SAME, AND NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SUMITOMO METAL MINING CO....

3. A method for manufacturing manganese-nickel complex hydroxide, the method comprising:mixing a solution containing sulfate salts to be used as a manganese source and a nickel source and an alkali mixed aqueous solution which contains sodium hydroxide and sodium carbonate, is obtained by adding sodium carbonate to a sodium hydroxide solution so that a ratio of the number of moles of sodium derived from sodium carbonate to the number of moles of entire sodium is 20% or less, and is used as an alkali aqueous solution; and
depositing a hydroxide by reactive crystallization to obtain the manganese-nickel complex hydroxide according to claim 1.

US Pat. No. 10,559,822

NEGATIVE ELECTRODE ACTIVE MATERIAL, MIXED NEGATIVE ELECTRODE ACTIVE MATERIAL, NEGATIVE ELECTRODE FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY, LITHIUM ION SECONDARY BATTERY, METHOD FOR PRODUCING NEGATIVE ELECTRODE ACTIVE MATERIAL, AND METHOD FOR PRODUCIN

SHIN-ETSU CHEMICAL CO., L...

1. A negative electrode active material, wherein the negative electrode active material is a negative electrode active material comprising negative electrode active material particles;the negative electrode active material particles comprise silicon compound particles comprising a silicon compound (SiOx: 0.5?x?1.6);
the silicon compound particles include at least any one kind or more kinds of Li2SiO3 and Li4SiO4;
the negative electrode active material particles have a loose bulk density BD of 0.5 g/cm3 or more and 0.9 g/cm3 or less, a tapped bulk density TD of 0.7 g/cm3 or more and 1.2 g/cm3 or less, and a compression degree of 25% or less, the compression degree being defined by (TD-BD)/TD.

US Pat. No. 10,559,819

TITANIUM OXIDE, AND ELECTRODE AND LITHIUM ION SECONDARY BATTERY EACH MANUFACTURED USING SAME

KUBOTA CORPORATION, Osak...

4. An electrode, wherein at least part of an electrode active material of the electrode is the titanium oxide compound according to claim 1.

US Pat. No. 10,559,818

NEGATIVE ELECTRODE FOR RECHARGEABLE LITHIUM BATTERY, AND RECHARGEABLE LITHIUM BATTERY INCLUDING SAME

Samsung SDI Co., Ltd., Y...

1. A negative electrode for a rechargeable lithium battery, comprising:a negative active material layer including a negative active material including a Si-based active material; nanoclay; and an aqueous binder; and
a current collector supporting the negative active material layer.

US Pat. No. 10,559,814

NONAQUEOUS ELECTROLYTE BATTERY AND BATTERY PACK

KABUSHIKI KAISHA TOSHIBA,...

1. A nonaqueous electrolyte battery comprising:a positive electrode;
a negative electrode containing monoclinic titanium dioxide or Li4+aTi5O12 (here, ?0.5?a?3) as an active material, and polyvinylidene fluoride with a molecular weight of 400,000 to 1,000,000 as a binder, the negative electrode satisfying a formula (I) below; and
a nonaqueous electrolyte containing at least one of difluorophosphate and monofluorophosphate,
0.1?(P2/P1)?0.4   (I),wherein P1 is an intensity of a peak that appears within a range of 689 to 685 eV in a spectrum according to photoelectron spectrometry of a surface of the negative electrode, and P2 is an intensity of a peak that appears within a range of 684 to 680 eV in the spectrum.

US Pat. No. 10,559,812

NEGATIVE ELECTRODE ACTIVE MATERIAL FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY, NEGATIVE ELECTRODE FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY, NONAQUEOUS ELECTROLYTE SECONDARY BATTERY, AND PRODUCTION METHOD OF NEGATIVE ELECTRODE ACTIVE MATERIAL FOR NON

SHIN-ETSU CHEMICAL CO., L...

1. A negative electrode active material for nonaqueous electrolyte secondary batteries comprising:a particle of negative electrode active material,
wherein the particle of negative electrode active material contains a particle of a silicon compound containing a silicon compound (SiOx: 0.5?x?1.6), on at least a part of a surface of the particle of the silicon compound a carbon coating film being formed, and
the negative electrode active material contains 2% by mass or less and greater than 0% by mass of a particle of silicon dioxide and the negative electrode active material contains a silicon dioxide-carbon composite secondary particle containing a plurality of particles of silicon dioxide and carbon.

US Pat. No. 10,559,811

GRAPHENE-ENHANCED ANODE PARTICULATES FOR LITHIUM ION BATTERIES

SAMSUNG ELECTRONICS CO., ...

1. A lithium-ion battery anode comprising:a particulate comprising an envelope, where the envelope comprises a first graphene sheet and encapsulates:
a plurality of anode active material particles; and
a second graphene sheet; wherein the second graphene sheet is operative to separate some of the anode active material particles from one another.

US Pat. No. 10,559,809

POWER STORAGE DEVICE

SHOWA DENKO PACKAGING CO....

1. A power storage device comprising:a first packaging material in which a first heat resistant resin layer is adhered to one surface of a first metal foil and a first heat fusible resin layer is adhered to the other surface of the first metal foil, wherein the first packaging material is provided with a first inner conducting portion allowing conduction to the first metal foil on a surface of the first heat fusible resin layer side;
a second packaging material in which a second heat resistant resin layer is adhered to one surface of a second metal foil and a second heat fusible resin layer is adhered to the other surface of the second metal foil, wherein the second packaging material is provided with a second inner conducting portion allowing conduction to the second metal foil on a surface of the second heat fusible resin layer side, and
an electrode body including a positive electrode in which a positive electrode active material is coated on a positive electrode current collector, a negative electrode in which a negative electrode active material is coated on a negative electrode current collector, and a separator disposed between the positive electrode and the negative electrode, wherein
the first packaging material is provided with a recess and a flange extending outwardly from an opening edge of the recess, a first outer conducting portion allowing conduction to the first metal foil is formed on a surface of the flange on the first heat resistant resin layer side, and a second outer conducting portion allowing conduction to the second metal foil is formed on a surface of a peripheral edge portion of the second outer packaging material,
a packaging member having an electrode body chamber in which the first inner conducting portion and the second inner conducting portion face in the chamber is formed such that the first heat fusible resin layer of the first packaging material and the second heat fusible resin layer of the second packaging material face each other and the chamber is surrounded by a heat-sealed portion in which the first heat fusible resin layer of the flange of the first packaging material and the second heat fusible resin layer of the peripheral edge portion of the second packaging material are fusion-bonded,
the positive electrode of the electrode body sealed in the electrode body chamber together with an electrolyte is conducted to the first inner conducting portion, and the negative electrode thereof is conducted to the second inner conducting portion, and
at least one of a pair of the first metal foil and the positive electrode current collector and a pair of the second metal foil and the negative electrode current collector is made of the same kind of metal.

US Pat. No. 10,559,806

BATTERY AND BATTERY MODULE

KABUSHIKI KAISHA TOSHIBA,...

1. A battery comprising:a container member comprising a main part and a terminal-connecting part adjacent to the main part;
an electrode body housed in the main part;
a lead electrically connected to the electrode body and housed in the terminal-connecting part;
a terminal electrically connected to the lead and provided on the terminal-connecting part; and
a gasket having a through hole,
wherein a thickness of the main part is larger than a thickness of the terminal-connecting part,
the main part of the container member comprises a main surface of the container member,
the terminal-connecting part of the container member comprises a first surface and a second surface as a reverse side with respect to the first surface, and the second surface faces the lead,
the terminal comprises a first end part and a second end part, the first end part is positioned outside the container member, and the second end part is positioned inside the container member, and
a distance from the first surface of the terminal-connecting part of the container member to a main surface of the first end part of the terminal is smaller than a distance from the first surface to a plane on which the main surface of the container member is positioned,
the terminal-connecting part comprises a rising part comprising a tip projected from the second surface, and a through hole passing through the terminal-connecting part from the first surface to the tip of the rising part, and the through hole comprises a tapered part having a diameter reduced with increasing proximity to the tip of the rising part,
the terminal comprises a main part extending to an axial direction toward the second end part from the first end part, and the main part comprises a diameter-reduction part between the first end part and the second end part, and the diameter-reduction part has a diameter that reduces with increasing proximity to the second end part,
at least a part of the gasket is located in the tapered part of the through hole of the container member,
at least a part of the diameter-reduction part of the main part of the terminal is located in the through hole of the gasket,
the at least a part of the gasket is sandwiched between the tapered part of the container member and the diameter-reduction part of the terminal, and
an inclination angle of the tapered part of the container member to the axial direction of the main part of the terminal is larger than an inclination angle of the diameter-reduction part to the axial direction.

US Pat. No. 10,559,804

BATTERY PACK

Samsung SDI Co., Ltd., G...

1. A battery pack, comprising:a first cell group including one or more cells, wherein the first cell group has first and second electrodes opposing each other;
a second cell group including one or more cells, wherein the second cell group has first and second electrodes opposing each other;
a circuit board electrically connected to the first and second cell groups; and
a connector provided in the circuit board and including a plurality of connector terminals,
wherein the connector terminals include:
a first connector terminal electrically connected to the first electrode of the first cell group;
a second connector terminal electrically connected to the second electrode of the first cell group;
a third connector terminal electrically connected to the first electrode of the second cell group; and
a fourth connector terminal electrically connected to the second electrode of the second cell group, and
wherein the first and third connector terminals are configured to be electrically connected with or disconnected from each other, wherein the second and fourth connector terminals are configured to be electrically connected with or disconnected from each other, wherein when the first and third connector terminals are electrically connected with each other, they are in contact with each other, and wherein when the second and fourth connector terminals are electrically connected with each other, they are in contact with each other.

US Pat. No. 10,559,803

BUS BAR HOLDING STRUCTURE

Yazaki Corporation, Mina...

1. A bus bar holding structure comprising:a bus bar; and
an insulating resin-made wire distribution body holding the bus bar,
wherein the bus bar electrically connects together adjacent terminals of a plurality of unit cells each having positive pole and negative pole electrode terminals,
wherein the bus bar includes a plate-shaped main body and a wire connecting part extended from the plate-shaped main body and connected to an end of a wire,
wherein the plate-shaped main body includes a fold-back part and a plurality of plate parts separated from each other at the fold-back part and folded back at the fold-back part so as to be superimposed with each other,
wherein the plate-shaped main body and the wire connecting part are formed integrally,
wherein the wire distribution body includes a locking part which locks lateral edges of the plate-shaped main body so as to hold in a bus bar storing part,
wherein the fold-back part includes a notch having a vertical side surface parallel to a peripheral wall of the bus bar storing part, and
wherein the locking part locks a peripheral edge of the notch.

US Pat. No. 10,559,802

SEPARATOR MEMBRANES FOR LITHIUM ION BATTERIES AND RELATED METHODS

Celgard, LLC, Charlotte,...

1. A ceramic coated separator for an energy storage device, such as a secondary lithium ion battery, comprising:a microporous polyolefin membrane having a first surface and a second surface, wherein said microporous membrane is at least one of a single layer, multiple layer, single ply, and/or multiple ply structure; and,
a ceramic coating on at least one surface of said microporous membrane, said ceramic coating comprising a layer of ceramic particles in a polymeric binder, said ceramic particles having an average particle size ranging from 0.01 ?m to 5 ?m in diameter, said polymeric binder includes poly (sodium acrylate-acrylamide-acrylonitrile) copolymer,
wherein said ceramic coated separator has a TMA TD shrinkage of about 0.5% or less at ?130° C. and at least one of the following physical characteristics: a TMA MD dimensional change of ?2% or more at ?110° C.; a MD shrinkage of 15% or less at 135° C. for one hour; a volatile component evolution of ?0.5% volatile components at ?250° C.; and a strain shrinkage of 0% at ?120° C.

US Pat. No. 10,559,801

NANOSTRUCTURED METAL ORGANIC MATERIAL ELECTRODE SEPARATORS AND METHODS THEREFOR

KING ABDULLAH UNIVERSITY ...

1. A nanostructured electrode separator, consisting essentially of:a covalent organic framework, wherein the nanostructured electrode separator is a phase-pure material.

US Pat. No. 10,559,800

ELECTRODE, SECONDARY BATTERY, BATTERY PACK, ELECTRIC VEHICLE, ELECTRIC POWER STORAGE SYSTEM, ELECTRIC POWER TOOL, AND ELECTRONIC APPARATUS

Murata Manufacturing Co.,...

1. A battery comprising:a cathode;
an anode;
an electrolytic solution;
an interlayer provided between the cathode and the anode;
wherein the interlayer includes at least one of a polymer compound, and one or more of a polyphosphate salt, a melamine salt, a metal hydroxide, and a metal hydrate,
the interlayer further includes a melamine derivative represented by Formula (1)

where R1 to R6 are each one of a hydrogen group (—H), a monovalent hydrocarbon group, a monovalent hydroxyl-group-containing hydrocarbon group, a monovalent group obtained by bonding one or more monovalent hydrocarbon groups and one or more oxygen bonds (—O—), a monovalent group obtained by bonding one or more monovalent hydroxyl-group-containing hydrocarbon groups and one or more oxygen bonds, and a monovalent group obtained by bonding two or more thereof.

US Pat. No. 10,559,799

CUTTING METHOD

MANZ ITALY S.R.L., Sasso...

1. A cutting method comprising:cutting with a laser arrangement at least one continuous sheet material of separator for electrodes;
performing at least two distinct cutting lines in which a first cutting line is intersected by a second cutting line at an intersection point;
providing an arrangement of a plurality of electrodes applied to said sheet material in a row one after the other in a longitudinal direction; and
leaving a space between one electrode and the other to enable the sheet material to be cut in the space between the electrodes,
wherein said first cutting line having at least an intermediate portion that extends in length with at least one component parallel to said longitudinal direction, and
wherein said intersection point being arranged in said intermediate portion, wherein said intermediate portion comprises a curve shaped in such a manner as to have, at at least one point, a tangent that is parallel to said longitudinal direction.

US Pat. No. 10,559,795

CHASSIS BRACE FOR PROTECTING TRACTION BATTERY

Ford Global Technologies,...

1. A vehicle comprising:a battery pack including siderails;
a front cradle including rearwardly extending arms connected to the siderails, a cross member longitudinally spaced from the battery pack, and a bushing assembly; and
a brace including a midportion connected to the cross member and ends connected to the arms such that the brace creates load paths between the cross member and the siderails to inhibit impact between the cross member and the battery pack, wherein the brace is attached to the cross member via the bushing assembly.

US Pat. No. 10,559,794

BATTERY SEALING ENCLOSURE

BYTON LIMITED, Hong Kong...

1. A battery enclosure comprising:a rigid frame forming a perimeter of the battery enclosure, the rigid frame having a T-shaped cross section including a web and a flange joined to an end of the web, the flange having a pair of flange sections that project away from the centerline of the web;
a bottom panel having an inner side and an outer side, the bottom panel being positioned within the perimeter formed by the rigid frame so that the outer side of the bottom panel rests on one of the pair of flange sections and so that a perimeter edge of the bottom panel is positioned in a corner formed by the web and the flange section on which the bottom panel rests;
a seal positioned in the corner formed by the inner side of the bottom panel and the web; and
a joiner to couple the bottom panel to the flange section on which the bottom panel rests.

US Pat. No. 10,559,793

BATTERY ARRAY RETENTION METHOD AND ASSEMBLY

Ford Global Technologies,...

1. A retention assembly, comprising: an enclosure; a first and a second rail; and a battery array having a first laterally outer region resting on the first rail and an opposing, second laterally outer region resting on the second rail, the battery array secured relative to the enclosure at a position spaced from the first and second laterally outer regions to clamp the first and second laterally outer regions against the first and second rails, wherein the first and the second rails are separate and distinct structures that are spaced a distance from one another, wherein the first and second rails are secured directly to a floor that is provided by a tray of the enclosure, wherein the tray is directly secured to a lid.

US Pat. No. 10,559,791

BATTERY MODULE

1. A battery module, comprising a plurality of round cells of identical dimensions, target charge capacity and voltage, which are grouped into a series of round cell stacks, which round cell stacks are arranged one behind the other in a row and which round cell stacks all consist of an identical plurality of round cells which lie in each round cell stack axis-parallel to the stack row direction, adjacent and on top of each other in identical position in the stack row direction, whereincontact plates interposed between adjacent round cell stacks are provided, as well as end-side contact plates at the ends of the round cell stack row disposed in the stack row direction, which connect the round cells of each round cell stack in an electrically parallel manner at their poles disposed in the stack row direction, and wherein
all the round cells are arranged in such a way that all identical electrical poles face in the same direction and form a plurality of aligned round cell rows corresponding to the plurality of round cells per round cell stack, the round cells of each round cell row are respectively electrically connected in series via the interposed contact plates, wherein
at least the contact plates interposed between adjacent round cell stacks comprise protrusions for contacting the poles of the round cells and are electrically conductive at the protrusions and in the flat sections between the protrusions, wherein the protrusions press on the poles, but are not integrally connected to the poles, and wherein,
at the two ends of the round cell stack row, a respective pole plate rests on the outside on the end-side contact plate there, which pole plates are thicker-walled as compared to the contact plates, and which form the ends of the round cell stack row forming the poles of the battery module, and wherein
the protrusions have either identical dimensions and are provided on the contact plates at the positions corresponding to the axes of the round cell rows, wherein the protrusions each contact a pole of a round cell or both mutually facing poles of two adjoining round cells of a round cell row, so that all round cell poles are contacted via one of the protrusions,
or
the contact plates, which contact the plus poles of a round cell stack, comprise respective protrusions of identical dimensions on their sides facing the plus poles on the axes of the round cell rows, which protrusions each contact a plus pole of one of the round cells, and the contact plates, which contact the minus poles of a round cell stack, respectively comprise a plurality of protrusions with identical dimension on their sides facing the minus poles around the positions corresponding to the axes of the round cell regions, which protrusions each contact one of the minus poles of one of the round cells.

US Pat. No. 10,559,790

LITHIUM ION SECONDARY BATTERY CONFIGURED TO MAKE BEST USE OF AN ACCOMMODATING SPACE IN AN ELECTRONIC APPARATUS

ROUTE JADE INC., Nonsan-...

1. A lithium ion secondary battery comprising:an electrode assembly in which a plurality of pocketing anode bodies and a plurality of cathode bodies are alternately stacked,
wherein a concavely recessed space is formed in the electrode assembly and a protrusion of an electronic apparatus is inserted into the space,
wherein one of the pocketing anode bodies includes:
an anode plate which has a coating layer of lithium or lithium metal complex oxide as an anode active material, has a plain protrusion, and has a first through hole formed therethrough;
a pair of separation films which covers both surfaces of the anode plate while exposing only the plain protrusion; and
a film unit which is located between the pair of separation films to be attached to the pair of separation films,
wherein the film unit includes:
a first insulating member which is located between the pair of separation films in an entire or partial outer circumference of the anode plate to be attached to the pair of separation films; and
a second insulating member which is located between the pair of separation films in an entire or partial inner circumference of the anode plate which forms the first through hole to be attached to the pair of separation films, and
wherein the film unit includes a connecting member which connects the first insulating member and the second insulating member to each other.

US Pat. No. 10,559,789

ADAPTER FOR CONNECTING A PLURALITY OF BATTERY PACKS TO A POWER TOOL

MAKITA CORPORATION, Anjo...

1. An adapter for connecting a plurality of first battery packs, each having a nominal voltage that is substantially equal to or greater than 18 volts but less than 36 volts, to a main body of an electric power tool having a rated voltage that is substantially equal to or greater than 36 volts, wherein the main body of the electric power tool comprises a second battery interface configured to removably attach a second battery pack and to electrically connect the second battery pack to an electric motor housed in the main body, the adapter comprising:a plurality of first battery interfaces configured to removably attach the plurality of first battery packs, the first battery interfaces having a different physical configuration than the second battery interface such that the second battery pack is not connectable to the first battery interface;
a connector configured to be removably attached to the second battery interface, wherein the plurality of first battery interfaces is configured to electrically connect the attached first battery packs in series to the connector; and
a plurality of visual indicators disposed on a surface of the adapter such that they have the same or substantially the same illumination direction, the visual indicators being configured to visually indicate at least a level of charge of each of the first battery packs respectively attached to the first battery interfaces.

US Pat. No. 10,559,787

ELECTROLYTE, BATTERY, BATTERY PACK, ELECTRONIC APPARATUS, ELECTRIC VEHICLE, POWER STORAGE APPARATUS, AND POWER SYSTEM

MURATA MANUFACTURING CO.,...

1. An electrolyte for a lithium-ion secondary battery, comprising:a non-aqueous solvent,
an electrolyte salt, and
at least one of compounds represented by a formula (2),
(in the formula (2), A2 represents a divalent saturated hydrocarbon group, a divalent unsaturated hydrocarbon group, a divalent halogenated saturated hydrocarbon group, or a divalent halogenated unsaturated hydrocarbon group, A2 has a number of carbon atoms from 3 to 5, a first ring being formed with A2, O (oxygen), and P (phosphorus) and R2 and R3 each independently represents a monovalent saturated hydrocarbon group, a monovalent unsaturated hydrocarbon group, a monovalent aromatic hydrocarbon group, a monovalent halogenated saturated hydrocarbon group, a monovalent halogenated unsaturated hydrocarbon group, or a monovalent halogenated aromatic hydrocarbon group).

US Pat. No. 10,559,785

SEALING APPARATUS FOR SECONDARY BATTERY

LG Chem, Ltd., Seoul (KR...

1. A sealing apparatus for a secondary battery, which seals a sealing part of a battery case at which an electrode lead coupled to an electrode assembly is disposed, the sealing apparatus comprising:a thermal fusion member applying heat and a pressure to the sealing part of the battery case, at which the electrode lead is disposed, to seal the sealing part; and
a temperature rising prevention member configured to contact a front end of the electrode lead to cool the sealing part through the electrode lead, thereby preventing the sealing part from increasing in temperature,
wherein the temperature rising prevention member includes a flat surface to contact the front end of the electrode lead.

US Pat. No. 10,559,784

INSULATING MOLDING FOR A BATTERY CELL

Robert Bosch GmbH, Stutt...

1. A battery apparatus including an insulating molding (1) and at least one battery cell, wherein the insulating molding is positioned around a housing of the at least one battery cell, wherein, on at least one molding sidewall (3a, 3b) of the insulating molding (1), a depression (5) is configured, which is constituted by means of a reduced wall thickness, in order to reduce the force acting on the battery cell, wherein the insulating molding (1) is in contact with the housing sidewalls of the battery cell, or wherein the insulating molding (1) is in contact with the housing sidewalls of the battery cell and on a housing base and/or a housing top cover of the battery cell.

US Pat. No. 10,559,783

DISPLAY DEVICE AND METHOD OF PRODUCING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising:a base substrate;
a cover plate opposite to the base substrate; and
a first frame sealant;
wherein the cover plate is bonded to the base substrate at least by the first frame sealant, at least one groove is provided in a bonding region of at least one of the base substrate and the cover plate, and at least a part of the first frame sealant is disposed in the groove,
wherein at least one thermosensitive laser circuit is disposed in the groove, the thermosensitive laser circuit configured to emit a laser for melting an inner wall of the groove when an ambient temperature exceeds a preset value.

US Pat. No. 10,559,781

DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME

Japan Display Inc., Toky...

1. A display device comprising:a display region arranged above a substrate;
a first light emitting element emitting light of a first color, a second light emitting element emitting light of a second color, and a third light emitting element emitting light of a third color arranged in the display region; and
a first optical path length adjustment film, a second optical path length adjustment film, and a third optical path length adjustment film in the display region,
wherein
the first optical path length adjustment film has a first region overlapping the first light emitting element, the second light emitting element and the third light emitting element;
the second optical path length adjustment film has a second region not overlapping the third light emitting element, and overlapping the first light emitting element and the second light emitting element; and
the third optical path length adjustment film has a third region not overlapping the second light emitting element, and overlapping the first light emitting element and the third light emitting element.

US Pat. No. 10,559,780

ELECTRONIC DEVICE INCLUDING MIDDLE LAYER LOCATED BETWEEN FIRST BASE AND SECOND BASE AND MANUFACTURING METHOD OF THE SAME

Japan Display Inc., Mina...

1. An electronic device, comprising:a first base formed of a resin material;
a second base formed of a resin material;
a middle layer including a metal layer located between the first base and the second base; and
a circuit unit and an electronic element unit located above the second base,whereinthe metal layer is formed of any one of titanium (Ti), palladium (Pd), zirconium (Zr), and aluminum (Al),
the middle layer comprises a first layer which is in contact with the first base, a second layer which is in contact with the second base, and a third layer which is in contact with the first layer and the second layer, and
a nitrogen content of each of the first layer and the second layer is higher than a nitrogen content of the third layer.

US Pat. No. 10,559,779

FLEXIBLE DISPLAY WITH STRESS-RELIEF LAYER IN TRENCH

SAMSUNG DISPLAY CO., LTD....

1. A flexible display, comprising:a flexible substrate including a bending area and a display area;
an insulating layer disposed on the flexible substrate;
at least one groove in the insulating layer within the bending area;
a stress relaxation layer disposed on the at least one groove; and
a plurality of wires disposed on the insulating layer and the stress relaxation layer,
wherein the bending area is bent with respect to a bending axis, and the at least one groove of the insulating layer extends along a direction parallel to the bending axis.

US Pat. No. 10,559,778

COMPOSITE GAS BARRIER LAMINATE AND METHOD FOR PRODUCING SAME

ZEON CORPORATION, Tokyo ...

1. A composite gas barrier layered body for an organic electroluminescent light-emitting element, consisting of:a gas barrier layered body (A) having a film (a) of an alicyclic polyolefin resin and one or more inorganic barrier layers (a) directly provided on at least one surface of the film (a);
a film (b) formed of an alicyclic polyolefin resin having a thickness that is equal to less than a thickness of the film (a); and
a heat-melting layer that is interposed between the inorganic barrier layer (a) and the film (b) to bond the inorganic barrier layer (a) to the film (b), wherein
a difference (TgB?TgA) between a glass transition temperature TgA of the heat-melting layer and a glass transition temperature TgB of the alicyclic polyolefin resin constituting the film (a) and the film (b) is 25° C. or higher,
a ratio of the thickness of the film (a) relative to the thickness of the film (b) is from 10:9 to 3:1,
a thickness of the heat-melting layer is 3 ?m or more and 50 ?m or less, and
the heat-melting layer is
a layer of a styrene-based thermoplastic elastomer resin,
a layer of an olefin-based thermoplastic elastomer resin,
a layer of a vinyl chloride-based thermoplastic elastomer resin,
a layer of a polyester-based thermoplastic elastomer resin, or
a layer of a urethane-based thermoplastic elastomer resin.

US Pat. No. 10,559,777

RADIATION CURABLE COMPOSITION FOR WATER SCAVENGING LAYER, AND METHOD OF MANUFACTURING THE SAME

1. A photocurable resin composition comprising:(A) 1-30% by weight of alkaline earth metal oxide particles selected from the group consisting of dehydrated CaO, dehydrated BaO and dehydrated MgO particles;
(B) 0.1-10% by weight of at least one photoinitiator, or any mixture thereof;
(C) 30-80% by weight of at least one acrylate or methacrylate component with a ClogP higher than 2, or any mixture thereof;
(D) 5-40% by weight of at least one monofunctional acrylate or methacrylate diluent component, or any mixture thereof;
(E) 5-30% by weight of at least one acrylate or methacrylate component with functionality equal or higher than 3, or any mixture thereof;
(F) 0.1-30% by weight of a polybutadiene acrylate or methacrylate, a silicone acrylate or methacrylate, or a two-mole ethoxylated bisphenol A di(meth)acrylate, or any mixture thereof;
based on the total weight of the composition;
wherein the photocurable resin exhibits a water content of less than 1000 ppm by weight;
wherein Mica is excluded from the group of (A) alkaline earth metal oxide particles; and
wherein the photocurable resin composition does not comprise any urethane (meth)acrylate, polyester (meth)acrylate, or polyethylene glycol (PEG) (meth)acrylate.

US Pat. No. 10,559,776

OLED DISPLAY DEVICE AND METHOD OF PACKAGING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. An OLED display device, comprising:a substrate;
a cover plate provided opposite to the substrate;
a light emitting region located on a surface of the substrate facing the cover plate, wherein the light emitting region has an OLED display structure;
a dam around the light emitting region; and
a packaging adhesive layer disposed on the light emitting region and configured to cover the OLED display structure,
wherein, the cover plate is provided with a groove at a position corresponding to the dam, an end of the dam away from the substrate being received in the groove,
the dam includes a first sub-dam and a second sub-dam stacked on the first sub-dam, wherein the first sub-dam is disposed close to the substrate, and the second sub-dam is received in the groove, and
the first sub-dam has a first surface, a portion of which is in contact with the second sub-dam and another portion of the first surface is in contact with the cover plate.

US Pat. No. 10,559,775

ORGANIC EL DISPLAY DEVICE

Japan Display Inc., Mina...

1. An organic EL display device comprising:a base material;
a plurality of pixels on the base material;
a lower electrode which each of the plurality of pixels is provided with;
an organic insulation layer which sections the plurality of pixels;
an organic material layer on the lower electrode and the organic insulation layer, the organic material layer including a plurality of layers; and
an upper electrode on the organic material layer, wherein
a level difference part is positioned on an upper surface of the organic insulation layer so as to form a recess part at the upper surface,
a first layer included in the organic material layer is divided at the level difference part, or has a thin part being thinner at the level difference part than at a position at which the first layer faces the lower electrode,
a second layer included in the organic material layer which is different from the first layer is not divided at the level difference part, and
a height of the level difference part is smaller than a thickness of the lower electrode.

US Pat. No. 10,559,774

LIGHTING APPARATUS USING ORGANIC LIGHT-EMITTING DIODE AND MANUFACTURING METHOD THEREOF

LG Display Co., Ltd., Se...

1. A lighting apparatus using an organic light-emitting diode, the lighting apparatus comprising:an auxiliary electrode disposed on a substrate;
a first electrode of a non-emission region formed of a transparent conductive film and covering the auxiliary electrode, and a first electrode of an emission region disposed on each of side surfaces of the first electrode of the non-emission region;
a first passivation layer disposed on an upper portion of the first electrode of the non-emission region;
an organic light-emitting layer and a second electrode, disposed in a lighting part of the substrate on which the first passivation layer is disposed; and
a metal film disposed in the lighting part of the substrate,
wherein the first electrode of the non-emission region has a resistance value higher than that of indium tin oxide (ITO), and the first electrode of the emission region has a resistance value lower than that of the first electrode of the non-emission region.

US Pat. No. 10,559,773

LIGHTING APPARATUS USING ORGANIC LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF

LG Display Co., Ltd., Se...

1. A lighting apparatus, comprising:a first substrate where a plurality of pixels is formed;
an auxiliary electrode disposed on the first substrate;
at least one conductive pattern disposed at each of the plurality of pixels; and
an organic light emitting diode disposed at each of the plurality of pixels and including a first electrode, an organic light emitting layer and a second electrode;
wherein the first electrode is electrically connected with the auxiliary electrode and the least one conductive pattern, and
wherein the first electrode is formed of a transparent conductive material having an electrical resistance of at least half of the organic light emitting layer.

US Pat. No. 10,559,772

DISPLAY DEVICE AND PRODUCTION METHOD THEREOF

SHARP KABUSHIKI KAISHA, ...

1. A display device comprising:a plurality of optical elements;
a sealing film sealing the plurality of optical elements and including a first inorganic layer, a second inorganic layer, and an organic layer provided between the first inorganic layer and the second inorganic layer; and
at least one organic layer stopper formed from a frame-shaped bank surrounding a display region on which the plurality of optical elements are provided, and defining edges of the organic layer,
wherein the at least one organic layer stopper includes an organic layer stopper including a first frame portion surrounding the display region in a plan view and including a plurality of corner portions, and a second frame portion contiguous to the first frame portion, surrounding each of the plurality of corner portions of the first frame portion, and protruding from the first frame portion at the plurality of corner portions of the first frame portion with a space between the second frame portion and each of the plurality of corner portions of the first frame portion.

US Pat. No. 10,559,770

PHOTOELECTRIC CONVERSION ELEMENT, IMAGING DEVICE, OPTICAL SENSOR AND METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION ELEMENT

Sony Corporation, Tokyo ...

1. A photoelectric conversion element, comprising:a first electrode formed of a first transparent material;
a second electrode formed of a second transparent material;
an organic photoelectric conversion layer disposed between the first electrode and the second electrode, the organic photoelectric conversion layer including one or more organic semiconductor materials; and
a buffer layer disposed between the first electrode and the organic photoelectric conversion layer, the buffer layer including an amorphous inorganic material and having an energy level of 7.7 to 8.0 eV, wherein a difference in a highest occupied molecular orbital (HOMO) energy level from the organic photoelectric conversion layer and the buffer layer is 2 eV or more, and
wherein the buffer layer is formed with a third transparent material having a refractive index with respect to at least the first electrode or the second electrode of 0.3 or less.

US Pat. No. 10,559,768

ADHESIVE AND FLEXIBLE DISPLAY USING THE SAME

LG DISPLAY CO., LTD., Se...

1. An adhesive interposed between a first adherend and a second adherend facing each other, the adhesive comprising:a strain layer comprising a plurality of spaced-apart divided strain layers, each spaced-apart divided strain layer having a polygonal top surface along a folding axis; and
a first adhesive layer having a first surface contacting the top surface of the strain layer and a second surface contacting the first adherend,
wherein each of the spaced-apart divided strain layers has the top surface, a bottom facing the second adherend, and a height between the top surface and the bottom surface,
wherein the top surface and the bottom surface have a first side along the folding axis and a second side crossing the first side, and the height is longer than the second side, and
wherein a distance between second sides of two adjacent spaced-apart divided strain layers is larger than or equal to a length of the second side.

US Pat. No. 10,559,765

ORGANIC LIGHT-EMITTING DEVICE

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting device comprising:a first electrode;
a second electrode facing the first electrode; and
an emission layer disposed between the first electrode and the second electrode; and
an electron transport region between the second electrode and the emission layer,
wherein the electron transport region comprises an electron injection layer comprising a first component comprising at least one halide of an alkali metal (Group I), a second component comprising at least one organometallic compound, and a third component comprising at least one lanthanide metal,
wherein the electron injection layer comprises a first layer and a second layer,
wherein the first layer is a film comprising the second component dispersed within a matrix comprising the first component, and the second layer is a film comprising the third component dispersed within a matrix comprising the first component; or
the first layer is a film comprising the second component dispersed within a matrix comprising the first component, and the second layer is a film comprising the third component dispersed within a matrix comprising the second component; or
the first layer is a film comprising the third component dispersed within a matrix comprising the first component, and the second layer is a film comprising the second component dispersed within a matrix comprising the first component; or
the first layer is a film comprising the third component dispersed within a matrix comprising the first component, and the second layer is a film comprising the third component dispersed within a matrix comprising the second component; or
the first layer is a film comprising the third component dispersed within a matrix comprising the second component, and the second layer is a film comprising the second component dispersed within a matrix comprising the first component; or
the first layer is a film comprising the third component dispersed within a matrix comprising the second component, and the second layer is a film comprising the third component dispersed within a matrix comprising the first component.

US Pat. No. 10,559,764

FUSED POLYCYCLIC HETEROAROMATIC COMPOUND, ORGANIC THIN FILM INCLUDING COMPOUND AND ELECTRONIC DEVICE INCLUDING ORGANIC THIN FILM

Samsung Electronics Co., ...

1. A fused polycyclic heteroaromatic compound represented by Chemical Formula 1A
wherein, in Chemical Formula 1A,
each of X1 to X4 are independently O, S, Se, Te, N—Ra, or —NC(?O)ORf,
wherein each Ra is independently hydrogen, a substituted or unsubstituted linear or branched C1 to C30 alkyl group, a substituted or unsubstituted C2 to C30 alkenyl group, a substituted or unsubstituted C2 to C30 alkynyl group, a substituted or unsubstituted C7 to C30 arylalkyl group, a substituted or unsubstituted C6 to C30 aryl group, or a substituted or unsubstituted C1 to C30 alkoxy group, and
wherein Rf is a substituted or unsubstituted C1 to C30 alkyl group,
each of R1 to R12 are independently hydrogen, a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C1 to C30 alkoxy group, a substituted or unsubstituted C2 to C30 alkenyl group, a substituted or unsubstituted C2 to C30 alkynyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C2 to C30 heteroaryl group, a substituted or unsubstituted C7 to C30 arylalkyl group, a substituted or unsubstituted C2 to C30 heteroarylalkyl group, a substituted or unsubstituted C2 to C30 alkylheteroaryl group, a substituted or unsubstituted C5 to C30 cycloalkyl group, or a substituted or unsubstituted C2 to C30 heterocycloalkyl group,
each of n1 and n2 are independently 1, 2, or 3.

US Pat. No. 10,559,763

PHOTOELECTRIC CONVERSION ELEMENT, IMAGING DEVICE, OPTICAL SENSOR, AND METHOD OF USING PHOTOELECTRIC CONVERSION ELEMENT

FUJIFILM Corporation, To...

1. A compound represented by General formula (17),
in General formula (17), each of R45 and R46 independently represents an aryl group which may have a substituent or a heteroaryl group which may have a substituent, and at least one of R45 and R46 is a group represented by General formula (14),

in General formula (14), each of R30 and R31 independently represents an alkyl group, an aryl group which may have a substituent, or a heteroaryl group which may have a substituent; R32 represents an arylene group which may have a substituent or a heteroarylene group which may have a substituent; R30 and R31, R30 and R32, or R31 and R32 form a ring by being directly bonded to each other or by being bonded to each other through a linking group; and *5 represents a bonding position,
wherein each of R30, R31 and R32 are directly bonded to the N.

US Pat. No. 10,559,762

ORGANIC COMPOUND, LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:a pair of electrodes; and
an organic compound represented by General Formula (G):

wherein either of A1 and A2 is represented by General Formula (G-1) and the other is hydrogen or another substituent,
wherein the another substituent represents an alkyl group having 1 to 6 carbon atoms, a cycloalkyl group having 3 to 6 carbon atoms, an alkylphenyl group, or a phenyl group,
wherein ?1 and ?2 each independently represent a substituted or unsubstituted phenylene group,
wherein n and in each independently represent 1 or 2, and
wherein P1 and P2 each independently represent hydrogen, a substituted or unsubstituted phenylene group, or a substituted or unsubstituted biphenylene group.

US Pat. No. 10,559,759

ORGANIC ELECTROLUMINESCENT DEVICE

HODOGAYA CHEMICAL CO., LT...

1. An organic electroluminescence device having an anode, a first hole transport layer, a second hole transport layer, a luminous layer, an electron transport layer, and a cathode in the order of description, wherein the second hole transport layer includes an arylamine derivative represented by any of the following formulas (1a-a), (1a-b), (1b-a), (1c-a), (1c-b), or (1c-c):
wherein Ar1 to Ar4 are phenyl groups that may have a substituent, biphenyl groups that may have a substituent, terphenyl groups that may have a substituent, triphenylenyl groups that may have a substituent, or fluorenyl groups that may have a substituent, said substituent being an alkyl group, a naphthyl group, or an indolyl group,
and the electron transport layer includes a pyrimidine compound represented by formula (2a)

wherein Ar5 is a phenyl group or a phenyl group substituted with a naphthyl group, Ar6 is a naphthyl group or a phenyl group substituted with a phenanthrenyl group, Ar7 is a hydrogen atom, and A is a phenyl group substituted with a pyridyl group.

US Pat. No. 10,559,756

MATERIALS FOR ELECTRONIC DEVICES

Merck Patent GmbH, Darms...

1. A compound of formula (I):
wherein
the groups Ar1 are naphthyl groups, which are optionally substituted by one or more radicals R1, and the groups Ar2 are phenyl groups, which are optionally substituted by one or more radicals R2; or
one of the two groups Ar1 is a phenyl group, which is optionally substituted by one or more radicals R1, and the other of the two groups Ar1 is a naphthyl group, which is optionally substituted by one or more radicals R1, and the groups Ar1 are phenyl groups, which are optionally substituted by one or more radicals R2
X1 is on each occurrence, identically or differently, BR3, C(R3)2, —C(R3)2—C(R3)2—, —C(R3)2—O—, —C(R3)2—S—, —R3C?CR3—, —R3C?N—, Si(R3)2, —Si(R3)2—Si(R3)2—, C?O, O, S, S?O, SO2, NR3, PR3, or P(?O)R3;
R1, R2, and R3
are on each occurrence, identically or differently, H, D, F, Cl, Br, I, C(?O)R4, CN, Si(R4)3, N(R4)2, P(?O)(R4)2, OR4, S(?O)R4, S(??O)2R4, a straight-chain alkyl or alkoxy group having 1 to 20 C atoms, a branched or cyclic alkyl or alkoxy group having 3 to 20 C atoms, or an alkenyl or alkynyl group having 2 to 20 C atoms, wherein the above-mentioned groups are optionally substituted by one or more radicals R4 and wherein one or more CH2 groups in the above-mentioned groups are optionally replaced by —R4C?CR4—, —C?C—, Si(R4)2, C?O, C?NR4, —C(?O)O—, —C(?O)NR4—, NR4, P(?O)(R4), —O—, —S—, SO, or SO2, or an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, which is optionally substituted by one or more radicals R4, and wherein two or more radicals R3 are optionally linked to one another so as to define a ring;
R4 is on each occurrence, identically or differently, H, D, F, Cl, Br, I, C(?O)R5, CN, Si(R5)3, N(R5)2, P(?O)(R5)2, OR5, S(?O)R5, S(?O)2R5, a straight-chain alkyl or alkoxy group having 1 to 20 C atoms, a branched or cyclic alkyl or alkoxy group having 3 to 20 C atoms, or an alkenyl or alkynyl group having 2 to 20 C atoms, wherein the above-mentioned groups are optionally substituted by one or more radicals R5 and wherein one or more CH2 groups in the above-mentioned groups are optionally replaced by —R5C?CR5—, —C?C—, Si(R5)2, C?O,
C?NR5, —C(?O)O—, —C(?O)NR5—, NR5, P(?O)(R5), —O—, —S—, SO, or SO2, or an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, which is optionally substituted by one or more radicals R5, and wherein two or more radicals R4 are optionally linked to one another so as to define a ring;
R5 is on each occurrence, identically or differently, H, D, F, or an aliphatic, aromatic, or heteroaromatic organic radical having 1 to 20 C atoms, wherein one or more H atoms are optionally replaced by D or F, and wherein two or more substituents R5 are optionally linked to one another so as to define a ring.

US Pat. No. 10,559,755

HETEROGENEOUS NANOSTRUCTURES FOR HIERARCHAL ASSEMBLY

INTERNATIONAL BUSINESS MA...

1. A carbon nanotube nanostructure, comprising:a first carbon nanotube structure, comprising:
a carbon nanotube having a first end and a second end;
a first body metal pad arranged on the first end, the first body metal pad having face metal layers arranged on two opposing surfaces of the first body metal pad; and
a second body metal pad arranged on the second end, the second body metal pad having face metal layers arranged on two opposing surfaces of the second body metal pad; and
a second carbon nanotube structure, comprising:
a carbon nanotube having a first end and a second end;
a first body metal pad arranged on the first end, the first body metal pad having face metal layers arranged on two opposing surfaces of the first body metal pad; and
a second body metal pad arranged on the second end, the second body metal pad having face metal layers arranged on two opposing surfaces of the second body metal pad;
wherein a sidewall of the first body metal pad of the first carbon nanotube structure is functionalized with a chemical compound that bonds to the second carbon nanotube structure, and the first carbon nanotube structure and the second nanotube structure are arranged end-to-end.

US Pat. No. 10,559,754

ORGANIC SEMICONDUCTOR SOLUTION BLENDS FOR SWITCHING AMBIPOLAR TRANSPORT TO N-TYPE TRANSPORT

THE REGENTS OF THE UNIVER...

1. A composition of matter, comprising:donor-acceptor copolymers each comprising a main chain section, the main chain section having a repeat unit that comprises a donor and an acceptor; and
hole trapping compounds combined with the donor-acceptor copolymers so as to switch ambipolar transport of the donor-acceptor copolymers to unipolar n-type transport.

US Pat. No. 10,559,753

DOPING ORGANIC SEMICONDUCTORS

Cambridge Display Technol...

1. A method for reducing a parasitic resistance at an interface between a conducting electrode region and an organic semiconductor in a thin film transistor, the method comprising:depositing an insulating layer onto said organic semiconductor;
providing a solution comprising a dopant for doping said semiconductor; and
depositing said solution onto said organic semiconductor and/or said conducting electrode region to selectively dope said organic semiconductor adjacent said interface between said conducting electrode region and said organic semiconductor, wherein the conducting electrode region extends beyond an outer surface of the organic semiconductor during said depositing,
wherein depositing said solution comprises inkjet-printing said solution, and
wherein the selectively doped portions of said organic semiconductor and/or said conducting electrode region are arranged between said conducting electrode region and the insulating layer.

US Pat. No. 10,559,752

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first word line extending in a first direction;
a first bit line extending in a second direction that intersects the first direction, wherein the first bit line and the first word line are spaced apart from each other in a third direction that intersects the first and second directions;
a mold film disposed between the first word line and the first bit line;
a first memory cell disposed in the mold film and including a core hole, wherein the first memory cell comprises:
a first lower electrode in contact with the first word line, wherein side surfaces of the first lower electrode are in direct contact with the mold film,
a first phase-charge memory in contact with the first lower electrode,
a first intermediate electrode in contact with the first phase-change memory,
a first ovonic threshold switch (OTS) in contact with the first intermediate electrode, and
a first upper electrode disposed between the first OTS and the first bit line, the first upper electrode in contact with the first OTS and the first bit line,
wherein the core hole extends in the first direction through the first lower electrode, the first phase-change memory, the first intermediate electrode, the first OTS and the first upper electrode;
a second bit line extending in the second direction, wherein the second bit line and the first bit line are spaced apart from each other in the first direction; and
a second memory cell disposed between the second bit line and the first word line,
wherein the second memory cell comprises:
a second lower electrode disposed on the first word line, wherein side surfaces of the second lower electrode are in direct contact with the mold film,
a second phase-change memory disposed on the second lower electrode,
a second intermediate electrode disposed on the second phase-change memory,
a second OTS disposed on the second intermediate electrode, and
a second upper electrode disposed between the second OTS and the second bit line, the second upper electrode being in contact with the second OTS and the second bit line.

US Pat. No. 10,559,751

BOTTOM ELECTRODE FOR SEMICONDUCTOR MEMORY DEVICE

International Business Ma...

1. A method for fabricating a structure for an integrated circuit device comprising:providing a conductive microstud on a substrate, the microstud being formed in a recess of an insulator layer formed on the substrate;
forming a bottom pedestal on a top surface of the microstud, wherein a material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud;
forming a top pedestal on a top surface of the bottom pedestal;
planarizing the top surface of at least one of the bottom pedestal and top pedestal;
forming a conductive layer on a top surface of the top pedestal; and
forming a conical structure, wherein the conical structure is comprised of at least the conductive layer and a top portion of the top pedestal, wherein a lower portion of the bottom pedestal is formed in the top portion of the recess and a top portion of the bottom pedestal is part of the conical structure.

US Pat. No. 10,559,750

NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A nonvolatile memory device comprising:a first conductive portion;
an insulating film surrounding a side surface of the first conductive portion;
an intermediate layer provided on the first conductive portion and the insulating film;
a first film including a first portion provided on the intermediate layer and at least one second portion provided in the intermediate layer and outside an upper edge of the first conductive portion, the first film including, above the first conductive portion, a resistance change portion that has a first resistance state and a second resistance state having resistance higher than resistance in the first resistance state; and
a second conductive portion provided at least on the resistance change portion,
wherein the resistance change portion is located at a position corresponding to a position where crystal grain boundaries of three crystal grains contained in the first film are gathered.

US Pat. No. 10,559,748

TUNNEL MAGNETIC RESISTANCE ELEMENT AND METHOD FOR MANUFACTURING SAME

TOHOKU UNIVERSITY, Miyag...

1. A tunnel magnetic resistance element comprising:a fixed magnetic layer in which a direction of magnetization is fixed;
a free magnetic layer which receives influence of a magnetic field from outside and in which the direction of magnetization changes; and
an insulating layer which is positioned between the fixed magnetic layer and the free magnetic layer,
wherein,
the fixed magnetic layer, the free magnetic layer, and the insulating layer form a magnetic tunnel junction,
a resistance of the insulating layer changes by a tunnel effect according to a difference in an angle between the direction of magnetization of the fixed magnetic layer and the direction of magnetization of the free magnetic layer,
the free magnetic layer includes a ferromagnetic layer joined to the insulating layer, a soft magnetic layer including NiFe, and a magnetic bonding layer placed in between, and
material of the magnetic bonding layer includes Ru or Ta, and a layer thickness is 1.0 nm to 1.3 nm.

US Pat. No. 10,559,747

TOPOLOGICAL INSULATOR-BASED HIGH EFFICIENCY SWITCHING OF MAGNETIC UNIT, METHOD AND APPLICATIONS

THE JOHNS HOPKINS UNIVERS...

1. A magneto-electronic device, comprising:a spin-orbit torque (SOT) generator layer;
a magnetic memory layer on the SOT generator layer; and
sensing electrodes configured to measure an anomalous Hall effect of the magnetic memory layer;
wherein the SOT generator layer comprises topological insulator material, and
wherein the magnetic memory layer comprises ferromagnetic material with perpendicular magnetic anisotropy.

US Pat. No. 10,559,746

MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A method of manufacturing an MRAM device, the method comprising:forming a first electrode on an upper surface of a substrate;
forming a first magnetic layer on the first electrode;
forming a tunnel barrier structure on the first magnetic layer, the tunnel barrier structure comprising a first tunnel barrier layer and a second tunnel barrier layer that are sequentially stacked on the first magnetic layer and have different resistivity distributions from each other along a horizontal direction that is parallel to the upper surface of the substrate;
forming a second magnetic layer on the tunnel barrier structure; and
forming a second electrode on the second magnetic layer.

US Pat. No. 10,559,745

MAGNETIC TUNNEL JUNCTION (MTJ) STRUCTURE WITH PERPENDICULAR MAGNETIC ANISOTROPY (PMA) HAVING AN OXIDE-BASED PMA-INDUCING LAYER AND MAGNETIC ELEMENT INCLUDING THE SAME

Industry-University Coope...

9. A magnetic tunnel junction (MTJ) structure with perpendicular magnetic anisotropy (PMA), the MTJ structure comprising:a substrate;
a first ferromagnetic layer disposed on the substrate and having PMA;
a tunneling barrier layer disposed on the first ferromagnetic layer;
a second ferromagnetic layer disposed on the tunneling barrier layer and having PMA;
a perpendicular antiferromagnetic layer disposed on the second ferromagnetic layer and including an antiferromagnetic material; and
a perpendicular magnetic anisotropic inducing layer disposed on the perpendicular antiferromagnetic layer and including an oxide-based material,
wherein the perpendicular antiferromagnetic layer generates perpendicular coupling at an interface with the perpendicular magnetic anisotropic inducing layer such that perpendicular coupling is further generated between the perpendicular antiferromagnetic layer and the second ferromagnetic layer.

US Pat. No. 10,559,744

TEXTURE BREAKING LAYER TO DECOUPLE BOTTOM ELECTRODE FROM PMTJ DEVICE

Intel Corporation, Santa...

1. A magnetic tunneling junction (MTJ) device, comprising:a free magnetic layer;
a fixed magnetic layer;
a tunneling layer disposed between the free magnetic layer and the fixed magnetic layer; and
a buffer layer disposed on a side of the fixed magnetic layer opposite the tunneling layer, wherein the buffer layer comprises an oxidized aluminum layer.

US Pat. No. 10,559,743

BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:providing a radio frequency (RF) filter at a backside of a substrate; and
forming at least one substrate conductor through the substrate, wherein the at least one substrate conductor electrically couples the RF filter to at least one device at a front side of the substrate,
wherein the providing the RF filter comprises forming a bulk acoustic wave (BAW) filter on the backside of the substrate, and
the at least one substrate conductor comprises a first through-silicon-via connected to a first electrode of the BAW filter and a second through-silicon-via connected to a second electrode of the BAW filter.

US Pat. No. 10,559,741

METHOD OF PROVIDING PROTECTIVE CAVITY AND INTEGRATED PASSIVE COMPONENTS IN WAFER LEVEL CHIP SCALE PACKAGE USING A CARRIER WAFER

SKYWORKS SOLUTIONS, INC.,...

1. A method of forming a wafer-level chip-scale package, the wafer-level chip-scale package including a device disposed on a piezoelectric substrate, the method comprising:forming a body of the package on a surface of a sacrificial semiconductor wafer;
forming conductive vias passing through the body;
forming contact bumps in electrical connection with lower ends of the conductive vias at lower portions of the body;
forming a metal seal ring within the body;
removing the sacrificial semiconductor wafer from the body;
forming a cavity within the body; and
bonding a lower surface of the piezoelectric substrate directly to upper ends of the conductive vias and to the seal ring to position the device within the cavity with the piezoelectric substrate defining an upper wall of the cavity.

US Pat. No. 10,559,740

DRIVING DEVICE, PIEZOELECTRIC MOTOR, ELECTRONIC COMPONENT CONVEYANCE APPARATUS, AND ROBOT

Seiko Epson Corporation, ...

1. A driving device comprising a plurality of motive power generators that receive electric power supply and generate motive power,the plurality of motive power generators forming a plurality of sets of motive power generators in which two or more of the motive power generators are electrically parallel-connected, and
the plurality of sets of motive power generators electrically series-connected.

US Pat. No. 10,559,739

THERMOELECTRIC MODULE FOR A THERMOELECTRIC GENERATOR

Valeo Systemes Thermiques...

1. A thermoelectric module comprising:a central thermoelectric assembly of cylindrical tubular shape inside which a first cold fluid flows and outside which a hot fluid flows; and
at least one peripheral thermoelectric assembly comprising:
an outer face in contact with a second cold fluid, and
an inner face positioned on a peripheral boundary surrounding the central thermoelectric assembly, said boundary defining a channel between said central and peripheral thermoelectric assemblies where the hot fluid flows.

US Pat. No. 10,559,738

PIN COUPLING BASED THERMOELECTRIC DEVICE

1. A thermoelectric device comprising:a flexible first substrate;
a plurality of sets of N and P thermoelectric legs coupled to the first substrate, each set comprising an N thermoelectric leg and a P thermoelectric leg electrically contacting each other through a conductive material on the first substrate;
a rigid second substrate;
a conductive thin film formed on the second substrate; and
a plurality of pins corresponding to the plurality of sets of N and P thermoelectric legs, each pin coupling the each set on an end thereof away from the first substrate to the conductive thin film formed on the second substrate, and the each pin being several times longer than a height of the N thermoelectric leg and the P thermoelectric leg of the each set,
wherein a temperature difference across the N thermoelectric leg and the P thermoelectric leg of the each set on the first substrate is controlled based on at least one of: varying a height of the each pin, varying a thickness of the each pin and replacing the each pin with another pin having a different area therefrom.

US Pat. No. 10,559,737

METHOD FOR PRODUCING THERMOELECTRIC CONVERSION APPARATUS AND THERMOELECTRIC CONVERSION APPARATUS

FUJITSU LIMITED, Kawasak...

1. A thermoelectric conversion apparatus comprising:a thermoelectric conversion element;
p-type thermoelectric conversion elements each provided at respective first sides of the thermoelectric conversion element in a first direction;
two protective films each disposed at respective second sides of the thermoelectric conversion element and the p-type thermoelectric conversion elements in a second direction perpendicular to the first direction; and
two heat sinks each disposed adjacent to each of the two protective films in the second direction,
wherein the thermoelectric conversion element includes:
a first film including a perovskite structure;
a second film and a third film, including a perovskite structure, disposed in such a manner that the first film is interposed between the second film and the third film and the second film and the third film are in contact with the first film;
a fourth film, including a perovskite structure, disposed adjacent to the second film and in a side opposite to the first film and being contact with the second film; and
a fifth film, including a perovskite structure, disposed adjacent to the third film and in a side opposite to the first film and being contact with the third film,
wherein each of an offset in conduction band at an interface between the first film and the second film and an offset in conduction band at an interface between the first film and the third film is less than 0.25 eV, and each of an offset in conduction band at an interface between the second film and the fourth film and an offset in conduction band at an interface between the third film and the fifth film is more than 1 eV,
wherein a first conductive film is disposed in one of the two protective films in such a manner that the first conductive film couples the first film and one of the p-type thermoelectric conversion elements and a second conductive film is disposed in the other of the two protective films in such a manner that the second conductive film couples the first film and another of the p-type thermoelectric conversion elements.

US Pat. No. 10,559,736

THERMOELECTRIC GENERATOR

KELK Ltd., Kanagawa (JP)...

1. A thermoelectric generator comprising:a heat-receiving plate configured to receive heat;
a cooling plate configured to be kept at a lower temperature than a temperature of the heat-receiving plate; and
a thermoelectric generation module interposed between the heat-receiving plate and the cooling plate, wherein
the thermoelectric generation module comprises: an opposed surface that is opposite the cooling plate; a plurality of heat-receiving electrodes and a plurality of cooling electrodes that are provided between the heat-receiving plate and the cooling plate, the plurality of heat-receiving electrodes being provided opposite the plurality of cooling electrodes; a plurality of thermoelectric elements that are electrically connected to each other through the heat-receiving electrodes and the cooling electrodes; a terminal configured to electrically conduct to the thermoelectric elements; a lead member bonded to the terminal; and a first thin sheet that covers an entire side of the plurality of thermoelectric elements opposite the cooling plate and that forms the opposed surface,
the terminal is provided at a surface of the first thin sheet opposite the thermoelectric elements,
the terminal is directly bonded to (i) a plurality of support members that support the terminal and (ii) one of the plurality of thermoelectric elements that is directly bonded to one of the heat-receiving electrodes or one of the cooling electrodes, the plurality of support members surrounding a bonding portion of the terminal bonded to the lead member,
the lead member penetrates the first thin sheet to extend to the cooling plate and is soldered to the terminal,
the thermoelectric generation module further comprises:
a second thin sheet covering an entire side of the plurality of thermoelectric elements opposite the heat-receiving plate, and
a support terminal provided on a surface of the second thin sheet facing the terminal,
each of the plurality of support members is bonded between the terminal and the support terminal, and
none of the plurality of thermoelectric elements directly contacts the support terminal.

US Pat. No. 10,559,735

LIGHT EMITTING DEVICE HAVING A PAIR OF VIAS PASSING THROUGH A CENTER OF THE CONCAVE COMPONENT

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate having a first main surface, a second main surface that is opposite from the first main surface, and a mounting surface that is adjacent to at least the second main surface, the substrate including
an insulating base material defining a concave component opening on the second main surface and the mounting surface,
a pair of connection terminals disposed on the first main surface,
a pair of external connection sections disposed on the second main surface, and
a pair of vias arranged at positions that interpose therebetween a line passing through a center of the concave component when viewed along a direction normal to the second main surface;
a light emitting element having a pair of electrodes which connect to element connection sections of the pair of connection terminals; and
a light transmissive member disposed on an upper surface of the light emitting element.

US Pat. No. 10,559,734

LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT INCLUDING THE SAME

LG Innotek Co., Ltd., Se...

1. A light emitting device package comprising:a body;
a plurality of lead frames including a first lead frame and a second lead frame embedded in the body;
a first light emitting device disposed on the first lead frame;
a second light emitting device disposed on the second lead frame;
a first wire having a first end connected to the first lead frame and a second end connected to the first light emitting device; and
a second wire having a first end connected to the second lead frame and a second end connected to the second light emitting device,
wherein the body includes:
a bottom portion;
a first sidewall and a second sidewall disposed on the bottom portion and extending in a first direction;
a third sidewall and a fourth sidewall disposed on the bottom portion and extending from the first sidewall toward the second sidewall, and
wherein the bottom portion is disposed on a bottom of the body between the first sidewall, the second sidewall, the third sidewall and the fourth sidewall,
wherein a length between an outer side of the first sidewall and an outer side of the second sidewall in a second direction orthogonal to the first direction is longer than a length between an outer side of the third sidewall and an outer side of the fourth sidewall in the first direction,
wherein the first lead frame includes:
a first upper surface on which the first light emitting device is disposed and exposed on the bottom portion; and
a second upper surface extending from the first upper surface toward the first sidewall, exposed on the bottom portion and on which the first end of the first wire is disposed,
wherein the second lead frame includes:
a third upper surface on which the second light emitting device is disposed and exposed on the bottom portion; and
a fourth upper surface extending from the third upper surface toward the second sidewall, exposed on the bottom portion and on which the first end of the second wire is disposed,
wherein the first light emitting device is disposed closer to a center line passing from a center of the outer side of the third sidewall to a center of the outer side of the fourth sidewall than the outer side of the first sidewall,
wherein the second light emitting device is disposed closer to the center line than the outer side of the second sidewall,
wherein the center line extends from the center of the outer side of the third sidewall toward the center of the outer side of the fourth sidewall in the first direction,
wherein a length of the first upper surface in the first direction is longer than a length of the second upper surface in the first direction,
wherein a length of the third upper surface in the first direction is longer than a length of the fourth upper surface in the first direction,
wherein a length of the first upper surface in the second direction is longer than a length of the second upper surface in the second direction,
wherein a length of the third upper surface in the second direction is longer than a length of the fourth upper surface in the second direction, and
wherein a region of the body in the first direction corresponding to the center line is exposed to the bottom portion of the body and on which the plurality of lead frames are not exposed.

US Pat. No. 10,559,731

HIGHLY RELIABLE AND REFLECTIVE LED SUBSTRATE

BRIDGELUX INC., Fremont,...

1. A reflective base for a light-emitting diode (LED) comprising:a substrate;
at least one reflective layer disposed above the substrate; and
a first diffusion barrier layer disposed on a first side of the at least one reflective layer that is closest to the substrate;
a planarized layer between the first diffusion barrier layer and the substrate, and
a second diffusion barrier layer disposed on a second side of the at least one reflective layer opposite the first side;
wherein the first diffusion barrier layer is between the at least one reflective layer and the planarized layer and is configured to reduce migration of reflective material from the at least one reflective layer toward the planarized layer and the substrate, and the second diffusion barrier is above the at least one reflective layer and below a first and second stacked dielectric layers.

US Pat. No. 10,559,728

SEMICONDUCTOR PACKAGE STRUCTURE

Everlight Electronics Co....

1. A semiconductor package structure, comprising:a first substrate, comprising a base portion, a first protrusion and a second protrusion, the base portion comprising a first front surface, a first side surface and a second side surface, the first protrusion and the second protrusion respectively extending from the first side surface and the second side surface, the first protrusion and the second protrusion respectively comprising a first connection surface and a second connection surface, and the first connection surface and the second connection surface respectively connecting to the first side surface and the second side surface;
a second substrate, comprising a second front surface, the first substrate being disposed on a portion of the second front surface, wherein the second substrate further comprises a rear surface and a conductive pattern layer, the rear surface is opposite to the second front surface, and the conductive pattern layer is disposed on the rear surface and the second front surface; and
a semiconductor chip, being disposed on the first front surface of the base portion.

US Pat. No. 10,559,725

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a light emitting element having a peak emission wavelength in a range of 410 nm to 440 nm; and
a phosphor member, the phosphor member containing a phosphor comprising:
a first phosphor having a peak emission wavelength in a range of 430 nm to 500 nm and containing an alkaline-earth phosphate, which includes Cl and is activated with Eu;
a second phosphor having a peak emission wavelength in a range of 440 nm to 550 nm and containing at least one of an alkaline-earth aluminate, which is activated with Eu, and a silicate, which includes Ca, Mg, and Cl and is activated with Eu;
a third phosphor having a peak emission wavelength in a range of 500 nm to 600 nm and containing a rare-earth aluminate, which is activated with Ce;
a fourth phosphor having a peak emission wavelength in a range of 610 nm to 650 nm and containing a silicon nitride, which includes Al and at least one of Sr and Ca and is activated with Eu; and
a fifth phosphor having a peak emission wavelength in a range of 650 nm to 670 nm and containing a fluorogermanate, which is activated with Mn, wherein a percentage content of the first phosphor to a total content of the phosphor is in a range of 20 mass % to 80 mass %, and wherein when the light emitting device is configured to emit light of correlated color temperature in a range of 5,500 K to 7,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.4 to 1.5;
when the light emitting device is configured to emit light of correlated color temperature in a range of 4,500 K to 5,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.4 to 1.5;
when the light emitting device is configured to emit light of correlated color temperature in a range of 3,500 K to 4,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.3 to 1.3; and
when the light emitting device is configured to emit light of correlated color temperature in a range of 2,500 K to 3,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.2 to 1.4;
wherein the light emitting device is configured to emit light with a sum of special color rendering Indices R9 to R15 of 600 or greater.

US Pat. No. 10,559,724

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SAME

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a light emitting element including a light extraction surface, an electrode-formed surface on a side opposite to the light extraction surface, lateral surfaces positioned between the light extraction surface and the electrode-formed surface, and a pair of electrodes on the electrode-formed surface;
a reflective member covering the lateral surfaces of the light emitting element, the part of the pair of the electrodes being exposed from the reflective member;
a first light-transmissive member arranged at least between lateral surfaces of the light emitting element and the reflective member, the first light-transmissive member being in contact with the lateral surfaces of the light emitting element;
a covering member including a lens portion on an upper surface thereof, the covering member covering the light emitting element and the reflective member;
a wavelength conversion member arranged over the light extraction surface of the light emitting element, the wavelength conversion member including a light-transmissive portion; and
a second light-transmissive member arranged between the wavelength conversion member and the covering member with an outer edge of the second light-transmissive member being disposed on an outer side of an outer edge of the light-transmissive portion of the wavelength conversion member, as seen in a plan view, a thickness of the second light-transmissive member as measured between the wavelength conversion member and the covering member being smaller than a thickness of the wavelength conversion member.

US Pat. No. 10,559,723

OPTICAL DEVICE

ROHM CO., LTD., Kyoto (J...

1. An optical device comprising:a substrate having an obverse surface and a reverse surface facing away from each other;
an obverse-surface conductive layer formed on the obverse surface of the substrate, the obverse-surface conductive layer including a first obverse-surface conducting region and a second obverse-surface conductive region;
a reverse-surface conductive layer formed on the reverse surface of the substrate;
a first conductive part extending through the substrate and overlapping with the first obverse-surface conducting region and the reverse-surface conductive layer as viewed in a thickness direction of the substrate;
an optical element disposed on the obverse-surface conductive layer; and
a reflector disposed on the substrate, the reflector having an inner surface that surrounds the optical element as viewed in the thickness direction,
wherein the optical element is located on the first obverse-surface conducting region, and the second obverse-surface conducting region is located between the first obverse-surface conducting region and the inner surface of the reflector as viewed in the thickness direction,
wherein the second obverse-surface conducting region is spaced apart from the inner surface of the reflector as viewed in the thickness direction, and
wherein the obverse-surface conductive layer includes a third obverse-surface conducting region that is disposed between the first obverse-surface conducting region and the second obverse-surface conducting region as viewed in the thickness direction and that connects the first obverse-surface conducting region and the second obverse-surface conducting region.

US Pat. No. 10,559,720

HIGH-POWER LIGHT-EMITTING DIODE AND LIGHT-EMITTING MODULE HAVING THE SAME

Seoul Viosys Co., Ltd., ...

1. A light emitting diode, comprising:a gallium nitride substrate;
a first conductivity-type semiconductor layer disposed on the gallium nitride substrate;
a mesa comprising a second conductivity-type semiconductor layer disposed on the first conductivity-type semiconductor layer and an active layer interposed between the second conductivity-type semiconductor layer and the first conductivity-type semiconductor layer;
a first contact layer comprising an outer contact portion disposed along a circumference of the mesa and contacting the first conductivity-type semiconductor layer near an edge of the gallium nitride substrate and a plurality of inner contact portions disposed in a region surrounded by the outer contact portion and contacting the first conductivity-type semiconductor layer;
a second contact layer disposed on the mesa and contacting the second conductivity-type semiconductor layer;
an upper insulation layer having a first opening overlapping the first contact layer and a second opening overlapping the second contact layer;
a first electrode pad electrically connected to the first contact layer through the first opening; and
a second electrode pad electrically connected to the second contact layer through the second opening,
wherein the light emitting diode is configured to operate at a current density of between 150 A/cm2 and 315 A/cm2 with a maximum junction temperature of between 150° C. and 190 °.

US Pat. No. 10,559,718

LIGHT-EMITTING DEVICE HAVING PLURAL RECESSES IN LAYERS

LG INNOTEK CO., LTD., Se...

1. A light emitting device comprising:a first conductive semiconductor layer;
an active layer disposed on the first conductive semiconductor layer and including a plurality of first recesses;
an electron blocking layer including a bent region including a plurality of second recesses disposed on the first recesses and a flat region disposed between the plurality of second recesses; and
a second conductive semiconductor layer disposed on the electron blocking layer,
wherein a ratio of a doping concentration of the flat region to a doping concentration of the bent region is in a range of 1:0.8 to 1:1,
wherein the active layer generates a first light and a second light,
wherein the first light has a peak in a wavelength band of 450 nm to 499 nm,
wherein the second light has a peak in a wavelength band of 500 nm to 550 nm, and wherein the electron blocking layer includes a first carrier injecting path formed in the flat region and a second carrier injecting path formed in the bent region.

US Pat. No. 10,559,717

LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF

EPISTAR CORPORATION, Hsi...

1. A light-emitting device, comprising:a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed therebetween, wherein the first semiconductor layer comprises a surrounding exposed region not covered by the active layer, and the surrounding exposed region surrounds the active layer;
a conductive layer formed on the second semiconductor layer, comprising a first conductive region extending toward and contacting the surrounding exposed region of the first semiconductor layer;
an electrode layer formed on the first conductive region in the surrounding exposed region;
an outside insulating layer covering a portion of the conductive layer and the electrode layer, and comprising a first opening exposing the other portion of the conductive layer;
a bonding layer covering the outside insulating layer and electrically connecting to the other portion of the conductive layer through the first opening; and
a conductive substrate, wherein the semiconductor stack is located on one side of the bonding layer, and the conductive substrate is located on the other side of the bonding layer.

US Pat. No. 10,559,713

MULTIPLE QUANTUM WELL LIGHT-EMITTING DEVICE

1. A light-emitting device comprising:a substrate;
three-dimensional semiconductor elements resting on the substrate;
for each semiconductor element, at least one shell at least partially covering lateral walls of the semiconductor element, the shell comprising an active area having multiple quantum wells; and
an electrode at least partially covering the shell, at least a portion of the active area being sandwiched between the electrode and the lateral walls of the semiconductor element,
wherein the active area comprises an alternation of first semiconductor layers mainly comprising a first element and a second element and of second semiconductor layers mainly comprising the first element and the second element and further comprising a third element, and wherein, in each of at least three of the second layers, mass concentration of the third element increases in said portion of the active area as a distance to the substrate decreases.

US Pat. No. 10,559,707

PHOTODETECTOR AND LIDAR DEVICE USING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A photodetector comprising:a first semiconductor layer;
a porous semiconductor layer disposed on the first semiconductor layer; and
at least one photo-sensing element including a second semiconductor layer of a first conductivity type disposed in a region of the porous semiconductor layer and a third semiconductor layer of a second conductivity type disposed on the second semiconductor layer.

US Pat. No. 10,559,706

AVALANCHE PHOTODIODE TYPE STRUCTURE AND METHOD OF FABRICATING SUCH A STRUCTURE

1. An avalanche photodiode type structure designed to receive an electromagnetic radiation within a first range of wave lengths, the structure comprising:a first semiconducting zone of a first type of conductivity for which majority carriers are holes, and with a first face intended to receive the electromagnetic radiation and a second face opposite the first face, the first semiconducting zone forming an absorption zone for absorbing the electromagnetic radiation,
a second semiconducting zone, called a multiplication zone, in contact with the second face of the first semiconducting zone and with a lower concentration of majority carriers than the first semiconducting zone, the second semiconducting zone being conformed to supply a multiplication of carriers by impact ionization that is preponderant for electrons,
a fourth semiconducting zone called a collection zone, the fourth semiconducting zone being of a second type of conductivity for which majority carriers are electrons, the fourth semiconducting zone having a higher concentration of majority carriers than the second semiconducting zone,
wherein at least one of the first and second semiconducting zones being formed from a semiconducting material with a suitable band gap width to promote absorption of the electromagnetic radiation,
wherein the structure comprises a third and a fifth semiconducting zone arranged between the second semiconducting zone and the fourth semiconducting zone, the third semiconducting zone having a lower concentration of majority carriers than the first semiconducting zone, the fourth semiconducting zone and the fifth semiconducting zone, the fifth semiconducting zone being of the second type of conductivity and having a higher concentration of majority carriers than the second semiconducting zone so as to create an electric field in the third semiconducting zone without multiplication of carriers by impact ionization,
wherein the third semiconducting zone is arranged between the fifth semiconducting zone and the fourth semiconducting zone, the fifth semiconducting zone being in contact with the second semiconducting zone,
wherein the third semiconducting zone has a lower concentration of majority carriers than the second semiconducting zone.

US Pat. No. 10,559,703

THICK-FILM PASTES CONTAINING LEAD-TELLURIUM-BORON-OXIDES, AND THEIR USE IN THE MANUFACTURE OF SEMICONDUCTOR DEVICES

DUPONT ELECTRONICS, INC.,...

1. A thick-film paste composition comprising:a) 85 to 99.5% by weight of an electrically conductive metal or derivative thereof, based on total solids in the composition;
b) 0.5 to 15% by weight based on solids of a lead-tellurium-boron-oxide, wherein the lead-tellurium-boron-oxide comprises 25 to 60 wt % PbO, greater than 25 to 70 wt % TeO2, 0.1 to less than 5 wt % B2O3, and 0 to 15 wt. % V2O5; and
c) an organic medium.

US Pat. No. 10,559,702

MONOLITHICALLY INTEGRATED THIN-FILM DEVICE WITH A SOLAR CELL, AN INTEGRATED BATTERY, AND A CONTROLLER

International Business Ma...

1. A method for manufacturing a thin-film solar module in a superstrate configuration, the method comprising:fabricating a thin-film solar cell, having at least one solar diode on a transparent substrate at a first temperature;
fabricating a thin-film energy storage device after the thin-film solar cell at a second temperature;
fabricating an electronic controller, comprising at least one thin-film transistor, above the thin-film energy storage device; fabricating an oxide semiconductor at room temperature on top of the thin-film energy storage device after the fabricating of the thin-film energy storage device: and
providing electrical connections between the electronic controller and the thin-film solar cell by a first set of vias, wherein the electronic controller is electrically connected to the thin-film energy storage device by a second set of vias, wherein the first set of vias extends through at least the thin-film energy storage device.

US Pat. No. 10,559,699

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductive layer over an insulating surface;
a first insulating layer over the first conductive layer;
oxide semiconductor stacked lavers comprising a first oxide semiconductor layer and a second oxide semiconductor layer, the oxide semiconductor stacked layers comprise a region overlapping with the first conductive layer with the first insulating layer interposed therebetween;
a second conductive layer and a third conductive layer, each of which comprises a region over and in contact with the second oxide semiconductor layer;
a second insulating layer comprising a region in direct contact with the oxide semiconductor stacked layers and positioned over the oxide semiconductor stacked layers, the second conductive layer and the third conductive layer; and
a fourth conductive layer comprising a region overlapping with the oxide semiconductor stacked layers with the second insulating layer interposed therebetween,
wherein the second semiconductor layer is provided over the first oxide semiconductor layer,
wherein the first oxide semiconductor layer comprises a region in direct contact with the first insulating layer,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises at least indium and gallium,
wherein an indium content in the first oxide semiconductor layer is higher than a gallium content,
wherein an indium content in the second oxide semiconductor layer is lower than a gallium content,
wherein the first oxide semiconductor layer comprises a microcrystal,
wherein the second oxide semiconductor layer comprises a c-axis aligned crystal part,
wherein the first conductive layer comprises molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, and
wherein the fourth conductive layer comprises indium oxide-tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium oxide-zinc oxide, or indium tin oxide to which silicon oxide is added.

US Pat. No. 10,559,698

OXIDE THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An oxide thin film transistor (Oxide TFT), comprising:a base substrate;
a gate electrode, a gate insulating layer and an active layer that are on the base substrate;
a source electrode and a drain electrode, the active layer being at least partly covered with the source electrode and the drain electrode; and
a channel protection layer between the source electrode and the drain electrode, each of the source electrode and the drain electrode comprising at least part of a first metallic layer and at least part of a second metallic layer, the first metallic and the second metallic layer being stacked one on another, wherein
a material of the second metallic layer is Copper (Cu),
a material of the first metallic layer is configured to be capable of being directly oxidized by an etchant of the second metallic layer, and
the channel protection layer is of a metal oxide of at least a part of the first metallic layer.

US Pat. No. 10,559,696

HYBRID CMOS DEVICE AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A manufacturing method of a hybrid CMOS device, comprising the following steps:step S1: providing a substrate, forming a buffer layer on the substrate, forming a first active layer on the buffer layer, the material of the first active layer comprising a low-temperature polysilicon;
forming a first gate insulating layer covering the first active layer on the buffer layer;
forming a first gate corresponding to a top of the first active layer and a second gate arranged spaced apart from the first gate on the first gate insulating layer;
step S2: performing a P-type heavy doping on two ends of the first active layer by using the first gate as a barrier layer, respectively forming a source contact region and a drain contact region on the two ends of the first active layer to obtain a sample to be hydrogenated;
step S3: performing a plasma treatment on the sample to be hydrogenated by using a hydrogen plasma to hydrogenate the first active layer;
step S4: forming a second gate insulating layer covering the first gate and the second gate on the first gate insulating layer;
forming a second active layer corresponding to a top of the second gate on the second gate insulating layer, a material of the second active layer comprising a metal oxide semiconductor;
step S5: forming an etched barrier layer on the second active layer, and forming a first via corresponding to a top of the source contact region of the first active layer and a second via corresponding to a top of the drain contact region of the first active layer on the first gate insulating layer and the second gate insulating layer;
step S6: forming a first source on the second gate insulating layer and a source-drain common structural layer and a second drain on the etched barrier layer, the second active layer and the second gate insulating layer;
the first source contacted with the source contact region of the first active layer via the first via; one end of the source-drain common structural layer contacted with the drain contact region of the first active layer via the second via, and the other end is directly contacted with one end of the second active layer; the second drain directly contact with the other end of the second active layer; a hybrid CMOS device being manufactured;
step S7: performing an annealing treatment on the hybrid CMOS device, wherein the annealing treatment is performed in a nitrogen environment, a temperature of the annealing treatment is 300° C. to 400° C., and a period for the annealing treatment is one hour to three hours;
step S8: after performing the annealing treatment, performing a rapid thermal annealing treatment on the hybrid CMOS device to remove hydrogen in the second active layer, wherein the rapid thermal annealing treatment is performed in a nitrogen environment, a temperature of the rapid thermal annealing treatment is 500° C. to 520° C., and a period for the rapid thermal annealing treatment is one minute to five minutes;
wherein in the hybrid CMOS device, the first active layer, the first gate, the first source, and the source-drain common structural layer jointly form a PMOS transistor, and the second active layer, the second gate, the source-drain common structural layer, and the second drain jointly form an NMOS transistor; in the PMOS transistor, the source-drain common structural layer functions as a drain; in the NMOS transistor, the source-drain common structural layer functions as a source.

US Pat. No. 10,559,694

GRAPHENE TRANSISTORS ON MICROBIAL CELLULOSE

HRL Laboratories, LLC, M...

1. A method of making a device comprising:transferring a biopolymer membrane onto a handling wafer;
forming a passivation layer on the biopolymer membrane;
transferring graphene onto the passivation layer;
patterning the graphene to form at least one graphene mesa;
forming a source contact on the graphene mesa;
forming a drain contact on the graphene mesa;
etching the passivation layer surrounding the graphene mesa, the source contact, and the drain contact to expose the biopolymer membrane; and
releasing the biopolymer membrane from the handling wafer.

US Pat. No. 10,559,687

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate;
a first active region and a second active region, which are arranged on the substrate;
a first recess on the first active region and intersecting with the first active region;
a second recess on the second active region and intersecting with the second active region;
a first gate spacer extending along sidewalls of the first recess and a second gate spacer extending along sidewalls of the second recess;
a first lower high-k dielectric film in the first recess, the first lower high-k dielectric film including a first high-k dielectric material in a first concentration and a second high-k dielectric material that is different from the first high-k dielectric material;
a second lower high-k dielectric film in the second recess, the second lower high-k dielectric film including the first high-k dielectric material in a second concentration that is greater than the first concentration, and the second high-k dielectric material;
a first metal-containing film on the first lower high-k dielectric film in the first recess, the first metal-containing film including silicon (Si) in a third concentration; and
a second metal-containing film on the second lower high-k dielectric film in the second recess, the second metal-containing film including silicon (Si) in a fourth concentration that is smaller than the third concentration.

US Pat. No. 10,559,686

METHODS OF FORMING GATE CONTACT OVER ACTIVE REGION FOR VERTICAL FINFET, AND STRUCTURES FORMED THEREBY

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a gate contact over an active region for a vertical FinFET, the method comprising:providing a partial vertical FinFET (VFinFET) structure, the partial VFinFET structure including a substrate having a bottom source/drain (S/D) layer thereover and a plurality of fins extending vertically therefrom, a bottom spacer layer over the bottom S/D layer, a high-k metal gate (HKMG) layer over the bottom spacer layer, and a top spacer layer over the HKMG layer;
forming a top S/D layer on a top surface of each of the fins;
forming at least two top S/D contacts on the top S/D layer and an upper interlayer dielectric (ILD) layer surrounding the at least two top S/D contacts, the at least two top S/D contacts being located directly above at least two adjacent fins;
creating recesses in a portion of each of the at least two top S/D contacts;
forming an isolation dielectric within a portion of the recesses, a remaining portion of the recesses being a gate contact landing region above the at least two adjacent fins;
removing at least a portion of the upper ILD layer and at least a portion of the top spacer layer between adjacent ends of the at least two adjacent fins to expose a portion of the HKMG layer located thereunder, thereby forming a gate contact opening; and
forming a gate contact in the gate contact opening and a gate contact landing in the gate contact landing region.

US Pat. No. 10,559,683

APPARATUS AND METHODS TO CREATE A BUFFER TO REDUCE LEAKAGE IN MICROELECTRONIC TRANSISTORS

Intel Corporation, Santa...

1. A microelectronic structure, comprising:a substrate;
a low band-gap active channel;
a high band-gap sub-structure, comprising a single material, disposed between the substrate and the low band-gap active channel, wherein the high band-gap sub-structure is a single structure that is the single material that extends from the substrate and abuts the low band-gap active channel to form an intersection therebetween;
an isolation structure on the substrate, wherein the high band-gap sub-structure is embedded in the isolation structure and wherein a portion of the low band-gap active channel is embedded in the isolation structure and another portion of the low hand-gap active channel extends above the isolation structure, such that the intersection is below an upper plane of the isolation structure;
a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench, wherein the high band-gap sub-structure and the nucleation layer are different materials and wherein the high band-gap sub-structure abuts the nucleation layer; and
a gate formed over the another portion of the active channel extending above the isolation structure, wherein the gate contacts the low band-gap active channel above the isolation structure.

US Pat. No. 10,559,679

NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE

COORSTEK KK, Shinagawa-K...

1. A nitride semiconductor epitaxial substrate, comprising a channel layer, a spacer layer, and an electron supply layer in this order, whereinthe channel layer is GaN,
the spacer layer is AlaGa1-aN(0 the electron supply layer is AlxInyGa1-x-yN 0.1?x?0.3 and y=0), and
the spacer layer has a thickness of one or two molecular layers wherein the thickness of one molecular layer is 0.25 nm.

US Pat. No. 10,559,677

METHOD OF FABRICATING AN ENHANCEMENT MODE GROUP III-NITRIDE HEMT DEVICE AND A GROUP III-NITRIDE STRUCTURE FABRICATED THEREFROM

IMEC VZW, Leuven (BE)

15. An enhancement mode Group III-nitride HEMT device comprising:a substrate having a main surface;
a layer stack overlying the main surface, wherein each layer of the layer stack comprises a Group III-nitride material;
a capping layer on the layer stack;
a recessed gate region through the capping layer; and
a monocrystalline p-type doped GaN layer in the recessed gate region and on the capping layer,
wherein the capping layer comprises an un-doped Group III-nitride material susceptible to nucleation of the monocrystalline p-type doped GaN layer at a predetermined temperature between 750° C. to 1,100° C.

US Pat. No. 10,559,676

VERTICAL FET WITH DIFFERENTIAL TOP SPACER

International Business Ma...

1. A method of forming a vertical transport field effect transistor (VTFET) device, comprising the steps of:patterning fins in a wafer, the fins comprising n-channel FET (NFET) fins and p-channel FET (PFET) fins;
forming bottom source and drains at a base of the NFET fins and the PFET fins;
forming bottom spacers on the bottom source and drains;
forming gate stacks alongside the NFET fins and the PFET fins, wherein the gate stacks formed alongside the NFET fins and the PFET fins comprise a same workfunction metal on top of a gate dielectric;
annealing the gate stacks which generates oxygen vacancies in the gate dielectric;
depositing a gate fill metal over the NFET fins, the PFET fins and the gate stacks;
forming top spacers over the gate stacks at tops of the NFET fins and the PFET fins, wherein the top spacers comprise an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and
forming top source and drains above the gate stacks at the tops of the NFET fins and the PFET fins.

US Pat. No. 10,559,673

SEMICONDUCTOR DEVICES HAVING VERTICAL TRANSISTORS WITH ALIGNED GATE ELECTRODES

SAMSUNG ELECTRONICS CO., ...

1. A method of fabricating a semiconductor device, the method comprising:forming an active pillar protruding from a surface of a semiconductor substrate;
forming a first source/drain region in the semiconductor substrate at a bottom end of the active pillar;
forming a first insulating layer covering the active pillar;
removing a portion of the first insulating layer to expose an upper portion of the active pillar;
forming a second source/drain region on the exposed upper portion of the active pillar, the second source/drain region having a greater width than the active pillar and spaced apart from the first insulating layer;
forming a second insulating layer on a sidewall and a bottom surface of the second source/drain region;
removing the first insulating layer to expose a bottom surface of the second insulating layer and a portion of a sidewall of the active pillar; and
forming a gate electrode on the bottom surface of the second insulating layer and on the sidewall of the active pillar.

US Pat. No. 10,559,671

VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR INCLUDING AIR-GAP TOP SPACER

International Business Ma...

1. A vertical transport field-effect transistor structure, comprising:a substrate;
a semiconductor fin extending vertically with respect to the substrate, the semiconductor fin including a top region, a bottom region, and a channel region between the top region and the bottom region;
a bottom source/drain region adjoining the bottom region of the semiconductor fin;
a gate dielectric layer adjoining the channel region of the semiconductor fin;
an electrically conductive gate electrode layer adjoining the gate dielectric layer;
a bottom dielectric spacer between the bottom source/drain region and the gate electrode layer;
first and second vertically extending dielectric layers;
a cavity bounded by the first and second vertically extending dielectric layers, the top region of the semiconductor fin extending within the cavity;
first and second divots extending downwardly from the cavity and located between the top region of the semiconductor fin and the first and second vertically extending dielectric layers;
a faceted, epitaxial top source/drain region on the top region of the semiconductor fin and within the cavity;
a dielectric liner extending over the gate dielectric layer and the gate electrode layer; and
a top spacer comprising first and second open gaps between the faceted, epitaxial top source/drain region and the dielectric liner.

US Pat. No. 10,559,669

INDIUM GALLIUM ARSENIDE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING A LOW CONTACT RESISTANCE TO METAL ELECTRODE

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device comprising:providing a field effect transistor including a region composed of a type III-V semiconductor material and an n-type conductivity;
forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface of the at least one of the type III-V semiconductor material to provide a passivated surface;
forming an n-type zinc oxide containing layer on the passivated surface; and
forming a metal contact on the n-type zinc oxide containing layer.

US Pat. No. 10,559,668

SEMICONDUCTOR DEVICE WITH SURFACE INSULATING FILM

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device, comprising:a semiconductor substrate;
a cell portion arranged at a center portion of the semiconductor substrate in a plan view;
an outer peripheral portion surrounding the cell portion in a plan view;
a plurality of gate trenches formed at the surface of the semiconductor substrate at the cell portion;
a plurality of gate electrodes formed so as to be buried in the plurality of gate trenches;
a surface insulating film with a first thickness formed so as to cover the plurality of gate electrodes at the cell portion, and with a second thickness formed so as to cover the semiconductor substrate at the outer peripheral portion;
a first source portion formed on/over the semiconductor substrate at the cell portion;
a gate portion formed on/over the semiconductor substrate at the outer peripheral portion;
a second source portion formed on/over the semiconductor substrate so as to surround the gate portion at the outer peripheral portion; and
a slit region formed in a uniform width along the gate portion in a plan view, wherein
the first thickness is thinner than the second thickness,
the gate portion has a gate pad that is formed at a center of a first line of the semiconductor substrate, and a gate finger that is formed along with the outer peripheral portion in a plan view,
the plurality of gate trenches are formed on/over the semiconductor substrate at the cell portion in a striped shape, and extends to reach the outer peripheral portion, and
the plurality of gate trenches are formed in a manner running across the gate finger in a region under the gate finger.

US Pat. No. 10,559,667

SEMICONDUCTOR DEVICE AND METHOD FOR MEASURING CURRENT OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor comprising:
a first gate;
a first gate insulating film over the first gate;
a first oxide semiconductor layer over the first gate insulating film, the first oxide semiconductor layer including a channel formation region overlapping with the first gate, wherein a width of the channel formation region is smaller than 70 nm;
a first conductive film and a second conductive film each over and in contact with a first region and a second region of a top surface of the first oxide semiconductor layer;
a second oxide semiconductor layer over and in contact with a top surface and side surfaces of each of the first conductive film and the second conductive film, and a third region of the top surface and side surfaces of the first oxide semiconductor layer;
a second gate insulating film over the second oxide semiconductor layer; and
a second gate over the second gate insulating film, the second gate overlapping with the channel formation region,
wherein a temporal change of off-state current of the first transistor is represented by Formula (a2):

wherein IOFF represents the off-state current, t represents time during which the first transistor is off, ? and ? are constants, ? is a constant that satisfies 0

US Pat. No. 10,559,665

FIELD-EFFECT TRANSISTOR

Qorvo US, Inc., Greensbo...

1. A field-effect transistor comprising:a substrate;
a channel layer having a proximal boundary relative to the substrate and a distal boundary relative to the substrate, wherein the channel layer is disposed over the substrate; and
a gate electrically isolated from the channel layer, a source, and a drain disposed over the channel layer, wherein the channel layer comprises a compound semiconductor material that includes at least one element having a concentration that is graded throughout the entire channel layer between the proximal boundary and the distal boundary beneath the drain, the gate, and the source, wherein a lower concentration of the at least one element at the distal boundary of the channel layer is no greater than 10% of a higher concentration of the at least one element at the proximal boundary of the channel layer such that transconductance (gm) of the field-effect transistor remains within 65% of a maximum gm value over at least 85% of a gate voltage range that transitions the field-effect transistor between an on-state that allows substantial current flow between the drain and the source through the channel layer and an off-state that prevents substantial current flow between the drain and the source through the channel layer.

US Pat. No. 10,559,663

SEMICONDUCTOR DEVICE WITH IMPROVED CURRENT FLOW DISTRIBUTION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate;
a transistor section provided in the semiconductor substrate; and
a diode section provided in the semiconductor substrate being adjacent to the transistor section; wherein
the diode section comprises:
a second conductivity-type anode region at least partially exposed on an upper surface of the semiconductor substrate;
a first conductivity-type drift region provided below the anode region;
a first conductivity-type cathode region provided below the drift region;
a plurality of dummy trench portions that penetrate at least the anode region and are arrayed along a predetermined array direction;
a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and
a second conductivity-type lower-surface side semiconductor region provided below the drift region and provided directly below an outer end portion of the contact portion in the extending direction.

US Pat. No. 10,559,661

TRANSISTOR DEVICE AND SEMICONDUCTOR LAYOUT STRUCTURE INCLUDING ASYMMETRICAL CHANNEL REGION

NANYA TECHNOLOGY CORPORAT...

1. A transistor device comprising:an active region disposed in a substrate, the active region comprising a first region comprising a first length, a second region comprising a second length, and a third region between the first region and the second region, wherein the first length is greater than the second length;
a gate structure disposed over the active region, the gate structure comprising:
a first portion extending in a first direction and disposed over at least the third region of the active region; and
a second portion extending in a second direction perpendicular to the first direction and disposed over at least a portion of the third region and a portion of the second region; and
a source/drain region disposed at two opposite sides of the gate structure;
wherein the first region comprises a first boundary and a second boundary, wherein the first boundary and the second boundary extend in the second direction, the second region comprises a third boundary and a fourth boundary, wherein the third boundary and the fourth boundary extend in the second direction, and the third region comprises a fifth boundary and a sixth boundary, wherein the fifth boundary extends in the second direction;
wherein the first boundary of the first region, the third boundary of the second region, and the fifth boundary of the third region are collinear with each other;
wherein the sixth boundary of the third region is in contact with the second boundary of the first region at a first point and the fourth boundary of the second region at a second point, the sixth boundary of the third region is a slanted line connecting the first point and the second point;
wherein the gate structure is absent from disposing over the first region of the active region;
wherein the gate structure is absent from disposing over at least one area of the second region of the active region.

US Pat. No. 10,559,652

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a drift layer that lies over an active region and a region outside the active region and is of a first conductivity type;
a well region that is provided on the drift layer within the active region and is of a second conductivity type different from the first conductivity type;
a first impurity region that is provided on the well region, is separated from the drift layer by the well region, and is of the first conductivity type;
a gate trench that is provided within the active region and includes a sidewall facing the first impurity region, the well region, and the drift layer;
an outer trench provided in the drift layer outside the active region;
a gate insulating film provided in the gate trench and the outer trench;
a gate electrode provided in the gate trench with the gate insulating film being interposed;
a gate connection layer that is in contact with the gate electrode and includes a portion placed on the outer trench with the gate insulating film being interposed;
a first main electrode including a main contact that is electrically connected to the well region and the first impurity region within the active region, and an outer contact that is spaced away from the active region and is in contact with a bottom face of the outer trench;
a second main electrode that is electrically connected to the drift layer, is separated from the well region by at least the drift layer, and faces the first main electrode with the drift layer being interposed;
a trench-bottom field relaxing region that is provided in the drift layer, is separated from the second main electrode by the drift layer, and is of the second conductivity type; and
a trench-bottom high-concentration region that is of the second conductivity type, has an impurity concentration higher than an impurity concentration of the trench-bottom field relaxing region, is provided on the trench-bottom field relaxing region, and extends from a position where the trench-bottom high-concentration region faces the gate connection layer with the gate insulating film being interposed, to a position where the trench-bottom high-concentration region is in contact with the outer contact of the first main electrode.

US Pat. No. 10,559,649

METAL INSULATOR METAL CAPACITOR WITH EXTENDED CAPACITOR PLATES

International Business Ma...

1. A metal insulator metal capacitor comprising:a first dielectric layer on a substrate, the first dielectric layer having a trench feature;
a bottom capacitor plate in a lower portion of the trench, the bottom capacitor plate having an extended top face, wherein the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions of the capacitor plate;
a high-k dielectric layer over the extended top face of the bottom capacitor plate; and
a top capacitor plate in a top, remainder portion of the trench on top of the high-k dielectric layer.

US Pat. No. 10,559,647

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus, comprising:a substrate;
a display unit arranged on the substrate;
a dam unit around a periphery of the display unit and on the substrate;
a first inorganic film covering the display unit and the dam unit;
a first organic film covering a portion of the first inorganic film; and
a second inorganic film covering the first organic film and the dam unit;
wherein the first organic film covers an entirety of the display unit,
wherein the dam unit is arranged at a periphery of the first organic film,
wherein the first organic film covers an upper surface and side surfaces of the display unit, and
wherein the first organic film is between the first inorganic film and the second inorganic film.

US Pat. No. 10,559,636

PIXEL CIRCUIT AND DISPLAY DEVICE, AND A METHOD OF MANUFACTURING PIXEL CIRCUIT

Sony Corporation, Tokyo ...

1. An organic EL display device comprising a plurality of pixel circuits, one of the plurality of pixel circuits including:a semiconductor layer comprising a first node of a first transistor, and a second node of the first transistor, a first node of a second transistor, and a second node of the second transistor;
a first metal layer comprising a first scanning line;
a second metal layer comprising a data signal line, a voltage supply line and a first wiring;
a third metal layer comprising an anode electrode of a light emitting element; and
a fourth metal layer comprising a cathode electrode of a light emitting element wherein:
the data signal line is connected to the first node of the first transistor,
the second transistor is connected between the voltage line and the light emitting element,
the first node of the second transistor is connected to the anode electrode of the light emitting element via the first wiring,
the data signal line extends along a first direction,
the first scanning line extends along a second direction perpendicular to the first direction,
the first scanning line electrically connects to a control terminal of the first transistor,
the data signal line crosses the first scanning line outside of a light emission region of the light emitting element,
the second metal layer includes aluminum.

US Pat. No. 10,559,635

PIXEL DEFINING LAYER, PRODUCTION METHOD THEREOF, AND DISPLAY SUBSTRATE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel defining layer, comprisinga base substrate,
a lyophilic material layer,
a first lyophobic material layer, and
a second lyophobic material layer,
wherein
the lyophilic material layer is located between the first lyophobic material layer and the base substrate, and the second lyophobic material layer is located between the lyophilic material layer and the first lyophobic material layer;
the first lyophobic material layer is repellent to solutions for forming respective layers of a light-emitting diode, the lyophilic material layer attracts the solutions for forming respective layers of the light-emitting diode, and the second lyophobic material layer is repellent to the solutions for forming respective layers of the light-emitting diode;
the pixel defining layer defines a plurality of openings in an array arrangement;
the first lyophobic material layer has a plurality of wall surfaces facing to each of the openings, wherein at least one wall surface of the plurality of wall surfaces has a slope angle larger than 0 degree and less than 90 degrees; and
a lyophobicity of the second lyophobic material layer is less than a lyophobicity of the first lyophobic material layer.

US Pat. No. 10,559,632

DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate comprising:a base substrate;
a plurality of light-emitting devices on the base substrate for displaying;
a plurality of driver thin film transistors on the base substrate for driving the plurality of light-emitting devices to emit light;
a plurality of optical fingerprint identification devices on the base substrate; and
a plurality of switch thin film transistors on the base substrate for controlling the plurality of optical fingerprint identification devices;
wherein the plurality of optical fingerprint identification devices are in a display area of the display substrate; and
wherein each film layer of each of the plurality of driver thin film transistors and a corresponding same film layer of each of the plurality of switch thin film transistors are in an identical layer and are made of a same material.

US Pat. No. 10,559,630

LIGHT EMITTING DEVICES FEATURING OPTICAL MODE ENHANCEMENT

X Development LLC, Mount...

1. A light emitting device, comprising:a substrate supporting a first light emitting element and a second light emitting element, the first light emitting element being configured to emit, in a first principal direction, light in a first wavelength band and the second light emitting element being configured to emit, in the first principal direction, light in a second wavelength band different from the first wavelength band, each light emitting element comprising:
a light emitting diode layer, extending in a plane perpendicular to the first principal direction, having a thickness of 10 microns or less in the first principal direction and a maximum lateral dimension of 100 microns or less orthogonal to the first principal direction, the light emitting diode layer comprising a semiconductor material; and
one or more layers configured to enhance an optical mode of the light emitted in the corresponding first or second wavelength band perpendicular to the plane and/or suppress an optical mode of the light emitted in the corresponding first or second wavelength band in the plane,
wherein, for at least one of the light emitting elements, the one or more layers comprise at least two layers positioned on opposite sides of the diode layer,
and wherein the at least two layers form a resonant optical cavity configured to enhance the optical mode of the light emitted in the corresponding one of the first or second wavelength bands perpendicular to the plane and the two layers are reflective at the corresponding one of the first and second emitted wavelengths.

US Pat. No. 10,559,628

SOLID-STATE IMAGE SENSOR, METHOD OF PRODUCING THE SAME, AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A solid-state image sensor, comprising,a pixel formed, upon forming a structure where a photoelectric conversion layer is laminated on a wiring layer constituting a pixel circuit, by forming at least the photoelectric conversion layer and a wiring layer bonding film on a different substrate from a semiconductor substrate in which the wiring layer is formed, and by bonding the wiring layer bonding film of the different substrate and the wiring layer of the semiconductor substrate together,
wherein the photoelectric conversion layer and the wiring layer bonding film are separated from each other for each pixel by removing the photoelectric conversion layer and the wiring layer bonding film on a pixel boundary portion after the bonding.

US Pat. No. 10,559,624

SELECTOR DEVICE HAVING ASYMMETRIC CONDUCTANCE FOR MEMORY APPLICATIONS

Avalanche Technology, Inc...

1. A memory cell comprising:a magnetic tunnel junction (MTJ) memory element including a magnetic free layer and a magnetic reference layer with an insulating tunnel junction layer interposed therebetween, said MTJ memory element having a low resistance state and a high resistance state that are switched in a bipolar manner; and
a two-terminal selector conducting in two directions, said two-terminal selector having a first insulative state and a first conductive state in a first direction and a second insulative state and a second conductive state in a second direction opposite to said first direction, said first conductive state having substantially lower resistance than said second conductive state,
wherein said two-terminal selector and said MTJ memory element are coupled in series in such a way that a switching current flowing in said second direction switches said MTJ memory element from said high resistance state to said low resistance state.

US Pat. No. 10,559,623

METHOD FOR MANUFACTURING IMAGE CAPTURING DEVICE AND IMAGE CAPTURING DEVICE

Renesas Electronics Corpo...

1. A method for manufacturing an image capturing device having a semiconductor substrate provided with a pixel region including a pixel having a photodiode, and a peripheral region adjacent to the pixel region and having a first peripheral transistor, the method comprising the steps of:(a) forming a first peripheral gate electrode of the first peripheral transistor in the peripheral region;
(b) forming the photodiode in the pixel region;
(c) forming a first insulating film so as to cover the pixel region and the peripheral region;
(d) forming a first resist pattern over the first insulating film so as to cover the pixel region;
(e) performing anisotropic etching of the first insulating film to form respective offset spacers on opposite side surfaces of the first peripheral gate electrode;
(f) removing the first resist pattern;
(g) forming respective first extension diffusion regions in the peripheral region on the opposite side surface sides of the first peripheral gate electrode by implanting an n type or p type impurity using the first peripheral gate electrode and the offset spacers as an implantation mask; and
(h) removing at least a portion of the first insulating film on the pixel region by performing a wet etching process.

US Pat. No. 10,559,618

METHODS AND APPARATUS FOR AN IMAGE SENSOR

SEMICONDUCTOR COMPONENTS ...

1. An image sensor, comprising:a substrate, comprising a plurality of pixels;
an array of dielectric elements disposed on a surface of the substrate, wherein;
each dielectric element comprises a convex surface extending upwardly away from the surface of the substrate; and
each dielectric element corresponds to and is vertically aligned with one pixel;
an array of color filters, wherein:
each color filter is disposed on the convex surface of one dielectric element; and
each color filter comprises a convex surface positioned above the convex surface of the dielectric element; and
wherein:
the substrate, the array of dielectric elements, and the array of color filters form a vertical stack;
each of the substrate, the dielectric elements, and the color filters have a predetermined refractive index; and
the refractive indices of the vertical stack increase in value from the color filter to the substrate.

US Pat. No. 10,559,616

SOLID-STATE IMAGING APPARATUS AND ELECTRONIC DEVICE

Sony Semiconductor Soluti...

1. A solid-state imaging apparatus comprising:a pixel array block on which a plurality of adjacent pixels is arranged, each pixel including a photoelectric conversion device;
a polarizer including a first conductive light-shielding material, wherein the polarizer covers a photosensitive surface of a photoelectric conversion device of a first pixel of the plurality of adjacent pixels;
a light-shielding film including a second conductive light-shielding material, wherein the light-shielding film is arranged between each of the adjacent pixels on the photosensitive surface side of the photoelectric conversion device of the first pixel of the plurality of adjacent pixels; and
a wiring layer arranged on a side of the photoelectric conversion device opposite to the photosensitive surface of the photoelectric conversion device of the first pixel of the plurality of adjacent pixels,
wherein the light-shielding film is connected to the polarizer and the wiring layer, wherein the polarizer is connected to a wiring of the wiring layer via the light-shielding film, and wherein the polarizer is capable of being applied with a negative potential via the wiring and the light-shielding film.

US Pat. No. 10,559,608

SOLID-STATE IMAGING DEVICE WITH LIGHT SHIELDING FILM AND DRIVING METHOD THEREOF, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device comprising:a first imaging pixel including:
a first photoelectric conversion region;
a first charge accumulation region coupled to the first photoelectric conversion region via a first transfer transistor; and
a first floating diffusion coupled to the first charge accumulation region;
a first phase difference detection pixel including:
a second photoelectric conversion region;
a second charge accumulation region coupled to the second photoelectric conversion region via a second transfer transistor; and
a second floating diffusion coupled to the second charge accumulation region; and
a light shielding film including a first light shielding portion and a second light shielding portion,
wherein the first light shielding portion is disposed above a light receiving surface of the first charge accumulation region, and
wherein the second light shielding portion is disposed above a light receiving surface of the second charge accumulation region and at least a part of a light receiving surface of the second photoelectric conversion region.

US Pat. No. 10,559,604

ARRAY SUBSTRATE, GATE DRIVING CIRCUIT AND DISPLAY PANEL

XIAMEN TIANMA MICRO-ELECT...

1. An array substrate, comprising:a display area and a non-display area, wherein the display area comprises a first display area and a second display area, the non-display area comprises a first non-display area and a second non-display area, wherein the display area is surrounded by the first non-display area, the second non-display area comprises an opening area, and the opening area is surrounded by the first display area;
a plurality of gate line groups and a plurality of first data lines arranged in the first display area, wherein each of the gate line groups comprises a first gate line and a second gate line, and the plurality of gate line groups intersect with the first data lines to define a plurality of sub-pixels arranged in an array, and the sub-pixels in at least two adjacent columns are connected to a same first data line, and among the two sub-pixels in a same row electrically connected to the same first data line, one sub-pixel is connected to the first gate line, and the other sub-pixel is connected to the second gate line; and
a plurality of gate lines and a plurality of second data lines arranged in the second display area, wherein the plurality of gate lines intersect with the second data lines to define a plurality of sub-pixels arranged in an array, the sub-pixels in a same column are connected to a same second data line, and the sub-pixels in different columns are connected to different second data lines, and the sub-pixels in a same row are connected to a same gate line, and the sub-pixels in different rows are connected to different gate lines.

US Pat. No. 10,559,601

ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

7. A method for manufacturing an array substrate, comprising steps of:obtaining a variation of a thickness of an active layer depending on a position on a substrate, the active layer having at least a first region with a larger thickness and a second region with a second thickness, the first thickness being larger than the second thickness;
determining an overlapped area between a source electrode or a drain electrode and the active layer of a thin film transistor to be formed according to the variation such that a ratio of the overlapped area to the thickness of the active layer is kept uniform over the first region and the second region; and
forming the thin film transistor on the substrate such that the formed thin film transistor has the determined overlapped area.

US Pat. No. 10,559,599

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a pixel portion over a substrate; and
a connection portion over the substrate, the connection portion being located outside the pixel portion,
wherein the connection portion comprises:
a first conductive layer comprising a material same as a gate wiring of the pixel portion;
a second conductive layer over the first conductive layer and comprising a material same as a source wiring of the pixel portion; and
a third conductive layer over the second conductive layer and comprising a material same as a pixel electrode of the pixel portion,
wherein the third conductive layer comprises a first region in contact with the second conductive layer,
wherein the third conductive layer comprises a second region in contact with the first conductive layer,
wherein the first conductive layer comprises a first edge and a second edge in a first direction in which the second conductive layer extends, and
wherein the second conductive layer comprises a third region extending from the first edge, and a fourth region extending from the second edge,
wherein, in a plan view:
in a second direction intersecting with the first direction, the second conductive layer comprises a first width, a second width smaller than the first width, and a third width smaller than the first width,
the third region has the second width,
the fourth region has the third width,
the second conductive layer comprises a fifth region between the third region and the fourth region, the fifth region having the first width,
the first conductive layer comprises a sixth region extending from the second conductive layer,
the sixth region overlaps the third conductive layer, and
the first region overlaps with the fifth region.

US Pat. No. 10,559,596

DISPLAY DEVICE

INNOLUX CORPORATION, Chu...

1. A display device, comprising:a substrate;
a first metal layer, disposed on the substrate and having a first pinhole;
a second metal layer, disposed on the first metal layer and having a second pinhole;
a pixel electrode layer, disposed on the second metal layer; and
a light detecting element for detecting a light passing through the second pinhole and the first pinhole;
wherein a first edge of the first pinhole has a first slope, and a second edge of the second pinhole has a second slope, and the first slope and the second slope are different.

US Pat. No. 10,559,593

FIELD-EFFECT TRANSISTORS WITH A GROWN SILICON-GERMANIUM CHANNEL

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a first field-effect transistor including a first channel region arranged over a buried insulating layer of a silicon-on-insulator substrate and a first gate electrode arranged over the first channel region, the first channel region comprised of a first semiconductor material having a first germanium concentration;
a second field-effect transistor including a second channel region arranged over the buried insulating layer of the silicon-on-insulator substrate and a second gate electrode arranged over the second channel region, the second channel region comprised of a second semiconductor material having a second germanium concentration that is greater than the first germanium concentration in the first semiconductor material of the first channel region; and
a third field-effect transistor including a third channel region and a third gate electrode arranged over the third channel region, the third channel region comprised of a section of a device layer of the silicon-on-insulator substrate,
wherein the third channel region has a first thickness, and the second channel region has a second thickness that is greater than the first thickness of the third channel region.

US Pat. No. 10,559,590

THREE-DIMENSIONAL SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A three-dimensional semiconductor device, comprising:a semiconductor substrate, an underlying layer on the semiconductor substrate,
and a first structure on the underlying layer;
an opening penetrating at least the first structure;
an insulating spacer on an inner wall of the opening;
a recessed hole disposed at a lower end of the opening and exposing a portion of the semiconductor substrate and a portion of the underlying layer;
and
a semiconductor pattern covering the insulating spacer in the opening and being in direct contact with an inner wall of the recessed hole, wherein
a bottom surface of the insulating spacer is positioned at a vertical level between top and bottom surfaces of the underlying layer, and
the bottom surface of the insulating spacer is spaced apart from a top surface of the semiconductor substrate.

US Pat. No. 10,559,589

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a well plate;
a separation layer disposed on the well plate;
an auxiliary source line layer disposed on the separation layer and spaced apart from the well plate;
a stack structure formed on the auxiliary source line layer; and
channel layers configured to pass through the stack structure, and electrically coupled to the well plate and the auxiliary source line layer.

US Pat. No. 10,559,585

VERTICAL MEMORY DEVICES WITH CONDUCTIVE PADS SUPPORTED BY DUMMY CHANNELS WITH VARYING DIMENSIONS

SAMSUNG ELECTRONICS CO., ...

1. A vertical memory device, comprising:a conductive pattern structure on a substrate and comprising a stack of interleaved conductive patterns and insulation layers, wherein edges of the conductive patterns are disposed at spaced apart points along a first direction to provide conductive pads arranged as respective steps in a staircase arrangement;
a plurality of channel structures extending through the conductive pattern structure in a second direction perpendicular to the first direction;
a plurality of dummy channel structures extending through the conductive pads in the second direction; and
respective contact plugs on the conductive pads,
wherein a first one of the conductive pads has a first number of the dummy channel structures passing therethrough and wherein a second one of the conductive pads has a second number of the dummy channel structures passing therethrough that is different from the first number of the dummy channel structures;
wherein widths of the dummy channel structures passing through the conductive pads increase from an uppermost one of the steps toward a lowermost one of the steps and wherein a width of the dummy channel structures passing through a lowermost one of the conductive pads is less than a width of the dummy channel structures passing through a next lowermost one of the conductive pads, and
wherein a number of the dummy channel structures passing through the conductive pads decreases from the uppermost one of the conductive pads toward the lowermost one of the conductive pads and wherein a number of the dummy channel structures passing through the lowermost one of the conductive pads is greater than a number of the dummy channel structures passing through the next lowermost one of the conductive pads.

US Pat. No. 10,559,576

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR HAVING OFFSET INSULATING LAYERS

SK hynix Inc., Gyeonggi-...

1. A method of manufacturing a semiconductor device, the method comprising:forming a punch-through stop implantation portion by injecting first type impurities into a first portion of a substrate;
forming first trenches and second trenches at the same time, wherein bottoms of the first trenches are arranged on both sides of the punch-through stop implantation portion, wherein the bottoms of the first trenches and the punch-through stop implantation portion are aligned in a straight line, wherein the second trenches define an active region, and wherein the first trenches are provided between the second trenches;
forming offset insulating layers in the first trenches and isolation layers in the second trenches; and
forming a gate electrode in the active region between the offset insulating layers, wherein the gate electrode has edges overlapping with the offset insulating layers.

US Pat. No. 10,559,573

STATIC RANDOM ACCESS MEMORY STRUCTURE

UNITED MICROELECTRONICS C...

1. A static random access memory (SRAM) structure, comprising:a substrate;
a first inverter comprising a first pull-up transistor (PL1) and a first pull-down transistor (PD1) disposed on the substrate;
a second inverter comprising a second (PL2) and a second pull-down transistor (PD2) on the substrate, wherein the first inverter and the second inverter are cross-coupled to each other;
a first pass gate transistor (PG1A) and a second pass gate transistor (PG1B) electrically connected to an output terminal of the first inverter, a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B) electrically connected to an output terminal of the second inverter, wherein a gate of the PG1A and a gate of the PG2A electrically connected to a first word line, a gate of the PG1B and a gate of the PG2B electrically connected to a second word line;
a plurality of transistors including the PL1, the PL2, the PD1, the PD2, the PG1A, the PG1B, the PG2A and the PG2B, each transistor comprises a gate structure crosses over a fin structure, wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure;
a first local interconnection layer disposed between the PG1A and the PG1B, and disposed on the first fin structure of the PG1A, the first fin structure of the PG1B, the fin structure of the PL1 and the fin structure of the PD1, wherein the first local interconnection layer simultaneously contacts the first fin structure of the PG1A, the first fin structure of the PG1B, the fin structure of the PL1 and the fin structure of the PD1 directly; and
a second local interconnection layer disposed between the PG2A and the PG2B, and disposed on the second fin structure of the PG2A, the second fin structure of the PG2B, the fin structures of the PL2 and the fin structure of the PD2.

US Pat. No. 10,559,569

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A method for fabricating a semiconductor device, comprising:forming a transistor in a semiconductor substrate;
forming a capacitor including a hydrogen-containing top electrode, the hydrogen-containing top electrode being positioned over the transistor to overlap with the transistor; and
performing an annealing process for a hydrogen passivation after the capacitor is formed.

US Pat. No. 10,559,568

METHOD FOR PREPARING SEMICONDUCTOR CAPACITOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A method for preparing a semiconductor capacitor structure, comprising:providing a multi-layer structure comprising a plurality of first insulating layers and a plurality of conductive layers, wherein the first insulating layers and the conductive layers are alternately arranged;
patterning the multi-layer structure to form a plurality of columns, wherein the plurality of columns are separated from each other by a plurality of first trenches;
forming a supporting layer on sidewalls of each of the plurality of columns;
filling the plurality of first trenches with a second insulating layer;
removing portions of the second insulating layer and a portion of the supporting layer to form a plurality of second trenches exposing the plurality of first insulating layers and the plurality of conductive layers;
removing the plurality of first insulating layers and the second insulating layer to form a plurality of comb-like bottom electrode;
forming a dielectric layer to cover the plurality of comb-like bottom electrodes; and
forming a plurality of top electrodes on the dielectric layer.

US Pat. No. 10,559,567

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Sony Corporation, Tokyo ...

1. A semiconductor device comprising:an n-type transistor comprising, in a cross section:
(a) a first sidewall insulating film on a substrate,
(b) a first gate insulating film having side surfaces and a bottom surface, the side surfaces of the first gate insulating film connecting with the bottom surface of the first gate insulating film to define a first region, the first gate insulating film comprising a high dielectric constant material,
(c) a first metal gate electrode formed in the first region,
(d) first source/drain regions in the substrate,
(e) a first silicon nitride film formed at an outside of the first metal gate electrode, and
(f) a second silicon nitride film formed over the first metal gate electrode, a portion of the second silicon nitride film contacting with the first metal gate electrode;
a p-type transistor comprising, in the cross section:
(a) a second sidewall insulating film on the substrate,
(b) a second gate insulating film having side surfaces and a bottom surface, the side surfaces of the second gate insulating film connecting with the bottom surface of the second gate insulating film to define a second region, the second gate insulating film comprising the high dielectric constant material,
(c) a second metal gate electrode formed in the second region,
(d) second source/drain regions in the substrate,
(e) a third silicon nitride film formed at an outside of the second metal gate electrode, and
(f) a fourth silicon nitride film formed over the second metal gate electrode, a portion of the fourth silicon nitride film contacting with the second metal gate electrode.

US Pat. No. 10,559,562

INDIRECT READOUT FET

International Business Ma...

1. A metal-insulator-metal (MIM) capacitor structure comprising:source and drain regions formed within a semiconductor substrate;
a first conducting layer formed over the source and drain regions;
a dielectric layer formed over the first conducting layer;
a second conducting layer formed over the dielectric layer;
a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer;
wherein an electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

US Pat. No. 10,559,560

SEMICONDUCTOR ELECTROSTATIC DISCHARGE PROTECTION DEVICE

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor electrostatic discharge (ESD) protection device comprising:a substrate comprising a first conductivity type;
a gate disposed on the substrate;
a source region and a drain region disposed in the substrate, the source region and the drain region comprising a second conductivity type complementary to the first conductivity type;
a body region disposed in the substrate, the body region comprising the first conductivity type, wherein the drain region is formed between the gate and the body region; and
an isolation structure formed in the substrate, the body region being separated from the drain region by the isolation structure;
wherein the body region is electrically connected to the gate;
wherein the drain region is electrically connected to a first pad;
wherein the gate is electrically connected to the first pad through a capacitor; and
wherein the body region is electrically coupled to a line formed between the gate and the capacitor.

US Pat. No. 10,559,556

OPTOELECTRONIC SEMICONDUCTOR COMPONENT

OSRAM OPTO SEMICONDUCTORS...

1. Optoelectronic semiconductor device witha semiconductor body which comprises a semiconductor layer sequence with a p-type semiconductor region, an n-type semiconductor region and an active layer arranged between the p-type semiconductor region and the n-type semiconductor region,
a carrier, which comprises a plastics material and comprises a first through-via and a second through-via,
a p-connection layer and an n-connection layer, which are arranged at least in places between the carrier and the semiconductor body, wherein the p-connection layer connects the first through-via with the p-type semiconductor region and the n-connection layer connects the second through-via with the n-type semiconductor region,
an ESD protective element, which is arranged between the carrier and the semiconductor body, wherein the ESD protective element is electrically conductively connected with the first through-via and the second through-via, and wherein a conducting direction of the ESD protective element is antiparallel to a conducting direction of the semiconductor layer sequence, and wherein the ESD protective element directly adjoins the first through-via and the second through-via.

US Pat. No. 10,559,547

SEMICONDUCTOR CHIP

Murata Manufacturing Co.,...

1. A semiconductor chip comprising:a semiconductor substrate having a main surface;
a first electrode formed above the main surface of the semiconductor substrate;
a second electrode formed above the main surface of the semiconductor substrate;
a first insulating layer formed above a first portion of the first electrode;
a first bump that is formed above a second portion of the first electrode and above the first insulating layer, and that is electrically connected to the first electrode; and
a second bump formed above the second electrode, an area of the second bump being larger than an area of the first bump in a plan view of the main surface of the semiconductor substrate,
wherein a level on which the first bump is formed is higher than a level on which the second bump is formed.

US Pat. No. 10,559,544

SEMICONDUCTOR DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREFOR

Microsoft Technology Lice...

1. A package comprising:an integrated circuit embedded in an electrically non-conductive moulded material, the moulded material including at least one moulded groove pattern on at least one surface of the moulded material, and at least one electrically conductive track of conductive material disposed in the moulded groove pattern, wherein the at least one moulded groove pattern is positioned on an exterior surface of the moulded material and the moulded material is positioned between the integrated circuit and the at least one electrically conductive track of conductive material, wherein the integrated circuit is encapsulated within the moulded material, the moulded material is positioned between and in contact with both the at least one electrically conductive track of conductive material and the integrated circuit, and the at least one electrically conductive track of conductive material overlaps the integrated circuit in plan view.

US Pat. No. 10,559,543

SEMICONDUCTOR DEVICE HAVING A PROTECTION TRENCH, SEMICONDUCTOR WAFER INCLUDING THE SAME, AND SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate including a first region and a second region at least partially surrounding the first region in a plan view;
a protection pattern disposed on the second region of the substrate and at least partially surrounding the first region of the substrate in the plan view; and
a protection trench overlapping the protection pattern in a cross-sectional view and at least partially surrounding the first region of the substrate in the plan view, along the protection pattern,
wherein a width of the protection trench is different from a width of the protection pattern.

US Pat. No. 10,559,542

CHIP SECURITY FINGERPRINT

International Business Ma...

1. A method for fabricating a semiconductor chip structure, the method comprising:forming at least one back-end-of-line layer (BEOL) dielectric layer on a substrate, the substrate including semiconductor devices;
depositing a layer of block copolymers (BCPs) on the BEOL dielectric layer, annealing the BCPs to self-assemble into microdomains of individual BCPs with dimension and pitch based on molecular weight of the individual BCPs, and forming a self-assembled random pattern of BCPs with uniform dimension and pitch but with no specific orientation;
selectively removing one block from the layer of BCPs leaving voids in the remaining layer of BCPs and forming an etch template;
etching, using the etch template, the BEOL dielectric layer, the etching forming trenches in a random fingerprint pattern in a fingerprint region in the BEOL dielectric layer, the trenches in the random fingerprint pattern in the fingerprint region extending from a top surface of the BEOL dielectric layer to a bottom surface of the BEOL dielectric layer;
depositing conductive material in the trenches in the BEOL dielectric layer followed by a planarization process to remove overburden of conductive material deposited on the top surface of the BEOL dielectric layer, forming a random fingerprint pattern of conductive material in the fingerprint region in the BEOL dielectric layer, the conductive material in the random fingerprint pattern extending from the top surface of the BEOL dielectric layer to the bottom surface of the BEOL dielectric layer;
sandwiching the conductive material in the random fingerprint pattern in the fingerprint region between first and second sets of conductors in a crossbar pattern, the first set of conductors being electrically connected to a first set of electrical contacts in a first grid pattern disposed under, and contacting the bottom surface of, the BEOL dielectric layer, and the second set of conductors being electrically connected to a second set of electrical contacts in a second grid pattern disposed on, and contacting, the top surface of the BEOL dielectric layer, and wherein at an intersection of one of the first set of electrical contacts contacting the bottom surface and one of the second set of electrical contacts contacting the top surface, a presence of conductive material of the random fingerprint pattern in the BEOL dielectric layer indicating a first fingerprint pattern and a lack of conductive material indicating a second fingerprint pattern, different from the first fingerprint pattern.

US Pat. No. 10,559,537

WIRE BOND WIRES FOR INTERFERENCE SHIELDING

Invensas Corporation, Sa...

1. An apparatus comprising:a substrate having an upper surface and a lower surface opposite the upper surface and having bond pads on the upper surface;
a microelectronic device coupled to the upper surface of the substrate;
wire bond wires having ends bonded to the bond pads;
wherein the wire bond wires extend away from the upper surface of the substrate and are arranged in a preselected manner to shield from one or more frequencies of an interference generated by the microelectronic device;
wherein the wire bond wires are positioned alongside of at least one side of the microelectronic device to provide a shielding region with respect to the interference; and
a conductive surface positioned above the wire bond wires for covering at least a portion of the shielding region.

US Pat. No. 10,559,532

LAYOUT TECHNIQUES FOR HIGH-SPEED AND LOW-POWER SIGNAL PATHS IN INTEGRATED CIRCUITS WITH SMALL CHANNEL DEVICES

QUALCOMM Incorporated, S...

1. An integrated circuit (IC) comprising:a plurality of layers, wherein at least a portion of the plurality of layers is configured to form a power/ground grid having odd-numbered metal layers and even-numbered metal layers, wherein a majority of traces of the even-numbered metal layers have a first orientation, and wherein a majority of traces of at least one of the odd-numbered metal layers are oriented parallel to the majority of the traces of the even-numbered metal layers, wherein the odd-numbered metal layers comprise a first metal layer (M1), a third metal layer (M3), and a fifth metal layer (M5), wherein M1 is disposed beneath M3, wherein M3 is disposed beneath M5, and wherein the even-numbered metal layers comprise a second metal layer (M2) disposed between M1 and M3, a fourth metal layer (M4) disposed between M3 and M5, and a sixth metal layer (M6) disposed above M5; and
one or more circuit components configured to use high-speed, low-power signals carried by one or more of the plurality of layers.

US Pat. No. 10,559,531

INTEGRATED CIRCUIT STRUCTURES COMPRISING CONDUCTIVE VIAS AND METHODS OF FORMING CONDUCTIVE VIAS

Micron Technology, Inc., ...

1. A method of forming conductive vias, comprising:forming a first via opening and a second via opening within dielectric material, the first via opening having a smaller minimum open horizontal width than the second via opening, the first via opening extending elevationally inward to a first elevationally inner circuit component, the second via opening extending elevationally inward to a second elevationally inner circuit component;
forming first conductive material of a first conductivity into the first and second via openings and that electrically couples to the first and second elevationally inner circuit components, the first conductive material less-than-filling the first via opening, the first conductive material lining sidewalls and a base of the second via opening to less-than-fill the second via opening, the first conductive material extending outwardly of the first and second via openings elevationally over the dielectric material and electrically coupling the first and second elevationally inner circuit components together;
forming second conductive material into the second via opening and into the first via opening, the second conductive material being of a second conductivity that is greater than the first conductivity and overfilling volume of the second via opening remaining after the forming of the first conductive material, the second conductive material extending outwardly of the first and second via openings elevationally over and directly against the first conductive material and elevationally over the dielectric material;
removing all of the second conductive material from the first via opening;
removing the first and second conductive materials from being elevationally over the dielectric material and from electrically coupling the first and second elevationally inner circuit components together and forming a first conductive via in the first via opening and a second conductive via in the second via opening, all conductive material of the first conductive via defining a first maximum conductance elevationally through the first conductive via to the first elevationally inner circuit component, all conductive material of the second conductive via defining a second maximum conductance elevationally through the second conductive via to the second elevationally inner circuit component, said second maximum conductance being greater than said first maximum conductance; and
forming a first elevationally outer circuit component electrically coupled to the first conductive via and a second elevationally outer circuit component electrically coupled to the second conductive via.

US Pat. No. 10,559,529

PITCH DIVISION PATTERNING APPROACHES WITH INCREASED OVERLAY MARGIN FOR BACK END OF LINE (BEOL) INTERCONNECT FABRICATION AND STRUCTURES RESULTING THEREFROM

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a substrate; and
a plurality of alternating first and second conductive line types disposed along a same direction of a back end of line (BEOL) metallization layer disposed above the substrate, wherein a total composition of the first conductive line type is different from a total composition of the second conductive line type, and wherein a bottom surface of one of the first conductive line types is co-planar with a bottom surface of one of the second conductive line types.

US Pat. No. 10,559,522

INTEGRATED DIE PADDLE STRUCTURES FOR BOTTOM TERMINATED COMPONENTS

INTERNATIONAL BUSINESS MA...

1. A bottom terminated component comprising:a die paddle; and
at least one die paddle structure configured to prevent wicking into a respective thermal via of a printed circuit board, the at least one die paddle structure comprising:
a base defining an axis, the base having an axial thickness extending from the die paddle;
a contact surface configured to contact the printed circuit board at the thermal via of the printed circuit board to prevent wicking of solder into the respective thermal via; and
a positioning member tapered in an axial direction, the positioning member configured to enable positioning the bottom terminated component on a printed circuit the positioning member is, wherein the positioning member extends from the contact surface in an axial direction away from the base.

US Pat. No. 10,559,520

BULK LAYER TRANSFER PROCESSING WITH BACKSIDE SILICIDATION

QUALCOMM Incorporated, S...

1. A radio frequency integrated circuit (RFIC), comprising:a bulk semiconductor die comprising a first active/passive device on a first-side of the bulk semiconductor die;
a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die;
a contact layer on the second-side of the bulk semiconductor die;
a first-side dielectric layer on the first active/passive device;
a second-side dielectric layer on the contact layer, in which the first deep trench isolation region extends through the contact layer and into the second-side dielectric layer, the second-side dielectric layer being distal from the first-side dielectric layer;
a trench interconnect extending from the first-side dielectric layer through the first deep trench isolation region and extending into the second-side dielectric layer;
a first-side metallization layer in the first-side dielectric layer and coupled to the trench interconnect; and
a second-side metallization layer in the second-side dielectric layer and coupled to the trench interconnect, the second-side metallization layer being distal from the first-side metallization layer.

US Pat. No. 10,559,515

ELECTRONIC DEVICE

FUJITSU LIMITED, Kawasak...

1. An electronic device comprising:a first electronic component;
a substrate on which the first electronic component is mounted, which includes an additional region formed on one side of the first electronic component in a first direction, which is a perpendicular direction to an insertion direction of the first electronic component, to add a second electronic component, and onto which cooling air flows; and
a wall member which surrounds the additional region and includes a front wall portion, which extends in the first direction and is perpendicular to a surface of the substrate, a rear wall portion, which extends in the first direction, is perpendicular to the surface of the substrate and is parallel to the front wall portion on the other side of the additional region, and a side wall portion, which extends in the insertion direction perpendicular to the first direction, is perpendicular to the surface of the substrate and is coupled to a side of the front wall portion and a side of the rear wall portion,
the side wall portion is arranged along a side wall of the first electronic component, each of the front wall portion and the rear wall portion of the wall member includes an opening for allowing the air to flow over the additional region and the side wall portion of the wall member includes no opening.

US Pat. No. 10,559,512

CIRCUIT PACKAGE

HEWLETT-PACKARD DEVELOPME...

1. A method of molding a circuit, comprising:depositing a first epoxy mold compound (EMC) over a cavity;
upon the first EMC gelling over a predetermined period of time, depositing a second EMC over the first EMC, wherein the second EMC has a higher thermal conductivity than the first EMC; and
depositing a circuit in at least one of the first and second EMCs.

US Pat. No. 10,559,507

DIRECT WAFER MAPPING AND SELECTIVE ELASTOMER DEPOSITION

Facebook Technologies, LL...

1. A method, comprising:applying a voltage difference across electrodes of each of a plurality of light emitting diodes (LEDs);
measuring at least one parameter associated with each of the plurality of LEDs to determine whether each of the plurality of LEDs is operational;
selectively depositing an elastomer coating on a top surface of each of the plurality of LEDs determined to be operational.

US Pat. No. 10,559,506

METHOD OF INSPECTING SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A method of inspecting a semiconductor device, the method comprising:setting at least one target place on a wafer, the target place including at least one deep trench;
forming a first cut surface by performing first milling on the target place in a first direction;
obtaining first image data of the first cut surface;
forming a second cut surface by performing second milling on the target place in a second direction opposite to the first direction;
obtaining second image data of the second cut surface;
obtaining a plurality of first critical dimension (CD) values for the deep trench from the first image data;
obtaining a plurality of second CD values for the deep trench from the second image data;
analyzing a degree of bending of the deep trench based on the plurality of first CD values and the plurality of second CD values; and
providing the semiconductor device meeting a condition based on results of the analyzing.

US Pat. No. 10,559,503

METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE

GLOBALFOUNDRIES INC., Gr...

1. A finFET device, comprising:a first gate structure and a second gate structure on a semiconductor substrate;
a first active area contacting a first end of said first gate structure and contacting a first end of said second gate structure;
a second active area contacting a second end of said first gate structure and contacting a second end of said second gate structure; and
a self-aligned trench silicide (TS) structure configured to operatively couple said first active area to said second active area, wherein said TS structure is flush in height with said first gate structure and said second gate structure.

US Pat. No. 10,559,497

SEAMLESS TUNGSTEN FILL BY TUNGSTEN OXIDATION-REDUCTION

Applied Materials, Inc., ...

1. A method of substrate processing comprising:providing a substrate with a first substrate surface of a first material and a second substrate surface of a second material, the substrate having at least one feature with a sidewall and a bottom, the sidewall formed by the first substrate surface and the bottom formed by the second substrate surface;
forming a tungsten film on the substrate, the tungsten film having a seam formed within the feature and an overburden formed on the first substrate surface outside the feature;
planarizing the substrate to remove the overburden from the first substrate surface so that a top of the tungsten film is about coplanar with the first substrate surface outside the feature;
oxidizing the tungsten film to form a tungsten oxide pillar which extends from the at least one feature without a seam;
reducing the tungsten oxide pillar to tungsten, the tungsten forming a substantially seamless tungsten gapfill within the at least one feature so that a top of the tungsten gapfill is below the first surface outside of the feature; and
selectively depositing additional tungsten on the tungsten gapfill to raise the top of the tungsten gapfill to be substantially coplanar with the first substrate surface outside of the feature, selectively depositing additional tungsten comprises depositing a silicon film on the tungsten gapfill and exposing the silicon film to a tungsten halide to convert the silicon film to tungsten.

US Pat. No. 10,559,496

TECHNIQUES FOR FILLING A STRUCTURE USING SELECTIVE SURFACE MODIFICATION

APPLIED MATERIALS, INC., ...

1. A method of device processing, comprising:providing a cavity in a layer;
directing energetic flux to a bottom surface of the cavity, the cavity having a sidewall oriented perpendicularly to the bottom surface, wherein the energetic flux is oriented parallel to the sidewall and does not strike the sidewall of the cavity;
performing an exposure of the cavity to a moisture-containing ambient; and
introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material forms in layers parallel to the bottom surface, while formation of fill material on the sidewall is suppressed.

US Pat. No. 10,559,495

METHODS FOR PROCESSING SEMICONDUCTOR DICE AND FABRICATING ASSEMBLIES INCORPORATING SAME

Micron Technology, Inc., ...

11. A method for fabricating a reconstituted wafer, the method comprising:forming a film comprising a metal material on a surface of a semiconductor wafer;
securing semiconductor dice to the film in an array of mutually spaced locations;
covering backs and sides of the semiconductor dice with a dielectric molding material; and
removing material from an opposing surface of the semiconductor wafer to expose the film.

US Pat. No. 10,559,487

WAFER DIVIDING METHOD AND DIVIDING APPARATUS

DISCO CORPORATION, Tokyo...

1. A wafer dividing method using a dividing apparatus, the dividing apparatus including a table adapted to suction hold a wafer through a heat-shrinkable tape of a work set, the work set having the tape attached to a ring frame to close an opening of the ring frame, the wafer being formed with division starting points along division lines and attached to the tape at the opening; a ring frame holding section adapted to hold the ring frame of the work set; a lifting unit adapted to relatively move the table and the ring frame holding section in a vertical direction for bringing them closer to and away from each other; and a heater adapted to heat the tape in a ring shape between an outer periphery of the wafer and an inner periphery of the ring frame of the work set, the table and the ring frame holding section being relatively moved respectively in an upward direction and a downward direction such as to be spaced away from each other by the lifting unit, in a state in which the work set is held by the ring frame holding section, to expand the tape at the opening and thereby to divide the wafer at the division starting points into chips, the water dividing method comprising:a holding step of holding the work set by the ring frame holding section;
a dividing step of relatively moving the table and the ring frame holding section away from each other by the lifting unit to expand the tape, and dividing the wafer at the division starting points to form a predetermined gap between the adjacent chips, after the holding step;
a tape holding step of suction holding that area of the expanded tape to which the wafer is adhered by the table, after the dividing step;
a ring tape expanding step of relatively moving the table and the ring frame holding section further away from each other, to expand the ring-shaped tape between the outer periphery of the wafer and the inner periphery of the ring frame, after the tape holding step; and
a fixing step of relatively moving the table and the ring frame holding section closer to each other by the lifting unit to slacken the ring-shaped tape and heating the ring-shaped tape by the heater, to heat shrink the ring-shaped tape and to fix the work set while maintaining the predetermined gap between the adjacent chips, after the ring tape expanding step.

US Pat. No. 10,559,482

HEAT TREATMENT METHOD OF LIGHT IRRADIATION TYPE

SCREEN HOLDINGS CO., LTD....

1. A heat treatment method for irradiating a substrate held on a quartz susceptor provided in a chamber with light from a continuous lighting lamp provided outside said chamber to heat the substrate, the heat treatment method comprising the steps of:(a) keeping temperature of a quartz window provided in said chamber by light irradiation from said continuous lighting lamp;
(b) holding an object to be heated that absorbs infrared light to increase in temperature on said susceptor before a substrate to be treated is transferred into said chamber so that said object to be heated is heated by light irradiation from said continuous lighting lamp to preliminary heat said susceptor; and
(c) holding said substrate on said susceptor after said step (b) so that said substrate is heated by light irradiation from said continuous lighting lamp, wherein
when temperature of each of said quartz window and said susceptor increases to be constant by continuously irradiating a plurality of substrates of one lot with light to heat the substrates without heating said quartz window and said susceptor, the temperature of said quartz window and the temperature of the susceptor are indicated as a first stable temperature and a second stable temperature, respectively,
said quartz window is heated so that the temperature of said quartz window is maintained at said first stable temperature in said step (a), and
said susceptor is heated so that the temperature of said susceptor reaches said second stable temperature in said step (b).

US Pat. No. 10,559,473

SEMICONDUCTOR PROCESS FOR IMPROVING LOADING EFFECT IN PLANARIZATION

UNITED MICROELECTRONICS C...

1. A semiconductor process for improving loading effects in planarization, comprising:providing a substrate with a first region and a second region;
forming multiple first protruding patterns on said first region and said second region of said substrate, wherein a density of said first protruding pattern in said first region is larger than a density of said first protruding pattern in said second region;
forming a first dielectric layer on said substrate and said first protruding patterns, wherein said first dielectric layer is provided with multiple second protruding patterns corresponding to underlying said first protruding patterns;
forming a second dielectric layer on said first dielectric layer;
performing a first planarization process to remove a portion of said second dielectric layer and expose top surfaces of said second protruding patterns;
performing an etch process to remove said second protruding patterns of said first dielectric layer;
removing remaining said second dielectric layer; and
performing a second planarization process to said first dielectric layer.

US Pat. No. 10,559,470

CAPPING STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:a plurality of gate structures in a first location with a first density;
a plurality of gate structures in a second location with a second density different than the first density; and
a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location,
wherein the plurality of gate structures in the first location are short gate structures and the plurality of gate structures in the second location are long gate structure and both the long gate structures and the short gate structure are replacement gate structures.

US Pat. No. 10,559,467

SELECTIVE GAS ETCHING FOR SELF-ALIGNED PATTERN TRANSFER

INTERNATIONAL BUSINESS MA...

1. A method for selective gas etching for self-aligned pattern transfer, the method comprising:forming a first block in a common sacrificial layer, the first block comprising a first hardmask material that can be plasma etched using a first gas; and
forming a second block separate from the first block in the common sacrificial layer, the second block comprising a second hardmask material that can be plasma etched using a second gas separate from the first gas;
wherein the first hardmask material is not plasma etched using the second gas, the second hardmask material is not plasma etched using the first gas and the first hard mask and second hardmask cover distinct locations within a given thickness of the common sacrificial layer.

US Pat. No. 10,559,466

METHODS OF FORMING A CHANNEL REGION OF A TRANSISTOR AND METHODS USED IN FORMING A MEMORY ARRAY

Micron Technology, Inc., ...

1. A method of forming a channel region of a transistor, comprising:forming amorphous channel material over a substrate, the amorphous channel material having first and second opposing sides;
forming an insulator material adjacent the second side of the amorphous channel material below a crystallization temperature at and above which the amorphous channel material would become crystalline; and
subjecting the amorphous channel material having the insulator material there-adjacent to a temperature at or above the crystallization temperature to transform the amorphous channel material into crystalline channel material; and
the insulator material being formed directly against the second side of the amorphous channel material.

US Pat. No. 10,559,464

METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE

Canon Kabushiki Kaisha, ...

1. A method for manufacturing a photoelectric conversion device comprising:fixing a first substrate which includes a first semiconductor layer including a photoelectric conversion element, to a second substrate;
thinning the first semiconductor layer after fixing the first substrate to the second substrate;
forming a through hole in the first semiconductor layer after the thinning of the first semiconductor layer;
forming a conductive member in the through hole; and
fixing the first substrate to a third substrate which includes a second semiconductor layer provided with a first transistor such that the first substrate is located between the third substrate and the second substrate after the forming of the conductive member;
wherein, in the step of fixing the first substrate to the second substrate, the first substrate is provided with a second transistor;
wherein the conductive member electrically between the first transistor and the second transistor.

US Pat. No. 10,559,457

MASS SPECTROMETER, SYSTEM COMPRISING THE SAME, AND METHODS FOR DETERMINING ISOTOPIC ANATOMY OF COMPOUNDS

CALIFORNIA INSTITUTE OF T...

1. A method for determining the isotopic composition of an analyte in a sample, the method comprising:using a first mass spectrometer comprising a single-collector and having a mass-resolution of about 30,000 or greater to measure ratios of ion beams at each cardinal mass of the analyte to produce first molecular analyte ion data;
using a second mass spectrometer comprising a multi-collector to measure relative abundances of closely-adjacent ions at different cardinal masses of the analyte to produce second molecular analyte ion data;
utilizing the first molecular analyte ion data to identify proportions of isotopologues that contribute to signal intensity at each cardinal mass measured with the second mass spectrometer; and
utilizing the proportions of the isotopologues that contribute to the signal intensity at each cardinal mass to compensate for unresolved detected molecular analyte species and calculate an abundance of one or more isotopic species of interest measured with the second mass spectrometer.

US Pat. No. 10,559,455

MASS SPECTROMETRY PROBES AND SYSTEMS FOR IONIZING A SAMPLE

Purdue Research Foundatio...

1. A method for analyzing a sample, the method comprising:providing a mass spectrometry probe comprising a paper substrate in which a portion of the paper substrate is coated with an electrically conductive material that is not a sample or a solvent, in a manner that a plurality of nanoscale features protrude from the paper substrate, the plurality of nanoscale features configured to act as a plurality of electrodes and upon application of a voltage of 3 volts or less, providing a field strength high enough to cause field emission of microscale solution droplets at the plurality of nanoscale features at a voltage that does not cause fragmentation of the analyte;
connecting the mass spectrometry probe to a voltage source, wherein the voltage source is configured to generate a voltage of 3 volts or less;
contacting the mass spectrometry probe with a sample;
ionizing the sample that has contacted the mass spectrometry probe; and
analyzing the ionized sample in a mass spectrometer.

US Pat. No. 10,559,452

PLASMA DEVICE DRIVEN BY MULTIPLE-PHASE ALTERNATING OR PULSED ELECTRICAL CURRENT

AGC FLAT GLASS NORTH AMER...

1. A plasma source comprising:at least three electrodes, including a first electrode, a second electrode, and a third electrode, the at least three electrodes being arranged linearly such that a first distance between the first electrode and the second electrode is smaller than a second distance between the first electrode and the third electrode; and
a source of power capable of producing multiple output waves, including a first output wave, a second output wave, and a third output wave, wherein the first output wave and the second output wave are out of phase, the second output wave and the third output wave are out of phase, and the first output wave and the third output wave are out of phase;
wherein each electrode is electrically connected to the source of power such that the first electrode is electrically connected to the first output wave, the second electrode is electrically connected to the second output wave, and the third electrode is electrically connected to the third output wave;
wherein electrical current flows between the at least three electrodes that are out of electrical phase;
wherein each electrode alternately serves as anode and cathode when powered by the multiple output waves, and
wherein the plasma source is capable of generating a plasma between the electrodes, including a first plasma directly between the first electrode and the second electrode, a second plasma directly between the second electrode and the third electrode, and a third plasma directly between the first electrode and the third electrode.

US Pat. No. 10,559,448

TRANSMISSION CHARGED PARTICLE MICROSCOPE WITH IMPROVED EELS/EFTEM MODULE

FEI Company, Hillsboro, ...

1. A method of using a Transmission Charged Particle Microscope comprising:n imaging system, for receiving a flux of charged particles transmitted through a specimen and directing the flux of charged particles after passing through the specimen onto a sensing device;
a controller, for controlling at least some operational aspects of the microscope,in which method the sensing device is chosen to be an EELS/EFTEM module comprising:an entrance plane;
an image plane, where in EELS mode an EELS spectrum is formed and in EFTEM mode an EFTEM image is formed;
a slit plane between said entrance plane and said image plane, where in EFTEM mode an energy dispersed focus is formed;
a dispersing device, between said entrance plane and said slit plane, for dispersing an incoming charged particle beam into an energy-dispersed beam with an associated dispersion direction;
a first series of quadrupoles between said dispersing device and slit plane;
a second series of quadrupoles between said slit plane and image plane,which dispersing device and quadrupoles are arranged along an optical axis,whereby, for a Cartesian coordinate system (X,Y,Z) in which said optical axis is disposed along Z, said dispersion direction is defined as being parallel to X,wherein:in said first quadrupole series, exciting one or more quadrupoles so as to deflect an off-axis non-dispersive YZ ray leaving said dispersing device onto a path paraxial to said optical axis from said slit plane to said image plane; and
in said second quadrupole series, exciting either:
(a) a single quadrupole; or
(b) a pair of adjacent quadrupoles,
so as to focus said energy-dispersed beam onto said image plane.

US Pat. No. 10,559,438

TOGGLE SWITCH ACTUATING MECHANISM

Honeywell International I...

1. A toggle switch comprising:a housing;
a plurality of switches disposed within the housing;
an actuating lever coupled to a pivot pin, wherein the actuating lever extends into the housing; and
an actuator assembly coupled to the actuating lever, the actuator assembly comprising:
an actuation pin coupled to the actuating lever, wherein the actuation pin is configured to actuate one or more of the plurality of switches, and
a spring disposed about an outer surface of the actuating lever, wherein the spring is configured to bias a cam follower into engagement with a cam profile on a bracket, and bias the actuating lever into an actuation position,
wherein the cam follower comprises a roller disposed about a pin, wherein the pin is configured to travel within a longitudinal travel slot disposed in the actuating lever.

US Pat. No. 10,559,435

SWITCH

Omron Corporation, Kyoto...

1. A switch, comprising:a housing including an internal compartment;
a stationary contact terminal extending from outside the housing to the compartment and fixed to the housing, and including a fixed portion housed in the compartment;
a moving contact terminal extending from outside the housing to the compartment, and being parallel to the stationary contact terminal, the moving contact terminal being fixed to the housing in a manner electrically independent of the stationary contact terminal;
a moving contact unit housed in the compartment, and including a body connected to the moving contact terminal and extending from the moving contact terminal toward the stationary contact terminal, a moving portion included in the body and facing the fixed portion and being movable toward and away from the fixed portion, and an urging member included in the body and being configured to urge the moving portion in an urging direction switchable between a closing direction for moving the moving portion toward the fixed portion and a separating direction for moving the moving portion away from the fixed portion;
an operating unit at least partly exposed outside the housing, and at least partly housed in the compartment to come in contact with and reciprocate with respect to the moving contact unit, the operating unit being configured to switch the urging direction in accordance with reciprocation of the operating unit to move the moving portion toward or away from the fixed portion;
a first elastic unit fixed to the housing, and configured to come in contact with the moving contact unit and elastically deform in the separating direction when the moving portion moves away from the fixed portion under an urging force of the urging member;
a second elastic unit including a contact point located between the moving portion and the fixed portion facing the moving portion in the closing direction and being configured to come in contact with the moving portion, the second elastic unit being fixed to the stationary contact terminal or the moving contact terminal and being configured to elastically deform in the closing direction and electrically connect the stationary contact terminal and the moving contact terminal when the moving portion moves toward the fixed portion under the urging force of the urging member and comes in contact with the contact point, and
a third elastic unit located near the second elastic unit in the compartment, the third elastic unit including an elastic protrusion located between the fixed portion and the contact point in the closing direction and being configured to come in contact with the contact point, and an elastic arm located between the moving portion and the contact point in the closing direction and being configured to come in contact with the moving portion.

US Pat. No. 10,559,434

CONTROL CIRCUIT FOR ELECTRIC LEAKAGE CIRCUIT BREAKER

LSIS CO., LTD., Anyang-s...

1. A control circuit for an electric leakage circuit breaker, comprising:a zero phase current transformer configured to detect a zero phase current on a circuit as a leakage detection signal;
a filter circuit section configured to remove a high frequency noise included in the leakage detection signal;
an input amplifier configured to amplify a voltage formed by a current of the leakage detection signal and an impedance of the filter circuit section, and including a pair of transistors, bases of the transistors connected to both output terminals of the filter circuit section, respectively;
a base current generator commonly connected to the bases of the pair of transistors and configured to supply the same amount of base current to the pair of transistors;
a trip determination circuit section configured to determine whether to output a trip control signal by comparing a voltage value of an amplified leakage detection signal outputted from the input amplifier with a preset reference voltage value, and
a gain adjuster, connected to the base current generator, configured to adjust the gain of a collector current of the pair of transistors over the base current by adjusting the base current supplied to the bases of the pair of transistors.

US Pat. No. 10,559,433

SWITCHING APPARATUS FOR SYNCHRONIZED TOGGLE POSITIONING AND RELATED SENSORY FEEDBACK

SWITCHDOWN LLC, Durham, ...

9. A system of controlling energization of an electrical load using multiple switch devices, said system comprising:a plurality of switch devices, each said switch device including
a toggle element movable between a first position and a second position, said toggle element including a magnetic element affixed thereto;
an electromagnetic element being selectively energized and fixed in position relative to said toggle element;
a sensor creating a signal indicative of said toggle element passing a position midway between said first position and said second position;
a communications wire for distributing said signal among said plurality of switches; and
a microprocessor controlling said electromagnetic element to selectively attract or repel each said magnetic element in each of said plurality of switches simultaneously in response to said signal thereby creating sensory feedback to a user of said system;
wherein said plurality of switches are connected via said communications wire.

US Pat. No. 10,559,432

ELECTROLYTIC CAPACITOR AND MANUFACTURING METHOD THEREFOR

Panasonic Intellectual Pr...

1. An electrolytic capacitor comprising a capacitor element, the capacitor element having:an anode member having a dielectric layer thereon; and
a cathode member including a conductive polymer layer that is in direct contact with the dielectric layer,
wherein the capacitor element is impregnated with a liquid containing at least one of polyalkylene glycol and derivatives selected from a group consisting of polyethylene glycol glyceryl ether, polyethylene glycol diglyceryl ether, polyethylene glycol sorbitol ether, polypropylene glycol glyceryl ether, polypropylene glycol diglyceryl ether, polypropylene glycol sorbitol ether, copolymers of ethylene glycol and propylene glycol, copolymers of ethylene glycol and butylene glycol, and copolymers of propylene glycol and butylene glycol.

US Pat. No. 10,559,431

HIGH VOLTAGE WINDOW ELECTROLYTE FOR SUPERCAPACITORS

UT-BATTELLE, LLC, Oak Ri...

1. A supercapacitor, comprising:a negative electrode comprising carbon black and sodium carboxymethyl cellulose which does not intercalate sodium;
a positive carbon-comprising electrode;
an electrolyte composition comprising sodium hexafluorophosphate and a non-aqueous solvent comprising at least one selected from the group consisting of ethylene glycol dimethyl ether, diethylene glycol dimethyl ether, triethylene glycol dimethyl ether, and tetraethylene glycol dimethyl ether;
wherein the supercapacitor has an electrochemical voltage window of from +0.0 V to 3.5 V (full cell voltage).

US Pat. No. 10,559,426

ELECTRONIC DEVICE HAVING CERAMIC ELEMENT BODY AND EXTERNAL TERMINAL

TDK CORPORATION, Tokyo (...

1. An electronic device, comprising:a chip component including a terminal electrode formed on an end surface of a ceramic element body containing an internal electrode; and
an external terminal including a first end electrically connected with the terminal electrode and a second end disposed opposite to the first end and connected with a mounting surface,
wherein:
the external terminal comprises:
a first metal; and
a second metal different from the first metal;
the first metal and the second metal are arranged next to each other in a surface direction of the external terminal and alternately exposed on a surface of the external terminal; and
a width of the second metal exposed to the surface of the external terminal is 1/10 to 9/10 of the width of the terminal electrode.

US Pat. No. 10,559,424

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor:a capacitor body having first and second surfaces opposing each other and third and fourth surfaces connected to the first and second surfaces and opposing each other, and including an active region including dielectric layers and pluralities of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween and first and second cover regions disposed on opposite surfaces of the active region, the first and second internal electrodes being exposed through the third and fourth surfaces, respectively;
third and fourth internal electrodes alternately disposed in the first cover region adjacent to the first surface with respective dielectric layers interposed therebetween;
first and second external electrodes including first and second connected portions respectively formed on the third and fourth surfaces of the capacitor body and respectively connected to the first and second internal electrodes, and first and second band portions respectively extending from the first and second connected portions to portions of the first surface of the capacitor body;
a first via electrode penetrating through the first cover region to connect the third internal electrode and the first band portion to each other; and
a second via electrode penetrating through the first cover region to connect the fourth internal electrode and the second band portion to each other,
wherein the first surface is a mounting surface,
the third internal electrode contacts only the first via electrode, from among the first and second via electrodes and first and second external electrodes, and
the fourth internal electrode contacts only the second via electrode, from among the first and second via electrodes and first and second external electrodes.

US Pat. No. 10,559,423

MULTILAYER CERAMIC ELECTRONIC DEVICE

TDK CORPORATION, Tokyo (...

7. A multilayer ceramic electronic device comprising a laminated body having alternately laminated internal electrode layers and dielectric layers, whereineach of the dielectric layers has a thickness of 0.5 ?m or less,
each of the internal electrode layers contains ceramic particles,
a content ratio of the ceramic particles contained in the each of the internal electrode layers is 2 to 15% by representation of cross sectional area, and
the each of the dielectric layers has a thickness standard deviation (?) of 100 nm or less.

US Pat. No. 10,559,422

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME USING TREATMENT WITH NITROGEN AND HYDROGEN

SK hynix Inc., Icheon-si...

1. A method for fabricating an electronic device including a semiconductor memory, comprising:forming a variable resistance element over a substrate, the variable resistance element including a metal-containing layer and an MTJ (Magnetic Tunnel Junction) structure which is located over the metal-containing layer and includes a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer;
forming an initial spacer containing a metal over the variable resistance element;
performing an oxidation process to transform the initial spacer into a middle spacer including an insulating metal oxide; and
performing a treatment using a gas or plasma including nitrogen and hydrogen to transform the middle spacer produced by the oxidation process into a final spacer including an insulating metal nitride or an insulating metal oxynitride.

US Pat. No. 10,559,421

STEP-UP BIPOLAR TRANSFORMER RECTIFIER WITHOUT COMMON MODE RIPPLE

The Boeing Company, Chic...

1. A multi-phase transformer comprising:a single rectifier; and
a plurality of groups of windings connected to the single rectifier, wherein each one of the groups of windings comprises:
a corresponding plurality of primary windings having a first output voltage;
a corresponding plurality of secondary windings joined in series to the corresponding plurality of primary windings and having a second output voltage; and
a corresponding plurality of tertiary windings joined in series to the corresponding plurality of secondary windings and having a third output voltage that is higher than the second output voltage;
wherein each end of a primary winding of the corresponding plurality of primary windings is coupled to an end of another primary winding to form a delta configuration and a junction at each coupling that interconnects at least one secondary winding of the corresponding plurality of secondary windings.