US Pat. No. 10,483,431

LIGHT SOURCE MODULE AND DISPLAY DEVICE

InnoLux Corporation, Mia...

1. A light source module, comprising:a quantum dot cell, comprising:
a first glass substrate;
a second glass substrate disposed corresponding to the first glass substrate, the second glass substrate having a light-emitting surface disposed at a side of the second glass substrate opposite to the first glass substrate;
a quantum dot region disposed between the first glass substrate and the second glass substrate, wherein a quantum dot material is disposed in the quantum dot region; and
a reflective sealant disposed between the first glass substrate and the second glass substrate and surrounding the quantum dot region, a reflectivity of the reflective sealant ranging from 30% to 100%;
a light emitting element disposed at a side of the first glass substrate opposite to the quantum dot region, wherein the light emitting element emits a light with a first wavelength range, the light enters the quantum dot region, and the quantum dot material converts the light with the first wavelength range into a light with a second wavelength range; and
an adhesive layer disposed at an outer side of the light emitting element for attaching the light emitting element to a surface of the first glass substrate, wherein the adhesive layer is disposed between the light emitting element and the first glass substrate in a direction parallel to a thickness direction of the first glass substrate.

US Pat. No. 10,483,430

MICRON-SIZED LIGHT EMITTING DIODE DESIGNS

Facebook Technologies, LL...

1. A light emitting diode (LED), comprising:an epitaxial structure defining:
a base defining a light emitting surface of the LED, the base including a current spreading layer with a first-type doping; and
a mesa on the base, the mesa including:
a first confinement layer with the first-type doping,
a light generation area on the first confinement layer to emit light,
a second confinement layer on the light generation area with a second-type doping opposite the first-type doping, and
a contact layer with the second-type doping on the second confinement layer, the contact layer defining a top of the mesa, the second confinement layer and the contact layer being thinner than the first confinement layer; and
a reflective contact on the contact layer to reflect a portion of the light emitted from the light generation area to the light emitting surface.

US Pat. No. 10,483,429

METHOD OF MANUFACTURING SOLAR CELL

Panasonic Intellectual Pr...

1. A method of manufacturing a solar cell comprising:providing an insulating layer on a semiconductor layer provided on at least a part of a principle surface of a semiconductor substrate;
providing a first mask layer on the insulating layer;
removing a part of the first mask layer by a first laser irradiation so as to form a first opening;
removing, by a first etching agent, the insulating layer exposed through the first opening so as to form a second opening through which the semiconductor layer is exposed;
removing, by a second etching agent, the semiconductor layer exposed through the second opening so as to form a third opening through which the semiconductor substrate is exposed;
removing the first mask layer by a third etching agent;
providing a second mask layer on the semiconductor substrate exposed through the third opening and on the insulating layer;
removing a part of the second mask layer located on the insulating layer by a second laser irradiation so as to form a fourth opening through which the insulating layer is exposed; and
removing, by a fourth etching agent, the insulating layer exposed through the fourth opening so as to form a fifth opening through which the semiconductor layer is exposed.

US Pat. No. 10,483,426

PHOTO CELL DEVICES FOR PHASE-SENSITIVE DETECTION OF LIGHT SIGNALS

Infineon Technologies AG,...

1. A method comprising:providing a first vertical trench in a substrate; and
providing a second vertical trench in the substrate laterally disposed from the first vertical trench, wherein a horizontal extent of the first and second vertical trenches extend in a first direction such that the first and second vertical trenches run in the first direction parallel to one another;
providing a third vertical trench in the substrate;
providing a fourth vertical trench in the substrate laterally disposed from the third vertical trench, wherein a horizontal extent of the third and fourth vertical trenches extend in a second direction generally perpendicular to the first direction, such that the third and fourth vertical trenches run in the second direction parallel to one another,
wherein the first vertical trench, the second vertical trench, the third vertical trench and the fourth vertical trench collectively substantially enclose and thus define a square region of the substrate therebetween;
alternately depleting a first region of the substrate surrounding the first vertical trench and a second region of the substrate surrounding the second vertical trench by alternately applying a voltage to a first vertical trench gate contact and a second vertical trench gate contact, and
alternately depleting a third region of the substrate surrounding the third vertical trench and a fourth region of the substrate surrounding the fourth vertical trench by alternately applying a voltage to a third vertical trench gate contact and a fourth vertical trench gate contact,
wherein the alternate depleting of the first, second, third and fourth regions comprising an interleaved biasing resulting in biasing of the various trenches serially in a circular fashion,
wherein a lateral distance separating the first vertical trench and the second vertical trench is related to a doping level of the substrate such that upon operation a biasing of one of the first vertical trench, the second vertical trench, the third vertical trench and the fourth vertical trench results in formation of a fully depleted gap in a region centrally located between the first vertical trench, the second vertical trench, the third vertical trench, and the fourth vertical trench.

US Pat. No. 10,483,425

OPTICAL SEMICONDUCTOR COMPONENT PACKAGE AND OPTICAL SEMICONDUCTOR DEVICE

Kyocera Corporation, Kyo...

1. An optical semiconductor component package, comprising:a plate-like base having a first surface including a mount area in which an optical semiconductor component is mountable;
a frame located on the first surface and surrounding the mount area;
a plate-like lid bonded to the frame and covering the mount area; and
a light absorbing member located on a second surface of the lid facing the mount area, the light absorbing member having a plurality of recesses on a surface thereof.

US Pat. No. 10,483,422

PHOTOVOLTAIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOYOTA JIDOSHA KABUSHIKI ...

1. A photovoltaic device comprising:a light absorbing layer, consisting of:
a plurality of first layers made of a first semiconducting material of GaAs; and
a plurality of second layers made of a second semiconducting material of GaNxAs1-xwherein 0.003?x?0.4,
wherein
the first layers and second layers are alternately arranged,
N atoms of the second layers adjacent to each other across an intermediate first layer in a thickness direction of the light absorbing layer are substantially equidistant from one another in the thickness direction,
each of the plurality of first layers comprises Si atoms in a range from 1017 to 1018 atoms per 1 cm3, and
the second semiconducting material includes a localized level or an intermediate band in a forbidden band; at least two of the second layers are each disposed between a pair of the first layers; and a thickness of each of the second layers is thinner than a thickness of four molecular layers of the first semiconducting material.

US Pat. No. 10,483,420

CELL MODULE

Raygen Resources PTY LTD,...

1. A photovoltaic cell assembly that is suitable for use in a dense array concentrated photovoltaic cell module, the assembly including a substrate, a plurality of photovoltaic cells mounted on the substrate, each cell having an exposed surface for acceptance of solar radiation, the cells being arranged in a dense array covering more than 95% of the assembly with active cell area that includes at least one string of cells which are electrically connected together and form a series electrical circuit, and each string including a plurality of straight lengths of cells that form rows, with an end cell of one row of cells being electrically connected to a cell at the beginning of a successive row of cells, and a by-pass diode associated with each cell to allow the cell to be by-passed in the electrical circuit in the event that the cell fails or has low illumination, the diodes being positioned in the shadows of the cells, and the diodes providing direct pathways for heat and electricity from the cells to the substrate, and the substrate being a multiple layer substrate including an electrical insulation material layer, a top metalized layer and a bottom metalized layer respectively on opposite top and bottom faces of the electrical insulation material layer, the top metalized layer comprising a plurality of mounting pads in each row on which the cells are secured, with at least 90% of each cell being maintained in thermal contact with the substrate via the mounting pads, each cell being mounted on one of the mounting pads, each mounting pad including a section that extends under a neighboring cell in the electrical circuit, the by-pass diode for the cell being positioned beneath and in the shadow of the neighboring cell and mounted on a section of the mounting pad that extends under the neighboring cell, the diode being electrically and thermally connected to the substrate via the section of the mounting pad, and the diode being electrically and thermally connected to the neighboring cell.

US Pat. No. 10,483,419

SOLAR CELL MODULE AND METHOD OF MANUFACTURING THE SOLAR CELL MODULE

Panasonic Intellectual Pr...

1. A solar cell module comprising:a plurality of solar cell groups forming a power generating field including a light receiving surface for receiving light and a back surface provided on the opposite side of the light receiving surface, for generating electric power by receiving light, wherein each of the plurality of solar cell groups includes a plurality of solar cells arrayed in a first direction, the plurality of solar cell groups being arranged one after another in a second direction substantially orthogonal to the first direction;
a power non-generating field which is an area outside of the plurality of solar cell groups;
a conductive member including a first conductive section extending to the power non-generating field from the power generating field in the first direction, a second conductive section extending to the power non-generating field from the power generating field in the first direction and being spaced apart from the first conductive section in the second direction, and a third conductive section extending along the second direction in the power non-generating field and electrically connecting the first conductive section and the second conductive section to each other in the power non-generating field, wherein at least a part of each of the first conductive section and the second conductive section is provided above an outermost solar cell group positioned at an outermost position among the plurality of solar cell groups in the second direction; and
an output interconnection through which the electric power generated in the power generating field is outputted to an outside of the solar cell module through a terminal box positioned at the back surface and including a bypass diode, wherein the output interconnection includes:
a first output interconnection section connected to the third conductive section in the power non-generating field and extending along the first direction from the power non-generating field to the power generating field; and
a second output interconnection section connected to the first output interconnection section and extending along the second direction over solar cells of two or more of the plurality of solar cell groups in the power generating field, the solar cell module further comprises:
a first wiring provided in an area closer, in the second direction, to the terminal box than the first conductive section is and extending to the power non-generating field from the power generating field in the first direction;
a second wiring being spaced apart from the first wiring in the second direction and extending to the power non-generating field from the power generating field in the first direction;
a solar cell group connecting member extending in the second direction from an area of one of the plurality of solar cell groups to an area of another of the plurality of solar cell groups in the power non-generating field and electrically connecting the first wiring and the second wiring to each other; and
a bypass diode connecting interconnection provided in an area closer, in the second direction, to the terminal box than the first output interconnection section is and extending along the first direction from the solar cell group connecting member to the power generating field,
wherein in the power non-generating field including a boundary between the power generating field and the power non-generating field, as seen in a direction orthogonal to the back surface of the solar cell module,
i) the output interconnection includes no portions that are overlapped with the bypass diode connecting interconnection,
ii) the output interconnection includes no portions that are overlapped with the first conductive section and the second conductive section,
iii) the bypass diode connecting interconnection includes no portions that are overlapped with the first wiring and the second wiring,
iv) the third conductive section includes no portions that are overlapped with the bypass diode connecting interconnection, and
v) the output interconnection includes no portions that are overlapped with the solar cell group connecting member, and
the third conductive section includes an extended portion extending from a position corresponding to the first conductive section toward a side of the terminal box in the second direction, the first output interconnection section connected to the extended portion of the third conductive section in the power non-generating field.

US Pat. No. 10,483,418

PRIMER FOR SOLAR CELL MODULE AND SOLAR CELL MODULE

KABUSHIKI KAISHA TOYOTA J...

1. A primer for a solar cell module, comprising:40 to 95 parts by mass of a polymerizable ester including at least one of an acryloyl group and a methacryloyl group;
5 to 60 parts by mass of an adhesion promoter including a functional group that is improvable in adhesion to an acrylic resin or a methacrylic resin, and an alkoxysilyl group; and
a polymerization initiator for initiating polymerization of the polymerizable ester, the content of which being 0.1 to 10 parts by mass based on 100 parts by mass as a total of the polymerizable ester and the adhesion promoter.

US Pat. No. 10,483,417

CAPACITIVE INFRARED PHOTODETECTOR COMPRISING A QUANTUM DOT LAYER

The Government of the Uni...

1. A photodetector device comprising:an n-type quantum dot layer in a semiconductor heterostructure, the quantum dot layer comprising a plurality of quantum dots embedded within an n-type semiconductor host, an energy gap between valence and conduction bands of the quantum dot layer being smaller than an energy gap between valence and conduction bands of the semiconductor host;
the n-type semiconductor host being n-doped to a doping density approximately equal to a density of the quantum dots embedded in the host such that a fundamental energy level of the semiconductor host is filled with electrons;
wherein electrons within the quantum dot layer are excited upon an application of a negative electrical bias to the device and are trapped within confined states in the quantum dots, the device having a first capacitance ?/W? at a time t1 as a result of the presence of the trapped electrons, where ? is an average dielectric permittivity of materials used in the photodetector and W? is a space charge region of the device after the application of the electrical bias; and
wherein upon an illumination of the device by light having a photon energy at least equal to a difference between an energy of the confined electrons and a conduction band energy in the quantum dot layer, a plurality of the trapped electrons are excited into a conduction band of the quantum dot layer, the device having a second capacitance ?/W? at a time t2 as a result of the excitement of the trapped electrons, where W? is a space charge region of the device after excitation of the plurality of the trapped electrons into the conduction band;
wherein a difference between ?/W? and ?/W? is indicative of an incidence of the light on the device.

US Pat. No. 10,483,413

PHOTOELECTRIC MODULE AND OPTICAL DEVICE

Sony Corporation, Tokyo ...

1. A photoelectric module, comprising:an optical device including an optical function element array made of a first base material, and a plurality of light emitting/receiving elements made of a second base material,
wherein the optical function element array includes an optical substrate and a plurality of optical function elements, the optical substrate having a first surface and a second surface, and the optical function elements being integrated with the optical substrate and being arranged one-dimensionally or two-dimensionally, and
the light emitting/receiving elements and their respective optical function elements face each other with the optical substrate in between to be located on a same axis in a direction perpendicular to the optical substrate, and the light emitting/receiving elements are disposed on the second surface with a space in between while being separated in units of a smaller number than array number in the optical function element array; and
a plurality of front end circuits, wherein wiring lengths between the light emitting/receiving elements and their respective front end circuits are substantially equal.

US Pat. No. 10,483,409

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

LG ELECTRONICS INC., Seo...

1. A solar cell comprising:a substrate having a first conductive type impurity;
an emitter region positioned at a first surface of the substrate, the emitter region forming a p-n junction along with the substrate;
a surface field region positioned at a second surface opposite the first surface of the substrate, the surface field region having the first conductive type impurity more heavily doped than that of the substrate;
a plurality of first electrodes positioned on the emitter region to be separated from one another and connected to the emitter region;
a plurality of second electrodes positioned on the surface field region to be separated from one another and connected to the surface field region;
a first anti-reflection layer positioned on the first surface of the substrate, the second surface of the substrate, and a third surface of the substrate other than the first and second surfaces of the substrate, the first anti-reflection layer which is formed of aluminum oxide and has negative fixed charges;
a second anti-reflection layer positioned on the first anti-reflection layer at the first surface and the third surface of the substrate, the second anti-reflection layer which is formed of silicon nitride and has positive fixed charges; and
a passivation layer positioned between the second surface of the substrate and the first anti-reflection layer,
wherein the first anti-reflection layer is positioned directly between the third surface of the substrate and the second anti-reflection layer,
wherein each of the first anti-reflection layer and the passivation layer has a plurality of first openings where the plurality of second electrodes penetrate therethrough on the second surface of the substrate, and
wherein the first anti-reflection layer continuously wraps around from the first surface to the third surface, and continuously wraps around from the third surface to the second surface.

US Pat. No. 10,483,406

SEMICONDUCTOR DEVICE INCLUDING AN OXIDE SEMICONDUCTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor; and
a photodiode electrically connected to the transistor;
wherein the transistor comprises:
a first oxide semiconductor layer;
a second oxide semiconductor layer over and in direct contact with the first oxide semiconductor layer;
a third oxide semiconductor layer in direct contact with a top surface of the second oxide semiconductor layer;
a gate electrode layer overlapping with the second oxide semiconductor layer with an insulating layer interposed therebetween; and
a source electrode layer and a drain electrode layer electrically connected to the second oxide semiconductor layer,
wherein a difference between a Fermi level and a bottom of a conduction band in the second oxide semiconductor layer is smaller than those in the first oxide semiconductor layer and the third oxide semiconductor layer.

US Pat. No. 10,483,404

THIN FILM TRANSISTOR WITH MULTIPLE OXIDE SEMICONDUCTOR LAYERS

Semiconductor Energy Labo...

2. A semiconductor device comprising:a first oxide semiconductor layer comprising indium and gallium;
a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer;
a third oxide semiconductor layer comprising indium and gallium over the second oxide semiconductor layer;
a first insulating layer over the third oxide semiconductor layer;
a gate electrode over the first insulating layer, and
a second insulating layer in contact with a side surface of the gate electrode,
wherein a content of the gallium in the first oxide semiconductor layer is higher than a content of the indium in the first oxide semiconductor layer,
wherein a content of the indium in the second oxide semiconductor layer is higher than a content of the gallium in the second oxide semiconductor layer,
wherein a content of the gallium in the third oxide semiconductor layer is higher than a content of the indium in the third oxide semiconductor layer,
wherein a proportion of the indium to the gallium in the first oxide semiconductor layer is lower than a proportion of the indium to the gallium in the third oxide semiconductor layer, and
wherein the second oxide semiconductor layer comprises a region which is not overlapped with the gate electrode and the second insulating layer and comprises at least one of nitrogen, argon, and aluminum.

US Pat. No. 10,483,403

SEMICONDUCTOR DEVICE, POWER DIODE, AND RECTIFIER

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode;
a gate insulating layer over the gate electrode;
an oxide semiconductor layer over the gate insulating layer;
a first layer comprising indium and zinc over and in contact with the oxide semiconductor layer; and
a second layer over and in contact with the first layer,
wherein an end portion of the first layer protrudes from an end portion of the second layer in a channel length direction,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein at least a part of the oxide semiconductor layer has c-axis alignment.

US Pat. No. 10,483,400

THIN FILM TRANSISTOR WITH CARBON NANOTUBES

Tsinghua University, Bei...

1. A thin film transistor comprising:an insulating substrate;
a gate electrode, the gate electrode located on the insulating substrate;
a gate insulating layer, the gate insulating layer located on the gate electrode;
a carbon nanotube structure, the carbon nanotube structure located on the gate insulating layer;
wherein the carbon nanotube structure comprises a plurality of carbon nanotubes, each carbon nanotube of the plurality of carbon nanotubes consists of a first metallic carbon nanotube segment, a second metallic carbon nanotube segment and a semiconducting carbon nanotube segment between the first metallic carbon nanotube segment and the second metallic carbon nanotube segment, the first metallic carbon nanotube segment, the second metallic carbon nanotube segment and the semiconducting carbon nanotube segment are connected and form an integrated structure, the first metallic carbon nanotube segment is used as a source electrode, the second metallic carbon nanotube segment is used as a drain electrode, the semiconducting carbon nanotube segment is used as a channel.

US Pat. No. 10,483,398

SEMICONDUCTOR DEVICE WITH GATE STACK

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a gate stack over a semiconductor substrate, wherein the gate stack has a work function layer and a metal filling, and tops of the work function layer and the metal filling are at different height levels;
a protection element over the gate stack, wherein a top and a bottom of the protection element have different widths;
a spacer over a side surface of the protection element and a sidewall of the gate stack;
a conductive feature over the semiconductor substrate; and
a conductive contact electrically connected to the conductive feature.

US Pat. No. 10,483,397

FIN FIELD EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A fin field effect transistor, comprising:a semiconductor substrate having a fin structure between two trenches, wherein each of the two trenches has a top portion and a bottom portion, the top portion of each of the two trenches is closer to a top portion of the fin structure than the bottom portion of each of the two trenches;
shallow trench isolations respectively formed in the bottom portions of the two trenches, wherein the top portion of the fin structure is tapered and above the shallow trench isolations;
a gate electrode over the fin structure and the shallow trench isolations, wherein the gate electrode is perpendicular to the fin structure;
a gate dielectric layer along sidewalls of the fin structure; and
a source/drain doped region formed in the fin structure,
wherein each of the shallow trench isolations has a rounded and convex top corner, a rounded and convex bottom corner and a straight side edge,
wherein the rounded and convex top corner of each of the shallow trench isolations is close to and separated from the fin structure,
wherein the rounded and convex bottom corner of each of the shallow trench isolations is in contact with the bottom portion of each of the two trenches,
wherein the rounded and convex top corner of each of the shallow trench isolations is directly connected the straight side edge of each of the shallow trench isolations, and the shallow trench isolations are in contact with the fin structure,
wherein the gate dielectric layer has a convex top surface and a concave bottom surface, and an entirety of the gate dielectric layer is disposed at a level between a top surface of the fin structure and the rounded and convex top corner of each of the shallow trench isolations.

US Pat. No. 10,483,396

INTERFACIAL LAYER BETWEEN FIN AND SOURCE/DRAIN REGION

Taiwan Semiconductor Manu...

1. A semiconductor structure comprising:a substrate;
a fin on the substrate, the fin comprising silicon germanium and having recessed portions;
an interfacial layer over the recessed portions of the fin, the interfacial layer having a thickness in a range from about 1 nm to about 4 nm, wherein the interfacial layer encapsulates impurities on a surface of the fin; and
a source/drain region over the interfacial layer, the source/drain region comprising silicon germanium.

US Pat. No. 10,483,395

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:providing a substrate having a first region and a second region;
forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region;
forming a first liner on the first fin-shaped structure and the second fin-shaped structure;
forming a first buffer layer on the first liner;
removing the first buffer layer on the first region;
forming an insulating layer on the first fin-shaped structure and the second fin-shaped structure; and
performing a curing process to combine the first buffer layer and the insulating layer into one unit while the first liner is on the first fin-shaped structure and the second fin-shaped structure and a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.

US Pat. No. 10,483,394

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a Fin FET device including:
a first fin structure disposed over a substrate;
an isolation insulating layer disposed over the substrate; and
a first source/drain stressor layer made of semiconductor material and disposed over the first fin structure, wherein:
an upper surface of the isolation insulating layer has a valley portion and a peak portion disposed between the valley portion and the first fin structure, and
a height Ha of an interface between the first fin structure and the first source/drain stressor layer measured from the substrate is greater than a height Hb of the valley portion measured from the substrate, and is less than a height Hc of the peak portion measured from the substrate.

US Pat. No. 10,483,391

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor substrate having a first surface;
an insulating isolation film disposed at the first surface; and
a gate electrode,
the semiconductor substrate having a source region disposed in contact with the first surface, a drain region disposed in contact with the first surface, a drift region disposed in contact with the first surface so as to surround the drain region, and a body region sandwiched between the drift region and the source region and disposed in contact with the first surface so as to surround the source region,
the source region, the drain region, and the drift region being of a first conductivity type,
the body region being of a second conductivity type which is opposite to the first conductivity type,
the insulating isolation film having a first portion disposed inside the drift region in plan view, a second portion protruding from the first portion in a direction toward the source region, and a third portion protruding from the first portion in the direction toward the source region and sandwiching the drift region between the second portion and the third portion,
the gate electrode facing a portion of the body region sandwiched between the source region and the drift region with being insulated from the portion, and being disposed so as to extend over the second portion and the third portion, wherein
the semiconductor substrate has a second surface opposite to the first surface,
the gate electrode has a first embedded portion embedded in the second portion, and a second embedded portion embedded in the third portion,
the drift region is sandwiched between the first embedded portion and the second embedded portion, and
the gate electrode has a third embedded portion embedded in the first portion and facing the drift region sandwiched between the second portion and the third portion.

US Pat. No. 10,483,390

INSULATED GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

FUJI ELECTRIC CO., LTD., ...

1. An insulated gate semiconductor device, comprising:a drift layer of a first conductivity type made of a semiconductor material having a wider bandgap than silicon, a top surface of the semiconductor material having an off-angle;
a base region of a second conductivity type made of said semiconductor material, disposed above the drift layer;
a first high-impurity region of the first conductivity type, embedded in a top of the base region and having a higher impurity density than the drift layer, wherein a trench is provided penetrating the first high-impurity region and the base region;
a gate insulating film disposed on side surfaces and a bottom surface of the trench;
an embedded gate electrode embedded inside the trench, with the gate insulating film being interposed between the trench and the embedded gate electrode;
a second high-impurity region of the first conductivity type made of said semiconductor material, disposed on a bottom surface side of the drift layer;
a gate bottom protection region of the second conductivity type, embedded in the drift layer at a bottom of the trench; and
a base bottom embedded region of the second conductivity type, embedded in the drift layer below the base region separately from the gate bottom protection region, and having a higher impurity density than the base region,
wherein a cross-section of the base bottom embedded region has a trapezoid-shaped portion on at least a bottom side of the base bottom embedded region, an upper base and a lower base of the trapezoid are parallel, and a virtual straight line that connects a midpoint of the upper base and a midpoint of the lower base is tilted from a line normal to the top surface of the drift layer towards a direction of the off-angle by a prescribed tilt angle, and
wherein a bottom surface of the base bottom embedded region is deeper than a bottom surface of the gate bottom protection region.

US Pat. No. 10,483,389

SILICON CARBIDE SEMICONDUCTOR DEVICE

HESTIA POWER INC., Hsinc...

12. A silicon carbide (SiC) semiconductor device, comprising:an n-type substrate, having a first doping concentration;
an n-type drift layer, disposed on the substrate, having a second doping concentration less than the first doping concentration;
a plurality of first doped regions and a plurality of second doped regions, disposed at the n-type drift layer, each of the first doped regions comprising a first p-well, a heavily doped n-type (n+) region located in the first p-well, and a first heavily doped p-type (p+) region located in the first p-well and surrounded by the heavily doped n+ region, each of the second doped regions comprising at least one sub-doped region, wherein each of a plurality of first junction field effect transistor (JFET) regions having a third doping concentration formed between each of the first doped regions and the second doped regions, and each of a plurality of second junction field effect transistor (JFET) regions having a fourth doping concentration formed between each of the sub-doped regions or enclosed by the sub-doped region;
a gate dielectric layer, disposed on the n-type drift layer;
a gate electrode, disposed on the gate dielectric layer;
an inter-layer dielectric layer, disposed on the gate dielectric layer and the gate electrode;
a plurality of source openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the heavily doped n+ region and the first heavily doped p+ region, and the plurality of source openings are separated by the gate electrode and the inter-layer dielectric layer, wherein a top surface of n-type drift layer and a top surface of the heavily doped p+ region are in a same first plane;
a plurality of junction openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the plurality of second JFET regions and the second doped regions, and the plurality of junction openings are separated by the gate electrode and the inter-layer dielectric layer;
a plurality of gate openings, penetrating through the inter-layer dielectric layer to a surface portion of the gate electrode;
a first metal layer, disposed only at a bottom of the source openings, formed an Ohmic contact with the surface portion of the heavily doped n+region and the first heavily doped p+ region;
a second metal layer, comprising a first portion and a second portion, wherein the first portion covers the source openings and the junction openings, is electrically connected to the first metal layer, and forms a Schottky contact with the surface portion of the plurality of second JFET regions, the second portion covers the gate openings and is electrically insulated from the first portion, wherein a bottom surface of the first metal layer and a bottom surface of a part of the second metal layer are in a same second plane, and
wherein the third doping concentration is greater than the second doping concentration.

US Pat. No. 10,483,388

NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE AND SEMICONDUCTOR DEVICE

SCIOCS COMPANY LlMITED, ...

1. A nitride semiconductor epitaxial substrate, comprising:a substrate;
a first nitride semiconductor layer formed on the substrate, as an electron transit layer in which two-dimensional electron gas exists; and
a second nitride semiconductor layer formed on the first nitride semiconductor layer, as an electron supply layer,
wherein in the whole second nitride semiconductor layer, a hydrogen concentration is higher than a hydrogen concentration of the first nitride semiconductor layer and a difference of the hydrogen concentration of the second nitride semiconductor layer from the hydrogen concentration of the first nitride semiconductor layer is 2×1018 cm?3 or less.

US Pat. No. 10,483,387

LATERAL/VERTICAL SEMICONDUCTOR DEVICE WITH EMBEDDED ISOLATOR

Sensor Electronic Technol...

1. A lateral/vertical device comprising:a device structure including a device channel, wherein the device channel includes a lateral portion, a vertical portion, and a transition region between the lateral portion and the vertical portion;
a first contact to the lateral portion of the device channel;
a second contact to the vertical portion of the device channel, wherein the first and second contacts are located on opposing surfaces of the device structure;
a set of insulating layers having a resistivity above 1010 Ohm×cm and located in the device structure between the lateral portion of the device channel and the second contact, wherein an opening in the set of insulating layers defines the transition region of the device channel; and
a channel layer located between the set of insulating layers and the second contact, and within the opening in the set of insulating layers.

US Pat. No. 10,483,386

SEMICONDUCTOR DEVICE, TRANSISTOR HAVING DOPED SEED LAYER AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a single layer substrate having a substrate lattice structure, wherein the substrate comprises p-type dopants;
an AlN seed layer above and in direct contact with the substrate, the AlN seed layer comprising an AlN first seed sublayer having a first lattice structure and an AlN second seed sublayer having a second lattice structure, the second lattice structure being different than the first lattice structure, wherein a portion of the AlN seed layer closest to the substrate comprises carbon dopants and has a different lattice structure from the substrate lattice structure, and wherein the second seed sublayer is formed at a temperature ranging from about 1000° C. to about 1300° C.;
a channel layer over the AlN seed layer;
an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer; and
a graded layer in direct contact with the AlN seed layer with the channel layer comprising a single material layer in direct contact with the graded layer, wherein the graded layer comprises:
a first graded sublayer including AlxGa1-xN, where x ranges from 0.7 to 0.9;
a second graded sublayer on the first graded sublayer, the second graded sublayer including AlxGa1-yN, where y ranges from 0.4 to 0.6; and
a third graded sublayer on the second graded sublayer, the third graded sublayer including AlzGa1-zN, where z ranges from 0.15 to 0.3.

US Pat. No. 10,483,382

TUNNEL TRANSISTOR

International Business Ma...

1. A tunnel field-effect transistor device comprising:a semiconductor substrate including a first region, a second region, and a channel region between the first and second regions;
a first gate electrode operatively associated with the channel region;
a first gate dielectric layer between the first gate electrode and the channel region;
a first doped epitaxial source region on the first region of the semiconductor substrate and having a first conductivity type;
a doped epitaxial drain region on the second region of the semiconductor substrate and having a second conductivity type opposite from the first conductivity type;
a first source contact electrically connected to the first source region;
a drain contact electrically connected to the drain region, the first source contact and the drain contact comprising different electrically conductive materials;
a first source contact cap on the first source contact, the first source contact cap comprising a first dielectric material;
a drain contact cap on the drain contact, the drain contact cap comprising a second dielectric material different from the first dielectric material, and
a first gate cap over the first gate electrode, the first gate cap comprising a third dielectric material different from the first and second dielectric materials and further including: a second doped source region on the semiconductor substrate; a second source contact electrically connected to the second doped source region; a second source contact cap on the second source contact; a first recess within the first source contact cap; a second recess within the second source contact cap, and a source wiring strap extending within the first and second recesses and electrically connecting the first source contact and the second source contact.

US Pat. No. 10,483,380

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a source region having a first dopant;
a drain region having a second dopant, the first dopant being different from the second dopant;
a channel region between the source region and drain region, wherein the channel region is intrinsic;
a tunnel barrier layer between the drain region and the channel region, wherein a material of the tunnel barrier layer having a larger bandgap than the channel region; and
a gate stack disposed on the channel region.

US Pat. No. 10,483,379

HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS

GlobalWafers Co., Ltd., ...

1. A method of forming a multilayer structure, the method comprising:forming a crystalline semiconductor nitride layer on a front surface of a silicon wafer handle substrate, wherein the crystalline semiconductor nitride layer is selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof and further wherein the crystalline semiconductor nitride layer is formed by metalorganic chemical vapor deposition occurring by a reaction between an organic compound or a metalorganic compound and a nitrogen-containing precursor and wherein the silicon wafer handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
forming a silicon dioxide layer having a thickness between about 500 nanometers and about 2 micrometers in interfacial contact with the crystalline semiconductor nitride layer; and
bonding a dielectric layer in interfacial contact with a front surface of a semiconductor donor substrate to the silicon dioxide layer in interfacial contact with the crystalline semiconductor nitride layer to thereby form a bonded structure, wherein the semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate.

US Pat. No. 10,483,378

EPITAXIAL FEATURES CONFINED BY DIELECTRIC FINS AND SPACERS

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first semiconductor fin extending upwardly from a semiconductor substrate;
an isolation structure over the semiconductor substrate and on sidewalls of the first semiconductor fin;
a first epitaxial feature over the first semiconductor fin;
a dielectric fin partially embedded in the isolation structure and projecting upwardly above the isolation structure, wherein a portion of the isolation structure is disposed between the dielectric fin and the semiconductor substrate thereby preventing the dielectric fin from interfacing with the semiconductor substrate; and
first and second spacer features over the isolation structure, wherein the first spacer feature is laterally between the first epitaxial feature and the dielectric fin, and the first epitaxial feature is laterally between the first and second spacer features.

US Pat. No. 10,483,376

METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE

UNISANTIS ELECTRONICS SIN...

1. A method for producing a semiconductor device, the method comprising:depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate;
forming a first hole for forming a gate electrode in the second insulating film;
filling the first hole with a first metal to form the gate electrode;
forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole;
performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film;
forming a gate insulating film on a side surface of the second hole; and
epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

US Pat. No. 10,483,375

FIN CUT ETCH PROCESS FOR VERTICAL TRANSISTOR DEVICES

International Business Ma...

1. A method for fabricating a semiconductor device including a vertical transistor, comprising:forming a fin structure from a substrate, the fin structure including a fin;
forming a bottom source/drain region on the substrate adjacent to the fin;
etching a longitudinal end portion of the fin to create a gap exposing the substrate;
forming a gate and a top source/drain region; and
forming a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region in a region including a location where the longitudinal end portion of the fin was removed by the etching.

US Pat. No. 10,483,373

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first insulating interlayer on a substrate;
a second insulating interlayer on the first insulating interlayer;
a gate structure extending through the first insulating interlayer and the second insulating interlayer on the substrate, a lower portion of the gate structure having a constant first width, and an upper portion of the gate structure having a second width that is greater than the first width and that gradually increases from a bottom toward a top thereof; and
a spacer structure on a sidewall of the gate structure, a width of an upper portion of the spacer structure being less than a width of a lower portion of the spacer structure.

US Pat. No. 10,483,370

SEMICONDUCTOR STRUCTURE WITH UNLEVELED GATE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a fin structure formed over a substrate;
a gate structure formed across the fin structure, wherein the gate structure comprises:
a gate dielectric layer formed over the substrate;
a work function metal layer formed over a portion of the gate dielectric layer; and
a gate electrode layer formed over a portion of the work function metal layer,
wherein a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer;
a spacer formed on a sidewall of the gate structure; and
a dielectric material formed over the top surface of the gate electrode layer and in direct contact with the top surface of the gate electrode layer,
wherein a topmost surface of the spacer is higher than a topmost surface of the gate electrode layer, and a bottommost of the dielectric material is lower than a topmost surface of the gate dielectric layer.

US Pat. No. 10,483,369

METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON TRANSISTOR DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a continuous line-type sacrificial gate structure above a semiconductor substrate by performing a method that comprises:
forming a sacrificial gate insulation layer above said semiconductor substrate;
forming a first sacrificial gate electrode material layer above said sacrificial gate insulation layer; and
forming a second sacrificial gate electrode material layer above said first sacrificial gate electrode material layer;
after forming said continuous line-type sacrificial gate structure, removing a portion of said second sacrificial gate electrode material layer and removing a portion of said first sacrificial gate electrode material layer so as to thereby form a first opening positioned above said sacrificial gate insulation layer, wherein said first opening extends through an entirety of said second sacrificial gate electrode material layer of said continuous line-type sacrificial gate structure and at least partially through said first sacrificial gate electrode material layer of said continuous line-type sacrificial gate structure;
forming an insulating gate separation structure in said first opening;
removing materials of said sacrificial gate structure on opposite sides of said insulating gate separation structure to form first and second replacement gate cavities on said opposite sides of said insulating gate separation structure; and
forming first and second replacement gate structures in said first and second replacement gate cavities, respectively.

US Pat. No. 10,483,367

VERTICAL GATE ALL AROUND (VGAA) DEVICES AND METHODS OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a semiconductor substrate having a doped region;
a spacer layer over the semiconductor substrate;
a protrusion extending from the doped region away from the semiconductor substrate, the protrusion comprising a first source/drain region adjacent the doped region, a channel region disposed over the first source/drain region, and a second source/drain region disposed over the channel region;
a gate stack encircling the channel region of the protrusion, the gate stack being over the spacer layer; and
an epitaxial semiconductor material disposed over a top surface and extending from sidewalls of the second source/drain region of the protrusion, the epitaxial semiconductor material having an octagonal shape in cross-sectional view.

US Pat. No. 10,483,366

SEMICONDUCTOR DEVICE

UNISANTIS ELECTRONICS SIN...

1. A semiconductor device comprising:a third first-conductivity-type semiconductor layer on a semiconductor substrate;
a first pillar-shaped semiconductor structure vertically extending from a surface of the semiconductor substrate, the first pillar-shaped semiconductor structure including, in sequence,
a first first-conductivity-type semiconductor layer,
a first body region,
a second first-conductivity-type semiconductor layer,
a first second-conductivity-type semiconductor layer;
a second body region,
a second second-conductivity-type semiconductor layer, and
a third second-conductivity-type semiconductor layer,
each layer and region vertically aligned within the first pillar-shaped semiconductor structure;
the semiconductor device further comprising:
a first gate insulating film around the first body region;
a first metal gate around the first gate insulating film;
a second gate insulating film around the second body region;
a second metal gate around the second gate insulating film;
an output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer; and
a first contact connecting the first metal gate and the second metal gate;
a first insulating film surrounding the first first-conductivity-type semiconductor layer and a second insulating film surrounding the second first-conductivity-type semiconductor layer;
a third insulating film surrounding the first second-conductivity-type semiconductor layer and a fourth insulating film surrounding the second second-conductivity-type semiconductor layer;
wherein the first insulating film and the second insulating film contain a same impurity as the first and second first-conductivity-type semiconductor layers, respectively; and
wherein the third insulating film and the fourth insulating film contain a same impurity as the first and second second-conductivity-type semiconductor layers, respectively.

US Pat. No. 10,483,362

HIGH ELECTRON MOBILITY TRANSISTOR DEVICES AND METHOD FOR FABRICATING THE SAME

VANGUARD INTERNATIONAL SE...

1. A method for fabricating a high electron mobility transistor (HEMT) device, comprising:providing a substrate;
forming a buffer layer on the substrate;
forming a first epitaxial layer on the buffer layer;
forming a second epitaxial layer on the first epitaxial layer;
forming an insulating layer on the second epitaxial layer;
disposing a gate in the insulating layer;
disposing a source and a drain in the insulating layer, wherein the source and the drain are located on both sides of the gate;
forming a trench to pass through the insulating layer and the second epitaxial layer, and to extend into the first epitaxial layer; and
forming a metal layer on the insulating layer to connect to the source, and to fill into the trench to electrically connect to the first epitaxial layer and the source, wherein an orthogonal projection of the metal layer onto the substrate does not overlap an orthogonal projection of the source onto the substrate.

US Pat. No. 10,483,360

SEMICONDUCTOR DEVICE COMPRISING A GRADUALLY INCREASING FIELD DIELECTRIC LAYER AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A method of manufacturing a semiconductor device, the method comprising:forming a trench in a semiconductor substrate;
forming an oxide layer over sidewalls and over a bottom side of the trench;
performing an ion implantation process so as to damage the oxide layer disposed over the sidewalls and the bottom side of the trench;
forming a covering layer in the trench over the damaged oxide layer;
patterning the covering layer in the trench, thereby forming an uncovered area of the damaged oxide layer at a first area in the trench and a covered area of the damaged oxide layer at a second area in the trench, wherein the covered area of the damaged oxide layer is covered by a remaining portion of the covering layer;
performing an isotropic etching process thereby removing the uncovered area of the damaged oxide layer in the trench and removing a portion of the covered area of the damaged oxide layer in the trench located adjacent to the uncovered area of the damaged oxide layer, wherein the removed portion of the covered area of the damaged oxide layer is located underneath the remaining portion of the covering layer; and
removing the remaining portion of the covering layer.

US Pat. No. 10,483,357

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate having a drift region of a first conductivity type;
a cathode region formed on a lower surface of the semiconductor substrate;
a diode portion having the cathode region formed on the lower surface of the semiconductor substrate;
a first dummy trench portion provided from an upper surface of the semiconductor substrate to the drift region, including one part provided inside the diode portion and the other part provided outside the diode portion, and provided extending in series from inside the diode portion to outside the diode portion in a predetermined extending direction on the upper surface of the semiconductor substrate; and
a first lead-out portion provided on the upper surface of the semiconductor substrate, and electrically connected to the first dummy trench portion outside the diode portion.

US Pat. No. 10,483,356

POWER SEMICONDUCTOR DEVICE WITH OPTIMIZED FIELD-PLATE DESIGN

SILICONIX INCORPORATED, ...

1. A semiconductor device comprising:a source bonding pad;
a drain bonding pad;
a drain metallization structure comprising a drain field plate; and
a source metallization structure comprising a source field plate;
at least a portion of the source bonding pad being situated directly over an active area of the device in a first area of the device;
at least a portion of the drain bonding pad being situated directly over an active area of the device in a second area of the device;
wherein the source field plate has a first dimension positioned in the first area, and a second dimension different from the first dimension positioned in an area of the device other than the first area; and
wherein the drain field plate has a first dimension positioned in the second area, and a second dimension different from the first dimension positioned in an area of the device other than the second area.

US Pat. No. 10,483,355

FORMING NON-LINE-OF-SIGHT SOURCE DRAIN EXTENSION IN AN NMOS FINFET USING N-DOPED SELECTIVE EPITAXIAL GROWTH

APPLIED MATERIALS, INC., ...

1. A finFET device, comprising:a semiconductor substrate having a bulk semiconductor region;
a semiconductor fin structure that is disposed on the bulk semiconductor region, the semiconductor fin structure comprising:
a source extension region epitaxially grown on the bulk semiconductor region, the source extension region comprising a first n-type dopant;
a drain extension region epitaxially grown on the bulk semiconductor region, the drain extension region comprising the first n-type dopant;
a first carbon-containing layer that is surrounded by the source extension region and not in direct contact with the bulk semiconductor region;
a second carbon-containing layer that is surrounded by the drain extension region and not in direct contact with the bulk semiconductor region;
a source region comprising a second n-type dopant, wherein the source region is surrounded by the first carbon-containing layer and not in direct contact with the bulk semiconductor region;
a drain region comprising the second n-type dopant, wherein the drain region is surrounded by the second carbon-containing layer and not in direct contact with the bulk semiconductor region; and
a channel region between the source extension region and the drain extension region; and
a gate electrode structure that is formed on a portion of the semiconductor fin structure, the gate electrode structure comprising:
a gate electrode layer;
a first gate spacer formed on a first sidewall of the gate electrode layer and on the source extension region; and
a second gate spacer formed on a second sidewall of the gate electrode layer and on the drain extension region wherein
the first n-type dopant is different than the second n-type dopant,
the first n-type dopant in the source extension region prevents diffusion of the second n-type dopant in the source region to the channel region, and
the first n-type dopant in the drain extension region prevents diffusion of the second n-type dopant in the drain region to the channel region.

US Pat. No. 10,483,353

TRANSISTOR INCLUDING TENSILE-STRAINED GERMANIUM CHANNEL

INTEL CORPORATION, Santa...

1. An integrated circuit comprising:a substrate;
a first transistor comprising
a first body above the substrate, the first body including tensile-strained semiconductor material that includes germanium,
a first gate structure at least above the first body, the first gate structure including one or more metals, and
a first source region and a first drain region, the first body between the first source and drain regions, the first source and drain regions including semiconductor material and n-type dopant; and
a second transistor comprising
a second body above the substrate, the second body including tensile-strained semiconductor material that includes germanium,
a second gate structure at least above the second body, the second gate structure including one or more metals, and
a second source region and a second drain region, the second body between the second source and drain regions, the second source and drain regions including semiconductor material and p-type dopant.

US Pat. No. 10,483,351

METHOD OF MANUFACTURING A SUBSTRATE WITH REDUCED THREADING DISLOCATION DENSITY

Nanyang Technological Uni...

1. A substrate with reduced threading dislocation density, comprising:a semiconductor substrate;
a first germanium layer formed on the semiconductor substrate, the first germanium layer being doped with a first concentration of at least one dopant that is of a different material to the first germanium layer; and
a second germanium layer formed on the first germanium layer, the second germanium layer being doped with a second concentration of the at least one dopant, doped concentration of the at least one dopant in the second germanium layer being decreased progressively from the first concentration to the second concentration,
wherein the dopant is different to silicon.

US Pat. No. 10,483,350

SEMICONDUCTOR DEVICE

HOSEI UNIVERSITY, Tokyo ...

1. A semiconductor device, comprising:a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure;
an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure;
a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and
a second electrode electrically connected to the first semiconductor layer on a lower surface of the first semiconductor layer,
wherein the insulating film is formed including a first insulating layer and a second insulating layer,
the first insulating layer is disposed so as to cover a corner portion where the side surface of the mesa structure and the outside upper surface of the mesa structure are connected to each other,
the second insulating layer is disposed so as to cover the pn junction interface exposed on the side surface of the mesa structure, or disposed so as to cover an area directly under an electrode end in a state of constituting an entire thickness of the insulating film directly under the electrode end of the first electrode,
a relative dielectric constant of the second insulating layer is equal to or larger than a relative dielectric constant of the semiconductor member, and
the relative dielectric constant of the first insulating layer is smaller than the relative dielectric constant of the second insulating layer, and
wherein the first insulating layer is in direct contact with the corner portion,
the second insulating layer is in direct contact with the pn junction interface, or in direct contact with the semiconductor member at an area directly under the electrode end of the first electrode, and
the second insulating layer is not in contact with the corner portion.

US Pat. No. 10,483,347

SEMICONDUCTOR DEVICE, STARTER CIRCUIT, AND SWITCHED-MODE POWER-SUPPLY CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;
a drift layer of a second conductivity type provided on the semiconductor substrate;
a drain region of the second conductivity type in contact with the drift layer to be provided on the semiconductor substrate at a center of the drift layer;
a gate region of the first conductivity type provided on the semiconductor substrate in an outer side of the drift layer, the gate region including U-shaped first and second concave patterns in a planar pattern, each of which having entrances of the U-shapes located with equal distances from the drain region, the bottoms of the U-shapes protruding toward an outer side of the planar pattern;
source regions of the second conductivity type provided in an inner side of the first concave patterns, each of the source regions contacts with the drift layer and the gate region; and
surge-current guiding-regions of the second conductivity type provided in an inner side of the second concave patterns, each of the surge-current guiding-regions contacts with the drift layer and the gate region.

US Pat. No. 10,483,344

FABRICATION OF A MIM CAPACITOR STRUCTURE WITH VIA ETCH CONTROL WITH INTEGRATED MASKLESS ETCH TUNING LAYERS

International Business Ma...

1. A method for fabricating a semiconductor device, comprising:forming a first plate of a metal-insulator-metal (MIM) capacitor structure and a first etch tuning layer adjacent to the first plate on a base structure, the base structure including contacts formed within a base layer;
forming a first dielectric layer on the first plate and the first etch tuning layer;
forming a second plate of the MIM capacitor structure and a second etch tuning layer adjacent to the second plate on the first dielectric layer;
forming a second dielectric layer on the second plate and the second etch tuning layer; and
forming a third plate of the MIM capacitor structure and a third etch tuning layer adjacent to the third plate on the second dielectric layer, wherein the etch tuning layers include materials for balancing etch depth during formation of a plurality of vias.

US Pat. No. 10,483,342

ORGANIC LIGHT EMITTING DIODE DISPLAY

Samsung Display Co., Ltd....

1. An organic light emitting diode display comprising:a substrate;
a scanning line on the substrate;
a data line;
a first thin film transistor coupled to the scanning line and the data line;
a first voltage line;
an organic light emitting diode;
a second thin film transistor utilizing a semiconductor layer, and electrically coupled to the first voltage line, the organic light emitting diode, and the first thin film transistor;
a third thin film transistor electrically coupled to the second thin film transistor;
an insulating layer covering the second thin film transistor; and
a storage capacitor electrically coupled to a gate electrode of the second thin film transistor,
wherein the storage capacitor comprises a first capacitor plate comprising a portion of the gate electrode of the second thin film transistor, a second capacitor plate over the first capacitor plate, and a portion of the insulating layer between the first capacitor plate and the second capacitor plate, and
wherein the semiconductor layer is extended to the third thin film transistor.

US Pat. No. 10,483,340

TRANSISTOR ARRAY PANEL, INCLUDING A SOURCE CONNECTING MEMBER AND A DRAIN CONNECTING MEMBER MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A transistor display panel comprising:a substrate;
a first transistor disposed on the substrate; and
a pixel electrode connected to the first transistor,
wherein the first transistor includes:
a first semiconductor on the substrate,
a first insulating layer covering the first semiconductor,
a first gate electrode on the first insulating layer overlapping the first semiconductor,
a first connecting member disposed on the first insulating layer and connected to the first semiconductor, the first connecting member including a first source connecting member and a first drain connecting member,
a second insulating layer covering the first gate electrode, the first source connecting member and the first drain connecting member, and
a first source electrode and a first drain electrode disposed on the second insulating layer,
wherein the first gate electrode includes at least three layers and the first connecting member includes at least two layers,
wherein the first source electrode is connected to the first source connecting member,
wherein the first semiconductor includes a first channel, and a first source region and a first drain region disposed at respective sides of the first channel, and
wherein the first source region and the first drain region are respectively connected to the first source connecting member and the first drain connecting member.

US Pat. No. 10,483,339

ORGANIC LIGHT-EMITTING DEVICE INCLUDING A BRIDGE ELECTRODE

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting device comprising:a substrate comprising a pixel area;
an oxide semiconductor layer disposed in the pixel area, wherein the oxide semiconductor layer comprises a channel region, a source region and a drain region, and wherein the channel region is disposed between the source region and the drain region;
a gate insulating layer disposed on the oxide semiconductor layer;
a gate electrode disposed on the gate insulating layer;
a conductive layer disposed between the substrate and the oxide semiconductor layer, wherein a first portion of the conductive layer is electrically connected to one of the source region and the drain region via a bridge electrode, wherein the bridge electrode is in contact with the one of the source region and the drain region and a second portion of the conductive layer, and wherein the first portion of the conductive layer overlaps the channel region;
a first insulation film covering the gate electrode and the bridge electrode; and
an organic light-emitting diode comprising a pixel electrode disposed on the first insulation film in the pixel area, an emissive layer disposed on the pixel electrode, and an opposite electrode disposed on the emissive layer,
wherein at least a portion of the oxide semiconductor layer overlaps the organic light-emitting diode.

US Pat. No. 10,483,338

ORGANIC LIGHT-EMITTING DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE

SHANGHAI TIANMA MICRO-ELE...

1. An organic light-emitting display panel, comprising:an array substrate;
a plurality of pixel driving circuits disposed on the array substrate;
a planarization layer disposed on the array substrate, wherein a plurality of connection holes corresponding to the plurality of pixel driving circuits is provided in the planarization layer;
a pixel defining layer disposed on the planarization layer, wherein the pixel defining layer comprises a plurality of pixel apertures; and
a plurality of organic light-emitting devices, wherein at least two organic light-emitting devices of the plurality of organic light-emitting devices for emitting a same color are disposed in each of the plurality of pixel apertures, each of the plurality of organic light-emitting devices comprises an anode and at least one organic light-emitting function layer, and anodes of the plurality of organic light-emitting devices are electrically connected to the plurality of pixel driving circuits through the plurality of connection holes in one-to-one correspondence,
wherein a plurality of grooves is provided in the planarization layer, wherein one groove of the plurality of grooves is disposed between two adjacent organic light-emitting devices of the plurality of organic light-emitting devices disposed in a respective one of the plurality of the pixel apertures; the plurality of grooves is filled with a hydrophobic layer having a trench, an extending direction of the trench in each groove of the plurality of grooves is the same as an extending direction of said groove.

US Pat. No. 10,483,337

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. An organic light emitting display device, comprising:a switching element disposed on a substrate;
a planarization layer covering the switching element;
a first electrode disposed on the planarization layer and coupled to the switching element, a first through hole being defined in a peripheral portion of the first electrode;
a pixel defining layer covering the peripheral portion of the first electrode to expose an emission portion of the first electrode;
an organic light emitting layer disposed on the emission portion of the first electrode; and
a second electrode disposed on the organic light emitting layer.

US Pat. No. 10,483,334

DISPLAY PANEL AND ELECTRONIC DEVICE COMPRISING THEREOF

Au Optronics Corporation,...

1. A display panel, comprising:a first substrate; and
a second substrate, corresponding to the first substrate, wherein a plurality of display units are provided between the first substrate and the second substrate, at least one of the display units respectively comprises three sub-pixels configured to display different colors respectively, the sub-pixels respectively have at least one switch element electrically connected to a signal line, wherein the sub-pixels respectively at least have a display region and a light shielding region disposed on at least one side of the display region, and at least one display element is disposed in the display region;
a color conversion layer, disposed on the display units, wherein the color conversion layer comprises three color conversion elements respectively corresponding to the sub-pixels, and the color conversion elements respectively convert a light into different colors, wherein each of the color conversion elements is disposed in at least one portion of the light shielding region of each of the sub-pixels; and
an image sensing layer, disposed on the display units and at least partially overlapping the color conversion layer, wherein the image sensing layer comprises three image sensing elements respectively corresponding to the sub-pixels, and each of the image sensing elements is electrically connected to a reading line through at least one reading element, wherein each of the image sensing elements is disposed in at least one portion of the light shielding region of each of the sub-pixels to serve as an image sensing region.

US Pat. No. 10,483,332

FLEXIBLE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...

1. A flexible display device, comprising:a first base having an active area and a dead area surrounding the active area, the first base including a pad portion provided in the dead area on one side of the active area;
an array in the active area of the first base;
an encapsulation layer configured to cover the array;
a second base opposite to the first base;
a touch electrode array on the second base to be opposite to the active area of the first base;
a plurality of path holes in the dead area on at least one of the other sides of the active area on which the pad portion is not located;
an inorganic dummy pattern spaced apart from the encapsulation layer among the path holes in a plane; and
an adhesive layer between the encapsulation layer and the touch electrode array to fill the path holes,
wherein the adhesive layer fills the path holes outside an edge of the encapsulation layer to surround the array and the touch electrode array.

US Pat. No. 10,483,328

ORGANIC LIGHT-EMITTING ELEMENT AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE

Duk San Neolux Co., Ltd, ...

1. An organic light emitting element having first, second, and third sub-pixels with different colors on a substrate, the organic light emitting element comprising:first electrodes disposed on the substrate;
a second electrode disposed on the substrate to face the first electrodes;
organic light emitting layers disposed between the first electrodes and the second electrode, the organic light emitting layers comprising a first organic light emitting layer disposed in the first sub-pixel, a second organic light emitting layer disposed in the second sub-pixel, and a third organic light emitting layer disposed in the third sub-pixel;
a hole transport layer disposed between the first electrodes and the organic light emitting layers; and
auxiliary light emitting layers disposed between the hole transport layer and the organic light emitting layers, the auxiliary light emitting layers comprising: a first auxiliary light emitting layer commonly disposed in the first sub-pixel, the second sub-pixel, and the third sub-pixel; a second auxiliary light emitting layer disposed in the second sub-pixel between the first auxiliary light emitting layer and the second organic light emitting layer, and a third auxiliary light emitting layer disposed in the third sub-pixel between the first auxiliary light emitting layer and the third light emitting layer,
wherein the first sub-pixel comprises the first auxiliary light emitting layer disposed between the hole transport layer and the first organic light emitting layer,
wherein the second sub-pixel comprises the first auxiliary light emitting layer and the second auxiliary light emitting layer between the hole transport layer and the second organic light emitting layer,
wherein the third sub-pixel comprises the first auxiliary light emitting layer and the third auxiliary light emitting layer between the hole transport layer and the third organic light emitting layer, and
wherein the highest occupied molecular orbital (HOMO) level of the first auxiliary light emitting layer is larger than the HOMO level of the hole transport layer, and smaller than the HOMO level of the second auxiliary light emitting layer and the third auxiliary light emitting layer,
wherein the first auxiliary light emitting layer, the second auxiliary light emitting layer, and the third auxiliary light emitting layer are formed of a hole transporting material.

US Pat. No. 10,483,327

LIGHT EMITTING DIODE AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A light-emitting diode, comprising:a first electrode;
a second electrode overlapping the first electrode;
a first emission layer and a second emission layer provided between the first electrode and the second electrode; and
a first charge generating layer provided between the first emission layer and the second emission layer, the first charge generating layer including a p-type charge generating layer and an n-type charge generating layer,
wherein:
the n-type charge generating layer includes an organic material and an inorganic material doped to the organic material,
the inorganic material includes a lanthanide metal, an alkali halide, and a ternary compound generated by combining the lanthanide metal and the alkali halide, or
the inorganic material includes an alkali earth metal, the alkali halide, and a ternary compound generated by combining the alkali earth metal and the alkali halide.

US Pat. No. 10,483,325

LIGHT EMITTING PHOTOTRANSISTOR

University of Florida Res...

18. A method of operating a photonic conversion device comprising a photoactive layer, a porous conductor layer, an electron transport layer in contact with the porous conductor layer, and a light emitting device in contact with the electron transport layer, the method comprising:applying a first bias voltage from the porous conductor layer across the photoactive layer;
applying a second bias voltage from the porous conductor layer across the electron transport layer and the light emitting device, the second bias voltage having a sign opposite to a sign of the first bias voltage,
wherein infrared photons incident on the photoactive layer produce visible photons from the light emitting device with a conversion efficiency exceeding 1000%.

US Pat. No. 10,483,324

3D VERTICAL MEMORY ARRAY CELL STRUCTURES AND PROCESSES

1. A method for forming a vertical memory structure, comprising:forming a layer stack comprising word line layers separated by insulator layers;
forming an opening through the layer stack to expose internal surfaces of the word line layers;
depositing a selector material directly on the internal surfaces of the word line layers, wherein the depositing forms segments of the selector material, and wherein each segment is deposited on a corresponding internal surface of a respective word line layer;
depositing a memory material directly on the selector material; and
depositing bit line material directly on the memory material.

US Pat. No. 10,483,323

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

12. A three-dimensional semiconductor device, comprising:a substrate; and
a cell array comprising:
a plurality of electrodes vertically stacked on the substrate, the plurality of electrodes forming m number of stepwise stacks at ends of the plurality of electrodes in a first direction;
a plurality of dummy electrodes vertically stacked and adjacent to the plurality of electrodes in a second direction, the second direction being perpendicular to the first direction, the plurality of dummy electrodes forming n number of stepwise stacks in the second direction;
a capping insulating layer covering the plurality of electrodes and the plurality of dummy electrodes; and
a plurality of contact plugs penetrating the capping insulating layer and contacting the plurality of electrodes at each step of the m number of stepwise stacks,
wherein the m and n are natural numbers equal to or greater than two, and the m is greater than n.

US Pat. No. 10,483,322

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A memory device, comprising:a plurality of transistors;
a first inter-layer dielectric layer over the transistors;
a plurality of first conductive features embedded in the first inter-layer dielectric layer;
a plurality of memory structures respectively over the first conductive features, wherein each of the memory structures has a top electrode, a bottom electrode coupled electrically to a respective one of the first conductive features, and a resistive material layer sandwiched between the top and bottom electrodes;
a filler in between the memory structures; and
a second inter-layer dielectric layer over the filler and the memory structures, the second inter-layer dielectric layer and the filler forming an interface, the interface extending from one of the memory structures to another of the memory structures, wherein the second inter-layer dielectric layer has a first portion over the filler and the memory structures and a second portion around the first portion, and a top surface of the first portion of the second inter-layer dielectric layer is higher than a top surface of the second portion of the second inter-layer dielectric layer.

US Pat. No. 10,483,321

HIGH DENSITY MEMORY ARCHITECTURE USING BACK SIDE METAL LAYERS

Intel Corporation, Santa...

1. A microelectronic memory comprising:a substrate comprising a single material structure, wherein the substrate has a front surface and an opposing back surface,
a source line directly contacting the substrate back surface; and
a memory bitcell transistor on the substrate front surface.

US Pat. No. 10,483,320

MAGNETORESISTIVE STACK WITH SEED REGION AND METHOD OF MANUFACTURING THE SAME

Everspin Technologies, In...

1. A magnetoresistive stack comprising:a seed region disposed at least partially on an electrically conductive material, wherein the seed region includes an alloy layer including at least 99 atomic percent (at. %) of nickel and chromium and comprises:
a first alloy layer including nickel and chromium in contact with the electrically conductive material;
a second alloy layer including nickel and chromium in contact with a fixed magnetic region; and
at least one auxiliary layer disposed between the first alloy layer and the second alloy layer;
the fixed magnetic region disposed at least partially on and in contact with the seed region, wherein the fixed magnetic region includes a synthetic antiferromagnetic structure comprising:
a first ferromagnetic region disposed on and in contact with the seed region;
a coupling layer disposed on and in contact with the first ferromagnetic region; and
a second ferromagnetic region disposed on and in contact with the coupling layer;
one or more dielectric layers disposed on and in contact with the second ferromagnetic region; and
a free magnetic region disposed on the one or more dielectric layers.

US Pat. No. 10,483,318

SOLID STATE LIGHTING DEVICES WITH OPPOSING EMISSION DIRECTIONS

CREE, INC., Durham, NC (...

1. A solid-state lighting device comprising:a primary light-extraction face and a secondary light-extraction face that generally opposes the primary light-extraction face;
a plurality of light-emitting diodes (LEDs) supported by a light-transmissive submount;
at least one light-segregation element positioned between different LEDs of the plurality of LEDs proximate to the primary light-extraction face; and
at least one lumiphoric material arranged between different LEDs of the plurality of LEDs registered with the at least one light-segregation element, wherein the at least one lumiphoric material is arranged between the at least one light-segregation element and the secondary light-extraction face.

US Pat. No. 10,483,317

IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. An image sensor comprising:a first substrate including a device region in which a plurality of unit pixels are disposed, a first residual scribe lane region surrounding the device region, and having a first surface and a second surface opposite the first surface;
a barrier structure penetrating the first residual scribe lane region of the first substrate;
a first structure including a first conductive film and a first insulating film, the first surface of the first substrate being on the first structure, a bottommost surface of the barrier structure being on top of a top surface of the first structure;
a second substrate including a second residual scribe lane region facing the first residual scribe lane region, and having a front surface and a rear surface; and
a second structure on the front surface of the second substrate, the second structure facing the first surface of the first substrate, the second structure being bonded to the first structure, and the second structure including a second conductive film and a second insulating film.

US Pat. No. 10,483,316

FABRICATION AND OPERATION OF MULTI-FUNCTION FLEXIBLE RADIATION DETECTION SYSTEMS

mPower Technology, Inc., ...

1. A radiation detector comprising:an array of singulated microscale semiconductor sensors disposed on a flexible substrate; and
at least one type of conversion layer;
wherein said conversion layer is sufficiently thin to enable the detector to flex in accordance with said substrate;
wherein the radiation detector is formable into an arbitrary three-dimensional shape; and
wherein the radiation detector comprises a rigid backer to maintain said shape of the radiation detector.

US Pat. No. 10,483,315

IMAGE SENSOR CONFIGURED FOR DUAL MODE OPERATION

Delta ID, Inc., Fremont,...

1. An image sensor comprising an image sensor substrate having an array of pixels formed thereon, said array of pixels comprising:a first pixel region comprising a contiguous first array of pixels, said first array of pixels comprising only pixels configured for peak sensitivity to wavelength(s) below 700 nm;
and
a second pixel region comprising a contiguous second array of pixels of at least 300 pixels, said second array of pixels comprising pixels of a first pixel type and pixels of a second pixel type, wherein
pixels of the first pixel type are configured for peak sensitivity to wavelength(s) between 700 nm and 1000 nm; and
pixels of the second pixel type are configured for peak sensitivity to wavelength(s) below 700 nm,
wherein the first pixel region surrounds the second pixel region such that an average distance of pixels within the second pixel region from a center of the image sensor is less than an average distance of pixels within the first pixel region from the center of the image sensor.

US Pat. No. 10,483,314

IMAGING DEVICE CAMERA SYSTEM AND DRIVING METHOD OF THE SAME

SONY SEMICONDUCTOR SOLUTI...

1. An imaging device comprising a pixel array on a substrate in which a plurality of pixels are arranged in an array, the plurality of pixels configured to convert light into electric signals, the plurality of pixels comprising a plurality of color pixels and at least one clear pixel, wherein:the plurality of color pixels include at least two of (i) a first color pixel with a first filter effective to cause the first color pixel to have a peak spectral sensitivity for red light, (ii) a second color pixel with a second filter effective to cause the second color pixel to have a peak spectral sensitivity for blue light, or (iii) a third color pixel with a third filter effective to cause the third color pixel to have a peak spectral sensitivity for green light;
the clear pixel has a fourth filter effective to cause the clear pixel to have a high transmittance to white light;
the plurality of pixels include respective micro lenses disposed at light incident sides of the pixels;
the first, second, third color filters are each thicker in a depth direction of the pixels than the fourth filter; and
the clear pixel is adjacent one of the plurality of color pixels.

US Pat. No. 10,483,313

SOLID-STATE IMAGE SENSOR AND ELECTRONIC DEVICE

Sony Corporation, Tokyo ...

1. An imaging device comprising:a first chip and a second chip stacked to the first chip, wherein the second chip includes, a plurality of 8-pixel share units, wherein each 8-pixel share unit of the plurality of 8-pixel share units includes:
first to fourth photodiode regions sharing a first floating diffusion and fifth to eighth photodiode regions sharing a second floating diffusion, the first to eighth photodiode regions sharing a single amplification transistor and a reset transistor; and
a power supply line for supplying a drain of the reset transistor with a power supply voltage, the power supply line including a first line disposed on a first layer and extending along a first direction and a second line disposed on a second layer and extending along a second direction, the first and second lines being coupled to each other and pass through the 8-pixel share unit.

US Pat. No. 10,483,312

BACKSIDE-ILLUMINATED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR SENSOR AND THE MANUFACTURING METHOD THEREOF

HUAIAN IMAGING DEVICE MAN...

1. A backside-illumination complementary metal oxide semiconductor (CMOS) image sensor, comprisinga semiconductor substrate including a first side for receiving incident light and a second side opposite to the first side; and
a reflector disposed at the second side of the semiconductor substrate,
wherein the reflector is configured to reflect incident light that transmits through the semiconductor substrate back into the semiconductor substrate, and
wherein the reflector is made of an electrically conductive material and is electrically grounded.

US Pat. No. 10,483,311

SOLID-STATE IMAGE PICKUP DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGE PICKUP DEVICE, AND IMAGE PICKUP DEVICE

CANON KABUSHIKI KAISHA, ...

1. A solid-state image pickup device, comprising:a semiconductor substrate including
a first photoelectric conversion portion having a first semiconductor region of a first conductivity type that collects signal charges,
a second photoelectric conversion portion having a second semiconductor region of the first conductivity type that collects signal charges, and
a third semiconductor region of a second conductivity type different from the first conductivity type,
wherein the third semiconductor region is arranged between the first semiconductor region and the second semiconductor region in plan view with respect to a first surface of the semiconductor substrate, and
an impurity concentration of the third semiconductor region has a local minimum value and an impurity concentration of the first semiconductor region has a local maximum value in a depth direction from the first surface to a second surface opposite to the first surface, and a depth range from a position 0.5 ?m shallower than a position indicating the local minimum value to a position 0.5 ?m deeper than the position indicating the local minimum value and a depth range from a position 0.5 ?m shallower than a position indicating the local maximum value to a position 0.5 ?m deeper than the position indicating the local maximum value are overlapped with each other.

US Pat. No. 10,483,308

REDUCING THICKNESS OF MODULE IN SOLID STATE IMAGING DEVICE

SONY CORPORATION, Tokyo ...

1. A camera module, comprising:a metal plate;
an image sensor on the metal plate;
a wiring substrate on the metal plate, wherein
the wiring substrate includes a plurality of wiring layers,
the wiring substrate comprises one of a ceramic material or organic material,
the metal plate comprises copper,
the metal plate has no wiring layer of the plurality of wiring layers,
the wiring substrate is in contact with the metal plate,
the wiring substrate extends entirely over a first region of the metal plate that surrounds a second region of the metal plate,
the image sensor is on the second region,
the image sensor is electrically connected to the wiring substrate,
the wiring substrate includes a first edge and a second edge, and
the wiring substrate is on the metal plate such that a width between the first edge and the second edge of the wiring substrate is equal to a width of the metal plate in a sectional view; and
a lens unit on the wiring substrate.

US Pat. No. 10,483,307

IMAGING DEVICE

CANON KABUSHIKI KAISHA, ...

1. An imaging device comprising:a substrate;
a pixel array in which a plurality of pixels are arranged in a two-dimensional manner on the substrate, wherein each of the pixels includes a photoelectric conversion unit configured to accumulate charges generated from an incident light, a charge holding unit configured to hold the charges transferred from the photoelectric conversion unit, and an amplification unit having an input node that receives the charges transferred from the charge holding unit; and
a light-shielding portion arranged to cover at least the charge holding unit,
wherein the photoelectric conversion unit and the charge holding unit included in one of the pixels are aligned in a first direction in a top view from a direction orthogonal to the substrate,
wherein a plurality of the charge holding units of the plurality of the pixels that are adjacent to each other are aligned in a second direction intersecting the first direction in the top view, and
wherein the light-shielding portion extends in the second direction and over the plurality of the charge holding units, and covers a region between the plurality of the charge holding units,
wherein each of the pixels further includes a plurality of contacts that connect electrodes provided to the substrate and a wiring layer formed above the substrate,
wherein the plurality of contacts are formed in a region between the plurality of the charge holding units aligned in the first direction in the top view, and
wherein the light-shielding portion includes a part extending in the first direction and provided between the photoelectric conversion unit and the plurality of contacts.

US Pat. No. 10,483,304

IMAGE SENSOR

Samsung Electronics Co., ...

1. An image sensor, comprising:a light-sensing element that generates charge in response to incident light;
a storage diode formed in a substrate, wherein the storage diode stores the charge generated by the light-sensing element;
a floating diffusion region formed in a top surface of the substrate and spaced apart from the storage diode;
a transfer gate at least partially buried under the top surface of the substrate, wherein the transfer gate controls both the transfer of the charge from the light-sensing element to the storage diode, and the transfer of the charge from the storage diode to the floating diffusion region.

US Pat. No. 10,483,301

IMAGING APPARATUS AND IMAGING SYSTEM

Canon Kabushiki Kaisha, ...

1. An imaging apparatus comprising:a substrate including a plurality of pixel circuits;
first, second, third, and fourth electrodes disposed on the substrate; and
a semiconductor layer disposed on the substrate and including a first portion and a second portion,
wherein
the first portion is disposed between the first electrode and the second electrode and is formed vertically above the second electrode and within a boundary of the second electrode,
the second portion is disposed between the third electrode and fourth electrode and is formed vertically above the fourth electrode and within a boundary of the fourth electrode,
each of the plurality of pixel circuits includes an amplification transistor configured to output a signal based on charge generated in the semiconductor layer, and
the charge generated in the semiconductor layer is accumulated in the first portion, and thereafter transferred from the first portion to the second portion in a first direction parallel to a surface of the substrate.

US Pat. No. 10,483,298

MULTI-SENSOR OPTICAL DEVICE FOR DETECTING CHEMICAL SPECIES AND MANUFACTURING METHOD THEREOF

STMicroelectronics S.R.L....

1. A device, comprising:a substrate;
a semiconductor layer on the substrate, the semiconductor layer having a first portion with a first thickness and a second portion with a second thickness, the first portion having a first surface;
a first optical sensor in the first portion, the first optical sensor including:
a first anode recessed in the first portion, the first anode having an exposed surface coplanar with the first surface; and
a second optical sensor in the second portion.

US Pat. No. 10,483,294

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. An array substrate, comprising a gate electrode layer, an active layer, and a source-drain electrode layer that are disposed on a substrate,wherein the substrate comprises a storage capacitance region thereon, in the storage capacitance region, projections of the gate electrode layer and the active layer on the substrate are at least partially overlapped, and projections of the active layer and the source-drain electrode layer on the substrate are at least partially overlapped,
wherein the array substrate further comprises a gate insulation layer between the gate electrode layer and the active layer and an etch-stopper layer between the active layer and the source-drain electrode layer,
wherein the etch-stopper layer is an insulating layer, and
wherein, in the storage capacitance region, the gate electrode layer and the active layer are spatially separated by the gate insulation layer so as to form a capacitor between them, and the active layer and the source-drain electrode layer are spatially separated by the etch-stopper layer so as to form another capacitor between them,
wherein the gate electrode layer comprises a portion in the storage capacitance region, the gate insulation layer comprises a portion in the storage capacitance region, the active layer comprises a portion in the storage capacitance region, the etch-stopper layer comprises a portion in the storage capacitance region, and the source-drain electrode layer comprises a portion in the storage capacitance region,
wherein the substrate further comprises a thin film transistor region, and a thickness of the gate insulation layer formed in the storage capacitance region is smaller than a thickness of the gate insulation layer formed in the thin film transistor region,
wherein the gate electrode layer at a contact hole in the gate insulation layer is in contact with the source-drain electrode layer.

US Pat. No. 10,483,292

ARRAY SUBSTRATE AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a plurality of signal lines;
a plurality of secondary discharging lines arranged substantially parallel to each other, each of the plurality of secondary discharging lines being arranged to cross the plurality of signal lines;
a plurality of first electrostatic discharging units arranged in one-to-one correspondence with the plurality of signal lines and arranged at an identical side of an entirety of the plurality of secondary discharging lines; and
a primary discharging line connected to the plurality of secondary discharging lines,
wherein a first end of each of the plurality of first electrostatic discharging units is connected to a corresponding signal line of the plurality of signal lines, and a second end of the each of the plurality of first electrostatic discharging units is connected to one of the plurality of secondary discharging lines,
each first electrostatic discharging unit of the plurality of first electrostatic discharging units comprises a first thin film transistor (TFT), a second TFT, and a third TFT;
a gate electrode and a source electrode of the first TFT are short-circuited and connected to one of the plurality of signal lines corresponding to the each first electrostatic discharging unit, and a drain electrode of the first TFT is connected to a source electrode of the second TFT and a gate electrode of the third TFT;
a gate electrode and a drain electrode of the second TFT are short-circuited and connected to the one of the plurality secondary discharging lines corresponding to the each first electrostatic discharging unit;
a source electrode of the third TFT is directly connected to the one of the plurality of signal lines, and a drain electrode of the third TFT is directly connected to the one of the plurality of secondary discharging lines; and
an extension portion of the one of the plurality of signal line corresponding to the each first electrostatic discharging unit is formed into the source electrode of the first TFT and the source electrode of the third TFT, the source electrode of the first TFT is connected to the gate electrode of the first TFT through a first via-hole, an active region of the first TFT is formed above the gate electrode of the first TFT, and the source electrode and the drain electrode of the first TFT are in direct contact with the active region of the first TFT so as to form a source region and a drain region of the first TFT.

US Pat. No. 10,483,291

FLEXIBLE DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate including a display area, the display area including a plurality of pixels configured to display an image and a pad area adjacent to the display area and configured to transfer electrical signals, wherein at least a portion of the pad area is bent;
an insulating layer disposed on the substrate and including a groove in the pad area, and a cutoff portion, wherein the groove includes a first sidewall adjacent the display area and a second sidewall opposite the first sidewall;
a plurality of peripheral wires dispose on the insulating layer; and
the cutoff portion disposed between adjacent peripheral wires,
wherein the cutoff portion extends from the first sidewall to the second sidewall in a first direction, and wherein a length of the cutoff portion in the first direction is less than a width of the groove in the first direction.

US Pat. No. 10,483,288

LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE USING THE SAME

Semiconductor Energy Labo...

1. A light-emitting device comprising:a substrate;
an oxide semiconductor over the substrate, the oxide semiconductor comprising indium, zinc, and gallium;
a gate electrode over the oxide semiconductor;
a first insulating film over the gate electrode, the first insulating film comprising an inorganic insulating material;
a source electrode and a drain electrode over the first insulating film, the source electrode and the drain electrode each comprising a region in contact with the oxide semiconductor;
a color filter over the first insulating film;
a light-emitting element over the color filter, the light-emitting element electrically connected to one of the source electrode and the drain electrode; and
an organic resin over the light-emitting element,
wherein the color filter is positioned between the first insulating film and the light-emitting element,
wherein the color filter comprises a region overlapping with the light-emitting element,
wherein the color filter does not overlap with the oxide semiconductor and the gate electrode,
wherein the light-emitting element comprises:
a first electrode;
a second electrode over the first electrode;
a charge generation layer between the first electrode and the second electrode;
a first light-emitting layer between the first electrode and the charge generation layer;
a second light-emitting layer between the charge generation layer and the second electrode; and
a third light-emitting layer between the charge generation layer and the second electrode,
wherein the first light-emitting layer comprises a blue-emissive fluorescent substance,
wherein the second light-emitting layer comprises a first phosphorescent substance,
wherein the first phosphorescent substance is a red-emissive phosphorescent substance,
wherein the third light-emitting layer comprises a second phosphorescent substance and overlaps with the second light-emitting layer, and
wherein the first electrode is positioned over the one of the source electrode and the drain electrode.

US Pat. No. 10,483,285

ELEMENT SUBSTRATE AND DISPLAY DEVICE

Innolux Corporation, Mia...

4. A display device, comprising:an element substrate comprising a substrate and an element layer, wherein the element layer is disposed on the substrate, the element layer comprises a plurality of active elements, the plurality of active elements respectively comprises:
a gate disposed on the substrate;
a gate insulating layer disposed on the substrate and overlapping the gate;
a metal oxide semiconductor layer disposed on the gate insulating layer;
a source and a drain disposed on the metal oxide semiconductor layer,
wherein the metal oxide semiconductor layer has a first portion and a second portion, the source and the drain overlap the first portion, the source and the drain do not overlap the second portion, the first portion has a first thickness, the second portion has a second thickness, the first thickness is greater than the second thickness,
wherein a difference between the first thickness and the second thickness is greater than or equal to 200 ? and less than or equal to 600 ?, and
wherein the source and the drain respectively comprise a first layer and a second layer, the first layer is disposed between the second layer and the metal oxide semiconductor layer, a material of the first layer comprises titanium nitride, a distance is between an edge of the first layer and an edge of the second layer, and the distance is greater than or equal to 0.1 ?m and less than or equal to 0.3 ?m;
an opposing substrate disposed relative to the element substrate; and
a display layer disposed between the element substrate and the opposing substrate.

US Pat. No. 10,483,282

VNAND TENSILE THICK TEOS OXIDE

Applied Materials, Inc., ...

1. A method for processing a substrate, comprising:positioning a substrate having a gate stack deposited thereon, the gate stack comprising a plurality of first layers and a plurality of second layers disposed alternatingly in a vertical arrangement perpendicular to a top surface of the substrate;
forming a first oxide layer on exposed surfaces of the gate stack using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas;
after the first oxide layer has reached a predetermined thickness, ramping up the first RF power while continuing the flow of the TEOS gas and the first oxygen-containing gas to form an initiation layer of oxide over the first oxide layer;
after the initiation layer has reached a predetermined thickness, increasing the RF power used to form the initiation layer and turning off the flow of the TEOS gas to form a transition layer of oxide on the initiation layer; and
forming a second oxide layer over the transition layer using a second RF power that is different from the first RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

US Pat. No. 10,483,281

SEMICONDUCTOR MEMORY DEVICE

SK hynix Inc., Gyeonggi-...

1. A method of manufacturing a semiconductor memory device comprising:forming bit lines on a substrate, wherein the substrate includes a cell array region, a word line contact region and a page buffer region;
wherein the page buffer region is coupled to the cell array region through bit lines,
wherein the bit lines include a first bit line and a second bit line, and
wherein the second bit line has a curved structure toward the word line contact region and a curvedness of the second bit line is greater than a curvedness of the first bit line.

US Pat. No. 10,483,280

METHOD OF FORMING STAIRCASE STRUCTURES FOR THREE-DIMENSIONAL MEMORY DEVICE DOUBLE-SIDED ROUTING

YANGTZE MEMORY TECHNOLOGI...

1. A method for forming a three-dimensional (3D) memory device, comprising:forming a first dielectric layer on a substrate and a first photoresist layer on the first dielectric layer;
patterning a recess through the first dielectric layer to the substrate by a plurality cycles of trimming the first photoresist layer and etching the first dielectric layer;
forming a plurality of dielectric/sacrificial layer pairs filling in the recess;
forming a second photoresist layer on a top surface of the plurality of dielectric/sacrificial layer pairs;
patterning the plurality of dielectric/sacrificial layer pairs by a plurality cycles of trimming the second photoresist layer and etching the plurality of dielectric/sacrificial layer pairs;
forming a second dielectric layer covering the patterned plurality of dielectric/sacrificial layer pairs; and
forming a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the patterned dielectric/sacrificial layer pairs.

US Pat. No. 10,483,277

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a substrate;
a plurality of interconnect portions, at least one portion of the plurality of interconnect portions being provided inside the substrate, each of the plurality of interconnect portions extending in a first direction along a surface of the substrate, the plurality of interconnect portions being arranged along a second direction, the second direction crossing the first direction and being along the surface of the substrate, the plurality of interconnect portions having a line-and-space arrangement arranged along the second direction;
a conductive layer provided on the plurality of interconnect portions;
a stacked body provided on the conductive layer, the stacked body including a plurality of electrode layers stacked to be separated from each other, each of the plurality of electrode layers extending in the second direction; and
a plurality of columnar portions provided inside the stacked body, each of the plurality of columnar portions including a semiconductor portion and a charge storage film, the semiconductor portion extending in a stacking direction of the plurality of electrode layers, the charge storage film being provided between the semiconductor portion and the stacked body,
the plurality of electrode layers being disposed continuously over two or more of the plurality of interconnect portions arranged along the second direction,
one interconnect portion of the plurality of interconnect portions overlapping two or more sets of the plurality of electrode layers when viewed from the stacking direction, the two or more sets of the plurality of electrode layers extending in the second direction respectively and being separated in the first direction from each other.

US Pat. No. 10,483,276

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:forming, over a first surface of a semiconductor substrate located in a region where a first transistor is to be formed, a first gate insulating film having a first oxide film, a first nitride film placed over the first oxide film, and a second oxide film placed over the first nitride film; and
forming a second gate insulating film over the first surface located in a region where a second transistor is to be formed,
wherein the second oxide film includes a first layer and a second layer placed over the first layer,
wherein the first gate insulating film formation step includes a step of forming a second nitride film placed over the first layer, and
wherein the second layer is formed by oxidation of at least a portion of the second nitride film,
wherein the second gate insulating film is formed by thermal oxidation,
wherein the method further comprises forming, over the first surface located in a region where a third transistor is to be formed, a third gate insulating film thinner than the second gate insulating film,
wherein the portion of the second nitride film remains at the time of formation of the second gate insulating film,
wherein the second nitride film oxidized at the time of formation of the second gate insulating film is removed by etching prior to the third gate insulating film formation step, and
wherein the portion of the second nitride film which has remained at the time of formation of the second gate insulating film is oxidized into the second layer at the time of formation of the third gate insulating film.

US Pat. No. 10,483,274

THREE-DIMENSIONAL SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A three-dimensional (3D) semiconductor device, comprising:an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a plurality of electrodes which are stacked in a direction perpendicular to a top surface of the substrate,
wherein the plurality of the electrodes respectively include pads which define a stepped structure in the second region of the substrate;
dummy pillars penetrating the pads and a portion of the electrode structure under the pads; and
contact plugs electrically connected to the pads, respectively,
wherein at least one of the dummy pillars penetrate a boundary between adjacent pads.

US Pat. No. 10,483,273

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) providing a semiconductor substrate including a first region for a first transistor, a second region for a nonvolatile memory cell and a third region for a second transistor;
(b) forming a first gate insulating film for the first transistor over a main surface of the semiconductor substrate in the first region;
(c) after the step (b), forming a second gate insulating film including a charge trapping layer for the nonvolatile memory cell over the main surface of the semiconductor substrate in the second region;
(d) after the step (c), forming a third gate insulating film for the second transistor over the main surface of the semiconductor substrate in the third region;
(e) after the step (d), forming a first film over the main surface of the semiconductor substrate covering the first, second and third gate insulating films; and
(f) after the step (e), patterning the first film for forming a first gate electrode for the first transistor in the first region, a second gate electrode for the nonvolatile memory cell in the second region and a third gate electrode for the second transistor in the third region,
wherein a thickness of the first gate insulating film for the first transistor is larger than that of the third gate insulating film for the third transistor,
wherein the semiconductor substrate provided in the step (a) and located in the third region has a SOI structure having a supporting substrate, an insulating layer over the supporting substrate, and a semiconductor layer over the insulating layer,
wherein the semiconductor substrate provided in the step (a) and located in each of the first and second region has neither the insulating layer nor the semiconductor layer while having the supporting substrate,
wherein, in the step (b), the first gate insulating film is formed over the supporting substrate located in the first region,
wherein, in the step (c), the second gate insulating film is formed over the supporting substrate located in the second region,
wherein, in the step (d), the third gate insulating film is formed over the semiconductor layer in the third region, and
wherein the third gate electrode is formed over the semiconductor layer located in the third region via the third gate insulating film.

US Pat. No. 10,483,270

INTEGRATED ASSEMBLIES AND METHODS OF FORMING INTEGRATED ASSEMBLIES

Micron Technology, Inc., ...

1. An integrated assembly, comprising:a first channel structure extending substantially vertically;
a second channel structure extending substantially vertically; each of the first and the second semiconductor channel structures having a first doped channel region interfacing a second doped channel region at a boundary region, the first doped channel regions being differently doped relative to the second doped channel regions; and
a gating structure extending between the first channel structure and the second channel structure and having a first gating region extending along the first channel structure, a second gating region extending along the second channel structure, and an interconnecting region extending laterally between the first and second gating regions, the interconnecting region being vertically narrower than first and second the gating regions.

US Pat. No. 10,483,269

EEPROM DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device comprising:a semiconductor substrate;
a first dielectric layer having a first thickness on the semiconductor substrate;
a first opening having a first width in the first dielectric layer;
a second dielectric layer having a second thickness disposed in a middle region of the first opening; and
a third dielectric layer having a first portion and a second portion disposed on opposite sides of second dielectric layer, the first portion and the second portion having a second width smaller than the first width, and the third dielectric layer having a third thickness smaller than the first thickness and the second thickness.

US Pat. No. 10,483,265

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:a hybrid pillar-type bottom electrode including a cylindrical first bottom electrode and a pillar-type second bottom electrode filling a cylindrical inside of the cylindrical first bottom electrode;
a supporter suitable for supporting an outer wall of the hybrid pillar-type bottom electrode;
a dielectric layer formed over the hybrid pillar-type bottom electrode and the supporter; and
a top electrode disposed over the dielectric layer,
wherein the cylindrical first bottom electrode includes:
a cylinder body; and
a cylinder head disposed on the cylinder body and having a sloped side wall to have a wider upper surface than the cylinder body.

US Pat. No. 10,483,264

FINFET CMOS DEVICE INCLUDING SINGLE DIFFUSION BREAK IN EACH OF NMOS AND PMOS REGIONS

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a first MOS region comprises a PMOS region and a second MOS region comprises a NMOS region on a substrate:
a first fin-shaped structure on the PMOS region;
a first single diffusion break (SDB) structure in the first fin-shaped structure;
a first gate structure on the first SDB structure;
a second gate structure on the first fin-shaped structure, wherein the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region of the first MOS region;
a second fin-shaped structure on the NMOS region;
a second SDB structure in the second fin-shaped structure; and
a third gate structure on the second SDB structure and a fourth gate structure on the second fin-shaped structure, wherein the third gate structure and the fourth gate structure are of same material, the third gate structure disposed directly on top of the second SDB structure is a metal gate and the fourth gate structure disposed on the second fin-shaped structure is also a metal gate in the NMOS region of the second MOS region, wherein each of the metal gates on the PMOS region and the NMOS region is transformed from a dummy gate, while the polysilicon gate is an active gate made of polysilicon.

US Pat. No. 10,483,263

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A manufacturing method for a semiconductor device, comprising:providing a substrate structure, wherein the substrate structure comprises:
a semiconductor substrate;
a single fin protruding from the semiconductor substrate, wherein trenches are formed on sides of the fin;
a pad insulator layer for padding the trenches;
a first insulator layer separately formed from the pad insulator layer and partially filling the trenches, wherein the single fin protrudes from the first insulator layer; and
a second insulator layer covering the single fin;
forming a plurality of pseudo gate structures on the second insulator layer, wherein each pseudo gate structure wraps a part of the single fin, wherein each pseudo gate structure comprises a pseudo gate located on the second insulator layer, wherein the plurality of pseudo gate structures comprises at least a first pseudo gate structure, a second pseudo gate structure, and a third pseudo gate structure that are spaced from each other, and wherein the second pseudo gate structure and the third pseudo gate structure are located at two opposite edge corners of the single fin and the first pseudo gate structure is a only pseudo gate structure disposed between the second pseudo gate structure and the third pseudo gate structure, and a first part of each of the second pseudo gate structure and the third pseudo gate is on and in direct contact with the first insulator layer and a second part of each of the second pseudo gate structure and the third pseudo gate structure is on and in direct contact with the second insulator layer;
forming, above the first insulator layer and the second insulator layer, spacers at two sides of each of the second pseudo gate structure and the third pseudo gate structure, where a bottom face of one of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the first insulator layer whereas a bottom face of another of the spacers for each of the second pseudo gate structure and the third pseudo gate structure is in direct contact with the second insulator layer;
etching, after forming the spacers, the second insulator layer and at least a part of the single fin that are not covered by the spacers and the pseudo gates, to form recesses in the single fin; and
forming at least one source or drain in the recesses.

US Pat. No. 10,483,261

INTEGRATED CIRCUIT HAVING CHEMICALLY MODIFIED SPACER SURFACE

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC), comprising:sidewall spacers having a second dielectric material on a first dielectric material, wherein the second dielectric material comprises carbon and silicon and the first dielectric material comprises silicon and another element besides carbon, and wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material,
wherein the transition region has a composition that includes silicon, carbon and the another element besides carbon, and
wherein at a widest point of the sidewall spacers, the transition region is thicker than the second dielectric material.

US Pat. No. 10,483,259

SERIES RESISTOR OVER DRAIN REGION IN HIGH VOLTAGE DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a transistor, comprising:
a ring-shaped drain region disposed in a substrate, the ring-shaped drain region having an inner edge and an outer edge;
a channel region disposed in the substrate and surrounding the ring-shaped drain region;
a source region disposed in the substrate and surrounding the channel region, wherein the channel region separates the drain region from the source region; and
a gate electrode arranged over the channel region, the gate electrode separated from the channel region by a gate dielectric, and having an inner edge proximate to the drain region; and
a resistor structure arranged in series with the transistor, the resistor structure arranged over the substrate and perimeterally bounded by the inner edge of the ring-shaped drain region, the resistor structure having a first end and a second end which are connected by a curved or polygonal path of resistive material, wherein the first end is electrically coupled to the ring-shaped drain region, and the second end is electrically-isolated from the gate electrode and the source region.

US Pat. No. 10,483,254

ELECTRONIC MODULE AND SEMICONDUCTOR PACKAGE DEVICE

ADVANCED SEMICONDUCTOR EN...

1. An electronic module, comprising:a first sub-module including a first substrate, a first electronic component disposed on the first substrate and a first electrode; and
a second sub-module including a second substrate, a second electronic component disposed on the second substrate and a second electrode spaced from the first electrode,
wherein the second electrode faces the first electrode to form a capacitor for transmitting an alternating current (AC) signal between the first sub-module and the second sub-module,
the first sub-module further comprises a converter configured to convert a first direct current (DC) signal to a converted AC signal and to transmit the converted AC signal to the second sub-module through AC coupling between the first electrode of the first sub-module and the second electrode of the second sub-module; and
the second sub-module further comprises a converter configured to covert the converted AC signal to a second DC signal.

US Pat. No. 10,483,253

DISPLAY WITH EMBEDDED PIXEL DRIVER CHIPS

Apple Inc., Cupertino, C...

1. A display panel comprising:an array of pixel driver chips embedded front side up in an insulator layer;
a front side redistribution layer (RDL) spanning across and in electrical connection with front sides of the array of pixel driver chips; and
an array of light emitting diodes (LEDs) bonded to the front side RDL, the array of LEDs arranged in an array of pixels, wherein each pixel driver chip is to switch and drive a plurality of LEDs in the array of LEDs for a plurality of pixels;
wherein each pixel driver chip has a minimum x-y dimension that that is larger than a maximum pitch in the x-y dimension between adjacent LEDs of the array of LEDs, and each pixel driver chip is characterized by pixel driver chip area in x-y dimensions that is directly underneath an entire LED area in the x-y dimensions for each of a corresponding plurality of LEDs of the array of LEDs.

US Pat. No. 10,483,251

POWER MODULE FOR DRIVETRAIN OF AN ELECTRIC VEHICLE

CHONGQING JINKANG NEW ENE...

1. A power module for a drivetrain of an electric vehicle, the power module comprising:a first polarity terminal having a first surface and a second surface;
an isolation layer having a first surface and a second surface, the first surface of the isolation layer coupled with the second surface of the first polarity terminal;
a second polarity terminal having a first surface and a second surface, the first surface of the second polarity terminal coupled with the second surface of the isolation layer;
a high side switch;
a first current path that electrically couples the first polarity terminal with the high side switch;
a low side switch;
a second current path that electrically couples the second polarity terminal with the low side switch;
a power loop formed from the first current path and the second current path;
the power loop having an overlapping current path formed from the first current path disposed in parallel with respect to the second current path with the first polarity terminal of the first current path disposed parallel with respect to the second polarity terminal of the second current path; and
the power loop having an overall inductance value equal to a sum of a self-inductance of the first current path and a self-inductance of the second current path minus a mutual inductance value of the overlapping current path.

US Pat. No. 10,483,247

SEMICONDUCTOR DEVICE, DISPLAY PANEL, AND METHOD FOR MANUFACTURING DISPLAY PANEL

LG Innotek Co., Ltd., Se...

1. A method for manufacturing a display panel, the method comprising:forming a semiconductor layer on a growth substrate, the semiconductor layer comprising an n-type semiconductor layer, an active layer formed on the n-type semiconductor layer, and a p-type semiconductor layer formed on the active layer;
performing an isolation process of isolating the semiconductor layer into a plurality of light-emitting structures to expose the n-type semiconductor layer between the plurality of light-emitting structures;
forming a protection layer on side and upper surfaces of each of the plurality of light emitting structures;
forming a p-type contact layer contacting the p-type semiconductor layer of each of the plurality of light-emitting structures;
forming a sacrificial layer between the side surfaces of the plurality of light-emitting structures and on the p-type contact layer;
attaching a first temporary substrate on the sacrificial layer by using an adhesion layer and separating the growth substrate;
etching the n-type semiconductor layer provided between the plurality of light-emitting structures to expose the sacrificial layer disposed between the plurality of light-emitting structures;
forming an n-type contact layer contacting an upper surface of the n-type semiconductor layer;
removing the sacrificial layer disposed between the plurality of light-emitting structures to expose the adhesion layer;
separating a portion of the plurality of light-emitting structures from the first temporary substrate so as to be arranged a predetermined interval on a second temporary substrate; and
collectively attaching the light-emitting structures, which are arranged on the second temporary substrate, on a panel and removing the second temporary substrate.

US Pat. No. 10,483,245

LIGHT BAR, EDGE-TYPE BACKLIGHT MODULE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A light bar, comprising: a circuit board and an integrated light emitting body arranged on the circuit board,wherein the integrated light emitting body comprises a package and a plurality of light sources, and the package is configured to package the plurality of light sources,
wherein a light emitting surface of the integrated light emitting body is perpendicular to a surface of the circuit board on which the integrated light emitting body is mounted, a distance between the light emitting surface and an edge of the surface of the circuit beard on which the integrated light emitting body is mounted, close to the light emitting surface and parallel to the light emitting surface is W1, and 0.3 mm?W1?1.0 mm.

US Pat. No. 10,483,242

SEMICONDUCTOR DEVICE

ULTRAMEMORY INC., Tokyo ...

1. A semiconductor device comprising:a plurality of memory chips, that are laminated, each of which includes a first transmission/reception coil for communication using inductive coupling, a first lead-out line led out from both ends of the first transmission/reception coil, and a first transmission/reception circuit connected to the first lead-out line, being input and output signals between the first transmission/reception circuit and the first transmission/reception coil; and
an interposer that is provided at one end in a direction in which the plurality of memory chips are laminated and includes, for each of the plurality of memory chips, a second transmission/reception coil which are coupled to the first transmission/reception coil by inductive coupling, a second lead-out line led out from both ends of each of the second transmission/reception coil, and a second transmission/reception circuit connected to the second lead-out line for inputting and outputting signals to and from the second transmission/reception coil,
wherein the plurality of memory chips have a structure in which a plurality of the first transmission/reception circuits are disposed at positions that overlap each other in a plan view and the first transmission/reception coils are disposed in the vicinity of the first transmission/reception circuits at positions that do not overlap each other in a plan view.

US Pat. No. 10,483,240

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOHOKU UNIVERSITY, Senda...

1. A method for manufacturing semiconductor devices comprising:a step of filling a mixture containing metal particles and polymers in a guide; and
a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column that stretches in a stretching direction of the guide from the metal particles, wherein
a pair of the guides is provided so as to extend in a horizontal direction, and
the mixture is filled between the guide and a heat treatment is performed whereby the polymer layer that makes contact with the guides is formed and the metal column that stretches in a horizontal direction is formed so as to be spaced from the guides with the polymer layer interposed therebetween.

US Pat. No. 10,483,238

INK PRINTED WIRE BONDING

STMICROELECTRONICS S.R.L....

1. A device, comprising:a package substrate;
a plurality of contact pads on the package substrate;
a first die coupled to the package substrate;
a first plurality of pillars on the first die; and
a first plurality of ink printed wires, each of the first plurality of ink printed wires electrically coupled between at least one of the plurality of contact pads on the package substrate and at least a corresponding one of the first plurality of pillars on the first die, at least one of the first plurality of ink printed wires having a first width adjacent to the first die and a second width adjacent to the respective at least one of the plurality of contact pads, the first width being different than the second width, wherein the at least one of the first plurality of ink printed wires contacts a top surface and a side surface of one of the first plurality of pillars.

US Pat. No. 10,483,236

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a substrate including an insulating layer, a first conductive layer on a first surface of the insulating layer, a second conductive layer on a second surface of the insulating layer that is opposite to the first surface, a third conductive layer extending in a plane direction of the substrate along the first and second surfaces in the insulating layer, and a via extending in a thickness direction of the substrate in the insulating layer; and
a semiconductor chip disposed on a first principal surface of the substrate above the first surface, wherein the substrate further includes:
a planar detection interconnection provided as part of either the first conductive layer or the third conductive layer, wherein the planar detection interconnection is not part of signal interconnections that are used during operation of the semiconductor chip and is not electrically connected to any circuit of the semiconductor chip, and a width of the planar detection interconnection is smaller than a width of the signal interconnections; and
first and second pads to be connected to part of a ball grid array (BGA) or a land grid array (LGA), the first and second pads provided as part of the second conductive layer and electrically connected to the planar detection interconnection through the via.

US Pat. No. 10,483,235

STACKED ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

WINBOND ELECTRONICS CORP....

1. A method for fabricating a stacked electronic device, comprising:providing a first substrate, wherein the first substrate comprises a wafer, a chip, or a combination thereof;
performing a first three-dimensional (3D) printing to form a first insulating layer and a plurality of first redistribution layers (RDLs) on the first substrate, wherein the plurality of first RDLs is embedded in the first insulating layer and is electrically connected to contacts of the first substrate;
performing a second 3D printing to form a second substrate, a plurality of through-substrate vias (TSVs) and insulating spacers on the first insulating layer simultaneously and respectively by at least three print heads, wherein the plurality of TSVs pass through the second substrate and are electrically connected to the plurality of first RDLs, and the insulating spacers electrically isolate the second substrate from the plurality of TSVs;
performing a third 3D printing to form a second insulating layer and a plurality of second RDLs on the second substrate, wherein the plurality of second RDLs is embedded in the second insulating layer and electrically connected to the plurality of TSVs; and
bonding a plurality of contacts of a third substrate to the plurality of second RDLs, so that the third substrate is mounted onto the second insulating layer.

US Pat. No. 10,483,231

BONDING METHOD OF FIXING AN OBJECT TO A ROUGH SURFACE

Tsinghua University, Bei...

1. A bonding method comprising:placing a sheet structure on a substrate surface of a substrate, wherein a surface roughness of the substrate surface is larger than 1.0 micrometer; the sheet structure comprises a first surface and a second surface opposite to the first surface, the first surface is in direct contact with the substrate surface, and a surface roughness of the second surface is less than or equal to 1.0 micrometer;
laying a carbon nanotube structure on the second surface, wherein the carbon nanotube structure comprises a first portion, a second portion, and a third portion, the first portion and the second portion are connected together by the third portion, the first portion and the second portion extend out of the second surface and are in direct contact with the substrate surface, the third portion is in direct contact with the sheet structure; the carbon nanotube structure comprises a super-aligned carbon nanotube film, the super-aligned carbon nanotube film comprises a plurality of carbon nanotubes, the plurality of carbon nanotubes extends substantially along a same direction, and an extending direction of the plurality of carbon nanotubes is substantially parallel to the second surface;
adding an organic solvent to the first portion and the second portion, to fix the sheet structure on the substrate surface only by the carbon nanotube structure;
laying an object on and in direct contact with the third portion, wherein the carbon nanotube structure is located between the sheet structure and the object, and a surface of the object being in direct contact with the third portion has a surface roughness less than or equal to 1.0 micrometer; and
applying a pressure to the object to make the object bonded to the substrate surface and forming a structure comprising the substrate, the sheet structure, the carbon nanotube structure and the object.

US Pat. No. 10,483,229

SINTERING DEVICE

Danfoss Silicon Power Gmb...

1. A sintering device for sintering at least one electronic assembly, having a lower die and an upper die which is slidable towards the lower die, or a lower die which is slidable towards the upper die, wherein the lower die forms a support for the assembly to be sintered and the upper die comprises a receptacle which receives a pressure pad for exerting pressure directed towards the lower die and which comprises a delimitation wall which laterally surrounds the pressure pad, and wherein the delimitation wall has an outer delimitation wall and an inner delimitation wall which is surrounded in an adjacent manner by the outer delimitation wall, and wherein the inner delimitation wall is mounted so as to be slidable towards the outer delimitation wall and, when pressure in the direction of the upper die is exerted on the pressure pad, is mounted so as to be slid in the direction of the lower die, whereby, following the placing of the inner delimitation wall on the lower die, the pressure pad is displaceable in the direction of the lower die.

US Pat. No. 10,483,228

APPARATUS FOR BONDING SEMICONDUCTOR CHIP AND METHOD FOR BONDING SEMICONDUCTOR CHIP

PROTEC CO., LTD., Gyeong...

1. A semiconductor chip bonding apparatus, comprising:a fixing member configured to fix a lower surface of a plurality of chip-substrate assemblies in which a non-conductive resin layer and a semiconductor chip are sequentially stacked on a substrate;
a pressing member arranged above the fixing member, the pressing member comprising a transparent portion through which a laser beam penetrates;
a lifting member configured to lift or lower one of the fixing member and the pressing member relative to the other of the fixing member and the pressing member to pressurize the semiconductor chips of the plurality of chip-substrate assemblies such that solder bumps of one of the semiconductor chips and the substrate penetrate the non-conductive resin layer to electrically contact the other of the semiconductor chips and the substrate; and
a laser head configured to irradiate the laser beam to the chip-substrate assemblies pressurized by using the pressing member, through the transparent portion of the pressing member, so as to bond solder bumps of one of the semiconductor chips and the substrate to the other of the semiconductor chips and the substrate,
wherein the pressing member further comprises a mask portion that is formed of an opaque material and supports the transparent portion,
wherein the transparent portion of the pressing member is disposed in areas respectively corresponding to the plurality of chip-substrate assemblies,
wherein the mask portion is disposed in a corresponding area between the plurality of chip-substrate assemblies.

US Pat. No. 10,483,227

SEMICONDUCTOR DEVICE

Rohm Co., Ltd., Kyoto (J...

1. A voltage generating apparatus that generates a predetermined output voltage from an input voltage, the apparatus comprising:a semiconductor chip including:
a semiconductor substrate; and
an element formed in an element-forming region on a front surface of the semiconductor substrate;
an insulating layer provided at a side of a first surface of the semiconductor chip;
a circuit component mounted on the insulating layer; and
an external connection member provided at a side of a second surface of the semiconductor substrate, which is opposite to the side of the first surface of the semiconductor chip,
wherein the external connection member includes an input voltage terminal to which the input voltage is input, a ground terminal connected to a ground potential, and an output terminal from which the output voltage is output,
wherein the element includes a first transistor and a second transistor connected in series between the input voltage terminal and the ground terminal,
wherein the element further includes a control circuit that controls the first transistor and the second transistor,
wherein the circuit component includes an inductor connected between the output terminal and a connection point of the first transistor and the second transistor, and
wherein the inductor is disposed directly over the first transistor or the second transistor.

US Pat. No. 10,483,226

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

9. A method of forming a semiconductor device, comprising:providing a first substrate having at least two chip regions separated by an insulating deep trench, wherein the first substrate has, in each chip region, a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump;
forming a first insulating layer over the metal bumps and the passivation stacks;
patterning the first insulating layer to form a first opening pattern and a second opening pattern therein, wherein a bottom of the first opening pattern and a bottom of the second opening pattern are at different height levels;
providing a second substrate having a second insulating layer thereon;
bonding the second substrate to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer; and
removing the first insulating layer and portions of the passivation stacks by flowing an etch gas from the insulating deep trench.

US Pat. No. 10,483,225

PACKAGING ASSEMBLY AND METHOD OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A packaging assembly, comprising:a semiconductor device comprising:
a conductive pad having a first width,
a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad,
a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad,
an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width,
a conductive pillar on the UBM layer, and
a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer;
a substrate comprising:
a conductive region, and
a mask layer overlying the substrate and exposing a portion of the conductive region; and
a joint solder structure between the conductive pillar and the conductive region.

US Pat. No. 10,483,224

SEMICONDUCTOR CHIP

Samsung Electronics Co., ...

1. A semiconductor chip comprising:a semiconductor substrate including a bump region, a non-bump region, and a dummy region between the bump region and the non-bump region;
a dummy pattern on the dummy region;
a bump on the bump region, the non-bump region having no bump; and
a passivation layer on the bump region, the dummy region, and the non-bump region of the semiconductor substrate,
a thickness of the passivation layer at the bump region being thicker than a thickness of the passivation layer at the non-bump region,
the passivation layer covering the dummy pattern and insulating the dummy pattern, and
the passivation layer including a step between the bump region and the non-bump region, the step defined by an upper surface of the passivation layer at a portion of the passivation layer that protrudes upward over a boundary between the dummy region and the non-bump region.

US Pat. No. 10,483,223

SEMICONDUCTOR DEVICE HAVING A LARGE AREA INTERCONNECT OR PAD

ABLIC INC., Chiba (JP)

1. A semiconductor device, comprising:a semiconductor substrate;
an insulating film on a surface of the semiconductor substrate;
a first interconnect on the insulating film and having a first width in a first direction and a second width in a second direction, the second direction orthogonal to the first direction;
a second interconnect having a length in the second direction of equal to or less than 20 microns and having a third width in the first direction, wherein the third width is smaller than the first width and the second width, and the second interconnect is coupled to the first interconnect at a first coupling portion between the first interconnect and one end of the second interconnect, the first coupling portion extending in the first direction;
a slit in the first interconnect spaced away from the first coupling portion by a length of equal to or less than 20 microns, and having a fourth width that is half or more of the third width; and
a third interconnect coupled to a terminal end of the second interconnect on an opposite side to the first coupling portion, wherein the third interconnect comprises a same layer as the first interconnect and the second interconnect and extends along the first direction.

US Pat. No. 10,483,222

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Amkor Technology, Inc., ...

1. A semiconductor device comprising:a semiconductor die comprising:
a top die surface; and
a bond pad on the top die surface;
a conductive layer comprising a first end coupled to the bond pad, wherein the conductive layer extends laterally from the bond pad over the top die surface;
a conductive interconnection structure coupled to a second end of the conductive layer; and
an insulation layer formed directly on the conductive interconnection structure and on the conductive layer, the insulation layer comprising a single continuous layer of a non-photosensitive material that laterally surrounds a lower portion of the conductive interconnection structure and does not laterally surround an upper portion of the conductive interconnection structure,
wherein:
the lower portion of the conductive interconnection structure that is surrounded by the insulation layer is shaped like a portion of a sphere, the portion of the sphere comprising a curvature in a vertical cross-sectional view; and
the single continuous layer of the non-photosensitive material that laterally surrounds the lower portion of the conductive interconnection structure conforms, in the vertical cross-sectional view, to said curvature.

US Pat. No. 10,483,221

3DI SOLDER CUP

MICRON TECHNOLOGY, INC., ...

1. A semiconductor device assembly comprising:a first substrate having a first surface and a second surface opposite the first surface, the first surface having at least one under bump metal (UBM) disposed thereon;
a second substrate having a first surface and a second surface opposite the first surface, the second substrate disposed over the first substrate, the second substrate having at least one solder cup on the second surface, the at least one solder cup comprising a pillar and a barrier on an exterior of the pillar, the barrier having a first end proximal to the second surface of the second substrate and a second end distal to the second surface of the second substrate, the barrier extends from the first end to the second end along the exterior of the pillar and being open at the second end, the pillar comprising solder positioned within an interior of the barrier, the opening at the second end of the barrier having a first perimeter and the UBM having a second perimeter, the first perimeter being larger than the second perimeter;
wherein the solder cup and UBM are connected together to form a support between the first substrate and the second substrate; and
wherein the UBM is encased by the solder positioned within the interior of the barrier.

US Pat. No. 10,483,220

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE

STIMICROELECTRONICS S.R.L...

14. A semiconductor device, comprising:a passivation layer having a marginal region;
a first metallization layer extending in a via through the passivation layer, at least a portion of the first metallization layer being positioned in the via lower than an upper surface of the passivation layer;
a first conductive barrier layer extending in the via, underlying said first metallization layer, and extending on the marginal region of the passivation layer; and
a second conductive barrier layer extending in the via and over the marginal region of the passivation layer between the first metallization and the first conductive barrier layer, the first conductive barrier layer having a first portion positioned in the via and contacting a bottom surface of the first metallization layer and a second portion positioned on the marginal region of the passivation layer and spaced apart from the second barrier layer by an undercut gap.

US Pat. No. 10,483,219

ARRAY SUBSTRATE WITH STATIC CHARGE RELEASING PATTERN AND METHOD FOR PRODUCING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising a metal pattern and an electrically conductive pattern formed sequentially on a base substrate, the electrically conductive pattern being insulated from the metal pattern, wherein the array substrate further comprises:a static charge releasing pattern formed in a same layer as the electrically conductive pattern and formed by a same material as the electrically conductive pattern,
wherein the static charge releasing pattern is insulated from the electrically conductive pattern and electrically connected with the metal pattern, and
wherein the metal pattern is a signal line, the signal line being continuous and comprising an input end and an output end, and the static charge releasing pattern comprises:
a first static charge releasing pattern portion arranged in a crimping region of the array substrate and connected with the input end of the signal line; and
a second static charge releasing pattern portion arranged in a display region of the array substrate and connected with the output end of the signal line.

US Pat. No. 10,483,218

INTEGRATED CIRCUIT (IC) DEVICES WITH VARYING DIAMETER VIA LAYER

QUALCOMM Incorporated, S...

1. An integrated circuit (IC) device comprising:an IC device layer; and
at least one electrical connection layer located over the IC device layer; and
a varying diameter via layer located over the at least one electrical connection layer, the varying diameter via layer comprising (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias,
wherein the plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region, and
wherein the varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

US Pat. No. 10,483,215

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT

International Business Ma...

1. A multi-layer wafer comprising:two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer, the polymer layer having a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition, the two heterogeneous wafers low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

US Pat. No. 10,483,214

OVERLAY STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:locating a first plurality of offset dummy features in a first layer;
locating a second plurality of offset dummy features in a second layer;
measuring a distance between each offset dummy feature of the first plurality of offset dummy features in the first layer with respect to one another and each offset dummy feature of the second plurality of offset dummy features in the second layer with respect to one another; and
determining that the first layer or the second layer is shifted with respect to one another by comparing the measurement from the first layer or the second layer to a known value.

US Pat. No. 10,483,212

APPARATUS FOR STACKING SUBSTRATES AND METHOD FOR THE SAME

Nikon Corporation, Tokyo...

14. A substrate processing method for stacking a first substrate and a second substrate on each other, to make a substrate stack, which is separable from a substrate stacking apparatus, by forming a contact region, where the first substrate held by a first holding section of the substrate stacking apparatus and the second substrate held by a second holding section of the substrate stacking apparatus contact each other, at one portion of the first substrate and the second substrate, and then expanding the contact region from the one portion by releasing holding of the first substrate by the first holding section, whereinan amount of deformation occurring in at least the first substrate differs at positions having the same distance from a center of the at least the first substrate in a plurality of circumferential directions,
the substrate processing method comprises a restricting step of restricting misalignment between corresponding circuit connection terminals of the first substrate and the second substrate caused by a difference in the amount of deformation, and
the substrate stack retains the restricted misalignment when separated from the substrate stacking apparatus.

US Pat. No. 10,483,210

GLASS ARTICLES WITH NON-PLANAR FEATURES AND ALKALI-FREE GLASS ELEMENTS

Corning Incorporated, Co...

1. An electronic device assembly, comprising:a backplane having a glass composition substantially free of alkali ions,
an elastic modulus of about 40 GPa to about 100 GPa,
a final thickness from about 20 ?m to about 100 ?m,
a first primary surface, and
a second primary surface, the primary surfaces characterized by a prior material removal to the final thickness from an initial thickness that is at least 20 ?m greater than the final thickness;
a protect layer on the first primary surface of the backplane; and
a plurality of electronic components on the second primary surface of the backplane,
wherein the backplane is configured with at least one static bend having a bend radius between about 25 mm and about 5 mm, and further comprising:
a cover over the plurality of electronic components, the cover having a glass composition, and at least one curved feature having a radius substantially equivalent to the bend radius,
wherein the cover is further characterized by:
(a) an optical transmissivity of at least 90%;
(b) a puncture resistance of greater than about 1.5 kgf when a first primary surface of the cover is supported by (i) an approximately 25 ?m thick pressure-sensitive adhesive having an elastic modulus of less than about 1 GPa and (ii) an approximately 50 ?m thick polyethylene terephthalate layer having an elastic modulus of less than about 10 GPa, and a second primary surface of the cover is loaded with a stainless steel pin having a flat bottom with a 200 ?m diameter; and
(c) a pencil hardness of greater than or equal to 8H.

US Pat. No. 10,483,208

INTERCONNECTION STRUCTURE, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a multi-gate transistor, the multi-gate transistor including an epitaxial source/drain region;
a dielectric layer overlying the epitaxial source/drain region;
a contact extending through an opening in the dielectric layer and electrically contacting the epitaxial source/drain region, the contact including:
a silicide layer contacting the epitaxial source/drain region, wherein a Si concentration of the silicide is varied along a height of the silicide;
a barrier layer contacting the silicide layer;
a metal layer contacting the barrier layer and contacting sidewalls of the opening in the dielectric layer, wherein the silicide layer is a silicide of the epitaxial source/drain region and the metal layer; and
a conductor contacting the barrier layer, wherein the barrier layer extends between and separates the conductor and the silicide layer.

US Pat. No. 10,483,207

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a first semiconductor region of a first conductivity type;
a stacked body provided on the first semiconductor region, the stacked body including a plurality of electrode layers stacked with an insulating body interposed, the stacked body including a first stacked portion and a second stacked portion, the plurality of electrode layers of the second stacked portion including a plurality of terrace portions arranged in a staircase configuration with a level difference in a first direction;
a first columnar portion extending through the first stacked portion in a stacking direction of the stacked body and including a first semiconductor body contacting the first semiconductor region;
an insulating layer provided on the plurality of terrace portions;
a plurality of contact portions extending through the insulating layer in the stacking direction and contacting the plurality of terrace portions;
a second columnar portion extending through the insulating layer and through the second stacked portion in the stacking direction, and including a second semiconductor body contacting the first semiconductor region; and
a first insulating portion dividing the first semiconductor region in the first direction, the first insulating portion provided under a boundary portion between the first stacked portion and the second stacked portion.

US Pat. No. 10,483,206

DEVICE COMPRISING NANOSTRUCTURES AND METHOD OF MANUFACTURING THEREOF

Waqas Khalid, Berkeley, ...

1. A method for manufacturing of a device comprising a first substrate comprising a plurality of sets of nanostructures arranged on said first substrate, wherein each of said sets of nanostructures is individually electrically addressable, said method comprising the steps of:providing a substrate having a first face, said substrate having an insulating layer comprising an insulating material arranged on said first face of said substrate forming an interface between said insulating layer and said substrate;
providing a plurality of stacks on said first substrate, said stacks being spaced apart from each other, wherein each stack comprises a first conductive layer comprising a first conductive material and a second conductive layer comprising a second conductive material different from said first material, said second conductive layer being arranged on said first conductive layer for catalyzing nanostructure growth; heating said first substrate having said plurality of stacks arranged thereon in a reducing atmosphere to enable formation of nanostructures on said second conductive material;
heating said first substrate having said plurality of stacks arranged thereon in an atmosphere such that nanostructures are formed on said second layer; wherein said insulating material and said first conductive material are selected such that during said heating steps, said first conductive material interacts with said insulating material to form an electrically conductive portion within said insulating layer below each of said stacks, wherein said electrically conductive portion comprises a mixture of said first conductive material and said insulating material and/or reaction adducts thereof.

US Pat. No. 10,483,205

CONTACT USING MULTILAYER LINER

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:patterning an opening within a substrate of a multi-layer integrated circuit device, said substrate comprising silicon;
performing a cleaning process of the opening;
forming a lower blocking layer within the opening, and the lower blocking layer contacts a surface of the opening, wherein the cleaning process leaves oxygen and fluorine particles within an area of the substrate adjacent the lower blocking layer;
forming a middle liner layer within the opening, and the middle liner layer contacts the lower blocking layer and comprises an oxide;
forming an upper blocking layer within the opening, and the upper blocking layer contacts the middle liner layer, and the middle liner layer is formed to be between the lower blocking layer and the upper blocking layer; and
forming a conductor layer within the opening, and the conductor layer contacts the upper blocking layer and comprises a conductive contact within the multi-layer integrated circuit device.

US Pat. No. 10,483,203

SEMICONDUCTOR MEMORY DEVICE HAVING PADS OF VARYING WIDTHS

SK hynix Inc., Icheon-si...

1. A semiconductor memory device comprising:channel layers protruding away from a substrate;
conductive layers configured to enclose the channel layers and stacked on the substrate, the conductive layers extending in a first direction;
a plurality of pads coupled to the channel layers and arranged in the first direction; and
a plurality of bit lines coupled to the channel layers through the plurality of pads,
wherein a pad of the plurality of pads has a width in the first direction so that the pad is wider relative to a preceding pad of the plurality of pads, and
wherein the channel layers are directly connected to the pads, respectively.

US Pat. No. 10,483,202

SEMICONDUCTOR DEVICE HAVING A WIRING LINE WITH AN END PORTION HAVING ROUNDED SIDE SURFACES AND MANUFACTURING METHOD THEREOF

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first wiring line provided on a first layer in a first direction;
a second wiring line provided on the first layer in the first direction, and the second wiring line having a first side surface facing the first wiring line and a second side surface which is opposite to the first side surface;
a third wiring line provided on the first layer in the first direction, and immediately adjacent to the second side surface of the second wiring line;
a fourth wiring line provided on the first layer in the first direction, the fourth wiring line having a first side surface immediately adjacent to the third wiring line and a second side surface which is opposite to the first side surface, the first side surface of an end portion of the fourth wiring line is rounded and curves toward the third wiring line;
a fifth wiring line provided on the first layer in the first direction, the second side surface of the fourth wiring line facing the fifth wiring line, wherein an end portion of the fifth wiring line projects further from the end portion of the fourth wiring line in the first direction; and
a sixth wiring line, a seventh wiring line, and an eighth wiring line, wherein end portions of the sixth wiring line, the seventh wiring line, and the eighth wiring line are symmetrical to the end portions of the second wiring line, the third wiring line, and the fourth wiring line about an axis perpendicular to the first direction, wherein
an end portion of the first wiring line projects further from an end portion of the second wiring line in the first direction,
the end portion of the second wiring line projects further from an end portion of the third wiring line in the first direction, and the first and second side surfaces of the end portion of the second wiring line are rounded and curve toward the third wiring line,
the end portion of the second wiring line curves along a side surface of the third wiring line, and
the end portion of the fourth wiring line curves along a side surface of the third wiring line.

US Pat. No. 10,483,201

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a semiconductor layer;
a first conductor disposed over the semiconductor layer;
a second conductor disposed over the first conductor; and
a fuse disposed between the first conductor and the second conductor, wherein the fuse includes a conductive portion and a non-conductive portion surrounded by the conductive portion, the conductive portion is in contact with the first conductor and the second conductor, and the non-conductive portion is in contact with the second conductor.

US Pat. No. 10,483,200

INTEGRATED CIRCUITS (ICS) EMPLOYING ADDITIONAL OUTPUT VERTICAL INTERCONNECT ACCESS(ES) (VIA(S)) COUPLED TO A CIRCUIT OUTPUT VIA TO DECREASE CIRCUIT OUTPUT RESISTANCE

QUALCOMM Incorporated, S...

1. An integrated circuit (IC), comprising:a substrate;
a diffusion region disposed in the substrate, the diffusion region comprising a semiconductor channel each having a first longitudinal axis in a first direction;
a dummy gate extending along a second longitudinal axis orthogonal to the first longitudinal axis, the first dummy gate disposed above the diffusion region;
a conducting gate extending along a third longitudinal axis orthogonal to the first longitudinal axis, the conducting gate disposed above the diffusion region and adjacent to a first side of the dummy gate by a gate pitch;
a circuit comprising:
a Field-Effect Transistor (FET) in the diffusion region, the FET comprising:
a semiconductor channel structure in the diffusion region;
a first gate comprising a first active gate in a portion of the conducting gate disposed above the semiconductor channel structure;
a source in a first end portion of the semiconductor channel structure; and
a drain in a second end portion of the semiconductor channel structure; and
a signal output node connected to at least one of the source and the drain of the FET;
an output contact disposed in a first output contact area above the signal output node and in contact with the signal output node;
an output metal interconnect line disposed above the output contact and in contact with the output contact and extending to a second output contact area outside the first output contact area, the second output contact area adjacent to a second side of the dummy gate opposite of the first side of the dummy gate;
a first via disposed above and in contact with the output metal interconnect line in the first output contact area; and
a second via disposed above and in contact with the output metal interconnect line in the second output contact area.

US Pat. No. 10,483,198

POST-GRIND DIE BACKSIDE POWER DELIVERY

Intel Corporation, Santa...

1. A microelectronics package comprising:a package substrate; and
a die connected to the package substrate, the die comprising:
a material layer having a top side and a backside, the top side including a plurality of pad connections, the backside including a power connection;
a plurality of vias extending through the material layer from the top side to the backside; and
a plurality of metal channels in contact with the backside, each of the plurality of metal channels in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias, at least one of the plurality of metal channels in electrical communication with the power connection,
wherein a first metal channel of the plurality of metal channels is located adjacent a reference channel within the material layer.

US Pat. No. 10,483,197

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a first connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package, the first connection member including an insulating member and a first redistribution layer embedded in the insulating member and having exposed regions in the second surface;
a semiconductor chip having an active surface having connection electrodes disposed thereon, and an inactive surface opposing the active surface in the stacking direction and disposed on the first connection member, the inactive surface facing the second surface of the first connection member;
an encapsulant disposed on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region positioned in the vicinity of the semiconductor chip;
a second redistribution layer including connection vias penetrating through the first region of the encapsulant and connected to the connection electrodes, through-vias penetrating through the second region of the encapsulant and connected to the exposed regions of the first redistribution layer, and a wiring pattern disposed on the encapsulant and having an integrated structure with the connection vias and the through-vias; and
a second connection member having a third surface disposed on the encapsulant and a fourth surface opposing the third surface in the stacking direction, the second connection member including a third redistribution layer connected to the second redistribution layer,
wherein an area of a surface of at least one of the through-vias adjacent to the first connection member is smaller than an area of a surface of the at least one of the through-vias adjacent to the second connection member.

US Pat. No. 10,483,195

RESIN BOARD, METHOD OF MANUFACTURING RESIN BOARD, CIRCUIT BOARD, AND METHOD OF MANUFACTURING CIRCUIT BOARD

FUJITSU LIMITED, Kawasak...

1. A resin board comprising:a first resin layer;
a columnar electrode buried in the first resin layer, the columnar electrode including a protruding portion that protrudes from a side surface of the columnar electrode and configured to cause an electric field applied to the columnar electrode to shift to inside of the first resin layer, the protruding portion having an exposed surface exposed from the first resin layer and a non-linear lateral surface connecting the exposed surface and the side surface, such that the exposed surface and the lateral surface form an obtuse angle; and
a second resin layer formed on the first resin layer so as to be in close contact with no gaps and including a plurality of wiring layers electrically connected to the columnar electrode through the exposed surface,
wherein a portion corresponding to a maximum diameter at the lateral surface of the protruding portion is embedded in the first resin layer,
a diameter of the exposed surface is smaller than the maximum diameter, and
the exposed surface has a shape which is recessed in a direction different from a direction of the second resin layer at a surface of the first resin layer.

US Pat. No. 10,483,194

INTERPOSER SUBSTRATE AND METHOD OF FABRICATING THE SAME

PHOENIX PIONEER TECHNOLOG...

1. An interposer substrate, comprising:a second dielectric material layer having opposing first and second surfaces;
a first wiring layer embedded in the second dielectric material layer and exposed from the first surface of the second dielectric material layer;
a first dielectric material layer formed on the first surface of the second dielectric material layer and the first wiring layer, wherein a portion of the first wiring layer extends continuously into the first dielectric material layer from the second dielectric material layer, and the first dielectric material layer has a plurality of openings, from which a portion of the first wiring layer is exposed;
a plurality of first conductive blocks embedded in the second dielectric material layer and having first terminal surfaces connected to the first wiring layer and second terminal surfaces opposing to the first terminal surfaces and flush with the second surface of the second dielectric material layer;
a second wiring layer formed on the second surface of the second dielectric material layer and having a first side connected to the second terminal surfaces of the first conductive blocks and a second side opposing to the first surface of the second wiring layer;
a plurality of second conductive blocks formed on the second side of the second wiring layer; and
an insulative protection layer formed on the second surface of the second dielectric material layer, the second wiring layer and the second conductive blocks, wherein an end of the second conductive blocks is exposed from the insulative protection layer, and the insulative protection layer has at least a concave portion formed between two of the second conductive blocks.

US Pat. No. 10,483,192

PACKAGED SEMICONDUCTOR DEVICES WITH LASER GROOVED WETTABLE FLANK AND METHODS OF MANUFACTURE

FAIRCHILD SEMICONDUCTOR C...

1. A method of producing a packaged semiconductor device, the method comprising:coupling a semiconductor device to a metal leadframe structure, the metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device;
encapsulating at least a portion of the semiconductor device and at least a portion of the metal leadframe structure in a molding compound, at least a segment of the signal lead being exposed outside the molding compound, a surface of the molding compound defining a primary plane of the packaged semiconductor device;
forming, with a laser, a groove in the segment of the signal lead;
applying solder plating to the segment of the signal lead, including the groove; and
separating, at the groove, the segment of the signal lead into a first portion and a second portion, such that the second portion of the segment of the signal lead is separated from the metal leadframe structure,
the separating the segment of the signal lead defines a signal lead flank on an end of the first portion of the segment of the signal lead, the signal lead flank having a surface area, a first portion of the surface area of the signal lead flank being defined by the solder plating, and a second portion of the surface area of the flank of the signal lead defined by exposed metal of the metal leadframe structure.

US Pat. No. 10,483,191

BOTTOM PACKAGE EXPOSED DIE MEMS PRESSURE SENSOR INTEGRATED CIRCUIT PACKAGE DESIGN

STMICROELECTRONICS, INC.,...

1. A package containing a MEMS sensor circuit, comprising:a lead frame having an open region in a middle of the lead frame and a first surface exposed to an ambient atmosphere;
a monolithic MEMS semiconductor die being laterally adjacent to the lead frame, the monolithic MEMS semiconductor die having an exposed outer surface thereof exposed to the ambient atmosphere, the exposed outer surface having a plurality of apertures, the plurality of apertures exposing an internal chamber of the monolithic MEMS semiconductor die to the ambient atmosphere;
a second semiconductor die attached to the monolithic MEMS semiconductor die;
a first plurality of bonding wires connected between the lead frame and the second semiconductor die;
a second plurality of bonding wires connected at least between one of the lead frame and the monolithic MEMS semiconductor die or the monolithic MEMS semiconductor die and the second semiconductor die; and
a molding compound partially covering the monolithic MEMS semiconductor die and the lead frame and encapsulating the second semiconductor die and the plurality of bonding wires, a first surface of the molding compound being flush with the exposed outer surface of the monolithic MEMS semiconductor die and also with the first surface of the lead frame, the exposed outer surface of the monolithic MEMS semiconductor die being a semiconductor material, and an opening of the apertures being flush with the first surface of the molding compound.

US Pat. No. 10,483,189

POWER CONVERSION APPARATUS

HONDA MOTOR CO., LTD., T...

1. A power conversion apparatus mounted in a vehicle, comprising:a semiconductor stack in which a plurality of semiconductor modules and a plurality of coolant bodies are disposed by being alternately stacked, wherein the plurality of coolant bodies includes coolant passages; and
a retaining unit which presses the semiconductor stack in a stacking direction to retain the semiconductor stack,
wherein the plurality of semiconductor modules and the plurality of coolant bodies are attached to each other by a resin adhesive member, and a roughened area on which a roughening treatment has been performed is formed in at least a part of an outer surface of the plurality of coolant bodies to which the resin adhesive member is attached, and wherein the roughened area is formed on an entire outer surface of the plurality of coolant bodies.

US Pat. No. 10,483,186

SEMICONDUCTOR DEVICE WITH HEAT RADIATOR

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor element; and
a first heat radiator connected to a first surface of the semiconductor element,
wherein
the first heat radiator comprises:
a first outer heat conductor constituted of metal and connected to the first surface of the semiconductor element;
a first inner heat conductor disposed in the first outer heat conductor; and
a second inner heat conductor disposed in the first outer heat conductor and stacked on the first inner heat conductor in a direction in which the semiconductor element and the first heat radiator are arranged,
the first inner heat conductor comprises a plurality of first graphite layers,
the second inner heat conductor comprises a plurality of second graphite layers,
the plurality of first graphite layers is stacked in a first direction which is orthogonal to the direction in which the semiconductor element and the first heat radiator are arranged, and
the plurality of second graphite layers is stacked in the direction in which the semiconductor element and the first heat radiator are arranged, or is stacked in a second direction which is orthogonal to the direction in which the semiconductor element and the first heat radiator are arranged and orthogonal to the first direction.

US Pat. No. 10,483,185

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

FUJITSU LIMITED, Kanagaw...

1. A semiconductor device comprising:a semiconductor chip including a substrate and an element region on the substrate;
a heat transfer body made of diamond; and
a metal layer between the semiconductor chip and the heat transfer body;
wherein the substrate includes an amorphous region on a back surface thereof,
the amorphous region and the metal layer are bonded to each other,
the metal layer and the heat transfer body are bonded to each other,
the substrate is a SiC substrate,
the amorphous region is an amorphous SiC region, and
an interface between the amorphous SiC region and the metal layer includes more C atoms than Si atoms.

US Pat. No. 10,483,184

RECURSIVE METAL EMBEDDED CHIP ASSEMBLY

HRL Laboratories, LLC, M...

1. An assembly comprising:two or more component modules,wherein at least a first one of the component modules comprises a first embedded chip assembly, and at least a second one of the component modules comprises a second embedded chip assembly;a thermally conductive material,wherein the two or more component modules are embedded in the thermally conductive material; andinterconnects coupling the two or more component modules to each other,wherein the first embedded chip assembly comprises at least two interconnected chips embedded in the thermally conductive material, andwherein the first embedded chip assembly further comprises a packaging substrate disposed at least partially around the at least two interconnected chips.

US Pat. No. 10,483,182

INTERMEDIATE CONNECTOR, SEMICONDUCTOR DEVICE INCLUDING INTERMEDIATE CONNECTOR, AND METHOD OF MANUFACTURING INTERMEDIATE CONNECTOR

NODA SCREEN CO., LTD., A...

1. An intermediate connector that is provided between a semiconductor integrated circuit and a circuit board on which the semiconductor integrated circuit is mounted, and electrically connects the semiconductor integrated circuit and the circuit board,the semiconductor integrated circuit including a bump mounting face on which a power source pad row including a plurality of power source pads, a ground pad row including a plurality of ground pads, and a signal pad row including a plurality of signal pads are arranged in parallel,
the intermediate connector comprising:
a power source bus bar in a form of an elongated thin plate that has a length of at least a length of the power source pad row, and is to be connected to each of the power source pads of the power source pad row;
a ground bus bar in a form of an elongated thin plate that has a length of at least a length of the ground pad row, and is to be connected to each of the ground pads of the ground pad row;
a thin film insulator layer that is formed between the power source bus bar and the ground bus bar; and
a conductive path portion in a form of an elongated thin plate that has a length of at least a length of the signal pad row, and includes a plurality of conductive paths to be connected to each of the signal pads of the signal pad row,
wherein the power source bus bar, the ground bus bar, and the conductive path portion are joined together in a parallel arrangement corresponding to the parallel arrangement of the power source pad row, the ground pad row, and the signal pad row, each of which being in a standing state such that a longitudinal direction of the thin plate is parallel to the bump mounting face of the semiconductor integrated circuit.

US Pat. No. 10,483,180

PROCESS FOR THE WAFER-SCALE FABRICATION OF HERMETIC ELECTRONIC MODULES

1. An electronic module comprising:a multilayer PCB circuit that comprises:
on one face, electrical connection balls for external electrical connection of the electronic module; and
a hermetically protective electrically insulating inorganic inner layer;
an electrically insulating or conductive inorganic hermetic protection layer;
one or more electronic components that are electrically connected to the PCB circuit; and
six faces with the electrically insulating or conductive inorganic hermetic protection layer entirely covering the five faces other than that formed by the PCB circuit, wherein
the hermetically protective electrically insulating inorganic inner layer is in direct contact with the electrically insulating or conductive inorganic hermetic protection layer so as to form a continuous hermetical joint around the one or more electronic components.

US Pat. No. 10,483,177

PACKAGE FOR A SEMICONDUCTOR DIE, METHOD FOR MAKING A DIE PACKAGING BARE DIE TAPE AND METHOD FOR SEMICONDUCTOR DIE PACKAGING

Intel Corporation, Santa...

1. A carrier medium for a semiconductor die, comprising:a carrier tape with at least one pocket for the die to sit in; and
a selectively applied non-activated adhesive on the carrier tape wherein the adhesive is located outside of the at least one pocket.

US Pat. No. 10,483,175

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A power semiconductor device, comprising:a substrate on which a semiconductor chip is disposed;
an electrode which has one end fixed to the substrate and stands upright on the substrate;
an insulating case which houses the electrode and has a part opposed to another end of the electrode;
a conductive nut which is inserted into the case in the part of the case; and
a conductive component which directly connects the another end of the electrode and the nut, wherein
the conductive component connects to the another end of the electrode at a position on an inner-surface side of the insulating case.

US Pat. No. 10,483,174

INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME

Taiwan Semiconductor Manu...

1. An integrated circuit component, comprising:a semiconductor substrate;
conductive pads, located on and electrically connected to the semiconductor substrate and each having a testing region and a contact region comprising a core contact region and a buffer contact region, wherein along one direction, the conductive pads each have a maximum length less than a sum of a maximum length of the testing region and a maximum length of the buffer contact region; and
conductive vias, respectively located on the core contact regions of the conductive pads.

US Pat. No. 10,483,173

SEMICONDUCTOR DEVICE INSPECTION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Kabushiki Kaisha Toshiba,...

1. A semiconductor device inspection method comprising:irradiating a semiconductor chip or a metal member with first inspection light having a plurality of linear beams parallel to each other from a first direction inclining with respect to a top surface of a substrate, the semiconductor chip being disposed on the substrate, and the metal member being disposed on the semiconductor chip;
obtaining a first image of the semiconductor chip irradiated with the first inspection light or the metal member irradiated with the first inspection light; and
calculating first three-dimensional information of the semiconductor chip or the metal member based on the first image by using an optical cutting method.

US Pat. No. 10,483,171

METHOD AND APPARATUS WITH CHANNEL STOP DOPED DEVICES

SYNOPSYS, INC., Mountain...

1. A method of performing channel stop doping in an integrated circuit, comprising:implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
making epitaxial semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxial semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxial semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface; and
making a transistor with a transistor channel in the epitaxial semiconductor material, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

US Pat. No. 10,483,170

METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION

Taiwan Semiconductor Manu...

1. A method comprising:providing a substrate including a first fin element and a second fin element extending from the substrate;
forming a first layer including an amorphous material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements; and
performing an anneal process to remove the gap in the first layer,
wherein the amorphous material of the first layer remains amorphous during the performing of the anneal process.

US Pat. No. 10,483,169

FINFET CUT-LAST PROCESS USING OXIDE TRENCH FILL

Taiwan Semiconductor Manu...

1. A method comprising:etching a substrate to form fins and trenches;
filling the trenches with a first oxide, the first oxide having first material composition, the first material composition having a first stress characteristic;
etching a first fin to remove a first portion of the first fin, thereby forming a void; and
filling the void with a second oxide, the second oxide having a second material composition different than the first material composition, the second material composition having a second stress characteristic, wherein the second stress characteristic is greater than the first stress characteristic, the second oxide encapsulating a second portion of the first fin.

US Pat. No. 10,483,167

METHOD FOR MANUFACTURING DUAL FINFET DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:providing a substrate which comprises a first region and a second region;
forming at least one hard mask that is a frame structure on the first region of the substrate;
forming a mask layer on the second region of the substrate;
recessing the substrate by using the at least one hard mask and the mask layer to form a first raised structure in the first region and a second raised structure in the second region;
forming two first isolation structures and two second isolation structures respectively covering two opposite sidewalls of the second raised structure, wherein forming the two first isolation structures comprises removing portions of the first raised structure to form a fin structure, wherein lower portions of two opposite sidewalls of the fin structure are respectively covered by the two first isolation structures;
forming a first gate structure extending on a first portion of the fin structure and portions of the two first isolation structures, and a second gate structure extending on a first portion of the second raised structure and portions of the two second isolation structures, wherein the first gate structure covers upper portions of the two opposite sidewalls and a top surface of the first portion of the fin structure; and
forming a first source and a first drain respectively on two opposite sides of the first gate structure on the fin structure, and a second source and a second drain respectively on two opposite sides of the second gate structure on the second raised structure.

US Pat. No. 10,483,165

METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION

Taiwan Semiconductor Manu...

1. An integrated circuit structure comprising:a semiconductor region;
a gate stack over the semiconductor region;
an Inter-layer Dielectric (ILD) having portions on opposite sides of the gate stack;
a source/drain region extending into the semiconductor region;
a source/drain silicide region over the source/drain region;
a source/drain contact plug comprising:
a conductive capping layer, the conductive capping layer comprising:
a bottom portion over the source/drain silicide region; and
sidewall portions over, and connected to, the bottom portion; and
a metal region over the bottom portion and between the sidewall portions of the conductive capping layer; and
a metal cap comprising a first portion overlapping the metal region, and second portions extending into the sidewall portions of the conductive capping layer.

US Pat. No. 10,483,164

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure, comprising:providing an epitaxial structure comprising a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material being greater than a lattice constant of the first semiconductor material;
depositing a metal-containing layer on the epitaxial structure, the metal-containing layer comprising the first semiconductor material, a first metal material and a second metal material, and an atomic size of the second metal material being greater than an atomic size of the first metal material; and
annealing the metal-containing layer and the epitaxial structure to form a metal silicide layer on the epitaxial structure, the metal silicide layer comprising the first semiconductor material, the second semiconductor material, the first metal material and the second metal material.

US Pat. No. 10,483,163

SELF-FORMING BARRIER PROCESS

Lam Research Corporation,...

1. A method, comprising:performing a deposition process on a substrate, the deposition process configured to deposit a ruthenium layer in a feature on the substrate, the ruthenium layer being doped with zinc at an atomic percentage less than approximately 30 percent;
after depositing the ruthenium layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface at an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the ruthenium layer.

US Pat. No. 10,483,161

MULTI-BARRIER DEPOSITION FOR AIR GAP FORMATION

Taiwan Semiconductor Manu...

1. An integrated circuit structure comprising:a dielectric layer;
a first conductive line and a second conductive line in the dielectric layer;
a trench in the dielectric layer, the trench extending between the first conductive line and the second conductive line;
a first etch stop layer having a first portion with a first thickness extending over the dielectric layer, and a second portion with a second thickness, less than the first thickness, extending along sidewalls of the trench;
a second etch stop layer contacting the first etch stop layer, the second etch stop layer having a third portion with a third thickness extending over the first portion and having a fourth portion with a fourth thickness over the second portion, wherein a first ratio of the fourth thickness to the third thickness is greater than a second ratio of the second thickness to the first thickness;
a dielectric material in the trench and contacting the second etch stop layer; and
an air gap in the dielectric material and in the trench.

US Pat. No. 10,483,160

ULTRA THIN HELMET DIELECTRIC LAYER FOR MASKLESS AIR GAP AND REPLACEMENT ILD PROCESSES

Intel Corporation, Santa...

1. A method to manufacture an electronic device, comprising:depositing a helmet layer on a plurality of conductive features on a first dielectric layer on a substrate;
depositing a second dielectric layer on a first portion of the helmet layer; and
depositing an etch stop layer on a second portion of the helmet layer, wherein the etch stop layer comprises a dielectric material.

US Pat. No. 10,483,157

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device including fin field effect transistors (FinFETs), comprising:a first FinFET including a first fin structure extending in a first direction, a first source/drain structure and a first source/drain contact in contact with the first source/drain structure;
a second FinFET disposed adjacent to the first FinFET and including a second fin structure extending in the first direction, a second source/drain structure and a second source/drain contact in contact with the second source/drain structure;
a dielectric layer separating the first source/drain contact and the second source/drain contact; and
a first liner layer, made of a different dielectric material than the dielectric layer, disposed between the dielectric layer and the first source/drain contact.

US Pat. No. 10,483,156

NON-EMBEDDED SILICON BRIDGE CHIP FOR MULTI-CHIP MODULE

International Business Ma...

1. A method comprising:providing a silicon bridge chip, the silicon bridge chip comprising a free-floating device;
providing two or more semiconductor chips;
electrically joining the two or more semiconductor chips to the silicon bridge chip;
providing a substrate structure comprising a plurality of metal interconnect structures and a plurality of metal layers disposed on an interlevel dielectric;
forming a recess within the substrate structure, the recess is located in a region of the substrate structure away from the plurality of metal interconnect structures and the plurality of metal layers;
aligning the silicon bridge chip with the recess; and
in response to electrically joining the two or more semiconductor chips to the silicon bridge chip and aligning the silicon bridge chip with the recess, electrically joining the silicon bridge chip and the two or more semiconductor chips to the substrate structure, wherein the silicon bridge chip extends into the recess in the substrate structure such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.

US Pat. No. 10,483,155

TRENCH ISOLATION INTERFACES

Micron Technology, Inc., ...

1. A method of forming a semiconductor structure, comprising:forming a shallow trench isolation (STI) structure in a polycrystalline silicon (polysilicon) substrate material;
depositing a layer of aluminum oxide (Al2O3) dielectric on vertical and horizontal surfaces of the STI structure to form a trench between the STI structure and a memory device;
forming an interface in the trench with a fixed negative charge by interaction of the polysilicon substrate material with the Al2O3 dielectric layer; and
thereby raising a parasitic threshold of the STI structure.

US Pat. No. 10,483,153

DEEP TRENCH ISOLATION STRUCTURE IN SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit comprising:a semiconductor substrate, wherein the semiconductor substrate is a semiconductor on insulator (SOI) substrate comprising a handle substrate, a semiconductor layer over the handle substrate, and a buried insulator layer between the handle substrate and the semiconductor layer;
an isolation region in the semiconductor substrate;
a first active component on the semiconductor layer of the semiconductor substrate; and
at least one deep trench isolation structure extending from a bottom of the isolation region toward a bottom of the semiconductor substrate, the deep trench isolation structure having at least one air void therein.

US Pat. No. 10,483,151

SUBSTRATE TRANSFER APPARATUS, SUBSTRATE PROCESSING APPARATUS, AND SUBSTRATE PROCESSING METHOD

SHIBAURA MECHATRONICS COR...

1. A substrate transfer apparatus, comprising:a first gripping plate;
a first claw fixedly supported by the first gripping plate, and has an abutment surface, which abuts on an outer peripheral surface of a substrate, located above and below a surface of the first gripping plate;
a second gripping plate overlapping the first gripping plate;
a second claw fixedly supported by the second gripping plate, and has an abutment surface, which abuts on the outer peripheral surface of the substrate, located above and below the surface of the first gripping plate; and
a gripper to move both the first gripping plate and the second gripping plate such that both the first claw and the second claw move to approach and separate from each other in a direction intersecting the outer peripheral surface of the substrate,
wherein the gripper includes
a support plate,
a linear guide supported by the support plate and extending in a direction in which the first claw and the second claw move to approach and separate from each other,
a first linear motion block fixed to the first gripping plate and configured to be movable along the linear guide,
a second linear motion block fixed to the second gripping plate and configured to be movable along the linear guide,
a cylinder connected to one of the first gripping plate and the second gripping plate to move the one of the gripping plates in the direction in which the first claw and the second claw move to approach and separate from each other, and
a swing pin mover configured to convert and transmit the movement of the one of the gripping plates caused by the cylinder to the other of the gripping plates such that the other of the gripping plates moves in a direction opposite to the movement of the one of the gripping plates.

US Pat. No. 10,483,150

APPARATUS FOR STACKING SEMICONDUCTOR CHIPS IN A SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. An apparatus for stacking semiconductor chips, comprising: a push member configured to apply pressure to a semiconductor chip disposed on a substrate, and wherein the push member comprises a push plate configured to contact the semiconductor chip, and a push rod connected to the push plate,wherein the push plate comprises:
a central portion having an area smaller than an area of an upper side of the semiconductor chip; and
a plurality of protrusions disposed at corners of the central portion, and each of the plurality of protrusions protrudes over two adjacent edges of the central portion of the push plate,
wherein a modulus of elasticity of the plurality of protrusions is higher than a modulus of elasticity of the central portion.

US Pat. No. 10,483,147

DUAL-PURPOSE VIAS FOR USE IN CERAMIC PEDESTALS

Wallow Electric Manufactu...

1. A ceramic pedestal assembly comprising:a substrate having a first functional layer and a second functional layer, the first and second functional layers disposed at opposite sides of the substrate; and
at least one via extending through the substrate comprising:
an upper via defining a cavity; and
a lower via defining a corresponding insert,
wherein the first functional layer, the second functional layer, and the at least one via define a material having a melting temperature greater than 2,000° C. and a CTE (coefficient of thermal expansion) lower than the substrate.

US Pat. No. 10,483,140

MASK TRANSMISSION EQUIPMENT

WINBOND ELECTRONICS CORP....

1. A mask transmission equipment, comprising:a wafer transmission container, comprising a plurality of first positioning grooves and a plurality of second positioning grooves, wherein the first positioning grooves face the second positioning grooves, the first positioning grooves and the second positioning grooves are adapted to position a plurality of wafers, and each first positioning groove and the corresponding second positioning groove are adapted to position one of the wafers; and
a supporting bracket, disposed in the wafer transmission container, comprising a first supporting unit, a second supporting unit, a first wing and a second wing, wherein the first supporting unit is stacked on the second supporting unit, the first wing is disposed on a first side of the supporting bracket, the second wing is disposed on a second side of the supporting bracket, the first side is opposite to the second side, the first wing is inserted into one of the first positioning grooves, and the second wing is inserted into one of the second positioning grooves.

US Pat. No. 10,483,138

WAFER CLAMP AND A METHOD OF CLAMPING A WAFER

Himax Technologies Limite...

1. A wafer clamp comprising:a platform with a top surface;
a stopper disposed at a front end of the platform;
a push rod disposed at a rear end of the platform;
at least one actuator pivotally connected to the push rod; and
a sensor disposed at the front end of the platform, the sensor measuring a distance between the sensor and a wafer over the sensor;
wherein the actuator comprises a pneumatic cylinder, a front end of which pulls back to an original position when the pneumatic cylinder is not actuated.

US Pat. No. 10,483,136

CERAMIC HEATER AND ELECTROSTATIC CHUCK

NGK SPARK PLUG CO., LTD.,...

1. A ceramic heater having a plate-like form and comprising:a laminate of a ceramic substrate and a base substrate, the ceramic substrate including an internal heat-generating element,
wherein, as viewed in a thickness direction, the ceramic heater has heating zones and a hole region disposed within a certain one of the heating zones, the hole region corresponding to:
(a) a hole defined by the ceramic substrate, or
(b) a through hole defined by the base substrate;
the internal heat-generating element includes zone heat-generating elements disposed in respective heating zones so as to heat the ceramic substrate independently; and
a zone heat-generating element disposed in the certain one of the heating zones having the hole region is formed of a heat-generating conductor which has a first parallel segment disposed in parallel with a second adjacent parallel segment and a turning-back segment which connects, while turning back, the first and second parallel segments of the heat-generating conductor extending toward the hole region so as to prevent the first and second parallel segments extending toward the hole region from overlying the hole region;
wherein, as viewed in the thickness direction, the entire turning-back segment is positioned between the first parallel segment and the second parallel segment.

US Pat. No. 10,483,134

SUBSTRATE TREATMENT DEVICE AND SUBSTRATE TREATMENT METHOD

J.E.T. CO., LTD., Okayam...

1. A substrate treatment device for cleaning and drying a substrate with fine patterns formed thereon, the substrate treatment device comprising:a substrate holding unit including a plate-shaped holding table that rotatably holds the substrate so that a surface of the substrate with the fine patterns formed thereon faces downward, and a plurality of holding pins provided on the holding table to hold an outer periphery of the substrate at a plurality of points;
a heater that heats the substrate disposed so that a distance between the heater and the substrate can be adjusted;
a cover that internally houses the substrate holding unit and the heater, and constitutes a treatment chamber;
a pump that exhausts the treatment chamber to make a negative-pressure atmosphere;
an inert gas supply port that faces an opposite side surface opposite to the surface with the fine patterns formed thereon, and supplies inert gas into the treatment chamber; and
a nozzle to jet a cleaning solution toward the surface with the fine patterns formed thereon and a gas exhaust port to communicate with the pump, the nozzle and the gas exhaust port being provided on the holding table, whereinthe cover is open when the substrate is carried in and out, closed when the substrate is treated, and configured to be capable of sealing the treatment chamber.

US Pat. No. 10,483,133

METHOD FOR FABRICATING A SEMICONDUCTOR CHIP PANEL

Infineon Technologies AG,...

1. A method for fabricating a semiconductor chip panel, the method comprising:providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces;
providing an adhesive layer located on a carrier;
placing at least one interposer on the adhesive layer located on the carrier;
placing the semiconductor chips on the at least one interposer with the second main faces facing the carrier; and
applying an encapsulation material by molding thereby forming the semiconductor chip panel, wherein the encapsulation material is applied so that the side faces of the semiconductor chips are covered with the encapsulation material while the first main faces are not.

US Pat. No. 10,483,132

POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a passivation layer formed on a semiconductor substrate, the passivation layer having a first opening exposing a contact pad, the passivation layer extending along sidewalls of the contact pad;
a protective layer overlying the passivation layer, the protective layer comprising a first protective layer and a second protective layer, the first protective layer being a single layer and having a second opening, the first protective layer extending along an upper surface and sidewalls of the passivation layer, the first protective layer contacting the contact pad;
an interconnect structure formed in and filling the second opening of the first protective layer and the first opening in the passivation layer, the interconnect structure having an entire top surface substantially co-planar with a top surface of the second protective layer, wherein the interconnect structure comprises a first interconnect layer extending continuously from the top surface of the second protective layer to a bottommost surface of the interconnect structure, wherein a sidewall of the second protective layer adjacent to the interconnect structure is substantially perpendicular to the top surface of the second protective layer;
a bump directly on the interconnect structure, wherein the interconnect structure is in physical contact with a top surface of the first protective layer directly below the bump; and
a molding compound layer in physical contact with the protective layer, the interconnect structure and a lower portion of the bump.

US Pat. No. 10,483,130

WIRE AND METHOD FOR MANUFACTURING THE SAME

KUNSHAN NEW FLAT PANEL DI...

1. A wire for use in an organic light-emitting diode (OLED) device, wherein the wire comprises a first part, a second part and a third part, which are connected in this order, wherein the first part and the third part are located at both ends of the wire respectively and each of the first part and third part is a single wire; andwherein the second part is located between the first part and the third part and is a composite wire, wherein the composite wire comprises at least two sub-wires extended in from the single wires, and wherein a wire width of any one of the at least two sub-wires is less than a wire width of any one of the single wires.

US Pat. No. 10,483,129

METHOD FOR ROUGHENING THE SURFACE OF A METAL LAYER, THIN FILM TRANSISTOR, AND METHOD FOR FABRICATING THE SAME

BOE Technology Group Co.,...

1. A method for fabricating a thin film transistor, the method comprising:forming an oxide semiconductor layer and a source-drain metal layer on an underlying substrate;
forming a first photo-resist layer on a surface of the source-drain metal layer, and processing the first photo-resist layer by pre-baking, exposing, developing, and post-baking the first photo-resist layer, wherein the post-baking is at a temperature ranging from 110° C. to 150° C.; and stripping the first photo-resist layer to roughen the surface of the source-drain metal layer; and
performing a patterning process on the roughened source-drain metal layer, and the oxide semiconductor layer to form patterns of source and drain electrodes, and a pattern of an active layer;
wherein performing the patterning process on the roughened source-drain metal layer, and the oxide semiconductor layer to form the patterns of the source and drain electrodes, and the pattern of the active layer comprises:
forming a second photo-resist layer on the roughened source-drain metal layer;
exposing and developing the second photo-resist layer to form an area where all the second photo-resist is reserved, an area where all the second photo-resist is removed, and an area where a part of the second photo-resist is reserved, wherein the area where a part of the second photo-resist is reserved corresponds to a channel area, and the area where all the second photo-resist is reserved corresponds to the patterns of the source and drain electrodes to be formed;
in the area where all the second photo-resist is removed, etching the roughened source-drain metal layer and the oxide semiconductor layer to form the pattern of the active layer;
ashing the second photo-resist layer to remove all of the second photo-resist layer located in the area where a part of the second photo-resist was reserved; and subsequently etching in the area where the part of the second photo-resist was reserved to remove the roughened source-drain metal layer to form the patterns of the source and drain electrodes;
wherein after etching the roughened source-drain metal layer and the oxide semiconductor layer to form the pattern of the active layer, the method further comprises:
over-etching the roughened source-drain metal layer and the oxide semiconductor layer for a period of time which is 5% to 20% of a length of time of etching the roughened source-drain metal layer and the oxide semiconductor layer.

US Pat. No. 10,483,126

SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing apparatus comprising:a stage capable of mounting a substrate;
a first nozzle supplying a chemical solution onto the substrate;
a first protection plate provided along an outer circumference of the substrate, the first protection plate receiving the chemical solution splashing from the substrate;
a second nozzle provided above the first protection plate, the second nozzle supplying pure water to an inner surface of the first protection plate;
a second protection plate provided at an outside of the first protection plate, the second protection plate receiving the chemical solution splashing from the substrate;
a third nozzle provided above the second protection plate, the third nozzle supplying pure water to an inner surface of the second protection plate; and
a sucker sucking the chemical solution supplied onto the substrate, wherein
an angle of inclination of the inner surface of the first protection plate is zero to 45 degrees with respect to an almost vertical direction,
the inner surface of the first protection plate is hydrophilic so that a contact angle between the inner surface of the first protection plate and pure water is less than 90 degrees,
the second nozzle is a pipe provided along an upper edge part of the first protection plate, the pipe comprising a plurality of first holes,
the first holes are provided to the second nozzle at an inner surface side of the first protection plate,
the third nozzle is a pipe provided along an upper edge part of the second protection plate, the pipe comprising a plurality of second holes,
the second holes are provided to the third nozzle at an inner surface side of the second protection plate, and
the stage rotates the substrate while the chemical solution or the pure water is supplied on the substrate.

US Pat. No. 10,483,125

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

TOWERJAZZ PANASONIC SEMIC...

1. A semiconductor device comprising:a substrate provided with a first region and a second region;
a first interlayer film formed on an upper surface of the substrate;
a first metal wiring line embedded in an upper portion of the first interlayer film in the first region;
a second interlayer film formed on the first interlayer film and the first metal wiring line;
a second metal wiring line embedded in an upper portion of the second interlayer film in the first region;
a first via penetrating the second interlayer film and electrically connecting the first metal wiring line and the second metal wiring line;
a landing pad embedded in the upper portion of the first interlayer film and penetrating the second interlayer film in the second region; and
a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad in the second region,
wherein a lower surface position of the landing pad is different from that of the first metal wiring line.

US Pat. No. 10,483,124

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a substrate;
a first stack above the substrate and including first insulation layers and first conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end part of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the first conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and
at least one second stack above the substrate and including at least one first layer and at least one second layer stacked in the first direction,
wherein, in the at least one of the second direction and the third direction, a first dimension of the first stack is larger than a second dimension of the second stack.

US Pat. No. 10,483,121

EMBEDDED MEMORY IN BACK-END-OF-LINE LOW-K DIELECTRIC

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a substrate comprising circuit components disposed on a substrate surface;
a plurality of interlevel dielectric (ILD) levels disposed on the substrate over the circuit components, wherein the plurality of interlevel dielectric (ILD) levels include a cell dielectric layer;
a storage unit of a memory cell between two adjacent ILD layers, wherein the storage unit is formed in the cell dielectric layer, the cell dielectric layer is disposed between the two adjacent ILD layers, the cell dielectric layer comprises a low-k dielectric material and is disposed over the storage unit; and
a polishing rate enhancer layer over the cell dielectric layer, the polishing rate enhancer layer comprising an oxide layer.

US Pat. No. 10,483,120

HYBRID DOUBLE PATTERNING METHOD FOR SEMICONDUCTOR MANUFACTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating an integrated circuit (IC) with a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution, comprising:deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution; and
classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.