US Pat. No. 10,217,844

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING AN N TYPE SEMICONDUCTOR REGION FORMED IN A P TYPE SEMICONDUCTOR LAYER

TOYODA GOSEI CO., LTD, K...

1. A method of manufacturing a semiconductor device, comprising:a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×107 cm?2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×107 cm?2;
an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and
a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer, wherein
in the performing of the heat treatment of the n-type semiconductor region forming process, a p-type impurity diffusion region formed in the n-type semiconductor layer and below the n-type semiconductor region.

US Pat. No. 10,217,842

METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INNER SPACERS

1. A method for making a semiconductor device, including at least:a) making, on a substrate, a stack comprising at least one first semiconductor portion arranged between at least two second portions of at least one material able to be selectively etched relative to the semiconductor of the first portion, the first portion being able to form at least one active zone of the semiconductor device,
b) making, on a part of the stack, outer spacers and at least one dummy gate arranged between the outer spacers,
c) etching the second portions such that remaining parts of the second portions are arranged at least under the dummy gate,
d) partially oxidising the remaining parts of the second portions from outer faces of the remaining parts of the second portions which are revealed by etching the second portions, forming inner spacers,
e) removing the dummy gate and the non-oxidised parts of the remaining parts of the second portions arranged at least under the dummy gate,
f) making a gate between the outer spacers and between the inner spacers, covering the channel and able to be electrically insulated from source and drain regions by the outer spacers and the inner spacers.

US Pat. No. 10,217,840

REPLACEMENT METAL GATE STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming a dummy gate structure with a first spacer;
forming a gate dielectric material on the first spacer;
removing a portion of the first spacer to form a space between an interlevel dielectric material and the gate dielectric material;
etching the gate dielectric material from within the space to form a recessed portion with exposure of sidewalls of the interlevel dielectric material above the first spacer;
depositing a second spacer on the exposed sidewalls of the interlevel dielectric material;
filling the recessed portion with a metal gate material; and
forming a self-aligned contact adjacent to the metal gate material.

US Pat. No. 10,217,839

FIELD EFFECT TRANSISTOR (FET) WITH A GATE HAVING A RECESSED WORK FUNCTION METAL LAYER AND METHOD OF FORMING THE FET

GLOBALFOUNDRIES INC., Gr...

1. A field effect transistor comprising:a gate adjacent to a semiconductor body at a channel region and comprising:
a conformal dielectric layer immediately adjacent to the semiconductor body; and,
a stack of gate conductor layers comprising:
a conformal metal layer on the conformal dielectric layer; and
a conductive fill material layer on the conformal metal layer, wherein the conductive fill material layer has a top surface and an outer sidewall, the outer sidewall has a lower portion and an upper portion above the lower portion, and the conformal metal layer has an essentially vertical portion positioned laterally immediately adjacent to the lower portion of the outer sidewall; and
a gate cap having a center portion and an edge portion, wherein the center portion is above and immediately adjacent to the top surface and the edge portion is positioned laterally immediately adjacent to the upper portion of the outer sidewall and is further above and immediately adjacent to a top of the vertical portion of the conformal metal layer.

US Pat. No. 10,217,837

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING ELECTRODE TRENCHES, ISOLATED SOURCE ZONES AND SEPARATION STRUCTURES

Infineon Technologies AG,...

1. A semiconductor device, comprising:a semiconductor mesa comprising source zones and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone;
electrode structures on opposite sides of the semiconductor mesa, at least one of the electrode structures comprising a gate electrode configured to control a charge carrier flow through the at least one body zone; and
a separation region arranged along an extension direction of the semiconductor mesa,
wherein in the separation region, the semiconductor mesa comprises a constricted portion that is partially or completely oxidized.

US Pat. No. 10,217,833

THIN FILM TRANSISTOR INCLUDING SCHOTTKY DIODE UNIT IN AN INSULATING MEDIUM LAYER

Tsinghua University, Bei...

1. A thin film transistor comprising:a gate electrode, an insulating medium layer and at least one Schottky diode unit, wherein the insulating medium layer is located on the gate electrode, the at least one Schottky diode unit is located on a surface of the insulating medium layer and insulated from the gate electrode via the insulating medium layer, the at least one Schottky diode unit comprises:
a first electrode located on the surface of the insulating medium layer, wherein the first electrode comprises a first metal layer and a second metal layer, the first metal layer covers the second metal layer, one end of the second metal layer is extended with respect to the first metal layer to form a step structure in the first electrode;
a second electrode located on the surface of the insulating medium layer and apart from the first electrode, wherein the second electrode comprises a third metal layer and a fourth metal layer, the third metal layer covers the fourth metal layer, one end of the third metal layer protrudes with respect to the fourth metal layer to form an inverted step structure in the second electrode; and
a semiconductor structure comprising a first end and a second end, wherein the first end of the semiconductor structure is sandwiched by the first metal layer and the second metal layer, the second end of the semiconductor structure is sandwiched by the third metal layer and the fourth metal layer, a portion of the semiconductor structure between the first end and the second end is defined as a middle portion, the step structure of the first electrode and the inverted step structure of the second electrode are both located between the first end and the second end of the semiconductor structure, and near the middle portion of the semiconductor structure, the semiconductor structure is a nano-scale semiconductor structure.

US Pat. No. 10,217,832

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate;
an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen;
a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and
an upper electrode that is provided above the insulating film, and contains Al as a main component, or Cu as a main component; wherein
a barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.

US Pat. No. 10,217,830

SEMICONDUCTOR DEVICE HAVING TRENCHES WITH ENLARGED WIDTH REGIONS

Infineon Technologies AG,...

1. A semiconductor device comprising:a plurality of trenches extending into a semiconductor substrate, wherein each trench of the plurality of trenches comprises a plurality of enlarged width regions distributed along the trench, and wherein at least one electrically conductive trench structure is located in each trench of the plurality of trenches;
an electrically insulating layer arranged between the semiconductor substrate and a first electrode structure; and
a first vertical electrically conductive structure extending through the electrically insulating layer, wherein the first vertical electrically conductive structure forms an electrical connection between the first electrode structure and an electrically conductive trench structure located in a first trench of the plurality of trenches at a first enlarged width region of the plurality of enlarged width regions of the first trench of the plurality of trenches, and
wherein the electrically insulating layer is arranged between a second enlarged width region of the plurality of enlarged width regions of the first trench and the first electrode structure or a second electrode structure above the second enlarged width region without any vertical electrical connections through the electrically insulating layer at the second enlarged width region.

US Pat. No. 10,217,829

COMPOUND SEMICONDUCTOR DEVICE INCLUDING DIFFUSION PREVENTING LAYER TO SUPPRESS CURRENT COLLAPSE PHENOMENON, METHOD OF MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE, POWER SUPPLY UNIT, AND AMPLIFIER

FUJITSU LIMITED, Kawasak...

1. A compound semiconductor device comprising:a substrate;
an electron transit layer formed on the substrate;
a compound semiconductor layer containing gallium and formed on the electron transit layer;
a diffusion preventing layer containing gallium oxide and formed on the compound semiconductor layer;
an insulation layer formed on the diffusion preventing layer;
a source electrode, a drain electrode, and a gate electrode formed over the electron transit layer at a distance from one another; and
a barrier layer formed on the electron transit layer,
wherein the compound semiconductor layer is a cap layer of gallium nitride formed on the barrier layer, and
the cap layer includes:
an upper layer located close to the diffusion preventing layer; and
a lower layer located below the upper layer,
wherein a composition ratio of gallium in the upper layer is smaller than a composition ratio of gallium in the lower layer.

US Pat. No. 10,217,828

TRANSISTORS WITH FIELD PLATES ON FULLY DEPLETED SILICON-ON-INSULATOR PLATFORM AND METHOD OF MAKING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:forming a silicon-on-insulator (SOI) substrate as a field plate on a field plate oxide;
forming a high-voltage p-type well in a p-type substrate of a bulk transistor on which the SOI substrate is formed, the high-voltage p-type well formed between shallow trench isolation (STI) regions of the p-type substrate;
forming an n-drift region in the high-voltage p-type well;
forming a first gate on the high-voltage p-type well; and
implanting a first n-type region adjacent to the gate as a source region and a second n-type region adjacent to the SOI substrate as a drain region,
wherein the SOI substrate comprises a silicon wafer with a buried oxide insulator, wherein the silicon wafer is the field plate and the buried oxide insulator is the field plate oxide.

US Pat. No. 10,217,824

CONTROLLED ION IMPLANTATION INTO SILICON CARBIDE USING CHANNELING AND DEVICES FABRICATED USING CONTROLLED ION IMPLANTATION INTO SILICON CARBIDE USING CHANNELING

Cree, Inc., Durham, NC (...

1. An electronic device, comprising:a silicon carbide drift region having a first conductivity type and a first doping concentration;
a well region in the drift region, the well region having a second conductivity type opposite the first conductivity type and having a second doping concentration; and
a deeply implanted region below the well region, wherein the deeply implanted region has a third doping concentration that is greater than the first doping concentration and less than the second doping concentration.

US Pat. No. 10,217,818

METHOD OF FORMATION OF GERMANIUM NANOWIRES ON BULK SUBSTRATES

International Business Ma...

1. A semiconductor structure comprising:a bulk substrate comprising a semiconductor material and having at least one notched surface portion and at least one recessed portion adjacent to the at least one notched surface portion of the substrate, wherein said at least one recessed portion has an uppermost horizontal surface below an uppermost surface of said at least once notched surface portion, and wherein said at least one notched surface portion of said bulk substrate has a pointed topmost surface;
a vertical stack of horizontal nanowires suspended directly above said at least one notched surface portion of said bulk substrate, wherein each horizontal nanowire of said vertical stack of horizontal nanowires consists of germanium and is of unitary construction, and wherein each horizontal nanowire has a horizontal planar topmost surface, a horizontal planar bottommost surface and faceted vertical sidewall surfaces, and wherein the planar topmost surface and the planar bottommost surface of each horizontal nanowire are parallel to a horizontal surface of said bulk substrate; and
a contiguous dielectric material layer located directly on an entire horizontal surface of said bulk substrate.

US Pat. No. 10,217,817

SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FORMATION IN STACKED-CHANNEL FETS

International Business Ma...

1. A method for forming a field effect transistor, comprising:forming a stack of nanosheets of alternating layers of channel material and sacrificial material, with a layer of sacrificial material forming a top layer of the stack;
forming a dummy gate over the stack;
etching away stack material outside of a region covered by the dummy gate;
selectively etching the sacrificial material to form recesses in the sacrificial material layers;
forming spacers in the recesses in the sacrificial material layers, with at least one pair of spacers being formed in recesses above an uppermost layer of channel material;
etching away the dummy gates with an anisotropic etch, where the top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch;
etching away the sacrificial material with an isotropic etch to expose the layers of channel material; and
forming a gate stack over and around the layers of channel material.

US Pat. No. 10,217,815

INTEGRATED CIRCUIT DEVICE WITH SOURCE/DRAIN BARRIER

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:receiving a workpiece that includes:
a substrate; and
a device fin extending above the substrate, wherein the device fin includes a channel region;
etching a portion of the device fin adjacent the channel region, wherein the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess;
cleaning the workpiece to remove a first portion of the dielectric barrier from the source/drain recess such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess; and
forming a source/drain feature within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

US Pat. No. 10,217,812

SILICON-ON-INSULATOR CHIP HAVING MULTIPLE CRYSTAL ORIENTATIONS

Infineon Technologies AG,...

1. A silicon-on-insulator device having multiple crystal orientations comprising:a substrate layer;
an insulating layer disposed on the substrate layer;
a first strained silicon layer having a first crystal orientation disposed directly on a portion of the insulating layer;
a strain inducing layer comprising a strained material disposed on another portion of the insulation layer; and
a second strained silicon layer disposed directly on the strain inducing layer so as to be spaced from the insulating layer by the strain inducing layer and having a crystal orientation different from the first crystal orientation.

US Pat. No. 10,217,811

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a silicon carbide layer having a front surface inclined at 0° or more and 10° or less with respect to a (0001) face;
a silicon oxide layer; and
a region located between the front surface and the silicon oxide layer and having the number of carbon-carbon single bonds larger than the number of carbon-carbon double bonds.

US Pat. No. 10,217,810

CAPACITOR FORMED ON HEAVILY DOPED SUBSTRATE

MICROCHIP TECHNOLOGY INCO...

1. A method for manufacturing a capacitor, the method comprising:depositing an oxide layer on a first side of a heavily doped substrate, wherein the oxide layer has a thickness of at least 14 ?m to provide a break down voltage above at least 6 kV;
depositing a first metal layer on the oxide layer; and
depositing a second metal layer on a second side of the heavily doped substrate so that the first metal layer and the second metal layer are physically separated at all points by the oxide layer; and
providing a first electrode connection to the first metal layer on the first side of the substrate and a second electrode connection to the second metal layer on the second side of the substrate.

US Pat. No. 10,217,809

METHOD OF FORMING RESISTORS WITH CONTROLLED RESISTIVITY

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:forming a doped metallic insulator layer having an insulating phase atop a substrate;
performing a controlled surface treatment process to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer having an electrical conducting phase, the electrical conducting resistive material layer is selected from the group consisting of a metallic nitride, a metallic oxide, and a metallic nitride-oxide;
patterning the doped metallic insulator layer and the electrical conducting resistive material layer to provide a resistor structure comprising a remaining portion of the doped metallic insulator layer and a remaining portion of the electrical conducting resistive material layer; and
forming an interconnect dielectric material on the substrate and the resistor structure.

US Pat. No. 10,217,808

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:an insulating base material;
a metal layer that is provided inside the insulating base material, and is electrically connected to an electric power supply;
an insulating layer that is provided over the insulating base material;
pixels arranged in a matrix form on the insulating layer, each of the pixels including an organic light emitting diode and a pixel circuit connected to the organic light emitting diode;
a power supply line which is arranged on the insulating layer and is connected to the pixels;
a driver integrated circuit connected to the pixels on the insulating layer;
a first through hole which is arranged in the insulating layer and electrically connects the power supply line and the metal layer to each other; and
second through holes which are arranged in the insulating layer and electrically connect the pixels and the metal layer to each other,
wherein the metal layer is arranged directly below the pixels and the power supply line,
wherein the metal layer continuously surrounds a pixel array including the pixels in a planar view, and
wherein the power supply line, the pixels, the second through holes, and the driver integrated circuit are arranged in sequential order.

US Pat. No. 10,217,807

ANISOTROPIC CONDUCTIVE FILM AND DISPLAY DEVICE USING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a substrate;
a display unit over the substrate;
a pad unit over one edge of the substrate and connected to the display unit;
a driving integrated circuit (IC) electrically connected to the pad unit; and
an anisotropic conductive film between the pad unit and the driving IC and electrically connecting the pad unit to the driving IC,
wherein the anisotropic conductive film comprises an adhesive resin insulating portion and a plurality of conductive particles dispersed in the adhesive resin insulating portion, and
wherein each of the plurality of conductive particles comprises a surface having a plurality of needle-shaped protrusions each having a conical shape, wherein some of the plurality of needle-shaped protrusions having the conical shape are stuck to the pad unit,
wherein the pad unit comprises a second layer and a third layer that are sequentially stacked, and
wherein the some of the plurality of needle-shaped protrusions having the conical shape contact the second layer through the third layer.

US Pat. No. 10,217,806

DISPLAY APPARATUS HAVING GROOVED TERMINALS

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus, comprising:a display panel comprising a display substrate on which a plurality of pad terminals are disposed; and
a driving unit comprising a plurality of driving terminals electrically connected to the plurality of pad terminals,
wherein each of the plurality of pad terminals includes a stepped groove that faces a corresponding driving terminal of the plurality of driving terminals or each of the plurality of pad terminals includes an opening hole that faces the corresponding driving terminal of the plurality of driving terminals.

US Pat. No. 10,217,805

DISPLAY APPARATUS

Sony Corporation, Tokyo ...

1. A display apparatus comprising:a plurality of pixels,
wherein each of the pixels includes:
a gate electrode of a driving transistor, a source region of the driving transistor is a portion of a polysilicon layer;
a first electrode of an accumulating capacitor that is physically connected to the gate electrode of the driving transistor, the gate electrode of the driving transistor is a portion of a lower layer and the first electrode of the accumulating capacitor is another portion of the lower layer;
a first electrode of an additional capacitor, a different portion of the lower layer is the first electrode of the additional capacitor;
a second electrode of the additional capacitor, a different portion of the polysilicon layer is the second electrode of the additional capacitor;
a second electrode of the accumulating capacitor that is physically connected to the second electrode of the additional capacitor, another portion of the polysilicon layer is the second electrode of the accumulating capacitor;
an intermediate layer between the lower layer and an upper layer, the intermediate layer is between the upper layer and the polysilicon layer; and
a first contact hole that at least partially overlaps a second contact hole in a plan view of a display panel, the second contact hole in the plan view of the display panel is larger than the first contact hole,
wherein a portion of the upper layer in the first contact hole is physically connected to the portion of the intermediate layer,
wherein the lower layer is a metal and the upper layer is a conductive layer that includes silver, the intermediate layer is a metal layer.

US Pat. No. 10,217,803

ORGANIC LIGHT-EMITTING DISPLAY AND AN ELECTRONIC APPARATUS INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting diode display comprising:a substrate comprising an active area and a dead area surrounding the active area;
a first organic light-emitting device disposed in the active area;
a second organic light-emitting device disposed in the dead area;
a sensor configured to sense light emitted from the second organic light-emitting device,
wherein the first organic light-emitting device emits light in a first direction, and the second organic light-emitting device emits light in a second direction that is opposite to the first direction and is toward the sensor;
an interlayer insulating layer disposed on the substrate; and
an insulating layer disposed on the interlayer insulating layer, wherein one of a first pixel electrode of the first organic light-emitting device or a second pixel electrode of the second organic light-emitting device is disposed between the insulating layer and the interlayer insulating layer, and the other one of the first pixel electrode and the second pixel electrode is not disposed between the insulating layer and the interlayer insulating layer.

US Pat. No. 10,217,802

ORGANIC LIGHT-EMITTING DISPLAY DEVICE WITH HIGH RESOLUTION AND HIGH DEFINITION

LG Display Co., Ltd., Se...

1. An organic light-emitting display (OLED) device comprising:a substrate having a display area including a plurality of sub-pixels each comprising an anode, an organic emitting layer and a cathode;
a first data line disposed on the substrate and configured to apply a first data voltage to a first sub-pixel emitting light of a first color and to a second sub-pixel emitting light of a second color different from the first color; and
a first line disposed between the first data line and an anode overlapping the first data line among the anodes of the plurality of sub-pixels,
wherein the first line is insulated from the first data line.

US Pat. No. 10,217,801

LIGHT-EMITTING STRUCTURE, DISPLAY DEVICE AND LIGHT SOURCE DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A light-emitting structure, comprising:a first light-emitting component and a second light-emitting component that are electrically connected, wherein,
the first light-emitting component comprises a first light-emitting layer and a second light-emitting layer, and the second light-emitting component comprises a third light-emitting layer;
a combination by electrical connection of the first light-emitting component and the second light-emitting component is driven by alternate current (AC) as a whole; the first light-emitting layer and the second light-emitting layer do not emit light at the same time;
the third light-emitting layer is configured to emit light at the same time as the first light-emitting layer and the third light-emitting layer is also configured to emit light at the same time as the second light-emitting layer;
the first light-emitting component further comprises an intermediate electrode; the second light-emitting component further comprises a fourth electrode; the intermediate electrode is connected to the fourth electrode via a second connection electrode, the intermediate electrode is in direct contact with the second connection electrode, and a center line of the second connection electrode, a center line of the intermediate electrode, and a center line of the fourth electrode are substantially on a same straight line.

US Pat. No. 10,217,800

RESISTANCE CHANGE MEMORY DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a resistance change element,
wherein the resistance change element includes:
first and second electrodes spaced apart from each other;
a metal material layer adjacent to the first electrode;
an oxide layer adjacent to each of the metal material layer and the first electrode; and
a resistance change layer disposed continuously between the second and first electrodes and between the second electrode and the oxide layer,
wherein the resistance change layer is made of a metal oxide,
wherein the metal material layer is made of a metal or a metal compound,
wherein the oxide layer is made of an oxide of the material forming the metal material layer,
wherein the first electrode is made of ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, gold, or copper, and
wherein a free energy of oxide formation of the oxide forming the oxide layer is higher than a free energy of oxide formation of the oxide forming the resistance change layer.

US Pat. No. 10,217,799

CELL PILLAR STRUCTURES AND INTEGRATED FLOWS

Micron Technology, Inc., ...

1. An apparatus, comprising:a source material including a transition metal combined with a semiconductor material;
an active switching device;
a memory stack arranged between the source material and the active switching device and having alternating levels of conductive materials and dielectric materials such that each level of conductive material is separated from another level of conductive material by a level of dielectric material, at least some of the conductive materials including a recessed charge storage structure formed substantially within a level of respective ones of the conductive material and separated from adjacent portions of the dielectric material by a charge-blocking dielectric material;
a buffer material formed between a level corresponding to the source material and the memory stack; and
a channel-fill material that is continuous from the source material to a level of the active switching device, the charge storage structures formed laterally away from the channel-fill material.

US Pat. No. 10,217,798

SYSTEMS AND METHODS FOR IMPLEMENTING SELECT DEVICES CONSTRUCTED FROM 2D MATERIALS

Inston, Inc., Santa Moni...

1. A stacked crossbar memory system comprising:a plurality of memory sub-systems and at least one insulation layer, wherein each insulation layer separates two of the plurality of memory sub-systems, wherein each memory sub-system comprises:
a first set of connection lines;
a second set of connection lines; and
an array of memory cells, each memory cell in the array comprising:
a select device; and
a memory device, wherein the memory device is one of: a spin-transfer torque random-access-memory device and a magneto-electric random-access-memory device;
wherein:
each memory cell in the array is coupled to a unique combination of one connection line in the first set of connection lines and one connection line in the second set of connection lines;
at least one of the select devices of the array of memory cells is crystalline; and
at least one of the select devices of the array of memory cells comprises a van der Waals heterostructure and thereby comprises a 2D material.

US Pat. No. 10,217,793

MASKLESS PARALLEL PICK-AND-PLACE TRANSFER OF MICRO-DEVICES

Applied Materials, Inc., ...

1. An apparatus for positioning micro-devices on a destination substrate, the apparatus comprising:a first support to hold a destination substrate;
a second support to provide or hold a transfer body having a surface to receive an adhesive layer;
one or more actuators configured to provide relative motion between the transfer body and the first support;
a light source to generate a light beam;
a mirror configured to adjustably position the light beam on the adhesive layer on the transfer body; and
a controller configured to
cause the one or more actuators to create relative motion such that a plurality of micro-devices attached to the adhesive layer on the transfer body contact the destination substrate,
cause the light source to generate the light beam and adjust the mirror to position the light beam on the adhesive layer so as to selectively expose one or more portions of the adhesive layer to create one or more neutralized portions, and
cause the one or more actuators to create relative motion such that the transfer body and the destination substrate are moved away from each other and one or more micro-devices corresponding to the one or more neutralized portions of the adhesive layer remain on the destination substrate.

US Pat. No. 10,217,791

METHOD OF MANUFACTURING BONDED SUBSTRATE, BONDED SUBSTRATE, METHOD OF MANUFACTURING SOLID-STATE IMAGING APPARATUS, SOLID-STATE IMAGING APPARATUS, AND CAMERA

Sony Corporation, Tokyo ...

1. A device comprising:a semiconductor layer having an electronic circuit;
a support substrate supporting the semiconductor layer;
a first bonding layer formed on a surface of and in direct physical contact with the semiconductor layer at the support substrate side; and
a second bonding layer formed on a surface of the support substrate at the semiconductor layer side and which is bonded to the first bonding layer,
wherein both the first bonding layer and the second bonding layer have silicon carbonitride, and
a layer having silicon carbonitride formed at a surface of at least a part of at least one of the first bonding layer and the second bonding laver.

US Pat. No. 10,217,790

IMAGING DETECTOR MODULE ASSEMBLY

KONINKLIJKE PHILIPS N.V.,...

1. A module assembly device configured for assembling a module assembly for a detector array of an imaging system, the module assembly including a module substrate, an application-specific integrated circuit (ASIC), a photo-detector array tile, and a scintillator, the module assembly device, comprising:a base having a long axis;
a first surface of the base;
side walls protruding perpendicular up from the first surface and extending in a direction of the long axis along at least two sides of the base, wherein the first surface and side walls form a recess configured to receive the module substrate on the surface and within the side walls; and
protrusions protruding from the side walls in a direction of the side walls, the protrusions and side walls interface forming a ledge which serves as a photo-detector array tile support configured to receive the photo-detector array tile directly over the ASIC and the module substrate.

US Pat. No. 10,217,788

IMAGING DEVICE

Ricoh Company, Ltd., Tok...

1. An imaging device comprising a plurality of arranged imaging elements,each of the plurality of imaging elements comprising:
a light-receiving element configured to generate charge from received light by photoelectric conversion,
a floating diffusion configured to convert the charge generated by the light-receiving element into voltage,
a charge transfer switch configured to transfer the charge from the light-receiving element to the floating diffusion,
a reset switch configured to reset the voltage of the floating diffusion, and
a source follower configured to amplify the voltage of the floating diffusion,
the reset switch being configured to reset the voltage of the floating diffusion a plurality of times for each of predetermined pixel groups in a single image data acquisition period, and
the charge transfer switch being configured to transfer the charge from the light-receiving element to the floating diffusion a plurality of times for each of the pixel groups in the single image data acquisition period.

US Pat. No. 10,217,785

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A solid-state imaging device including:a first substrate having a pixel circuit including a pixel array unit formed thereon;
a second substrate having a plurality of signal processing circuits formed thereon,
wherein the plurality of signal processing circuits are arranged adjacent to one another and include a spacing region therebetween,
wherein the first substrate and the second substrate are stacked,
wherein a first signal processing circuit of the plurality of signal processing circuits and a second signal processing circuit of the plurality of signal processing circuits are electrically connected, and
wherein the first signal processing circuit and the second signal processing circuit are electrically connected through a first wiring layer formed on the second substrate;
a first moisture-resistant structure that surrounds at least a part of a periphery of the first signal processing circuit; and
a second moisture-resistant structure that surrounds at least a part of a periphery of the second signal processing circuit.

US Pat. No. 10,217,783

METHODS FOR FORMING IMAGE SENSORS WITH INTEGRATED BOND PAD STRUCTURES

SEMICONDUCTOR COMPONENTS ...

1. Imaging circuitry, comprising:a substrate;
a first plurality of photodiodes in the substrate;
a second plurality of photodiodes in the substrate;
a light shielding layer on the substrate, wherein the light shielding layer has a shielding portion that covers the first plurality of photodiodes and shields the first plurality of photodiodes from receiving incoming light, wherein the light shielding layer has a grid portion that covers the second plurality of photodiodes, and wherein the second plurality of photodiodes receives incoming light through the grid portion;
a conductive layer over the light shielding layer, wherein a portion of the conductive layer serves as a bond pad region; and
a dielectric layer interposed between the conductive layer and the light shielding layer, wherein the dielectric layer has an opening and the conductive layer and the shielding portion are electrically connected through the opening.

US Pat. No. 10,217,782

IMAGE PICKUP MODULE AND MANUFACTURING METHOD OF IMAGE PICKUP MODULE

OLYMPUS CORPORATION, Tok...

1. An image pickup module comprising:an image pickup device including a light receiving surface where a light receiving portion is formed, an opposite surface opposing the light receiving surface, and an inclined surface inclined at an acute first angle to the light receiving surface, and provided with a plurality of electrode pads lined up on the inclined surface;
a transparent member joined through an adhesive layer so as to cover the light receiving surface of the image pickup device; and
a flexible wiring board arranged on a side of the opposite surface of the image pickup device and provided with a plurality of bond electrodes each bonded with each of the plurality of electrode pads of the image pickup device and lined up in parallel to an end side,
wherein the image pickup module further comprising a holding portion that is a triangular angle regulating portion extended from a side face of the wiring board, an angle of which formed by a first side and a second side is the first angle, and a resin member fixing the opposite surface of the image pickup device and a distal end portion of a main surface of the wiring board, a relative angle of which is regulated to the first angle by the holding portion; and
the holding portion and the wiring board are configured from a same base substance.

US Pat. No. 10,217,779

SYSTEMS AND METHODS FOR IMPROVING A SPECTRAL RESPONSE CURVE OF A PHOTO SENSOR

1. A photo sensor array comprising:a plurality of photodiodes;
a first portion of the plurality of photodiodes having a red filter;
a second portion of the plurality of photodiodes having a green filter;
a third portion of the plurality of photodiodes having a blue filter;
a fourth portion of the plurality of photodiodes having no filter
a fifth portion of the plurality of photodiodes having spectral photo sensors; and
a sixth portion of the plurality of photodiodes having temperature compensation sensors.

US Pat. No. 10,217,777

DISPLAY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE

Sony Corporation, Tokyo ...

1. A display device comprising, in this order:a substrate;
a semiconductor film;
a first insulating film;
a first metal film;
a second insulating film;
a second metal film;
a third insulating film;
a third metal film;
a fourth insulating film; and
a pixel electrode film,
wherein a pixel circuit region includes:
(1) a transistor including a first portion of the semiconductor film, a first portion of the first insulating film and a first portion of the first metal film;
(2) a first capacitor including a first portion of the second metal film, a first portion of the third insulating film and a first portion of the third metal film;
(3) a second capacitor including a second portion of the semiconductor film, a second portion of the first insulating film and a second portion of the first metal film; and
(4) a first wiring including a second portion of the second metal film, and the first wiring is electrically connected to the transistor,
wherein the first capacitor overlaps with the second capacitor in a plan view, and
wherein the pixel electrode film is disposed over the first capacitor.

US Pat. No. 10,217,776

SEMICONDUCTOR DEVICE COMPRISING FIRST METAL OXIDE FILM AND SECOND METAL OXIDE FILM

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first insulating film;
a first metal oxide film portion on and in contact with the first insulating film;
a second metal oxide film portion on and in contact with the first insulating film;
a transistor comprising the first metal oxide film portion as a channel formation region; and
a pixel electrode overlapping the second metal oxide film portion,
wherein a second insulating film is on and in direct contact with the second metal oxide film portion and overlaps the first metal oxide film portion,
wherein a third insulating film is interposed between the first metal oxide film portion and the second insulating film and overlaps the second metal oxide film portion, and
wherein a concentration in hydrogen of the second metal oxide film portion is greater than or equal to 8×1019 atoms/cm3.

US Pat. No. 10,217,773

ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, DISPLAY PANEL AND FABRICATION METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, whereina passivation layer of the array substrate is made of a black insulation material and the passivation layer is provided with an opening at a pixel display region of the array substrate,
the array substrate comprises a thin film transistor provided below the passivation layer and a pixel electrode provided on the passivation layer,
the passivation layer has a lower surface directly contacting the thin film transistor and an upper surface directly contacting the pixel electrode, and
a thickness of the passivation layer with its lower surface directly contacting the thin film transistor and its upper surface directly contacting the pixel electrode is no less than
where n represents an optical density of the black insulation material with a thickness of 1 micron, and the thickness of the passivation layer with its lower surface directly contacting the thin film transistor and its upper surface directly contacting the pixel electrode is no more than 1 micron.

US Pat. No. 10,217,772

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a first display element comprising a first electrode, the first display element electrically connected to a first transistor;
a second display element comprising a second electrode, the second display element electrically connected to a second transistor;
a third display element comprising a third electrode, the third display element electrically connected to a third transistor;
a fourth display element comprising a fourth electrode, the fourth display element electrically connected to a fourth transistor;
a first wiring;
a second wiring; and
a third wiring;
wherein the first transistor and the second transistor are along a first direction,
wherein the third transistor and the fourth transistor are along the first direction,
wherein the first transistor and the third transistor are along a second direction perpendicular to the first direction,
wherein the second transistor and the fourth transistor are along the second direction,
wherein the first electrode, the second electrode, the third electrode, and the fourth electrode, are along the second direction,
wherein the first wiring is electrically connected to a gate of the first transistor and a gate of the third transistor,
wherein the second wiring is electrically connected to a gate of the second transistor and a gate of the fourth transistor, and
wherein the third wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor.

US Pat. No. 10,217,771

THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor array panel comprising:a substrate;
a gate electrode on the substrate;
a gate insulating layer on the gate electrode;
a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween;
an interlayer insulating layer on the semiconductor member;
a data conductor on the interlayer insulating layer; and
a passivation layer on the data conductor,
wherein the interlayer insulating layer has a first hole on the channel region, and a second hole on the source region or the drain region,
the first hole and the second hole are separated from each other such that the interlayer insulating layer remains between the first hole and the second hole in a plan view, and
the data conductor is connected to the source region or the drain region via the second hole.

US Pat. No. 10,217,769

LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE USING THE SAME

Semiconductor Energy Labo...

1. A light-emitting device comprising:an adhesive layer over a flexible substrate;
a transistor over the flexible substrate with the adhesive layer therebetween, wherein the transistor comprises an oxide semiconductor layer, and wherein the oxide semiconductor layer is in contact with a source electrode layer and a drain electrode layer;
a first insulating film over and in contact with the transistor;
a color filter over and in contact with the first insulating film;
a second insulating film over and in contact with the color filter, the second insulating film comprising the same material as the first insulating film;
a partition layer over the second insulating film, the partition layer comprising a tapered surface and an even surface; and
a light-emitting element over the color filter, the light-emitting element comprising a first electrode over the color filter, an EL layer over the partition layer and the first electrode, and a second electrode over the EL layer,
wherein the transistor and the color filter overlap each other in a vertical direction, and
wherein the source electrode layer and the drain electrode layer are in direct contact with the color filter and the second insulating film in an opening of the color filter and an opening of the second insulating film.

US Pat. No. 10,217,767

THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor array panel comprising:a substrate;
a thin film transistor disposed on a surface of the substrate and including a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another, wherein the semiconductor is between the source electrode and the drain electrode;
a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material,
wherein a first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode;
a light blocking film disposed between the buffer layer and the substrate;
a gate conductor disposed on the substrate;
an interlayer insulating layer disposed on the thin film transistor and including a first contact hole overlapping the drain electrode, a second contact hole overlapping the light blocking film and a third contact hole overlapping the gate conductor, wherein a depth of the third contact hole is substantially the same as a depth of the first contact hole or a depth of the second contact hole.

US Pat. No. 10,217,766

SYSTEM ON CHIP FULLY-DEPLETED SILICON ON INSULATOR WITH RF AND MM-WAVE INTEGRATED FUNCTIONS

International Business Ma...

1. A method for fabricating radio frequency fully depleted silicon on insulator (RF-FDSOI) devices, the method comprising:constructing a silicon wafer for digital circuits using fully depleted silicon on insulator technology having a thin buried oxide layer; and
constructing localized areas of the silicon wafer comprising at least one of radio frequency circuits and passive devices, and further comprising a trap rich layer implanted underneath a thin buried oxide layer.

US Pat. No. 10,217,765

SEMICONDUCTOR INTEGRATED CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor integrated circuit comprising:a semiconductor layer of a first conductivity type stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the support substrate;
a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer;
a second well region of the first conductivity type buried in an upper part of the first well region; and
an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer so that the isolation region does not contact the first well region and does not contact the insulating layer.

US Pat. No. 10,217,764

LIGHT-EMITTING DEVICE AND INPUT/OUTPUT DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:a first substrate;
a transistor over the first substrate;
a first insulating layer over the transistor;
a first conductive layer over the first insulating layer;
a second insulating layer covering an edge portion of the first conductive layer;
a layer comprising an organic compound over the first conductive layer and the second insulating layer;
a second conductive layer over the layer;
a bonding layer over the second conductive layer;
a third conductive layer over and in contact with the bonding layer and the second conductive layer;
a third insulating layer over the third conductive layer;
a fourth conductive layer over the third insulating layer and the third conductive layer; and
a second substrate over the fourth conductive layer,
wherein the bonding layer comprises a resin,
wherein the first conductive layer is electrically connected to the transistor,
wherein the third conductive layer is electrically connected to the fourth conductive layer,
wherein the third insulating layer comprises an opening, and
wherein the fourth conductive layer and the opening of the third insulating layer overlap each other.

US Pat. No. 10,217,762

DOPING CHANNELS OF EDGE CELLS TO PROVIDE UNIFORM PROGRAMMING SPEED AND REDUCE READ DISTURB

SanDisk Technologies LLC,...

1. A memory device, comprising:a plurality of word line layers which are vertically spaced apart from one another by dielectric layers in a stack; and
a set of NAND strings extending through the plurality of word line layers, the set of NAND strings are arranged between first and second isolation regions which extend vertically in the stack, the set of NAND strings comprises NAND strings in a first edge region of the stack adjacent to the first isolation region and in a second edge region of the stack adjacent to the second isolation region, and NAND strings in an interior region between the first and second edge regions, the NAND strings in the first and second edge regions comprising doped channels and the NAND strings in the interior region comprising undoped channels.

US Pat. No. 10,217,761

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

MACRONIX International Co...

1. A semiconductor structure for a three-dimensional memory device, comprising:a substrate;
a stacked structure, disposed on the substrate and having a plurality of openings penetrating through the stacked structure and extending into the substrate, wherein the stacked structure comprises a plurality of insulating layers and a plurality of gate layers alternately stacked, each of the plurality of openings comprises a first portion located above a surface of the substrate and a second portion located below the surface of the substrate, and an aspect ratio of the second portion is greater than 1; and
an epitaxial layer, disposed in each of the plurality of openings, wherein a top surface of the epitaxial layer is between a top surface of and a bottom surface of an i-th insulating layer as counted upward from the substrate, and i?2.

US Pat. No. 10,217,759

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a semiconductor substrate;
a protruding portion which is a portion of the semiconductor substrate, protrudes from an upper surface of the semiconductor substrate, and extends in a first direction along the upper surface of the semiconductor substrate;
a first gate electrode formed over the protruding portion via a first insulating film and extending in a second direction orthogonal to the first direction;
a second gate electrode formed over the protruding portion via a second insulating film including a charge accumulation portion, adjacent to one of side surfaces of the first gate electrode via the second insulating film, and extending in the second direction; and
an n type source region and an n type drain region formed in an upper surface of the protruding portion so as to sandwich, in the first direction, a part of the protruding portion immediately below a pattern having the first gate electrode and the second gate electrode,
wherein the second gate electrode has an upper portion extending across the upper surface of the protruding portion and a lower portion extending along both side surfaces of the protruding portion,
wherein the first gate electrode, the second gate electrode, the source region, and the drain region constitute parts of a nonvolatile memory element, and
wherein an n type impurity concentration of the upper portion of the second gate electrode is lower than an n type impurity concentration of the lower portion of the second gate electrode.

US Pat. No. 10,217,757

SEMICONDUCTOR MEMORY DEVICE INCLUDING A SUBSTRATE, VARIOUS INTERCONNECTIONS, SEMICONDUCTOR MEMBER, CHARGE STORAGE MEMBER AND A CONDUCTIVE MEMBER

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a substrate;
a first interconnect provided on one side of the substrate in a first direction;
a second interconnect provided on the one side of the first interconnect;
a plurality of third interconnects extending in a second direction, being arranged to be separated from each other along the first direction, and being provided on the one side of the second interconnect, the second direction crossing the first direction;
a fourth interconnect provided on the one side of the third interconnects;
a semiconductor member extending in the first direction and piercing the plurality of third interconnects, one end portion of the semiconductor member being connected to the second interconnect;
a charge storage member provided between the semiconductor member and one of the plurality of third interconnects; and
a conductive member connected between the first interconnect and the fourth interconnect and insulated from the second interconnect and the plurality of third interconnects,
one of the plurality of third interconnects being disposed on two second-direction sides of the conductive member, and portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member being formed as one body.

US Pat. No. 10,217,756

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

United Microelectronics C...

1. A method for fabricating a semiconductor device, comprising:providing a substrate having a logic transistor and a non-volatile memory (NVM) cell thereon; and
forming a contact etching stop layer (CESL), comprising:
forming a first silicon nitride layer on the logic transistor but not on the NVM cell;
forming a silicon oxide layer on the first silicon nitride layer and on the NVM cell; and
forming a second silicon nitride layer on the silicon oxide layer over the logic transistor, and also on the silicon oxide layer on the NVM cell.

US Pat. No. 10,217,755

FLASH MEMORY CELLS, COMPONENTS, AND METHODS

Intel Corporation, Santa...

1. A flash memory component, comprising:a plurality of insulative layers vertically spaced apart from one another;
a vertically oriented conductive channel extending through the plurality of insulative layers;
a charge storage structure disposed between adjacent insulative layers and having a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side, wherein a length of the first side is greater than a length of the second side; and
a control gate positioned between the plurality of insulative layers and lateral to the charge storage structure such that the charge storage structure is between the control gate and the conductive channel, wherein no portion of the control gate extends between the insulative layers and the charge storage structure.

US Pat. No. 10,217,754

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

MACRONIX International Co...

1. A memory device, comprising:a substrate, having a first region, a second region, and a third region, wherein the third region is located between the first region and the second region and has a plurality of first self-align trenches;
a first embedded doped region extending along a first direction, and located in a portion of the substrate in a part of the first region, a portion of the substrate in a part of the second region, and a portion of the substrate in a part of the third region;
a second embedded doped region extending along a second direction, located in the substrate at bottoms and around sidewalls of the plurality of first self-align trenches in the third region, the first embedded doped region being electrically connected to the second embedded doped region, and the first direction being different from the second direction;
a plurality of control gates extending along the second direction, located at two sides of the second embedded doped region, and crossed over the first embedded doped region;
a plurality of floating gates, each of the plurality of floating gates being located between an overlapping control gate among the plurality of control gates and the substrate;
a plurality of tunneling dielectric layers, each of the plurality of tunneling dielectric layers being located between an overlapping floating gate among the plurality of floating gates and the substrate;
a plurality of inter-gate dielectric layers, each of the plurality of inter-gate dielectric layers being located between an underlying floating gate among the plurality of floating gates and an overlapping control gate among the plurality of control gates;
a plurality of first doped regions located in the substrate at two sides of each of the control gates in the first region;
a plurality of second doped regions located in the substrate at two sides of each of the control gates in the second region; and
a plurality of third doped regions located in the substrate in the third region, wherein
the first embedded doped region crosses under the plurality of control gates and is in contact with at least two of the plurality of first doped regions, at least two of the plurality of second doped regions and at least two of the plurality of third doped regions, and the second embedded doped region is electrically connected to the plurality of third doped regions.

US Pat. No. 10,217,752

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a memory cell comprising a first transistor, a second transistor, and a capacitor,
wherein:
a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and one electrode of the capacitor,
the first transistor and the second transistor each comprise an oxide semiconductor layer containing indium (In), an element M, and zinc (Zn),
in the first transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by g:h:i (each of g, h, i is a positive number),
in the second transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by d:e:f (each of d, e, f is a positive number), and
g/(g+h+i) is smaller than d/(d+e+f).

US Pat. No. 10,217,751

STATIC RANDOM ACCESS MEMORY DEVICE WITH HALO REGIONS HAVING DIFFERENT IMPURITY CONCENTRATIONS

RENESAS ELECTRONICS CORPO...

1. A method for manufacturing a semiconductor device having a static random access memory, comprising the steps of:defining a first element formation region and a second element formation region by forming an element isolation insulation film on a main surface of a semiconductor substrate, a transistor of first conductivity type being to be formed in said first element formation region, a transistor of second conductivity type being to be formed in said second element formation region;
forming a gate structure, the step of forming said gate structure including a step of forming an access gate structure above a region interposed between a first region and a second region and forming a drive gate structure above a region interposed between a third region and a fourth region in said first element formation region, a first source-drain region electrically connected to a predetermined bit line of a pair of bit lines being to be formed in said first region, a second source-drain region electrically connected to a storage node being to be formed in said second region, said first region and said second region being spaced away from each other, a third source-drain region electrically connected to said storage node being to be formed in said third region, a fourth source-drain region electrically connected to a ground interconnection being to be formed in said fourth region, said third region and said fourth region being spaced away from each other;
forming a first halo implantation mask that exposes a first side surface of said access gate structure at a side of said second region, said second region, said drive gate structure, said third region, and said fourth region, and that covers a second side surface of said access gate structure at a side of said first region, said first region, and said second element formation region;
implanting a first impurity of second conductivity type into the exposed regions of said semiconductor substrate through said first halo implantation mask, at an angle oblique to a direction perpendicular to said main surface;
forming a second halo implantation mask that exposes a first side surface of said drive gate structure at a side of said third region, said third region, said access gate structure, said first region, and said second region, and that covers a second side surface of said drive gate structure at a side of said fourth region, said fourth region, and said second element formation region;
implanting a second impurity of the second conductivity type into the exposed regions of said semiconductor substrate through said second halo implantation mask, at an angle oblique to the direction perpendicular to said main surface; and
forming said first source-drain region, said second source-drain region, said third source-drain region, and said fourth source-drain region by implanting an impurity of first conductivity type,
by forming said first source-drain region to said fourth source-drain region by implanting said first impurity of the second conductivity type and implanting said second impurity of the second conductivity type,
in a region just below said access gate structure, a first halo region having a first impurity concentration and the second conductivity type being formed adjacent to said first source-drain region, a second halo region having a second impurity concentration higher than said first impurity concentration and the second conductivity type being formed adjacent to said second source-drain region,
in a region just below said drive gate structure, a third halo region having a third impurity concentration and the second conductivity type being formed adjacent to said third source-drain region, a fourth halo region having a fourth impurity concentration and the second conductivity type being formed adjacent to said fourth source-drain region, said fourth impurity concentration being lower than said third impurity concentration and different from said first impurity concentration.

US Pat. No. 10,217,749

MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

UNITED MICROELECTRONICS C...

1. A manufacturing method of a semiconductor memory device, comprising:providing a semiconductor substrate having a memory cell region and a peripheral region defined thereon;
forming bit line structures on the memory cell region;
forming at least one gate structure on the peripheral region;
forming a spacer layer covering the semiconductor substrate, the gate structure, and the bit line structures, wherein the spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region;
performing a first etching process to the spacer layer for removing a part of the spacer layer on the memory cell region, wherein at least a part of the spacer layer remains on the memory cell region after the first etching process; and
performing a second etching process after the first etching process for removing the spacer layer remaining on the memory cell region, wherein the first etching process is different from the second etching process, the first etching process comprises an anisotropic etching process, and the second etching process comprises an isotropic etching process.

US Pat. No. 10,217,748

DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME

Winbond Electronics Corp....

1. A dynamic random access memory (DRAM) comprising:a bit line located on a substrate;
a capacitor contact aside the bit line, wherein an upper surface of the capacitor contact is higher than an upper surface of the bit line, such that upper sidewalls of the capacitor contact are exposed by the bit line;
a dielectric structure located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contact, wherein the dielectric structure comprises a first liner layer being partially removed for defining an opening exposing the upper surface of the capacitor contact;
a capacitor located above and electrically contacted to the capacitor contact; and
a landing pad formed in the opening, wherein the landing pad is located between the capacitor contact and the capacitor to electrically connect the capacitor contact and the capacitor together, the landing pad at least covers one portion of the upper surface of the capacitor contact, wherein a contact area between the landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.

US Pat. No. 10,217,746

THREE-DIMENSIONAL MEMORY DEVICE HAVING L-SHAPED WORD LINES AND A SUPPORT STRUCTURE AND METHODS OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, wherein each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion;
memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
a mesa structure located over the substrate, wherein each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure;
contact structures that contact a respective one of the non-horizontally-extending portions of the first electrically conductive layers;
a support structure extending through the first alternating stack; and
metal line structures having a respective first end portion that electrically contacts a respective contact structure and a respective second end portion that electrically contacts a respective contact pad structure;
wherein:
the mesa structure comprises a dielectric sidewall that contacts a sidewall of a non-horizontally-extending portion of a most proximal one of the first insulating layers;
the support structure comprises a support panel structure comprising a first sidewall that contacts a second dielectric sidewall of the mesa structure and sidewalls of the non-horizontally-extending portions of the first electrically conductive layers; and
each non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers has a respective pair of sidewalls that are parallel to the first dielectric sidewall of the mesa structure.

US Pat. No. 10,217,745

HIGH-K GATE DIELECTRIC AND METAL GATE CONDUCTOR STACK FOR FIN-TYPE FIELD EFFECT TRANSISTORS FORMED ON TYPE III-V SEMICONDUCTOR MATERIAL AND SILICON GERMANIUM SEMICONDUCTOR MATERIAL

INTERNATIONAL BUSINESS MA...

1. An electrical device comprising:a first fin structure and a second fin structure of a germanium containing semiconductor material;
an n-type FinFET including a channel region in the first fin structure, the n-type finFET including a n-type work function gate structure including a first interface layer of an aluminum containing dopant at an interface of the channel region, and a first metal work function adjusting layer; and
a p-type FinFET including a channel region in the second fin structure, the p-type finFET including a p-type work function gate structure including a second interface layer including a dopant of a group IIA element, a group IIIB element or a combination thereof at an interface of the channel region, wherein the first interface layer includes oxygen to provide an oxygen source so that the oxygen vacancy concentration in the p-type FinFET is greater than an oxygen vacancy concentration in the n-type FinFET.

US Pat. No. 10,217,743

DETECTING PROCESS VARIATION OF MEMORY CELLS

ARM Limited, Cambridge (...

1. An integrated circuit, comprising:a memory cell array disposed in a first area of the integrated circuit, the memory cell array having memory cells with first transistors of multiple types; and
a process sensor disposed in a second area of the integrated circuit that is different than the first area, the process sensor having a process detector with second transistors of the multiple types that are separate from the first transistors,
wherein the second transistors of the process detector are arranged for detecting process variation of the memory cells of the memory cell array based at least in part on detecting a process point of the memory cells skewing to a process corner of one or more process corners.

US Pat. No. 10,217,741

FIN STRUCTURE AND METHOD OF FORMING SAME THROUGH TWO-STEP ETCHING PROCESSES

Taiwan Semiconductor Manu...

1. A method comprising:in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device region simultaneously, wherein a first semiconductor strip is formed between the first recesses, and a second semiconductor strip is formed between the second recesses;
in a second etching step, etching the semiconductor substrate in the second device region to extend the second recesses lower than the first recesses, wherein when the semiconductor substrate in the second device region is etched, portions of the semiconductor substrate on opposite sides of the first semiconductor strip are etched to form a semiconductor base, and wherein a plurality of semiconductor strips comprising the first semiconductor strip are on top of the semiconductor base;
filling the first recesses and the second recesses with a dielectric material to form first isolation regions in the first recesses and second isolation regions in the second recesses;
recessing the first isolation regions and the second isolation regions, wherein portions of the semiconductor substrate in the first device region protrude higher than top surfaces of the first isolation regions to form a first semiconductor fin, and portions of the semiconductor substrate in the second device region protrude higher than top surfaces of the second isolation regions to form a second semiconductor fin; and
wherein after the second etching step, the first semiconductor strip has a first sidewall having a first straight portion close to a bottom of the first semiconductor strip, and the second semiconductor strip has a second sidewall having a second straight portion close to a bottom of the second semiconductor strip, and the first sidewall has a first tilt angle smaller than a second tilt angle of the second sidewall.

US Pat. No. 10,217,737

CASCODE SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device comprising:a semiconductor substrate having a first major surface and an opposing second major surface, wherein the semiconductor substrate comprises a first doped region having a first conductivity type adjacent the second major surface;
a heterostructure adjacent the first major surface, wherein the heterostructure comprises:
a channel layer comprising a group III-V material; and
a barrier layer disposed over the channel layer and comprising a group III-V material;
a first electrode disposed proximate to a first portion of the channel layer;
a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode;
a control electrode disposed between the first electrode and the second electrode;
a first trench electrode extending through the heterostructure into the semiconductor substrate, wherein the first trench electrode is electrically coupled to the first electrode;
a second trench electrode extending through the heterostructure and the semiconductor substrate at least to the first doped region, wherein the second trench electrode electrically connects the control electrode to a third electrode disposed adjacent to the second major surface, and wherein the control electrode is electrically coupled to the third electrode through the semiconductor substrate; and
a rectifier device comprising a second doped region of a second conductivity type opposite to the first conductivity type disposed adjoining the first trench electrode in the semiconductor substrate, wherein:
the rectifier device is electrically coupled to the first trench electrode and electrically coupled to the third electrode, but not electrically coupled to the second electrode;
the rectifier device is configured to provide a current path generally perpendicular to the channel layer; and
the semiconductor device is configured as a two terminal device.

US Pat. No. 10,217,736

SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND CAPACITOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:a semiconductor;
a first conductive film and a second conductive film each comprising a region in contact with a top surface and a side surface of the semiconductor;
a first insulating film comprising a region in contact with the top surface and the side surface of the semiconductor;
a third conductive film comprising a region facing the top surface and the side surface of the semiconductor with the first insulating film between the third conductive film and the semiconductor;
a second insulating film which is in contact with the first conductive film and comprises an opening reaching the first conductive film;
a fourth conductive film comprising a first region facing the first conductive film and a second region in contact with a side surface of the opening;
a third insulating film comprising a region facing the first region and the side surface of the opening with the fourth conductive film between the third insulating film and the side surface of the opening; and
a fifth conductive film comprising a region facing the fourth conductive film with the third insulating film between the fifth conductive film and the fourth conductive film;
wherein a part of a top surface of the fourth conductive film is located below a bottom surface of the semiconductor.

US Pat. No. 10,217,735

SEMICONDUCTOR SWITCH DEVICE

NXP B.V., Eindhoven (NL)...

1. A semiconductor switch device comprisinga field effect transistor located on a semiconductor substrate,
wherein the field effect transistor comprises a plurality of gates,
each gate comprising a gate electrode and gate dielectric arranged in a loop on a major surface of the substrate,
wherein the loops formed by the gates are arranged concentrically;
wherein adjacent to each gate is
a source region located adjacent to one of an inner edge or an outer edge of the loop formed by that gate and
a drain region located adjacent to another of said inner edge or said outer edge of the loop formed by that gate;
wherein the field effect transistor includes at least one isolation region arranged in a loop; and
wherein the loop formed by the isolation region is located in between the source or drain region adjacent to the inner edge of one of said gates and the source or drain region adjacent to the outer edge of another of said gates.

US Pat. No. 10,217,734

SEMICONDUCTOR DEVICE

DENSO CORPORATION, Kariy...

1. A semiconductor device comprising:a control unit that controls a potential difference between a first terminal and a second terminal of a switching element to a predetermined clamp voltage, the switching element being connected in series to a load between a power source node having a power source potential and a first reference node having a predetermined reference potential, the first terminal of the switching element being adjacent to the power source node and the second terminal of the switching element being adjacent to the first reference node, the switching element including a control terminal for controlling a current flowing between the first terminal and the second terminal;
a first clamping circuit that is connected between the first terminal and the control terminal, and is energized at a voltage equal to or higher than a first clamp voltage;
a second clamping circuit that is connected between the control terminal and a second reference node having a reference potential of the control unit, and clamps the potential difference to a second clamp voltage lower than the first clamp voltage by charging or discharging charges of the control terminal; and
a third clamping circuit that is connected between the control terminal and the second terminal, and discharges the charges of the control terminal, wherein
the control unit includes a current detector that detects a load current flowing in the load, and
the control unit activates the second clamping circuit when the load current is equal to or greater than a predetermined threshold, and activates the third clamping circuit when a predetermined time period elapses after the second clamping circuit is activated.

US Pat. No. 10,217,733

FAST SCR STRUCTURE FOR ESD PROTECTION

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device for protection against electrostatic discharge (ESD), the device comprising:a substrate, the substrate being a semiconductor of a first conductivity type;
a lightly-doped epitaxial layer on the substrate with an intervening heavily-doped buried layer in at least one region, the epitaxial layer and buried layer having a second conductivity type different than the first; and
a semiconductor-controlled rectifier (SCR) structure within said at least one region, the SCR structure including, between a ground terminal and a pad terminal:
a first shallow region heavily-doped to be of the first conductivity type within a first well moderately-doped to be of the second conductivity type, the first shallow region and first well forming an emitter-base junction of a trigger transistor;
a second shallow region heavily-doped to be of the second conductivity type within a second well moderately-doped to be of the first conductivity type, the second shallow region and second well forming an emitter-base junction of a latching transistor, wherein the first and second wells are separated by a lightly-doped portion of the epitaxial layer;
a PN junction coupled to either the first or second shallow region as a series diode that is forward-biased for current flow from the pad terminal to the ground terminal to increase a holding voltage of the SCR structure; and
a third well moderately-doped to be of the first conductivity type, the third well interposed between the second well and the lightly-doped portion of the epitaxial layer to enhance a holding current of the device.

US Pat. No. 10,217,732

TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS

INTEL CORPORATION, Santa...

1. An integrated circuit comprising:a substrate;
a grid including diffusion lines extending from the substrate: and
an array of functional cells including two adjacent cells, the two adjacent cells at least in part on at least three diffusion lines included in the grid, each cell having a boundary with no diffusion lines between the boundaries of the two adjacent cells, such that one of the two adjacent cells includes two or more of the at least three diffusion lines and the other of the two adjacent cells includes one or more of the at least three diffusion lines;
wherein a distance between the boundaries of the two adjacent cells is less than 50 nanometers (nm).

US Pat. No. 10,217,731

METHOD OF PRODUCING OPTOELECTRONIC MODULES AND AN ASSEMBLY HAVING A MODULE

OSRAM Opto Semiconductors...

1. A method of producing a plurality of optoelectronic modules comprising:A) providing a metal carrier composite having a plurality of carrier units,
B) applying at least one logic chip each having at least one integrated circuit to the carrier units,
C) attaching a plurality of light-emitting diode chips comprising in each case multiple emitter regions individually electrically-controllable, which are based on a semiconductor material and configured to generate radiation and can be controlled individually, to the logic chips attached to the carrier units,
D) covering the emitter regions and the logic chips with a protective material so that upper sides of at least one of the emitter regions and the logic chips facing away from the carrier units are covered by the protective material,
E) molding around the emitter regions and the logic chips so that a cast body is produced, which connects at least the carrier units and the logic chips with one another,
F) removing the protective material and applying electrical conductor paths at least to the upper sides of the logic chips and to a cast body upper side of the cast body facing away from the carrier units, and
G) severing the carrier assembly into the modules, wherein the carrier units as a whole or at least carrier isles on which the emitter regions and the logic chip are located do not have any electrical function in the finished module, and electrically controlling the emitter regions is effected exclusively via the logic chip of the respective module.

US Pat. No. 10,217,730

EFFICIENTLY MICRO-TRANSFER PRINTING MICRO-SCALE DEVICES ONTO LARGE-FORMAT SUBSTRATES

X-Celeprint Limited, Cor...

1. A method of making a micro-transfer printed system, comprising:providing a source wafer having a plurality of micro-transfer printable source devices arranged in or on the source wafer at a source spatial density;
providing an intermediate wafer having a plurality of micro-transfer printable intermediate supports arranged in or on the intermediate wafer at an intermediate spatial density less than or equal to the source spatial density;
providing a destination substrate;
micro-transfer printing the source devices from the source wafer to the intermediate supports of the intermediate wafer with a source stamp having a plurality of stamp posts at a source transfer density to make an intermediate device on each intermediate support; and
micro-transfer printing the intermediate devices from the intermediate wafer to the destination substrate at a destination spatial density less than the source spatial density with an intermediate stamp having a plurality of stamp posts at an intermediate transfer density less than the source transfer density.

US Pat. No. 10,217,729

APPARATUS FOR MICRO PICK AND BOND

Intel Corporation, Santa...

1. A method of transferring micro light emitting diodes (LEDs), comprising:aligning a donor substrate with a macro transfer head, wherein the donor substrate includes a plurality of micro LEDs, and wherein the macro transfer head includes a plurality of micro transfer heads;
moving the donor substrate towards the macro transfer head so that the plurality of micro LEDs each contact one of the micro transfer heads, wherein the micro transfer heads each secure one of the micro LEDs;
removing the micro LEDs from the donor substrate by moving the donor substrate away from the macro transfer head;
aligning a host substrate with the macro transfer head;
moving the host substrate towards the macro transfer head so that the plurality of micro LEDs contact the host substrate; and
bonding the micro LEDs to the host substrate; wherein the macro transfer head is substantially stationary during the transfer process.

US Pat. No. 10,217,727

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING A FIRST SEMICONDUCTOR CHIP INCLUDING AN INSULATED GATE BIPOLAR TRANSISTOR AND A SECOND SEMICONDUCTOR CHIP INCLUDING A DIODE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a first semiconductor chip including an insulated gate bipolar transistor, a first front surface in which an emitter electrode pad is formed, and a first back surface in which a collector electrode is formed and which is a surface opposite to the first front surface;
a second semiconductor chip including a diode, a second front surface in which an anode electrode pad is formed and a second back surface in which a cathode electrode is formed and which is a surface opposite to the second front surface;
a first chip mounting portion including a first upper surface on which the first semiconductor chip is mounted and which is electrically connected to the first back surface of the first semiconductor chip, and a first lower surface which is a surface opposite to the first upper surface;
a second chip mounting portion including a second upper surface on which the second semiconductor chip is mounted and which is electrically connected to the second hack surface of the second semiconductor chip, and a second lower surface which is a surface opposite to the second upper surface;
a first lead electrically connected to the emitter electrode pad of the first semiconductor chip via a first conductive member;
a second lead electrically connected to the anode electrode pad of the second semiconductor chip via a second conductive member; and
a sealing material including a first main surface which includes a first side and a second side opposite to the first side, and a second main surface which is a surface opposite to the first main surface, the sealing material sealing the first semiconductor chip, the second semiconductor chip, a part of the first chip mounting portion, a part of the second chip mounting portion, a part of the first lead, and a part of the second lead,
wherein the first lower surface of the first chip mounting portion and the second lower surface of the second chip mounting portion are exposed from the second main surface of the sealing material,
wherein the first lead and the second lead are arranged so as to line along the first side of the sealing material extending in a first direction in a plan view,
wherein the first chip mounting portion is electrically separated from the second chip mounting portion,
wherein the first conductive member is electrically separated from the second conductive member,
wherein the emitter electrode pad, of the insulated gate bipolar transistor is electrically isolated from the anode electrode pad of the diode, and
wherein the collector electrode of the insulated gate bipolar transistor is electrically isolated from the cathode electrode of the diode.

US Pat. No. 10,217,726

STACKED SEMICONDUCTOR DIES INCLUDING INDUCTORS AND ASSOCIATED METHODS

Micron Technology, Inc., ...

1. A semiconductor device comprising:a package substrate having an upper surface and a lower surface;
a stack of dies attached to the upper surface of the substrate, wherein the stack includes—
a first die including a front side and one or more first inductors at the front side; and
a second die disposed over and offset from the first die, the second die including a front side facing the first die and one or more second inductors at the front side of the second die, wherein one or more of the second inductors are inductively coupled to one or more of the first inductors;
a first plurality of wirebonds electrically coupling a first plurality of substrate bond pads on the upper surface of the substrate to a first plurality of die bond pads on the front side of the first die;
a second plurality of wirebonds electrically coupling a second plurality of substrate bond pads on the lower surface of the substrate to a second plurality of die bond pads on the front side of the second die; and
a mold material encapsulating at least a portion of the stack and the substrate, wherein the mold material covers only a portion of each of the second plurality of wirebonds.

US Pat. No. 10,217,725

MICROSTRUCTURE MODULATION FOR METAL WAFER-WAFER BONDING

International Business Ma...

1. A three-dimensional (3D) bonded semiconductor structure comprising:a first structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and at least one first metallic bonding structure embedded in the first bonding oxide layer; and
a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and at least one second metallic bonding structure embedded in the second bonding oxide layer, wherein each of the first and second metallic bonding structures has a columnar grain microstructure, and wherein a bonding interface is present between the first and second bonding oxide layers and another bonding interface is present between the at least one first and second metallic bonding structures, wherein at least one columnar grain extends across the another bonding interface that is present between the first and second metallic bonding structures.

US Pat. No. 10,217,724

SEMICONDUCTOR PACKAGE ASSEMBLY WITH EMBEDDED IPD

MediaTek Inc., Hsin-Chu ...

1. A semiconductor package assembly, comprising:a first semiconductor package, comprising:
a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto;
a first semiconductor die disposed on the first surface of the first RDL structure;
a first molding compound disposed on the first surface of the first RDL structure and surrounding the first semiconductor die; and
an integrated passive device (IPD) embedded in the first RDL structure, wherein:
the IPD is electrically coupled to the first semiconductor die located above the IPD through the first RDL structure,
the IPD comprises first and second electrode layers disposed respectively at least on first and second portions of a lower surface of a body of the IPD, and
the first electrode layer of the IPD is electrically coupled to a first conductive trace of the first RDL structure and the second electrode layer of the IPD is electrically coupled to a second conductive trace of the first RDL structure, the first and second conductive traces being located below the body of the IPD.

US Pat. No. 10,217,723

SEMICONDUCTOR PACKAGE WITH IMPROVED BANDWIDTH

MEDIATEK INC., Hsin-Chu ...

1. A semiconductor chip package, comprising:a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and second semiconductor die are coplanar and disposed in proximity to each other in a side-by-side fashion;
a non-straight line shaped interface gap between the first semiconductor die and second semiconductor die;
a molding compound surrounding the first semiconductor die and second semiconductor die; and
a redistribution layer (RDL) structure on the first semiconductor die, the second semiconductor die and on the molding compound, wherein the first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.

US Pat. No. 10,217,720

MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTE WAFER

Invensas Corporation, Sa...

1. An apparatus for a microelectronic device, comprising:a first integrated circuit die having first contacts on a die surface thereof in a molding layer of a reconstituted wafer having a wafer surface including a layer surface of the molding layer and the die surface of the first integrated circuit die;
a redistribution layer on the wafer surface including electrically conductive layers and dielectric layers to provide conductive routing and shortest path vertically oriented conductors, the conductors extending away from the die surface of the first integrated circuit die and respectively coupled to the first contacts at bottom ends of the conductors;
at least second and third integrated circuit dies respectively having second contacts on die surfaces thereof interconnected to the first integrated circuit die through the conductors of the redistribution layer;
a first portion of the second contacts of each of the at least second and third integrated circuit dies interconnected to top ends of the conductors opposite the bottom ends thereof, the top ends of the conductors in part for alignment of the at least second and third integrated circuit dies to the first integrated circuit die located below the redistribution layer; and
a second portion of the second contacts interconnected to one another through the conductive routing.

US Pat. No. 10,217,717

DISTRIBUTION OF ELECTRONIC CIRCUIT POWER SUPPLY POTENTIALS

STMicroelectronics (Rouss...

1. An integrated circuit, comprising:a first peripheral conductive pad located adjacent a first edge of an integrated circuit chip;
a second peripheral conductive pad located adjacent a second edge of the integrated circuit chip, said second edge being opposite from the first edge;
wherein the first and second peripheral conductive pads are interconnected by a first peripheral conductive track within the integrated circuit chip;
a first conductive wire external to the integrated circuit chip, said first conductive wire having a first end in direct contact with the first peripheral conductive pad and having a second end in direct contact with the second peripheral conductive pad;
a package encapsulating the integrated circuit chip and said first conductive wire, wherein said package includes an external terminal; and
a further conductive wire having a first end in direct contact with said external terminal and having a second end in direct contact with a third peripheral conductive pad, said third peripheral conductive pad being connected to the first peripheral conductive track; and
said package further encapsulating the further conductive wire.

US Pat. No. 10,217,707

TRENCH CONTACT RESISTANCE REDUCTION

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a source/drain over a semiconductor substrate;
epitaxially growing a single sacrificial layer directly in contact with only the source/drain to protect the source/drain from subsequent etches;
forming an inter-level dielectric (ILD) layer contacting the single sacrificial layer;
forming a first portion of trenches that extend through the ILD layer at an oblique angle with respect to the semiconductor substrate, and into a first section of the single sacrificial layer such that the single sacrificial layer remains in contact with an entire upper surface of the source/drain;
removing a second section of the single sacrificial layer to expose the entire upper surface of the source/drain and to create a second portion of the trenches which extends laterally beyond sidewalls of the first portion of the trenches; and
filling the first and second portions of the trenches with a plurality of conducting materials extending laterally over all the exposed portions of the source/drain.

US Pat. No. 10,217,705

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first conductive element;
a first insulating layer and a second insulating layer sequentially stacked on the first conductive element;
a conductive via in the first insulating layer and the second insulating layer, wherein the conductive via is connected to the first conductive element;
a via extension portion in the second insulating layer, the via extension portion extending along an upper surface of the first insulating layer from one side surface of the conductive via; and
a second conductive element on the second insulating layer, wherein the second conductive element is connected to the via extension portion.

US Pat. No. 10,217,704

METHOD FOR SIMULTANEOUS MODIFICATION OF MULTIPLE SEMICONDUCTOR DEVICE FEATURES

1. A method, comprising:simultaneously modifying a plurality of features of a previously manufactured semiconductor device, wherein the semiconductor device comprises a plurality of layers deposited on a substrate, the plurality of layers defining the plurality of features of the semiconductor device, the modifying the plurality of features comprising:
applying a mask layer to the previously manufactured semiconductor device;
forming a pattern in the mask layer, the pattern aligned with the plurality of features of the semiconductor device;
etching one or more of the layers based upon the pattern to create a plurality of vias, each of the vias extending through one or more of the layers to a respective feature in the features; and
forming a plurality of connections between the features and a surface of the semiconductor device by way of the vias.

US Pat. No. 10,217,702

SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN EMBEDDED SOP FAN-OUT PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a semiconductor package including a first semiconductor die and a first encapsulant disposed over the first semiconductor die;
disposing a second semiconductor die over the semiconductor package;
forming a plurality of bumps over the semiconductor package and around the second semiconductor die;
depositing a second encapsulant in contact with the semiconductor package and around the second semiconductor die and in contact with the bumps, wherein a portion of the bumps extends outward beyond the second encapsulant and an active surface of the second semiconductor die is coplanar with a surface of the second encapsulant; and
forming an interconnect structure over the second semiconductor die and second encapsulant and contacting the bumps after depositing the second encapsulant.

US Pat. No. 10,217,700

LEAD FRAME FOR INTEGRATED CIRCUIT DEVICE HAVING J-LEADS AND GULL WING LEADS

NXP USA, INC., Austin, T...

1. An article of manufacture, comprising:a central die receiving area configured for receiving at least one integrated circuit die;
a plurality of first leads surrounding the die receiving area and extending outwardly therefrom in a first plane;
a plurality of second leads surrounding the die receiving area and extending outwardly therefrom in the first plane,
wherein the plurality of second leads are interleaved with the plurality of first leads;
wherein each lead of the pluralities of first and second leads has a first inner lead area proximate to the die receiving area, said first inner lead area configured for electrical connection to bonding pads of the at least one integrated circuit die, a second inner lead area extending from the first inner lead area to a package boundary, and an outer lead area that extends beyond the package boundary; and
wherein each of the second leads includes a down-set portion that extends from the second inner lead area to the outer lead area, wherein the down-set portion facilitates maintaining the first inner lead area in the first plane when a force from a mold tool presses the outer lead area proximate to the inner lead areas downwards.

US Pat. No. 10,217,696

NON-BRIDGING CONTACT VIA STRUCTURES IN PROXIMITY

International Business Ma...

1. A structure comprising:a stack of a template layer and a contiguous spacer layer, wherein said contiguous spacer layer is located on an entire topmost surface of said template layer, and wherein sidewall surfaces of said template layer are vertically aligned to sidewall surfaces of said contiguous spacer layer;
an etch-resistant material portion overlying an entirety of a recessed portion of said stack, wherein said etch resistant material portion has sidewall surfaces that are vertically aligned to sidewall surfaces of said recessed portion of said stack; and
a pair of via structures embedded within said stack and laterally spaced by said etch-resistant material portion and said recessed portion of said stack, wherein a top surface of said contiguous spacer layer, a top surface of said etch-resistant material portion, and top surfaces of said pair of via structures are coplanar among one another, and wherein said etch-resistant material portion has an H-shaped pattern, and a lateral extent of said pair of via structures is bounded by a pair of parallel line portions within said H-shaped pattern.

US Pat. No. 10,217,695

CONNECTOR BLOCK WITH TWO SORTS OF THROUGH CONNECTIONS, AND ELECTRONIC DEVICE COMPRISING A CONNECTOR BLOCK

Infineon Technologies AG,...

1. A connector block for providing a vertical interconnection between opposing main surface regions of a semiconductor package, the connector block comprising:an encapsulant;
at least one first electrically conductive through connection, in particular a plurality of first electrically conductive through connections, extending through the encapsulant from a first surface of the encapsulant to a second surface of the encapsulant;
at least one second electrically conductive through connection, in particular a plurality of second electrically conductive through connections, extending along an exterior third surface of the encapsulant from the first surface of the encapsulant to the second surface of the encapsulant,
wherein a cross-sectional area of the at least one first electrically conductive through connections is larger than a cross sectional area of the at least one second electrically conductive through connections in a plane perpendicular to a direction extending from the first surface of the encapsulant to the second surface of the encapsulant by a factor of at least 3.

US Pat. No. 10,217,694

LDMOS TRANSISTOR AND METHOD

Infineon Technologies AG,...

1. A method for electrically coupling an electrode of a transistor structure arranged at a first surface of a substrate to a third conductive layer arranged at a second surface of the substrate opposing the first surface, the method comprising:forming a blind via in the substrate adjacent the transistor structure;
depositing a first conductive layer onto side walls of the blind via and a region of a second conductive layer arranged on the first surface of the substrate adjacent the blind via and coupled to the electrode of the transistor structure, the first conductive layer consists of a single integral unit consisting of a same material throughout;
working the second surface of the substrate so as to expose a portion of the first conductive layer; and
depositing the third conductive layer onto the second surface of the substrate and the portion of the first conductive layer so as to electrically couple the third conductive layer with the electrode of the transistor structure,
wherein the transistor structure is a LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor structure and the electrode is a highly doped source region of a silicon substrate, wherein the source region has a doping concentration of at least 5·1019 cm?3,
wherein the single integral unit of the first conductive layer directly contacts a sidewall of the blind via and directly contacts a portion of the first surface of the substrate between the sidewall of the blind via and the region of the second conductive layer arranged on the first surface.

US Pat. No. 10,217,691

HEAT SPREADER WITH OPTIMIZED COEFFICIENT OF THERMAL EXPANSION AND/OR HEAT TRANSFER

NLIGHT, Inc., Vancouver,...

1. An apparatus comprising:a heat spreader having a heat source coefficient of thermal expansion (HS CTE), the heat spreader comprising an anisotropic material having a high expansion axis and a low expansion axis oblique to the high expansion axis;
a surface of the heat spreader configured to couple to a heat source, wherein the high expansion axis of the anisotropic material is oblique to the surface of the heat spreader and wherein the high expansion axis of the anisotropic material is oriented at a first angle of rotation about a first axis of the heat spreader wherein the first angle of rotation is selected to optimize a match of a first CTE of the heat spreader with the HS CTE.

US Pat. No. 10,217,689

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor integrated circuit device comprising:an insulating substrate;
a via which penetrates through the insulating substrate;
a first metal layer disposed on a front surface of the insulating substrate;
a first resist layer disposed on the first metal layer in the vicinity of the via;
a solder layer disposed on the first metal layer, the via and the first resist layer;
a gap region formed between the solder layer and the first resist layer; and
a semiconductor integrated circuit, including an island and a semiconductor integrated circuit chip, disposed on the solder layer,
wherein the island is fused to the solder layer and the semiconductor integrated circuit chip is disposed on the island.

US Pat. No. 10,217,688

ELECTRONIC COMPONENT HAVING A HEAT-SINK THERMALLY COUPLED TO A HEAT-SPREADER

Infineon Technologies Aus...

1. An electronic component, comprising:one or more semiconductor dice embedded in a first dielectric layer;
a heat-spreader embedded in a second dielectric layer, wherein the heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice; and
a heat-sink thermally coupled to the heat-spreader, wherein the heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice, and the heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor dice.

US Pat. No. 10,217,687

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a conductive pad over the semiconductor substrate;
a conductor over the conductive pad;
a polymeric material over the semiconductor substrate and surrounding the conductor; and
a seed layer between the polymeric material and the conductor,wherein a bottom surface and longitudinal sidewalls of the conductor are in contact with the seed layer, a top surface of the conductor is entirely exposed through the seed layer and the polymeric material, and the top surface of the polymeric material is entirely exposed through the seed layer.

US Pat. No. 10,217,685

AIR-CAVITY PACKAGE WITH DUAL SIGNAL-TRANSITION SIDES

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a bottom package precursor, which comprises a bottom substrate and a bottom electronic component, wherein:
the bottom substrate comprises a bottom substrate body having an upper side and a lower side, at least one first bottom metal structure on the upper side of the bottom substrate body, at least one second bottom metal structure on the lower side of the bottom substrate body, and at least one bottom signal via that extends from the upper side of the bottom substrate body through the bottom substrate body to the lower side of the bottom substrate body and is electrically coupled to the at least one second bottom metal structure; and
the bottom electronic component is mounted on the upper side of the bottom substrate body and electrically coupled to the at least one bottom signal via;
providing a top package precursor, which comprises a top substrate and a top electronic component, wherein:
the top substrate comprises a top substrate body having an upper side and a lower side, at least one first top metal structure on the upper side of the top substrate body, at least one second top metal structure on the lower side of the top substrate body, and at least one top signal via that extends from the upper side of the top substrate body through the top substrate body to the lower side of the top substrate body and is electrically coupled to the at least one first top metal structure; and
the top electronic component is mounted on the lower side of the top substrate body and electrically coupled to the at least one top signal via;
providing a perimeter wall, which comprises at least one signal via structure extending from an upper surface of the perimeter wall through the perimeter wall to a lower surface of the perimeter wall; and
assembling the bottom package precursor, the perimeter wall, and the top package precursor, wherein:
the perimeter wall extends from a periphery of the lower side of the top substrate body to a periphery of the upper side of the bottom substrate body such that a cavity is defined by a portion of the upper side of the bottom substrate body, an inside surface of the perimeter wall, and a portion of the lower side of the top substrate body;
the bottom electronic component and the top electronic component are exposed to the cavity; and
the at least one signal via structure is electrically coupled to the at least one first bottom metal structure and the at least one second top metal structure.

US Pat. No. 10,217,683

MOUNTED SEMICONDUCTOR MODULE WITH A MOLD RESIN PORTION

Mitsubishi Electric Corpo...

1. A semiconductor module comprising:a semiconductor element that is mounted;
a mold resin portion, wherein the mold resin portion comprises:
a plurality of sides;
a plurality of corner portions; and
a holding side portion provided at each of at least two diagonally opposing corner portions, from among the plurality of corner portions; and
a plurality of outside connecting modules drawn from a first side of the mold resin portion;
wherein a surface of at least one of the holding side portions is oblique relative to the first side of the mold resin portion.

US Pat. No. 10,217,682

TIME TEMPERATURE MONITORING SYSTEM

International Business Ma...

1. A time temperature monitoring system, comprising:a substrate having an active region;
a dopant source located proximate the active region;
an activation system for activating a diffusion of the dopant source into the active region; and
a set of spatially distributed transistors embedded in the active region of the substrate, wherein the transistors are configured to detect the diffusion correlated to time and temperature in the active region at varying distances from the dopant source to provide time temperature information.

US Pat. No. 10,217,677

REMOVABLE SACRIFICIAL CONNECTIONS FOR SEMICONDUCTOR DEVICES

Qorvo US, Inc., Greensbo...

1. A semiconductor device comprising:a semiconductor layer comprising:
a circuit layout on the semiconductor layer comprising:
a plurality of bump pads comprising a plurality of ground bump pads and a plurality of signal bump pads;
at least one ground probe pad connected to at least one of the plurality of ground bump pads; and
at least one signal probe pad connected to at least one of the plurality of signal bump pads;
a saw street on the periphery of the circuit layout; and
one or more sacrificial connections connecting at least two of the plurality of bump pads in the circuit layout.

US Pat. No. 10,217,674

THREE-DIMENSIONAL MONOLITHIC VERTICAL FIELD EFFECT TRANSISTOR LOGIC GATES

INTERNATIONAL BUSINESS MA...

1. A logic device, comprising:a first vertical transport field effect transistor formed over and adjacent a substrate;
a first bonding film deposited over the first vertical transport field effect transistor;
a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor, wherein the second bonding film affixes the second vertical transport field effect transistor to the first vertical transport field effect transistor; and
one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.

US Pat. No. 10,217,673

INTEGRATED CIRCUIT DIE HAVING REDUCED DEFECT GROUP III-NITRIDE STRUCTURES AND METHODS ASSOCIATED THEREWITH

Intel Corporation, Santa...

1. An integrated circuit (IC) die comprising:a semiconductor substrate;
a buffer layer disposed over the semiconductor substrate, the buffer layer having a plurality of openings formed therein; and
a plurality of group III-Nitride structures, wherein individual group III-Nitride structures of the plurality of group III-Nitride structures include a lower portion disposed in a respective opening of the plurality of openings and an upper portion disposed over the respective opening, the upper portion including a base extending radially from sidewalls of the respective opening over a surface of the buffer layer to form a perimeter around the respective opening; and
wherein a shape of an upper portion of at least one group III-Nitride structure of the plurality of group III-Nitride structures is one of a substantially pyramidal structure or a substantially frustum pyramidal structure or a substantially cuboidal structure and wherein glide planes for defects in the at least one group III-Nitride structure extend vertically in the respective opening and terminate at respective faces of the at least one group III-Nitride structure, wherein regions of the cuboidal structure disposed above the buffer layer have a reduced defect density in comparison to group III-Nitride material disposed above the opening.

US Pat. No. 10,217,670

WRAP-AROUND CONTACT INTEGRATION SCHEME

Tokyo Electron Limited, ...

1. A substrate processing method, comprising:providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film;
depositing a metal-containing film on the second dielectric film;
forming a patterned metal-containing film by etching mask openings in the metal-containing film; and
anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, wherein the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

US Pat. No. 10,217,666

STACKED STRUCTURE HAVING A PROTECTIVE LAYER BETWEEN AN INSULATION LAYER AND WIRING

SONY SEMICONDUCTOR SOLUTI...

1. A stacked structure, comprising:a wiring;
a first insulating layer;
a substrate;
an element in the substrate;
a protective layer; and
a connection section in the first insulating layer and the protective layer,
wherein the connection section connects the element to the wiring,
wherein the first insulating layer is stacked on the substrate, the protective layer is stacked on the first insulating layer, and the wiring is stacked on the protective layer,
wherein an end portion of the wiring projects from a side face of the stacked structure,
wherein the protective layer comprises a Silicon Nitride (SiN) based material, and
wherein the protective layer has a first etching rate for an etching condition different from a second etching rate of a material of the first insulating layer.

US Pat. No. 10,217,664

REFLOW INTERCONNECT USING RU

INTERNATIONAL BUSINESS MA...

1. A method for forming conductive structures for a semiconductor device, comprising:forming a repeating sequence of reflow materials on reflow liners that is present on walls of an opening formed in a dielectric layer, the reflow liner comprised of a material having a higher melting temperature than the reflow material; and
reflowing the reflow material to collect in a lower portion of the openings prior to reflowing the reflow liners to fill the opening.

US Pat. No. 10,217,663

APPARATUS FOR UNIFORM METAL DEPOSITION

SEMICONDUCTOR MANUFACTURI...

1. An apparatus for manufacturing a semiconductor device, comprising:a deposition chamber comprising a first station, a second station, and one or more third stations;
a delivery system configured to provide a substrate to the deposition chamber for processing;
a processing system configured to process the substrate;
a controller configured to control the delivery system and the processing system; and
an etch chamber,
wherein:
the delivery system provides the substrate to the first station, where the processing system performs a nucleation process on the substrate to form a metal nucleation layer under the control of the controller;
the substrate including the metal nucleation layer is provided by the delivery system to the second station, where the processing system performs a first deposition process at a first temperature to form a first metal layer;
the delivery system provides the substrate including the first metal layer to the etch chamber, where an etch-back process is performed using a first gas on the first metal layer;
the delivery system returns the substrate with the etched-back first metal layer back to the first station, wherein the processing system performs a cleaning process on the substrate using a second gas;
the delivery system provides the cleaned substrate to the second station or the one or more third stations, where a second deposition is performed to form a second metal layer on the etched-back first metal layer.

US Pat. No. 10,217,661

ARTICLES INCLUDING ULTRA LOW DIELECTRIC LAYERS

International Business Ma...

1. An article comprising:a structure comprising a patterned metal on a surface of a substrate, the patterned metal comprising metal features separated by gaps of an average gap dimension of less than about 100 nm; and
a porous low dielectric constant material having a dielectric value of less than about 2.7 substantially occupying all gaps, wherein an interfacial region between the metal features and the porous low dielectric constant material comprises less than about 0.1% by volume of voids.

US Pat. No. 10,217,660

TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A LATE MANUFACTURING STAGE

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:bordering a semiconductor region of a semiconductor device along a length direction, wherein bordering said semiconductor region comprises forming an isolation structure in a semiconductor substrate and laterally adjacent to a lateral bounding surface of said semiconductor region;
forming at least a portion of each of a plurality of gate electrode structures above said semiconductor region, said at least said portion of each of said plurality of gate electrode structures having a length dimension extending along said length direction and a width dimension extending along a width direction, the width direction being transverse to the length direction; and
after forming said plurality of gate electrode structures, bordering said semiconductor region along said width direction.

US Pat. No. 10,217,659

DUAL ISOLATION FIN AND METHOD OF MAKING

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure comprising:a substrate;
a fin of a second epitaxially formed material provided on a dielectric layer provided on the substrate, a first isolation region on the dielectric layer and adjacent a fin sidewall, and a second isolation region adjacent another fin sidewall including a bottom portion in contact with the substrate by:
applying a mask to portions of the substrate and etching exposed areas of the substrate to form a mandrel;
forming the dielectric layer disposed on a surface of the substrate and adjacent to the mandrel;
forming a first epitaxially formed material on an exposed portion of the mandrel;
forming the second epitaxially formed material on the first epitaxially formed material;
forming a first isolation layer on top of the dielectric layer and adjacent to the second epitaxially formed material;
removing the mask and mandrel after forming the first isolation layer to form an open area of the substrate;
removing the first epitaxially formed material after removing the mask and mandrel; and
forming a second isolation layer in the open area of the substrate such that the second isolation layer is formed on a sidewall and directly on a portion of a top surface of the dielectric layer;
wherein:
the first isolation layer has a thickness equal to a height of the second epitaxially formed material; and
wherein the second epitaxially formed material has fewer defects relative to forming the second epitaxially formed material without the first epitaxially formed material.

US Pat. No. 10,217,658

METHOD AND STRUCTURE FOR MINIMIZING FIN REVEAL VARIATION IN FINFET TRANSISTOR

International Business Ma...

1. A semiconductor device, comprising:a plurality of fins spaced apart from each other on a substrate, wherein a gate structure is around each of the fins;
a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and
a plurality of isolation regions on a top surface of the liner layer on the substrate and adjacent and between the plurality of fins;
wherein the plurality of isolation regions comprise:
a dielectric layer; and
a doped region on the dielectric layer.

US Pat. No. 10,217,657

ACTIVE SUBSTRATE ALIGNMENT SYSTEM AND METHOD

Varian Semiconductor Equi...

1. An active substrate alignment system for an ion implanter comprising:a platen;
a registration device adapted to selectively move a substrate engagement surface disposed adjacent the platen for limiting movement of a substrate disposed on the platen;
a camera configured to capture an image of the substrate before the substrate is disposed on the platen; and
a controller in communication with the camera and the registration device, the controller configured to command the registration device to move the substrate engagement surface based on the image to limit movement of the substrate in a predetermined manner.

US Pat. No. 10,217,656

PURGE APPARATUS AND PURGE METHOD

MURATA MACHINERY, LTD., ...

1. A purge apparatus for purging by purge gas a container that houses an article and includes a gas introduction hole in a bottom portion thereof, the purge apparatus comprising:a platform on which the container is placed;
a nozzle that protrudes upward from the platform and contacts the gas introduction hole of the container to inject purge gas; and
an alignment member that aligns the container; wherein
a side surface of a tip portion of the nozzle includes a guide surface that guides the container; and
an upper surface of the nozzle is supported by an elastic member such that the upper surface of the nozzle is lowered in response to a load applied from the container.

US Pat. No. 10,217,652

HEAT TREATMENT APPARATUS, HEAT TREATMENT METHOD, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A heat treatment apparatus for performing a heat treatment on a coating film formed on a substrate, the apparatus comprising:a placing table provided within a processing container, and configured to place the substrate thereon;
a heater configured to heat the substrate placed on the placing table;
a top plate having a bottom surface which faces an upper surface of the placing table across a gap in the processing container, the top plate including:
a plurality of outer circumferential exhaust ports opened circumferentially along and radially within an edge portion of the bottom surface of the top plate, and configured to exhaust an inside of the processing container; and
a central exhaust port opened in a central portion at the bottom surface of the top plate such that a center of the central exhaust port coincides with a center of the substrate placed on the placing table, and configured to exhaust the inside of the processing container; and
a cylindrical shutter provided to surround the placing table and configured to block an entire circumference of the gap formed between the placing table and the top plate to form a processing space in the processing container, the cylindrical shutter including a gas supply port formed at equal intervals over an entire circumference of an inner circumferential surface of the cylindrical shutter and configured to supply gas into the processing space of the processing container, wherein the gas supply port is opened at a position lower than the substrate.

US Pat. No. 10,217,648

FABRICATION OF MICROFLUIDIC CHANNELS IN DIAMOND

HRL Laboratories, LLC, M...

1. A method of forming a diamond microchannel structure, the method comprising:patterning a base layer of sacrificial material on a substrate to define a location and dimensions of a microchannel;
depositing a layer of diamond using chemical vapor deposition (CVD) to cover the patterned base layer; and
selectively removing the patterned sacrificial material from underneath the CVD deposited diamond layer to form a CVD diamond microchannel on the substrate.

US Pat. No. 10,217,646

TRANSITION METAL DRY ETCH BY ATOMIC LAYER REMOVAL OF OXIDE LAYERS FOR DEVICE FABRICATION

Intel Corporation, Santa...

1. A method of etching a film, the method comprising:reacting a surface layer of a transition metal species of a transition metal-containing film with a molecular oxidant species, wherein reacting the surface layer of the transition metal species of the transition metal-containing film with the molecular oxidant species comprises transferring oxygen from molecules having a reactive nitrogen based organic skeleton;
removing volatile fragments of the reacted molecular oxidant species to provide an oxidized surface layer of the transition metal species;
reacting the oxidized surface layer of the transition metal species with a molecular etchant; and
removing the reacted oxidized surface layer of the transition metal species and the reacted molecular etchant by volatlilization.

US Pat. No. 10,217,644

PRODUCTION OF ADHESION STRUCTURES IN DIELECTRIC LAYERS USING PHOTOPROCESS TECHNOLOGY AND DEVICES INCORPORATING ADHESION STRUCTURES

INFINEON TECHNOLOGIES AG,...

1. A semiconductor device structure, comprising:at least one semiconductor device comprising a semiconductor substrate;
a first dielectric layer having a top surface and a bottom surface,
wherein the bottom surface adjoins the semiconductor substrate;
geometric structures formed in the first dielectric layer,
wherein each of the geometric structures defines a respective blind hole in the first dielectric layer extending from the top surface to a respective intermediate surface of the first dielectric layer that is between the top surface and the bottom surface, and
at least one of the geometric structures has an undercut profile in the first dielectric layer, such that a cross-sectional gap width of the first dielectric layer increases, at least in part, from the top surface towards the respective intermediate surface; and
a conductive layer on the first dielectric layer,
wherein the conductive layer is at least located over the geometric structures and completely fills the geometric structures.

US Pat. No. 10,217,643

METHOD OF PROCESSING TARGET OBJECT

TOKYO ELECTRON LIMITED, ...

1. A method of processing a target object, the method comprising:preparing the target object including a first protrusion portion, a second protrusion portion, an etching target layer and a groove portion, the etching target layer having a region belonging to the first protrusion portion and a region belonging to the second protrusion portion, the groove portion being provided on a main surface of the target object, being provided on the etching target layer and being defined by the first protrusion portion and the second protrusion portion, and an inner surface of the groove portion being included in the main surface of the target object, and
performing a first sequence repeatedly N times (N is an integer equal to or larger than 2),
wherein the first sequence comprises:
forming a protection film conformally on the main surface of the target object in a processing vessel of a plasma processing apparatus in which the target object is accommodated; and
etching a bottom portion of the groove portion of the target object with plasma of a gas generated within the processing vessel after the forming of the protection film conformally is performed,
wherein a mask is formed on the region belonging to the first protrusion portion while the mask is not formed on the region belonging to the second protrusion portion, and
a deposition film is formed on the mask.

US Pat. No. 10,217,642

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND SUBSTRATE HOLDING MEMBER

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus comprising:a process chamber;
a turntable provided in the process chamber and including a substrate holding region formed in a top surface along a circumferential direction of the turntable, the substrate holding region having a first depth;
a surface area increasing region provided in the top surface of the turntable around the substrate holding region and configured to increase a surface area of the top surface of the turntable to an area larger than a surface area of a flat surface by including a concavo-convex pattern in its top surface, the concavo-convex pattern having a second depth that is shallower than the first depth of the substrate holding region; and
a process gas supply unit configured to supply a process gas to the top surface of the turntable.

US Pat. No. 10,217,641

CONTROL OF CURRENT COLLAPSE IN THIN PATTERNED GAN

International Business Ma...

1. A semiconductor device comprising:a substrate having a recessed region disposed in a surface thereof, the recessed region includes a first vertical sidewall of the substrate, a second vertical sidewall of the substrate, and a horizontal surface of a semiconductor material of the substrate;
a seed layer disposed within the recessed region and directly on the horizontal surface of the semiconductor material, wherein the seed layer extends continuously from the first vertical sidewall to the second vertical sidewall of the recess region; and
a layered structure disposed on the seed layer, the layered structure comprising a buffer layer and a gallium nitride layer, wherein the buffer layer is present directly on a topmost surface of the seed layer and extends continuously from the first vertical sidewall to the second vertical sidewall, and wherein the seed layer and the layered structure have outermost vertical sidewalls that are vertically aligned to each other, wherein the first and second vertical sidewalls include a sidewall of a dielectric material and a sidewall of a topmost semiconductor layer, the sidewall of the dielectric material is between the sidewall of the topmost semiconductor layer and the horizontal surface of the semiconductor material of the substrate.

US Pat. No. 10,217,639

METHOD OF FORMING DRAIN EXTENDED MOS TRANSISTORS FOR HIGH VOLTAGE CIRCUITS

Cypress Semiconductor Cor...

1. A method comprising:implanting a first type of ions at a first energy level in a first drain portion of a first drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of a substrate;
implanting the first type of ions at the first energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate, the LV_MOS region being located where a first LV_MOS transistor is to be formed, the implanting of the first type of ions in the LV_MOS region adjusting a voltage threshold of the first LV_MOS transistor, and the implanting of the first type of ions the first drain portion being concurrent with the implanting of the first type of ions in the LV_MOS region, wherein the first DE_MOS transistor and the first LV_MOS transistor are of an opposite type of transistors;
implanting the first type of ions at a second energy level in the first drain portion of the first DE_MOS transistor; and
subsequent to implanting the first type of ions at the second energy level in the first drain portion of the first DE_MOS transistor, forming a gate oxide of the first DE_MOS transistor.

US Pat. No. 10,217,638

METHOD FOR REMOVING CRYSTAL ORIGINATED PARTICLES FROM A CRYSTALLINE SILICON BODY USING AN ETCH PROCESS

Infineon Technologies AG,...

1. A method for removing crystal originated particles from a crystalline silicon body having opposite first and second surfaces, the method comprising:increasing a surface area of at least one of the first and second surfaces by an etch process, the etch process comprising etching a plurality of trenches into the crystalline silicon body;
oxidizing the increased surface area at a temperature of at least 1000° C. and for a duration of at least 20 minutes; and
forming at least one of: an electrically conductive electrode and semiconductor material in the plurality of trenches after the oxidizing.

US Pat. No. 10,217,637

CHIP HANDLING AND ELECTRONIC COMPONENT INTEGRATION

International Business Ma...

1. An assembly for integrating electronic elements into an electronic package assembly, comprising:a semiconductor structure including:
a device wafer comprising an array of singulated electronic elements, the singulated electronic elements including a plurality of targeted electronic elements,
a handle wafer bonded to the device wafer,
one or more first alignment markers, the targeted electronic elements being located at selected distances from the one or more first alignment markers, and
a release layer between the device wafer and the handle wafer;
a carrier assembly including one or more second alignment markers and selected surface areas configured for attaching the targeted electronic elements, the selected surface areas being configured for alignment with the targeted electronic elements when the one or more first alignment markers are aligned with the one or more second alignment markers;
an electromagnetic radiation source configured to direct electromagnetic radiation through the handle wafer, at least one of the electromagnetic radiation source and the handle wafer being configured to allow ablation of discrete, selected portions of the release layer beneath and corresponding to the targeted plurality of the singulated electronic elements using the electromagnetic radiation source;
an electronic package assembly include one or more third alignment markers and a plurality of targeted bonding sites, the selected surface areas of the carrier assembly being configured for alignment with the targeted bonding sites when the one or more second alignment markers are aligned with the one or more third alignment markers.

US Pat. No. 10,217,636

METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE BY REMOVING AMORPHIZED PORTIONS

Infineon Technologies AG,...

1. A semiconductor device comprising:a trench gate structure extending from a first surface into a semiconductor body,
wherein the trench gate structure fills a trench,
wherein the trench being rounded and/or chamfered along a rim section of the first surface, and
wherein, in a horizontal cross-section parallel to the first surface, the trench gate structure includes a long side, a short side and a rounded transition between the short side and the long side.

US Pat. No. 10,217,634

FIN PATTERNS WITH VARYING SPACING WITHOUT FIN CUT

International Business Ma...

1. A method of forming semiconductor fins, comprising:forming first spacers on a first sidewall of each of a plurality of mandrels using a first directional deposition;
masking a finless region by forming a first mask on a second sidewall of one or more of the plurality of mandrels;
forming second spacers on a second sidewall of unmasked mandrels using a second directional deposition;
unmasking the finless region;
etching away each of the plurality of mandrels; and
forming said semiconductor fins from a substrate using the first and second spacers as a second mask, such that no fins are formed in the finless region.

US Pat. No. 10,217,633

SUBSTANTIALLY DEFECT-FREE POLYSILICON GATE ARRAYS

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a semiconductor structure, comprising:forming a polysilicon layer over a semiconductor substrate;
forming an array of mandrels directly over the polysilicon layer, the array of mandrels including a pair of adjacent end mandrels each having a top surface, a bottom surface and sidewalls;
depositing a conformal layer of a spacer material over the array of mandrels and between any two mandrels of the array;
depositing a dielectric layer over the conformal layer and between any two mandrels of the array;
forming a masking layer directly over the dielectric layer, wherein the masking layer overlies each of the pair of adjacent end mandrels, is separated from the conformal layer by the dielectric layer, and (i) the masking layer extends continuously from over the pair of adjacent end mandrels to over the dielectric layer spaced laterally from the sidewalls of each of the pair of adjacent end mandrels within a first region of the semiconductor substrate, (ii) the masking layer does not overlie at least one end mandrel within a second region of the semiconductor substrate;
etching the dielectric layer within the first region of the semiconductor substrate using the masking layer as a mask to form a patterned layer of dielectric material extending laterally from sidewalls of the conformal layer disposed over the pair of adjacent end mandrels; and
etching the dielectric layer within the second region of the semiconductor substrate using the masking layer as a mask to form another patterned layer of dielectric material laterally offset from sidewalls of the conformal layer disposed over the at least one end mandrel.

US Pat. No. 10,217,632

INTEGRATION OF III-V COMPOUND MATERIALS ON SILICON

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, the method comprising:depositing a hard mask material on a silicon substrate;
patterning and removing portions of the hard mask material and the silicon substrate to form trenches and first fins comprising silicon, the first fins having a top surface and two sidewalls;
filling the trenches with a dielectric material;
recessing the dielectric material in the trenches to form dielectric layers at a bottom of the trenches;
depositing an AlAs interlayer directly on the sidewalls of the first fins and on the dielectric layers, the AlAs interlayer having a thickness of one to a few atoms, the AlAs interlayer being deposited via an atomic layer deposition process;
growing a III-V compound material on the AlAs interlayer, the III-V compound material comprising InP or InGaAs;
forming a second fin comprising the III-V compound material, wherein the second fin does not encase any of the first fins.

US Pat. No. 10,217,631

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A semiconductor package comprising:a first connection member having a through-hole, and including first redistribution layers and a first electromagnetic interference (EMI) blocking part;
a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip, and including a portion filling in a portion of the through-hole to separate side surfaces of the semiconductor chip from the first connection member; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip, and including a second redistribution layer and a second EMI blocking part,
wherein the first electromagnetic interference (EMI) blocking part surrounds the side surfaces of the semiconductor chip,
the first redistribution layers are disposed between the first EMI blocking part and the semiconductor chip,
the second EMI blocking part surrounds the second redistribution layer,
a signal pattern of the first redistribution layers is electrically connected to one of the connection pads through a signal pattern of the second redistribution layer, and
the first EMI blocking part and the second EMI blocking part are electrically connected to each other, and are electrically isolated from the signal patterns of the first and second redistribution layers.

US Pat. No. 10,217,630

METHOD OF FORMING SILICON-CONTAINING FILM

TOKYO ELECTRON LIMITED, ...

1. A method of forming a silicon-containing film, comprising:an adsorption step of supplying a silicon-containing gas represented by a general formula XSiCl3 (wherein X is an element whose bonding energy with Si is smaller than bonding energy of a Si—Cl bond) into a processing chamber accommodating substrates to cause the silicon-containing gas to be adsorbed to a surface of each of the substrates; and a reaction step of supplying a reaction gas reacting with the silicon-containing gas into the processing chamber to cause the silicon-containing gas adsorbed to the surface of each of the substrates to react with the reaction gas, wherein by alternately repeating the adsorption step and the reaction step, a reaction product of the silicon-containing gas and the reaction gas is deposited on the surface of each of the substrates to form the silicon-containing film.

US Pat. No. 10,217,629

METHOD OF FORMING DIELECTRIC FILMS, NEW PRECURSORS AND THEIR USE IN SEMICONDUCTOR MANUFACTURING

1. A method of depositing a Group IV metal containing thin film on a substrate, the method comprisingvaporizing a M1 containing precursor to form a gas phase M1 source, the M1 containing precursor having the formula:
(RtCp)zM1R?4-z wherein M1 is Hf or Zr; z is 1; t is an integer from 0 to 5; Cp is a cyclopentadienyl ligand; each R is independently a C1-C4 linear or branched alkyl or alkylsilylamide; and each R? is independently a C1-C4 linear or branched alkylamide; andintroducing the gas phase M1 source and a reactant species into a reaction chamber containing a substrate to deposit the Group IV metal containing thin film on the substrate.

US Pat. No. 10,217,628

SUBSTRATE PROCESSING APPARATUS AND PROCESSING METHOD OF SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus which performs a processing of removing a film on a peripheral portion of a substrate, the substrate processing apparatus comprising:a rotating/holding unit configured to hold and rotate the substrate;
a first processing liquid supply unit configured to supply a first processing liquid for removing the film onto the peripheral portion of the substrate while the substrate is being rotated in a first rotational direction by the rotating/holding unit;
a second processing liquid supply unit configured to supply a second processing liquid for removing the film onto the peripheral portion of the substrate while the substrate is being rotated in a second rotational direction opposite to the first rotational direction by the rotating/holding unit; and
an imaging unit configured to image the peripheral portion of the substrate,
wherein the imaging unit is provided at a position not overlapping with arrival regions of the first and second processing liquids when viewed from above and between the first processing liquid supply unit and the second processing liquid supply unit.

US Pat. No. 10,217,625

CONTINUOUS-WAVE LASER-SUSTAINED PLASMA ILLUMINATION SOURCE

KLA-Tencor Corporation, ...

1. An optical system for generating broadband light via light-sustained plasma formation, comprising:a chamber, the chamber configured to contain a buffer material in a first phase and a plasma-forming material in a second phase, wherein the second phase is at least one of a solid phase or a liquid phase;
an illumination source configured to generate continuous-wave pump illumination;
a set of focusing optics configured to focus the continuous-wave pump illumination through the buffer material to an interface between the buffer material and the plasma-forming material in order to generate a plasma by excitation of at least the plasma-forming material;
a set of collection optics configured to receive broadband radiation emanated from the plasma; and
a flow subsystem configured to direct a flow of the buffer material to the plasma, the flow subsystem including a nozzle directed at the plasma so that the flow of the buffer material intersects with an illumination path of the continuous-wave pump illumination at the interface between the buffer material and the plasma-forming material.

US Pat. No. 10,217,623

SECONDARY ELECTROSPRAY IONIZATION AT REDUCED PRESSURE

MICROMASS UK LIMITED, Wi...

12. A method of mass spectrometry or ion mobility spectrometry comprising:passing an analyte through a liquid or gas chromatography device and a heated capillary so as to provide a gas phase analyte;
drawing the gas phase analyte into a vacuum housing, entrained in a gas, by a pressure difference maintained between the inside and outside of the vacuum housing;
electrospraying a reagent solution outside of the vacuum housing in a region substantially at atmospheric pressure so as to form charged droplets of reagent solution;
conveying the electrosprayed charged droplets into the vacuum housing through an atmospheric pressure sampling orifice, wherein the electrosprayed charged droplets desolvate after entering the vacuum housing to form gas phase reagent ions;
reacting the reagent ions with the analyte in a region of the vacuum housing that is below atmospheric pressure so as to form analyte ions;
urging the analyte ions into a mass analyser and/or ion mobility analyser using a pressure gradient and/or electric field; and
analysing the analyte ions with the mass analyser and/or ion mobility analyser.

US Pat. No. 10,217,622

AMBIENT IONISATION WITH AN IMPACTOR SPRAY SOURCE

MICROMASS UK LIMITED, Wi...

1. An ion source comprising:a nebuliser arranged and adapted to emit a liquid spray;
a first target arranged downstream of said nebuliser, wherein said liquid spray is arranged to impact upon said first target;
wherein said ion source further comprises:
a sample target located at a distance of (i) 1-2 mm; (ii) 2-3 mm; (iii) 3-4 mm; (iv) 4-5 mm; (v) 5-6 mm; (vi) 6-7 mm; (vii) 7-8 mm; (viii) 8-9 mm; (ix) 9-10 mm; or (x) >10 mm from said first target, wherein a sample to be analysed is provided at said sample target.

US Pat. No. 10,217,617

PLASMA PROCESSING APPARATUS AND METHOD THEREFOR

PANASONIC INTELLECTUAL PR...

1. A plasma processing apparatus for plasma processing a substrate held by a carrier having a frame and a holding sheet, comprising:a chamber having a pressure reducible internal space;
a process gas supply section configured to supply a process gas into the internal space;
a pressure reducing section configured to reduce pressure of the internal space;
a plasma generating section configured to generate plasma in the internal space;
a stage in the chamber and including an electrode unit on which the carrier is positioned;
a substantially flat portion in a first area of the electrode unit, the first area being an area in which the substrate is positioned via the holding sheet;
a first non-flat portion in a second area of the electrode unit, the second area including at least an area in which the frame is positioned via the holding sheet and an area in which the holding sheet between the substrate and the frame is positioned, the first non-flat portion having at least one concave portion recessed in a direction away from the carrier; and
a first heat transfer gas supply section configured to supply a heat transfer gas to a first minute space defined between the first non-flat portion and the carrier via at least one heat transfer gas supply hole,
wherein the at least one heat transfer gas supply hole is in the second area of the electrode unit and no heat transfer gas hole is in the first area of the electrode unit, and
wherein the substantially flat portion has no concave portion recessed in the direction away from the carrier, and the substantially flat portion has no concave portion formed by any heat transfer gas supply hole.

US Pat. No. 10,217,616

METHOD OF CONTROLLING TEMPERATURE AND PLASMA PROCESSING APPARATUS

Tokyo Electron Limited, ...

15. A method of controlling a temperature, the method comprising steps of:performing a first plasma process in a processing chamber on an object to be processed placed on an electrostatic chuck configured to have its temperature adjustable, the electrostatic chuck being controlled to have a first temperature;
purging the processing chamber with an inactive gas by supplying the inert gas to a space above the object to be processed placed on the electrostatic chuck in the processing chamber after performing the first plasma process;
changing the temperature of the electrostatic chuck from the first temperature to a second temperature that is lower than the first temperature during a first predetermined period of time;
causing a temperature of the object to be processed to follow the temperature of the electrostatic chuck by maintaining the temperature of the electrostatic chuck at the second temperature for a second predetermined period of time;
changing the temperature of the electrostatic chuck from the second temperature to a third temperature that is lower than the second temperature during a third predetermined period of time;
stopping the supply of the inert gas to the space above the object to be processed in the processing chamber; and
performing a second plasma process in the processing chamber on the object to be processed placed on the electrostatic chuck while maintaining the temperature of the electrostatic chuck at the third temperature after stopping the supply of the inert gas to the space above the object to be processed in the processing chamber,
wherein at least part of any of the steps of changing the temperature of the electrostatic chuck from the first temperature to the second temperature, maintaining the temperature of the electrostatic chuck at the second temperature and changing the temperature of the electrostatic chuck from the second temperature to the third temperature is performed in parallel with the step of purging the processing chamber with the inactive gas, and
wherein the second period of time is longer than each of the first period of time and the third period of time.

US Pat. No. 10,217,615

PLASMA PROCESSING APPARATUS AND COMPONENT THEREOF INCLUDING AN OPTICAL FIBER FOR DETERMINING A TEMPERATURE THEREOF

LAM RESEARCH CORPORATION,...

1. A plasma processing apparatus for processing semiconductor substrates, comprising:a plasma processing chamber in which a semiconductor substrate is processed;
a process gas source in fluid communication with the plasma processing chamber adapted to supply a process gas into the plasma processing chamber;
a RF energy source adapted to energize the process gas into a plasma state in the plasma processing chamber;
a vacuum source adapted to exhaust process gas and byproducts of the plasma processing from the plasma processing chamber; and
a substrate support assembly comprising:
a dielectric layer including a clamping electrode;
a heater layer attached to the underside of the dielectric layer, the heater layer including a plurality of planar thermal zones; and
an optical fiber laterally extending in a channel embedded in the dielectric layer and arranged between the clamping electrode and the heater layer, the optical fiber including a plurality of gratings configured to measure temperatures of respective thermal zones,
wherein the optical fiber is configured to be coupled to a temperature monitoring arrangement to monitor temperatures of the plurality of planar thermal zones measured by the plurality of gratings;
wherein the temperature monitoring arrangement includes a light source and a detector, the light source to provide near infrared, infrared, natural, or ultraviolet light into the optical fiber and the detector to measure light exiting the optical fiber; and
wherein the temperature monitoring arrangement is configured to determine the temperatures of the plurality of planar thermal zones based on parameters of the light entering and exiting the optical fiber.

US Pat. No. 10,217,614

CERAMIC GAS DISTRIBUTION PLATE WITH EMBEDDED ELECTRODE

LAM RESEARCH CORPORATION,...

1. A method for manufacturing a gas distribution plate for a substrate processing system, comprising:(a) creating a ceramic lower portion of the gas distribution plate, wherein the ceramic lower portion includes a plurality of ceramic green sheets;
(b) creating a ceramic upper portion of the gas distribution plate, wherein the ceramic upper portion includes a plurality of ceramic green sheets;
(c) while the ceramic lower portion and the ceramic upper portion are in a green state, printing an electrode on at least one of an upper surface of the ceramic lower portion and a lower surface of the ceramic upper portion using metal screen printing process;
(d) while the ceramic lower portion and the ceramic upper portion are in the green state, sandwiching the electrode between the ceramic lower portion and the ceramic upper portion after (c);
(e) while the ceramic lower portion and the ceramic upper portion are in the green state, machining a first plurality of through holes through the ceramic lower portion, the ceramic upper portion, and the electrode after (d),
wherein the first plurality of through holes are configured to pass gas to a substrate side of the gas distribution plate;
(f) machining a second plurality of through holes through the ceramic lower portion, the ceramic upper portion, and the electrode,
wherein the second plurality of through holes is arranged radially outside of the first plurality of through holes,
wherein the second plurality of through holes is configured to exhaust gas from the substrate side of the gas distribution plate, and
wherein the through holes of the second plurality of through holes have a different shape than the through holes of the first plurality of through holes; and
(g) sintering the ceramic upper portion and the ceramic lower portion to form the gas distribution plate after (e).

US Pat. No. 10,217,613

PLASMA PROCESSING APPARATUS

Hitachi High-Technologies...

1. A plasma processing apparatus, comprising:a processing chamber disposed inside a vacuum vessel and, in the processing chamber, a first gas is supplied and a first plasma for processing a wafer is generated using the first gas;
a stage disposed in the processing chamber and the wafer is mounted on an upper surface of the stage;
a ring-shaped member which is constituted of a dielectric material and is disposed on an outer peripheral portion of the stage and surroundinq the upper surface of the stage, the ring-shaped member defining a discharge space in which a second gas is supplied and a second plasma is generated using the second gas;
a vacuum evacuator which is coupled to the vacuum vessel and is configured to evacuate and decompress the inside of the processing chamber,
a first electrode which is disposed inside the stage and to which a first high frequency power source is electrically connected and a first high frequency power therefrom is supplied;
a second electrode and a third electrode which are disposed sandwiching the discharge space inside the ring-shaped member, where the second electrode is electrically connected to a second high frequency power source and supplied a second high frequency power therefrom, and the third electrode is connected to a ground potential;
wherein a surface of the ring-shaped member defines an opening which is in communication with the discharge space and the processing chamber and which is configured to supply particles of the second plasma into the processing chamber.

US Pat. No. 10,217,612

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD WITH A CARRIER WAVE GROUP GENERATING UNIT

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus, comprising:a processing vessel;
a carrier wave group generating unit configured to generate a carrier wave group including multiple carrier waves having different frequencies belonging to a preset frequency band centered around a predetermined center frequency; and
a plasma generating unit configured to generate plasma within the processing vessel by using the carrier wave group,
wherein a number of the multiple carrier waves belonging to the carrier wave group is 400 or more.

US Pat. No. 10,217,611

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

Hitachi High-Technologies...

1. A plasma processing apparatus that processes a wafer to be processed, which is placed on a surface of a sample stage arranged in a processing chamber inside a vacuum container, using a plasma formed in the processing chamber, the apparatus comprising:a dielectric film which constitutes an upper surface of the sample stage on which the wafer is placed;
a first electrode which is arranged inside the sample stage below the upper surface of the sample stage and to which a first high-frequency power is supplied during the processing;
a second electrode having a ring shape, and which is arranged on an upper portion of the sample stage surrounding an upper surface of the sample stage and an outer peripheral side thereof, and to which a second-high frequency power is supplied from a second-high frequency power supply via a matching device and a load impedance variable box, and a series resonant circuit is formed on a power supply path between the second electrode and the second-high frequency power supply, the series resonant circuit being configured to include a coil and a capacitance in series;
a ring-shaped dielectric cover which is constituted by a dielectric material and arranged surrounding the upper surface of the sample stage and covering the second electrode; and
a control unit configured to adjust the supply of the first and second high-frequency powers,
wherein the control device is configured to adjust the supply of the second high-frequency power by adjusting an inductance of the coil using a result of a first voltage detected in a first location between the coil and the second electrode on the power supply path, and
wherein the coil is part of the load impedance variable box, and the capacitance is between the wafer and the ring-shaped dielectric cover.

US Pat. No. 10,217,610

ARRANGEMENTS FOR MANIPULATING PLASMA CONFINEMENT WITHIN A PLASMA PROCESSING SYSTEM AND METHODS THEREOF

Lam Research Corporation,...

1. A method for controlling etch rate during plasma processing within a processing chamber of a plasma processing system, comprising:securing a substrate onto a lower electrode within said processing chamber;
providing a power source;
flowing a gas mixture into said processing chamber;
adjusting a first match arrangement, said first match arrangement is coupled to an upper electrode, wherein said first match arrangement is configured to control current flowing through said upper electrode to change said upper electrode from a grounded state to a floating state, thereby minimizing plasma formation between said upper electrode and said lower electrode;
adjusting a second match arrangement, the second match arrangement is coupled to a top ring electrode, wherein said second match arrangement is configured for at least controlling said current flowing through said top ring electrode to control a first plasma formed above a top edge of said substrate, wherein said first plasma is configured for at least etching a part of said top edge of said substrate; and
lowering an extension of said upper electrode during said plasma processing, said extension being a movable component of said upper electrode, wherein said extension of said upper electrode is lowered to minimize a gap between said extension of said upper electrode and said substrate, wherein said extension of said upper electrode is not touching said substrate and said gap is incapable of supporting a plasma.

US Pat. No. 10,217,606

CHARGED PARTICLE BEAM DRAWING METHOD AND CHARGED PARTICLE BEAM DRAWING APPARATUS

NuFlare Technology, Inc.,...

6. A charged particle beam drawing apparatus of irradiating a resist film on a substrate with a charged particle beam,the substrate including a light-shielding film pattern that is formed by developing the resist film to form a resist pattern, and by etching a light-shielding film lying under the resist film with the resist pattern used as a mask, the apparatus comprising:
a storage unit that stores data representing a relation between a resist area rate and a resist film reduction amount, drawing data, a second dimension correction map to correct a relatively macroscopic dimensional variation, data representing an initial film thickness of the resist film on the substrate, and data representing a correlation between a film thickness of the resist pattern and a dimension of the light-shielding film pattern;
an area rate calculation processing circuitry calculating an area rate of a pattern, which is to be drawn on the substrate, on the basis of the drawing data;
a film reduction amount distribution calculation processing circuitry calculating a resist film reduction amount distribution resulted with etching by employing both data representing the relation between the resist area rate and the resist film reduction amount and the calculated area rate;
a remaining film thickness distribution calculation processing circuitry calculating a remaining resist-film thickness distribution after the etching from both the initial film thickness and the calculated resist film reduction amount distribution;
a dimension correction map creating processing circuitry creating a first dimension correction map by estimating a dimension distribution of the light-shielding film pattern from both the data representing the correlation and the calculated remaining resist-film thickness distribution, and by determining a dimension correction amount of the light-shielding film pattern from both the estimated dimension distribution and a design dimension;
a map synthesis processing circuitry creating a third dimension correction map by synthesizing the first dimension correction map and the second dimension correction map;
an irradiation dose calculation processing circuitry calculating an irradiation dose of the charged particle beam by employing the third dimension correction map; and
a drawing section drawing the pattern by irradiating the resist film with the charged particle beam at the calculated irradiation dose.

US Pat. No. 10,217,605

METHOD AND APPARATUS FOR INSPECTION OF SCATTERED HOT SPOT AREAS ON A MANUFACTURED SUBSTRATE

KLA-Tencor Corporation, ...

1. An electron beam apparatus comprising:an electron source for generating a primary electron beam;
a lens system configured to focus the primary electron beam onto a surface of the substrate;
a detector configured to detect scattered electrons from the substrate in order to perform off-axis imaging of one or more hot spot areas;
a variable speed stage configured to hold the substrate and controllably move the substrate under the primary electron beam; and
one or more controllers including one or more processors configured to:
control movement of the variable speed stage along a swath path so as to move a field of view of the electron beam apparatus such that the moving field of view covers a target area on the substrate, wherein the speed of the variable speed stage is adjusted based on the number of hot spot areas within the moving field of view, wherein the swath path is independent of the location of the one or more hot spot areas.

US Pat. No. 10,217,604

CHARGED PARTICLE BEAM APPARATUS

HITACHI HIGH-TECHNOLOGIES...

1. A charged particle beam device comprising:a charged particle source that generates a charged particle beam;
a focus adjustment unit that adjusts a focal position of the charged particle beam;
a deflection unit configured to scan the charged particle beam on a sample;
a detection unit that detects charged particles generated when the sample is irradiated with the charged particle beam;
a detected charged particle selection unit that selects charged particles to be detected by the detection unit; and
a control processing unit comprising a filter control unit operably coupled to and which controls the detected charged particle selection unit,
wherein the control processing unit is configured to perform focus adjustment of the focus adjustment unit, and is configured to perform reference adjustment of the detected charged particle selection unit by calculating and outputting a reference voltage to the filter control unit, based on information received from the detection unit acquired from one scan.

US Pat. No. 10,217,602

CHARGED PARTICLE BEAM APPARATUS AND ABERRATION CORRECTOR

HITACHI HIGH-TECHNOLOGIES...

1. A charged particle beam apparatus, which is configured to irradiate a sample with a charged particle beam to detect a charged particle ascribable to the sample, the charged particle beam apparatus comprising an aberration correction unit,the aberration correction unit comprising:
a first magnetic quadrupole and a second magnetic quadrupole;
a third magnetic quadrupole and a fourth magnetic quadrupole that are provided between the first magnetic quadrupole and the second magnetic quadrupole; and
a first electrostatic quadrupole and a second electrostatic quadrupole that are provided between the first magnetic quadrupole and the second magnetic quadrupole, wherein
the first magnetic quadrupole, the second magnetic quadrupole, the third magnetic quadrupole and the fourth magnetic quadrupole and the first electrostatic quadrupole and a second electrostatic quadrupole are arranged symmetrically with respect to a center symmetry plane, and are respectively excited antisymmetrically;
the second magnetic quadrupole is provided in a first plane that is different from a second plane in which the first electrostatic quadrupole is provided;
the third magnetic quadrupole is provided in a third plane that is different from a fourth plane in which the second electrostatic quadrupole is provided;
the aberration correction unit is arranged on one of a path for irradiating the sample with the charged particle beam and a path for detecting the charged particle ascribable to the sample;
the charged particle beam apparatus further comprises a vacuum path unit configured to decompress a path of the charged particle beam passing through the aberration correction unit;
the first electrostatic quadrupole and the second electrostatic quadrupole are arranged within a decompressed space inside the vacuum path unit, wherein a support is arranged between the first and second electrostatic quadrupoles, along an interior of a liner tube disposed within the decompressed space, and is constructed to provide alignment accuracy of said first and second electrostatic quadrupoles;
the first magnetic quadrupole, the second magnetic quadrupole, the third magnetic quadrupole and the fourth magnetic quadrupole each comprising the excitation unit are arranged outside the vacuum path unit; and
the aberration correction unit is configured to adjust an amount of chromatic aberration correction by adjusting an amount of overlap between one of said magnetic quadrupoles and a corresponding one of said electrostatic quadrupoles.

US Pat. No. 10,217,601

ION SOURCE

VARIAN SEMICONDUCTOR EQUI...

1. An ion source, comprising:an ion source chamber having an elongate shape defined by a height, a width, and a length greater than the height and the width, and a longitudinal axis extending along the length of the elongate shape, the ion source chamber operative to define a plasma therein; and
a split solenoid assembly comprising a first solenoid and a second solenoid that are mutually disposed along opposite sides of the ion source chamber, each of the first solenoid and second solenoid comprising:
a metal member having a long axis parallel to the longitudinal axis of the ion source chamber; and
a main coil having an elongate shape defined by a main coil height, a main coil width, and a main coil length greater than the main coil height and main coil width, the main coil having a coil axis extending along the main coil length parallel to the long axis and the longitudinal axis, the main coil comprising a plurality of windings that circumscribe the metal member, the main coil defining a coil footprint that is larger than an ion source chamber footprint the ion source chamber, wherein the main coil length is at least two times greater than the ion source chamber length and the main coil width is at least two times greater than the ion source chamber width.

US Pat. No. 10,217,598

X-RAY GENERATOR

ADAPTIX LIMITED, Oxfords...

1. A method of generating x-rays comprising the steps of:emitting a plurality of electron beams from a plurality of electron beam emitters arranged in an array;
energizing a subset of a plurality of solenoid coils arranged in an array and disposed adjacent to the plurality of electron beam emitters, wherein each of the energized solenoid coils generates a magnetic field;
deflecting a subset of the plurality of electron beams to strike at least one target, thereby generating x-ray photons;
detecting the x-ray photons at a detector after the x-ray photons pass through a region of interest; and
generating an image of at least a portion of the region of interest using information provided by the detector.

US Pat. No. 10,217,596

HIGH TEMPERATURE ANNEALING IN X-RAY SOURCE FABRICATION

General Electric Company,...

1. An X-ray source, comprising:an emitter configured to emit an electron beam; and
a target configured to generate X-rays when impacted by the electron beam, the target comprising:
at least one X-ray generating layer comprising X-ray generating material, wherein planar density hydrogen held within some or all of the X-ray generating layers is less than 5×1016/cm2; and
at least one thermally-conductive layer in thermal communication with each X-ray generating layer, wherein each thermally conductive layer or substrate comprises grain boundaries in which hydrogen is held, and wherein the planar density hydrogen held within some or all of the thermally conductive layers is less than 5×1016/cm2.

US Pat. No. 10,217,594

BRIDGE ASSEMBLY

MANDO CORPORATION, Pyeon...

1. A bridge assembly, comprising:a bridge including
a first leg fixed to a first surface of a printed circuit board,
a second leg fixed to the first surface of printed circuit board to be spaced apart from the first leg, and
an elastic part connecting between the first leg and the second leg and applying an elastic force to any one of the first and second legs; and
a cover positioned at an upper side of the bridge to receive the elastic part, including
an upper part positioned over the elastic part,
a first extending part extending from a first side of the upper part to be toward a first surface of the first leg, and
a second extending part extending from a second side of the upper part to be toward a first surface of the second leg,
wherein a second surface of the first leg and a second surface of the second leg that are positioned opposite to the first surface of the first leg and the first surface of the second leg, respectively, are fixed to the first surface of the printed circuit board, and
wherein at least one of the first and second extending parts is positioned to be spaced apart from the corresponding first surface of the first leg or the corresponding first surface of the second leg.

US Pat. No. 10,217,593

FUSE BOX FOR MOTOR VEHICLE

RENAULT s.a.s., Boulogne...

1. A fuse box for an automotive vehicle, comprising:a receptacle having a bottom and an opening leading to said bottom; and
a pair of fuses fitted into said bottom and intended to protect an electrical device, each of the fuses of said pair having a first end and a second end;
a pair of output terminals coupled to the first ends, respectively, of said fuses and a pair of input terminals coupled to the second ends, respectively, of said fuses, said pair of output terminals extending from said receptacle in a first direction, while said pair of input terminals extends from said receptacle in a second direction;
at least one other pair of fuses fitted into said bottom and intended to protect another electrical device that is connected in parallel with said first device, each of the fuses of said at least one other pair having another first end and another second end, and another pair of input terminals coupled to the other second ends, respectively, said other pair of input terminals extending substantially in parallel to said second direction, and the other first ends of said at least one other pair of fuses are coupled to said pair of output terminals, respectively; and
a pair of input conductors to couple said pair of input terminals to said second ends, respectively, of said fuses, said pair of input conductors having two superposed first portions defining two parallel distal planes, respectively,
wherein the pair of input terminals is positioned below the pair of fuses and the at least one other pair of fuses, and the other pair of input terminals is positioned below the pair of input terminals.

US Pat. No. 10,217,592

CIRCUIT BREAKER AND METHOD FOR OPERATION THEREOF

1. A circuit breaker comprising:an input terminal;
a load terminal;
a switching device arranged in a current path between the input terminal and the load terminal, the switching device having a thermal and/or magnetic tripping device for an interruption of a current circuit, which comprises the current path, in an event of an overcurrent or a short-circuit,
wherein a functional component of the switching device is connected in the current path and is bridged via a bypass, which carries a current detected via a current sensor when the current is below a current threshold and is shut off when the current threshold is exceeded, and
wherein the current and/or voltage supply of the switching device and/or of the control circuit is provided via a function component based on a principle of energy harvesting.

US Pat. No. 10,217,591

CIRCUIT BREAKER TOGGLE LINK APPARATUS, TOGGLE LINK ASSEMBLIES, CIRCUIT BREAKER TRIP MECHANISM ASSEMBLIES, AND METHODS OF LIMITING CRADLE MOTION OF A CIRCUIT BREAKER

1. A toggle link apparatus of a circuit breaker, comprising:a link body having a pivot end and an engagement end opposite the pivot end, the engagement end including:
an open-ended slot including a pivot feature and a stop feature configured to interface with a toggle pin, wherein the open-ended slot comprises:
a first slot region extending from the pivot feature to the stop feature of the open-ended slot, and
a second slot region extending from the stop feature to an open end of the open-ended slot,
wherein a center of the open end is positioned at a lateral offset distance O from a line of action LOA passing between the pivot feature to the stop feature.

US Pat. No. 10,217,589

HIGH-SPEED CIRCUIT BREAKING ARRAY FOR BREAKING A CURRENT PATH IN A SWITCHING DEVICE

EATON INTELLIGENT POWER L...

1. A high-speed circuit breaker arrangement for interrupting a current path in a switching device in the event of short-circuiting or overload, the arrangement comprising:a drive configured to move a drive armature from a standby position into a tripping position, the movement of the drive armature being configured to act on at least one moving contact of the switching device such that a current path is interrupted;
a holding apparatus configured to hold the drive armature the tripping position,
wherein the holding apparatus includes a holding armature, rigidly coupled to the drive armature, and a magnet arrangement,
wherein the holding armature is held in a holding position by a magnetic force of the magnet arrangement as soon as the drive armature reaches the tripping position, and
wherein the high-speed circuit breaker arrangement is configured solely for interrupting the current path in the switching device in the event of short-circuiting or overload, and is independent of a drive configured to switch the switching device during operation.

US Pat. No. 10,217,588

ENCLOSED TYPE ELECTROMAGNETIC SWITCH HAVING STATUS INDICATION FUNCTION

LSIS CO., LTD., Anyang-s...

1. An enclosed type electromagnetic switch having a status indication function, the enclosed type electromagnetic switch comprising:an enclosure having an enclosed structure; and
an electromagnetic switch, wherein the enclosure, which is separate from and independent of the electromagnetic switch, encloses the entire electromagnetic switch to protect the electromagnetic switch from moisture, dust, or impurities,
wherein the electromagnetic switch comprises:
an electromagnetic contactor installed inside the enclosure;
an auxiliary contact unit attached to one side of the electromagnetic contactor; and
an overload relay installed inside the enclosure and providing a trip signal to the electromagnetic contactor,
wherein the enclosure comprises:
a first indicating means that is installed on the enclosure and connected to contacts a (NO contacts) of the auxiliary contact unit to show that the electromagnetic contactor is in the on state; and
a second indicating means that is installed on the enclosure and connected to contacts b (NC contacts) of the auxiliary contact unit to show that the electromagnetic contactor is in the off state, and
wherein the first indicating means and the second indicating means operate in a mutually exclusive manner to each other,
wherein the first and second indicating means include first and second conductor parts connected to the contacts a and the contacts b, respectively, and first and second indicating parts installed in a way that are exposed on the enclosure, and
wherein mounting holes are formed in part of the enclosure to mount the first and second indicating means.

US Pat. No. 10,217,586

ELECTROMAGNETIC ACTUATOR

SIEMENS AKTIENGESELLSCHAF...

1. A method for driving an electromagnetic actuator including an exciter winding for generating a magnetic field and a movable armature, the method comprising:generating a magnetic flux in the exciter winding in order to move the armature from a starting position into an end position;
and
measuring the magnetic flux through the exciter winding, or a flux variable which correlates with the magnetic flux through the exciter winding, by forming an actual value, wherein, to move the armature from the starting position into the end position, the magnetic flux is regulated by the exciter winding, and wherein a profile of the actual value corresponds to a setpoint flux curve, the setpoint flux curve including a rise ramp section in which the setpoint flux curve rises from zero to a ramp end value.

US Pat. No. 10,217,583

PRESSURE RESPONSIVE SWITCH FOR ACTUATING A DEVICE

Halliburton Energy Servic...

1. In an apparatus exposed to a first pressure and a second pressure, a switch responsive to a pressure differential, wherein the pressure differential is equal to the first pressure minus the second pressure, the switch comprising:(a) a pressure response mechanism for providing a pressure response in response to the pressure differential, wherein the pressure response mechanism comprises:
(i) a switch cylinder having a first switch cylinder end and a second switch cylinder end;
(ii) a switch piston contained within the switch cylinder such that the switch piston and the switch cylinder are reciprocable relative to each other, wherein the switch piston divides the switch cylinder into a first switch chamber adjacent to the first switch cylinder end and a second switch chamber adjacent to the second switch cylinder end;
(iii) wherein the first switch chamber is in pressure communication with the first pressure; and
(iv) wherein the second switch chamber is in pressure communication with the second pressure;
(b) a device actuator arranged to interact with the pressure response mechanism and to utilize the pressure response of the pressure response mechanism to actuate a device, wherein the device actuator actuates the device to an operative state when the pressure differential is below a lower pressure differential threshold;
(c) a first fluid isolation system for isolating the first switch chamber from a first fluid; and
(d) a second fluid isolation system for isolating the second switch chamber from a second fluid.

US Pat. No. 10,217,582

FORCE SWITCH

Ethicon Endo-Surgery, Inc...

1. A method of creating a switch to be disposed along a longitudinal axis of a device, comprising:providing a hollow body defining an interior cavity;
disposing a switching element movably within the interior cavity to define:
a first position along a switching axis of the switching element; and
a second position along the switching axis of the switching element, the second position being different from the first position;
disposing a biasing element about the switching element to impart a longitudinal biasing force to the switching element to place the switching element in one of the first position and the second position until an external force imparted to the switching element exceeds the biasing force to thereby cause the switching element to move to the other one of the first position and the second position;
disposing a biasing force-adjusting element in cooperative engagement with the biasing element such that a magnitude of the biasing force is adjustable using the biasing force-adjusting element; and
coupling an electrically-conductive contact to the switching element to define:
a first switching state when the switching element is in the first position; and
a second switching state when the switching element is in the second position.

US Pat. No. 10,217,579

OPERATING MECHANISM FOR A TOGGLE SWITCH HANDLE

EATON INTELLIGENT POWER L...

1. An operating mechanism for a toggle switch handle comprising:a bar movably mounted along its longitudinal axis, and
a roller head mounted at one end of the bar and comprising two axes for rolls, wherein a first roll of the rolls is provided for turning on the toggle switch handle depending on a movement of the bar and a second roll of the rolls is provided for rolling over a plate and blocking a rotation of the bar around its longitudinal axis.

US Pat. No. 10,217,575

SWITCH DEVICE

ALPS ELECTRIC CO., LTD., ...

1. A switch device comprising:a base part which includes a switch element switchable between a pressed state and a released state;
an operating member which is disposed so as to be movable between a pressing position causing the pressed state of the switch element and a release position causing the released state of the switch element, in a pressing direction toward the pressing position from the release position and a release direction toward the release position from the pressing position;
a force transmission member which is disposed so as to be movable in the pressing direction and the release direction between the switch element and the operating member in an internal space defined between the base part and the operating member and transmits a force between the switch element and the operating member;
a light source configured to radiate light to the internal space; and
a reflective surface,
wherein the operating member includes
an operating outer surface configured to receive an operating force in the pressing direction from the outside,
an operating inner surface configured to be irradiated with light from the light source in the internal space, and
a transmitting member configured to transmit light between the operating outer surface and the operating inner surface,
the transmitting member has a transmitting inner surface which faces the internal space in the pressing direction,
at least a portion of the force transmission member is disposed along the pressing direction between the transmitting inner surface and the switch element,
the reflective surface is included in force transmission member and is disposed at a position where the reflective surface reflects at least a part of the light from the light source to at least a portion of the transmitting inner surface,
the operating member includes an operation-side contact portion which comes into contact with the force transmission member,
the force transmission member includes a light guiding part and a support post which moves integrally with each other,
the light guiding part has the reflective surface,
the support post has a transmission-side contact portion, and
the transmission-side contact portion is disposed at a position where the transmission-side contact portion is pressed from the operation-side contact portion in the pressing direction.

US Pat. No. 10,217,574

LOW-VOLTAGE SWITCHING DEVICE WITH A VARIABLE DESIGN

Siemens Aktiengesellschaf...

1. A low-voltage switching device, comprising:a base module having at least one connection region for electric conductors;
a separate auxiliary module having auxiliary contacts and a coil connection arranged in a separable manner from the base module, the separate auxiliary module being configured to attach to differently sized switching devices;
wherein the separate auxiliary module includes a variable configuration exchangeable surge limiter, selected for an intended application of the separate auxiliary module and arranged within the separate auxiliary module, includes an arc chamber having a variable configuration and includes an exchangeable enclosure having a variable configuration and moveable switching contacts with a contact carrier and a base plate, which are universally configured identically in each of a plurality of separate auxiliary modules; and
wherein the separate auxiliary module is selected from a group consisting of a first auxiliary module having a first configuration, a second auxiliary module having a second configuration and a third auxiliary module having a third configuration, the first, second and third configurations being different from each other.

US Pat. No. 10,217,572

LOW FREQUENCY CONVERTERS HAVING ELECTROCHEMICAL CAPACITORS

INTEL CORPORATION, Santa...

1. A power converter circuit comprising:an inductor to charge when coupled to an input voltage during a first state and to discharge during a second state; and
a load coupled to the inductor, the load including at least one electrochemical capacitor coupled in parallel to a resistor, wherein the at least one electrochemical capacitor comprises a pair of porous semiconductor structures, each porous semiconductor structure containing an electrolyte loaded into a plurality of pores to simplify monolithic integration with the power converter circuit.

US Pat. No. 10,217,570

ELECTRIC STORAGE DEVICE

JTEKT CORPORATION, Osaka...

1. An electric storage device comprising:an electrode body that has a plurality of positive plates and a plurality of negative plates, the positive plates and the negative plates being alternately stacked on each other via separators; and
a housing body that houses the electrode body together with an ion conductor, wherein
the electric storage device is provided with a magnetic field generating unit that generates magnetic force lines in a certain direction,
each of the positive plates includes a positive active material applied to both surfaces of a collecting foil.

US Pat. No. 10,217,569

DEVICES COMPRISING A CAPACITOR AND SUPPORT MATERIAL THAT LATERALLY SUPPORTS THE CAPACITOR

Micron Technology, Inc., ...

1. A device comprising:a capacitor comprising first and second electrodes having a capacitor insulator there-between;
the first electrode being elongated and extending elevationally, the first electrode comprising elevationally-extending first conductive material and comprising second conductive material that projects laterally outward from an elevationally-extending part of the first conductive material, the laterally-projecting second conductive material having a vertical thickness that is less than that of the elevationally-extending first conductive material; and
support material that laterally supports the capacitor, the support material contacting a tip end of the laterally-projecting second conductive material, the second electrode being vertically directly above and vertically directly below the laterally-projecting second conductive material and the second electrode being vertically directly above and vertically directly below the support material.

US Pat. No. 10,217,565

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component, comprising:a multilayer body including a first end surface and a second end surface located opposite each other in a length direction, a first lateral surface and a second lateral surface located opposite each other in a width direction perpendicular or substantially perpendicular to the length direction, and a first principal surface and a second principal surface located opposite each other in a thickness direction perpendicular or substantially perpendicular to the length direction and the width direction;
a first outer electrode that reaches the first principal surface, the second principal surface, the first lateral surface, and the second lateral surface from the first end surface;
a second outer electrode that reaches the first principal surface, the second principal surface, the first lateral surface, and the second lateral surface from the second end surface;
a third outer electrode that is provided on the first lateral surface so as to be located between the first end surface and the second end surface in the length direction and reaches the first principal surface and the second principal surface from the first lateral surface;
a fourth outer electrode that is provided on the second lateral surface so as to be located between the first end surface and the second end surface in the length direction and reaches the first principal surface and the second principal surface from the second lateral surface;
a pair of first insulating coating portions that is provided so that the third outer electrode is located therebetween in the length direction and reaches the first principal surface and the second principal surface from the first lateral surface; and
a pair of second insulating coating portions that is provided so that the fourth outer electrode is located therebetween in the length direction and reaches the first principal surface and the second principal surface from the second lateral surface; wherein
the multilayer body includes a plurality of dielectric layers and a plurality of inner electrode layers alternately laminated in a laminating direction that is the thickness direction;
the plurality of inner electrode layers include:
a plurality of first inner electrode layers connected to the first outer electrode and the second outer electrode; and
a plurality of second inner electrode layers connected to the third outer electrode and the fourth outer electrode;
the pair of first insulating coating portions is in at least one of a state in which inner end portions of the pair of first insulating coating portions in the length direction are in contact with the third outer electrode and a state in which outer end portions of the pair of first insulating coating portions in the length direction are in contact with the first outer electrode and the second outer electrode;
the pair of second insulating coating portions is located opposite the pair of first insulating coating portions in the width direction;
the pair of second insulating coating portions is in at least one of a state in which inner end portions of the pair of second insulating coating portions in the length direction are in contact with the fourth outer electrode and a state in which outer end portions of the pair of second insulating coating portions in the length direction are in contact with the first outer electrode and the second outer electrode;
the pair of first insulating coating portions are provided only on the first principal surface, the second principal surface, and the first lateral surface; and
the pair of second insulating coating portions are provided only on the first principal surface, the second principal surface, and the second lateral surface.

US Pat. No. 10,217,562

METHOD FOR MANUFACTURING R-T-B BASED SINTERED MAGNET

HITACHI METALS, LTD., To...

1. A method for producing a sintered R-T-B based magnet, comprising the steps of:providing a plurality of sintered R-T-B based magnet bodies (R is at least one of rare earth elements and necessarily contains Nd and/or Pr; and T is at least one of transition metals and necessarily contains Fe);
providing a plurality of alloy powder particles having a size of 90 ?m or less and containing a heavy rare earth element RH (the heavy rare earth RH is Tb and/or Dy) at a content of 20 mass % or greater and 80 mass % or less;
loading the plurality of sintered R-T-B based magnet bodies and the plurality of alloy powder particles of a ratio of 2% by weight or greater and 15% by weight or less with respect to the plurality of sintered R-T-B based magnet bodies into a process chamber; and
heating, while rotating and/or swinging, the process chamber to move the sintered R-T-B based magnet bodies and the alloy powder particles continuously or intermittently to perform an RH supply and diffusion process.

US Pat. No. 10,217,560

INDUCTOR

SIEMENS AKTIENGESELLSCHAF...

1. An inductor for induction thermography comprising:a rectangularly wound conductor with two short sides and two long sides;
wherein one of the two long sides comprises a closed conductor loop forming a rectangle with two longitudinal sides perpendicular to two width sides, all four sides free of electrical components except for a conductor that forms the closed conductor loop;
wherein two electrical terminals extend out from a first longitudinal side and away from a second longitudinal side, perpendicular to the two longitudinal sides and parallel to the two width sides along the one of the two long sides of the rectangularly wound conductor.

US Pat. No. 10,217,558

EMBEDDED MAGNETIC COMPONENT TRANSFORMER DEVICE

MURATA MANUFACTURING CO.,...

1. An embedded transformer device, comprising:an insulating substrate including a first side and a second side opposite the first side, and including a cavity therein, the cavity including an inner and an outer periphery;
a magnetic core housed in the cavity;
a primary winding extending through the insulating substrate and around a first side of the magnetic core;
a secondary winding extending through the insulating substrate and around a second side of the magnetic core; and
an auxiliary winding extending through the insulating substrate and around the first side of the magnetic core so as not to overlap with the primary winding; wherein
each of the primary, secondary, and auxiliary windings includes:
upper conductive traces;
lower conductive traces;
inner conductive connectors extending through the insulating substrate adjacent an inner periphery of the magnetic core, the inner conductive connectors respectively define electrical connections between respective upper conductive traces and respective lower conductive traces; and
outer conductive connectors extending through the insulating substrate adjacent an outer periphery of the magnetic core, the outer conductive connectors respectively define electrical connections between respective upper conductive traces and respective lower conductive traces;
the primary winding is spaced from the auxiliary winding so that electrical isolation is provided by a gap between the primary and auxiliary windings;
a conductive element is provided in the gap between the primary and auxiliary windings and on a same layer of the insulating substrate as the upper or lower conductive traces.

US Pat. No. 10,217,557

LAMINATED INDUCTOR

TAIYO YUDEN CO., LTD., T...

1. A laminated inductor, comprising:at least one first magnetic layer, the at least one first magnetic layer including three or more magnetic alloy particles arranged in the one axial direction and a first oxide film, the three or more magnetic alloy particles having an average particle diameter of 4 ?m or smaller, the first oxide film binding the magnetic alloy particles together and containing a first component including one or more elements that are more susceptible to oxidation than Fe, the one or more elements being other than Si and Zr;
an internal conductor including a plurality of conductive patterned portions, the plurality of conductive patterned portions being disposed so as to be opposed to each other in the one axial direction across the at least one first magnetic layer, the plurality of conductive patterned portions electrically connected to each other with the at least one first magnetic layer placed therebetween, each of the plurality of conductive patterned portions constituting a part of a coil wound around the one axial direction;
a plurality of second magnetic layers composed of magnetic alloy particles, the plurality of second magnetic layers being disposed around the plurality of conductive patterned portions so as to be opposed to each other in the one axial direction across the at least one first magnetic layer;
a plurality of third magnetic layers composed of magnetic alloy particles, the plurality of third magnetic layers being disposed so as to be opposed to each other in the one axial direction across the at least one first magnetic layer, the plurality of second magnetic layers, and the internal conductor; and
a pair of external electrodes electrically connected to the internal conductor.

US Pat. No. 10,217,548

COAXIAL CABLE

Hitachi Metals, Ltd., To...

1. A coaxial cable, comprising:a conductor;
an insulation layer provided around the conductor;
a shield layer provided around the insulation layer; and
a sheath provided around the shield layer,
wherein the insulation layer comprises a first insulation layer, a second insulation layer and a third insulation layer that are arranged in this order from a conductor side,
wherein the second layer comprises a foamed layer not adhering to the first insulation layer,
wherein the third insulation layer has a larger tensile strength than the second insulation layer, and
wherein the third insulation layer is provided to fill air bubble holes appearing on a surface of the second insulation layer.

US Pat. No. 10,217,543

TRANSPARENT ELECTROCONDUCTIVE FILM AND TOUCH SENSOR IN WHICH SAME IS USED

NITTO DENKO CORPORATION, ...

1. A transparent electroconductive film comprising:a transparent substrate; and
a transparent electroconductive coating formed on one side of the transparent substrate,
wherein
the transparent substrate has a second cured resin layer on its one surface on which the transparent electroconductive coating is not formed, the second cured resin layer including particles;
arithmetic mean surface roughness Ra in a 452 ?m×595 ?m field of view on a surface of the transparent electroconductive coating is more than 0 nm and 10 nm or less;
arithmetic mean surface roughness Ra in a 452 ?m×595 ?m field of view on a surface of the second cured resin layer of the transparent substrate on which the transparent electroconductive coating is not formed is more than 5 nm and less than 100 nm; and
a difference between the arithmetic mean surface roughness Ra in the 452 ?m×595 ?m field of view on the surface of the second cured resin layer and the arithmetic mean surface roughness Ra in the 452 ?m×595 ?m field of view on the surface of the transparent electroconductive coating is 5 nm or more.

US Pat. No. 10,217,542

CONDUCTIVE MEMBER

Sumitomo Wiring Systems, ...

1. A conductive member to be routed in a vehicle, comprising:a shape-retaining tubular conductor having excellent conductivity and an end, the tubular conductor has high shape retainability and is elongated;
a flexible conductor having first and second opposite ends, the flexible conductor has flexibility, the first end of the flexible conductor is connected to the end of the tubular conductor; and
a terminal that is connected to the second end of the flexible conductor, wherein the tubular conductor is longer than the flexible conductor.

US Pat. No. 10,217,538

CREATION OF ISOTOPES USING LASER BEAMS

ECOLE POLYTECHNIQUE, Pal...

1. A process for creating isotopes using laser beams, comprising steps of:/1/ converting a target, comprising a fuel, to a plasma state, and
/2/ generating particles with a set of laser beams and bombarding the target in the plasma state with the particles wherein:
the particle generation is synchronized with the target conversion; and
the bombarding produces nuclear reactions between the fuel and the particles and creates said isotopes.

US Pat. No. 10,217,536

SYSTEM FOR THE HIGHLY AUTONOMOUS OPERATION OF A MODULAR LIQUID-METAL REACTOR WITH STEAM CYCLE

U.S. Department of Energy...

1. A system for regulating nuclear reactor core activity comprising:a naturally circulating nuclear reactor having a nuclear reactor cooling outlet,
a nuclear reactor cooling inlet, and
a nuclear core with a negative temperature reactivity coefficient;
a steam generator having a saturated liquid space displaced above the nuclear reactor cooling outlet, and
a steam space;
a coolant loop where the coolant loop cycles coolant out through the nuclear reactor coolant outlet, where the coolant loop is in thermal communication with the saturated liquid space of the steam generator, and where the coolant loop cycles coolant in through the nuclear reactor coolant inlet;
a steam piping system in fluid communication with the steam space of the steam generator;
a three way valve having a valve shaft, in fluid communication at a three way valve inlet port with the steam piping system which leaves the steam generator;
an expansion turbine directly fluidly connected to and in fluid communication with the three way valve only at a three way valve first outlet port;
a condenser in fluid communication with the expansion turbine;
a pump header in fluid communication with the condenser;
a feedwater heater in fluid communication at a heater inlet port with the three way valve at a three way valve second outlet port and in fluid communication at a heater outlet port with the condenser;
a feedwater pump having a pump inlet port in fluid communication with the pump header, and
a pump discharge port;
a feedwater header in fluid communication with the pump discharge port of the feedwater pump, in thermal communication with the feedwater heater, and in fluid communication with the saturated liquid space of the steam generator;
an electric generator mechanically driven by the expansion turbine and electrically connected to an electrical grid; and
a controller separate from and in data communication with both the valve shaft of the three way valve and the electric generator, where the controller is programmed to
respond to an increase in power demand from the electric generator by directing movement of the valve shaft to concomitantly increase steam flow to the expansion turbine and decrease steam flow to the feedwater heater, and
respond to a decrease in power demand from the electric generator by directing movement of the valve shaft to concomitantly decrease steam flow to the expansion turbine and increase steam flow to the feedwater heater.

US Pat. No. 10,217,535

DEVICE AND METHOD FOR REMOVING CONTAMINATED MATERIAL

1. Device for removing contaminated materials from a wall, the device comprisingsuction plates which fix a support system of the device to the wall by means of a negative pressure, and
a rotating tool which has impact cutters in the circumferential direction, characterized in that disc-like saw blades spaced from one another are arranged in a second rotating tool upstream of the rotating tool in the working direction;
wherein the device can be arranged in the support system in a height-adjustable manner and the support system can be moved on the floor by way of a dolly.

US Pat. No. 10,217,534

METHOD FOR JOINING SILICON CARBIDE COMPONENTS TO ONE ANOTHER

1. A method for joining components to one another, comprising:(a) providing a first component, wherein the first component includes ceramic, metal, or composite, and wherein the first component has an upper portion and a contoured lower portion;
(b) providing a second component, wherein the second component includes ceramic, metal, or composite, and wherein the second component has an upper portion and a lower portion, and wherein the upper portion is adapted to receive the contoured lower portion of the first component;
(c) providing a predetermined amount of Al—Si braze foil, wherein the Al—Si braze foil includes a first phase that melts at a first temperature, and a second phase interspersed throughout the first phase, and wherein the second phase melts at a second temperature that is lower than the melting temperature of the first phase;
(d) grinding the Al—Si braze foil into a powder;
(e) mixing a predetermined amount of braze paste binder with the Al—Si powder to form a slurry;
(f) uniformly applying the slurry to the lower portion of the first component;
(g) uniformly applying the slurry to the upper portion of the second component and bringing the upper portion of the second component into contact with the lower portion of the first component; and
(h) heating the applied slurry to a temperature in the range of 725° C. to 1450° C. for a predetermined period of time, wherein heating the applied slurry to a temperature in the range of 725° C. to 1450° C. for a predetermined period of time softens the first phase and melts the second phase, wherein the first phase remains in a solid or a semi-solid state, and wherein the second phase segregates to the boundaries of the first phase and transforms the applied slurry into a substantially porosity-free adherent material that joins the first component to the second component.

US Pat. No. 10,217,531

FORMATION OF A FIELD REVERSED CONFIGURATION FOR MAGNETIC AND ELECTROSTATIC CONFINEMENT OF PLASMA

THE REGENTS OF THE UNIVER...

1. A method comprising the steps ofcreating a magnetic guide field within a cylindrical chamber having a longitudinal axis, wherein the magnetic guide field having field lines axially extending within the chamber parallel to the longitudinal axis,
injecting a plasma of charged electron and ion particles into the chamber toward a midplane of the chamber,
causing the plasma of charged electron and ion particles to rotate within the chamber and form a magnetic poloidal self-field surrounding the rotating plasma due to the current carried by the rotating plasma, and
increasing the rotational energy of the plasma to increase the magnitude of the self-field to a level that overcomes the magnetic guide field axially extending within the chamber causing the formation of a magnetic field within the chamber with field reversed topology.

US Pat. No. 10,217,530

PATIENT-SPECIFIC CUTTING BLOCK AND METHOD OF MANUFACTURING SAME

ZIMMER, INC., Warsaw, IN...

1. A method of creating a model of a patient-specific structure of a cutting block, the cutting block used for assisting an operator in cutting at least one plane in a bone of a patient, the method comprising:obtaining geometrical data of a bone and of an intramedullary canal of the bone;
determining a penetration of a fixing rod to be inserted in and extending partially out from an intramedullary canal of the bone, the penetration based on the geometrical data of the intramedullary canal of the bone and on a geometry of the fixing rod;
determining an orientation of a portion of the fixing rod projecting out of the bone relative to the bone based on the geometrical data of the bone, on the geometry of the fixing rod and on the penetration; and
creating the model of the patient-specific structure of the cutting block using the geometrical data of the bone, a desired position and orientation of the at least one cut plane on the bone, and the orientation of the portion of the fixing rod projecting out of the bone, the model of the patient-specific structure being three dimensional and having a unique coupling orientation in which the cutting block is on the portion of the fixing rod projecting out of the bone and the cutting block contacts the bone in blocked abutment planned pre-operatively, a cut slot of the cutting block being aligned with the at least one cut plane on the bone at said unique coupling orientation.

US Pat. No. 10,217,528

OPTIMIZING STATE TRANSITION SET POINTS FOR SCHEDULE RISK MANAGEMENT

General Electric Company,...

1. A computer-implemented method comprising:calculating, using a processor, a cumulative distribution function for a cumulative duration of one or more tasks in a schedule for a healthcare protocol for a hospital system in a healthcare facility based on a probability density function associated with a task duration for each of the one or more tasks;
determining, using the processor based on the cumulative distribution function, a plurality of schedule risk states for each task in a healthcare protocol, each schedule risk state associated with an upper specification limit and a lower specification limit defining the schedule risk state along the cumulative distribution function, each schedule risk state associated with a corrective workflow based on the upper specification limit and the lower specification limit along the cumulative distribution function;
identifying, within the upper specification limit and the lower specification limit for each respective schedule risk state, one or more schedule risk state transition setpoints associated with one or more probabilities along the cumulative distribution function, each of the one or more setpoints indicating a change in schedule risk;
monitoring, using the processor, execution of the one or more tasks in the healthcare protocol to identify a transition in schedule risk state according to the upper specification limit and lower specification limit indicated by at least one of the one or more setpoints; and
automatically triggering, using the processor, a corrective workflow associated with the respective schedule risk state to react to an actual or predicted change in schedule risk state based on the one or more setpoints associated with the schedule risk state by adjusting at least one of the one or more schedule risk state transition setpoints for the schedule risk state based on the actual or predicted change to improve a probability of execution of one or more tasks within the schedule for the healthcare protocol and updating a configuration associated with the hospital system based on the adjusted one or more schedule risk state transition setpoint.

US Pat. No. 10,217,526

METHOD FOR MEASURING STRENGTH OF ASSOCIATIONS

University of Washington,...

1. A method of measuring a subject's strength of associations involving each of a first pair of first and second categories with each of a second pair of third and fourth categories, without any use of single-task practice trials, the method comprising:in a first set of trials, causing presentation, via a display device coupled to a computer accessible to a subject, of a first series of exemplars, the first series of exemplars including exemplars from all four categories;
storing performance by the subject of a series of tasks in the first set of trials, wherein the tasks in the first set of trials are to respond in a first manner when there is presented an exemplar of either the first category or the third category and in a second manner when there is presented an exemplar in any other category, and wherein the task as to the second manner of response has no explicit reference to the second or fourth category;
in a second set of trials, causing presentation, via the display device, of a second series of exemplars in the second set of trials, the second series of exemplars including exemplars from all four categories;
storing performance by the subject of a series of tasks in the second set of trials, wherein the tasks in the second set of trials are to respond in a first manner when there is presented an exemplar of either the second category or the third category and in a second manner when there is presented an exemplar in any other category, and wherein the task as to the second manner of response has no explicit reference to the first or fourth category;
measuring, in a first computer process, for each response in each trial, a time elapsed between exemplar presentation to the subject and response of the subject via the computer to the presented exemplar, to produce a latency measurement therefor; and
in a second computer process, calculating a measure of the subject's strength of associations involving each of the first and second categories with each of the third and fourth categories from the latency measurements,
so that performance data from the subject is obtained without any use of single-task practice trials.

US Pat. No. 10,217,525

MEMORY APPARATUS WITH POST PACKAGE REPAIR

Micron Technology, Imc., ...

1. An apparatus comprising:a non-volatile storage element;
a storage latch circuit coupled to the non-volatile storage element; and
a control circuit configured, during a first repair mode, to provide first repair address information to the non-volatile storage element,
wherein the control circuit is configured, during a second repair mode, to provide second repair address information to the storage latch circuit.

US Pat. No. 10,217,524

AUTORECOVERY AFTER MANUFACTURING/SYSTEM INTEGRATION

Micron Technology, Inc., ...

1. A method of managing a system comprising a processor and a memory device external to the processor, the method comprising:exposing the memory device to heat of soldering the memory device to a platform of the system, then powering up the memory device;
testing pre-programmed data using control circuitry of the memory device, wherein the pre-programmed data comprises data programmed to the memory device prior to exposing the memory device to the heat of soldering the memory device to the platform;
in response to results of the testing indicating repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device instructing the memory device to repair the pre-programmed data; and
in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.

US Pat. No. 10,217,522

FAST MAGNETOELECTRIC DEVICE BASED ON CURRENT-DRIVEN DOMAIN WALL PROPAGATION

Regents of the University...

1. An electronic device comprising:an input ferroelectric (FE) capacitor including a first dielectric layer;
an output FE capacitor including a second dielectric layer;
a channel positioned beneath the first dielectric layer of the input FE capacitor and positioned beneath the second dielectric layer of the output FE capacitor, wherein the channel forms at least part of a lower terminal of the input FE capacitor, wherein the channel forms at least part of a lower terminal of the output FE capacitor, and wherein the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor;
a transistor-based drive circuit electrically connected to an output node at an upper terminal of the output FE capacitor, wherein the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device;
a layer of high-resistivity material (HRM) positioned beneath the channel; and
a switch electrically connected to the layer of HRM proximate the output FE capacitor or proximate the input FE capacitor, wherein the layer of HRM is configured to carry an electrical current when the switch is closed, and wherein the electrical current is configured to facilitate the channel to carry the magnetic signal.