US Pat. No. 10,193,406

ROTATING MACHINERY

MITSUBISHI HITACHI POWER ...

1. Rotating machinery comprising:a rotor of 2n poles, n being an integer equal to or greater than 1;
84n slots; and
three-phase stator windings;
a top coil being accommodated at the diametrically inner side of each of the slots;
a bottom coil being accommodated at the diametrically outer side of each of the slots;
the top coil and the bottom coil being connected to each other to form each of the stator windings;
the stator windings having 2n phase belts per one phase;
each of the phase belts being configured from a first parallel winding and a second parallel winding;
where an average position in the circumferential direction of all of the top coils and the bottom coils that configure each of the phase belts is the center of the phase belt and the arrangement of the first and second parallel windings on at least one of the phase belts is viewed in order from the side near to the center of the phase belt, the top or bottom coils being disposed in the order of the second, first, first, second, first, second, first, second, second, first, second, first, second, and first parallel windings while the bottom or top coils connected to the top or bottom coils are disposed in the order of the first, second, second, first, second, first, second, first, second, first, first, second, first, and second parallel windings.

US Pat. No. 10,193,405

ROTARY ELECTRIC MACHINE AND MANUFACTURING METHOD THEREOF

Mitsubishi Electric Corpo...

1. A rotary electric machine comprising: a stator that includes stator coils for a plurality of phases at an inner circumference portion of a stator core that is formed in an annular shape; a rotor that is inserted to central space of the stator, and includes a plurality of magnetic poles at an outer circumference portion; and a connection component that is mounted at least at one end portion in an axis direction of the stator, and mutually connects the stator coils for the plurality of phases, and holds bus bars that feed an electric current to the stator coils for the plurality of phases; wherein the connection component includes a holder made of an insulating material that is formed in an annular shape, and is mounted at the stator in a state where one end portion in an axis direction of the connection component is faced to the one end portion in the axis direction of the stator, and includes a plurality of bus-bar storage grooves having an annular shape that are concentrically arranged at the other end portion in the axis direction of the connection component, a plurality of bus bars having an annular shape that are respectively installed in the plurality of bus-bar storage grooves, and are respectively corresponded to the plurality of phases, and an adhesive resin that is arranged in each of the bus-bar storage grooves, and fixes the plurality of bus bars to the holder; and the plurality of bus bars include bus-bar lead terminals that are respectively connected to coil lead terminals of the stator coils for the plurality of phases that are corresponded to the bus bars; and the bus-bar lead terminals are formed in such a way that the bus-bar lead terminals are protruded from the bus bars to the axis direction of the stator; and the plurality of bus-bar storage grooves are formed by using a plurality of partitions that are concentrically arranged in a diameter direction of the stator via gaps; and in the plurality of partitions, lengths, in the axis direction, of a most outer circumference partition that is positioned at a most outer circumference side in the diameter direction, and a most inner circumference partition that is positioned at a most inner circumference side in the diameter direction, are longer than lengths, in the axis direction, of a plurality of middle partitions that are positioned between the most outer circumference partition and the most inner circumference partition; wherein the bus-bar lead terminals include first extended portions that are configured in such a way that those are led from the bus bars to the axis direction of the stator, and a thickness direction is identical to a diameter direction of the stator, and a width direction is identical to a circumference direction of the stator; and second extended portions that are bent from end portions of the first extended portions in the axis direction of the stator to an edgewise direction of the first extended portions, and are extended in the circumference direction of the stator.

US Pat. No. 10,193,401

GENERATORS HAVING ROTORS THAT PROVIDE ALTERNATE MAGNETIC CIRCUITS

1. A generator comprising:stator comprising:
a generator coil wrapped around a generator core;
a first magnetic flux element having a first stator pole,
wherein the first magnetic flux element is magnetically coupled to a first end of the generator core across a first medium having a first reluctance;
a first magnetic flux donor that donates magnetic flux having a first polarity to the first magnetic flux element;
a second magnetic flux element having a second stator pole,
wherein the second magnetic flux element is magnetically coupled to a second end of the generator core across a second medium having a second reluctance; and
a second magnetic flux donor that donates magnetic flux having a second polarity, opposite to the first polarity, to the second magnetic flux element; and
a rotor comprising:
a third magnetic flux element having first and second rotor poles;
a rotor coil wrapped around the third magnetic flux element;
a third magnetic flux donor that donates magnetic flux having the second polarity to the third magnetic flux element; and
a fourth magnetic flux donor that donates magnetic flux having the first polarity to the third magnetic flux element, and
wherein the first stator pole and the first rotor pole are magnetically coupled across a third medium having a third reluctance when the first rotor pole is substantially aligned with the first stator pole, and
wherein the first reluctance is greater than the third reluctance when the first rotor pole is substantially aligned with the first stator pole.

US Pat. No. 10,193,393

WIRELESS INDUCTIVE POWER TRANSFER

KONINKLIJKE PHILIPS N.V.,...

1. A power transmitter for wirelessly providing power to a power receiver using an inductive power signal; the power transmitter comprising:a variable resonance circuit for generating the inductive power signal in response to a drive signal, the variable resonance circuit having a resonance frequency being a variable resonance frequency;
a driver for generating the drive signal for the variable resonance circuit, the drive signal having an operating frequency;
a load modulation receiver for demodulating load modulation of the inductive power signal by the power receiver and for generating a demodulation quality measure; and
an adaptor for adapting the operating frequency and the resonance frequency to converge, the adaptation of the operating frequency and the resonance frequency further being in response to the demodulation quality measure.

US Pat. No. 10,193,392

WIRELESS POWER TRANSFER DEVICE AND WIRELESS POWER TRANSFER SYSTEM

LG INNOTEK CO., LTD., Se...

1. A transmitter for generating a wireless power transmitted to a receiver, the transmitter comprising:a control part for generating first to fourth AC power control signals; and
a power conversion part for generating an AC power including a positive polarity output voltage and a negative polarity output voltage in response to the first to fourth AC power control signals, wherein the power conversion part includes:
a first switching element connected between a first node and a second node and controlled in response to the first AC power control signal;
a second switching element connected between the second node and a ground and controlled in response to the second AC power control signal;
a third switching element connected between the first node and a third node and controlled in response to the third AC power control signal; and
a fourth switching element connected between the third node and the ground and controlled in response to the fourth AC power control signal,
wherein when the first and fourth switching elements are turned on in response to the first and fourth AC power control signals, the positive polarity output voltage is generated, and when the second and third switching elements are turned on in response to the second and third AC power control signals, the negative polarity output voltage is generated,
wherein a duty ratio of the positive polarity output voltage is determined by a falling time of the fourth AC power control signal, and
wherein a duty ratio of the negative polarity output voltage is determined by a falling time of the third AC power control signal.

US Pat. No. 10,193,391

POWER TRANSMITTING APPARATUS, POWER RECEIVING APPARATUS, WIRELESS POWER TRANSFER SYSTEM, CONTROL METHOD, AND STORAGE MEDIUM

CANON KABUSHIKI KAISHA, ...

1. A power transmitting apparatus comprising:a power transmission unit configured to wirelessly transmit power to one or more power receiving apparatuses; and
a processor configured to function as:
a receiving unit configured to receive, from each of the one or more power receiving apparatuses, function information;
a determination unit configured to determine, based on the function information received from each of the one or more power receiving apparatuses, whether each of the one or more power receiving apparatuses has a function for internally lowering a voltage obtained through power reception; and
a control unit configured to control the power transmission unit to perform power transmission in a first manner in a case where the determination unit determines that at least one of the one or more power receiving apparatuses does not have the function for internally lowering the voltage obtained through power reception, and to control the power transmission unit to perform power transmission in a second manner that is different from the first manner in a case where the determination unit determines that all of the one or more power receiving apparatuses have the function for internally lowering the voltage obtained through power reception.

US Pat. No. 10,193,390

WIRELESS POWER TRANSMITTER CONFIGURATION FOR POWER TRANSMISSION THROUGH A PARTITION

MediaTek Inc., Hsin-Chu ...

1. A method for configuring a wireless power transmitter to transmit power wirelessly through a partition between a wireless power receiver and the wireless power transmitter at an installation location of the wireless power transmitter, the method comprising:detecting, at the wireless power receiver, a plurality of signals representative of wirelessly received power levels by at least one receiving coil of the wireless power receiver, wherein the power levels correspond to wireless power transmitted in a sequence of power levels by the wireless power transmitter through the partition;
indicating, on a display of the wireless power receiver, a direction in which to move the wireless power receiver to receive a higher magnetic field from the wireless power transmitter; and
identifying by the wireless power receiver, to the wireless power transmitter, at least one transmit power level of the power levels received from the wireless power transmitter that provides a received power level at the at least one receiving coil that is suitable for charging and/or operating a wireless power device, wherein the identifying occurs after the plurality of signals have been detected by the wireless power receiver.

US Pat. No. 10,193,386

WIRELESS CHARGING METHOD AND SYSTEM, WIRELESS CHARGING DEVICE AND WEARABLE DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A wireless charging method, comprising:receiving, by a charging device, electric power usage data from at least two wearable devices;
determining, by the charging device, an electric power distribution solution according to the electric power usage data, the electric power distribution solution being used to determine a charging order and charging electric power for charging one or more of the at least two wearable devices;
performing, by the charging device, wireless charging on one or more of the at least two wearable devices according to the electric power distribution solution; and
sending, by the charging device, the electric power distribution solution to at least one of the at least two wearable devices, the at least one of the at least two wearable devices controlling output load and a quantity of turns of a wireless charging coil to receive electric power, and the at least one of the at least two wearable devices controlling output of the received electric power and an output time to a service in use and a battery.

US Pat. No. 10,193,385

POWER SYSTEM MONITORING APPARATUS, POWER SYSTEM CONTROL APPARATUS, AND POWER SYSTEM MONITORING METHOD EMPLOYING EVENTS OF ASSUMABLE BREAKDOWNS AND ASSUMABLE OUTPUT CHANGES

Hitachi, Ltd., Tokyo (JP...

1. A power system monitoring apparatus that monitors a power system, the apparatus comprising a processor coupled to the power system and programmed to:input assumable system breakdown data, which is data of assumable breakdown of the power system, including an occurrence frequency of each assumable breakdown of the power system and assumable output change data including an occurrence frequency of each assumable output change of each generator connected to the power system; and
generate conditions by which events of the assumable breakdowns and the assumable output changes are combined based on the occurrence frequencies of the assumable breakdown and the assumable output change and outputs a control plan to control said each generator for each of the conditions;
wherein an event of an assumable breakdown is an event of breakdown that is assumed to cause supply troubles in a main segment of the power system; and
wherein an event of an assumable output change is an event of output change of a power generation facility group which can affect a main current of the power system.

US Pat. No. 10,193,384

SYSTEMS AND METHODS FOR SELECTING GRID ACTIONS TO IMPROVE GRID OUTCOMES

3M INNOVATIVE PROPERTIES ...

1. A computer-implemented method, comprising:receiving an opportunity to vary a control on a utility grid comprising a plurality of possible grid control actions;
receiving effectiveness data for the possible grid control actions comprising confidence intervals around the effects of each possible grid control action;
selecting a grid control action, using a processor, based on the overlap in confidence intervals of the effectiveness data; and
implementing the selected grid control action on the utility grid,
further comprising determining an opportunity to vary a control on a utility grid by referencing current states of the controls on the utility grid and a multidimensional space representing possible grid control actions.

US Pat. No. 10,193,383

DUAL-SHAFT GAS TURBINE POWER GENERATION SYSTEM, AND CONTROL DEVICE AND CONTROL METHOD FOR GAS TURBINE SYSTEM

Hitachi, Ltd., Tokyo (JP...

1. A dual-shaft gas turbine power generation system comprising:a compressor which pressurizes air and generates compressed air;
a combustor which mixes and combusts the compressed air and a fuel;
a high-pressure gas turbine which is driven by a combustion gas obtained in the combustor;
a first rotating shaft which connects the compressor and the high-pressure gas turbine;
an electric motor connected to the first rotating shaft;
a governor which adjusts an amount of air taken into the compressor and thus controls an output of the high-pressure gas turbine;
a low-pressure gas turbine driven by the combustion gas after driving the high-pressure gas turbine;
a second rotating shaft connected to the low-pressure gas turbine;
a synchronous power generator connected to the second rotating shaft generating power of an external grid frequency and connected to an external grid;
a frequency converter which is provided on a power transmission path to bidirectionally transmit power between the synchronous power generator and the electric motor, and which converts a frequency of power transmitted between the synchronous power generator and the electric motor;
a control device which controls a frequency converter control device for controlling the frequency converter and the governor on the basis of a power output command value indicating power to be outputted to the external grid, and thus controls a total output of the high-pressure gas turbine, the low-pressure gas turbine and the electric motor;
a transformer which converts a voltage outputted from the synchronous power generator to the external grid;
a circuit breaker to cut off power transmitted to the external grid via the transformer;
a voltage measuring device disposed between the external grid and the circuit breaker and which measures a voltage on a side of the external grid; and
an abnormality control device which detects a voltage abnormality generated in the external grid on the basis of a result of comparison between a predetermined voltage abnormality reference value for the external grid and the measured voltage by the voltage measuring device, and, when the voltage abnormality is detected, controls the frequency converter control device in such a way that a load, by the electric motor as viewed from the high-pressure turbine via the first rotating shaft, is decreased.

US Pat. No. 10,193,381

LOAD MANAGEMENT AND SWITCHING DEVICES AND METHODS

Reliance Controls Corpora...

1. A method for managing loads supplied by a secondary power source, the method comprising the steps of:providing a first set of normally closed relays electrically connected to a first plurality of loads;
providing a second set of normally closed relays electrically connected to a second plurality of loads;
providing a first timer electrically connected to the first set of relays and set to a predetermined amount of time;
providing a second timer electrically connected to the second set of relays and set to a predetermined amount of time, wherein the set time of the second timer is greater than the set time of the first timer;
providing a first current transformer;
providing a second current transformer;
wherein the first and second current transformers receive a current draw from the secondary power source and produce an actual voltage proportional to the current passed through each of the first and second current transformers;
providing a reference voltage, wherein the reference voltage is a voltage equal to a predetermined percentage of a maximum allowable current draw from the secondary power source;
monitoring the actual voltage;
comparing the reference voltage with the actual voltage; and
when the actual voltage exceeds the reference voltage:
opening both the first and second set of relays;
starting both the first and second timers;
when the set time of the first timer elapses, close the first set of relays; and
when the set time of the second timer elapses, close the second set of relays.

US Pat. No. 10,193,379

DIRECT CURRENT UNINTERRUPTIBLE POWER SUPPLY SYSTEM

Jae Jin Lee, Chungcheong...

1. A direct current (DC) uninterruptible power supply system provided with a first connection unit electrically connected to a DC power conversion system which converts prevailing alternating current (AC) power into DC power, an auxiliary power supply device charged with the DC power, and a second connection unit which is electrically connected to a load and supplies the DC power or power output from the auxiliary power supply device to the load, the DC uninterruptible power supply system comprising:a charging portion which boosts a level of DC voltage power supplied from the DC power conversion system normally connected to the first connection unit and charges the auxiliary power supply device with the boosted DC voltage power;
a discharge portion which generates internal voltage power by stepping down a level of voltage power of the auxiliary power supply device;
a comparator which compares the level of the DC voltage power supplied from the DC power conversion system with a level of a set reference voltage and outputs a clear voltage or a set voltage according to a result thereof; and
a switchover portion which comprises a relay connected to the first connection unit, the second connection unit, and the discharge portion, in which due to disconnection of the DC power conversion system from the first connection unit and a damage or short circuit of the DC power conversion system, the set voltage is supplied from the comparator, thereby allowing the relay to be set in such a way that connection between the first connection unit and the second connection unit is cut off and the discharge portion and the second connection unit are connected to allow the internal voltage power generated by the discharge portion to be supplied to the second connection unit, and as the DC power conversion system is normally connected to the first connection unit, the clear voltage is supplied from the comparator to allow the relay to become in a clear state in such a way that connection between the discharge portion and the second connection unit is cut off and the first connection unit and the second connection unit are connected to supply the DC power supplied from the DC power conversion system to the second connection unit.

US Pat. No. 10,193,371

CHARGING/DISCHARGING APPARATUS USING THERMOELECTRIC CONVERSION EFFECT

Inventec (Pudong) Technol...

1. A charging/discharging apparatus, comprising:a thermoelectric conversion module disposed between an upper cover and a lower cover of a wearable device, the thermoelectric conversion module generating a current according to a temperature difference between the upper cover and the lower cover;
a current path providing unit coupling with the thermoelectric conversion module for providing a first current path and a second current path;
a charging/discharging element coupling with the current path providing unit;
a third current path, wherein the charging/discharging element provides a first current to the thermoelectric conversion module through the third current path to heat up a temperature of the upper cover and cool down a temperature of the lower cover, wherein the first current flows through the thermoelectric conversion module according to a first direction;
a fourth current path, wherein the charging/discharging element provides a second current to the thermoelectric conversion module through the fourth current path to heat up a temperature of the lower cover and cool down a temperature of the upper cover, wherein the second current flows through the thermoelectric conversion module according to a second direction, wherein the first direction is opposite to the second direction; and
a switch disposed among the thermoelectric conversion module, the third current path, the forth current path and the current path providing unit, wherein the switch selects one of the third current path, the fourth current path and the current path providing unit to couple with the thermoelectric conversion module,
wherein, when a temperature of the lower cover is higher than a temperature of the upper cover, the current charges the charging/discharging element through the first current path, and
when a temperature of the upper cover is higher than a temperature of the lower cover, the current charges the charging/discharging element through the second current path.

US Pat. No. 10,193,370

MECHANICALLY CONTROLLED PRE-CHARGE SYSTEM

Amazon Technologies, Inc....

1. A system to pre-charge an electrical device having a capacitance, the system comprising:first, second, and third terminals mounted in a battery compartment of the electrical device; and
a mechanism configured to receive a battery and move the battery from an insertion position outside the battery compartment, through a range of pre-charging positions where the battery is partially inserted into the battery compartment, to an installed position where the battery is fully inserted into the battery compartment, wherein:
at the insertion position, the battery is not electrically connected to the first and second terminals;
within the range of pre-charging positions, a first battery terminal of the battery is electrically connected with the first terminal and a second battery terminal of the battery is electrically connected with the second terminal, the first terminal being electrically connected with a first charge path having a first nonzero resistivity; and
at the installed position, the first battery terminal is electrically connected with the third terminal and the second battery terminal is electrically connected with the second terminal, the third terminal being electrically connected with a second charge path having a second resistivity that is lower that the first resistivity.

US Pat. No. 10,193,362

TERMINAL STAND AND WIRELESS CHARGING DEVICE

1. A terminal support, comprising:a base with a placing surface used for placing a terminal;
a force generation module; and
a control module configured to control the force generation module to generate a force which acts on the terminal to change a relative position relationship between the terminal and the placing surface,
wherein the terminal support further comprises a detection module connected with the control module, and the detection module is configured to acquire a detection signal of a state parameter of the terminal or an instruction input by a user, and send the detection signal to the control module to make the control module control the force generation module according to the detection signal to generate a force on the terminal.

US Pat. No. 10,193,361

BATTERY PROTECTION CIRCUIT AND METHOD

MOTOROLA SOLUTIONS, INC.,...

1. A battery protection circuit within a battery pack, the battery protection circuit comprising:a current limiting switch provided on a current path of a battery and coupled to a current limiting control circuit to limit current output by the battery, the current limiting switch having a switch voltage contributing to a first voltage;
a control switch;
a power limiting circuit comparator having a reference voltage input to receive a reference voltage, a voltage input to receive the first voltage, and a control output coupled to the control switch, the power limiting circuit comparator configured to provide a control signal that opens the control switch when the first voltage exceeds the reference voltage to prevent the battery pack from generating excess heat, wherein the current limiting switch is a first current limiting switch, and wherein the control switch is a second current limiting switch provided on the current path of the battery and is coupled to a second current limiting control circuit to limit current output by the battery, the second current limiting switch having a second switch voltage contributing to the first voltage,
a first driving switch having a first driver control input coupled to the control output of the power limiting circuit comparator and a first driving output coupled to a first control input of the current limiting switch; and
a second driving switch having a second driver control input coupled to the control output of the power limiting circuit comparator and a second driving output coupled to a second control input of the second current limiting switch.

US Pat. No. 10,193,354

NEAR ZERO VOLT STORAGE TOLERANT ELECTROCHEMICAL CELLS THROUGH REVERSIBLE ION MANAGEMENT

Rochester Institute of Te...

1. An electrochemical cell, comprising:a positive electrode;
a negative electrode; and
an electrolyte, wherein the electrochemical cell contains reversible ions in an amount sufficient to maintain a negative electrode potential verses reference level that is less than a damage potential of the negative electrode and a positive electrode potential verses reference level that is greater than a damage potential of the positive electrode of the cell under an applied load at a near zero cell voltage state, such that the cell is capable of recharge from the near zero cell voltage state.

US Pat. No. 10,193,352

WIRELESS POWER TRANSMISSION APPARATUS

LG INNOTEK CO., LTD., Se...

1. A wireless power transmission apparatus comprising:a mounting member;
an upper transmission coil disposed on the mounting member; and
first and second terminals disposed in the mounting member,
wherein the upper transmission coil comprises:
an outer coil part connected to the first terminal and formed in one-turn with respect to a central axis between the first and second terminals;
a first inner coil part connected to the outer coil part and formed in a half-turn on a first side of the central axis;
a second inner coil part connected to the first inner coil part, formed in a half-turn on a second side of the central axis;
a third inner coil part connected to the second inner coil part, formed in a half-turn on the first side of the central axis; and
a fourth inner coil part connected to the third inner coil part and the second terminal, formed in a half-turn on the second side of the central axis,
wherein the one-turn of the outer coil includes a rectangular shape with rounded corners or a circular shape, and
wherein the half-turn of the first, second and third inner coil parts includes two rounded corners of a rectangular shape or one half or less of a circular shape.

US Pat. No. 10,193,350

POWER SUPPLYING DEVICE AND POWER RECEIVING DEVICE

SONY CORPORATION, Tokyo ...

1. A power supplying device, comprising:a controller configured to:
receive, from a first device of a plurality of devices, a first request to supply power through a direct-current bus line, wherein DC power flows through the direct-current bus line;
determine, based on the first request, whether the power supplying device is able to supply the power to the first device;
transmit a response to the first device based on the determination that the power supplying device is able to supply the power, wherein the response indicates the power supplying device as a candidate to supply the power;
determine one of a presence or an absence of a right to control the direct-current bus line, wherein the presence of the right to control the direct-current bus line indicates that a second device of the plurality of devices has the right to control the direct-current bus line;
acquire the right to control the direct-current bus line, based on the absence of the right to control;
notify the plurality of devices of the acquisition of the right to control the direct-current bus line; and
control the supply of the power through the direct-current bus line to the first device based on the acquired right to control the direct-current bus line.

US Pat. No. 10,193,348

ARRANGEMENT AND INSTALLATION FOR TRANSMITTING ELECTRIC POWER WITH A RESERVE RECTIFIER

Siemens Aktiengesellschaf...

1. An arrangement, comprising:a first group of rectifiers having a DC voltage side connected to form a series circuit on the DC voltage side, and an AC voltage side to be connected to a first AC voltage network;
a plurality of switching devices;
a reserve rectifier having an AC voltage side and a DC voltage side, wherein, on occasion of a fault of one of said rectifiers of said first group of rectifiers, said AC voltage side of said reserve rectifier is to be electrically connected by way of a respective said switching device of said plurality of switching devices to the first AC voltage network and said DC voltage side of said reserve rectifier is to be connected to a first DC voltage line to form an augmented series circuit with said rectifiers of said first group of rectifiers.

US Pat. No. 10,193,346

INTERFACE FOR RENEWABLE ENERGY SYSTEM

Technology Research, LLC,...

1. An interface system for a renewable energy system, the interface system comprising:a plurality of micro-inverter boards, the micro-inverter boards each comprising:
a micro-inverter;
a DC power input configured for connecting the micro-inverter to a DC power source;
an AC power output configured for connecting the micro-inverter to a load and an external AC power grid; and
a controller for controlling AC power from the micro-inverter to be in phase with the external AC power grid; and
a switching matrix comprising:
a first switch, wherein the first switch is positioned between the load and the micro-inverters of the plurality of micro-inverter boards and also between the micro-inverters of the plurality of micro-inverter boards and the external AC power grid; and
a second switch, wherein the second switch is positioned between the external AC power grid and the micro-inverters of the plurality of micro-inverter boards and also between the external AC power grid and the load,
wherein the first switch and the second switch are each adjustable between an open position and a closed position, the micro-inverters of the plurality of micro-inverter boards being connected to the external AC power grid when the first switch and the second switch are in their respective closed positions, and the micro-inverters of the plurality of micro-inverter boards being disconnected from the external AC power grid when at least one of the first switch or the second switch is in the open position.

US Pat. No. 10,193,339

GRID INTEGRATED CONTROL APPARATUS, GRID CONTROL SYSTEM, GRID CONTROL APPARATUS, PROGRAM, AND CONTROL METHOD

NEC Corporation, Tokyo (...

1. A grid control system, comprising:a plurality of grids, wherein each of the plurality of grids includes at least one processor configured to execute machine-readable instructions to implement:
a power transmission and reception unit that transmits and receives power between a grid of the plurality of grids and one or more other grids of the plurality of grids through a power transmission line; and
a grid control unit that controls the power transmission and reception unit on the basis of a control instruction received from a grid integrated control apparatus connected through a communication line,
wherein at least one of the grids of the plurality of grids includes a distribution unit that distributes power to a consumer consuming power; and
the grid integrated control apparatus comprises at least one processor configured to execute machine-readable instructions to implement:
a supply and demand energy information receiver unit that receives, for each of the grids of the plurality of grids, supply and demand energy information indicating a difference between supply energy from the grid to the one or more other grids and supply energy to the grid from the one or more other grids;
a cost information receiver unit that receives cost information indicating a cost required for power transmission between the plurality of grids, the cost information including a wheeling charge per unit time required for power transmission through the power transmission line for each combination of a grid of the plurality of grids that supplies power and a grid of the plurality of grids that receives power, and a power loss caused by power transmission through the power transmission line for each combination of a grid of the plurality of grids that supplies power and a grid of the plurality of grids that receives power;
a grid control instruction generation unit that performs:
determining a combination of: the grid that supplies power; the grid that receives power; and a transmitted energy, on the basis of the supply and demand energy information received by the supply and demand energy information receiver unit and the cost information received by the cost information receiver unit;
generating the control instruction for controlling power transmission of each of the grids of the plurality of grids on the basis of the determined combination; and
transmitting the control instruction to each of the grids, the control instruction adjusting an amount of the power supplied by the grid that supplies power based on the determined combination;
wherein one or more of the grids includes a power storage unit configured to store energy; and
a range determination unit that sets a range of the stored energy by increasing and/or decreasing an upper limit and/or a lower limited of a range of the stored energy on the basis of the control instruction.

US Pat. No. 10,193,337

SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A semiconductor device comprising:an internal circuit;
a power supply line;
a grounding line;
a voltage regulator configured to generate, based on a power supply voltage, an internal power supply voltage for operating said internal circuit to apply said internal power supply voltage to said internal circuit via said power supply line and said grounding line, said internal power supply voltage having a voltage value lower than a voltage value of said power supply voltage; and
a protection circuit having first to n-th transistors (“n” denotes an integer being 2 or more) of PNP type which are Darlington-connected with one another,
wherein
a collector terminal of each of said first to n-th transistors is connected to said grounding line, and
an emitter terminal of the first transistor within said first to n-th transistors is connected to said power supply line while a base terminal of the n-th transistor within said first to n-th transistors is connected to said grounding line.

US Pat. No. 10,193,336

ESD PROTECTION CIRCUIT, DIFFERENTIAL TRANSMISSION LINE, COMMON MODE FILTER CIRCUIT, ESD PROTECTION DEVICE, AND COMPOSITE DEVICE

MURATA MANUFACTURING CO.,...

1. An ESD protection circuit comprising:a first terminal and a second terminal defining a first balanced port;
a third terminal and a fourth terminal defining a second balanced port;
a first ESD protection circuit that includes a first Zener diode and is connected between a ground and a first node between the first terminal and the third terminal;
a second ESD protection circuit that includes a second Zener diode, is connected between the ground and a second node between the second terminal and the fourth terminal, and is symmetric with respect to the first ESD protection circuit;
a first coil provided in series between the first terminal and the first node;
a third coil that is cumulatively connected to the first coil and is provided in series between the third terminal and the first node;
a second coil provided in series between the second terminal and the second node; and
a fourth coil that is cumulatively connected to the second coil and is provided in series between the fourth terminal and the second node.

US Pat. No. 10,193,327

SAFETY CONTROL METHOD AND DEVICE FOR SYSTEM WITH PRECHARGING CIRCUIT, AND SYSTEM THEREOF

SCHNEIDER TOSHIBA INVERTE...

1. A safety control method for a system including a precharging circuit, the control method comprising:detecting if a number of times that the precharging circuit has reached an undervoltage condition reaches a threshold number of times;
calculating a duration between the precharging circuit reaching the undervoltage condition for a first time and the precharging circuit reaching the undervoltage condition for the threshold number of times;
issuing an error alarm and stopping operation of the system when the number of times reaches the threshold number of times and the duration is less than or equal to a threshold period of time.

US Pat. No. 10,193,326

NON-INTRUSIVE SHORT-CIRCUIT PROTECTION FOR POWER SUPPLY DEVICES

Continental Automotive Sy...

1. A method of protecting a power source, having an output voltage, from a short circuit, the method comprising:providing to a first input of a voltage comparator, a power source voltage minus a voltage drop across a first, forward-biased, non-ideal diode carrying electric current from the power source to a load;
providing to a second input of the voltage comparator, the power source voltage minus a voltage drop across a second, forward-biased, non-ideal diode, which is also coupled to the power source and which carries a reference current, to a second input of the voltage comparator; and
providing a control voltage signal, which is output from the voltage comparator, to a switching device located between the power source and the first forward-biased non-ideal diode, the control voltage signal and switching device being selected and configured to disconnect the power source when a power supply voltage drop across the first forward-biased, non-ideal diode exceeds a predetermined threshold relative to a power supply voltage drop across the second forward-biased, non-ideal diode.

US Pat. No. 10,193,317

ELECTRICAL SYSTEM AND SWITCHING ASSEMBLY THEREFOR

EATON INTELLIGENT POWER L...

1. A switching assembly comprising: an enclosure member; a backpan coupled to said enclosure member; an electrical switching apparatus coupled to said enclosure member; an electrical receptacle electrically connected to said electrical switching apparatus; and a bussing assembly comprising a number of stabs, said electrical switching apparatus being coupled to at least one of said number of stabs by a plug-on connection-; and a first door member and a second door member each pivotably connected to said enclosure member, said first door member overlaying said electrical switching apparatus in order to provide access thereto, said second door member overlaying said electrical receptacle in order to provide access thereto, said first door member having a first center point structured to open in a first plane, said second door member having a second center point structured to open in a second plane substantially coplanar with the first plane, wherein said enclosure member, said backpan, said electrical switching apparatus, and said electrical receptacle are structured so as to form a self-contained sub-assembly; wherein said backpan comprises a mounting surface disposed in a third plane; wherein said electrical receptacle comprises an interface surface disposed in a fourth plane; and wherein the fourth plane is disposed at an angle of between 30 degrees and 60 degrees with respect to the third plane.

US Pat. No. 10,193,315

CORRUGATED TUBE ASSEMBLY FOR RECEIVING LINES, AND METHOD FOR PRODUCING SUCH A CORRUGATED TUBE ASSEMBLY

1. A corrugated tube assembly for receiving lines, wiring harnesses or the like, comprising an inner and an outer respectively flexible corrugated tube made from plastic with circumferential corrugations and within each case one longitudinal slot, it being possible for the outer corrugated tube to be plugged onto the inner corrugated tube with mutual radial engagement of the corrugations of the two corrugated tubes, a longitudinal bar which is configured on the inner corrugated tube protruding radially into the longitudinal slot of the outer corrugated tube in a plugged-on state and covering said longitudinal slot, which longitudinal bar is provided with corrugations of identical shape and pitch to those on the outer corrugated tube, and an external diameter of which corresponds to that of the corrugations on the outer corrugated tube, characterized in that radial end cross sections of all corrugations are completely closed by way of coverings that are formed integrally with the corrugations on a first and a second side edge of the longitudinal slot of the outer corrugated tube and a third and a fourth side edge of the longitudinal bar on the inner corrugated tube and a fifth and a sixth side edge on longitudinal sides of a remaining cross section of the inner corrugated tube which runs on both sides of said longitudinal bar, the longitudinal bar of the inner corrugated tube is connected on both longitudinal sides to the remaining cross section of the inner corrugated tube in each case via a depression which is V-shaped as seen in a radial cross section and runs radially as far as an internal diameter of the corrugations of the inner corrugated tube, each V-shaped depression being defined between the third and the fifth edge and the fourth and the sixth edge, respectively, and in that, in a plugged-together state of the two corrugated tubes, each side edge of the longitudinal slot of the outer corrugated tube protrudes into each V-shaped depression on a respective facing longitudinal side of the longitudinal bar of the inner corrugated tube.

US Pat. No. 10,193,311

SPARK PLUG

NGK SPARK PLUG CO., LTD.,...

1. A spark plug comprising:an insulator comprising an alumina-based sintered body containing an alumina crystal, wherein
the alumina-based sintered body includes 92 mass % to 96 mass % of Al in terms of an oxide, and at least three elements selected from Group II elements in the periodic table based on IUPAC Recommendations 1990, one of the at least three elements being 1.90 mass % or more of Ba in terms of an oxide,
the alumina-based sintered body includes the following phases in a grain boundary phase present between grains of the alumina crystal;
a first crystal phase containing Si and at least one of the Group II elements, and
a second crystal phase containing Al and at least one of the Group II elements, with the proviso that a crystal phase containing Si and a crystal phase containing Mg as a sole Group II element are excluded from the second crystal phase, and
in an X-ray diffraction of the alumina-based sintered body, the maximum relative intensity of the first crystal phase and the maximum relative intensity of the second crystal phase are both 2 or above relative to the maximum diffraction intensity of the alumina crystal.

US Pat. No. 10,193,294

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a base member;
a laser element mounted on or above the base member;
a retaining member having a light reflective inner wall defining a through hole, the retaining member having a first surface on a laser element side and a second surface not on the laser element side;
a fluorescent member fixed to the through hole and disposed on an optical path of laser light emitted by the laser element; and
a first fixing member and a second fixing member clamping the retaining member, the first fixing member having a first contact surface in contact with the first surface of the retaining member, the second fixing member having a second contact surface in contact with the second surface of the retaining member, the first contact surface and the second contact surface being disposed in such a manner that a distance between the first contact surface and the second contact surface becomes smaller as the first contact surface and the second contact surface become farther from the through hole,
wherein the retaining member, the first fixing member and the second fixing member are arranged in such a manner that a space surrounded by the retaining member, the first fixing member, and the second fixing member exists around the retaining member.

US Pat. No. 10,193,283

BUSWAY STAB ASSEMBLIES AND RELATED SYSTEMS AND METHODS

Eaton Intelligent Power L...

1. A plug-in device for use with a busway system comprising a busway housing defining a longitudinal axis, the plug-in device comprising:a stab base housing having first and second opposite sides;
one or more stab conductors extending out of and away from the stab base housing at the first side of the stab base housing;
one or more stab conductors extending out of and away from the stab base housing at the second side of the stab base housing; and
a ground conductor at an upper portion of the stab base housing;
wherein the stab base housing is configured to be received through an opening at a bottom portion of the busway housing and positioned in a first position with each stab conductor extending away from the stab base housing in a direction substantially parallel to the longitudinal axis of the busway housing and with the ground conductor contacting a top wall of the busway housing;
wherein the stab base housing is configured to be rotated from the first position to a second position with each stab conductor extending away from the stab base housing in a direction substantially perpendicular to the longitudinal axis of the busway housing and with the ground conductor contacting the top wall of the busway housing;
wherein:
an enclosure is coupled to a lower portion of the stab base housing;
a cable extends from each stab conductor and from the ground conductor to outside the stab base housing at the lower portion thereof; and
each cable is electrically connected to one or more components in the enclosure.

US Pat. No. 10,193,281

ELECTRICAL CONNECTOR ASSEMBLY HAVING A SHIELD ASSEMBLY

TE CONNECTIVITY CORPORATI...

1. A connector assembly for terminating a cable having a cable shield that is electrically conductive, the connector assembly comprising:a backshell that is electrically conductive comprising a body that extends from a mating end to a cable end along a mating axis of the connector assembly, the backshell configured to provide shielding for an electrical connector configured to be received in the backshell at the mating end, the cable end comprising a cable channel that extends through the body and is configured to hold an end segment of the cable therein;
a shield assembly comprising a clamp system, wherein the clamp system is electrically conductive and held within the cable end of the body of the backshell, the clamp system comprising a front clamping member and a rear clamping member, the cable shield of the cable configured to terminate to the front clamping member and to the rear clamping member of the clamp system between the front clamping member and the rear clamping member; and
an electromagnetic interference (EMI) gasket, wherein the EMI gasket is electrically coupled to the backshell and held within the cable end of the body of the backshell, the EMI gasket comprising a backshell interface and a clamp interface, wherein the backshell interface is configured to engage the backshell and the clamp interface is configured to engage an exterior surface of at least one of the front clamping member or the rear clamping member of the clamp system.

US Pat. No. 10,193,278

EXCHANGEABLE MODULE FOR A COMPUTER SYSTEM AS WELL AS COMPUTER SYSTEM

FUJITSU LIMITED, Kawasak...

1. Exchangeable module for a computer system, comprising:a module body, which can be secured at a predetermined installation position inside the computer system,
a cable connection leading to the outside from the module body, at the end of which connection is arranged a plug connector, so that the module can be electrically coupled with another component of the computer system, and
a safety device, by means of which the plug connector is mechanically connected to the module body,
wherein the safety device is configured such that when a pulling force is applied to the module body, the cable connection is not subject to the pulling force.

US Pat. No. 10,193,263

CONNECTOR

YAZAKI CORPORATION, Toky...

1. A connector comprising:a housing provided with a terminal chamber;
a terminal including a terminal-connecting portion and a wire-connecting portion, the terminal-connecting portion accommodated in the terminal chamber and configured to connect with an opponent terminal, the wire-connecting portion configured to connect with an end of an electric wire drawn out from the housing to an outside of the housing;
a locking lance flexibly provided in the terminal chamber, the locking lance including a locking portion on a free end side of the locking lance, the locking portion configured to lock the terminal-connecting portion;
a plate portion provided in the terminal-connecting portion, and arranged facing the locking lance;
a hole portion formed in the plate portion, configured to receive the locking portion thereinto;
an engagement surface provided at an edge of the hole portion facing against an insertion direction of the terminal to the terminal chamber, the engagement surface configured to be engaged with the locking portion in a detachment direction of the terminal from the terminal chamber;
a pair of chamfered portions provided at edges of the hole portion on both sides of the engagement surface, the chamfered portions inclined toward an inside of the hole portion; and
a pair of supplemental engagement surfaces provided at parts of the engagement surface where the pair of chamfered portions is located, the supplemental engagement surfaces configured to be engaged with the locking portion in the detachment direction of the terminal from the terminal chamber.

US Pat. No. 10,193,260

MULTI-CONTACT CONNECTOR

IRISO ELECTRONICS CO., LT...

1. A multi-contact connector comprising: terminals each includinga first contact piece section having a first contact section that achieves pressing contact with a connection target object in a first direction and a first elastic arm that extends in a direction that intersects the first direction and displaceably supports the first contact section, and
a second contact piece section having a second contact section that achieves pressing contact with the connection target object in the first direction and a second elastic arm that displaceably supports the second contact section,
wherein the second elastic arm extends in the first direction toward the first elastic arm and has a front end portion facing the first elastic arm and is formed as a spring piece linked to the second contact section.

US Pat. No. 10,193,259

RECEPTACLE CONNECTOR HOUSING WITH HOLD-DOWN RIBS

TE CONNECTIVITY CORPORATI...

1. A receptacle connector comprising:a housing including a mating end and a cable end and defining a cavity therebetween, the housing including a top wall, a bottom wall, and first and second side walls that extend between and connect the top wall and the bottom wall, the housing including a first hold-down rib in a first corner region of the cavity defined by the top wall and the first side wall, and a second hold-down rib in a second corner region of the cavity defined by the top wall and the second side wall, the first hold-down rib extending from the first side wall, the second hold-down rib extending from the second side wall; and
a terminal held in the cavity of the housing, the terminal having a contact segment that includes a floor and first and second rolled walls that extend from the floor, the floor engaging the bottom wall of the housing, the contact segment defining a receptacle configured to receive a mating tab contact therein through the mating end of the housing,
wherein the first hold-down rib extends over the terminal and is configured to engage an outer surface of the first rolled wall of the terminal and the second hold-down rib extends over the terminal and is configured to engage an outer surface of the second rolled wall of the terminal such that the terminal is held vertically between the bottom wall of the housing and the first and second hold-down ribs of the housing to limit vertical float of the terminal within the cavity.

US Pat. No. 10,193,255

PLUG CONNECTOR AND CONNECTOR SET

PANASONIC INTELLECTUAL PR...

1. A plug connector to be fitted in an opening of a receptacle connector,the plug connector comprising:
a plug housing having a lower exterior surface; and
a plurality of plug terminals stored in the plug housing,
the receptacle connector having a receptacle terminal,
the plug connector being connected to a cable having a sheet shape and including a cable terminal, so that electrical connection is established between the receptacle terminal and the cable terminal, wherein
each of the plug terminals has a contact section and a connection section, the connection section extending toward the lower exterior surface of the plug housing,
the contact section is contactable with the receptacle terminal,
the connection section is connectable to the cable terminal,
the connection section is disposed such that the connection section is exposed from the plug housing in a state in which the plug connector is fitted in the receptacle connector,
the plug housing has a recessed section provided on the lower exterior surface of the plug housing,
the recessed section is configured to store a coupling region of the cable on which the cable terminal is formed, and
when the plug connector is inserted into the opening of the receptacle connector, the coupling region of the cable is sandwiched between the recessed section of the plug connector and an inner surface of the receptacle connector defining the opening.

US Pat. No. 10,193,241

FIXING STRUCTURE AND FIXING METHOD

Japan Aviation Electronic...

1. A fixing method for fixing a terminal to an object to be fixed with a solder disposed therebetween, the fixing method comprising:a first step of disposing the solder on the object to be fixed;
a second step of bringing the terminal into contact with the solder; and
a third step of forming a penetrating hole in the terminal by irradiating a laser beam onto the terminal,
wherein in the third step, the laser beam is irradiated onto the terminal in such a manner that the solder melted by the irradiation of the laser beam passes through the penetrating hole and reaches the vicinity of an upper end of the penetrating hole, and
wherein in the third step, the laser beam is irradiated onto the terminal while the terminal is pressed against the solder by an external force or a weight of a connector including the terminal.

US Pat. No. 10,193,238

DIPOLE ANTENNA ELEMENT WITH OPEN-END TRACES

CommScope Technologies LL...

1. A base station antenna, comprising:an array of low-band radiating elements that are configured to operate in a first frequency band; and
an array of high-band radiating elements that are configured to operate in a second frequency band that encompasses frequencies that are higher than frequencies of the first frequency band,
wherein a first of the low-band radiating elements comprises a first printed circuit board feed stalk that includes:
a feed line that includes a balun; and
an open-ended trace that is electrically connected to a ground plane and that is configured to reduce the flow of radio frequency energy in the second frequency band on the first printed circuit board feed stalk,
wherein the open-ended trace has a length that is a quarter wavelength of a wavelength corresponding to the second frequency band.

US Pat. No. 10,193,223

MODULAR PARALLEL BEAMFORMING SYSTEM AND ASSOCIATED METHODS

General Electric Company,...

1. A beamforming system, comprising:a plurality of modular beamformers operatively coupled to each other, each modular beamformer comprising:
a plurality of signal generation units, each being configured to generate a respective signal;
a plurality of respective delaying units, each corresponding to a respective signal generation unit, each delaying unit being configured to receive a respective signal from the respective signal generating unit, each delaying unit being configured to adaptively delay the respective signal and each delaying unit being configured to output a respective delayed signal;
a plurality of multipliers assigned to each of the delaying units, each multiplier being configured to receive the respective delayed signal output from the respective delaying unit, each multiplier being configured to generate a respective conditioned signal by adaptively applying a respective weight to the respective received delayed signal from the respective delaying unit and each multiplier being configured to output the respective conditioned signal; and
a plurality of summers, each configured to receive a respective group of conditioned signals from a respective group of the plurality of multipliers, being configured to combine the respective group of conditioned signals and being configured to generate a respective phased array output signal, each of the plurality of summers being configured to receive at least another input other than the respective group of conditioned signals; and
the plurality of modular beamformers being interconnected such that each of the plurality of summers within each beamformer receives, as the at least another input, a respective phased array output signal from a summer of a different one of the plurality of modular beamformers.

US Pat. No. 10,193,216

ELECTRONIC DEVICE WITH COMPONENT TRIM ANTENNA

Apple Inc., Cupertino, C...

1. An electronic device comprising:a housing having a camera window;
a camera aligned with the camera window;
an antenna resonating element that extends at least partially along a periphery of the camera window; and
radio-frequency transceiver circuitry coupled to the antenna resonating element.

US Pat. No. 10,193,211

SMARTCARDS, RFID DEVICES, WEARABLES AND METHODS

1. An RFID device comprising:an RFID chip (IC);
a module antenna (MA) connected to the RFID chip (IC);
a coupling frame (CF) having a slit (S) or non-conductive stripe (NCS) overlapping at least a portion of the module antenna (MA); and
a capacitor connected across the slit (S) or non-conductive stripe (NCS).

US Pat. No. 10,193,208

WIRELESS DISTRIBUTION USING CABINETS, PEDESTALS, AND HAND HOLES

CenturyLink Intellectual ...

1. A method, comprising:placing one or more first lines in a first channel in a first ground surface;
placing a capping material in the first channel;
placing a container in a second ground surface;
placing one or more second lines in a second channel in a third ground surface, the second channel connecting the container and the first channel;
providing an antenna within a signal distribution device, the signal distribution device comprising the container, a top portion of the container being substantially level with a top portion of the second ground surface, and a pedestal disposed above the top portion of the container, the antenna being disposed within the pedestal; and
communicatively coupling the antenna to at least one of the one or more second lines and to at least one of the one or more first lines.

US Pat. No. 10,193,194

BATTERY ASSEMBLY CONTROLLER WHICH MONITORS VOLTAGES OF SECONDARY BATTERIES

PANASONIC INTELLECTUAL PR...

1. A battery assembly controller controlling terminal voltages of a plurality of series-connected secondary batteries to be equal, the controller comprising:a discharge circuit selectively reducing the terminal voltages of the secondary batteries; and
a monitoring circuit directly connected to positive and negative electrodes of the secondary batteries to monitor the terminal voltages of the secondary batteries, wherein
the discharge circuit includes:
a plurality of switches, each being connected to positive and negative electrodes of associated one of the secondary batteries, and
a control circuit controlling not to turn on odd-numbered and even-numbered switches simultaneously, where the switches are sequentially numbered as 1, 2, 3, . . . , from a high-potential side,
each of the switches is a MOS transistor, and
the discharge circuit further includes:
a plurality of resistors, each being connected between a gate and a source of one of the MOS transistors,
a plurality of current supplies, and
a plurality of other switches, each being connected between the gate of one of the MOS transistors and associated one of the current supplies.

US Pat. No. 10,193,164

FLOW FIELDS FOR ELECTROCHEMICAL CELL

Hydrogenics Corporation, ...

1. A set of flow field plates for an electrochemical cell comprising,a first flow field plate having a flow field wherein 50% or more of the area of the flow field of the first flow field plate is defined by a plurality of elongate ridges, and
a second flow field plate having a flow field wherein 50% or more of the area of the flow field of the second flow filed plate is defined by a plurality of discontinuous lines of short ridges, wherein the short ridges are less than 10 times as long as an average gap between successive elongate ridges, the gap measured perpendicular to the elongate ridges.

US Pat. No. 10,193,163

FUEL CELL

NGK INSULATORS, LTD., Na...

1. A fuel cell comprising:an anode,
a cathode containing a perovskite oxide as a main component, the perovskite oxide expressed by the general formula ABO3, the A site including at least one selected from the group consisting of La and Sr, and the B site including at least one selected from the group consisting of Fe, Co, Mn and Ni, and
a solid electrolyte layer disposed between the anode and the cathode, wherein:
the cathode includes a surface region which is within 5 micrometers from a surface opposite the solid electrolyte layer,
the surface region contains a main phase comprising the perovskite oxide and a secondary phase comprising strontium oxide,
an occupied surface area ratio of the strontium oxide in a cross section of the surface region is greater than or equal to 0.05% and less than or equal to 3%, the cross section of the surface region being parallel to a thickness direction of the cathode, and
an average equivalent circle diameter of the strontium oxide in the cross section of the surface region is greater than or equal to 10 nm and less than or equal to 500 nm.

US Pat. No. 10,193,154

CATHODE COMPOSITION FOR PRIMARY BATTERY

Medtronic, Inc., Minneap...

1. A primary battery configured to supply operation power to an implantable medical device, the primary battery comprising:a cathode comprising an active material and at least one of a metal oxide or a metal fluoride, wherein the active material exhibits a first discharge capacity and the at least one of the metal oxide or the metal fluoride exhibits a second discharge capacity at a voltage lower than the first discharge capacity;
a current collector, wherein the cathode comprises a cathode layer on the current collector, wherein the cathode layer is formed of a mixture of the active material and the at least one of the metal oxide or the metal fluoride;
an anode comprising a metal as an electron source; and
an electrolyte between the cathode and anode, wherein the metal reacts with the electrolyte below a third discharge capacity at a voltage lower than the second discharge capacity to form a gas,
wherein the metal reacts with the active material at the first discharge capacity to consume the active material, and, following the consumption of the active material of the cathode, the metal reacts with the at least one of the metal oxide or the metal fluoride of the cathode prior to reacting with the electrolyte below the third discharge capacity, and
wherein the cathode includes an amount of the active material and the at least one of the metal oxide or the metal fluoride, and the anode includes an amount of metal such that an excess portion of the metal and an amount of the at least one of the metal oxide or the metal fluoride remains following the consumption of the active material, and wherein the amount of the at least one of the metal oxide or the metal fluoride is proportioned to consume all of the excess portion of the metal.

US Pat. No. 10,193,128

SWITCHING DEVICE FOR A BATTERY, AND BATTERY COMPRISING SAID SWITCHING DEVICE

Robert Bosch GmbH, Stutt...

1. A switching device (1) for a battery (2), wherein the switching device (1) is configured to be operated by an acoustic resonance effect in order to interrupt an electrical line of the battery (2) to a device located outside of the battery, wherein the switching device (1) has at least one container (12) which is prestressed by a spring element (11) and is configured to be destroyed by acoustic resonance.

US Pat. No. 10,193,120

METHOD FOR FORMING ADHESION LAYER FOR SECONDARY BATTERY

LG CHEM, LTD., Seoul (KR...

1. A method for forming an adhesion layer, comprising:preparing a mask having openings which are open vertically;
etching a photosensitive film through the mask to form grooves corresponding to the openings of the mask in the photosensitive film;
pouring polydimethylsiloxane onto the photosensitive film having the grooves, curing the polydimethylsiloxane, and separating the cured polydimethylsiloxane from the photosensitive film to manufacture a polydimethylsiloxane mold having a concavo-convex part;
coating a polymer binder slurry on the polydimethylsiloxane mold having the concavo-convex part; and
transferring only the polymer binder slurry directly from the polydimethylsiloxane mold onto a surface of a separator or an electrode of a secondary battery to form an adhesion layer having a cavity part on the surface of the separator or the electrode, the cavity part being open vertically.

US Pat. No. 10,193,118

HYDROXIDE-ION-CONDUCTIVE DENSE MEMBRANE AND COMPOSITE MATERIAL

NGK Insulators, Ltd., Na...

1. A separator for a zinc secondary battery comprising a composite material including a porous alumina substrate and a hydroxide-ion-conductive dense membrane disposed on at least one surface of the porous alumina substrate, the hydroxide-ion-conductive dense membrane consisting of a layered double hydroxide dense membrane and having a He permeability per unit area of 10 cm/min·atm or less,wherein the porous alumina substrate has a water-permeable structure and an average pore size of 0.001 ?m to 1.5 ?m, and
wherein the layered double hydroxide dense membrane is formed from a stock solution containing at least two cations that are different from one another.

US Pat. No. 10,193,116

CERAMIC COATING ON BATTERY SEPARATORS

Applied Materials, Inc., ...

1. A method, comprising:preparing a separator for an electrochemical storage device; and
using a controlled process to coat the separator with a ceramic layer having a desired thickness, wherein the controlled process comprises:
coating the separator with a first layer of ceramic particles having a first charge;
coating the first layer with a second layer of ceramic particles having a second charge opposite the first charge;
repeating the coating steps until a ceramic coating having the desired thickness is obtained.

US Pat. No. 10,193,115

BATTERY COVER

East Penn Manufacturing C...

1. A battery cover, comprising:a lower battery cover, and
an upper battery cover matable with the lower battery cover to form a labyrinth and a plurality of battery cover sides including a terminal side and an opposite side, the labyrinth defined by a plurality of walls formed by the lower battery cover and the upper battery cover and having
a plurality of labyrinth cell passageways each extending only between one of a plurality of cell openings and one of a plurality of mixing areas positioned on the terminal side,
a plurality of exhaust passageways extending along an entirety of the opposite side of the upper battery cover, and
a channel disposed between the plurality of mixing areas and the plurality of exhaust passageways, the channel connecting the plurality of mixing areas to the plurality of exhaust passageways by extending from a lower end of each of the plurality of mixing areas at the terminal side and splitting into the plurality of exhaust passageways, the plurality of labyrinth cell passageways each extending to a position directly adjacent one of the plurality of exhaust passageways at the opposite side before leading to the one of the plurality of mixing areas at the terminal side, each of the plurality of labyrinth cell passageways is separated only by one of the plurality of walls from one of the plurality of exhaust passageways at the position directly adjacent one of the plurality of exhaust passageways.

US Pat. No. 10,193,110

ELECTROCHEMICAL DEVICE, SUCH AS A MICROBATTERY OR AN ELECTROCHROMIC SYSTEM, COVERED BY AN ENCAPSULATION LAYER COMPRISING A BARRIER FILM AND AN ADHESIVE FILM, AND METHOD FOR FABRICATING ONE SUCH DEVICE

1. An electrochemical device comprising(1) a substrate,
(2) at least one stack of active layers containing lithium, said stack comprising
(2a) at least a first electrode connected to a first current collector and
(2b) at least a second electrode connected to a second current collector,
said stack being arranged on the substrate
(3) an encapsulation layer covering said at least one stack, the encapsulation layer comprising at least:
(3a) a barrier film presenting at least one electrically insulating surface and comprising at least one layer hermetic to oxidising species,
(3b) an adhesive film, provided with a first surface and a second surface,
the first surface being in contact with the electrically insulating surface of the barrier film and
the second surface covering a stack of active layers and a part of the substrate,
wherein the adhesive film comprises a juxtaposition of electrically conducting adhesive strips and of electrically insulating adhesive strips,
wherein two electrically conducting strips are separated by an electrically insulating strip to be electrically insulated from one another,
each electrically conducting strip being connected to the first current collector or to the second current collector of the stack of active layers.

US Pat. No. 10,193,108

SECONDARY BATTERY, ELECTRONIC DEVICE, AND VEHICLE

Semiconductor Energy Labo...

1. A secondary battery comprising:a film comprising flat portions and curved portions,
wherein the flat portions and the curved portions are alternately provided each other,
wherein a thickness of a top portion of each of the curved portions is thicker than a thickness of the flat portions.

US Pat. No. 10,193,105

ULTRAVIOLET IRRADIATION DEVICE FOR PACKAGE OF LIGHT-EMITTING DIODE

WUHAN CHINA STAR OPTOELEC...

1. An ultraviolet irradiation device for package of a light-emitting diode, wherein the ultraviolet irradiation device comprises:a sealed shell, wherein the light-emitting diode to he packaged is arranged in the shell, and a UV mask that is movable in the shell is arranged below the light-emitting diode;
a UV lamp, which is arranged below the UV mask; and
to a sealed chamber which is in communication with the shell, wherein the chamber is arranged at a side of the shell, wherein a first rolling unit configured to deliver the light-emitting diode is arranged in the chamber, and a first gate and a second gate are respectively arranged at two ends of the chamber, and wherein the chamber is further in communication with an air exhaust unit and a first gas source respectively.

US Pat. No. 10,193,102

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a substrate;
a plurality of pixels above the substrate, each of the pixels including a light emitting element;
a display region including the plurality of pixels;
a thin film transistor which each of the plurality of pixels includes;
a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element;
a sealing film including a second inorganic insulating material and covering the light emitting element; and
at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film,
wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.

US Pat. No. 10,193,100

ARRAY SUBSTRATE, FABRICATING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising: a thin film transistor, an auxiliary electrode, and a transparent cathode which is electrically connected with the auxiliary electrode, wherein both the auxiliary electrode and an active layer of the thin film transistor are directly arranged on a gate insulating layer of the thin film transistor, the active layer comprises an oxide semiconductor, and the auxiliary electrode is an electric conductor comprising a modified oxide semiconductor,wherein the array substrate further comprises a first etch-stopping layer which is arranged on the auxiliary electrode, and a passivation layer which is arranged on the gate insulating layer and covers the first etch-stopping layer,
wherein a via hole is arranged in the passivation layer, a via hole is arranged in the first etch-stopping layer, and the transparent cathode is electrically connected with the auxiliary electrode through the via hole in the first etch-stopping layer and the via hole in the passivation layer.

US Pat. No. 10,193,088

PEROVSKITE NANOCRYSTALLINE PARTICLES AND OPTOELECTRONIC DEVICE USING SAME

POSTECH ACADEMY-INDUSTRY ...

1. A perovskite nanocrystal particle capable of being dispersible in an organic solvent and comprising a perovskite nanocrystal structure,wherein the perovskite nanocrystal particle is an organic-inorganic-hybrid perovskite or an inorganic metal halide perovskite, and
the perovskite nanocrystal particle has a diameter greater than a Bohr exciton diameter on an area that is not affected by a quantum confinement effect.

US Pat. No. 10,193,079

MATERIALS FOR ELECTRONIC DEVICES

Merck Patent GmbH, (DE)

1. A compound of the formula (I)
or a compound containing exactly two or three units of the formula (I) joined to one another via a single bond or an L group,
where:
L is any divalent or trivalent organic group;
A is a group of the formula (A)

bonded via the dotted bond;
Ar1 is the same or different at each instance and is an aromatic or heteroaromatic ring system which has 5 to 30 aromatic ring atoms and may be substituted by one or more R1 radicals;
Y is the same or different at each instance and is a single bond, BR1, C(R1)2, Si(R1)2, NR1, PR1, P(?O)R1, O, S, S?O or S(?O)2;
B is the same or different at each instance and is selected from H, a straight-chain alkyl group having 1 to 10 C atoms or a branched or cyclic alkyl group having 3 to 10 C atoms, each of which may be substituted by one or more R1 radicals, or an aryl group having 6 to 14 aromatic ring atoms, each of which may be substituted by one or more R1 radicals;
RA is the same or different at each instance and is CF3, CN, and an E group, which is an aryl or heteroaryl group which has 6 to 14 aromatic ring atoms and may be substituted by one or more R1 radicals, and which contains one or more V groups as constituents of the aromatic ring, where the V groups are the same or different at each instance and are selected from ?N—, ?C(F)—, ?C(CN)— and ?C(CF3)—, and where the heteroaryl group is not bonded via a nitrogen atom;
RB is selected from H, a straight-chain alkyl group having 1 to 10 carbon atoms or a branched or cyclic alkyl group having 3 to 10 carbon atoms, each of which may be substituted by one or more R1 radicals, and an aryl group having 6 to 14 aromatic ring atoms, which may be substituted by one or more R1 radicals;
R1 is the same or different at each instance and is H, D, F, C(?O)R2, CN, Si(R2)3, N(R2)2, P(?O)(R2)2, OR2, S(?O)R2, S(?O)2R2, a straight-chain alkyl or alkoxy group having 1 to 20 carbon atoms or a branched or cyclic alkyl or alkoxy group having 3 to 20 carbon atoms, where the abovementioned groups may each be substituted by one or more R2 radicals and where one or more CH2 groups in the abovementioned groups may be replaced by —R2C?CR2—, —C?C—,Si(R2)2, C?O, C?NR2, —C(?O)O—, —C(?O)NR2—, NR2, P(?O)(R2), —O—, —S—, SO or SO2, or an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, each of which may be substituted by one or more R2 radicals, where two or more R1 radicals may be joined to one another and may form a ring;
R2 is the same or different at each instance and is H, D, F or an aliphatic, aromatic or heteroaromatic organic radical having 1 to 20 carbon atoms, in which one or more hydrogen atoms may also be replaced by D or F; at the same time, two or more R2 substituents may be joined to one another and may form a ring.

US Pat. No. 10,193,078

ORGANIC LIGHT-EMITTING DEVICE

Samsung Display Co., Ltd....

1. An organic light-emitting device, comprising:a first electrode;
a second electrode; and
an organic layer between the first electrode and the second electrode,
wherein the organic layer includes at least one first material and at least one second material, the first material being represented by Formula 1 and the second material being represented by Formula 2,

wherein, in Formulae 1 and 2,
L11 is selected from a substituted or unsubstituted C6-C60 arylene group, a substituted or unsubstituted C1-C60 heteroarylene group, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group;
L21 and L22 are each independently selected from a methylene group, an ethylene group, a propylene group, a butylene group, a phenylene group, a naphthylene group, a phenanthrenylene group, an anthracenylene group, a triphenylenylene group, a pyrenylene group, a chrysenylene group, a pyrrolylene group, a thiophenylene group, a furanylene group, an imidazolylene group, an indolylene group, a quinolinylene group, an isoquinolinylene group, a benzoquinolinylene group, a phenanthridinylene group, an acridinylene group, a phenanthrolinylene group, a benzofuranylene group, a benzothiophenylene group, a triazolylene group, a tetrazolylene group, a dibenzofuranylene group, and a dibenzothiophenylene group; and
a methylene group, an ethylene group, a propylene group, a butylene group, a phenylene group, a naphthylene group, a phenanthrenylene group, an anthracenylene group, a triphenylenylene group, a pyrenylene group, a chrysenylene group, a pyrrolylene group, a thiophenylene group, a furanylene group, an imidazolylene group, an indolylene group, a quinolinylene group, an isoquinolinylene group, a benzoquinolinylene group, a phenanthridinylene group, an acridinylene group, a phenanthrolinylene group, a benzofuranylene group, a benzothiophenylene group, a triazolylene group, tetrazolylene group, a dibenzofuranylene group, and a dibenzothiophenylene group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid or a salt thereof, a sulfonic acid or a salt thereof, a phosphoric acid or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a cyclopentyl group, a cyclohexyl group, a cycloheptyl group, a cyclopentenyl group, a cyclohexenyl group, a phenyl group, a pentalenyl group, an indenyl group, a naphthyl group, an azulenyl group, a heptalenyl group, an indacenyl group, acenaphthyl group, a fluorenyl group, a spiro-fluorenyl group, a benzofluorenyl group, a dibenzofluorenyl group, a phenalenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a naphthacenyl group, a picenyl group, a perylenyl group, pentaphenyl group, a hexacenyl group, a pentacenyl group, a rubicenyl group, a coronenyl group, an ovalenyl group, a pyrrolyl group, a thiophenyl group, a furanyl group, an imidazolyl group, a pyrazolyl group, a thiazolyl group, an isothiazolyl group, an oxazolyl group, an isooxazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoimidazolyl group, a benzofuranyl group, a benzothiophenyl group, an isobenzothiazolyl group, a benzooxazolyl group, an isobenzooxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, dibenzofuranyl group, a dibenzothiophenyl group, a benzocarbazolyl group, a dibenzocarbazolyl group, a thiadiazolyl group, and an imidazopyridinyl group;
a11, a21, and a22 are each independently 0 or 1;
R11 and R12 are each independently selected from a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group;
R21 and R22 are each independently selected from a phenyl group, a pentalenyl group, an indenyl group, a naphthyl group, an azulenyl group, a heptalenyl group, an indacenyl group, an acenaphthyl group, a fluorenyl group, a spiro-fluorenyl group, a benzofluorenyl group, a dibenzofluorenyl group, phenalenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a naphthacenyl group, a picenyl group, a perylenyl group, a pentaphenyl group, a hexacenyl group, a pentacenyl group, a rubicenyl group, a coronenyl group, a ovalenyl group, a pyrrolyl group, a thiophenyl group, a furanyl group, an imidazolyl group, a pyrazolyl group, a thiazolyl group, an isoothiazolyl group, a oxazolyl group, an isooxazolyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a carbazolyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzofuranyl group, a benzothiophenyl group, an isobenzothiazolyl group, a benzooxazolyl group, an isobenzooxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a dibenzofuranyl group, a dibenzothiophenyl group, a dibenzosilolyl group, a benzocarbazolyl group, and a dibenzocarbazolyl group; and
a phenyl group, a pentalenyl group, an indenyl group, a naphthyl group, an azulenyl group, a heptalenyl group, an indacenyl group, acenaphthyl group, a fluorenyl group, a spiro-fluorenyl group, a benzofluorenyl group, a dibenzofluorenyl group, a phenalenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a naphthacenyl group, a picenyl group, a perylenyl group, pentaphenyl group, a hexacenyl group, a pentacenyl group, a rubicenyl group, a coronenyl group, an ovalenyl group, a hexacenyl group, a pentacenyl group, a rubicenyl group, a coronenyl group, an ovalenyl group, a pyrrolyl group, a thiophenyl group, a furanyl group, an imidazolyl group, a pyrazolyl group, a thiazolyl group, an isothiazolyl group, an oxazolyl group, an isooxazolyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a carbazolyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzofuranyl group, a benzothiophenyl group, an isobenzothiazolyl group, a benzooxazolyl group, an isobenzooxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, dibenzofuranyl group, a dibenzothiophenyl group, a dibenzosilolyl group, a benzocarbazolyl group, and a dibenzocarbazolyl group, each substituted with at least one selected from a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid or a salt thereof, a sulfonic acid or a salt thereof, a phosphoric acid or a salt thereof, a C20-C20 alkyl group, a C20-C20 alkoxy group, a phenyl group, a pentalenyl group, an indenyl group, a naphthyl group, an azulenyl group, a heptalenyl group, an indacenyl group, acenaphthyl group, a fluorenyl group, a spiro-fluorenyl group, a benzofluorenyl group, a dibenzofluorenyl group, a phenalenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a naphthacenyl group, a picenyl group, a perylenyl group, pentaphenyl group, a hexacenyl group, a pentacenyl group, a rubicenyl group, a coronenyl group, an ovalenyl group, a pyrrolyl group, a thiophenyl group, a furanyl group, an imidazolyl group, a pyrazolyl group, a thiazolyl group, an isothiazolyl group, an oxazolyl group, an isooxazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a carbazolyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoimidazolyl group, a benzofuranyl group, a benzothiophenyl group, an isobenzothiazolyl group, a benzooxazolyl group, an isobenzooxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, dibenzofuranyl group, a dibenzothiophenyl group, a benzocarbazolyl group, and a dibenzocarbazolyl group;
b11 and b12 are each independently selected from 1, 2, and 3;
R13 and R14 are each independently selected from a hydrogen, a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid or a salt thereof, a sulfonic acid or a salt thereof, a phosphoric acid or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, and —Si(Q1)(Q2)(Q3);
b13 and b14 are each independently selected from 1, 2, 3, and 4;
X21 is selected from an oxygen atom, a sulfur atom, and a selenium atom;
Y21 is selected from a moiety represented by one of Formulae 7-1 to 7-7 below:

wherein, in Formula 7-1, E21 is selected from:
a benzene, a naphthalene, a phenanthrene, an anthracene, a triphenylene, a pyrrole, an imidazole, a benzoxazole, a benzothiazole, a benzoimidazole, a pyrazine, an indole, a quinoline, an isoquinoline, a benzoquinoline, a phenanthridine, an acridine, a phenanthroline, a triazole, and a tetrazole; and
a benzene, a naphthalene, a phenanthrene, an anthracene, a triphenylene, a pyrrole, an imidazole, a benzoxazole, a benzothiazole, a benzoimidazole, a pyrazine, an indole, a quinoline, an isoquinoline, a benzoquinoline, a phenanthridine, an acridine, a phenanthroline, a triazole, and a tetrazole, each substituted with at least one selected from a methyl group, a phenyl group, and a naphthyl group;
wherein, in Formulae 7-3 to 7-7, E21 to E25 are each independently selected from:
a benzene, a naphthalene, a phenanthrene, an anthracene, a triphenylene, a pyrrole, an imidazole, a benzoxazole, a benzothiazole, a benzoimidazole, a pyridine, a pyrazine, a pyrimidine, an indole, a quinoline, an isoquinoline, a benzoquinoline, a phenanthridine, an acridine, a phenanthroline, a triazole, a tetrazole, and a triazine; and
a benzene, a naphthalene, a phenanthrene, an anthracene, a triphenylene, a pyrrole, an imidazole, a benzoxazole, a benzothiazole, a benzoimidazole, a pyridine, a pyrazine, a pyrimidine, an indole, a quinoline, an isoquinoline, a benzoquinoline, a phenanthridine, an acridine, a phenanthroline, a triazole, a tetrazole, and a triazine, each substituted with at least one selected from a methyl group, a phenyl group, and a naphthyl group;
wherein, in Formula 7-2,
E21 is selected from:
a benzene, a naphthalene, a phenanthrene, an anthracene, a triphenylene, a pyrrole, an imidazole, a benzoxazole, a benzothiazole, a benzoimidazole, a pyridine, a pyrimidine, an indole, a quinoline, an isoquinoline, a benzoquinoline, a phenanthridine, an acridine, a phenanthroline, a triazole, a tetrazole, and a triazine; and
a benzene, a naphthalene, a phenanthrene, an anthracene, a triphenylene, a pyrrole, an imidazole, a benzoxazole, a benzothiazole, a benzoimidazole, a pyridine, a pyrimidine, an indole, a quinoline, an isoquinoline, a benzoquinoline, a phenanthridine, an acridine, a phenanthroline, a triazole, a tetrazole, and a triazine, each substituted with at least one selected from a methyl group, a phenyl group, and a naphthyl group; and
E22 is selected from:
a benzene, a naphthalene, a phenanthrene, an anthracene, a triphenylene, a pyrrole, an imidazole, a benzoxazole, a benzothiazole, a benzoimidazole, a pyrimidine, an indole, a quinoline, an isoquinoline, a benzoquinoline, a phenanthridine, an acridine, a phenanthroline, a triazole, a tetrazole, and a triazine; and
a benzene, a naphthalene, a phenanthrene, an anthracene, a triphenylene, a pyrrole, an imidazole, a benzoxazole, a benzothiazole, a benzoimidazole, a pyrimidine, an indole, a quinoline, an isoquinoline, a benzoquinoline, a phenanthridine, an acridine, a phenanthroline, a triazole, a tetrazole, and a triazine, each substituted with at least one selected from a methyl group, a phenyl group, and a naphthyl group;
n21 is 1; and
at least one substituent of the substituted C6-C60 arylene group, the substituted C1-C60 heteroarylene group, the substituted divalent non-aromatic condensed polycyclic group, the substituted divalent non-aromatic condensed heteropolycyclic group, the substituted C6-C60 aryl group, the substituted C1-C60 heteroaryl group, the substituted monovalent non-aromatic condensed polycyclic group, the substituted monovalent non-aromatic condensed heteropolycyclic group, the substituted C1-C60 alkyl group, the substituted C1-C60 alkoxy group, the substituted C3-C10 cycloalkyl group, the substituted C6-C60 aryloxy group, the substituted C6-C60 aryl ring, and the substituted C1-C60 heteroaryl ring is selected from:
a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, and —Si(Q11)(Q12)(Q13);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group;
a C3-C10 cycloalkyl group, a C2-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one selected from a deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C1-C60 alkenyl group, a C1-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, and —Si(Q21)(Q22)(Q23); and
—Si(Q31)(Q32)(Q33),
Q1 to Q3, Q11 to Q13, Q21 to Q23, and Q31 to Q33 are each independently selected from a C1 -C60 alkyl group, a C6-C60 aryl group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,193,069

POLYMER FOR USE IN ORGANIC ELECTROLUMINESCENT ELEMENT AND ORGANIC ELECTROLUMINESCENT ELEMENT EMPLOYING SAME

1. A polymer for an organic electroluminescent element, comprising a repeating unit represented by the following general formula (1) in repeating units constituting a main chain:
where Z represents one or two or more kinds of repeating units selected from groups derived from indolocarbazoles represented by the following formulae (1a) to (1e), A represents one or two or more kinds of repeating units represented by the following formula (4a) or (4b) and different from Z, l and m each represent an abundance molar ratio, and when a ratio of all repeating units is defined as 100 mol %, l is 10 to 90 mol % and m is 10 to 90 mol %, and n represents an average repetition number and is 5 to 1,000;

in the formulae (1a) to (1e), Ar1's each independently represent a substituted or unsubstituted C6 to C18 arylene group, or a substituted or unsubstituted C3 to C18 heteroarylene group, and R1's each independently represent hydrogen, a C1 to C12 alkyl group, a C1 to C12 alkoxy group, a C6 to C18 aryl group, a C6 to C18 aryloxy group, a C7 to C30 arylalkyl group, a C7 to C30 arylalkyloxy group, a C3 to C18 heteroaryl group, a C3 to C18 heteroaryloxy group, or a C3 to C18 cycloalkyl group;

where Y1 represents a substituted or unsubstituted C1 to C6 alkylene group, O, or S,
Y2 represents a C(R4)2 group, or O,
R3's each independently represent hydrogen, a C1 to C12 alkyl group, a C1 to C12 alkoxy group, a C6 to C18 aryl group, a C6 to C18 aryloxy group, a C7 to C30 arylalkyl group, a C7 to C30 arylalkyloxy group, a C3 to C18 heteroaryl group, a C3 to C18 heteroaryloxy group, or a C3 to C18 cycloalkyl group, and
R4 represents a hydrogen atom, a C1 to C12 alkyl group, a C3 to C18 cycloalkyl group, a C6 to C18 aryl group, a C7 to C30 arylalkyl group, a C3 to C18 heteroaryl group, or a C4 to C30 heteroarylalkyl group.

US Pat. No. 10,193,064

MEMORY CELLS INCLUDING DIELECTRIC MATERIALS, MEMORY DEVICES INCLUDING THE MEMORY CELLS, AND METHODS OF FORMING SAME

Micron Technology, Inc., ...

1. A memory cell, comprising:a threshold switching material comprising amorphous silicon doped with at least one of boron, aluminum, gallium, or phosphorus;
at least one doped dielectric material between the threshold switching material and at least one electrode of a pair of electrodes, the threshold switching material on a side of the at least one doped dielectric material; and
a memory material on a side of one of the electrodes of the pair of electrodes.

US Pat. No. 10,193,057

MAGNETIC MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A magnetic memory device comprising:a stacked structure including a magnetic element; and
a protective insulating film which covers the stacked structure and is formed of a metallic oxide,
wherein:
a metal element contained in the metallic oxide is selected from yttrium (Y), calcium (Ca) and hafnium (Hf), and
a linear coefficient of thermal expansion of the metallic oxide is greater than 5×10?6/K.

US Pat. No. 10,193,056

MINIMAL THICKNESS SYNTHETIC ANTIFERROMAGNETIC (SAF) STRUCTURE WITH PERPENDICULAR MAGNETIC ANISOTROPY FOR STT-MRAM

Headway Technologies, Inc...

1. A synthetic antiferromagnetic free layer structure, comprising:(a) a FL2 layer with intrinsic perpendicular magnetic anisotropy that is comprised of an (A1/A2)n laminate where n is an integer less than 6, A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Mg, Si, V, NiCo, and NiFe, or A1 is Fe and A2 is V, and wherein a magnetization direction thereof is perpendicular-to-plane of the FL2 layer;
(b) a CoFeB layer with perpendicular magnetic anisotropy in which a magnetization direction in said CoFeB layer is perpendicular-to-plane of the CoFeB layer and is established by antiferromagnetic coupling with the FL2 layer through an antiferromagnetic coupling layer formed between the FL2 layer and CoFeB layer; and
(c) the antiferromagnetic coupling layer that is made of a non-magnetic material to give an FL2 layer/antiferromagnetic coupling/CoFeB configuration or a CoFeB/antiferromagnetic coupling/FL2 layer configuration in a magnetic tunnel junction.

US Pat. No. 10,193,045

LIGHT EMITTING DEVICE HAVING HEAT DISIPATION TERMINAL ARRANGED ON SUBSTRATE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate having a first main surface, a second main surface that is opposite from the first main surface, and a mounting surface that is adjacent to at least the second main surface, the substrate including an insulating base material and a pair of connection terminals;
a plurality of light emitting elements mounted on the first main surface of the substrate;
a sealing member that is in contact with at least a part of a side surface of each of the light emitting elements, is formed substantially in the same plane as the substrate on the mounting surface, and a width of the sealing member between adjacent ones of the light emitting elements is larger than a width of the sealing member on an outside of an outermost one of the light emitting elements;
a light transmissive member that covers upper surfaces of the light emitting elements and a part of an upper surface of the sealing member, side surfaces of the light transmissive member being covered with the sealing member; and
a heat dissipation terminal that is arranged generally in the center on the second main surface of the substrate and that has a recess portion as viewed along a direction normal to the second main surface.

US Pat. No. 10,193,040

LED PACKAGE WITH A PLURALITY OF LED CHIPS

Rohm Co., Ltd., Kyoto (J...

1. An LED package comprising:a substrate having a substrate main surface and a substrate back surface, which face opposite sides in a thickness direction;
a main surface electrode which is disposed on the substrate main surface, the main surface electrode including:
a first pad and a first die pad separated from each other, and
a second pad and a second die pad connected to each other;
a first LED chip which is mounted on the first die pad and has an electrode pad formed on a first chip main surface facing the same direction as the substrate main surface;
a first wire connecting the first pad and the electrode pad;
a second LED chip which is mounted on the second die pad and has a first electrode pad formed on a second chip main surface facing the same direction as the substrate main surface; and
a second wire connecting the second pad and the first electrode pad,
wherein the substrate main surface has a first side along a first direction perpendicular to the thickness direction of the substrate and a second side along a second direction perpendicular to both the thickness direction of the substrate and the first direction,
the first pad has a first base portion in contact with both the first side and the second side of the substrate main surface, and a first pad portion having one end connected to the first base portion,
the first pad portion of the first pad extends from the first base portion toward the first die pad, obliquely with respect to both the first direction and the second direction,
the second pad has a second base portion in contact with the first side of the substrate main surface, and a second pad portion having one end connected to the second base portion, and
the second pad portion of the second pad extends along the second direction.

US Pat. No. 10,193,038

THROUGH BACKPLANE LASER IRRADIATION FOR DIE TRANSFER

GLO AB, Lund (SE)

1. A method of manufacturing an assembly of a backplane and light emitting devices, the method comprising:providing a substrate with dies of light emitting devices thereupon, wherein a device-side bonding pad is provided on each of the light emitting devices;
bonding at least one of the light emitting devices to the backplane without bonding at least another of the light emitting devices to the backplane;
dissociating the at least one bonded light emitting device from the substrate by irradiating a laser beam through the substrate and onto each region of the substrate in contact with the at least one bonded light emitting device while the at least another of the light emitting devices remains attached to the substrate and not bonded to the backplane; and
separating the substrate and the at least another of the light emitting devices from an assembly of the backplane and the at least one bonded light emitting device that is bonded to the backplane;
wherein the backplane comprises a metal interconnect layer including a plurality of metal interconnect structures embedded in at least one insulating material and providing electrical connections between the light emitting devices on the backplane and input/output pins of the backplane.

US Pat. No. 10,193,033

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a plurality of light emitting elements each having a pair of electrodes on a lower surface thereof;
a light-transmissive member disposed on an upper surface of each of the light emitting elements to transmit light from the light emitting elements;
a first member disposed on one or more lateral surfaces of the light-transmissive member, and constituting part of an upper surface of the light emitting device with an upper surface of the light-transmissive member being exposed from the first member; and
a second member surrounding an outer periphery of each of the light emitting elements, and constituting part of a bottom-most surface of the light emitting device,
wherein lower surfaces of the electrodes are exposed from the second member to constitute part of the bottom-most surface of the light emitting device,
the first member and the second member respectively constitute parts of an outermost lateral surface of the light emitting device, and
the second member is in contact with a part of each of the light emitting elements.

US Pat. No. 10,193,023

LIGHT-EMITTING DIODE CHIP

PlayNitride Inc., Tainan...

1. A light-emitting diode chip, comprising:a p-type semiconductor layer;
a light-emitting layer;
an n-type semiconductor layer, the light-emitting layer being disposed between the p-type semiconductor layer and the n-type semiconductor layer, and the n-type semiconductor layer comprising:
a first n-type semiconductor sub-layer;
a second n-type semiconductor sub-layer; and
an ohmic contact layer, disposed between the first n-type semiconductor sub-layer and the second n-type semiconductor sub-layer, wherein the first n-type semiconductor sub-layer and the second n-type semiconductor sub-layer are separated by the ohmic contact layer; and
a first metal electrode, disposed on the first n-type semiconductor sub-layer, wherein a region of the first n-type semiconductor sub-layer located between the first metal electrode and the ohmic contact layer contains metal atoms diffusing from the first metal electrode, such that ohmic contact is formed between the first metal electrode and the ohmic contact layer.

US Pat. No. 10,193,020

SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

Seoul Viosys Co., Ltd., ...

1. A nitride semiconductor light emitting device, comprising:a first conductive type nitride semiconductor layer;
an active layer disposed under the first conductive type nitride semiconductor layer;
a second conductive type nitride semiconductor layer disposed under the active layer;
mesa regions disposed upward from the second conductive type nitride semiconductor layer so as to expose the first conductive type nitride semiconductor layer;
a second electrode disposed under the second conductive type nitride semiconductor layer;
a cover metal layer disposed at a corner under the second conductive type nitride semiconductor layer so as to overlap a part of the second electrode, and partially exposed in the upward direction;
an insulating layer disposed under the cover metal layer, the second electrode, and the mesa regions;
openings of the insulating layer, disposed at portions corresponding to the mesa regions so as to expose the first conductive type nitride semiconductor layer;
a first electrode disposed under the insulating layer and in the openings;
a conductive substrate disposed under the first electrode; and
a second electrode pad disposed over the exposed cover metal layer, wherein when a first width of the second electrode between one mesa region of the mesa regions and another mesa region adjacent to the mesa region is represented by a and a second width of the second electrode between a mesa region at an edge and an extension line of the cover metal layer at the corner is represented by b, a relation of a>b is established.

US Pat. No. 10,193,017

LIGHT EMITTING DIODE

SEOUL VIOSYS CO., LTD., ...

1. A light emitting device comprising:a substrate including a first to fourth corners, the first corner and the second corner disposed in a direction along an edge of the substrate and the third corner and the forth corner disposed in the direction along another edge of the substrate opposite to the edge of the substrate;
a first to third light emitting cells that are disposed on the substrate and sequentially arranged along the direction, each light emitting cell including a first conductive type semiconductor layer, a second conductive type semiconductor layer disposed on the first conductive type semiconductor layer, and an active layer interposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer;
a first electrode pad disposed in the first light emitting cell and electrically connected to the first conductivity type semiconductor layer of the first light emitting cell, the first electrode pad located closer to the first corner than the second to fourth corners;
a second electrode pad disposed in the third light emitting cell and electrically connected to the second conductivity type semiconductor layer of the third light emitting cell, the second electrode pad located closer to the third corner than the first, second and fourth corners;
a first connector connecting the first light emitting cell to the second light emitting cell and disposed closer to the fourth corner than the first, the second and the third corners;
a second connector connecting the second light emitting cell to the third light emitting cell and disposed closer to the second corner than the first, the third and the fourth corners; and
an insulation layer formed above the substrate and under the second connector,
wherein a surface of the second connector and a surface of the insulation layer include a pattern corresponding to a shape of an upper surface of the substrate,
wherein the second light emitting cell includes a second extension and a third extension that are electrically connected to the second conductivity type semiconductor layer of the second light emitting cell,
wherein the insulation layer comprises a first portion under the second connector and second portion under the second and the third extension, and
wherein a width of the first portion is wider than a width of the second portion and the third extension.

US Pat. No. 10,192,987

FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A fin-type field effect transistor, comprising:a substrate having fins and insulators disposed between the fins, wherein at least one fin of the fins comprises a stop layer embedded within the at least one fin, and the stop layer is located below top surfaces of the insulators;
at least one gate stack, disposed on the fins and on the insulators; and
strained material portions, disposed on the at least one fin and disposed on two opposite sides of the at least one gate stack.

US Pat. No. 10,192,964

COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

FUJITSU LIMITED, Kawasak...

1. A compound semiconductor device comprising:a carrier transit layer;
a carrier supply layer over the carrier transit layer;
a source electrode and a drain electrode above the carrier supply layer;
a gate electrode above the carrier supply layer between the source electrode and the drain electrode; and
a first insulating film, a second insulating film, and a third insulating film above the carrier supply layer between the gate electrode and the drain electrode, wherein
the gate electrode includes a portion above the third insulating film,
a first concentration of electron traps in the first insulating film is higher than a second concentration of electron traps in the second insulating film,
a third concentration of electron traps in the third insulating film is higher than the second concentration of the electron traps in the second insulating film, and
the third insulating film has a lamer size than the first insulating film in planar view.

US Pat. No. 10,192,940

DOUBLE SIDED ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND ITS MANUFACTURING METHOD THEREOF

Wuhan China Star Optoelec...

1. A manufacturing method for a double sided organic light-emitting display apparatus, comprising:providing a rigid substrate;
forming at least one transmission flexible substrate and at least one reflective flexible substrate on the rigid substrate;
forming a display substrate having a plurality of switching elements on the at least one transmission flexible substrate and the at least one reflective flexible substrate; and
forming at least one top-emission OLED light-emitting layer and at least one bottom-emission OLED light-emitting layer on the display substrate, wherein the at least one top-emission OLED light-emitting layer is corresponding to the at least one reflective flexible substrate and the at least one bottom-emission OLED light-emitting layer is corresponding to the at least one transmission flexible substrate;
wherein the at least one transmission flexible substrate and the at least one reflective flexible substrate are formed on a surface of the rigid substrate and are spaced from and corresponding to the at least one bottom-emission OLED light-emitting layer and the at least one top-emission OLED light-emitting layer, such that the at least one top-emission OLED light-emitting layer is separated by the display substrate from the at least one reflective flexible substrate.

US Pat. No. 10,192,939

DISPLAY DEVICE AND FABRICATION METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising:a thin film transistor array and an organic light emitting diode (OLED) pixel array on a base substrate;
an encapsulation film encapsulating the thin film transistor array and the OLED pixel array;
a protection film over the encapsulation film, the protection film including a first retardation film;
a touch film on the protection film, the touch film including a second retardation film; and
a polarizer film on the touch film,
wherein each of the first and second retardation films includes a ?? retardation film.

US Pat. No. 10,192,937

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate including a display area and a non-display area;
a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels which displays a different color from a color of the first pixel column; and
data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column,
wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines,
in the non-display area, the sub lines connected to the first pixel column are connected with one another through at least one first contact hole, the sub lines connected to the second pixel column are connected with one another through at least one second contact hole, and the sub lines connected to the second pixel column are connected through the at least one second contact hole having a larger area than an area of the at least one first contact hole, through which the sub lines connected to the first pixel column are connected with one another, and
wherein a resistance of the data line connected to the first pixel column is provided to be relatively larger than a resistance of the sub lines connected to the second pixel column.

US Pat. No. 10,192,934

LIGHT-EMITTING DEVICE HAVING LIGHT EMISSION BY A SINGLET EXCITON AND A TRIPLET EXCITON

Semiconductor Energy Labo...

1. An active matrix type light emitting device comprising a pixel portion comprising:a first pixel which emits red light comprising:
a first EL element comprising a hole injecting layer and a light emitting layer between a first electrode and a second electrode;
a first current controlling TFT electrically connected to the first electrode, wherein the first current controlling TFT is configured to control a current flowing in the first EL element;
a first switching TFT configured to control a signal to be input to a gate electrode of the first current controlling TFT; and
a first capacitor electrically connected to the gate electrode of the first current controlling TFT, wherein the first capacitor is configured to maintain a voltage applied to the gate electrode of the first current controlling TFT;
a second pixel which emits green light comprising:
a second EL element comprising a hole injecting layer and a light emitting layer between a third electrode and a fourth electrode;
a second current controlling TFT electrically connected to the third electrode, wherein the second current controlling TFT is configured to control a current flowing in the second EL element;
a second switching TFT configured to control a signal to be input to a gate electrode of the second current controlling TFT; and
a second capacitor electrically connected to the gate electrode of the second current controlling TFT, wherein the second capacitor is configured to maintain a voltage applied to the gate electrode of the second current controlling TFT;
a third pixel which emits blue light comprising:
a third EL element comprising a hole injecting layer and a light emitting layer between a fifth electrode and a sixth electrode;
a third current controlling TFT electrically connected to the fifth electrode, wherein the third current controlling TFT is configured to control a current flowing in the third EL element;
a third switching TFT configured to control a signal to be input to a gate electrode of the third current controlling TFT; and
a third capacitor electrically connected to the gate electrode of the third current controlling TFT, wherein the third capacitor is configured to maintain a voltage applied to the gate electrode of the third current controlling TFT;
an insulating film over the first current controlling TFT, the second current controlling TFT, and the third current controlling TFT,
wherein the insulating film comprises a first opening, a second opening, and a third opening,
wherein the first electrode overlaps with the first opening,
wherein the third electrode overlaps with the second opening,
wherein the fifth electrode overlaps with the third opening,
wherein an upper surface of the insulating film is provided over an upper surface of the first electrode, an upper surface of the third electrode, and an upper surface of the fifth electrode,
wherein the hole injecting layer included in the first EL element, the hole injecting layer included in the second EL element, and the hole injecting layer included in the third EL element are provided as a common layer,
wherein the second electrode, the fourth electrode, and the sixth electrode are provided as a common layer,
wherein the first EL element included in the first pixel which emits red light is configured to emit light by a triplet exciton,
wherein the third EL element included in the third pixel which emits blue light is configured to emit light by a singlet exciton, and
wherein an operation voltage of the first EL element, an operation voltage of the second EL element, and an operation voltage of the third EL element are in a range of 10 V or less.

US Pat. No. 10,192,923

PHOTODIODE ARRAY

HAMAMATSU PHOTONICS K.K.,...

1. A photodiode array comprising:avalanche photodiodes;
an insulating layer provided at a light incident side of a semiconductor substrate, covering the avalanche photodiodes; and
quenching resistors respectively connected to the avalanche photodiodes, each quenching resistor being provided on the insulating layer and arranged to cover an edge of a semiconductor region that forms one side of each avalanche photodiode,
wherein each of the quenching resistors includes:
an upper surface,
a lower surface, and
side surfaces extending along a surface of the insulating layer in a plan view, a strip of the quenching resistor defined by the side surfaces and forming a ring-like strip shape in the plan view.

US Pat. No. 10,192,922

CHARGE PACKET SIGNAL PROCESSING USING PINNED PHOTODIODE DEVICES

SEMICONDUCTOR COMPONENTS ...

1. An image sensor, comprising:an image pixel comprising a first pinned photodiode coupled to a pixel output line; and
analog-to-digital conversion (ADC) circuitry coupled to the pixel output line, wherein the ADC circuitry comprises:
a second pinned photodiode;
a comparator with first and second inputs;
a sampling transistor;
a first capacitive node that is coupled between the second pinned photodiode the first input of the comparator; and
a second capacitive node that is coupled between the sampling transistor and the second input of the comparator.

US Pat. No. 10,192,907

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

10. An array substrate, comprising:a base substrate; and
a first conductive pattern, a second conductive pattern, and an insulating pattern disposed on the base substrate, the insulating pattern at least covering an upper surface of the first conductive pattern, wherein
the first conductive pattern comprises a first crystalline transparent conductive pattern and a first metallic pattern, the first crystalline transparent conductive pattern is closer to the base substrate than the first metallic pattern; and the second conductive pattern comprises a second crystalline transparent conductive pattern.

US Pat. No. 10,192,905

ARRAY SUBSTRATES AND THE MANUFACTURING METHODS THEREOF, AND DISPLAY DEVICES

Shenzhen China Star Optoe...

1. A manufacturing method of array substrates, the method adopting four masking processes to obtain the array substrate and at least one pixel electrode within the array substrate, wherein a second masking process to form an active layer, a source electrode, and a drain electrode comprising:forming a semiconductor thin-film layer, N+ doping thin-film layer, a metal thin-film layer, and a photo-resistor layer on a gate insulation layer in sequence;
applying a gray-tone-mask process to expose and develop the photo-resistor layer to obtain a first photo-resistor mask;
under protection of the first photo-resistor mask, applying a first wet etching process to etch a portion of the metal thin-film layer that is not covered by the first photo-resistor mask;
under the protection of the first photo-resistor mask, applying a first dry etching process to etch portions of the semiconductor thin-film layer and the N+ doping thin-film layer that are not covered by the first photo-resistor mask to obtain the active layer;
applying a plasma ashing process to the first photo-resistor mask to obtain a second photo-resistor mask, and the metal thin-film layer is exposed by a central area of the second photo-resistor mask;
under the protection of the second photo-resistor mask, applying a second wet etching process to etch away a portion of the metal thin-film layer that is not covered by the second photo-resistor mask to obtain the source electrode and the drain electrode; and
peeling off the second photo-resistor mask, applying a second dry etching process to etch away the portion of the N+ doping thin-film layer between the source electrode and the drain electrode to obtain the N+ contact layer respectively between the source electrode and the active layer and between the drain electrode and the active layer.

US Pat. No. 10,192,903

METHOD FOR MANUFACTURING TFT SUBSTRATE

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing a TFT substrate, comprising:step 101: providing a substrate and depositing a buffer layer on the substrate, wherein the substrate includes a drive TFT region and a display TFT region;
step 102: depositing a first amorphous silicon layer on the buffer layer, and performing excimer laser annealing on the first amorphous silicon layer so as to convert the first amorphous silicon layer into a first polysilicon layer through crystallization;
patterning the first polysilicon layer, to obtain a first active layer that is located in the drive TFT region;
step 103: depositing a gate insulating layer on the first active layer and the buffer layer;
depositing and patterning a first metal layer on the gate insulating layer, to form a first gate electrode at a position corresponding to position of the first active layer and form a second gate electrode at a position corresponding to position where the first active layer is not arranged;
step 104: implanting ions into the gate insulating layer taking the first gate electrode and the second gate electrode as a shading layer;
step 105: depositing an interlayer insulating layer on the gate insulating layer, the first gate electrode and the second gate electrode, depositing a second amorphous silicon layer on the interlayer insulating layer, implanting ions into the second amorphous silicon layer, and performing solid phase crystallization on the second amorphous silicon layer so as to convert the second amorphous silicon layer into a second polysilicon layer;
patterning the second polysilicon layer to form a second active layer at a position corresponding to the second gate electrode;
wherein the second amorphous silicon layer is implanted with boron (B) ions;
step 106: forming a first via hole and a second via hole in the gate insulating layer and the interlayer insulating layer corresponding to the first active layer, and forming a third via hole in the interlayer insulating layer corresponding to the second gate electrode;
step 107: depositing a source-drain electrode layer, patterning the source-drain electrode layer, and forming a channel on a surface of the second active layer at the same time;
step 108: depositing a passivation layer and patterning the passivation layer, depositing a flat layer on the passivation layer, and forming a fourth via hole in the flat layer at a position thereof in the display TFT region, the fourth via hole extending to a surface of the source-drain electrode layer; and
step 109: depositing an anode electrode on the flat layer, the anode electrode being in contact with the source-drain electrode layer through a fourth via hole, depositing a pixel definition layer, and defining a pattern, so that the TFT substrate is manufactured.

US Pat. No. 10,192,902

LTPS ARRAY SUBSTRATE

Shenzhen China Star Optoe...

1. A low temperature poly-silicon (LTPS) array substrate, comprising:a substrate;
a source electrode and a drain electrode, which are arranged on the substrate;
a poly-silicon layer, which is arranged on the substrate including the source electrode and the drain electrode, wherein the poly-silicon layer partially covers the source electrode and the drain electrode;
an insulating layer, which is arranged on the poly-silicon layer and the source and drain electrodes, wherein the insulating layer is formed through passivation of a part of the poly-silicon layer that covers the substrate including the source electrode and the drain electrode;
a gate electrode, which is arranged on the insulating layer between the source electrode and the drain electrode, wherein the source and drain electrodes, the poly-silicon layer, and the gate electrode collectively form a thin-film transistor (TFT);
a planar layer, which is arranged on the substrate including the gate electrode, wherein the planar layer is formed with a contact hole extending therethrough to expose a surface of the drain electrode;
a common electrode, which is arranged on the planar layer except the TFT of the LTPS array substrate;
a passivation layer, which is arranged on the planar layer and the common electrode layer, such that the passivation layer does not cover the contact hole;
a pixel electrode, which is arranged on the passivation layer, wherein the pixel electrode is electrically connected with the drain electrode through the contact hole;
wherein the poly-silicon layer has a first region that is stacked atop and covers an inner part of each of the source electrode and the drain electrode and a portion of the substrate that is between the source electrode and the drain electrode and a second region that is integrally extended from the first region and is partly stacked atop and covers an outer part of each of the source electrode and the drain electrode; and
wherein the first region of the poly-silicon has a thickness that is greater than a thickness of the second region of the poly-silicon and the first region of the poly-silicon has a lower part in direct contact with the inner parts of the source electrode and the drain electrode and the portion of substrate between the source electrode and the drain electrode and an upper part that forms a first portion of the insulating layer; and the second region of the poly-silicon, in the entirety thereof, forms a second portion of the insulating layer that integrally extends from the first portion of the insulating layer, such that the insulating layer is integrally combined with the lower part of the poly-silicon layer and is extended to cover the source electrode and the drain electrode.

US Pat. No. 10,192,899

DISPLAY AND MANUFACTURE METHOD THEREOF

AU OPTRONICS CORPORATION,...

1. A display, comprising:a first substrate;
a second substrate;
a plurality of pixels, disposed between the first substrate and the second substrate;
a seal disposed between the first substrate the second substrate; and
a photo-catalyst layer, disposed above a surface of the second substrate facing the first substrate or above a surface of the first substrate facing the second substrate, wherein the photo-catalyst layer and the plurality of pixels are located at two opposite sides of the seal respectively;
wherein each of the plurality of pixels comprises a transistor, and each of the transistors comprises a gate electrode, a source electrode, and an active layer, wherein the photo-catalyst layer and the gate electrode, or the photo-catalyst layer and the source electrode are belonging to a same first film layer.

US Pat. No. 10,192,889

DISPLAY DEVICE AND METHOD OF MANUFACTURING A DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a first substrate including a display area and a non-display area;
a gate line and a gate electrode in the display area;
a data line connected to the gate line;
a gate insulating layer on the gate line and the gate electrode;
a semiconductor layer on the gate insulating layer;
a drain electrode and a source electrode on the semiconductor layer;
a first passivation layer on the drain electrode and the source electrode;
a color filter on the first passivation layer;
a common electrode on the first passivation layer;
a second passivation layer on the common electrode; and
a pixel electrode on the second passivation layer,
wherein the gate insulating layer has substantially a same shape as a shape of the gate electrode,
wherein the gate insulating layer has a width wider than a width of the gate electrode,
wherein the gate insulating layer is spaced apart from the first substrate, and
wherein a side surface of the gate electrode is exposed below a bottom surface of the gate insulating layer.

US Pat. No. 10,192,887

METHOD TO IMPROVE CRYSTALLINE REGROWTH

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor device comprising:a conductive strap electrically connecting an electrode with a single crystal region of a semiconductor substrate; and
a conductive barrier layer between the conductive strap and the single crystal region,wherein the conductive barrier layer comprises carbon, hydrogen, cobalt or titanium nitride, and at least one of germanium and phosphorus.

US Pat. No. 10,192,880

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:gate stacked structures surrounding channel layers;
a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, wherein the first concave portions are arranged in a first direction crossing a lengthwise direction of the channel layer; and
a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.

US Pat. No. 10,192,879

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device having a memory cell of a nonvolatile memory, comprising:a semiconductor substrate;
a first gate electrode formed over the semiconductor substrate via a first gate insulating film; and
a second gate electrode formed over the semiconductor substrate via a multi-layer insulating film, and adjacent to the first gate electrode via the multi-layer insulating film,
wherein the multi-layer insulating film includes a first insulating film, a second insulating film over the first insulating film, and a third insulating film over the second insulating film,
wherein the second insulating film has a charge storing function,
wherein the second gate electrode has a lower surface facing the semiconductor substrate, a first side surface adjacent to the first gate electrode via the multi-layer insulating film, and a second side surface opposite to the first side surface, and
wherein a fourth insulating film is formed between the lower surface of the second gate electrode and the semiconductor substrate and is in contact with the first, second and third insulating films such that the fourth insulating film is located closer to a first end portion of the second side surface of the second gate electrode than to a second end portion of the first side surface of the second gate electrode.

US Pat. No. 10,192,869

REDUCTION OF NEGATIVE BIAS TEMPERATURE INSTABILITY

INTERNATIONAL BUSINESS MA...

1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:an n-channel field effect transistor (nFET), the nFET comprising a high-k dielectric layer on an interlayer, an nFET work function setting metal on the high-k dielectric layer, a cap layer on the nFET work function setting metal, and a pFET work function setting metal on the cap layer, wherein the interlayer is silicon dioxide (SiO2); and
a p-channel field effect transistor (pFET), the pFET comprising the high-k dielectric layer directly on the interlayer, the cap layer directly on the high-k dielectric layer, and the pFET work function setting metal directly on the cap layer, wherein the cap layer is aluminum-based and the pFET work function setting metal is a nitride and metal atoms from the cap layer do not intermix with the interlayer.

US Pat. No. 10,192,862

SEMICONDUCTOR DEVICE

Murata Manufacturing Co.,...

1. A semiconductor device comprising:an amplifier circuit including a semiconductor element formed on a substrate;
a protection circuit including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit; and
a pad conductive layer at least partially including a pad for connecting to a circuit outside the substrate, wherein
the pad conductive layer and the protection circuit at least partially overlap each other in plan view, and
at least one of the protection diodes includes a substantially U-shaped electrode in plan view.

US Pat. No. 10,192,860

ENGINEERING CHANGE ORDER (ECO) CELL, LAYOUT THEREOF AND INTEGRATED CIRCUIT INCLUDING THE ECO CELL

Samsung Electronics Co., ...

1. An integrated circuit (IC) comprising:an integrated circuit substrate;
a plurality of standard cells on said integrated circuit substrate; and
at least one engineering change order (ECO) base cell on the integrated circuit substrate;
wherein the ECO base cell has a layout that is generated based on a layout of a functional cell corresponding to a first circuit including a plurality of logic gates having different logic configurations relative to each other;
wherein the layout of the ECO base cell includes a plurality of spaced-apart and dissimilar regions that are each associated with a respective one of the plurality of logic gates, with each of the plurality of dissimilar regions comprising a plurality of spaced-apart active regions and a plurality of gate lines overlapping the plurality of spaced-apart active regions; and
wherein the plurality of gate lines are disposed asymmetrically on said integrated circuit substrate so that the gate lines within at least two of the plurality of dissimilar regions lack symmetry relative to each other and relative to an axis extending between the at least two of the plurality of dissimilar regions.

US Pat. No. 10,192,858

LIGHT EMITTING STRUCTURE

Apple Inc., Cupertino, C...

1. A display comprising:a substrate;
a first bottom electrode line on the substrate;
a passivation layer over the display substrate;
a first plurality of vertical semiconductor-based light emitting diodes (LEDs) coupled with the first bottom electrode line and embedded within the passivation layer such that the passivation layer laterally surrounds a quantum well within each of the first plurality of vertical semiconductor-based LEDs;
a second plurality of vertical semiconductor-based LEDs embedded within the passivation layer such that the passivation layer laterally surrounds a quantum well within each of the second plurality of vertical semiconductor-based LEDs, wherein the second plurality of vertical semiconductor-based LEDs and the first plurality of vertical semiconductor-based LEDs share a same vertical semiconductor-based LED; and
a first top electrode line in electrical contact with the second plurality of vertical semiconductor-based LEDs.

US Pat. No. 10,192,846

METHOD OF INSERTING AN ELECTRONIC COMPONENT INTO A SLOT IN A CIRCUIT BOARD

Infineon Technologies Aus...

1. A method, comprising:inserting an electronic component comprising a power semiconductor device embedded in a dielectric core layer into a slot in a side face of a circuit board, wherein the inserting the electronic component causes one or more electrically conductive contacts on one or more surfaces of the electronic component to electrically couple with one or more corresponding electrical contacts arranged on one or more surfaces of the slot,
exerting pressure on the contact of the slot to electrically couple the one or more electrical contacts arranged on one or more surfaces of the slot to the one or more electrically conductive contacts of the electronic component, wherein the exerting the pressure comprises exerting pressure on a surface of the circuit board defining the slot by applying one or more fixation elements.

US Pat. No. 10,192,845

ELECTRONIC DEVICE AND MOUNTING STRUCTURE OF THE SAME

ROHM CO., LTD., Kyoto (J...

1. An electronic device comprising:a first electronic element; a second electronic element spaced apart from and electrically connected to the first electronic element; a main electrode on which the first electronic element and the second electronic element are disposed;
an insulating joining part directly interposed between the first electronic element and the main electrode;
a plurality of insulating spacers mixed in the joining part and each directly contacting the main electrode and the first electronic element; a joining layer interposed between the second electronic element and the main electrode, the joining layer being made of an electroconductive material comprising silver (Ag); and; and
a sealing resin covering the first electronic element, the second electronic element and the main electrode.

US Pat. No. 10,192,844

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip, a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant, the first interconnection member and the second interconnection member including, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip: and
a component package including a wiring substrate disposed above the second interconnection member and connected to the second interconnection member through the first connection terminals and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate,
wherein the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer.

US Pat. No. 10,192,840

BALL PAD WITH A PLURALITY OF LOBES

Intel Corporation, Santa...

1. An electronic assembly comprising:a substrate that includes a conductive trace embedded within the substrate, wherein the conductive trace is exposed to an upper exterior surface of the substrate; and
a ball pad mounted on the upper exterior surface of the substrate, wherein the ball pad engages the conductive trace and includes a plurality of lobes projecting distally from a center of the ball pad, wherein each lobe in the plurality of lobes includes two sides that form an edge with the two sides extending from the edge at an acute angle, wherein one of the two sides in each lobe forms a planar surface with a side of another lobe and the other of the two sides forms a separate planar surface with a side of a different lobe.

US Pat. No. 10,192,833

INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES

Taiwan Semiconductor Manu...

1. An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising:a substrate body having opposed first and second surfaces;
a plurality of conductive layers disposed in a dielectric material on said substrate body, wherein a first one of said plurality of conductive layers includes a first lead and a second of said plurality of conductive layers includes a second lead, wherein said first lead is shielded from said second lead by a shield including portions of a first interposed conductive layer and a second interposed conductive layer of said plurality of conductive layers coupled by a via such that an entirety of a longitudinal width of each of the first interposed conductive layer and the second interposed conductive layer of the shield is contained within a boundary of a first coupling via and a second coupling via;
said first lead extending along a longitudinal direction of said interposer and said shield extending continuously along a transverse direction of said interposer, wherein said shield extends across at least a majority of a transverse width of said interposer between said first and second leads; and
wherein said plurality of conductive layers are formed of metal materials or semiconductor materials;wherein said shield forms a continuous member of said metal materials or semiconductor materials, and there is no dielectric path from said first lead to said second lead through said shield.

US Pat. No. 10,192,825

SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A semiconductor device comprising:a first gate line, having a first long axis extending along a first direction;
a second gate line, parallel to the first gate line;
a first bar-shaped contact structure, having a second axis forming an angle substantially greater than 0° and less than 90° with the first long axis, wherein the first bar-shaped contact structure at least partially covers on the first gate line and the second gate line;
a first semiconductor fin, having a third long axis perpendicular to the first direction and overlapping with the first gate line and the second gate line, and
a second semiconductor fin, parallel to and adjacent to the first semiconductor fin and overlapping with the first gate line and the second gate line,
wherein the first bar-shaped contact structure is completely disposed on a portion of an insulation structure disposed between the first semiconductor fin and the second semiconductor fin.

US Pat. No. 10,192,815

WIRING BOARD AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring board comprising:a first insulating layer;
a first wiring layer formed on a lower surface of the first insulating layer;
a first through hole which penetrates the first insulating layer in a thickness direction of the first insulating layer;
a first via wiring comprising:
a filling portion formed to fill the first through hole and connected to the first wiring layer; and
a protruding portion protruding upward from an upper surface of the first insulating layer;
a second wiring layer comprising a land, wherein the land comprises:
an outer circumferential portion covering the upper surface of the first insulating layer; and
a central portion formed integrally with the outer circumferential portion to cover a side surface and an upper surface of the protruding portion and protruding upward from an upper surface of the outer circumferential portion,
a second insulating layer formed on the upper surface of the first insulating layer to cover the second wiring layer;
a second through hole which penetrates the second insulating layer in the thickness direction to expose a side surface and an upper surface of the central portion;
a second via wiring formed to fill the second through hole to cover the side surface and the upper surface of the central portion; and
a third wiring layer formed on an upper surface of the second insulating layer and connected to the second via wiring,
wherein
the filling portion comprises:
a first metal film covering an inner side surface of the first through hole, the first metal film including an upper end surface that is planar with the upper surface of the first insulating layer;
a second metal film covering the first metal film; and
a metal layer covering the second metal film,
the protruding portion comprises:
the metal layer protruding upward from the upper surface of the first insulating layer; and
the second metal film covering a side surface and an upper surface of the metal layer exposed from the upper surface of the first insulating layer, and
the first via wiring has a step at a boundary between the protruding portion and the filling portion, the step formed along the upper end surface of the first metal film and a side surface and an upper surface of the second metal film, the side surface and the upper surface of the second metal film being exposed from the first metal film.

US Pat. No. 10,192,813

HARD MACRO HAVING BLOCKAGE SITES, INTEGRATED CIRCUIT INCLUDING SAME AND METHOD OF ROUTING THROUGH A HARD MACRO

QUALCOMM Incorporated, S...

1. A hard macro having a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro from the top to the bottom and including an array of blockage sites extending through the hard macro, wherein the plurality of vias are formed in at least some of the array of blockage sites and wherein at least one via is configured to connect a first element to a second element, the first element in a first layer different from a layer that includes the hard macro, the first element positioned in a first direction from a line that passes through the at least one via, the second element in a second layer different from the layer that includes the hard macro, the second element positioned in a second direction from the line that passes through the at least one via, and wherein, between the top and the bottom of the hard macro, the line is entirely contained within the hard macro.

US Pat. No. 10,192,807

POWER SEMICONDUCTOR MODULE, FLOW PATH MEMBER, AND POWER-SEMICONDUCTOR-MODULE STRUCTURE

FUJI ELECTRIC CO., LTD., ...

1. A power semiconductor module comprising:a metal base plate including a first surface and a second surface opposite to the first surface;
a multi-layer substrate including a third surface and a fourth surface opposite to the third surface, the fourth surface being joined to the first surface;
a semiconductor element mounted on the third surface;
a resin case disposed on the first surface of the metal base plate, the resin case surrounding the multi-layer substrate and the semiconductor element; and
a cooling case including
a bottom wall,
a side wall formed around the bottom wall and having one end of the side wall being joined to the second surface of the metal base plate to form a space enclosed by the metal base plate, the bottom wall, and the side wall for circulating a coolant,
an inlet portion having an inlet opening for introducing the coolant to the cooling case and an outlet portion having an outlet opening for discharging the coolant from the cooling case, the inlet portion and the outlet portion being connected to either the bottom wall or the side wall and disposed along a peripheral edge of the second surface of the metal base plate,
a first flange disposed at an inlet opening side of the inlet portion and having a main surface opposite to the inlet portion, the main surface of the first flange being parallel to a first surface of the metal base plate, and
a second flange disposed at an outlet opening side of the outlet portion and having a main surface opposite to the outlet portion, the main surface of the second flange being parallel to the first surface.

US Pat. No. 10,192,806

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:an insulating substrate including a metal plate, an insulating resin plate laminated on the metal plate, and circuit plates laminated on the insulating resin plate and including one circuit plate having a circuit pattern and an adhering pattern, which are selectively formed on the insulating resin plate;
a semiconductor element fixed to the circuit pattern of the insulating substrate with a bonding material;
a wiring member having an end connected to the one circuit plate of the insulating substrate;
a housing accommodating the insulating substrate, the semiconductor element, and the wiring member; and
a sealing material sealing the insulating substrate, the semiconductor element, and the wiring member accommodated in the housing,
wherein the adhering pattern is an opening, in a plan view, disposed in the one circuit plate, and arranged between the semiconductor element fixed to the one circuit plate and the end of the wiring member fixed to the one circuit plate,
the sealing material bonds the insulating resin plate through the opening to increase a bond between the sealing material and the insulating resin plate, and
one of the circuit plates having the adhering pattern is bonded to the insulating resin plate by the sealing material through the opening as the adhering pattern.

US Pat. No. 10,192,800

SEMICONDUCTOR DEVICE

ABB Schweiz AG, Baden (C...

1. A semiconductor device, comprising:two electrodes with opposite faces;
a semiconductor wafer sandwiched between the two electrodes;
an outer insulating ring attached to the two electrodes and surrounding the semiconductor wafer;
a middle insulating ring inside the outer insulating ring and surrounding the semiconductor wafer, whereby the middle insulating ring is made of a plastics material;
an inner insulating ring inside the middle insulating ring, whereby the inner insulating ring is made of ceramics and/or glass material;
wherein either the middle insulating ring or the inner insulating ring has a tongue and the other thereof has a groove such that the tongue fits into the groove for their rotational alignment and
wherein the middle insulating ring and the inner insulating ring have a radial opening for receiving a gate connection of the semiconductor device.

US Pat. No. 10,192,795

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a power transistor that passes a current from a high-potential terminal to a low-potential terminal, the power transistor comprising a gate electrode insulated from a channel region of the power transistor by an insulating film; and
a temperature sensing diode that senses a variation in temperature due to heating of the power transistor,
wherein the low-potential terminal of the power transistor and a cathode of the temperature sensing diode are directly electrically connected to each other so as to have a same potential.

US Pat. No. 10,192,785

DEVICES AND METHODS RELATED TO FABRICATION OF SHIELDED MODULES

Skyworks Solutions, Inc.,...

1. A method for preparing a carrier assembly for processing of packaged modules, the method comprising:providing a plate having a first side and a second side, and defining a plurality of openings, such that each opening extends through the plate between the first side and the second side; and
implementing an adhesive layer on the first side of the plate, such that the adhesive layer defines a plurality of openings arranged to substantially match the openings of the plate, each opening of the adhesive layer dimensioned such that the adhesive layer is capable of providing an adhesive engagement between a perimeter portion of an underside of a package and a perimeter portion about the corresponding opening of the adhesive layer, and such that the underside of the package not in engagement with the adhesive layer is exposed through the respective opening on the second side of the plate.

US Pat. No. 10,192,777

METHOD OF FABRICATING STI TRENCH

UNITED MICROELECTRONICS C...

1. A method of fabricating a shallow trench isolation (hereafter abbreviated as STI) trench, comprising:providing a substrate;
forming a first mask covering the substrate, and the first mask comprising a plurality of sub-masks, wherein a first trench is disposed between the sub-masks adjacent to each other;
forming a protective layer filling up the first trench;
forming a second mask covering the first mask, and the second mask comprising an opening, wherein one of the sub-masks directly under the opening is defined as a joint STI pattern;
removing the joint STI pattern to transform the first mask into a third mask by taking the second mask as a first protective mask;
removing the second mask;
removing the protective layer; and
removing part of the substrate to form a plurality of STI trenches by taking the third mask as a second protective mask.

US Pat. No. 10,192,774

TEMPERATURE CONTROL DEVICE FOR PROCESSING TARGET OBJECT AND METHOD OF SELECTIVELY ETCHING NITRIDE FILM FROM MULTILAYER FILM

TOKYO ELECTRON LIMITED, ...

6. A method of selectively etching a nitride film from a processing target object, which has a multilayer film in which an oxide film and the nitride film are alternately stacked on top of each other, by using a temperature control device comprising a moving stage allowed to be heated and configured to mount a processing target object on a top surface thereof; a cooling body allowed to be cooled and fixed at a position under the moving stage; a shaft, having one end connected to the moving stage; the other end positioned under the cooling body; a first flange provided at the other end; and a second flange provided between the first flange and the cooling body, extended between the one end and the other end; a driving plate, provided between the first flange and the second flange, having a top surface facing the second flange and a bottom surface opposite to the top surface; an elastic body provided between the bottom surface of the driving plate and the first flange; and a driving unit configured to move the driving plate up and down, the method comprising:placing the processing target object on the top surface of the moving stage;
bringing the moving stage into contact with the cooling body by moving the driving plate downwards;
adjusting a contact thermal resistance between the moving stage and the cooling body by adjusting an amount of a downward movement of the driving plate;
etching the nitride film selectively from the multilayer film by plasma of a processing gas containing fluorine and hydrogen after the bringing of the moving stage into contact with the cooling body;
spacing the moving stage apart from the cooling body by moving the driving plate upwards after the etching of the nitride film; and
removing a reaction product, which is generated in the etching of the nitride film, by heating the moving stage after the spacing of the moving stage apart from the cooling body.

US Pat. No. 10,192,770

SPRING-LOADED PINS FOR SUSCEPTOR ASSEMBLY AND PROCESSING METHODS USING SAME

Applied Materials, Inc., ...

1. A susceptor assembly, comprising:a susceptor having a susceptor body and a top surface with at least one recess therein sized to enclose a wafer during processing, each recess having a bottom surface with at least three flared openings; and
at least three lift pins positioned within each recess, each lift pin positioned within one of the at least three flared openings in the bottom surface of the recess, each lift pin comprising a sleeve having an elongate body with a flared top end, bottom, sides and an elongate axis, the sleeve movable within the recess along the elongate axis so that the flared top end of the sleeve can extend above the bottom surface of the recess, a spring within the elongate body of the sleeve adjacent the bottom of the sleeve and a pin positioned within the elongate sleeve in contact with the spring, the pin having a flared top portion and movable along the elongate axis of the sleeve so that a top surface of the pin can extend above the flared top end of the sleeve.

US Pat. No. 10,192,767

CERAMIC ELECTROSTATIC CHUCK INCLUDING EMBEDDED FARADAY CAGE FOR RF DELIVERY AND ASSOCIATED METHODS FOR OPERATION, MONITORING, AND CONTROL

Lam Research Corporation,...

1. A substrate support system, comprising:a ceramic assembly having a top surface and a bottom surface, the top surface including an area configured to support a substrate;
at least one clamp electrode positioned within the ceramic assembly;
a primary radiofrequency (RF) power delivery electrode positioned within the ceramic assembly at a location vertically below the at least one clamp electrode;
a lower support structure formed of an electrically conductive material, the ceramic assembly secured to the lower support structure such that an outer peripheral region of the bottom surface of the ceramic assembly is supported by the lower support structure, the lower support structure including a hollow interior region exposed to a portion the bottom surface of the ceramic assembly; and
a plurality of electrical connections established between the lower support structure and the primary RF power delivery electrode, each of the plurality of electrical connections extending through a respective portion of the ceramic assembly.

US Pat. No. 10,192,765

SUBSTRATE PROCESSING SYSTEMS, APPARATUS, AND METHODS WITH FACTORY INTERFACE ENVIRONMENTAL CONTROLS

Applied Materials, Inc., ...

1. A method of processing substrates within an electronic device processing system, comprising:providing a factory interface including a factory interface chamber, one or more substrate carriers docked to the factory interface, each of the one or more substrate carriers having a substrate carrier door, one or more carrier purge chambers within the factory interface chamber, and one or more load lock chambers coupled to the factory interface;
sealing a carrier purge housing to the factory interface chamber, the carrier purge housing having a carrier purge chamber located therein, the sealing covering a substrate carrier door and isolating the carrier purge chamber from the factory interface chamber;
monitoring one or more environmental conditions in the carrier purge chamber;
setting one or more environmental conditions in the carrier purge chamber in response to the monitoring;
opening the substrate carrier door by attaching a door opener to the substrate carrier door, the door opener being attached to a rack and pinion, the rack located within the carrier purge chamber, the pinion being attached to a motor at least partially located external to the carrier purge chamber; and
unsealing the carrier purge housing from the factory interface.

US Pat. No. 10,192,763

METHODOLOGY FOR CHAMBER PERFORMANCE MATCHING FOR SEMICONDUCTOR EQUIPMENT

Applied Materials, Inc., ...

1. A method for calibrating a plasma processing chamber for semiconductor manufacturing process, comprising:performing a first predetermined plasma process in a plasma processing chamber;
maintaining a desired gas pressure in the plasma processing chamber;
collecting a first set of signals transmitted from a first group of sensors disposed in the plasma processing chamber to a controller while performing the predetermined process;
analyzing the collected first set of signals;
comparing the collected first set of signals with database stored in the controller of the plasma processing chamber to check sensor responses from the first group of sensors;
calibrating sensors based on the collected first set of signals when a mismatch sensor response is found;
subsequently performing a first series of plasma processes including at least two processes in the processing chamber, wherein the first series of processes comprises multiple processes including the process parameters set in the first predetermined process, 20% above and below of the process parameters set in the first predetermined process, and 10% above and below of the process parameters set in the first predetermined process; and
collecting a second set of signals transmitted from the sensors to the controller while performing the series of plasma processes in the plasma processing chamber.

US Pat. No. 10,192,759

IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING

LAM RESEARCH CORPORATION,...

1. A semiconductor processing tool, comprising:one or more process chambers;
one or more gas inlets into the one or more process chambers and associated flow-control hardware;
a low frequency radio frequency (LFRF) generator;
a high frequency radio frequency (HFRF) generator; and
a controller having at least one processor and a memory, wherein
the at least one processor and the memory are communicatively connected with one another,
the at least one processor is at least operatively connected with the flow-control hardware, the LFRF generator, and the HFRF generator, and
the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow-control hardware, the HFRF generator, and the LFRF generator to:
etch a semiconductor substrate to transfer a pattern from an overlying photoresist to a core amorphous carbon layer on the semiconductor substrate;
deposit a conformal film over the patterned core amorphous carbon layer on the semiconductor substrate;
deposit a gap-fill amorphous carbon layer over the conformal film;
planarize the semiconductor substrate with a process that etches both the conformal film and the gap-fill amorphous carbon layer to remove the conformal film overlying the core amorphous carbon layer without removing the conformal film deposited between the core amorphous carbon layer and the gap-fill amorphous carbon layer; and
selectively etch the conformal film to form a mask.

US Pat. No. 10,192,756

METHOD OF MACHINING A LEAD FRAME, AND LEAD FRAME

OSRAM Opto Semiconductors...

1. A method of processing a lead frame having at least one electrically conductive contact section, comprising:forming a depression in the at least one electrically conductive contact section so that a first electrically conductive contact subsection and a second electrically conductive contact subsection are formed, which are delimited from one another by the depression, wherein the depression has a bottom via which an electrically conductive connection between the first electrically conductive contact subsection and the second electrically conductive contact subsection is established, and
forming a housing made of a housing material, which housing comprises a housing frame that at least partially embeds the lead frame, formation of the housing comprising introduction of housing material into the depression so that a housing frame section formed by the housing material introduced into the depression is formed between the first and second electrically conductive contact subsections to mechanically stabilize the first and second electrical conductive contact subsections by the housing frame section.

US Pat. No. 10,192,755

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
a plurality of wiring layers formed over the semiconductor substrate;
a pad electrode formed in the uppermost layer of the wiring layers;
a first protective film having an opening over the pad electrode;
a first redistribution line formed over the first protective film and having an upper surface, a side surface and a lower surface, the first redistribution line coupled electrically to the pad electrode through the opening;
a sidewall barrier film comprised of an insulating film formed on the side surface of the first redistribution line; and
a cap metallic film covering the upper surface of the first redistribution line and having an overlapping part with sidewall barrier film,
wherein the cap metallic film covers the side surface of the first redistribution line, and
wherein the cap metallic film and the sidewall barrier film are overlapped with each other at the side surface of the first redistribution line.

US Pat. No. 10,192,753

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

10. A nonvolatile semiconductor memory device, comprising:a plurality of conductive layers arranged in a first direction and a second direction crossing the first direction, the plurality of conductive layers extending in a third direction, the third direction crossing the first direction and the second direction, the plurality of conductive layers including a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer being arranged in the second direction;
a first semiconductor layer having the first direction as a longitudinal direction and facing the first conductive layer;
a first charge accumulation layer disposed between the first semiconductor layer and the first conductive layer; and
a second semiconductor layer having the first direction as a longitudinal direction and facing the second conductive layer; and
a second charge accumulation layer disposed between the second semiconductor layer and the second conductive layer, wherein
at least a part of the first conductive layer is disposed between the first semiconductor layer and the second semiconductor layer,
at least a part of the second conductive layer is disposed between the first conductive layer and the second semiconductor layer, and
the first conductive layer having a first surface in the second direction facing the first semiconductor layer and a second surface in the second direction facing the second conductive layer, an upper end and a lower end of the second surface being rounded.

US Pat. No. 10,192,740

HIGH THROUGHPUT SEMICONDUCTOR DEPOSITION SYSTEM

Alliance for Sustainable ...

1. A method of performing hydride vapor phase epitaxy (HVPE) deposition, the method comprising:providing at least one first source material and at least one first carrier gas flow to a first HVPE mixing zone coupled to a first deposition zone;
providing at least one second source material and at least one second carrier gas flow to a second HVPE mixing zone coupled to a second deposition zone;
heating the first deposition zone to a first temperature;
heating the first HVPE mixing zone to a second temperature;
heating the second deposition zone to a third temperature, wherein the third temperature is different from the first temperature;
heating the second HVPE mixing zone to a fourth temperature;
outputting, from the first HVPE mixing zone into the first deposition zone, first reactant gases produced from the at least one first source material and the at least one first carrier gas flow;
outputting, from the second HVPE mixing zone into the second deposition zone, second reactant gases produced from the at least one second source material and the at least one second carrier gas flow;
placing a substrate into the first deposition zone to grow a first layer from the first reactant gases; and
placing the substrate into the second deposition zone to grow a second layer from the second reactant gases,
wherein the heating of the first deposition zone to the first temperature and the heating of the second deposition zone to the third temperature are performed concurrently.

US Pat. No. 10,192,733

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND CHEMICAL LIQUID

TOSHIBA MEMORY CORPORATIO...

1. A method of manufacturing a semiconductor device comprising:attaching, by a liquid treatment, a first liquid to a surface of a semiconductor substrate having a fine pattern formed therein;
substituting the first liquid attached to the surface of the semiconductor substrate with a solution, the solution comprising a precipitating material dissolved in a second liquid;
vaporizing the second liquid and precipitating the precipitating material to the surface of the semiconductor substrate; and
removing the precipitating material by transforming the precipitating material from solid to gas by depressurization and/or heating,
the precipitating material comprising at least one material selected from a group consisting of:
materials represented by chemical formulae A1, A2, A3, and A4 indicated in FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D where X1, X2, and X3 in the chemical formulae A1, A2, A3, and A4 each independently represent either of a hydroxy group (—OH), a carboxyl group (—COOH), an amino group (—NH2), an amide group (—CONH2), a nitro group (—NO2), and a methylester group (—COO—CH3), and
materials represented by chemical formulae B1, B2, B3, B4, and B5 indicated in FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, and FIG. 6E where X1, X2, X3, and X4 in the chemical formulae B 1, B2, B3, B4 and B5 each independently represent either of a hydroxy group (—OH), a carboxyl group (—COOH), an amino group (—NH2), an amide group (—CONH2), a nitro group (—NO2), a methylester group (—COO—CH3), a methoxy group (—OCH3), an ethoxy group (—OCH2CH3), and a propoxy group (—OCH2CH2CH3),
in the materials represented by chemical formulae A1, A4, B1, B3, and B5, a group bonded to one of adjacent bonding sites is a carboxyl group and one or more groups bonded to the other of the adjacent bonding sites include a carboxyl group, a hydroxyl group, or an amino group.

US Pat. No. 10,192,720

PLASMA PROCESSING APPARATUS

Hitachi High-Technologies...

1. A plasma processing apparatus comprising:a processing chamber disposed inside a vacuum vessel having a sidewall made of a dielectric material having transparency or translucency, the processing chamber configured to be internally reduced in pressure;
a stage disposed at a lower portion inside the processing chamber and configured to mount a wafer to be processed thereon;
a coil disposed around outer side of the sidewall, the coil configured to be supplied with radio-frequency power and form plasma above the stage in the processing chamber;
a lamp disposed above the coil outside the vacuum vessel, the lamp configured to radiate light onto the wafer from an upper portion of the processing chamber;
a reflector disposed around an outer side of the coil, the reflector configured to reflect the light to radiate towards an inside of the processing chamber; and
a member disposed between the lamp and the stage, the member being configured to change direction of the light from the lamp and suppress expansion of the light toward an outside of the processing chamber.

US Pat. No. 10,192,716

MULTI-BEAM DARK FIELD IMAGING

KLA-Tencor Corporation, ...

1. An apparatus, comprising:an electron source;
at least one optical device configured to produce a plurality of primary beam lets utilizing electrons provided by the electron source, the at least one optical device further configured to deliver the plurality of primary beam lets toward a target; and
an array of multi-channel detectors configured to receive a plurality of image beam lets emitted by the target in response to the plurality of primary beamlets, the array of multi-channel detectors further configured to render an array of dark field images to form a contiguous dark field image, wherein each multi-channel detector of the array of detectors comprises a set of detector elements.

US Pat. No. 10,192,711

FLUID INJECTOR FOR X-RAY TUBES AND METHOD TO PROVIDE A LIQUID ANODE BY LIQUID METAL INJECTION

Siemens Aktiengesellschaf...

1. A fluid injector for x-ray tubes to provide a liquid anode by liquid metal injection, comprising:a device which injects fluid from an opening in a chamber of the device as a fluid jet generated by an arrangement for changing a volume within the chamber;
a pipe connected to the chamber of the device; and
a reservoir for storing the anode material, said reservoir being fluidically connected by the pipe with the chamber of the device;
wherein the pipe comprises a part formed in a fluid flow direction with a shape to block fluid flow from the chamber to the reservoir during injection.

US Pat. No. 10,192,707

FUSE ASSEMBLY WITH REPLACEABLE CASING

1. A fuse assembly comprising:a casing having two slots defined through a first end thereof, the casing having a room defined therein which communicates with the two slots, two protrusions extending from an inside of the room, the casing having two insertion recesses defined through the first end thereof, each of the insertion recesses having a positioning member formed in an inside surface thereof;
a conductive member located in the casing and having a first end extending through a second end of the casing, the conductive member including two blades which are located with a gap formed therebetween, a fuse connected between the two blades, each of the two blades having a hole, the two protrusions engaged with the two holes of the two blades;
a cap having an open bottom which is detachably mounted to the first end of the casing, two arms respectively extending from two ends of the cap and each arm having a hook end, the two arms inserted into the two insertion recesses and the two hook ends being detachably hooked to the two positioning members, and
a light member connected to the cap and having a bulb and a leg portion which is electrically connected to the bulb, the leg portion being electrically connected to a second end of the conductive member.

US Pat. No. 10,192,702

ELECTROMAGNETIC RELAY AND RELAY DEVICE

PANASONIC INTELLECTUAL PR...

1. An electromagnetic relay, comprising:a contact point including a fixed contact and a movable contact;
a driver including a coil and is configured to bring the movable contact into contact with the fixed contact and to separate the movable contact from the fixed contact;
a base having an opening and including a first wall section surrounding an accommodation space in which the contact point and the driver are accommodated;
a cover covering the opening of the base; and
at least one connection terminal configured to electrically connect the coil to an external connection body, wherein
the first wall section of the base has a through hole communicating with an interior and an exterior of the accommodation space,
the at least one connection terminal includes:
a first terminal section accommodated in the base and electrically connected to the coil; and
a second terminal section protruding outside the base through the through hole and electrically connected to the external connection body,
the cover includes a second wall section disposed to leave a space from the first wall section having the through hole, and the second terminal section lies in the space, and
the space in which the second terminal section lies is sealed with a sealant.

US Pat. No. 10,192,700

AIR CIRCUIT BREAKER HAVING AN IMPROVED ELECTRIC ARC QUENCHING CHAMBER

SCHNEIDER ELECTRIC INDUST...

1. An air circuit breaker, comprising:two separable electrical contacts connected to electric current input and output terminals; and
a chamber for quenching an electric arc, to extinguish the electric arc formed during the separation of the electrical contacts, said quenching chamber comprising a stack of splitter plates that are spaced apart from one another, and lateral walls placed on either side of the stack, the splitter plates being fixed to the lateral walls, each lateral wall including a thermosetting-resin impregnated polyamide fabric and being devoid of glass fibres,
wherein the quenching chamber furthermore includes protective elements made of crosslinked polyamide, said protective elements being placed inside the quenching chamber, along the lateral walls on either side of the stack, in junction zones between the lateral walls and the splitter plates, the protective elements covering corners of the splitter plates which corners are adjacent to the lateral walls, so as to separate these corners of the splitter plates from the electrical contacts, and
wherein each protective element comprises seats and a plurality of fingers, the seats being bounded by the fingers, one corner of the splitter plate of the stack being received inside each seat, and each pair of fingers in the plurality of fingers having one of the splitter plates disposed therebetween,
wherein the protective elements extend substantially parallel to the stack, from a lower end of the stack to a lower edge of an upper arcing horn situated above the stack, such that are there splitter plates included in the stack of splitter plates which are not covered by the protective elements.

US Pat. No. 10,192,699

POWER SEAT OPERATION DEVICE AND POWER SEAT

NHK Spring Co., Ltd., Yo...

1. A power seat operation device comprising:a dial that is rotatably installed at a side face of a power seat provided with a plurality of moving mechanisms, one of the plurality of moving mechanisms being selected by rotational operation of the dial, and an interior and an exterior of the dial being in communication through an opening formed at a peripheral outer side of the dial;
a switch that is attached inside the dial, the switch actuating the selected moving mechanism;
a knob that is installed inside the dial at a seat width direction outer side of the switch, that is rotatably supported by the dial, that includes an operation portion inserted through the opening so as to project outside the dial, and that is capable of operating the switch by operation of the operation portion; and
a channel that is formed inside the dial by the dial and the knob, the channel being partitioned from the switch, and, in cases in which liquid has infiltrated into the dial through the opening in a state in which the opening is positioned at an upper side of the switch, the channel letting the liquid flow downward to a lower side of the switch so as to discharge the liquid to outside the dial.

US Pat. No. 10,192,696

LIGHT-EMITTING ASSEMBLY FOR KEYBOARD

APPLE INC., Cupertino, C...

1. A keyboard assembly, comprising:a switch housing defining a switch opening and a light source recess formed in a sidewall of the switch opening;
a tactile dome positioned at least partially within the switch opening;
a keycap positioned above the switch housing and configured to move toward the tactile dome when pressed; and
a light-emitting assembly positioned within the light source recess of the switch housing, and comprising:
a light source;
a luminescent structure at least partially enclosing the light source and defining a front face of the light-emitting assembly;
an opaque material defining a rear face of the light-emitting assembly, the rear face being positioned opposite the front face;
a first sidewall defining a first side face of the light-emitting assembly; and
a second sidewall opposite the first sidewall and defining a second side face of the light-emitting assembly, wherein the switch housing is configured to receive light from each of the front face, the first side face, and the second side face and to guide the received light toward the keycap, wherein the opaque material is configured to prevent light from passing through it.

US Pat. No. 10,192,692

EXPLOSION-PROOF CROSS-TYPE LIMIT SWITCH

1. An explosion-proof limit switch (10) comprising:a housing (12);
a gear mechanism (24) arranged in said housing (12), said gear mechanism including a gear mechanism cover plate (38), a gear mechanism base plate (48) and at least one intermediate plate (42) arranged between the gear mechanism cover plate (38) and the gear mechanism base plate (48);
said intermediate plate (42) having at least one cutout (44) in which a first gearwheel (54) is arranged and at least one second cutout (46) in which a second gearwheel (58) is arranged;
said first gearwheel (54) having a first plug-through opening (56) and said second gearwheel (58) having a second plug-through opening (60);
a shaft (20) having an actuating lever (18) arranged outside the housing (12) and being rotatably supported in a first bearing arrangement (22) connected to the housing (12) and extending through the first plug-through opening (56) of the first gearwheel (54) in order to couple with the first gearwheel (54) in a torque transmitting manner and to radially support said first gearwheel (54); and
a rotary switch (30) arranged in the housing (12) and having a switch shaft (138) that is rotatably supported in a second bearing arrangement (106, 134) and extends through the second plug-through opening (60) of the second gearwheel (58) in order to couple with the second gearwheel (58) in a torque transmitting manner and to radially support said second gearwheel (58).

US Pat. No. 10,192,672

COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A coil component, comprising:a substrate; and
a coil pattern disposed on the substrate,
wherein the coil pattern includes a vertical region having a side surface perpendicular with respect to the substrate and a tapered region connected to the vertical region and having a side surface inclined with respect to the substrate,
in a cross section of the coil pattern, a minimum width of the tapered region is less than a minimum width of upper and lower surfaces of the coil pattern,
the vertical region and the tapered region form a trapezoidal shape and are made of the same material, and
wherein a spacing between coil pattern turns is between 0.15 and 0.45 times a width of a cross sectional shape of the coil pattern.

US Pat. No. 10,192,671

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component, comprising:a multilayer body including a plurality of insulator layers stacked together;
a plurality of inner conductors including at least a first inner conductor, a second inner conductor, a third inner conductor and a fourth inner conductor formed between the insulator layers and extended to a side surface of the multilayer body; and
a plurality of outer electrodes formed on both side surfaces of the multilayer body, the outer electrodes including at least a first outer electrode connected to the first inner conductor, a second outer electrode connected to the second inner conductor, a third outer electrode connected to the third inner conductor and a fourth outer electrode connected to the fourth inner conductor,
wherein each of the outer electrodes is formed on a single side surface so as not to extend over two side surfaces of the multilayer body, and
wherein the first outer electrodes and the second outer electrode are facing each other, and the first outer electrode and the second outer electrode differ in length in a direction in which the insulator layers are stacked.

US Pat. No. 10,192,663

COIL FOR A SWITCHING DEVICE WITH A HIGH-FREQUENCY POWER

1. A coil system comprising a coil and several windings,wherein a first winding of the coil provides a first winding diameter and a first winding spacing;
wherein a last winding of the coil provides a second winding diameter and a second winding spacing;
wherein the first winding diameter is larger than the second winding diameter;
wherein the first winding spacing is smaller than the second winding spacing;
wherein the coil system further comprises a coil former filling an interior cavity of the coil;
wherein the coil former provides four recesses extending along its longitudinal axis, separated by webs, which are 90° offset relative to one another with reference to the coil former;
wherein the coil former comprises synthetic material,
wherein the coil former provides a relative permittivity that is no greater than about 1.2;
wherein the windings of the coil are guided in a guide groove of the coil former; and
wherein a wire thickness of the coil is larger than a depth of the guide groove.

US Pat. No. 10,192,657

GROMMET AND WIRE HARNESS

Sumitomo Wiring Systems, ...

1. A grommet that is to be attached to a group of electrical wires and mounted to a vehicle body panel so as to block an opening in the vehicle body panel, the grommet comprising:a first cylindrical portion through which the group of electrical wires is inserted;
a second cylindrical portion that is formed shorter in an axial direction than the first cylindrical portion and surrounds the first cylindrical portion;
a seat portion that is constituted by an annular rubber elastic body that surrounds the second cylindrical portion and is capable of constriction in diameter, the seat portion having an annular unevenness portion capable of fitting around an edge portion of the opening in the vehicle body panel; and
an annular connection portion that elastically connects the first cylindrical portion and the seat portion,
wherein the seat portion has an approximately elliptical shape,
the connection portion has an inclined annular wall portion that forms an inclined annular surface that is inclined in the axial direction between the first cylindrical portion and the seat portion, the inclined annular wall portion supporting a base end portion of the second cylindrical portion, and
a plurality of rib portions are integrally provided on the inclined annular wall portion and the second cylindrical portion, the plurality of rib portions extending from an axially intermediate portion of the second cylindrical portion to the inclined annular wall portion on two sides in a major axis direction of the approximately elliptical shape, and projecting from the second cylindrical portion to a seat portion side.

US Pat. No. 10,192,647

PACKAGE COMPRISING IMPROVED MEANS OF DAMPENING IMPACT BETWEEN AN ASSEMBLY CONTAINING RADIOACTIVE MATERIALS AND THE COVER OF THE PACKAGING

TN INTERNATIONAL, Montig...

1. A package comprising:a packaging for storing and/or transporting radioactive materials;
an assembly containing radioactive materials housed in a cavity of the packaging extending along a longitudinal axis of the packaging and being closed by a cover crossed by said longitudinal axis; and
a system for dampening impact of the assembly against the cover, the system comprising at least one plastically deformable dampening device and a loading device,
wherein one of the loading device and deformable dampening device is mounted moveable on the cover in a plane orthogonal to the longitudinal axis of the packaging, and has means of self-centring relatively to the other of the loading device and the deformable dampening device which is provided on said assembly containing the radioactive materials, and
wherein the deformable dampening device is arranged between the assembly and the cover along the longitudinal axis of the packaging.

US Pat. No. 10,192,638

METHODS AND SYSTEMS FOR MANAGING PATIENT TREATMENT COMPLIANCE

WellDoc, Inc., Columbia,...

1. A computer-implemented method, comprising:receiving, over a network, application features for generating an application including instructions for using a treatment plan;
programmatically generating the application for a user to use on an electronic device by using the received application features;
receiving an activation code from the user to use the application, wherein the activation code is acquired by the user after the user receives authorization from a medical professional to use the application;
after receiving the activation code:
processing the activation code to determine if the user is authorized to use the application;
after determining that the user is authorized, authorizing the user to use and activate the application;
receiving input data from the user; and
using the input data from the user to evaluate user compliance with the treatment plan.

US Pat. No. 10,192,634

WIRE ORDER TESTING METHOD AND ASSOCIATED APPARATUS

MEDIATEK SINGAPORE PTE. L...

1. A wire order testing method for determining pin connection relationships between a memory device and an electronic device, the method comprising:testing the memory device with at least one test pattern to obtain at least one first data;
predicting at least one second data that is to be correspondingly obtained from testing of the memory device with the at least one test pattern according to mapping relationships between the test pattern and pins of the memory device; and
determining the pin connection relationships between the memory device and the electronic device according to the at least one first data and the at least one second data.

US Pat. No. 10,192,632

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:a memory cell array including a plurality of memory cells coupled between a common source line and a bit line; and
a voltage generator applying operating voltages to word lines coupled to the memory cells or discharging potential levels of the word lines,
wherein during a program verify operation, the voltage generator applies a program verify voltage and a pass voltage as the operating voltages to the word lines, and subsequently applies a set voltage to the common source line during a period in which the memory cells are turned on.

US Pat. No. 10,192,624

NON-VOLATILE MEMORY DEVICE INCLUDING DECOUPLING CIRCUIT

Samsung Electronics Co., ...

1. A non-volatile memory device comprising:a memory cell array including a plurality of planes;
a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, the page buffer being configured to receive a bit line voltage control signal (BLSHF) via a first node;
a decoupling circuit connected to the first node, the decoupling circuit including at least one decoupling capacitor, the decoupling circuit being configured to execute charge sharing via the first node; and
a BLSHF generator connected to the first node;
wherein the BLSHF generator is configured to generate the BLSHF, and
the first node is between the decoupling circuit and the BLSHF generator.

US Pat. No. 10,192,617

CIRCUIT AND ARRAY CIRCUIT FOR IMPLEMENTING SHIFT OPERATION

Huawei Technologies Co., ...

1. A circuit for implementing a shift operation, the circuit comprising:a resistive random-access memory, a first switch, a second switch, a third switch, and a fourth switch;
wherein the first switch is closed when a first end of the first switch is at a low level, the second switch is closed when a first end of the second switch is at a high level, the third switch is closed when a first end of the third switch is at a high level, and the fourth switch is closed when a first end of the fourth switch is at a low level;
wherein a second end of the first switch and a second end of the third switch are connected to a negative input end of the resistive random-access memory;
wherein a second end of the second switch and a second end of the fourth switch are connected to a positive input end of the resistive random-access memory;
wherein the first end of the first switch, the first end of the second switch, the first end of the third switch, and the first end of the fourth switch are connected to an output end of a previous-stage circuit for implementing the shift operation;
wherein a third end of the first switch and a third end of the second switch are connected to a bias voltage end; and
wherein a third end of the third switch and a third end of the fourth switch are connected to a ground end.

US Pat. No. 10,192,615

ONE-TIME PROGRAMMABLE DEVICES HAVING A SEMICONDUCTOR FIN STRUCTURE WITH A DIVIDED ACTIVE REGION

Attopsemi Technology Co.,...

1. An One-Time Programmable (OTP) memory, comprising:a plurality of OTP cells, at least one of the OTP cells comprising:
a resistive element; and
at least one semiconductor fin structure residing in a common well or on an isolated substrate, the semiconductor fin structure including a plurality of fins, at least one of the plurality of fins being covered by at least one MOS gate to divide the at least one of the plurality of fins into at least a first active region and a second active region, the first active region having a first type of dopant, and the second active region having the first type of dopant or the second type of dopant; the first active region coupled to one end of the resistive element, the other end of the resistive element coupled to a first voltage supply line, the second active region coupled to a second voltage supply line, and the MOS gate coupled to a third voltage supply line,
wherein the first and/or the second active regions of two or more of the plurality of fins are coupled together by at least one extended source/drain, and
wherein the resistive element can be configured to be programmable into a different resistance state by applying voltages to the first, second, and the third voltage supply lines.

US Pat. No. 10,192,614

ADAPTIVE READ THRESHOLD VOLTAGE TRACKING WITH GAP ESTIMATION BETWEEN DEFAULT READ THRESHOLD VOLTAGES

Seagate Technology LLC, ...

1. A device comprising:a controller configured to adjust a read threshold voltage for a memory by performing the following steps, wherein the controller is distinct from the memory:
estimating a gap between two adjacent default read threshold voltages using binary data from the memory;
determining, using the controller, statistical characteristics comprising at least a mean and a standard deviation of each of two adjacent memory levels of the memory based at least in part on a type of statistical distribution of the memory levels, a distribution of data values read from one or more cells using a plurality of discrete read threshold voltages associated with at least one of the two adjacent default read threshold voltages and the gap, wherein each of the plurality of discrete read threshold voltages associated with a first one of the two adjacent default read threshold voltages is obtained by adding a corresponding offset value to the first default read threshold voltage, wherein the corresponding offset values are relative to the first default read threshold voltage, wherein the first default read threshold voltage has a first set of non-zero offset values that are independent of each other;
computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and
updating the read threshold voltage with the adjusted read threshold voltage.

US Pat. No. 10,192,613

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first memory module;
a second memory module; and
a third memory module,
each of the memory modules having a memory cell array including a plurality of memory cells,
each of the memory modules having a first state to consume less electric power than in a second state, and
the first memory module having a greater number of memory cells than the second memory module;
a first control signal line coupled with the first memory module and the second memory module to transmit a control signal for controlling the first state and the second state to the first memory module and the second memory module;
a second control signal line coupled with the first memory module and the third memory module to transmit the control signal from the first memory module to the third memory module;
wherein a first wiring is disposed in the first memory module, and coupled between the first control signal line and the second control signal line for transmitting the control signal from the first control signal line to the second control signal line via the first wiring, and
wherein the first wiring is coupled with a first MOS transistor in the first memory module.

US Pat. No. 10,192,611

SENSING CIRCUIT, SET OF PRE-AMPLIFIERS, AND OPERATING METHOD THEREOF

NATIONAL TSING HUA UNIVER...

1. A set of pre-amplifiers of a sense amplifier, comprising:a first pre-amplifier, coupled to a first input terminal of the sense amplifier; and
a second pre-amplifier, coupled to a second input terminal of the sense amplifier;
wherein the first pre-amplifier and the second pre-amplifier respectively performs a discharging operation to discharge the first input terminal and the second input terminal of the sense amplifier after the first input terminal and the second input terminal of the sense amplifier are charged to a predetermined voltage; and
one of the first pre-amplifier and the second pre-amplifier amplifies a voltage difference between the first input terminal and the second input terminal of the sense amplifier by terminating the discharging operation of another of the first pre-amplifier and the second pre-amplifier;
wherein the first pre-amplifier comprises:
a first switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch is coupled to the predetermined voltage, the second terminal of the first switch is coupled to the first input terminal of the sense amplifier, and the control terminal of the first switch receives a pre-charge signal;
a second switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the first switch and the control terminal of the second switch is coupled to the second input terminal of the sense amplifier;
a third switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled to the second terminal of the second switch, the second terminal of the third switch is coupled to a ground, and a control terminal of the third switch receives an initializing signal; and
a first capacitor, having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the second terminal of the second switch.

US Pat. No. 10,192,610

METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER

Rambus Inc., Sunnyvale, ...

1. An integrated-circuit device comprising:a data transmitter having a data input to receive a data input signal, a timing input to receive a timing signal, and a data output to transmit a data output signal timed to the timing signal;
a strobe transmitter to transmit a transmit-strobe signal synchronized with the timing signal; and
a phase-control circuit to control a phase of the timing signal and the transmit-strobe signal, the phase-control circuit including:
memory to store at least one transmit state setting the phase of the timing signal and the transmit-strobe signal.

US Pat. No. 10,192,609

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

Rambus Inc., Sunnyvale, ...

1. A controller to control operations of a memory component, the controller comprising:a first circuit to transmit commands to the memory component, the commands including:
a first command that specifies a first data pattern to be stored in a first register of the memory component;
a second command that specifies a second data pattern to be stored in a second register of the memory component; and,
a third command to select one of the first data pattern or the second data pattern to be output by the memory component;
a second circuit to receive, from the memory component as a received data pattern, the one of the first data pattern or the second data pattern output by the memory component, as selected by the third command; and,
calibration circuitry to based on the received data pattern, adjust a timing of a timing reference signal for sampling data at the second circuit.

US Pat. No. 10,192,608

APPARATUSES AND METHODS FOR DETECTION REFRESH STARVATION OF A MEMORY

Micron Technology, Inc., ...

1. An apparatus comprising:a plurality of memory cells; and
a control circuit configured to monitor refresh request commands and to perform an action that prevents unauthorized access to data stored at the plurality of memory cells in response to detection that timing of the refresh request commands has failed to meet a refresh timing limit.

US Pat. No. 10,192,605

MEMORY CELLS AND SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC MATERIALS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a ferroelectric material comprising hafnium oxide, zirconium oxide, or a combination thereof, the ferroelectric material configured to exhibit asymmetric characteristics and configured to switch from a first polarization state to a second polarization state responsive to exposure to a first bias voltage and configured to change from the second polarization state to the first polarization state responsive to exposure to a negative bias voltage having a different magnitude than the positive bias voltage.

US Pat. No. 10,192,596

APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME

Micron Technology, Inc., ...

1. An apparatus, comprising:an input-output control circuit;
a memory array configured to store data, the memory array further including signal lines for accessing memory of the memory array;
control logic coupled to the input-output control circuit and the memory array, the control logic configured to provide, in a first mode, internal control signals responsive to receiving a read command that controls activation of a charge pump circuit to develop a full pumped voltage prior to driving signal lines to a target signal line voltage based on the full pumped voltage, and
wherein the control logic is configured to provide, in a second mode, internal control signals prior to receiving a read command that controls the charge pump circuit to develop a ready pumped voltage that is less than the full pumped voltage, the control logic further configured to provide control signals to control the ready pumped voltage based on temperature compensation information of the memory array.

US Pat. No. 10,192,591

MEMORY DEVICES HAVING SPECIAL MODE ACCESS

Micron Technology, Inc., ...

1. A memory device comprising a register, a memory array, and a serial interface controller configured to receive and operate using a serial message to access the register that controls operation of the memory array by storing bits, the serial message having a format that comprises:a command field of the serial message configured to enable the serial interface controller to access the register;
a register address field of the serial message immediately following the command field indicating an address of the register; and
a data field of the serial message immediately following the register address field;
wherein the serial interface controller is configured to receive the serial message, wherein the command field of the serial message comprises a command that the serial interface controller is configured to interpret as enabling write access to a special mode enable register of the memory device, wherein the address of the register is configured to identify the special mode enable register, wherein the data field of the serial message comprises data to be written into the special mode enable register that is configured, when written into the special mode enable register, to cause the memory device to operate according to a special mode of operation, wherein the special mode of operation comprises a one time programmable (OTP) access mode, a parameter page access mode, or a block lock access mode, or any combination thereof.

US Pat. No. 10,192,587

MOVIE ADVERTISING PLAYBACK SYSTEMS AND METHODS

Open Text SA ULC, Halifa...

1. A method of video production, comprising:receiving, in playback of a video, a command from a viewer to advance the play of the video, wherein advancement of the play of the video skips a proxy advertisement in the video, the receiving performed by a video player device having a transcoder embodied in at least one physical unit;
responsive to the command from the viewer to advance the play of the video, determining a location in the video to resume playback of the video, the determining performed by the video player device;
moving the proxy advertisement to the location in the video determined by the video player device, the moving performed by the video player device, the proxy advertisement including an ad request;
sending the ad request to an advertisement server, the sending performed by the video player device;
receiving an advertisement from the advertisement server, the receiving performed by the video player device; and
delivering the advertisement received from the advertisement server to the location in the video indicated by the proxy advertisement, the delivering performed by the video player device, the video player device to play the advertisement at the location.

US Pat. No. 10,192,584

COGNITIVE DYNAMIC VIDEO SUMMARIZATION USING COGNITIVE ANALYSIS ENRICHED FEATURE SET

International Business Ma...

1. A method of providing a summary of a media production comprising:receiving the media production in computer-readable form, by executing first instructions in a computer system;
dividing the media production into original segments having respective time stamps indicating a time order of the original segments, by executing second instructions in the computer system;
conducting a cognitive analysis of each of the original segments to extract at least one cognitive feature associated with each original segment, by executing third instructions in the computer system;
grouping the original segments into multiple clusters based on the cognitive features by identifying one or more predominant features for each given cluster based on segments making up the given cluster, by executing fourth instructions in the computer system;
selecting a representative segment for each of the clusters based on one or more selection factors which include a distance of a given segment to a centroid of its corresponding cluster, an emotion level of the given segment, an audio uniqueness of the given segment, or a video uniqueness of the given segment wherein the representative segment for a given cluster corresponds to one of the original segments within the given cluster, by executing fifth instructions in the computer system; and
combining the representative segments in time order according to their time stamps to form a media summary, by executing sixth instructions in the computer system.

US Pat. No. 10,192,581

REPRODUCING DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A reproducing device capable of reproducing content from an optical information recording medium in which the content is recorded in a form of a pit group including one or more pits shorter than an optical system resolution limit of the reproducing device, comprising:an irradiation section for irradiating the optical information recording medium with reproduction light;
a conversion section for converting, into reproduction signal indicative of the content, light which reflected off the optical information recording medium;
a signal quality evaluating section for evaluating quality of the reproduction signal converted by the conversion section; and
a spherical aberration correcting section for correcting a spherical aberration caused by the irradiation section, by using a result of evaluation of the quality of the reproduction signal which quality has been evaluated by the signal quality evaluating section; wherein
the signal quality evaluating section is an i-MLSE (Integrated-Maximum Likelihood Sequence Estimation) detecting section for (a) detecting an i-MLSE which is an evaluation index for evaluating a signal characteristic of the reproduction signal and (b) evaluating quality of the reproduction signal,
the optical information recording medium has a BCA (Burst Cutting Area) recording region, and
the reproducing device further comprises a BCA reproduction control section for reproducing information recorded in the BCA recording region.

US Pat. No. 10,192,575

SPLIT ACTUATOR WITH MULTIPLE HEAD STACK ASSEMBLIES BONDED TO BEARING SLEEVES

Seagate Technology LLC, ...

1. An apparatus, comprising:at least one actuator shaft;
first and second head stack assemblies coaxially located on the at least one actuator shaft, the first and second head stack assemblies each comprising:
at least one bearing having an inner race coupled to an outer surface of the at least one actuator shaft;
a bearing sleeve surrounding an outer race of the at least one bearing;
an E-block surrounding the bearing sleeve;
an annular gap between the E-block and the outer race of the at least one bearing;
a ring of bonding material filling the annular gap;
an access gap providing a fluid path to the annular gap from at least one of a top and a bottom of the E-block; and
a groove fluidly coupled to the annular gap and facing away from the access gap, the groove encompassing a greater volume than that of the annular gap.

US Pat. No. 10,192,569

INFORMING A SUPPORT AGENT OF A PARALINGUISTIC EMOTION SIGNATURE OF A USER

INTUIT INC., Mountain Vi...

1. A computer-implemented method for assisting a support agent assigned to interact with a user during a support encounter, comprising:receiving, at a computing device, an audio stream comprising audio of a user interacting with an application;
evaluating the audio stream to identify a collection of paralinguistic information present in the audio stream, wherein the paralinguistic information comprises a set of descriptors characterizing acoustic aspects of the audio that are distinct from verbal content of the audio;
determining, from the paralinguistic information, one or more attribute measures associated with the user interacting with the application; and
upon receiving a request to initiate a support encounter:
generating, before a support agent assigned to handle the support encounter interacts with the user and based on evaluating at least one of the attribute measures with an uplift model, a set of activities for the support agent to use when interacting with the user that increases a likelihood of achieving a specified outcome for the support encounter;
providing information content on a support agent interface before the support agent interacts with the user, the information content comprising the one or more attribute measures determined from the paralinguistic information and the generated set of activities, wherein the one or more attribute measures comprises an emotional state of the user responsive to at least one content item provided by the application; and
generating, before the support agent interacts with the user, a mockup of the application on the support agent interface, the mockup comprising the at least one content item.

US Pat. No. 10,192,565

CROSS PRODUCT ENHANCED HARMONIC TRANSPOSITION

Dolby International AB, ...

1. A system for decoding an audio signal, the system comprising:a core decoder for decoding a low frequency component of the audio signal;
an analysis filter bank for providing a plurality of analysis subband signals of the low frequency component of the audio signal;
a subband selection reception unit for receiving information associated with a fundamental frequency ? of the audio signal, and for selecting, in response to the information, a first analysis subband signal and a second analysis subband signal from the plurality of analysis subband signals;
a non-linear processing unit to generate a synthesis subband signal from the first analysis subband signal and the second analysis subband signal by modifying the phase of the first analysis subband signal and modifying the phase of the second analysis subband signal, and by combining the phase-modified first analysis subband signal and the phase-modified second analysis subband signal; and
a synthesis filter bank for generating a high frequency component of the audio signal from the synthesis subband signal;
wherein the information associated with the fundamental frequency ? of the audio signal is received in an encoded bit stream.

US Pat. No. 10,192,564

SIGNAL QUALITY-BASED ENHANCEMENT AND COMPENSATION OF COMPRESSED AUDIO SIGNALS

Harman International Indu...

1. A system for treatment of compressed audio signals, comprising:a processor;
a sampler executable by the processor to divide an audio signal into a series of sequential samples;
a signal quality detector executable by the processor to identify a consistent brick wall frequency of the audio signal spanning a plurality of the sequential samples at an outset of the audio signal and to determine a signal treatment indication proportional to the brick wall frequency; and
a signal enhancer executable by the processor to
sequentially receive and analyze one or more sample components of the audio signal to identify lost parts of the audio signal in the one or more sample components of respective sequential samples, and
apply to the audio signal, at a level in accordance with the signal quality indication, a corresponding signal treatment for each of the one or more sample components of respective sequential samples having a corresponding identified lost part.

US Pat. No. 10,192,560

ROBUST SPECTRAL ENCODING AND DECODING METHODS

Digimarc Corporation, Be...

1. A device for decoding a digital watermark embedded in an audio signal, wherein the digital watermark is embedded in the audio signal by adjusting signal values, the device comprising:a memory in which is stored blocks of the audio signal;
a processor in communication with the memory to obtain blocks of the audio signal, the processor configured with instructions to:
perform an initial synchronization of the digital watermark, distorted due to time scale change, by converting blocks of the audio to frequency domain data, pre-filtering the frequency domain data to produce first pre-filtered blocks, summing the first pre-filtered blocks to produce a first accumulated block, the first pre-filtered blocks being selected over a sufficiently long block of audio such that plural instances of watermark signal representing the same code at different time locations are accumulated, and correlating the first accumulated block with a pattern to detect a time scale of an embedded code signal; and
perform decoding of variable code data of the digital watermark at the detected time scale by correlating phase of the audio signal at the detected shift with a data signal pattern, wherein the processor is configured with instructions to decode the variable code data by correlating phase of the audio signal with a synchronization code signal to identify a start position of the variable code, and correlating phase of the audio signal with data code signals to detect data code signals encoded as the variable code data of the digital watermark.

US Pat. No. 10,192,559

METHODS AND APPARATUS FOR DECOMPRESSING A COMPRESSED HOA SIGNAL

Dolby Laboratories Licens...

1. A method of decoding a compressed Higher Order Ambisonics (HOA) representation of a sound or soundfield, the method comprising:receiving a bit stream containing the compressed HOA representation;
determining whether there are multiple layers relating to the compressed HOA representation;
decoding, based on a determination that there are multiple layers, the compressed HOA representation from the bitstream to obtain a sequence of decoded HOA representations, wherein a first subset of the sequence of decoded HOA representations corresponds to a first set of indices and a second subset of the sequence of decoded HOA representations corresponds to a second set of indices,
wherein the first set of indices is based on OMIN channels,
wherein, for each index in the first set of indices, a corresponding decoded HOA representation in the first subset is determined based on only a corresponding ambient HOA component,
wherein the second set of indices is determined based on at least one of the multiple layers, and
where, for an index n and a frame k,
wherein ?AMB,n(k?1) represents a corresponding ambient sound component and ?n,PS(k?1) represents a corresponding predominant sound component.

US Pat. No. 10,192,558

ADAPTIVE GAIN-SHAPE RATE SHARING

Telefonaktiebolaget LM Er...

1. A method in an encoder for allocating bits to a gain adjustment quantizer and a shape quantizer to be used for encoding a gain shape vector for a received audio signal, the method comprising:determining a current bitrate and a value for a first signal property of the audio signal;
identifying a bit allocation for the gain adjustment quantizer and the shape quantizer for the determined current bitrate and the determined value for the first signal property, by using information from a table indicating a number of bits to be allocated to the gain adjustment quantizer and the shape quantizer for each of a plurality of combinations of bitrate and values for the first signal property; and
applying the identified bit allocation when encoding the gain shape vector.

US Pat. No. 10,192,550

CONVERSATIONAL SOFTWARE AGENT

Microsoft Technology Lice...

1. A computer system comprising:an input configured to receive voice input from a user;
an automatic speech recognition (ASR) system for identifying individual words in the voice input, the ASR system configured to generate in memory a set of one or more words it has identified in the voice input, and update the set each time it identifies a new word in the voice input by adding the new word to the set;
a speech detection module configured to detect speech activity in the voice input, prevent a speech inactivity interval from commencing until a grammatically complete sentence is detected in the voice input, cause the speech inactivity interval to commence when the grammatically complete sentence is detected in the speech input, and determine whether the ASR system has identified any more words in the voice input during the speech inactivity interval; and
a response module configured to generate a response for output based on the set of identified words, in response to the detection of an end of the speech inactivity interval, the response module configured to output the generated response after the speech inactivity interval has ended and only if the ASR system has not identified any more words in the voice input during the speech inactivity interval such that the generated response is not output if one or more words are identified in the voice input during the speech inactivity interval.

US Pat. No. 10,192,548

METHOD AND APPARATUS FOR EVALUATING TRIGGER PHRASE ENROLLMENT

Google Technology Holding...

1. A computer-implemented method comprising:during a trigger phrase enrollment process:
receiving, at a speech recognition-enabled electronic device, a first audio signal corresponding to a user of the speech recognition-enabled electronic device speaking a trigger phrase, the first audio signal comprising a first number of frames having a measure of noise variability of background noise exceeding a noise variability threshold;
when a count of the first number of frames in the first audio signal satisfies a frame number threshold, prompting, by the speech recognition-enabled electronic device, the user to speak the trigger phrase again;
receiving, by the speech recognition-enabled electronic device, a second audio signal corresponding to the user speaking the trigger phrase again, the second audio signal comprising a second number of frames having the measure of noise variability of background noise exceeding the noise variability threshold; and
when a count of the second number of frames in the second audio signal dissatisfies the frame number threshold, training, by the speech recognition-enabled electronic device, a trigger phrase model with the second audio signal corresponding to the user speaking the trigger phrase again; and
after the trigger phrase enrollment process:
receiving, at the speech recognition-enabled electronic device and while the speech recognition-enabled electronic device is in a sleep mode, a third audio signal including an utterance of the trigger phrase spoken by the user; and
detecting, by the speech recognition-enabled electronic device and using the trigger phrase model trained during the trigger phrase enrollment process, the utterance of the trigger phrase in the third audio signal, the trigger phrase when detected in the third audio signal causing the speech recognition-enabled electronic device to wake from the sleep mode, the sleep mode comprising a power-saving mode of operation in which one or more parts of the speech recognition-enabled electronic device are in a low-power state or powered off.

US Pat. No. 10,192,541

SYSTEMS AND METHODS FOR GENERATING SPEECH OF MULTIPLE STYLES FROM TEXT

Nuance Communications, In...

1. A method for use in a text-to-speech system comprising a computer-implemented linguistic analysis component operative to generate a phonetic transcription based upon input text, a speech base comprising speech unit recordings associated with a plurality of styles of speech, and at least one computer-implemented speech generation component operative to generate output speech from stored speech unit recordings based at least in part on the phonetic transcription, the method comprising acts of:(A) receiving, by the linguistic analysis component, input text produced by a text-producing application, wherein the text produced by a text-producing application comprises a speech style indication indicating a style of speech to be output by the text-to-speech system for an associated segment of the input text;
(B) generating, by the linguistic analysis component, a phonetic transcription based at least in part on the input text, the phonetic transcription specifying a first style of speech of the plurality of styles of speech to be output by the at least one speech generation component for the segment of the input text; and
(C) generating, by the at least one speech generation component, output speech based at least in part on the phonetic transcription generated in the act (B), wherein the generating comprises the at least one speech generation component selecting, from the speech unit recordings in the speech base, speech unit recordings associated with a second style of speech of the plurality of styles of speech, the second style of speech being different than the first style of speech, and concatenating the selected speech unit recordings to generate output speech in the first style.

US Pat. No. 10,192,536

PEDAL BOARD AND SOUND EFFECT ADJUSTING DEVICE USING SAME

SWIFF TECHNOLOGY CO., LTD...

1. A sound effect adjusting device, comprising:an effect pedal including a second pins assembly;
a pedal board including a first housing, a three-way toggle switch mounted in the first housing, a microswitch mounted in the first housing and electrically connected with the three-way toggle switch, and a mounting member mounted on the first housing to attach to the effect pedal;
wherein,
the first housing includes an input interface, an output interface, a send interface and a return interface formed thereon;
the three-way toggle switch has a first contact blade electrically connected with the input interface, a second contact blade electrically connected with the send interface, and a third contact blade connected with the microswitch;
the mounting member has a first pins assembly electrically coupled to the second pins assembly and removably attached to the second pins assembly; wherein,
while the effect pedal is assembled with the pedal board, the microswitch is off, and actuates the three-way toggle switch so that the effect pedal is connected between the input interface and the output interface in series, or, the effect pedal is connected between the send interface and the return interface in series.

US Pat. No. 10,192,534

PERCUSSION INSTRUMENT

YAMAHA CORPORATION, Shiz...

1. A percussion instrument comprising:a shell having a wall portion and at least one opening;
a head attached to the shell and overlying the at least one opening of the shell; and
a speaker provided inside of the shell and oriented to output sound having a main direction of propagation towards the wall portion of the shell according to an input signal.

US Pat. No. 10,192,532

TELESCOPING MUSICAL DRUM

18. A telescoping musical drum, comprising:at least two truncated, conical annular bodies, which can be extended into overlapping end-to-end positions, wherein the open-locking mechanism is accomplished via the increasingly tight friction fit created by extending such concentric conical bodies, working in combination with a ridge or ridges surrounding the lower or upper inner or outer edge of each of said annular bodies that may fit into a groove surrounding the corresponding lower inner or upper outer edge of said adjacent annular body.

US Pat. No. 10,192,531

NONSLIP INSTRUMENT PICK

1. An apparatus for a finger of a user to play a stringed instrument, the finger having a finger diameter, the apparatus comprising:a string pick configured to pick strings of the stringed instrument, and having a tip end, a tail end opposite the tip end, a pick body extending between the tip end and the tail end that is substantially flat, has a first flat face and a second flat face opposite the first flat face, a periphery about the pick body extending between the first flat face and the second flat face, and is tapered at the tip end, the pick body also having a pick axis extending between the tip end and the tail end, a grip axis normal to the pick axis and intersecting the first flat face and the second flat face, a pick length as measured between the tip end and the tail end along the pick axis, and a maximum pick width as measured normal to the pick axis and through the pick body, the maximum pick width greater than the finger diameter, the string pick including a pair of opposing tail side tabs extending outwardly from the pick body, normal to both the pick axis and the grip axis, and defining the maximum pick width; and
an elastic securing band forming a loop about a band center axis, and having a finger end, a pick end opposite the finger end, a band length extending between the finger end and the pick end parallel with the band center axis, a tube wall thickness, a tubular inner surface extending between the finger end and the pick end, and a tubular outer surface opposite the tubular inner surface and extending between the finger end and the pick end, the elastic securing band configured to couple with the string pick via the tail side tabs, and to secure the string pick to the finger of a user via a conformal fit against the finger.

US Pat. No. 10,192,520

BACKLIGHT UNIT, DISPLAY PANEL AND DISPLAY DEVICE

SHANGHAI TIANMA MICRO-ELE...

1. A backlight unit, comprising:a light source having a plurality of light-emitting units that emit light in at least three different colors;
only one light guide plate having N preset regions, where N is a positive integer, and N>1; and
a backlight control unit controlling the light-emitting units to provide light to the preset regions in the only one light guide plate,
wherein:
the only one light guide plate has a light incidence side and a side surface opposite to the light incidence side, and the N preset regions continuously extend from the light incidence side to the side surface of the only one light guide plate;
all light-emitting units in the light source are disposed at the light incidence side of the only one light guide plate, and the light emitted from the plurality of light-emitting units enters the N preset regions from the light incidence side of the only one light guide plate;
in the light-emitting units corresponding to a same preset region in the N present regions, the light-emitting units with a same color are connected in series;
the light-emitting units corresponding to different preset regions in the N present regions are independent;
the light emitted by the light source spreads in the preset regions in a convergent way;
the backlight control unit acquires image data information corresponding to the N preset regions, and derives chrominance and luminance information of an image corresponding to each preset region, by calculating the image data information corresponding to each preset region, wherein the chrominance and luminance information of the image corresponding to each present region comprises a ratio of a red component, a green component and a blue component; and
the backlight control unit then, based on the chrominance and luminance information of each preset region, determines an electric current for each red light-emitting unit, each green light-emitting unit and each blue light-emitting unit of each preset region, according to the ratio of the red component, the green component and the blue component.

US Pat. No. 10,192,518

DISPLAY METHOD AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display method, comprising:converting three-channel data of each of pixels in a target image to be displayed to four-channel data;
calculating a color different between the four-channel data and the three-channel data for each of the pixels;
decreasing, for pixels whose color difference of which meets a preset adjustment condition, a ratio of a numerical value of a newly added channel in the four-channel data with respect to the three-channel data to obtain an adjusted four-channel data; and
displaying the target image by using the adjusted four-channel data for the pixels the four-channel data of which is adjusted and using the four-channel data for the pixels the four-channel data of which is not adjusted;
wherein deceasing the ratio of the numerical value of the newly added channel in the four-channel data with respect to the three-channel data to obtain the adjusted four-channel data so that coordinate points of the adjusted four-channel data and coordinate points of the three-channel data belong to same margin ranges in a chrominance coordinate system.

US Pat. No. 10,192,513

CIRCUITS FOR PROCESSING A VOLTAGE OF A PIXEL ELECTRODE AND DISPLAY APPARATUSES

BOE TECHNOLOGY GROUP CO.,...

1. A circuit for processing a voltage of a pixel electrode, comprising:a first input terminal configured to input an original voltage of the pixel electrode;
a second input terminal configured to input a voltage of a common electrode; and
an output terminal configured to output a processed voltage of the pixel electrode,
wherein the circuit for processing a voltage of a pixel electrode is configured to superimpose the voltage of the common electrode on the original voltage of the pixel electrode, to acquire a voltage which is stable with respect to the voltage of the common electrode as the processed voltage of the pixel electrode,
wherein the circuit for processing a voltage of a pixel electrode further comprises:an operational amplifier having a negative phase input terminal connected to the ground through a first resistor and connected to an output terminal thereof through a second resistor;a third resistor having a first end connected to the first input terminal and a second end connected to a positive phase input terminal of the operational amplifier; and
a fourth resistor having a first end connected to the second input terminal and a second end connected to a positive phase input terminal of the operational amplifier;
wherein a resistance value of the second resistor and a resistance value of the fourth resistor satisfy:

wherein K is a superposition multiple of a dynamic fluctuation voltage waveform of the common electrode; R2 is a resistance value of the second resistor, and R4 is a resistance value of the fourth resistor, and
wherein the fourth resistor is a variable resistor.

US Pat. No. 10,192,511

DISPLAY DRIVING CIRCUIT AND PIXEL STRUCTURE

WUHAN CHINA STAR OPTOELEC...

1. A display driving circuit, comprising:a first latch for latching a first data voltage;
a second latch for latching a second data voltage;
a logic control unit having two logic control ends, four voltage input ends and a voltage output end, wherein an output end of the first latch and an output end of the second latch are respectively connected with one of the logic control ends, the four voltage input ends are respectively connected with four different preset voltages, and the logic control unit is used for selecting to output one of the four preset voltages to a pixel electrode via the voltage output end based upon a first data voltage and a second data voltage input by the two logic control ends.

US Pat. No. 10,192,509

DISPLAY APPARATUS AND A METHOD OF OPERATING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus, comprising:a timing controller configured to generate a mode selection signal and output image data in response to input image data, the mode selection signal indicating a first operation mode or a second operation mode;
a first data driver configured to generate first through M-th data voltages and (M+1)-th through N-th data voltages in response to the mode selection signal and the output image data, and to apply the first through N-th data voltages to first through N-th data lines, respectively, where M is a natural number and N is a natural number greater than M; and
a display panel connected to the first through N-th data lines,
wherein, during a first duration of the first operation mode, each of a polarity pattern of the first through M-th data voltages and a polarity pattern of the (M+1)-th through N-th data voltages repeats a first polarity pattern,
wherein, during a first duration of the second operation mode, the polarity pattern of the first through M-th data voltages repeats the first polarity pattern, and the polarity pattern of the (M+1)-th through N-th data voltages repeats a second polarity pattern different from the first polarity pattern,
wherein the first data driver includes:
a digital-to-analog converter configured to generate the first through N-th data voltages in response to the mode selection signal, a polarity control signal and the output image data, wherein the mode selection signal and the polarity control signal are directly provided to the digital-to-analog converter; and
an output buffer configured to output the first through N-th data voltages to the first through N-th data lines.

US Pat. No. 10,192,506

DRIVING METHOD FOR DISPLAY PANEL, TIMING CONTROLLER AND LIQUID CRYSTAL DISPLAY

Shenzhen China Star Optoe...

1. A liquid crystal display, comprising:a timing controller for outputting a timing control signal;
a display driving circuit including a source driver and a gate driver for receiving the timing control signal, wherein the source driver generates a data driving signal according to the timing control signal, and the gate driver generates a scanning driving signal; and
a liquid crystal display panel including multiple data lines, multiple scanning lines and multiple pixel units, wherein the scanning line receives the scanning driving signal and the data line receives the data driving signal in order to control a corresponding pixel unit to display;
wherein, the timing controller comprises:
a control circuit for outputting a first frequency switching instruction when an image frame to be displayed is detected as an overloaded image;
a signal generation circuit connected with the control circuit for switching an operation frequency from a first frequency to a second frequency in a switching moment of adjacent frames according to the first frequency switching instruction, and using the second frequency to output the timing control signal to the source driver such that after the source driver receives the timing control signal, the source driver outputs the data driving signal having a lower frequency to drive the display panel to display the overloaded image;
the control circuit is further used for outputting a second frequency switching instruction when an image frame to be displayed is detected as a non-overloaded image;
the signal generation circuit is further used for switching the operation frequency from the second frequency to the first frequency according to the second frequency switching instruction, and using the first frequency to output the timing control signal to the source driver such that after the source driver receives the timing control signal, the source driver outputs corresponding data driving signal to drive the display panel to display the non-overloaded image;
wherein, the second frequency is one half of the first frequency; and
wherein the overloaded image is defined as when the timing controller adopts the first frequency as the operation frequency to control the source driver to display an image frame to be displayed, the power consumption of the source driver exceeds a preset power consumption value, and the image frame to be displayed is an overloaded image.

US Pat. No. 10,192,490

PIXEL ARRAY AND DISPLAY CIRCUIT FOR VIRTUAL REALITY WITH TWO DISPLAY MODES

EVERDISPLAY OPTRONICS (SH...

1. A pixel array with two display modes, comprising a plurality of rows of pixel circuits, each of the pixel circuits comprising:a first transistor comprising a first end connected to a power supply terminal, a second end, and a control end accessing a first enable signal,
a second transistor comprising a first end connected to a display device, a second end connected to the second end of the first transistor, and a control end accessing the first enable signal;
a third transistor comprising a first end connected to the power supply terminal, a second end connected to the second end of the first transistor, and a control end connected to a second enable signal; and
a fourth transistor comprising a first end connected to the display device, a second end connected to the second end of the second transistor, and a control end accessing the second enable signal;
a fifth transistor comprising a first end connected to the second end of the second transistor, a second end connected to the second end of the first transistor, and a control end connected to the power supply terminal through a capacitor;
a sixth transistor comprising a first end connected to a cathode of the capacitor, a second end, and a control end accessing the first control signal, the capacitor comprising an anode connected to the power supply terminal;
a seventh transistor comprising a first end connected to a second terminal of the sixth transistor, a second end connected to an initial voltage power supply terminal, and a control end accessing the first control signal; and
an eighth transistor comprising a first end connected to the initial voltage supply terminal and a second end connected to the display device;
wherein the first transistor and the second transistor are transistors of the same channel type, and the third transistor and the fourth transistor are transistors of the same channel type, and
wherein the first enable signal drives the display devices in each row of the pixel circuits to light line by line, and the second enable signal which accesses each row of the pixel circuits is the same so that the second enable signal drives display devices in each row of the pixel circuits to be lit at the same time.

US Pat. No. 10,192,487

PIXEL CIRCUIT HAVING THRESHOLD VOLTAGE COMPENSATION, DRIVING METHOD THEREOF, ORGANIC ELECTROLUMINESCENT DISPLAY PANEL, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit, comprising a light emitting element, a driving control module, a resetting control module, a charging control module, a writing control module, and a light emitting control module, wherein:a first control terminal and a second control terminal of the resetting control module are connected to a reset signal terminal, an input terminal of the resetting control module is connected to a first level signal terminal, a first output terminal of the resetting control module is connected to a first node, and a second output terminal of the resetting control module is connected to an output terminal of the driving control module and an input terminal of the light emitting element; the resetting control module is configured to reset the first node and the light emitting element;
a control terminal of the charging control module is connected to the reset signal terminal, an input terminal of the charging control module is connected to an output terminal of the light emitting control module and a first input terminal of the driving control module, and an output terminal of the charging control module is connected to a second node; the charging control module is configured to charge the second node through the light emitting control module and discharge the second node through the driving control module and the resetting control module;
a control terminal of the writing control module is connected to a scan signal terminal, an input terminal of the writing control module is connected to a data signal terminal, and an output terminal of the writing control module is connected to the second node; the writing control module is configured to write a data signal to the second node;
a control terminal of the light emitting control module is connected to a light emitting signal terminal, and an input terminal of the light emitting control module is connected to a second level signal terminal; the light emitting control module is configured to control the driving control module to drive the light emitting element to emit light;
a second input terminal of the driving control module is connected to the first node, and a third input terminal of the driving control module is connected to the second node; and
an output terminal of the light emitting element is connected to a third level signal terminal,
wherein the driving control module comprises a driving transistor having a gate connected to the first node, a first electrode connected to the input terminal of the charging control module and the output terminal of the light emitting control module, a second electrode connected to the input terminal of the light emitting element and the second output terminal of the resetting control module without intervention of any transistor.

US Pat. No. 10,192,485

PIXEL COMPENSATION CIRCUIT AND AMOLED DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel compensation circuit comprising:a capacitor;
a driving transistor;
a light emitting device;
a data signal writing circuit connected to a first end of the capacitor;
a high voltage writing circuit connected to the first end of the capacitor; and
a first reference voltage generation circuit connected to a second end of the capacitor, an anode of the light emitting device and a drain electrode of the driving transistor,
wherein a gate electrode of the driving transistor is connected to the second end of the capacitor, a source electrode of the driving transistor is connected to the high voltage writing circuit, and the drain electrode of the driving transistor is connected to the anode of the light emitting device; and
wherein a cathode of the light emitting device is connected to a common grounding electrode,
wherein the high voltage writing circuit comprises a high voltage signal terminal and a second transistor, and
wherein a control electrode of the second transistor is connected to a light emitting signal terminal, a source electrode of the second transistor is connected to the high voltage signal terminal, and a drain electrode of the second transistor is connected to the first end of the capacitor.

US Pat. No. 10,192,482

PIXEL COMPENSATION CIRCUITS, SCANNING DRIVING CIRCUITS AND FLAT DISPLAY DEVICES

Shenzhen China Star Optoe...

1. A pixel compensation circuit, comprising:a first controllable transistor having a control end, a first end, and a second end, the control end of the first controllable transistor connects to a first scanning line, and the first end of the first controllable transistor connects to one data line to receive a data voltage via the data line;
a driving transistor having a control end, a first end, and a second end, the control end of the driving transistor directly connects to the second end of the first controllable transistor, and the first end of the driving transistor connects to a first voltage end;
a second controllable transistor having a control end, a first end, and a second end, the control end of the second controllable transistor connects to a second scanning line, and the first end of the second controllable transistor connects to the second end of the driving transistor;
an OLED having an anode and a cathode, the anode of the OLED directly connects to the second end of the second controllable transistor, and the cathode of the OLED is grounded;
a first capacitor having a first end and a second end, the first end of the first capacitor connects to the control end of the driving transistor, and the second end of the first capacitor connects to the first end of the second controllable transistor; and
a second capacitor includes a first end and a second end, the first end of the second capacitor connects to the first end of the second controllable transistor and the second end of the first capacitor, and the second end of the second capacitor connects to a second voltage end.

US Pat. No. 10,192,476

OPERATING MODULE FOR DISPLAY AND OPERATING METHOD, AND ELECTRONIC DEVICE SUPPORTING THE SAME

Samsung Electronics Co., ...

1. An electronic device comprising a display driver configured to:in response to receiving display data, divide the display data into a plurality of segments corresponding to a plurality of display regions;
compare the display data in the plurality of segments to determine whether the display data in at least one segment is substantially same as the display data in another segment; and
based on the comparison outcome, selectively amplify a first display signal generated from the display data in the at least one segment or a second display signal generated from the display data in the another segment,
wherein the display driver comprises:
a data latch configured to transmit stored line data to a source driver;
data shift registers configured to sequentially transmit shifted line data to the data latch;
a logic circuit block including a data comparison circuit configured to compare the display data to be provided to the data shift registers,
wherein the data shift registers is grouped into groups of a certain number of members for each channel corresponding to each sub pixel,
wherein the source driver comprises:
source pads connected to output stages of amplifiers associated with each segment,
switches disposed between each output stage and each source pad, and
a MUX connected to the switches, and
wherein the display driver is configured to control the plurality of segments through the MUX.