US Pat. No. 10,193,806

PERFORMING A FINISHING OPERATION TO IMPROVE THE QUALITY OF A RESULTING HASH

NICIRA, INC., Palo Alto,...

1. A non-transitory machine readable medium storing a program that, when executed by at least one processing unit, generates a hash of a portion of a packet to process a packet, the program comprising sets of instructions for:generating a first hash from at least a portion of a packet header;
performing a finishing operation on the first hash to produce a resulting second hash, wherein the finishing operation comprises accumulating a length of the portion of the packet header into the hash by hashing a combination of the first hash and the length of the portion of the packet header; and
processing the packet based on the resulting second hash.

US Pat. No. 10,193,805

USER ORIENTED IOT DATA DISCOVERY AND RETRIEVAL IN ICN NETWORKS

Futurewei Technologies, I...

1. A method for accessing content in a network, comprising:receiving an interest message including semantics information to be matched to the content in the network, the semantics information excluding a name of the content;
accessing a memory to identify the content requested in the interest message using the semantics information, the memory including at least one of a content store (CS) caching the content and a forwarding information base (FIB) storing routing entries, the routing entries including content names with corresponding semantics information, forwarding faces and hop count;
aggregating the routing entries in the FIB having the same content name, the semantics information, forwarding faces and hop count to form an aggregated FIB; and
sending a FIB propagation message to neighboring network nodes, the FIB propagation message including at least changes made to the existing routing entries in the FIB.

US Pat. No. 10,193,804

METHOD OF FORWARDING DATA PACKETS, METHOD OF CREATING MERGED FIB KEY ENTRY AND METHOD OF CREATING A SEARCH KEY

HUAWEI TECHNOLOGIES CO., ...

1. A method of creating a key entry of a merged forwarding information base (FIB) for at least two routing instances (RI) on a network node, each RI having a corresponding RI FIB with corresponding RI FIB key entries and a corresponding routing instance identifier (RII), the method comprising:inserting a corresponding RII after at least a portion of a corresponding RI FIB key entry;
identifying a common root in a plurality of the RI FIB entries, wherein the merged FIB key entries have the corresponding RII immediately after the common root of the corresponding RI FIB key entries.

US Pat. No. 10,193,803

TRANSMITTING APPARATUS, RECEIVING APPARATUS AND CONTROLLING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A transmitting apparatus comprising:a packet generator configured to generate a packet comprising a header and a payload; and
a transmitter configured to transmit the generated packet,
wherein the header comprises a first field and a second field,
wherein the first field comprises a first value or a second value,
wherein the first value indicates that a length of the second field is a first length, and the second value indicates that the length of the second field is a second length, and
wherein, if the first field comprises the first value, the second field is represented as a pointer field, and if the first field comprises the second value, the second field is a concatenation of the pointer field and an added pointer field,
wherein the second field comprises a pointer value,
wherein the pointer value is an offset from a beginning of the payload to a first start position of at least one input packet that begins in the payload,
wherein if the first field comprises the second value, the header comprises a third field including one of a third value, a fourth value and a fifth value,
wherein the third value indicates absence of a fourth field and a fifth field in the packet,
wherein the fourth value indicates presence of the fourth field of which a length is 1 byte,
wherein the fifth value indicates presence of the fourth field of which the length is 2 bytes,
wherein the fourth field comprises length information indicating a length of the fifth field, and
wherein if the fourth field comprises the fifth value, the fourth field comprises least significant bits LSB and most significant bits MSB.

US Pat. No. 10,193,802

METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PROCESSING MESSAGES USING STATEFUL AND STATELESS DECODE STRATEGIES

ORACLE INTERNATIONAL CORP...

1. A method for processing a message containing type-length-value (TLV) elements, the method comprising:at a processing node including at least one message processor, wherein the processing node shares validation information about an ingress message among decode algorithms:
receiving the ingress message containing a plurality of TLV elements;
determining, using at least one message related attribute, whether the ingress message is to be processed using a stateless decode algorithm;
in response to determining that the ingress message is to be processed using the stateless decode algorithm, processing the ingress message using the stateless decode algorithm, wherein the stateless decode algorithm uses pointer arithmetic and length values associated with the plurality of TLV elements to decode the ingress message;
determining, using the stateless decode algorithm, whether the ingress message includes at least one TLV element indicating that the ingress message is to be further processed using a stateful decode algorithm; and
in response to determining that the ingress message includes the at least one TLV element indicating that the ingress message is to be further processed using the stateful decode algorithm, processing the ingress message using the stateful decode algorithm.

US Pat. No. 10,193,801

AUTOMATIC TRAFFIC MAPPING FOR MULTI-PROTOCOL LABEL SWITCHING NETWORKS

Juniper Networks, Inc., ...

1. A method comprising:executing, by a network device, a multiprotocol label switching protocol to direct a plurality of routers along a path to establish a label switched path along the path, the plurality of routers including a head-end label edge router that acts as an ingress to admit traffic into the label switched path and a tail-end label edge router that acts as an egress from the label switched path;
executing, by the network device, a path computation element communication protocol to generate a communication associating a label switched path community with the established label switched path;
transmitting, by the network device, in accordance with the path computation element communication protocol, and after the label switched path has been established to use one or more labels when admitting traffic into the label switched path, the communication to the head-end label edge router;
identifying, by the network device and based on traffic mapping rules, a mapping between a layer three network flow and the label switched path community;
executing, by the network device, a routing protocol used for routing advertising information to generate an advertisement advertising the mapping; and
transmitting, by the network device and in accordance with the routing protocol, the advertisement to the head-end label edge router so that the head-end label edge router is able to map the layer three network flow to the label switched path identified by the label switched path community and admit traffic corresponding to the layer three network flow into the label switched path identified by the label switched path community, and the layer three network flow identified in the advertisement by one or more of a destination address, a destination port, a source address, a source port, and a protocol.

US Pat. No. 10,193,800

SERVICE LABEL ROUTING IN A NETWORK

Level 3 Communications, L...

6. A telecommunications network, comprising:a service edge device in communication with a customer device to receive a request from the customer device to add a telecommunication service for a customer, wherein the telecommunication service comprises one of Firewall services or distributed denial of service (DDOS) protection;
metro edge devices in communication with the service edge device wherein an intermediate metro edge device of the metro edge devices on the telecommunication network is intermediate to two of the metro edge devices; and
a network management computing device comprising a processor configured to:
instantiate the telecommunication service on the service edge device and the metro edge devices, wherein instantiating the telecommunication service comprises associating a unique service label identifier to the requested telecommunication service; and
configure the service edge device and the metro edge devices to route information associated with the telecommunication service;
generate a segment label identifier associated with the service edge device and the metro edge devices;
wherein the service edge device and the metro edge devices route at least one data packet associated with the telecommunication service on the telecommunications network to the customer based at least on the unique service label identifier associated with the data packet, the at least one data packet comprising at least one of the unique service label identifier, the segment label identifier, and a frame associated with the instantiated telecommunication service;
wherein the intermediate metro edge device modifies the unique service label identifier based on network changes, and
wherein the service edge device and the metro edge devices comprise at least a portion of a Multiprotocol Label Switching (MPLS) network.

US Pat. No. 10,193,798

METHODS AND MODULES FOR MANAGING PACKETS IN A SOFTWARE DEFINED NETWORK

Telefonaktiebolaget LM Er...

1. A method, performed by an entry module, for managing packets in a communication system based on Software Defined Networking, wherein the communication system comprises the entry module, a radio network node, a mobile device, a forwarding module, a service module, a peer device and a management module for managing the forwarding module, the service module and the entry module, wherein a data plane of the communication system comprises the forwarding module, the service module and the entry module and a control plane of the communication system comprises the management module, wherein the mobile device is attached to the radio network node, wherein the method comprises:receiving an Internet Protocol (IP) packet from the peer device, wherein the IP packet includes a destination IP address associated with the mobile device;
obtaining, from the management module, a location value specifying the radio network node associated with the destination IP address;
associating the location value with the IP packet, wherein the location value is related to a location tag name, indicating the radio network node that serves the mobile device, thereby obtaining a packet; and
sending the packet, via the forwarding module, towards the radio network node as indicated by the location value of the location tag name.

US Pat. No. 10,193,797

TRIGGERED-ACTIONS NETWORK PROCESSOR

ORACLE INTERNATIONAL CORP...

1. A network processor, comprising:an input network stack configured to receive messages from an inbound network link;
a format decoder, coupled to the network stack, configured to: extract one or more fields from a given message; provide the one or more fields to application logic; determine a context for the given message; provide the given message and the context to a data handler, wherein the context is based on a message type and an identifier of the network connection on which the given message was received; determine a message status for the given message; and provide the message status to the data handler, wherein the message status includes a length of the given message and information specifying any error conditions associated with the given message;
the application logic, coupled to the format decoder, configured to: determine one or more trigger values based on the one or more fields and one or more trigger expressions; and provide the one or more trigger values to the data handler, wherein the one or more trigger expressions include checks on information in a payload of the given message; and
the data handler, coupled to the format decoder and the application logic, configured to determine one or more actions to be taken for the given message based on the context and the one or more trigger values, wherein the one or more actions to be taken include whether the given message is forwarded and one or more forwarding destinations, wherein the data handler is further configured to determine the one or more actions to be taken based on the information specifying any error conditions associated with the given message.

US Pat. No. 10,193,795

ROBUST DATA ROUTING IN WIRELESS NETWORKS WITH DIRECTIONAL TRANSMISSIONS

SONY CORPORATION, Tokyo ...

1. A wireless communication apparatus, comprising:(a) a wireless communication circuit configured for wirelessly communicating with other wireless communication stations;
(b) a computer processor coupled to said wireless communication circuit;
(c) a non-transitory computer-readable memory storing instructions executable by the computer processor; and
(d) wherein said instructions, when executed by the computer processor, perform steps comprising:
(i) communicating with the other wireless communication stations utilizing a routing protocol;
(ii) performing primary and secondary path discovery in establishing communications with a destination wireless communication station, through intermediate wireless communication stations;
(iii) determined by the processor that intermediate station of the primary and secondary path to be selected such that the antenna pattern for the primary and secondary path are spatially uncorrelated, using beamforming (BF) training information toward candidate intermediate stations;
(iv) transmitting data on the primary and the same data on the secondary path, for receipt by the destination wireless communication station toward overcoming link blockages of the primary path in response to data received on the secondary path; and
(v) wherein said instructions when executed by the computer are configured to provide reception at a destination station which is selected from the group of reception types consisting of: uncoordinated reception, coordinated reception by combining received signal powers, or coordinated reception with conditional reception from the secondary routing path.

US Pat. No. 10,193,794

MULTIPARTY CALL METHOD AND APPARATUS

HUAWEI TECHNOLOGIES CO., ...

1. A multiparty call method, applied in a process in which a transmit end makes a multiparty call with at least two receive ends, wherein the transmit end and the at least two receive ends are user equipment, wherein the method comprises:acquiring, by the transmit end, one piece of communications data to be transmitted to the at least two receive ends and identifiers of each of the at least two receive ends, wherein the identifiers of each of the at least two receive ends comprise internet protocol (IP) addresses of the at least two receive ends and port numbers for the at least two receive ends: and
sending, by the transmit end, the one piece of communications data and the identifiers of each of the at least two receive ends to a network side device.

US Pat. No. 10,193,793

BROWSER APPARATUS, RECORDING MEDIUM, SERVER APPARATUS, AND INFORMATION PROCESSING METHOD

SONY CORPORATION, Tokyo ...

1. A browser apparatus comprising:circuitry configured to
implement a web browser application including a first communication function section that sends a request to a web site and receives web content from the web site using a unicast protocol, and a second communication function section that receives web content multicast-distributed using a multicast protocol,
control, in response to an external input, the first communication function section of the web browser application to send a request to a web site and receive web content from the web site using the unicast protocol, wherein
the second communication function section receives a plurality of web content items,
the circuitry is configured to record only a web content item of the plurality of web content items, which has a particular URL address, on a recording medium, and
the circuitry is configured to control, when the web content received by the second communication function section has an error, the first communication function section to request the web content from the web site.

US Pat. No. 10,193,791

METHOD OF ALLOCATING WAVELENGTH AND WAVELENGTH ALLOCATION DEVICE

FUJITSU LIMITED, Kawasak...

1. A method of allocating a wavelength, the method comprising:first deciding whether a wavelength bandwidth of an optimum route for a demand has a free bandwidth to which the demand is able to be allocated;
allocating the demand to a bypass route other than the optimum route when the wavelength bandwidth of the optimum route does not have the free bandwidth;
acquiring a degree of influence of a section on the optimum route that is decided not to have the free bandwidth, by accumulating a difference in a route cost between the optimum route and the bypass route, the degree of influence being indicative of powerful influence on the bypass route when the demand is accommodated in the bypass route;
second deciding whether the acquired degree of influence becomes a predetermined value or more;
third deciding whether there is the wavelength link that can be added to the section in which the acquired degree of influence becomes a predetermined value or more;
adding an unused wavelength link to the wavelength bandwidth of the section in which there is the wavelength link that can be added to the section, to activate a laser of a transmitter of the section, and set a filter of a receiver of the section to filter the wavelength in the added wavelength link;
re-calculating the optimum route for the demand being allocated to the bypass route, after adding the unused wavelength link to the wavelength bandwidth of the section; and
allocating the demand to the optimum route obtained by the re-calculation in the case that the wavelength bandwidth of the optimum route obtained by the re-calculation has the free bandwidth, and a type of the demand is a momentary interruption toleration type that permits the momentary interruption of data.

US Pat. No. 10,193,789

HANDLING PORT IDENTIFIER OVERFLOW IN SPANNING TREE PROTOCOL

ARRIS Enterprises LLC, S...

1. A method comprising:receiving, by a network device, a spanning tree protocol (STP) bridge protocol data unit (BPDU);
extracting, by the network device, a port identifier value from the BPDU;
determining, by the network device, a fourteen-bit port number associated with the BPDU by decoding the least significant fourteen bits of the port identifier value; and
determining, by the network device, an eight-bit port priority associated with the BPDU by:
decoding the most significant two bits of the port identifier value; and
converting the most significant two bits of the port identifier value into the eight-bit port priority, the converting comprising padding the least significant six bits of the eight-bit port priority with zeroes.

US Pat. No. 10,193,788

SYSTEMS AND METHODS IMPLEMENTING AN AUTONOMOUS NETWORK ARCHITECTURE AND PROTOCOL

1. A computing node device comprising:a communication interface to communicate with other devices in a communications network; and
a networking interface to:
identify a plurality of computing nodes in the communications network, respective computing nodes of the plurality of computing nodes capable of being assigned a parent node of the computing node device;
verify an identity of a particular computing node of the plurality of computing nodes, the particular node capable of requesting to join the communications network;
transmit an identity of the computing node device to the particular computing node to enable the particular computing node to verify the identity of the computing node device;
when the identify of the particular computing node has been verified, transmit, using the communications interface, a message, to the particular computing node;
receive a response from the particular computing node, the response including metadata identifying a current load of the particular computing node;
based on the metadata identifying the current load of the particular computing node, identify the particular computing node as the parent node of the computing node device;
transmit, to the parent node, a request to register as part of the communications network.

US Pat. No. 10,193,787

METHOD OF NOTIFYING FUNCTION IDENTIFICATION INFORMATION AND COMMUNICATION SYSTEM

KABUSHIKI KAISHA TOSHIBA,...

1. A communication apparatus, comprising:a receiver configured to receive a probe request frame comprising a first SSID (Service Set Identifier) field from a first communication apparatus, wherein the first SSID field comprises first characters indicating a wireless communication function, the first SSID field of the probe request frame is defined in IEEE802.11 specification, and the wireless communication function is defined in a first specification different from the IEEE802.11 specification; and
a transmitter configured to transmit a probe response frame comprising a second SSID field to the first communication apparatus after a reception of the probe request frame, wherein the second SSID field comprises the first characters, and the second SSID field of the probe response frame is defined in the IEEE802.11 specification, the first SSID field and the second SSID field are defined as a field comprising an identifier of a service set in the IEEE802.11 specification.

US Pat. No. 10,193,786

WIRELESS ROUTERS UNDER TEST

Contec, LLC, Schenectady...

1. A universal tester for testing a plurality of wireless routers, comprising:a plurality of test slots, each test slot of the plurality of test slots configured to host a wireless router of a plurality of wireless routers; and
a plurality of sets of test connections, each set of test connections of the plurality of sets of test connections being associated with one test slot of the plurality of test slots,
wherein each set of test connections of the plurality of sets of test connections comprises:
a wireless networking test connection configured to test a corresponding wireless networking interface on a wireless router of the plurality of wireless routers,
an Ethernet test connection configured to test a corresponding Ethernet interface on a wireless router of the plurality of wireless routers, and
a MoCA test connection configured to test a corresponding MoCA interface on a wireless router of the plurality of wireless routers.

US Pat. No. 10,193,785

METHODS AND APPARATUS TO PREDICT END OF STREAMING MEDIA USING A PREDICTION MODEL

The Nielsen Company, LLC,...

1. An apparatus comprising:a predictor to determine a bandwidth rate associated with presentation of streaming media based on monitored traffic between a user device and a streaming media distributor;
a modeler to generate a prediction model based on characteristics of the bandwidth rate, the characteristics of the bandwidth rate including an amplitude of the bandwidth rate, a mean value of the bandwidth rate, and a standard deviation of the bandwidth rate; and
a forecaster to determine that a time when an output of the prediction model is below a minimum bandwidth threshold is a session end time for a streaming media session, the session end time corresponding to when the user device stops receiving the streaming media.

US Pat. No. 10,193,784

TRACKING VIRTUAL IP CONNECTION CHANGES

Cisco Technology, Inc., ...

1. A network device comprising:a memory; and
a processor, wherein the processor is configured to:
increment a sequence number associated with a virtual IP connection at the network device in response to a change of a status of the virtual IP connection, wherein the network device is a primary device configured to probe the virtual IP connection, wherein the network device is part of a mesh comprising a plurality of network devices, wherein the mesh comprises a standby network device configured to probe the virtual IP connection, and wherein the sequence number is attached to data corresponding to the status and is stored at the network device;
send, in response to a pull request from one of the plurality of network devices of the mesh, the data corresponding to the status of the virtual IP connection in response to the incremented sequence number of the virtual IP connection being greater than a requested sequence number, wherein the plurality of network devices are configured to pull incremental answer statuses at a configurable frequency; and
send, in response to the network device rebooting, the data corresponding to the status of the virtual IP connection to the standby network device with a request to overwrite all previously stored statuses.

US Pat. No. 10,193,783

SYSTEM FOR AGGREGATING STATISTICS ASSOCIATED WITH INTERFACES

NICIRA, INC., Palo Alto,...

1. A method of aggregating statistics for a set of interfaces associated with a logical forwarding element (LFE), the method comprising:for each particular interface in the set of interfaces associated with the LFE, defining at least one flow entry comprising (i) a set of matching fields that store flow-identifying parameters for matching with attributes of packets and (ii) a tag identifier that identifies the particular interface and that is not part of a matching field to match with packet attributes;
sending the flow entries to a plurality of physical forwarding elements (PFEs) that implement the LFE, at least a subset of the PFEs executing on host computers along with data compute nodes associated with the LFE;
receiving, from the plurality of PFEs, statistics generated by each PFE for each flow entry that has a tag identifier; and
aggregating the received statistics to produce overall statistics relating to each interface associated with the LFE.

US Pat. No. 10,193,781

FACILITATION OF MULTIPATH TRANSMISSION CONTROL PROTOCOLS

1. A method, comprising:receiving, by a network device comprising a processor, web site request data related to a request for a web site made by a mobile device;
receiving, by the network device, preference data associated with sending web site data related to the web site request data via a Wi-Fi connection of the network device or via a cellular network connection of the network device, wherein the preference data comprises benefit data related to a number of bytes that are deliverable via the Wi-Fi connection of the mobile device and the cellular network connection of the mobile device;
receiving, by the network device, resource data associated with the sending the web site data via the Wi-Fi connection of the network device or via the cellular network connection of the network device;
analyzing, by the network device, the preference data and the resource data, resulting in analyzed data; and
in response to a condition associated with the analyzed data being determined to have been satisfied, sending, by the network device, the web site data.

US Pat. No. 10,193,780

SYSTEM AND METHOD FOR ANOMALY ROOT CAUSE ANALYSIS

Futurewei Technologies, I...

1. A method comprising:receiving, by a processor from a radio network controller (RNC) of a network, one of a first anomaly data point, a second anomaly data point, and a third anomaly data point, the first, second, and third anomaly data points being related to a plurality of variables;
classifying, by the processor in response to receiving the first anomaly data point, the first anomaly data point as a relationship type anomaly, upon determining that the first anomaly data point is inside a magnitude bounding box and outside a principal component analysis (PCA) bounding box, wherein the PCA bounding box excludes all of a plurality of anomaly data points of a data set, and limits of the PCA bounding box are orthogonal to eigenvectors of the data set;
classifying, by the processor in response to receiving the second anomaly data point, the second anomaly data point as a joint magnitude anomaly, upon determining that the second anomaly data point is outside the magnitude bounding box, outside the PCA bounding box, and between major limits of the PCA bounding box;
classifying, by the processor in response to receiving the third anomaly data point, the third anomaly data point as both the relationship type anomaly and the joint magnitude anomaly, upon determining that the third anomaly data point is outside the magnitude bounding box, outside the PCA bounding box, and not between the major limits of the PCA bounding box;
determining, in response to classifying the first anomaly data point as the relationship type anomaly, at least a first subset of the variables related to the classified first anomaly data point;
performing, by the processor based on classifying the first anomaly data point as the relationship type anomaly, corrective action on the network in accordance with the classified first anomaly data point and the at least a first subset of the variables related to the classified first anomaly data point;
determining, in response to classifying the second anomaly data point as the joint magnitude anomaly, at least a second subset of the variables related to the classified second anomaly data point;
performing, by the processor based on classifying the second anomaly data point as the joint magnitude anomaly, corrective action on the network in accordance with the classified second anomaly data point and the at least a second subset of the variables related to the classified second anomaly data point;
determining, in response to classifying the third anomaly data point as both the relationship type anomaly and the joint magnitude anomaly, at least a third subset of the variables related to the classified third anomaly data point; and
performing, by the processor based on classifying the third anomaly data point as both the relationship type anomaly and the joint magnitude anomaly, corrective action on the network in accordance with the classified third anomaly data point and the at least a third subset of the variables related to the classified third anomaly data point.

US Pat. No. 10,193,777

WI-FI/BPL DUAL MODE REPEATERS FOR POWER LINE NETWORKS

1. A method for transmitting information, comprising:receiving a message, at a node of a power line network, from a first power line segment of the power line network;
detecting, at the node, an interruption in the power line network;
in response to detecting the interruption in the power line network, comparing, using a processor at the node, a transmission characteristic of a wireless transmission of the message and a transmission characteristic of a wired transmission of the message; and
transmitting the message, from the node, via one of the wireless transmission or the wired transmission, to a second power line segment of the power line network, based on the comparing of the transmission characteristic of the wireless transmission of the message and the transmission characteristic of the wired transmission of the message.

US Pat. No. 10,193,776

ANONYMIZATION OF TRAFFIC PATTERNS OVER COMMUNICATION NETWORKS

International Business Ma...

1. A computer program product for obfuscating communication traffic patterns occurring over a communication infrastructure including a computer server, the computer program product comprising:one or more non-transitory computer-readable storage devices and program instructions stored on at least one of the one or more non-transitory storage devices, the program instructions executable by a processor, the program instructions comprising:
instructions to detect, at a first communications device, data communication sessions with a second communications device via the computer server using a network protocol;
instructions to access, at the first communications device, a first traffic pattern based on the data communication sessions, the first traffic pattern determining communication occurrences between the first and the second communication devices over a first predefined time period;
instructions to access, at the first communications device, a second traffic pattern based on the data communication sessions, the second traffic pattern determining communication occurrences between the first and the second communications devices over a second predefined time period that occurs after the first predefined time period; and
instructions to generate, at the first communications device, based on a randomization process, a dummy data communication pattern for transmission to the second communications device, wherein the dummy data communication pattern is appended to the second traffic pattern for obfuscating a traffic pattern change between the first and the second traffic pattern at the computer server used to establish the communication sessions, wherein the generating of the dummy data communication pattern comprises:
instructions to determine, at the first communications device, a first information content value associated with the first traffic pattern;
instructions to determine, at the first communications device, a second information content value associated with the second traffic pattern;
instructions to compare, at the first communications device, the first and the second information content values; and
instructions to generate a first binary value based on the comparing determining the second information content value to be outside a predefined threshold range of the first information content value.

US Pat. No. 10,193,775

AUTOMATIC EVENT GROUP ACTION INTERFACE

Splunk Inc., San Francis...

1. A method comprising: causing display of an interface enabling a user to indicate information to control the operation of a service monitoring system to automatically identify and update a group of events from among a plurality of events in an event datastore; receiving user input via the interface including: an indication of group membership criteria; an indication of a causable group action; an indication of a precondition related to the causable group action; creating an event group policy definition in computer storage based at least in part on the group membership criteria, the causable group action, and the precondition; wherein one or more events of the plurality of events in the event datastore is each a notable event produced by a correlation search against stored key performance indicator (KPI) values, each KPI value produced by a search query that defines the KPI and that derives the KPI value from machine data associated with one or more entities that perform a service, each entity having an entity definition that identifies machine data associated with the respective entity, and each said entity definition associated with a service definition representing the service; wherein the machine data is produced by one or more components within an information technology environment and reflects activity within the information technology environment; and wherein the method is performed by one or more processing devices.

US Pat. No. 10,193,771

DETECTING AND HANDLING ELEPHANT FLOWS

NICIRA, INC., Palo Alto,...

1. A non-transitory machine readable medium that stores a program which when executed by at least one processing unit implements a forwarding element, the program comprising sets of instructions for:monitoring data flows associated with a network host to detect an elephant flow for which the forwarding element processes a plurality of packets, wherein the forwarding element encapsulates the packets of the elephant flow with an outer header; and
for at least two packets of the elephant flow, differentiating the two packets by (i) encapsulating a first packet of the elephant flow using a first header field value for a particular header field of the outer header and (ii) encapsulating a second packet of the elephant flow using a second header field value for the particular header field of the outer header,
wherein the different header field values for the particular header field break the elephant flow into at least two different mouse flows such that subsequent forwarding elements, to which the packets are sent from the forwarding element, send the packets of the detected elephant flow along different paths to reach a same destination.

US Pat. No. 10,193,751

SYSTEM, METHOD AND APPARATUS FOR CONFIGURING A NODE IN A SENSOR NETWORK

Senseware, Inc., Vienna,...

1. A method, comprising:receiving, by a sensor data control system, a request to change a configuration of a wireless node in a wireless sensor network at a monitored location, the wireless node supporting one or more sensors at the monitored location;
transmitting, by the sensor data control system, a configuration message for delivery to the wireless node, the configuration message including configuration information that enables the wireless node to change at least one configuration setting used by the wireless node in controlling a delivery of sensor data from the one or more sensors to the sensor data control system;
generating, by the sensor data control system, a first configuration hash value using a hash function having an input based on the at least one configuration setting identified by the request;
receiving, by the sensor data control system from a gateway device at the monitored location, a status message associated with the wireless node at the monitored location, the status message including a second configuration hash value generated by the wireless node using the hash function and having an input based on current configuration settings of the wireless node;
comparing, by the sensor data control system, the first configuration hash value to the second configuration hash value; and when the comparison indicates that the first configuration hash value is different from the second configuration hash value, retransmitting, by the sensor data control system to the gateway device, the configuration message based on the request to effect a change in the current configuration settings of the wireless node.

US Pat. No. 10,193,744

MASS RESTORATION OF ENTERPRISE BUSINESS SERVICES FOLLOWING SERVICE DISRUPTION

INTUIT INC., Mountain Vi...

1. A computer-implemented method for restoring a plurality of services of an application in a computer network following a service disruption, the method comprising:identifying, via a processor, one or more servers hosting at least one of the services;
identifying at least a first dependency between the at least one of the services and another one of the plurality of services;
generating a run list comprising one or more scripts for restoring the plurality of services in one or more successive phases, wherein each successive phase is determined based on the at least a first dependency, wherein each script is associated with one of the plurality of services and comprises instructions for one of starting, stopping, or restarting the service; and
based on the run list:
saving data of a downstream dependent service in a temporary restoration directory, wherein the downstream dependent service depends on the at least one of the services;
stopping the downstream dependent service;
restarting the at least one of the services;
restarting the downstream dependent service; and
loading the data of the downstream dependent service saved in the temporary restoration directory into the downstream dependent service.

US Pat. No. 10,193,734

METHOD FOR TRANSCEIVING SIGNAL IN A WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR THE SAME

LG ELECTRONICS INC., Seo...

1. A method for transceiving a signal in a wireless communication system supporting narrow-band (NB)-LTE, which is performed a terminal, the method performed by a terminal and comprising:receiving, from a base station, a narrow band synchronization signal;
acquiring time synchronization and frequency synchronization with the base station based on the narrow band synchronization signal and detecting an identifier of the base station; and
receiving, from the base station, broadcast information based on the detected identifier of the base station,
wherein the narrow band synchronization signal and the broadcast information are received through a narrow band (NB),
wherein the narrow band has a system bandwidth of 180 kHz and includes 12 subcarriers disposed at an interval of 15 kHz,
wherein the narrow band synchronization signal includes a narrow band primary synchronization signal and a narrow band secondary synchronization signal,
wherein the narrow band primary synchronization signal and the narrow band secondary synchronization signal are transmitted in different subframes, and
wherein the broadcast information is transmitted in a first subframe of a radio frame.

US Pat. No. 10,193,732

APPARATUS AND METHOD FOR SENDING AND RECEIVING BROADCAST SIGNALS

LG ELECTRONICS INC., Seo...

1. A broadcast signal receiver comprising:a tuner for tuning a broadcast signal;
a reference signal detector for detecting pilots from the tuned broadcast signal;
a de-framer for de-framing a signal frame of the broadcast signal and deriving service data based on a number of carriers of the signal frame; and
a decoder for performing error correction process on the derived service data;
wherein the number of carriers of the signal frame is determined by reducing a product of a control unit value and a reducing coefficient (k) from a maximum number of carriers,
wherein the control unit value is 96 for 8K Fast Fourier Transform (FFT), 192 for 16K FFT and 384 for 32K FFT and the reducing coefficient is an integer value which ranges from 0 to 4,
wherein the maximum number of carriers is 6913 for the 8K FFT, 13825 for the 16K FFT, and 27649 for the 32K FFT,
wherein the pilots comprises Scattered Pilots (SPs) and Continual Pilots (CPs) and the CPs comprises a common CP set and an additional CP set,
wherein a common CP of the common CP set does not overlap with a location of the SP and an additional CP of the additional CP set overlaps with the location of the SP, and
wherein the additional CP set for a specific SP pattern and a specific FFT size comprises a different number of additional CPs based on the reducing coefficient.

US Pat. No. 10,193,725

APPARATUS AND METHOD FOR SENDING AND RECEIVING BROADCAST SIGNALS

LG ELECTRONICS INC., Seo...

1. A broadcast signal transmitter, comprising:a Forward Error Correction (FEC) encoder configured to perform error correction processing on Physical Layer Pipe (PLP);
a time interleaver configured to perform time-interleaving on the PLP data;
a framer configured to generate a signal frame comprising the PLP data;
a frequency interleaver configured to perform frequency-interleaving on the signal frame; and
a waveform generator configured to generate a transmission signal comprising the signal frame,
wherein the signal frame comprises a bootstrap, a preamble, and at least one subframe,
wherein the bootstrap comprises first information for indicating system bandwidth, second information for emergency alert wake up, and third information for indicating structure of the preamble,
wherein the preamble comprises at least one preamble symbol,
wherein the at least preamble symbol carries Layer 1 (L1) signaling data for the signal frame,
wherein a first preamble symbol of the at least one preamble symbol comprises fourth information,
wherein the fourth information indicates a number of at least one remaining preamble symbol other than the first preamble symbol,
wherein the first preamble symbol of the at least one preamble symbol has a minimum number of carriers (NoCs),
wherein the first preamble symbol comprises fifth information related to an NoC of the at least one remaining preamble symbol when the preamble comprises a plurality of preamble symbols, and
wherein the first preamble symbol is a foremost preamble symbol among the plurality of preamble symbols.

US Pat. No. 10,193,723

APPARATUS FOR TRANSMITTING AND RECEIVING A SIGNAL AND METHOD OF TRANSMITTING AND RECEIVING A SIGNAL

LG ELECTRONICS INC., Seo...

1. A method of transmitting a broadcast signal, the method comprising:first encoding signaling data;
padding the first-encoded signaling data with zero bits, the zero bits filling information bits required for second encoding;
second encoding the padded signaling data by appending parity bits; and
puncturing a portion of the appended parity bits from the second-encoded signaling data and removing the padded zero bits to generate forward error correction (FEC)-encoded signaling data that is punctured and has zero bits removed;
mapping the FEC-encoded signaling data into signaling symbols that include channel bonding information;
third encoding data according to at least one code rate;
mapping the third-encoded data onto constellations according to a symbol mapping method that includes Non-uniform QAM (Quadrature amplitude modulation);
building a signal frame based on a preamble symbol including the FEC-encoded signaling data and data symbols including the third-encoded data;
modulating the signal frame according to an OFDM (Orthogonal Frequency Division Multiplexing) scheme; and
transmitting the broadcast signal carrying the modulated signal frame.

US Pat. No. 10,193,718

METHOD FOR DATA MODULATION IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR THE SAME

ELECTRONICS AND TELECOMMU...

1. A data modulation apparatus comprising:a single-to-differential (S2D) conversion part including a first amplifier operating based on a carrier wave signal and two transformers receiving an output signal of the first amplifier;
a first switch part transferring status of input data to the first amplifier based on the input data;
a differential amplification part receiving output signals of the S2D conversion part and amplifying the output signals of the S2D conversion part;
a differential-to-signal (D2S) conversion part receiving output signals of the differential amplification part and performing modulation on the output signals of the differential amplification part by converting the output signals of the differential amplification part to a single signal; and
a second switch part transferring the output signals of the differential amplification part to the D2S conversion part based on the input data,
wherein the first switch part and the second switch part are alternately turned on and off, and
the two transformers include a first transformer connected to a first inductor of the first amplifier and a second transformer connected to a second inductor of the first amplifier, wherein the first inductor and the second inductor are connected in parallel with the first amplifier.

US Pat. No. 10,193,709

METHOD FOR PROCESSING REQUEST MESSAGES IN WIRELESS COMMUNICATION SYSTEM, AND DEVICE FOR SAME

LG ELECTRONICS INC., Seo...

1. A method for processing request messages between heterogeneous systems in a wireless communication system, the method being performed by a gateway device and comprising:receiving an advertisement message about a service of a first node from the first node belonging to a first system;
when the advertisement message includes an indicator indicating that the service is shared with a second system, generating resources which represent the shared service and a resource for access control for the generated resources;
receiving a request message for retrieving information on resources corresponding to at least one service shared with the second system, which have been generated in the gateway device from a second node of the second system;
transmitting the information on the resources corresponding to the at least one service to the second node when the second node has an access right for the retrieving information on the resources corresponding to the at least one service;
receiving, from the second node, a request message for generating a resource corresponding to a service to be called selected from the information on the resources corresponding to the at least one service, as a child resource of the generated resources;
checking an access right for generation of the child resource; and
generating the child resource when the second node has an access right for generation of the child resource.

US Pat. No. 10,193,706

DISTRIBUTED RULE PROVISIONING IN AN EXTENDED BRIDGE

ARRIS Enterprises LLC, S...

1. A method comprising:receiving, by a controlling bridge (CB) in an extended bridge, a command to create or delete a packet classification rule for one or more virtual ports of the extended bridge;
determining, by the CB, a port extender (PE) of the extended bridge that hosts one or more physical ports corresponding to the one or more virtual ports; and
transmitting, by the CB, a message to the PE with instructions for creating or deleting the packet classification rule in a ternary content addressable memory (TCAM) of the PE,
wherein the CB manages a virtualized representation of the TCAM of the PE, and
wherein the virtualized representation includes an indication of a total capacity of the TCAM of the PE.

US Pat. No. 10,193,687

METHOD FOR ACQUIRING SYNCHRONIZATION, AND PHY TRANSMITTER AND PHY RECEIVER FOR CABLE NETWORK

Electronics and Telecommu...

1. A method for acquiring synchronization in a cable network, comprising:receiving, by a physical (PHY) receiver, a signal from a PHY transmitter; and
acquiring, by the PHY receiver, channel synchronization when a symbol in which a channel preamble exists is detected from the received signal and a position of a frequency at which a channel subcarrier exists is detected from the detected symbol by performing a cross correlation operation on the received signal and the channel preamble,
wherein the acquiring of the channel synchronization includes obtaining a position of a symbol having a cross correlation maximum value, and obtaining a subcarrier position on a frequency axis having the cross correlation maximum value.

US Pat. No. 10,193,677

METHOD FOR RECEIVING DOWNLINK SIGNAL BY MEANS OF UNLICENSED BAND IN WIRELESS COMMUNICATION SYSTEM AND DEVICE FOR SAME

LG ELECTRONICS INC., Seo...

1. A method of receiving a downlink signal by a user equipment (UE) from an eNB in a wireless communication system, the method comprising:receiving information on a second reference signal being QCL (Quasi Co-Location) with a first reference signal for demodulating the downlink signal from the eNB;
determining quasi-continuity of the second reference signal according to average density of the second reference signal existing within a window for determining quasi-continuity; and
receiving the downlink signal from the eNB based on whether or not the second reference signal is quasi-continuous.

US Pat. No. 10,193,673

METHOD FOR GENERATING AND TRANSMITTING PILOT SEQUENCE BY FORMING ASYMMETRIC SEQUENCE SET BY MEANS OF SHIFTING ON TIME AXIS IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method of transmitting pilot sequences to a receiver in a wireless communication system, the method performed by a transmitter and comprising:generating an asymmetric sequence set including a plurality of pilot sequences cyclically shifted at irregular intervals in a frequency domain;
mapping additional information represented by different bit values to the plurality of pilot sequences; and
transmitting a pilot sequence selected from the plurality of pilot sequences to a receiver,
wherein the plurality of pilot sequences are grouped based on shifting values, and
wherein the additional information is represented by a combination of a shared bit mapped as a same value to a specific group of the plurality of pilot sequences and a non-shared bit mapped as different values to each pilot sequence in the specific group.

US Pat. No. 10,193,671

SYSTEM AND METHOD FOR TRANSMISSION SYMBOL ARRANGEMENT FOR REDUCING MUTUAL INTERFERENCE

Huawei Technologies Co., ...

1. A method for operating a transmitting device, the method comprising:transmitting, by the transmitting device, a pilot signal associated with the transmitting device in a plurality of tones of a first transmission symbol in accordance with a spreading pattern in frequency domain associated with the transmitting device, without transmitting the pilot signal in a remainder of the tones in the first transmission symbol; and
transmitting, by the transmitting device, data to a receiving device in the plurality of tones of a second transmission symbol in accordance with the spreading pattern in the frequency domain, without transmitting the data or the pilot signal in a remainder of the tones in the second transmission symbol.

US Pat. No. 10,193,669

NIB COMP TRANSMISSION METHOD AND DEVICE IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for performing a Coordinated Multi-Point (CoMP) transmission at a first eNodeB in wireless communication system, the method comprising:receiving, by the first eNodeB from a second eNodeB, CoMP information including a CoMP hypothesis set and a benefit metric associated with the CoMP hypothesis set; and
performing, by the first eNodeB, the CoMP transmission based on the CoMP information,
wherein a CoMP hypothesis included in the CoMP hypothesis set is hypothetical physical resource block (PRB)-specific resource allocation information,
wherein the benefit metric quantifies a benefit assuming that the CoMP hypothesis is applied,
wherein the benefit metric has a value that is one of a value within a specific range or is a predefined value outside of the specific range, and
wherein, when the benefit metric has the predefined value, a benefit of the CoMP hypothesis is unknown.

US Pat. No. 10,193,667

METHOD FOR PERFORMING COMP OPERATION IN WIRELESS COMMUNICATION SYSTEM AND AN APPARATUS FOR SUPPORTING THE SAME

LG Electronics Inc., Seo...

1. A method of performing an inter-eNB Coordinated Multi-Point (CoMP) operation in a wireless communication system, the method comprising:receiving, by a first eNB, a first LOAD INFORMATION message from a second eNB requesting that the first eNB start the CoMP operation;
sending, by the first eNB, a second LOAD INFORMATION message to the second eNB requesting a Benefit Metric Information Element (IE);
receiving, by the first eNB, a third LOAD INFORMATION message from the second eNB, including the Benefit Metric IE;
coordinating, by the first eNB, resources for the CoMP operation; and
sending, by the first eNB, a fourth LOAD INFORMATION message to the second eNB, including results of the resource coordination,
wherein the first LOAD INFORMATION message includes an Invoke Indication IE, and the Invoke Indication IE includes CoMP Initiation IE for requesting the start of the CoMP operation.

US Pat. No. 10,193,663

METHOD AND APPARATUS FOR DETERMINING NUMBER OF HARQ PROCESSES IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...


wherein D denotes a downlink subframe, S denotes a special subframe and U denotes an uplink subframe, and,
wherein a maximum number of HARQ processes of the second serving cell is determined as a maximum number of HARQ processes of the first serving cell regardless of whether the second serving cell uses the TDD frame or the FDD frame.

US Pat. No. 10,193,656

SYSTEMS AND METHODS FOR ADAPTIVE DOWNLINK CONTROL INFORMATION SET FOR WIRELESS TRANSMISSIONS

HUAWEI TECHNOLOGIES CO., ...

1. A method for performing blind detection, the method comprising:identifying, by a user equipment (UE), a search space in a control channel, the control channel carrying signaling using at least some control formats in a set of control formats defined for the control channel;
determining, by the UE, a subset of control formats to search for in the search space based at least on a sub-carrier spacing configuration assigned to the UE, at least two sub-carrier spacing configurations being associated with different subsets of control formats, and the subset of control formats excluding one or more control formats in the set of control formats defined for the control channel;
searching, by the UE, for the subset of control formats in the search space without searching for the one or more control formats excluded from the subset of control formats; and
transmitting or receiving, by the UE, a data signal in accordance with control information detected in the search space.

US Pat. No. 10,193,655

METHOD AND APPARATUS FOR SCHEDULING MULTIMEDIA STREAMS OVER A WIRELESS BROADCAST CHANNEL

FUTUREWEI TECHNOLOGIES, I...

1. A method of broadcasting data, the method comprising:receiving a plurality of broadcast data streams, a first broadcast data stream including data processed with a first modulation and coding scheme, and a second broadcast data stream including the same data processed with a second modulation and coding scheme;
assigning the broadcast data streams into a plurality of frames, each frame being assigned to only one broadcast data stream, each frame carrying data from only its assigned broadcast data stream, index information carried by each frame of other frames assigned to the broadcast data streams being limited, per broadcast stream, to a sole instance of index information of only a single next frame carrying data from that same broadcast data stream, and the index information varying from frame-to-frame; and
causing the frames to be broadcast wirelessly.

US Pat. No. 10,193,647

GENERATING INTERFERENCE PATTERN FOR CONTROLLING INTER-CELL INTERFERENCE AND METHOD FOR SIGNALING THEREFOR

LG ELECTRONICS INC., Seo...

1. A method of transmitting, by a base station supported by a reference cell, a demodulation pilot signal for controlling inter-cell interference, the method comprising:determining a pattern length of a first interference pattern and a cyclic shift offset,
wherein the first interference pattern is included in an interference pattern set and is allocated to a first time resource of a predetermined reference resource, and
wherein the cyclic shift offset is used for distinguishing each interference pattern in the interference pattern set;
generating a cell-specific sequence related with a demodulation pilot signal in which a cyclic shift offset for the first interference pattern is applied,
wherein a pattern of the demodulation pilot signal is determined based on the pattern length of the first interference pattern and a number of frequency domain resources that are used for the demodulation pilot signal;
transmitting the demodulation pilot signal based on the cell-specific sequence through a resource allocated according to the pattern of the demodulation pilot signal,
wherein the demodulation pilot signal is used for signaling the first interference pattern.

US Pat. No. 10,193,643

METHOD FOR REPORTING CHANNEL STATE INFORMATION ON UNLICENSED BAND IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR SAME

LG ELECTRONICS INC., Seo...

1. A method of reporting channel state information on an unlicensed band by a user equipment to an evolved Node B (eNB) in a wireless communication system, the method comprising:receiving a triggering message of a sounding reference signal from the eNB to report the channel state information on the unlicensed band;
measuring interference on the unlicensed band;
determining a transmit power of the sounding reference signal according to the measured interference; and
if the interference measured on the unlicensed band is less than a threshold value, transmitting the sounding reference signal for reporting the channel state information on the unlicensed band to the eNB according to the determined transmit power,
wherein the channel state information on the unlicensed band is transmitted using a specific symbol of a subframe on which the sounding reference signal is transmitted.

US Pat. No. 10,193,642

MARGIN TEST METHODS AND CIRCUITS

Rambus Inc., Sunnyvale, ...

1. A receiver comprising:a data sampler having at least one sampler input to receive input data, the data sampler to sample the input data to provide a series of first data bits;
a multiplexer having:
a first multiplexer input coupled to the data sampler to receive the first data bits;
a second multiplexer input to receive a series of second data bits; and
a multiplexer output to issue the first data bits and the second data bits;
a multi-bit register having a series of delay elements coupled between the multiplexer output and the at least one sampler input, the multi-bit register to shift the first data bits and the second data bits sequentially through the delay elements as historical bits applied to the at least one sampler input; and
logic coupled to the multi-bit register to apply a function of the historical bits to the second multiplexer input.

US Pat. No. 10,193,637

METHOD AND SYSTEM OF NETWORK SWITCH OPTIMIZATION

The United States of Amer...

1. A method for determining a network configuration for delivery of entangled photons to a plurality of users such that any user of the plurality of users may share one of a pair of entangled photons with any other user; the network comprising a plurality of inputs; a plurality of switches, and a plurality of outputs operatively connected to the plurality of inputs by a plurality of optical fibers;the plurality of switches, each having a first switch input and a second switch input and a first switch output and a second switch output and being switchable between two states, a first state in which the first switch input is connected to the first switch output and the second switch input is connected to the second switch output and a second state in which the first switch input is connected to the second switch output and the second switch input is connected to the first switch output; the method comprising:
determining the minimum number of switches necessary to deliver entangled photon pairs from a predetermined number of sources to a predetermined number of users,
minimizing the loss experienced by an entangled photon passing through the plurality of switches by minimizing the number of switches that any one photon passes through by selecting only nondominated switch configurations;
determining the minimum number of equivalent network switch configurations and eliminating all but one of the equivalent network switch configurations; and
selecting an optimum network configuration by which the plurality of inputs and the plurality of outputs are operatively interconnected so as to enable the delivery of one photon of the pair of entangled photons to each of the plurality of output ports using a minimum number of switches in any route connecting each of the plurality of outputs to the plurality of inputs.

US Pat. No. 10,193,635

LOW-POWER APD BIAS CONTROLLER, BIAS CONTROL METHOD, AND PHOTOELECTRIC RECEIVER

InnoLight Technology (Suz...

1. An avalanche photodiode (APD) bias control method, comprising:acquiring a photocurrent intensity voltage;
generating a control signal by superposing the acquired photocurrent intensity voltage and a bias setting signal, wherein the control signal controls a voltage drop between an adjustable power supply and the APD;
adjusting an adjustable power supply output voltage that is output from the adjustable power supply and the bias setting signal simultaneously so that the voltage drop is within a target voltage drop range and a bias voltage applied across the APD approaches a target bias voltage that corresponds to an optical input power of an incident light that reaches the APD.

US Pat. No. 10,193,626

AUTO-DISCOVERY OF NEIGHBOR RELATIONSHIPS AND LIGHTING INSTALLATION SELF-MAPPING VIA VISUAL LIGHT COMMUNICATION

ABL IP HOLDING LLC, Cony...

4. A method comprising steps of:triggering a general illumination lighting device to modulate a visual light output from a general illumination source of the lighting device to repeat transmission of a packet of predetermined data a number of times,
the predetermined data of the repeatedly transmitted packet including an identification of the lighting device;
receiving, from another general illumination lighting device, a report of number of visual light receptions of the transmitted packet by the other general illumination lighting device; and
identifying the other general illumination lighting device as a neighbor of the general illumination lighting device based on detection of a predetermined relationship between the number of times of transmission and the number of visual receptions of the packet of predetermined data.

US Pat. No. 10,193,614

DATA-RECEIVING METHOD AND APPARATUS FOR RELAY STATION IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method of transmitting one or more signals in a wireless communication system, performed by an evolved NodeB (eNB), the method comprising:transmitting one or more reference signals to a relay node (RN),
wherein the one or more reference signals are transmitted on an antenna port 7;
transmitting the one or more signals in one or more downlink subframes,
wherein the one or more signals are eNB-to-RN transmissions on a R-PDCCH (relay-physical downlink control channel),
wherein the R-PDCCH is demodulated based on the one or more reference signals transmitted on the antenna port 7,
wherein the one or more downlink subframes are configured as one or more MBSFN (Multimedia Broadcast multicast service Single Frequency Network) subframes,
wherein each of the one or more downlink subframes includes a plurality of OFDM (orthogonal frequency division multiplexing) symbols in a time domain,
wherein, when six OFDM symbols in a second slot of the downlink subframe are used for the eNB-to-RN transmissions, the one or more reference signals are only mapped to one or more resource elements in a first slot of the downlink subframe.

US Pat. No. 10,193,608

METHOD FOR TRANSMITTING/RECEIVING CHANNEL STATE INFORMATION IN WIRELESS COMMUNICATION SYSTEM AND DEVICE THEREFOR

LG ELECTRONICS INC., Seo...

1. A method for transmitting, by a user equipment (UE), channel state information (CSI) in a wireless communication system, the method comprising:determining CSI for a serving cell of an unlicensed band; and
transmitting the CSI at a periodic CSI reporting instance within a reserved resource period (RRP) which is a time period occupied to transmit and receive data in the serving cell,
wherein another CSI prior to an initial rank indication (RI) reporting instance within the RRP is dropped or transmitted through an out of range (OOR) message.

US Pat. No. 10,193,607

DETERMINING A SOUNDING INTERVAL BASED ON THROUGHPUT

ARRIS Enterprises LLC, S...

15. A method for determining a sounding interval, wherein the method comprises:by an electronic device:
initializing a set of potential sounding intervals, wherein a given potential sounding interval specifies how often transmission beamforming is updated using sounding packets;
communicating, for at least another electronic device, first packets with and second packets without transmission beamforming for the set of potential sounding intervals, wherein, during the communication, an antenna pattern of the electronic device for use when communicating the first packets is updated;
receiving transmission statistics for the communication with at least the other electronic device;
calculating rank positions for the set of potential sounding intervals based at least in part on a performance metric associated with the transmission statistics and numbers of packets transmitted with transmission beamforming for the set of potential sounding intervals out of a total number of packets transmitted;
determining an output sounding interval based at least in part on the calculated rank positions;
repeating the communicating, receiving, calculating, and determining until a convergence criterion is achieved, wherein the convergence criterion corresponds to a difference in the output sounding interval determined in two or more instances of the repeating;
calculating frequencies, over multiple iterations, based at least in part on the rank positions for the set of potential sounding intervals;
determining, when the convergence criterion is achieved, a moment based at least in part on the calculated frequencies;
revising the set of potential sounding intervals; and
repeating, one or more times, the communicating, receiving, calculating, determining the output sounding interval, calculating the frequencies, and determining the moment based at least in part on the revised set of potential sounding intervals.

US Pat. No. 10,193,606

BEAM CONFIGURATION METHOD AND DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A beam configuration method applied to an electronic device, wherein the electronic device comprises a first plane, the first plane comprises at least two antenna array units, and the method comprises:determining whether an included angle between a ray that is perpendicular to the first plane and that extends outward from the electronic device and a ray pointing from the electronic device to a peer device is less than or equal to a preset angle; and
when the included angle between the ray that is perpendicular to the first plane and that extends outward from the electronic device and the ray pointing from the electronic device to the peer device is less than or equal to the preset angle, adjusting a phase difference between the antenna array units in the first plane, so that the array factors satisfy a condition of an end-fire state;
when the at least two antenna array units in the first plane are in uniform straight-line distribution, array factors of the antenna array units in the first plane are
wherein ?=?+kd cos ?, ? is a wave path difference between different antenna array units, ? is a phase difference between the two antenna array units,k is a quantity of waves, ? is a wavelength, d is a distance between the two antenna array units, and ? is an included angle between the ray that is perpendicular to the first plane and that extends outward from the electronic device and a ray in the direction of the first beam.

US Pat. No. 10,193,604

DEVICE, NETWORK, AND METHOD FOR RECEIVING DATA TRANSMISSION UNDER SCHEDULING DECODING DELAY IN MMWAVE COMMUNICATION

Futurewei Technologies, I...

1. A method for receiving a millimeter wave (mmWave) communication, comprising the operations of:receiving, at a user equipment (UE), a control transmission portion of the mmWave communication;
assigning scheduling restrictions to an earlier portion of the control transmission portion of the mmWave communication;
performing demodulation and decoding of the earlier portion of the control transmission portion;
prior to completion of the demodulation and decoding of the earlier portion of the control transmission portion, receiving, an earlier portion of a data transmission portion of the mmWave communication, the earlier portion of the data transmission portion of the mmWave communication corresponding to the earlier portion of the control transmission portion of the mmWave communication;
performing beamforming of the earlier portion of the data transmission portion of the mmWave communication using default parameters;
performing demodulation and decoding of a later portion of the control transmission portion; and
performing beamforming of the later portion of the data transmission portion of the mmWave communication using parameters obtained during the performing of demodulation and decoding of the later portion of the control transmission portion.

US Pat. No. 10,193,592

TECHNIQUES FOR DETECTING AND CANCELLING INTERFERENCE IN WIRELESS COMMUNICATIONS

QUALCOMM Incorporated, S...

1. A method for cancelling interference in wireless communications, comprising:performing an energy level detection of a received signal to determine an allocation size and position corresponding to an interfering device in the received signal;
determining an interference demodulation reference signal (DM-RS) and cyclic shift of the interfering device in the received signal;
determining, based at least in part on the allocation size and position and the interference DM-RS and cyclic shift, whether to apply successive interference cancellation on the received signal to cancel interference from the interfering device; and
applying the successive interference cancellation on the received signal based on determining to apply the successive interference cancellation.

US Pat. No. 10,193,582

INTERFERENCE CANCELLATION METHOD AND BASE STATION APPARATUS THEREFOR

Samsung Electronics Co., ...

1. A method of operating a base station for interference cancellation in a wireless communication system, the method comprising:receiving, from a target terminal, an uplink signal comprising at least one interference signal generated by at least one interference terminal;
identifying at least one dominant terminal from the at least one interference terminal based on a reception power of each of the at least one interference terminal;
performing primary decoding for the uplink signal;
generating a cancelling signal corresponding to an interference signal of the at least one dominant terminal if the primary decoding fails;
performing a cancellation by applying the cancelling signal to the uplink signal; and
performing secondary decoding for the uplink signal to which the cancelling signal has been applied.

US Pat. No. 10,193,578

FLEXIBLE POLAR ENCODERS AND DECODERS

1. A method of encoding data comprising:inputting data to a first non-systematic polar encoder having a first pipeline defining a first input and a first output, and capable of encoding a polar code of length nmax;
extracting, via at least one first multiplexer of size log nmax×1, a first polar code of length n modifying the first encoded output to set frozen bits to a known value to obtain a modified first encoded output;
inputting the modified first encoded output to a second non-systematic polar encoder having a second pipeline defining a second input and a second output, and capable of encoding a polar code of length nmax; and
extracting, via at least one second multiplexer of size log nmax×1, a second polar code of length n

US Pat. No. 10,193,575

DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN DIGITAL BROADCASTING SYSTEM

LG ELECTRONICS INC., Seo...

1. An apparatus for receiving a broadcast signal, the apparatus comprising:a tuner to receive the broadcast signal, wherein the broadcast signal includes a first region and a second region, wherein the first region is concatenated with the second region, wherein the broadcast signal includes known data, signaling information, and service data;
a signaling decoder to decode the signaling information for signaling the service data, wherein the signaling information includes a first field indicating a number of subframes in a frame;
a deinterleaver to deinterleave the service data; and
a decoder to decode the deinterleaved service data,
wherein the broadcast signal further includes fast service acquisition information between a physical layer and an upper layer,
wherein the signaling information further includes a second field for the fast service acquisition information,
wherein the service data includes a data packet which includes a header and a payload,
wherein the header of the data packet includes a pointer field which represents start position information of the payload, and
wherein the header of the data packet further includes a field which is related with stuffing bytes which fills a portion in front of the payload in the data packet.

US Pat. No. 10,193,569

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method, for a flash memory device, the decoding method comprising:executing at least one first iteration decoding procedure of a low density parity code (LDPC) on a first codeword according to a first clock signal by a correcting circuit;
generating, by a memory control circuit unit, a control parameter for adjusting a first frequency of the first clock signal to a second frequency of a second clock signal according to a first iteration count of the at least one first iteration decoding procedure in order to reduce a power consumption for decoding and maintain a decoding efficiency;
outputting, by the memory control circuit unit, the second clock signal to the correcting circuit according to the control parameter;
executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit;
outputting, by the memory control circuit unit, another clock signal to an adding circuit for outputting a valid codeword to a host system, wherein the another clock signal inputted to the adding circuit has a preset frequency which is different from the first frequency of the first clock signal or the second frequency of the second clock signal inputted to the correcting circuit for executing the at least one first iteration decoding procedure of the LDPC or the at least one second iteration decoding procedure of the LDPC;
correcting the second codeword, by the adding circuit, according to the another clock signal and error index information output by the correcting circuit,
wherein the error index information includes an error bit index, the error bit index is used to correct one or more data bits in the second codeword to generate the valid codeword; and
outputting, by the adding circuit, the valid codeword to the host system.

US Pat. No. 10,193,562

DIGITAL PHASE LOCKED LOOP CIRCUIT ADJUSTING DIGITAL GAIN TO MAINTAIN LOOP BANDWIDTH UNIFORMLY

Samsung Electronics Co., ...

1. A digital phase locked loop circuit comprising:a phase frequency detector configured to,
generate a first detection value associated with order between a first phase of a reference signal and a second phase of a fed-back signal, and
generate a second detection value based on the first detection value in response to the reference signal;
a bandwidth calibrator configured to,
amplify a signal level of the second detection value by a gain value, to generate an amplified detection value, and
adjust the gain value based on the first detection value;
a digital loop filter configured to generate a digital code based on the amplified detection value; and
a digital controlled oscillator configured to generate an output signal which has a frequency corresponding to the digital code, wherein
the fed-back signal is generated based on the output signal and is fed back to the phase frequency detector.

US Pat. No. 10,193,538

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first circuit block that is connected between a first power supply voltage line and a first reference voltage line;
a second circuit block that is connected between a second power supply voltage line and a second reference voltage line and transmits and receives signals with the first circuit block;
a resistor circuit that is connected between the second power supply voltage line and the second circuit block; and
a first clamp circuit that is connected between a line connected between the resistor circuit and the second circuit block and the first reference voltage line and clamps a potential difference between the line connected between the resistor circuit and the second circuit block and the first reference voltage line.

US Pat. No. 10,193,537

RANDOM DATA GENERATION CIRCUIT, MEMORY STORAGE DEVICE AND RANDOM DATA GENERATION METHOD

PHISON ELECTRONICS CORP.,...

1. A random data generation circuit, comprising:a phase difference detection circuit, configured to sample a first clock signal and a second clock signal based on a plurality of sampling clock signals, so as to detect a phase difference between the first clock signal and the second clock signal and output phase difference information; and
a random data output circuit, coupled to the phase difference detection circuit and configured to output random data according to the phase difference information.

US Pat. No. 10,193,535

OSCILLATION CIRCUIT, BOOSTER CIRCUIT, AND SEMICONDUCTOR DEVICE

ABLIC INC., Chiba (JP)

1. An oscillation circuit, comprising:a ring oscillator circuit in which odd stages of inverter circuits, each of which includes a PMOS transistor and an NMOS transistor that are connected to each other in series, are cascade connected such that the inverter circuits are connected to form a ring;
a first constant current element formed of a PMOS transistor configured to cause a predetermined current to flow to the inverter circuits;
a second constant current element formed of an NMOS transistor configured to cause a predetermined current to flow to the inverter circuits; and
a power supply circuit configured to generate a first bias voltage, a second bias voltage, and a second power supply voltage from a first power supply voltage,
the second power supply voltage being a constant voltage when the first power supply voltage is at a predetermined voltage or higher,
the PMOS transistor in each of the inverter circuits including a source connected to a drain of the PMOS transistor, which is the first constant current element, and a substrate to which the first power supply voltage is input,
the NMOS transistor in each of the inverter circuits including a source connected to a drain of the NMOS transistor, which is the second constant current element, and a substrate to which a ground voltage is input,
the PMOS transistor, which is the first constant current element, including a gate to which the first bias voltage is input, and a source and a substrate to which the second power supply voltage is input,
the NMOS transistor, which is the second constant current element, including a gate to which the second bias voltage is input, and a source and a substrate to which the ground voltage is input.

US Pat. No. 10,193,533

METHODS AND SYSTEMS FOR EVENT-DRIVEN RECURSIVE CONTINUOUS-TIME DIGITAL SIGNAL PROCESSING

The Trustees of Columbia ...

1. A continuous-time digital signal processor comprising:an event-grouping block, configured to receive a first input timing signal, a second input timing signal, and to generate an intermediate timing signal;
a first time delay block, configured to receive the intermediate timing signal and generate an output timing signal;
a second time delay block, configured to receive the output timing signal and generate the second input timing signal;
a two-channel memory configured to receive a first data input and a second data input and to generate a first intermediate data signal and a second intermediate data signal;
an arithmetic operation block, configured to receive the first intermediate data signal, the second intermediate data signal and to generate an output data signal, the arithmetic operation block comprising:
a scalar block configured to receive the second intermediate data signal and generate a scaled version of the second intermediate data signal; and
an adder configured to receive the first intermediate data signal and the scaled version of the second intermediate data signal, and generate the output data signal; and
a first-in-first-out (FIFO) memory configured to receive the output data signal and to generate the second input data signal.

US Pat. No. 10,193,532

METHOD OF OPERATING A FINITE IMPULSE RESPONSE FILTER

AGENCY FOR SCIENCE, TECHN...

1. A method of operating a finite impulse response filter comprising an input; an output; and a plurality of storage elements each coupled to the input via a sample switch and to the output via a transfer switch, the method comprising:during charging of the plurality of storage elements, applying a sample clock signal to each of the sample switches that achieves an operation mode where up to every one of the sample switches is simultaneously closed to connect all of the plurality of storage elements to the input; and
during averaging of the plurality of storage elements, applying a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output, wherein all the transfer switches are simultaneously closed during the averaging of the plurality of storage elements.

US Pat. No. 10,193,522

SINGLE PORT WIDE BAND IMPEDANCE MATCHING CIRCUIT WITH NARROW BAND HARMONIC BYPASS, WIRELESS COMMUNICATION DEVICE, AND METHOD FOR PROVIDING ANTENNA MATCHING

Motorola Mobility LLC, C...

15. A wireless communication device comprising:one or more transceivers;
a single signal port coupled to the one or more transceivers, the single signal port including a wide band signal;
an impedance matching circuit including a narrow band harmonic bypass, the narrow band harmonic bypass being configured to produce a short at a predetermined frequency, which corresponds to a harmonic of a lower frequency signal included as part of the wide band signal received at the single signal port;
an antenna port coupled to the single signal port via the impedance matching circuit; and
an antenna coupled to the antenna port.

US Pat. No. 10,193,512

PHASE-SHIFTING POWER DIVIDER/COMBINER ASSEMBLIES AND SYSTEMS

Werlatone, Inc., Brewste...

1. A power divider/combiner assembly comprising:a divider network for dividing a received divider-network input signal into N divider-network output signals, where N is an integer greater than seven, the divider network including at least one divider and at least one of each of first, second, and third divider phase-shift circuits, each divider having a divider input and a plurality of divider outputs and being configured to divide a divider input signal on the divider input into a divider output signal on each of the plurality of divider outputs, each divider phase-shift circuit being configured to produce a respective non-zero phase shift between divider output signals on an associated pair of divider outputs of an associated divider of the at least one divider, each first divider phase-shift circuit producing a first phase shift, each second divider phase-shift circuit producing a second phase shift that is more than the first phase shift, and each third divider phase-shift circuit producing a third phase shift that is more than the second phase shift;
N amplifiers, each amplifier amplifying one of the N divider-network output signals into a respective amplified signal; and
a combiner network for combining the N amplified signals into a combiner-network output signal, the combiner network including at least one combiner and at least one of each of first, second, and third combiner phase-shift circuits, with each combiner having a plurality of combiner inputs and a combiner output and being configured to combine combiner input signals on the plurality of combiner inputs into a combiner output signal on the combiner output, each combiner phase-shift circuit being configured to produce a respective non-zero phase shift between combiner input signals on an associated pair of combiner inputs of an associated combiner of the at least one combiner, each first combiner phase-shift circuit producing the first phase shift, each second combiner phase-shift circuit producing the second phase shift, and each third combiner phase-shift circuit producing the third phase shift.

US Pat. No. 10,193,480

PROPORTIONAL INTEGRAL REGULATING LOOP FOR DIGITAL REGULATOR DEVICE FOR MOTOR VEHICLE EXCITATION ROTARY ELECTRICAL MACHINE

Valeo Equipements Electri...

1. A proportional integral regulating loop (10) for a digital regulator device (2) for a motor vehicle excitation rotary electrical machine (1) configured to function as a generator which provides an output voltage (Ub+) adjusted by an excitation current (Ie), said digital regulator device (2) comprising a control device (11) for controlling said excitation current (Ie) and said regulating loop (10), said regulating loop (10) comprising:at an input, a measuring device (35) for measurement by sampling of said output voltage (Ub+) generating a measurement signal (Um);
an error calculation system (13) generating an error signal (e) equal to a difference between said measurement signal (Um) and a set point (U0);
a processing system (14, 15, 16, 17, 18, 20) for processing of said error signal (e) generating a regulating signal (Ysat), said processing system comprising in parallel a first amplifier (14), an integrator (15) and an anti-saturation system (23); and
at an output, a generation system (38) for generation of a control signal (PWM) controlling said control device (11) according to said regulating signal (Ysat),
said anti-saturation system (23) comprising a saturation detector (24) generating a disconnection signal (Cmd) controlling a switch (25) which disconnects said integrator (15, 29) of said error calculation system (13) in the case of detection of a state of saturation (SM) of said regulating signal (Ysat).

US Pat. No. 10,193,479

DEVICE FOR CONTROLLING A REGULATOR OF A MOTOR VEHICLE ALTERNATOR, AND ALTERNATOR COMPRISING THE CORRESPONDING REGULATOR

Valeo Equipements Electri...

1. Device (1, 2) for controlling a regulator of a motor vehicle alternator, of the type comprising firstly a control circuit (1) which generates a command (KEY_ON) for activation of said regulator, by taking to a first voltage higher than a predetermined high reference voltage a single-wire two-way communication line (6) which is connected to, secondly, a circuit (2) for detection of a state (KEY_DETECT) of said activation command (KEY_ON), said detection circuit (2) comprising means (7, 9) for generation of a fault signal from a flag (LAMP_ON) which indicates a fault of said alternator, by connection of said communication line (6) to a ground by at least one semiconductor switching element (7), by this means taking said communication line (6) to a second voltage lower than a predetermined fault voltage lower than said high reference voltage, and said control circuit (1) comprising means (4) for detection of said fault signal, wherein said control circuit (1) also transmits a pulse width modulated set signal with a maximum which is higher than said high reference voltage, and a minimum which is lower than a predetermined low reference voltage higher than said fault voltage, a duty cycle of said set signal being representative of a set voltage (V0) of said regulator.

US Pat. No. 10,193,447

DC TOPOLOGY CIRCUIT WORKABLE WITH VARIOUS LOADS THROUGH INCLUSION OF SUBTRACTOR

SHENZHEN CHINA STAR OPTOE...

1. A DC topology circuit, comprising a control chip, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first inductor, a first capacitor, and a second capacitor;the control chip comprises a control module and a subtractor; a first input terminal of the subtractor is inputted with an input voltage, a second input terminal of the subtractor is connected with a load-rated voltage and an output terminal of the subtractor is electrically connected with the control module;
a gate electrode of the first field effect transistor is inputted with a first control signal, a drain electrode of the first field effect transistor is connected with the input voltage, and a source electrode of the first field effect transistor is electrically connected to one terminal of the first inductor; a gate electrode of the second field effect transistor is inputted with a second control signal, a drain electrode of the second field effect transistor is connected the terminal of the first inductor, and a source electrode of the second field effect transistor is grounded; a gate electrode of the third field effect transistor is inputted with a third control signal, a drain electrode of the third field effect transistor is electrically connected to one other terminal of the first inductor, and the source electrode of the third field effect transistor is grounded; a gate electrode of the fourth field effect transistor is inputted with a fourth control signal, the drain electrode of the fourth field effect transistor outputs a output voltage, and the source electrode of the fourth field effect transistor is electrically connected with the other terminal of the first inductor; one terminal of the first capacitor is electrically connected with the terminal of the first inductor and one other terminal of the first capacitor is electrically connected to a first bootstrap pin of the control chip; one terminal of the second capacitor is electrically connected to the other terminal of the first inductor and one other terminal of the second capacitor is electrically connected with a second bootstrap pin of the control chip;
the first control signal, the second control signal, the third control signal, and the fourth control signal are all provided by the control module;
wherein the subtractor subtracts the input voltage and the load-rated voltage and outputs an operation result to the control module; the control module adjusts the first control signal, the second control signal, the third control signal, and the fourth control signal, to correspondingly control on/off of the first field effect transistor, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor.

US Pat. No. 10,193,431

LINEAR MOTOR

SANYO DENKI CO., LTD., T...

1. A linear motor, comprising:a stator;
a mover that moves a subject to be moved linearly along the stator; and
a multi-member spacer that is interposed between the mover and the subject to be moved, wherein
the stator includes a plurality of permanent magnets,
the mover includes a plurality of coils arranged to be opposed to the permanent magnets,
the multi-member spacer includes two or more members different in thermal conductivity,
the plurality of coils is interposed between the plurality of permanent magnets and the multi-member spacer in a direction orthogonal to a moving direction of the mover,
the mover comprises:
a plurality of teeth protruded toward the plurality of permanent magnets;
a plurality of slots defined by the plurality of teeth, the plurality of slots storing the plurality of coils; and
a core closing upper ends of the plurality of the slots, the plurality of teeth being coupled together via the core, the core comprising an electromagnetic steel plate,
the multi-member spacer is interposed between the core and the subject to be moved,
one of the two or more members of the multi-member spacer is in direct contact with the subject to be moved,
another one of the two or more members of the multi-member spacer is in direct contact with the core, and
a contact area between the subject to be moved and the one of the two or more members is smaller than a contact area between the electromagnetic steel plate and the another one of the two or more members.

US Pat. No. 10,193,404

CLAW ROTOR WITH REDUCED CROSS-SECTION, AND ALTERNATOR COMPRISING ROTOR OF THIS TYPE

VALEO EQUIPEMENTS ELECTRI...

1. A rotor (1) for a rotary electrical machine, the rotor comprising:a first magnet wheel (3); and
a second magnet wheel (5);
each of the first and second magnet wheels comprising a series of claws with axial orientation and a globally trapezoidal form;
the claws extend axially from a radial projection of an outer radial end edge of each of the magnet wheel in the direction of the other magnet wheel such that each claw of each of the magnet wheels is situated between two consecutive claws of the other magnet wheel;
an interpolar space (30) is defined between each two consecutive claws of the rotor (1); and
a magnetic assembly (20) disposed in the interpolar space (30) defined between a first claw (4) of the first magnet wheel (3) and a second claw (6a) of the second magnet wheel (5);
the magnetic assembly (20) comprising laterally two first faces (22) delimited by first and second free ends (23, 24) of the magnetic assembly (20), the two first faces (22) extending respectively along first and second claws (4, 6a);
each of the first and second claws (4, 6a) having a claw head end (40), opposite lateral faces (7) and sloped lateral facets (12) between the claw head end (40) and the lateral faces (7), each of the lateral faces (7) comprising third and fourth opposite ends (8, 9) between which the magnetic assembly (20) is in contact so that the magnetic assembly (20) does not project beyond the third and fourth ends (8, 9) of the lateral face (7) of each of the first and second claws (4, 6a);
the lateral faces of each of the first and second claws (4, 6a) define a non-linear decrease in the cross-section (60) of each of the first and second claws (4, 6a) between the lateral face of each of the first and second claws (4, 6a) and the sloped lateral facet (12) starting from one of the free ends (23, 24) of the magnetic assembly (20) in order then to extend towards the claw head end (40) of the claw, the decrease in the cross-section (60) followed by the sloped lateral facet (12).

US Pat. No. 10,193,398

WIRELESS POWER TRANSFER AND RECEIVE METHOD, APPARATUS AND SYSTEM

LG ELECTRONICS INC., Seo...

1. A wireless power transmitter for transferring power to a wireless power receiver in a wireless manner, the wireless power transmitter comprising:a power transmission control unit configured to detect the wireless power receiver; and
a power conversion unit configured to transfer the power to the wireless power receiver;
wherein the wireless power transmitter is configured to:
receive at least one of an identification packet or a configuration packet transmitted in a first mode from the wireless power receiver;
determine, based on the configuration packet, whether or not the wireless power receiver supports a second mode different from the first mode; and
communicate with the wireless power receiver in at least one of the first mode or the second mode when the wireless power receiver supports the second mode,
wherein the first mode is used for communication between one wireless power transmitter and one wireless power receiver, and the second mode is used for communication between one wireless power transmitter and a plurality of wireless power receivers, and
wherein the configuration packet comprises operation mode information indicating a communication execution mode supported by the wireless power receiver.

US Pat. No. 10,193,387

WIRELESS POWER TRANSMISSION APPARATUS AND METHOD

LG ELECTRONICS INC., Seo...

1. A wireless power transfer device, which is a medium-power wireless power transfer device that transfers power to a low-power wireless power reception device or a medium-power wireless power reception device, the wireless power transfer device comprising:a power conversion unit that converts electrical energy to a power signal; and
a communications and control unit that communicates with the wireless power reception device and controls power transfer,
the power conversion unit comprising:
an inverter that converts DC input to an AC waveform that drives a resonant circuit;
a primary coil that generates a magnetic field;
a shield material aligned with the primary coil; and
a current sensor that monitors current in the primary coil,
wherein the primary coil has a rectangular shape with a single layer of which a number of turns is 12, and consists of 105 strands Litz wire of which the diameter is 0.08 mm,
wherein the shield material is at least 1.5 mm thick and extends at least 2.5 mm beyond the outside of the primary coil,
wherein the primary coil and the shield material have a self-inductance 10.0 ?H, and
wherein the inverter operates in a full-bridge mode or in a half-bridge mode, the initial operation mode is set to the half-bridge mode, and if a detected wireless power reception device is the medium-power wireless power reception device, the communications and control unit changes the inverter operation mode from the half-bridge mode to the full-bridge mode alter receiving a control error packet from the wireless power reception device.

US Pat. No. 10,193,386

WIRELESS CHARGING METHOD AND SYSTEM, WIRELESS CHARGING DEVICE AND WEARABLE DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A wireless charging method, comprising:receiving, by a charging device, electric power usage data from at least two wearable devices;
determining, by the charging device, an electric power distribution solution according to the electric power usage data, the electric power distribution solution being used to determine a charging order and charging electric power for charging one or more of the at least two wearable devices;
performing, by the charging device, wireless charging on one or more of the at least two wearable devices according to the electric power distribution solution; and
sending, by the charging device, the electric power distribution solution to at least one of the at least two wearable devices, the at least one of the at least two wearable devices controlling output load and a quantity of turns of a wireless charging coil to receive electric power, and the at least one of the at least two wearable devices controlling output of the received electric power and an output time to a service in use and a battery.

US Pat. No. 10,193,375

CLOSED LOOP CURRENT CONTROL IN A WIRELESS POWER SYSTEM

MediaTek Inc., Hsin-Chu ...

1. A wireless power transmitter, comprising:a first controller configured to set a target coil current value based, at least in part, on a voltage value reported by a wireless power receiver;
an amplifier configured to generate a transmitter coil current based, at least in part, on a supply voltage received by the amplifier; and
a second controller configured to adjust the supply voltage received by the amplifier based, at least in part, on a comparison of a value of the transmitter coil current to the target coil current value.

US Pat. No. 10,193,374

MULTIFUNCTION BATTERY CHARGING AND HAPTIC DEVICE

Intel Corporation, Santa...

1. An electronic device comprising:a processor;
a memory device comprising instructions to be executed by the processor;
a battery to provide electrical power to the processor and the memory device;
a multifunction charger comprising an enclosure, a first conductive winding fixedly disposed on an inner wall of the enclosure, and a magnetic core suspended within the enclosure by a spring; and
control circuitry configured to activate one of a plurality of available operating modes of the multifunction charger, wherein the plurality of operating modes of the multifunction charger comprises a wireless charging mode and a haptic feedback mode, wherein, to activate wireless charging mode, the control circuitry is to conductively couple the first conductive winding to a battery charging circuit.

US Pat. No. 10,193,363

HYBRID COUPLING FOR A SMART BATTERY SYSTEM

Bren-Tronics, Inc., Comm...

1. A smart battery system comprising:a battery housing containing a first battery, a second battery, and first and second memory locations for storing data about said first and second batteries respectively; and
a single hybrid coupling having a mating jack comprising
(i) a power coupling including two pairs of D.C. battery conductors disposed in a first circular configuration within said mating jack for electrically connecting an external device to said first and second batteries; and
(ii) a data coupling providing two system management buses for communicating data between the external device and said first and second memory locations respectively, wherein said data coupling has two pairs of digital bus conductors disposed in a second circular configuration within said mating jack, wherein said second circular configuration is concentric with said first circular configuration,wherein said power coupling and said data coupling terminate in contacts that are arranged in the jack starting from the 12:00 position and moving clockwise as follows:a first battery conductor of said first pair of D.C. battery conductors;
a first digital bus clock data conductor of said first pair of digital bus conductors;
an additional battery-type conductor;
a first digital bus data conductor of said first pair of digital bus conductors;
a first battery conductor of said second pair of D.C. battery conductors;
an additional data-type conductor;
a second battery conductor of said first pair of D.C. battery conductors;
a second digital bus clock data conductor of said second pair of digital bus conductors;
a second battery conductor of said second pair of D.C. battery conductors; and
a second digital bus data conductor of said second pair of digital bus conductors, andwherein the external device comprises a charger, and further comprising a further battery-type conductor in the center of the jack, and wherein said additional data-type conductor provides a charge enable signal and said further battery-type conductor provides a charge enable return signal.

US Pat. No. 10,193,323

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor switching element having a sense terminal and capable of outputting from the sense terminal a sense current given at a predetermined shunt ratio to a main current;
a sense resistor having one end connected to the sense terminal, having the other end configured to be connected to a ground, and receiving a current from the sense terminal to generate a sense voltage;
a correction voltage generation circuit which generates a correction voltage;
a voltage dividing circuit including a first resistor which receives the sense voltage at its one end and a second resistor which receives at its one end the correction voltage from the correction voltage generation circuit, and whose other end is connected to the other end of the first resistor, the voltage dividing circuit outputting from the point of connection between the first and second resistors a corrected sense voltage obtained by correcting the sense voltage with the correction voltage;
an overcurrent protection circuit to which the corrected sense voltage is input, and which outputs a halt signal when the corrected sense voltage is higher than a threshold voltage;
a drive circuit which stops driving of the semiconductor switching element upon receiving the halt signal from the overcurrent protection circuit; and
a correction voltage switching element which connects the correction voltage generation circuit and the one end of the second resistor,
wherein the correction voltage switching element is turned on from an off state after a lapse of a predetermined time period from a moment at which the semiconductor switching element is turned on, and with the correction voltage switching element turned on, the correction voltage generation circuit is connected to the one end of the second resistor.

US Pat. No. 10,193,321

FILLER ASSEMBLY FOR CABLE GLAND

1. A filler assembly for filling a cable gland with curable liquid material, the assembly comprising:(a) a dispenser apparatus for a curable liquid material, the apparatus comprising:
a body defining at least one first chamber accommodating a first component of a curable liquid material, and at least one second chamber accommodating a second component of said curable liquid material, wherein mixing of said first and second components initiates curing of said curable liquid material; and
at least one dispenser device adapted to dispense said mixed curable liquid material therefrom between a plurality of said cores of said cable; and
(b) at least one flexible barrier member capable of having at least one respective aperture therethrough configured to be adapted to stretch to engage a plurality of cores of a cable while in use to provide a barrier to passage of said curable liquid material along said cores.

US Pat. No. 10,193,289

PLUG-IN POWER SOURCE ADAPTING SEAT

Rich Brand Industries Lim...

1. A plug-in power source adapting seat composed of a main body, an adapting barrel, a positive pole clip, a negative pole clip and a joining body, wherein:the main body is integrally formed by a cylinder like portion and a disc like portion, the cylinder like portion has a straight-type external surface, the top surface of the cylinder like portion is opened, an inside of the cylinder like portion is disposed with a positive pole clip slot and a negative pole clip slot, an outward appearance of the cylinder like portion is formed with a shield ring at a small distance away from a bottom of the cylinder like portion, the bottom is circularly disposed with a plurality of slots, a circumference wall is disposed with a notch; the disc like portion is formed at the bottom of the cylinder like portion and formed with an expanded area, the bottom of the disc like portion is formed with a set of inserting troughs, the set of inserting troughs inwardly passing through and respectively piercing through the positive pole clip slot and the negative pole clip slot inside the cylinder like portion;
the adapting barrel is formed by a conductive material and has a cylinder shape, a circumference wall of the adapting barrel is formed with a screwing strip as a spiral shape, a bottom of the screwing strip is a vertical wall, the vertical wall is circularly disposed with a plurality of concave bodies, a top surface of the adapting barrel is formed with an opening and is embedded with an insulation body, the insulation body has a joining groove vertically penetrating;
a sheet body of the positive pole clip is formed with an extension and a bending, the positive pole clip obliquely protrudes to form a fasten piece, and a bottom of the positive pole clip is formed into a clamp line end;
a sheet body of the negative pole clip is formed with an extension and a bending, the negative pole clip obliquely protrudes to form a fasten piece, and a bottom of the negative pole clip is formed into a clamp line end; and
the joining body is formed by a conductive material to have a top cover showing an arc shape and a joining lever downwardly stretching, the top cover covers the opening of the adapting barrel, and an external diameter of the joining lever equals an inner diameter of the joining groove;
in assembling, the positive pole clip is downwardly accommodated into the positive pole clip slot from a top opening of the main body so that the clamp line end of the positive pole clip aligns with one of the set of inserting troughs, with the fasten piece of the positive pole clip and the positive pole clip slop achieving fastening and positioning; the negative pole clip is downwardly accommodated into the negative pole clip slot so that the clamp line end of the negative pole clip aligns with another of the set of inserting troughs, the fasten piece of the negative pole clip and the negative pole clip slot achieves fastening and positioning, after positioning the negative pole clip, a top section of the negative pole clip stretches from the notch of the cylinder like portion; the adapting barrel downwardly fits the cylinder like portion to enable the screwing strip of the adapting barrel to exist on the straight-type external surface of the cylinder like portion, the vertical wall is downwardly and vertically disposed from the shield ring of the cylinder like portion, the plurality of concave bodies of the adapting barrel is fastened into a corresponding slot of the cylinder like portion one on one so that the adapting barrel and the cylinder like portion achieve a combination, in the process, the top section of the negative pole clip achieves electric conductance together with the adapting barrel, at the same time, a top section of the positive pole clip enters the joining groove of the insulation body at a top end of the adapting barrel, the joining lever of the joining body pierces through the joining groove of the insulation body from an outside, the joining lever is in contact with the top section of the positive pole clip, the joining lever and the joining groove performing a packing motion, achieve an electric conductance together with the top section of the positive pole clip, and at the same time, the top cover completely covers the opening of the adapting barrel.

US Pat. No. 10,193,283

BUSWAY STAB ASSEMBLIES AND RELATED SYSTEMS AND METHODS

Eaton Intelligent Power L...

1. A plug-in device for use with a busway system comprising a busway housing defining a longitudinal axis, the plug-in device comprising:a stab base housing having first and second opposite sides;
one or more stab conductors extending out of and away from the stab base housing at the first side of the stab base housing;
one or more stab conductors extending out of and away from the stab base housing at the second side of the stab base housing; and
a ground conductor at an upper portion of the stab base housing;
wherein the stab base housing is configured to be received through an opening at a bottom portion of the busway housing and positioned in a first position with each stab conductor extending away from the stab base housing in a direction substantially parallel to the longitudinal axis of the busway housing and with the ground conductor contacting a top wall of the busway housing;
wherein the stab base housing is configured to be rotated from the first position to a second position with each stab conductor extending away from the stab base housing in a direction substantially perpendicular to the longitudinal axis of the busway housing and with the ground conductor contacting the top wall of the busway housing;
wherein:
an enclosure is coupled to a lower portion of the stab base housing;
a cable extends from each stab conductor and from the ground conductor to outside the stab base housing at the lower portion thereof; and
each cable is electrically connected to one or more components in the enclosure.

US Pat. No. 10,193,267

MULTIFUNCTION CONNECTOR

3M Innovative Properties ...

1. An elongated electrical connector for mating with a mating connector along a mating direction, the connector comprising:an elongated base extending along a longitudinal direction perpendicular to the mating direction and comprising a groove oriented along a thickness direction perpendicular to the mating and longitudinal directions, and a sliding portion configured to slide along the groove;
a bottom tongue extending forwardly along the mating direction from the base;
a top tongue extending forwardly along the mating direction from the sliding portion of the base and spaced apart from the bottom tongue along the thickness direction, the top tongue reversibly attachable to and removable from the connector by the sliding portion of the base sliding along the groove; and
a plurality of contacts disposed on the top and bottom tongues.

US Pat. No. 10,193,260

MULTI-CONTACT CONNECTOR

IRISO ELECTRONICS CO., LT...

1. A multi-contact connector comprising: terminals each includinga first contact piece section having a first contact section that achieves pressing contact with a connection target object in a first direction and a first elastic arm that extends in a direction that intersects the first direction and displaceably supports the first contact section, and
a second contact piece section having a second contact section that achieves pressing contact with the connection target object in the first direction and a second elastic arm that displaceably supports the second contact section,
wherein the second elastic arm extends in the first direction toward the first elastic arm and has a front end portion facing the first elastic arm and is formed as a spring piece linked to the second contact section.

US Pat. No. 10,193,252

ELECTRONIC COMPONENT AND IMAGING DEVICE

IRISO ELECTRONICS CO., LT...

1. An electronic component comprising:a housing accommodating an imaging component including a board having a first contact portion and a second contact portion; and
an external device connection portion conductively connecting the imaging component to an external device,
wherein the external device connection portion includes a first rod-shaped contact piece that conductively contacts the first contact portion, a conductive first elastic member that urges the first rod-shaped contact piece toward the first contact portion, a dielectric that is formed in a tubular shape and has an accommodation hole accommodating the first rod-shaped contact piece and the first elastic member displaceably in the hole axis direction, and an external conductor that is formed in a tubular shape and holds the outer periphery of the dielectric.

US Pat. No. 10,193,241

FIXING STRUCTURE AND FIXING METHOD

Japan Aviation Electronic...

1. A fixing method for fixing a terminal to an object to be fixed with a solder disposed therebetween, the fixing method comprising:a first step of disposing the solder on the object to be fixed;
a second step of bringing the terminal into contact with the solder; and
a third step of forming a penetrating hole in the terminal by irradiating a laser beam onto the terminal,
wherein in the third step, the laser beam is irradiated onto the terminal in such a manner that the solder melted by the irradiation of the laser beam passes through the penetrating hole and reaches the vicinity of an upper end of the penetrating hole, and
wherein in the third step, the laser beam is irradiated onto the terminal while the terminal is pressed against the solder by an external force or a weight of a connector including the terminal.

US Pat. No. 10,193,223

MODULAR PARALLEL BEAMFORMING SYSTEM AND ASSOCIATED METHODS

General Electric Company,...

1. A beamforming system, comprising:a plurality of modular beamformers operatively coupled to each other, each modular beamformer comprising:
a plurality of signal generation units, each being configured to generate a respective signal;
a plurality of respective delaying units, each corresponding to a respective signal generation unit, each delaying unit being configured to receive a respective signal from the respective signal generating unit, each delaying unit being configured to adaptively delay the respective signal and each delaying unit being configured to output a respective delayed signal;
a plurality of multipliers assigned to each of the delaying units, each multiplier being configured to receive the respective delayed signal output from the respective delaying unit, each multiplier being configured to generate a respective conditioned signal by adaptively applying a respective weight to the respective received delayed signal from the respective delaying unit and each multiplier being configured to output the respective conditioned signal; and
a plurality of summers, each configured to receive a respective group of conditioned signals from a respective group of the plurality of multipliers, being configured to combine the respective group of conditioned signals and being configured to generate a respective phased array output signal, each of the plurality of summers being configured to receive at least another input other than the respective group of conditioned signals; and
the plurality of modular beamformers being interconnected such that each of the plurality of summers within each beamformer receives, as the at least another input, a respective phased array output signal from a summer of a different one of the plurality of modular beamformers.

US Pat. No. 10,193,220

ANTENNA ARRAY

Electronics and Telecommu...

1. An antenna array, comprising:a first antenna;
a second antenna; and
a dielectric substance, of which a height is determined based on a distance between the first and second antennas and beam widths of main lobes of the first and second antennas,
wherein when the distance between the first and second antennas is smaller than two times the beam widths of the main lobes of the first and second antennas, the height of the dielectric substance is determined by lengths from distal ends of the first and second antennas to a point defining the beam width.

US Pat. No. 10,193,199

BATTERY SYSTEM

ARCIMOTO, INC., Eugene, ...

1. A battery enclosure, comprising:a pair of opposing enclosure portions that collectively define a battery region, each enclosure portion including:
a first segment that includes a plurality of fluid pathways spaced apart from each other, the first segment forming a notched region at a distal end of the first segment;
a second segment that joins the first segment at an interface opposite a distal end of the first segment, the second segment being orthogonal to the first segment, the second segment forming a flange at a distal end of the second segment opposite the interface;
a first wall interfacing with a first edge of the pair of opposing enclosure portions to further collectively define the battery region, an inner face of the first wall including a first set of a plurality of openings that are aligned with at least some of the plurality of fluid pathways of a first enclosure portion of the pair of enclosure portions along the first edge, the first wall including a second set of a plurality of openings that are aligned with at least some of the plurality of fluid pathways of a second enclosure portion of the pair of enclosure portions along the first edge, at least some of the first set of the plurality of openings and at least some of the second set of the plurality of openings joining each other within the first wall via fluid pathways formed therein; and
a second wall interfacing with a second edge of the pair of opposing enclosure portions opposite the first edge to further collectively define the battery region, an inner face of the second wall including a third set of a plurality of openings that are aligned with at least some of the plurality of fluid pathways of the first enclosure portion of the pair of enclosure portions along the second edge, the second wall including a fourth set of a plurality of openings that are aligned with at least some of the plurality of fluid pathways of the second enclosure portion of the pair of enclosure portions along the second edge, at least some of the third set of the plurality of openings and at least some of the fourth set of the plurality of openings joining each other within the second wall via fluid pathways formed therein;
wherein each notched region of each enclosure portion accommodates the flange of the other enclosure portion.

US Pat. No. 10,193,193

STRUCTURE OF BATTERY PROTECTION CIRCUIT MODULE PACKAGE COUPLED WITH HOLDER, AND BATTERY PACK HAVING SAME

ITM SEMICONDUCTOR CO., LT...

1. A structure of a battery protection circuit module package coupled with a holder, the structure comprising:a basic package comprising a lead frame consisting of a plurality of leads spaced apart from each other, and protection circuit elements provided on the lead frame without use of a printed circuit board; and
an encapsulant and a holder simultaneously produced by disposing the basic package in a first injection mold and injecting a melt of resin into the first injection mold to perform an insert injection molding process,
wherein the encapsulant encapsulates the protection circuit elements to expose part of the lead frame,
wherein the encapsulant and the basic package configure the battery protection circuit module package, and
wherein the holder is coupled to the battery protection circuit module package by the insert injection molding process.

US Pat. No. 10,193,184

LITHIUM ION SECONDARY BATTERY AND METHOD FOR MANUFACTURING SAME

NEC ENERGY DEVICES, LTD.,...

1. A method for manufacturing a lithium ion secondary battery, the lithium ion secondary battery comprising a positive electrode and a negative electrode disposed with a separator sandwiched therebetween and contained together with an electrolytic solution in an outer case including a flexible film, whereina quantity of dissolved nitrogen in the electrolytic solution in injecting the electrolytic solution into the outer case is 100 ?g/mL or less, the quantity being 5 ?g/mL or more.

US Pat. No. 10,193,168

FUEL CELL SYSTEM

NISSAN MOTOR CO., LTD., ...

1. A fuel cell system that generates electric power by supplying anode gas and cathode gas to a fuel cell, comprising:a control valve adapted to control a pressure of the anode gas to be supplied to the fuel cell;
a buffer unit adapted to store an anode-off gas to be discharged from the fuel cell; and
a controller programmed to:
control the control valve in order to periodically increase and decrease the pressure of the anode gas at a specific width of a pulsation; and
correct the width of the pulsation based on a temperature of an upstream buffer volume comprising an anode gas flow passage from the control valve to the fuel cell.

US Pat. No. 10,193,156

HIGH-DENSITY AND HIGH-HARDNESS GRAPHENE-BASED POROUS CARBON MATERIAL, METHOD FOR MAKING THE SAME, AND APPLICATIONS USING THE SAME

Graduate School at Shenzh...

1. A method for making graphene-based porous carbon material comprising steps of:forming a sol by dispersing a graphene-based component and an auxiliary component in a solvent, the auxiliary component selected from the group consisting of polyvinyl alcohol, sucrose, glucose, and combinations thereof;
adjusting a pH value of the sol to 8 or less;
preparing a graphene-based gel by reacting the sol in a reacting container at a temperature of about 20° C. to about 500° C. for about 0.1 hours to 100 hours; and
evaporative drying the graphene-based gel at a temperature of about 0° C. to about 200° C. to obtain the graphene-based porous carbon material.

US Pat. No. 10,193,154

CATHODE COMPOSITION FOR PRIMARY BATTERY

Medtronic, Inc., Minneap...

1. A primary battery configured to supply operation power to an implantable medical device, the primary battery comprising:a cathode comprising an active material and at least one of a metal oxide or a metal fluoride, wherein the active material exhibits a first discharge capacity and the at least one of the metal oxide or the metal fluoride exhibits a second discharge capacity at a voltage lower than the first discharge capacity;
a current collector, wherein the cathode comprises a cathode layer on the current collector, wherein the cathode layer is formed of a mixture of the active material and the at least one of the metal oxide or the metal fluoride;
an anode comprising a metal as an electron source; and
an electrolyte between the cathode and anode, wherein the metal reacts with the electrolyte below a third discharge capacity at a voltage lower than the second discharge capacity to form a gas,
wherein the metal reacts with the active material at the first discharge capacity to consume the active material, and, following the consumption of the active material of the cathode, the metal reacts with the at least one of the metal oxide or the metal fluoride of the cathode prior to reacting with the electrolyte below the third discharge capacity, and
wherein the cathode includes an amount of the active material and the at least one of the metal oxide or the metal fluoride, and the anode includes an amount of metal such that an excess portion of the metal and an amount of the at least one of the metal oxide or the metal fluoride remains following the consumption of the active material, and wherein the amount of the at least one of the metal oxide or the metal fluoride is proportioned to consume all of the excess portion of the metal.

US Pat. No. 10,193,148

CARBON-SILICON COMPOSITE AND MANUFACTURING METHOD THEREOF

OCI COMPANY LTD., Seoul ...

11. A carbon-silicon composite comprising:silicon-carbon-polymer carbonized matrix structure particles, comprising:
a polymer matrix having a network structure consisting of knots and chains connecting the knots with a cross-linking point;
carbon particles dispersed in the polymer matrix; and
silicon dispersed in the silicon-carbon-polymer carbonized matrix structure particles, wherein the silicon is bound to the carbon particles; and
a first carbon body, wherein the first carbon body is carbonized, and the silicon-carbon-polymer carbonized matrix structure particles are captured and dispersed in the first carbon body;
wherein the carbon particles are connected to each other and to the first carbon body to form inner pores,
wherein at least a portion of the silicon is in the inner pores,
wherein the silicon-carbon-polymer carbonized matrix structure particle has a porosity higher than a porosity of the first carbon body.

US Pat. No. 10,193,145

CARBON-COATED ACTIVE PARTICLES AND PROCESSES FOR THEIR PREPARATION

HYDRO-QUEBEC, Montreal, ...

1. A process for producing carbon-coated particles, the process comprising the steps of:a. forming an emulsion by mixing particles, acrylonitrile monomers, and an aqueous solvent, said particles comprising an electrochemically active material;
b. polymerizing the acrylonitrile monomers in the mixture of step (a) by emulsion polymerization;
c. drying the particles from step (b) to form a nano-layer of poly(acrylonitrile) at the surface of the particles; and
d. thermally treating the dried particles of step (c) to form the carbon-coated particles, said carbon consisting in a nano-layer of carbon comprising fibers on the surface of the particles.

US Pat. No. 10,193,137

LITHIUM-ION BATTERIES WITH NANOSTRUCTURED ELECTRODES

WASHINGTON STATE UNIVERSI...

1. A method to produce an anode suitable for a lithium-ion battery, the method comprising:preparing a surface of an anode substrate, the anode substrate being at least partially compliant and having a compliance of about 3.0×10?7 to 8×10?12 l/Pa, wherein preparing the surface of the anode substrate comprises polishing the anode substrate, treating the anode substrate with a basic solution, treating the anode substrate with an acidic solution, or combinations thereof;
forming a plurality of conductive nanostructures on the surface of the anode substrate via electrodeposition; and
controlling at least one operating condition of the electrodeposition based on a target profile for the plurality of conductive nanostructures formed on the surface of the anode substrate, the target profile including the conductive nanostructures forming a plurality of freestanding structures.

US Pat. No. 10,193,135

POSITIVE ELECTRODE ACTIVE MATERIALS WITH COMPOSITE COATINGS FOR HIGH ENERGY DENSITY SECONDARY BATTERIES AND CORRESPONDING PROCESSES

Zenlabs Energy, Inc., Fr...

1. A particulate material comprising a core of lithium cobalt oxide, a partial coating with domains of a lithium manganese nickel cobalt oxide, and a distinct inert stabilization nanocoating, and having from about 2 weight percent to about 19 weight percent lithium manganese nickel cobalt oxide evaluated according to weight of added metal during coating formation.

US Pat. No. 10,193,116

CERAMIC COATING ON BATTERY SEPARATORS

Applied Materials, Inc., ...

1. A method, comprising:preparing a separator for an electrochemical storage device; and
using a controlled process to coat the separator with a ceramic layer having a desired thickness, wherein the controlled process comprises:
coating the separator with a first layer of ceramic particles having a first charge;
coating the first layer with a second layer of ceramic particles having a second charge opposite the first charge;
repeating the coating steps until a ceramic coating having the desired thickness is obtained.

US Pat. No. 10,193,115

BATTERY COVER

East Penn Manufacturing C...

1. A battery cover, comprising:a lower battery cover, and
an upper battery cover matable with the lower battery cover to form a labyrinth and a plurality of battery cover sides including a terminal side and an opposite side, the labyrinth defined by a plurality of walls formed by the lower battery cover and the upper battery cover and having
a plurality of labyrinth cell passageways each extending only between one of a plurality of cell openings and one of a plurality of mixing areas positioned on the terminal side,
a plurality of exhaust passageways extending along an entirety of the opposite side of the upper battery cover, and
a channel disposed between the plurality of mixing areas and the plurality of exhaust passageways, the channel connecting the plurality of mixing areas to the plurality of exhaust passageways by extending from a lower end of each of the plurality of mixing areas at the terminal side and splitting into the plurality of exhaust passageways, the plurality of labyrinth cell passageways each extending to a position directly adjacent one of the plurality of exhaust passageways at the opposite side before leading to the one of the plurality of mixing areas at the terminal side, each of the plurality of labyrinth cell passageways is separated only by one of the plurality of walls from one of the plurality of exhaust passageways at the position directly adjacent one of the plurality of exhaust passageways.

US Pat. No. 10,193,111

CONVERTIBLE BATTERY PACK

1. A battery pack comprising:a support board having a planar surface;
a plurality of contact pads arranged in a predefined configuration in the support board, each of the plurality of contact pads having an exposed planar surface generally parallel to the support board planar surface; and
a converter element including a housing having a first side facing the support board planar surface, at least one contact held in the housing, the at least one contact having a mating surface and extending towards the support board planar surface, and at least one spring held in the housing positioned between the housing and the at least one contact forcing the at least one contact towards the planar surface and the plurality of contact pads.

US Pat. No. 10,193,110

ELECTROCHEMICAL DEVICE, SUCH AS A MICROBATTERY OR AN ELECTROCHROMIC SYSTEM, COVERED BY AN ENCAPSULATION LAYER COMPRISING A BARRIER FILM AND AN ADHESIVE FILM, AND METHOD FOR FABRICATING ONE SUCH DEVICE

1. An electrochemical device comprising(1) a substrate,
(2) at least one stack of active layers containing lithium, said stack comprising
(2a) at least a first electrode connected to a first current collector and
(2b) at least a second electrode connected to a second current collector,
said stack being arranged on the substrate
(3) an encapsulation layer covering said at least one stack, the encapsulation layer comprising at least:
(3a) a barrier film presenting at least one electrically insulating surface and comprising at least one layer hermetic to oxidising species,
(3b) an adhesive film, provided with a first surface and a second surface,
the first surface being in contact with the electrically insulating surface of the barrier film and
the second surface covering a stack of active layers and a part of the substrate,
wherein the adhesive film comprises a juxtaposition of electrically conducting adhesive strips and of electrically insulating adhesive strips,
wherein two electrically conducting strips are separated by an electrically insulating strip to be electrically insulated from one another,
each electrically conducting strip being connected to the first current collector or to the second current collector of the stack of active layers.

US Pat. No. 10,193,108

SECONDARY BATTERY, ELECTRONIC DEVICE, AND VEHICLE

Semiconductor Energy Labo...

1. A secondary battery comprising:a film comprising flat portions and curved portions,
wherein the flat portions and the curved portions are alternately provided each other,
wherein a thickness of a top portion of each of the curved portions is thicker than a thickness of the flat portions.

US Pat. No. 10,193,106

METHOD FOR MANUFACTURING OLED DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing an OLED device, comprising steps of:a. providing a substrate and manufacturing an anode and a buffer layer in sequence on the substrate;
b. subjecting the substrate with the anode and the buffer layer thereon to an acid treatment;
c. drying the substrate and manufacturing a liquid light emitting layer on the buffer layer;
d. providing a cover plate and manufacturing a cathode and an electron transport layer in sequence on the cover plate;
e. subjecting the cover plate with the cathode and the electron transport layer thereon to the acid treatment; and
f. bonding the cover plate and the substrate together by lamination to obtain the OLED device.

US Pat. No. 10,193,105

ULTRAVIOLET IRRADIATION DEVICE FOR PACKAGE OF LIGHT-EMITTING DIODE

WUHAN CHINA STAR OPTOELEC...

1. An ultraviolet irradiation device for package of a light-emitting diode, wherein the ultraviolet irradiation device comprises:a sealed shell, wherein the light-emitting diode to he packaged is arranged in the shell, and a UV mask that is movable in the shell is arranged below the light-emitting diode;
a UV lamp, which is arranged below the UV mask; and
to a sealed chamber which is in communication with the shell, wherein the chamber is arranged at a side of the shell, wherein a first rolling unit configured to deliver the light-emitting diode is arranged in the chamber, and a first gate and a second gate are respectively arranged at two ends of the chamber, and wherein the chamber is further in communication with an air exhaust unit and a first gas source respectively.

US Pat. No. 10,193,102

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a substrate;
a plurality of pixels above the substrate, each of the pixels including a light emitting element;
a display region including the plurality of pixels;
a thin film transistor which each of the plurality of pixels includes;
a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element;
a sealing film including a second inorganic insulating material and covering the light emitting element; and
at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film,
wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.

US Pat. No. 10,193,090

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method of forming a gate structure for a gate-all-around field effect transistor, the method comprising:disposing a carbon nanotube (CNT) over a substrate;
forming anchor structures on both ends of the CNT disposed over the substrate;
after the anchor structures are formed, recessing a part of the substrate under the CNT;
after the recessing, forming a gate dielectric layer wrapping around the CNT and forming a gate electrode layer over the gate dielectric layer; and
removing the CNT with the gate dielectric layer and the gate electrode layer from the substrate, thereby forming the gate structure.

US Pat. No. 10,193,089

DISPLAY DEVICE, ARRAY SUBSTRATE, AND MANUFACTURING METHOD

Shenzhen China Star Optoe...

1. An array substrate, comprising a substrate base, and two gates, a source, a drain, an active layer, and a pixel electrode on the substrate base, wherein the drain and the pixel electrode are connected together; the source and the drain contact the active layer, respectively; and the two gates control the conduction and cut off of the active layer, which in turn controls the conduction and cut off between the source and the drain;wherein the source, the two gates, the active layer, the drain, and the pixel electrode are sequentially stacked on the substrate base; and the drain and the pixel electrode are at a same level;
wherein the array substrate further comprises a buffer layer on the substrate base, wherein a buffer via is configured in the buffer layer, exposing the substrate base; the source is disposed in the buffer via; and the source has a top surface level with that of the buffer layer;
wherein the array substrate further comprises a passivation layer on the buffer layer and the source, wherein a passivation via is configured in the passivation layer, exposing the source; the two gates are disposed on the passivation layer oppositely across the passivation via; a gate metal, formed when the gates are formed, is disposed in the passivation via, contacting the source; and the gate metal has a top surface level with that of the passivation layer.

US Pat. No. 10,193,088

PEROVSKITE NANOCRYSTALLINE PARTICLES AND OPTOELECTRONIC DEVICE USING SAME

POSTECH ACADEMY-INDUSTRY ...

1. A perovskite nanocrystal particle capable of being dispersible in an organic solvent and comprising a perovskite nanocrystal structure,wherein the perovskite nanocrystal particle is an organic-inorganic-hybrid perovskite or an inorganic metal halide perovskite, and
the perovskite nanocrystal particle has a diameter greater than a Bohr exciton diameter on an area that is not affected by a quantum confinement effect.

US Pat. No. 10,193,086

LIGHT-EMITTING ELEMENT, COMPOUND, ORGANIC COMPOUND, DISPLAY MODULE, LIGHTING MODULE, LIGHT-EMITTING DEVICE, DISPLAY DEVICE, LIGHTING DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

5. A method for synthesizing a compound, the method including:conducting a reaction according to the following scheme:

wherein X represents one of a halogen and a boronic acid,
wherein R1 to R5 separately represent any one of hydrogen, an alkyl group having 1 to 6 carbon atoms, a substituted or unsubstituted monocyclic saturated hydrocarbon having 5 to 7 carbon atoms, a substituted or unsubstituted polycyclic saturated hydrocarbon having 7 to 10 carbon atoms, and a substituted or unsubstituted aryl group having 6 to 13 carbon atoms,
wherein B represents the other of the halogen and the boronic acid, and
wherein A1 represents a group comprising at least one of a phenyl group, a fluorenyl group, a phenanthryl group, a triphenylenyl group, a dibenzothiophenyl group, a dibenzofuranyl group, a carbazolyl group, a benzimidazolyl group, a benzoxazolyl group, a benzthiazolyl group, and a triphenyl amine skeleton which are substituted or unsubstituted.

US Pat. No. 10,193,084

2,2?-BIBENZO[D]IMIDAZOLIDENE COMPOUND HAVING HETEROMONOCYCLIC GROUPS AT THE 1-, 1?-, 3- AND 3?- POSITIONS, AND ORGANIC LIGHT-EMITTING ELEMENT AND DISPLAY DEVICE CONTAINING THE SAME

Canon Kabushiki Kaisha, ...

1. A 2,2?-bibenzo[d]imidazolidene compound expressed by the following general formula (1):
wherein Ar1 to Ar4 each represent a substituted or unsubstituted heteromonocyclic group; R1 to R8 each represent a hydrogen atom or a substituent selected from the group consisting of halogen atoms, alkyl groups having a carbon number in the range of 1 to 8, and substituted or unsubstituted aromatic hydrocarbon groups.

US Pat. No. 10,193,082

CONDENSED-CYCLIC COMPOUND AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A condensed-cyclic compound represented by Formula 1:
wherein, in Formula 1,
Ar11 is represented by one of Formulae 10-1 to 10-4:

wherein, in Formulae 1 and 10-1 to 10-4,
X1 is N or C(R1), X2 is N or C(R2), X3 is N or C(R3), X4 is N or C(R4), X5 is N or C(R5), X6 is N or C(R6), X7 is N or C(R7), X8 is N or C(R8), X11 is N or C(R11), X12 is N or C(R12), X13 is N or C(R13), X14 is N or C(R14), X15 is N or C(R15), X16 is N or C(R16), X17 is N or C(R17), and X18 is N or C(R18);
Y11 is O, S, N(R101), C(R101)(R102), or Si(R101)(R102);
Z11 is selected from N and C(A12);
Z12 to Z14 are each independently selected from C(A11) and C(A12); and at least one of Z12 to Z14 is C(A11); and
A11 comprises at least one cyano group (CN); and A11 is represented by one of Formulae 2-1 to 2-10:

wherein, in Formulae 2-1 to 2-10,
X21 is N or C(R21), X22 is N or C(R22), X23 is N or C(R23), X24 is N or C(R24), and X25 is N or C(R25);
A12, R1 to R8, R11 to R18, R101, R102, R21 to R25, and R201 to R203 are each independently selected from
a hydrogen, a deuterium, —F, a hydroxyl group, a cyano group (CN), a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group;
a C1-C20 alkyl group and a C1-C20 alkoxy group, each substituted with at least one selected from a deuterium, —F, a hydroxyl group, a cyano group (CN), a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, and a phosphoric acid group or a salt thereof;
a phenyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, and a dibenzothiophenyl group;
a phenyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, and a dibenzothiophenyl group, each substituted with at least one selected from a deuterium, —F, a hydroxyl group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, a dibenzothiophenyl group, and —Si(Q1)(Q2)(Q3); and
—Si(Q11)(Q12)(Q13),
b201 is selected from 1, 2, 3, 4, and 5;
b202 and b203 are each independently selected from 1, 2, 3, and 4; and
* indicates a carbon atom in Formula 1,
wherein Q1 to Q3 and Q11 to Q13 are each independently selected from a hydrogen, a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, a pyridinyl group, a fluorenyl group, a dibenzofuranyl group, and a dibenzothiophenyl group.

US Pat. No. 10,193,079

MATERIALS FOR ELECTRONIC DEVICES

Merck Patent GmbH, (DE)

1. A compound of the formula (I)
or a compound containing exactly two or three units of the formula (I) joined to one another via a single bond or an L group,
where:
L is any divalent or trivalent organic group;
A is a group of the formula (A)

bonded via the dotted bond;
Ar1 is the same or different at each instance and is an aromatic or heteroaromatic ring system which has 5 to 30 aromatic ring atoms and may be substituted by one or more R1 radicals;
Y is the same or different at each instance and is a single bond, BR1, C(R1)2, Si(R1)2, NR1, PR1, P(?O)R1, O, S, S?O or S(?O)2;
B is the same or different at each instance and is selected from H, a straight-chain alkyl group having 1 to 10 C atoms or a branched or cyclic alkyl group having 3 to 10 C atoms, each of which may be substituted by one or more R1 radicals, or an aryl group having 6 to 14 aromatic ring atoms, each of which may be substituted by one or more R1 radicals;
RA is the same or different at each instance and is CF3, CN, and an E group, which is an aryl or heteroaryl group which has 6 to 14 aromatic ring atoms and may be substituted by one or more R1 radicals, and which contains one or more V groups as constituents of the aromatic ring, where the V groups are the same or different at each instance and are selected from ?N—, ?C(F)—, ?C(CN)— and ?C(CF3)—, and where the heteroaryl group is not bonded via a nitrogen atom;
RB is selected from H, a straight-chain alkyl group having 1 to 10 carbon atoms or a branched or cyclic alkyl group having 3 to 10 carbon atoms, each of which may be substituted by one or more R1 radicals, and an aryl group having 6 to 14 aromatic ring atoms, which may be substituted by one or more R1 radicals;
R1 is the same or different at each instance and is H, D, F, C(?O)R2, CN, Si(R2)3, N(R2)2, P(?O)(R2)2, OR2, S(?O)R2, S(?O)2R2, a straight-chain alkyl or alkoxy group having 1 to 20 carbon atoms or a branched or cyclic alkyl or alkoxy group having 3 to 20 carbon atoms, where the abovementioned groups may each be substituted by one or more R2 radicals and where one or more CH2 groups in the abovementioned groups may be replaced by —R2C?CR2—, —C?C—,Si(R2)2, C?O, C?NR2, —C(?O)O—, —C(?O)NR2—, NR2, P(?O)(R2), —O—, —S—, SO or SO2, or an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, each of which may be substituted by one or more R2 radicals, where two or more R1 radicals may be joined to one another and may form a ring;
R2 is the same or different at each instance and is H, D, F or an aliphatic, aromatic or heteroaromatic organic radical having 1 to 20 carbon atoms, in which one or more hydrogen atoms may also be replaced by D or F; at the same time, two or more R2 substituents may be joined to one another and may form a ring.

US Pat. No. 10,193,077

BISCARBAZOLE DERIVATIVE, MATERIAL FOR ORGANIC ELECTROLUMINESCENCE DEVICE AND ORGANIC ELECTROLUMINESCENCE DEVICE USING THE SAME

IDEMITSU KOSAN CO., LTD.,...

1. An organic electroluminescence device comprising:a cathode;
an anode; and
a plurality of organic thin-film layers provided between the cathode and the anode, wherein
at least one of the organic thin-film layers is an emitting layer comprising a first host material, a second host material and a phosphorescent material that exhibits a phosphorescence,
the first host material is a compound represented by a formula (4) below, and
the second host material is a compound represented by a formula (5) below,

where
A1 represents a substituted or unsubstituted nitrogen-containing heterocyclic group having 1 to 30 ring carbon atoms,
when A1 has a substituent, the substituent of A1 is an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a haloalkyl group having 1 to 20 carbon atoms, an alkylsilyl group having 1 to 10 carbon atoms, an arylsilyl group having 6 to 30 carbon atoms, a cyano group, a halogen atom, an aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, or a monocyclic aromatic heterocyclic group having 2 to 30 ring carbon atoms,
A2 represents a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, or a substituted or unsubstituted nitrogen-containing heterocyclic group having 1 to 30 ring carbon atoms,
when A2 has a substituent, the substituent of A2 is an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a haloalkyl group having 1 to 20 carbon atoms, an alkylsilyl group having 1 to 10 carbon atoms, an arylsilyl group having 6 to 30 carbon atoms, a cyano group, a halogen atom, an aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms or a monocyclic aromatic heterocyclic group having 2 to 30 ring carbon atoms,
X1 and X2 are each a linking group and independently represent a single bond, substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, or substituted or unsubstituted fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms,
when X1 has a substituent and/or X2 has a substituent, the substituent for X1 and X2 is an alkyl group having 1 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a haloalkyl group having 1 to 20 carbon atoms, an alkylsilyl group having 1 to 10 carbon atoms, an arylsilyl group having 6 to 30 carbon atoms, a cyano group, a halogen atom, an aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, or a monocyclic aromatic heterocyclic group having 2 to 30 ring carbon atoms,
Y1, Y3 and Y4 each independently represent a hydrogen atom, a fluorine atom, a cyano group, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted haloalkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted alkylsilyl group having 1 to 10 carbon atoms, a substituted or unsubstituted arylsilyl group having 6 to 30 carbon atoms, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a substituted or unsubstituted fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, a substituted or unsubstituted aromatic heterocyclic group having 2 to 30 ring carbon atoms, or a substituted or unsubstituted fused aromatic heterocyclic group having 2 to 30 ring carbon atoms,
Y2 represents a hydrogen atom, a fluorine atom, a cyano group, an unsubstituted alkyl group having 1 to 20 carbon atoms, an unsubstituted alkoxy group having 1 to 20 carbon atoms, an unsubstituted haloalkyl group having 1 to 20 carbon atoms, an unsubstituted haloalkoxy group having 1 to 20 carbon atoms, an unsubstituted alkylsilyl group having 1 to 10 carbon atoms, an unsubstituted arylsilyl group having 6 to 30 carbon atoms, an unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, an unsubstituted fused aromatic hydrocarbon group having 10 to 30 ring carbon atoms, an unsubstituted aromatic heterocyclic group having 2 to 30 ring carbon atoms, or an unsubstituted fused aromatic heterocyclic group having 2 to 30 ring carbon atoms,
adjacent ones of Y1 to Y4 are optionally bonded to each other to form a ring structure,
p and q represent an integer of 1 to 4, and r and s represent an integer of 1 to 3, and
when p and q are an integer of 2 to 4 and r and s are an integer of 2 to 3, a plurality of Y1 to Y4 may be the same or different,
(Cz?)aA3  (5)
where:
Cz represents a substituted or unsubstituted arylcarbazolyl group or carbazolylaryl group;
A3 represents a group represented by a formula (7A) below; and
a represents an integer of 1 to 3,
(M1)c?(L5)d?(M2)e  (7A)
where:
M1 and M2 each independently represent a substituted or unsubstituted nitrogen-containing fused aromatic heterocyclic ring having 2 to 40 ring carbon atoms, M1 and M2 being optionally the same or different;
L5 represents a single bond, a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 carbon atoms, a substituted or unsubstituted fused aromatic hydrocarbon group having 10 to 30 carbon atoms, a substituted or unsubstituted cycloalkylene group having 5 to 30 carbon atoms, or a substituted or unsubstituted fused aromatic heterocyclic group having 2 to 30 carbon atoms; and
c represents an integer of 0 to 2, d represents an integer of 1 to 2, and e represents an integer of 0 to 2 with a proviso that c+e is 1 or more.

US Pat. No. 10,193,066

APPARATUS AND TECHNIQUES FOR ANISOTROPIC SUBSTRATE ETCHING

VARIAN SEMICONDUCTOR EQUI...

12. A method of etching a substrate to form a surface feature, comprising:providing a chlorine-containing gas to a plasma chamber;
generating a plasma in the plasma chamber, the plasma comprising an etchant species derived from the chlorine-containing gas;
extracting a pulsed ion beam from the plasma chamber and directing the pulsed ion beam to the substrate, the pulsed ion beam comprising an ON portion and an OFF portion; and
pulsing a level of RF power of the plasma in concert with the pulsed ion beam, wherein the plasma comprises a first RF power level during the ON portion and a second RF power level during the OFF portion, wherein the first RF power level is higher than the second RF power level,
wherein a duration of the OFF portion is less than a transit time of the etchant species from the plasma chamber to the substrate.

US Pat. No. 10,193,064

MEMORY CELLS INCLUDING DIELECTRIC MATERIALS, MEMORY DEVICES INCLUDING THE MEMORY CELLS, AND METHODS OF FORMING SAME

Micron Technology, Inc., ...

1. A memory cell, comprising:a threshold switching material comprising amorphous silicon doped with at least one of boron, aluminum, gallium, or phosphorus;
at least one doped dielectric material between the threshold switching material and at least one electrode of a pair of electrodes, the threshold switching material on a side of the at least one doped dielectric material; and
a memory material on a side of one of the electrodes of the pair of electrodes.

US Pat. No. 10,193,061

SPIN-ORBIT TORQUE MAGNETIZATION ROTATIONAL ELEMENT

TDK CORPORATION, Tokyo (...

1. A spin-orbit torque magnetization rotational element comprising:a ferromagnetic metal layer, a magnetization direction of which is configured to be changed;
a spin-orbit torque wiring bonded to the ferromagnetic metal layer; and
an interfacial distortion supply layer bonded to a surface of the spin-orbit torque wiring on a side opposite to the ferromagnetic metal layer,
wherein a degree of lattice mismatching between the spin-orbit torque wiring and the interfacial distortion supply layer is 5% or more.

US Pat. No. 10,193,056

MINIMAL THICKNESS SYNTHETIC ANTIFERROMAGNETIC (SAF) STRUCTURE WITH PERPENDICULAR MAGNETIC ANISOTROPY FOR STT-MRAM

Headway Technologies, Inc...

1. A synthetic antiferromagnetic free layer structure, comprising:(a) a FL2 layer with intrinsic perpendicular magnetic anisotropy that is comprised of an (A1/A2)n laminate where n is an integer less than 6, A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Mg, Si, V, NiCo, and NiFe, or A1 is Fe and A2 is V, and wherein a magnetization direction thereof is perpendicular-to-plane of the FL2 layer;
(b) a CoFeB layer with perpendicular magnetic anisotropy in which a magnetization direction in said CoFeB layer is perpendicular-to-plane of the CoFeB layer and is established by antiferromagnetic coupling with the FL2 layer through an antiferromagnetic coupling layer formed between the FL2 layer and CoFeB layer; and
(c) the antiferromagnetic coupling layer that is made of a non-magnetic material to give an FL2 layer/antiferromagnetic coupling/CoFeB configuration or a CoFeB/antiferromagnetic coupling/FL2 layer configuration in a magnetic tunnel junction.

US Pat. No. 10,193,054

PIEZOELECTRIC CERAMIC, METHOD FOR PRODUCING PIEZOELECTRIC CERAMIC, AND PIEZOELECTRIC CERAMIC ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A piezoelectric ceramic comprising an alkali niobate compound as a main ingredient, the alkali niobate compound having a perovskite crystal structure represented by AmBO3 and containing at least one alkali metal, whereinSn exists in part of site A and Zr exists in part of site B.

US Pat. No. 10,193,052

DEVICE AND INSPECTION METHOD OF THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A device comprising:a substrate;
an element provided on the substrate;
a film on the substrate, the film and the substrate constituting a cavity in which the element is housed; and
a member provided outside the cavity, and capable of generating heat,
wherein the member generates the heat when current flows through the member.

US Pat. No. 10,193,042

DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate;
a driving circuit disposed on the substrate;
a light-emitting unit disposed on the driving circuit and electrically connected to the driving circuit, wherein the light-emitting unit comprises:
a first semiconductor layer;
a quantum well layer disposed on the first semiconductor layer; and
a second semiconductor layer disposed on the quantum well layer, and the second semiconductor layer comprises a first top surface; and
a first protective layer disposed on the driving circuit and adjacent to the light-emitting unit, and the first protective layer comprises a second top surface and a plurality of conductive elements formed therein,
wherein an elevation of the first top surface is higher than an elevation of the second top surface.

US Pat. No. 10,193,040

LED PACKAGE WITH A PLURALITY OF LED CHIPS

Rohm Co., Ltd., Kyoto (J...

1. An LED package comprising:a substrate having a substrate main surface and a substrate back surface, which face opposite sides in a thickness direction;
a main surface electrode which is disposed on the substrate main surface, the main surface electrode including:
a first pad and a first die pad separated from each other, and
a second pad and a second die pad connected to each other;
a first LED chip which is mounted on the first die pad and has an electrode pad formed on a first chip main surface facing the same direction as the substrate main surface;
a first wire connecting the first pad and the electrode pad;
a second LED chip which is mounted on the second die pad and has a first electrode pad formed on a second chip main surface facing the same direction as the substrate main surface; and
a second wire connecting the second pad and the first electrode pad,
wherein the substrate main surface has a first side along a first direction perpendicular to the thickness direction of the substrate and a second side along a second direction perpendicular to both the thickness direction of the substrate and the first direction,
the first pad has a first base portion in contact with both the first side and the second side of the substrate main surface, and a first pad portion having one end connected to the first base portion,
the first pad portion of the first pad extends from the first base portion toward the first die pad, obliquely with respect to both the first direction and the second direction,
the second pad has a second base portion in contact with the first side of the substrate main surface, and a second pad portion having one end connected to the second base portion, and
the second pad portion of the second pad extends along the second direction.

US Pat. No. 10,193,039

METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, METHOD OF MANUFACTURING LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEM

NICHIA CORPORATION, Anan...

1. A light emitting element mounting base member comprising:recesses formed on at least one surface of the light emitting element mounting base member;
a plurality of electrical conductor cores;
a plurality of light-reflecting insulating members that each cover a lateral surface of each of the electrical conductor cores; and
a light blocking resin that is disposed between the insulating members,
wherein the light blocking resin exposes one or more upper surfaces of the electrical conductor cores, one or more lower surfaces of the electrical conductor cores, and the insulating members disposed around the one or more upper surfaces and the one or more lower surfaces of the electrical conductor cores, and
the light blocking resin serves as lateral surfaces of recesses.

US Pat. No. 10,193,038

THROUGH BACKPLANE LASER IRRADIATION FOR DIE TRANSFER

GLO AB, Lund (SE)

1. A method of manufacturing an assembly of a backplane and light emitting devices, the method comprising:providing a substrate with dies of light emitting devices thereupon, wherein a device-side bonding pad is provided on each of the light emitting devices;
bonding at least one of the light emitting devices to the backplane without bonding at least another of the light emitting devices to the backplane;
dissociating the at least one bonded light emitting device from the substrate by irradiating a laser beam through the substrate and onto each region of the substrate in contact with the at least one bonded light emitting device while the at least another of the light emitting devices remains attached to the substrate and not bonded to the backplane; and
separating the substrate and the at least another of the light emitting devices from an assembly of the backplane and the at least one bonded light emitting device that is bonded to the backplane;
wherein the backplane comprises a metal interconnect layer including a plurality of metal interconnect structures embedded in at least one insulating material and providing electrical connections between the light emitting devices on the backplane and input/output pins of the backplane.

US Pat. No. 10,193,033

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a plurality of light emitting elements each having a pair of electrodes on a lower surface thereof;
a light-transmissive member disposed on an upper surface of each of the light emitting elements to transmit light from the light emitting elements;
a first member disposed on one or more lateral surfaces of the light-transmissive member, and constituting part of an upper surface of the light emitting device with an upper surface of the light-transmissive member being exposed from the first member; and
a second member surrounding an outer periphery of each of the light emitting elements, and constituting part of a bottom-most surface of the light emitting device,
wherein lower surfaces of the electrodes are exposed from the second member to constitute part of the bottom-most surface of the light emitting device,
the first member and the second member respectively constitute parts of an outermost lateral surface of the light emitting device, and
the second member is in contact with a part of each of the light emitting elements.

US Pat. No. 10,193,032

METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a light emitting device comprising:providing a substrate including a placement region for placing a light emitting element on a top surface;
mounting the light emitting element in the placement region; and
forming a frame body surrounding the placement region on the substrate by
arranging a first frame body by discharging a resin material on the substrate to surround the placement region, and
successively arranging a second frame body having a larger diameter than the first frame body on the first frame body and having the same thickness as the first frame body by continuously discharging the resin material from the arranging of the first frame body.

US Pat. No. 10,193,029

LIGHT CONVERSION DEVICE AND DISPLAY DEVICE COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A light conversion device, comprising:a light source; and
a light conversion film provided on one surface of the light source,
wherein the light conversion film includes a first light conversion film containing one first organic fluorescent dye, and a second light conversion film disposed to be closer to the light source than the first light conversion film and containing one second organic fluorescent dye, and a maximum light emission wavelength of the second light conversion film is smaller than a maximum light emission wavelength of the first light conversion film when the light is irradiated from the light source,
wherein the second organic fluorescent dye of the second light conversion film is a green emission fluorescent dye having a maximum emission wavelength of 500 to 550 nm and the first organic fluorescent dye of the first light conversion film is a red emission fluorescent dye having a maximum emission wavelength of 600 to 660 nm, and
wherein the organic fluorescent dye has a full width at half maximum (FWHM) of 60 nm or less and a molecular absorption coefficient of 50,000 to 150,000 M?1 cm?1.

US Pat. No. 10,193,027

LIGHT EMITTING DEVICE AND METHOD OF PRODUCING THE SAME

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a resin package comprising:
a plurality of leads that includes:
a first lead having an upper surface, and
a second lead having an upper surface,
a first resin portion having at least one inner lateral wall surface,
a second resin portion, and
a third resin portion having an upper surface,
the plurality of leads and the at least one inner lateral wall surface of the first resin portion defining a recess,
the third resin portion being located between the first lead and the second lead,
the upper surface of the first lead, the upper surface of the second lead and the upper surface of the third resin portion located at a bottom of the recess, and
the second resin portion disposed surrounding an element mounting region at the bottom of the recess; and
at least one light emitting element disposed on the element mounting region at the bottom of the recess of the resin package,
wherein at least one of the at least one inner lateral wall surface of the recess has at least one protruding portion that protrudes toward the at least one light emitting element, and
wherein a region of the recess between the at least one inner lateral wall surface and the second resin portion is covered by a light-reflective member.

US Pat. No. 10,193,013

LED STRUCTURES FOR REDUCED NON-RADIATIVE SIDEWALL RECOMBINATION

Apple Inc., Cupertino, C...

1. A light emitting diode (LED) comprising:a p-n diode layer including:
a top doped layer doped with a first dopant type;
a bottom doped layer doped with a second dopant type opposite the first dopant type; and
an active layer between the top doped layer and the bottom doped layer; and
p-n diode layer sidewalls spanning the top doped layer, the active layer, and the bottom doped layer; and
a semiconductor passivation layer formed on the p-n diode layer sidewalls spanning the top doped layer, the active layer, and the bottom doped layer, wherein the semiconductor passivation layer spans underneath the bottom doped layer and completely covers a bottom surface of the bottom doped layer.

US Pat. No. 10,193,006

NANOWIRE COMPOSITE STRUCTURE AND METHODS OF FORMING THE SAME, SENSING DEVICE AND METHODS OF FORMING THE SAME AND PROTECTIVE STRUCTURES OF A NANOWIRE

NATIONAL TSING HUA UNIVER...

1. A sensing device, comprising:a substrate;
a first electrode and a second electrode disposed on the substrate; and
a plurality of nanowires disposed on the substrate and between the first electrode and the second electrode, wherein the plurality of nanowires comprises a first nanowire in contact with the first electrode and a second nanowire in contact with the second electrode, and every nanowire of the plurality of nanowires is in contact with at least another nanowire, and wherein the plurality of nanowires is a photo sensor, and the sensing device is used for a bend sensing, a somatosensory sensing or a pressure sensing.

US Pat. No. 10,192,998

ANALOG FLOATING-GATE ATMOMETER

TEXAS INSTRUMENTS INCORPO...

1. A method of measuring evaporation rate, comprising:applying a drain-to-source voltage to a floating-gate transistor in an integrated circuit;
capacitively coupling a voltage to a floating-gate electrode in the floating-gate transistor, to establish a gate-to-source voltage at that transistor;
then dispensing moisture at a surface of the integrated circuit at which an electrode in electrical contact with the floating-gate electrode and at least one reference electrode are exposed;
then monitoring current conducted by the floating-gate transistor to measure an elapsed time at which the current stabilizes; and
determining an evaporation rate responsive to the measured elapsed time.

US Pat. No. 10,192,996

THIN FILM TRANSISTOR, DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising:a base substrate;
an active layer on the base substrate comprising a channel region, a source electrode contact region, and a drain electrode contact region;
an etch stop layer on a side of the channel region distal to the base substrate covering the channel region;
a source electrode on a side of the source electrode contact region distal to the base substrate; and
a drain electrode on a side of the drain electrode contact region distal to the base substrate;
wherein the active layer is made of a semiconductor material comprising M1OaNb, wherein M1 is a single metal or a combination of metals, a>0, and b?0;
the source electrode and the drain electrode are made of a metal material;
the etch stop layer is made of a doped semiconductor material comprising M1OaNb doped with a dopant; the doped semiconductor material being substantially resistant to an etchant for etching the metal material; and
a thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.

US Pat. No. 10,192,994

OXIDE SEMICONDUCTOR FILM INCLUDING INDIUM, TUNGSTEN AND ZINC AND THIN FILM TRANSISTOR DEVICE

Sumitomo Electric Industr...

1. An oxide semiconductor film composed of nanocrystalline oxide or amorphous oxide, whereinthe oxide semiconductor film includes indium, tungsten and zinc,
a content rate of tungsten to a total of indium, tungsten and zinc in the oxide semiconductor film is higher than 0.5 atomic % and equal to or lower than 5 atomic %, and
an electric resistivity of the oxide semiconductor film is equal to or higher than 10?1 ?cm; wherein
an atomic ratio of zinc to tungsten (Zn/W ratio) in the oxide semiconductor film is equal to or higher than 3 and equal to or lower than 30.

US Pat. No. 10,192,993

THIN FILM TRANSFER, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor (TFT), comprising a substrate, a poly-silicon (p-Si) active layer arranged on the substrate, a first amorphous silicon (a-Si) layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate, and a buffer layer arranged on a surface of the substrate at a side adjacent to the first a-Si layer, wherein an orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate, a groove is formed in the buffer layer, and the first a-Si layer is arranged in the groove.

US Pat. No. 10,192,991

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A manufacturing method of an oxide thin film transistor, comprising:providing a substrate;
depositing an active layer film, a gate insulator layer film, and a gate metal layer film on the substrate in sequence, and patterning the active layer film, the gate insulator layer film, and the gate metal layer film to form an active layer, a gate insulator layer and a gate metal layer respectively; and
depositing an insulator layer film at a first temperature and patterning the insulator layer film to form an insulator layer;
wherein a portion of the active layer, which portion is not overlapped with the gate metal layer, is treated to become conductive to provide a conductor during deposition of the insulator layer film.

US Pat. No. 10,192,983

LDMOS WITH ADAPTIVELY BIASED GATE-SHIELD

Silanna Asia Pte Ltd, Si...

1. A system, comprising:a lateral diffusion field effect transistor comprising:
a source region of doped semiconductor material that is electrically coupled to a metallic source contact,
a first drain region of doped semiconductor material that has a lower dopant concentration than the source region,
a second drain region of doped semiconductor material that has a higher dopant concentration than the first drain region and forms an electrically conductive path between the first drain region and a metallic drain contact,
an active region between the source region and the first drain region,
a gate dielectric between a gate electrode and the active region, wherein the active region is responsive to a control signal applied to the gate electrode, and
an electrically conductive shield plate separated from the source contact and respective portions of the gate electrode and the first drain region by an interlayer dielectric; and
a control circuit electrically coupled to the shield plate and configured to apply to the shield plate a variable voltage that is temporally offset from the control signal applied to the gate electrode, wherein the variable voltage is applied to the shield plate at a first level that increases conductivity in the first drain region in a turn-on transition of the lateral diffusion field effect transistor, and the variable voltage is applied to the shield plate at a second level that decreases conductivity in the first drain region in a turn-off transition of the lateral diffusion field effect transistor.

US Pat. No. 10,192,975

LOW TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR

Wuhan China Star Optoelec...

1. A low temperature polycrystalline silicon thin film transistor, wherein: the low temperature polycrystalline silicon thin film transistor comprises: a substrate; a buffer layer formed on the substrate; a semiconductor layer formed on the buffer layer; a gate insulation layer formed on the buffer layer and the semiconductor layer; gates formed on the gate insulation layer; a dielectric layer formed on the gate insulation layer and the gates; a passivation layer formed on the dielectric layer; a first contact hole and a second contact hole formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and sources ad drains source electrodes and drain electrodes formed respectively on the first contact hole and the second contact hole; and the semiconductor layer being a low temperature poly silicon layer, and one of a reflective layer and an insulation layer being disposed between the buffer layer and the semiconductor layer;wherein the low temperature polycrystalline silicon thin film transistor comprises a pixel thin film transistor and a driving thin film transistor; the substrate comprises a pixel region and a peripheral driving region; the pixel region is used for forming the pixel thin film transistor; and the peripheral driving region is used for forming the driving thin film transistor;
the driving thin film transistor comprises a substrate located inside the peripheral driving region, and all the buffer layer, the semiconductor layer, the gate insulation layer, gates, the dielectric layer and the passivation layer are formed sequentially from the top on the substrate inside the peripheral driving region; the first contact hole and the second contact hole are formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and the source electrodes and the drain electrodes are formed respectively on the first contact hole and the second contact hole; wherein the one of the reflective layer and the insulation layer is disposed between the buffer layer and the semiconductor layer; and
wherein the pixel thin film transistor comprises: a substrate inside the pixel region, and all the buffer layer, the semiconductor layer, the gate insulation layer, gates, the dielectric layer and the passivation layer are formed sequentially from the top on the substrate inside the pixel region; the first contact hole and the second contact hole are formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and the source electrodes and the drain electrodes are formed respectively on the first contact hole and the second contact hole.

US Pat. No. 10,192,966

SEMICONDUCTOR DEVICES INCLUDING RECESSED GATE ELECTRODE PORTIONS

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first active pattern and a second active pattern on a substrate;
a first gate electrode and a second gate electrode respectively extending across the first active pattern and the second active pattern;
an insulation pattern located between the first and second gate electrodes to separate the first and second gate electrodes from one another, and
a device isolation layer filling a trench between the first and second active patterns and covering lower sidewalls of the first and second active patterns,
wherein the first gate electrode, the insulation pattern, and the second gate electrode are arranged along a first direction, and
wherein the first gate electrode comprises:
a first part extending in the first direction; and
a second part between the first active pattern and the insulation pattern, the second part including a top surface having a height lower than a height of a top surface of the first part closest to the second part,
wherein the second part vertically overlaps with the device isolation layer, and
wherein the height of the top surface of the second part decreases with approaching the insulation pattern from the first part and then increases again after reaching an inflection point in the top surface of the second part.

US Pat. No. 10,192,965

SEMICONDUCTOR DEVICE INCLUDING FIRST AND SECOND GATE ELECTRODES AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor substrate;
a first gate electrode formed on a main surface of the semiconductor substrate;
a first gate insulating film formed between the first gate electrode and the semiconductor substrate;
a second gate electrode formed on the semiconductor substrate and adjacent to the first gate electrode; and
a second gate insulating film formed between the second gate electrode and the semiconductor substrate and between the second gate electrode and the first gate electrode and having a charge accumulating portion therein,
wherein the semiconductor substrate includes a first region, a second region, and a third region on the main surface side,
the second region is arranged closer to a first side than the first region in a first direction in a plan view,
the third region is arranged between the first region and the second region,
the first gate electrode is formed on a first upper surface of the first region,
the second gate electrode is formed on a second upper surface of the second region,
the second upper surface is lower than the first upper surface,
the third region has a first connection surface connecting the first upper surface and the second upper surface,
the second gate insulating film is formed on the first connection surface and the second upper surface,
a first end of the first connection surface is connected to the second upper surface,
a second end of the first connection surface which is on the opposite side to the first end is connected to the first upper surface,
the first end is arranged closer to the first side than the second end in the first direction, and is arranged lower than the second end, and
the first connection surface has a constant slope between the first end and the second end wherein the semiconductor substrate includes a fourth region on the main surface side, the fourth region is arranged closer to the opposite side to the first side than the first region in the first direction in a plan view, a third upper surface of the fourth region is lower than the first upper surface, and the second upper surface is lower than the third upper surface.

US Pat. No. 10,192,962

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor layer, including a front surface having a plurality of first trenches formed therein and having a second trench formed therein in a region between mutually adjacent ones of the plurality of first trenches;
channel regions, formed in regions between the first and second trenches in a surface layer portion of the semiconductor layer;
a first insulating film, covering an inner surface of each of the first trenches at a bottom portion side of each of the first trenches;
a field plate electrode, embedded in each of the first trenches so as to face the semiconductor layer across the first insulating film;
a first gate insulating film covering a lateral surface of each of the first trenches above the first insulating film in each of the first trenches;
a first gate electrode, embedded at an opening portion side of each of the first trenches so as to face the channel regions across the first gate insulating film;
a second insulating film, interposed between the field plate electrode and the first gate electrode in each of the first trenches;
an embedded insulating film, embedded at a bottom portion side of the second trench;
a second gate insulating film covering a lateral surface of the second trench above the embedded insulating film in the second trench; and
a second gate electrode, embedded at an opening portion side of the second trench so as to face the channel regions across the second gate insulating film.

US Pat. No. 10,192,954

JUNCTIONLESS NANOWIRE TRANSISTOR AND MANUFACTURING METHOD FOR THE SAME

Wuhan China Star Optoelec...

1. A junctionless nanowire transistor, comprising:an active layer, a barrier layer, a source region, a source electrode, a drain region, a drain electrode, a gate electrode, first insulation medium and at least two channel nanowires;
wherein, the source region and the drain region are disposed on the active layer; the at least two channel nanowires are disposed above the active layer in a stacked arrangement, and two terminals of each of the at least two channel nanowires are respectively connected with the source region and the drain region; the barrier layer is located at a side of the active layer away from the source region and the drain region; the source electrode and the drain electrode are respectively disposed on the source region and the drain region; the first insulation medium is disposed between the at least two channel nanowires and the gate electrode;
the source region, the drain region and the at least two channel nanowires uses a same doping material; and
the source electrode, the drain electrode and the gate electrode are manufactured by a same material; and
the junctionless nanowire transistor further comprises a second insulation medium having a first part, a second part and a third part, wherein the first part of the second insulation medium is disposed on the active layer and surrounds bottoms of the source region, the drain region and the gate electrode so as to expose tops of the source region and the drain region, the second part and the third part of the second insulation medium are disposed at two sides of the gate electrode.

US Pat. No. 10,192,948

AMOLED DISPLAY DEVICE AND ARRAY SUBSTRATE THEREOF

SHENZHEN CHINA STAR OPTOE...

1. An array substrate of an AMOLED display device, comprising a baseplate, a surface-shaped power line, a point-shaped power line, and a plurality of insulating layers arranged between the surface-shaped power line and the point-shaped power line,wherein the surface-shaped power line and the point-shaped power line are configured to provide a positive polarity power source to a light-emitting diode; and
wherein the surface-shaped power line is formed on the baseplate, the point-shaped power line is formed on the plurality of insulating layers, and the surface-shaped power line and the point-shaped power line are electrically connected to each other through a via hole;
further comprising a metal lead wire formed on an edge area thereof, wherein the metal lead wire is used for leading a power source signal to the surface-shaped power line;
wherein the metal lead wire and the point-shaped power line are arranged in a same layer, and the metal lead wire and the surface-shaped power line are electrically connected to each other through a via hole.

US Pat. No. 10,192,944

THIN FILM TRANSISTOR ARRAY PANEL WITH DIFFUSION BARRIER LAYER AND GATE INSULATION LAYER AND ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor array panel comprising:a substrate;
a semiconductor disposed on the substrate;
a first gate insulation layer disposed on the semiconductor;
a first diffusion barrier layer disposed on the first gate insulation layer;
a second diffusion barrier layer disposed on the first gate insulation layer and in contact with a lateral surface of the first diffusion barrier layer;
a first gate electrode disposed on the first diffusion barrier layer; and
a source electrode and a drain electrode connected to the semiconductor,
wherein the semiconductor is between the substrate and the first diffusion barrier layer, and
wherein the first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal.

US Pat. No. 10,192,940

DOUBLE SIDED ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND ITS MANUFACTURING METHOD THEREOF

Wuhan China Star Optoelec...

1. A manufacturing method for a double sided organic light-emitting display apparatus, comprising:providing a rigid substrate;
forming at least one transmission flexible substrate and at least one reflective flexible substrate on the rigid substrate;
forming a display substrate having a plurality of switching elements on the at least one transmission flexible substrate and the at least one reflective flexible substrate; and
forming at least one top-emission OLED light-emitting layer and at least one bottom-emission OLED light-emitting layer on the display substrate, wherein the at least one top-emission OLED light-emitting layer is corresponding to the at least one reflective flexible substrate and the at least one bottom-emission OLED light-emitting layer is corresponding to the at least one transmission flexible substrate;
wherein the at least one transmission flexible substrate and the at least one reflective flexible substrate are formed on a surface of the rigid substrate and are spaced from and corresponding to the at least one bottom-emission OLED light-emitting layer and the at least one top-emission OLED light-emitting layer, such that the at least one top-emission OLED light-emitting layer is separated by the display substrate from the at least one reflective flexible substrate.

US Pat. No. 10,192,935

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device having a substrate, comprising:a light shielding layer on the substrate;
first, second, third and fourth subpixels sequentially arranged on the substrate in a horizontal direction;
a first power line disposed on one side of the first subpixel and connected to the first and second subpixels;
a sensing line disposed between the second subpixel and the third subpixel and connected to the first to fourth subpixels;
a second power line disposed on one side of the fourth subpixel and connected to the third and fourth subpixels;
first and second data lines disposed between the first subpixel and the second subpixel and third and fourth data lines disposed between the third subpixel and the fourth subpixel; and
a scan line on the first to fourth subpixels and extended to the horizontal direction,
wherein the first to fourth data lines, the sensing line, and the first and second power lines are disposed on the same plane as the light shielding layer.

US Pat. No. 10,192,931

COMPLEMENTARY THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A complementary thin film transistor, comprising:a substrate defined by an n-type transistor region and a p-type transistor region adjacent to the n-type transistor region;
an n-type semiconductor layer disposed on the substrate and within the n-type transistor region, wherein the n-type semiconductor layer comprises a metal oxide material, and the metal oxide material of the n-type semiconductor layer is selected from indium gallium zinc oxide, indium zinc oxide or zinc tin oxide;
a p-type semiconductor layer disposed on the substrate and within the p-type transistor region, wherein the p-type semiconductor layer comprises organic semiconductor material; and
an etched barrier layer formed on the n-type semiconductor layer and disposed within the n-type transistor region and the p-type transistor region, wherein the p-type semiconductor layer is formed on the etched barrier layer and the organic semiconductor material of the p-type semiconductor layer is selected from pentacene, triphenylamine, fullerene, phthalocyanine, perylene derivative, or cyanine; and
a buffer layer formed on the whole etched barrier layer and disposed within the n-type transistor region and the p-type transistor region.

US Pat. No. 10,192,924

IMAGE PICKUP DEVICE AND IMAGE PICKUP APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device comprising:a substrate;
a first photoelectric conversion region disposed in the substrate;
a second photoelectric conversion region disposed in the substrate, the second photoelectric conversion region being adjacent to the first photoelectric conversion region;
a third photoelectric conversion region disposed in the substrate, the third photoelectric conversion being adjacent to the second photoelectric conversion region;
a first trench disposed between the first photoelectric conversion region and the second photoelectric conversion region; and
a second trench disposed between the second photoelectric conversion region and the third photoelectric conversion region,
wherein an area of the first photoelectric conversion region is larger than an area of the second photoelectric conversion region in a cross-sectional view,
wherein, in the cross-sectional view, the first trench extends a first distance along a first sidewall of the first photoelectric conversion region, wherein the first distance is taken along the first side wall from a first light receiving surface of the first photoelectric conversion region to an end of the first trench,
wherein, in the cross-sectional view, the second trench extends a second distance along a second sidewall of the second photoelectric conversion region, wherein the second distance is taken along the second sidewall from a second light receiving surface of the second photoelectric conversion region to an end of the second trench, and
wherein the first distance is greater than the second distance.

US Pat. No. 10,192,922

CHARGE PACKET SIGNAL PROCESSING USING PINNED PHOTODIODE DEVICES

SEMICONDUCTOR COMPONENTS ...

1. An image sensor, comprising:an image pixel comprising a first pinned photodiode coupled to a pixel output line; and
analog-to-digital conversion (ADC) circuitry coupled to the pixel output line, wherein the ADC circuitry comprises:
a second pinned photodiode;
a comparator with first and second inputs;
a sampling transistor;
a first capacitive node that is coupled between the second pinned photodiode the first input of the comparator; and
a second capacitive node that is coupled between the sampling transistor and the second input of the comparator.

US Pat. No. 10,192,921

SOLID STATE IMAGING DEVICE FOR REDUCING DARK CURRENT, METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS

Sony Corporation, Tokyo ...

1. A solid state imaging device, comprising:a semiconductor substrate comprising a light sensing section and comprising a first surface and a second surface opposite to the first surface, wherein the first surface is at a light incident side of the semiconductor substrate;
a wiring layer on the second surface; and
at least three layers over the first surface, the at least three layers comprising a first layer, a second layer, and a third layer,
wherein the first layer and the third layer are insulating layers, and the second layer comprises a material selected from the group including hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), erbium oxide (Er2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3), yttrium oxide (Y2O3), hafnium nitride, aluminum nitride, hafnium oxide nitride, and aluminum oxide nitride,
wherein the second layer is disposed between the first layer and third layer,
wherein the light sensing section includes at least a first light receiving surface and a second light receiving surface and a pixel separating region,
wherein the pixel separating region is disposed between the first light receiving surface and the second light receiving surface, and
wherein at least one of the first layer, the second layer, and the third layer is disposed over the first light receiving surface, the second light receiving surface, and the pixel separating region.

US Pat. No. 10,192,912

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE

Sony Semiconductor Soluti...

1. A back-illuminated type solid-state imaging device comprising:a first layer including at least one of an amplification transistor, a reset transistor, or a selection transistor;
a second layer including at least one photo diode, the second layer separated from the first layer in a depth direction;
a transfer transistor configured to control charge transfer of the photo diode, wherein the transfer transistor is at least partially disposed in the second layer; and
a floating diffusion configured to receive charge transferred from the photo diode, wherein the floating diffusion penetrates the first layer such that the photo diode is in electrical communication with the at least one of an amplification transistor, a reset transistor, or a selection transistor via the floating diffusion,
wherein the floating diffusion is formed at a position including the second layer.

US Pat. No. 10,192,911

HYBRID IMAGE SENSORS WITH IMPROVED CHARGE INJECTION EFFICIENCY

APPLE INC., Cupertino, C...

1. Imaging apparatus, comprising:a photosensitive medium configured to convert incident photons into charge carriers;
a bias electrode, which is at least partially transparent, overlying the photosensitive medium and configured to apply a bias potential to the photosensitive medium;
an array of pixel circuits formed on a semiconductor substrate, each pixel circuit defining a respective pixel and comprising:
a pixel electrode coupled to collect the charge carriers from the photosensitive medium;
a readout circuit configured to output a signal indicative of a quantity of the charge carriers collected by the pixel electrode;
a skimming gate coupled between the pixel electrode and the readout circuit; and
a shutter gate coupled in parallel with the skimming gate between a node in the pixel circuit and a sink site; and
control circuitry coupled to sequentially open and close the shutter gate and the skimming gate of each of the pixels in each of a sequence of image frames so as to apply a global shutter to the array and then to read out the collected charge carriers via the skimming gate to the readout circuit,
wherein the pixel circuit comprises:
a charge storage node between the skimming gate and the readout circuit;
at least one charge transfer gate that connects to the charge storage node; and
a reset gate coupled between the charge transfer gate and a reset potential and configured to reset the charge stored on the charge storage node under control of the control circuitry,
wherein the control circuitry is configured, in each of the image frames, to actuate one of the gates so as to fill a potential well at the pixel electrode with charge carriers, and then to close the shutter gate, whereby the charge carriers acquired at the pixel electrode from the photosensitive medium is transferred through the skimming gate to the readout circuit,
wherein while the one of the gates is actuated, a potential well of the charge storage node is filled with the charge carriers, and wherein the control circuitry is configured, prior to acquiring the charge carriers, to actuate the reset gate and the at least one charge transfer gate so as to allow the charge carriers to drain from the charge storage node while the charge carriers remain in the potential well at the pixel electrode, and
wherein the control circuitry is configured to apply a charge pump signal so as to inject an additional number of the charge carriers into the potential well of the pixel electrode after the acquisition of the photocharge but before reading out the charge carriers to the readout circuit.

US Pat. No. 10,192,906

TOUCH DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of a touch display substrate, comprising steps of:forming a touch signal line on a base substrate through patterning process;
depositing a photoresist layer and forming a first thickness photoresist layer, a second thickness photoresist layer, and a photoresist layer opening area through patterning process, the touch signal line being located in the photoresist layer opening area;
depositing a first insulating layer on the photoresist layer, the first insulating layer comprising a first area and a second area, wherein the first area is located on the first thickness photoresist layer, the second area is located on the second thickness photoresist layer and the photoresist layer opening area, the first area and the second area of the first insulating layer are disconnected;
removing the photoresist layer and the first insulating layer located on the photoresist layer; and
depositing a second insulating layer.

US Pat. No. 10,192,905

ARRAY SUBSTRATES AND THE MANUFACTURING METHODS THEREOF, AND DISPLAY DEVICES

Shenzhen China Star Optoe...

1. A manufacturing method of array substrates, the method adopting four masking processes to obtain the array substrate and at least one pixel electrode within the array substrate, wherein a second masking process to form an active layer, a source electrode, and a drain electrode comprising:forming a semiconductor thin-film layer, N+ doping thin-film layer, a metal thin-film layer, and a photo-resistor layer on a gate insulation layer in sequence;
applying a gray-tone-mask process to expose and develop the photo-resistor layer to obtain a first photo-resistor mask;
under protection of the first photo-resistor mask, applying a first wet etching process to etch a portion of the metal thin-film layer that is not covered by the first photo-resistor mask;
under the protection of the first photo-resistor mask, applying a first dry etching process to etch portions of the semiconductor thin-film layer and the N+ doping thin-film layer that are not covered by the first photo-resistor mask to obtain the active layer;
applying a plasma ashing process to the first photo-resistor mask to obtain a second photo-resistor mask, and the metal thin-film layer is exposed by a central area of the second photo-resistor mask;
under the protection of the second photo-resistor mask, applying a second wet etching process to etch away a portion of the metal thin-film layer that is not covered by the second photo-resistor mask to obtain the source electrode and the drain electrode; and
peeling off the second photo-resistor mask, applying a second dry etching process to etch away the portion of the N+ doping thin-film layer between the source electrode and the drain electrode to obtain the N+ contact layer respectively between the source electrode and the active layer and between the drain electrode and the active layer.

US Pat. No. 10,192,903

METHOD FOR MANUFACTURING TFT SUBSTRATE

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing a TFT substrate, comprising:step 101: providing a substrate and depositing a buffer layer on the substrate, wherein the substrate includes a drive TFT region and a display TFT region;
step 102: depositing a first amorphous silicon layer on the buffer layer, and performing excimer laser annealing on the first amorphous silicon layer so as to convert the first amorphous silicon layer into a first polysilicon layer through crystallization;
patterning the first polysilicon layer, to obtain a first active layer that is located in the drive TFT region;
step 103: depositing a gate insulating layer on the first active layer and the buffer layer;
depositing and patterning a first metal layer on the gate insulating layer, to form a first gate electrode at a position corresponding to position of the first active layer and form a second gate electrode at a position corresponding to position where the first active layer is not arranged;
step 104: implanting ions into the gate insulating layer taking the first gate electrode and the second gate electrode as a shading layer;
step 105: depositing an interlayer insulating layer on the gate insulating layer, the first gate electrode and the second gate electrode, depositing a second amorphous silicon layer on the interlayer insulating layer, implanting ions into the second amorphous silicon layer, and performing solid phase crystallization on the second amorphous silicon layer so as to convert the second amorphous silicon layer into a second polysilicon layer;
patterning the second polysilicon layer to form a second active layer at a position corresponding to the second gate electrode;
wherein the second amorphous silicon layer is implanted with boron (B) ions;
step 106: forming a first via hole and a second via hole in the gate insulating layer and the interlayer insulating layer corresponding to the first active layer, and forming a third via hole in the interlayer insulating layer corresponding to the second gate electrode;
step 107: depositing a source-drain electrode layer, patterning the source-drain electrode layer, and forming a channel on a surface of the second active layer at the same time;
step 108: depositing a passivation layer and patterning the passivation layer, depositing a flat layer on the passivation layer, and forming a fourth via hole in the flat layer at a position thereof in the display TFT region, the fourth via hole extending to a surface of the source-drain electrode layer; and
step 109: depositing an anode electrode on the flat layer, the anode electrode being in contact with the source-drain electrode layer through a fourth via hole, depositing a pixel definition layer, and defining a pattern, so that the TFT substrate is manufactured.

US Pat. No. 10,192,902

LTPS ARRAY SUBSTRATE

Shenzhen China Star Optoe...

1. A low temperature poly-silicon (LTPS) array substrate, comprising:a substrate;
a source electrode and a drain electrode, which are arranged on the substrate;
a poly-silicon layer, which is arranged on the substrate including the source electrode and the drain electrode, wherein the poly-silicon layer partially covers the source electrode and the drain electrode;
an insulating layer, which is arranged on the poly-silicon layer and the source and drain electrodes, wherein the insulating layer is formed through passivation of a part of the poly-silicon layer that covers the substrate including the source electrode and the drain electrode;
a gate electrode, which is arranged on the insulating layer between the source electrode and the drain electrode, wherein the source and drain electrodes, the poly-silicon layer, and the gate electrode collectively form a thin-film transistor (TFT);
a planar layer, which is arranged on the substrate including the gate electrode, wherein the planar layer is formed with a contact hole extending therethrough to expose a surface of the drain electrode;
a common electrode, which is arranged on the planar layer except the TFT of the LTPS array substrate;
a passivation layer, which is arranged on the planar layer and the common electrode layer, such that the passivation layer does not cover the contact hole;
a pixel electrode, which is arranged on the passivation layer, wherein the pixel electrode is electrically connected with the drain electrode through the contact hole;
wherein the poly-silicon layer has a first region that is stacked atop and covers an inner part of each of the source electrode and the drain electrode and a portion of the substrate that is between the source electrode and the drain electrode and a second region that is integrally extended from the first region and is partly stacked atop and covers an outer part of each of the source electrode and the drain electrode; and
wherein the first region of the poly-silicon has a thickness that is greater than a thickness of the second region of the poly-silicon and the first region of the poly-silicon has a lower part in direct contact with the inner parts of the source electrode and the drain electrode and the portion of substrate between the source electrode and the drain electrode and an upper part that forms a first portion of the insulating layer; and the second region of the poly-silicon, in the entirety thereof, forms a second portion of the insulating layer that integrally extends from the first portion of the insulating layer, such that the insulating layer is integrally combined with the lower part of the poly-silicon layer and is extended to cover the source electrode and the drain electrode.

US Pat. No. 10,192,900

METHODS FOR FABRICATING THIN FILM TRANSISTOR AND ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A fabrication method of a thin film transistor, comprising an operation of forming an active layer, a source electrode and a drain electrode of a thin film transistor, wherein the source electrode and the drain electrode are separately provided on two sides of the active layer, an interval is provided between the source electrode and the drain electrode to define a channel area, the operation of forming the active layer, the source electrode and the drain electrode of the thin film transistor comprises:forming an active layer film;
forming a first photoresist pattern on the active layer film, wherein the first photoresist pattern covers an area of the active layer film for forming the active layer, the first photoresist pattern comprises a photoresist area of a first thickness and a photoresist area of a second thickness, a thickness of the photoresist area of the first thickness is greater than a thickness of the photoresist area in the second thickness, and the photoresist area of the first thickness corresponds to the area of the active layer film for forming the channel area;
etching the active layer film by using the first photoresist pattern as a mask to form the active layer;
ashing the first photoresist pattern to remove the photoresist area of the second thickness and to reduce the thickness of the photoresist area of the first thickness to form a second photoresist pattern, which corresponds to the area of the active layer for forming the channel area;
forming a source-drain electrode film on the active layer and the second photoresist pattern;
forming a third photoresist pattern on the source-drain electrode film;
etching the source-drain electrode film by using the third photoresist pattern as a mask to form the source electrode and the drain electrode and to expose the second photoresist pattern; and
stripping off the second photoresist pattern and the third photoresist pattern;
wherein a distance between photoresist that covers a position where the source electrode is to be formed in the source-drain electrode film and photoresist that covers a position where the drain electrode is to be formed in the source-drain electrode film in the third photoresist pattern is equal to a width of the second photoresist pattern between these positions correspondingly.

US Pat. No. 10,192,894

THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor comprising, successively from the bottom up, a gate, a first common electrode located in a same layer as the gate, a gate insulating layer, an active layer, a pixel electrode, a source-drain electrode layer and a passivation layer located above the layer where the gate is located, and a second common electrode located on the passivation layer, wherein,the thin film transistor further comprises at least one connection electrode located in a same layer as the pixel electrode, wherein at least two via holes are provided between the first common electrode and the second common electrode so as to connect the first common electrode and the second common electrode through the connection electrode.

US Pat. No. 10,192,891

THIN FILM TRANSISTOR AND DISPLAY DEVICE COMPRISING THE SAME

JOLED INC., Tokyo (JP)

1. A thin film transistor comprising:an oxide semiconductor layer provided above an insulating substrate and including a source region, a drain region and a channel region between the source region and the drain region;
a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region;
a gate electrode provided on the first insulating film;
a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal;
a second protective film provided on the first protective film; and
a third protective film provided on the second protective film, as an insulating film containing a metal, wherein the first protective film directly contacts sidewalls and a top surface of the gate electrode, wherein the third protective film is thicker than the first protective film.

US Pat. No. 10,192,890

TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THEREOF

Samsung Display Co., Ltd,...

1. A transistor display panel comprising:a substrate; and
a transistor disposed on the substrate,
wherein the transistor comprises:
a gate electrode disposed on the substrate;
a semiconductor that overlaps the gate electrode;
an upper electrode disposed on the semiconductor and overlapping the gate electrode;
a source connection member and a drain connection member disposed on the same layer as the upper electrode and respectively connected with the semiconductor;
a source electrode connected with the source connection member and the upper electrode; and
a drain electrode connected with the drain connection member.

US Pat. No. 10,192,889

DISPLAY DEVICE AND METHOD OF MANUFACTURING A DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a first substrate including a display area and a non-display area;
a gate line and a gate electrode in the display area;
a data line connected to the gate line;
a gate insulating layer on the gate line and the gate electrode;
a semiconductor layer on the gate insulating layer;
a drain electrode and a source electrode on the semiconductor layer;
a first passivation layer on the drain electrode and the source electrode;
a color filter on the first passivation layer;
a common electrode on the first passivation layer;
a second passivation layer on the common electrode; and
a pixel electrode on the second passivation layer,
wherein the gate insulating layer has substantially a same shape as a shape of the gate electrode,
wherein the gate insulating layer has a width wider than a width of the gate electrode,
wherein the gate insulating layer is spaced apart from the first substrate, and
wherein a side surface of the gate electrode is exposed below a bottom surface of the gate insulating layer.

US Pat. No. 10,192,882

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a stacked body including a plurality of conductive layers stacked with an insulator interposed;
a columnar portion extending through the stacked body in a stacking direction of the stacked body; and
a first air gap extending through the stacked body in the stacking direction,
the insulator including
an insulating layer provided at a periphery of a side surface of the columnar portion, and
a second air gap communicating with the first air gap and being provided between the insulating layer and the first air gap,
the insulating layer having a protrusion at an end adjacent to the second air gap.

US Pat. No. 10,192,880

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:gate stacked structures surrounding channel layers;
a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, wherein the first concave portions are arranged in a first direction crossing a lengthwise direction of the channel layer; and
a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.

US Pat. No. 10,192,879

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device having a memory cell of a nonvolatile memory, comprising:a semiconductor substrate;
a first gate electrode formed over the semiconductor substrate via a first gate insulating film; and
a second gate electrode formed over the semiconductor substrate via a multi-layer insulating film, and adjacent to the first gate electrode via the multi-layer insulating film,
wherein the multi-layer insulating film includes a first insulating film, a second insulating film over the first insulating film, and a third insulating film over the second insulating film,
wherein the second insulating film has a charge storing function,
wherein the second gate electrode has a lower surface facing the semiconductor substrate, a first side surface adjacent to the first gate electrode via the multi-layer insulating film, and a second side surface opposite to the first side surface, and
wherein a fourth insulating film is formed between the lower surface of the second gate electrode and the semiconductor substrate and is in contact with the first, second and third insulating films such that the fourth insulating film is located closer to a first end portion of the second side surface of the second gate electrode than to a second end portion of the first side surface of the second gate electrode.

US Pat. No. 10,192,873

MEMORY CELL, AN ARRAY OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR WITH THE ARRAY COMPRISING ROWS OF ACCESS LINES AND COLUMNS OF DIGIT LINES, A 2T-1C MEMORY CELL, AND METHODS OF FORMING AN ARRAY OF CAPACITORS AND ACCESS TRANSISTORS

Micron Technology, Inc., ...

1. A memory cell having a total of only two transistors and a total of only one capacitor, comprising:a capacitor comprising a laterally-outer electrode having an upwardly-open container shape;
a laterally-inner electrode;
a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode;
a lower vertical transistor having an upper source/drain region thereof electrically coupled to the laterally-outer electrode having the upwardly-open container shape; and
an upper vertical transistor having a lower source/drain region thereof electrically coupled to the laterally-inner electrode.

US Pat. No. 10,192,872

MEMORY DEVICE HAVING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first region in electrical contact with said floating body region; and
a back-bias region configured to maintain a charge in said floating body region;
wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity;
wherein said back bias region is commonly connected to at least two of said memory cells,
wherein said back bias region has a lower band gap than a band gap of said floating body region; and
a control circuit configured to provide electrical signals to said back bias region.

US Pat. No. 10,192,871

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor; and
a first circuit,
wherein the transistor includes a first gate and a second gate,
wherein the first gate and the second gate overlap with each other with a semiconductor layer positioned therebetween,
wherein the first circuit includes a temperature sensor and a comparator,
wherein the temperature sensor is configured to obtain temperature information, and
wherein the first circuit is configured to apply, to the second gate, a voltage depending on the temperature information.

US Pat. No. 10,192,870

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a semiconductor substrate of a first conductivity type;
a first semiconductor region of a second conductivity type, selectively provided in one main surface of the semiconductor substrate;
an isolating structure formed by a pn junction of the semiconductor substrate and the first semiconductor region, the isolating structure isolating regions of differing potentials;
a semiconductor element having: a second semiconductor region of the second conductivity type, selectively provided in the one main surface of the semiconductor substrate so as to be separated from the first semiconductor region and electrically connected to an electrode of a minimum potential through a first resistor; a third semiconductor region of the second conductivity type selectively provided inside the first semiconductor region and having a higher impurity concentration than the first semiconductor region; a gate insulating film provided along the semiconductor substrate between the first semiconductor region and the second semiconductor region; and a gate electrode provided along the gate insulating film, the semiconductor element converting a signal referenced to the minimum potential into a signal referenced to a potential differing from the minimum potential; and
a fourth semiconductor region of the first conductivity type selectively provided in the one main surface of the semiconductor substrate so as to be separated from the second semiconductor region at a prescribed distance and electrically connected to the electrode of the minimum potential, the fourth semiconductor region having a higher impurity concentration than the semiconductor substrate,
wherein the second semiconductor region is electrically connected to the fourth semiconductor region through a second resistor, and
wherein the second resistor comprises a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region.

US Pat. No. 10,192,869

REDUCTION OF NEGATIVE BIAS TEMPERATURE INSTABILITY

INTERNATIONAL BUSINESS MA...

1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:an n-channel field effect transistor (nFET), the nFET comprising a high-k dielectric layer on an interlayer, an nFET work function setting metal on the high-k dielectric layer, a cap layer on the nFET work function setting metal, and a pFET work function setting metal on the cap layer, wherein the interlayer is silicon dioxide (SiO2); and
a p-channel field effect transistor (pFET), the pFET comprising the high-k dielectric layer directly on the interlayer, the cap layer directly on the high-k dielectric layer, and the pFET work function setting metal directly on the cap layer, wherein the cap layer is aluminum-based and the pFET work function setting metal is a nitride and metal atoms from the cap layer do not intermix with the interlayer.

US Pat. No. 10,192,868

SEMICONDUCTOR DEVICE AND OPERATION THEREOF

Semiconductor Manufacturi...

1. A semiconductor device, comprising:a substrate;
an active area on the substrate, wherein the active area comprises:
a first active area; and
a second active area positioned along an extension direction of the first active area, wherein the first active area comprises a first component, a second component, and a connection component, and the first component and the second component each directly contact a side of the connection component, wherein the second active area comprises a third component and a fourth component being separated by a groove isolation, and wherein the groove isolation in the second active area corresponds to the connection component in the first active area; and
a first pseudo gate covering the connection component and the groove isolation.

US Pat. No. 10,192,866

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

FUJITSU SEMICONDUCTOR LIM...

1. A semiconductor device, comprising:a semiconductor substrate including a first region and a second region;
a semiconductor layer formed on the upper surface of the semiconductor substrate;
a first impurity region formed in the first region of the semiconductor substrate and including a first impurity;
a second impurity region formed in the second region of the semiconductor layer and including a second impurity;
a first gate insulating film formed on the semiconductor layer in the first region;
a second gate insulating film formed on the semiconductor layer in the second region;
a first gate electrode formed on the first gate insulating film;
a second gate electrode formed on the second gate insulating film;
a first source region and a first drain region formed in the semiconductor layer at both sides of the first gate electrode, and having a conductivity type opposite to a conductivity type of the first impurity region; and
a second source region and a second drain region formed in the semiconductor layer at both sides of the second gate electrode, and having a conductivity type opposite to a conductivity type of the second impurity region, and wherein
a maximum concentration peak of the second impurity in the second region is positioned in the semiconductor layer, a maximum concentration peak of the first impurity in the first region is positioned in the first impurity region.

US Pat. No. 10,192,863

SERIES CONNECTED ESD PROTECTION CIRCUIT

Texas Instruments Incorpo...

1. An electrostatic discharge (ESD) protection circuit, comprising:a substrate;
an n-type buried layer formed below a surface of the substrate;
a first terminal formed on the surface of the substrate;
a second terminal formed on the surface of the substrate;
a first ESD protection device having a first current path connecting between the first terminal and the n-type buried layer, the first ESD protection device including a first NPN bipolar transistor having a collector positioned in the n-type buried layer; and
a second ESD protection device having a second current path connecting between the second terminal and the n-type buried layer, the second current path arranged in series with the first current path, the second ESD protection device including a second NPN bipolar transistor having an emitter positioned in the n-type buried layer,
wherein the first NPN bipolar transistor has a first base that is electrically isolated from a second base of the second NPN transistor.

US Pat. No. 10,192,861

OPC METHOD FOR A SHALLOW ION IMPLANTING LAYER

SHANGHAI HUALI MICROELECT...

1. An OPC method for a shallow ion implanting layer, providing a shallow ion implanting original layout and other layers corresponding to the shallow ion implanting original layout include an active area layer, a contact hole layer and a poly-silicon layer, wherein the active area layer includes an active region pattern, the contact hole layer includes a contact hole pattern and the poly-silicon layer includes a ploy-silicon pattern; wherein the method comprising the following steps of:S01: selecting a valid device region in an implanting active region of the shallow ion implanting original layout; wherein a portion other than an active region pattern in an active area layer is a STI region, the shallow ion implanting original layout includes a shallow ion implanting region and a non-shallow ion implanting region, and a portion overlapped between the shallow ion implanting region and the active region pattern in the active area layer is the implanting active region; a portion to remain the implanting active region which touches to the contact hole pattern in the contact hole layer is a valid device region, and anther portion to remain the implanting active region which does not touch to the contact hole pattern in the contact hole layer is a non-device invalid region;
S02: selecting a region in the valid device region which is contacted with a poly-silicon pattern in a poly-silicon layer, as a poly-silicon contacting region, and selecting a region in the valid device region which is not contacted with the poly-silicon pattern in the poly-silicon layer, as a non poly-silicon contacting region;
S03: extending the length and width of the poly-silicon contacting region and the non poly-silicon contacting region, to form a new poly-silicon contacting region and a new non poly-silicon contacting region; wherein the new poly-silicon contacting region and the new non poly-silicon contacting region are located in any region except the active region pattern touching with the contact hole pattern in the non-shallow ion implanting region;
S04: combining one gap portion or more gap portions which an interval between any two new poly-silicon contacting regions and/or new non poly-silicon contacting regions after extending is smaller than or equal to G, with the poly-silicon contacting regions and the non poly-silicon contacting regions after extending, to form a correction target layer, wherein G is an interval safe value determined according to the actual process capability;
S05: performing a model-based OPC correction on the correction target layer, and to obtain a mask layer.

US Pat. No. 10,192,860

ENGINEERING CHANGE ORDER (ECO) CELL, LAYOUT THEREOF AND INTEGRATED CIRCUIT INCLUDING THE ECO CELL

Samsung Electronics Co., ...

1. An integrated circuit (IC) comprising:an integrated circuit substrate;
a plurality of standard cells on said integrated circuit substrate; and
at least one engineering change order (ECO) base cell on the integrated circuit substrate;
wherein the ECO base cell has a layout that is generated based on a layout of a functional cell corresponding to a first circuit including a plurality of logic gates having different logic configurations relative to each other;
wherein the layout of the ECO base cell includes a plurality of spaced-apart and dissimilar regions that are each associated with a respective one of the plurality of logic gates, with each of the plurality of dissimilar regions comprising a plurality of spaced-apart active regions and a plurality of gate lines overlapping the plurality of spaced-apart active regions; and
wherein the plurality of gate lines are disposed asymmetrically on said integrated circuit substrate so that the gate lines within at least two of the plurality of dissimilar regions lack symmetry relative to each other and relative to an axis extending between the at least two of the plurality of dissimilar regions.

US Pat. No. 10,192,859

INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:a substrate having a semiconducting surface; and
a structure formed in and on the semiconducting surface, the structure including a first block of standard cells, and at least a second block,
the first and second blocks arranged in a horizontal row, and at least partially aligned in height, such that at least a portion of a first vertical block boundary of the first block is adjacent to and aligned with at least a portion of a second vertical block boundary of the second block, thereby defining a region of alignment between the first and second blocks,
the first block including a first base level extending across a portion but not all of the first vertical block boundary to form a first vertical base-level boundary at least partially within the region of alignment,
the second block including a second base level extending across a portion but not all of the second vertical block boundary to form a second vertical base-level boundary at least partially within the region of alignment;
the first and second blocks placed on the semiconducting surface such that the blocks are separated by a protective separation strip between the blocks;
the first block including a first DWD1 dimension between its first vertical block boundary, and the second vertical base-level boundary of the second base level,
the second block including a second DWD1 dimension between its second vertical block boundary, and the first vertical base-level boundary of the first base level,
the separation strip having a uniform width dimension DWD1 between a vertical block boundary and a vertical base-level boundary,
the DWD1 dimension defined such that a minimum separation exists between the first and second vertical base-level boundaries corresponding to the protective separation strip.