US Pat. No. 10,193,060

MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A magnetoresistive random access memory (MRAM) device, comprising:an insulating interlayer on a substrate, the insulating interlayer including an opening therethrough;
a first electrode in a lower portion of the opening, the first electrode having a pillar shape;
a second electrode on a sidewall of the opening, the second electrode contacting an edge portion of the first electrode and vertically protruding from an upper surface of the first electrode, and an upper surface of the second electrode having a ring shape;
an insulation pattern on the second electrode, the insulation pattern filling an upper portion of the opening; and
a variable resistance structure on the second electrode and the insulation pattern, the variable resistance structure including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked, wherein
the variable resistance structure includes a plurality of variable resistance structures,
an upper surface of the insulating interlayer between the plurality of variable resistance structures is lower than the upper surface of the second electrode, and is higher than the upper surface of the first electrode, and
an upper surface of the insulating interlayer under the variable resistance structure is higher than the upper surface of the insulating interlayer between the plurality of variable resistance structures.

US Pat. No. 10,193,056

MINIMAL THICKNESS SYNTHETIC ANTIFERROMAGNETIC (SAF) STRUCTURE WITH PERPENDICULAR MAGNETIC ANISOTROPY FOR STT-MRAM

Headway Technologies, Inc...

1. A synthetic antiferromagnetic free layer structure, comprising:(a) a FL2 layer with intrinsic perpendicular magnetic anisotropy that is comprised of an (A1/A2)n laminate where n is an integer less than 6, A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Mg, Si, V, NiCo, and NiFe, or A1 is Fe and A2 is V, and wherein a magnetization direction thereof is perpendicular-to-plane of the FL2 layer;
(b) a CoFeB layer with perpendicular magnetic anisotropy in which a magnetization direction in said CoFeB layer is perpendicular-to-plane of the CoFeB layer and is established by antiferromagnetic coupling with the FL2 layer through an antiferromagnetic coupling layer formed between the FL2 layer and CoFeB layer; and
(c) the antiferromagnetic coupling layer that is made of a non-magnetic material to give an FL2 layer/antiferromagnetic coupling/CoFeB configuration or a CoFeB/antiferromagnetic coupling/FL2 layer configuration in a magnetic tunnel junction.

US Pat. No. 10,193,054

PIEZOELECTRIC CERAMIC, METHOD FOR PRODUCING PIEZOELECTRIC CERAMIC, AND PIEZOELECTRIC CERAMIC ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A piezoelectric ceramic comprising an alkali niobate compound as a main ingredient, the alkali niobate compound having a perovskite crystal structure represented by AmBO3 and containing at least one alkali metal, whereinSn exists in part of site A and Zr exists in part of site B.

US Pat. No. 10,193,052

DEVICE AND INSPECTION METHOD OF THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A device comprising:a substrate;
an element provided on the substrate;
a film on the substrate, the film and the substrate constituting a cavity in which the element is housed; and
a member provided outside the cavity, and capable of generating heat,
wherein the member generates the heat when current flows through the member.

US Pat. No. 10,193,050

HANDLE FOR A COOKING VESSEL, COMPRISING A LATENT HEAT SINK

SEB S.A., Ecully (FR)

1. A handle for a cooking vessel or lid that comprises at least one thermoelectric generator, wherein the thermoelectric generator comprises at least one first contact surface connected thermally to a heat sink, and the heat sink is comprised of a material that undergoes a phase transition when the material is heated to temperatures of 50° C. to 70° C.,wherein the heat sink fills a cavity of the handle with a heat diffuser comprising one or more rods that extend through the heat sink.

US Pat. No. 10,193,045

LIGHT EMITTING DEVICE HAVING HEAT DISIPATION TERMINAL ARRANGED ON SUBSTRATE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate having a first main surface, a second main surface that is opposite from the first main surface, and a mounting surface that is adjacent to at least the second main surface, the substrate including an insulating base material and a pair of connection terminals;
a plurality of light emitting elements mounted on the first main surface of the substrate;
a sealing member that is in contact with at least a part of a side surface of each of the light emitting elements, is formed substantially in the same plane as the substrate on the mounting surface, and a width of the sealing member between adjacent ones of the light emitting elements is larger than a width of the sealing member on an outside of an outermost one of the light emitting elements;
a light transmissive member that covers upper surfaces of the light emitting elements and a part of an upper surface of the sealing member, side surfaces of the light transmissive member being covered with the sealing member; and
a heat dissipation terminal that is arranged generally in the center on the second main surface of the substrate and that has a recess portion as viewed along a direction normal to the second main surface.

US Pat. No. 10,193,042

DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate;
a driving circuit disposed on the substrate;
a light-emitting unit disposed on the driving circuit and electrically connected to the driving circuit, wherein the light-emitting unit comprises:
a first semiconductor layer;
a quantum well layer disposed on the first semiconductor layer; and
a second semiconductor layer disposed on the quantum well layer, and the second semiconductor layer comprises a first top surface; and
a first protective layer disposed on the driving circuit and adjacent to the light-emitting unit, and the first protective layer comprises a second top surface and a plurality of conductive elements formed therein,
wherein an elevation of the first top surface is higher than an elevation of the second top surface.

US Pat. No. 10,193,040

LED PACKAGE WITH A PLURALITY OF LED CHIPS

Rohm Co., Ltd., Kyoto (J...

1. An LED package comprising:a substrate having a substrate main surface and a substrate back surface, which face opposite sides in a thickness direction;
a main surface electrode which is disposed on the substrate main surface, the main surface electrode including:
a first pad and a first die pad separated from each other, and
a second pad and a second die pad connected to each other;
a first LED chip which is mounted on the first die pad and has an electrode pad formed on a first chip main surface facing the same direction as the substrate main surface;
a first wire connecting the first pad and the electrode pad;
a second LED chip which is mounted on the second die pad and has a first electrode pad formed on a second chip main surface facing the same direction as the substrate main surface; and
a second wire connecting the second pad and the first electrode pad,
wherein the substrate main surface has a first side along a first direction perpendicular to the thickness direction of the substrate and a second side along a second direction perpendicular to both the thickness direction of the substrate and the first direction,
the first pad has a first base portion in contact with both the first side and the second side of the substrate main surface, and a first pad portion having one end connected to the first base portion,
the first pad portion of the first pad extends from the first base portion toward the first die pad, obliquely with respect to both the first direction and the second direction,
the second pad has a second base portion in contact with the first side of the substrate main surface, and a second pad portion having one end connected to the second base portion, and
the second pad portion of the second pad extends along the second direction.

US Pat. No. 10,193,039

METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, METHOD OF MANUFACTURING LIGHT EMITTING DEVICE USING THE LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEMBER, LIGHT EMITTING ELEMENT MOUNTING BASE MEM

NICHIA CORPORATION, Anan...

1. A light emitting element mounting base member comprising:recesses formed on at least one surface of the light emitting element mounting base member;
a plurality of electrical conductor cores;
a plurality of light-reflecting insulating members that each cover a lateral surface of each of the electrical conductor cores; and
a light blocking resin that is disposed between the insulating members,
wherein the light blocking resin exposes one or more upper surfaces of the electrical conductor cores, one or more lower surfaces of the electrical conductor cores, and the insulating members disposed around the one or more upper surfaces and the one or more lower surfaces of the electrical conductor cores, and
the light blocking resin serves as lateral surfaces of recesses.

US Pat. No. 10,193,038

THROUGH BACKPLANE LASER IRRADIATION FOR DIE TRANSFER

GLO AB, Lund (SE)

1. A method of manufacturing an assembly of a backplane and light emitting devices, the method comprising:providing a substrate with dies of light emitting devices thereupon, wherein a device-side bonding pad is provided on each of the light emitting devices;
bonding at least one of the light emitting devices to the backplane without bonding at least another of the light emitting devices to the backplane;
dissociating the at least one bonded light emitting device from the substrate by irradiating a laser beam through the substrate and onto each region of the substrate in contact with the at least one bonded light emitting device while the at least another of the light emitting devices remains attached to the substrate and not bonded to the backplane; and
separating the substrate and the at least another of the light emitting devices from an assembly of the backplane and the at least one bonded light emitting device that is bonded to the backplane;
wherein the backplane comprises a metal interconnect layer including a plurality of metal interconnect structures embedded in at least one insulating material and providing electrical connections between the light emitting devices on the backplane and input/output pins of the backplane.

US Pat. No. 10,193,033

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a plurality of light emitting elements each having a pair of electrodes on a lower surface thereof;
a light-transmissive member disposed on an upper surface of each of the light emitting elements to transmit light from the light emitting elements;
a first member disposed on one or more lateral surfaces of the light-transmissive member, and constituting part of an upper surface of the light emitting device with an upper surface of the light-transmissive member being exposed from the first member; and
a second member surrounding an outer periphery of each of the light emitting elements, and constituting part of a bottom-most surface of the light emitting device,
wherein lower surfaces of the electrodes are exposed from the second member to constitute part of the bottom-most surface of the light emitting device,
the first member and the second member respectively constitute parts of an outermost lateral surface of the light emitting device, and
the second member is in contact with a part of each of the light emitting elements.

US Pat. No. 10,193,032

METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a light emitting device comprising:providing a substrate including a placement region for placing a light emitting element on a top surface;
mounting the light emitting element in the placement region; and
forming a frame body surrounding the placement region on the substrate by
arranging a first frame body by discharging a resin material on the substrate to surround the placement region, and
successively arranging a second frame body having a larger diameter than the first frame body on the first frame body and having the same thickness as the first frame body by continuously discharging the resin material from the arranging of the first frame body.

US Pat. No. 10,193,029

LIGHT CONVERSION DEVICE AND DISPLAY DEVICE COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A light conversion device, comprising:a light source; and
a light conversion film provided on one surface of the light source,
wherein the light conversion film includes a first light conversion film containing one first organic fluorescent dye, and a second light conversion film disposed to be closer to the light source than the first light conversion film and containing one second organic fluorescent dye, and a maximum light emission wavelength of the second light conversion film is smaller than a maximum light emission wavelength of the first light conversion film when the light is irradiated from the light source,
wherein the second organic fluorescent dye of the second light conversion film is a green emission fluorescent dye having a maximum emission wavelength of 500 to 550 nm and the first organic fluorescent dye of the first light conversion film is a red emission fluorescent dye having a maximum emission wavelength of 600 to 660 nm, and
wherein the organic fluorescent dye has a full width at half maximum (FWHM) of 60 nm or less and a molecular absorption coefficient of 50,000 to 150,000 M?1 cm?1.

US Pat. No. 10,193,027

LIGHT EMITTING DEVICE AND METHOD OF PRODUCING THE SAME

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a resin package comprising:
a plurality of leads that includes:
a first lead having an upper surface, and
a second lead having an upper surface,
a first resin portion having at least one inner lateral wall surface,
a second resin portion, and
a third resin portion having an upper surface,
the plurality of leads and the at least one inner lateral wall surface of the first resin portion defining a recess,
the third resin portion being located between the first lead and the second lead,
the upper surface of the first lead, the upper surface of the second lead and the upper surface of the third resin portion located at a bottom of the recess, and
the second resin portion disposed surrounding an element mounting region at the bottom of the recess; and
at least one light emitting element disposed on the element mounting region at the bottom of the recess of the resin package,
wherein at least one of the at least one inner lateral wall surface of the recess has at least one protruding portion that protrudes toward the at least one light emitting element, and
wherein a region of the recess between the at least one inner lateral wall surface and the second resin portion is covered by a light-reflective member.

US Pat. No. 10,193,013

LED STRUCTURES FOR REDUCED NON-RADIATIVE SIDEWALL RECOMBINATION

Apple Inc., Cupertino, C...

1. A light emitting diode (LED) comprising:a p-n diode layer including:
a top doped layer doped with a first dopant type;
a bottom doped layer doped with a second dopant type opposite the first dopant type; and
an active layer between the top doped layer and the bottom doped layer; and
p-n diode layer sidewalls spanning the top doped layer, the active layer, and the bottom doped layer; and
a semiconductor passivation layer formed on the p-n diode layer sidewalls spanning the top doped layer, the active layer, and the bottom doped layer, wherein the semiconductor passivation layer spans underneath the bottom doped layer and completely covers a bottom surface of the bottom doped layer.

US Pat. No. 10,193,006

NANOWIRE COMPOSITE STRUCTURE AND METHODS OF FORMING THE SAME, SENSING DEVICE AND METHODS OF FORMING THE SAME AND PROTECTIVE STRUCTURES OF A NANOWIRE

NATIONAL TSING HUA UNIVER...

1. A sensing device, comprising:a substrate;
a first electrode and a second electrode disposed on the substrate; and
a plurality of nanowires disposed on the substrate and between the first electrode and the second electrode, wherein the plurality of nanowires comprises a first nanowire in contact with the first electrode and a second nanowire in contact with the second electrode, and every nanowire of the plurality of nanowires is in contact with at least another nanowire, and wherein the plurality of nanowires is a photo sensor, and the sensing device is used for a bend sensing, a somatosensory sensing or a pressure sensing.

US Pat. No. 10,192,998

ANALOG FLOATING-GATE ATMOMETER

TEXAS INSTRUMENTS INCORPO...

1. A method of measuring evaporation rate, comprising:applying a drain-to-source voltage to a floating-gate transistor in an integrated circuit;
capacitively coupling a voltage to a floating-gate electrode in the floating-gate transistor, to establish a gate-to-source voltage at that transistor;
then dispensing moisture at a surface of the integrated circuit at which an electrode in electrical contact with the floating-gate electrode and at least one reference electrode are exposed;
then monitoring current conducted by the floating-gate transistor to measure an elapsed time at which the current stabilizes; and
determining an evaporation rate responsive to the measured elapsed time.

US Pat. No. 10,192,996

THIN FILM TRANSISTOR, DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising:a base substrate;
an active layer on the base substrate comprising a channel region, a source electrode contact region, and a drain electrode contact region;
an etch stop layer on a side of the channel region distal to the base substrate covering the channel region;
a source electrode on a side of the source electrode contact region distal to the base substrate; and
a drain electrode on a side of the drain electrode contact region distal to the base substrate;
wherein the active layer is made of a semiconductor material comprising M1OaNb, wherein M1 is a single metal or a combination of metals, a>0, and b?0;
the source electrode and the drain electrode are made of a metal material;
the etch stop layer is made of a doped semiconductor material comprising M1OaNb doped with a dopant; the doped semiconductor material being substantially resistant to an etchant for etching the metal material; and
a thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.

US Pat. No. 10,192,994

OXIDE SEMICONDUCTOR FILM INCLUDING INDIUM, TUNGSTEN AND ZINC AND THIN FILM TRANSISTOR DEVICE

Sumitomo Electric Industr...

1. An oxide semiconductor film composed of nanocrystalline oxide or amorphous oxide, whereinthe oxide semiconductor film includes indium, tungsten and zinc,
a content rate of tungsten to a total of indium, tungsten and zinc in the oxide semiconductor film is higher than 0.5 atomic % and equal to or lower than 5 atomic %, and
an electric resistivity of the oxide semiconductor film is equal to or higher than 10?1 ?cm; wherein
an atomic ratio of zinc to tungsten (Zn/W ratio) in the oxide semiconductor film is equal to or higher than 3 and equal to or lower than 30.

US Pat. No. 10,192,991

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A manufacturing method of an oxide thin film transistor, comprising:providing a substrate;
depositing an active layer film, a gate insulator layer film, and a gate metal layer film on the substrate in sequence, and patterning the active layer film, the gate insulator layer film, and the gate metal layer film to form an active layer, a gate insulator layer and a gate metal layer respectively; and
depositing an insulator layer film at a first temperature and patterning the insulator layer film to form an insulator layer;
wherein a portion of the active layer, which portion is not overlapped with the gate metal layer, is treated to become conductive to provide a conductor during deposition of the insulator layer film.

US Pat. No. 10,192,983

LDMOS WITH ADAPTIVELY BIASED GATE-SHIELD

Silanna Asia Pte Ltd, Si...

1. A system, comprising:a lateral diffusion field effect transistor comprising:
a source region of doped semiconductor material that is electrically coupled to a metallic source contact,
a first drain region of doped semiconductor material that has a lower dopant concentration than the source region,
a second drain region of doped semiconductor material that has a higher dopant concentration than the first drain region and forms an electrically conductive path between the first drain region and a metallic drain contact,
an active region between the source region and the first drain region,
a gate dielectric between a gate electrode and the active region, wherein the active region is responsive to a control signal applied to the gate electrode, and
an electrically conductive shield plate separated from the source contact and respective portions of the gate electrode and the first drain region by an interlayer dielectric; and
a control circuit electrically coupled to the shield plate and configured to apply to the shield plate a variable voltage that is temporally offset from the control signal applied to the gate electrode, wherein the variable voltage is applied to the shield plate at a first level that increases conductivity in the first drain region in a turn-on transition of the lateral diffusion field effect transistor, and the variable voltage is applied to the shield plate at a second level that decreases conductivity in the first drain region in a turn-off transition of the lateral diffusion field effect transistor.

US Pat. No. 10,192,975

LOW TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR

Wuhan China Star Optoelec...

1. A low temperature polycrystalline silicon thin film transistor, wherein: the low temperature polycrystalline silicon thin film transistor comprises: a substrate; a buffer layer formed on the substrate; a semiconductor layer formed on the buffer layer; a gate insulation layer formed on the buffer layer and the semiconductor layer; gates formed on the gate insulation layer; a dielectric layer formed on the gate insulation layer and the gates; a passivation layer formed on the dielectric layer; a first contact hole and a second contact hole formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and sources ad drains source electrodes and drain electrodes formed respectively on the first contact hole and the second contact hole; and the semiconductor layer being a low temperature poly silicon layer, and one of a reflective layer and an insulation layer being disposed between the buffer layer and the semiconductor layer;wherein the low temperature polycrystalline silicon thin film transistor comprises a pixel thin film transistor and a driving thin film transistor; the substrate comprises a pixel region and a peripheral driving region; the pixel region is used for forming the pixel thin film transistor; and the peripheral driving region is used for forming the driving thin film transistor;
the driving thin film transistor comprises a substrate located inside the peripheral driving region, and all the buffer layer, the semiconductor layer, the gate insulation layer, gates, the dielectric layer and the passivation layer are formed sequentially from the top on the substrate inside the peripheral driving region; the first contact hole and the second contact hole are formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and the source electrodes and the drain electrodes are formed respectively on the first contact hole and the second contact hole; wherein the one of the reflective layer and the insulation layer is disposed between the buffer layer and the semiconductor layer; and
wherein the pixel thin film transistor comprises: a substrate inside the pixel region, and all the buffer layer, the semiconductor layer, the gate insulation layer, gates, the dielectric layer and the passivation layer are formed sequentially from the top on the substrate inside the pixel region; the first contact hole and the second contact hole are formed respectively inside the passivation layer, the dielectric layer and the gate insulation layer, and the source electrodes and the drain electrodes are formed respectively on the first contact hole and the second contact hole.

US Pat. No. 10,192,966

SEMICONDUCTOR DEVICES INCLUDING RECESSED GATE ELECTRODE PORTIONS

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first active pattern and a second active pattern on a substrate;
a first gate electrode and a second gate electrode respectively extending across the first active pattern and the second active pattern;
an insulation pattern located between the first and second gate electrodes to separate the first and second gate electrodes from one another, and
a device isolation layer filling a trench between the first and second active patterns and covering lower sidewalls of the first and second active patterns,
wherein the first gate electrode, the insulation pattern, and the second gate electrode are arranged along a first direction, and
wherein the first gate electrode comprises:
a first part extending in the first direction; and
a second part between the first active pattern and the insulation pattern, the second part including a top surface having a height lower than a height of a top surface of the first part closest to the second part,
wherein the second part vertically overlaps with the device isolation layer, and
wherein the height of the top surface of the second part decreases with approaching the insulation pattern from the first part and then increases again after reaching an inflection point in the top surface of the second part.

US Pat. No. 10,192,963

COMPOSITE GATE DIELECTRIC LAYER APPLIED TO GROUP III-V SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

INSTITUTE OF MICROELECTRO...

1. A composite gate dielectric layer for a Group III-V substrate, comprising:an AlxY2-xO3 interface passivation layer formed on the group III-V substrate by thermally treating an Al2Om passivation layer formed on the group III-V substrate and a Y2On strengthening layer formed on the Al2Om passivation layer in situ to mix the Al2Om passivation layer and the Y2On strengthening layer; and
a high-k dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2?x?1.9.

US Pat. No. 10,192,962

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor layer, including a front surface having a plurality of first trenches formed therein and having a second trench formed therein in a region between mutually adjacent ones of the plurality of first trenches;
channel regions, formed in regions between the first and second trenches in a surface layer portion of the semiconductor layer;
a first insulating film, covering an inner surface of each of the first trenches at a bottom portion side of each of the first trenches;
a field plate electrode, embedded in each of the first trenches so as to face the semiconductor layer across the first insulating film;
a first gate insulating film covering a lateral surface of each of the first trenches above the first insulating film in each of the first trenches;
a first gate electrode, embedded at an opening portion side of each of the first trenches so as to face the channel regions across the first gate insulating film;
a second insulating film, interposed between the field plate electrode and the first gate electrode in each of the first trenches;
an embedded insulating film, embedded at a bottom portion side of the second trench;
a second gate insulating film covering a lateral surface of the second trench above the embedded insulating film in the second trench; and
a second gate electrode, embedded at an opening portion side of the second trench so as to face the channel regions across the second gate insulating film.

US Pat. No. 10,192,948

AMOLED DISPLAY DEVICE AND ARRAY SUBSTRATE THEREOF

SHENZHEN CHINA STAR OPTOE...

1. An array substrate of an AMOLED display device, comprising a baseplate, a surface-shaped power line, a point-shaped power line, and a plurality of insulating layers arranged between the surface-shaped power line and the point-shaped power line,wherein the surface-shaped power line and the point-shaped power line are configured to provide a positive polarity power source to a light-emitting diode; and
wherein the surface-shaped power line is formed on the baseplate, the point-shaped power line is formed on the plurality of insulating layers, and the surface-shaped power line and the point-shaped power line are electrically connected to each other through a via hole;
further comprising a metal lead wire formed on an edge area thereof, wherein the metal lead wire is used for leading a power source signal to the surface-shaped power line;
wherein the metal lead wire and the point-shaped power line are arranged in a same layer, and the metal lead wire and the surface-shaped power line are electrically connected to each other through a via hole.

US Pat. No. 10,192,944

THIN FILM TRANSISTOR ARRAY PANEL WITH DIFFUSION BARRIER LAYER AND GATE INSULATION LAYER AND ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor array panel comprising:a substrate;
a semiconductor disposed on the substrate;
a first gate insulation layer disposed on the semiconductor;
a first diffusion barrier layer disposed on the first gate insulation layer;
a second diffusion barrier layer disposed on the first gate insulation layer and in contact with a lateral surface of the first diffusion barrier layer;
a first gate electrode disposed on the first diffusion barrier layer; and
a source electrode and a drain electrode connected to the semiconductor,
wherein the semiconductor is between the substrate and the first diffusion barrier layer, and
wherein the first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal.

US Pat. No. 10,192,940

DOUBLE SIDED ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND ITS MANUFACTURING METHOD THEREOF

Wuhan China Star Optoelec...

1. A manufacturing method for a double sided organic light-emitting display apparatus, comprising:providing a rigid substrate;
forming at least one transmission flexible substrate and at least one reflective flexible substrate on the rigid substrate;
forming a display substrate having a plurality of switching elements on the at least one transmission flexible substrate and the at least one reflective flexible substrate; and
forming at least one top-emission OLED light-emitting layer and at least one bottom-emission OLED light-emitting layer on the display substrate, wherein the at least one top-emission OLED light-emitting layer is corresponding to the at least one reflective flexible substrate and the at least one bottom-emission OLED light-emitting layer is corresponding to the at least one transmission flexible substrate;
wherein the at least one transmission flexible substrate and the at least one reflective flexible substrate are formed on a surface of the rigid substrate and are spaced from and corresponding to the at least one bottom-emission OLED light-emitting layer and the at least one top-emission OLED light-emitting layer, such that the at least one top-emission OLED light-emitting layer is separated by the display substrate from the at least one reflective flexible substrate.

US Pat. No. 10,192,935

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device having a substrate, comprising:a light shielding layer on the substrate;
first, second, third and fourth subpixels sequentially arranged on the substrate in a horizontal direction;
a first power line disposed on one side of the first subpixel and connected to the first and second subpixels;
a sensing line disposed between the second subpixel and the third subpixel and connected to the first to fourth subpixels;
a second power line disposed on one side of the fourth subpixel and connected to the third and fourth subpixels;
first and second data lines disposed between the first subpixel and the second subpixel and third and fourth data lines disposed between the third subpixel and the fourth subpixel; and
a scan line on the first to fourth subpixels and extended to the horizontal direction,
wherein the first to fourth data lines, the sensing line, and the first and second power lines are disposed on the same plane as the light shielding layer.

US Pat. No. 10,192,931

COMPLEMENTARY THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A complementary thin film transistor, comprising:a substrate defined by an n-type transistor region and a p-type transistor region adjacent to the n-type transistor region;
an n-type semiconductor layer disposed on the substrate and within the n-type transistor region, wherein the n-type semiconductor layer comprises a metal oxide material, and the metal oxide material of the n-type semiconductor layer is selected from indium gallium zinc oxide, indium zinc oxide or zinc tin oxide;
a p-type semiconductor layer disposed on the substrate and within the p-type transistor region, wherein the p-type semiconductor layer comprises organic semiconductor material; and
an etched barrier layer formed on the n-type semiconductor layer and disposed within the n-type transistor region and the p-type transistor region, wherein the p-type semiconductor layer is formed on the etched barrier layer and the organic semiconductor material of the p-type semiconductor layer is selected from pentacene, triphenylamine, fullerene, phthalocyanine, perylene derivative, or cyanine; and
a buffer layer formed on the whole etched barrier layer and disposed within the n-type transistor region and the p-type transistor region.

US Pat. No. 10,192,924

IMAGE PICKUP DEVICE AND IMAGE PICKUP APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device comprising:a substrate;
a first photoelectric conversion region disposed in the substrate;
a second photoelectric conversion region disposed in the substrate, the second photoelectric conversion region being adjacent to the first photoelectric conversion region;
a third photoelectric conversion region disposed in the substrate, the third photoelectric conversion being adjacent to the second photoelectric conversion region;
a first trench disposed between the first photoelectric conversion region and the second photoelectric conversion region; and
a second trench disposed between the second photoelectric conversion region and the third photoelectric conversion region,
wherein an area of the first photoelectric conversion region is larger than an area of the second photoelectric conversion region in a cross-sectional view,
wherein, in the cross-sectional view, the first trench extends a first distance along a first sidewall of the first photoelectric conversion region, wherein the first distance is taken along the first side wall from a first light receiving surface of the first photoelectric conversion region to an end of the first trench,
wherein, in the cross-sectional view, the second trench extends a second distance along a second sidewall of the second photoelectric conversion region, wherein the second distance is taken along the second sidewall from a second light receiving surface of the second photoelectric conversion region to an end of the second trench, and
wherein the first distance is greater than the second distance.

US Pat. No. 10,192,922

CHARGE PACKET SIGNAL PROCESSING USING PINNED PHOTODIODE DEVICES

SEMICONDUCTOR COMPONENTS ...

1. An image sensor, comprising:an image pixel comprising a first pinned photodiode coupled to a pixel output line; and
analog-to-digital conversion (ADC) circuitry coupled to the pixel output line, wherein the ADC circuitry comprises:
a second pinned photodiode;
a comparator with first and second inputs;
a sampling transistor;
a first capacitive node that is coupled between the second pinned photodiode the first input of the comparator; and
a second capacitive node that is coupled between the sampling transistor and the second input of the comparator.

US Pat. No. 10,192,921

SOLID STATE IMAGING DEVICE FOR REDUCING DARK CURRENT, METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS

Sony Corporation, Tokyo ...

1. A solid state imaging device, comprising:a semiconductor substrate comprising a light sensing section and comprising a first surface and a second surface opposite to the first surface, wherein the first surface is at a light incident side of the semiconductor substrate;
a wiring layer on the second surface; and
at least three layers over the first surface, the at least three layers comprising a first layer, a second layer, and a third layer,
wherein the first layer and the third layer are insulating layers, and the second layer comprises a material selected from the group including hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), erbium oxide (Er2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3), yttrium oxide (Y2O3), hafnium nitride, aluminum nitride, hafnium oxide nitride, and aluminum oxide nitride,
wherein the second layer is disposed between the first layer and third layer,
wherein the light sensing section includes at least a first light receiving surface and a second light receiving surface and a pixel separating region,
wherein the pixel separating region is disposed between the first light receiving surface and the second light receiving surface, and
wherein at least one of the first layer, the second layer, and the third layer is disposed over the first light receiving surface, the second light receiving surface, and the pixel separating region.

US Pat. No. 10,192,912

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE

Sony Semiconductor Soluti...

1. A back-illuminated type solid-state imaging device comprising:a first layer including at least one of an amplification transistor, a reset transistor, or a selection transistor;
a second layer including at least one photo diode, the second layer separated from the first layer in a depth direction;
a transfer transistor configured to control charge transfer of the photo diode, wherein the transfer transistor is at least partially disposed in the second layer; and
a floating diffusion configured to receive charge transferred from the photo diode, wherein the floating diffusion penetrates the first layer such that the photo diode is in electrical communication with the at least one of an amplification transistor, a reset transistor, or a selection transistor via the floating diffusion,
wherein the floating diffusion is formed at a position including the second layer.

US Pat. No. 10,192,911

HYBRID IMAGE SENSORS WITH IMPROVED CHARGE INJECTION EFFICIENCY

APPLE INC., Cupertino, C...

1. Imaging apparatus, comprising:a photosensitive medium configured to convert incident photons into charge carriers;
a bias electrode, which is at least partially transparent, overlying the photosensitive medium and configured to apply a bias potential to the photosensitive medium;
an array of pixel circuits formed on a semiconductor substrate, each pixel circuit defining a respective pixel and comprising:
a pixel electrode coupled to collect the charge carriers from the photosensitive medium;
a readout circuit configured to output a signal indicative of a quantity of the charge carriers collected by the pixel electrode;
a skimming gate coupled between the pixel electrode and the readout circuit; and
a shutter gate coupled in parallel with the skimming gate between a node in the pixel circuit and a sink site; and
control circuitry coupled to sequentially open and close the shutter gate and the skimming gate of each of the pixels in each of a sequence of image frames so as to apply a global shutter to the array and then to read out the collected charge carriers via the skimming gate to the readout circuit,
wherein the pixel circuit comprises:
a charge storage node between the skimming gate and the readout circuit;
at least one charge transfer gate that connects to the charge storage node; and
a reset gate coupled between the charge transfer gate and a reset potential and configured to reset the charge stored on the charge storage node under control of the control circuitry,
wherein the control circuitry is configured, in each of the image frames, to actuate one of the gates so as to fill a potential well at the pixel electrode with charge carriers, and then to close the shutter gate, whereby the charge carriers acquired at the pixel electrode from the photosensitive medium is transferred through the skimming gate to the readout circuit,
wherein while the one of the gates is actuated, a potential well of the charge storage node is filled with the charge carriers, and wherein the control circuitry is configured, prior to acquiring the charge carriers, to actuate the reset gate and the at least one charge transfer gate so as to allow the charge carriers to drain from the charge storage node while the charge carriers remain in the potential well at the pixel electrode, and
wherein the control circuitry is configured to apply a charge pump signal so as to inject an additional number of the charge carriers into the potential well of the pixel electrode after the acquisition of the photocharge but before reading out the charge carriers to the readout circuit.

US Pat. No. 10,192,905

ARRAY SUBSTRATES AND THE MANUFACTURING METHODS THEREOF, AND DISPLAY DEVICES

Shenzhen China Star Optoe...

1. A manufacturing method of array substrates, the method adopting four masking processes to obtain the array substrate and at least one pixel electrode within the array substrate, wherein a second masking process to form an active layer, a source electrode, and a drain electrode comprising:forming a semiconductor thin-film layer, N+ doping thin-film layer, a metal thin-film layer, and a photo-resistor layer on a gate insulation layer in sequence;
applying a gray-tone-mask process to expose and develop the photo-resistor layer to obtain a first photo-resistor mask;
under protection of the first photo-resistor mask, applying a first wet etching process to etch a portion of the metal thin-film layer that is not covered by the first photo-resistor mask;
under the protection of the first photo-resistor mask, applying a first dry etching process to etch portions of the semiconductor thin-film layer and the N+ doping thin-film layer that are not covered by the first photo-resistor mask to obtain the active layer;
applying a plasma ashing process to the first photo-resistor mask to obtain a second photo-resistor mask, and the metal thin-film layer is exposed by a central area of the second photo-resistor mask;
under the protection of the second photo-resistor mask, applying a second wet etching process to etch away a portion of the metal thin-film layer that is not covered by the second photo-resistor mask to obtain the source electrode and the drain electrode; and
peeling off the second photo-resistor mask, applying a second dry etching process to etch away the portion of the N+ doping thin-film layer between the source electrode and the drain electrode to obtain the N+ contact layer respectively between the source electrode and the active layer and between the drain electrode and the active layer.

US Pat. No. 10,192,903

METHOD FOR MANUFACTURING TFT SUBSTRATE

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing a TFT substrate, comprising:step 101: providing a substrate and depositing a buffer layer on the substrate, wherein the substrate includes a drive TFT region and a display TFT region;
step 102: depositing a first amorphous silicon layer on the buffer layer, and performing excimer laser annealing on the first amorphous silicon layer so as to convert the first amorphous silicon layer into a first polysilicon layer through crystallization;
patterning the first polysilicon layer, to obtain a first active layer that is located in the drive TFT region;
step 103: depositing a gate insulating layer on the first active layer and the buffer layer;
depositing and patterning a first metal layer on the gate insulating layer, to form a first gate electrode at a position corresponding to position of the first active layer and form a second gate electrode at a position corresponding to position where the first active layer is not arranged;
step 104: implanting ions into the gate insulating layer taking the first gate electrode and the second gate electrode as a shading layer;
step 105: depositing an interlayer insulating layer on the gate insulating layer, the first gate electrode and the second gate electrode, depositing a second amorphous silicon layer on the interlayer insulating layer, implanting ions into the second amorphous silicon layer, and performing solid phase crystallization on the second amorphous silicon layer so as to convert the second amorphous silicon layer into a second polysilicon layer;
patterning the second polysilicon layer to form a second active layer at a position corresponding to the second gate electrode;
wherein the second amorphous silicon layer is implanted with boron (B) ions;
step 106: forming a first via hole and a second via hole in the gate insulating layer and the interlayer insulating layer corresponding to the first active layer, and forming a third via hole in the interlayer insulating layer corresponding to the second gate electrode;
step 107: depositing a source-drain electrode layer, patterning the source-drain electrode layer, and forming a channel on a surface of the second active layer at the same time;
step 108: depositing a passivation layer and patterning the passivation layer, depositing a flat layer on the passivation layer, and forming a fourth via hole in the flat layer at a position thereof in the display TFT region, the fourth via hole extending to a surface of the source-drain electrode layer; and
step 109: depositing an anode electrode on the flat layer, the anode electrode being in contact with the source-drain electrode layer through a fourth via hole, depositing a pixel definition layer, and defining a pattern, so that the TFT substrate is manufactured.

US Pat. No. 10,192,902

LTPS ARRAY SUBSTRATE

Shenzhen China Star Optoe...

1. A low temperature poly-silicon (LTPS) array substrate, comprising:a substrate;
a source electrode and a drain electrode, which are arranged on the substrate;
a poly-silicon layer, which is arranged on the substrate including the source electrode and the drain electrode, wherein the poly-silicon layer partially covers the source electrode and the drain electrode;
an insulating layer, which is arranged on the poly-silicon layer and the source and drain electrodes, wherein the insulating layer is formed through passivation of a part of the poly-silicon layer that covers the substrate including the source electrode and the drain electrode;
a gate electrode, which is arranged on the insulating layer between the source electrode and the drain electrode, wherein the source and drain electrodes, the poly-silicon layer, and the gate electrode collectively form a thin-film transistor (TFT);
a planar layer, which is arranged on the substrate including the gate electrode, wherein the planar layer is formed with a contact hole extending therethrough to expose a surface of the drain electrode;
a common electrode, which is arranged on the planar layer except the TFT of the LTPS array substrate;
a passivation layer, which is arranged on the planar layer and the common electrode layer, such that the passivation layer does not cover the contact hole;
a pixel electrode, which is arranged on the passivation layer, wherein the pixel electrode is electrically connected with the drain electrode through the contact hole;
wherein the poly-silicon layer has a first region that is stacked atop and covers an inner part of each of the source electrode and the drain electrode and a portion of the substrate that is between the source electrode and the drain electrode and a second region that is integrally extended from the first region and is partly stacked atop and covers an outer part of each of the source electrode and the drain electrode; and
wherein the first region of the poly-silicon has a thickness that is greater than a thickness of the second region of the poly-silicon and the first region of the poly-silicon has a lower part in direct contact with the inner parts of the source electrode and the drain electrode and the portion of substrate between the source electrode and the drain electrode and an upper part that forms a first portion of the insulating layer; and the second region of the poly-silicon, in the entirety thereof, forms a second portion of the insulating layer that integrally extends from the first portion of the insulating layer, such that the insulating layer is integrally combined with the lower part of the poly-silicon layer and is extended to cover the source electrode and the drain electrode.

US Pat. No. 10,192,900

METHODS FOR FABRICATING THIN FILM TRANSISTOR AND ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A fabrication method of a thin film transistor, comprising an operation of forming an active layer, a source electrode and a drain electrode of a thin film transistor, wherein the source electrode and the drain electrode are separately provided on two sides of the active layer, an interval is provided between the source electrode and the drain electrode to define a channel area, the operation of forming the active layer, the source electrode and the drain electrode of the thin film transistor comprises:forming an active layer film;
forming a first photoresist pattern on the active layer film, wherein the first photoresist pattern covers an area of the active layer film for forming the active layer, the first photoresist pattern comprises a photoresist area of a first thickness and a photoresist area of a second thickness, a thickness of the photoresist area of the first thickness is greater than a thickness of the photoresist area in the second thickness, and the photoresist area of the first thickness corresponds to the area of the active layer film for forming the channel area;
etching the active layer film by using the first photoresist pattern as a mask to form the active layer;
ashing the first photoresist pattern to remove the photoresist area of the second thickness and to reduce the thickness of the photoresist area of the first thickness to form a second photoresist pattern, which corresponds to the area of the active layer for forming the channel area;
forming a source-drain electrode film on the active layer and the second photoresist pattern;
forming a third photoresist pattern on the source-drain electrode film;
etching the source-drain electrode film by using the third photoresist pattern as a mask to form the source electrode and the drain electrode and to expose the second photoresist pattern; and
stripping off the second photoresist pattern and the third photoresist pattern;
wherein a distance between photoresist that covers a position where the source electrode is to be formed in the source-drain electrode film and photoresist that covers a position where the drain electrode is to be formed in the source-drain electrode film in the third photoresist pattern is equal to a width of the second photoresist pattern between these positions correspondingly.

US Pat. No. 10,192,891

THIN FILM TRANSISTOR AND DISPLAY DEVICE COMPRISING THE SAME

JOLED INC., Tokyo (JP)

1. A thin film transistor comprising:an oxide semiconductor layer provided above an insulating substrate and including a source region, a drain region and a channel region between the source region and the drain region;
a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region;
a gate electrode provided on the first insulating film;
a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal;
a second protective film provided on the first protective film; and
a third protective film provided on the second protective film, as an insulating film containing a metal, wherein the first protective film directly contacts sidewalls and a top surface of the gate electrode, wherein the third protective film is thicker than the first protective film.

US Pat. No. 10,192,890

TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THEREOF

Samsung Display Co., Ltd,...

1. A transistor display panel comprising:a substrate; and
a transistor disposed on the substrate,
wherein the transistor comprises:
a gate electrode disposed on the substrate;
a semiconductor that overlaps the gate electrode;
an upper electrode disposed on the semiconductor and overlapping the gate electrode;
a source connection member and a drain connection member disposed on the same layer as the upper electrode and respectively connected with the semiconductor;
a source electrode connected with the source connection member and the upper electrode; and
a drain electrode connected with the drain connection member.

US Pat. No. 10,192,889

DISPLAY DEVICE AND METHOD OF MANUFACTURING A DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a first substrate including a display area and a non-display area;
a gate line and a gate electrode in the display area;
a data line connected to the gate line;
a gate insulating layer on the gate line and the gate electrode;
a semiconductor layer on the gate insulating layer;
a drain electrode and a source electrode on the semiconductor layer;
a first passivation layer on the drain electrode and the source electrode;
a color filter on the first passivation layer;
a common electrode on the first passivation layer;
a second passivation layer on the common electrode; and
a pixel electrode on the second passivation layer,
wherein the gate insulating layer has substantially a same shape as a shape of the gate electrode,
wherein the gate insulating layer has a width wider than a width of the gate electrode,
wherein the gate insulating layer is spaced apart from the first substrate, and
wherein a side surface of the gate electrode is exposed below a bottom surface of the gate insulating layer.

US Pat. No. 10,192,884

BUTTED BODY CONTACT FOR SOI TRANSISTOR

pSemi Corporation, San D...

1. A semiconductor structure comprising:a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type;
a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type;
a first drain region adjacent to the first body region having a second conductivity type;
a first source region adjacent to the first body region having the second conductivity type;
a second source region adjacent to the second body region having the second conductivity type;
a second drain region adjacent to the second body region having the second conductivity type,
the first source region and the second drain region defining a first common source/drain region having the second conductivity type;
a first non-conductive isolation region configured to form an interruption in the second body region to divide the second body region in two separate second body regions;
at least one first body contact region of the first conductivity type formed within the first common source/drain region separate from the first and the second body regions and abutting the first non-conductive isolation region; and
at least one first body tab of the first conductivity type extending across the first common source/drain region in contact with the first body region and the at least one first body contact region,
wherein the first non-conductive isolation region, the at least one first body contact region and the at least one first body tab define a first butted body tie structure.

US Pat. No. 10,192,883

VERTICAL MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A memory device, comprising:a first region including a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a protective layer disposed in the first insulating layer; and
a second region including a second substrate disposed on the first insulating layer, wherein the second substrate includes a first impurity region, a channel region extending in a first direction substantially perpendicular to an upper surface of the second substrate, and a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, wherein the protective layer is disposed below the first impurity regions, and includes a plurality of regions separated from each other.

US Pat. No. 10,192,882

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a stacked body including a plurality of conductive layers stacked with an insulator interposed;
a columnar portion extending through the stacked body in a stacking direction of the stacked body; and
a first air gap extending through the stacked body in the stacking direction,
the insulator including
an insulating layer provided at a periphery of a side surface of the columnar portion, and
a second air gap communicating with the first air gap and being provided between the insulating layer and the first air gap,
the insulating layer having a protrusion at an end adjacent to the second air gap.

US Pat. No. 10,192,881

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate comprising a source region portion;
gate stacks disposed on the substrate and spaced apart from each other in a first direction, with a separation region directly contacting the source region portion of the substrate and interposed between the gate stacks, the source region portion of the substrate being disposed between the separation region and regions of the substrate not within the source region portion;
channel regions penetrating through the gate stacks and disposed within each of the gate stacks; and
a guide region adjacent to the separation region, penetrating through at least a portion of one of the gate stacks, and having a bent portion that is bent toward the separation region;
wherein the channel regions are disposed in channel openings that penetrate through the gate stacks,
the guide region is disposed in a guide opening that penetrates through at least the portion of the one of the gate stacks,
the separation region is disposed in a separation opening that penetrates through the gate stacks, and
a width of the separation opening is greater than a width of each of the guide opening and the channel openings,
wherein the guide opening is closer to the separation region than the channel openings, and an upper portion of the guide opening is spaced apart from an upper portion of the separation region.

US Pat. No. 10,192,880

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:gate stacked structures surrounding channel layers;
a common source line filling a separation area between the gate stacked structures adjacent to each other and having an upper surface including first concave portions, wherein the first concave portions are arranged in a first direction crossing a lengthwise direction of the channel layer; and
a support insulating layer filling the first concave portions and having sidewalls facing portions of the channel layers.

US Pat. No. 10,192,879

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device having a memory cell of a nonvolatile memory, comprising:a semiconductor substrate;
a first gate electrode formed over the semiconductor substrate via a first gate insulating film; and
a second gate electrode formed over the semiconductor substrate via a multi-layer insulating film, and adjacent to the first gate electrode via the multi-layer insulating film,
wherein the multi-layer insulating film includes a first insulating film, a second insulating film over the first insulating film, and a third insulating film over the second insulating film,
wherein the second insulating film has a charge storing function,
wherein the second gate electrode has a lower surface facing the semiconductor substrate, a first side surface adjacent to the first gate electrode via the multi-layer insulating film, and a second side surface opposite to the first side surface, and
wherein a fourth insulating film is formed between the lower surface of the second gate electrode and the semiconductor substrate and is in contact with the first, second and third insulating films such that the fourth insulating film is located closer to a first end portion of the second side surface of the second gate electrode than to a second end portion of the first side surface of the second gate electrode.

US Pat. No. 10,192,873

MEMORY CELL, AN ARRAY OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR WITH THE ARRAY COMPRISING ROWS OF ACCESS LINES AND COLUMNS OF DIGIT LINES, A 2T-1C MEMORY CELL, AND METHODS OF FORMING AN ARRAY OF CAPACITORS AND ACCESS TRANSISTORS

Micron Technology, Inc., ...

1. A memory cell having a total of only two transistors and a total of only one capacitor, comprising:a capacitor comprising a laterally-outer electrode having an upwardly-open container shape;
a laterally-inner electrode;
a capacitor insulator between the laterally-outer electrode and the laterally-inner electrode;
a lower vertical transistor having an upper source/drain region thereof electrically coupled to the laterally-outer electrode having the upwardly-open container shape; and
an upper vertical transistor having a lower source/drain region thereof electrically coupled to the laterally-inner electrode.

US Pat. No. 10,192,872

MEMORY DEVICE HAVING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first region in electrical contact with said floating body region; and
a back-bias region configured to maintain a charge in said floating body region;
wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity;
wherein said back bias region is commonly connected to at least two of said memory cells,
wherein said back bias region has a lower band gap than a band gap of said floating body region; and
a control circuit configured to provide electrical signals to said back bias region.

US Pat. No. 10,192,871

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a transistor; and
a first circuit,
wherein the transistor includes a first gate and a second gate,
wherein the first gate and the second gate overlap with each other with a semiconductor layer positioned therebetween,
wherein the first circuit includes a temperature sensor and a comparator,
wherein the temperature sensor is configured to obtain temperature information, and
wherein the first circuit is configured to apply, to the second gate, a voltage depending on the temperature information.

US Pat. No. 10,192,870

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a semiconductor substrate of a first conductivity type;
a first semiconductor region of a second conductivity type, selectively provided in one main surface of the semiconductor substrate;
an isolating structure formed by a pn junction of the semiconductor substrate and the first semiconductor region, the isolating structure isolating regions of differing potentials;
a semiconductor element having: a second semiconductor region of the second conductivity type, selectively provided in the one main surface of the semiconductor substrate so as to be separated from the first semiconductor region and electrically connected to an electrode of a minimum potential through a first resistor; a third semiconductor region of the second conductivity type selectively provided inside the first semiconductor region and having a higher impurity concentration than the first semiconductor region; a gate insulating film provided along the semiconductor substrate between the first semiconductor region and the second semiconductor region; and a gate electrode provided along the gate insulating film, the semiconductor element converting a signal referenced to the minimum potential into a signal referenced to a potential differing from the minimum potential; and
a fourth semiconductor region of the first conductivity type selectively provided in the one main surface of the semiconductor substrate so as to be separated from the second semiconductor region at a prescribed distance and electrically connected to the electrode of the minimum potential, the fourth semiconductor region having a higher impurity concentration than the semiconductor substrate,
wherein the second semiconductor region is electrically connected to the fourth semiconductor region through a second resistor, and
wherein the second resistor comprises a portion of the semiconductor substrate between the second semiconductor region and the fourth semiconductor region.

US Pat. No. 10,192,869

REDUCTION OF NEGATIVE BIAS TEMPERATURE INSTABILITY

INTERNATIONAL BUSINESS MA...

1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:an n-channel field effect transistor (nFET), the nFET comprising a high-k dielectric layer on an interlayer, an nFET work function setting metal on the high-k dielectric layer, a cap layer on the nFET work function setting metal, and a pFET work function setting metal on the cap layer, wherein the interlayer is silicon dioxide (SiO2); and
a p-channel field effect transistor (pFET), the pFET comprising the high-k dielectric layer directly on the interlayer, the cap layer directly on the high-k dielectric layer, and the pFET work function setting metal directly on the cap layer, wherein the cap layer is aluminum-based and the pFET work function setting metal is a nitride and metal atoms from the cap layer do not intermix with the interlayer.

US Pat. No. 10,192,868

SEMICONDUCTOR DEVICE AND OPERATION THEREOF

Semiconductor Manufacturi...

1. A semiconductor device, comprising:a substrate;
an active area on the substrate, wherein the active area comprises:
a first active area; and
a second active area positioned along an extension direction of the first active area, wherein the first active area comprises a first component, a second component, and a connection component, and the first component and the second component each directly contact a side of the connection component, wherein the second active area comprises a third component and a fourth component being separated by a groove isolation, and wherein the groove isolation in the second active area corresponds to the connection component in the first active area; and
a first pseudo gate covering the connection component and the groove isolation.

US Pat. No. 10,192,866

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

FUJITSU SEMICONDUCTOR LIM...

1. A semiconductor device, comprising:a semiconductor substrate including a first region and a second region;
a semiconductor layer formed on the upper surface of the semiconductor substrate;
a first impurity region formed in the first region of the semiconductor substrate and including a first impurity;
a second impurity region formed in the second region of the semiconductor layer and including a second impurity;
a first gate insulating film formed on the semiconductor layer in the first region;
a second gate insulating film formed on the semiconductor layer in the second region;
a first gate electrode formed on the first gate insulating film;
a second gate electrode formed on the second gate insulating film;
a first source region and a first drain region formed in the semiconductor layer at both sides of the first gate electrode, and having a conductivity type opposite to a conductivity type of the first impurity region; and
a second source region and a second drain region formed in the semiconductor layer at both sides of the second gate electrode, and having a conductivity type opposite to a conductivity type of the second impurity region, and wherein
a maximum concentration peak of the second impurity in the second region is positioned in the semiconductor layer, a maximum concentration peak of the first impurity in the first region is positioned in the first impurity region.

US Pat. No. 10,192,863

SERIES CONNECTED ESD PROTECTION CIRCUIT

Texas Instruments Incorpo...

1. An electrostatic discharge (ESD) protection circuit, comprising:a substrate;
an n-type buried layer formed below a surface of the substrate;
a first terminal formed on the surface of the substrate;
a second terminal formed on the surface of the substrate;
a first ESD protection device having a first current path connecting between the first terminal and the n-type buried layer, the first ESD protection device including a first NPN bipolar transistor having a collector positioned in the n-type buried layer; and
a second ESD protection device having a second current path connecting between the second terminal and the n-type buried layer, the second current path arranged in series with the first current path, the second ESD protection device including a second NPN bipolar transistor having an emitter positioned in the n-type buried layer,
wherein the first NPN bipolar transistor has a first base that is electrically isolated from a second base of the second NPN transistor.

US Pat. No. 10,192,862

SEMICONDUCTOR DEVICE

Murata Manufacturing Co.,...

1. A semiconductor device comprising:an amplifier circuit including a semiconductor element formed on a substrate;
a protection circuit including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit; and
a pad conductive layer at least partially including a pad for connecting to a circuit outside the substrate, wherein
the pad conductive layer and the protection circuit at least partially overlap each other in plan view, and
at least one of the protection diodes includes a substantially U-shaped electrode in plan view.

US Pat. No. 10,192,861

OPC METHOD FOR A SHALLOW ION IMPLANTING LAYER

SHANGHAI HUALI MICROELECT...

1. An OPC method for a shallow ion implanting layer, providing a shallow ion implanting original layout and other layers corresponding to the shallow ion implanting original layout include an active area layer, a contact hole layer and a poly-silicon layer, wherein the active area layer includes an active region pattern, the contact hole layer includes a contact hole pattern and the poly-silicon layer includes a ploy-silicon pattern; wherein the method comprising the following steps of:S01: selecting a valid device region in an implanting active region of the shallow ion implanting original layout; wherein a portion other than an active region pattern in an active area layer is a STI region, the shallow ion implanting original layout includes a shallow ion implanting region and a non-shallow ion implanting region, and a portion overlapped between the shallow ion implanting region and the active region pattern in the active area layer is the implanting active region; a portion to remain the implanting active region which touches to the contact hole pattern in the contact hole layer is a valid device region, and anther portion to remain the implanting active region which does not touch to the contact hole pattern in the contact hole layer is a non-device invalid region;
S02: selecting a region in the valid device region which is contacted with a poly-silicon pattern in a poly-silicon layer, as a poly-silicon contacting region, and selecting a region in the valid device region which is not contacted with the poly-silicon pattern in the poly-silicon layer, as a non poly-silicon contacting region;
S03: extending the length and width of the poly-silicon contacting region and the non poly-silicon contacting region, to form a new poly-silicon contacting region and a new non poly-silicon contacting region; wherein the new poly-silicon contacting region and the new non poly-silicon contacting region are located in any region except the active region pattern touching with the contact hole pattern in the non-shallow ion implanting region;
S04: combining one gap portion or more gap portions which an interval between any two new poly-silicon contacting regions and/or new non poly-silicon contacting regions after extending is smaller than or equal to G, with the poly-silicon contacting regions and the non poly-silicon contacting regions after extending, to form a correction target layer, wherein G is an interval safe value determined according to the actual process capability;
S05: performing a model-based OPC correction on the correction target layer, and to obtain a mask layer.

US Pat. No. 10,192,860

ENGINEERING CHANGE ORDER (ECO) CELL, LAYOUT THEREOF AND INTEGRATED CIRCUIT INCLUDING THE ECO CELL

Samsung Electronics Co., ...

1. An integrated circuit (IC) comprising:an integrated circuit substrate;
a plurality of standard cells on said integrated circuit substrate; and
at least one engineering change order (ECO) base cell on the integrated circuit substrate;
wherein the ECO base cell has a layout that is generated based on a layout of a functional cell corresponding to a first circuit including a plurality of logic gates having different logic configurations relative to each other;
wherein the layout of the ECO base cell includes a plurality of spaced-apart and dissimilar regions that are each associated with a respective one of the plurality of logic gates, with each of the plurality of dissimilar regions comprising a plurality of spaced-apart active regions and a plurality of gate lines overlapping the plurality of spaced-apart active regions; and
wherein the plurality of gate lines are disposed asymmetrically on said integrated circuit substrate so that the gate lines within at least two of the plurality of dissimilar regions lack symmetry relative to each other and relative to an axis extending between the at least two of the plurality of dissimilar regions.

US Pat. No. 10,192,859

INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:a substrate having a semiconducting surface; and
a structure formed in and on the semiconducting surface, the structure including a first block of standard cells, and at least a second block,
the first and second blocks arranged in a horizontal row, and at least partially aligned in height, such that at least a portion of a first vertical block boundary of the first block is adjacent to and aligned with at least a portion of a second vertical block boundary of the second block, thereby defining a region of alignment between the first and second blocks,
the first block including a first base level extending across a portion but not all of the first vertical block boundary to form a first vertical base-level boundary at least partially within the region of alignment,
the second block including a second base level extending across a portion but not all of the second vertical block boundary to form a second vertical base-level boundary at least partially within the region of alignment;
the first and second blocks placed on the semiconducting surface such that the blocks are separated by a protective separation strip between the blocks;
the first block including a first DWD1 dimension between its first vertical block boundary, and the second vertical base-level boundary of the second base level,
the second block including a second DWD1 dimension between its second vertical block boundary, and the first vertical base-level boundary of the first base level,
the separation strip having a uniform width dimension DWD1 between a vertical block boundary and a vertical base-level boundary,
the DWD1 dimension defined such that a minimum separation exists between the first and second vertical base-level boundaries corresponding to the protective separation strip.

US Pat. No. 10,192,858

LIGHT EMITTING STRUCTURE

Apple Inc., Cupertino, C...

1. A display comprising:a substrate;
a first bottom electrode line on the substrate;
a passivation layer over the display substrate;
a first plurality of vertical semiconductor-based light emitting diodes (LEDs) coupled with the first bottom electrode line and embedded within the passivation layer such that the passivation layer laterally surrounds a quantum well within each of the first plurality of vertical semiconductor-based LEDs;
a second plurality of vertical semiconductor-based LEDs embedded within the passivation layer such that the passivation layer laterally surrounds a quantum well within each of the second plurality of vertical semiconductor-based LEDs, wherein the second plurality of vertical semiconductor-based LEDs and the first plurality of vertical semiconductor-based LEDs share a same vertical semiconductor-based LED; and
a first top electrode line in electrical contact with the second plurality of vertical semiconductor-based LEDs.

US Pat. No. 10,192,857

DIRECT BANDGAP SEMICONDUCTOR BONDED TO SILICON PHOTONICS

Hewlett Packard Enterpris...

1. A method comprising:receiving an assembly comprising a silicon photonics (SiP) wafer bonded to a complementary metal-oxide-semiconductor (CMOS) wafer, wherein the SiP wafer includes photonics circuitry and the CMOS wafer includes electronic circuitry; and
after receiving the assembly:
bonding a direct bandgap (DBG) semiconductor structure to the SiP wafer such that the SiP wafer is disposed between the CMOS wafer and the DBG semiconductor structure;
optically coupling the direct bandgap (DBG) semiconductor structure to the photonics circuitry; and
electrically connecting the DBG semiconductor structure to the electronic circuitry of the CMOS wafer.

US Pat. No. 10,192,855

SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING HEAT DISSIPATION PATTERN AND/OR HEAT CONDUCTING LINE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package, comprising:a lower semiconductor package including a lower package substrate and at least a first lower semiconductor chip mounted thereon;
an upper semiconductor package provided on the lower semiconductor package and including an upper package substrate and at least a first upper semiconductor chip mounted thereon; and
a solder bump provided between the upper package substrate and the lower package substrate adjacent to a sidewall of the first lower semiconductor chip to connect the lower semiconductor package and the upper semiconductor package,
wherein the upper package substrate comprises an upper heat-dissipation pattern not electrically connected to any circuitry for transmitting signals to, from, or through the first lower semiconductor chip or the upper package substrate, and
wherein the first lower semiconductor chip comprises at least a first lower heat-conducting via connected to the upper heat-dissipation pattern through the first lower semiconductor chip, the first lower heat-conducting via providing a pathway for dissipating heat generated in the first lower semiconductor chip.

US Pat. No. 10,192,854

LIGHT EMITTER COMPONENTS AND RELATED METHODS

Cree, Inc., Durham, NC (...

1. A light emitter component comprising:a submount comprising ceramic;
a reflective material disposed on portions of the submount, wherein the reflective material comprises a reflective surface; and
a plurality of light emitter chips disposed on the reflective surface of the reflective material and in contact with one or more electrical traces on the submount, wherein the reflective surface extends below each of the plurality of light emitter chips and between each of the one or more electrical traces, wherein each light emitter chip comprises a sapphire substrate, an epi area disposed over the sapphire substrate, and first and second electrical contacts that face the reflective surface;
wherein a ratio of a combined epi area of the plurality of light emitter chips to a surface area of the reflective surface not covered by the plurality of light emitter chips is at least 0.4 or more, and
wherein a ratio of a combined planar surface area of the plurality of light emitter chips to a planar surface area of the reflective surface not covered by the plurality of light emitter chips is at least approximately 0.25 or more.

US Pat. No. 10,192,852

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a semiconductor substrate;
a dielectric material over the substrate;
a conductive trace extending at least partially through the dielectric material; and
a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—
a conductive member coupled to the conductive trace, and
a conductive bond material bonded to the conductive member,
wherein all of the redundant electrical connectors are coupled to the conductive trace.

US Pat. No. 10,192,851

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device comprising:(a) providing a wiring substrate including:
an upper surface,
a lower surface opposite to the upper surface,
a first device region provided on the lower surface,
a second device region provided on the lower surface and also provided next to the first device region,
a dicing region provided between the first device region and the second device region
a peripheral region provided on the lower surface and also provided around the first device region, the second device region and the dicing region,
a target mark provided in the peripheral region and also not located on an extended line of the dicing region,
a plurality of first bump lands provided in a matrix, in the first device region,
a plurality of second bump lands provided in a matrix, in the second device region, and
a first insulating film formed over the lower surface such that the first insulating film exposes the plurality of first bump lands and the plurality of second bump lands,
wherein the plurality of first bump lands has a first outermost peripheral land row arranged on the outermost peripheral row of the plurality of first bump lands, which is closest to the dicing region,
wherein the plurality of second bump lands has a second outermost peripheral land row arranged on the outermost peripheral row of the plurality of second bump lands, which is closest to the dicing region,
wherein the target mark is comprised of a first pattern formed between the extended line of the dicing region and an extended line of the first outermost peripheral land row in plan view, and a second pattern formed between the extended line of the dicing region and an extended line of the second outermost peripheral land row in plan view, the first pattern and the second pattern being spaced apart from each other,
wherein a first feeder line and a second feeder line are connected to the first pattern and the second pattern, respectively,
wherein each of the first feeder line and the second feeder line has a first portion exposed from the first insulating film, and a second portion covered with the first insulating film,
wherein the first pattern, the second pattern, the first feeder line and the second feeder line are comprised of a conductive member, and
wherein a first plating film is formed on a surface of each of the first pattern exposed from the first insulating film and the second pattern exposed from the first insulating film by using the first feeder line and the second feeder line, respectively;
(b) after (a), mounting a first semiconductor chip and a second semiconductor chip on the upper surface of the wiring substrate;
(c) after (b), sealing the first semiconductor chip and the second semiconductor chip with resin;
(d) after (c), forming a plurality of first external terminals and a plurality of second external terminals on the plurality of first bump lands and the plurality of second bump lands, respectively; and
(e) after (d), identifying the dicing region on the basis of the target mark, and cutting the wiring substrate along the dicing region,
wherein, in (e), the dicing region of the wiring substrate and a first region of the peripheral region of the wiring substrate are cut off by using a rotating cutting blade,
wherein the first region is located between the first pattern and the second pattern in plan view, and
wherein the first pattern, the second pattern, the first feeder line and the second feeder line are not formed in the first region.

US Pat. No. 10,192,850

BONDING PROCESS WITH INHIBITED OXIDE FORMATION

SiTime Corporation, Sant...

1. A method of forming a wafer-to-wafer bond, the method comprising:forming, on a first wafer, a first contact from a first conductive material subject to surface oxidation when exposed to air;
disposing a layer of oxide-inhibiting material over a bonding surface of the first contact;
forming, on a second wafer, a second contact from a second conductive material that, upon heating while in physical contact with the first conductive material, will form a eutectic bond;
positioning the first and second wafers relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material; and
after positioning the first and second wafers relative to one another, heating the first and second contacts and the layer of oxide-inhibiting material to a first temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond;
the method further comprising, prior to positioning the first and second wafers relative to one another such that the bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material, heating the first contact and the layer of oxide-inhibiting material to a second temperature that alloys the oxide-inhibiting material with the first conductive material.

US Pat. No. 10,192,849

SEMICONDUCTOR MODULES WITH SEMICONDUCTOR DIES BONDED TO A METAL FOIL

Infineon Technologies AG,...

1. A method of manufacturing semiconductor modules, the method comprising:providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer;
attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil;
encasing the semiconductor dies attached to the metal foil in an electrically insulating material;
structuring the metal layer and the metal foil after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer; and
dividing the electrically insulating material along the surface regions devoid of the metal foil and the metal layer to form individual modules,
wherein structuring the metal layer and the metal foil comprises:
masking the metal layer so that regions of the metal layer are exposed;
removing the exposed regions of the metal layer so that regions of the metal foil are exposed; and
removing the exposed regions of the metal foil using the remaining metal layer as a mask.

US Pat. No. 10,192,848

PACKAGE ASSEMBLY

Taiwan Semiconductor Manu...

1. A package assembly, comprising:a bump on a first substrate;
a molding compound on the first substrate and contacting sidewalls of the bump;
a no-flow underfill layer on a conductive region of a second substrate, wherein the no-flow underfill layer and the conductive region contact the bump; and
a mask layer arranged on the second substrate and laterally surrounding the no-flow underfill layer, wherein the no-flow underfill layer contacts the second substrate between the conductive region and the mask layer, wherein the no-flow underfill layer physically contacts sidewalls and an upper surface of the mask layer facing the first substrate, and wherein the upper surface of the mask layer continuously extends from directly below the no-flow underfill layer to a non-zero distance laterally past an outermost edge of the no-flow underfill layer.

US Pat. No. 10,192,846

METHOD OF INSERTING AN ELECTRONIC COMPONENT INTO A SLOT IN A CIRCUIT BOARD

Infineon Technologies Aus...

1. A method, comprising:inserting an electronic component comprising a power semiconductor device embedded in a dielectric core layer into a slot in a side face of a circuit board, wherein the inserting the electronic component causes one or more electrically conductive contacts on one or more surfaces of the electronic component to electrically couple with one or more corresponding electrical contacts arranged on one or more surfaces of the slot,
exerting pressure on the contact of the slot to electrically couple the one or more electrical contacts arranged on one or more surfaces of the slot to the one or more electrically conductive contacts of the electronic component, wherein the exerting the pressure comprises exerting pressure on a surface of the circuit board defining the slot by applying one or more fixation elements.

US Pat. No. 10,192,845

ELECTRONIC DEVICE AND MOUNTING STRUCTURE OF THE SAME

ROHM CO., LTD., Kyoto (J...

1. An electronic device comprising:a first electronic element; a second electronic element spaced apart from and electrically connected to the first electronic element; a main electrode on which the first electronic element and the second electronic element are disposed;
an insulating joining part directly interposed between the first electronic element and the main electrode;
a plurality of insulating spacers mixed in the joining part and each directly contacting the main electrode and the first electronic element; a joining layer interposed between the second electronic element and the main electrode, the joining layer being made of an electroconductive material comprising silver (Ag); and; and
a sealing resin covering the first electronic element, the second electronic element and the main electrode.

US Pat. No. 10,192,844

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip, a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant, the first interconnection member and the second interconnection member including, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip: and
a component package including a wiring substrate disposed above the second interconnection member and connected to the second interconnection member through the first connection terminals and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate,
wherein the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer.

US Pat. No. 10,192,840

BALL PAD WITH A PLURALITY OF LOBES

Intel Corporation, Santa...

1. An electronic assembly comprising:a substrate that includes a conductive trace embedded within the substrate, wherein the conductive trace is exposed to an upper exterior surface of the substrate; and
a ball pad mounted on the upper exterior surface of the substrate, wherein the ball pad engages the conductive trace and includes a plurality of lobes projecting distally from a center of the ball pad, wherein each lobe in the plurality of lobes includes two sides that form an edge with the two sides extending from the edge at an acute angle, wherein one of the two sides in each lobe forms a planar surface with a side of another lobe and the other of the two sides forms a separate planar surface with a side of a different lobe.

US Pat. No. 10,192,839

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

International Business Ma...

1. A method of fabricating a pillar-type connection, the method comprising:forming a first conductive layer;
forming a second conductive layer on the first conductive layer to define a conductive pillar that includes a top surface defining a recess aligned with a hollow core of the first conductive layer; and
forming a conductive via that terminates at a top surface of the first conductive layer.

US Pat. No. 10,192,838

FABRICATION METHOD OF PACKAGING SUBSTRATE

Siliconware Precision Ind...

1. A fabrication method of a packaging substrate, comprising:providing a base body having at least a conductive pad on a surface thereof and a dielectric layer formed on the surface of the base body and at least a first opening formed in the dielectric layer for exposing the conductive pad;
forming at least a second opening in the dielectric layer around a periphery of the first opening, wherein the second opening is spaced apart from the first opening, and the second opening is free from being located directly above the conductive pad;
after forming the second opening in the dielectric layer around the periphery of the first opening, forming a metal layer on the dielectric layer and the conductive pad, allowing the metal layer to extend to only a part of a sidewall of the second opening without covering an entire surface of the second opening; and
forming at least a solder bump on the metal layer.

US Pat. No. 10,192,837

MULTI-VIA REDISTRIBUTION LAYER FOR INTEGRATED CIRCUITS HAVING SOLDER BALLS

NXP B.V., San Jose, CA (...

1. An article of manufacture comprising an integrated circuit (IC), the IC comprising:a top metal conducting layer;
a passivation layer on top of the top metal conducting layer, wherein the passivation layer comprises openings to the top conducting layer;
a redistribution layer on top of the passivation layer, wherein material of the redistribution layer fills the openings in the passivation layer to form via structures electrically connecting the redistribution layer to the top metal conducting layer; and
a solder ball placed on top of the redistribution layer that has a footprint that spans a first plurality of the via structures of the redistribution layer such that electricity can flow vertically between the solder ball and the top metal conducting layer through the redistribution layer and the first plurality of the via structures,
wherein there is no under-bump metallization (UBM) layer under the solder ball other than the redistribution layer, and
wherein the solder ball is in direct contact with the redistribution layer, and the footprint of the solder ball is vertically aligned with the first plurality of the via structures over the top metal conducting layer.

US Pat. No. 10,192,835

SUBSTRATE DESIGNED TO PROVIDE EMI SHIELDING

Apple Inc., Cupertino, C...

1. A package comprising:a package substrate including a top surface and a bottom surface;
a die bonded to the package substrate top surface;
a plurality of ground pads at a periphery of the package substrate top surface;
a plurality of electrically conductive wire bonds on the plurality of ground pads such that more than one electrically conductive wire bond is bonded to a corresponding ground pad;
a molding compound that encapsulates the die and the electrically conductive wire bonds on the package substrate top surface, the molding compound including top and side surfaces, wherein a corresponding plurality of surfaces of the plurality of electrically conductive wire bonds are exposed at a side surface of the molding compound; and
an electrically conductive shield layer on the top and side surfaces of the molding compound, and in physical contact with the plurality of surfaces of the exposed electrically conductive wire bonds.

US Pat. No. 10,192,834

SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

Siliconware Precision Ind...

1. A semiconductor package, comprising:a substrate;
a first semiconductor element disposed on the substrate and having a first conductive pad and a second conductive pad, wherein the second conductive pad is electrically connected to the first conductive pad by a first bonding wire and grounded to the substrate;
a conductive layer formed on the first semiconductor element and electrically connected to the first conductive pad, wherein the first semiconductor element is disposed between the conductive layer and the substrate, and the conductive layer is in direct contact with the first conductive pad and encapsulates the first conductive pad and a portion of the first bonding wire;
a second semiconductor element disposed on the conductive layer; and
an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements.

US Pat. No. 10,192,833

INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES

Taiwan Semiconductor Manu...

1. An interposer for connecting a semiconductor die to a printed circuit board, said interposer comprising:a substrate body having opposed first and second surfaces;
a plurality of conductive layers disposed in a dielectric material on said substrate body, wherein a first one of said plurality of conductive layers includes a first lead and a second of said plurality of conductive layers includes a second lead, wherein said first lead is shielded from said second lead by a shield including portions of a first interposed conductive layer and a second interposed conductive layer of said plurality of conductive layers coupled by a via such that an entirety of a longitudinal width of each of the first interposed conductive layer and the second interposed conductive layer of the shield is contained within a boundary of a first coupling via and a second coupling via;
said first lead extending along a longitudinal direction of said interposer and said shield extending continuously along a transverse direction of said interposer, wherein said shield extends across at least a majority of a transverse width of said interposer between said first and second leads; and
wherein said plurality of conductive layers are formed of metal materials or semiconductor materials;wherein said shield forms a continuous member of said metal materials or semiconductor materials, and there is no dielectric path from said first lead to said second lead through said shield.

US Pat. No. 10,192,832

ALIGNMENT MARK STRUCTURE WITH DUMMY PATTERN

United Microelectronics C...

1. An alignment mark structure, comprising:a substrate;
an alignment mark disposed on the substrate;
dummy patterns disposed on the substrate and located adjacent to the alignment mark;
a first passivation layer covering a top surface of the dummy patterns; and
a second passivation layer covering the first passivation layer, wherein
a size of the dummy patterns is smaller than a size of the alignment mark,
a metal layer of the alignment mark and a metal layer of the dummy patterns are derived from the same metal layer, and
the second passivation layer directly contacts and covers entire top surface of the alignment mark, and the first passivation layer does not cover any of the top surface of the alignment mark.

US Pat. No. 10,192,829

LOW-TEMPERATURE DIFFUSION DOPING OF COPPER INTERCONNECTS INDEPENDENT OF SEED LAYER COMPOSITION

International Business Ma...

1. An interconnect structure, comprising:at least one trench patterned in a dielectric material;
a barrier layer lining the trench;
a metal liner on the barrier layer;
a copper (Cu) interconnect doping layer on the metal liner; and
a Cu interconnect in the trench such that the Cu interconnect doping layer is present between the metal liner and the Cu interconnect, wherein the Cu interconnect doping layer fully surrounds the Cu interconnect whereby the Cu interconnect doping layer is continuous along all bottom, sidewall and top surfaces of the Cu interconnect.

US Pat. No. 10,192,826

CONDUCTIVE LAYOUT STRUCTURE INCLUDING HIGH RESISTIVE LAYER

UNITED MICROELECTRONICS C...

1. A layout structure comprising a conductive structure comprising:a dielectric layer formed on a substrate; and
the conductive structure formed in the dielectric layer, the conductive structure further comprising:
a barrier layer;
a metal layer formed within the barrier layer;
a first nucleation layer sandwiched in between the barrier layer and the metal layer; and
a high resistive layer sandwiched in between the first nucleation layer and the metal layer.

US Pat. No. 10,192,824

EDGE STRUCTURE FOR MULTIPLE LAYERS OF DEVICES, AND METHOD FOR FABRICATING THE SAME

MACRONIX International Co...

1. An edge structure for multiple layers of devices, wherein the multiple layers of devices comprises a plurality of unit layers being stacked, comprising:a first stair structure at a first direction of the multiple layers of devices where contacts for the devices are to be formed, including first edge portions of the unit layers at the first direction, wherein borders of the first edge portions gradually retreat with increase of a level height thereof, and an elevation angle from the border of the first edge portion of the bottom unit layer to the border of the first edge portion of the top unit layer is a first angle (?1); and
a second stair structure, including second edge portions of the unit layers at a second direction, wherein variation of border position of the second edge portion with increase of the level height is irregular, and an elevation angle from the border of the second edge portion of the bottom unit layer to the border of the second edge portion of the top unit layer is a second angle (?2) that is larger than the first angle ?1,
wherein a number of the unit layers is 16 or more,
the first direction is orthogonal with the second direction, and
the second stair structure has a first part and a second part above the first part, wherein
in the first part, variation of border position of the second edge portion with increase of the level height is regular,
in the second part, borders of the second edge portions of a corresponding part of the unit layers are aligned with each other, and
a height of the second part is over a half of a total height of the second stair structure.

US Pat. No. 10,192,823

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including a first region and a second region;
a transistor comprising a gate electrode and first and second dopant regions that are disposed on the first region of the substrate;
first, second, and third contact plugs electrically connected to the first dopant region, the second dopant region, and the gate electrode, respectively; and
a fuse structure disposed on the second region of the substrate, the fuse structure comprising: first and second fuse contact plugs having a same height as the first and second contact plugs; and a connection pattern having a same height as the third contact plug,
wherein the connection pattern is connected between the first and second fuse contact plugs,
wherein top surfaces of the first and second contact plugs are substantially coplanar with a top surface of the third contact plug, and
wherein the top surface of the third contact plug is substantially coplanar with a top surface of the connection pattern.

US Pat. No. 10,192,818

ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE

NSK LTD., Tokyo (JP)

1. An electronic part mounting heat-dissipating substrate which comprises: a conductor plate which is formed on lead frames of wiring pattern shapes to mount an electronic part; and an insulating member which is provided between said lead frames of said wiring pattern shapes on said conductor plate; in which a plate surface of a part arrangement surface of said conductor plate and a plate surface of a part arrangement surface-side of said insulating member are formed in an identical vertical plane, and a plate surface of a back surface of said part arrangement surface of said conductor plate and a plate surface of a back surface of said part arrangement surface-side of said insulating member are formed in an identical vertical plane,wherein said lead frames of said wiring pattern shapes have different thicknesses of at least two types or more, a thickness of the lead frames being measured in a direction parallel to the mounting direction of the electronic part, and a thick lead frame is used for a large current signal and a thin lead frame is used for a small current signal,
wherein said plate surface of said back surface of said part arrangement surface of said lead frames of said wiring pattern shapes and said plate surface of said back surface of said part arrangement surface-side of said insulating member are formed in an identical vertical plane to meet said plate surface of said back surface of said part arrangement surface of a thickest lead frame among said lead frames,
wherein said lead frames having different thicknesses are configured so that different wiring patterns are formed for said respective different thicknesses so as not to mutually cross and overlap and said lead frames having different thicknesses form an electronic circuit by mounting said electronic part,
wherein wiring widths of thin lead frames are smaller than wiring widths of thick lead frames, and said thin lead frames are arranged between said thick lead frames when said electronic part arrangement surface is seen from an upper side, and
wherein both side surfaces of said lead frames are formed with a plane vertical to said plate surface from a top surface of said electronic part arrangement surface to a back surface thereof.

US Pat. No. 10,192,817

ELECTROSTATIC DISCHARGE PROTECTION ELEMENT

REALTEK SEMICONDUCTOR COR...

1. An electrostatic discharge (ESD) protection element of a semiconductor device, the ESD protection element leading out an electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge, comprising:an input/output (I/O) pad connected between the I/O terminal and the internal circuit;
a first conductor connected to the I/O pad;
a second conductor connected to a ground terminal; and
a gap structure disposed between the first conductor and the second conductor and configured to establish a path from the I/O pad to the first conductor, the second conductor and to the ground terminal for conducting the electrostatic discharge current;
wherein the first conductor, the second conductor and the gap structure are disposed in a same layer of the semiconductor device with a substantially same thickness.

US Pat. No. 10,192,815

WIRING BOARD AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring board comprising:a first insulating layer;
a first wiring layer formed on a lower surface of the first insulating layer;
a first through hole which penetrates the first insulating layer in a thickness direction of the first insulating layer;
a first via wiring comprising:
a filling portion formed to fill the first through hole and connected to the first wiring layer; and
a protruding portion protruding upward from an upper surface of the first insulating layer;
a second wiring layer comprising a land, wherein the land comprises:
an outer circumferential portion covering the upper surface of the first insulating layer; and
a central portion formed integrally with the outer circumferential portion to cover a side surface and an upper surface of the protruding portion and protruding upward from an upper surface of the outer circumferential portion,
a second insulating layer formed on the upper surface of the first insulating layer to cover the second wiring layer;
a second through hole which penetrates the second insulating layer in the thickness direction to expose a side surface and an upper surface of the central portion;
a second via wiring formed to fill the second through hole to cover the side surface and the upper surface of the central portion; and
a third wiring layer formed on an upper surface of the second insulating layer and connected to the second via wiring,
wherein
the filling portion comprises:
a first metal film covering an inner side surface of the first through hole, the first metal film including an upper end surface that is planar with the upper surface of the first insulating layer;
a second metal film covering the first metal film; and
a metal layer covering the second metal film,
the protruding portion comprises:
the metal layer protruding upward from the upper surface of the first insulating layer; and
the second metal film covering a side surface and an upper surface of the metal layer exposed from the upper surface of the first insulating layer, and
the first via wiring has a step at a boundary between the protruding portion and the filling portion, the step formed along the upper end surface of the first metal film and a side surface and an upper surface of the second metal film, the side surface and the upper surface of the second metal film being exposed from the first metal film.

US Pat. No. 10,192,812

POLYMER LAYER ON METAL CORE FOR PLURALITY OF BUMPS CONNECTED TO CONDUCTIVE PADS

Samsung Display Co., Ltd....

1. A semiconductor chip, comprising:a substrate;
one or more conductive pads disposed on the substrate; and
one or more bumps electrically connected to the one or more conductive pads,
wherein the one or more bumps comprise a metal core, a polymer layer disposed over side and upper surfaces of the metal core, and a conductive coating layer disposed over side and upper surfaces of the polymer layer and electrically connected to the one or more conductive pads.

US Pat. No. 10,192,811

POWER SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A power semiconductor device comprising:a metallic lead frame that includes a mounting surface and a dissipating surface opposite to the mounting surface, and including a P-potential electrode, intermediate potential electrodes, and an N-potential electrode that are electrically independent;
power semiconductor chips and a current detection resistor that are disposed on the mounting surface of the metallic lead frame via conductive joining members;
a wiring member that connects an electrode of one of the power semiconductor chips to a portion of the metallic lead frame; and
a resin that covers a portion of the mounting surface of the metallic lead frame, the power semiconductor chips, the current detection resistor and the wiring member,
wherein the P-potential electrode and the N-potential electrode are disposed on a centerline of the metallic lead frame, and
the metallic lead frame, the power semiconductor chips, the wiring member and the current detection resistor are disposed in symmetry with respect to the centerline.

US Pat. No. 10,192,810

UNDERFILL MATERIAL FLOW CONTROL FOR REDUCED DIE-TO-DIE SPACING IN SEMICONDUCTOR PACKAGES

Intel Corporation, Santa...

1. A semiconductor apparatus, comprising:first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies laterally adjacent to one another and separated by a spacing;
a barrier structure disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die; and
an underfill material layer in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die, wherein the underfill material layer is disposed on and over an uppermost surface of the barrier structure at a location of a highest point of the uppermost surface of the barrier structure above the common semiconductor package substrate but is not on a portion of the uppermost surface of the barrier structure underneath the first semiconductor die.

US Pat. No. 10,192,809

SEMICONDUCTOR ARRAY AND PRODUCTION METHOD FOR MICRO DEVICE

TOYODA GOSEI CO., LTD., ...

1. A method for producing a micro device, the method comprising:forming a decomposition layer;
forming a bridging portion on the decomposition layer;
decomposing the decomposition layer;
forming a plurality of semiconductor laminates on the bridging portion;
and separating the substrate from the semiconductor laminates, wherein,
in the decomposition layer formation, a plurality of threading dislocations are extended during growth of the decomposition layer;
in the bridging portion formation, the bridging portion having a leg portion and a top portion is formed, and the threading dislocations are exposed to the surface of the bridging portion;
in the decomposition of the decomposition layer, the threading dislocations exposed to the surface of the bridging portion are widened to thereby provide a plurality of through holes penetrating the bridging portion, and the decomposition layer is decomposed through the through holes; and
in the semiconductor laminate formation, each of the semiconductor laminates is grown from the top portion of the bridging portion.

US Pat. No. 10,192,807

POWER SEMICONDUCTOR MODULE, FLOW PATH MEMBER, AND POWER-SEMICONDUCTOR-MODULE STRUCTURE

FUJI ELECTRIC CO., LTD., ...

1. A power semiconductor module comprising:a metal base plate including a first surface and a second surface opposite to the first surface;
a multi-layer substrate including a third surface and a fourth surface opposite to the third surface, the fourth surface being joined to the first surface;
a semiconductor element mounted on the third surface;
a resin case disposed on the first surface of the metal base plate, the resin case surrounding the multi-layer substrate and the semiconductor element; and
a cooling case including
a bottom wall,
a side wall formed around the bottom wall and having one end of the side wall being joined to the second surface of the metal base plate to form a space enclosed by the metal base plate, the bottom wall, and the side wall for circulating a coolant,
an inlet portion having an inlet opening for introducing the coolant to the cooling case and an outlet portion having an outlet opening for discharging the coolant from the cooling case, the inlet portion and the outlet portion being connected to either the bottom wall or the side wall and disposed along a peripheral edge of the second surface of the metal base plate,
a first flange disposed at an inlet opening side of the inlet portion and having a main surface opposite to the inlet portion, the main surface of the first flange being parallel to a first surface of the metal base plate, and
a second flange disposed at an outlet opening side of the outlet portion and having a main surface opposite to the outlet portion, the main surface of the second flange being parallel to the first surface.

US Pat. No. 10,192,806

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:an insulating substrate including a metal plate, an insulating resin plate laminated on the metal plate, and circuit plates laminated on the insulating resin plate and including one circuit plate having a circuit pattern and an adhering pattern, which are selectively formed on the insulating resin plate;
a semiconductor element fixed to the circuit pattern of the insulating substrate with a bonding material;
a wiring member having an end connected to the one circuit plate of the insulating substrate;
a housing accommodating the insulating substrate, the semiconductor element, and the wiring member; and
a sealing material sealing the insulating substrate, the semiconductor element, and the wiring member accommodated in the housing,
wherein the adhering pattern is an opening, in a plan view, disposed in the one circuit plate, and arranged between the semiconductor element fixed to the one circuit plate and the end of the wiring member fixed to the one circuit plate,
the sealing material bonds the insulating resin plate through the opening to increase a bond between the sealing material and the insulating resin plate, and
one of the circuit plates having the adhering pattern is bonded to the insulating resin plate by the sealing material through the opening as the adhering pattern.

US Pat. No. 10,192,804

BUMP-ON-TRACE PACKAGING STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a first package component;
a first metal trace and a second metal trace on a top surface of the first package component, the first metal trace having a first thickness with respect to the top surface of the first package component and the second metal trace having a second thickness with respect to the top surface of the first package component, the first thickness and the second thickness being substantially equal;
a dielectric mask layer covering a top surface of the first package component and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace in a cross sectional view, the dielectric mask layer not exposing the second metal trace in the cross sectional view, wherein a first side surface of the second metal trace forms a first interface with the dielectric mask layer in the cross sectional view, wherein a second side surface of the second metal trace opposite the first side surface forms a second interface with the dielectric mask layer in the cross sectional view, the first interface and the second interface each extending continuously from a topmost surface of the second metal trace to a bottommost surface of the second metal trace, and the dielectric mask layer has constantly sloped sidewall surfaces defining the opening, the dielectric mask layer being a photodefinable layer;
a second package component; and
an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, the solder bump being in contact with a top surface and a side surface of the first metal trace in the opening of the dielectric mask layer, the constantly sloped sidewall surfaces of the dielectric mask layer being in contact with the side surface of the first metal trace at a first point, the solder bump being in contact with the side surface of the first metal trace at a second point, the first point being higher than the second point, an entirety of the side surface of the first metal trace being perpendicular to the top surface of the first metal trace, the side surface of the first metal trace extending continuously from a topmost surface of the first metal trace to a bottommost surface of the first metal trace, a continuous portion of the side surface of the first metal trace extending continuously from the first point to the second point being not in contact with the dielectric mask layer and not in contact with the solder bump, the second point being above a bottommost surface of the first metal trace.

US Pat. No. 10,192,801

SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE IN SUBSTRATE FOR IPD AND BASEBAND CIRCUIT SEPARATED BY HIGH-RESISTIVITY MOLDING COMPOUND

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a semiconductor substrate;
a first semiconductor die disposed over a first surface of the semiconductor substrate;
a capacitor formed over the first surface of the semiconductor substrate and laterally offset from the first semiconductor die, the capacitor including,
(a) a first conductive layer formed over the first surface of the semiconductor substrate,
(b) an insulating layer formed over the first conductive layer, and
(c) a second conductive layer formed over the insulating layer;
an encapsulant deposited around the first semiconductor die and over the capacitor;
a vertical interconnect structure formed through the encapsulant; and
a third conductive layer formed over a surface of the encapsulant opposite the capacitor, wherein the third conductive layer is in physical contact with the vertical interconnect structure and a portion of the third conductive layer is wound to form an inductor.

US Pat. No. 10,192,800

SEMICONDUCTOR DEVICE

ABB Schweiz AG, Baden (C...

1. A semiconductor device, comprising:two electrodes with opposite faces;
a semiconductor wafer sandwiched between the two electrodes;
an outer insulating ring attached to the two electrodes and surrounding the semiconductor wafer;
a middle insulating ring inside the outer insulating ring and surrounding the semiconductor wafer, whereby the middle insulating ring is made of a plastics material;
an inner insulating ring inside the middle insulating ring, whereby the inner insulating ring is made of ceramics and/or glass material;
wherein either the middle insulating ring or the inner insulating ring has a tongue and the other thereof has a groove such that the tongue fits into the groove for their rotational alignment and
wherein the middle insulating ring and the inner insulating ring have a radial opening for receiving a gate connection of the semiconductor device.

US Pat. No. 10,192,799

METHOD AND APPARATUS TO MODEL AND MONITOR TIME DEPENDENT DIELECTRIC BREAKDOWN IN MULTI-FIELD PLATE GALLIUM NITRIDE DEVICES

TEXAS INSTRUMENTS INCORPO...

13. A test method comprising:providing a first set of test structures TS0 through TSN for a gallium nitride (GaN) transistor that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSX of the first set of test structures comprising:
a GaN substrate,
a dielectric material overlying the GaN substrate,
a respective source contact abutting the GaN substrate,
a respective drain contact abutting the GaN substrate,
a respective gate overlying the substrate and lying between the source contact and the drain contact,
X respective field plates corresponding to X field plates of the N field plates of the GaN transistor that are nearest to the GaN substrate, and
a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate;
for each test structure TSX, the test method comprising:
applying a stress voltage to the drain contact of test structure TSX until a dielectric breakdown condition is detected; and
recording the time-to-failure of test structure TSX at the stress voltage.

US Pat. No. 10,192,798

INTEGRATED CIRCUIT DIE HAVING A SPLIT SOLDER PAD

EM Microelectronic-Marin ...

1. An electronic system, comprising:an integrated circuit die having:
at least two bond pads, and
a redistribution layer having:
at least one solder pad comprising a first and second portion being separated from each other to provide a separation space between the first and second portion and being configured to provide an electrical connection between each of the first and second portion by a solder ball disposed on the at least one solder pad, and to electrically isolate the first and second portion in an absence of the solder ball on the at least one solder pad, and
at least two redistribution wires, each connecting a different one of the first and second portion to a different one of the at least two bond pads, a second bond pad of the at least two bond pads being connected via a second redistribution wire of the at least two redistribution wires to a second portion of the first and second portion of the at least one solder pad being dedicated to testing the integrated circuit die; and
a grounded printed circuit board track,
wherein the solder ball is disposed between the at least one solder pad and the grounded printed circuit board track, and
wherein no redistribution wires traverse the separation space between the first and second portion.

US Pat. No. 10,192,797

SEMICONDUCTOR DEVICE AND ELECTRICAL CONTACT STRUCTURE THEREOF

Mitsubishi Electric Corpo...

1. A semiconductor device having a semiconductor element region, in which a semiconductor element is formed, and a terminal region provided in an outer peripheral part of said semiconductor element, the semiconductor device comprising:a plurality of electrodes formed on a surface of said semiconductor element;
a protective layer having opening parts respectively provided vertically over the semiconductor element at each electrode such that a portion of each said electrode is exposed at the opening parts, and vertically over and covering the other portions of said electrodes excluding said portion of said electrodes exposed at said opening part, said protective layer being insulative; and
a conductive layer formed so as to cover said protective layer and said opening parts and directly connected to said electrodes at said opening parts, wherein
said electrodes have substantially the same electric potential, and
said conductive layer is formed across said electrodes, wherein said protective layer has a plurality of said opening parts for each said electrode.

US Pat. No. 10,192,796

SEMICONDUCTOR DEVICE AND METHOD OF FORMING DUAL-SIDED INTERCONNECT STRUCTURES IN FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a substrate;
a vertical interconnect structure formed in contact with a first surface of the substrate, wherein the substrate includes an opening extending from a second surface of the substrate opposite the first surface of the substrate to the vertical interconnect structure;
a semiconductor die disposed over the first surface of the substrate;
an encapsulant deposited over the first surface of the substrate, a side surface of the substrate, and around the semiconductor die, including a surface of the encapsulant outside the substrate coplanar with the second surface of the substrate; and
a first interconnect structure formed over the encapsulant opposite the substrate and coupled to the semiconductor die.

US Pat. No. 10,192,795

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a power transistor that passes a current from a high-potential terminal to a low-potential terminal, the power transistor comprising a gate electrode insulated from a channel region of the power transistor by an insulating film; and
a temperature sensing diode that senses a variation in temperature due to heating of the power transistor,
wherein the low-potential terminal of the power transistor and a cathode of the temperature sensing diode are directly electrically connected to each other so as to have a same potential.

US Pat. No. 10,192,793

PATTERN FORMATION METHOD, IMPRINT DEVICE, AND COMPUTER-READABLE NON-VOLATILE STORAGE MEDIUM STORING DROP RECIPE ADJUSTMENT PROGRAM

Toshiba Memory Corporatio...

1. A pattern formation method comprising:forming a first imprint pattern for a prepared sample;
measuring residual film thickness distribution of the first imprint pattern;
calculating change rate of the residual film thickness of the first imprint pattern with respect to drop density of a resist material at the time of formation of the first imprint pattern;
forming a first etching pattern using the first imprint pattern as a mask;
measuring dimension distribution of the first etching pattern;
calculating a correction coefficient based on the residual film thickness distribution of the first imprint pattern and the dimension distribution of the first etching pattern;
correcting the residual film thickness of the first imprint pattern based on the correction coefficient to reduce a variation in size of the first etching pattern;
calculating a first drop density of an imprint material based on the change rate of the residual film thickness of the first imprint pattern with respect to drop density to obtain the corrected residual film thickness;
dropping the imprint material onto an etching material based on the first drop density;
pressing a template against the dropped imprint material to form the second imprint pattern with the corrected residual film thickness on the etching material;
etching the etching material using the second imprint pattern as a mask to form a second etching pattern;
determining whether dimension distribution of the second etching pattern falls within a specification;
calculating, when the dimension distribution of the second etching pattern does not fall within the specification, an additional residual film thickness to compensate for insufficient adjustment of the dimension of the second etching pattern; and
calculating a second drop density of the imprint material to obtain the additional residual film thickness.

US Pat. No. 10,192,790

SRAM DEVICES AND FABRICATION METHODS THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a static random-access memory (SRAM) device, comprising:providing a base substrate including a pull up (PU) transistor region and a pull down (PD) transistor region adjacent to the PU transistor region;
forming a gate dielectric layer on a portion of the base substrate in the PU transistor region and the PD transistor region;
forming a first work function (WF) layer using a P-type WF material on the gate dielectric layer;
removing a portion of the first WF layer formed in the PD transistor region;
forming a second WF layer using a P-type WF material on a remaining portion of the first WF layer in the PU transistor region and on the gate dielectric layer in the PD transistor region;
removing a portion of the second WF layer formed in the PD transistor region;
forming a third WF layer using an N-type WF material on a top surface and a sidewall surface of a remaining portion of the second WF layer in the PU transistor region, a sidewall surface of the remaining portion of the first WF layer in the PU transistor region, and the gate dielectric layer in the PD transistor region; and
forming a gate electrode layer on the third WF layer.

US Pat. No. 10,192,785

DEVICES AND METHODS RELATED TO FABRICATION OF SHIELDED MODULES

Skyworks Solutions, Inc.,...

1. A method for preparing a carrier assembly for processing of packaged modules, the method comprising:providing a plate having a first side and a second side, and defining a plurality of openings, such that each opening extends through the plate between the first side and the second side; and
implementing an adhesive layer on the first side of the plate, such that the adhesive layer defines a plurality of openings arranged to substantially match the openings of the plate, each opening of the adhesive layer dimensioned such that the adhesive layer is capable of providing an adhesive engagement between a perimeter portion of an underside of a package and a perimeter portion about the corresponding opening of the adhesive layer, and such that the underside of the package not in engagement with the adhesive layer is exposed through the respective opening on the second side of the plate.

US Pat. No. 10,192,783

GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a gate electrode above a substrate, the gate electrode having a bottom surface, a first portion of the gate electrode bottom surface over a single crystalline region of the substrate and a second portion of the gate electrode bottom surface over a trench isolation layer of the substrate;
a source region or drain region in the single crystalline region of the substrate at a side of the gate electrode;
a dielectric sidewall spacer laterally adjacent the side of the gate electrode;
a gate etch stop layer over the gate electrode;
a trench contact structure on the source region or drain region, laterally adjacent the dielectric sidewall spacer; and
a single conductive via structure over and in contact with the trench contact structure, over the dielectric sidewall spacer, and over and in direct contact with the gate electrode, the conductive via structure in an opening in the gate etch stop layer, the opening exposing a portion of but not all of the gate electrode.

US Pat. No. 10,192,781

INTERCONNECT STRUCTURES INCORPORATING AIR GAP SPACERS

International Business Ma...

1. A process for manufacturing a dual damascene article of manufacture comprising a trench and a conductive metal column, said trench and said conductive metal column extending down into and contiguous with a via, said trench and said conductive metal column and said via having a common axis, wherein said trench and said via further comprise a sidewall air gap adjacent the side walls of said trench, said via, and said conductive metal column, said sidewall air-gap extending down to said via to a depth below a line fixed by the bottom of said trench, and continues downward in said via for a distance of from about 1 Angstrom below said line to the full depth of said via, said air gap being on opposite sides of said trench and said via, said process comprising forming said trench and said via of said dual damascene article of manufacture, coating the side wall of said trench and the side wall of said via with a dielectric material said dielectric material being on opposite sides of said trench and said via, damaging said dielectric material to form a damaged dielectric material on said side wall of said trench and said side wall of said via, metallizing said trench and said via having said damaged dielectric material to form a conductive metal column in said trench and a conductive metal column in said via and separately forming a metallization liner material in said trench and said via whereby said metallization liner is on opposite sides of said conductive metal column and contiguous with and interposed between said conductive metal column and said dielectric material, and removing said damaged dielectric material to form a sidewall air-gap adjacent said side wall, wherein said air gap is contiguous with said metallization liner and said metallization liner is contiguous with said conductive metal column, and further comprising providing a perforated pinched off cap operatively associated with said article, said perforated pinched off cap comprising a first cap layer patterned with a patterning layer that defines a narrower gap or narrower gaps extending from the top surface of said first cap layer to the bottom surface of said first cap layer, with said narrower gap or narrower gaps extending through said bottom surface of said first cap layer and being positioned over and projecting into said sidewall air-gap, and sealing only said narrower gap or narrower gaps, and further providing a second non-perforated cap layer operatively associated with and extending over said top surface of said first cap layer.

US Pat. No. 10,192,775

METHODS FOR GAPFILL IN HIGH ASPECT RATIO STRUCTURES

APPLIED MATERIALS, INC., ...

1. A processing method comprising:providing a substrate surface having an opening formed by at least one feature, the at least one feature, the at least one feature extending a depth from the substrate surface to a bottom surface, the at least one feature having a width defined by a first sidewall and a second sidewall;
forming a first quantity of a film on the substrate surface and the first sidewall, second sidewall and bottom surface of the at least one feature in a first deposition sequence, the first quantity of the film having a seam located within the width of the at least one feature wherein a bottom of the seam being at a first distance from the bottom surface of the at least one feature; and
reducing a height of the first quantity of the film to less than the first distance to remove at least some of the first quantity of the film and to completely remove the seam.

US Pat. No. 10,192,774

TEMPERATURE CONTROL DEVICE FOR PROCESSING TARGET OBJECT AND METHOD OF SELECTIVELY ETCHING NITRIDE FILM FROM MULTILAYER FILM

TOKYO ELECTRON LIMITED, ...

6. A method of selectively etching a nitride film from a processing target object, which has a multilayer film in which an oxide film and the nitride film are alternately stacked on top of each other, by using a temperature control device comprising a moving stage allowed to be heated and configured to mount a processing target object on a top surface thereof; a cooling body allowed to be cooled and fixed at a position under the moving stage; a shaft, having one end connected to the moving stage; the other end positioned under the cooling body; a first flange provided at the other end; and a second flange provided between the first flange and the cooling body, extended between the one end and the other end; a driving plate, provided between the first flange and the second flange, having a top surface facing the second flange and a bottom surface opposite to the top surface; an elastic body provided between the bottom surface of the driving plate and the first flange; and a driving unit configured to move the driving plate up and down, the method comprising:placing the processing target object on the top surface of the moving stage;
bringing the moving stage into contact with the cooling body by moving the driving plate downwards;
adjusting a contact thermal resistance between the moving stage and the cooling body by adjusting an amount of a downward movement of the driving plate;
etching the nitride film selectively from the multilayer film by plasma of a processing gas containing fluorine and hydrogen after the bringing of the moving stage into contact with the cooling body;
spacing the moving stage apart from the cooling body by moving the driving plate upwards after the etching of the nitride film; and
removing a reaction product, which is generated in the etching of the nitride film, by heating the moving stage after the spacing of the moving stage apart from the cooling body.

US Pat. No. 10,192,772

SUBSTRATE TABLE AND LITHOGRAPHIC APPARATUS

ASML Netherlands B.V., V...

1. A substrate table to support a substrate, the substrate table comprising:a main body;
burls extending from the main body and having first upper ends, the first upper ends defining a support surface to support the substrate; and
support pins having second upper ends, the support pins being movable between a retracted position, in which the second upper ends are arranged below the support surface, and an extended position, in which the second upper ends extend above the support surface,
wherein at least some of the support pins are arranged to support the substrate in the extended position,
wherein the support pins are arranged to be switched to a first stiffness mode and a second stiffness mode,
wherein, in the first stiffness mode, the at least some of the support pins have a first stiffness in a direction parallel to the support surface,
wherein, in the second stiffness mode, the at least some of the support pins have a second stiffness in the direction parallel to the support surface,
wherein the first stiffness is different from the second stiffness.

US Pat. No. 10,192,771

SUBSTRATE HOLDING/ROTATING DEVICE, SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME, AND SUBSTRATE PROCESSING METHOD

SCREEN Holdings Co., Ltd....

1. A substrate holding/rotating device comprising:a rotary table;
a rotation driving unit that rotates the rotary table around a rotational axis aligned with a vertical direction; and
a plurality of movable pins that supports a substrate horizontally, each of the movable pins having a support portion movable between an open position that is far apart from the rotational axis and a hold position that has approached the rotational axis, the plurality of movable pins being arranged to rotate around the rotational axis together with the rotary table,
the plurality of movable pins including a first movable pin group including at least three movable pins, and a second movable pin group including at least three movable pins other than the movable pins belonging to the first movable pin group,
the substrate holding/rotating device further comprising:
an urging unit that urges the support portion of each of the movable pins to one of the open position and the hold position;
first driving magnets, mounted in correspondence to the respective movable pins of the first movable pin group, having magnetic pole directions orthogonal to the rotational axis and mutually equal with respect to the rotational axis;
second driving magnets, mounted in correspondence to the respective movable pins of the second movable pin group, having magnetic pole directions orthogonal to the rotational axis and opposite those of the first driving magnets with respect to the rotational axis;
a first moving magnet, arranged in a non-rotating state, having a magnetic pole direction such as to apply a repulsive force or an attractive force to the first driving magnets along directions orthogonal to the rotational axis, and, by the repulsive force or the attractive force, urging the support portions of the first movable pin group to the other of the open position and the hold position;
a second moving magnet, arranged in a non-rotating state, having a magnetic pole direction such as to apply a repulsive force or an attractive force to the second driving magnets along directions orthogonal to the rotational axis, and, by the repulsive force or the attractive force, urging the support portions of the second movable pin group to the other of the open position and the hold position;
a first relative movement unit that makes the first moving magnet and the rotary table move relatively between a first position, at which the first moving magnet applies the repulsive force or the attractive force to the first driving magnets, and a second position, at which the first moving magnet does not apply the repulsive force or the attractive force to the first driving magnets; and
a second relative movement unit that makes the second moving magnet and the rotary table move relatively between a third position, at which the second moving magnet applies the repulsive force or the attractive force to the second driving magnets, and a fourth position, at which the second moving magnet does not apply the repulsive force or the attractive force to the second driving magnets, independently of the relative movement of the first moving magnet and the rotary table.

US Pat. No. 10,192,770

SPRING-LOADED PINS FOR SUSCEPTOR ASSEMBLY AND PROCESSING METHODS USING SAME

Applied Materials, Inc., ...

1. A susceptor assembly, comprising:a susceptor having a susceptor body and a top surface with at least one recess therein sized to enclose a wafer during processing, each recess having a bottom surface with at least three flared openings; and
at least three lift pins positioned within each recess, each lift pin positioned within one of the at least three flared openings in the bottom surface of the recess, each lift pin comprising a sleeve having an elongate body with a flared top end, bottom, sides and an elongate axis, the sleeve movable within the recess along the elongate axis so that the flared top end of the sleeve can extend above the bottom surface of the recess, a spring within the elongate body of the sleeve adjacent the bottom of the sleeve and a pin positioned within the elongate sleeve in contact with the spring, the pin having a flared top portion and movable along the elongate axis of the sleeve so that a top surface of the pin can extend above the flared top end of the sleeve.

US Pat. No. 10,192,769

THERMOSETTING ADHESIVE SHEET AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

DEXERIALS CORPORATION, T...

1. A thermosetting adhesive sheet to be applied to a grinding-side surface of a semiconductor wafer when dicing the semiconductor wafer comprising:a polymer containing an elastomer;
a (meth)acrylate containing more than 95 wt % of a polyfunctional (meth)acrylate with respect to total (meth)acrylate content;
an organic peroxide having a one-minute half-life temperature of 130° C. or lower; and
a transparent filler,
wherein the transparent filler is contained at 50 to 150 pts. mass with respect to 25 pts. mass of the polymer.

US Pat. No. 10,192,767

CERAMIC ELECTROSTATIC CHUCK INCLUDING EMBEDDED FARADAY CAGE FOR RF DELIVERY AND ASSOCIATED METHODS FOR OPERATION, MONITORING, AND CONTROL

Lam Research Corporation,...

1. A substrate support system, comprising:a ceramic assembly having a top surface and a bottom surface, the top surface including an area configured to support a substrate;
at least one clamp electrode positioned within the ceramic assembly;
a primary radiofrequency (RF) power delivery electrode positioned within the ceramic assembly at a location vertically below the at least one clamp electrode;
a lower support structure formed of an electrically conductive material, the ceramic assembly secured to the lower support structure such that an outer peripheral region of the bottom surface of the ceramic assembly is supported by the lower support structure, the lower support structure including a hollow interior region exposed to a portion the bottom surface of the ceramic assembly; and
a plurality of electrical connections established between the lower support structure and the primary RF power delivery electrode, each of the plurality of electrical connections extending through a respective portion of the ceramic assembly.

US Pat. No. 10,192,765

SUBSTRATE PROCESSING SYSTEMS, APPARATUS, AND METHODS WITH FACTORY INTERFACE ENVIRONMENTAL CONTROLS

Applied Materials, Inc., ...

1. A method of processing substrates within an electronic device processing system, comprising:providing a factory interface including a factory interface chamber, one or more substrate carriers docked to the factory interface, each of the one or more substrate carriers having a substrate carrier door, one or more carrier purge chambers within the factory interface chamber, and one or more load lock chambers coupled to the factory interface;
sealing a carrier purge housing to the factory interface chamber, the carrier purge housing having a carrier purge chamber located therein, the sealing covering a substrate carrier door and isolating the carrier purge chamber from the factory interface chamber;
monitoring one or more environmental conditions in the carrier purge chamber;
setting one or more environmental conditions in the carrier purge chamber in response to the monitoring;
opening the substrate carrier door by attaching a door opener to the substrate carrier door, the door opener being attached to a rack and pinion, the rack located within the carrier purge chamber, the pinion being attached to a motor at least partially located external to the carrier purge chamber; and
unsealing the carrier purge housing from the factory interface.

US Pat. No. 10,192,763

METHODOLOGY FOR CHAMBER PERFORMANCE MATCHING FOR SEMICONDUCTOR EQUIPMENT

Applied Materials, Inc., ...

1. A method for calibrating a plasma processing chamber for semiconductor manufacturing process, comprising:performing a first predetermined plasma process in a plasma processing chamber;
maintaining a desired gas pressure in the plasma processing chamber;
collecting a first set of signals transmitted from a first group of sensors disposed in the plasma processing chamber to a controller while performing the predetermined process;
analyzing the collected first set of signals;
comparing the collected first set of signals with database stored in the controller of the plasma processing chamber to check sensor responses from the first group of sensors;
calibrating sensors based on the collected first set of signals when a mismatch sensor response is found;
subsequently performing a first series of plasma processes including at least two processes in the processing chamber, wherein the first series of processes comprises multiple processes including the process parameters set in the first predetermined process, 20% above and below of the process parameters set in the first predetermined process, and 10% above and below of the process parameters set in the first predetermined process; and
collecting a second set of signals transmitted from the sensors to the controller while performing the series of plasma processes in the plasma processing chamber.

US Pat. No. 10,192,762

SYSTEMS AND METHODS FOR DETECTING THE EXISTENCE OF ONE OR MORE ENVIRONMENTAL CONDITIONS WITHIN A SUBSTRATE PROCESSING SYSTEM

APPLIED MATERIALS, INC., ...

1. A method for operating a substrate processing cluster tool, comprising:positioning a substrate storage cassette at least partially within a factory interface of the substrate processing cluster tool, the substrate storage cassette defining an interior volume dimensioned and arranged to receive one or more substrates;
sensing, with a plurality of sensors, at least one condition including temperature within the substrate storage cassette, an elapsed time between termination of a first process involving the substrate storage cassette and initiation of a second process involving the substrate storage cassette, a concentration of one or more airborne contaminants within at least one of the substrate storage cassette or the factory interface, or a humidity within the substrate storage cassette; and
responsive to a sensed condition generating an alert and performing a corrective operation involving the substrate storage cassette.

US Pat. No. 10,192,759

IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING

LAM RESEARCH CORPORATION,...

1. A semiconductor processing tool, comprising:one or more process chambers;
one or more gas inlets into the one or more process chambers and associated flow-control hardware;
a low frequency radio frequency (LFRF) generator;
a high frequency radio frequency (HFRF) generator; and
a controller having at least one processor and a memory, wherein
the at least one processor and the memory are communicatively connected with one another,
the at least one processor is at least operatively connected with the flow-control hardware, the LFRF generator, and the HFRF generator, and
the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow-control hardware, the HFRF generator, and the LFRF generator to:
etch a semiconductor substrate to transfer a pattern from an overlying photoresist to a core amorphous carbon layer on the semiconductor substrate;
deposit a conformal film over the patterned core amorphous carbon layer on the semiconductor substrate;
deposit a gap-fill amorphous carbon layer over the conformal film;
planarize the semiconductor substrate with a process that etches both the conformal film and the gap-fill amorphous carbon layer to remove the conformal film overlying the core amorphous carbon layer without removing the conformal film deposited between the core amorphous carbon layer and the gap-fill amorphous carbon layer; and
selectively etch the conformal film to form a mask.

US Pat. No. 10,192,758

SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus that processes a substrate with a processing liquid and dries the substrate, the substrate processing apparatus comprising:a substrate rotating device configured to rotate the substrate;
a processing liquid discharging unit configured to discharge the processing liquid toward the substrate;
a substitution liquid discharging unit configured to discharge a substitution liquid, which is substituted with the processing liquid on the substrate, toward the substrate while relatively moving with respect to the substrate to form a liquid film of the substitution liquid on the substrate; and
an inert gas discharging unit configured to:
discharge a first inert gas, from a first inert gas discharge nozzle provided vertically downward, vertically downward from above a central portion of the substrate toward a central portion of the liquid film of the substitution liquid formed on the substrate to form an interface where the liquid film of the substitution liquid is thicker at a peripheral portion side of the substrate than at a central portion side thereof and to increase an area confined by the interface uniformly from the central portion of the substrate toward a peripheral portion thereof, and then
push the interface from the central portion of the substrate toward the peripheral portion thereof by discharging a second inert gas, from a second inert gas discharge nozzle provided to be inclined downward, toward a peripheral portion of the substrate in an inclined direction from above the substrate while moving the second inert gas discharge nozzle relatively with respect to the substrate in a direction different from a direction in which the substitution liquid discharging unit is moved.

US Pat. No. 10,192,757

SUBSTRATE CLEANING APPARATUS AND SUBSTRATE CLEANING METHOD

EBARA CORPORATION, Tokyo...

1. A substrate cleaning apparatus, comprising:a substrate holder configured to hold a substrate and rotate the substrate about a rotational axis;
a roll cleaning tool configured to be placed in sliding contact with the substrate to thereby clean the substrate; and
a cleaning-tool rotating device coupled to the roll cleaning tool;
a vertically-moving device coupled to the cleaning-tool rotating device, the vertically-moving device being configured to change a vertical position of the roll cleaning tool toward the substrate held by the substrate holder and keep the vertical position of the roll cleaning tool while cleaning the substrate;
a cleaning-liquid supply nozzle configured to supply cleaning liquid onto a first region of the substrate;
a fluid supply nozzle arranged in parallel with a longitudinal direction of the roll cleaning tool as viewed from an extending direction of the rotational axis, the fluid supply nozzle being configured to supply fluid, which is constituted by pure water or chemical liquid, onto a second region of the substrate, the cleaning-liquid supply nozzle being located at one side of the roll cleaning tool, while the fluid supply nozzle being located at an opposite side of the roll cleaning tool beside the roll cleaning tool, the fluid supply nozzle being located at a position to form a flow of the fluid along the longitudinal direction of the roll cleaning tool at the second region located at an opposite side of the substrate from the first region across the roll cleaning tool.

US Pat. No. 10,192,755

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
a plurality of wiring layers formed over the semiconductor substrate;
a pad electrode formed in the uppermost layer of the wiring layers;
a first protective film having an opening over the pad electrode;
a first redistribution line formed over the first protective film and having an upper surface, a side surface and a lower surface, the first redistribution line coupled electrically to the pad electrode through the opening;
a sidewall barrier film comprised of an insulating film formed on the side surface of the first redistribution line; and
a cap metallic film covering the upper surface of the first redistribution line and having an overlapping part with sidewall barrier film,
wherein the cap metallic film covers the side surface of the first redistribution line, and
wherein the cap metallic film and the sidewall barrier film are overlapped with each other at the side surface of the first redistribution line.

US Pat. No. 10,192,752

SELF-ASSEMBLED MONOLAYER BLOCKING WITH INTERMITTENT AIR-WATER EXPOSURE

Applied Materials, Inc., ...

14. A method of processing a substrate, comprising:exposing a substrate to a self-assembled monolayer (“SAM”) molecule for a first period of time to achieve selective deposition of a SAM on a first material in a first processing chamber, wherein the substrate comprises an exposed first material and an exposed second material;
transferring the substrate to a second processing chamber;
exposing the substrate to a hydroxyl moiety formed from water vapor in the second processing chamber for a second period of time;
repeating the exposing the substrate to a SAM molecule in the first processing chamber and the exposing the substrate to the hydroxyl moiety formed from water vapor in the second processing chamber in a time ratio of the first period of time to the second period of time between about 1:1 and about 100:1, respectively, and wherein a first repetition occurs for a first total time and a subsequent repetition occurs for a second total time that is less than the first total time;
after performing the repeating, exposing the substrate to the SAM molecule in the first processing chamber;
selectively depositing a third material on the exposed second material; and
removing the SAM from the first material.

US Pat. No. 10,192,751

SYSTEMS AND METHODS FOR ULTRAHIGH SELECTIVE NITRIDE ETCH

LAM RESEARCH CORPORATION,...

1. A method for selectively etching a silicon nitride layer on a substrate, comprising:arranging the substrate on a substrate support of a substrate processing chamber,
wherein the substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper chamber region and the lower chamber region, and
wherein the gas dispersion device includes a plurality of holes in fluid communication with the upper chamber region and the lower chamber region;
supplying an etch gas mixture to the upper chamber region;
striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil, wherein the etch gas mixture etches silicon nitride, promotes silicon dioxide passivation and promotes polysilicon passivation;
selectively etching the silicon nitride layer on the substrate;
extinguishing the inductively coupled plasma after a predetermined period; and
after the selectively etching, dry cleaning the substrate by supplying a dry clean gas mixture to the substrate processing chamber and striking plasma in the substrate processing chamber for another predetermined period.

US Pat. No. 10,192,750

PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method for processing a workpiece that includes a silicon-containing etching target layer, an organic film provided on the etching target layer, an antireflective film provided on the organic film, and a first mask provided on the antireflective film, using a plasma processing apparatus that includes a processing container, the plasma processing method comprising:generating a first plasma in the processing container;
etching the antireflective film using the first plasma generated in the processing container and the first mask to form a second mask from the antireflective film;
etching the organic film using the first plasma generated in the processing container and the second mask to form a third mask from the organic film;
generating a second plasma of a mixed gas including a first gas and a second gas in the processing container; and
etching the etching target layer using the second plasma generated in the processing container and the third mask,
wherein the plasma processing apparatus further includes an upper electrode,
the upper electrode is provided above a placing table that supports the workpiece in the processing container,
an electrode plate of the upper electrode contains silicon,
the first gas is oxygen gas, and
after generating the second plasma of the mixed gas and before etching the etching target layer using the second plasma, a silicon oxide film is formed on a surface of the electrode plate by colliding oxygen ions contained in the second plasma of the first gas with the electrode plate.

US Pat. No. 10,192,747

MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE AND METHOD OF MANUFACTURING THEREOF

Cypress Semiconductor Cor...

1. The method of fabricating a semiconductor device, comprising:forming, on a substrate, a first gate stack having a first gate conductor layer and a first gate dielectric structure between the first gate conductor layer and the substrate;
forming an inter-gate dielectric structure at a sidewall of the first gate conductor;
forming, adjacent to the inter-gate dielectric structure, a second gate stack having a second gate conductor layer and a second gate dielectric structure between the second gate conductor layer and the substrate; and
performing a wet etch to clean the first and second gate stacks prior to forming a dielectric layer to encapsulate at least the first and second gate stacks, and the inter-gate,
wherein the inter-gate dielectric structure includes four or more layers of two or more different dielectric films disposed in an alternating manner, and having significantly different wet etch rates against a same etchant, wherein each of the four or more layers includes a width in an approximate range of 30 ? or less, and wherein the inter-gate dielectric structure is substantially un-etched by the wet etch in a direction perpendicular to the substrate.

US Pat. No. 10,192,744

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

Semiconductor Manufacturi...

1. A semiconductor device comprising:a first substrate, wherein a through hole extends through the first substrate;
a second substrate, which overlaps the first substrate;
a first conductor, which is configured to electrically connect two elements associated with the first substrate, wherein the through hole is positioned between two opposite edges of the first conductor;
a second conductor, which is positioned on the first substrate and is electrically connected to the first conductor;
a third conductor, which is configured to electrically connect two elements associated with the second substrate;
a fourth conductor which is positioned on the second substrate and is electrically connected to the third conductor; and
a fifth conductor, which directly contacts each of the second conductor and the fourth conductor and is positioned between the second conductor and the fourth conductor.

US Pat. No. 10,192,743

METHOD OF ANISOTROPIC EXTRACTION OF SILICON NITRIDE MANDREL FOR FABRICATION OF SELF-ALIGNED BLOCK STRUCTURES

TOKYO ELECTRON LIMITED, ...

1. A method of preparing a self-aligned block (SAB) structure, comprising:providing a substrate having raised features defined by a first material containing silicon nitride and a second material containing silicon oxide formed on side walls of the first material, and a third material containing an organic material covering some of the raised features and exposing some raised features according to a block pattern formed in the third material;
forming a first chemical mixture by plasma-excitation of a first process gas containing H and optionally a noble gas;
exposing the first, second, and third materials on the substrate to the first chemical mixture;
thereafter, forming a second chemical mixture by plasma-excitation of a second process gas containing N, F, O, and optionally a noble element; and
exposing the first, second, and third materials on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second and third materials.

US Pat. No. 10,192,741

DEVICE SUBSTRATE, METHOD OF MANUFACTURING DEVICE SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method of manufacturing a device substrate, the method comprising:forming a mask film on an entire surface of a device substrate in which a multilayer film is disposed on a substrate;
removing a portion of the mask film on a bevel region that is provided as a region from a peripheral edge portion of a patterning region to an end portion of the device substrate, the patterning region being provided as the region on which a resist is to be applied during an imprint process of the device substrate; and
planarizing an upper surface of the mask film positioned on the patterning region,
wherein the planarizing of the upper surface of the mask film includes
dropping the resist onto the mask film,
placing a blank template including no rugged patterns, with respect to the mask film through the resist, such that there is a predetermined distance between the blank template and the mask film, and curing the resist, and
etching back an entire surface of the device substrate by use of dry etching.

US Pat. No. 10,192,740

HIGH THROUGHPUT SEMICONDUCTOR DEPOSITION SYSTEM

Alliance for Sustainable ...

1. A method of performing hydride vapor phase epitaxy (HVPE) deposition, the method comprising:providing at least one first source material and at least one first carrier gas flow to a first HVPE mixing zone coupled to a first deposition zone;
providing at least one second source material and at least one second carrier gas flow to a second HVPE mixing zone coupled to a second deposition zone;
heating the first deposition zone to a first temperature;
heating the first HVPE mixing zone to a second temperature;
heating the second deposition zone to a third temperature, wherein the third temperature is different from the first temperature;
heating the second HVPE mixing zone to a fourth temperature;
outputting, from the first HVPE mixing zone into the first deposition zone, first reactant gases produced from the at least one first source material and the at least one first carrier gas flow;
outputting, from the second HVPE mixing zone into the second deposition zone, second reactant gases produced from the at least one second source material and the at least one second carrier gas flow;
placing a substrate into the first deposition zone to grow a first layer from the first reactant gases; and
placing the substrate into the second deposition zone to grow a second layer from the second reactant gases,
wherein the heating of the first deposition zone to the first temperature and the heating of the second deposition zone to the third temperature are performed concurrently.

US Pat. No. 10,192,738

METHODS OF PRODUCING SEED CRYSTAL SUBSTRATES AND GROUP 13 ELEMENT NITRIDE CRYSTALS, AND SEED CRYSTAL SUBSTRATES

NGK INSULATORS, LTD., Na...

1. A method of producing a seed crystal substrate, the method comprising the steps of:providing a seed crystal layer comprising a nitride of a group 13 element on a supporting body; and
irradiating a laser light from a side of said supporting body to provide an altered portion along an interface between said supporting body and said seed crystal layer, said altered portion comprising said nitride of said group 13 element and comprising a portion with dislocation defects introduced therein or an amorphous portion,
wherein the laser light is irradiated at an optical energy such that voids are not generated along the interface between the supporting body and seed crystal layer.

US Pat. No. 10,192,737

METHOD FOR HETEROEPITAXIAL GROWTH OF III METAL-FACE POLARITY III-NITRIDES ON SUBSTRATES WITH DIAMOND CRYSTAL STRUCTURE AND III-NITRIDE SEMICONDUCTORS

Foundation for Research a...

1. A method of heteroepitaxial growth of III-Nitride semiconductors on a substrate achieving (0001) orientation and metal-face polarity for a first nucleation layer and subsequent layers, comprising the following steps:utilizing a nitrogen plasma source for molecular beam epitaxy to deposit an Al-face polarity (0001) AlN nucleation layer less than 5 nm in deposited layer thickness to minimize degradation of the epitaxial growth of the AlN layer and inversion of its polarity;
depositing said AlN layer on a substrate independent of the crystalline surface orientation of said substrate, said substrate being polycrystalline diamond; and
by the cooperation between said utilizing the nitrogen plasma source for epitaxy and said depositing of said AlN layer less than 5 nm in thickness, subsequently overgrowing on said AlN layer one or more additional III-Nitride compound layers while preserving said (0001) orientation and III metal-face polarity; and
between the steps of depositing of said AlN layer and overgrowing of said AlN layer by a III-nitride compound layer, interrupting the depositing of said AlN layer and exposing said MN layer to active nitrogen species produced by the nitrogen plasma source.

US Pat. No. 10,192,733

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND CHEMICAL LIQUID

TOSHIBA MEMORY CORPORATIO...

1. A method of manufacturing a semiconductor device comprising:attaching, by a liquid treatment, a first liquid to a surface of a semiconductor substrate having a fine pattern formed therein;
substituting the first liquid attached to the surface of the semiconductor substrate with a solution, the solution comprising a precipitating material dissolved in a second liquid;
vaporizing the second liquid and precipitating the precipitating material to the surface of the semiconductor substrate; and
removing the precipitating material by transforming the precipitating material from solid to gas by depressurization and/or heating,
the precipitating material comprising at least one material selected from a group consisting of:
materials represented by chemical formulae A1, A2, A3, and A4 indicated in FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D where X1, X2, and X3 in the chemical formulae A1, A2, A3, and A4 each independently represent either of a hydroxy group (—OH), a carboxyl group (—COOH), an amino group (—NH2), an amide group (—CONH2), a nitro group (—NO2), and a methylester group (—COO—CH3), and
materials represented by chemical formulae B1, B2, B3, B4, and B5 indicated in FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, and FIG. 6E where X1, X2, X3, and X4 in the chemical formulae B 1, B2, B3, B4 and B5 each independently represent either of a hydroxy group (—OH), a carboxyl group (—COOH), an amino group (—NH2), an amide group (—CONH2), a nitro group (—NO2), a methylester group (—COO—CH3), a methoxy group (—OCH3), an ethoxy group (—OCH2CH3), and a propoxy group (—OCH2CH2CH3),
in the materials represented by chemical formulae A1, A4, B1, B3, and B5, a group bonded to one of adjacent bonding sites is a carboxyl group and one or more groups bonded to the other of the adjacent bonding sites include a carboxyl group, a hydroxyl group, or an amino group.

US Pat. No. 10,192,732

CONTAMINANT REMOVAL IN ULTRA-THIN SEMICONDUCTOR DEVICE FABRICATION

TEXAS INSTRUMENTS INCORPO...

1. A method of fabricating a semiconductor device, the method comprising:forming topside circuitry for an integrated circuit (IC) on a topside of a semiconductor substrate of the semiconductor device, the topside circuitry having a topside metal structure and a topside passivation structure;
applying a topside protection material to protect the topside circuitry;
grinding a backside of the semiconductor substrate to a selected thickness;
removing the topside protection material;
after removal of the topside protection material, applying a chemical solution cleaning process to remove contaminants from the backside of the semiconductor substrate;
applying a deionized (DI) water cleaning process to the semiconductor substrate after the chemical cleaning process; and
forming a backside metallization (BSM) layer over the backside of the semiconductor substrate,
wherein the topside metal structure comprises a gold (Au) metal structure and the topside passivation structure comprises a polyimide passivation structure, and further wherein the chemical solution cleaning process comprises exposing the semiconductor device to a solution of a mixture having ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) in a ratio of one part of NH4OH to two parts of H2O2, and the mixture is diluted in water in a ratio of one part of the mixture to eight parts of water.

US Pat. No. 10,192,731

LIQUID PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A liquid processing method for performing a liquid processing on a substrate disposed inside a processing container, and then, drying the substrate, the method comprising:a processing liquid supplying step of performing a liquid processing by supplying a processing liquid to a center portion of the substrate inside the processing container;
a low humidity gas supplying step of supplying a low humidity gas for lowering a humidity inside the processing container, into the processing container during a time period when the processing liquid is supplied to the substrate; and
a drying step of removing the processing liquid on the substrate and drying the substrate,
wherein the drying step is started after a humidity measurement value obtained by measuring the humidity inside the processing container becomes equal to or less than a preset humidity target value.

US Pat. No. 10,192,729

APPARATUS AND METHOD FOR STATIC GAS MASS SPECTROMETRY

Thermo Fisher Scientific ...

1. A method of static gas mass spectrometry comprising the steps of:introducing a sample gas comprising two or more isotopes to be analyzed into a static vacuum mass spectrometer at a time, t0;
operating an electron impact ionization source of the mass spectrometer with a first electron energy below the ionization potential of the sample gas for a first period of time that is following t0 until a time t1, wherein the first time period from t0 to t1 is set based on a previous determination of an equilibration period taken for the isotopes of the sample gas to equilibrate in the mass spectrometer; and
operating the electron impact ionization source with a second electron energy at least as high as the ionization potential of the sample gas for a second period of time that is after time t1;
wherein isotope ratio measurements are taken by the spectrometer during the second period but not during the first period.

US Pat. No. 10,192,728

MASS SPECTROMETER AND METHOD APPLIED THEREBY FOR REDUCING ION LOSS AND SUCCEEDING STAGE VACUUM LOAD

SHIMADZU CORPORATION, Ky...

1. A mass spectrometer, comprising:an ion source, located in a first gas pressure region and providing ions;
a vacuum chamber, having an inlet and an outlet and located in a second gas pressure region having a gas pressure lower than that of said first gas pressure region; wherein ions in said first gas pressure region are allowed to pass through said inlet of said vacuum chamber and enter said vacuum chamber located in said second gas pressure region along with a gas flow generated by a pressure difference, and exit said vacuum chamber from said outlet of said vacuum chamber;
an ion guiding device, arranged in said vacuum chamber and located at a succeeding stage of said vacuum chamber inlet but a preceding stage of said vacuum chamber outlet; and
a hollow tubular lens, arranged in said vacuum chamber and located at said succeeding stage of said vacuum chamber inlet but said preceding stage of said ion guiding device;
wherein said tubular lens is an aerodynamic lens whose central axis is parallel to a direction of said gas flow entering said vacuum chamber from said inlet of said vacuum chamber, said gas flow produces a Mach disc as a result of a free expanded jet after entering said vacuum chamber, and the inlet of said tubular lens is located at the upstream part of said Mach disc.

US Pat. No. 10,192,727

ELECTRODYNAMIC MASS ANALYSIS

Varian Semiconductor Equi...

1. An electrodynamic mass analysis system, comprising:an ion source;
an electrode assembly to extract a pulse of ions from the ion source; and
a deflector to receive the pulse of ions after the ions travel a predetermined distance from the electrode assembly, the deflector comprising two curved electrodes disposed on opposite sides of a path of the ions;
a plate having a resolving aperture disposed at an output end of the deflector;
wherein the deflector deflects the ions in accordance with an arrival time, such that only ions arriving during a predetermined time interval are guided through the deflector, and exit the deflector through the resolving aperture.

US Pat. No. 10,192,726

RAPID INLINE PREPARATION OF A DILUTED SAMPLE

ELEMENTAL SCIENTIFIC, INC...

1. A spectrometry analysis system including an inline dilution environment, comprising:a dilution apparatus including
a first valve assembly configured to prepare a first sample by accepting at least one of the first sample, a diluent, a carrier, or an internal standard, where the first valve assembly includes a first sample loop within the first valve assembly, and where the first sample loop prepares the first sample within the first valve assembly;
a second valve assembly configured to prepare the first sample by accepting the first sample from the first valve assembly, where the second valve assembly is coupled to the first valve assembly, where the second valve assembly includes a second sample loop within the second valve assembly, where the second sample loop isolates the first sample for injection into a torch assembly, and where the first valve assembly accepts and prepares a second sample while the first sample is isolated in the second sample loop; and
the torch assembly coupled to the dilution apparatus, where the second sample loop isolates and dilutes the first sample for injection into a torch assembly, and where the second valve assembly is coupled with the first valve assembly and the torch assembly;
wherein the dilution apparatus is configured to perform multiple injections of the prepared first sample to an analysis device.

US Pat. No. 10,192,724

MS/MS MASS SPECTROMETRIC METHOD AND MS/MS MASS SPECTROMETER

SHIMADZU CORPORATION, Ky...

1. An MS/MS mass spectrometer including an ionizing unit for ionizing a target component in a sample, a first mass separating unit for selecting, as a precursor ion, an ion having a specific mass-to-charge ratio from multivalent ions, the multivalent ion having a valence of two or more out of ions originated from the target component, a dissociation operation unit for dissociating the precursor ion selected by the first mass separating unit, a second mass separating unit for selecting a product ion having a specific mass-to-charge ratio from product ions generated through the dissociation, and a detecting unit for detecting the ion selected by the second mass separating unit, the MS/MS mass spectrometer comprising:a) a first inputting unit for allowing a user to input and set a mass mLoss of a fragment eliminated from the precursor ion through the dissociation;
b) a second inputting unit for allowing the user to input and set at least two of three parameters of a valence zLoss of the fragment, a valence zPrec of the precursor ion and a valence zprod of the product ion, the valence zLoss of the fragment being a valence of the fragment eliminated from the precursor ion through the dissociation when the dissociation is based on dissociation operation other than electron capture dissociation or a valence of a fragment before neutralized that captures an electron to be neutralized and eliminated when the dissociation is based on the electron capture dissociation;
c) a lack information calculating unit for calculating, when one of the three parameters zLoss, zPrec and zProd is not input, the one uninput parameter zLoss, zPrec or zProd from the parameters input by the second inputting unit using relation, zPrec=zProd+zLoss; and
d) a controlling unit for individually controlling operations of the first mass separating unit and the second mass separating unit in performing MS/MS analysis such that a mass-to-charge ratio MProd of the product ion selected by the second mass separating unit with respect to a mass-to-charge ratio MPrec of the precursor ion selected by the first mass separating unit satisfies relation, MProd=(MPrec×zPrec?mLoss)/zProd.

US Pat. No. 10,192,719

PLASMA PROCESSING METHOD

Tokyo Electron Limited, ...

1. A plasma processing method comprising:a step of loading a substrate into a chamber where a plasma process is to be executed;
a step of mounting the substrate on a mounting table;
a first step of applying a bias power to the mounting table for a predetermined time period,
stopping the bias power after the predetermined time period, the bias power having a frequency that is lower than a frequency of excitation power for plasma excitation;
a second step of applying the bias power to the mounting table on which the substrate is mounted before applying an excitation power for plasma excitation;
a step of applying a DC voltage to an electrostatic chuck and electrostatically attracting the substrate that is mounted on the mounting table;
a step of supplying etching gas in the chamber; and
a step of applying the excitation power for the plasma excitation,
wherein the first step of applying the bias power and the second step of applying the bias power are performed on an identical substrate as one cycle before the DC voltage is applied on the electrostatic chuck so as to electrostatically attract the substrate by the electrostatic chuck,
wherein the first and second steps of applying the bias power are performed before supplying the etching gas, and
wherein the bias power of the first and the second steps are the same bias power and applied by one high frequency power source.

US Pat. No. 10,192,717

CONDITIONING REMOTE PLASMA SOURCE FOR ENHANCED PERFORMANCE HAVING REPEATABLE ETCH AND DEPOSITION RATES

APPLIED MATERIALS, INC., ...

10. The method of claim 9, wherein the passivation time of the interior wall surface of the remote plasma source and the processing time for performing a series of processes on N number of substrates are at a ratio of about 1:5 to about 1:30.

US Pat. No. 10,192,716

MULTI-BEAM DARK FIELD IMAGING

KLA-Tencor Corporation, ...

1. An apparatus, comprising:an electron source;
at least one optical device configured to produce a plurality of primary beam lets utilizing electrons provided by the electron source, the at least one optical device further configured to deliver the plurality of primary beam lets toward a target; and
an array of multi-channel detectors configured to receive a plurality of image beam lets emitted by the target in response to the plurality of primary beamlets, the array of multi-channel detectors further configured to render an array of dark field images to form a contiguous dark field image, wherein each multi-channel detector of the array of detectors comprises a set of detector elements.

US Pat. No. 10,192,715

MEASUREMENT OF THE ELECTRIC CURRENT PROFILE OF PARTICLE CLUSTERS IN GASES AND IN A VACUUM

1. A Faraday detector to measure the electric current profile of clusters of electrically charged particles, comprising:a detector electrode having structural elements in a bipolar arrangement of two groups, where neighboring structural elements have opposite polarities and structural elements with the same polarity are electrically connected, and bordering a gas-filled or evacuated space;
at least one voltage supply which is connected with the two groups of structural elements and supplies the two groups of structural elements simultaneously with different electric potentials such that charged particles originating from the space are substantially all deflected onto one of the two groups of structural elements having one polarity; and
a set of measurement electronics which is configured to separately measure current profiles at the structural elements of both polarities and to generate a differential signal by subtracting the current profiles to leave only a particle current profile.

US Pat. No. 10,192,712

CHARGED PARTICLE BEAM WRITING APPARATUS, METHOD OF ADJUSTING BEAM INCIDENT ANGLE TO TARGET OBJECT SURFACE, AND CHARGED PARTICLE BEAM WRITING METHOD

NuFlare Technology, Inc.,...

1. A method of adjusting a beam incident angle to a target object surface comprising:applying, using a blanking deflector arranged backward of an electron lens with respect to a direction of an optical axis, a voltage for beam-on to the blanking deflector, converging, using the electron lens and a magnet coil arranged in a center height position of the blanking deflector, a charged particle beam by varying a voltage to be applied to the electron lens while supplying, to the magnet coil, a current for a deflection amount smaller than a deflection amount for performing deflection to make a beam-off state by the blanking deflector, and measuring a positional deviation amount of an irradiation position of the charged particle beam irradiating a target object, for each voltage to be applied to the electron lens;
determining whether the positional deviation amount is within an allowable value, for the each voltage to be applied to the electron lens; and
when the positional deviation amount is determined to be greater than an allowable value, the each voltage to be applied to the electron lens are adjusted so that the positional deviation amount is within the allowable value.

US Pat. No. 10,192,711

FLUID INJECTOR FOR X-RAY TUBES AND METHOD TO PROVIDE A LIQUID ANODE BY LIQUID METAL INJECTION

Siemens Aktiengesellschaf...

1. A fluid injector for x-ray tubes to provide a liquid anode by liquid metal injection, comprising:a device which injects fluid from an opening in a chamber of the device as a fluid jet generated by an arrangement for changing a volume within the chamber;
a pipe connected to the chamber of the device; and
a reservoir for storing the anode material, said reservoir being fluidically connected by the pipe with the chamber of the device;
wherein the pipe comprises a part formed in a fluid flow direction with a shape to block fluid flow from the chamber to the reservoir during injection.

US Pat. No. 10,192,708

ELECTRON EMITTER SOURCE

OREGON PHYSICS, LLC, Bea...

1. An electron emitter comprising:a wehnelt
an anode spaced downstream from said wehnelt;
a co-axial aperture formed through said wehnelt and said anode; and
an emitter extending into said co-axial aperture so that a terminal surface of said emitter is positioned between said wehnelt and said anode, said emitter having a cylindrical base formed of a high work function material having a hole formed through said terminal surface and extending into a body of the cylindrical base, said emitter further including a structure formed of a low work function material embedded within said hole and having an exposed emissive area,
wherein said emitter is heated and biased to a negative voltage relative to the anode.

US Pat. No. 10,192,707

FUSE ASSEMBLY WITH REPLACEABLE CASING

1. A fuse assembly comprising:a casing having two slots defined through a first end thereof, the casing having a room defined therein which communicates with the two slots, two protrusions extending from an inside of the room, the casing having two insertion recesses defined through the first end thereof, each of the insertion recesses having a positioning member formed in an inside surface thereof;
a conductive member located in the casing and having a first end extending through a second end of the casing, the conductive member including two blades which are located with a gap formed therebetween, a fuse connected between the two blades, each of the two blades having a hole, the two protrusions engaged with the two holes of the two blades;
a cap having an open bottom which is detachably mounted to the first end of the casing, two arms respectively extending from two ends of the cap and each arm having a hook end, the two arms inserted into the two insertion recesses and the two hook ends being detachably hooked to the two positioning members, and
a light member connected to the cap and having a bulb and a leg portion which is electrically connected to the bulb, the leg portion being electrically connected to a second end of the conductive member.

US Pat. No. 10,192,703

BYPASS SWITCH COMPRISING A PLUNGER, A FIRST CONTACT DEVICE AND A SECOND CONTACT DEVICE

ABB SCHWEIZ AG, Baden (C...

1. A bypass switch for providing a bypass path between a first terminal and a second terminal, the bypass switch comprising:a first contact device;
a second contact device; and
a plunger being moveable from an initial state, via a first state, to a second state, wherein in the initial state the first terminal and second terminal are conductively separated; in the first state a movement of the plunger causes the first contact device to close a first conductive connection between the first terminal and the second terminal; and in the second state the plunger mechanically forces the second contact device to close a second conductive connection between the first terminal and the second terminal, AND
wherein the plunger comprises a front section and a back section, wherein the front section is detachably connected to the back section, and wherein, in the first state, it is the back section which causes the first contact device to close the first conductive connection.

US Pat. No. 10,192,702

ELECTROMAGNETIC RELAY AND RELAY DEVICE

PANASONIC INTELLECTUAL PR...

1. An electromagnetic relay, comprising:a contact point including a fixed contact and a movable contact;
a driver including a coil and is configured to bring the movable contact into contact with the fixed contact and to separate the movable contact from the fixed contact;
a base having an opening and including a first wall section surrounding an accommodation space in which the contact point and the driver are accommodated;
a cover covering the opening of the base; and
at least one connection terminal configured to electrically connect the coil to an external connection body, wherein
the first wall section of the base has a through hole communicating with an interior and an exterior of the accommodation space,
the at least one connection terminal includes:
a first terminal section accommodated in the base and electrically connected to the coil; and
a second terminal section protruding outside the base through the through hole and electrically connected to the external connection body,
the cover includes a second wall section disposed to leave a space from the first wall section having the through hole, and the second terminal section lies in the space, and
the space in which the second terminal section lies is sealed with a sealant.

US Pat. No. 10,192,701

SWITCH ACTUATION APPARATUS AND METHOD

GM Global Technology Oper...

1. An actuation apparatus comprising:a steering wheel armature including a base member;
wherein a module includes an air bag assembly;
the base member having a base defining a base axis and a base face;
wherein the steering wheel armature is rotatable about a rotation axis;
wherein the rotation axis and the base axis are non-coincident;
a plurality of base magnetic elements mounted to the base face and distributed around the base axis;
the module having a module face; and
a plurality of module magnetic elements mounted to the module face;
wherein the module is movably tethered to the base member;
wherein each of the base magnetic elements is aligned with a respective one of the module magnetic elements to form a paired magnet set such that the plurality of module magnetic elements and the plurality of base magnetic elements form a plurality of paired magnet sets; and
wherein the base magnetic element and the module magnetic element of each paired magnet set are oriented such that a repulsive magnetic force is generated between the base magnetic element and the module magnetic element of each paired magnetic set.

US Pat. No. 10,192,700

AIR CIRCUIT BREAKER HAVING AN IMPROVED ELECTRIC ARC QUENCHING CHAMBER

SCHNEIDER ELECTRIC INDUST...

1. An air circuit breaker, comprising:two separable electrical contacts connected to electric current input and output terminals; and
a chamber for quenching an electric arc, to extinguish the electric arc formed during the separation of the electrical contacts, said quenching chamber comprising a stack of splitter plates that are spaced apart from one another, and lateral walls placed on either side of the stack, the splitter plates being fixed to the lateral walls, each lateral wall including a thermosetting-resin impregnated polyamide fabric and being devoid of glass fibres,
wherein the quenching chamber furthermore includes protective elements made of crosslinked polyamide, said protective elements being placed inside the quenching chamber, along the lateral walls on either side of the stack, in junction zones between the lateral walls and the splitter plates, the protective elements covering corners of the splitter plates which corners are adjacent to the lateral walls, so as to separate these corners of the splitter plates from the electrical contacts, and
wherein each protective element comprises seats and a plurality of fingers, the seats being bounded by the fingers, one corner of the splitter plate of the stack being received inside each seat, and each pair of fingers in the plurality of fingers having one of the splitter plates disposed therebetween,
wherein the protective elements extend substantially parallel to the stack, from a lower end of the stack to a lower edge of an upper arcing horn situated above the stack, such that are there splitter plates included in the stack of splitter plates which are not covered by the protective elements.

US Pat. No. 10,192,699

POWER SEAT OPERATION DEVICE AND POWER SEAT

NHK Spring Co., Ltd., Yo...

1. A power seat operation device comprising:a dial that is rotatably installed at a side face of a power seat provided with a plurality of moving mechanisms, one of the plurality of moving mechanisms being selected by rotational operation of the dial, and an interior and an exterior of the dial being in communication through an opening formed at a peripheral outer side of the dial;
a switch that is attached inside the dial, the switch actuating the selected moving mechanism;
a knob that is installed inside the dial at a seat width direction outer side of the switch, that is rotatably supported by the dial, that includes an operation portion inserted through the opening so as to project outside the dial, and that is capable of operating the switch by operation of the operation portion; and
a channel that is formed inside the dial by the dial and the knob, the channel being partitioned from the switch, and, in cases in which liquid has infiltrated into the dial through the opening in a state in which the opening is positioned at an upper side of the switch, the channel letting the liquid flow downward to a lower side of the switch so as to discharge the liquid to outside the dial.

US Pat. No. 10,192,696

LIGHT-EMITTING ASSEMBLY FOR KEYBOARD

APPLE INC., Cupertino, C...

1. A keyboard assembly, comprising:a switch housing defining a switch opening and a light source recess formed in a sidewall of the switch opening;
a tactile dome positioned at least partially within the switch opening;
a keycap positioned above the switch housing and configured to move toward the tactile dome when pressed; and
a light-emitting assembly positioned within the light source recess of the switch housing, and comprising:
a light source;
a luminescent structure at least partially enclosing the light source and defining a front face of the light-emitting assembly;
an opaque material defining a rear face of the light-emitting assembly, the rear face being positioned opposite the front face;
a first sidewall defining a first side face of the light-emitting assembly; and
a second sidewall opposite the first sidewall and defining a second side face of the light-emitting assembly, wherein the switch housing is configured to receive light from each of the front face, the first side face, and the second side face and to guide the received light toward the keycap, wherein the opaque material is configured to prevent light from passing through it.

US Pat. No. 10,192,692

EXPLOSION-PROOF CROSS-TYPE LIMIT SWITCH

1. An explosion-proof limit switch (10) comprising:a housing (12);
a gear mechanism (24) arranged in said housing (12), said gear mechanism including a gear mechanism cover plate (38), a gear mechanism base plate (48) and at least one intermediate plate (42) arranged between the gear mechanism cover plate (38) and the gear mechanism base plate (48);
said intermediate plate (42) having at least one cutout (44) in which a first gearwheel (54) is arranged and at least one second cutout (46) in which a second gearwheel (58) is arranged;
said first gearwheel (54) having a first plug-through opening (56) and said second gearwheel (58) having a second plug-through opening (60);
a shaft (20) having an actuating lever (18) arranged outside the housing (12) and being rotatably supported in a first bearing arrangement (22) connected to the housing (12) and extending through the first plug-through opening (56) of the first gearwheel (54) in order to couple with the first gearwheel (54) in a torque transmitting manner and to radially support said first gearwheel (54); and
a rotary switch (30) arranged in the housing (12) and having a switch shaft (138) that is rotatably supported in a second bearing arrangement (106, 134) and extends through the second plug-through opening (60) of the second gearwheel (58) in order to couple with the second gearwheel (58) in a torque transmitting manner and to radially support said second gearwheel (58).

US Pat. No. 10,192,691

ELECTRICITY STORAGE UNIT

Panasonic Intellectual Pr...

1. An electricity storage unit comprising:an electricity storage device;
a holder for holding the electricity storage device;
a control board that is formed with a wiring electrically connected with the electricity storage device;
a case having a tubular side wall part and a bottom surface part closing one end of the side wall part, the case being formed with an opening at another end of the side wall part; and
a cover for covering the opening, wherein:
the electricity storage device, the holder, and the control board are housed inside the case,
the holder is fixed to the control board, and
a rear end of the holder is supported inside the case by abutting the rear end to an inner surface of the bottom surface part, the rear end facing the bottom surface part.

US Pat. No. 10,192,690

TITANIUM OXIDE-BASED SUPERCAPACITOR ELECTRODE MATERIAL AND METHOD OF MANUFACTURING SAME

SHANGHAI INSTITUTE OF CER...

1. A titanium oxide-based supercapacitor electrode material, comprising a conductive titanium oxide as an active substance, wherein the conductive titanium oxide is selected from the group consisting of titanium sub-oxide, reduced titanium dioxide, and doped reduced titanium dioxide, a whole or a surface of the titanium sub-oxide, the reduced titanium dioxide, or the doped reduced titanium dioxide having amorphous layers comprising defect structures and activated Ti3+; and the titanium oxide-based supercapacitor electrode material has a density of charge carrier higher than 1018 cm?3, and a specific capacitance in a range of 20 F/g˜1,740 F/g, under a charge-discharge current of 1 A/g; and the titanium sub-oxide, the reduced titanium dioxide, or the doped reduced titanium dioxide is prepared by a step of performing a high surface reduction treatment on titanium dioxide to obtain the titanium sub-oxide or the reduced titanium dioxide, or by a step of performing the high surface reduction treatment and a doping treatment on titanium dioxide to obtain the doped reduced titanium dioxide; wherein the high surface reduction treatment is performed at 200˜500° C. for 2˜12 hours.

US Pat. No. 10,192,689

SELF-ASSEMBLY OF PEROVSKITE FOR FABRICATION OF TRANSPARENT DEVICES

YISSUM RESEARCH DEVELOPME...

1. A patterned perovskite material, comprising a plurality of continuous intersecting perovskite line patterns, defining confined regions enclosed by walls of said intersecting line patterns, wherein the confined regions are perovskite-free voids.

US Pat. No. 10,192,686

MULTILAYER ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer electronic component comprising:a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, one ends of the first and second internal electrodes being exposed through the third and fourth surfaces, respectively;
first and second external electrodes including, respectively, first and second band portions disposed on the first surface of the capacitor body to be spaced apart from each other and first and second connected portions, respectively extending from the first and second band portions to the third and fourth surfaces of the capacitor body;
first and second connection terminals formed of insulators and disposed on the first and second band portions, respectively; and
first and second insulating portions disposed on at least some circumferential surfaces of the first and second connection terminals, respectively,
wherein the first connection terminal includes a first conductive pattern formed on a surface thereof facing the first band portion, a second conductive pattern formed on a surface thereof opposing the surface on which the first conductive pattern is formed, a first cut portion formed in some circumferential surfaces thereof connecting the first and second conductive patterns to each other, and a first connection pattern formed on the first cut portion to electrically connect the first and second conductive patterns to each other, and
the second connection terminal includes a third conductive pattern formed on a surface thereof facing the second band portion, a fourth conductive pattern formed on a surface thereof opposing the surface on which the third conductive pattern is formed, a second cut portion formed in some circumferential surfaces thereof connecting the third and fourth conductive patterns to each other, and a second connection pattern formed on the second cut portion to electrically connect the third and fourth conductive patterns to each other.

US Pat. No. 10,192,685

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body including a plurality of first and second internal electrodes alternately disposed therein and a dielectric layer interposed therebetween, the capacitor body having a first surface and a second surface opposing each other, a third surface and a fourth surface opposing each other and connected to the first and second surfaces, and a fifth surface and a sixth surface opposing each other and connected to the first to fourth surfaces;
a plurality of external electrodes connected to the plurality of first and second internal electrodes;
an insulating layer disposed on the first surface of the capacitor body;
a first terminal electrode and a second terminal electrode disposed on the insulating layer and spaced apart from each other in a direction in which the third and fourth surfaces are connected to each other; and
a connecting member electrically connecting the first and second terminal electrodes and the plurality of external electrodes to each other.

US Pat. No. 10,192,684

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME MOUNTED THEREON

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body including dielectric layers and a plurality of first and second internal electrodes alternately disposed therein, having the dielectric layers interposed therebetween, and having a first surface and a second surface opposing each other in a first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposing each other in a second direction, and a fifth surface and a sixth surface connected to the first surface and the second surface, connected to the third surface and the fourth surface, and opposing each other in a third direction, the plurality of first and second internal electrodes being exposed through at least the third surface and the fourth surface, respectively;
a first external electrode and a second external electrode including first and second connection portions disposed on the third surface and the fourth surface of the capacitor body and electrically connected to exposed portions of the plurality of first and second internal electrodes, and first and second band portions extending from the first and second connection portions to portions of the first surface and the second surface of the capacitor body and to portions of the fifth surface and the sixth surface of the capacitor body, respectively;
a first conductive resin layer including a first portion covering a portion of the first band portion and disposed on the first surface of the capacitor body, and a second portion extending from the first surface onto one of the surfaces of the capacitor body other than the first surface;
a second conductive resin layer including a third portion covering a portion of the second band portion and disposed on the first surface of the capacitor body, and a fourth portion extending from the first surface onto one of the surfaces of the capacitor body other than the first surface;
an insulating layer disposed on the first surface of the capacitor body; and
a first terminal electrode and a second terminal electrode disposed to be spaced apart from each other in the second direction, covering portions of the insulating layer disposed on the first surface of the capacitor body, and connected to the first and second external electrodes, respectively.

US Pat. No. 10,192,683

MULTILAYER CAPACITOR AND BOARD HAVING THE MULTILAYER CAPACITOR MOUNTED THEREON

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor, comprising:a capacitor body including dielectric layers and a plurality of first internal electrodes and second internal electrodes, the plurality of first internal electrodes and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, the capacitor body further having a first surface and a second surface opposing each other, a third surface and a fourth surface each connected to each of the first surface and the second surface and the third surface and the fourth surface opposing each other, and a fifth surface and a sixth surface each connected to each of the first surface and the second surface, each of the fifth surface and the sixth surface connected to each of the third surface and the fourth surface, and the fifth surface and the sixth surface opposing each other, the first internal electrodes and the second internal electrodes being exposed through at least the third surface and the fourth surface, respectively;
an insulating layer disposed on the first surface of the capacitor body;
a buffer layer at least partially covering the insulating layer;
a first terminal electrode and a second terminal electrode extended from the third surface and the fourth surface of the capacitor body to the buffer layer, respectively, and spaced apart from each other; and
a first external electrode and a second external electrode disposed on the third surface and the fourth surface of the capacitor body, respectively, so that on a same side of the capacitor body at least a portion of at least one of the insulating layer or the buffer layer is arranged between at least one of the first external electrode or the second external electrode and at least one of the first terminal electrode or the second terminal electrode, respectively.

US Pat. No. 10,192,682

COMPOSITE ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A composite electronic component comprising:a multilayer capacitor;
an electrostatic discharge (ESD) protecting element; and
first to fourth conductive resin layers,
wherein the multilayer capacitor includes:
a capacitor body including dielectric layers and a plurality of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, each of the first internal electrodes extending from the third surface to the fourth surface and being exposed through the third and fourth surfaces, and each of the second internal electrodes extending from the fifth surface to the sixth surface and being exposed through the fifth and sixth surfaces;
first and second external electrodes extending from the third and fourth surfaces of the capacitor body to portions of the first surface of the capacitor body, respectively, and connected to exposed portions of the first internal electrodes; and
third and fourth external electrodes extending from the fifth and sixth surfaces of the capacitor body to portions of the first surface of the capacitor body, respectively, and connected to exposed portions of the second internal electrodes,
the ESD protecting element includes:
first and second lead electrodes disposed on the first surface of the capacitor body to be connected to the first and second external electrodes, respectively;
a third lead electrode disposed on the first surface of the capacitor body to connect the third and fourth external electrodes to each other, the first and second lead electrodes being spaced apart from the third lead electrode;
a discharge portion disposed on the first surface of the capacitor body and covering the first to third lead electrodes; and
a protective layer disposed to cover the discharge portion, and
the first to fourth conductive resin layers are formed on the first to fourth external electrodes, respectively, and extend to portions of a first surface of the protective layer, respectively.

US Pat. No. 10,192,679

METHOD OF MANUFACTURING RARE EARTH MAGNET

TOYOTA JIDOSHA KABUSHIKI ...

1. A method of manufacturing a rare earth magnet comprising:preparing a powder by preparing a rapidly-solidified ribbon by liquid solidification, and by crushing the rapidly-solidified ribbon to obtain a crushed powder, the rapidly-solidified ribbon being a plurality of fine crystal grains, the powder including a RE-Fe—B main phase and a grain boundary phase of a RE-X alloy present around the main phase, RE representing at least one of Nd and Pr, and X representing a metal element;
manufacturing a sintered compact including by press-forming the powder; and
manufacturing a rare earth magnet by performing hot deformation processing on the sintered compact to impart anisotropy to the sintered compact, wherein
a nitrogen content in the powder is adjusted to be at least 1,000 ppm and less than 3,000 ppm by performing at least one of the preparation of the powder and the manufacturing of the sintered compact in a nitrogen atmosphere,
wherein a grain size of the crushed powder is adjusted to be in a range of 75 ?m to 300 ?m,
an average grain size of the main phase constituting the sintered compact is adjusted to be 300 nm or less, and
a content ratio of RE in the RE-Fe—B main phase is 29 mass % to 32 mass %.

US Pat. No. 10,192,674

COIL COMPONENT HAVING TERMINAL ELECTRODES WITH HIGH MOUNTING STRENGTH, AND ELECTRONIC DEVICE INCLUDING THE COIL COMPONENT

TAIYO YUDEN CO., LTD., T...

1. A coil component comprising an air-core coil embedded in a magnetic body constituted by resin and metal magnetic grains, and having terminal electrodes electrically connected to both ends of the coil, wherein:both ends of the coil are exposed on a surface of the magnetic body;
the terminal electrodes are formed across the surface of the magnetic body and ends of the coil, and constituted by an underlying layer formed with metal material and a cover layer placed on an outer side of the underlying layer; and
the underlying layer is in contact with the resin and metal parts of the metal magnetic grains where the underlying layer is in contact with the magnetic body,
wherein a magnetic body surface on a side where either terminal electrode is connected to the end of the coil contains less resin than a magnetic body surface on a side where no terminal electrode is connected to the end of the coil.

US Pat. No. 10,192,673

INDUCTOR

SAMSUNG ELECTRO-MECHANICS...

1. An inductor comprising:a body comprising a magnetic material and having an upper surface, a lower surface, and side surfaces connecting the upper surface and the lower surface; and
a coil part disposed in the body and including a support member comprising an insulating resin, the coil part comprising first and second coil patterns respectively formed on an upper surface and a lower surface of the support member, wherein
1.15?b/a?1.45, where a is a length from a central plane between the upper surface and the lower surface of the support member to an upper surface of the body, and b is a length from the central plane of the support member to the lower surface of the body.

US Pat. No. 10,192,672

COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A coil component, comprising:a substrate; and
a coil pattern disposed on the substrate,
wherein the coil pattern includes a vertical region having a side surface perpendicular with respect to the substrate and a tapered region connected to the vertical region and having a side surface inclined with respect to the substrate,
in a cross section of the coil pattern, a minimum width of the tapered region is less than a minimum width of upper and lower surfaces of the coil pattern,
the vertical region and the tapered region form a trapezoidal shape and are made of the same material, and
wherein a spacing between coil pattern turns is between 0.15 and 0.45 times a width of a cross sectional shape of the coil pattern.

US Pat. No. 10,192,671

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component, comprising:a multilayer body including a plurality of insulator layers stacked together;
a plurality of inner conductors including at least a first inner conductor, a second inner conductor, a third inner conductor and a fourth inner conductor formed between the insulator layers and extended to a side surface of the multilayer body; and
a plurality of outer electrodes formed on both side surfaces of the multilayer body, the outer electrodes including at least a first outer electrode connected to the first inner conductor, a second outer electrode connected to the second inner conductor, a third outer electrode connected to the third inner conductor and a fourth outer electrode connected to the fourth inner conductor,
wherein each of the outer electrodes is formed on a single side surface so as not to extend over two side surfaces of the multilayer body, and
wherein the first outer electrodes and the second outer electrode are facing each other, and the first outer electrode and the second outer electrode differ in length in a direction in which the insulator layers are stacked.

US Pat. No. 10,192,668

COIL COMPONENT

Murata Manufacturing Co.,...

1. A coil component comprising:a drum-shaped core including a winding core portion and first and second flange portions provided at respective end portions of the winding core portion along a predetermined direction that is a length direction of the winding core portion;
each of the first and second flange portions having an inner end surface that faces a side of the winding core portion and positions the corresponding end portion of the winding core portion, an outer end surface that faces an outer side opposite to the inner end surface, a bottom surface that couples the inner end surface with the outer end surface and faces a side of a mount substrate at mounting, and a top surface opposite to the bottom surface;
a plate-shaped core bridged between the first and second flange portions while one principal surface of the plate-shaped core contacts the top surface of each of the first and second flange portions;
at least one first terminal electrode provided on the bottom surface of the first flange portion;
at least one second terminal electrode provided on the bottom surface of the second flange portion; and
at least one wire wound around the winding core portion and connected between the first and second terminal electrodes,
wherein, for dimensions measured along the predetermined direction, a dimension of each of the top surfaces of the first and second flange portions is equal to or larger than a dimension of the winding core portion.

US Pat. No. 10,192,667

ENCLOSURE SYSTEM AND METHOD FOR FACILITATING INSTALLATION OF ELECTRICAL EQUIPMENT

Hubbell Incorporated, Sh...

8. A method for installing a transformer:providing an enclosure for electrical equipment, the enclosure including a frame;
coupling a first member to the frame;
coupling the transformer to a first plate;
placing the first plate into the enclosure such that it is at least partially supported by the first member; and
fastening the first plate to the frame by manipulating a fastener that is coupled to the first plate and received through a hole in the frame, wherein fastening the first plate to the frame lifts the first plate from the first member.

US Pat. No. 10,192,666

MAGNETIC DEVICE FOR LOCKING A GEAR SELECTOR LEVER OF A VEHICLE IN A PREDETERMINED POSITION, METHOD FOR PRODUCING A MAGNETIC DEVICE, AND METHOD FOR OPERATING A MAGNETIC DEVICE

ZF Friedrichshafen AG, F...

1. A magnetic device for locking a gear shift lever of a vehicle in a predetermined position, the magnetic device comprising:a coil;
a tie component, which is movably supported in the coil;
a spring disposed outside the coil, wherein the spring is designed to push at least a portion of the tie component out of the coil;
a switch element which is designed to interact with a positioning element and the tie component disposed on a movement track in order to detect a position of the magnetic device in the movement track.

US Pat. No. 10,192,664

EXCITING DEVICE FOR ELECTROMAGNETIC CONNECTION DEVICE

OGURA CLUTCH CO., LTD., ...

1. An exciting device for an electromagnetic connection device, comprising:a yoke including an annular groove and a first through hole formed in a bottom wall serving as a bottom of the annular groove;
an exciting coil stored in the annular groove;
a terminal housing including a convex portion fitted in the first through hole and a concave portion located on an opposite side of the annular groove with respect to the convex portion, the convex portion including a second through hole extending in a direction parallel to a center line of the first through hole; and
an external connecting terminal buried in the terminal housing in a state in which a portion of the external connecting terminal is exposed in the concave portion, the external connecting terminal including a coil extraction hole formed in the portion exposed in the concave portion and continuing to the second through hole, and the exciting coil including an extraction end soldered to the external connecting terminal in a state in which the extraction end is passed through the second through hole and the coil extraction hole.

US Pat. No. 10,192,663

COIL FOR A SWITCHING DEVICE WITH A HIGH-FREQUENCY POWER

1. A coil system comprising a coil and several windings,wherein a first winding of the coil provides a first winding diameter and a first winding spacing;
wherein a last winding of the coil provides a second winding diameter and a second winding spacing;
wherein the first winding diameter is larger than the second winding diameter;
wherein the first winding spacing is smaller than the second winding spacing;
wherein the coil system further comprises a coil former filling an interior cavity of the coil;
wherein the coil former provides four recesses extending along its longitudinal axis, separated by webs, which are 90° offset relative to one another with reference to the coil former;
wherein the coil former comprises synthetic material,
wherein the coil former provides a relative permittivity that is no greater than about 1.2;
wherein the windings of the coil are guided in a guide groove of the coil former; and
wherein a wire thickness of the coil is larger than a depth of the guide groove.

US Pat. No. 10,192,662

METHOD FOR PRODUCING GRAIN-ORIENTED ELECTRICAL STEEL SHEET

JFE Steel Corporation, T...

1. A method for producing a grain-oriented electrical steel sheet by comprising a series of steps of hot rolling a raw steel material comprising C: 0.002-0.10 mass %, Si: 2.0-8.0 mass %, Mn: 0.005-1.0 mass % and the remainder being Fe and inevitable impurities to obtain a hot rolled sheet, subjecting the hot rolled steel sheet to a hot band annealing as required and further to one cold rolling or two or more cold rollings including an intermediate annealing therebetween to obtain a cold rolled sheet having a final sheet thickness, subjecting the cold rolled sheet to primary recrystallization annealing combined with decarburization annealing, applying an annealing separator to the steel sheet surface and then subjecting to final annealing, characterized in that rapid heating is performed at a rate of not less than 50° C./s in a region of 200-700° C. in the heating process of the primary recrystallization annealing, and the steel sheet is held at any temperature of 250-600° C. in the region of 200-700° C. for 1-5 seconds, while a soaking process of the primary recrystallization annealing is controlled to a temperature range of 750-900° C., a time of 90-180 seconds and PH2O/PH2 in an atmosphere of 0.25-0.40, where PH2O means a partial water vapor pressure of the atmosphere and PH2 means a partial hydrogen pressure of the atmosphere.

US Pat. No. 10,192,657

GROMMET AND WIRE HARNESS

Sumitomo Wiring Systems, ...

1. A grommet that is to be attached to a group of electrical wires and mounted to a vehicle body panel so as to block an opening in the vehicle body panel, the grommet comprising:a first cylindrical portion through which the group of electrical wires is inserted;
a second cylindrical portion that is formed shorter in an axial direction than the first cylindrical portion and surrounds the first cylindrical portion;
a seat portion that is constituted by an annular rubber elastic body that surrounds the second cylindrical portion and is capable of constriction in diameter, the seat portion having an annular unevenness portion capable of fitting around an edge portion of the opening in the vehicle body panel; and
an annular connection portion that elastically connects the first cylindrical portion and the seat portion,
wherein the seat portion has an approximately elliptical shape,
the connection portion has an inclined annular wall portion that forms an inclined annular surface that is inclined in the axial direction between the first cylindrical portion and the seat portion, the inclined annular wall portion supporting a base end portion of the second cylindrical portion, and
a plurality of rib portions are integrally provided on the inclined annular wall portion and the second cylindrical portion, the plurality of rib portions extending from an axially intermediate portion of the second cylindrical portion to the inclined annular wall portion on two sides in a major axis direction of the approximately elliptical shape, and projecting from the second cylindrical portion to a seat portion side.

US Pat. No. 10,192,653

TWISTED STRING-SHAPED ELECTRIC CABLE FOR UNDERWATER PURPOSE

Panasonic Intellectual Pr...

1. An electric cable comprising:at least one electric wire; and
a plurality of string-shaped bodies each extending in a longitudinal direction of the electric cable and twisting with one another around the at least one electric wire being a core, wherein the plurality of string-shaped bodies has a connection part twisting with one another excluding the at least one electric wire, and
wherein the connection part is connected to a frame of an underwater robot.

US Pat. No. 10,192,651

TRANSFER MATERIAL, METHOD OF MANUFACTURING TRANSFER MATERIAL, LAMINATED BODY, METHOD OF MANUFACTURING LAMINATED BODY, METHOD OF MANUFACTURING CAPACITANCE-TYPE INPUT DEVICE, AND METHOD OF MANUFACTURING IMAGE DISPLAY DEVICE

FUJIFILM CORPORATION, To...

1. A transfer material comprising, in this order, a temporary support body, a first resin layer, and a second resin layer,the first resin layer not being water soluble,
the second resin layer including a water soluble polymer,
the second resin layer including a compound that has a heteroaromatic ring including a nitrogen atom as a ring member, and
a content of the compound that has a heteroaromatic ring including a nitrogen atom as a ring member in the second resin layer being 3.0% by mass or greater with respect to a total solid content of the second resin layer.