US Pat. No. 10,714,471

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor device, comprising:forming a plurality of gate structures on a base structure, a source/drain region in the base structure on each side of each gate structure, and an interlayer dielectric layer on the base structure to cover sidewall surfaces of the gate structures, wherein the plurality of gate structures are separated by a plurality of isolation areas;
forming a first mask layer to cover the interlayer dielectric layer and the gate structures and a second mask layer to cover the first mask layer, wherein the second mask layer and the first mask layer are made of different materials;
forming a plurality of first patterned layers separated by a plurality of first openings on the second mask layer, wherein a projected pattern of the plurality of first patterned layers covers at least top surfaces of the gate structures, and each first opening is formed across a source region, a drain region, and a portion of an isolation area between the source region and the drain region;
forming a patterned second mask layer by etching the second mask layer using the plurality of first patterned layers as an etch mask until a portion of the first mask layer is exposed;
forming a plurality of second patterned layers on an exposed portion of first mask layer and a remaining portion of the second mask layer, wherein the plurality of second patterned layers are formed vertically above the isolation areas between neighboring source and drain regions;
forming a patterned first mask layer by etching the first mask layer using the plurality of second patterned layers as an etch mask until a portion of the interlayer dielectric layer is exposed;
forming a plurality of contact vias to expose top surfaces of source/drain regions by etching the interlayer dielectric layer using the patterned first mask layer and the patterned second mask layer as an etch mask; and
forming a plurality of metal silicide layers on the source/drain regions exposed in the plurality of contact vias.

US Pat. No. 10,714,469

ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE

Semiconductor Manufacturi...

1. An electrostatic discharge protection structure, comprising:a base substrate including a substrate and a fin portion on the substrate, wherein the substrate includes a first region and a second region;
a first doped layer on a surface of the fin portion in the first region; and
a second doped layer on a surface of the fin portion in the second region and on a surface of the substrate in the second region, wherein an aspect ratio of gaps between adjacent fin portions in the second region is smaller than an aspect ratio of gaps between adjacent fin portions in the first region; wherein:
the second doped layer is directly on and completely covers a top surface and side surfaces of the fin portion in the second region, and a top surface of the substrate in the second region.

US Pat. No. 10,714,468

OPTICAL INTEGRATED CIRCUIT SYSTEMS, DEVICES, AND METHODS OF FABRICATION

STMICROELECTRONICS S.R.L....

1. An optical integrated circuit device comprising:a semiconductor substrate;
a first waveguide made of a first material and disposed over the semiconductor substrate, the first waveguide comprising a parallel region and a tapered region;
a first cladding structure disposed over and surrounding the parallel region of the first waveguide;
a first extension made of the first material and disposed over the semiconductor substrate, the first extension physically contacting the parallel region of the first waveguide, wherein the first extension comprises a first portion within the first cladding structure and a second portion outside the first cladding structure; and
an electrostatic discharge (ESD) protection structure electrically coupled to the first extension.

US Pat. No. 10,714,467

INTEGRATED CIRCUIT (IC) DEVICE

Samsung Electronics Co., ...

1. An integrated circuit (IC) device comprising:a logic cell having an area defined by a cell boundary,
the logic cell including a first device region, a device isolation region, and a second device region,
the first device region and the second device region arranged apart from each other in a first direction that is perpendicular to a second direction,
the device isolation region being between the first device region and the second device region,
a first maximum length of the first device region in the second direction being less than a width of the cell boundary in the second direction, and
a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

US Pat. No. 10,714,466

LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY

UNITED MICROELECTRONICS C...

1. A layout pattern for magnetoresistive random access memory (MRAM), comprising:a first magnetic tunneling junction (MTJ) pattern on a substrate;
a second MTJ pattern adjacent to the first MTJ pattern; and
a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement, the first MTJ pattern comprises a circle while the first metal interconnection pattern comprises an ellipse, and the first MTJ pattern and the second MTJ pattern are on a same level.

US Pat. No. 10,714,464

METHOD OF SELECTIVELY TRANSFERRING LED DIE TO A BACKPLANE USING HEIGHT CONTROLLED BONDING STRUCTURES

GLO AB, Lund (SE)

1. A method of transferring devices to a target substrate, comprising:providing a supply coupon comprising a combination of a source substrate and devices thereupon;
providing a target substrate that includes bonding sites;
forming first bonding material portions on one of surfaces of the devices or surfaces of the bonding sites of the target substrate;
coining the first bonding material portions to form first bonding material pads having a flatter bonding surface than that of the first bonding material portions;
bonding a first set of the first bonding material pads with respective bonding structures to form a first set of bonded material portions, wherein the first set of the first bonding material pads is located on one of a first set of devices or the first set of bonding sites of the target substrate, and the bonding structures are located on another one of the first set of devices or the first set of the bonding sites of the target substrate, wherein the step of bonding the first set of the first bonding material pads with respective the first set of bonding structures comprises selectively reflowing the first set of the first bonding pads of the first set of devices without reflowing a second set of the first bonding material pads of the second set of devices, and wherein the selective reflowing is performed by irradiating a laser beam on the first set of the first bonding material pads; and
detaching the first set of devices from the source substrate, wherein the first set of the devices is bonded to the bonding sites of the target substrate by the first set of bonded material portions, while a remaining second set of devices remains on the source substrate.

US Pat. No. 10,714,462

MULTI-CHIP PACKAGE WITH OFFSET 3D STRUCTURE

Advanced Micro Devices, I...

1. A semiconductor chip device, comprising:a reconstituted semiconductor chip package including an interposer having a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by an inorganic dielectric layer on the metallization stack, plural interconnects positioned between and electrically connecting the first semiconductor chip and the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

US Pat. No. 10,714,461

ELECTRONIC UNIT

VISHAY SEMICONDUCTOR GMBH...

1. An electronic unit comprising:at least one first electronic component and one second electronic component that are fastened to a substrate; and
a shielding arranged between the first and second electronic components, wherein the shielding comprises an elevated portion that projects from a plane defined by the substrate or extends from a surface of the substrate, and wherein the shielding acts as a shielding and is formed in one piece with the substrate, and wherein at least one of the first electronic component and the second electronic component is electrically conductively connected, by a wire, to a contact point arranged at a base section of a third recess.

US Pat. No. 10,714,459

LIGHT EMITTING DEVICE WITH LED STACK FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME

Seoul Viosys Co., Ltd., ...

1. A light emitting device for a display, comprising:a first substrate;
a first LED sub-unit disposed under the first substrate;
a second LED sub-unit disposed under the first LED sub-unit;
a third LED sub-unit disposed under the second LED sub-unit;
a first transparent electrode interposed between the first and second LED sub-units, and in ohmic contact with a lower surface of the first LED sub-unit;
a second transparent electrode interposed between the second and third LED sub-units, and in ohmic contact with a lower surface of the second LED sub-unit;
a third transparent electrode interposed between the second transparent electrode and the third LED sub-unit, and in ohmic contact with an upper surface of the third LED sub-unit;
at least one current spreader connected to at least one of the first, second, and third LED sub-units;
electrode pads disposed on the first substrate; and
through-hole vias formed through the first substrate to electrically connect the electrode pads to the first, second, and third LED sub-units,
wherein at least one of the through-hole vias is formed through the first substrate, the first LED sub-unit, and the second LED sub-unit.

US Pat. No. 10,714,455

INTEGRATED CIRCUIT PACKAGE ASSEMBLIES INCLUDING A CHIP RECESS

Intel IP Corporation, Sa...

1. A method of assembling an integrated circuit (IC) package, the method comprising:receiving an IC chip having a front side including a plurality of first metal features, and a back side separated from the front side by an initial chip z-thickness;
forming a molding compound around a perimeter of the IC chip, wherein forming the molding compound contacts a sidewall of the IC chip with the molding compound;
recessing the IC chip back side relative to a back side of the molding compound by removing a thickness of a semiconductor substrate with a process that exposes a sidewall of at least some of the molding compound that was in contact with a portion of the sidewall of the IC chip; and
stacking a component having a smaller area than that of the IC chip within a recess over the recessed back side of the IC chip and spaced apart from the sidewall of the molding compound.

US Pat. No. 10,714,454

STACK PACKAGING STRUCTURE FOR AN IMAGE SENSOR

Semiconductor Components ...

1. A semiconductor package comprising:a substrate;
a first semiconductor device coupled to a surface of the substrate, the first semiconductor device including an image signal processor (ISP) die;
a second semiconductor device coupled to the surface of the substrate;
an image sensor device coupled to the first semiconductor device and the second semiconductor device, the first semiconductor device being disposed between the surface of the substrate and the image sensor device;
a transparent member coupled to the image sensor device;
at least one bond wire connected to the image sensor device and the surface of the substrate;
an inner molding disposed between the surface of the substrate and the image sensor device, the first semiconductor device being encapsulated within the inner molding; and
an outer molding disposed on the surface of the substrate, the at least one bond wire being encapsulated within the outer molding, the outer molding being coupled to the transparent member.

US Pat. No. 10,714,452

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

UNITED MICROELECTRONICS C...

1. A package structure, comprising:a first die and a second die, both the first die and the second die comprise:
a first surface;
a second surface disposed opposite to the first surface; and
at least two sidewalls disposed between the first surface and the second surface; and
an underfill layer covering and directly contacting the first surface of the first die, the first surface of the second die and at least one sidewall of the first die, wherein at least one sidewall of the first die is and both two sidewalls of the second die are not covered by the underfill layer, wherein at least one sidewall of the underfill layer, the at least one sidewall of the first die which is not covered by the underfill layer and one of the two sidewalls of the second die which are not covered by the underfill layer are coplanar with each other along a first direction, and wherein the first direction is perpendicular to the first surface.

US Pat. No. 10,714,451

TILING STRUCTURE TYPE LIGHT APPARATUS FOR ORGANIC LIGHT EMITTING DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting diode (OLED) lighting apparatus of a tiling structure, comprising:a first flexible OLED panel in which a bezel area and a part of a light emitting area are bent;
a second flexible OLED panel in which a bezel area arranged adjacent to the bezel area of the first flexible OLED panel is bent;
a fastening member to couple the first and second flexible OLED panels; and
a light guide plate which is arranged on the fastening member and guides a light which is emitted from a bent side of the first flexible OLED panel upward.

US Pat. No. 10,714,450

METHOD OF BONDING TERMINAL OF SEMICONDUCTOR CHIP USING SOLDER BUMP AND SEMICONDUCTOR PACKAGE USING THE SAME

JMJ Korea Co., Ltd., Buc...

1. A method of bonding a terminal of a semiconductor chip using a solder bump, the method comprising:preparing a semiconductor chip with an aluminum (Al) pad terminal formed thereon (S-1);
forming the solder bump on the Al pad terminal through a primary solder (S-2);
attaching the solder bump and a metal structure to each other via a secondary solder with a higher melting point than a melting point of the primary solder (S-3), wherein the secondary solder is positioned between the solder bump and the metal structure;
performing a heat treatment in a state in which the solder bump and the secondary solder are attached to each other at a heat treatment temperature determined based on the melting point of the secondary solder (S-4); and
mixing the primary solder and the secondary solder that are melted during the heat treatment and converting a resulting mixture into a tertiary solder including only one solder layer having a re-melting point higher than the melting point of the primary solder (S-5),
wherein the forming the solder bump (S-2) comprises forming an intermetallic compound (IMC) on a portion of the solder bump adjacent to the Al pad terminal to be distributed by a predetermined region during formation of the solder bump,
wherein the IMC includes Al.

US Pat. No. 10,714,448

CHIP MODULE WITH POROUS BONDING LAYER AND STACKED STRUCTURE WITH POROUS BONDING LAYER

UNIMICRON TECHNOLOGY CORP...

1. A chip module, comprising:a chip body;
a bump disposed on the chip body; and
a first bonding layer wrapping around an entirety of a sidewall of the bump, wherein the first bonding layer is made of porous copper and the bump is made of porous-free copper.

US Pat. No. 10,714,447

ELECTRODE TERMINAL, SEMICONDUCTOR DEVICE, AND POWER CONVERSION APPARATUS

Mitsubishi Electric Corpo...

1. An electrode terminal, comprising:a body composed of a single length of wire and made of only a first metal material, wherein an elastic part is provided between one end of said body and an other end of said body; and
a first bonding part located on a flat surface of said one end of said body, said first bonding part composed of a second metal material other than said first metal material, the second metal material being clad directly to the first metal material with nothing in-between in cross-section, and being clad to the first metal material proximate to the first bonding part in cross-section,
said first bonding part being ultrasonically bonded directly to a first bonded member with nothing in-between in cross-section, the first bonded member being a bondable metal disposed directly on a semiconductor chip, wherein
said elastic part includes at least one of a notch and a plurality of discrete bends in the body, such that said elastic part produces a spring effect and thus is elastically deformable,
a surface, which is ultrasonically bonded to said first bonded member in said first bonding part, is provided with a groove or irregularities, and
said groove or said irregularities of said electrode terminal accommodate a protruding part provided in said first bonded member.

US Pat. No. 10,714,446

APPARATUS WITH MULTI-WAFER BASED DEVICE COMPRISING EMBEDDED ACTIVE AND/OR PASSIVE DEVICES AND METHOD FOR FORMING SUCH

Intel Corporation, Santa...

6. A method comprising:forming a substrate;
fabricating a first active device adjacent to the substrate;
forming a first set of one or more layers to interconnect with the first active device;
forming a second set of one or more layers;
fabricating a second active or passive device adjacent to the second set of one or more layers;
forming a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets;
dry etching a surface of the second wafer such that pads are exposed; and
forming solder bumps on the exposed pads.

US Pat. No. 10,714,445

THERMAL BONDING SHEET, THERMAL BONDING SHEET WITH DICING TAPE, BONDED BODY PRODUCTION METHOD, AND POWER SEMICONDUCTOR DEVICE

NITTO DENKO CORPORATION, ...

1. A thermal bonding sheet comprising a pre-sintering layer containing a mixture of copper particles and polypropylene carbonate.

US Pat. No. 10,714,444

ANISOTROPIC CONDUCTIVE FILM

DEXERIALS CORPORATION, T...

1. An anisotropic conductive film having a regular disposition region in which conductive particles are disposed regularly in an insulating resin binder,wherein the anisotropic conductive film is formed on a release film, and
a standard region including no sections with more than a prescribed number of consecutive omissions in conductive particles is present in the regular disposition region over a prescribed width in a short-side direction of the anisotropic conductive film and at least a prescribed length in a long-side direction of the anisotropic conductive film.

US Pat. No. 10,714,442

INTERCONNECT STRUCTURES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

9. An interconnect structure comprising:a contact pad on a top surface of a first substrate;
a first passivation layer on the top surface of the first substrate, the first passivation layer directly adjoining a first portion of a top surface of the contact pad;
a second passivation layer on the first passivation layer, the second passivation layer directly adjoining a second portion of the top surface of the contact pad;
a post-passivation interconnect (PPI) contacting a third portion of the top surface of the contact pad and extending along a top surface of the second passivation layer;
a third passivation layer directly adjoining a top surface of the PPI;
a connector on the top surface of the PPI, the third passivation layer directly adjoining a lower portion of the connector;
a molding compound disposed on a surface of the third passivation layer and having a concave top surface adjoining the connector, the concave top surface of the molding compound having an angle from 10 degrees to 60 degrees relative to a plane parallel with a major surface of the first substrate; and
a bond pad on a first surface of a second substrate, the bond pad being bonded to the connector, the bond pad having a second width, the connector having a first width at an adjoining top surface of the molding compound.

US Pat. No. 10,714,436

SYSTEMS AND METHODS FOR ACHIEVING UNIFORMITY ACROSS A REDISTRIBUTION LAYER

Lam Research Corporation,...

1. A method for fabricating a redistribution layer, the method comprising:depositing a dielectric layer on top of a pad located on a substrate;
creating at least one via within the dielectric layer, wherein the dielectric layer has at least two intermediate portions and the at least one via extending therebetween;
depositing a barrier and seed layer on top the dielectric layer, wherein said depositing forms a film on the at least one via and on top of the at least two intermediate portions;
providing a layer of photoresist on top of the film of the barrier and seed layer, wherein the photoresist layer extends into the at least one via;
patterning the photoresist layer over the at least one via, wherein the patterning exposes at least a portion of an upper surface of the barrier and seed layer adjacent to the at least one via;
overfilling the redistribution layer within the at least one via and laterally extending the redistribution layer on top of the exposed upper surface of the barrier and seed layer, wherein said overfilling defines a localized bump over the at least one via and the redistribution layer has a height that is less than a height of the patterned photoresist layer; and
selectively removing the localized bump of the redistribution layer, wherein the localized bump is selectively removed while the height of the patterned photoresist layer is maintained.

US Pat. No. 10,714,432

LAYOUT TO REDUCE NOISE IN SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:an isolation structure disposed in a semiconductor substrate, wherein an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate;
a gate disposed over the device region, wherein an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure;
a first source/drain region disposed in the device region and on a first side of the gate;
a second source/drain region disposed in the device region and on a second side of the gate opposite the first side; and
a silicide blocking structure partially covering the gate, partially covering the first source/drain region, and partially covering the isolation structure, wherein a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

US Pat. No. 10,714,431

SEMICONDUCTOR PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING

UTAC Headquarters Pte. Lt...

1. A method for forming a semiconductor package, comprising:providing a base carrier defined with an active region and a non-active region, the base carrier has first and second major surfaces;
forming a fan-out redistribution structure over the first major surface of the base carrier;
mounting a die having first and second major surfaces onto the base carrier over the fan-out redistribution structure after formation of the fan-out redistribution structure, the first major surface of the die is an active surface of the die and the second major surface of the die is an inactive surface of the die, wherein the die comprises elongated die contacts protruding from the active surface of the die, the die contacts corresponding to conductive pillars, wherein the die contacts are in electrical communication with the fan-out redistribution structure;
forming an encapsulant having a first major surface and a second major surface opposite to the first major surface, wherein the first major surface is proximate to the inactive surface of the die, wherein the encapsulant surrounds the die contacts and sidewalls of the die; and
forming an electromagnetic interference (EMI) shielding layer, wherein the EMI shielding layer lines the first major surface and sides of the encapsulant.

US Pat. No. 10,714,430

EMI SHIELD FOR MOLDED PACKAGES

OCTAVO SYSTEMS LLC, Suga...

1. A packaged integrated circuit device encapsulated using liquid encapsulant during packaging, the packaged integrated circuit device comprising:a substrate;
a radiation-generating component disposed on the substrate; and
an electromagnetic radiation blocking element comprising (i) one or more openings and (ii) a flap disposed over at least one of said one or more openings, wherein
the electromagnetic radiation blocking element is mounted over the radiation-generating component, and
a space between the electromagnetic radiation blocking element and the radiation-generating component is filled with the liquid encapsulant during the packaging,
wherein the radiation-generating component is connected to one or more components disposed on the substrate via at least one of said one or more openings.

US Pat. No. 10,714,429

CIRCUIT SYSTEMS

Snap Inc., Santa Monica,...

1. A circuit board system comprising:a first circuit board comprising a substrate and a first component susceptible to electromagnetic interference carried by the substrate;
a second circuit board comprising a second substrate; and
a shield engaged to the substrate of the first component, the shield substantially completely encapsulating the first component to insulate the first component from electromagnetic interference, wherein the shield couples the substrate of the first circuit board to the substrate of the second circuit board.

US Pat. No. 10,714,428

SEMICONDUCTOR POWER DEVICE AND A METHOD OF ASSEMBLING A SEMICONDUCTOR POWER DEVICE

1. A method of assembling a power semiconductor device, the method comprising:obtaining a first substrate including a switching semiconductor element, the first substrate having a first surface and locally including first electrically conductive layers and a first receiving element, the switching semiconductor element being provided on the first surface;
obtaining a second substrate including a second surface facing the first surface, the second substrate including a second receiving element and locally including second electrically conductive layers;
obtaining an alignment interconnect element;
providing the alignment interconnect element to one of the first receiving element and the second receiving element to effect a partial reception of the alignment interconnect element by the receiving element; and
providing the alignment interconnect element to another one of the first receiving element and the second receiving element to effect a partial reception of the alignment interconnect element by the receiving element;
wherein the method further comprises:
obtaining data describing a required positioning of the first substrate with respect to the second substrate,
measuring characteristics of the first receiving element and of the second receiving element; and
determining characteristics of the alignment interconnect element based on of the obtained data and the measured characteristics,
wherein obtaining the alignment interconnect element comprises obtaining the alignment interconnect element on basis of the determined characteristics,
and wherein the receiving elements are holes or recesses and measuring the characteristics of the first receiving element and of the second receiving element comprises at least one of determining a radius of the receiving element and determining a depth of the receiving element.

US Pat. No. 10,714,427

SECURE CHIPS WITH SERIAL NUMBERS

ASML Netherlands B.V., V...

1. An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip:wherein the semiconductor chip is a member of a set of semiconductor chips, wherein the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets;
wherein the plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset are different from the non-common structures of the semiconductor chips in every other subset;
wherein at least a first portion of the non-common structures is adapted to store or generate a first predetermined value;
wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.

US Pat. No. 10,714,425

FLEXIBLE SYSTEM INTEGRATION TO IMPROVE THERMAL PROPERTIES

Apple Inc., Cupertino, C...

1. An apparatus comprising:an interposer;
a plurality of integrated circuits attached to a surface of the interposer, wherein:
a subset of the plurality of integrated circuits are processors;
the processors are distributed over the surface of the interposer; and
other ones of the plurality of integrated circuits that are not processors are arranged between the processors, distributing a power consumption density of the plurality of integrated circuits over the surface;
a phase change material in contact with the plurality of integrated circuits and the interposer, wherein the phase change material absorbs heat by melting and releases heat by solidifying during operation of the apparatus; and
a battery in contact with the phase change material, wherein the battery includes one or more openings through which the phase change material extends to conduct heat away from the plurality of integrated circuits.

US Pat. No. 10,714,423

THROUGH VIA STRUCTURE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:forming an opening extending through an interlayer dielectric layer over a substrate and partially through the substrate;
depositing a photoresist layer over the opening, wherein the photoresist layer partially fills the opening;
patterning the photoresist layer to remove the photoresist layer in the opening and form a metal line opening over the interlayer dielectric layer;
filling the opening and the metal line opening with a conductive material to form a via and a metal line, wherein an upper portion of the opening is free of the conductive material; and
depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the opening.

US Pat. No. 10,714,421

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONDUCTIVE FEATURES

Taiwan Semiconductor Manu...

16. A semiconductor device structure, comprising:a substrate;
a first conductive feature over the substrate;
a second conductive feature above the first conductive feature, wherein the second conductive feature has an upper portion and a protruding portion, the protruding portion is below the upper portion and extends towards the first conductive feature, and a bottom of the upper portion is wider than a top of the upper portion and is wider than a top of the protruding portion; and
a dielectric layer surrounding the first conductive feature and the second conductive feature; and
a closed hole in the dielectric layer.

US Pat. No. 10,714,418

ELECTRONIC DEVICE HAVING INVERTED LEAD PINS

TEXAS INSTRUMENTS INCORPO...

1. An electronic device, comprising:a package having a longitudinal center line, a mounting portion on one side of the longitudinal center line and a non-mounting portion on an opposite side of the longitudinal center line;
a low voltage die attach pad embedded in a non-mounting portion of the package, the low voltage die attach pad having a first side facing toward the longitudinal center line and a second side facing away from the longitudinal center line;
a low voltage die attached to the first side of the low voltage die attach pad;
a plurality of low voltage lead pins extending from the package in a direction toward the mounting portion and away from the non-mounting portion of the package;
a high voltage die attach pad embedded in the non-mounting portion of the package, the high voltage die attach pad having a first side facing toward the longitudinal center line and a second side facing away from the longitudinal center line;
a high voltage die attached to the first side of the high voltage die attach pad; and
a plurality of high voltage lead pins extending from the package in the direction toward the mounting portion and away from the non-mounting portion of the package.

US Pat. No. 10,714,417

SEMICONDUCTOR DEVICE WITH ELECTROPLATED DIE ATTACH

TEXAS INSTRUMENTS INCORPO...

1. A method of semiconductor die attachment, comprising:providing a dielectric cover having a first repeating pattern of recesses and a metal substrate including a second repeating pattern having positions matching the first repeating pattern including center through-hole apertures having an outer ring that position match the recesses and a plurality of raised traces around the through-hole apertures comprising a metal layer on a dielectric base layer on the metal substrate;
inserting a semiconductor die having a back side metal (BSM) layer top side up into respective ones of the plurality of apertures to sit on the outer ring;
placing the dielectric cover over the semiconductor die to form a plurality of stacks;
sealing along a periphery between the dielectric cover and the metal substrate;
immersing the stacks in a metal electroplating solution within a solution container, with the metal substrate connected to a negative terminal of a power supply and an electrically conductive structure spaced apart from the metal substrate connected to a positive terminal of the power supply, and
electroplating to deposit an electroplated single metal layer to fill a volume between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment.

US Pat. No. 10,714,416

SEMICONDUCTOR PACKAGE HAVING A CIRCUIT PATTERN

SAMSUNG ELECTRONICS CO., ...

1. A printed circuit board comprising:a base layer having a first surface;
a first conductive pattern disposed on the first surface; and
a first insulation layer disposed on the first conductive pattern, the first insulation layer including first protrusions and a second protrusion, wherein the first protrusions protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the first conductive pattern and form a mesh structure, and the second protrusion protrudes from the bottom surface of the first insulation layer and penetrates the at least the portion of the first conductive pattern,
wherein the second protrusion is spaced apart from the first protrusions, and the second protrusion is formed within a first coefficient of thermal expansion (CTE) adjusting region.

US Pat. No. 10,714,415

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a wiring substrate including:
a first insulating layer having a first surface, a second surface opposite to the first surface, and a first through hole filled with a first through hole via,
a first wiring formed on the first surface of the first insulating layer,
a second wiring formed on the second surface of the first insulating layer, and electrically connected with the first wiring via the first through hole via,
a second insulating layer having a second through hole filled with a second through hole via, and formed on the first surface of the first insulating layer so as to cover the first wiring,
a third wiring formed on the second insulating layer, and electrically connected with the first wiring via the second through hole via,
a third insulating layer having a third through hole filled with a third through hole via, and formed on the second surface of the first insulating layer so as to cover the second wiring, and
a fourth wiring formed on the third insulating layer, and electrically connected with the second wiring via the third through hole via,
a semiconductor component mounted over the second insulating layer of on the wiring substrate; and
an external connection terminal formed over the third insulating layer of the wiring substrate,
wherein each of the first insulating layer, the second insulating layer, and the third insulating layer is a build-up substrate,
wherein a diameter of each of the first through hole, the second through hole, and the third through hole is equal to or less than 100 ?m, and
wherein each of the first insulating layer, the second insulating layer and the third insulating layer contains a glass cloth.

US Pat. No. 10,714,411

INTERCONNECTED INTEGRATED CIRCUIT (IC) CHIP STRUCTURE AND PACKAGING AND METHOD OF FORMING SAME

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a packaging substrate including a top surface and a bottom surface;
a first bond pad array on the top surface of the packaging substrate, the first bond pad array including:
a set of operable bond pads, and
a set of structural support bond pads adjacent to the set of operable bond pads,
wherein the structural support bond pads are electrical opens;
a second bond pad array on the bottom surface of the packaging substrate, the second bond pad array including:
a set of operable bond pads, and
a set of structural bond pads adjacent to the set of operable bond pads;
an interconnected chip structure including an operable region having a first device connected to the set of operable bond pads of the first bond pad array, and an inoperable region coupled to the set of operable bond pads of the second bond pad array, wherein the operable region includes a first crack stop structure surrounding the first device, and wherein a connector wire extending through an opening of the first crack stop structure electrically couples the operable region to the inoperable region; and
an interconnect structure positioned within the packaging substrate, wherein the interconnect structure electrically connects the set of operable bond pads of the first bond pad array to the set of operable bond pads of the second bond pad array.

US Pat. No. 10,714,408

SEMICONDUCTOR DEVICES AND METHODS OF MAKING SEMICONDUCTOR DEVICES

AMKOR TECHNOLOGY, INC., ...

1. An electronic package comprising:a substrate comprising an upper substrate side, and a substrate pad on the upper substrate side;
an electronic component comprising an upper component side and a lower component side, the lower component side coupled to the upper substrate side;
a wire comprising an upper wire end and a lower wire end, the lower wire end coupled to the substrate pad; and
a package body enclosing the wire and the electronic component, the package body comprising a lower package body side facing the substrate and an upper package body side facing away from the substrate, the upper package body side comprising a cavity that exposes the upper wire end from the package body.

US Pat. No. 10,714,407

AMPLIFICATION APPARATUS

TOKYO KEIKI INC., Tokyo ...

1. An amplification apparatus, comprising:a signal splitter for splitting an input radio frequency signal and outputting the resulting split radio frequency signals;
a plurality of amplifier units for amplifying the radio frequency signals outputted from the signal splitter, the amplifier units being disposed circularly to form a generally cylindrical shape;
a plurality of water cooling heat sinks disposed circularly at positions corresponding to positions of the plurality of amplifier units so as to cool the plurality of amplifier units by cooling water;
a signal combiner for combining the radio frequency signals outputted from the plurality of amplifier units, respectively, and outputting the resulting combined radio frequency signal,
an input power monitor for determining whether or not a power level of an input radio frequency signal received by the signal splitter is appropriate; and
an amplitude/phase adjuster for adjusting an amplitude and a phase of a radio frequency signal outputted from the signal splitter,
wherein the input power monitor and the amplitude/phase adjuster are disposed within a hollow space of the generally cylindrical shape.

US Pat. No. 10,714,406

ELECTRONIC POWER MODULE AND ELECTRICAL POWER CONVERTER INCORPORATING SAME

INSTITUT VEDECOM, Versai...

1. Electronic power module having an architecture with 3D stacking, comprising first and second dielectric substrates that are intended to come into thermal contact with first and second heat sinks, respectively, at least one pair of first and second stacked electronic power switching chips and a common intermediate substrate, said first and second electronic power switching chips being sandwiched between said first dielectric substrate and said common intermediate substrate and between said common intermediate substrate and said second dielectric substrate, respectively, wherein said common intermediate substrate is a metal element formed as a single piece and comprises a central portion for implanting said electronic power switching chips, and a thermal conduction portion that is in thermal contact with said first dielectric substrate and/or said second dielectric substrate.

US Pat. No. 10,714,404

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor element;
a lead electrode comprising a lower surface connected to an upper surface of the semiconductor element at one end of the lead electrode;
a cooling mechanism disposed on a lower surface side of the semiconductor element; and
a heat dissipation mechanism provided to be thermally joined between the lower surface of the lead electrode, the lower surface being more adjacent to an other-end side of the lead electrode than the one end, and the cooling mechanism, the heat dissipation mechanism comprising at least one insulating layer,
wherein the heat dissipation mechanism comprises
a first heat dissipation block connected to the lower surface of the lead electrode, the lower surface being more adjacent to the other-end side than the one end,
the insulating layer at least partly connected to a lower surface of the first heat dissipation block, and
a heat dissipation material connected to a lower surface of the insulating layer,
wherein the lead electrode comprises a hole penetrating from an upper surface of the lead electrode to the lower surface of the lead electrode, and
wherein an upper surface of the first heat dissipation block comprises a screw hole in a position superposed on the hole of the lead electrode in plan view.

US Pat. No. 10,714,403

SEMICONDUCTOR DEVICE PACKAGE WITH PATTERNED CONDUCTIVE LAYERS AND AN INTERCONNECTING STRUCTURE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a carrier having a first surface and a second surface opposite to the first surface;
a first patterned conductive layer adjacent to the first surface of the carrier;
an interconnection structure disposed on the first patterned conductive layer and electrically connected to the first patterned conductive layer, the interconnection structure having a side surface and a top surface;
a first semiconductor device disposed on the interconnection structure and electrically connected to the interconnection structure;
an encapsulant disposed on the first patterned conductive layer and encapsulating the first semiconductor device, the top surface of the interconnection structure, and the side surface of the interconnection structure;
a second patterned conductive layer disposed and in direct contract with on a top surface and a side surface of the encapsulant and electrically connected to the first patterned conductive layer; and
a passivation layer disposed on the second patterned conductive layer and covering the side surface of the encapsulant.

US Pat. No. 10,714,401

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Samsung Electronics Co., ...

1. A semiconductor package comprising:a package substrate including a mounting region and at least one through-hole arranged in the mounting region;
a semiconductor chip mounted on the mounting region, the semiconductor chip including a first lateral side and a second lateral side, the second lateral side of the semiconductor chip being opposite to the first lateral side of the semiconductor chip, the second lateral side of the semiconductor chip being closer to the at least one through-hole of the package substrate than the first lateral side of the semiconductor chip; and
a non-conductive molding layer including an underfill part and an extension part, the underfill part between the semiconductor chip and the package substrate, the extension part filling at least a portion of the at least one through-hole.

US Pat. No. 10,714,400

METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING THIN FILM TRANSISTORS INCLUDING OXIDE SEMICONDUCTORS

Micron Technology, Inc., ...

1. A method of forming a semiconductor structure, the method comprising:forming an array of vertical thin film transistors, forming the array of vertical thin film transistors comprising:
forming a source region;
forming a channel material comprising an oxide semiconductor material over the source region;
exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures;
forming a gate dielectric material on sidewalls of the channel regions;
forming a gate electrode material adjacent to the gate dielectric material; and
forming a drain region over the channel regions.

US Pat. No. 10,714,399

GATE-LAST PROCESS FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR

International Business Ma...

1. A method of forming a semiconductor structure, comprising:forming a plurality of fins over a top surface of a substrate;
forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins comprising channels for the one or more vertical transport field-effect transistors; and
forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack comprising a gate dielectric layer, a work function metal layer, and a gate conductor layer;
wherein the gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins;
wherein the box profile in the area between the at least two adjacent fins comprises:
the gate dielectric layer formed on (i) sidewalls of the two adjacent fins, (ii) portions of a top surface of a bottom spacer extending between the at least two adjacent fins, and (iii) portions of a bottom surface of a top spacer extending between the at least two adjacent fins;
the work function metal layer formed on interior surfaces of the gate dielectric layer; and
the gate conductor layer filling a cavity defined by interior surfaces of the work function metal layer.

US Pat. No. 10,714,397

SEMICONDUCTOR DEVICE INCLUDING AN ACTIVE PATTERN HAVING A LOWER PATTERN AND A PAIR OF CHANNEL PATTERNS DISPOSED THEREON AND METHOD FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method for manufacturing a semiconductor device, comprising:forming an active pattern on a substrate; and
forming a gate electrode intersecting the active pattern, the gate electrode extending in a first direction,
wherein the forming of the active pattern comprises: forming a lower pattern and a pair of channel patterns on the lower pattern,
wherein the lower pattern includes a first semiconductor material,
wherein each of the pair of channel patterns includes a second semiconductor material different from the first semiconductor material,
wherein a first portion of the gate electrode is disposed between the pair of channel patterns,
wherein each of the pair of channel patterns is angled towards one another, and
wherein a width of the first portion of the gate electrode, measured along the first direction, decreases in a direction away from the substrate.

US Pat. No. 10,714,396

VARIABLE GATE LENGTHS FOR VERTICAL TRANSISTORS

International Business Ma...

1. A method for fabricating a vertical field-effect transistor (FET) structure, the method comprising:prior to depositing a gate of a first vertical FET on a semiconductor substrate, depositing a first layer of the first vertical FET on the semiconductor substrate;
prior to depositing a gate of a second vertical FET on the semiconductor substrate, depositing a second layer of the second vertical FET on the semiconductor substrate;
etching the first layer of the first vertical FET to a lower height than the second layer of the second vertical FET;
depositing a gate material of both the first vertical FET and the second vertical FET; and
etching the gate material of both the first vertical FET and the second vertical FET to a co-planar height, wherein the first layer and the second layer comprises a spacer.

US Pat. No. 10,714,395

FIN ISOLATION STRUCTURE FOR FINFET AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:a substrate having adjacent first and second fins protruding from the substrate;
an isolation feature between and adjacent to the first fin and the second fin; and
a fin isolation structure between the first fin and the second fin, comprising:
a first insulating layer partially embedded in the isolation feature;
a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer;
a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer; and
a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

US Pat. No. 10,714,394

FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A method of forming a fin field effect transistor (finFET) on a substrate, the method comprising:forming a fin structure on the substrate;
forming a shallow trench isolation (STI) region on the substrate, wherein first and second fin portions of the fin structure extend above a top surface of the STI region;
oxidizing the first fin portion to convert a first material of the first fin portion to a second material, wherein the second material is different from the first material of the first fin portion and a material of the second fin portion;
forming an oxide layer on the oxidized first fin portion and the second fin portion; and
forming first and second polysilicon structures on the oxide layer.

US Pat. No. 10,714,393

MIDDLE OF THE LINE SUBTRACTIVE SELF-ALIGNED CONTACTS

International Business Ma...

1. A method for forming contacts on a semiconductor device, comprising:depositing conductive material in a first trench and a second trench formed through an interlayer dielectric and an etch stop layer disposed on the interlayer dielectric and over the etch stop layer to a height above the etch stop layer;
patterning a resist on the conductive material with a shape over a source/drain region in the first trench;
forming a trench line and a self-aligned contact below the shape in the first trench, including subtractively etching the conductive material based on the resist to remove the conductive material from over the etch stop layer and to recess the conductive material in the second trench; and
depositing a second interlayer dielectric to fill up to the height.

US Pat. No. 10,714,392

OPTIMIZING JUNCTIONS OF GATE ALL AROUND STRUCTURES WITH CHANNEL PULL BACK

International Business Ma...

1. A method of forming a nanosheet device, the method comprising the steps of:forming an alternating series of first nanosheets comprising a first material and second nanosheets comprising a second material as a stack on a wafer;
forming at least one dummy gate on the stack;
forming spacers along opposite sidewalls of the at least one dummy gate;
patterning the stack into at least one fin stack beneath the at least one dummy gate;
etching the at least one fin stack to selectively pull back the second nanosheets in the at least one fin stack forming pockets in the at least one fin stack;
filling the pockets with a strain-inducing material comprising an epitaxial material;
forming source and drains on opposite sides of the at least one fin stack;
burying the at least one dummy gate in a dielectric material;
selectively removing the at least one dummy gate forming at least one gate trench in the dielectric material;
selectively removing, through the at least one gate trench, either the first nanosheets or the second nanosheets from the at least one fin stack; and
forming at least one replacement gate in the at least one gate trench.

US Pat. No. 10,714,388

METHOD AND APPARATUS FOR DEPOSITING COBALT IN A FEATURE

APPLIED MATERIALS, INC., ...

1. A method of processing a substrate, comprising:exposing a substrate at a first temperature to a cobalt containing precursor to deposit a cobalt layer within a word line feature formed in the substrate, wherein the word line feature is part of a 3D NAND device; and
annealing the substrate to remove contaminants from the cobalt layer and to reflow the cobalt layer into the word line feature, wherein the substrate is at a second temperature greater than the first temperature during the annealing;
wherein the first temperature is about 100 degrees Celsius to about 300 degrees Celsius;
wherein the second temperature is up to about 1000 degrees Celsius;
wherein annealing the substrate further comprises annealing the substrate in a hydrogen gas atmosphere; and
wherein the cobalt layer is deposited using a fluorine-free chemical vapor deposition process.

US Pat. No. 10,714,387

INTEGRATED CIRCUIT DEVICES AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit device comprising:a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate;
a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and
source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions comprising:
an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, the upper semiconductor layer including a gap; and
a gap-fill semiconductor layer, in the gap having a second impurity concentration greater than the first impurity concentration.

US Pat. No. 10,714,386

INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING METAL OXIDE ADHESIVE LAYER

Intel Corporation, Santa...

1. A microelectronic assembly, comprising:a first dielectric layer, wherein the first dielectric layer comprises 60% or more filler;
a metal oxide layer in contact with the first dielectric layer, wherein a thickness of the metal oxide layer is between 4 nanometers and 40 nanometers;
a conductive layer in contact with the metal oxide layer; and
a second dielectric layer in contact with the conductive layer, wherein the second dielectric layer comprises 60% or more filler.

US Pat. No. 10,714,385

SELECTIVE DEPOSITION OF TUNGSTEN

ASM IP Holding B.V., Alm...

1. A method of selectively forming a film comprising metal, the method comprising:providing a substrate for processing in a reaction chamber and a hot wire for contacting at least a gas;
exposing the substrate to a metal precursor; and
exposing the substrate to a gas which has been exposed to a vicinity of the hot wire;
wherein the substrate comprises at least two different materials and the metal film is selectively formed in one of the at least two different materials.

US Pat. No. 10,714,384

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming an integrated circuit comprising a first circuit and a second circuit separated from the first circuit;
forming a first dielectric layer over the first circuit and the second circuit;
forming a first metal layer comprising a first metal portion, a second metal portion, a third metal portion, a fourth metal portion, and a fifth metal portion over the first dielectric layer, wherein:
the fifth metal portion is coupled to the first circuit,
the first metal portion surrounds the fifth metal portion to define an inner ring,
the second metal portion surrounds the first metal portion to define an outer ring,
the third metal portion extends between the first metal portion and the second metal portion to define a first connector,
the fourth metal portion extends between the first metal portion and the second metal portion to define a second connector, and
the inner ring, the outer ring, the first connector, and the second connector define an electrically conductive path; and
forming a second dielectric layer over the first metal layer, wherein:
the second dielectric layer isolates the fifth metal portion from the first metal portion, the second metal portion, the third metal portion, and the fourth metal portion, and
the second dielectric layer is disposed between a sidewall of the first connector and a sidewall of the second connector facing the sidewall of the first connector.

US Pat. No. 10,714,382

CONTROLLING PERFORMANCE AND RELIABILITY OF CONDUCTIVE REGIONS IN A METALLIZATION NETWORK

INTERNATIONAL BUSINESS MA...

1. A method of forming a conductive coupling region of a metallization network associated with a substrate, the method comprising:forming a trench in a dielectric material on the substrate;
forming a first liner layer in a first portion of the trench;
forming a second liner layer in a second portion of the trench;
forming a conductive material over the second liner layer in the trench;
forming the first liner layer such that the first liner layer is not present over a bottom surface of the trench; and
forming the second liner layer such that at least a portion of the second liner is over the bottom surface of the trench, wherein the bottom surface of the trench is defined by a portion of the dielectric material; and
performing an anneal to form a copper barrier at the bottom surface of the trench, the copper barrier comprising an alloy material in the second liner layer, oxygen, and silicon in the dielectric material on the substrate.

US Pat. No. 10,714,380

METHOD OF FORMING SMOOTH SIDEWALL STRUCTURES USING SPACER MATERIALS

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming mandrel structures;
forming a first spacer material on each of the mandrel structures;
forming a second spacer material over the first spacer material; and
removing the first spacer material and the mandrel structures to form a sidewall structure having a sidewall smoothness greater than a sidewall smoothness of the mandrel structures,
wherein the forming the first spacer material and the second spacer material comprises a deposition process followed by an anisotropic etching process to expose the mandrel structures.

US Pat. No. 10,714,379

REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS

International Business Ma...

1. An interconnect structure comprising:a contact present within an opening having at least two widths, wherein the contact extends into contact with an electrically conductive feature, wherein a gouge is present in an upper surface of the electrically conductive feature; and
a shield liner present on the sidewalls of the opening, wherein the shield liner includes discontinuous segments on each end of opposed ends of the opening.

US Pat. No. 10,714,378

SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor device, comprising:a package substrate comprising:
a top substrate side comprising top pads;
a bottom substrate side comprising bottom pads; and
conductive paths connecting the top pads and the bottom pads;
an interposer die comprising:
an interposer die top side;
an interposer die bottom side; and
interposer die conductive paths that:
pass through the interposer die from the interposer die top side to the interposer die bottom side; and
are electrically connected to the top pads of the package substrate;
a first device die and a second device die that are:
coupled to the interposer die top side;
surrounded by a perimeter of the interposer die top side; and
electrically connected to the interposer die conductive paths; and
an encapsulating layer that encapsulates the first device die, the second device die, and the interposer die top side, wherein the encapsulating layer comprises an encapsulating layer top side, an encapsulating layer bottom side in contact with the interposer die top side, and an exposed encapsulating layer sidewall.

US Pat. No. 10,714,377

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER INCLUDING A POROUS LAYER AND METHOD OF MANUFACTURING

Infineon Technologies AG,...

1. A method of manufacturing a semiconductor device, the method comprising:forming an auxiliary mask comprising a plurality of mask openings on a main surface of a crystalline semiconductor substrate;
forming a porous structure in the semiconductor substrate, the porous structure comprising a porous layer at a distance to the main surface and porous columns protruding from the porous layer into a direction of the main surface and laterally separated from each other by a non-porous portion; and
forming a non-porous device layer on the non-porous portion and on the porous columns,
wherein forming the non-porous device layer comprises a heat treatment in an atmosphere containing hydrogen to form a non-porous crystalline starting layer.

US Pat. No. 10,714,375

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEIKO EPSON CORPORATION, ...

1. A semiconductor device comprising:a semiconductor layer;
a first conductivity type first well that is arranged in a first region of the semiconductor layer;
a first conductivity type first impurity diffusion region that is arranged in the first well;
a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer;
a second conductivity type second well that is arranged so as to surround the second impurity diffusion region in the semiconductor layer:
an insulating film that is arranged on the second impurity diffusion region;
an electrode that is arranged on the insulating film; and
a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

US Pat. No. 10,714,374

HIGH-PRECISION PRINTED STRUCTURES

X Display Company Technol...

1. A method of making a printed structure, comprising:providing a target substrate and a structure protruding from a surface of the target substrate;
providing a transfer element and a component adhered to the transfer element, wherein the component comprises a component substrate that is separate and independent from the target substrate;
moving the transfer element with the adhered component vertically toward the surface of the target substrate and horizontally towards the structure at least until the component physically contacts the structure or is adhered to the surface of the target substrate; and
separating the transfer element from the component.

US Pat. No. 10,714,373

ELECTROSTATIC CHUCK AND WAFER PROCESSING APPARATUS

Toto Ltd., Fukuoka (JP)

1. An electrostatic chuck, comprising:a ceramic dielectric substrate including a first major surface where a processing object is placed, a second major surface on a side opposite to the first major surface, and a sealing ring, the sealing ring forming a portion of the first major surface and being provided at a peripheral edge portion of the ceramic dielectric substrate, the ceramic dielectric substrate being a polycrystalline ceramic sintered body; and
an electrode layer interposed between the first major surface and the second major surface of the ceramic dielectric substrate, the electrode layer being sintered in the ceramic dielectric substrate as one body,
the electrode layer including a plurality of electrode components arranged to be separated from each other,
an outer perimeter of the ceramic dielectric substrate being provided to cause a spacing between the outer perimeter of the ceramic dielectric substrate and an outer perimeter of the electrode layer to be uniform when viewed from a direction orthogonal to the first major surface,
the spacing between the outer perimeter of the electrode layer and the outer perimeter of the ceramic dielectric substrate being narrower than a spacing of the plurality of electrode components when viewed from the direction,
a width of the sealing ring being not less than 0.3 millimeters and not more than 3 millimeters,
a width where the electrode layer interfaces with the sealing ring being not less than ?0.7 millimeters and not more than 2 millimeters when viewed in the direction, where a negative width corresponds to a spacing between the electrode layer and the sealing ring in a state in which the electrode layer is separated from the sealing ring without overlapping the sealing ring when viewed in the direction, and wherein a positive width corresponds to an overlapping of the electrode layer and the sealing ring when viewed in the direction.

US Pat. No. 10,714,372

SYSTEM FOR COUPLING A VOLTAGE TO PORTIONS OF A SUBSTRATE

APPLIED MATERIALS, INC., ...

1. A substrate support assembly, comprising:a substrate support configured to support a substrate;
a cooling base disposed below the substrate support;
a plurality of electrodes extending through the substrate support and exposed at an upper surface of the substrate support, wherein each electrode is configured to contact the substrate, wherein each electrode is fixed or movably coupled to the cooling base, wherein each electrode is connected to a pair of switches, and wherein each switch has a switch frequency of about 1 MHz; and
a chucking electrode planarly embedded in the substrate support.

US Pat. No. 10,714,371

METHOD AND APPARATUS FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION

TAIWAN SEMICONDUCTOR MANU...

10. A lithographic system, comprising:a vacuum vessel having a first vacuum pressure;
a housing positioned in the vacuum vessel and having a second vacuum pressure that is higher than the first vacuum pressure, wherein the housing has an opening;
a reticle chuck positioned in the housing and having an effective surface for holding a reticle, wherein the effective surface is exposed through the opening;
an exposure tool configured to generate high-brightness light toward the reticle for reflection; and
a wafer stage configured to support a semiconductor wafer so as to allow the semiconductor wafer to receive the high-brightness light reflected from the reticle;
wherein the housing comprises:
a top housing member;
a lateral housing member extending from the top housing member and terminating at a lower edge which is located on a predetermined plane, wherein the effective surface of the reticle chuck is located between the predetermined plane and the top housing member; and
a lower housing member connected to the lower edge, wherein the opening is formed on the lower housing member, and a projection of the lower housing member in a direction that is perpendicular to the effective surface is located outside of the effective surface.

US Pat. No. 10,714,370

MOUNTING TABLE AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

13. A mounting table for mounting thereon an object to be processed, comprising:a base portion having a coolant path formed therein; and
an electrostatic chuck provided on the base portion, the electrostatic chuck having a mounting surface for mounting thereon the object and serving to electrostatically attract the object,
wherein the base portion includes:
(i) a first top surface on which the electrostatic chuck is provided;
(ii) a ring-shaped second top surface provided below the first top surface at an outer side of the first top surface;
(iii) a bottom surface;
(iv) a first side surface extending in a vertical direction between the first top surface and the second top surface; and
(v) a second side surface extending in a vertical direction between the second top surface and the bottom surface;
wherein the coolant path includes:
(i) a central path configured to circulate therein a liquid coolant and extending below the first top surface; and
(ii) a L-shaped peripheral path configured to circulate therein a liquid coolant and having (a) a first portion extending below the second top surface toward the second side surface and (b) a second portion extending above the second top surface toward the first top surface along the first side surface,
wherein a distance between an upper end of the second portion of the peripheral path and the first top surface is smaller than a distance between an upper end of the central path and the first top surface,
wherein the second portion has a fin structure,
wherein the fin structure has a U-shaped cross section, and
wherein the fin structure extends from an upper end toward a lower end of the peripheral path along the first side surface.

US Pat. No. 10,714,368

CEILING TRANSPORT VEHICLE SYSTEM AND TEACHING UNIT

MURATA MACHINERY, LTD., ...

1. An overhead transport vehicle system comprising:an overhead transport vehicle to convey an object; and
a teaching unit to teach transfer of the object by the overhead transport vehicle to a load port on which the object is to be placed; wherein
the teaching unit includes:
a body including a detector to be brought into contact with a positioning pin disposed on the load port to detect a position of the positioning pin; and
a flange movable up and down with respect to the body and to be held by a holder to be raised and lowered by an elevator of the overhead transport vehicle.

US Pat. No. 10,714,367

FUME-REMOVING DEVICE

Bum Je Woo, Seongnam (KR...

1. An apparatus for removing fume, comprising:a wafer cassette for stacking a plurality of wafers;
a front opening for incoming and outgoing of the wafers;
an exhaust for exhausting fume of the wafers; and
a plurality of stacking shelves provided in the wafer cassette, for stacking the wafers vertically,
wherein said plurality of stacking shelves comprise a first stacking shelf supporting a first wafer among the wafers,
wherein said first stacking shelf comprises:
a plate-shaped body;
a purge gas flow path provided in said plate-shaped body in a horizontal direction, said purge gas flow path including a main flow path and branch flow paths branched from said main flow path;
a plurality of purge gas outlets formed on a side surface of said plate-shaped body and connected with said branch flow paths, respectively, for supplying purge gas;
a pin provided on said side surface of said plate-shaped body for directly supporting said first wafer; and
a ramp portion slanted towards a side of said front opening on said side surface of said plate-shaped body,
wherein said plurality of purge gas outlets comprise:
a plurality of first purge gas outlets supplying purge gas; and
a plurality of second gas purge outlets provided in said ramp portion and supplying purge gas towards said front opening.

US Pat. No. 10,714,366

SHAPE METRIC BASED SCORING OF WAFER LOCATIONS

KLA-Tencor Corp., Milpit...

1. A system configured for shape metric based sorting of wafer locations, comprising:one or more computer subsystems configured for:
selecting shape based grouping rules for at least two locations on a wafer, wherein for one of the locations on the wafer, selecting the shape based grouping rule comprises:
determining distances between geometric primitives in a field of view centered on the one location by modifying distances between the geometric primitives in a design for the wafer with metrology data for the one location on the wafer;
determining metrical complexity scores for shape based grouping rules associated with the geometric primitives in the field of view based on the determined distances between the geometric primitives; and
selecting one of the shape based grouping rules for the one location based on the metrical complexity scores; and
sorting the at least two locations on the wafer based on the shape based grouping rules selected for the at least two locations.

US Pat. No. 10,714,365

LIQUID PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A liquid processing apparatus comprising:a processing unit that processes a substrate by using processing liquid including first and second processing liquids;
a first supply route configured to supply the first processing liquid to the processing unit;
a first device that is used for supplying the first processing liquid to the first supply route;
a second supply route configured to supply the second processing liquid to the processing unit, the second processing liquid having higher temperature than the first processing liquid;
a second device that is used for supplying the second processing liquid to the second supply route;
a housing that accommodates the processing unit; and
an external housing that accommodates the first and second devices, the external housing being adjacent to the housing, wherein
the external housing includes a partition wall between the first and second devices.

US Pat. No. 10,714,364

APPARATUS AND METHOD FOR INSPECTING WAFER CARRIERS

Taiwan Semiconductor Manu...

1. An apparatus for inspecting wafer carriers, comprising:a housing having an opening on a wall of the housing;
a load port outside the housing, wherein the load port is coupled to the wall and configured to load a wafer carrier for inspection;
a robot arm inside the housing, wherein the robot arm is configured to move a first camera connected to the robot arm, wherein the first camera is configured to capture a plurality of images of the wafer carrier; and
a processor configured to process the plurality of images to inspect the wafer carrier.

US Pat. No. 10,714,362

SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KOKUSAI ELECTRIC CORPORAT...

1. A substrate processing apparatus comprising:a substrate holder configured to hold a plurality of substrates in an array at respective positions at predetermined intervals and used to hold a plurality of product substrates at the positions where the substrates are allocable and not hold any dummy substrate along with the product substrates;
a tubular reactor including an opening through which the substrate holder can be carried in and out at a lower side and a ceiling with a flat inner surface and houses the substrate holder;
a furnace body surrounding an upper side and a lateral side of the tubular reactor;
a main heater provided in the furnace body and configured to heat the side portion of the tubular reactor;
a ceiling heater provided in the furnace body and configured to heat the ceiling;
a lid that closes the opening;
a cap heater arranged inside the tubular reactor and also located below the substrate holder and configured to perform heating;
and
a gas supply mechanism configured to individually supply a gas to a top side of each of the plurality of product substrates held by the substrate holder inside the tubular reactor,
wherein a volume of an upper end space partitioned from others by the top plate and interposed between the ceiling and the top plate is set to 1 time or more and 3 times or less volume of a space interposed between the product substrates adjacent to each other and held by the substrate holder.

US Pat. No. 10,714,358

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising:forming an oxide semiconductor layer containing indium by sputtering method;
forming a conductive film comprising a region in contact with the oxide semiconductor layer; and
etching the conductive film for forming a source electrode and a drain electrode and etching a region of the oxide semiconductor layer which is not covered by the source electrode or the drain electrode,
wherein the oxide semiconductor layer comprises a region in which a c-axis of a crystal is aligned along a direction perpendicular to a surface of the oxide semiconductor layer.

US Pat. No. 10,714,355

PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma etching method, comprising:a recess forming process of forming a recess having a depth smaller than a thickness of a first silicon oxide film by etching the first silicon oxide film by a first plasma generated from a first processing gas, wherein a silicon-containing reaction product is formed by the first plasma and adhered to the recess in the recess forming process;
a removing process of removing the silicon-containing reaction product by a second plasma generated from a second processing gas; and
a penetrating process of forming a hole penetrating the first silicon oxide film by etching the recess, from which the silicon-containing reaction product is removed, by the first plasma until a film formed under the first silicon oxide film is exposed,
wherein the first processing gas and the second processing gas contain a fluorocarbon gas, and
a flow rate of the fluorocarbon gas of the second processing gas is larger than a flow rate of the fluorocarbon gas of the first processing gas.

US Pat. No. 10,714,353

PLANARIZATION METHOD

DISCO CORPORATION, Tokyo...

1. A planarization method for planarizing a separation surface of a silicon carbide ingot after a focal point of a laser beam with such a wavelength as to be transmitted through silicon carbide is positioned at a depth corresponding to a wafer to be generated from an end surface of the silicon carbide ingot and the silicon carbide ingot is irradiated with the laser beam to form a separation layer in which silicon carbide is separated into silicon and carbon and cracks are isotropically generated along a c-plane, and the wafer is separated from the silicon carbide ingot at the separation layer, the planarization method comprising:a grinding step of holding an opposite side to the separation surface in the silicon carbide ingot by a rotatable chuck table and rotating a grinding wheel having a plurality of grinding abrasives disposed in a ring manner to grind the separation surface of the silicon carbide ingot held by the chuck table; and
a flatness detection step of irradiating the separation surface of the silicon carbide ingot exposed from the grinding wheel with light and detecting reflected light to detect a degree of flatness, wherein:
the grinding step is ended when it has been detected in the flatness detection step that the separation surface of the silicon carbide ingot has become flat,
wherein:
in the flatness detection step, detecting that the separation surface has become flat comprises irradiating the separation surface with the light at an oblique incident angle ?, and receiving the reflected light at an oblique reflection angle ?, and determining when an amount of received light surpasses a threshold, wherein said oblique incident angle ? is equal to said oblique reflection angle ?.

US Pat. No. 10,714,351

MULTI-LAYERED SUBSTRATE MANUFACTURING METHOD

Nikon Corporation, Tokyo...

1. A substrate bonding method for aligning and layering a pair of substrates, comprising:holding one of the pair of substrates with a first holding member that has a member to be joined;
holding the other of the pair of substrates to face the one of the substrates with a second holding member that has a joining member exerting a joining force on the member to be joined;
aligning the pair of substrates;
layering the pair of substrates, such that the aligned pair of substrates make direct contact and are held in a layered state between the first holding member and the second holding member;
using the joining force to make contact between the member to be joined and the joining member in order to join the member to be joined and the joining member, the contact between the member to be joined and the joining member being made after the layering of the pair substrates; and
restricting a magnitude of the joining force during at least one of the aligning and the layering of the pair of substrates, such that the joining force applied to the member to be joined and the joining member is reduced.

US Pat. No. 10,714,348

SEMICONDUCTOR DEVICE HAVING HYDROGEN IN A DIELECTRIC LAYER

Taiwan Semiconductor Manu...

1. A structure comprising:an active area on a substrate, the active area having a channel region;
a gate structure over the channel region of the active area, wherein the gate structure includes:
an interfacial layer over the active area;
a conformal dielectric layer over the interfacial layer; and
a gate electrode layer over the interfacial layer; and
wherein a ratio of a peak concentration of hydrogen in the interfacial layer to a peak concentration of hydrogen in the conformal dielectric layer is in a range from about 0.1 to about 5.

US Pat. No. 10,714,344

MASK FORMATION BY SELECTIVELY REMOVING PORTIONS OF A LAYER THAT HAVE NOT BEEN IMPLANTED

Taiwan Semiconductor Manu...

1. A method for semiconductor processing, the method comprising:forming a dielectric layer over a substrate, the dielectric layer having a conductive region therein;
forming a mask layer over the dielectric layer;
forming a first patterned mask over the mask layer, the first patterned mask having a first opening exposing a first portion of the mask layer, the first patterned mask covering a second portion of the mask layer;
performing one or more species implant processes into the first portion of the mask layer;
removing the first patterned mask;
etching the second portion of the mask layer to form a second patterned mask, wherein an etch rate of the first portion is less than an etch rate of the second portion;
after removing the second portion, etching the dielectric layer using the second patterned mask as a mask to form a second opening; and
forming a conductive material in the second opening.

US Pat. No. 10,714,341

REACTIVE ION ETCHING ASSISTED LIFT-OFF PROCESSES FOR FABRICATING THICK METALLIZATION PATTERNS WITH TIGHT PITCH

ELPIS TECHNOLOGIES INC., ...

1. A method comprising:forming a sacrificial layer having a first thickness on a top surface of a substrate;
forming a mask layer over the sacrificial layer, wherein the mask layer comprises an opening;
isotropically etching a portion of the sacrificial layer exposed through the opening of the mask layer to form an undercut region of a second thickness in the top portion of the sacrificial layer below the mask layer, wherein the undercut region defines an overhang structure, wherein the second thickness is less than the first thickness;
anisotropically etching a remaining portion of the sacrificial layer exposed through the opening of the mask layer to form an opening through the sacrificial layer down to the top surface of the substrate;
directionally depositing a metallic material to at least partially fill the opening formed in the sacrificial layer with metallic material without coating the overhang structure with metallic material; and
dissolving the sacrificial layer to lift-off the mask layer and the metallic material deposited on the mask layer thereby leaving a metal line disposed on the top surface of the substrate;
wherein the metallic material within the opening of the sacrificial layer comprises the metal line disposed on the top surface of the substrate, wherein an upper portion of the metal line comprises a tapered profile.

US Pat. No. 10,714,334

CONDUCTIVE FEATURE FORMATION AND STRUCTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a conductive structure comprising:forming a dielectric layer on a semiconductor substrate, the semiconductor substrate having a source/drain region;
forming an opening through the dielectric layer to the source/drain region; and
by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process, forming a silicide region on the source/drain region and a barrier layer in the opening along sidewalls of the dielectric layer, wherein each precursor used in the same PECVD process is introduced to the dielectric layer simultaneously.

US Pat. No. 10,714,333

APPARATUS AND METHOD FOR SELECTIVE OXIDATION AT LOWER TEMPERATURE USING REMOTE PLASMA SOURCE

APPLIED MATERIALS, INC., ...

1. A method for selective oxidation of non-metal surfaces, comprising:positioning a substrate in a processing chamber, wherein the processing chamber is maintained at a pressure less than 2 Torr;
flowing activated hydrogen gas into the processing chamber through a first inlet, the activated hydrogen gas activated by a hot wire apparatus;
soaking the substrate in the activated hydrogen gas in the absence of plasma comprising oxygen;
generating a remote RF plasma comprising oxygen after soaking the substrate in the activated hydrogen gas;
flowing the remote RF plasma into the processing chamber through a second inlet, wherein the remote RF plasma mixes with the activated hydrogen gas to create an activated processing gas; and
exposing the substrate to the activated processing gas.

US Pat. No. 10,714,330

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A STEP OF PERFORMING ION IMPLANTATION USING A RESIST PATTERN AS A MASK

Renesas Electronics Corpo...

1. A method for manufacturing a semiconductor device, comprising the steps of:(a) providing a semiconductor substrate;
(b) forming a resist pattern over the semiconductor substrate;
(c) forming a first film over the semiconductor substrate in such a manner as to cover the resist pattern;
(d) ion implanting an impurity into the semiconductor substrate with the resist pattern covered with the first film;
(e) after the step (d), removing the first film by wet etching; and
(f) after the step (e), removing the resist pattern, and
further comprising a step of:
(a1) after the step (a), and before the step (b), forming an insulation film over the semiconductor substrate,
wherein the insulation film and the first film are formed of mutually different materials,
wherein in the step (b), the resist pattern is formed over the insulation film,
wherein in the step (c), the first film is formed over the insulation film in such a manner as to cover the resist pattern, and
wherein in the step (e), wet etching is performed under the conditions in which the first film is more likely to be etched than the resist pattern, and the insulation film is less likely to be etched than the first film, thereby to remove the first film.

US Pat. No. 10,714,325

GLOW DISCHARGE ION SOURCE

Micromass UK Limited, Wi...

1. A mass spectrometer comprising:a first vacuum chamber;
an atmospheric pressure ion source for generating first ions, wherein first ions generated by said atmospheric pressure ion source are transmitted, in use, into said vacuum chamber via a sampling cone or first aperture, wherein the direction along which at least some of said first ions are transmitted, in use, through said sampling cone or first aperture into said first vacuum chamber defines a first axis;
a glow discharge device for generating second ions, wherein said second ions comprise lock mass or calibration ions for calibrating the mass spectrometer, wherein second ions generated by said glow discharge device are generated within said first vacuum chamber and a discharge pin of said glow discharge device is arranged orthogonally to said first axis, and wherein said second ions are transmitted into or generated within said first vacuum chamber without being transmitted through said sampling cone or first aperture; and
one or more dispensing devices for dispensing one or more reagents in proximity to said glow discharge device, wherein said one or more reagents comprise one or more lock mass or calibration reagents for mass calibrating the mass spectrometer, which lock mass or calibration reagents are ionised, in use, by a glow discharge formed or generated by said discharge pin of said glow discharge device to generate said second ions comprising lock mass or calibration ions,
wherein said second ions comprising lock mass or calibration ions and said first ions are onwardly transmitted from said first vacuum chamber through the same extraction cone or aperture and into a downstream chamber of said mass spectrometer,
wherein the first vacuum chamber comprises a central cylindrical bore or port to control the passage of the second ions, and the discharge pin of the glow discharge device is located within the central cylindrical bore or port of the first vacuum chamber.

US Pat. No. 10,714,324

INLET INSTRUMENTATION FOR ION ANALYSER COUPLED TO RAPID EVAPORATIVE IONISATION MASS SPECTROMETRY (“REIMS”) DEVICE

Micromass UK Limited, Wi...

1. An apparatus comprising:a first device for generating aerosol, smoke or vapour from one or more regions of a target;
an inlet conduit to an ion analyser or mass spectrometer, said inlet conduit having an inlet through which said aerosol, smoke or vapour passes;
a Venturi pump arrangement arranged and adapted to direct said aerosol, smoke or vapour towards said inlet, wherein said Venturi pump arrangement is arranged and adapted to direct said aerosol, smoke or vapour onto a deflection device or surface prior to said aerosol, smoke or vapour passing through said inlet, wherein said deflection device comprises a hollow member having a first side and a second side, wherein the first side is solid and the second side comprises one or more apertures arranged and adapted to allow said aerosol, smoke or vapour to pass therethrough and wherein said Venturi pump arrangement is arranged and adapted to direct said aerosol, smoke or vapour onto the first surface of said deflection device;
a matrix conduit for introducing and mixing a matrix with said aerosol, smoke or vapour prior to said aerosol, smoke or vapour passing through the inlet; and
a collision surface located within a vacuum chamber and arranged and adapted such that said aerosol, smoke or vapour is caused to impact upon said collision surface so as to generate a plurality of analyte ions.

US Pat. No. 10,714,323

ZERO VOLTAGE MASS SPECTROMETRY PROBES AND SYSTEMS

Purdue Research Foundatio...

1. A system comprising:a mass spectrometry probe comprising a porous material, wherein at least a portion of a surface of the porous material comprises one or more modified properties; and
a mass spectrometer, wherein the system operates without an application of voltage to the probe.

US Pat. No. 10,714,322

IRMS SAMPLE INTRODUCTION SYSTEM AND METHOD

Thermo Fisher Scientific ...

1. A method of introducing a sample into an Isotope Ratio Spectrometer, comprising steps of(a) generating sample ions in a solvent matrix in an ionization source;
(b) removing at least a proportion of the solvent matrix from the sample ions in a desolvation chamber, so as to produce a flow of sample ions along with non-ionized solvent and solvent ions into a separation chamber;
(c) applying voltages to electrodes in the separation chamber to apply an AC and/or a DC electric field to the flow of ions along with solvent vapors, so as to direct wanted sample ions, having a first mass to charge ratio or range of mass to charge ratios, along a first flow path towards an outlet of the separation chamber, whilst unwanted solvent ions, other ions, and non-ionized solvent are directed away from the said separation chamber outlet, the unwanted solvent ions and other ions having a second mass to charge ratio or range of mass to charge ratios, different to the said first mass to charge ratio or range of ratios; and
(d) decomposing the sample ions to molecular products once they have passed through the outlet of the separation chamber and into a reaction chamber; and
(e) providing molecular products of the decomposed sample ions to the Isotope Ratio Spectrometer.

US Pat. No. 10,714,320

PLASMA PROCESSING METHOD INCLUDING CLEANING OF INSIDE OF CHAMBER MAIN BODY OF PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method including cleaning of an inside of a chamber main body of a plasma processing apparatus,wherein the plasma processing apparatus comprises:
the chamber main body which provides a chamber;
a stage, provided within the chamber, having an electrostatic chuck configured to hold a processing target object placed thereon; and
a temperature control device configured to adjust a temperature of the electrostatic chuck, and
wherein the plasma processing method comprises:
etching an etching target film of the processing target object placed on the electrostatic chuck by generating plasma of a processing gas containing a fluorocarbon gas and/or a hydrofluorocarbon gas within the chamber, the etching of the etching target film including a main etching of etching the etching target film in a state that the temperature of the electrostatic chuck is set to be equal to or lower than ?30° C. by the temperature control device, wherein the etching target film is a silicon oxide film, a silicon nitride film or a multilayered film composed of one or more silicon oxide films and one or more silicon nitride films stacked on top of each other alternately;
carrying-out the processing target object from the chamber after the etching of the etching target film is performed; and
cleaning the inside of the chamber main body by generating plasma of a cleaning gas containing oxygen within the chamber in a state that the temperature of the electrostatic chuck is set to be equal to or higher than 0° C. to reduce a deposit containing carbon and fluorine by the temperature control device after the carrying-out of the processing target object is performed,
wherein the etching of the etching target film further includes an overetching of etching the etching target film additionally after the main etching is performed, and
raising the temperature of the electrostatic chuck by the temperature control device when the overetching is being performed, in order to raise the temperature of the electrostatic chuck to be equal to or higher than 0° C. before the cleaning of the inside of the chamber main body is performed.

US Pat. No. 10,714,317

REDUCTION OF CONDENSED GASES ON CHAMBER WALLS VIA HEATED CHAMBER HOUSING FOR SEMICONDUCTOR PROCESSING EQUIPMENT

Axcelis Technologies, Inc...

1. A workpiece processing system, comprising:a chamber having one or more chamber walls defining a respective one or more surfaces generally enclosing a chamber volume;
one or more chamber wall heaters associated with the one or more chamber walls, wherein the one or more chamber wall heaters are configured to selectively heat the one or more chamber walls to a chamber wall temperature;
a workpiece support positioned within the chamber and configured to selectively support a workpiece having one or more materials residing thereon, wherein each of the one or more materials has a respective condensation temperature associated therewith, above which, the one or more materials are respectively in a gaseous state;
a heater apparatus configured to selectively heat the workpiece to a predetermined temperature; and
a controller configured to heat the workpiece to the predetermined temperature via a control of the heater apparatus, thereby heating the one or more materials to respectively form one or more outgassed materials within the chamber volume, and wherein the controller is further configured to control the chamber wall temperature via a control of the one or more chamber wall heaters, wherein the chamber wall temperature is greater than a condensation temperature associated with the one or more outgassed materials, thereby preventing a condensation of the outgassed material on the one or more surfaces.

US Pat. No. 10,714,316

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KOKUSAI ELECTRIC CORPORAT...

1. A method of manufacturing a semiconductor device, comprising:supplying a first process gas to a process space where a substrate is accommodated, and using an inert gas as a carrier gas of the first process gas; and
supplying plasma of a second process gas to the process space where the substrate is accommodated, and using an active auxiliary gas, which is different from the inert gas, as a carrier gas of the second process gas,
wherein the plasma of the second process gas is supplied without the inert gas, which is used in the act of supplying the first process gas,
wherein the inert gas is supplied in the act of supplying the first process gas without supplying the active auxiliary gas, which is used in the act of supplying the plasma of the second process gas, and
wherein the act of supplying the plasma is performed by setting an internal pressure of the process space to be lower than an internal pressure of the process space in the act of supplying the first process gas.

US Pat. No. 10,714,313

HIGH FREQUENCY AMPLIFIER APPARATUSES

1. A high-frequency amplifier apparatus suitable for generating power for plasma excitation, the apparatus comprising:two Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors each having a drain terminal and a source terminal that is connected to a ground connection point, wherein the LDMOS transistors are embodied alike and are arranged as a package;
a circuit board that lies flat on a metal cooling plate and is connected to the cooling plate, wherein the cooling plate is connectable to ground by a plurality of ground connections, wherein the package is arranged on the circuit board;
a power transformer including a primary winding connected to the drain terminals of the two LDMOS transistors; and
a signal transformer including a secondary winding having a first end and a second end, wherein
the secondary winding is connected at the first end to a first gate terminal of one of the two LDMOS transistors by one or more first resistive elements, and
the secondary winding is connected at the second end to a second gate terminal of the other of the two LDMOS transistors by one or more second resistive elements; and
wherein each of the first gate terminal and second gate terminal is connected to ground by one or more voltage-limiters.

US Pat. No. 10,714,310

METHODS AND APPARATUS FOR HIGH THROUGHPUT SEM AND AFM FOR CHARACTERIZATION OF NANOSTRUCTURED SURFACES

NANOWEAR INC., Brooklyn,...

1. A method of forming an overlay image, comprising(a) providing an SEM image of a nanosensor sample including a plurality of vertically free standing nanostructures;
(b) AFM imaging a top portion of selected ones of the plurality of vertically standing nano structures;
(c) creating an overlaid image including an AFM imaged top portion overlayed on the SEM image.

US Pat. No. 10,714,304

CHARGED PARTICLE BEAM APPARATUS

Hitachi High-Tech Corpora...

1. A charged particle beam device comprising:an optical element configured to adjust a charged particle beam emitted from a charged particle source;
an adjustment element configured to adjust the charged particle beam incident on the optical element; and
a control device configured to control the adjustment element, wherein
the control device obtains an extent of deviation from an equilibrium temperature of the optical element based on a condition setting of the optical element and executes adjustment with the adjustment element when the extent of deviation satisfies a predetermined condition.

US Pat. No. 10,714,287

FUSE ELEMENT

HKR AUTOMOTIVE GMBH, (DE...

1. A fuse element for an electric circuit, arranged on a circuit board of the electric circuit, the fuse element comprising:a surface area for fastening and establishing an electric contact of the fuse element on the circuit board,
a first deforming area adjacent to the surface area,
a second deforming area which is connected to the first deforming area via a central area, and wherein the second deforming area includes a contact area by which the fuse element abuts on the circuit board, and
a hook-shaped element formed on the second deforming area and being insertable into an opening in the circuit board disposed adjacent to the contact area of the second deforming area, wherein
the hook-shaped element is insertable into the opening of the circuit board by elastic deformation of the fuse element in the direction of the circuit board, and
due to an elastic bias of the hook-shaped element toward the second deforming area after inserting the hook-shaped element into the opening and positively holding the hook-shaped element on a lower surface of the circuit board adjacent to the opening, the first and second deforming areas exert an elastic force upon the surface area in the direction away from the circuit board.

US Pat. No. 10,714,272

GRAPHENE FRAMEWORKS FOR SUPERCAPACITORS

THE REGENTS OF THE UNIVER...

1. An electrode comprising a holey 3D graphene framework, comprising:a) an interconnected conductive network of holey graphene sheets, wherein nanopores are formed within the holey graphene sheets; and
b) a capacitive or pseudo-capacitive material comprising sulfur particles, wherein the sulfur particles are encapsulated within the interconnected conductive network of holey graphene sheets, wherein the encapsulation inhibits polysulfide shuttling;
wherein the electrode has a sulfur content of at least 60% by weight or mass of a total weight or mass of the electrode.

US Pat. No. 10,714,259

METHOD FOR MAKING A MULTILAYERED CERAMIC CAPACITOR

KEMET Electronic Corporat...

1. A method for forming a multilayered ceramic capacitor (MLCC) comprising:forming a ceramic precursor layer;
printing an active layer on said ceramic precursor layer wherein said active layer comprises a multiplicity of conductive internal electrodes and a multiplicity of identification markers (ID markers) wherein each ID marker of said ID markers is coplanar with at least one internal electrode of said internal electrodes;
forming an alternating stack of said ceramic precursor layers and said active layers wherein adjacent active layers are offset;
sintering said alternating stack;
dicing said alternating stack to form discrete capacitors wherein said ID markers extend to an outer boundary of said discrete capacitors; and
forming external terminations in electrical contact with said internal electrodes wherein adjacent internal electrodes are terminated to opposite polarity.

US Pat. No. 10,714,258

STATIONARY INDUCTION APPARATUS

MITSUBISHI ELECTRIC CORPO...

1. A stationary induction apparatus comprising:a winding formed of a plurality of winding layers disposed in a central axis direction;
an insulating barrier disposed between outer peripheral ends of the winding layers adjacent to each other in the central axis direction, the outer peripheral ends being not connected to each other; and
an insulating oil in which each of the winding and the insulating barrier is immersed,
the insulating barrier including
a first extension extending radially outwardly of the winding and partitioning the outer peripheral ends,
a second extension bent from an end of the first extension, extending toward one side in the central axis direction, and covering at least a part of one outer peripheral end of the outer peripheral ends,
a third extension bent from an end of the second extension and extending radially outwardly of the winding, and
a fourth extension bent from an end of the third extension, extending toward the other side in the central axis direction, and covering at least a part of the other outer peripheral end of the outer peripheral ends,
the fourth extension facing the second extension with a spacing therebetween.

US Pat. No. 10,714,245

METHOD FOR PREPARING AN R-T-B PERMANENT MAGNET

Beijing Zhong Ke San Huan...

1. A method of manufacturing a R-T-B permanent magnet, comprising the steps of:sintering a compact comprising a R-T-B material at a temperature of between 900° C. and 1040° C. to obtain a pre-sintered block, wherein R comprises one or more rare-earth elements selected from the group consisting of Sc, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Y, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and R comprises at least one heavy rare earth element and at least one rare earth element other than a heavy rare earth element; T comprises one or more transition metal elements; and B is boron;
wherein the actual density of the pre-sintered block is 6.0-7.4 g/cm3;
coating a heavy rare earth compound powder on the pre-sintered block to form a coated block; and
wherein, prior to sintering the coated block, placing the coated block in a container that comprises a sintering aid comprising between 10 and 20% of alumina and between 80 and 90% of magnesium oxide,
sintering the coated block to obtain the R-T-B permanent magnet,
wherein sintering the coated block comprises heating the coated block at between 860° C. and 950° C. for between 12 and 24 hours under vacuum, cooling, and heating the coated block at between 450° C. and 620° C. under vacuum to obtain the R-T-B permanent magnet.

US Pat. No. 10,714,234

CABLE DISCONNECTION PREVENTING STRUCTURE

OMRON Corporation, Kyoto...

1. A cable disconnection preventing structure comprising:a case which has a cable hole through which a cable having a plurality of conducting wires covered with a sheath passes and in which one end portion of the cable is embedded; and
a conducting wire fixing member which fixes only the conducting wires exposed from the sheath at the one end portion of the cable to the sheath in a state in which the conducting wires are bent toward the other end portion side of the cable and is formed larger than the cable hole, wherein
a portion of each of the conducting wires exposed from the sheath is disposed between an inner surface around the cable hole in the case and the conducting wire fixing member.

US Pat. No. 10,714,229

BEAM FILTER ASSEMBLY AND BEAM FILTER POSITIONING DEVICE

Varian Medical Systems, I...

1. A beam filter positioning device comprising a base stage carrying a base filter and one or more additional stages each carrying a filter slice in and/or out of a beam line thereby allowing the filter slice carried by the one or more additional stages to be stacked with the base filter carried by the base stage along the beam line, whereinthe base stage is provided with a first engagement site and a second engagement site;
the one or more additional stages comprise at least a first stage carrying a first filter slice and being provided with a first engagement site, a second engagement site, and an open port, wherein
the first stage and the base stage are each independently movable relative to the beamline by a linear motion axis; and
the first stage is engageable with the base stage when at least one of the first and second engagement sites of the first stage is aligned with at least one of the first and second engagement sites of the base stage, and further movable with the base stage in unison when engaged,
wherein when engaged the first stage and the base stage are further movable in unison by an additional linear motion axis.

US Pat. No. 10,714,216

METHOD AND SYSTEM FOR INCREASING ACCURACY OF HYGIENE COMPLIANCE DETERMINATIONS

SwipeSense, Inc., Chicag...

16. A computer implemented method for increasing accuracy of hygiene compliance in medical facilities, the method comprising:determining received signal strength between a tag and one or more location beacons;
transmitting the received signal strength to a hygiene compliance datastore;
determining one or more of tag accelerometer data, orientation data, heading data, or tag movement data;
transmitting the one or more of the tag accelerometer data, the orientation data, the heading data, or the tag movement data to the hygiene compliance datastore;
processing, by a computer, data stored in the hygiene compliance datastore;
determining hygiene compliance based at least on the processed data;
determining positions of a plurality of location beacons in a coordinate system;
transmitting the positions of the plurality of location beacons to the hygiene compliance datastore;
determining possible and impossible movement paths of the tag;
transmitting the possible and impossible movement paths of the tag to the hygiene compliance datastore;
determining one or more of usage of logs, timestamps associated with the tag, or timestamps associated with a use of a hygiene dispenser;
transmitting the one or more of the usage of logs, the timestamps associated with the tag, or the timestamps associated with the use of a hygiene dispenser to the hygiene compliance datastore;
processing, by the computer, the data stored in the hygiene compliance datastore; and
determining the hygiene compliance based at least on the processed data.

US Pat. No. 10,714,215

SYSTEM AND METHOD OF MONITORING AND CONFIRMING MEDICATION DOSAGE

1070715 B.C. Unlimited Li...

1. A method of monitoring and dispensing patient information relating to use and consumption of medication, the method comprising the steps of:communicatively coupling a first device with a second device, at least one of the first device and the second device including a processor, a memory and a patient monitoring unit;
providing a technician user interface on one of the first device and the second device, the technician user interface including a video display portion configured to display a video image of a user after communicatively coupling the first device with the second device, the technician user interface portion including a medication listing portion to view medications prescribed to the user, and the technician user interface portion including a video portion to view recorded video associated with at least one of the user and preparation and administration of each medication prescribed to the user;
transmitting live images from the first device to the second device;
analyzing the content of the live images to identify at least one of a biometric attribute of the user and a bar code on a medication container in a captured image from the live images;
providing the user with at least one of injection information, medication information and dosage information via at least one of the video display portion and the video portion of the technician user interface; and
further analyzing the content of the live images to determine the user's compliance with the at least one of injection information, medication information and dosage information provided to the user.

US Pat. No. 10,714,205

MULTI-PURPOSED LEAK DETECTOR

SanDisk Technologies LLC,...

1. A method for detecting a word line leakage in a memory array of a non-volatile memory system, comprising:in a first stage:
enabling a M-bit coarse digital-to-analog converter (DAC) logic of a N-bit analog-to-digital converter (ADC), the analog-to-digital converter (ADC) having a comparator with a reference voltage (VREF) as a first input;
voltage biasing a load current of a memory array to produce an input voltage (Vint) as a second input to the comparator; and
according to a clock signal from the coarse digital-to-analog converter (DAC) logic, comparing the input voltage (Vint) level to the reference voltage (VREF) level; and
in a second stage:
if the input voltage (Vint) level is greater than or equal to the reference voltage (VREF) level, enabling a P-bit fine ramp digital-to-analog converter (DAC) logic of the analog-to-digital converter (ADC) to:
enable drawing a second current (Ifine) from the load current to thereby decrease the input voltage (Vint) level;
compare the input voltage (Vint) level to a first voltage (Vfinestart) level, wherein the first voltage (Vfinestart) level is less than the reference voltage (VREF) level;
if the input voltage (Vint) level is less than or equal to the first voltage (Vfinestart) level, begin a counter and conduct leakage detection with the analog-to-digital converter (ADC) according to a clock signal (CLK) from the fine ramp digital-to-analog converter (DAC) logic;
compare the input voltage (Vint) level to a second voltage (Vfinestop) level, wherein the second voltage (Vfinestop) level is less than the first voltage (Vfinestart) level; and
if the input voltage (Vint) level is equal to the second voltage (Vfinestop) level, disable the clock signal (CLK) thereby completing the leakage detection.

US Pat. No. 10,714,182

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a bit line;
a source line;
a memory string that is provided between the bit line and the source line, and that includes a plurality of memory cells electrically connected in series, the plurality of memory cells including:
a first memory cell,
a second memory cell, the first memory cell being provided between the source line and the second memory cell,
a third memory cell, the second memory cell being provided between the source line and the third memory cell, and
a fourth memory cell, the third memory cell being provided between the source line and the fourth memory cell;
first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively;
a voltage generation circuit configured to generate at least three kinds of voltages, the three kinds of voltages including a first voltage, a second voltage, and a third voltage;
a first circuit configured to:
output the first voltage or one of the second voltage and the third voltage to a first wire, and
output the first voltage or the one of the second voltage and the third voltage to a second wire;
a second circuit configured to output the other one of the second voltage and the third voltage to a third wire and a fourth wire;
a third circuit configured to connect the first and second wires or the third and fourth wires to the first and second word lines, respectively; and
a fourth circuit configured to connect the first and second wires or the third and fourth wires to the third and fourth word lines, respectively.

US Pat. No. 10,714,175

METHOD, SYSTEM AND DEVICE FOR TESTING CORRELATED ELECTRON SWITCH (CES) DEVICES

ARM, Ltd., Cambridge (GB...

1. An integrated circuit device comprising:one or more correlated electron switch (CES) elements;
one or more first terminals configured to receive one or more first signals to control operations to transition the at least one of the one or more CES elements between a low impedance and/or conductive state and a high impedance and/or insulative state;
one or more second terminals to comprise signal pins external to the integrated circuit device, the one or more second terminals to be configured to receive an externally applied signal, the externally applied signal to be at a first voltage level during a first operation to place the at least one of the one or more CES elements in the low impedance and/or conductive state, the externally applied signal to be at a second voltage level during a second operation to place the least one of the one or more CES elements in the high impedance and/or insulative state; and
a circuit configured to limit a magnitude of a current in the at least one of the one or more CES elements during the first operation to place the at least one of the one or more CES elements in the low impedance and/or conductive state responsive to the externally applied signal at the first voltage level received at the one or more second terminals.

US Pat. No. 10,714,173

SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS IN RRAM CELLS

Hefei Reliance Memory Lim...

1. A resistive RAM device, comprising:a plurality of bit lines;
a word line;
a source line carrying a first bias voltage while performing set operations, a second bias voltage during reset operations and a third bias voltage during read operations, wherein the first, second, and third bias voltages are positive and substantially the same;
a plurality of RRAM cells coupled to the word line, wherein each RRAM cell of the plurality of RRAM cells coupled to the word line comprises:
a single resistive memory element,
a transistor having a gate node coupled to the word line,
a bias node coupled to the source line, and
a bit line node coupled to a respective bit line of the plurality of bit lines; and
a bit line control circuit coupled to one or more of the plurality of bit lines, the bit line control circuit generating command voltages to perform respective memory operations on one or more RRAM cells of the plurality of RRAM cells, wherein the respective memory operations include a read operation that reads values stored in respective RRAM cells of the plurality of RRAM cells.

US Pat. No. 10,714,172

BI-SIDED PATTERN PROCESSOR

HangZhou HaiCun Informati...

1. A bi-sided pattern processor, comprising:an input for transferring at least a first portion of a first pattern;
a plurality of storage-processing units (SPU's) communicatively coupled with said input, each of said SPU's comprising at least a memory array and a pattern-processing circuit, wherein said memory array stores at least a second portion of a second pattern, said pattern-processing circuit performs pattern processing for said first and second patterns;
a semiconductor substrate with first and second surfaces, wherein said memory array is disposed on said first surface, said pattern-processing circuit is disposed on said second surface, said memory array and said pattern-processing circuit are communicatively coupled by a plurality of inter-surface connections.

US Pat. No. 10,714,171

NAND FLASH MEMORY SYSTEM STORING MULTI-BIT DATA AND READ/WRITE CONTROL METHOD THEREOF

Toshiba Memory Corporatio...

1. A memory system comprising:a semiconductor storage device including m memory cells (m is an integer of 2 or more) connected to a word line in common, each of the m memory cells being capable of storing n-bit data (n is an integer of 2 or more); and
a controller circuit,
wherein the semiconductor storage device is configured to determine values of m pieces of n-bit read data stored in the all of m memory cells, by a first reading operation using k reading voltages different from each other (k is an integer equal to or higher than 2 (n?1) and less than 2 n?1),
the controller circuit is configured to convert the determined values of m pieces of n-bit read data into data corresponding to (k+1) decimal data of m digits, and
the all of the m memory cells have a positive threshold voltage corresponding to a programmed state, without using a negative threshold voltage corresponding to an erased state, during the first reading operation.

US Pat. No. 10,714,170

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a first memory cell capable of storing 3-bit data, wherein
when first data including a first bit is received from an external controller, the received first data is written to the first memory cell,
when second data including a second bit and a third bit is received from the controller after the first data is received, the first bit is read from the first memory cell and the 3-bit data is written to the first memory cell based on the read first bit and the received second data, and
in the 3-bit data written to the first memory cell, lower bit data is determined by three read operations, middle bit data is determined by two read operations, and upper bit data is determined by two read operations.

US Pat. No. 10,714,168

STRAP CELL DESIGN FOR STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY

TAIWAN SEMICONDUCTOR MANU...

1. A static random access memory (SRAM) array, comprising:a first bit cell array and a second bit cell array arranged along a first direction;
a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction,
wherein the strap cell comprises:
a first P-type well region;
a first N-type well region and a second N-type well region respectively on opposite first sides of the first P-type well region, wherein the first N-type well region, the first P-type well region, and the second N-type well region are arranged along the first direction; and
a second P-type well region and a third P-type well region respectively on opposite second sides of the first N-type well region, wherein the second P-type well region, the first N-type well region, the third P-type well region are arranged along the second direction; and
a deep N-type well region underlying and connected to the first N-type well region and the second N-type well region.

US Pat. No. 10,714,163

METHODS FOR MITIGATING TRANSISTOR AGING TO IMPROVE TIMING MARGINS FOR MEMORY INTERFACE SIGNALS

Intel Corporation, San J...

1. An integrated circuit die, comprising:an interface block operable to communicate with an external component in accordance with a predetermined interface protocol, wherein the interface block is configured to output an interface clock signal and to output a control signal that is latched at the external component using the interface clock signal, and wherein the interface block is further configured to periodically toggle the control signal during idle periods to improve timing margins by mitigating transistor aging effects in the interface block.

US Pat. No. 10,714,157

NON-VOLATILE MEMORY AND RESET METHOD THEREOF

Winbond Electronics Corp....

1. A reset method of non-volatile memory, comprising:performing a first reset operation on a plurality of memory cells;
recording a plurality of first verifying currents respectively corresponding to a plurality of first failure memory cells;
performing a second reset operation on the first failure memory cells, and verifying a plurality of second failure memory cells to obtain a plurality of second verifying currents;
setting a first voltage modify flag according to a plurality of first ratios between the second verifying currents and the respectively corresponding first verifying currents; and
adjusting a reset voltage for performing the first reset operation and the second reset operation according to the first voltage modify flag.

US Pat. No. 10,714,156

APPARATUSES AND METHOD FOR TRIMMING INPUT BUFFERS BASED ON IDENTIFIED MISMATCHES

Micron Technology, Inc., ...

1. An apparatus comprising:an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal, wherein the first input stage circuit comprises a plurality of serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage, wherein each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal; and
a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components; wherein the trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

US Pat. No. 10,714,150

FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY

Micron Technology, Inc., ...

1. A memory system, comprising:multiple DRAM memory die stacked above a substrate,
wherein each die includes multiple partitions which operate independently from other partitions, and
wherein multiple vertically interconnected partitions of the stack are interconnected to form multiple respective memory vaults; and
a controller supported by the substrate and configured to interface with a first memory vault through a first group of data interface contacts, to interface with the second memory vault through a second group of data interface contacts, and to interface with at least the first and second memory vaults through a shared group of command interface contacts.

US Pat. No. 10,714,144

CORROBORATING VIDEO DATA WITH AUDIO DATA FROM VIDEO CONTENT TO CREATE SECTION TAGGING

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method, comprising:receiving, by a computer device, a video stream from a user computer device, the video stream comprising audio data and video data;
determining, by the computer device, a candidate audio tag based on analyzing the audio data;
establishing, by the computer device, an audio confidence score of the candidate audio tag based on the analyzing of the audio data;
determining, by the computer device, a candidate video tag based on analyzing the video data;
establishing, by the computer device, a video confidence score of the candidate video tag based on the analyzing of the video data;
determining, by the computer device, a correlation factor of the candidate audio tag relative to the candidate video tag;
assigning, by the computer device, a tag to a portion in the video stream based on the correlation factor exceeding a correlation threshold value and at least one of the audio confidence score exceeding an audio threshold value and the video confidence score exceeding a video threshold value; and
de-assigning the tag to the portion in the video stream based on the audio confidence score falling below the audio threshold value, the video confidence score falling below the video threshold value, and a correlation factor experiencing a delta.

US Pat. No. 10,714,143

DISTINGUISHING HEVC PICTURES FOR TRICK MODE OPERATIONS

Cisco Technology, Inc., ...

1. A method comprising:receiving a user request for a trick mode operation;
decoding a High Efficiency Video Coding (HEVC) bitstream in response to the user request for the trick mode operation starting at a Random Access Point (RAP) picture that is not a Random Access Skipped Leading (RASL) picture and is of a tier equal to K where K is an integer, wherein the RAP picture is decodable if all immediately preceding pictures in tiers 0 to K have been decoded, and wherein tier information is contained in Personal Video Recording (PVR) assistance information provided in data filed of the bitstream;
extracting, based on the tier information, reference pictures from the decoded HEVC stream; and
providing, based on the reference pictures, the requested trick mode.

US Pat. No. 10,714,142

DISK DEVICE AND MEDIA SCANNING METHOD

Kabushiki Kaisha Toshiba,...

1. A disk device, comprising:a disk;
a head that performs data read/write processing on a recording region of the disk; and
a controller that controls the media scan processing for detecting a presence or absence of a defect in a sector in the recording region of the disk in track unit,
wherein when the controller performs media scan processing on a first sector and a second sector arranged in the track, and a third sector arranged between the first sector and the second sector, the controller performs skip processing in which the controller scans the first sector and the second sector, and does not scan the third sector, and
the controller optionally changes, for each media scan processing, at least one of the number and a location of the third sector to be skipped in the media skip processing, and performs selection so that physical positions of sectors to be skipped between adjacent tracks do not overlap at the time of the change.

US Pat. No. 10,714,140

METHOD OF PLAYING SYSTEM STREAM FILES WITH DIFFERENT RECORDING FORMATS

PANASONIC INTELLECTUAL PR...

1. A non-transitory tangible recording medium in which is recorded AV data having a system stream file played by a playback device,the playback device having:
an individual decryption key that is owned individually by each of a plurality of playback devices, and
a common decryption key that is owned in common by the plurality of playback devices;
the system stream file including:
a first system stream file configured to be played back using both the individual decryption key and the common decryption key, and
a second system stream file configured to be played back using only the common decryption key among the individual decryption key and the common decryption key,
wherein whether the system stream file to be played back is the first system stream file or the second system stream file is identified by the playback device in accordance with a file extension of the system stream file.

US Pat. No. 10,714,138

PERPENDICULAR MAGNETIC RECORDING MEDIUM

FUJI ELECTRIC CO., LTD., ...

1. A perpendicular magnetic recording medium comprising:a nonmagnetic substrate; and
a magnetic recording layer on the nonmagnetic substrate, wherein:
said magnetic recording layer has a granular structure including a first magnetic crystal grain and a first nonmagnetic crystal grain boundary surrounding said first magnetic crystal grain,
said first magnetic crystal grain consists of an ordered alloy having, by atom, 30-70% Fe, 30-70% Pt and 1-25% Rh, said ordered alloy being an L10 type ordered alloy, and
said first nonmagnetic crystal grain boundary consists of carbon, boron or a combination thereof, an amount of said first nonmagnetic crystal grain boundary being, by volume, in a range of 10% to 50% of a total amount of a material of said magnetic recording layer.

US Pat. No. 10,714,137

NEAR-FIELD TRANSDUCER HAVING A PEG SURROUNDED BY A METAL APERTURE PLATE

Seagate Technology LLC, ...

1. A recording head, comprising:a waveguide core layer that delivers light from a light source to a region proximate a magnetic write pole;
a near-field transducer formed of a thin metal film deposited over the waveguide core layer, the near-field transducer comprising:
an enlarged part with two straight edges facing a media-facing surface and at obtuse angles relative to the media-facing surface;
a peg extending from the enlarged part towards the media-facing surface, and end of the peg parallel to the media-facing surface; and
a metal aperture plate at the media-facing surface, the metal aperture plate contiguously surrounding at least three sides of the end of the peg, the magnetic write pole surrounding a fourth side of the peg, the metal aperture plate shifting an electric field profile of the peg to be concentrated along a downtrack edge of the peg facing away from the write pole.

US Pat. No. 10,714,133

DATA STORAGE DEVICE CAPABLE OF OVERRIDING A SERVO COMMAND TO AVOID AN OVERCURRENT CONDITION

Western Digital Technolog...

1. A data storage device comprising:a disk;
a head;
a first actuator configured to actuate the head over the disk;
a second actuator configured to rotate the disk;
a first control circuit configured to generate a servo command; and
a second control circuit configured to:
receive the servo command from the first control circuit;
control the first actuator or the second actuator using the servo command; and
override the servo command to avoid an overcurrent condition.

US Pat. No. 10,714,132

MAGNETIC FLUX GUIDING DEVICES ALL AROUND MAIN POLE DESIGN WITHOUT LEADING SHIELD AND SIDE SHIELDS IN ASSISTED WRITING APPLICATIONS

Headway Technologies, Inc...

1. A perpendicular magnetic recording (PMR) writer, comprising:(a) a main pole (MP) having a pole tip with a leading side and a trailing side, the leading side adjoins a lead gap (LG) at an air bearing surface (ABS), and the trailing side has a track width and adjoins a write gap (WG) at the ABS, and the MP trailing side at the ABS is at a first plane that is orthogonal to the ABS;
(b) a side gap (SG) which contacts a side of the MP tip formed between the trailing side and leading side on each side of a center plane that bisects the MP tip in a direction orthogonal to the ABS and the first plane;
(c) a shield structure comprising a first trailing shield (TS) on the WG, and a second TS on the first TS and contacting the first plane on portions thereof proximate to a WG side on each side of the center plane; and
(d) a flux guiding (FG) device that is formed in each of the WG, SG, and LG and known as FGWG, FGSG, and FGLG, respectively, and wherein each of the FG devices comprises a flux guiding layer (FGL) and is configured so that a FGL magnetization in FGWG, FGSG, and FGLG flips to a direction substantially opposing a flux field in the WG, SG, and LG, respectively, when a current (Ib) of sufficient current density is applied across the WG, SG, and LG so that reluctance is increased in each of the WG, SG, and LG thereby enhancing a write field from the MP tip on a magnetic medium; and
(e) at least one of a first non-magnetic conductor (NMC1) with an inner side that adjoins a side of the FGLG that faces away from the MP leading side, and a second non-magnetic conductor (NMC2) with an inner side that adjoins a side of each FGSG that faces away from a MP tip side, and wherein NMC1 is configured to enable the current Ib to flow across the LG, and wherein NMC2 is configured to enable the current Ib to flow across each SG.

US Pat. No. 10,714,130

MAGNETIC READER SENSOR WITH SHIELD-TO-SHIELD SPACING IMPROVEMENT AND BETTER FREE LAYER-TO-SHIELD SPACING CONTROL

Headway Technologies, Inc...

1. A method of forming an MTJ or MR read sensor, comprising:providing a bottom shield layer;
sequentially forming on said bottom shield layer a reversed thin-film MTJ or MR sensor stack deposition, wherein a spacer layer is formed on said bottom shield layer, a free layer (FL) is formed on said spacer layer, a barrier layer (for an MTJ) or conducting layer (for an MR) is then formed on the FL and a pinned layer structure is formed thereon; then
patterning said sensor stack deposition in a cross-track (x) direction to remove laterally extending portions of each layer formed sequentially on said bottom shield layer and to reduce the stack width and produce symmetrically sloping sides; then
forming a first layer of insulation over said bottom shield layer and over said symmetrically sloping sides; then
forming biasing layers over said layer of insulation, said biasing layers abutting said insulation layer covering said symmetrically sloping sides; then
forming a second layer of insulation over said biasing layers; then
patterning a back end of said sensor stack deposition in a stripe-height (y) direction, reducing the height of all layers thereof and producing a sloping side thereon; then
forming an insulating refill layer covering said sloping side on said back end and extending down said sloping side and forming a horizontal portion extending horizontally rearward; then
forming an antiferromagnetic (AFM) coupling layer on said horizontal portion of said insulating refill layer, said AFM coupling layer abutting said insulating refill layer covering said sloping side; and
forming a smooth surface in which a top surface of said AFM coupling layer and said pinned layer structure are co-planar.

US Pat. No. 10,714,128

MAGNETIC WRITE HEAD WITH DUAL RETURN POLE

Western Digital Technolog...

1. A heat-assisted magnetic recording (HAMR) write head, comprising:an air-bearing surface (ABS);
a main pole extending to the ABS;
a first return pole extending to the ABS and disposed, at the ABS, between the main pole and a leading side of the magnetic write head;
a waveguide extending to the ABS and disposed, at the ABS, between the first return pole and the main pole;
a near-field transducer extending to the ABS and disposed, at the ABS, between the waveguide and the main pole; and
a second return pole disposed between the main pole and a trailing side of the magnetic write head, wherein the second return pole comprises a tapered portion adjacent to the ABS, wherein the tapered portion extends in a direction toward the main pole, and wherein a distance between the main pole and the second return pole is between approximately 600 nm and approximately 1000 nm.

US Pat. No. 10,714,121

DISTINGUISHING USER SPEECH FROM BACKGROUND SPEECH IN SPEECH-DENSE ENVIRONMENTS

VOCOLLECT, INC., Pittsbu...

1. A method of speech recognition, the method comprising:receiving at a microphone of a speech recognition device (SRD) an audio input;
identifying, via a hardware processor of the SRD which is communicatively coupled with the microphone, a vocalization of a human language in the received audio input; and
categorizing, via the hardware processor, the received vocalization of a human language, based on a speech difference between the received vocalization of human language and an audio mix which is stored in a memory of the SRD, the memory communicatively coupled with the hardware processor, as either one of:
a first vocalization originating from a user of the SRD in response to determining that an absolute value of the speech difference is less than a speech rejection threshold stored in the memory; or
a second vocalization originating from a background, in response to determining that the absolute value of the speech difference is greater than the speech rejection threshold, wherein the background speech is a non-user background speech in the vicinity of the SRD or a background environmental sound.

US Pat. No. 10,714,120

MULTISENSORY SPEECH DETECTION

Google LLC, Mountain Vie...

1. A method comprising:detecting, by data processing hardware of a mobile device, movement of the mobile device from a first pose to a second pose, the second pose corresponding to the mobile device in a talking pose proximate to a part of a user of the mobile device;
in response to detecting the movement of the mobile device from the first pose to the second pose:
initiating, by the data processing hardware, execution of an audio recording process using a microphone of the mobile device; and
notifying, by the data processing hardware, the user of the mobile device when execution of the audio recording process starts by:
generating a visual notification that indicates to the user when execution of the audio recording process starts; and
displaying the visual notification on a user interface of the mobile device, wherein the visual notification comprises a microphone graphic;
receiving, at the data processing hardware, a speech utterance of the user captured by the microphone during execution of the audio recording process; and
generating, by the data processing hardware, a transcription of the speech utterance captured by the microphone during the audio recording process.

US Pat. No. 10,714,119

COMMUNICATION DEVICE AND COMMUNICATION SYSTEM

Plantronics, Inc., Santa...

1. A communication device for a communication system, the communication device having at leastan I/O interface for connection with one or more audio sources to at least receive an input audio signal;
a user audio output;
an audio processor to provide an output audio signal to the user audio output from the input audio signal; and
a reporting module, configured to analyze the input audio signal and to determine, whether at least one acoustic safety incident is given, upon which the reporting module is configured to generate metadata of the acoustic safety incident wherein
the reporting module is further configured to capture an input audio snippet of the input audio signal upon determination of the acoustic safety incident.

US Pat. No. 10,714,117

VOICE TRIGGER FOR A DIGITAL ASSISTANT

Apple Inc., Cupertino, C...

8. An electronic device comprising:one or more processors;
a memory; and
one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for:
operating a voice trigger in a first mode;
determining whether the electronic device is in an enclosed space by detecting that one or more of a microphone and a camera of the electronic device is occluded, wherein a trigger phrase associated with the voice trigger is adapted based on the determination of whether the electronic device is in the enclosed space;
upon a determination that the electronic device is in the enclosed space, generating instructions to switch the voice trigger to a second mode; and
switching the voice trigger to the second mode based on the instructions.

US Pat. No. 10,714,113

AUDIO DECODING DEVICE, AUDIO CODING DEVICE, AUDIO DECODING METHOD, AUDIO CODING METHOD, AUDIO DECODING PROGRAM, AND AUDIO CODING PROGRAM

NTT DOCOMO, INC., Tokyo ...

1. A speech decoding device that decodes an encoded speech signal and outputs a speech signal, the speech decoding device comprising:a low frequency decoder that receives and decodes a code sequence including encoded information of a low frequency signal to obtain the low frequency signal;
a high frequency decoder that receives first information from the low frequency decoder and generates a high frequency signal based on the first information;
a high frequency temporal envelope shape determiner that determines a temporal envelope shape of the generated high frequency signal based on second information sent from an encoding device;
a high frequency temporal envelope modifier that modifies the temporal envelope shape of the generated high frequency signal based on the temporal envelope shape determined by the high frequency temporal envelope shape determiner and outputs the modified high frequency signal; and
a low frequency/high frequency signal combiner that receives the low frequency signal from the low frequency decoder, receives the high frequency signal, whose temporal envelope shape is modified, from the high frequency temporal envelope modifier and combines the low frequency signal and the high frequency signal, whose temporal envelope shape is modified, to obtain a speech signal to be output,
wherein the high frequency temporal envelope modifier modifies the temporal envelope shape of the generated high frequency signal using a high frequency signal generated in a time segment identical to that of the generated high frequency signal and outputs the modified high frequency signal, when the high frequency temporal envelope shape determiner determines the temporal envelope shape to be flat, and utilizes time envelope information of a high frequency signal determined by power of the high frequency signal generated by the high frequency decoder, during decoding of an encoded speech signal and obtaining of a speech signal.

US Pat. No. 10,714,110

DECODING DATA SEGMENTS REPRESENTING A TIME-DOMAIN DATA STREAM

Fraunhofer-Gesellschaft z...

1. An apparatus for decoding data segments representing a time-domain data stream, a data segment encoded in a time domain, a data segment encoded in a frequency domain having successive blocks of data representing successive and overlapping blocks of time-domain data samples, the apparatus comprising:a time-domain decoder for decoding the data segment encoded in the time domain;
a processor for processing the data segment encoded in the frequency domain and output data of the time-domain decoder to obtain overlapping time-domain data blocks; and
an overlap/add-combiner for combining the overlapping time-domain data blocks to obtain decoded data segments of a time-domain data stream.

US Pat. No. 10,714,109

METHODS AND APPARATUS FOR BUFFERING AND COMPRESSION OF DATA

Cirrus Logic, Inc., Aust...

1. A device, comprising:an allocation module, for determining one or more metrics of each of a plurality of data streams;
a compression module, for compressing each of the plurality of data streams and generating a plurality of compressed data streams, the compression module applying a compression ratio that varies as a function of the metrics determined by the allocation module; and
a buffer memory, for storing the plurality of compressed data streams, wherein the buffer memory comprises Y rows, each row being X bits wide, wherein X and Y are integers, and wherein data values stored in each row correspond to samples of said plurality of data streams acquired at an instance in time, wherein the compression ratios for each of the plurality of data streams are selected such that a row of the buffer memory is fully occupied with samples of said plurality of data streams acquired at an instance in time.

US Pat. No. 10,714,108

LINEAR PREDICTION COEFFICIENT CONVERSION DEVICE AND LINEAR PREDICTION COEFFICIENT CONVERSION METHOD

NTT DOCOMO, INC., Tokyo ...

1. A linear prediction coefficient conversion device that converts first linear prediction coefficients calculated at a first sampling frequency F1 to second linear prediction coefficients at a second sampling frequency F2 (where F1 calculate, on the real axis of the unit circle, autocorrelation coefficients from the power spectrum; and
convert the autocorrelation coefficients to the second linear prediction coefficients at the second sampling frequency.

US Pat. No. 10,714,106

JITTER BUFFER CONTROL, AUDIO DECODER, METHOD AND COMPUTER PROGRAM

Fraunhofer-Gesellschaft z...

1. A jitter buffer control for controlling a provision of a decoded audio content on the basis of an input audio content,wherein the jitter buffer control is configured to select a frame-based time scaling or a sample-based time scaling in a signal-adaptive manner, such that a decision whether a frame-based time scaling or a sample-based time scaling is used is adapted to the characteristics of the audio signal, and
wherein the jitter buffer control is implemented using a hardware apparatus, or using a computer, or using a combination of a hardware apparatus and a computer.

US Pat. No. 10,714,105

AUDIO FINGERPRINTING

Gracenote, Inc., Emeryvi...

1. An apparatus comprising:a vector generator to:
determine first and second groups of frequencies in a plurality of frequencies from spectral data derived from audio data, the first group including frequencies different from frequencies in the second group of frequencies, each of the frequencies of the first group being higher than each of the frequencies in the second group,
identify a first subgroup of frequencies in the first group of frequencies based on energy values of the first group, each of the frequencies of the first subgroup having energy values that are greater than energy values of other frequencies in the first group,
identify a second subgroup of frequencies in the second group of frequencies based on energy values of the second group, each of the frequencies of the second subgroup having energy values that are greater than energy values of other frequencies in the second group, and
generate a vector that assigns a first value to the frequencies in the first subgroup and assigns a second value to the frequencies in the second subgroup;
a scrambler to generate permutations of the vector, the permutations differently arranging instances of the first and second values;
a coder to generate a sequence that indicates an instance of the first value or of the second value within a corresponding permutation of the permutations; and
a fingerprint generator to generate a fingerprint of the audio data based on the sequence, wherein the generation and decoding of the fingerprint is to conserve computing resources.

US Pat. No. 10,714,104

AUDIO ENCODER AND DECODER

Dolby International AB, ...

1. A method for encoding a vector of parameters in an audio encoding system, each parameter corresponding to a non-periodic quantity, the vector having a first element and at least one second element, the method comprising:representing each parameter in the vector by an index value which may take N values;
calculating one or more symbols, the calculating including:
calculating a difference between the index value of the second element and the index value of its preceding element in the vector; and
applying modulo N to the difference;
associating each of the at least one second element with a respective symbol of the one or more symbols; and
encoding each of the at least one second element by entropy coding of the symbol associated with the at least one second element based on a probability table comprising probabilities of the symbols.

US Pat. No. 10,714,103

APPARATUS FOR ENCODING AND DECODING OF INTEGRATED SPEECH AND AUDIO

ELECTRONICS AND TELECOMMU...

1. An encoding method of an input signal performed by at least one processor, the encoding method comprising:determining a frame of the input signal whether the frame is a speech frame or an audio frame;
encoding the core band of the input signal in a speech encoder based CELP coding scheme when the frame is the speech frame, and
encoding the core band of the input signal in an audio encoder based MDCT coding scheme when the frame is the audio frame; and
generating a bitstream including the encoded core band of the input signal,
wherein the core band is a low frequency band which is not expanded in a frequency band of the input signal,
wherein a high frequency band is generated from the core band based on a frequency band expander in a decoding process, and
wherein the input signal is processed by using information for compensating a change of a frame unit between the speech frame and the audio frame when a switching occurs between the speech frame and the audio frame in a decoding process about the input signal.

US Pat. No. 10,714,099

LAYERED CODING AND DATA STRUCTURE FOR COMPRESSED HIGHER-ORDER AMBISONICS SOUND OR SOUND FIELD REPRESENTATIONS

Dolby International AB, ...

1. A method of decoding a compressed Higher Order Ambisonics (HOA) representation of a sound or sound field, the method comprising:receiving a hit stream containing the compressed HOA representation corresponding to a plurality of hierarchical layers that include a base layer and one or more hierarchical enhancement layers, wherein the plurality of layers have assigned thereto components of a basic compressed sound representation of the sound or sound field, the components being assigned to respective layers in respective groups of components,
determining a highest usable layer among the plurality of layers for decoding;
extracting a HOA extension payload assigned to the highest usable layer, wherein the HOA extension payload includes side information for parametrically enhancing a reconstructed HOA representation corresponding to the highest usable layer, wherein the reconstructed HOA representation corresponding to the highest usable layer is obtainable on the basis of transport signals assigned to the highest usable layer and any layers lower than the highest usable layer;
decoding the compressed HOA representation corresponding to the highest usable layer based on layer information, the transport signals assigned to the highest usable layer and any layers lower than the highest usable layer; and
parametrically enhancing the decoded HOA representation using the side information included in the HOA extension payload assigned to the highest usable layer.

US Pat. No. 10,714,095

INTELLIGENT ASSISTANT FOR HOME AUTOMATION

Apple Inc., Cupertino, C...

2. The user device of claim 1, wherein the one or more programs comprise further instructions for:before transmitting the plurality of commands, querying each of the plurality of electronic devices to determine a current state of each of the plurality of electronic devices.

US Pat. No. 10,714,094

VOICEPRINT RECOGNITION MODEL CONSTRUCTION

Alibaba Group Holding Lim...

1. A computer-implemented method, comprising:receiving a first voice input from a user during a first session of the user interacting with a voice recognition system of a service system that implements a particular service with a corresponding security requirement;
obtaining one or more predetermined keywords wherein the one or more predetermined keywords include at least a minimum number of required keywords, the minimum number of required keywords being based on the corresponding security requirement for training a voiceprint recognition model;
searching the first voice input to determine whether the one or more predetermined keywords occur in the first voice input;
determining, from the first voice input, that the user spoke at least one of the one or more predetermined keywords during the first session of the user interacting with the voice recognition system of the service system;
in response to determining that the user spoke at least one of the one or more predetermined keywords during the first session of the user interacting with the voice recognition system of the service system, training the voiceprint recognition model based on one or more voice segments corresponding respectively to the one or more predetermined keywords;
receiving a second voice input from the user during a second session of the user interacting with the voice recognition system of the service system; and
responsive to obtaining, prior to receiving the second voice input, all of the required keywords based on the corresponding security requirement, verifying an identity of the user based on the second voice input received during the second session using the voiceprint recognition model generated from the one or more voice segments from the first session of the user interacting with the voice recognition system of the service system.

US Pat. No. 10,714,091

SYSTEMS AND METHODS TO PRESENT VOICE MESSAGE INFORMATION TO A USER OF A COMPUTING DEVICE

OATH INC., New York, NY ...

1. A method, comprising:receiving first data associated with prior communications for a first user of a computing device, the first data comprising a plurality of person profiles including a person profile for a person referenced in a prior communication between the first user and a caller that creates a voice message for the first user;
receiving, via a computing apparatus, the voice message;
transcribing, via the computing apparatus, the voice message using the first data to provide a transcribed message; and
sending the transcribed message to the computing device for providing to the first user.

US Pat. No. 10,714,087

SPEECH CONTROL FOR COMPLEX COMMANDS

Josh.ai LLC, Denver, CO ...

1. A system, comprising:a communication interface configured to receive a user utterance;
a processor coupled to the communication interface and configured to recognize and determine an operational meaning of the received user utterance, at least in part by:
determining that a first subset of the received user utterance is associated with a first recognized input, comprising at least in part:
placing a breakpoint between every word of the received user utterance at least in part to separate sentences between breakpoints; and
removing a given breakpoint when it is at least in part determined that a candidate sentence associated with the given breakpoint is of low score quantified by a quality metric that is decreased for sentences that make less sense;
determining whether a meaning of a remaining portion of the received user utterance other than the first subset is recognized as being associated with a second recognized input; and
based at least in part on a determination that the meaning of the remaining portion of the received user utterance is recognized as being associated with said second recognized input, concluding that the received user utterance comprises a compound input comprising the first and second recognized inputs.

US Pat. No. 10,714,086

GENERATING AND TRANSMITTING INVOCATION REQUEST TO APPROPRIATE THIRD-PARTY AGENT

GOOGLE LLC, Mountain Vie...

1. A method implemented by one or more processors, comprising:receiving an initial voice input provided by a user via a client device;
performing a voice to text conversion to convert the initial voice input to initial text;
determining an intended action based on the initial text;
identifying a mandatory parameter that is stored as mandatory for the intended action;
determining that the initial text lacks specification of any value for the mandatory parameter;
in response to determining that the initial text lacks specification of any value for the mandatory parameter:
generating a natural language prompt based on the mandatory parameter, and
providing the natural language prompt as a reply to the initial voice input, the prompt being provided for presentation to the user via a user interface output device of the client device;
receiving additional voice input provided by the user in response to providing the natural language prompt;
determining a value for the mandatory parameter based on the additional voice input;
selecting a particular third-party agent from a group of third-party agents that can each perform the intended action;
transmitting a third-party invocation request that includes the value for the mandatory parameter, wherein the transmitting is to the particular third-party agent via one or more network interfaces;
receiving responsive content from the particular third-party agent in response to transmitting the intended action and the value, the receiving being via one or more of the network interfaces;
providing output that is based on the responsive content for presentation to the user;
receiving further voice input provided by the user in response to providing the output;
performing an additional voice to text conversion to convert the further voice input to further text;
transmitting the further text to the particular third-party agent;
in response to transmitting the further text to the particular third-party agent:
receiving further responsive content from the particular third-party agent, and
providing further output that is based on the further responsive content for presentation to the user;
receiving yet further voice input provided by the user in response to the further output;
determining that the yet further voice input indicates a desire to interact with another third-party agent; and
in response to determining that the yet further voice input indicates a desire to interact with another third-party agent:
transmitting, to an alternative third-party agent of the group of third party agents, an additional third-party invocation request that includes the value for the mandatory parameter.

US Pat. No. 10,714,085

TEMPORARY ACCOUNT ASSOCIATION WITH VOICE-ENABLED DEVICES

Amazon Technologies, Inc....

1. A system comprising:one or more processors; and
computer-readable media storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
receiving a first indication that a temporary association between a first account identifier of a user account and a device identifier of a voice-enabled device associated with an environment is established;
determining that a dissociation event associated with the voice-enabled device has occurred, the dissociation event representing at least a lapsing of a period of time identified for maintaining the temporary association;
dissociating the first account identifier from the device identifier based at least in part on determining that the dissociation event has occurred; and
associating a second account identifier corresponding to a default account with the device identifier, wherein the default account is associated with a system associated with the environment.

US Pat. No. 10,714,084

ARTIFICIAL INTELLIGENCE BASED SERVICE IMPLEMENTATION

ACCENTURE GLOBAL SOLUTION...

1. A system comprising:a voice call analyzer, executed by at least one hardware processor, to
receive a voice call,
analyze the voice call to generate voice data,
convert the voice data to text data,
analyze the text data to identify keywords in the text data, and
identify, based on an analysis of the identified keywords, a user of a plurality of users;
a digital converter, executed by the at least one hardware processor, to
ascertain a user assistance flow of a plurality of user assistance flows that corresponds to a determined intent of the identified user, and
cause the voice call to be transferred to a digital assistant that is executed by the at least one hardware processor,
wherein the digital assistant is to provide artificial intelligence based assistance to the identified user based on the user assistance flow that corresponds to the determined intent; and
a user profile generator, executed by the at least one hardware processor, to
ascertain a plurality of attributes for the plurality of users,
generate, based on an analysis of the plurality of attributes for the plurality of users, scores for the plurality of user assistance flows for each of the plurality of users, wherein each of the scores is determined by rating each of the attributes on a specified scale that includes a plurality of rating levels and determining, based on the rating of each of the attributes, an overall rating for an associated user assistance flow, and wherein at least one attribute of the plurality of attributes is assigned a different weight compared to another attribute of the plurality of attributes for generation of the scores; and
determine an intent for each of the plurality of users by identifying, for each of the plurality of users, a user assistance flow of the plurality of user assistance flows that corresponds to a highest score of the plurality of generated scores.

US Pat. No. 10,714,080

WFST DECODING SYSTEM, SPEECH RECOGNITION SYSTEM INCLUDING THE SAME AND METHOD FOR STORING WFST DATA

SAMSUNG ELECTRONICS CO., ...

1. A weighted finite-state transducer (WFST) decoding system, comprising:a memory configured to store WFST data; and
a WFST decoder circuit comprising a data fetch logic,
wherein the WFST data has a structure including one or more states, and one or more arcs connecting the one or more states with directivity,
the WFST data is compressed in the memory, and includes body data and header data,
the header data includes an arc index of the one or more arcs, a number of the one or more arcs, and compression information of the one or more arcs, the header data being aligned per state and stored in the memory discontinuously,
the body data includes, for each of the one or more arcs, one or more elements, the body data being continuously stored in the memory,
the compression information comprises one or more bits corresponding respectively to the one or more elements, each bit indicating for a respective element whether or not the respective element is compressed, and
the data fetch logic is configured to de-compress the WFST data using the compression information, and retrieve the WFST data from the memory.

US Pat. No. 10,714,079

METHODS AND SYSTEM FOR ANALYZING CONVERSATIONAL STATEMENTS AND PROVIDING FEEDBACK IN REAL-TIME

MOTOROLA SOLUTIONS, INC.,...

2. A method for analyzing conversational statements and providing feedback in real-time, the method comprising:receiving, by a natural-language electronic processing device, audio stream data including a natural-language statement recorded by a communication device;
converting, by a natural-language electronic processing device, the natural-language statement into a logical analysis format representation;
performing, by a natural-language electronic processing device, an automatic logical analysis on the logical analysis format representation of the natural-language statement to identify one or more candidate output resolutions and identify supplemental data that can confirm the one or more candidate output resolutions,
wherein each candidate output resolution of the one or more candidate output resolutions relates to an assessment of a factual accuracy of the natural-language statement;
accessing, by a natural-language electronic processing device, the identified supplemental data and evaluating the one or more candidate output resolutions based at least in part on the supplemental data;
eliminating at least one of the one or more candidate output resolutions based at least in part on the supplemental data;
identifying a plurality of candidate output resolutions that are not eliminated after evaluating the one or more possible output resolutions based at least in part on the supplemental data;
generating a formula identifying a criteria that will differentiate between the plurality of candidate output resolutions that are not eliminated;
generating, by a natural-language electronic processing device, a feedback message to be output by the communication device, the feedback message being indicative of the evaluation of the one or more candidate output resolutions, by converting the generated formula into a natural-language feedback message;
transmitting the natural-language feedback message as a recommended follow-up question to be displayed on the communication device;
monitoring the received audio stream data for a second natural-language statement responding to the natural-language feedback message; and
further evaluating the plurality of candidate output resolutions based on the second natural-language statement.

US Pat. No. 10,714,077

APPARATUS AND METHOD OF ACOUSTIC SCORE CALCULATION AND SPEECH RECOGNITION USING DEEP NEURAL NETWORKS

Samsung Electronics Co., ...

1. An apparatus for recognizing an audio signal, the apparatus comprising:a processor configured to:
sequentially extract audio frames of the audio signal into respective plural windows of information without overlapping of same audio frames in successive windows of information over time;
include non-zero padding frames in a window of information, of the plural windows of information, so that the window of information overlaps in time with one or more frames of an other window of information, of the plural windows of information, adjacent to the window of information;
calculate first acoustic scores of each frame of the window of information, of the plural windows of information, using a deep neural network (DNN)-based acoustic model, by inputting the window of information, to which the non-zero padding frames are included, to input layers of the DNN-based acoustic model;
recalculate second acoustic scores of the overlapping frames of the window of information based on pre-calculated acoustic scores of non-zero padding frames of the other window of information to update the first acoustic scores using the second acoustic scores with respect to the overlapping frames; and
recognize the audio signal based on the first acoustic scores of the window of information and the second acoustic scores of the overlapping frames of the window of information.

US Pat. No. 10,714,073

WIND NOISE SUPPRESSION FOR ACTIVE NOISE CANCELLING SYSTEMS AND METHODS

SYNAPTICS INCORPORATED, ...

1. An active noise cancellation system comprising:a reference sensor configured to generate a reference signal from external noise;
an error sensor configured to generate an error signal from sound sensed in a noise cancellation zone;
a feedforward noise cancellation subsystem configured to generate a first anti-noise signal using the reference signal and the error signal;
a feedback noise cancellation subsystem configured to generate a second anti-noise signal using the error signal;
a wind detection module configured to determine whether wind noise is present in the reference signal, and output a wind noise detection status; and
a wind handler module configured to control the feedforward noise cancellation subsystem and the feedback noise cancellation subsystem in accordance with the wind noise detection status and to generate an output anti-noise signal using the first anti-noise signal and the second anti-noise signal;
wherein the wind handler module is configured to disable adaptive feedback noise cancellation if wind noise is not present.

US Pat. No. 10,714,072

ON-DEMAND ADAPTIVE ACTIVE NOISE CANCELLATION

Cirrus Logic, Inc., Aust...

1. An integrated circuit for implementing at least a portion of a personal audio device, comprising:an output for providing a signal to a transducer including both a source audio signal for playback to a listener and an anti-noise signal for countering the effects of ambient audio sounds in an acoustic output of the transducer;
a user trigger input for receiving a user trigger signal indicating a user desire to update characteristics of an adaptive filter;
an error microphone input for receiving an error microphone signal indicative of the output of the transducer and the ambient audio sounds at the transducer; and
a processing circuit configured to:
implement the adaptive filter having a response that generates the anti-noise signal to reduce the presence of the ambient audio sounds in the error microphone signal;
responsive to receiving the user trigger signal, determine if undesirable ambient conditions exist such that updating characteristics of the adaptive filter in the presence of the undesirable ambient conditions would lead to the anti-noise signal having undesirable characteristics;
responsive to determining a presence of undesirable ambient conditions such that updating characteristics of the adaptive filter in the presence of the undesirable ambient conditions would lead to the anti-noise signal having undesirable characteristics, prevent updating characteristics of the adaptive filter; and
responsive to determining an absence of the undesirable ambient conditions, update characteristics of the adaptive filter.

US Pat. No. 10,714,070

SOUND ISOLATION DEVICE

1. A sound isolation device comprising at least one acoustic scatterer, wherein the at least one acoustic scatterer includes:an acoustic monopole response and an acoustic dipole response, wherein the acoustic dipole response and the acoustic monopole response of the acoustic scatterer have substantially similar resonant frequencies;
a first resonant chamber defined by a housing;
a first channel extending from a first opening defined within the housing to the first resonant chamber;
a second resonant chamber defined by the housing;
a second channel extending from a second opening defined within the housing to the second resonant chamber; and
wherein the first opening is substantially diametrically opposed to the second opening.

US Pat. No. 10,714,067

CONTROLLER FOR PRODUCING CONTROL SIGNALS

ROLI Ltd., (GB)

1. A controller for producing control signals, comprising:a pressure sensor;
a hinged input mechanism configured to:
receive input forces between a hinge point and a front end of the hinged input mechanism; and
direct said input forces towards the pressure sensor; and
a processor, configured to receive a signal from the pressure sensor indicating that the hinged input mechanism is being depressed or released and, based on the received signal, further configured to:
determine, during a time interval, a rate of change of pressure detected at the pressure sensor resulting from the input forces received between the hinge point and the front end of the hinged input mechanism; and
generate a control signal associated with the hinged input mechanism;
wherein the control signal comprises a velocity characteristic representative of a speed at which the hinged input mechanism is depressed or released, and
wherein the velocity characteristic of the control signal is based at least partly on the determined rate of change of pressure resulting from the input forces received between the hinge point and the front end of the hinged input mechanism.

US Pat. No. 10,714,066

CONTENT CONTROL DEVICE AND STORAGE MEDIUM

YAMAHA CORPORATION, Hama...

1. A content control device comprising:a plurality of controls respectively assigned to a plurality of parameters for controlling properties of a content containing sound, each of the plurality of controls outputting a first indicated value in accordance with an operation amount of the respective control; and
a processor configured to:
obtain a second indicated value;
acquire predetermined setting information for determining a range of each of the respective first indicated values of the plurality of parameters; and
set the respective first indicated values of the plurality of parameters in accordance with the second indicated value and the setting information to control the properties of the content.

US Pat. No. 10,714,064

INSTRUMENT SUPPORT STRAP WITH COOLING FEATURE

1. A cooling accessory for attachment to a strap to support a musical instrument, the cooling accessory comprising:a pouch having opposite sides;
a coolant pack held in the pouch between the opposite sides;
rear interior surface holding one side of the pouch, the rear interior surface having opposite ends;
a front exterior surface opposite the rear interior surface, the front exterior surface in contact with an interior surface of the strap; and
an attachment device on each of the opposite ends to attach the cooling accessory to the strap, wherein the side of the pouch opposite the side held by the rear interior surface is in contact with a musician when the musician wears the strap.

US Pat. No. 10,714,060

GLOVE FOR STRINGED INSTRUMENT

1. A stringed instrument glove, comprising a stringed instrument:a glove body having a palmate side, a distal side, a palm cuff area, a distal cuff area, and a wrist opening adjacent said palm cuff area and said distal cuff area;
a thumb sleeve protruding away from said glove body opposite said wrist opening, said thumb sleeve having a thumb pick affixed to a distal end and a thumb air vent located adjacent said thumb pick;
an index sleeve protruding away from said glove body opposite said wrist opening, said index sleeve having an index pick affixed to a distal end and an index air vent located adjacent said index pick;
a middle sleeve protruding away from said glove body opposite said wrist opening, said middle sleeve having a middle pick affixed to a distal end and a middle air vent located adjacent said middle pick;
a ring sleeve protruding away from said glove body opposite said wrist opening, said ring sleeve having a ring pick affixed to a distal end of each of said ring sleeves and a ring air vent located adjacent said ring pick;
a fingerless pinky sleeve;
a securement aid located on said glove body for removably fastening said glove to a user; and
a bifurcated portion located on said distal end, extending upward from said distal cuff area and terminating subjacent to said pinky sleeve;
wherein each said pick is affixed to a distal side of a respective sleeve; and
wherein said glove further comprises multiple ventilation holes disposed about said distal side thereof.

US Pat. No. 10,714,058

DECISION-BASED DATA COMPRESSION BY MEANS OF DEEP LEARNING TECHNOLOGIES

International Business Ma...

1. A method for handling data based on compressibility, wherein the method comprises:training, using sample data, a supervised learning model, wherein the training comprises determining weighting factors and bias for the supervised learning model, and wherein the sample data comprises a set of known further compressible data and a set of known non-compressible data;
evaluating, using the trained supervised learning model, a set of unclassified data;
predicting a subset of the unclassified data is non-compressible data; and
testing the prediction that the subset of unclassified data is non-compressible data by attempting to compress the subset of unclassified data, wherein:
if the subset of unclassified data compresses then the predication is false, and
if the subset of unclassified data does not compress then the prediction is true such that the supervised learning model is accurately predicting compressibility.

US Pat. No. 10,714,053

DRIVING CIRCUIT, METHOD FOR CONTROLLING LIGHT EMISSION AND DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...

1. A driving circuit, comprising one or more light emission shift registers, wherein each of the one or more light emission shift registers comprises:a first processing module electrically connected to an input signal terminal, a first clock signal terminal and a second clock signal terminal, and configured to control a signal at a first node based on a signal at the input signal terminal, a signal at the first clock signal terminal and a signal at the second clock signal terminal;
a second processing module electrically connected to a first level signal terminal, the first clock signal terminal, the second clock signal terminal, a pulse signal terminal and the first node, and configured to control a signal at a second node based on a signal at the first level signal terminal, the signal at the first clock signal terminal, the signal at the second clock signal terminal, a signal at the pulse signal terminal and the signal at the first node, wherein the second processing module comprises a first transistor and a second transistor, the first transistor is a dual-gate transistor having a control terminal electrically connected to the first node, a first terminal electrically connected to the first clock signal terminal and a second terminal electrically connected to a third node, and the second transistor has a control terminal electrically connected to the first node or the first clock signal terminal, a first terminal electrically connected to the pulse signal terminal and a second terminal electrically connected to the second node; and
an output module electrically connected to the first level signal terminal, a second level signal terminal, the first node and the second node, and configured to control a signal at an output signal terminal based on the signal at the first level signal terminal, a signal at the second level signal terminal, the signal at the first node and the signal at the second node,
wherein the first processing module comprises a third transistor, a fourth transistor, a fifth transistor, and a first capacitor,
the third transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the input signal terminal, and a second terminal electrically connected to the first node;
the fourth transistor has a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to the first node, and a second terminal;
the fifth transistor has a control terminal electrically connected to the third node, a first terminal electrically connected to the second terminal of the fourth transistor, and a second terminal electrically connected to the input signal terminal or the first clock signal terminal; and
the first capacitor has a first terminal electrically connected to the first node, and a second terminal electrically connected to the second clock signal terminal.

US Pat. No. 10,714,052

DISPLAY DEVICE

YAZAKI CORPORATION, Mina...

1. A display device comprising: a display that displays an image including an object; and a controller configured to: set color component values of respective display colors of corresponding pixels forming the image to first component values, while the displayed object is not moving, wherein the color component values are provided as R, G, and B values that indicate red, green, and blue color components, respectively; and execute, when the displayed object is displayed as moving, moving-manner correction processing by which the color component values of respective display colors of destination pixels for newly displaying the object are set to second component values, wherein the second component values are component values obtained by adding RGB correction values to the first component values, wherein the first color component values are different from the second color component values when representing the same display color, wherein in each pixel, the RGB correction values have been previously determined in common for the color component values of a corresponding display color, and the RGB correction values are set so as to be larger when corresponding to a display color of a pixel in a region of the displayed object that is relatively short in the direction of moving the displayed object and to be smaller when corresponding to a display color of a pixel in a region of the displayed object that is relatively long in the direction of the moving the displayed object.

US Pat. No. 10,714,051

DRIVING APPARATUS AND DRIVING SIGNAL GENERATING METHOD THEREOF

Au Optronics Corporation,...

1. A driving apparatus adapted for a display, comprising:a timing controller, providing an output differential voltage and having a pre-emphasis circuit, the timing controller generating a bi-direction lock signal;
at least one driver, having an equalizer, coupled to the timing controller through a first data line and a second data line and receiving a differential signal pair, the at least one driver generating at least one lock signal;
at least one switch, coupled between the first data line and the second data line, and the at least one switch being turned on or cut off according to an eye diagram detection result of the differential signal pair; and
at least one resistor, connected in series with the at least one switch between the first data line and the second data line,
wherein, according to the bi-direction lock signal, the timing controller and the at least one driver are configured to:
perform a first clock and data synchronization operation on the differential signal pair in a first time period;
set setting parameters of the output differential voltage, the pre-emphasis circuit and the equalizer according to the eye diagram detection result of the differential signal pair and an on or off state of the at least one switch, and perform a second clock and data synchronization operation on the differential signal pair in a second time period; and
drive the display according to the differential signal pair in a third time period.

US Pat. No. 10,714,050

REDUCING LATENCY IN AUGMENTED REALITY (AR) DISPLAYS

DAQRI, LLC, Los Angeles,...

1. A method comprising:receiving, by a display controller of a display device, a first stream of image pixels of a first frame of virtual content to be presented on a display of the display device, the first stream of image pixels received from a Graphics Processing Unit (GPU) that rendered the first frame based on an initial three-dimensional pose of the display device, the initial three-dimensional pose determined based on sensor data gathered by one or more sensors of the display device, the first stream of image pixels received by the display controller via a high-speed bulk interface that transfers data at least as fast as can be consumed by the display;
converting, by the display controller, each respective image pixel in the stream of image pixels as the respective image pixel is received from the GPU, each respective image pixel converted from a first data format used to transmit the first stream of image pixels via the high-speed bulk interface to a second data format that is compatible for display by the display, wherein each respective image pixel is converted without any portion of the first frame of virtual content being buffered by the display controller;
after each image pixel is converted into the second data format, storing the respective image pixel in one of a plurality of pixel cells of the display, wherein at least a first pixel of the first stream of pixels of the first frame is stored in a pixel cell of the display while a second pixel of the first stream of pixels of the first frame is being converted into the second data format by the display controller; and
in response to the first stream of image pixels of the first frame being converted into the second data format and stored in the pixel cells of the display, causing the display to present the first frame.

US Pat. No. 10,714,048

FLEXIBLE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A flexible display device, comprising: a main flexible display panel and at least one auxiliary flexible display panel stacked on the main flexible display panel, wherein:the main flexible display panel comprises a plurality of main pixel units spaced apart from each other, the auxiliary flexible display panel comprises a plurality of auxiliary pixel units spaced apart from each other, and orthographic projections of the auxiliary pixel units onto the main flexible display panel overlap with the main pixel units;
the main flexible display panel is configured to, in the case that the flexible display device is stretched, enable at least a part of an orthographic projection of each main pixel unit of the main flexible display panel onto the auxiliary flexible display panel to be arranged between two adjacent auxiliary pixel units of the auxiliary flexible display panel, and/or
the auxiliary flexible display panel is configured to, in the case that the flexible display device is stretched, enable at least a part of an orthographic projection of each auxiliary pixel unit of the auxiliary flexible display panel onto the main flexible display panel to be arranged between two adjacent main pixel units of the main flexible display panel.

US Pat. No. 10,714,039

DISPLAY DEVICE AND DATA TRANSMISSION METHOD IN DISPLAY DEVICE

SAKAI DISPLAY PRODUCTS CO...

1. A display device, comprising:a display panel having a display region constituted by a plurality of pixels; and
a signal processing section configured to perform prescribed signal processing on input data including pixel values of the respective plurality of pixels for generating first output data for displaying an input image based on the input data in the display region, wherein
the signal processing section includes:
a receiving section;
a transmitting section configured to transmit, to the receiving section, a data signal based on the input data or a specified data signal in synchronization with a clock signal; and
a controller connected to the receiving section and the transmitting section,
at a previous stage prior to displaying the input image in the display region, the controller
issues, to the transmitting section, a first instruction to transmit a first data signal having a specific pattern with a phase difference from the clock signal set to a first phase difference,
reads, from the receiving section, a first received data signal corresponding to a data signal received by the receiving section from the transmitting section having received the first instruction,
performs first determination based on the first data signal and the first received data signal as receipt result determination whether or not the data signal transmitted by the transmitting section has been able to be correctly received by the receiving section, and
determines, based on a result of the first determination, a set phase difference corresponding to a phase difference from the clock signal employed in transmitting the data signal based on the input data.

US Pat. No. 10,714,037

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a display unit in which a plurality of sub-pixels are arranged in a matrix along row and column directions; and
a signal processor configured to output output signals for causing the display unit to display an image based on input signals for the image in which pixel data including three colors of red, green, and blue is arranged in a matrix,
wherein the sub-pixels comprise a first sub-pixel for red, a second sub-pixel for green, a third sub-pixel for blue, and a fourth sub-pixel for white,
wherein either the first sub-pixel or the third sub-pixel is interposed between the second sub-pixel and the fourth sub-pixel arranged in one direction of the row direction and the column direction,
wherein the signal processor is configured to output the output signals to assign, to a set of the sub-pixels included in the display unit, color components assigned to two pieces of the pixel data arranged in the one direction in the input signals,
wherein the set of the sub-pixels is made up of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel arranged along the row direction, and
wherein the signal processor is configured to assign a first color component to the fourth sub-pixel and second color components to the first sub-pixel, the second sub-pixel, and the third sub-pixel, the first color component being a part or the whole of a white component included in one piece of the pixel data among the color components included in the two pieces of the pixel data, the second color components being components other than the first color component of the color components included in the two pieces of the pixel data,
wherein scanning for driving the sub-pixels in the display unit is performed along the column direction,
wherein white at the highest luminance reproducible by a combination of the first sub-pixel, the second sub-pixel, and the third sub-pixel is higher in luminance than white at the highest luminance reproducible by the fourth sub-pixel,
wherein the first color component is a part of white component included in one of the two pieces of the pixel data arranged in the row direction in the input signals, the one piece of the pixel data being closer to an arrangement position in the row direction of the fourth sub-pixel in the set of the sub-pixels,
wherein the colors of the sub-pixels are arranged in a staggered manner,
wherein the signal processor is configured to, when the signal processor receives the input signals including the one piece of the pixel data and another piece of the pixel data next to the one piece of the pixel data in the row direction each piece of which is pixel data for causing a corresponding pixel to be relatively bright, assign color components not included in the first color component among the color components included in the one piece of the pixel data to the first sub-pixel, the second sub-pixel, and the third sub-pixel located corresponding to the other piece of the pixel data, and
wherein the signal processor is configured to, when the signal processor receives the input signals including the one piece of the pixel data for causing a corresponding pixel to be relatively bright and the other piece of the pixel data for causing a corresponding pixel to be relatively dark, assign the color components not included in the first color component among the color components included in the one piece of the pixel data to the first sub-pixel, the second sub-pixel, and the third sub-pixel aligned, in a direction of the scanning, with the fourth sub-pixel assigned the first color component.

US Pat. No. 10,714,036

ELECTRONIC DEVICE, DISPLAY DEVICE AND DISPLAY CONTROL METHOD

Japan Display Inc., Mina...

1. An electronic device comprising:a display panel including a plurality of pixels arranged in a matrix; and
a correction circuit configured to determine gray levels of the pixels according to a gray level of a first frame, a gray level of a second frame and positions of the pixels in the matrix, wherein
the correction circuit includes look-up tables according to positions of some pixels among the pixels in the matrix, and
each of the look-up tables indicates a gray level of a post-correction video signal with respect to the gray level of the first frame and the gray level of the second frame.

US Pat. No. 10,714,035

DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a timing controller configured to receive an image signal from an external source, identify a color pattern of the image signal and set an output enable value corresponding to the identified color pattern, wherein the color pattern is identified based on whether the image signal comprises each of a plurality of colors and the output enable value comprises a first output enable value when the color pattern is a monochromatic pattern and a second output enable value different from the first output enable value when the color pattern is a white pattern; and
a scan driver configured to receive the output enable value and generate a first scan signal having a first turn-on signal and a second scan signal adjacent to the first scan signal and having a second turn-on signal,
wherein the scan driver adjusts an interval between the first turn-on signal and the second turn-on signal based on the output enable value.

US Pat. No. 10,714,034

DISPLAY DEVICE, CONTROL CIRCUIT OF DISPLAY PANEL, AND DISPLAY METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A display method for a display panel, comprising:determining a current display mode of the display panel; and
determining whether or not to subject a to-be-displayed image on the display panel to color enhancement in accordance with at least one of the current display mode of the display panel and an image parameter of the to-be-displayed image,
wherein determining whether or not to subject the to-be-displayed image on the display panel to the color enhancement in accordance with at least one of the current display mode of the display panel and the image parameter of the to-be-displayed image comprises:
in the case that the current display mode of the display panel is a first display mode, not subjecting the to-be-displayed image on the display panel to the color enhancement, wherein in the case that the display panel is in the first display mode, power consumption of the display panel is smaller than a predetermined threshold.

US Pat. No. 10,714,032

GENERATING QUINCUNX VIDEO STREAMS FOR LIGHT MODULATING BACKPLANES WITH CONFIGURABLE MULTI ELECTRODE PIXELS

Syndiant, Inc., Dallas, ...

1. A method to generate a quincunx video stream from a high resolution video stream having a plurality of high resolution video frames, the method comprising:generating a first first-type quincunx field having a plurality quincunx pixels, from a first high resolution video frame having a plurality of high resolution pixels, wherein each quincunx pixel in the first first-type quincunx field has an associated pixel in the first high resolution video frame;
calculating each quincunx pixel of the first first-type quincunx field using smoothing filter and a pixel block containing high resolution pixels including the associated pixel;
generating a first second-type quincunx field from a second high resolution video frame.

US Pat. No. 10,714,031

DISPLAY DEVICE

Japan Display Inc., Mina...

2. A display device comprising:a display portion that is provided on a thin-film transistor (TFT) substrate and that comprises pixel capacitors and pixel transistors included in a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, a plurality of scan lines each coupled to some of the pixels arranged in the first direction, and a plurality of video signal lines each coupled to some of the pixels arranged in the second direction; and
a driver that is provided on the TFT substrate and that is configured to supply video signals to the video signal lines and to control the pixel transistors to be on and off through the scan lines, wherein
the pixel transistors comprise:
first pixel transistors that are p-channel metal-oxide semiconductor (PMOS) transistors coupled between the video signal lines and the pixel capacitors; and
second pixel transistors that are n-channel metal-oxide semiconductor (NMOS) transistors coupled in parallel to the first pixel transistors,
the scan lines comprise:
first scan lines coupled to gates of the first pixel transistors; and
second scan lines coupled to gates of the second pixel transistors, and
the driver comprises:
a first shift register configured to generate first scan signals to be sequentially supplied to the first scan lines at intervals of a predetermined period; and
a second shift register configured to generate second scan signals to be sequentially supplied to the second scan lines at intervals of the predetermined period, wherein
a high potential of the first scan signals is higher than a voltage upper limit value of the video signals supplied to the video signal lines,
a low potential of the first scan signals is equal to or lower than a middle value of a potential difference between a voltage upper limit value and a voltage lower limit value of the video signals supplied to the video signal lines,
a low potential of the second scan signals is lower than the voltage lower limit value of the video signals supplied to the video signal lines, and
a high potential of the second scan signals is equal to or higher than the middle value of the potential difference between the voltage upper limit value and the voltage lower limit value of the video signals supplied to the video signal lines.

US Pat. No. 10,714,030

DISPLAY DEVICE AND APPARATUS, DISPLAY CONTROL METHOD AND STORAGE MEDIUM

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising a first substrate, a first dimming layer, a light-emitting layer, a second dimming layer and a second substrate which are laminated in sequence; wherein,the first dimming layer is configured to control the light emitted from the light-emitting layer and incident onto the first dimming layer to present one of the following two states:
being reflected but not transmitted into the first dimming layer; and
being transmitted and emergent from one side where the first substrate lies;
the second dimming layer is configured to control the light emitted from the light-emitting layer and incident onto the second dimming layer to present one of the following two states:
being reflected but not transmitted into the second dimming layer; and
being transmitted and emergent from one side where the second substrate lies;
wherein the first dimming layer and the second dimming layer each comprises a dimming medium for adjusting a light emergent direction;
the dimming medium comprises an electric deflection material, one side of the light-emitting layer close to the first dimming layer and the other side of the light-emitting layer close to the second dimming layer each is provided with a common electrode, one side of the first substrate close to the first dimming layer is provided with at least one pair of bottom electrodes, and one side of the second substrate close to the second dimming layer is provided with at least one pair of the bottom electrodes; and
the electric deflection material comprises graphene oxide.

US Pat. No. 10,714,029

DISPLAY DEVICE HAVING A PLURALITY OF SUBPIXEL ELECTRODES ARRANGED IN DIFFERENT DIRECTIONS

Japan Display Inc., Toky...

1. A display device comprisinga display unit having a display surface on which a plurality of pixels are arranged in row and column directions, wherein
each of the pixels includes a plurality of subpixels having different colors,
subpixels included in the pixels include a first subpixel and a second subpixel, the first subpixel including an electrode having an opening with a longitudinal direction along a first direction, the second subpixel including an electrode having an opening with a longitudinal direction along a second direction,
the first direction and the second direction are directions along the display surface and are different from the row and column directions,
the longitudinal directions of the openings of all of the subpixels that are arranged in a third direction are identical,
the number of subpixels constituting one color pattern in a fourth direction is 2?,
the number of subpixels in which the first subpixels and the second subpixels arranged in the fourth direction constitute one cycle is 4?,
at least two of the first subpixels, having the first direction, are consecutively arranged in the fourth direction,
at least two of the second subpixels, having the second direction, are consecutively arranged in the fourth direction,
the third direction is one of the row and column directions, and the fourth direction is the other direction of the row and column directions,
the number of the first subpixels with odd numbers, the number of the first subpixels with even numbers, the number of the second subpixels with odd numbers, and the number of the second subpixels with even numbers when counted from one end side in the fourth direction within the one cycle are equal to one another, and
? is a natural number.

US Pat. No. 10,714,026

DISPLAY DEVICE AND CONTROL METHOD OF DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:a plurality of light sources of different luminous colors;
a first substrate;
a second substrate opposed to the first substrate;
a liquid crystal layer interposed between the first and second substrates, to which light from the light sources enters;
a display area on which an image is displayed; and
a drive circuit configured to control quantity of light from each of the light sources on the basis of analyzation results of a signal value corresponding to a pixel in the display area used to display the image and a lighting time of each of the light sources, wherein
the light sources are arranged on a side surface of a display panel including the first substrate, the second substrate, and the liquid crystal layer, and
the first and second substrates have optical transparency.

US Pat. No. 10,714,022

INFORMATION PROCESSING APPARATUS AND PROGRAM

SONY CORPORATION, Tokyo ...

1. An electronic device comprising:a battery configured to supply power; and
circuitry configured to
detect brightness and output an illuminance value corresponding to the detected brightness;
derive a luminance set value for controlling a light signal setting luminance of a light source based on the illuminance value corresponding to the detected brightness and one luminance level set by a user among a plurality of luminance levels, wherein the luminance set value is derived by deriving a slope specific to the one luminance level, multiplying the slope by the illuminance value, and adding a lower limit of the luminance set value specific to the one luminance level, wherein the slope is computed based on a difference between the lower limit of the luminance set value and a luminance set value determined in advance to correspond to the one luminance level and a difference between the illuminance value and a minimum illuminance value corresponding to the lower limit of the luminance set value;
derive power consumption consumed from the battery in the light source based on the luminance set value; and
control a display to display information relating to the power consumption, the luminance set value and the one luminance level set among the plurality of luminance levels.

US Pat. No. 10,714,021

VOLTAGE VALUE SETTING DEVICE AND METHOD

Samsung Display Co., Ltd....

1. A voltage value setting device, comprising: a test control unit configured to provide a temporary black grayscale voltage value and a temporary transistor off voltage value to a display device; and a luminance measurement unit configured to measure a luminance of a black grayscale that the display device displays based on the temporary black grayscale voltage value and the temporary transistor off voltage value, wherein, when the measured luminance of the black grayscale is lower than a black luminance threshold, the test control unit provides the display device with a black grayscale voltage value, set by adding a first margin value to the temporary black grayscale voltage value, and a transistor off voltage value, set by adding a second margin value to the temporary transistor off voltage value; andwherein, when the measured luminance is equal to or higher than the black luminance threshold, the test control unit resets the temporary black grayscale voltage value by adding a first delta value thereto and resets the temporary transistor off voltage value by adding a second delta value thereto.

US Pat. No. 10,714,019

BRIGHTNESS COMPENSATION METHOD FOR DISPLAY APPARATUS, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A brightness compensation method for a display apparatus, the display apparatus comprising n rows of display units, where n is an integer no less than 2, wherein the brightness compensation method comprises: for each row of display units,turning on the row of display units S times during a display time of one frame of image;
inputting, to each display unit in the row of display units, a pixel data signal of the frame of image corresponding to the display unit, when the row of display units are turned on for the i-th time; and
inputting a compensation signal to a to-be-compensated display unit in the row of display units, and controlling other display unit than the to-be-compensated display unit in the row of display units to present black, when the row of display units are turned on for each time other than the i-th time;
wherein both S and i are integers, S?2, 1?i?S; for every two adjacent rows of display units, a time interval between same turning-ons of the latter row and the former row is the same;
wherein S equals to 3;
a time interval t1 between the first turning-on and the second turning-on of the row of display units equals to

a time interval t2 between the second turning-on and the third turning-on of the row of display units equals to

where L1, L2 and L3 are brightness values respectively outputted by a first display unit, a second display unit, and a third display unit in the case that the first display unit, the second display unit and the third display unit are applied with a same pixel data, respectively, and L1>L2>L3, T is the display time of one frame of images, the second display unit is the to-be-compensated display unit in the second turning-on, the third display unit is the to-be-compensated display unit in the second turning-on and the third turning-on, and the first display unit is other display unit than the to-be-compensated display unit.

US Pat. No. 10,714,015

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

SHENZHEN CHINA STAR OPTOE...

1. An organic light emitting diode (OLED) display device, comprising:a plurality of scan lines configured to receive a scan signal;
a plurality of data lines configured to receive a data signal;
a source driver chip connected with the data lines through a plurality of first connection lines; and
a gate driver chip connected with the scan lines through a plurality of second connection lines, wherein the source driver chip and the gate driver chip are arranged on a same side of the OLED display device, and the first connection lines and the second connection lines are led from a side of source driver chip;
wherein a plurality of first terminals of the second connection lines are connected with the gate driver chip, and a plurality of second terminals of the second connection lines are connected with a plurality of first terminals of the scan lines;
wherein the gate driver chip comprises a plurality of gate driving units having at least one primary gate driving unit and at least one secondary gate driving unit, and the at least one primary gate driving unit and the at least one secondary gate driving unit are symmetrically arranged; and
wherein the scan lines are arranged at a horizontal direction and an extension direction of the second connection lines inclines to the scan lines at an acute angle in a display area, terminals of the second connection lines are connected with terminals of the scan lines through via holes in the display area, the via holes are vertically arranged with each other, the via holes are formed on a same edge of the display area along a same vertical axis, and the same vertical axis is perpendicular to the scan lines.

US Pat. No. 10,714,013

WIRELESS DISPLAY SCAN LINE CONTROL

A.U. VISTA, INC., Milpit...

1. A display panel, comprising:a substrate defining a display area thereon, and having a first surface and a second surface opposite to each other;
a pixel structure disposed on the first surface of the substrate and corresponding to the display area, the pixel structure comprising a plurality of pixels arranged in an array;
a receiver antenna structure disposed on the substrate and corresponding to the pixel structure, configured to provide data signals to the pixels, wherein the receiver antenna structure comprises a plurality of receiver antennas; and
a transmitter antenna structure facing the second surface of the substrate and spatially separated from the receiver antenna structure, configured to transmit wireless signals to the receiver antenna structure, wherein the transmitter antenna structure comprises a plurality of transmitter antennas one-to-one corresponding to the receiver antennas;
wherein each of the receiver antennas corresponds to a corresponding hole formed on the substrate.

US Pat. No. 10,714,012

DISPLAY DEVICE, ARRAY SUBSTRATE, PIXEL CIRCUIT AND DRIVE METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit, comprising a reset sub-circuit, a drive control sub-circuit, a power supply sub-circuit, a storage sub-circuit, a drive sub-circuit, and a light-emitting element, whereinthe reset sub-circuit is respectively coupled to a first scanning terminal, a reset terminal, a second scanning terminal, a reference power source terminal, a first control point and a second control point, and is configured to write an input voltage of the reset terminal into the first control point based on a scanning signal of the first scanning terminal and to write an input voltage of the reference power source terminal into the second control point based on a scanning signal of the second scanning terminal;
the drive control sub-circuit is respectively coupled to a third scanning terminal, a data terminal and the first control point, and is configured to write an input voltage of the data terminal into the first control point based on a scanning signal of the third scanning terminal;
the power supply sub-circuit is respectively coupled to a first power source terminal, the second scanning terminal, the second control point, a third control point and a fourth control point, and is configured to supply a voltage of the first power source terminal to the second control point based on the scanning signal of the second scanning terminal and to enable the third control point to communicate with the fourth control point;
the storage sub-circuit is respectively coupled to the first control point and the second control point, and is configured to store a voltage of the first control point and a voltage of the second control point;
the drive sub-circuit is respectively coupled to the first control point, the second control point and the third control point, and is configured to discharge electricity under the control of the voltage of the first control point and the voltage of the second control point; and
the light-emitting element is respectively coupled to the fourth control point and a second power source terminal, and is configured to emit light under the control of a voltage of the fourth control point,
wherein the reset sub-circuit comprises,
a first transistor, wherein a control electrode of the first transistor is coupled to the first scanning terminal, a first electrode of the first transistor is coupled to the reset terminal, and a second electrode of the first transistor is coupled to the first control point, and
a second transistor, wherein a control electrode of the second transistor is coupled to the second scanning terminal, a first electrode of the second transistor is coupled to the reference power source terminal, and a second electrode of the second transistor is coupled to the second control point,
wherein the drive sub-circuit comprises:
a third transistor, wherein a control electrode of the third transistor is coupled to the third scanning terminal, and a first electrode of the third transistor is coupled to the data terminal; and
a fourth transistor, wherein a first electrode of the fourth transistor is coupled to a second electrode of the third transistor, and a control electrode of the fourth transistor is coupled to a second electrode of the fourth transistor and then is coupled to the first control point,
wherein the second is the N-type transistor, and the first transistor, the third transistor and the fourth transistor are P-type transistors,
wherein in a reset of the pixel circuit, the third and the fourth transistor are configured to be turned off, and the first transistor and the second transistor are configured to be turned on so that the input voltage of the reset terminal is written into the first control point and the input voltage of the reference power source terminal is written into the second control point.

US Pat. No. 10,714,000

DISPLAY DEVICE, METHOD FOR CONTROLLING THE SAME, WEARABLE DEVICE

BEIJING BOE DISPLAY TECHN...

1. A display device, comprising:an organic light-emitting structural layer;
a first and a second control assembly at both sides of the organic light-emitting structural layer; and
a control circuit,
wherein the first control assembly comprises a first color filter layer and a first control electrode layer arranged on the first color filter layer, and the first color filter layer directly contacts both the organic light-emitting structural layer and the first control electrode layer, the second control assembly comprises a second color filter layer and a second control electrode layer arranged on the second color filter layer, and the second color filter layer directly contacts both the organic light-emitting structural layer and the second control electrode layer,
the first color filter layer comprises a plurality of first color filter regions and a plurality of first light-transmissible regions arranged alternately, the second color filter layer comprises a plurality of second color filter regions and a plurality of second light-transmissible regions arranged alternately,
each of the plurality of first color filter regions is arranged to correspond to one of the plurality of second light-transmissible region, and each of the plurality of second color filter regions is arranged to correspond to one of the plurality of first light-transmissible region,
the first control electrode layer comprises a plurality of first electrodes and a plurality of second electrodes arranged alternately, each of the plurality of first electrodes directly contacts one or two of the plurality of second electrodes,
the second control electrode layer comprises a plurality of third electrodes and a plurality of fourth electrodes arranged alternately, each of the plurality of third electrodes directly contacts one or two of the plurality of fourth electrodes,
each of the plurality of first electrodes is arranged on one of the plurality of first color filter regions corresponding to the each of the plurality of first electrodes and light transmittance of the each of the plurality of first electrodes is changeable under an effect of a first voltage,
each of the plurality of second electrodes is arranged on one of the plurality of first light-transmissible regions corresponding to the each of the plurality of second electrodes and light transmittance of the each of the plurality of second electrodes is changeable under an effect of a third voltage,
each of the plurality of third electrodes is arranged on one of the plurality of second color filter regions corresponding to the each of the plurality of third electrodes and light transmittance of the each of the plurality of third electrodes is changeable under an effect of a fifth voltage,
each of the plurality of fourth electrodes is arranged on one of the plurality of second color filter regions corresponding to the each of the plurality of third electrodes and light transmittance of the each of the plurality of fourth electrodes is changeable under an effect of a seventh voltage, and
the control circuit is connected to the plurality of first electrodes, the plurality of second electrodes, the plurality of third electrodes, and the plurality of fourth electrodes, and is configured to apply the first voltage to the seventh voltage to the plurality of first electrodes, the plurality of second electrodes, the plurality of third electrodes, and the fourth electrodes, respectively, so as to control the light transmittance of the first electrodes, the light transmittance of the second electrodes, the light transmittance of the third electrodes, and the light transmittance of the fourth electrodes, respectively.