1. A method for detecting potential for glitch failures in a digital integrated circuit, said method being embodied as a set of computer instructions stored on computer readable media, said computer instructions, when loaded into a computer, causing the computer to perform the steps of said method, said detection being performed on a model of said digital integrated circuit to be fabricated, said model comprising a multiplicity of combinational logic circuits, each of said logic circuits having a multiplicity of inputs and one output, each of said inputs and output taking either the logic value 0, or the logic value 1, or a symbolic value indicating logic value transition from 0 to 1, or a symbolic value indicating logic value transition from 1 to 0, said detection being performed for the purpose of ensuring error-free operation of said digital integrated circuit to be fabricated, the method comprising:analyzing, for each of said logic circuits, whether any path from an input of said logic circuit to the output of said logic circuit has the characteristic that its delay is either unmeasured or that the amount of said delay would cause a value change from said input to propagate to said output later than the time at which said output value change is intended to be observed or intended to be captured in a storage element connected to said output, a path with said characteristic being termed an untimed path;

classifying any logic circuit from said multiplicity of logic circuits to be free of glitch failure if said logic circuit has no untimed path;

determining from said multiplicity of logic circuits in said integrated circuit model a subset of logic circuits, each logic circuit in said subset having untimed paths that all emanate from a single input of said logic circuit, said subset being termed single-driver logic cones;

determining a subset of said single-driver logic cones, each logic circuit in said subset having no pair of untimed paths that converge with different inversion parity, said subset being termed single-driver glitch-free logic cones, and classifying each logic circuit in said subset to be free of glitch failure;

determining a subset of said single-driver logic cones, each logic circuit in said subset not belonging to said single-driver glitch-free logic cones, terming said subset single-driver potentially-glitchy logic cones;

determining from said multiplicity of logic circuits in said integrated circuit model a subset of logic circuits, each logic circuit in said subset having more than one input from which untimed paths emanate, said subset being termed multi-driver logic cones;

performing Boolean analysis for each logic circuit in said multi-driver logic cones to determine if logic value transitions on two or more inputs to said logic circuit can simultaneously propagate along untimed paths in said logic circuit to the output of said logic circuit, said logic circuit being classified as having potential for glitch failure if said simultaneous propagation is determined to be possible, said logic circuit being termed multi-driver glitchy logic cone, otherwise said logic circuit being termed multi-driver glitch-free logic cones if said simultaneous propagation is deemed to not be possible;

optionally removing from said multi-driver glitch-free logic cones any logic circuit that does not have two untimed paths emanating from a single input to said logic circuit, said two untimed paths converging with different inversion parities;

performing Boolean analysis for each logic circuit in said single-driver potentially glitchy logic cones or in said multi-driver glitch-free logic cones to determine if logic value transitions on a single input to said logic circuit can simultaneously propagate along two or more untimed paths in said logic circuit to the output of said logic circuit, at least two of said two or more untimed paths converging with different inversion parity, said logic circuit being classified as having potential for glitch failure if said simultaneous propagation is determined to be possible, said logic circuit being termed single-driver glitchy logic cone, otherwise said logic circuit being termed glitch-free if said simultaneous propagation is deemed to not be possible;

reporting all logic circuits from said multiplicity of logic circuits in said integrated circuit model, which are not determined to be glitch free, as erroneous logic circuits requiring correction, said erroneous logic circuits being termed glitchy logic cones;

and, if all logic circuits from said multiplicity of logic circuits in said integrated circuit model are determined to be glitch free, providing said error-free integrated circuit model to a fabrication facility to fabricate an error-free integrated circuit.