US Pat. No. 10,484,097

COMMUNICATION REPEATER SYSTEM AND METHOD

Kabushiki Kaisha Tashiba,...

1. A communication repeater system comprising:a plurality of radio frequency units which correspond to base station systems and convert a radio signal from the corresponding base station systems into a digital signal and transmit the digital signal, the base station systems having mutually independent reference clocks for a transmission and reception switching timing at which transmission and reception of an uplink signal and a downlink signal are switched by time division,
a plurality of slave station devices, and
a master station device that receives the digital signal from the radio frequency units and establishes communication with a mobile communication terminal device via the slave station devices, the communication repeater system that repeats communication between the mobile communication terminal device and each of the base station systems via the slave station devices, wherein
at least one of the radio frequency units, the master station device, and the slave station devices includes:
a learning-signal input port, and
first processor configured to generate a reference transmission and reception switching timing signal based on a learning signal input to the learning-signal input port, and set the reference transmission and reception switching timing signal as a reference transmission and reception switching timing; and
the rest of the radio frequency units, the master station device, and the slave station devices each includes a second processor configured to correct a variation in the transmission and reception switching timing in accordance with the reference transmission and reception switching timing.

US Pat. No. 10,484,096

RELAY APPARATUS AND RELAY METHOD FOR PASSIVE OPTICAL NETWORK

LIGHTWORKS TECHNOLOGY INC...

1. A relay apparatus for a passive optical network which relays optical signals of an optical line terminal (OLT) and an optical network terminal (ONT) using a pair of optical transceivers, the relay apparatus comprising:a signal detector that detects presence or absence of an upstream burst signal earlier than an electrical signal generation preparation time of the optical transceiver connected with the ONT;
a burst mode clock data recovery (BCDR) unit that recovers a clock and data from an upstream burst signal received to the optical transceiver and converted into an electrical signal by an optical-electrical conversion function;
a clock data recovery (CDR) unit that recovers an OLT clock and data from a downstream continuous signal received by the optical transceiver connected to the OLT and converted into an electrical signal through an optical-electrical conversion function;
an asynchronous buffer unit that stores an upstream burst signal using the clock recovered by the BCDR unit as an input clock and outputs the stored signal using the clock recovered by the CDR unit as an output clock; and
a control unit that proactively generates an upstream burst frame preamble in accordance with the OLT clock recovered by the CDR unit when the upstream burst signal is detected by the signal detector, selects upstream burst frame data subsequent to the upstream burst frame preamble proactively generated when the recovered upstream burst frame data is stored in the asynchronous buffer unit from the asynchronous buffer unit to provide the selected upstream burst frame data to the optical transceiver connected with the OLT according to the OLT clock.

US Pat. No. 10,484,095

COMMUNICATIONS RELAY SATELLITE WITH A SINGLE-AXIS GIMBAL

The Aerospace Corporation...

1. A satellite configured to simultaneously receive and transmit data in space, comprising:a receiver configured to receive an incoming beam transmitted from a source along a receive vector between the source and the receiver;
an attitude-control system configured to rotate the satellite about an axis parallel to the receive vector;
a transmitter configured to generate a transmit beam along a transmit vector; and
a gimbal having a single rotation axis, the single rotation axis of the gimbal is substantially perpendicular to the receive vector, wherein
the gimbal is configured to rotate a transmit vector using a mirror attached to the gimbal about the single rotation axis that is substantially perpendicular to the receive vector, and
the receiver comprises an optical receiver configured to receive the incoming beam, and optically amplify the incoming beam prior to converting the incoming beam to an electronic signal.

US Pat. No. 10,484,094

OPTICAL SIGNAL TRANSMISSION SYSTEM, A METHOD FOR TRANSMITTING A PLURALITY OF OPTICAL SIGNALS, AND A METHOD FOR MAKING A PHOTONIC DEVICE

Macquarie University, No...

1. An optical signal transmission system comprising:a multimode optical fiber link for transmission of a plurality of optical signals in a plurality of spatial modes supported by the multimode optical fiber link; and
a spatial mode add drop multiplexer comprising a multimode optical fiber input optically coupled to the multimode optical fiber link, a multimode optical fiber output optically coupled to the multimode optical fiber link, and a glass photonic chip comprising a waveguide network comprising a multimode waveguide input at which the multimode optical fiber input in optically coupled and a multimode waveguide output at which the multimode fiber output is optically coupled, wherein the spatial mode add drop multiplexer is configured for at least one of coupling into the multimode optical fiber link an optical signal of the plurality of optical signals into a spatial mode of the plurality of spatial modes and selectively coupling out of the multimode optical fiber link the optical signal of the spatial mode.

US Pat. No. 10,484,093

OPTICAL INTERPOSER FOR ARRAY ANTENNAS

Precision Optical Transce...

1. A method for feeding a plurality of antenna elements of an array antenna, comprising:receiving at a photonic substrate at least one transmit modulated optical carrier (TMOC) signal;
communicating the TMOC signal to an array level photonic integrated circuit (ALPIC) disposed on the photonic substrate;
using the ALPIC to extract a plurality of transmit element-level optical carrier (ELOC) signals from the TMOC;
using a plurality of optical waveguides to optically distribute the plurality of transmit ELOC signals from the ALPIC to a plurality of conversion locations distributed on the photonic substrate;
using photodetectors respectively provided at each of the plurality of conversion locations to convert each of the transmit ELOC signals to a transmit element-level modulated radio frequency (ELMRF) signal;
coupling the transmit ELMRF signal from each photodetector respectively to one of the plurality of antenna elements;
performing at least one antenna control operation in the optical domain to selectively cause a variation in at least one of a phase and an amplitude in at least one of the plurality of transmit ELMRF signals; and
communicating at least one antenna control signal for specifying the antenna beam control operation from a remote location to a local control element using a common optical fiber through which the TMOC signal is also communicated.

US Pat. No. 10,484,091

LIGHT-BASED FIDUCIAL COMMUNICATION

OSRAM SYLVANIA Inc., Wil...

1. A luminaire comprising:a plurality of panels, each panel associated with one or more solid-state light sources, wherein the one or more solid-state light sources are configured to produce light; and
at least one driver configured to:
control the one or more solid-state light sources to transmit light through the plurality of panels at varying light intensities to display a first fiducial pattern recognizable by a mobile computing device, wherein the first fiducial pattern represents position information;
detect an error in the display of the first fiducial pattern by monitoring electrical current to the one or more solid-state light sources in each of the plurality of panels, wherein an error is detected when a difference between the monitored electrical current and a stored electrical current exceeds a threshold; and
control the one or more solid-state light sources to display a coarse fiducial pattern when the mobile computing device is located a long distance from the luminaire and a fine fiducial pattern when the mobile computing device is located near the luminaire.

US Pat. No. 10,484,089

DRIVER ASSISTED BY CHARGE SHARING

Hewlett Packard Enterpris...

1. A device, comprising:a switch configured to couple a current source with an output terminal upon receipt of a data signal; and
a first variable capacitor coupled in parallel to the current source at a common node on a source terminal of the switch, wherein the first variable capacitor comprises multiple capacitive elements coupled in parallel and configured to be activated by a programmable signal, and wherein the programmable signal is selected to increase a charge transfer rate from an output terminal coupled to a load, when the switch is turned on.

US Pat. No. 10,484,087

OPTICAL TRANSMISSION DEVICE

FUJI XEROX CO., LTD., Mi...

1. An optical transmission device comprising:a first light emitting element configured to emit light at a wavelength ?;
a second light emitting element configured to emit light at the wavelength ?, the second light emitting element being connected in parallel with the first light emitting element and being configured to have a shorter expected initial service life than the first light emitting element; and
a detector configured to detect whether the second light emitting element is deteriorated,
wherein the first light emitting element and the second light emitting element have current confinement structures, and
wherein the second light emitting element has a current confinement diameter smaller than a current confinement diameter of the first light emitting element.

US Pat. No. 10,484,084

METHOD AND SYSTEM TO INCREASE CAPACITY OF HIGH THROUGHPUT SATELLITE COMMUNICATION

Hughes Network Systems, L...

1. A method for providing high throughput communications via a Radio Frequency (RF) satellite, the method comprising:providing a plurality of information bit streams intended for a plurality of downlinks;
modulating an uplink stream comprising the plurality of information bit streams with an uplink modulation scheme to generate an uplink signal;transmitting the uplink signal to the satellite;partitioning, at the satellite, the uplink signal into a plurality of downlink signals, each one of the downlink signals intended for one of the plurality of downlinks;
encoding the uplink stream with a Forward Error Correcting (FEC) scheme; and
decoding and demodulating, at the satellite, the uplink signal,
wherein
the uplink stream comprises the plurality of information bit streams, and
the uplink modulation scheme uses a higher order constellation as compared to a order constellation used by a modulation scheme used for at least one of the plurality of downlinks, and based on the FEC scheme, a Signal-to-Noise (SNR) ratio of an uplink and the uplink modulation scheme, the uplink stream has a frame error rate that is less than or equal to a desired frame error rare.

US Pat. No. 10,484,082

SPACE ASSET TRACKER

Haris Corporation, Melbo...

16. A space asset tracking system, comprising:a space asset tag including
a tag housing;
a space vehicle tracking system (SVTS) disposed within the tag housing;
the SVTS including
a power supply which exclusively provides electrical power to the SVTS;
a position sensing receiver system (PSRS) configured to detect a position of the SVTS based on PSRS radio signals which are received respectively from a plurality of earth orbiting satellites;
a processing circuit which receives from the PSRS position information specifying at least the position;
a ground link radio frequency (GLRF) transmitter under the control of the processing circuit;
at least one data storage device in which a ground station database is stored containing information concerning locations of ground stations;
at least one PSRS antenna system integrated in or on the tag housing and operatively coupled to the PSRS to facilitate receiving the PSRS radio signals;
at least one GLRF antenna system integrated in or on the tag housing and operatively coupled to the GLRF transmitter;
wherein the processing circuit autonomously (1) uses the PSRS position information to determine a transmission location at which the SVTS is to be when transmitting tracking information to a given station, and (2) causes transmission of the tracking information from the GLRF transmitter when the SVTS is at the transmission location.

US Pat. No. 10,484,076

METHODS, NETWORK NODE AND WIRELESS TERMINAL FOR BEAM TRACKING WHEN BEAMFORMING IS EMPLOYED

Telefonaktiebolaget LM Er...

1. A method performed by a network node for supporting beam tracking in a wireless terminal when beamforming is employed in radio communication between the wireless terminal and the network node using a current selected network beam (Bc) and a current selected terminal beam (Tc), the method comprising:identifying a set of candidate network beams (B) having spatial characteristics similar to the current selected network beam (Bc), wherein a beam reference signal is associated with each candidate network beam in the set of candidate network beams (B);
signalling to the wireless terminal identities of the beam reference signals associated with the set of candidate network beams (B) or identities of the candidate network beams; and
transmitting the beam reference signals in the set of candidate network beams (B) using beam sweeping where at least some of the beam reference signals are transmitted separately multiple times, thereby enabling the wireless terminal to measure received power of the beam reference signals using different candidate terminal beams (T).

US Pat. No. 10,484,073

PRECODING INFORMATION COLLECTION METHOD AND TRANSMISSION DEVICE

HAUWEI TECHNOLOGIES CO., ...

1. A method of precoding information collection, applied to a receive apparatus, wherein there are M data streams used for data transmission between the receive apparatus and a transmit apparatus, and M is an integer greater than 1, the method comprising:receiving, by the receive apparatus, a precoded first pilot signal group sent by the transmit apparatus, and receiving i precoded second pilot signal groups sent by the transmit apparatus, wherein i is an integer greater than or equal to 1;
demodulating, by the receive apparatus, the precoded first pilot signal group to obtain a first pilot signal group, and demodulating the i precoded second pilot signal groups to obtain i second pilot signal groups respectively; and
sending, by the receive apparatus, precoding feedback information to the transmit apparatus according to the first pilot signal group and the i second pilot signal groups, wherein the first pilot signal group comprises M first pilot signals, and the ith second pilot signal group comprises Ai second pilot signals; and
the sending, by the receive apparatus, precoding feedback information to the transmit apparatus according to the first pilot signal group and the i second pilot signal groups comprises:
obtaining, by the receive apparatus, signal quality of the M first pilot signals in the first pilot signal group, and obtaining signal quality of

 second pilot signals in the i second pilot signal groups; and
selecting, by the receive apparatus, B pilot signals according to signal quality of all of the first pilot signals and signal quality of all of the second pilot signals, and sending the precoding feedback information to the transmit apparatus according to the B pilot signals, wherein B is an integer that is greater than or equal to 1 and less than or equal to

US Pat. No. 10,484,070

METHOD AND APPARATUS FOR CHANNEL STATE INFORMATION REFERENCE SIGNAL (CSI-RS)

Samsung Electronics Co., ...

1. A method of transmitting channel state information (CSI) by a terminal in a wireless communication system, the method comprising:receiving, from a base station, first information for configuring a set of CSI reference signal (CSI-RS) resources;
receiving, from the base station, second information for selecting at least one CSI-RS resource from the set of CSI-RS resources;
receiving, from the base station, downlink control information (DCI) requesting a report of a CSI, the DCI indicating a CSI-RS resource among the at least one CSI-RS resource;
calculating a CSI parameter based on a CSI-RS corresponding to the indicated CSI-RS resource; and
transmitting, to the base station, the CSI based on the calculated CSI parameter.

US Pat. No. 10,484,069

METHOD FOR FEEDING BACKCHANNEL STATE INFORMATION, USER EQUIPMENT, AND BASE STATION

HUAWEI TECHNOLOGIES CO., ...

1. A method performed by a user equipment (UE) for sending channel state information as feedback information to a base station wherein the method comprises:receiving a reference signal sent by the base station;
selecting a precoding matrix W from a codebook based on an antenna port corresponding to the reference signal, wherein a column vector of the precoding matrix W is expressed as ?[v ej?]T, v=[1 ej?], wherein ? is a constant, ? and ? are phases, and [ ]T indicates transposing of a matrix or vector, wherein the codebook comprises a matrix set; and
sending a precoding matrix indicator (PMI) to the base station, wherein the PMI is corresponding to the selected precoding matrix W,
wherein the matrix set is one of:

wherein
indicates the greatest integer not greater than i2/2.

US Pat. No. 10,484,068

METHOD FOR REPORTING CHANNEL STATE INFORMATION IN WIRELESS COMMUNICATION SYSTEM AND APPARATUS FOR THE SAME

LG Electronics Inc., Seo...

1. A method of reporting, by a user equipment (UE), channel state information (CSI) in a wireless communication system, the method comprising:receiving, by the UE and from a base station (BS), downlink control information (DCI) related to an aperiodic CSI report that is to be performed by the UE in a slot n;
determining, by the UE, a value nCQI_ref based on a number of symbols Z? related to a time for computing the CSI;
determining, by the UE, a CSI reference resource as being a slot n?nCQI_ref in a time domain that is to be used for the aperiodic CSI report; and
transmitting, by the UE and to the BS, the aperiodic CSI report in the slot n, based on the CSI reference resource being slot n?nCQI_ref,
wherein the nCQI_ref is a smallest value greater than or equal to ?Z?/Nsymbslot? such that the slot n?nCQI_ref satisfies a valid downlink slot criteria, and
wherein ?·? is a floor function and Nsymbslot is a number of symbols in one slot.

US Pat. No. 10,484,066

BEAM MANAGEMENT USING SYNCHRONIZATION SIGNALS THROUGH CHANNEL FEEDBACK FRAMEWORK

QUALCOMM Incorporated, S...

1. A method for wireless communication at a user equipment (UE), comprising:identifying a first feedback resource set and a first reporting configuration according to a channel state information (CSI) framework that indicates a plurality of synchronization signal (SS) blocks of an SS burst transmitted by a base station using a first set of transmission beams;
performing first channel measurements for the plurality of SS blocks;
reporting, to the base station, a first resource indicator for at least one of the plurality of SS blocks based at least in part on the first channel measurements;
obtaining a second feedback resource set and a second reporting configuration according to the CSI framework, wherein the second feedback resource set and the second reporting configuration identify a set of resources associated with a CSI reference signal (CSI-RS) transmitted by the base station using a second set of transmission beams;
performing second channel measurements for the CSI-RS; and
reporting according to the second reporting configuration, to the base station based at least in part on the second channel measurements, at least one channel metric for at least one of the set of resources associated with the CSI-RS and a second resource indicator of the at least one of the set of resources.

US Pat. No. 10,484,065

METHOD AND DEVICE FOR TRANSMITTING CHANNEL STATE INFORMATION

CHINA ACADEMY OF TELECOMM...

16. A network side device, comprising:a processor; and
a memory connected to the processor via a bus interface and configured to store therein programs and data for the operation of the processor, wherein
the processor is configured to call and execute the programs and data stored in the memory to:
determine a first number of bits used for a joint encoding operation on a Beam Indicator (BI) and a Rank Indicator (RI), the BI being configured to indicate an index of a resource for transmitting a reference signal corresponding to the RI measured by a User Equipment (UE), an identical first number of bits being used for the joint encoding operation on RI(s) and the BI corresponding to all resources for transmitting the reference signal; and
perform a joint decoding operation on encoding information from the UE in accordance with the first number of bits, to acquire the RI corresponding to the resource for transmitting the reference signal measured by the UE,
wherein the processor is further configured to:
determine numbers of bits for the RIs corresponding to all resources for transmitting the reference signal, determine a second number of bits for encoding the RI in accordance with a maximum value of the numbers of bits for the RIs corresponding to all resources for transmitting the reference signal, and determine the first number of bits in accordance with the second number of bits and a number of bits corresponding to the BI; or
determine a total number of possible values of the RIs corresponding to all resources for transmitting the reference signal, and determine the first number of bits in accordance with the total number of the possible values of the RIs corresponding to all resources for transmitting the reference signal.

US Pat. No. 10,484,063

TRANSMISSION OF BEAMFORMING WEIGHT COEFFICIENTS FROM DIGITAL BASEBAND UNIT TO REMOTE RADIO UNIT

1. A baseband unit device, comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
determining a group of beamforming coefficients for a stream of data, wherein the group of beamforming coefficients comprises respective subgroups of beamforming coefficients associated with respective antenna ports of a group of antenna ports;
selecting a portion of the subgroups of beamforming coefficients to add to a reduced size group of beamforming coefficients; and
transmitting the reduced size group of beamforming coefficients to a remote radio unit device to facilitate digital beamforming of a transmission to occur at the remote radio unit device.

US Pat. No. 10,484,062

TRANSMIT BEAMFORMING

INTEL IP CORPORATION, Sa...

1. An apparatus of a network entity capable to establish a communication connection with a user equipment (UE), the network entity comprising processing circuitry to:transmit a primary synchronization signal (xPSS) and a beamforming reference signal (xBRS) using transmit beamforming sweeping;
receive, from the UE, an identifier associated with one or more beamforming patterns for a downlink signal;
receive, from the UE, an uplink transmission of a first physical random access channel (PRACH) transmitted using beamforming sweeping;
identify at least one beamforming pattern in the uplink transmission of the physical random access channel;
transmit to the UE a signal comprising an identifier associated with the at least one beamforming pattern in the uplink transmission, wherein the signal comprising the identifier associated with the at least one beamforming pattern in the uplink transmission enables the UE to select a beamforming pattern for uplink transmission;
repeatedly transmit a primary synchronization signal (xPSS) and a beamforming reference signal (xBRS) using transmit beamforming sweeping on a periodic basis based at least in part on radio resource control (RRC) signaling from a primary cell (PCell);
receive, from the UE, the first PRACH via a omnidirectional antenna;
in response to the first PRACH, transmit to the UE a timing advance and a Cell Radio Network Temporary Identifier (C-RNTI) for data transmission from the UE;
receive, from the user equipment, a physical uplink shared control channel (PUSCH) which contains a request for a beamformed PRACH transmission;
in response to the request for a beamformed PRACH transmission, transmit a physical downlink control channel (PDCCH) to the UE;
receive, from the user equipment, the beamformed PRACH transmission; and
determine, from the beamformed PRACH transmission, a suitable transmission beam for uplink transmission from the UE.

US Pat. No. 10,484,060

METHOD AND DEVICE FOR TRANSMITTING AND RECEIVING CHANNEL STATE INFORMATION IN MOBILE COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method for transmitting channel state information by a user equipment (UE) in a mobile communication system, the method comprising:receiving, from a base station, a higher layer signaling message comprising information indicating a reporting mode for the channel state information and information related to a codebook subset configuration indicating subsampling a master codebook for use in reporting the channel state information;
determining whether to apply codebook subsampling to the master codebook based on the codebook subset configuration and the reporting mode, wherein the master codebook is defined as a set of precoding matrices shared by the UE and the base station;
upon determining to apply the codebook subsampling to the master codebook, generating a subsampled codebook by subsampling the master codebook and generating the channel state information comprising a first precoding matrix indicator (PMI) indicating a precoding matrix selected from the subsampled codebook;
when a plurality of feedback components are permitted to be simultaneously transmitted, further generating the channel state information further comprising a second PMI generated by assuming a particular codebook subset configuration which does not require subsampling and neglecting the codebook subset configuration made by the higher layer signaling; and
transmitting the channel state information to the base station.

US Pat. No. 10,484,059

MULTI-BEAM CODEBOOKS WITH FURTHER OPTIMIZED OVERHEAD

TELEFONAKTIEBOLAGET LM ER...

1. A method for a user equipment to transmit an indication of a precoder to a base station, the method comprising:determining from a codebook an indication of a precoder comprising a first beam phase parameter and a second beam phase parameter corresponding to a first beam and second beam, respectively;
the first beam phase parameter taking on one of a first integer number of phase values; and
the second beam phase parameter taking on one of a second integer number of phase values, the second beam having a lesser power than the first beam and the second integer number of phase values being less than the first integer number of phase values, each of the first and second beam phase parameters corresponding to a plurality of frequency subbands; and
reporting the determined indication of the precoder to a base station.

US Pat. No. 10,484,058

TRANSMISSION METHOD AND TRANSMISSION DEVICE

PANASONIC INTELLECTUAL PR...

1. A transmission method, comprising:encoding processing that generates a first encoded block and a second encoded block using a forward error correction coding scheme;
modulation processing that generates a plurality of first symbols and a plurality of second symbols from the first encoded block and generates a plurality of third symbols and a plurality of fourth symbols from the second encoded block;
phase change processing that changes a phase of the plurality of second symbols and the plurality of fourth symbols;
orthogonal frequency division multiplexing (OFDM) symbol generation processing that generates a first OFDM symbol by arranging the first symbols and the third symbols on data carriers of the first OFDM symbol and generates a second OFDM symbol by arranging the second symbols and the fourth symbols; and
transmitting processing that transmits the first OFDM symbol and the second OFDM symbol by using a plurality of antennas, wherein
in the first OFDM symbol, the first symbols are allocated with a predetermined period and the third symbols are allocated on data carriers adjacent to the first symbols,
in the second OFDM symbol, the second symbols are allocated with the predetermined period and the fourth symbols are allocated on data carriers adjacent to the second first symbols,
amounts of the phase change applied to the second symbols are regularly changed in a frequency direction, and
an amount of the phase change applied to each of the fourth symbols is same as that applied to each of the adjacent second symbols.

US Pat. No. 10,484,057

SYSTEM AND METHOD FOR COORDINATING MULTIPLE WIRELESS COMMUNICATIONS DEVICES IN A WIRELESS COMMUNICATIONS NETWORK

MEDIATEK SINGAPORE PTE. L...

1. A method for allocating radio resources by a coordinating wireless communications device in a wireless communications network including a plurality of wireless communications devices, the method comprising:obtaining a plurality of supported narrow-band channels in the wireless communications network;
selecting a primary channel from the supported narrow-band channels and using the primary channel to communicate with the plurality of wireless communications devices;
organizing the plurality of wireless communications devices into one or more communication groups;
assigning one of the one or more communication groups a non-overlapping operating channel for multi-user down-link multiple-input multiple-output (MU DL MIMO) operation with the coordinating wireless communications device, wherein the non-overlapping operating channel contains at least two of the plurality of supported narrow-band channels in a coalesced manner in frequency domain; and
assigning another one of the one or more communication groups another non-overlapping operating channel for multi-user up-link multiple-input multiple-output (MU UL MIMO) operation with the coordinating wireless communications device, wherein the another non-overlapping operating channel contains at least two of the plurality of supported narrow-band channels in a coalesced manner in the frequency domain;
wherein communication on the non-overlapping operating channel for the MU DL MIMO operation and communication on the another non-overlapping operating channel for the MU UL MIMO operation are concurrent, wherein the bandwidth of each of the non-overlapping operating channel and the another non-overlapping operating channel is determined based on at least one parameter selected from a group comprising the availability of the number of the supported narrow-band channels, the level of the interference of each supported narrow-band channel, and the respective supported narrow-band channels supported by each of the wireless communications device, and the bandwidth of at least one of the non-overlapping operating channel and the another non-overlapping operating channel is less than a sum of the bandwidths of the plurality of supported narrow-band channels.

US Pat. No. 10,484,056

ANALOG BEAM SIMULATION FOR WIRED DEVICE TESTING IN CP-OFDM SYSTEMS

Keysight Technologies, In...

1. A test device for simulating analog beams applied to a device under test (DUT), the test device comprising:a memory that stores instructions; and
a processor that executes the instructions,
wherein, when executed by the processor, the instructions cause the test device to perform a process comprising:
obtaining, from the memory and based on received instructions for testing the DUT, a first predetermined power level for a first beam to be simulated for the DUT and a first predetermined time delay for the first beam to be simulated for the DUT;
applying the first predetermined power level for the first beam and the first predetermined time delay for the first beam to a first set of subcarriers and cyclic prefix orthogonal frequency-division multiplexing (CP-OFDM) symbol to obtain simulated characteristics of the first beam from a perspective of the DUT; and
sending, over a wired connection, the simulated characteristics of the first beam from the processor to the DUT for testing the DUT using the simulated characteristics of the first beam to simulate wireless communication without over-the-air (OTA) transmission.

US Pat. No. 10,484,055

RATE-ADAPTIVE MULTIPLE INPUT/MULTIPLE OUTPUT (MIMO) SYSTEMS

SONY CORPORATION, Tokyo ...

1. A method executed in a first station having a plurality of first station antennas that communicates with a second station having M second station antennas, M>1, the method comprising:receiving, from said second station on a frequency simultaneously, a plurality of frames through two or more of said first station antennas, each frame including a training stream, a payload stream, and a control stream, wherein
respective control streams of said plurality of frames are identical streams and transmitted by transmission diversity through said two or more of said second station antennas.

US Pat. No. 10,484,054

TECHNIQUES AND APPARATUSES FOR PRIORITY-BASED RESOURCE CONFIGURATION

QUALCOMM Incorporated, S...

1. A method for wireless communication performed by a user equipment (UE), comprising:receiving configuration information that signals a first set of resources and a second set of resources,
wherein the configuration information indicates that the first set of resources is associated with high priority transmissions and the second set of resources is associated with low priority transmissions, and
wherein the first set of resources comprises one or more slots reserved for transmissions in one link direction across a plurality of cells, and the second set of resources comprises one or more slots that are not reserved for transmissions in any one link direction across the plurality of cells;
selecting, based at least in part on the configuration information and a priority of a transmission, either the first set of resources or the second set of resources for transmitting the transmission,
wherein the selecting of the first set of resources or the second set of resources is based on latency requirements or reliability requirements of transmissions to be transmitted by the UE; and
transmitting the transmission using the selected set of resources.

US Pat. No. 10,484,053

PROCESSING RADIO-FREQUENCY SIGNALS WITH TUNABLE MATCHING CIRCUITS

SKYWORKS SOLUTIONS, INC.,...

1. A method for processing a radio-frequency (RF) signal, the method comprising:amplifying a first RF signal using a first amplifier disposed along a first path corresponding to a first frequency band;
amplifying a second RF signal using a second amplifier disposed along a second path corresponding to a second frequency band;
generating a first impedance tuning signal in response to a band select signal indicating an in-band frequency band as the first frequency band and an out-of-band frequency band as the second frequency band; and
producing, based on the first impedance tuning signal, a first impedance along the first path, the first impedance configured to increase an in-band metric of the first path for the in-band frequency band and to decrease an out-of-band metric of the first path for the out-of-band frequency band.

US Pat. No. 10,484,052

METHOD AND DEVICE FOR TRANSMITTING ELECTRICAL POWER AND/OR SIGNALS BETWEEN A WALL AND A LEAF PIVOTABLE RELATIVE THERETO

1. A device for transmitting at least one of electrical power and signals between a wall and a leaf which is mounted so as to pivot on the wall, the device comprising:a transmission device which comprises,
a device for detecting a magnetic field strength in surroundings of the transmission device, the device for detecting a magnetic field strength comprising a magnetic field sensor which is designed as at least one of a reed switch and a Hall sensor,
a coil arrangement arranged on a side of the wall, and
a coil arrangement arranged on a side of the leaf;
a coil arrangement comprising a coil housing and a coil winding; and
an electrical circuit arrangement comprising a board,
wherein,
the magnetic field sensor is arranged on the board,
the board is arranged on an outer side of the coil housing,
the board comprises a transmission and/or receiving unit of an opto-electronic signal transmission device, and
the opto-electronic signal transmission device is provided as a part of a control loop for controlling power which is applied to the coil winding on the side of the wall which based on a power requirement of the side of the leaf.

US Pat. No. 10,484,047

CHANGING BETWEEN SEGMENTS OF A NETWORK

1. A mobile network subscriber for use in a cabled network, wherein the cabled network has at least one first segment and at least one second segment, the mobile network subscriber comprising:a first slave modem;
a second slave modem;
a first contact arrangement; and
a second contact arrangement,
wherein the first slave modem and the second slave modem are configured for communicating with at least one first master modem, at least one second master modem, or the at least one first master modem and the at least one second master modem via the first contact arrangement and the second contact arrangement and the at least one first segment and the at least one second segment,
wherein the mobile network subscriber is configured for movement along the at least one first segment and the at least one second segment, and
wherein the first contact arrangement and the second contact arrangement of the mobile network subscriber are arranged such that a change from the at least one first segment to the at least one second segment involves at least one contact arrangement of the first contact arrangement and the second contact arrangement being connected to the at least one first segment and at least one further contact arrangement being connected to the at least one second segment.

US Pat. No. 10,484,046

SYSTEMS AND METHODS FOR A TWISTED PAIR TRANSCEIVER WITH CORRELATION DETECTION

Marvell International Ltd...

1. A method for transmitting data on an Ethernet link between a first device compatible with a first Ethernet transmission protocol and a second device compatible with a second Ethernet transmission protocol, the method comprising:selecting a third baud rate to be a common factor of both a first baud rate specified in the first Ethernet transmission protocol and a second baud rate specified in the second Ethernet transmission protocol;
receiving, at the first device and from the second device, one or more encoded data symbols at the third baud rate;
determining a clock division factor based on the first baud rate and the third baud rate;
sampling, at the first device, the one or more encoded data symbols using a divided clock signal based on the clock division factor; and
generating, from the sampling, a number of samples representing at least one data symbol, wherein the number equals a result of the first baud rate divided by the common factor.

US Pat. No. 10,484,044

DIFFERENTIAL TERMINATION MODULATION FOR BACK-CHANNEL COMMUNICATION

HUAWEI TECHNOLOGIES CO., ...

1. A receiver for receiving a data signal over a communication link and sending back-channel data over the communication link, comprising:a first resistive element having an adjustable first resistance, the first resistance being adjusted based on a received first resistor tuning signal;
a second resistive element having a second resistance;
a terminator for differentially terminating the communication link using the first resistive element and the second resistive element; and
a back-channel data encoder for:
receiving a back-channel data signal; and
providing a first resistor tuning signal to the first resistive element based on the back-channel data signal.

US Pat. No. 10,484,043

ADAPTIVE BLIND SOURCE SEPARATOR FOR ULTRA-WIDE BANDWIDTH SIGNAL TRACKING

HRL Laboratories, LLC, M...

1. A system for blind source separation, the system comprising:one or more processors and a non-transitory computer-readable medium having executable instructions encoded thereon such that when executed, the one or more processors perform operations of:
continuously passing a time-series of data points from one or more mixtures of source signals through a plurality of adaptable filters having center frequencies, resulting in a plurality of output signals, each filter in the plurality of adaptable filters having a corresponding output signal;
determining an error of each output signal, resulting in a set of error signals;
determining a filter state of each filter using the error signals, resulting in a set of filter states;
adapting a set of filter center frequencies with a filter center frequency adapter by receiving and using both the set of error signals and the set of filter states, resulting in new filter center frequencies;
updating the set of filter center frequencies with the new filter center frequencies; and
extracting separated source signals from the mixture of signals.

US Pat. No. 10,484,042

BIDIRECTIONAL DATA LINK

TEXAS INSTRUMENTS INCORPO...

1. A bidirectional data link, comprising:a forward channel transmitter circuit, comprising:
a forward channel driver circuit; and
a back channel receiver circuit coupled to the forward channel driver circuit, the back channel receiver circuit comprising:
a summation circuit coupled to the forward channel driver circuit; and
an active filter circuit coupled to the summation circuit; and
a forward channel receiver circuit, comprising:
a forward channel receiver; anda back channel driver circuit coupled to the forward channel receiver;wherein the active filter circuit comprises:
a first transistor coupled to the summation circuit;
a second transistor coupled to the first transistor to form a differential amplifier; and
a first capacitor coupled to outputs of the differential amplifier;wherein the active filter circuit comprises:a third transistor;
a fourth transistor connected to the third transistor to form a cross-coupled pair; and
a second capacitor coupled to outputs of the cross-coupled pair.

US Pat. No. 10,484,041

GLITCH-FREE WIDE SUPPLY RANGE TRANSCEIVER FOR INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A transmitter, comprising:an input circuit configured to couple a logic signal to a first node and a second node;
a first level-shifter having an input coupled to the first node;
a first pre-driver having an input coupled to an output of the first level-shifter;
a second-level shifter having an input coupled to the second node, the second level-shifter is configured to perform a first level shift of the logic signal to generate a first logic signal and a second level shift of the logic signal to generate a second logic signal, and wherein an output of the second level-shifter includes the first logic signal and the second logic signal;
a second pre-driver having an input coupled to the output of the second level-shifter, the second pre-driver configured to generate an output signal having a first voltage swing in a first mode and a second voltage swing in a second mode, the second pre-driver comprising a stack of a first p-channel transistor, a second p-channel transistor, a first n-channel transistor, and a second n-channel transistor coupled between a supply node and a reference node, a gate of the first p-channel transistor receiving the first logic signal, a gate of the second n-channel transistor receiving the second logic signal, and gates of the second p-channel transistor and the first n-channel transistor receiving a first and second bias voltages, respectively; and
a driver including a stack of a top p-channel transistor, a bottom p-channel transistor, a top n-channel transistor, and a bottom n-channel transistor coupled between a the supply node and a ground node, a gate of the top p-channel transistor coupled to receive the output signal of the second pre-driver, a gate of the bottom n-channel transistor coupled to an output of the first pre-driver, and gates of the bottom p-channel transistor and the top n-channel transistor coupled to receive the first and second bias voltages, respectively.

US Pat. No. 10,484,040

APPARATUS AND METHOD FOR CANCELLING SELF-INTERFERENCE SIGNAL IN COMMUNICATION SYSTEM SUPPORTING FULL-DUPLEX SCHEME

Samsung Electronics Co., ...

1. A method for cancelling a self-interference (SI) signal in a communication system supporting a full-duplex scheme, the method comprising:estimating an SI channel;
performing a pre-filtering operation on a transmission signal based on the estimated SI channel;
generating copied-SI signals based on the estimated SI channel and the pre-filtered transmission signal; and
cancelling an SI signal based on the copied-SI signals,
wherein the pre-filtering operation includes an operation for decreasing a number of SI signals, and
wherein the performing of the pre-filtering operation on the transmission signal based on the estimated SI channel comprises:
acquiring a pre-filter which is time reverse for the estimated SI channel and is a complex conjugate, and
filtering the transmission signal based on the acquired pre-filter.

US Pat. No. 10,484,039

MULTIPLEXER, RADIO FREQUENCY FRONT-END CIRCUIT, AND COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. A multiplexer comprising:a first 90° hybrid coupler that is connected to an antenna terminal, that includes a plurality of transmission lines, and that is configured to shift, with respect to a radio frequency signal passing through one of the plurality of transmission lines of the first 90° hybrid coupler, a phase of a radio frequency signal passing through another of the plurality of transmission lines of the first 90° hybrid coupler by approximately 90 degrees;
a second 90° hybrid coupler that is connected to a terminating resistor, that includes a plurality of transmission lines, and that is configured to shift, with respect to a radio frequency signal passing through one of the plurality of transmission lines of the second 90° hybrid coupler, a phase of a radio frequency signal passing through another of the plurality of transmission lines of the second 90° hybrid coupler by approximately 90 degrees;
a first filter connected to the first 90° hybrid coupler and configured to selectively pass a first radio frequency signal of a first pass band; and
a second filter and a third filter, the second and third filters both being connected to both the first 90° hybrid coupler and the second 90° hybrid coupler, and both having the same filter characteristics,
wherein the second filter and the third filter are band elimination filters configured to reflect the first radio frequency signal and pass a second radio frequency signal of a band other than the first pass band, low-pass filters configured to reflect a third radio frequency signal of a band including the first pass band and pass a fourth radio frequency signal of a band lower than the band of the third radio frequency signal, or high-pass filters configured to reflect a fifth radio frequency signal of a low frequency band including the first pass band and pass a sixth radio frequency signal of a band higher than the band of the fifth radio frequency signal.

US Pat. No. 10,484,037

RADIO FREQUENCY (RF) TRANSCEIVER AND OPERATING METHOD THEREOF

Samsung Electronics Co., ...

1. A radio frequency (RF) transceiver comprising:a first oscillator configured to generate a first oscillation frequency associated with an RF signal;
a second oscillator configured to generate a second oscillation frequency associated with a clock frequency;
a quenching wave generator configured to generate a quenching signal to control a negative-R generator of the first oscillator using the second oscillation frequency; and
a comparer configured to generate a digital output signal associated with the RF signal based on consideration of the first oscillation frequency, the second oscillation frequency, and a reference.

US Pat. No. 10,484,035

PROTECTIVE CASE FOR MOBILE ELECTRONIC COMMUNICATION DEVICE

PELICAN PRODUCTS, INC., ...

1. A protective case for a mobile electronic communication device, the protective case comprising:a rear cover; and
a front cover configured to selectively connect to the rear cover and define a space between the front cover and the rear cover for receiving the mobile electronic communication device, the front cover having an opening surrounded by an annular ledge defining a surface that faces away from the rear cover when the front cover and rear cover are connected together; and
a transparent membrane affixed to the surface of the annular ledge and extending over the opening in the front cover;
wherein the front cover includes an outer body of a first material, and a liner of a second material, and wherein the liner has an upper surface that forms the annular ledge of the front cover.

US Pat. No. 10,484,034

TABLET COMPUTER CASE

Griffin Technology, LLC, ...

1. A device case for a portable electronic device, the device case comprising:a housing having a back surface, the back surface having hinge holes and hinge slots;
an inner stand connected to the back surface by hinge protrusions on the inner stand that are inserted into the hinge holes;
an outer stand connected to the back surface by compressible protrusions that engage said hinge slots such that the outer stand can separate from the device case without breaking, at least a portion of the outer stand is flexible such that applying a threshold pressure to the device case causes the flexible portion to flex; and
a locking portion formed on the outer stand that locks the inner stand into an open position with respect to the outer stand, wherein the locking portion releases the inner stand and the outer stand from the open position when the threshold pressure is applied.

US Pat. No. 10,484,031

MOTORCYCLE COMMUNICATION SYSTEM AND METHOD

1. A computer-readable, non-transitory, programmable product, stored in memory of a mobile device, comprising code for causing a processor to:determine a rider location in connection with geo-locator input data;
provide a user-selectable list of contacts retrieved from the mobile device; assemble a group, in order to form a network, based on user input;
determine a group location in connection with processing information containing geographic locations of mobile devices within the group, and determining a geographic center of the group;
generate a distance alert in connection with comparing rider locations to the group location, determining a rider distance based on the rider location and the group location, and determining that a rider location exceeds a predetermined threshold for the rider distance;
determine a rider crash baseline in connection with continuously monitoring an accelerometer, determining an accelerometer average from the accelerometer's measurements over a predetermined period, monitoring a gyroscope, and determining a gyroscope average from the gyroscope's readings over a predetermined period;
monitor for a crash in connection with comparing measurements from the accelerometer to the accelerometer average in real-time, generating a crash alert if the accelerometer measurements exceed the accelerometer average, comparing measurements from the gyroscope to the gyroscope average in real-time, generating the crash alert if the gyroscope measurements exceed the gyroscope average, adding the mobile device's geographic location to the crash alert, and causing the presentation of the crash alert on a display for a predetermined period, and causing the dispatch of the crash alert over a wireless network if the crash alert is not rejected by a user.

US Pat. No. 10,484,030

EUICC MANAGEMENT METHOD, EUICC, SM PLATFORM, AND SYSTEM

HUAWEI TECHNOLOGIES CO., ...

1. A method of managing an embedded universal integrated circuit card (eUICC), comprising:acquiring, by the eUICC, capability information of a terminal in which the eUICC is embedded; and
sending, by the eUICC, the capability information of the terminal to a subscription management (SM) platform, so that according to the capability information of the terminal and current status information of the eUICC, the SM platform:
manages a profile on the eUICC,
generates a profile, or
manages the eUICC;
wherein the current status information of the eUICC comprises current available storage space of the eUICC.

US Pat. No. 10,484,026

CIRCUIT ARRANGEMENT AND METHOD FOR ATTENUATION COMPENSATION IN AN ANTENNA SIGNAL LINK

BURY SP.Z.O.O., Mielec (...

1. A circuit arrangement for compensating for an attenuation occurring in an antenna signal link between a mobile radio terminal and an antenna, comprising:at least one antenna signal amplifier in the antenna signal link for amplifying or attenuating an antenna signal;
a control unit associated with said at least one antenna amplifier for adjusting a gain factor by which the antenna signal conducted through the at least one signal amplifier is amplified or attenuated; and
at least one detection unit for detecting an antenna signal power of the antenna signal in a signal path of the antenna signal link, wherein
the control unit is configured
for changing the gain factor incrementally in predetermined variables of the gain factor by way of a test to provide a corresponding pattern,
for detecting a change, following as response to the test-wise change of the gain factor, of antenna signal power caused by a change of transmit power of a mobile radio terminal, and
for adapting the gain factor to a coupling attenuation of the antenna signal link in dependence on the corresponding pattern of a detected response of the mobile radio terminal.

US Pat. No. 10,484,025

MULTIPLE BAND MULTIPLE MODE TRANSCEIVER FRONT END FLIP-CHIP ARCHITECTURE AND CIRCUITRY WITH INTEGRATED POWER AMPLIFIERS

Skyworks Solutions, Inc.,...

1. An integrated circuit architecture defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns, the integrated circuit architecture comprising:a first operating frequency region corresponding to a physical area on the die structure including a first transmit chain, a first receive chain, and a first antenna conductive pad, the first operating frequency region being defined by a first outer periphery and an opposed first inner periphery;
a second operating frequency region corresponding to a physical area on the die structure including a second transmit chain, a second receive chain, and a second antenna conductive pad, the second operating frequency region being defined by a second outer periphery and an opposed second inner periphery; and
a shared region of the die structure corresponding to a physical area thereon and defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the first inner periphery of the first operating frequency region and the second inner periphery of the second operating frequency region both being adjacent to the shared region, the shared region including either one or both of a shared power input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

US Pat. No. 10,484,023

WIRELESS SYSTEM AND METHODS FOR COEXISTENCE UNDER CONCURRENT USE OF SUB-7 GHZ AND MILLIMETER WAVE SPECTRUM

Phazr, Inc., Allen, TX (...

1. A wireless communications system, comprising:a first device configured to transmit signals in millimeter wave spectrum and receive signals in both millimeter wave spectrum and Sub-7 GHz spectrum, wherein millimeter wave and Sub-7 GHz receive antenna paths of the first device are combined into same receive ports through a first power combiner;
a second device configured to transmit signals in Sub-7 GHz spectrum and receive signals in both Sub-7 GHz spectrum and millimeter wave spectrum, wherein millimeter wave and Sub-7 GHz receive antenna paths of the second device are combined into same receive ports through a second power combiner,
wherein the second device includes a sub-7 GHz transceiver where a receive port switches between a signal path from Sub-7 GHz spectrum and millimeter wave spectrum based on a composite switch control signal derived from transmit/receive status of a plurality of transceivers.

US Pat. No. 10,484,022

WIRELESS COMMUNICATION NODE WITH MULTI-BAND FILTERS

Telefonaktiebolaget LM Er...

1. A wireless communication network node comprising:at least one antenna arrangement,
at least one radio arrangement,
at least one power splitter arrangement, and
at least one power amplifier,
where each antenna arrangement in turn comprises at least one antenna device, and where each power splitter arrangement comprises an input port and at least two output ports, wherein each of said at least one power amplifier is connected to a corresponding input port, and where, for each power splitter arrangement, the at least two output ports of each power splitter arrangement are connected to at least one corresponding antenna device via a corresponding multi-band filter for each of the at least two output ports of the each power splitter arrangement, where each multi-band filter is arranged for at least two frequency bands, and
wherein the wireless communication network node comprises a first power amplifier, a second power amplifier, a first power splitter arrangement, a second power splitter arrangement, where the first power amplifier is connected to an input port of the first power splitter arrangement and where the output ports of the first power splitter arrangement are connected to a first set of antenna devices of a combined antenna arrangement via corresponding multi-band filters for each of said output ports and phase shifters, and where the second power amplifier is connected to an input port of the second power splitter arrangement, where the output ports of the second power splitter arrangement are connected to a second set of antenna devices of the combined antenna arrangement via corresponding multi-band filters for each of said output ports and phase shifters, the combined antenna arrangement comprising antenna devices of a first polarization and a second polarization, where first polarization is orthogonal to the second polarization.

US Pat. No. 10,484,021

LOG-LIKELIHOOD RATIO PROCESSING FOR LINEAR BLOCK CODE DECODING

XILINX, INC., San Jose, ...

1. A decoder, comprising:a control circuit configured to receive a first sign signal, a second sign signal, a partial sum signal, a function select signal, a third sign signal, and a carry signal as an input vector to provide an output sign signal and a vector select signal;
a select generation circuit configured to receive the first sign signal, the second sign signal, and the partial sum signal to provide an add/subtract select signal;
a subtractor configured to subtract from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal;
responsive to the add/subtract select signal, an adder/subtractor configured to either add or subtract the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal; and
a multiplexer configured to select from the first absolute value signal, the second absolute value signal, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select signal.

US Pat. No. 10,484,020

SYSTEM AND METHOD FOR PARALLEL DECODING OF CODEWORDS SHARING COMMON DATA

SK Hynix Inc., Gyeonggi-...

1. A decoding apparatus configured for decoding a plurality of codewords in parallel, comprising:a memory;
a processor coupled to the memory, the processor configured to read encoded data including a plurality of codewords from the memory, the plurality of codewords being encoded in a product code in which each codeword has multiple data blocks, each data block having a number of data bits, wherein the plurality of codewords are encoded such that codewords belonging to a same pair of codewords share a common data block; and
one or more decoders, configured to perform parallel decoding of two or more codewords, wherein decoding of each codeword at least partially overlaps in time with decoding of one or more other codewords;
wherein the decoding apparatus is configured to:
perform parallel decoding of a first codeword with one or more other codewords to determine error information associated with each codeword, the first codeword sharing a respective common data block with each of the one or more other codewords, wherein the error information identifies one or more data blocks having one or more errors and associated error bit pattern;
update the one or more other codewords based on the error information;
determine whether to update the first codeword as follows:
determine if common data blocks shared between the first codeword with the one or more other codewords have been identified as having errors in the decoding of the first codeword;
upon determining that the common data blocks have no errors, update the first codeword based on the error information;
for each of the common data blocks in the first codeword that has an error, compare the error bit pattern for the data block in the first codeword with the error bit pattern for a corresponding common data block in the other codewords;
if the error bit patterns match for all the common data blocks that have errors, update data blocks other than the common data blocks in the first codeword without updating the common data blocks; and
if the error bit patterns do not match for any one of the common data blocks that have errors, skip updating of the first codeword;
whereby comparing error bit pattern in updating the first codeword allows reducing skip procedures and reducing a number of codewords that include data blocks which have errors but have not been updated, thus shortening latency loss and increasing decoding throughput.

US Pat. No. 10,484,019

ADAPTIVE ENCODER/DECODER

Western Digital Technolog...

18. A storage device comprising:volatile memory;
data encoding means for encoding data to generate data parity;
mode encoding means for encoding mode information to generate mode parity;
codeword forming means for forming a first sub-codeword that comprises the data and the data parity, the codeword forming means further for forming a second sub-codeword that comprises the mode information and the mode parity;
codeword storing means for storing the first sub-codeword and the second sub-codeword in the volatile memory;
codeword reading means for accessing the first sub-codeword and the second sub-codeword from the volatile memory;
mode decoding means for decoding the second sub-codeword that was accessed from the volatile memory to obtain the mode information; and
data decoding means for decoding the first sub-codeword that was accessed from the volatile memory based on the mode information, the data decoding means comprising normal data decoding means for decoding the first sub-codeword in response to the mode information indicating a normal data mode, the data decoding means comprising special data decoding means for decoding the first sub-codeword in response to the mode information indicating a special data mode.

US Pat. No. 10,484,018

PARTIAL REVERSE CONCATENATION FOR DATA STORAGE DEVICES USING COMPOSITE CODES

International Business Ma...

1. A method, comprising:writing data to a storage medium, via a write channel, by applying a partial reverse concatenated modulation code to the data prior to storing encoded data to the storage medium,
wherein the applying the partial reverse concatenated modulation code to the data comprises application of a C2 encoding scheme to the data to produce C2-encoded data prior to application of one or more modulation encoding schemes to the C2-encoded data to produce modulated data, followed by application of a C1 encoding scheme to the modulated data subsequent to the application of the one or more modulation encoding schemes to produce the encoded data.

US Pat. No. 10,484,017

DATA PROCESSING APPARATUS, AND DATA PROCESSING METHOD

Sony Corporation, Tokyo ...

1. A data processing apparatus in which data as an object of transmission is low density parity check-coded on a transmission side, the resulting low density parity check code is mapped to a symbol on a complex plane corresponding to a predetermined modulation system, a data stream representing the symbol to which the mapping is carried out is bit-interleaved with a predetermined bit group as a unit, and the bit-interleaved data stream transmitted in accordance with the predetermined modulation system is set as an object of processing, the data processing apparatus comprising:a parallel demapping processing portion configured to obtain a second data stream by executing in parallel demapping processing corresponding to the mapping on the transmission side for a first data stream, as the object of processing, corresponding to the bit-interleaved data stream transmitted from the transmission side;
a bit interleave reverse processing portion configured to obtain a third data stream by executing in parallel bit interleave reverse processing corresponding to a bit interleave on the transmission side for the second data stream;
a barrel shifter configured to obtain a fourth data stream by performing in parallel column twist reverse processing on the third data stream; and
a low density parity check decoding portion configured to decode the fourth data stream inputted in parallel with the predetermined bit group as the unit.

US Pat. No. 10,484,016

DATA DEDUPLICATION WITH ADAPTIVE ERASURE CODE REDUNDANCY

Quantum Corporation, San...

1. A non-transitory computer-readable storage medium storing computer-executable instructions that when executed by a computer control the computer to perform a method, the method comprising:generating, by a processor, a characterization of segments of a plurality of segments with failure probabilities associated with the segments that indicate a likelihood of failure of the segments;
parsing, by a processor, the plurality of segments to generate a plurality of original chunks;
deduplicating, by a processor, the plurality of original chunks to generate a plurality of unique chunks;
grouping, by a processor, the plurality of unique chunks to form grouped chunks;
encoding, by a processor, the grouped chunks to generate a desired number of erasure code symbols that satisfy the failure probabilities associated with the segments; and
selectively storing members of the desired number of erasure code symbols on a number of storage devices.

US Pat. No. 10,484,015

DATA STORAGE SYSTEM WITH ENFORCED FENCING

Amazon Technologies, Inc....

1. A method comprising:requesting, by a head node of a data storage system, credentials for accessing portions of mass storage devices of a plurality of data storage sleds of the data storage system, wherein the head node includes a sequence number for the head node with requests to the plurality of data storage sleds;
receiving, by the head node, credentials for accessing the portions, wherein the credentials are issued based, at least in part, on sled controllers of the data storage sleds determining the sequence number for the head node is greater than one or more respective greatest sequence numbers previously stored for the portions;
receiving, by the head node, a write request from a client of the data storage system;
writing, by the head node, data included with the write request to a data storage of the head node; and
requesting, by the head node, to write the data included with the write request to a plurality of mass storage devices in a plurality of data storage sleds of the data storage system, wherein requesting to write the data comprises:
presenting at least some of the respective credentials obtained from the plurality of data storage sleds; and
determining the respective credentials are valid credentials for accessing respective portions of the plurality of mass storage devices; and
writing the data included with the write request to the plurality of mass storage devices in the plurality of data storage sleds of the data storage system.

US Pat. No. 10,484,014

CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. An operating method of a memory system including a controller and a memory device, the operating method comprising:receiving a message from a host by the controller;
generating a square message matrix of k×k based on the message by the controller;
minimizing a length of each codes included in the square message matrix;
generating an encoded message by the controller which encodes the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code; and
storing the encoded message in the memory device; and
obtaining the encoded message in the memory device by the controller for decoding,
wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix,
wherein the upper triangular matrix includes “?” numbers of message blocks, each of which has a size of “?+1”, and “(N??)” numbers of message blocks, each of which has a size of “?”, and
wherein “?”, “?” and N have relationships represented by equations

where “M” represents a size of the message input from the host and “N” represents a number of message blocks forming the upper triangular matrix,
wherein the generating of the encoded message includes generating a parity block for each row of the square message matrix, and
wherein each size of the zero-padding blocks is the same as the parity block.

US Pat. No. 10,484,013

SHIFT-COEFFICIENT TABLE DESIGN OF QC-LDPC CODE FOR SMALLER CODE BLOCK SIZES IN MOBILE COMMUNICATIONS

MEDIATEK INC., Hsin-Chu ...

1. A method of wireless communication, comprising:establishing, by a processor of an apparatus, a wireless communication link with at least one other apparatus via a transceiver of the apparatus; and
wirelessly communicating, by the processor, with the other apparatus via the wireless communication link by:
selecting a first shift-coefficient table from a plurality of shift-coefficient tables;
generating a quasi-cyclic-low-density parity-check (QC-LDPC) code using a base matrix and at least a portion of the first shift-coefficient table;
selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code;
storing the selected codebook in a memory associated with the processor;
encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and
controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link,
wherein the selecting of the first shift-coefficient table from the plurality of shift-coefficient tables comprises selecting the first shift-coefficient table according to one or more rules related to either or both of a code block size and a code rate of the data for relatively smaller code block sizes.

US Pat. No. 10,484,009

DECODING METHOD AND DECODER FOR LOW-DENSITY PARITY-CHECK CODE

HUAWEI TECHNOLOGIES CO., ...

1. A decoding method for a low-density parity-check (LDPC) code, comprising:dividing, by a decoder, an LDPC code C whose bit length is n into k divided LDPC codes D, the LDPC code C={c1,c2,c3,K,cn-1,cn}, the divided LDPC codes D={D1,D2,K,Dk-1,Dk}, Di={c(i-1)l+1,c(i-1)l+2,K,cil-1,cil}i=1,2,K,k?1,k, and a bit length of the Di comprising l=n/k;
arranging, by the decoder, the Di,i=1,2,K,k?1,k by column to obtain transpose codes (DT) of the divided LDPC codes D, the DT={D1T,D2T,K,Dk-1T,DkT}, DiT={c(i-1)l+1,c(i-1)l+2,K,cil-1,cil}T, and i=1,2,K,k?1,k;
performing, by the decoder, cyclic shift on the DiT,i=1,2,K,k?1,k by row according to values of corresponding elements in a target check matrix to obtain shift codes (E), the E={E1,E2,K,Et-1,Et}, t being equal to a quantity of rows of the target check matrix, Ej comprising a result of shifting the DT according to an element of a jth row in the target check matrix, and j=1,2,K,t?1,t;
obtaining, by the decoder, t*m groups of LDPC subcodes according to the E and a bit length of the decoder (d), the LDPC subcodes comprising F1,F2,K,Ftm-1,Ftm, the Ej being divided into m groups, the Ej={(Ej)1d,(Ej)d+12d,K,(Ej)(m-2)d+1(m-1)d,(Ej)(m-1)d+1md}={F(j-1)m+1,F(j-1)m+2,K,Fjm-1,Fjm}, (Ej)(s-1)d+1sd, s=1,2,K, m?1,m denoting an [(s?1)d+1]th row to an (sd)th row of the Ej, and m=?l/d?; and
decoding, by the decoder, m groups of the LDPC subcodes to obtain a decoding result of the LDPC code C such that a quantity of parallel decoding operations on the LDPC code C being controlled flexibly.

US Pat. No. 10,484,006

SYSTEM AND METHOD FOR ARITHMETIC ENCODING AND DECODING

NTT DOCOMO, INC., Tokyo ...

1. A method of arithmetic decoding for converting an information sequence comprised of at least one information piece to derive an event sequence comprised of at least one event, the method comprising:receiving the at least one information piece of the information sequence;
generating context information for the at least one event;
generating, according to the generated context information, a probability estimate estimating a probability of occurrence of the at least one event; and
converting the at least one received information piece to derive the at least one event, using the generated probability estimate, by accounting for a bounded ratio of events to information pieces,
wherein the bounded ratio of events to information pieces is an average bounded ratio of events to information pieces.

US Pat. No. 10,484,005

METHOD AND APPARATUS OF AN ACOUSTIC ENERGY DETECTION CIRCUIT FOR A PULSE DENSITY MODULATION MICROPHONE

NUVOTON TECHNOLOGY CORPOR...

1. A PDM (pulse density modulation) signal energy detection circuit, comprising:a multiple-stage switched-capacitor filter circuit having multiple filter stages for receiving a PDM digital input signal, the multiple-stage switched-capacitor filter circuit producing a non-inverting analog output signal and an inverting analog output signal based on the PDM digital input signal;
a comparator circuit for receiving the non-inverting analog output signal and the inverting analog output signal from the multiple-stage switched-capacitor filter circuit, the comparator circuit producing a pulsed signal when a magnitude of the non-inverting analog output signal or the inverting analog output signal exceeds a pre-set threshold; and
a counter circuit receiving the pulsed signal from the comparator circuit and producing an energy detection signal when a number of consecutive pulsed signals exceeds a pre-set count;
wherein the filter stages each comprises of a single MOSFET gain stage, a MOSFET current source carrying a current Ibias and a switched capacitor network, the single MOSFET gain stage being biased at a current Ibias and having an average voltage of Vnbias at a drain and gate connection, wherein Vnbias is a bias voltage derived from an external MOSFET gate voltage having drain and gate tied together and biased at a current Ibias.

US Pat. No. 10,484,004

DELTA-SIGMA MODULATOR

MEDIATEK INC., Hinchu (T...

1. A delta-sigma modulator (DSM) comprising:a first loop filter for filtering a first signal to a second signal;
a second loop filter for filtering a third signal;
a comparator;
a register coupled to the comparator;
a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator;
a first path coupled between the register and the first loop filter, causing a delayed signal to be linearly combined with an input signal to form the first signal; and
a second path coupled between the register and the second loop filter, causing the delayed signal to be linearly combined with the second signal to form the third signal; wherein:
the delayed signal is formed by delaying an output signal of the register; and
during a second phase and a third phase, the first capacitor bank is conducted to the comparator; and
during a fourth phase and a repeated first phase, the second capacitor bank is conducted to the comparator.

US Pat. No. 10,484,003

A/D CONVERTER

DENSO CORPORATION, Kariy...

1. An A/D converter comprising:an integrator that includes an operational amplifier, and a first feedback capacitor and a second feedback capacitor which are connected in parallel with each other between a first input terminal and an output terminal of the operational amplifier;
a quantizer that outputs a quantization result obtained by quantizing an output signal output from the output terminal of the operational amplifier; and
a D/A converter that includes a D/A converter capacitor having a first terminal connected to the first input terminal of the operational amplifier, wherein
the integrator includes a first feedback switch interposed between the first feedback capacitor and the output terminal of the operational amplifier and a second feedback switch interposed between the second feedback capacitor and the output terminal of the operational amplifier,
an input signal is input to at least one of a portion between the first feedback capacitor and the first feedback switch, and a portion between the second feedback capacitor and the second feedback switch,
the D/A converter capacitor has a second terminal on an opposite side to the first terminal of the D/A converter capacitor, and the second terminal of the D/A converter is connected to the output terminal of the operational amplifier,
the D/A converter repeatedly subtracts charges from charges accumulated in the first feedback capacitor and the second feedback capacitor based on the quantization result to perform A/D conversion of the input signal, and performs subtraction operation for outputting a residual of the A/D conversion as the output signal of the operational amplifier,
the D/A converter transfers the charges accumulated in the first feedback capacitor to the second feedback capacitor after the subtraction operation to perform amplification operation for amplifying the residual of the A/D conversion in the subtraction operation,
the D/A converter repeats subtraction and amplification sequentially based on the quantization result for the residual of the A/D conversion in the subtraction operation amplified by the amplification operation, to perform cyclic operation for A/D converting the residual of the A/D conversion in the subtraction operation, and
the D/A converter performs the A/D conversion of the input signal by adding a result of the A/D conversion in the cyclic operation to a result of the A/D conversion in the subtraction operation.

US Pat. No. 10,484,002

HIGH-SPEED HIGH-RESOLUTION DIGITAL-TO-ANALOG CONVERTER

Keithley Instruments, LLC...

1. A digital-to-analog converter, comprising:an input to receive a digital signal;
a first comparator configured to receive the digital signal and output a first signal based on the digital signal and a first threshold;
a second comparator configured to receive the digital signal and output a second signal based on the digital signal and a second threshold, the second threshold different from the first threshold;
an integrator configured to receive the first signal and the second signal and integrate the first signal and the second signal into an analog signal that represents the digital signal;
a first resistor coupled between the first comparator and an input of the integrator; and
a second resistor coupled between the second comparator and the input of the integrator.

US Pat. No. 10,484,001

MULTI-BIT SUCCESSIVE-APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

TEXAS INSTRUMENTS INCORPO...

1. A system for digitizing a sampled input value, comprising:a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes; and
a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles;
wherein dither is dynamically added to the digital-to-analog converter in the intermediate cycle, and corrected for in the subsequent cycle.

US Pat. No. 10,483,995

CALIBRATION OF RADIX ERRORS USING LEAST-SIGNIFICANT-BIT (LSB) AVERAGING IN A SUCCESSIVE-APPROXIMATION REGISTER ANALOG-DIGITAL CONVERTER (SAR-ADC) DURING A FULLY SELF-CALIBRATING ROUTINE

Caelus Technologies Limit...

1. A self-calibrating mixed-signal converter comprising:an array of digital-analog elements, each for converting a binary bit to an analog signal;
a comparator that compares two analog inputs to generate a compare result;
a Least-Significant-Bit (LSB) digital-analog element in the array of digital-analog elements, the LSB digital-analog element having a smallest effect on the two analog inputs, the LSB digital-analog element having an ideal radix of one;
wherein other digital-analog elements in the array of digital-analog elements each have an ideal radix that is a function of a ratio of a design size of a digital-analog element to the design size of the LSB digital-analog element;
wherein the array of digital-analog elements comprise at least five digital-analog elements with different design sizes and having at least five different values of the ideal radix;
wherein the array of digital-analog elements is connected to at least one of the two analog inputs to the comparator wherein each of the at least five digital-analog elements with different design sizes cause at least five different values of an effect on at least one of the two analog inputs to the comparator;
wherein manufactured sizes of the digital-analog elements differ from the design sizes by an error amount;
a Successive-Approximation Register (SAR) that applies a SAR search sequence of binary bits to a portion of the array of digital-analog elements having an ideal radix less than a target ideal radix of a target digital-analog element in the array of digital-analog elements;
wherein bits are set or cleared in the SAR during the SAR search sequence in response to the compare result from the comparator to generate a final SAR value when the SAR search sequence is completed;
a plurality of LSB averaging digital-analog elements, having an ideal radix of 1, and connected to at least one of the two analog inputs to the comparator;
a LSB averaging accumulator that is incremented or decremented in response to the compare result from the comparator when test values of binary bits are applied to the plurality of LSB averaging digital-analog elements, the LSB averaging accumulator adjusting the final SAR value after the SAR search sequence is completed to generate a LSB-corrected final SAR value;
a summer for summing the ideal radixes for digital-analog elements having a corresponding bit set in the LSB-corrected final SAR value to generate a target measured radix;
a digital averager for averaging a plurality of the LSB-corrected final SAR value generated during a plurality of repetitions of the SAR search sequence measuring the target digital-analog element, the digital averager generating an actual measured radix that is the average of the plurality of the LSB-corrected final SAR value; and
a Look-Up Table (LUT) that stores the actual measured radix from the digital averager for the target digital-analog element, the LUT also storing the ideal radixes for the portion of the array of digital-analog elements having the ideal radix that is less than the target ideal radix of the target digital-analog element;
wherein the LUT also stores actual measured radixes for other digital-analog elements having an ideal radix greater than the target radix, the other digital-analog elements each successively acting as the target digital-analog element in the SAR search sequence and digital averager to generate the actual measured radix for that digital-analog element;
wherein the summer reads the LUT for the actual measured radix for digital-analog elements having a corresponding actual measured radix stored in the LUT, the summer using the actual measured radix rather than the ideal radix when the actual measured radix is available in the LUT to generate a target measured radix during calibration;
whereby radix error calibration uses the actual measured radix that is read from the LUT instead of the ideal radix for radixes above the target ideal radix, and uses the ideal radix for radixes below the target ideal radix.

US Pat. No. 10,483,994

KICKBACK COMPENSATION FOR A CAPACITIVELY DRIVEN COMPARATOR

TEXAS INSTRUMENTS INCORPO...

1. An analog-to-digital converter (ADC), comprising:a comparator;
a voltage reference circuit;
a first capacitive digital-to-analog converter (CDAC) comprising:
a plurality of capacitors, each comprising:
a top plate coupled to first input of the comparator; and
a bottom plate switchably coupled to an output of the voltage reference circuit;
a second CDAC comprising:
a plurality of capacitors, each comprising:
a top plate coupled to a second input of the comparator; and
a bottom plate switchably coupled to a ground reference;
further comprising edge rate control circuitry configured to adjust the edge rate of an output signal of the comparator based on a significance of a bit being generated by the ADC.

US Pat. No. 10,483,993

RESIDUE AMPLIFIER

TEXAS INSTRUMENTS INCORPO...

1. An analog-to-digital converter (ADC), comprising:a capacitive digital-to-analog converter (CDAC);
a residue amplifier coupled to the CDAC, and comprising:
a first complementary transistor pair coupled to a first output of the CDAC, and comprising:
a high-side transistor; and
a low-side transistor; and
a first tail current circuit coupled to the high side transistor;
a switched capacitor circuit coupled to inputs of the CDAC and the first tail current circuit, and configured to:
generate a voltage to bias the first tail current circuit; and
compensate for common mode voltage at the inputs of the CDAC.

US Pat. No. 10,483,991

SEMICONDUCTOR DEVICE AND TEST METHOD

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor device comprising a PLL circuit configured to produce an oscillation signal in synchronism with a reference signal, and first and second external terminals, whereinsaid PLL circuit includes:
a phase comparison part configured to detect a phase difference between said reference signal and said oscillation signal to produce a phase difference signal indicative of said phase difference in binary;
a voltage conversion part configured to convert said phase difference signal into a phase difference voltage having a voltage value corresponding to said phase difference represented by said phase difference signal to apply said phase difference voltage to a phase difference voltage node;
an oscillation part configured to produce, as said oscillation signal, a signal having a frequency depending on said phase difference voltage; and
a correction circuit configured to supply a correction current for correcting said phase difference voltage to said phase difference voltage node, wherein
said phase comparison part outputs said phase difference signal through said first external terminal, and
upon reception of a test control signal through said second external terminal, said correction circuit produces a current serving as said correction current depending on said test control signal to supply the produced current to said phase difference voltage node.

US Pat. No. 10,483,990

FREQUENCY COMPENSATOR, ELECTRONIC DEVICE AND FREQUENCY COMPENSATION METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A frequency compensator, comprising:a control circuit configured to generate a frequency control word according to an initial frequency and a target frequency; and
a frequency compensation circuit is configured to:
receive an input signal of the initial frequency; and
generate and output an output signal of a compensated frequency according to the frequency control word and the input signal of the initial frequency,
wherein the control circuit comprises:
an input sub-circuit configured to obtain the initial frequency, the target frequency, and a frequency multiplication parameter;
a calculation sub-circuit configured to generate the frequency control word according to the initial frequency, the target frequency, and the frequency multiplication parameter; and
an output sub-circuit configured to output the frequency control word to the frequency compensation circuit.

US Pat. No. 10,483,988

SYNCHRONIZATION CIRCUIT AND METHOD RELATING TO THE SYNCHRONIZATION CIRCUIT

SK hynix Inc., Icheon-si...

1. A synchronization circuit comprising:a variable delay circuit configured to delay a first clock signal by a varied delay time according to delay control signals, and configured to output a delayed signal of the variable delay circuit as a second clock signal;
a phase detector configured to generate a phase detection signal by detecting a phase difference between the first and second clock signals; and
a delay control circuit configured to perform a phase unstable period detection operation according to the phase detection signal, and configured to perform a delay skip operation to adjust the delay control signals according to skip period information such that a phase unstable period, detected in the phase unstable period detection operation, is skipped in a delay time tuning operation,
wherein the delay control circuit includes a skip period information generation circuit configured to generate the skip period information by performing the phase unstable period detection operation according to the phase detection signal.

US Pat. No. 10,483,987

FAILSAFE CLOCK PRODUCT USING FREQUENCY ESTIMATION

Silicon Laboratories Inc....

1. A method for operating a clock product comprising:generating a quality determination for a reference clock signal based on frequency metrics for a plurality of independent clock signals, the frequency metrics being generated using the reference clock signal; and
generating an output clock signal by locking to an active clock signal selected from the plurality of independent clock signals in response to the quality determination satisfying a predetermined quality metric,
wherein for each input clock signal of the plurality of independent clock signals, the frequency metrics include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts, and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.

US Pat. No. 10,483,985

OSCILLATOR USING SUPPLY REGULATION LOOP AND OPERATING METHOD THEREOF

Samsung Electronics Co., ...

1. An oscillator comprising:a reference voltage generator configured to generate reference voltages from a supply voltage;
a supply regulation loop circuit comprising a first operational amplifier and a transistor, the first operational amplifier being configured to receive a first reference voltage of the reference voltages, and the transistor being connected to an output terminal of the first operational amplifier; and
a frequency locked loop (FLL) circuit configured to generate a clock signal, based on an input voltage determined based on a current flowing in the transistor and a second reference voltage of the reference voltages,
wherein the first operational amplifier comprises:
an input terminal configured to receive the first reference voltage and to receive negative feedback from the transistor; and
the output terminal being configured to generate an output voltage independent of noise of the supply voltage.

US Pat. No. 10,483,982

FREQUENCY SYNTHESIZER WITH TUNABLE ACCURACY

INTEGRATED DEVICE TECHNOL...

1. An apparatus comprising:a first circuit configured to generate a first code by counting a number of cycles of an input clock signal during a period, wherein said period is determined by an output clock signal and a second code;
a second circuit configured to generate a third code by a delta-sigma modulation of said first code, wherein said third code has fewer bits than the first code; and
a third circuit configured to generate an initial frequency said output clock signal in response to said third code, wherein an accuracy of said initial frequency of said output clock signal is adjusted in response to a current value of said second code.

US Pat. No. 10,483,980

PARAMETRICALLY ACTIVATED QUANTUM LOGIC GATES

1. A method comprising:obtaining operating parameters for one or more of a plurality of qubit devices in a quantum processor circuit, the plurality of qubit devices comprising a fixed-frequency qubit device and a tunable qubit device, the operating parameters based on measurements of the quantum processor circuit under an operating condition, the operating condition comprising a flux modulation applied to the tunable qubit device; and
based on the operating parameters, selecting gate parameters of a two-qubit quantum logic gate for application to a pair of qubits defined by the fixed-frequency qubit device and the tunable qubit device;
generating a control signal configured to modulate, at a modulation frequency, a transition frequency of the tunable qubit device, the modulation frequency being determined based on a transition frequency of the fixed-frequency qubit device; and
applying the two-qubit quantum logic gate to the pair of qubits by communicating the control signal to a control line coupled to the tunable qubit device;
wherein the control signal is a first control signal, the modulation frequency is a first modulation frequency, the fixed-frequency qubit device is a first fixed-frequency qubit device that defines a first qubit, the two-qubit quantum logic gate is a first two-qubit quantum logic gate, the pair of qubits is a first pair of qubits, and the method further comprises:
generating a second control signal configured to modulate the transition frequency of the tunable qubit device at a second modulation frequency, the second modulation frequency being determined based on a transition frequency of a second fixed-frequency qubit device in the quantum processor circuit; and
applying a second two-qubit quantum logic gate to a second pair of qubits in the quantum processor circuit by communicating the second control signal to the control line coupled to the tunable qubit device, the second pair of qubits comprising a second qubit defined by the tunable qubit device and a third qubit defined by the second fixed-frequency qubit device.

US Pat. No. 10,483,979

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

iCometrue Company Ltd., ...

1. A multi-chip package comprising:a semiconductor integrated-circuit (IC) chip comprising:
a plurality of non-volatile memory cells; and
a programmable logic circuit configured to be programmed to perform a logic function, comprising a plurality of input points for an input data set for the logic operation, a multiplexer configured to select, in accordance with the input data set, a resulting value from a plurality of resulting values of a look-up table (LUT) as an output data for the logic operation, and an output point for the output data for the logic operation; and
a memory chip coupling to the semiconductor integrated-circuit (IC) chip, wherein communication between the semiconductor integrated-circuit (IC) chip and the memory chip has a data bit width greater than or equal to 64.

US Pat. No. 10,483,978

MEMORY DEVICE PROCESSING

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory device comprising a plurality of banks of memory cells, wherein particular banks of memory cells among the plurality of banks includes a bank processor configured to control memory operations for the bank on which the bank processor is located; and
a system processor resident on a bank of the memory device that does not include the bank processor, wherein the system processor is configured to control performance of memory operations for the memory device.

US Pat. No. 10,483,977

LEVEL SHIFTER

TEXAS INSTRUMENTS INCORPO...

1. A level shifter circuit, comprising:a high voltage latch circuit comprising:
a non-inverting output terminal;
an inverting output terminal;
a high state trigger input terminal; and
a low state trigger input terminal;
a low voltage latch circuit coupled to the high voltage latch circuit, and comprising:
a high state trigger input terminal coupled to the inverting output terminal of the high voltage latch circuit; and
a low state trigger input terminal coupled to the non-inverting output terminal of the high voltage latch circuit;
a high state pulse generator coupled to the high state trigger input terminal of the high voltage latch circuit; and
a low state pulse generator coupled to the low state trigger input terminal of the high voltage latch circuit.

US Pat. No. 10,483,976

CIRCUITS TO INTERPRET PIN INPUTS

TEXAS INSTRUMENTS INCORPO...

1. An apparatus comprising:a pin;
an input buffer coupled to the pin;
a first current mirror coupled to the input buffer, the first current mirror comprising three transistors, each of the three transistors in the first current mirror coupling to a different one of three legs of the apparatus;
a second current mirror coupled to the input buffer, the second current mirror comprising three transistors, each of the three transistors in the second current mirror coupling to a different one of the three legs of the apparatus;
multiple level shifters positioned in a common leg of the three legs;
a voltage divider circuit coupled to the multiple level shifters;
a first output buffer coupled to the input buffer and the first current mirror; and
a second output buffer coupled to the input buffer and the second current mirror.

US Pat. No. 10,483,974

METHOD FOR MULTIPLEXING BETWEEN POWER SUPPLY SIGNALS FOR VOLTAGE LIMITED CIRCUITS

Apple Inc., Cupertino, C...

1. A system, comprising:a plurality of functional circuits;
a power supply circuit configured to:
generate a shared power signal coupled to the plurality of functional circuits; and
generate an adjustable power signal coupled to a particular functional circuit of the plurality of functional circuits; and
a power management circuit configured to send a request to the power supply circuit to change a voltage level of the adjustable power signal from a first voltage level to a second voltage level;
wherein the particular functional circuit is configured to:
selectively couple a power node included in the particular functional circuit to either of the shared power signal or the adjustable power signal based on a control signal; and
maintain an operational voltage level on the power node when selectively coupling the power node to either of the shared power signal or the adjustable power signal.

US Pat. No. 10,483,973

TEMPERATURE INSTABILITY-AWARE CIRCUIT

Taiwan Semiconductor Manu...

1. A circuit, comprising:a first swing reduction circuit coupled between an input/output pad and a buffer circuit, wherein the first swing reduction circuit comprises a first p-type metal-oxide-semiconductor field-effect-transistor gated by a first bias voltage and comprises a second p-type metal-oxide-semiconductor field-effect-transistor drained by the first bias voltage; and
a second swing reduction circuit coupled between the input/output pad and the buffer circuit,
wherein the first swing reduction circuit is configured to increase a voltage received by respective gates of a first subset of transistors of the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage, and the second swing reduction circuit is configured to reduce a voltage received by respective gates of a second subset of transistors of the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

US Pat. No. 10,483,972

DELAY CIRCUIT

INFINEON TECHNOLOGIES AG,...

1. A delay circuit, comprising:an electronic transmission element with
a first transmission element input and a first transmission element output, wherein the first transmission element input is coupled to the first transmission element output by means of two first complementary switches wired in parallel, wherein the first switches each have a control input;
a second transmission element input and a second transmission element output, wherein the second transmission element input is coupled to the second transmission element output by means of two second complementary switches wired in parallel, wherein the second switches each have a control input;
wherein the first transmission element output is coupled to the control inputs of the second switches and the second transmission element output is coupled to the control inputs of the first switches;
an input circuit, configured to receive an input signal and feed the input signal to one of the transmission element inputs and feed the inverted input signal to the other of the transmission element inputs; and
an output circuit, coupled to the first transmission element output and the second transmission element output and configured to provide an output signal, wherein the output circuit is configured in such a way that the output signal only changes in the case of a change in the input signal if the change in the input signal has brought about a change both at the first transmission element output and at the second transmission element output.

US Pat. No. 10,483,971

PHYSICAL UNCLONABLE DEVICE AND METHOD OF MAXIMIZING EXISTING PROCESS VARIATION FOR A PHYSICALLY UNCLONABLE DEVICE

Taiwan Semiconductor Manu...

1. A physically unclonable function (PUF) device comprising:a plurality of PUF cells, configured to generate an output, wherein each of the plurality of PUF cells comprising:
a harvester circuit comprising a first circuit which comprises a first pair of transistors and a second circuit which comprises a second pair of transistors, the harvester circuit is configured to generate a bit line and a complementary bit line, wherein the harvester circuit is selected to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells,
a sense amplifier comprising a plurality of transistors configured to receive a first input signal and a second input signal from the harvester circuit; and
a pulse evaluation circuit, programmable to generate a pulse evaluation signal coupled to a control terminal of the second pair of transistors.

US Pat. No. 10,483,970

DYNAMIC TERMINATION EDGE CONTROL

Micron Technology, Inc., ...

1. A semiconductor device comprising:a delay pipeline comprising a plurality of serially connected flip-flops, wherein the delay pipeline is configured to receive an ODT command to assert on-die termination (ODT) for a data pin of the semiconductor device and to generate and output a plurality of delayed commands in a backward direction to generate a shifted command; and
selection circuitry configured to receive a selection signal to indicate a selected delayed command from the plurality of delayed commands used to generate the shifted command, wherein the shifted command is configured to enable the ODT during a memory write based at least in part on the selected delayed command.

US Pat. No. 10,483,969

INPUT DEVICE

PANASONIC INTELLECTUAL PR...

1. An input device comprising:a switch that is switched between on and off by being pressed;
a plurality of light sources, the plurality of light sources including:
a first light source; and
a second light source disposed at a position different from a position of the first light source; and
a light guide that guides light emitted from each of the plurality of light sources in an anti-pressing direction opposite to a pressing direction of the switch,
wherein the light guide includes:
an emission part that is disposed in the anti-pressing direction from the switch and emits the light emitted by each of the plurality of light sources, in the anti-pressing direction;
a first light guide leg that is coupled to the emission part and guides first light emitted by the first light source to the emission part; and
a second light guide leg that is coupled to the emission part and guides second light emitted by the second light source to the emission part,
the emission part includes:
a first design that illuminates by reflecting the first light in the anti-pressing direction; and
a second design that illuminates by reflecting the second light in the anti-pressing direction,
the first light guide leg is a plate-shaped part and includes a first reflection surface disposed along a thickness of the first light guide leg and reflects the first light,
the second light guide leg is a plate-shaped part and includes a second reflection surface disposed along a thickness of the second light guide leg and reflects the second light, and
the first light guide leg and the second light guide leg are arranged on approximately a same plane.

US Pat. No. 10,483,966

SWITCHING CIRCUIT

PANASONIC INTELLECTUAL PR...

1. A switching circuit, comprising:a drive power supply which includes a positive electrode terminal and a negative electrode terminal, and outputs a predetermined drive voltage;
a first transistor and a second transistor which are connected in parallel;
a drive signal source which outputs a drive pulse signal for turning on and off the first transistor and the second transistor; and
a drive circuit, which includes a power supply terminal and a ground terminal, receives supply of electric power from the drive power supply, and outputs, according to the drive pulse signal, a first drive signal for turning on and off the first transistor and a second drive signal for turning on and off the second transistor,
wherein each of the first transistor and the second transistor includes:
a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON;
a gate electrode which changes an impedance between the drain electrode and the source electrode according to a corresponding one of the first drive signal and the second drive signal;
a gate terminal connected to the gate electrode;
a drain terminal connected to the drain electrode;
a first source terminal connected to the source electrode for passing the main current between the drain electrode and the source electrode; and
a second source terminal connected to the source electrode for detecting a source voltage and flowing a gate drive current, the second source terminal being provided in addition to the first source terminal,
the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal,
the drain terminal of the first transistor and the drain terminal of the second transistor are connected to each other,
the first source terminal of the first transistor and the first source terminal of the second transistor are connected to each other,
the gate terminal of the first transistor receives the first drive signal,
the gate terminal of the second transistor receives the second drive signal, and
the second source terminal of the first transistor and the second source terminal of the second transistor are individually and separately connected to a portion of a wiring line which connects the negative electrode terminal of the drive power supply and the ground terminal of the drive circuit.

US Pat. No. 10,483,965

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a first switching element including a first gate, a first source connected to a common terminal via a first connection line, and a first drain;
a second switching element including a second gate, a second source that is connected to the first source via a second connection line and connected to the common terminal via the first connection line and the second connection line;
a first capacitor for connecting the first source and a high voltage side of a power supply;
a first circuit element having first end connected between the high voltage side of the power supply and the first capacitor; and
a second capacitor for connecting the second source and second end of the first circuit element.

US Pat. No. 10,483,964

SIGNAL PROCESSING DEVICE

KABUSHIKI KAISHA TOKAI RI...

1. A signal processing device, comprising:an input terminal configured to be input with an input signal that is active high or an input signal that is active low;
a switching terminal connectable to a power supply or ground;
a selection circuit configured to select and output the input signal that is active high in a case that the switching terminal is connected to the power supply and select and output the input signal that is active low in a case that the switching terminal is connected to the ground.

US Pat. No. 10,483,962

LEVEL SHIFTER

Samsung Electronics Co., ...

1. A level shifter, comprising:a driving circuit, which is configured to receive an input signal and to output a driving signal in response to a first voltage level of the input signal;
a level shifting circuit, which is configured to output an output signal of a second voltage level in response to the driving signal; and
a leakage prevention circuit, which is configured to prevent a leakage current of the driving circuit; and
a damage prevention circuit that prevents damage to the leakage prevention circuit,
wherein the driving circuit comprises at least one native transistor,
wherein the leakage prevention circuit comprises at least one low voltage transistor, and
wherein the damage prevention circuit comprises at least one damage preventing device that is connected to the low voltage transistor in parallel.

US Pat. No. 10,483,961

CHARGE INJECTOR WITH INTEGRATED LEVEL SHIFTER FOR LOCALIZED MITIGATION OF SUPPLY VOLTAGE DROOP

Intel Corporation, Santa...

1. An apparatus comprising:a first power supply rail to provide a first power supply voltage;
a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage;
a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first power supply voltage, wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication, wherein the first circuitry comprises a level-shifter with an asymmetric input pair circuitry, and wherein the asymmetric input pair circuitry is to turn on the first circuitry faster than turning the first circuitry off; and
a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.

US Pat. No. 10,483,959

VARIABLE STREAM PULSE WIDTH MODULATION

TEXAS INSTRUMENTS INCORPO...

1. A modulator comprising:splitter logic to receive and to partition an input sample data into at least a first data field and a second data field, wherein the first data field includes a pulse structure value and the second data field includes a pulse placement value;
pattern logic coupled to the splitter logic to:
receive the first data field; and
determine a sequence of pulses based on the pulse structure value of the first data field, wherein the sequence of pulses has a plurality of edges;
edge mover logic coupled to the splitter logic to:
receive the second data field; and
determine edge adjustment data based on the pulse placement value of the second data field, wherein the edge adjustment data specifies a move in time of an edge of the plurality of edges of the sequence of pulses; and
combiner logic coupled to the pattern logic and the edge mover logic to:
receive the sequence of pulses and the edge adjustment data; and
combine the sequence of pulses and the edge adjustment data to provide an output pulse stream that includes the sequence of pulses with the edge occurring at a time as specified by the edge adjustment data.

US Pat. No. 10,483,958

VOLTAGE DETECTOR AND METHOD FOR DETECTING VOLTAGE

Cypress Semiconductor Cor...

1. A voltage detector, comprising:a comparison unit having a plurality of comparators, said comparison unit configured to compare a threshold voltage received via a voltage divider and determination voltages corresponding to said each comparator, and output a first result of High or Low for each comparator based on the comparison of the threshold voltage and the determination voltages, the comparison unit being further configured to compare an input voltage received via the voltage divider and the determination voltages, and output a second result of High or Low for each comparator based on the comparison of the input voltage and the determination voltages; and
a determination unit comprising a counter configured to determine whether or not the input voltage is less than or equal to the threshold voltage, the determination being based on a count of High levels output by each of the plurality of comparators for the threshold voltage, and based on a count of High levels output by each of the plurality of comparators for the input voltage.

US Pat. No. 10,483,957

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:an addition circuit of adding input data and feedback data and outputting addition data;
a first sampling circuit of sampling the addition data from the addition circuit synchronously with a first clock signal and outputting sampling data;
a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data;
a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and
a phase adjustment circuit, when reference data for adjusting a timing of sampling of the first sampling circuit is output as the addition data from the addition circuit, of adjusting phase of the first clock signal so that sampling data output from the first sampling circuit corresponds to the reference data.

US Pat. No. 10,483,956

PHASE INTERPOLATOR, TIMING GENERATOR, AND SEMICONDUCTOR INTEGRATED CIRCUIT

ROHM CO., LTD., Ukyo-Ku,...

1. A semiconductor integrated circuit comprising:a set signal generator structured to generate a set signal; and
a reset signal generator structured to generate a reset signal,
wherein at least one from among the set signal generator and the reset signal generator comprises a timing generator, the timing generator comprising N (N?2) stages,
wherein an i-th (1?i?N?1) stage comprises a first phase interpolator and a second phase interpolator,
wherein an output node of the first phase interpolator in the i-th (1?i?N?1) stage is coupled to a first input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,
wherein an output node of the second phase interpolator in the i-th stage is coupled to a second input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,
wherein the first phase interpolator and the second phase interpolator are each arranged such that a first signal is received via the first input node and such that a second signal is received via the second input node, and structured to generate an output signal having an edge at a timing that corresponds to control data,
and wherein the first phase interpolator and the second phase interpolator each comprise a phase interpolator, the phase interpolator comprising:
a first input node coupled to receive a first signal that transits from a first level to a second level;
a second input node coupled to receive a second signal that transits from the first level to the second level with a delay with respect to the first signal;
a first line coupled to receive a first voltage;
a second line coupled to receive a second voltage;
an intermediate line;
a capacitor having one end coupled to the intermediate line;
an initializing circuit structured to initialize a voltage across the capacitor during a period in which the first signal and the second signal are both set to the first level;
a plurality of circuit units that correspond to a plurality of bits of an input code, and coupled in parallel between the intermediate line and the second line; and
an output circuit structured to generate an output signal having a level that changes when the voltage across the capacitor crosses a predetermined threshold value,
wherein each circuit unit comprises:
a resistor and a first path arranged in series between the intermediate line and the second line; and
a second path arranged in parallel with the first path,
wherein the first path is structured such that, when the first signal is set to the second level and the corresponding bit of the input code is set to a first value, the first path is turned on,
wherein the second path is structured such that, when the second signal is set to the second level and the corresponding bit of the input code is set to a second value, the second path is turned on,
and wherein the semiconductor integrated circuit is structured to output a pulse signal that transits to a first level according to an output signal of the set signal generator, and that transits to a second level according to an output signal of the reset signal generator.

US Pat. No. 10,483,953

RING OSCILLATOR-BASED TIMER

TEXAS INSTRUMENTS INCORPO...

1. A circuit, comprising:a ring oscillator;
a state capture register, coupled to the ring oscillator, to capture a state of the ring oscillator upon occurrence of an edge of an input periodic signal;
an edge-phase detector to assert an edge detect high signal in response to a first reference clock derived from the ring oscillator being high upon occurrence of the edge of the input periodic signal and to assert an edge detect low signal in response to the first reference clock derived from the ring oscillator being low upon occurrence of the edge of the input periodic signal; anda first register to receive data from the state capture register upon occurrence of one of a rising or falling edge of a second clock derived from the ring oscillator;further comprising:a first state encoder, coupled to the first register, to read data from the first register, invert even numbered bits of the data read from the first register, and pad the data read from the first register, with the even numbered bits inverted, with a plurality of logic ‘1’s;
a second register to receive data from the state capture register upon occurrence of the other of the rising or falling edge of the second clock; and
a second state encoder, coupled to the second register, to read data from the second register, invert odd numbered bits of the data read from the second register, and pad the data read from the second register, with the odd numbered bits inverted, with a plurality of logic ‘0’s.

US Pat. No. 10,483,952

BASELINE WANDER CORRECTION USING ZERO AND ONE MISMATCH ADAPTATION

Oracle International Corp...

1. An apparatus, comprising:an equalizer circuit configured to receive a serial data stream, wherein the serial data stream encodes a plurality of data symbols; and
a circuit configured to:
determine an average magnitude of a first data value using a subset of the plurality of data symbols;
determine an average magnitude of a second data value using the subset of the plurality of data symbols; and
adjust a common mode operating point of the equalizer circuit by sinking a current from an input of the equalizer circuit, wherein a value of the current is based on a comparison of the average magnitude of the first data value and the average magnitude of the second data value.

US Pat. No. 10,483,950

LEVEL CONVERSION DEVICE AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A device, comprising:a level shifter configured to output a first output signal at a first output terminal in response to a first input signal having a first logic level, and configured to output a second output signal at a second output terminal in response to the first input signal having a second logic level; and
an output stage configured to receive and adjust the first output signal or the second output signal that is selected in response to the first input signal, and configured to generate a third output signal,
wherein the third output signal has a logic value that is the same as a logic value of the first output signal or the second output signal.

US Pat. No. 10,483,947

ANTI-ALIASING FILTER

MEDIATEK INC., Hsinchu (...

1. An anti-aliasing filter (AAF) for discretization at a sampling period, comprising:an operational amplifier having an input terminal and an output terminal;
a first capacitor coupled between the input terminal and the output terminal;
a second capacitor; and
a first switch coupled between the first capacitor and the second capacitor; wherein:
during a first phase, the first switch conducts the second capacitor to the first capacitor;
during a second phase, the first switch stops conducting the second capacitor to the first capacitor; and
the first phase lasts for one said sampling period, such that a signal transfer function of the AAF has one or more notches at one or more integer multiplications of a sampling frequency, with the sampling frequency being a reciprocal of said sampling period.

US Pat. No. 10,483,946

SINGLE SOLUTION IMPEDANCE MATCHING SYSTEM, METHOD AND APPARATUS

PALSTAR, INC., Piqua, OH...

1. A method for matching an impedance of a radio frequency (RF) load to an impedance of a RF source, said method comprising the steps of:coupling a RF source having a first impedance to an input of a 1:N step-up impedance transformer, wherein the first impedance of the RF source is stepped up to a second impedance at an output of the 1:N step-up impedance transformer, the second impedance is N times the first impedance, and the second impedance is greater than the RF load impedance;
coupling a matching network to the output of the 1:N step-up impedance transformer, wherein the matching network comprises a variable capacitor and a variable inductor;
increasing the RF load impedance with a step-up impedance transformer or decreasing the RF load impedance with a step-down impedance transformer, wherein the step-up impedance transformer or the step-down impedance transformer is coupled between the RF load and the matching network; and
adjusting the variable capacitor and the variable inductor so that the impedance of the RF load appears to the RF source to be at substantially the first impedance.

US Pat. No. 10,483,945

SWITCHED CAPACITOR BASED DIGITAL STEP ATTENUATOR

TEXAS INSTRUMENTS INCORPO...

13. A computing device comprising:a processing unit;
a memory module coupled to the processing unit; and
an RF receiver coupled to the processing unit and the memory module, the RF receiver further comprising:
an input driver configured to receive a coarse signal, and configured to generate an input signal;
a digital step attenuator (DSA) coupled to the input driver and configured to receive the input signal; and
an analog to digital converter (ADC) coupled to the DSA, wherein the DSA further comprises:
a serial capacitor coupled to the input driver; and
a sampling capacitor coupled to the ADC.

US Pat. No. 10,483,943

ARTIFICIALLY ORIENTED PIEZOELECTRIC FILM FOR INTEGRATED FILTERS

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a piezoelectric film with effective crystalline orientations of a polar axis rotated 90 degrees from a natural orientation for planar deposited films; and
a conductor pattern formed on a surface of the piezoelectric film, wherein
the conductor pattern comprises electrodes formed on a single, planar surface of the piezoelectric film,
the piezoelectric film has an effective crystalline orientation of the polar axis in a horizontal orientation, with respect to the conductor pattern, and
the effective crystalline orientations of the polar axis are in a vertical direction adjacent to an underlying substrate.

US Pat. No. 10,483,942

ACOUSTIC WAVE DEVICE WITH ACOUSTICALLY SEPARATED MULTI-CHANNEL FEEDBACK

Skyworks Solutions, Inc.,...

11. A multiplexer comprising:a transmit filter including first acoustic wave resonators;
a receive filter including second acoustic wave resonators, the receive filter and the transmit filter being coupled to each other at a common node;
a first canceling circuit coupled to the transmit filter and to the receive filter, the first canceling circuit including an interdigital transducer electrode;
a second canceling circuit coupled to the transmit filter and to the receive filter; and
an acoustic obstacle disposed between the first canceling circuit and the second canceling circuit, the acoustic obstacle and the interdigital transducer electrode each including the same material, and the acoustic obstacle further including a polymer.

US Pat. No. 10,483,941

ACOUSTIC WAVE DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIYO YUDEN CO., LTD., T...

1. An acoustic wave device comprising:a single piezoelectric substrate;
an IDT that is formed on the single piezoelectric substrate and includes a pair of comb-shaped electrodes facing each other, each of the pair of comb-shaped electrodes including a grating electrode that excites an acoustic wave and a bus bar to which the grating electrode is connected; and
reforming regions that are located only inside the single piezoelectric substrate and arranged at intervals each other under the IDT, and in which a material of the single piezoelectric substrate is reformed,
wherein the reforming regions have an amorphous structure.

US Pat. No. 10,483,939

DOWNHOLE LOGGING TOOL USING RESONANT CAVITY ANTENNAS WITH REAL-TIME IMPEDANCE MATCHING

Halliburton Energy Servic...

1. A system for real-time impedance matching comprising:a transmit cavity antenna that transmits signals through a subsurface formation;
an impedance-matching circuit comprising a variable inductor or a variable capacitor, wherein the impedance-matching circuit comprises three single pole triple throw switches, one throw on each switch coupled to a variable inductor, and another throw on each switch coupled to a variable capacitor;
a cable that routes signals within the system; and
a processor that:
measures a reflection of a signal transmitted through the formation;
determines a target impedance based on the impedance of the cable and the reflection; and
adjusts the at least one variable inductor or capacitor such that the impedance of the matching circuit substantially equals the target impedance.

US Pat. No. 10,483,938

TUNABLE FILTER

NATIONAL TAIWAN UNIVERSIT...

1. A tunable filter, having an input end and an output end, comprising:a first circuit and a second circuit, wherein both of the first circuit and the second circuit include:
a first tunable capacitor, having a first end and a second end;
a first inductor and a second inductor, wherein the first inductor and the second inductor are connected in serial and further connected with the first tunable capacitor in parallel, and a mutual induction is generated between the first inductor and the second inductor; and
a second tunable capacitor, having a first end and a second end, wherein the first end of the second tunable capacitor is connected between the first inductor and the second inductor, and the second end of the second tunable capacitor is grounded;
wherein the first end of the first tunable capacitor of the first circuit is coupled to the input end of the tunable filter through a first coupling tunable capacitor, the second end of the first tunable capacitor of the first circuit is coupled to the first end of the first tunable capacitor of the second circuit through a second coupling tunable capacitor, and the second end of the first tunable capacitor of the second circuit is coupled to the output end of the tunable filter through a third coupling tunable capacitor;
wherein a ratio of a capacitance of the first tunable capacitor to a capacitance of the second tunable capacitor is 0.08˜0.12 in the first circuit, and a ratio of a capacitance of the first tunable capacitor to a capacitance of the second tunable capacitor is 0.08˜0.12 in the second circuit.

US Pat. No. 10,483,937

TRANSCEIVER CIRCUIT AND CONFIGURATION METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A transceiver circuit, comprising:a substrate;
a signal coupler configured on the substrate and comprising a coiled first conductive layer pattern; and
a notch filter configured on the substrate and comprising a coiled second conductive layer pattern;
wherein each of the coiled first conductive layer pattern and the coiled second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a first virtual axis;
wherein the coiled first conductive layer pattern is arranged as a substantially circular pattern and the coiled second conductive layer pattern is arranged as a substantially two-circle pattern;
wherein the substantially two-circle pattern comprises two circle patterns disposed apart from and adjacent to each other.

US Pat. No. 10,483,934

AUDIO LEVELING AND ENHANCEMENT DEVICE

1. A device for audio leveling and sound enhancement, which comprises:(a) a housing having an input port for receiving an original inputted digital audio or audio-visual signal from a source and an output port for transmitting the signal from the device to a receiving device;
(b) an audio leveler disposed within the housing and including;
(1) an input port in electrical communication with the housing input port;
(2) means for leveling the original input signal from the source;
(3) an output port for outputting the leveled original input signal;
(c) means for enhancing the original input signal received from the source the means for enhancing including;
(1) an input port for receiving the outputted leveled original input signal from the audio leveler; and
(2) an output port in electrical communication with the output port of the housing; and
(3) means for layering the inputted original signal received from the audio leveler, with at least one exact duplicate of the original input signal.

US Pat. No. 10,483,933

AMPLIFICATION ADJUSTMENT IN COMMUNICATION DEVICES

Sorenson IP Holdings, LLC...

1. A method to adjust audio amplification in a communication device, the method comprising:obtaining a request from a user regarding adjusting settings of audio output by the communication device;
in response to obtaining the request, presenting an audio configuration interface on a display of the communication device, the audio configuration interface including a visual depiction of a plurality of amplification settings that each correspond to a different one of a plurality of frequencies, the plurality of amplification settings indicating amplifications applied to the plurality of frequencies of the audio output by the communication device;
obtaining an action from the user to adjust the amplification of one or more of the plurality of amplification settings in the audio configuration interface to generate adjusted amplification settings;
in response to obtaining the action, automatically applying the adjusted amplification settings to test audio, the test audio including a female voice and a male voice;
in response to applying the adjusted amplification settings, automatically outputting the test audio with the applied adjusted amplification settings through a speaker of the communication device;
while outputting the test audio with the applied adjusted amplification settings, obtaining a second action from the user to adjust the amplification of one or more of the plurality of amplification settings in the audio configuration interface to generate second adjusted amplification settings;
automatically applying the second adjusted amplification settings to the test audio; and
in response to automatically applying the second adjusted amplification settings to the test audio, un-applying the adjusted amplification settings to the test audio.

US Pat. No. 10,483,932

METHOD FOR AMPLIFYING AUDIO SIGNAL BASED ON ITS AMPLITUDE AND ELECTRONIC DEVICE SUPPORTING THE SAME

Samsung Electronics Co., ...

1. An electronic device comprising a processor, wherein the processor is configured to:examine a sound level of an audio signal for a preset time, the audio signal obtained from an external source;
check if a frequency with which the examined sound level becomes higher than or equal to a specified level satisfies a preset condition;
change, if the frequency with which the examined sound level becomes higher than or equal to the specified level satisfies the preset condition, a reference level at which a gain value for audio signal amplification is changed in accordance with an amplitude change of the audio signal, for at least one section of the audio signal satisfying the preset condition; and
amplify the at least one section of the audio signal according to the changed reference level.

US Pat. No. 10,483,931

AUDIO DEVICE, SPEAKER DEVICE, AND AUDIO SIGNAL PROCESSING METHOD

YAMAHA CORPORATION, Hama...

9. A speaker device comprising:an audio device comprising;
a user interface that receives a user instruction to set a volume of an input signal;
a volume control circuit that generates a first audio signal obtained by adjusting the volume of the input signal in accordance with the user instruction;
filters that change frequency characteristics of the first audio signal;
a first detecting circuit that detects a volume of the first audio signal where the frequency characteristics thereof have been changed by the filters; and
a low-frequency component adjusting circuit that generates a second audio signal by:
lowering a level of a low-frequency component of the first audio signal in a case where the volume detected by the first detecting circuit exceeds a predetermined threshold; and
without lowering the level of the low-frequency component of the first audio signal in a case where the volume detected by the first detecting circuit does not exceed the first predetermined threshold; and
at least one speaker that emits sound based on the second audio signal.

US Pat. No. 10,483,929

POWER AMPLIFIER SELF-HEATING COMPENSATION CIRCUIT

pSemi Corporation, San D...

1. A compensation circuit configured to monitor a target circuit having one or more performance parameters affected by self-heating during operation of the target circuit, wherein the compensation circuit is configured to be coupled to and adjust circuitry controlling the one or more circuit parameters of the target circuit sufficient to substantially offset the effect of self-heating during operation of the target circuit on the one or more performance parameters, the compensation circuit including:(a) at least one sensor located with respect to the target circuit so as to measure the temperature of the target circuit and generate an output signal T representing such temperature;
(b) at least one sample and hold circuit, each coupled to at least one sensor through an amplifier coupled between the at least one sensor and the at least one sample and hold circuit, configured to capture a temperature T(t=t0) at a time t0 after the commencement of operation of the target circuit, and to sample a temperature T(t>t0) at times after time t0 and during operation of the target circuit;
(c) a comparison circuit, coupled to at least one sample and hold circuit, for determining a signal ?T=T(t>t0)?T(t=t0); and
(d) a mapping circuit, coupled to the comparison circuit, for receiving values of the signal ?T and mapping the values of the signal ?T to corresponding control signal values, the compensation circuit being configured to couple the control signal values to the circuitry controlling the one or more circuit parameters of the target circuit.

US Pat. No. 10,483,928

POWER AMPLIFICATION MODULE

MURATA MANUFACTURING CO.,...

1. A power amplification module comprising:a first input terminal receiving a first transmit signal in a first frequency band;
a second input terminal receiving a second transmit signal in a second frequency band having a narrower transmit/receive frequency interval than the first frequency band;
a first amplification circuit receiving and amplifying the first transmit signal to produce a first amplified signal and outputting the first amplified signal;
a second amplification circuit receiving and amplifying the second transmit signal to produce a second amplified signal and outputting the second amplified signal; and
an attenuation circuit located between the second input terminal and the second amplification circuit and configured to attenuate a component of the second frequency band,
wherein no attenuation circuit is located between the first input terminal and the first amplification circuit, wherein:
the first and second frequency bands are between 699 MHz and 915 MHz.

US Pat. No. 10,483,927

AMPLIFIER ERROR CURRENT BASED ON MULTIPLE INTEGRATORS

TEXAS INSTRUMENTS INCORPO...

1. An amplifier, comprising:a first integrator to receive a differential input signal;
a second integrator coupled to the first integrator;
a third integrator coupled to the second integrator;
a comparator to receive outputs of the second and third integrators, to compare each of the outputs to a reference signal that is below a power supply rail voltage supplied to the amplifier, and to produce an error current based on the comparison; and
a feedback connection between the comparator and inputs to the second integrator, wherein the feedback connection injects the inputs to the second integrator with a current that is determined at least in part by the error current.

US Pat. No. 10,483,926

POWER AMPLIFIER MODULE WITH POWER SUPPLY CONTROL

Skyworks Solutions, Inc.,...

1. A power amplification control system comprising:an interface configured to receive a transceiver control signal from a transceiver, the interface including one or more control registers including one or more power amplifier control registers and one or more power supply control registers;
a power amplifier control component configured to generate a power amplifier control signal based on the transceiver control signal from the transceiver and configured to generate a local control signal based on a sensed condition of a power amplifier of the power amplification control system, the power amplifier control component configured to overwrite one or more of the power supply control registers with the local control signal; and
a power supply control component configured to generate a power supply control signal based on the transceiver control signal from the transceiver and the local control signal from the power amplifier control component.

US Pat. No. 10,483,925

CIRCUIT MODULE HAVING DUAL-MODE WIDEBAND POWER AMPLIFIER ARCHITECTURE

MEDIATEK INC., Hsin-Chu ...

1. A circuit module, comprising:a first power amplifier, having a signal input node coupled to an input signal, a signal output node to generate an output signal, and a power input node coupled to a supply output signal of a supply modulator;
a first switch, externally coupled to the first power amplifier, coupled between the power input node of the first power amplifier and a first bypass capacitor; and
the first bypass capacitor, coupled between the first switch and a ground level;
wherein a distance from the first bypass capacitor to the first power amplifier is shorter than a distance from the first bypass capacitor to the supply modulator.

US Pat. No. 10,483,918

DOHERTY POWER AMPLIFIER FOR RADIO-FREQUENCY APPLICATIONS

Skyworks Solutions, Inc.,...

18. A wireless device comprising:a transmitter circuit configured to generate a signal;
a power amplifier configured to amplify the signal, and including a carrier amplifier having first and second differential amplification cells with outputs coupled by a primary loop of a carrier transformer, and a peaking amplifier having first and second differential amplification cells with outputs coupled by a primary loop of a peaking transformer, the power amplifier further including a combiner having a quarter-wave circuit implemented between a first end of a secondary loop of the carrier transformer and a first end of a secondary loop of the peaking transformer, the quarter-wave circuit configured such that the carrier and peaking amplifiers are presented with a desired impedance when both of the carrier and peaking amplifiers are turned on, and the carrier amplifier is presented with an impedance that is approximately twice the desired impedance when the carrier amplifier is turned on and the peaking amplifier is turned off, the power amplifier further including an output node implemented at a second end of the secondary loop of the carrier transformer; and
an antenna in communication with the output node of the power amplifier and configured to support transmission of the amplified signal.

US Pat. No. 10,483,917

POWER AMPLIFIER FOR MILLIMETER WAVE DEVICES

GLOBALFOUNDRIES INC., Gr...

1. An apparatus, comprising:a first circuit configured to provide an injection current, the first circuit comprising at least a first transistor, wherein a tuning of an injection current is at least partially controlled by a first back gate voltage of the first transistor;
an oscillator circuit configured to receive the injection current, wherein the oscillator circuit comprises a second transistor, wherein an oscillator circuit current tuning is at least partially controlled by a second back gate voltage of the second transistor; and
a back gate voltage source capable of providing the first back gate voltage and the second back gate voltage.

US Pat. No. 10,483,916

SYSTEMS AND METHODS FOR RING-OSCILLATOR BASED OPERATIONAL AMPLIFIERS FOR SCALED CMOS TECHNOLOGIES

SEAMLESS MICROSYSTEMS, IN...

1. A closed loop amplifier, comprising:a first oscillator having an input and a plurality of N outputs;
a second oscillator having an input and a plurality of N outputs;
a plurality of N phase detectors, each of the plurality of N phase detectors has a first input, a second input, a first output, and a second output, wherein each first input of each phase detector is coupled to respective one of the plurality of N outputs of the first oscillator, wherein each second input of each phase detector is coupled to respective one of the plurality of N outputs of the second oscillator;
a first impedance element having two terminals, wherein one terminal is coupled to the input of the first oscillator;
a second impedance element having two terminals, wherein one terminal is coupled to the input of the second oscillator;
a plurality of N third impedance elements, each of the plurality of N third impedance elements has a first terminal and a second terminal, wherein each first terminal of each third impedance element is coupled to the input of the first oscillator, wherein each second terminal of each third impedance element is coupled to respective one first output of the plurality of N phase detectors; and
a plurality of N fourth impedance elements, each of the plurality of N fourth impedance elements has a first terminal and a second terminal, wherein each first terminal of each fourth impedance element is coupled to the input of the second oscillator, wherein each second terminal of each fourth impedance element is coupled to respective one second output of the plurality of N phase detectors,
wherein the closed loop amplifier amplifies a continuous-time continuous-amplitude signal to a continuous-time discrete-amplitude signal.

US Pat. No. 10,483,914

VERY HIGH FIDELITY AUDIO AMPLIFIER

DEVIALET, Paris (FR)

1. An audio amplifier comprising:an input for an audio signal to be amplified and an output for powering a load on the basis of the amplified audio signal;
a generator of reference voltage of very high linearity and low output impedance, able to receive, as input, the audio signal to be amplified;
a power current generator comprising a power voltage generator whose output is connected to the output of the reference voltage generator through a coupling impedance;
the coupling impedance comprising two coupling inductances mounted in series between the output of the reference generator and the output of the power voltage generator and an attenuation impedance linking a mid-point between the two coupling inductances and a reference potential,
wherein the attenuation impedance comprises an attenuation inductance.

US Pat. No. 10,483,912

NON-INVERTING MULTI-MODE OSCILLATOR

1. An oscillator circuit, comprising:a non-inverting sustaining amplifier, the non-inverting sustaining amplifier comprises an amplifier input and an amplifier output; and
a feedback network, the feedback network comprises:
a crystal, the crystal of the feedback network connected between the amplifier input and the amplifier output of the non-inverting sustaining amplifier;
an input portion, the input portion connected between the amplifier input and ground, the input portion comprises an inductor, a tank circuit capacitor, and a tank circuit resistor, wherein the inductor forms a first path between the amplifier input and ground, and wherein the tank circuit capacitor and the tank circuit resistor are connected in series and form a second path between the amplifier input and ground, the second path being separate from but parallel to the first path; and
an output portion, the output portion connected between the amplifier output and ground, the output portion comprises a capacitor.

US Pat. No. 10,483,911

MOS TRANSISTOR-BASED RF SWITCH TOPOLOGIES FOR HIGH SPEED CAPACITIVE TUNING OF OSCILLATORS

Intel Corporation, Santa...

1. A switch circuit for a digitally controlled oscillator having a low varactor switching transient, comprising:a main switch device comprising a gate connected to a control terminal, a drain connected to a first terminal that is connected to a first capacitor, and a source connected to a second terminal that is connected to a second capacitor;
a first n-channel metal-oxide semiconductor (NMOS) device comprising a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the first terminal;
a second NMOS device comprising a gate connected to the main switch device gate, a source connected to the ground, and a drain connected to the second terminal; and
a first and a second p-channel metal-oxide semiconductor (PMOS) device each comprising a gate and a source each connected to a PMOS common junction, the PMOS common junction connected to the ground, a drain of the first PMOS device connected to the first terminal, and a drain of the second PMOS device connected to the second terminal,
wherein the first and second PMOS devices are configured to provide a finite resistance and predefined direct current (DC) voltage to the first and second NMOS devices when an off control signal is applied to the control terminal and the main switch device and the NMOS devices are in an off state.

US Pat. No. 10,483,910

MULTIPORT INDUCTORS FOR ENHANCED SIGNAL DISTRIBUTION

Credo Technology Group Li...

1. An integrated circuit comprising:a substrate; and
an inductor having:
multiple loops on said substrate, each loop defining a corresponding dipole, said dipoles summing to zero with two side loop dipoles being equal and arranged symmetrically relative to a center loop dipole;
a drive port on an outer perimeter of the inductor; and
a sense port connected to taps on the outer perimeter, the sense port positioned diametrically opposite the drive port.

US Pat. No. 10,483,909

METHODS AND APPARATUS FOR GENERATING A HIGH SWING IN AN OSCILLATOR

TEXAS INSTRUMENTS INCORPO...

1. An oscillator comprising:a tank having an enable input, a tank output, and first and second nodes, the tank configured to generate an oscillating output signal at the tank output responsive to an enable signal at the enable input, the oscillating output signal corresponding to a voltage differential between a first node voltage at the first node and a second node voltage at the second node;
a feedback generator including:
a first feedback loop coupled to the first node, the first feedback loop, configured to provide a first charge at the first node to maintain the oscillating output signal, the first feedback loop including: a sine-to-square wave converter having a converter input and a converter output, the converter input coupled to the first node, and the sine-to-square wave converter configured to amplify and convert an oscillating voltage at the first node to a square wave at the converter output; and a logic gate having first and second logic gate inputs and a logic gate output, the first logic gate input coupled to the converter output, the second logic gate input coupled to the enable input, the logic gate output coupled to the first node, and the logic gate configured to provide an output voltage at the logic gate output when the enable signal and the square wave are above a threshold; and
a second feedback loop coupled to the second node, the second feedback loop configured to provide a second charge at the second node to maintain the oscillating output signal, in which a voltage swing of the oscillating output signal is greater than ±Vb, and Vb is a breakdown voltage of the active components; and
an attenuator, coupled between the first node and the feedback generator, and coupled between the second node and the feedback generator, the attenuator configured to isolate the tank from the active components.

US Pat. No. 10,483,908

WEARABLE POWER MANAGEMENT SYSTEM

SHENZHEN DANSHA TECHNOLOG...

1. A wearable power management system comprising:a bottom coating layer;
a bottom center layer disposed above the bottom coating layer;
a circuit layer disposed above the bottom center layer;
a top center layer disposed above the circuit layer; and
a top coating layer disposed above the top center layer; wherein:
the Young's modulus of both the bottom center layer and the top center layer is in the range of 2.5 kPa-4.5 kPa and the thickness of both the bottom center layer and the top center layer is in the range of 250 um-350 um;
the Young's modulus of both the bottom coating layer and the top coating layer is in the range of 50 kPa-70 kPa and the thickness of both the bottom coating layer and the top coating layer is in the range of 250 um-350 um;
the circuit layer comprises a device layer and a connection layer disposed above the device layer;
the device layer comprises a device matrix and alloy connection wires, the device matrix comprising a plurality of cells and a plurality of rechargeable batteries;
odd rows of the device matrix comprise a plurality of solar cells;
even rows of the device matrix comprise a plurality of rechargeable batteries;
the solar cells are composite semiconductor solar cells with thickness between 30 um-40 um;
the rechargeable batteries are lithium-ion chip cells y with thickness between 180 um-220 um;
the alloy connection wires are connected and conducting between the device layer and the connection layer, and made of indium silver alloy;
the connection layer comprises a connection wire network, the connection wire network comprising a plurality of connection wires and overlapping with the device matrix;
each device in the device matrix is connected to an adjacent device in the device matrix through the alloy connection wires and the connection wires of the connection network;
the connection wires essentially have a shape of sine waveforms; and
the connection layer comprises:
a first polyimide layer;
a copper layer disposed above the first polyimide layer; and
a second polyimide layer disposed above the copper layer.

US Pat. No. 10,483,907

ELECTRICAL CONNECTION DEVICE FOR A PHOTOVOLTAIC SYSTEM

ArcelorMittal, Luxembour...

1. A building exterior cladding panel comprising:an upper transverse edge including an upper overlap area intended to be covered by an adjacent panel;
a lower transverse edge including a lower overlap area intended to overlap a further adjacent panel;
a central part connecting the upper and lower transverse edges, covered by at least one photovoltaic module including an electrical pole on a longitudinal extremity and a further electrical pole of reverse polarity on another longitudinal extremity;
a perforation located in the lower overlap area and traversed by an electrical cable connecting one of the two electrical poles of the photovoltaic module to an electrical plug located on a reverse side of the panel in the lower overlap area;
an opening located in the upper overlap area, into which is inserted an electrical junction box connected to the other of the two electrical poles of the photovoltaic module by an electrical cable, the electrical junction box comprising:
a base;
a lateral wall surrounding and extending perpendicular to the base, the lateral wall including, on an external surface, a peripheral shoulder intended to hold the electrical junction box in place in the opening;
a cable outlet, situated in a part of the junction box located above the peripheral shoulder to connect the electrical junction box to the other electrical pole of the photovoltaic module;
an internal cavity delimited by the base and the wall, including an electrical terminal with an axis perpendicular to the base, intended for the connection of an electrical plug located on a reverse side of the or the further adjacent exterior cladding panel;
a movable electrical switch connecting the electrical terminal to the cable outlet and located on the lateral wall of the junction box.

US Pat. No. 10,483,906

PHOTOVOLTAIC SOLAR CONVERSION

Orenko Limited, Cambridg...

1. A photovoltaic solar conversion apparatus comprising:a plurality of photovoltaic chips arranged to convert sunlight into electrical energy;
a plurality of coupling devices operable to secure a plurality of optical fibers in a configuration with a light transmission end-face arranged to couple sunlight transported by the optical fibers onto photosensitive surfaces of the photovoltaic chips;
a carrier which supports the photovoltaic chips, with each of the coupling devices being arranged to couple sunlight transported by a respective one or more of the optical fibers to a corresponding photovoltaic chip; and
a rack having a horizontally disposed rack mounting, wherein the coupling devices are fixedly mounted on the rack with respect to the rack mounting, and the carrier is movably mounted in alignment with the coupling devices with respect to the rack mounting for ease of replacement.

US Pat. No. 10,483,905

IMAGE PRODUCING NANOSTRUCTURE SURFACE

4. A method of fabricating an image producing surface for covering a solar panel having reflective nanostructures generating a reflective color image of the solar panel on the image producing surface using reflected light, comprising:dispensing an X-Y planar layer of curable, polar material upon a substrate of the image producing surface on the solar panel;
applying one or more X-Y planar polarizing fields to said planar layer;
selectively curing a pattern of nanostructures on the planer layer of polar material specifically chosen to reflect selective wavelengths of light while allowing the remaining wavelengths outside the reflective band to pass through the planar layer with no attenuation to create the reflective color image.

US Pat. No. 10,483,902

SYSTEM AND METHOD FOR REDUCING CURRENT HARMONIC DISTORTION IN A MOTOR CONTROLLER

Rockwell Automation Techn...

1. A system for reducing current harmonic distortion in a motor controller, wherein the motor controller is operative to control operation of a multi-phase motor, the system comprising:at least two inputs, each input configured to receive a feedback signal corresponding to a current present in one phase of the motor;
a reference frame transformer operative to convert the feedback signals from the at least two inputs to a first synchronous current feedback signal and a second synchronous current feedback signal, wherein the first synchronous current feedback signal is at a fundamental frequency and the second synchronous current feedback signal is at a harmonic frequency;
a first current regulator configured to receive a current reference signal and the first synchronous current feedback signal as inputs and to generate a first regulator output signal corresponding to desired operation of the motor at the fundamental frequency; and
a second current regulator configured to receive the second synchronous current feedback signal as an input and to generate a second regulator output signal at the harmonic frequency, wherein the motor controller is operative to sum the first regulator output signal and the second regulator output signal to generate a modified current regulator output signal.

US Pat. No. 10,483,899

MODULATION SCHEME FOR MULTIPHASE MACHINES

KSR IP Holdings, LLC, Wi...

1. An electrical power system for a six-phase electric motor comprising:a first set of three-phase windings,
a second set of three-phase windings,
a first pulse width modulator operating at a conversion frequency and a first phase which converts a DC power source to an alternating current, said first pulse width modulator being electrically connected to said first set of three-phase windings,
a second pulse width modulator operating at said conversion frequency and a second phase which converts said DC power source to an alternating current, said second pulse width modulator being electrically connected to said second set of three-phase windings,
wherein said first and second phases are offset from each other by between 80 and 100 degrees to thereby reduce ripple current in said windings.

US Pat. No. 10,483,898

MOTOR CONTROL SYSTEM FOR ELECTRIC MOTOR AND METHOD OF USE

Regal Beloit America, Inc...

1. A motor control system for operating an electric motor, said motor control system comprising:a power supply module disposed external to the electric motor and configured to convert an alternating current (AC) voltage at a first level to a direct current (DC) voltage at a second level lower than a DC-equivalent voltage of the AC voltage at the first level; and
a motor control assembly coupled to the electric motor, said motor control assembly comprising:
an input power connector configured to receive the DC voltage at the second level from said power supply module; and
an inverter module coupled to said input power connector, said inverter module configured to convert the DC voltage at the second level to an AC motor voltage to operate the electric motor.

US Pat. No. 10,483,895

METHOD AND APPARATUS FOR WIRELESS POWER TRANSFER TO AN INDEPENDENT MOVING CART

Rockwell Automation Techn...

1. An apparatus for wireless power transfer in a motion control system, the apparatus comprising:a plurality of movers;
a plurality of electrical devices; wherein at least one of the electrical devices is mounted to each of the plurality of movers;
a closed track defining a continuous path along which each of the plurality of movers travels;
a primary winding mounted along the closed track including a primary forward conduction path and a primary reverse conduction path, wherein the primary forward conduction path and the primary reverse conduction path are spaced apart from each other and extend longitudinally in a direction of travel along the continuous path and wherein the primary winding is configured to receive power from a power supply;
a plurality of secondary windings, wherein:
each secondary winding is mounted to one of the plurality of movers,
each secondary winding includes a secondary forward conduction path and a secondary reverse conduction path,
the secondary forward conduction path and the secondary conduction path are spaced apart from each other and extend along the mover in the direction of travel, and
each of the secondary forward and reverse conduction paths are generally aligned with the primary forward and reverse conduction paths with an air gap separating the secondary forward and reverse conduction paths from the primary forward and reverse conduction paths as the mover travels along the closed track; and
a plurality of power converters, wherein each of the plurality of power converters is mounted to one of the plurality of movers and is operative to receive power from the secondary winding mounted to the mover and to supply power to the at least one electrical device mounted on the mover.

US Pat. No. 10,483,892

VARIABLE MAGNETIZATION MACHINE CONTROLLER

Nissan Motor Co., Ltd., ...

13. A variable magnetization machine control system comprising:a controller configured to detect a magnetization state of a variable magnetization machine and carry out a control to change the magnetization state of the variable magnetization machine based on the detected magnetization state,
the controller being further configured to output a control signal indicating a speed and a torque of the variable magnetization machine for controlling the speed and the torque of the variable magnetization machine, configured to output an ideal magnetization state of a low-coercive-force magnet of the variable magnetization machine based on the speed and the torque indicated by the control signal, and configured to adjust a shape of a d-axis current waveform and a shape of a q-axis current waveform in accordance with the ideal magnetization state of the low-coercive-force magnet of the variable magnetization machine to generate an adjusted d-axis current waveform and an adjusted q-axis current waveform that provide a driving voltage to drive the variable magnetization machine at a predetermined speed associated with the ideal magnetization state of the low-coercive-force magnet of the variable magnetization machine while maintaining the driving voltage below a predetermined maximum magnitude, and
the controller being configured to adjust the d-axis current waveform and the q-axis current waveform by making slopes at leading and trailing edges of the d-axis current waveform and the q-axis current waveform for a high driving voltage more gentle relative to slopes at leading and trailing edges of the d-axis current waveform and the q-axis current waveform for a low driving voltage that is lower than the high driving voltage.

US Pat. No. 10,483,891

DOUBLE STATOR PERMANENT MAGNET MACHINE WITH MAGNETIC FLUX REGULATION

HAMILTON SUNDSTRAND CORPO...

1. A permanent magnet (PM) dynamoelectric machine with directly controllable PM flux control comprising:a drive shaft;
a PM rotor assembly with multiple PMs arranged annularly around an outer periphery of the PM rotor assembly;
a first stator assembly comprising a ferromagnetic stator yoke, a first plurality ferromagnetic stator teeth mounted to the stator core with distal ends proximate the outer axial periphery of the rotor assembly separated by a first air gap and a first plurality of stator coils mounted between the stator teeth of the first plurality of stator teeth; and
a second stator assembly comprising a second ferromagnetic stator yoke, a second plurality of ferromagnetic stator teeth mounted to the stator core with distal ends proximate an inner periphery of the rotor assembly separated by a second air gap and at least one control coil, the at least one control coil wrapped about a saturable region of each the second plurality of stator teeth;
wherein each saturable region of the second plurality of stator teeth is operable as a magnetic diverter to divert air gap magnetic flux (?g) generated by the multiple PMs across the second air gap through the distal ends of the second plurality of stator teeth.

US Pat. No. 10,483,890

ENGINE GENERATOR COMPRISING AN ELECTRICAL LOAD-DEPENDENT DELTA TO WYE SWITCHING UNIT

Honda Motor Co., Ltd., T...

1. An engine generator, comprising:a general purpose engine, an engine speed of the engine being configured to be variably controlled;
a generator unit having a three-phase winding and configured to be driven by the engine to generate power;
an inverter unit configured to convert alternating current output from the generator unit to alternating current of a predetermined frequency to output to a load;
a connection switching unit configured to switch a connection configuration of the winding to one of a wye-connection and a delta-connection;
a load detection unit configured to detect a power consumption of the load; and
a connection switching control unit configured to control the connection switching unit to switch the connection configuration to the wye-connection when the power consumption of the load detected by the load detection unit is equal to or lower than a predetermined value, and to switch the connection configuration to the delta-connection when the power consumption of the load detected by the load detection unit is higher than the predetermined value.

US Pat. No. 10,483,889

OPERATION OF A LOCAL ALTERNATING CURRENT NETWORK WITH A GENSET AND A UPS

PILLER GROUP GMBH, Oster...

1. A method of operating a local AC power grid comprising a genset which includes a combustion engine and a generator, and an uninterruptable power supply (UPS) which includes an energy storage, the method comprisingdefining a frequency of an AC voltage of the AC power grid present at the genset by means of the UPS;
altering the frequency of the AC voltage defined by means of the UPS in one direction away from a desired frequency, if a present power demand in the AC power grid increases beyond a present power supply in the AC power grid, and altering the frequency of the AC voltage defined by means of the UPS in the other direction away from the desired frequency, if the present power demand falls below the present power supply in the AC power grid;
with increasing power demand of the AC power grid, limiting an alteration of the frequency of the AC voltage defined by means of the UPS in the one direction to a maximum value in that missing power is temporarily fed out of the energy storage into the AC power grid;
keeping a shift of the frequency of the AC voltage defined by means of the UPS in the one direction away from the desired frequency until no more power flows out of the energy storage into the AC power grid; and
responding to deviations of the frequency of the AC voltage of the AC power grid from the desired frequency in one direction by an increase of a genset power supplied by means of the genset, and responding to deviations of the frequency of the AC voltage of the AC power grid from the desired frequency in the other direction by a reduction of the genset power supplied by means of the genset.

US Pat. No. 10,483,888

PERMANENT MAGNET SYNCHRONOUS GENERATOR BASED DIRECT CURRENT POWER GENERATING SYSTEM

HAMILTON SUNDSTRAND CORPO...

1. A method of compensating for rotor position error of a rotor of a permanent magnet synchronous generator (PMG) that provides electrical power to a direct current (DC) power generating system, the method comprising:obtaining PMG phase voltages and resolver processed angular position output signals by a resolver-to-digital (R/D) converter of the DC power generating system when the PMG is driven by a prime mover;
filtering the PMG phase voltages by a filter;
sending the filtered PMG phase voltages to a digital signal processor (DSP) component including at least one computer processor and at least one computer readable storage medium;
selecting a PMG fundamental phase voltage waveform from the filtered PMG phase voltages and by the at least one computer processor;
converting a mechanical angle of a rotor into an electrical angle by the at least one computer processor of an electrical angle and frequency derivation component of the DC power generating system;
aligning the electrical angle within the mechanical angle with a corresponding PMG fundamental phase voltage angle by adjusting offset to the electrical angle;
storing a plurality of resolver error offset values associated with the electrical angle into a computer readable storage medium of the at least one computer readable storage medium;
adding additional values to the compensation table by interpolating data between two corresponding resolver error offset values of the plurality of resolver error offset values by a computer processor of the at least one computer processor; and
running the prime mover at a pre-determined speed before obtaining the PMG phase voltages;
further comprising:
feeding an excitation signal to a resolver rotor coil;
feeding sinusoidal and cosine-shaped signals from respective coils of a resolver associated with a rotor of the PMG;
deriving angular and speed values by the R/D converter; and
feeding the angular and speed values to the DSP component before running the prime mover;
wherein the resolver comprises a two-pole resolver;
wherein the resolver is frameless; and
wherein the PMG includes about twenty-eight poles.

US Pat. No. 10,483,882

DRIVE DEVICE

Toyota Jidosha Kabushiki ...

1. A drive device comprising:a motor;
an inverter configured to drive the motor with switching of a plurality of switching elements; and
a rotation angle detector configured to detect a rotation angle of the motor, the rotation angle detector including a resolver and an electronic control unit, wherein:
the resolver is attached to a rotational shaft of the motor and is configured to output a signal according to rotation of the motor;
the electronic control unit is configured to convert a signal from the resolver to a master rotation angle of the motor;
the electronic control unit is configured to convert a signal obtained by attenuating a high frequency component of a frequency higher than a predetermined frequency with respect to the signal from the resolver to a slave rotation angle of the motor; and
the electronic control unit is configured to determine that the master rotation angle is normal when a determination condition that a difference between the master rotation angle and the slave rotation angle is equal to or greater than a first threshold and a temporal variation as a variation of the master rotation angle per unit time is equal to or greater than a second threshold is not established, and determine that the master rotation angle is abnormal when the determination condition is established.

US Pat. No. 10,483,881

SYSTEMS AND METHODS FOR MOTOR TORQUE COMPENSATION

INTUITIVE SURGICAL OPERAT...

18. A teleoperative medical device comprising:a manipulator arm;
a medical instrument detachably connected to the manipulator arm;
a plurality of motors connected to the manipulator arm, each motor of the plurality of motors configured to move the medical instrument in a different manner from another of the plurality of motors;
a control system comprising a processor and a memory, the memory comprising machine readable instructions that when executed by the processor, cause the control system to:
store a separate compensation profile for each motor of the plurality of motors, each compensation profile configured for controlling an input signal to a respective motor, each compensation profile defining adjustments to the input signal of the respective motor as a second function of a rotor angle of the respective motor, each compensation profile being based on a torque profile associated with the respective motor, wherein the torque profile associated with the respective motor defines torque output as a first function of the rotor angle at a set of discrete loads; and
apply each compensation profile during operation of each of the plurality of motors.

US Pat. No. 10,483,879

ON-LOAD TAP CHANGER AND METHOD OF AND SYSTEM FOR OPERATING SAME

MASCHINENFABRIK REINHAUSE...

1. An on-load tap changer for uninterrupted switching between winding taps of a control winding, comprisinga changeover switch that has a first changeover contact, a second changeover contact and a third changeover contact and that can assume a first position in which the first and third changeover contacts are connected to each other, a second position in which the second and third changeover contacts are connected to each other, and a bridging position in which the first, second, and third changeover contacts are connected to one another;
a first fixed contact that can be connected with an associated first winding tap;
a second fixed contact that can be connected with an associated second winding tap;
a first movable contact that can selectably contact each of the fixed contacts
a second movable contact that can selectably contact each of the fixed contacts;
a main branch that connects the first movable contact with the first changeover contact;
an auxiliary branch that connects the second movable contact with the second changeover contact by a current-limiting resistor or varistor; and
a switching element connected between the main branch and the second changeover contact.

US Pat. No. 10,483,878

ELECTRO-ADHESION GRIPPERS WITH FRACTAL ELECTRODES

1. An electroadhesion gripper for holding workpieces, comprising:a first electrode and a second electrode that mutually engage, in a plan view of the electrodes,
wherein, at least in a sub-region, the first electrode and the second electrode correspond to border lines of a two-dimensional fractal space-filling curve of a second or higher order, and
wherein the border lines result from enclosing a shape of the space-filling curve on both sides on an auxiliary grid that is offset with respect to a grid of the space-filling curve by half a grid spacing in each grid direction.

US Pat. No. 10,483,876

ELECTROSTATICALLY DEFLECTABLE MICROMECHANICAL DEVICE

1. A micromechanical device comprising:a deflectable element, wherein the deflectable element comprises:
an electrostatic actuator which is implemented as a plate capacitor extending along and spaced apart in a deflection direction from a neutral fiber of the deflectable element,
the capacitor comprising a distal electrode and a proximal electrode, wherein the proximal electrode is arranged between the distal electrode and the neutral fiber and the plate capacitor is subdivided along a direction into segments between which the distal electrode is fixed mechanically at segment boundaries such that the deflectable element, by providing the plate capacitor with a voltage, is deflected along the direction in or opposite to the deflection direction; and
wherein the proximal electrode is arranged at a side of an insulation material of the deflectable element facing the distal electrode and is structured along the direction so as to comprise gaps at the segment boundaries such that the distal electrode is mounted mechanically to the insulation material at the segment boundaries in a manner laterally spaced apart from the proximal electrode.

US Pat. No. 10,483,875

SURFACE ELASTIC WAVE GENERATOR, TRANSCEIVER, AND GENERATION METHOD THEREOF

Industrial Technology Res...

1. A surface elastic wave generator comprising:a substrate;
a first conductivity type region formed in the substrate; and
a second conductivity type doped region doped on a surface of the first conductivity type region, a depletion capacitance region being formed through applying reverse bias to junctions between the first conductivity type region and the second conductivity type doped region, a surface elastic wave being generated on the substrate through inputting an alternating current signal to the first conductivity type region or the second conductivity type doped region,
wherein the second conductivity type doped region comprising at least one doping pattern.

US Pat. No. 10,483,874

REVERSIBLE AC-DC AND DC-AC THYRISTOR CONVERTER

STMicroelectronics (Tours...

1. A reversible converter, comprising:a first field effect transistor and a second field effect transistor coupled in series between a first terminal and a second terminal associated with a DC voltage;
an inductive element linking a first midpoint of the series coupling of the first and second field effect transistors to a first terminal associated with an AC voltage;
a first thyristor and a second thyristor coupled in series between the first and second terminals associated with the DC voltage, wherein a second midpoint of the series coupling of the first thyristor and the second thyristor is linked to a second terminal associated with said AC voltage, and wherein an anode of the first thyristor and a cathode of the second thyristor are coupled to said second midpoint; and
a third thyristor and a fourth thyristor coupled in series between the first and second terminals associated with the DC voltage, wherein a third midpoint of the series coupling of the third thyristor and the fourth thyristor is directly connected to the second midpoint, and wherein a cathode of the third thyristor and an anode of the fourth thyristor are coupled to said third midpoint.

US Pat. No. 10,483,873

POWER CONVERSION APPARATUS AND CONTROL METHOD OF INVERTER

OMRON Corporation, Kyoto...

1. A power conversion apparatus, comprising:an inverter comprising a plurality of legs constituted by a pair of switching elements connected in series and converting DC power into AC power by drive controlling a plurality of the switching elements;
a plurality of drive circuits driving the plurality of the switching elements;
a control circuit outputting a control signal of the plurality of the switching elements;
a current detection part detecting a direct current inputted to the inverter;
an overcurrent detection circuit detecting overcurrent based on a current detected by the current detection part; and
a protection circuit provided between the control circuit and the plurality of drive circuits,
wherein the overcurrent detection circuit outputs a detection signal indicating detection of overcurrent to the protection circuit when detecting overcurrent,
wherein the protection circuit receives the detection signal,
wherein the protection circuit outputs to the plurality of drive circuits a signal for turning off a switching element when the switching element has been turned on by the control signal from the control circuit for at least a predetermined time,
wherein the protection circuit delays the output of the signal for turning off the switching element when the switching element has been turned on for less than the predetermined time, and outputs the signal for turning off the switching element when the switching element has been turned on for the predetermined time.

US Pat. No. 10,483,872

POWER SUPPLY SYSTEM AND ENERGY STORAGE SYSTEM

GENERAL ELECTRIC COMPANY,...

1. A power supply system, comprising:an auxiliary power supply output terminal for providing an auxiliary power supply;
a first energy storage device;
a first converter comprising a first switch and a second switch which are series-connected, wherein the first converter is coupled to the first energy storage device;
a first transformer that transforms a high voltage from the first energy storage device into a low voltage output from the auxiliary power supply output terminal and comprising a primary winding and a secondary winding, wherein the primary winding of the first transformer is connected between the first energy storage device and a connecting point of the first and the second switches, and a first terminal of the secondary winding of the first transformer is connected to the auxiliary power supply output terminal via a first diode and an opposite terminal thereof is grounded; and
a first capacitor, wherein one terminal of the first capacitor is connected to a negative electrode of the first diode and the other terminal thereof is grounded.

US Pat. No. 10,483,871

POWER CONVERSION APPARATUS AND POWER SYSTEM

Mitsubishi Electric Corpo...

1. A power conversion device comprising:a power converter including a plurality of phase arms in which a first arm and a second arm for each of phases are connected in series to each other, the plurality of phase arms being connected in parallel between positive and negative DC lines, the power converter performing power conversion between three-phase AC and DC; and
a control device which generates respective voltage command values for the first arm and the second arm and performs drive-control of the power converter on the basis of the voltage command values, wherein
the first arm and the second arm each include a converter cell composed of: a first series body having semiconductor switching elements in both of upper and lower arms; and a DC capacitor connected in parallel to the first series body,
the converter cell in the second arm is a second converter cell formed by connecting the DC capacitor, the first series body, and a second series body in parallel, the second series body having a semiconductor switching element in one of upper and lower arms and a diode in the other one, the second converter cell being configured to output positive-polarity and negative-polarity voltages corresponding to a magnitude of both-end voltage of the DC capacitor,
when short-circuit between the DC lines is detected, the control device performs protection control to turn off the semiconductor switching elements in the power converter, and
when elimination of the short-circuit between the DC lines is detected, the control device performs restart control of the power converter by giving a voltage command value for causing negative-polarity current flowing through the diode to flow to the phase arm, to each converter cell in the first arm and the second arm.

US Pat. No. 10,483,868

POWER SUPPLY UNIT WITH RE-RUSH CURRENT LIMITING

DELL PRODUCTS, LP, Round...

1. A method comprising:detecting, by an alternating current (AC) input monitoring circuit, an AC voltage dropout;
placing, by the AC input monitoring circuit, a first transistor in an OFF state in response to detecting the AC voltage dropout, wherein the first transistor is connected in series with a first bulk capacitor of a power supply unit;
detecting that the AC voltage is re-applied;
adopting, by a current source, an adaptive gate voltage to control the first transistor in response to the re-applied AC voltage, wherein the adaptive gate voltage includes diversion of a gate current when the first transistor reaches a plateau region;
providing the diverted gate current to a virtual miller capacitor to set a re-rush current through the first transistor at a constant value; and
turning on the first transistor based on the adaptive gate voltage to keep the first transistor operating in the plateau region.

US Pat. No. 10,483,866

SMART POWER DELIVERY SYSTEM AND RELATED METHOD

AVAGO TECHNOLOGIES INTERN...

1. An electronic device configured to deliver power, comprising:a first circuit configured to connect a power source to a second electronic device via a first power delivery conduit;
a second circuit configured to connect the power source to a third electronic device via a second power delivery conduit, the first power delivery conduit being configured to deliver power to the second electronic device in parallel with the second power delivery conduit delivering power to the third electronic device;
circuitry configured to exchange information with the second electronic device and the third electronic device, wherein the information includes an indication of respective device power requirements; and
a power management module (PMM) configured to manage power delivery to the respective electronic devices, wherein
based on the indication of respective device power requirements, the PMM is configured to manage delivery of power to the second electronic device and the third electronic device by partitioning and dynamically applying the power on a per conduit basis across the first power delivery conduit and the second power delivery conduit, wherein
the PMM is configured to deliver power on at least one of a first-come-first-served basis, a programmed prioritization basis, a quickest time to charge basis, or an equal current partition basis.

US Pat. No. 10,483,865

CONVERTERS FOR WIND TURBINE GENERATORS

1. A system for converting an alternating current (AC) output from a generator of a wind turbine, the system comprising:a first rectifier and a second rectifier of the wind turbine, each rectifier connected to the AC output of the generator and arranged to generate a respective direct current (DC) output, wherein:
a positive DC level output from the first rectifier is applied to a first, positive DC conductor;
a negative DC level output from the first rectifier is connected together with a positive DC level output from the second rectifier and applied to a second, neutral DC conductor; and
a negative DC level output from the second rectifier is applied to a third, negative DC conductor, the first, second, and third DC conductors being arranged to transmit the resulting DC voltages; and
a controller configured to, responsive to sensing a presence of current flowing in the second DC conductor, control the rectifiers to balance current flowing in the first DC conductor and the third DC conductor, wherein the current in the second DC conductor is reduced.

US Pat. No. 10,483,862

BI-DIRECTIONAL ISOLATED DC-DC CONVERTER FOR THE ELECTRIFICATION OF TRANSPORTATION

VANNER, INC., Hilliard, ...

1. A bi-directional DC-DC converter (20) comprising:a first stage (30) comprising:
a first port (22) connected between a first node (N1) and ground;
the first port (22) being bi-directionally operable as an output or an input;
the first port (22) being operatively connected to a primary winding (80) of a first transformer (Tr1);
a second stage (40) comprising:
a second port (24) connected between seventh and eighth nodes (N7), (N8);
the second port (24) being bi-directionally operable as an output or an input;
the second port (24) being operatively connected to a secondary winding (82) of the first transformer (Tr1);
the secondary winding of the first transformer having first and second terminals;
a fifth switch (S5) having first and second terminals
the fifth switch having a body diode,
an anode of the body diode of the fifth switch being connected to the second terminal of the fifth switch,
a cathode of the body diode of the fifth switch being connected to the first terminal of the fifth switch;
a sixth switch (S6) having first and second terminals
the sixth switch having a body diode,
an anode of the body diode of the sixth switch being connected to the second terminal of the sixth switch,
a cathode of the body diode of the sixth switch being connected to the first terminal of the sixth switch;
a seventh switch (S7) having first and second terminals
the seventh switch having a body diode,
an anode of the body diode of the seventh switch being connected to the second terminal of the seventh switch,
a cathode of the body diode of the seventh switch being connected to the first terminal of the seventh switch;
an eighth switch (S8) having first and second terminals
the eighth switch having a body diode,
an anode of the body diode of the eighth switch being connected to the first terminal of the eighth switch,
a cathode of the body diode of the eighth switch being connected to the second terminal of the eighth switch;
a first resonant inductor (Lr1) having first and second terminals;
a first resonant capacitor (Cr1) having first and second terminals;
a second resonant capacitor (Cr2) having first and second terminals;
a third resonant capacitor (Cr3) having first and second terminals;
a fourth resonant capacitor (Cr4) having first and second terminals;
the first terminal of the fifth switch (S5) being connected to the seventh node (N7), the second terminal of the fifth switch (S5) being connected to a sixth node (N6);
the first terminal of the sixth switch (S6) being connected to the sixth node (N6);
the second terminal of the sixth switch (S6) being connected to the eighth node;
the first terminal of the seventh switch (S7) being connected to a tenth node (N10);
the second terminal of the seventh switch (S7) being connected to an eleventh node (N11);
the first terminal of the eighth switch (S8) being connected to the eleventh node (N11);
the second terminal of the eighth switch (S8) being connected to a twelfth node (N12);
the first terminal of the secondary winding (82) of the first transformer (Tr1) being connected to the sixth node (N6);
the second terminal of the secondary winding (82) of the first transformer (Tr1) being connected to a ninth node (N9);
the first terminal of the first resonant inductor (Lr1) being connected to the ninth node (N9);
the second terminal of the first resonant inductor (Lr1) being connected to the tenth node (N10);
the first terminal of the first resonant capacitor (Cr1) being connected to the seventh node (N7);
the second terminal of the first resonant capacitor (Cr1) being connected to the twelfth node (N12);
the first terminal of the second resonant capacitor (Cr2) being connected to the twelfth node (N12);
the second terminal of the second resonant capacitor (Cr2) being connected to the eighth node (N8);
the first terminal of the third resonant capacitor (Cr3) being connected to the seventh node (N7);
the second terminal of the third resonant capacitor (Cr3) being connected to the tenth node (N10);
the first terminal of the fourth resonant capacitor (Cr4) being connected to the tenth node (N10);
the second terminal of the fourth resonant capacitor (Cr4) being connected to the eighth node (N8).

US Pat. No. 10,483,860

PRIMARY SIDE CONSTANT CURRENT REGULATION

SEMICONDUCTOR COMPONENTS ...

1. A current sense circuit, comprising:a first sense diode having a first diode anode and a first diode cathode;
wherein the first diode anode is grounded; and
wherein the first diode cathode is connected to a second terminal of a first coil of a transformer having an operating frequency (TSW);
wherein the first coil includes a first terminal coupled to an input voltage received at an input current (IP);
wherein the transformer includes a second coil coupled to at least one output node providing an output voltage and an output current (IO);
a second sense diode having a second diode anode and a second diode cathode;
a sensing resistor providing a sense resistance;
a sensing capacitor;
wherein the sensing resistor and the sensing capacitor are grounded;
a voltage reference regulator configured to operate at a reference voltage (VREF), comprising:
a ground node;
a first reference node; and
a second reference node;
a set resistor having a set resistance (RSNS);
wherein the set resistor is configured to receive a sensed voltage (VS); and
a compensating resistor having a compensating resistance (RCOMP);
wherein the compensating resistor is connected, in parallel, at the first reference node, to the set resistor;
wherein the second diode anode is connected to the second terminal and the second diode cathode is connected, in parallel, to the sensing resistor, the sensing capacitor, and the compensating resistor at a voltage sense node.

US Pat. No. 10,483,859

AC/DC CONVERTER INCLUDING A BIDIRECTIONAL SWITCH

Rohm Co., Ltd., Kyoto (J...

1. An AC/DC converter comprising:a transformer including a primary winding connected to an AC power source and a secondary winding electromagnetically coupled to the primary winding;
a bidirectional switch connected in series to the primary winding;
a resonant capacitor connected in parallel or series to the bidirectional switch;
a capacitor voltage divider circuit arranged to divide a voltage across both ends of the bidirectional switch so as to generate a divided voltage; and
a control circuit arranged to turn on the bidirectional switch at a timing when the divided voltage becomes zero.

US Pat. No. 10,483,856

SYSTEMS AND METHODS WITH PREDICTION MECHANISMS FOR SYNCHRONIZATION RECTIFIER CONTROLLERS

On-Bright Electronics (Sh...

10. A system controller for a power converter, the system controller comprising:a first controller terminal; and
a second controller terminal;
wherein the first controller terminal is configured to receive an input signal;
wherein the second controller terminal is configured to output a first drive signal to a first switch to affect a first current associated with a first winding of the power converter, the first drive signal being associated with the input signal;
wherein the system controller is configured to:
detect a first duration of a first time period for a second drive signal, the second drive signal being outputted to a second switch to affect a second current associated with a second winding of the power converter, the second winding being coupled to the first winding, the first time period including a first beginning and a first end;
detect a demagnetization duration of a demagnetization period associated with the first winding, the demagnetization period including a second beginning and a second end;
detect a second duration of a second time period for the second drive signal, the second time period including a third beginning and a third end; and
determine a third duration of a third time period for the first drive signal based at least in part on the first duration, the demagnetization duration, and the second duration, the third time period including a fourth beginning and a fourth end, the fourth end being after the first end, the second end, and the third end;
wherein:
the second switch is closed from the first beginning to the first end;
the second switch is open from the first end to the third beginning; and
the second switch is closed from the third beginning to the third end.

US Pat. No. 10,483,854

RESONANT POWER SUPPLY CONVERTER CIRCUIT AND METHOD THEREFOR

SEMICONDUCTOR COMPONENTS ...

1. A method of forming a resonant mode power supply control circuit comprising:configuring the resonant mode power supply control circuit to switchingly control a high-side transistor and a low-side transistor to regulate an output voltage delivered to a load wherein the high-side transistor and the low-side transistor both have a current conducting electrode coupled together at a half-bridge node wherein the half-bridge node is configured for coupling to an inductor;
configuring a switching control circuit to form one or more drive signals to switch the high-side transistor and the low-side transistor in a normal operating mode in response to a first value of the output voltage and to control the high-side and low-side transistors in a light-load operating mode in response to a second value of the output voltage wherein the first value is greater than the second value and wherein the switching control circuit forms the light-load operating mode to include one or more sequences of a drive interval wherein the one or more drive signals are formed to switch the high-side and low-side transistors, followed by an Off-interval wherein the high-side and low-side transistors are not switched;
configuring a light-load control circuit to generate a drive pattern having one or more pulse sets wherein each pulse set is formed to enable the low-side transistor for a substantially fixed time interval, subsequently enable the high-side transistor for a second time interval determined by the output voltage, and subsequently enable the low side transistor for a third time interval formed to be one of proportional to the second time interval or in response to a substantially zero value of a current sense signal; and
configuring the light-load control circuit to measure a duration of the drive interval and the Off-interval and to adjust a number of pulse sets in a subsequent drive pattern for a subsequent drive interval in response to the duration.

US Pat. No. 10,483,853

DC-DC CONVERTER

TOYOTA JIDOSHA KABUSHIKI ...

1. A DC-DC converter, comprising:a high potential input wiring connected to a positive electrode of a direct current source;
a high potential output wiring;
a low potential wiring connected to a negative electrode of the direct current source;
a first lower FET of n-channel type, a source of the first lower FET being connected to the low potential wiring;
a first upper FET of n-channel type, a source of the first upper FET being connected to a drain of the first lower FET, and a drain of the first upper FET being connected to the high potential output wiring;
a second lower FET of n-channel type, a source of the second lower FET being connected to the low potential wiring;
a second upper FET of n-channel type, a source of the second upper FET being connected to a drain of the second lower FET, and a drain of the second upper FET being connected to the high potential output wiring;
a first diode, an anode of the first diode being connected to the source of the first upper FET, and a cathode of the first diode being connected to the drain of the first upper FET;
a second diode, an anode of the second diode being connected to the source of the second upper FET, and a cathode of the second diode being connected to the drain of the second upper FET;
a main reactor comprising a first terminal and a second terminal, the first terminal being connected to the high potential input wiring;
a first sub-reactor, one end of the first sub-reactor being connected to the second terminal of the main reactor, and other end of the first sub-reactor being connected to the drain of the first lower FET;
a second sub-reactor, one end of the second sub-reactor being connected to the second terminal of the main reactor, and other end of the second sub-reactor being connected to the drain of the second lower FET; and
a gate controller connected to a gate of the first lower FET, a gate of the first upper FET, a gate of the second lower FET, and a gate of the second upper FET, wherein
the gate controller is configured to perform a first operation and a second operation based on a variable current flowing through the main reactor,
the gate controller is configured to perform the first operation during a zero-cross mode in which the variable current decreases to zero, and to perform the second operation during a non-zero-cross mode in which the variable current does not decrease to zero,
in the first operation, the gate controller controls the first lower FET, the first upper FET, the second lower FET, and the second upper FET so as to satisfy following conditions:
a first state, a second state, a third state, and a fourth state repeatedly appear in this order, the first state being a state in which the first lower FET is on, the second state being a state in which the first lower FET and the second lower FET are off, the third state being a state in which the second lower FET is on, and the fourth state being a state in which the first lower FET and the second lower FET are off; and
the first upper FET and the second upper FET are not turned on,
in the second operation, the gate controller controls the first lower FET, the first upper FET, the second lower FET, and the second upper FET so as to satisfy following conditions:
a fifth state, a sixth state, a seventh state, and an eighth state repeatedly appear in this order, the fifth state being a state in which the first lower FET is on and the second lower FET is off, the sixth state being a state in which the first lower FET and the second lower FET are off, the seventh state being a state in which the first lower FET is off and the second lower FET is on, and the eighth state being a state in which the first lower FET and the second lower FET are off; and
the first upper FET is turned on in at least a part of a period of the sixth state, and the second upper FET is turned on in at least a part of a period of the eighth state.

US Pat. No. 10,483,849

AUTOMATIC TRANSITION BETWEEN PFM AND PWM MODES IN A SWITCHING REGULATOR

CIREL SYSTEMS PRIVATE LIM...

1. A method of transitioning a switching regulator from a Pulse Frequency Modulation mode to a Pulse Width Modulation mode, the method comprising:measuring a load current in the Pulse Frequency Modulation mode, wherein the load current is measured at an output of the switching regulator by deriving slope of waveform of output voltage at an intersection of an inductor an a load capacitor of the switching regulator, wherein the slope of the waveform of the output voltage is measured during a dead-time of the switching regulator, wherein the dead-time is defined as the time between an instant an NMOS switch is turned OFF by a zero crossing detector to an instant a PMOS switch is turned ON by one of a pulse frequency modulation controller and a pulse width modulation controller;
determining a current threshold setting to be one of an upper threshold and a lower threshold; and
transitioning the switching regulator from the Pulse Frequency Modulation mode to the Pulse Width Modulation mode when the load current measured is greater than the upper threshold.

US Pat. No. 10,483,848

ASSEMBLY FOR CONTROLLING SOLID-STATE SWITCHING ELEMENTS IN AN AIRCRAFT

ZODIAC AERO ELECTRIC, Mo...

1. An assembly for controlling solid-state switching elements in an aircraft having at least one power pathway comprising at least one power line supplying power to at least one item of equipment on board an aircraft from at least one electrical power source via a power switch,at least one control member controlling at least one power switch according to control signals arising from a control means,
wherein the control assembly comprises a single power supply supplying power to all of the control members, the single power supply being electrically isolated with respect to the control means,
wherein the assembly comprises at least one analogue level offset means positioned between the control means and a control member, and
the analogue level offset means being capable of maintaining the amplitude of the control signal transmitted by the control means while changing the reference potential of the control signal from the reference potential of the control means to the reference potential of the control member and of the isolated power supply.

US Pat. No. 10,483,847

POWER CONVERTER CALIBRATION METHOD AND APPARATUS

Infineon Technologies Aus...

1. A power regulator, comprising:a sensor configured to generate a first measurement comprising at least one of a voltage measurement and a current measurement;
a memory configured to store a correction parameter associated with the first measurement;
a correction system configured to adjust the first measurement according to the correction parameter;
a power stage;
a controller configured to regulate an output of the power regulator according to the adjusted first measurement, wherein the controller comprises a PWM (pulse width modulation) circuit configured to provide, to the power stage, a duty cycle based upon the adjusted first measurement.

US Pat. No. 10,483,846

MULTI-MODE CHARGE PUMP

Allegro MicroSystems, LLC...

1. A multi-mode charge pump for generating a regulated voltage at an output node from a battery, comprising:a plurality of flying capacitors;
a plurality of switches, each coupled to at least one of the flying capacitors, wherein the plurality of switches is configured to selectively couple the flying capacitors to the battery, to the output node or to a reference potential;
a storage capacitor selectively coupled to one or more of the flying capacitors, wherein the regulated voltage is provided across the storage capacitor;
a comparator having a first input coupled to receive the regulated voltage, a second input coupled to receive a reference voltage, and an output providing an asynchronous regulation signal; and
a controller configured to automatically transition between operational modes of the multi-mode charge pump by controlling actuation of the plurality of switches in response to the asynchronous regulation signal, wherein the operational mode is selected from a buck mode, a doubler mode, and a tripler mode.

US Pat. No. 10,483,844

CHARGE PUMP ARRANGEMENT AND METHOD FOR OPERATING A CHARGE PUMP ARRANGEMENT

INFINEON TECHNOLOGIES AG,...

1. A charge pump arrangement, comprising:a charge pump circuit configured to convert an input voltage into an output voltage based on a pump clock signal;
a feedback path configured to provide a feedback signal representing the output voltage of the charge pump circuit;
a control circuit configured to receive a clock signal and to control the output voltage of the charge pump circuit by controlling the pump clock signal based on the feedback signal and the clock signal;wherein the feedback path comprises a voltage divider circuit, wherein the voltage divider circuit is coupled to the charge pump circuit to sense the output voltage and further coupled to the control circuit to provide the feedback signal;wherein the voltage divider circuit comprises a first capacitor and a second capacitor coupled in a series arrangement, wherein the feedback signal is tapped between the first capacitor and the second capacitor;additional voltage divider circuit to sense the output voltage of the charge pump circuit and to provide an additional feedback signal for the control circuit; wherein the additional voltage divider circuit comprises a third capacitor and a fourth capacitor coupled in a series arrangement, wherein the additional feedback signal is tapped between the third capacitor and the fourth capacitor; anda switch arrangement configured to switch the charge pump arrangement into a first operation mode and into a second operation mode by switching between the feedback signal of the voltage divider circuit and the additional feedback signal of the additional voltage divider circuit.

US Pat. No. 10,483,843

APPARATUS AND METHODS FOR MULTI-MODE CHARGE PUMPS

Skyworks Solutions, Inc.,...

1. A multi-mode charge pump comprising:a charge pump output terminal configured to provide a charge pump output voltage that is less than a reference voltage;
a mode control circuit configured to operate the multi-mode charge pump in a selected mode chosen from a plurality of modes including a first mode and a second mode;
a first switched capacitor;
a charge pump filter electrically connected to the charge pump output terminal and having a filter resistance that changes based on the selected mode;
a capacitor charging circuit configured to connect a first end of the first switched capacitor to a charging voltage in a first phase of a clock signal, and to connect the first end of the first switched capacitor to the reference voltage in a second phase of the clock signal, the capacitor charging circuit including a plurality of supply selection switches configured to control the charging voltage with a first supply voltage in the first mode and with a second supply voltage in the second mode; and
a plurality of switches configured to connect a second end of the first switched capacitor to the reference voltage in the first phase, and to connect the second end of the first switched capacitor to the charge pump output terminal in the second phase.

US Pat. No. 10,483,842

DRIVE SYSTEM HAVING DC POWER SUPPLY FOR A SUBMARINE

THYSSENKRUPP MARINE SYSTE...

1. A drive system for a submarine comprising:a DC power supply system configured to supply electrical energy to a drive of the submarine;
a plurality of battery strings, wherein each battery string includes a plurality of series-connected battery modules; and
a plurality of string connection units, each of the plurality of string connection units comprising a bidirectional voltage converter and a switching device either connected in series to the bidirectional voltage converter or incorporated into the bidirectional voltage converter for galvanic isolation of each battery string from the DC power supply system, individual ones of the plurality of string connection units connected to a corresponding one of the plurality of battery strings via which each battery string is selectively connected to or disconnected from the DC power supply system, with each of the plurality of string connection units being configured to adjust a string current flowing in each corresponding battery string.

US Pat. No. 10,483,837

VARIABLE FREQUENCY MODULATION SCHEME BASED ON CURRENT-SENSING TECHNIQUES FOR SWITCHED-CAPACITOR DC-DC CONVERTERS

Renesas Electronics Ameri...

1. An apparatus for converting an input voltage at an input to an output voltage at an output, the apparatus comprising:a capacitor, wherein the capacitor is configured such that a charging and discharging of the capacitor transfers energy from the input to the output;
switches configured to control the charging and discharging of the capacitor;
a controller that controls a switching frequency of the switches based on a current associated with the transfer of energy from the input to the output; and
a lookup table coupled to the controller, wherein the controller is configured to set the switching frequency based on the current using one or more entries in the lookup table,
wherein the lookup table stores a plurality of different switching frequency values for a same given current value, and wherein the controller is configured to select a certain at least one of the plurality of different switching frequency values based on the current, and wherein the plurality of different switching frequency values for the same given current value correspond to a plurality of different performance metric values associated with the transfer of energy from the input to the output.

US Pat. No. 10,483,835

LINEAR MOTOR

FANUC CORPORATION, Yaman...

1. A linear motor comprising:a magnet plate on which magnets of different polarity are alternately arranged along a movement direction; and
an armature having a core serving as a main body and a coil attached to the core,
wherein the magnet plate and the armature are made to relatively move along an arrangement direction of the magnets, by way of thrust produced between the magnet plate and the armature,
wherein the magnet plate has a non-thrust region that extends along an arrangement direction of the magnets, and does not contribute to the thrust, and
wherein the core of the armature includes a plurality of main teeth to which the coil is attached and an auxiliary tooth provided between the main teeth which are adjacent to each other, wherein the main teeth and auxiliary tooth are not provided in a region opposing the non-thrust region of the magnet plate.

US Pat. No. 10,483,834

VERTICAL SLIDER WITH BUILT-IN MOVABLE COIL LINEAR MOTOR

NIPPON THOMPSON CO., LTD....

1. A vertical slider comprising: an elongated plate bed constituting opposing plate magnet yokes, a movable table travelling in a reciprocating manner lengthwise of the bed through a ball spline, field magnets lying on opposed surfaces of the magnet yokes each constituted with more than one magnets which are arranged lengthwise in such a relation that unlike poles are alternately adjacent each other and also opposed across a gap, and a movable coil linear motor having an armature assembly lying in the gap between the field magnets and having more than one armature coils is arranged on a coil substrate fastened to the movable table to move in a reciprocating manner relatively to the bed under the electromagnetic mutual relation between a current flow in the armature assembly and the magnetic flux in the field magnet,wherein a hollow ball-spline shaft having a through-hole extends through a lengthwise through-hole of the ball spline shaft is supported for sliding movement by a first outer shell fastened to the underneath of the bed and a second outer shell fastened to an upper portion of the bed,
wherein a foremost nozzle is formed at a lower portion of the through-hole of the ball spline shaft and a rearmost nozzle is formed at a top side of the through-hole of the ball spline shaft,
wherein the bed is composed of an elongated rectangular substrate to provide one of the magnet yokes, an opposite upper plate of rectangular shape less in width and length than the substrate arranged in parallel and in opposition to the substrate while keeping a predetermined interval between them to provide another magnet yoke, and a side plate is fastened to any one of the substrate and the opposite upper plate to provide a mounting reference surface for the substrate,
wherein a location opposing to the substrate other than the portions opposing to the opposite upper plate are covered with a covering fastened to the substrate at a predetermined interval and a plane surface of the opposite upper plate opposing to the substrate is made in a reference surface of the linear motor, and wherein a dimension from the reference surface of the substrate to the outside plane of the covering is made in the width dimension of the slider, and
wherein escape holes are made in a part of the covering and a part of the substrate of the bed opposing to outer shells constituting the ball spline, and the outer shells fit into the escape holes in the covering and the escape holes are designed to have dimensions lying within the thickness dimensions of the substrate and the covering.

US Pat. No. 10,483,833

VIBRATION MOTOR

NIDEC SEIMITSU CORPORATIO...

1. A vibration motor, comprising:a stationary portion, which includes a casing and a coil;
a vibrating body, which includes a magnet and a weight and is supported to be capable of vibrating in a lateral direction relative to the stationary portion;
a first elastic member having a plate shape; and
a second elastic member having a plate shape,
wherein the first elastic member includes a first fastening portion, a second fastening portion, and a first coupling portion,
wherein the second elastic member includes a third fastening portion, a fourth fastening portion, and a second coupling portion,
wherein the first coupling portion couples the first fastening portion to the second fastening portion,
wherein the second coupling portion couples the third fastening portion to the fourth fastening portion,
wherein the first fastening portion, the second fastening portion, the third fastening portion, and the fourth fastening portion extend in the lateral direction,
wherein the first fastening portion and the second fastening portion face each other in a longitudinal direction perpendicular to the lateral direction,
wherein the third fastening portion and the fourth fastening portion face each other in the longitudinal direction,
wherein the first coupling portion and the second coupling portion each include a plane portion extending in the longitudinal direction when the vibrating body has zero displacement,
wherein the weight includes
a first side wall extending in the lateral direction,
a second side wall extending in the longitudinal direction, and
a third side wall extending in the longitudinal direction,
wherein the second side wall and the third side wall face each other in the lateral direction;
wherein the first fastening portion is fixed to a first side of the first side wall in the lateral direction,
wherein the third fastening portion is fixed to a second side of the first side wall in the lateral direction,
wherein the plane portion of the first coupling portion faces the second side wall in the lateral direction,
wherein the plane portion of the second coupling portion faces the third side wall in the lateral direction,
wherein the second fastening portion and the fourth fastening portion are fixed to an inner wall surface of the casing extending in the lateral direction,
wherein the first coupling portion further includes a first curve, which is bent to be oriented in the lateral direction from a first end of the plane portion of the first coupling portion, and a second curve, which is bent to be oriented in the lateral direction from a second end of the plane portion of the first coupling portion,
wherein the first fastening portion extends in the lateral direction without being bent at a coupled portion between the first fastening portion and the first curve,
wherein the second fastening portion extends in the lateral direction without being bent at a coupled portion between the second fastening portion and the second curve,
wherein the second coupling portion further includes a third curve, which is bent to be oriented in the lateral direction from the first end of the plane portion of the second coupling portion, and a fourth curve, which is bent to be oriented in the lateral direction from the second end of the plane portion of the second coupling portion,
wherein the third fastening portion extends in the lateral direction without being bent from a coupled portion between the third fastening portion and the third curve, and
wherein the fourth fastening portion extends in the lateral direction without being bent from a coupled portion between the fourth fastening portion and the fourth curve.

US Pat. No. 10,483,829

BRUSH ASSEMBLY AND MOTOR USING SAME

Johnson Electric Internat...

1. A motor comprising:a housing,
a rotor assembly mounted in the housing,
a stator assembly mounted in the housing,
a commutator,
an end cap assembly mounted to one side of the housing; and
a brush assembly comprising:
a circuit board;
at least two brushes;
a plurality of power connecting terminals for connecting with an external power supply;
a power supply branch circuit connected in series between a corresponding one of the power connecting terminals and a corresponding one of the brushes; and
an EMI suppressor connected between the power supply branch circuit and ground, the EMI suppressor being an axial capacitor formed by a conductor core, a cover, and a filling medium;
wherein the end cap assembly comprises an end cap portion and a bearing seat, the end cap portion defines a first receiving chamber and a second receiving chamber at two sides thereof, and defines a through hole in communication with the first receiving chamber and the second receiving chamber, a bearing seat accommodating portion is defined in the first receiving chamber, the bearing seat comprises a plate member and a bearing sleeve disposed on the plate member, the plate member is disposed between the first receiving chamber and a bottom wall of the second receiving chamber, and the bearing sleeve is accommodated in the bearing seat accommodating portion.

US Pat. No. 10,483,827

BUILT-IN CAPACITOR MOTOR STRUCTURE

Sagitta Industrial Corp.,...

1. An improved built-in capacitor motor structure comprising:a housing including a front cover and a rear cover;
a stator portion received in the housing including a core frame, the core frame is provided with an annular insulating frame body, a plurality of circularly arranged docking units extending from the periphery of a side of the insulating frame body;
an insulating member connected on the insulating frame body having an accommodating space in communication with the outside, a capacitor being combined inside the accommodating space of the insulating member, and a plurality of corresponding docking units being provided at the bottom side edge of the insulating member; and
a rotor portion received in the stator portion,
wherein the plurality of corresponding docking units are engaged with the docking units of the insulating frame body, respectively, to connect the insulating member on the insulating frame body.

US Pat. No. 10,483,826

THERMODYNAMIC SYSTEM FOR STORING/PRODUCING ELECTRICAL ENERGY

BOREALES ENERGY, (FR)

1. A system for producing and storing electrical energy, comprising a thermally insulated chamber containing a first closed circuitry in which circulates a first working fluid, a hot source through which a first leg of the first circuitry passes for a heat exchange between the first working fluid and the hot source, a cold source through which a second leg of the first circuitry passes for a heat exchange between the first working fluid and the cold source, the hot and cold sources being thermally insulated from each other, the first circuitry further comprising third and fourth legs connecting in series the first and second legs, the third leg comprising a first member for circulating the first working fluid in liquid phase and the fourth leg comprising a second member for circulating the first working fluid in gas phase, wherein the hot source is composed of a pure water ice slurry always at 0° C., the cold source is composed of an ice slurry with a temperature lower than or equal to ?40° C. and the system for producing/storing electrical energy further comprises a second circuitry for circulating a second working fluid between the hot source and a constant temperature system outside the thermally insulated chamber, the constant temperature system being selected from the group comprising ambient air, a water reserve, a water stream, a water course, a waterway, wherein the second working fluid is circulated between said constant temperature system and the hot source by an auxiliary expansion valve and an auxiliary compressor, and is caused to exchange heat with the constant temperature system and the hot source; and,wherein the system further comprises an intermediate temperature source at an intermediate temperature between the temperature of the hot source and the temperature of the cold source, and comprises an intermediate fluid circuitry carrying an intermediate working fluid, said intermediate fluid circuitry passing through and exchanging heat with the hot source, the cold source, and the intermediate temperature source, the intermediate temperature source being connected to the intermediate fluid circuitry in parallel to the hot source, by a first sub-leg equipped with a first compressor and a second sub-leg equipped with an first expansion valve, and the intermediate temperature source being connected to the intermediate fluid circuitry in parallel to the cold source, by a third sub-leg equipped with a second compressor and a fourth sub-leg equipped with an second expansion valve.

US Pat. No. 10,483,825

ROTARY ACTUATOR

CTS Corporation, Lisle, ...

1. A rotary actuator comprising:a connector housing including a frame;
a separate motor housing secured and extending outwardly from a first side of the frame of the connector housing and defining an interior adapted to house a motor; and
a separate gear and sensor housing secured and extending outwardly from a second side of the frame of the connector housing opposed to the first side of the frame of the connector housing and defining an interior adapted to house a plurality of gears, a sensor, and an output shaft; and
clips on the respective motor housing and the gear and sensor housing for securing the motor housing and the gear and sensor housing to the frame of the connector housing.

US Pat. No. 10,483,824

SELF-RELEASING LOCK MECHANISM

Woodward, Inc., Fort Col...

1. A self-releasing lock mechanism configured to lock a driveshaft to mechanical ground, the driveshaft being in mechanical communication with a first end of a rotor of a motor, the motor being disposed in a motor housing having a flange region that is connected to mechanical ground, the self-releasing lock mechanism comprising:a ground lock housing, the ground lock housing configured to surround at least a portion of the motor housing and the ground lock housing including a locking arrangement configured to selectively engage a second end of the rotor;
at least one locking pin that extends from the ground lock housing, the at least one locking pin configured to extend into and pass through the flange region of the motor housing;
a locking plate comprising the driveshaft and at least one locking site, the at least one locking site adapted to selectively receive the at least one locking pin; and
a biasing member disposed between the ground lock housing and the flange region;
wherein the biasing member biases the ground lock housing away from the flange region;
wherein the locking arrangement engages the second end of the rotor to overcome the bias from the biasing member when the at least one locking pin is received in the at least one locking site.

US Pat. No. 10,483,823

ELECTRIC ACTUATOR

NIDEC TOSOK CORPORATION, ...

1. An electric actuator comprising:a motor that has a motor shaft extending in an axial direction;
a speed reduction mechanism disposed on an outer side in a radial direction of a portion on one side of the motor shaft in the axial direction and connected to the motor shaft;
a case that accommodates the motor and the speed reduction mechanism;
an output portion to which rotation of the motor shaft is transmitted via the speed reduction mechanism;
a first board electrically connected to the motor;
a rotation detection device that detects rotation of the output portion;
a connector portion provided in the case and connected to electrical wiring outside the case;
a first wiring member electrically connected at least indirectly to the electrical wiring via the connector portion; and
a second wiring member electrically connected to the rotation detection device,
wherein the case includes
a first case provided with the connector portion and including a first opening portion which opens on the one side in the axial direction, and
a second case including a second opening portion which opens on the other side in the axial direction,
the first board is accommodated in the first case,
the rotation detection device is accommodated in the second case,
an end portion on the one side in the axial direction of the first case and an end portion on the other side in the axial direction of the second case are fixed to each other in a state where the first opening portion and the second opening portion are opposed to each other in the axial direction,
the first wiring member includes a first connecting portion held in the first case,
the second wiring member includes a second connecting portion held in the second case,
the first connecting portion is exposed on the one side of the first case in the axial direction,
the second connecting portion is exposed on the other side of the second case in the axial direction, and
the first connecting portion and the second connecting portion are disposed at positions overlapping in the axial direction in a state where the first case and the second case are fixed to each other, and are electrically connected to each other.

US Pat. No. 10,483,822

MOTOR

NIDEC CORPORATION, Kyoto...

1. A motor comprising:a rotating shaft extending in a central axial direction;
a stator including a core back concentric with the rotating shaft; and
a bracket housing the stator; wherein
the bracket includes a cylindrical bracket main body, and a stator frame which faces the bracket main body and holds an outer surface of the stator on a radially inward side of the bracket main body, the bracket main body and the stator frame being defined by separate members;
the bracket is provided with a cooling passage through which a cooling medium is able to flow, and an inflow port and an outflow port connected with the cooling passage;
the cooling passage includes a first portion provided directly adjacent to a radially outermost surface of the bracket main body, a second portion provided radially between a radially innermost surface of the bracket main body and the stator frame, and a communication passage coupling an output of the first portion and an input of the second portion with each other;
a cooling medium in the first portion and a cooling medium in the second portion flow in opposite circumferential directions with respect to one another;
at least a portion of the communication passage is located at a position which is farther outward in a radial direction than any portion of the second portion such that the communication passage does not overlap a radially inner surface of the second portion when viewed in a direction extending along the communication passage; and
a portion of the communication passage and a portion of the core back overlap one another when viewed from a radial direction which is orthogonal to both the central axial direction and the direction extending along the communication passage.

US Pat. No. 10,483,821

STATOR FOR ROTATING ELECTRIC MACHINE FIXED TO FRAME WITH PREDETERMINED INTERFERENCE

Mitsubishi Electric Corpo...

1. A stator for a rotating electric machine, comprising:a stator core formed in a cylindrical shape; and
a frame having an inner circumferential side to which the stator core is fitted and fixed with a predetermined interference, and an outer circumferential side on which a passage for cooling fluid for cooling the stator core is formed,
wherein the interference at a thin portion of the frame formed along an inner surface of the cooling passage is greater than the interference at a thick portion thereof where there is no cooling passage,
wherein the thin portion of the frame is provided adjacent to the thick portion of the frame in an axial direction of the stator core, and
wherein an inner diameter of the thin portion of the frame is smaller than an inner diameter of the thick portion.

US Pat. No. 10,483,820

METHOD OF ENCAPSULATING INDUCTION MOTOR STATOR

Shanghai XPT Technology L...

1. An induction motor stator encapsulate method, comprising:arranging a stator of an induction motor in a case of the induction motor, wherein the stator comprises a stator core and a stator winding surrounding the stator core;
filling a first encapsulating material into the case for forming a first insulation layer, wherein the first insulation layer directly covers the stator winding; and
filling a second encapsulating material into the case for forming a second insulation layer, wherein the second insulation layer covers the first insulation layer;
wherein a shrink rate of the first encapsulating material is smaller than a shrink rate of the second encapsulating material.

US Pat. No. 10,483,819

STATOR ASSEMBLY FOR MOTOR

Hanon Systems, Daejeon (...

1. A stator assembly for a motor comprising:a stator core having a plurality of teeth around each of which a stator coil is wound;
a first insulator coupled to one side of the stator core to provide insulation between one tooth and an adjacent tooth;
a second insulator coupled to the other side of the stator core to provide insulation between one tooth and an adjacent tooth; and
a three-phase terminal inserted between the stator core and the second insulator and protruded partially to the outside of the second insulator to be electrically connected to an inverter,
wherein the three-phase terminal has a form that one ring shape is divided into a plurality of parts, and
wherein each of the plurality of parts of the three-phase terminal comprises a plurality of streamlined terminal bodies, inverter connecting portions protruded to one side of the terminal bodies and inserted into an inverter housing, and a plurality of coil engaging portions formed to be spaced from the inverter connecting portions, and disposed not to overlap each other.

US Pat. No. 10,483,817

ROTOR FOR AN ELECTRIC MOTOR INCLUDING A STRUCTURE FOR RETAINING ROTOR SEGMENTS AND PERMANENT MAGNETS ON A HUB THEREOF

Equipmake Ltd, Norwich (...

1. A rotor for an electric motor, the rotor comprising:a hub having a central axis;
a plurality of rotor segments arranged around the hub;
a plurality of permanent magnets; and
an assembly for retaining the segments on the hub,
wherein the assembly includes a plurality of rods which extend in an axial direction so as to retain respective rotor segments,
the segments are arranged around the hub to define at least two rings, which are adjacent to each other in the axial direction,
the rotor includes an intermediate plate between each ring of segments, wherein the rods pass through each intermediate plate,
wherein the magnets and the hub are shaped so as to engage with each other in such a way that the hub restrains the magnets in the circumferential direction, with each magnet received by and in direct engagement with a parallel-sided groove defined by an outer circumferential surface of the hub, and the intermediate plate between each ring of segments defines a series of inwardly directed projections in engagement with the grooves in the hub in such a way as to resist rotation of the intermediate plate between each ring of segments around the axis of the hub.

US Pat. No. 10,483,816

MOTOR, ROTOR, COMPRESSOR, AND REFRIGERATION AND AIR CONDITIONING APPARATUS

Mitsubishi Electric Corpo...

1. A motor comprising a stator and a rotor provided inside the stator, the rotor comprising:a rotor core having a magnet insertion hole, and
a plurality of permanent magnets disposed in the magnet insertion hole of the rotor core and having two permanent magnets adjacent to each other,
wherein the rotor core has a first magnet holding portion disposed between the two permanent magnets adjacent to each other in the magnet insertion hole, and a second magnet holding portion disposed at an end of the magnet insertion hole in a circumferential direction of the rotor core;
wherein the rotor core has a plurality of electromagnetic steel sheets stacked in an axial direction, and
wherein relationships A>B and A>C are satisfied, where a number of the plurality of electromagnetic steel sheets of the rotor core is represented by A, and among the plurality of electromagnetic steel sheets of the rotor core, a number of electromagnetic steel sheets having the first magnet holding portions is represented by B, and a number of electromagnetic steel sheets having the second magnet holding portions is represented by C.

US Pat. No. 10,483,815

ROTOR, ELECTRIC MOTOR, COMPRESSOR, AND REFRIGERATION AIR CONDITIONER

Mitsubishi Electric Corpo...

1. A rotor comprising:an iron core that assumes a cylindrical or columnar shape; and
a plurality of magnets embedded in the iron core and equiangularly arranged with respect to an axis of the iron core,
the iron core comprising
a first end surface portion including a first end surface of the iron core,
a second end surface portion including a second end surface of the iron core opposed to the first end surface, and
a central portion disposed between the first end surface portion and the second end surface portion,
the plurality of magnets each penetrating through the first and second end surface portions and the central portion,
the iron core having a plurality of first gaps penetrating from the first end surface portion to the second end surface portion, and a plurality of second gaps formed from the first end surface portion without reaching the central portion, and
the first gap and the second gap being alternately arranged.