US Pat. No. 10,115,700

POWER MODULE, ELECTRICAL POWER CONVERSION DEVICE, AND DRIVING DEVICE FOR VEHICLE

Hitachi, Ltd., Tokyo (JP...

1. A power module, comprising:a first switching device; and
a second switching device connected in parallel to the first switching device and having a threshold voltage higher than that of the first switching device,
the second switching device being mounted at a first location at which a temperature of the power module during operation is higher than a temperature of the power module at a second location at which the first switching device is mounted,
wherein each of the first switching device and the second switching device is an SiC-MOSFET.

US Pat. No. 10,115,699

METHOD FOR MANUFACTURING WIRE BONDING STRUCTURE, WIRE BONDING STRUCTURE, AND ELECTRONIC DEVICE

ROHM CO., LTD., Kyoto (J...

12. A wire bonding structure comprising:a first joining target having a first surface;
a second joining target; and
a wire joined to both the first joining target and the second joining target,
wherein the wire is made of Cu and has a circular cross-sectional shape with a diameter of 150 to 1000 ?m, the circular cross-sectional shape having a curvature depending on the diameter,
the wire includes a bonding part joined to the first joining target,
the bonding part has an outer circumferential surface and a joining surface joined to the first joining target,
the joining surface is withdrawn toward a central axis of the wire from the outer circumferential surface and elongated along the central axis,
in a cross-section perpendicular to the central axis of the wire, the bonding part comprises first, second and third arcs spaced apart from each other about the central axis,
the first arc is disposed opposite to the joining surface with respect to the central axis, and the second arc and the third arc are spaced apart from each other via the joining surface, and
each of the first, the second and the third arcs has a curvature that is equal to the curvature of the circular cross-sectional shape of the wire.

US Pat. No. 10,115,692

METHOD OF FORMING SOLDER BUMPS

International Business Ma...

1. A method of forming solder bumps, the method includes:preparing a substrate having a surface on which a plurality of electrode pads are formed;
forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads;
forming a conductive pillar in each of the openings of the resist layer;
forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer;
filling molten solder in each of the openings in which the conductive layers has been formed, wherein the conductive layers include metals having a same composition ratio as a composition ratio of metals of the molten solder; and
removing the resist layer.

US Pat. No. 10,115,686

SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor structure, comprising:forming a conductive layer on a first insulating layer;
etching a portion of the conductive layer to expose a portion of the first insulating layer;
deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and
removing a residue of the conductive layer from the rough surface of the first insulating layer.

US Pat. No. 10,115,685

METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor structure, comprising:providing a transceiver;
forming a molding to surround the transceiver;
forming a plurality of recesses extending through the molding;
disposing a conductive material into the plurality of recesses to form a plurality of vias;
disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver; and
forming a redistribution layer (RDL) over the insulating layer;wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.

US Pat. No. 10,115,684

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a first semiconductor chip comprising:
a first plurality of wiring layers;
a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers; and
a first resin film formed over the uppermost layer of the first plurality of the wiring layers, a thickness of the first resin film being uniform between the first coil and the first dummy wires, and over top surfaces of the first coil and the first dummy wires; and
a second semiconductor chip comprising:
a second plurality of wiring layers;
a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers; and
a second resin film formed over the uppermost layer of the second plurality of the wiring layers, a thickness of the second resin film being uniform between the second coil and the second dummy wires, and over top surfaces of the second coil and the second dummy wires,
wherein the first semiconductor chip and the second semiconductor chip face each other via an insulation sheet,
wherein the first dummy wires are isolated from each other,
wherein the second dummy wires are isolated from each other, and
wherein the first coil and the second coil are magnetically coupled with each other.

US Pat. No. 10,115,683

ELECTROSTATIC DISCHARGE PROTECTION FOR ANTENNA USING VIAS

NXP USA, Inc., Austin, T...

1. An antenna comprising:a metal patch comprising a metal region on one side of a first centerline of the metal patch;
a ground plane; and
a plurality of vias, each of the plurality of vias connected to the ground plane and wherein the plurality of vias is disposed only in the metal region and symmetrically about a second centerline of the metal patch.

US Pat. No. 10,115,681

COMPACT THREE-DIMENSIONAL MEMORY DEVICE HAVING A SEAL RING AND METHODS OF MANUFACTURING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A semiconductor die, comprising:a pair of first alternating stacks of first portions of insulating layers and electrically conductive layers located over a semiconductor substrate;
groups of memory stack structures vertically extending through a respective one of the pair of the first alternating stacks, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel laterally surrounded by the memory film;
a pair of second alternating stacks of second portions of the insulating layers and dielectric material layers laterally adjoined to a respective one of the first alternating stacks, wherein each second portion of the insulating layers is connected to a respective one of the first portions of the insulating layers; and
at least one seal ring structure laterally enclosing, and laterally spaced from, the pair of first alternating stacks, and contacting at least a first sidewall of each of the pair of second alternating stacks.

US Pat. No. 10,115,680

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a substrate;
a first stacked body provided in a first region on the substrate, and including a first insulating film and an electrode film stacked alternately on one another;
a columnar part provided in the first stacked body, extending in a stacking direction of the first stacked body, and including a connection part widened in width in a first direction along an upper surface of the substrate;
a second insulating film provided in a second region on the substrate, and having a first thickness in the stacking direction; and
a second stacked body provided on the second insulating film, and including a first film and a third insulating film stacked alternately on one another,
an uppermost first film in the second stacked body being located at a first distance in the stacking direction from the upper surface of the substrate, and
the first thickness is not less than 30 percent of the first distance.

US Pat. No. 10,115,679

TRENCH STRUCTURE AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A trench structure comprising:a top metal layer;
a silicon carbide (SiC) layer on the top metal layer;
a first passivation layer overlying the SiC layer; and
a second passivation layer overlying the first passivation layer,
wherein
a first sidewall of the trench structure, a second sidewall of the trench structure, and the top metal layer form a trench, and
at least one of the first sidewall or the second sidewall comprises:
a sidewall of the SiC layer; and
a sidewall of the second passivation layer,
wherein a portion of the second passivation layer is between the first passivation layer and the at least one of the first sidewall or the second sidewall.

US Pat. No. 10,115,678

WIRE BOND WIRES FOR INTERFERENCE SHIELDING

Invensas Corporation, Sa...

1. An apparatus, comprising:a substrate having an upper surface and a lower surface opposite the upper surface and having bond pads on the upper surface;
a first and a second microelectronic device coupled to the upper surface of the substrate;
an EMI shield covering the first microelectronic device, the EMI shield comprising at least one side portion and a top portion, the at least one side portion including wire bond wires having first ends bonded to the bond pads, the wire bond wires arranged in a preselected manner for one or more frequencies associated with an interference, the wire bond wires positioned on at least one side of the first microelectronic device to shield the interference relative to the first microelectronic device; and
the second microelectronic device located in a region not covered by the EMI shield.

US Pat. No. 10,115,677

VERTICAL INTERCONNECTS FOR SELF SHIELDED SYSTEM IN PACKAGE (SIP) MODULES

Apple Inc., Cupertino, C...

9. A semiconductor device package, comprising:a substrate;
one or more terminals coupled to a lower surface of the substrate;
a first device coupled to an upper surface of the substrate;
a second device coupled to the upper surface of the substrate;
a ground ring coupled to the lower surface of the substrate, the ground ring being electrically coupled to at least one of the terminals coupled to the lower surface of the substrate;
a plurality of conductive structures individually attached to the upper surface of the substrate, wherein at least one of the conductive structures is electrically coupled to the ground ring, wherein the plurality of conductive structures at least partially surround the first device on the upper surface of the substrate, and wherein at least one conductive structure is located between the first device and the second device on the upper surface of the substrate; and
a shield positioned above the first device, the second device, and the conductive structures, the shield being electrically coupled to at least one of the conductive structures electrically coupled to the ground ring.

US Pat. No. 10,115,676

INTEGRATED CIRCUIT AND METHOD OF MAKING AN INTEGRATED CIRCUIT

NXP B.V., Eindhoven (NL)...

1. An integrated circuit comprising:a semiconductor substrate; and
a metallization stack located on a major surface of the semiconductor substrate, the metallization stack comprising a plurality of metal layers including patterned metal features, wherein each metal layer of the metallization stack is separated by an intervening dielectric layer,
wherein the metallization stack forms a first grid including patterned metal features for supplying power and providing signal connections to components of the integrated circuit located in the semiconductor substrate, and
wherein the metallization stack also forms a second grid for securing the integrated circuit against electromagnetic attacks, wherein the second grid includes patterned metal features interspersed with the patterned metal features of the first grid in at least some of the metal layers of the metallization stack, and wherein the patterned metal features of the second grid are electrically connected to the first grid.

US Pat. No. 10,115,675

PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A PACKAGED SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A packaged semiconductor device, comprising:a first package structure having a first cut edge, wherein the first package structure comprises a die, a molding compound and at least one outer via, the die and the outer via are encapsulated by the molding compound, and the outer via penetrates the molding compound;
at least one outer conductive bump disposed on the first package structure and having a second cut edge;
a second package structure jointed onto the first package structure;
a sealing material disposed on the first package structure, surrounding the second package structure, and covering the outer conductive bump, wherein the sealing material has a third cut edge and the sealing material is in physical contact with the outer conductive bump; and
an electromagnetic interference (EMI) shielding layer disposed over the first cut edge, the second cut edge, and the third cut edge, and being in electrical contact with the outer conductive bump, wherein the EMI shielding layer is electrically connected with the outer via through the outer conductive bump.

US Pat. No. 10,115,674

SEMICONDUCTOR DEVICE INCLUDING ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING LAYER AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method for manufacturing a semiconductor device, comprising:providing a substrate having a first surface, a second surface opposite to the first surface, and a side surface between the first surface and the second surface;
providing a semiconductor chip on the first surface;
forming a resin portion that seals the semiconductor chip;
forming a conductive film on an upper surface of the resin portion and a side surface of the resin portion, the conductive film being electrically connectable to a ground potential source; and
forming a film stack including a first film that is a metal oxide film formed by depositing metal in an oxygen containing environment or a metal nitride film formed by depositing metal in a nitrogen containing environment, wherein
a lightness value of the film stack is less than a lightness value of the resin portion.

US Pat. No. 10,115,673

EMBEDDED SUBSTRATE PACKAGE STRUCTURE

1. An embedded substrate package structure, comprising: a first substrate being disposed with a plurality of first through holes, and having an upper surface and a lower surface disposed respectively with a first upper wire layer and a first lower wire layer, the first upper wire layer and the first lower wire layer being electrically connected by the plurality of first through holes;a first dielectric layer covering the first lower wire layer on the lower surface of the first substrate, and having a plurality of openings located at a position of the first lower wire layer to expose a portion of a surface of the first lower wire layer, and the exposed surface being disposed with a conductive bump;
a second dielectric layer covering the first upper wire layer on the upper surface of the first substrate, and having a plurality of openings located at a position of the first upper wire layer to expose a portion of a surface of the first upper wire layer, and the exposed surface being disposed with a conductive bump, and the conductive bump comprising a solder bump and an under-bump metallurgy;
a second substrate being disposed with at least a cavity and a plurality of second through holes, the at least a cavity being for accommodating a chip, and the second substrate having an upper surface and a lower surface disposed respectively with a second upper wire layer and a second lower wire layer;
a third dielectric layer covering the second lower wire layer on the lower surface of the second substrate, and having a plurality of openings located at a position of the second lower wire layer to expose a portion of a surface of the second lower wire layer, and the exposed surface being disposed with a conductive bump, and the conductive bump comprising a solder bump and an under-bump metallurgy;
a fourth dielectric layer covering the second upper wire layer and the chip, serving as a protective layer of the back of the chip, and having a plurality of openings located at a position of the second upper wire layer to expose a portion of a surface of the second upper wire layer, and the exposed surface being disposed with a conductive bump, and the conductive bump comprising a solder bump and an under-bump metallurgy; and
a fifth dielectric layer covering surroundings of the chip to fill gaps between the chip and the cavity and fixing the chip to inside of the cavity, wherein the second dielectric layer and the third dielectric layer respectively have a plurality of openings at positions of the cavity, inside of the plurality of openings being disposed with an under bump metallurgy or a solder bump, and a conductive bump or a solder bump is formed on a pad of the chip, the chip being disposed in the cavity and electrically connected to the first upper wire layer of the first substrate through the conductive bump or the solder bump.

US Pat. No. 10,115,670

FORMATION OF ADVANCED INTERCONNECTS INCLUDING SET OF METAL CONDUCTOR STRUCTURES IN PATTERNED DIELECTRIC LAYER

International Business Ma...

1. A method for fabricating an advanced metal conductor structure comprising:providing a pattern in a dielectric layer, wherein the pattern includes a set of features in the dielectric layer for a set of metal conductor structures, the set of features having a first dimension;
creating an adhesion promoting layer disposed over the patterned dielectric layer;
depositing a ruthenium layer disposed on the adhesion promoting layer;
depositing a cobalt layer over the ruthenium layer;
performing a high temperature thermal anneal which creates a ruthenium cobalt alloy layer to cover surfaces of the set of features; wherein a portion of the cobalt layer is unreacted with the ruthenium layer after the high temperature thermal anneal producing unreacted cobalt;
etching the unreacted cobalt from the ruthenium cobalt alloy layer; and
depositing a metal layer disposed on the ruthenium cobalt alloy layer to form the set of metal conductor structures.

US Pat. No. 10,115,669

HIGH DENSITY NONVOLATILE MEMORY CELL UNIT ARRAY

Sony Semiconductor Soluti...

1. A memory cell unit array, comprisingmemory cell units arranged in a two-dimensional matrix form in a first direction and a second direction, the memory cell units being each constituted of
a plurality of first wires extending in the first direction,
a plurality of second wires that are disposed separately from the first wires in upper and lower directions and extend in the second direction unlike the first wires, and
a nonvolatile memory cell that is disposed in a region in which the first wires and the second wires overlap one another and connected to the first wires and the second wires, wherein
each of the memory cell units includes, below the memory cell unit, a control circuit that controls an operation of the memory cell unit,
the control circuit is constituted of
a first control circuit that controls an operation of the nonvolatile memory cell that constitutes the memory cell unit via the first wires, and
a second control circuit that controls an operation of the nonvolatile memory cell that constitutes the memory cell unit via the second wires,
the second wires that constitute the memory cell unit are connected to the second control circuit that constitutes the memory cell unit,
some of the first wires that constitute the memory cell unit are connected to the first control circuit that constitutes the memory cell unit, and
others of the first wires that constitute the memory cell unit are connected to a first control circuit that constitutes an adjacent memory cell unit adjacent thereto in the first direction.

US Pat. No. 10,115,668

SEMICONDUCTOR PACKAGE HAVING A VARIABLE REDISTRIBUTION LAYER THICKNESS

Intel IP Corporation, Sa...

1. A semiconductor package, comprising:an integrated circuit die encapsulated in a mold compound, the integrated circuit die having an exposed surface co-planar with a surface of the mold compound;
a dielectric layer having a front surface and a back surface opposite from the front surface, wherein one or more openings extend from the front surface to the back surface, wherein the front surface of the dielectric layer is on the co-planar exposed surface of the integrated circuit die and on the surface of the mold compound; and
a redistribution layer on the back surface, wherein the redistribution layer includes a plurality of first conductive traces, the plurality of first conductive traces immediately adjacent to each other and having a first thickness and a first pitch, and wherein the redistribution layer includes a plurality of second conductive traces, the plurality of second conductive traces immediately adjacent to each other and having a second thickness and a second pitch, and wherein the first thickness is different than the second thickness and both thicknesses are measured in a same direction normal to the exposed surface of the integrated circuit die, and wherein the first pitch is different than the second pitch.

US Pat. No. 10,115,667

SEMICONDUCTOR DEVICE WITH AN INTERCONNECTION STRUCTURE HAVING INTERCONNECTIONS WITH AN INTERCONNECTION DENSITY THAT DECREASES MOVING AWAY FROM A CELL SEMICONDUCTOR PATTERN

AMSUNG ELECTRONICS CO., L...

1. A semiconductor device, comprising:a cell semiconductor pattern disposed on a semiconductor substrate;
a first circuit disposed between the semiconductor substrate and the cell semiconductor pattern;
a cell array region disposed on the cell semiconductor pattern, the cell semiconductor pattern extending beyond the cell array region;
a first interconnection structure disposed between the semiconductor substrate and the cell semiconductor pattern and electrically connected to the first circuit, wherein the first interconnection structure includes a plurality of first interconnections, and the first interconnections have an interconnection density that decreases moving away from the cell semiconductor pattern;
a first dummy structure disposed between the semiconductor substrate and the cell semiconductor pattern, wherein the first dummy structure includes first dummy patterns co-planar with the first interconnections; and
second dummy patterns disposed on the semiconductor substrate, wherein the second dummy patterns are co-planar with the first interconnections,
wherein the second dummy patterns have a lower pattern density at an area closer to the cell semiconductor pattern than at an area farther away from the cell semiconductor pattern.

US Pat. No. 10,115,665

SEMICONDUCTOR RESISTOR STRUCTURES EMBEDDED IN A MIDDLE-OF-THE-LINE (MOL) DIELECTRIC

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:providing a substrate having a first doped semiconductor material structure present in a first device region, and a second doped semiconductor material structure present in a second device region, wherein a middle-of-the-line (MOL) dielectric material is located on the substrate and surrounds the first and second doped semiconductor material structures, and wherein the MOL dielectric material contains a lower contact structure containing a metal liner and a contact metal present in both the first and second device regions;
forming a hard mask in the first device region and atop the MOL dielectric material and the lower contact structure, while leaving the second device region physically exposed;
removing at least a portion of the contact metal of the lower contact structure present in the second device region to physically expose at least a portion of the metal liner; and
forming a next level dielectric material located above the lower contact structure present in the first device region and between and above the metal liner present in the second device region, wherein the next level dielectric material contains an upper contact structure in both of the first and second device regions.

US Pat. No. 10,115,663

3D SEMICONDUCTOR DEVICE AND STRUCTURE

Monolithic 3D Inc., San ...

1. A 3D semiconductor device, the device comprising:a first single crystal layer comprising a plurality of first transistors and a first metal layer,
wherein said first metal layer comprises interconnecting said first transistors forming a plurality of logic gates;
a plurality of second transistors overlaying said first single crystal layer;
a plurality of third transistors overlaying said second transistors;
a second metal layer overlaying said third transistors;
Input/Output pads to provide connection to external devices;
a global power grid to distribute power to said device, said global power grid overlaying said first metal layer; and
a local power grid to distribute power to said plurality of logic gates,
wherein said third transistors are aligned to said first transistors with less than 40 nm misalignment,
wherein said first single crystal layer comprises an Electrostatic Discharge (“ESD”) structure connected to at least one of said Input/Output pads,
wherein said global power grid is connected to said local power grid by a plurality of vias,
wherein at least one of said plurality of vias has a radius of less than 200 nm,
wherein at least one of said third transistors is a junction-less transistor, and
wherein a memory cell comprises at least one of said third transistors.

US Pat. No. 10,115,662

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A CURVED IMAGE SENSOR

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a semiconductor die including a base semiconductor material comprising a first surface and a second surface opposite the first surface, wherein the second surface includes an image sensor area;
removing a portion of the first surface of the base semiconductor material to form a first curved surface;
disposing the semiconductor die on a substrate with the first curved surface oriented toward the substrate; and
asserting movement of the base semiconductor material by external force to change orientation of the second surface with the image sensor area into a second curved surface.

US Pat. No. 10,115,661

SUBSTRATE-LESS DISCRETE COUPLED INDUCTOR STRUCTURE

QUALCOMM Incorporated, S...

1. An inductor structure, comprising:a first inductor winding that includes an electrically conductive material;
a second inductor winding that includes an electrically conductive material; and
an epoxy filler laterally located between the first inductor winding and the second inductor winding, the epoxy filler configured to provide structural coupling of the first and second inductor windings, wherein the first inductor winding, the second inductor winding and the epoxy filler are substrate-less, and not in direct contact with any substrate base portion,
wherein the inductor structure comprises a thickness of 200 microns or less.

US Pat. No. 10,115,660

LEADFRAME STRIP WITH VERTICALLY OFFSET DIE ATTACH PADS BETWEEN ADJACENT VERTICAL LEADFRAME COLUMNS

TEXAS INSTRUMENTS INCORPO...

1. A leadframe strip comprising:a first leadframe column and a second leadframe column, each of the first leadframe column and the second leadframe column including a plurality of leadframes, each of the plurality of leadframes including a die attach pad of a plurality of die attach pads, the plurality of die attach pads including a first die attach pad of the first leadframe column and a second die attach pad of the second leadframe column; and
a plurality of leads associated with each of the plurality of die attach pads, the plurality of leads associated with the first die attach pad and the second die attach pad connected to a first dam bar associated with the first die attach pad and a second dam bar associated with the second die attach pad, the first and second dam bars connected together using a portion of the leadframe strip, the portion aligned in a first direction;
wherein the first die attach pad and the second die attach pad are offset from each other in a second direction, the second direction being at an angle with respect to the first direction.

US Pat. No. 10,115,659

MULTI-TERMINAL DEVICE PACKAGING USING METAL SHEET

Sensor Electronics Techno...

1. A device package array comprising:a wafer including a plurality of devices;
a first metal sheet located adjacent to the wafer, wherein the first metal sheet is patterned to include a plurality of openings extending through the first metal sheet; and
a second metal sheet located adjacent to the first metal sheet, wherein the second metal sheet is patterned to include a plurality of openings extending through the second metal sheet, wherein the first metal sheet and the second metal sheet are positioned such that the plurality of openings in the first metal sheet alternate with the plurality of openings in the second metal sheet, such that a first electrode in each device of the plurality of devices is bonded to the first metal sheet and a second electrode in each device of the plurality of devices is bonded to the second metal sheet.

US Pat. No. 10,115,658

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor chip having a first upper surface on which a plurality of electrodes are formed and a first back surface opposite the first upper surface;
a tab having a second upper surface to which the semiconductor chip is fixed;
a plurality of leads arranged along a first side of the tab in a plan view;
a plurality of first wires connecting a plurality of first electrodes of the plurality of electrodes with the plurality of leads, respectively;
a plurality of second wires connecting a plurality of second electrodes of the plurality of electrodes with the tab, respectively; and
a seal member sealing the semiconductor chip, the tab, a part of each of the plurality of leads, the plurality of first wires and the plurality of second wires,
wherein, in the plan view, the semiconductor chip has a second side along which the plurality of electrodes are arranged and extended in a first direction,
wherein, in the plan view, the first side of the tab is extended along the second side of the semiconductor chip,
wherein, in the plan view, the first side of the tab is located between the second side of the semiconductor chip and the plurality of leads,
wherein, in the plan view, the tab has a slit that pierces the tab formed between the second side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the slit has a first portion extended in the first direction, and a second portion extended from the first portion toward the first side of the tab and also extended in a second direction crossing the first direction,
wherein, in the plan view, a wire connecting portion of each of the plurality of second wires, which is connected to the tab, is located between the slit and the first side of the tab,
wherein, in the plan view, each of the plurality of second wires intersects with the slit, and
wherein a length of the first portion of the slit in the first direction is longer than a length of the second portion of the slit in the second direction.

US Pat. No. 10,115,656

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a substrate;
a semiconductor chip coupled onto the substrate via a bump electrode; and
an underfill material disposed between the substrate and the semiconductor chip,
wherein the underfill material contains a resin, potassium ions, and graphene particles.

US Pat. No. 10,115,655

HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING HEAT DISSIPATION SUBSTRATE

SUPERUFO291 TEC, Kyoto (...

12. A heat dissipation substrate, comprising:an alloy composite body mainly composed of a principal metal, an additional metal which is different from the principal metal and is at least one substance selected from a group consisting of Ti, Cr, Co, Mn, Ni, Fe, B, Y, Mg and Zn, and diamond, the diamond being provided as a powder of diamond; and
a metallic layer composed of Cu, the metallic layer being formed on a surface of the alloy composite body,
wherein a coefficient of linear expansion of the heat dissipation substrate is in a range of 6.5 ppm/K or higher and 15 ppm/K or lower,
a degree of thermal conductivity of the heat dissipation substrate is 420 W/m·K or higher,
a percentage of defects on the surface of the metallic layer is 5% or lower, and
a carbide of the additional metal is formed on a surface of the powder of diamond.

US Pat. No. 10,115,654

BURIED THERMALLY CONDUCTIVE LAYERS FOR HEAT EXTRACTION AND SHIELDING

PALO ALTO RESEARCH CENTER...

1. A device comprising:a plurality of blocks grown sequentially on each other, the plurality of the blocks being interconnected by vertical vias filled with thermally conducting material, wherein each of the blocks comprises:
an insulating layer,
a semiconductor layer being deposited on the insulating layer below,
a thermally insulating layer being deposited on the semiconductor layer below, and
a buried thermally conductive layer being deposited on the thermally insulating layer below; and
a thermally conductive layer bonded to bottom or top of the plurality of blocks as a ground plane or a heat extraction layer, the thermally conductive layer having a high thermal conductivity,
wherein
the vertical vias contact the thermally conductive layer and pass through the insulating layer, the thermally insulating layer, and the buried thermally conductive layer in the plurality of blocks,
the vertical vias do not contact the semiconductor layers of the plurality of blocks, and
inter-plane vias connect the semiconductor layers of the plurality of blocks.

US Pat. No. 10,115,653

THERMAL DISSIPATION THROUGH SEAL RINGS IN 3DIC STRUCTURE

Taiwan Semiconductor Manu...

1. A package comprising:a first die comprising a first seal ring comprising a plurality of sides adjacent to edges of the first die;
a heat spreader encircling the first die;
a thermal conductive path connecting the heat spreader to the first seal ring, wherein an entirety of the thermal conductive path is formed of metal-containing features; and
an interposer underlying and bonded to the first die through a first solder region, wherein the interposer comprises:
a substrate;
a metal line over the substrate, wherein the metal line forms a portion of the thermal conductive path, and the metal line is in contact with the first solder region;
a plurality of through-vias penetrating through the substrate of the interposer; and
a second seal ring over the substrate of the interposer, wherein the second seal ring is electrically coupled to the heat spreader.

US Pat. No. 10,115,652

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS

Renesas Electronics Corpo...

1. A semiconductor device comprising:a power device; and
a temperature detection diode,
wherein the semiconductor device has a device structure configured to insulate between a power line of the power device and the temperature detection diode, and
wherein the device structure comprises a resistor between a first conductive type electrode included in the power line of the power device and a cathode electrode of the temperature detection diode.

US Pat. No. 10,115,651

ELECTRONIC COMPONENT HAVING A CHIP MOUNTED ON A SUBSTRATE WITH A SEALING RESIN AND MANUFACTURING METHOD THEREOF

ROHM CO., LTD., Kyoto (J...

1. An electronic component, comprising:a substrate that has a first principal surface and a second principal surface;
a chip that includes a mounting surface on which a plurality of terminal electrodes are formed, and a non-mounting surface opposite to the mounting surface, the mounting surface facing the first principal surface of the substrate; and
a sealing resin that is disposed on the first principal surface of the substrate, and seals the chip so as to expose the non-mounting surface of the chip, the sealing resin having an outer surface that is flush with the non-mounting surface of the chip.

US Pat. No. 10,115,650

DIE-ON-INTERPOSER ASSEMBLY WITH DAM STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:bonding a die to a chip area on a frontside of a wafer to form a die-on-wafer assembly, the wafer having the frontside and a backside, the chip area being surrounded by scribe line regions, the chip area comprising four corner areas;
forming a dam structure in each of the four corner areas on the backside of the wafer; and
performing a dicing process on the scribe line regions, wherein after performing the dicing process, each of the four corner areas of the chip area includes at least a portion of one of the dam structures, each of the remaining portions of the dam structures being at least a part of a circle in a plane parallel to the backside of the wafer.

US Pat. No. 10,115,649

EXTERNAL CONNECTION MECHANISM, SEMICONDUCTOR DEVICE, AND STACKED PACKAGE

TOHOKU-MICROTEC CO., LTD....

1. A semiconductor device comprising:a connecting base including:
a semiconductor substrate,
a surface insulating-film having a flat upper face and provided on the semiconductor substrate,
an interconnection buried in the surface insulating-film, and
a surface electrode arranged on the upper face of the surface insulating-film and connected to the interconnection;
a passivation film covering the upper face of the surface insulating-film and the surface electrode, establishing a groove that exposes a central part of the surface electrode at a bottom;
a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film so as to cover an area corresponding to the surface electrode in a plane pattern; and
a plurality of micro-bumps arranged on the barrier-metal film located on the passivation film.

US Pat. No. 10,115,648

FAN-OUT SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A semiconductor package comprising:a semiconductor chip;
a first interconnection member stacking on the semiconductor chip, electrically connected to the semiconductor chip, and having a connection terminal pad; and
a passivation layer disposed at one side of the first interconnection member and having an opening part opening a portion of the connection terminal pad,
wherein distances from a center of the connection terminal pad to at least two points of an edge thereof are different from each other, and
the center of the connection terminal pad and the at least two points of the edge are positioned in a plane vertical to a stacking direction of the first interconnection member and the semiconductor chip.

US Pat. No. 10,115,647

NON-VERTICAL THROUGH-VIA IN PACKAGE

1. A package comprising:a device die;
a through-via, wherein the through-via has a sand timer profile, wherein a longitudinal cross-section profile of the through-via is curved continuously;
a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die;
a first dielectric layer overlapping the molding material and the device die;
a second dielectric layer overlapped by the molding material and the device die;
a via in the second dielectric layer, wherein the via and the through-via in combination comprise:
a metal seed layer comprising a first metal, wherein the metal seed layer comprises a first portion as a bottom portion of the via, a second portion as a bottom portion of the through-via, and a third portion lining a sidewall of the via; and
a metallic material comprising a second metal different from the first metal; and
a plurality of redistribution lines (RDLs) extending into the first dielectric layer to electrically couple to the device die and the through-via.

US Pat. No. 10,115,646

SEMICONDUCTOR ARRANGEMENT, SEMICONDUCTOR SYSTEM AND METHOD OF FORMING A SEMICONDUCTOR ARRANGEMENT

INFINEON TECHNOLOGIES AG,...

1. A semiconductor arrangement, comprising:an electrically conductive plate having a top surface;
a plurality of power semiconductor devices arranged on the top surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices is electrically coupled to the electrically conductive plate;
a plurality of electrically conductive blocks, each electrically conductive block being electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and
encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the top surface of the electrically conductive plate is free from the encapsulation material.

US Pat. No. 10,115,645

REPACKAGED RECONDITIONED DIE METHOD AND ASSEMBLY

Global Circuit Innovation...

1. A method comprising:removing one or more existing ball bonds from an extracted die, the extracted die comprising a fully functional semiconductor die removed from a previous package;
reconditioning die pads of the extracted die to create a reconditioned die, reconditioning comprising applying a plurality of metallic layers to the die pads;
securing the reconditioned die within a cavity of a new package base;
providing a plurality of bond connections interconnecting the reconditioned die pads and package leads or downbonds of the new package base;
applying an encapsulating compound over the reconditioned die and the plurality of bond connections to create an assembled package base, the encapsulating compound configured to exhibit low thermal expansion; and
securing a lid to the new package base.

US Pat. No. 10,115,644

INTERPOSER MANUFACTURING METHOD

Disco Corporation, Tokyo...

1. An interposer manufacturing method for manufacturing a plurality of interposers from a material substrate including a glass substrate having a first surface and a second surface opposite to said first surface and a multilayer member provided on said first surface or said second surface of said glass substrate, said glass substrate being partitioned by a plurality of crossing division lines to define a plurality of separate regions, said multilayer member including an insulating layer and a wiring layer, said interposer manufacturing method comprising:a cut groove forming step of cutting an exposed surface of said multilayer member along each division line by using a first cutting blade to thereby form a cut groove on said exposed surface of said multilayer member, said cut groove having a depth not reaching said glass substrate; and
a dividing step of cutting said glass substrate along each cut groove by using a second cutting blade having a thickness smaller than the width of each cut groove to thereby divide said glass substrate and manufacture said plurality of interposers.

US Pat. No. 10,115,643

CIRCUIT AND METHOD FOR MONOLITHIC STACKED INTEGRATED CIRCUIT TESTING

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:receiving an integrated circuit (IC) having a first layer, wherein the first layer has a first surface and a second surface;
attaching probe pads to the first surface;
applying a first fault testing to the IC through the probe pads, wherein the first fault testing is designed to detect faults in at least the first layer, wherein the first fault testing includes supplying first test patterns to the IC, receiving first outputs from the IC, and determining whether the first outputs are acceptable;
after determining that the first outputs are acceptable, forming a second layer of the IC over the second surface and connected to the first layer; and
after the forming of the second layer, applying a second fault testing to the IC through the probe pads that are attached to the first surface, the IC having the first and second layers, wherein the second fault testing is designed to detect faults in at least the second layer, wherein the second fault testing includes supplying second test patterns to the IC, receiving second outputs from the IC, and determining whether the second outputs are acceptable.

US Pat. No. 10,115,642

SEMICONDUCTOR DEVICES COMPRISING NITROGEN-DOPED GATE DIELECTRIC, AND METHODS OF FORMING SEMICONDUCTOR DEVICES

Micron Technology, Inc., ...

1. A method of forming a semiconductor device comprising:forming a gate dielectric layer extending across a location of a channel region of a PMOS transistor and across a location of a channel region of an NMOS transistor;
doping a first region of the gate dielectric layer with nitrogen to a first concentration;
after doping the first region of the gate dielectric layer with the nitrogen to the first concentration, doping a second region of the gate dielectric layer with nitrogen to a second concentration different from the first concentration; one of the nitrogen-doped first and second regions of the gate dielectric layer including a nitrogen-doped NMOS gate dielectric material over and in direct physical contact with the channel region location of the NMOS transistor, and the other of the nitrogen-doped first and second regions of the gate dielectric layer including a nitrogen-doped PMOS gate dielectric material over and in direct physical contact with the channel region location of the PMOS transistor; and
the nitrogen-doped NMOS gate dielectric material being doped to a higher concentration of nitrogen than the nitrogen-doped PMOS gate dielectric material.

US Pat. No. 10,115,639

FINFET DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:depositing an amorphous material in an opening disposed between a first semiconductor structure and a second semiconductor structure, the amorphous material comprising at least one first void;
recrystallizing the amorphous material to form a first conductive material comprising the at least one void;
removing a portion of the first conductive material to form a trench, the trench exposing the at least one first void and being defined by a remaining portion of the first conductive material; and
depositing a second conductive material in the trench, the second conductive material and the remaining portion of the first conductive material forming a dummy gate layer, wherein depositing the second conductive material in the trench is sufficient to cause the dummy gate layer to be free from voids.

US Pat. No. 10,115,638

PARTIALLY RECESSED CHANNEL CORE TRANSISTORS IN REPLACEMENT GATE FLOW

TEXAS INSTRUMENTS INCORPO...

1. A method of forming an integrated circuit, comprising the steps of:providing a substrate comprising semiconductor material;
concurrently removing a first sacrificial gate in a first MOS transistor and removing a second sacrificial gate in a second MOS transistor;
concurrently removing a first sacrificial gate dielectric layer in said first MOS transistor and removing a second sacrificial gate dielectric layer in said second MOS transistor;
forming an etch mask over said substrate in said second MOS transistor so as to expose said substrate in said first MOS transistor;
concurrently removing semiconductor material from said substrate in an area for a recessed replacement gate in said first MOS transistor and from a field oxide adjacent to the area to form a recess, such that an etched surface of said substrate is substantially coplanar with an etched surface of field oxide adjacent to said etched surface of said substrate at a bottom of said recess, and such that semiconductor material is not removed from said substrate in said second MOS transistor;
concurrently forming a first replacement gate dielectric layer in said first MOS transistor and forming a second replacement gate dielectric layer in said second MOS transistor; and
concurrently forming a recessed first replacement gate on said first replacement gate dielectric layer and forming a second replacement gate on said second replacement gate dielectric layer;
so that said recessed first replacement gate is recessed below a top surface of said substrate and said first MOS transistor and said second MOS transistor have a same polarity.

US Pat. No. 10,115,636

PROCESSING METHOD FOR WORKPIECE

Disco Corporation, Tokyo...

1. A method of processing a workpiece in which a plurality of low-dielectric-constant insulation films and a metallic pattern are stacked on a surface of a semiconductor substrate and in which devices are formed in a plurality of regions formed in a grid pattern, the method comprising:a masking step of covering surfaces of the devices formed on the workpiece with a surface protective member, leaving spaces between adjacent regions exposed;
a wet blasting step of dispersing abrasive grains in an etching liquid capable of dissolving the metallic pattern, and blasting the dispersion against the workpiece together with compressed gas so as to remove the low-dielectric-constant insulation films and the metallic pattern in the regions, thereby exposing the semiconductor substrate to form streets in the regions; and
a dividing step of subjecting the workpiece with the semiconductor substrate exposed by the wet blasting step to dry etching so as to divide the workpiece along the streets,
wherein dissolving of the metallic pattern on the streets and removal of the low dielectric constant insulation films are simultaneous in the wet blasting step.

US Pat. No. 10,115,634

SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS AND METHOD OF MANUFACTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor component comprising:a semiconductor substrate having an opening;
a first dielectric liner having a first stress over an interior surface of the opening;
a second dielectric liner having a second stress over the first dielectric liner, wherein a direction of the first stress is opposite a direction of the second stress; and
a conductive material over the second dielectric liner.

US Pat. No. 10,115,632

THREE-DIMENSIONAL MEMORY DEVICE HAVING CONDUCTIVE SUPPORT STRUCTURES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:a lower-interconnect-level dielectric material layer located over a substrate and embedding lower-interconnect-level metal interconnect structures;
a horizontal layer overlying the lower-interconnect-level dielectric material layer;
an alternating stack of insulating layers and electrically conductive layers located over the horizontal layer;
an array of memory stack structures extending through the alternating stack;
laterally-insulated conductive via structures that vertically extend through each layer in the alternating stack and through the horizontal layer, wherein each of the laterally-insulated conductive via structures comprises a respective first conductive core that is electrically shorted to a respective one of the lower-interconnect-level metal interconnect structures, and a respective first cylindrical dielectric spacer that laterally surrounds the respective first conductive core;
laterally-insulated support structures that vertically extend through a subset of layers in the alternating stack, wherein each of the laterally-insulated support structures comprises a respective second conductive core having a same composition as the first conductive core, and a respective second cylindrical dielectric spacer that laterally surrounds the respective second conductive core, and wherein an entirety of a top planar surface of each second conductive core contacts a respective bottom surface of an overlying upper-interconnect-level dielectric material layer;
wherein:
the alternating stack includes a staircase region in which each electrically conductive layer except a topmost electrically conductive layer laterally extends farther than any overlying electrically conductive layer to provide multiple sets of stepped surfaces, wherein each set of stepped surfaces continuously extend from a bottommost layer of the alternating stack to a topmost layer of the alternating stack;
a retro-stepped dielectric material portion overlies the multiple sets of stepped surfaces; and
the laterally-insulated support structures vertically extend through a respective portion of the multiple sets of stepped surfaces and the retro-stepped dielectric material portion.

US Pat. No. 10,115,631

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a circuit comprising a first transistor;
a first pixel and a second pixel; and
a first wire, a second wire, and a third wire, wherein the first wire, the second wire and the third wire are electrically connected to the circuit,
wherein the second wire is electrically connected to the first pixel,
wherein the third wire is electrically connected to the second pixel,
wherein the circuit is configured to distribute a signal from the first wire to the second wire and the third wire,
wherein the first transistor comprises a first oxide semiconductor film and a second oxide semiconductor film on the first oxide semiconductor film, and
wherein an atomic ratio of indium in the first oxide semiconductor film is different from an atomic ratio of indium in the second oxide semiconductor film.

US Pat. No. 10,115,630

INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming an interconnect structure, comprising:forming a lower etch stop layer (ESL);
forming a middle low-k (LK) dielectric layer over the lower ESL;
forming a supporting layer over the middle LK dielectric layer;
forming an upper LK dielectric layer over the supporting layer;
forming an upper conductive feature in the upper LK dielectric layer through the supporting layer;
forming a gap along an interface of the upper conductive feature and the upper LK dielectric layer and along an interface of the upper conductive feature and the middle LK dielectric layer, wherein the step of forming the gap along the interface of the upper conductive feature and the upper LK dielectric layer is performed by removing a portion of the upper LK dielectric layer along the interface by a wet etching process; and
forming an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

US Pat. No. 10,115,629

AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES

International Business Ma...

1. A semiconductor device, comprising:a first metallic structure and a second metallic structure disposed adjacent to each other on a substrate with a space disposed between the first and second metallic structures, wherein the first metallic structure comprises a gate structure of a transistor and wherein the second metallic structure comprises a source/drain contact; and
a dielectric capping layer formed over the first and second metallic structures to form an air gap in the space between the first and second metallic structures;
wherein an upper portion of the air gap is disposed above an upper surface the first metallic structure and below an upper surface of the second metallic structure; and
wherein a bottom portion of the air gap is disposed below a bottom surface of the second metallic structure.

US Pat. No. 10,115,627

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a base;
a memory cell region on the base comprising a first plurality of conductive layers including first and second portions, and a first plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers;
a first stacked body on the base comprising a second plurality of insulating layers and a second plurality of conductive layers fewer than the number of the first plurality of conductive layers, each of the conductive layers of the second plurality being connected to one of the conductive layers of the first portion of the first plurality, wherein an insulating layer of the second plurality of insulating layers extends between, and separates, each two adjacent conductive layers of the second plurality of conductive layers, an end portion of the first stacked body having a first stair portion having a first stair-like shape wherein a surface of each of the second plurality of conductive layers is exposed; and
a second stacked body on the base comprising a third plurality of insulating layers and a third plurality of conductive layers fewer in number than the first plurality of conductive layers, each of the conductive layers of the third plurality being connected to one of the conductive layers of the second portion of the first plurality, wherein an insulating layer of the third plurality of insulating layers extends between, and separates, each two adjacent conductive layers of the third plurality of conductive layers, an end portion of the second stacked body having a second stair portion having a second stair-like shape wherein a surface of each of the third plurality of conductive layers is exposed, the second stair portion spaced from the first stair portion by a first distance, wherein
the lowermost layer of the first stacked body is in contact with the base and the lowermost layer of the second stacked body is in contact with the base.

US Pat. No. 10,115,624

METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION

Taiwan Semiconductor Manu...

1. A method comprising:forming a plurality of fin elements extending from a substrate using a hardmask layer;
forming isolation features disposed between adjacent fin elements;
irradiating the isolation features using a first pulsed laser beam having a first pulse duration,
wherein prior to the irradiating the isolation features, the isolation features have a first etch rate in a first solution, and
wherein after the irradiating the isolation features, a top portion of the isolation features has a second etch rate less than the first etch rate in the first solution, and a bottom portion of the isolation features has the first etch rate;
after the irradiating the isolation features, removing the hardmask layer over the substrate by an etching process using the first solution;
forming a gate structure over the plurality of fin elements;
depositing an inter-level dielectric (ILD) layer over the gate structure; and
irradiating the ILD layer using a second pulsed laser beam having a second pulse duration different from the first pulse duration.

US Pat. No. 10,115,622

WAFER PROCESSING LAMINATE AND METHOD FOR PROCESSING WAFER

SHIN-ETSU CHEMICAL CO., L...

1. A wafer processing laminate comprising a support, a temporary adhesive material layer laminated on the support, and a wafer stacked on the temporary adhesive material layer, the wafer having a front surface on which a circuit is formed and a back surface to be processed, the temporary adhesive material layer comprising a first temporary adhesive layer composed of a thermoplastic resin layer (A) laminated on the front surface of the wafer, a second temporary adhesive layer composed of a thermosetting resin layer (B) laminated on the first temporary adhesive layer, and a third temporary adhesive layer composed of a separation layer (C) laminated between the support and the thermosetting resin layer (B), the thermoplastic resin layer (A) being soluble in a cleaning liquid (D) after processing the wafer, the thermosetting resin layer (B) being insoluble in the cleaning liquid (D) after heat curing and capable of absorbing the cleaning liquid (D) such that the cleaning liquid (D) permeates into the layer (B), the layer (C) having a peeling force of 0.5 gf or more and 50 gf or less which is required for peeling the thermosetting resin layer (B) along an interface between the thermosetting polymer layer (B) and the separation layer (C), or which is required for peeling the thermosetting polymer layer (B) with cohesion failure of the separation layer (C), when the polymer layer (B) laminated on the separation layer (C) on the support is thermally cured, as measured by 180° peeling using a test piece having a width of 25 mm.

US Pat. No. 10,115,619

COUPLING TRANSFER SYSTEM

NATIONAL INSTITUTE OF ADV...

1. A transfer box having a sealing structure hermetically sealable by means of tight coupling of a transfer box body and a transfer box door, said transfer box structured in such a way that magnets of the transfer box body face magnetic bodies of the transfer box door when the transfer box door is closed on the transfer box body, wherein these magnets and the magnetic bodies which are connected together form a loop constituting a first magnetic closed circuit in which magnetism is transmitted through the magnets and the magnetic bodies, said magnetic bodies of the transfer box door being configured to form a loop constituting a second magnetic closed circuit with magnetized electromagnets connected together with the magnetic bodies when the electromagnets face the magnetic bodies on a side opposite to the transfer box body side in which magnetism is transmitted through the magnetic bodies and the magnetized electromagnets.

US Pat. No. 10,115,618

RETICLE TRANSFER SYSTEM AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:moving reticles in a local fabrication system, the local fabrication system comprising:
a plurality of lithography apparatuses;
a first service area configured to serve a first group of lithography apparatuses;
a second service area configured to serve a second group of lithography apparatuses; and
an internal buffer located at a boundary between the first service area and the second service area, wherein the internal buffer is a movable buffer;
transporting a first reticle from the first service area to a lithography apparatus in the second service area;
transporting a second reticle from the second service area to the lithography apparatus in the second service area; and
loading the first reticle into the internal buffer when the second reticle is processed in the lithography apparatus.

US Pat. No. 10,115,617

SYSTEM ARCHITECTURE FOR VACUUM PROCESSING

INTEVAC, INC., Santa Cla...

1. A system for processing wafers in a vacuum processing chamber, comprising:a plurality of carriers, each carrier comprising a frame having a plurality of openings, each opening configured to accommodate a single wafer;
a transport mechanism configured to transport the plurality of carriers through a loading station, to the vacuum processing chamber, and to an unloading station;
a return mechanism configured to return empty carriers from the unloading station to the loading station in an atmospheric environment, the return mechanism comprising a first carrier elevator positioned in the unloading station, a second carrier elevator positioned in the loading station, and a conveyor between the first and second carrier elevators;
a plurality of susceptors, each susceptor configured for supporting a single wafer;
an attachment mechanism for attaching a plurality of susceptors to each of the carriers, wherein each of the susceptors is attached to a corresponding position at an underside of a corresponding carrier, such that a wafer positioned on one of the susceptors is situated within one of the plurality of opening in the carrier;
a plurality of masks, each mask attached over front side of one of the plurality of opening in the carrier;
an alignment mechanism, configured to align the wafers to the masks;
a lifter configured for separating the susceptors from the carrier and masks;wherein said plurality of masks comprise:a plurality of inner masks, each configured for placing on top of one of the plurality of opening in the carrier, the inner mask having an opening-pattern to mask parts of the wafer and expose remaining parts of the wafer; and,
a plurality of outer masks, each configured for placing on top of a corresponding inner mask, the outer mask having an opening configured to partially cover the inner mask.

US Pat. No. 10,115,616

CARRIER ADAPTER INSERT APPARATUS AND CARRIER ADAPTER INSERT DETECTION METHODS

Applied Materials, Inc., ...

5. An adapter insert, comprising:an adapter frame configured to be received within a substrate carrier, wherein the substrate carrier is adapted to hold 450 mm substrates;
a plurality of support rails coupled to the adapter frame and adapted to support a plurality of 300 mm substrates;
a frame extension adapted to be coupled to the adapter frame; and
a mapping feature located on the frame extension and configured to be detected by a sensor affixed to an end effector of a robot external to the substrate carrier when the adapter insert is received within the substrate carrier, the mapping feature for determining whether the adapter insert is present or absent in a the substrate carrier.

US Pat. No. 10,115,615

SUBSTRATE PROCESSING APPARATUS AND CONTROL METHOD OF SUBSTRATE PROCESSING APPARATUS

TOSHIBA MEMORY CORPORATIO...

1. A substrate processing apparatus comprising:a processing unit to process a substrate; and
a manipulator for maintenance, the manipulator being placed near the processing unit,
wherein the manipulator includes:
a first arm; and
a second arm combined with the first arm,
the manipulator causes the first arm and the second arm to move independently of each other according to control of a controller;
the substrate processing apparatus further comprises a load lock chamber for maintenance that can accommodate the first arm and the second arm;
wherein the manipulator, according to control of the controller, causes at least a tip portion of the second arm to move into the processing unit for the tip portion to suck a part in the processing unit and causes the first arm and the second arm to hand the part from the second arm onto the first arm and to transfer the part with the first arm into the load lock chamber.

US Pat. No. 10,115,614

TRANSFER CHAMBER AND METHOD FOR PREVENTING ADHESION OF PARTICLE

TOKYO ELECTRON LIMITED, ...

1. A method for preventing particle adhesion to a target substrate in a chamber, the chamber comprising a chamber main body which is switchable between a depressurized environment and an atmospheric pressure environment, an ionization unit configured to generate an ionized gas to be supplied into the chamber main body, and a gas exhaust unit configured to exhaust the chamber main body, the method comprising:accommodating the target substrate into the chamber main body in the atmospheric pressure environment while supplying the ionized gas into the chamber main body;
performing a first step in which an inner pressure of the chamber main body is decreased to a first pressure by exhausting the chamber main body;
performing a second step in which the inner pressure is increased to a second pressure by supplying the ionized gas into the chamber main body without exhausting the chamber main body; and
performing a third step in which the inner pressure is decreased to a third pressure by exhausting the chamber main body,
wherein the second and third steps are both sequentially repeated a plurality of times until an environment of the chamber main body reaches a predetermined pressure which is lower than the pressure of the atmospheric pressure environment,
wherein the third pressure is lower than the first and the second pressures and the second pressure is higher than the first pressure and lower than the pressure of the atmospheric pressure environment, andwherein, for each sequential repetition of the second and third steps, the second and the third pressures of a subsequent repetition are lower than the second and third pressures, respectively, of a prior repetition of the second and third steps.

US Pat. No. 10,115,612

MANUFACTURING METHOD FOR VERTICAL CAVITY SURFACE EMITTING LASER

Murata Manufacturing Co.,...

1. A manufacturing method for a vertical cavity surface emitting laser, the method comprising steps of:forming, on a substrate, a multilayer body including first and second Distributed Bragg Reflector layers, an active layer, and a to-be-oxidized layer becoming a current constriction structure;
processing the multilayer body such that a lateral surface of at least the to-be-oxidized layer is exposed; and
forming the current constriction structure by oxidizing the to-be-oxidized layer from the lateral surface thereof after the multilayer body has been processed,
wherein the step of forming the current constriction structure includes steps of:
placing a uniformly-heated plate on a heat conduction member, the uniformly-heated plate having a planar upper surface;
positioning the substrate along the uniformly-heated plate so that the entire substrate is spaced from the planar upper surface of the uniformly-heated plate thereby forming a gap between the planar upper surface of the uniformly-heated plate and the substrate; and
heating the substrate by radiant heat from the uniformly-heated plate by heating the heat conduction member,
wherein the uniformly-heated plate is made of an anisotropic material having a larger thermal conductivity in a planar direction than in a vertical direction, and
wherein the step of positioning the substrate includes a step of supporting a peripheral edge portion of the substrate by a spacer that is attached to the heat conduction member, and a thermal conductivity of the spacer is smaller than the thermal conductivity of the uniformly-heated plate in the vertical direction.

US Pat. No. 10,115,611

SUBSTRATE COOLING METHOD, SUBSTRATE TRANSFER METHOD, AND LOAD-LOCK MECHANISM

TOKYO ELECTRON LIMITED, ...

1. A substrate cooling method for, by using a load-lock mechanism for controlling a pressure therein between a first pressure and a second pressure in the case of transferring the substrate between a first module maintained at a first pressure close to an atmospheric pressure and a second module maintained at a second pressure in a vacuum state, cooling a high-temperature substrate transferred from the second module to the first module, the load-lock mechanism including a chamber accommodating a substrate, a cooling member disposed in the chamber and configured to cool the substrate disposed proximate to the cooling member, a gas exhaust unit configured to exhaust the chamber, and a purge gas inlet unit configured to introduce a purge gas into the chamber, the method comprising:maintaining a pressure in the chamber to the second pressure, allowing the chamber to communicate with the second module, and loading the high-temperature substrate into the chamber;
placing the substrate to a cooling position close to the cooling member;
exhausting the chamber to a third pressure at which a region between a surface of the cooling member and a backside of the substrate satisfies a molecular flow condition to obtain uniform temperature distribution of the substrate; and
after maintaining the third pressure in the chamber at the third pressure for a first duration, introducing a purge gas into the chamber to increase the pressure in the chamber to the first pressure, and cooling the substrate by using the cooling member.

US Pat. No. 10,115,609

SEPARATION AND REGENERATION APPARATUS AND SUBSTRATE PROCESSING APPARATUS

Tokyo Electron Limited, ...

1. A separation and regeneration apparatus comprising:a controller including a processor coupled with a memory;
a mixed gas generating unit configured to receive a wafer covered with a first fluorine-containing organic solvent having a first boiling point;
a supercritical fluid supply line connecting to the mixed gas generating unit, the supercritical fluid supply line being provided with a first valve;
a discharge line connected to the mixed gas generating unit and including a second valve; and
a distillation tank configured to store hot water, the distillation tank including:
a water supply line that allows for periodic supply of water into the distillation tank,
a water level gauge configured to measure a level of the hot water within the distillation tank,
a distillation tank heater, and
an introduction line connected to the discharge line and running between the mixed gas generating unit and the distillation tank, the introduction line terminating in the distillation tank,
wherein the controller is programmed to:
control a mixed gas generating unit heater that heats the mixed gas generating unit to a predetermined temperature;
control the distillation tank heater to maintain the water within the distillation tank at a temperature between the first boiling point and the second boiling point,
open the first valve of the supercritical fluid supply line so as to introduce a second fluorine-containing organic solvent having a second boiling point lower than the first boiling point from the supercritical fluid supply line into the mixed gas generating unit, such that a mixed gas is generated from the first fluorine-containing organic solvent covering the wafer and the second fluorine-containing organic solvent introduced from the supercritical fluid supply line; and
close the first valve of the supercritical fluid supply line and open the second valve of the discharge line so as to discharge the mixed gas from the mixed gas generating unit to the distillation tank through the discharge line such that the mixed gas is conveyed into the hot water within the distillation tank through the introduction line to be separated into a liquid state of the first fluorine-containing organic solvent, a gaseous state of the second fluorine-containing organic solvent, and F ions that will be incorporated into the hot water.

US Pat. No. 10,115,607

METHOD AND APPARATUS FOR WAFER OUTGASSING CONTROL

APPLIED MATERIALS, INC., ...

1. A semiconductor processing system, comprising:a purge station, comprising:
an enclosure;
a gas supply coupled to the enclosure;
an exhaust pump coupled to the enclosure;
a first purge gas port formed in the enclosure;
a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, wherein the first channel comprises:
a particle filter;
a heater; and
a flow controller;
a second purge gas port formed in the enclosure; and
a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end, wherein the second channel comprises a dry scrubber.

US Pat. No. 10,115,606

METHODS OF PROMOTING ADHESION BETWEEN UNDERFILL AND CONDUCTIVE BUMPS AND STRUCTURES FORMED THEREBY

Intel Corporation, Santa...

1. A method of forming a package structure comprising:modifying a filler to have a surface comprising a thiol based adhesion promoter; and
subsequent to modifying the filler, adding the modified filler to an underfill material; and
forming the underfill material having the modified filler on conductive bumps of the package structure, wherein the thiol based adhesion promoter comprises a molecular weight above about 150 g/mol.

US Pat. No. 10,115,604

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE

MediaTek Inc., Hsin-Chu ...

1. A method for fabricating a base for a semiconductor package, comprising:providing a carrier with conductive seed layers on the top surface and the bottom surface of the carrier;
forming radio-frequency (RF) devices respectively on the conductive seed layers;
laminating a first base material layer and a second base material layer respectively on the conductive seed layers, covering the RF devices; and
separating the first base material layer the second base material layer, which contain the RF devices thereon, from the carrier to form a first base and a second base.

US Pat. No. 10,115,601

SELECTIVE FILM FORMATION FOR RAISED AND RECESSED FEATURES USING DEPOSITION AND ETCHING PROCESSES

Tokyo Electron Limited, ...

1. A substrate processing method, comprising:providing a substrate having a recessed feature with a sidewall and a bottom portion;
depositing a film in the recessed feature and on a field area around the opening of the recessed feature, wherein the film is non-conformally deposited with a greater film thickness on the bottom portion than on the sidewall and the field area;
etching the film in an atomic layer etching (ALE) process in the absence of a plasma, wherein the etching thins the film on the bottom portion and removes the film from the sidewall and the field area; and
repeating the depositing and the etching at least once to increase the film thickness on the bottom portion.

US Pat. No. 10,115,600

METHOD OF ETCHING SEMICONDUCTOR STRUCTURES WITH ETCH GAS

American Air Liquide, Inc...

1. A method of depositing an etch-resistant polymer layer on a substrate, the method comprising:introducing a vapor of a compound into a reaction chamber containing the substrate, the compound having a formula selected from the group consisting of: C2F4S2 (CAS 1717-50-6), F3CSH (CAS 1493-15-8), F3C—CF2—SH (CAS 1540-78-9), F3C—CH2—SH (CAS 1544-53-2), CHF2—CF2—SH (812-10-2), CF3—CF2—CH2—SH (CAS 677-57-6), F3C—CH(SH)—CF3 (CAS 1540-06-3), F3C—S—CF3 (CAS 371-78-8), F3C—S—CHF2 (CAS 371-72-2), F3C—CF2—S—CF2—CF3 (CAS 155953-22-3), F3C—CF2—CF2—S—CF2—CF2—CF3 (CAS 356-63-8), c(—S—CF2—CF2—CHF—CF2—) (CAS 1035804-79-5), c(—S—CF2—CHF—CHF—CF2—) (CAS 30835-84-8), c(—S—CF2—CF2—CF2—CF2—CF2—) (CAS 24345-52-6), c(—S—CFH—CF2—CF2—CFH—)(2 R, 5 R) (CAS 1507363-75-8), c(—S—CFH—CF2—CF2—CFH—)(2 R, 5 S) (CAS 1507363-76-9), and c(—S—CFH—CF2—CF2—CH2—) (CAS 1507363-77-0); and
plasma activating the compound to form the etch-resistant polymer layer on the substrate.

US Pat. No. 10,115,599

SPECTRALLY AND TEMPORALLY ENGINEERED PROCESSING USING PHOTOELECTROCHEMISTRY

The Board of Trustees of ...

1. A method for fabricating a photodetector integral with a parabolic reflector, the method comprising:a. photoelectroplating a top-contact metal-semiconductor-metal photodetector on a semiconductor wafer; and
b. defining a parabolic surface on the semiconductor wafer by
i. applying an etch solution to the surface of the semiconductor wafer;
ii. generating a spatial pattern of electron-hole pairs by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface of the semiconductor wafer; and
iii. applying an AC electrical potential across the interface of the semiconductor and the etch solution with any specified temporal profile of onset and duration relative to the temporal profile of the spatial pattern of illumination.

US Pat. No. 10,115,598

SUBSTRATE HOLDER, A METHOD FOR HOLDING A SUBSTRATE WITH A SUBSTRATE HOLDER, AND A PLATING APPARATUS

EBARA CORPORATION, Tokyo...

1. An apparatus for plating a substrate, comprising:a plating bath configured to house the substrate and an anode; and
an intermediate mask arranged between the substrate and the anode, wherein
the intermediate mask has a plate-shaped member having an opening through which an electric field from the anode to the substrate is made to pass and a plurality of edge parts that form the opening, and wherein
the apparatus further includes a drive mechanism configured to move each of the edge parts in a direction toward the substrate in a state where the plate-shaped member is fixed to the plating bath.

US Pat. No. 10,115,597

SELF-ALIGNED DUAL-METAL SILICIDE AND GERMANIDE FORMATION

Taiwan Semiconductor Manu...

1. A method comprising:growing a first epitaxy semiconductor region on a wafer, wherein the first epitaxy semiconductor region comprises an upward facing facet facing upwardly and a downward facing facet facing downwardly;
forming a second epitaxy semiconductor region on the upward facing facet and the downward facing facet;
forming a first metal layer over the second epitaxy semiconductor region on the upward facing facet; and
performing a first anneal, wherein the first metal layer reacts with the second epitaxy semiconductor region to form a first metal silicide/germanide layer, the downward facing facet being free of the first metal silicide/germanide layer.

US Pat. No. 10,115,596

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A T-SHAPE IN THE METAL GATE LINE-END

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a metal gate structure in a semiconductor device, the method comprising:removing a dummy poly gate;
removing interlayer (IL) oxide and shallow trench isolation (STI) using a dry etch process and a wet lateral etch process to form a reversed T-shape void in the semiconductor device; and
depositing metal gate material in the reversed T-shape void to form a reversed T-shape structure in a metal gate line-end.

US Pat. No. 10,115,593

CHEMICAL MODIFICATION OF HARDMASK FILMS FOR ENHANCED ETCHING AND SELECTIVE REMOVAL

Applied Materials, Inc., ...

1. A carbon-based hardmask layer, comprising:a substrate; and
an amorphous carbon layer above the substrate, the amorphous carbon layer comprising carbon and hydrogen, and the amorphous carbon layer comprising a metallic filler bonded to the carbon, wherein a total atomic percentage of the hydrogen in the amorphous carbon layer is between 5% and 50%, and the total atomic percentage of the metallic filler in the amorphous carbon layer is between 5% and 90%.

US Pat. No. 10,115,592

PATTERNING PROCESS WITH SILICON MASK LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A lithography method, comprising:forming an under layer on a substrate;
forming a silicon-containing middle layer on the under layer, wherein the silicon-containing layer includes a type of monomers that each has four cross-linkable sides, and wherein the silicon-containing middle layer has a thermal base generator (TBG) composite that is capable of releasing a base;
forming a photosensitive layer on the silicon-containing middle layer;
performing an exposing process to the photosensitive layer; and
developing the photosensitive layer, thereby forming a patterned photosensitive layer.

US Pat. No. 10,115,591

SELECTIVE SIARC REMOVAL

Tokyo Electron Limited, ...

1. A method for an integration process of selectively removing a silicon-containing antireflective coating (SiARC) in a substrate, the method comprising:providing a substrate in a process chamber, the substrate comprising:
a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer;
performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer;
performing a nitridation modification process on the SiARC layer of the structure, the nitridation modification process using a plasma of nitrogen ions and bombarding the SiARC layer to implant the nitrogen ions therein to an implantation depth, converting the SiARC layer into a nitrided SiARC layer having an increased nitrogen content; and
performing a removal process of the nitrided SiARC layer of the structure, wherein the increased nitrogen content increases percent removal of the SiARC layer and increases etch selectivity of the SiARC layer relative to the pattern transfer layer and/or the underlying layer.

US Pat. No. 10,115,590

MANUFACTURING OF SILICON STRAINED IN TENSION ON INSULATOR BY AMORPHISATION THEN RECRYSTALLISATION

1. A method for making a structure comprising a strained silicon layer, the method comprising:providing a substrate that has at least one region coated with a stack comprising a silicon semiconducting layer, the silicon semiconducting layer itself being coated with a second semiconducting area comprising silicon germanium, the second semiconducting area itself being coated with a third semiconducting area comprising an interface delimitation layer that is in contact with the second semiconducting area, the interface delimitation layer being made of silicon or silicon germanium with a germanium concentration lower than a germanium concentration of the second semiconducting area;
making at least one ion implantation such that the silicon semiconducting layer and the second semiconducting area are selectively amorphised, while keeping a continuous crystalline portion in the third semiconducting area; and then
recrystallising the second semiconducting area and the silicon semiconducting layer using the continuous crystalline portion of the third semiconducting area as a starting area for a recrystallisation front, the second semiconducting area imposing its parameter on the silicon semiconducting layer so as to strain the silicon semiconducting layer.

US Pat. No. 10,115,589

EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICES, ELECTRONIC DEVICE, METHOD FOR PRODUCING THE EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICES, AND METHOD FOR PRODUCING THE ELECTRONIC DEVICE

SHIN-ETSU HANDOTAI CO., L...

1. A method for producing an electronic device, comprising:forming an AlN initial layer on a Si-based substrate;
forming a buffer layer on the AlN initial layer;
forming a channel layer on the buffer layer;
forming a barrier layer on the channel layer;
forming a cap layer on the barrier layer; and
forming electrodes on the cap layer,
wherein
a roughness Sa of a surface of the AN initial layer on a side where the buffer layer is located is set at 4 nm or more and 8 nm or less.

US Pat. No. 10,115,587

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device comprising:providing a silicon wafer manufactured by a floating method from a polycrystalline silicon ingot, the silicon wafer having a first main surface and a second main surface that are opposite to each other;
forming an oxide layer on the first main surface of the silicon wafer, the oxide layer having an opening through which the silicon wafer is exposed and in which a diffusion source is filled; and
performing heat treatment to the silicon wafer with the oxide layer formed thereon, to thereby diffuse impurity from the diffusion source at the first main surface to the second main surface of the silicon wafer, so as to create a diffusion layer that forms a pn junction with the silicon wafer, wherein
the heat treatment is performed for a time that is at least as long as a time for forming the diffusion layer with a predetermined diffusion depth of 100 ?m, and
the entire heat treatment has a single heat treatment step that is performed in a diffusion furnace, in a nitrogen-free inert gas atmosphere and at a temperature that is more than 1300° C. and no more than 1350° C.

US Pat. No. 10,115,586

METHOD FOR DEPOSITING A PLANARIZATION LAYER USING POLYMERIZATION CHEMICAL VAPOR DEPOSITION

Tokyo Electron Limited, ...

1. A method for processing a substrate, the method comprising:providing a substrate containing a plurality of features with gaps between the plurality of features;
delivering precursor molecules by gas phase exposure to the substrate;
adsorbing the precursor molecules on the substrate to at least substantially fill the gaps with a layer of the adsorbed precursor molecules; and
reacting the precursor molecules to form a polymer layer that at least substantially fills the gaps.

US Pat. No. 10,115,582

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate comprising a MEMS region and a connection region thereon;
a dielectric layer disposed on said substrate in said connection region;
a poly-silicon layer disposed on said dielectric layer, wherein said poly-silicon layer serves as an etch-stop layer;
a connection pad disposed on said poly-silicon layer;
a passivation layer covering said dielectric layer and directly contacting with said poly-silicon layer, wherein said passivation layer comprises an opening that exposes entire said connection pad and a transition region between said connection pad and said passivation layer; and
a conductive layer conformally covering said connection pad and said poly-silicon layer in said opening of said passivation layer.

US Pat. No. 10,115,581

REMOVAL OF PARTICLES ON BACK SIDE OF WAFER

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor device, comprising:loading a semiconductor wafer into a wafer handling system, the semiconductor wafer having a front side and a back side and having an outer rim, an inner region, and an outer region, wherein one or more alignment marks are positioned in an outer region of the wafer's front side, wherein the outer region is shaped an as annular ring having a predetermined width, wherein an outer boundary of the annular ring is spaced apart from the outer rim of the wafer by a distance in a range of about 2 mm to about 3 mm;
removing, with a brush, contaminant particles in the outer region of the wafer's back side without brushing the outer rim and without brushing the inner region, such that the brush is passed over the outer region on the back side of the wafer;
holding the brush against the back side of the wafer with tension provided by a spring; and
collecting the removed contaminant particles and discarding the collected contaminant particles out of the wafer handling system.

US Pat. No. 10,115,578

WAFER AND METHOD OF PROCESSING WAFER

Disco Corporation, Tokyo...

1. A method of processing a wafer having on a face side thereof a device area with a plurality of devices formed therein and an outer circumferential excess area surrounding the device area, comprising:a grinding step for grinding a reverse side of the wafer corresponding to the device area with a grinding wheel that is smaller in diameter than the wafer, thereby forming a first portion corresponding to the device area and an annular second portion surrounding said first portion, said annular second portion being thicker and more protrusive toward a reverse side thereof than said first portion,
wherein in the grinding step, said grinding wheel and said wafer are moved relatively to each other so that an angle formed between the reverse side of said first portion and an inner side surface of said annular second portion is larger than 45° and smaller than 75°.

US Pat. No. 10,115,577

ISOTOPE RATIO MASS SPECTROMETRY

California Institute of T...

1. A method of isotope ratio mass spectrometry, comprising:injecting a sample for analysis into a gas chromatography column;
directing an effluent from the gas chromatography column to a switching arrangement; and
selecting a configuration of the switching arrangement, such that: in a first mode, the effluent from the gas chromatography column is provided as an input to a peak broadener; and in a second mode, an effluent from the peak broadener is provided to a mass spectrometer for isotope ratio mass spectrometry without the effluent from the gas chromatography column being provided as an input to the peak broadener.

US Pat. No. 10,115,576

METHOD AND AN APPARATUS FOR ANALYZING A COMPLEX SAMPLE

WATERS TECHNOLOGIES CORPO...

1. A computer-implemented method of analyzing a complex sample, comprising:generating, via a sequential chromatographic-IMS-MS apparatus, a separated sample by separating the complex sample based on a chromatographic retention time via a chromatography module and an ion-mobility drift time via an ion-mobility spectrometry (IMS) module;
performing, via a mass spectrometry (MS) module of the sequential chromatographic-IMS-MS apparatus, mass analysis of the separated sample to generate a plurality of experimental mass spectra having isotopic clusters, wherein each spectrum of the plurality of spectra is associated with the chromatographic retention time and the ion-mobility drift time; and
resolving, via a data processing unit operably coupled to the sequential chromatographic-IMS-MS apparatus, one or more saturated or interfered peaks of the experimental isotopic cluster by:
calculating a model isotopic cluster of a precursor or product ion associated with a candidate compound in the sample, in correspondence to the natural isotopic-abundance ratios of elements composing the compound; and
comparing peaks of the model isotopic cluster to corresponding peaks of an isotopic cluster of one of the experimental mass spectra to extract one or more saturated or interfered peaks of the experimental isotopic cluster, wherein the peaks of the experimental isotopic cluster comprise at least one un-saturated and un-interfered peak.

US Pat. No. 10,115,575

PROBABILITY-BASED LIBRARY SEARCH ALGORITHM (PROLS)

DH Technologies Developme...

1. A system for determining corresponding mass peaks in experimental and library product ion spectra using a mass-to-charge ratio (m/z) tolerance probability function with values between 1 and 0, comprising:an ion source that ionizes one or more known compounds of a sample, producing an ion beam of precursor ions;
a tandem mass spectrometer that receives the ion beam from the ion source and that selects at least one precursor ion from the ion beam corresponding to at least one compound of the one or more known compounds and fragments the at least one precursor ion, producing a product ion mass spectrum for the at least one precursor ion; and
a processor in communication with the tandem mass spectrometer that
receives the product ion mass spectrum from the tandem mass spectrometer,
receives an m/z tolerance probability function that varies from 1 to 0 with increasing values of an m/z difference between two mass peaks and that includes one or more values between 1 and 0,
retrieves from a memory a library product ion mass spectrum for the at least one compound,
calculates an m/z difference between at least one experimental product ion mass peak in the product ion mass spectrum and at least one library product ion mass peak in the library product ion mass spectrum,
calculates an m/z tolerance probability, (pm/z)1, from the m/z difference using the m/z tolerance probability function, and
determines if the at least one experimental product ion mass peak and the at least one library product ion mass peak are corresponding peaks based on the m/z tolerance probability, (pm/z)1.

US Pat. No. 10,115,573

APPARATUS FOR HIGH COMPRESSIVE STRESS FILM DEPOSITION TO IMPROVE KIT LIFE

APPLIED MATERIALS, INC., ...

1. A process kit, comprising:a first ring having an inner wall defining an inner diameter, an outer wall defining an outer diameter, an upper surface disposed between the inner wall and the outer wall, and an opposing lower surface disposed between the inner wall and the outer wall, wherein a first portion of the upper surface proximate the inner wall is concave, and wherein a second portion of the upper surface has a length that extends horizontally away from the first portion and terminates at the outer wall; and
a second ring having an upper surface and an opposing lower surface, wherein a first portion of the lower surface of the second ring is configured to rest upon the length of the upper surface of the second portion of the first ring, wherein a second portion of the lower surface of the second ring is convex and extends into but does not touch the concave first portion of the upper surface of the first ring.

US Pat. No. 10,115,572

METHODS FOR IN-SITU CHAMBER CLEAN IN PLASMA ETCHING PROCESSING CHAMBER

Applied Materials, Inc., ...

1. A method for in-situ chamber cleaning after an etching process, comprising:supplying a cleaning gas mixture including at least an oxygen containing gas and a hydrogen containing gas into a processing chamber in which the etching process was performed on a substrate comprising Cr containing material;
controlling a processing pressure at less than 2 millitorr;
applying a RF source power to the processing chamber to form a plasma from the cleaning gas mixture; and
cleaning the processing chamber in the presence of the plasma.

US Pat. No. 10,115,571

REAGENT DELIVERY SYSTEM FREEZE PREVENTION HEAT EXCHANGER

APPLIED MATERIALS, INC., ...

1. A reagent delivery system, comprising:a water tank having an inner volume that holds a reagent liquid when disposed therein; and
a heat exchanger having a central opening disposed in the inner volume and configured to keep a top surface of the reagent liquid from freezing when reagent liquid is disposed within the water tank,
wherein the heat exchanger is formed from a plurality of concentric cylinders that permits a flow of a reagent liquid between the concentric cylinders, and wherein each of the plurality of concentric cylinders is perforated to allow the reagent liquid to flow through the concentric cylinders.

US Pat. No. 10,115,570

PLASMA SOURCE AND METHODS FOR DEPOSITING THIN FILM COATINGS USING PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION

AGC FLAT GLASS NORTH AMER...

1. A method of forming a coating using plasma enhanced chemical vapor deposition (PECVD), comprising:a) providing a plasma source comprising a first hollow cathode and a second hollow cathode disposed adjacently and separated by a space;
b) producing, with the plasma source, a plasma that is linear and that is made substantially uniform over its length in the substantial absence of Hall current;
c) providing a substrate with at least one surface to be coated proximate to the plasma;
d) flowing a precursor gas through the space;
e) energizing, partially decomposing, or fully decomposing the precursor gas by contacting the plasma with the precursor gas; and
f) depositing the coating on the at least one surface of the substrate using PECVD;
wherein the depositing includes one of bonding and condensing a chemical fragment of the precursor gas containing a desired chemical element for coating on the at least one surface of the substrate.

US Pat. No. 10,115,567

PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus of generating plasma by high frequency discharge of a processing gas within a decompression processing vessel that accommodates therein a processing target object, which is loaded into and unloaded from the processing vessel, and performing a process on the processing target object within the processing vessel with the plasma, the plasma processing apparatus comprising:a first high frequency power supply configured to output a first high frequency power;
a first high frequency power modulation unit configured to pulse-modulate an output of the first high frequency power supply with a modulation pulse having a regular frequency such that the first high frequency power has a high level during a first period and has a low level lower than the high level during a second period, the first period and the second period being repeated alternately with a preset duty ratio;
a first high frequency transmission line configured to transmit the first high frequency power outputted from the first high frequency power supply to a first electrode provided within or in the vicinity of the processing vessel; and
a first matching device configured to measure a load impedance on the first high frequency transmission line with respect to the first high frequency power supply, and configured to match a weighted average measurement value, which is obtained by weighted-averaging a load impedance measurement value during the first period and a load impedance measurement value during the second period with a preset weighted value, with an output impedance of the first high frequency power supply.

US Pat. No. 10,115,566

METHOD AND APPARATUS FOR CONTROLLING A MAGNETIC FIELD IN A PLASMA CHAMBER

APPLIED MATERIALS, INC., ...

1. An electromagnetic cosine-theta (cos ?) coil ring assembly for use in a process, comprising:a cylindrical body;
an inner electromagnetic cosine-theta (cos ?) coil ring including a first plurality of inner coils disposed about an inner surface of the cylindrical body and configured to generate a magnetic field in a first direction; and
an outer electromagnetic cosine-theta (cos ?) coil ring including a second plurality of outer coils disposed about an outer surface of the cylindrical body and configured to generate a magnetic field in a second direction different from the first direction, wherein the outer electromagnetic cos ? coil ring is disposed concentrically about the inner electromagnetic cos ? coil ring.

US Pat. No. 10,115,563

ELECTRON-BEAM LITHOGRAPHY METHOD AND SYSTEM

NATIONAL TAIWAN UNIVERSIT...

1. An electron-beam lithography method, comprising:performing a low-temperature treatment to chill a developer solution;
utilizing an electron-beam to irradiate an exposure region of a positive-tone electron-sensitive layer; and
utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer, wherein the development region is present within the exposure region, and an area of the development region is smaller than an area of the exposure region;
inputting a size value of a predetermined pattern to be formed in the positive-tone electron-sensitive layer into a pattern dimension simulation system; and
computing and outputting a parameter recipe of the electron-beam used to irradiate the positive-tone electron-sensitive layer by the pattern dimension simulation system, wherein the parameter recipe of the electron-beam includes a high current parameter, and the high current parameter is substantially in a range between 30 pA to 300 pA, such that the pattern dimension simulation system is based on a model of two dimensional Gaussian function.

US Pat. No. 10,115,562

SYSTEMS INCLUDING A BEAM PROJECTION DEVICE PROVIDING VARIABLE EXPOSURE DURATION RESOLUTION

Samsung Electronics Co., ...

1. A beam projection device, comprising: a charged particle beam source configured to radiate a first beam; an aperture plate having a first array of apertures therein, respective ones of the apertures configured to generate respective second beams from the first beam; a blanking aperture plate having an array of blanking apertures therein corresponding to respective apertures of the first array of apertures and configured to selectively deflect second beams passing therethrough responsive to voltages applied to respective potential electrodes of the blanking apertures; a limiting aperture plate comprising a limiting aperture configured to pass ones of the second beams not deflected by the blanking apertures; and a plurality of electrode control circuits, respective ones of which are configured to apply voltages to respective ones of the potential electrodes, wherein, during a first time interval, the plurality of electrode control circuits applies voltages to the potential electrodes for durations based on clock signal with a first frequency, wherein, during a second time interval, the plurality of electrode control circuits applies voltages to the potential electrodes for durations based on a clock signal with a second frequency different from the first frequency, and wherein, during the first time interval and second time interval, beams passing through the limiting aperture are projected on the same target object to provide overlapping exposures of the target object.

US Pat. No. 10,115,559

APPARATUS OF PLURAL CHARGED-PARTICLE BEAMS

HERMES MICROVISION, INC.,...

1. A method for converting a single charged particle source into a plurality of virtual sub-sources, comprising steps of:deflecting, by a plurality of micro-deflectors of a micro-deflector array, a charged-particle beam of the single charged-particle source into a plurality of parallel beamlets forming a plurality of virtual images respectively, wherein each of the plurality of virtual images is one of the plurality of sub-sources;
adding, by a plurality of micro-compensators of a micro-compensator array, aberrations to each of the plurality of virtual images, wherein each micro-compensator of the plurality of micro-compensators is aligned with a corresponding one of the micro-deflectors; and
cutting a current of each of the plurality of beamlets.

US Pat. No. 10,115,557

X-RAY GENERATION DEVICE HAVING MULTIPLE METAL TARGET MEMBERS

HAMAMATSU PHOTONICS K.K.,...

1. An X-ray generation device comprising:an electron gun for emitting an electron beam;
a target unit having a target buried in a substrate having principal faces opposed to each other;
a housing at one end side of which the target unit is arranged and at the other end side opposed to the one end side of which the electron gun is arranged, the housing having an electron passage for the electron beam to pass;
a deflector for deflecting the electron beam passing in the electron passage to enable scanning on the target unit;
a signal acquisition unit for acquiring an incident signal generated from scanning the target unit with the electron beam; and
a control unit for controlling the deflector, based on the incident signal acquired by the signal acquisition unit,
wherein the target unit comprises:
the substrate comprising an electrical insulating material having X-ray permeability
a plurality of first metal members buried in the substrate and serving as the target; and
one or more second metal members, the one or more second metal members being surrounded by the plurality of first metal members or surrounding at least one of the plurality of first metal members, and the one or more second metal members generating location information by serving as a reference when identifying a location of the at least one of the plurality of first metal members based on the incident signal generated from the scanning with the electron beam,
wherein the one or more second metal members, when viewed from a normal direction to the principal faces, have a surface area larger than the a surface area of the plurality of first metal members, and have a length in the normal direction shorter than a length of the target, and
the control unit controls the deflector to scan the electron beam over the target, detects the plurality of first metal members based on the location information of the one or more second metal members acquired from the incident signal, and controls the deflector to irradiate the first metal member with the electron beam and generate X-rays.

US Pat. No. 10,115,555

ELECTRICAL SWITCH FOR A LOAD IN A VEHICLE

Amazon Technologies, Inc....

1. An unmanned aerial vehicle (UAV), comprising:a frame;
a power load;
a power source; and
an electrical switch comprising a moving member and a plurality of electrically conductive members, the plurality of electrically conductive members configured to move between mechanical positions in a predefined order to electrically couple the power load and the power source, wherein:
a first electrically conductive member is configured to move to a first mechanical position and form a first electrically conductive path between the power load and the power source based at least in part on the first mechanical position, the first electrically conductive path having first electrical resistivity;
a second electrically conductive member is configured to move to a second mechanical position and form a second electrically conductive path between the power load and the power source based at least in part on the second mechanical position, the second electrically conductive path having second electrical resistivity different from the first electrical resistivity; and
the moving member is configured to move the second electrically conductive member based at least in part on movement of the first electrically conductive member to the first mechanical position such that movement of the second electrically conductive member to the second mechanical position occurs based at least in part on the movement of the first electrically conductive member according to the predefined order.

US Pat. No. 10,115,554

FUSE CASE AND CASE COVER OF VACUUM CONTACTOR

LSIS CO., LTD., Anyang-S...

1. A fuse case and a case cover, which are detachable and applied to a vacuum contactor including a truck, a main circuit unit, and a front cover covering a front side of the main circuit unit, the fuse case and the case cover comprising:a fuse connected to an upper terminal of the main circuit unit and blowing, when a fault current is generated in a circuit, to break the circuit;
the fuse case opened in an upper side, accommodating the fuse, and having an insertion coupling part formed on a side surface thereof; and
the case cover coupled to the upper side of the fuse case, coupled to the insertion coupling part in an insertion-coupling manner, and covering a rear end portion of the fuse,
wherein the case cover includes an upper surface portion and side surface portions, and the side surface portions include a first side surface portion formed on a front side and a second side surface portion formed on a rear side,
wherein the first and second side surface portions are formed as dual walls and have a first rail recess and a second rail recess, respectively, and
wherein the side surface of the fuse case is inserted into the first rail recess and the second rail recess.

US Pat. No. 10,115,551

PROTECTIVE CIRCUIT BREAKER

SIEMENS AKTIENGESELLSCHAF...

1. A protective circuit breaker comprising:a switch housing;
a first and a second connection piece, each of the first and a second connection pieces extending on a rear side through and outside the switch housing and each of the first and a second connection pieces being connectable to a busbar;
a switching contact, arranged in the switch housing, including two contact elements configured to rest against one another when the switching contact is closed and configured to separate from one another when the switching contact is open, wherein at least one of the two contact elements is designed to be movable, and wherein the two contact elements are each respectively electrically connected to a respective one of the first and a second connection pieces;
a converter housing, including a first passage opening, inserted into a recess in the switch housing, wherein the second connection piece runs through the first passage opening;
a converter coil, arranged in the converter housing around the passage opening and around the second connection piece, connectable to a first electronics system to trigger opening of the switching contact;
a plate-like converter cover, covering the converter housing to the outside and including a second passage opening through which the second connection piece extends and runs to the outside, a side of the plate-like converter cover, facing the protective circuit breaker, including arranged on thereon
a first contact bearing against the second connection piece at the plate-like converter cover in a region of the passage opening,
a second contact, electrically connectable to the first connection piece, and
a third contact, connectable to the first or a second electronics system; and
an electrical connection, via which the third contact is selectively connectable to the first or second contact.

US Pat. No. 10,115,549

ELECTRICAL STORAGE SYSTEM

TOYOTA JIDOSHA KABUSHIKI ...

1. An electrical storage system comprising:an electrical storage device;
a load;
a positive electrode line that connects the electrical storage device to the load;
a negative electrode line that connects the electrical storage device to the load;
a first relay provided in the positive electrode line;
a second relay provided in the negative electrode line;
a third relay connected in series with a first resistive element, the third relay and the first resistive element being connected in parallel with the first relay, the first resistive element being provided in the positive electrode line;
a drive circuit including a coil, a first power line, a second power line, and a sensor,
the coil being configured to generate electromagnetic force for switching the second relay and the third relay from a non-energized state to an energized state by energization at a first current value, the coil being configured to generate electromagnetic force for switching the first relay, the second relay and the third relay from a non-energized state to an energized state by energization at a second current value larger than the first current value, the energized state being on state, the non-energized state being off state,
the first power line including a first switch element and a second switch element connected in series with each other, the first power line being configured to supply current having the second current value from a power supply to the coil,
the second power line including a second resistive element and a third switch element connected in series with each other, the second power line being configured to supply current having the first current value from the power supply to the coil, and
the sensor being configured to change an output signal on the basis of whether each switch element is in the energized state or the non-energized state,
the drive circuit being configured to cause both the second and third relays and the first relay to operate at different timings; and
a controller configured to:
(a) control operation of the drive circuit,
(b) output a control signal for setting each switch element to the non-energized state, and
(c) determine whether any one of the switch elements has a failure in the energized state on the basis of the output signal of the sensor.

US Pat. No. 10,115,548

GAS CIRCUIT BREAKER

MITSUBISHI ELECTRIC CORPO...

1. A gas circuit breaker comprising:a rod-shaped fixed arc contact;
a cylindrical movable arc contact to contact or be separated from the fixed arc contact, the movable arc contact having a plurality of contact pieces on a side of the fixed arc contact, the contact pieces being separated from one another by a plurality of slits arranged in a circumferential direction of the movable arc contact and extending in an axial direction of the movable arc contact, each of the contact pieces having a proximal part and a distal end part larger in thickness than the proximal part, the distal end part of each contact piece including a bend having opposed walls extending in the axial direction of the movable arc contact, the distal end parts of the plurality of contact pieces having receiving holes, each of the receiving holes being defined between the opposed walls of a corresponding one of the distal end parts;
a puffer chamber storing an arc-extinguishing gas to be blown to an arc generated between the fixed arc contact and the movable arc contact; and
an insulator received within the receiving holes, the receiving holes being open to an opposite side to a side of the fixed arc contact, a portion of an end surface of the insulator on the side of the fixed arc contact facing the side of the fixed arc contact via opening ends of the slits on the side of the fixed arc contact, the end surface on the side of the fixed arc contact being disposed on the opposite side to the side of the fixed arc contact and farther from the side of the fixed arc contact than the opening ends are, the insulator being made of an ablation material to be vaporized by heat of the arc.

US Pat. No. 10,115,546

ELECTRICAL TRIPOUT DEVICE INTEGRATING A CIRCUIT BREAKER AND AN ISOLATOR

GENERAL ELECTRIC TECHNOLO...

1. A current-interrupter device (1) comprising a circuit breaker (2) including a first stationary conductive support (4) carrying both a stationary arcing contact (14) and a movable arcing contact (16) that is movable between a closed position and an open position, and also carrying a movable permanent contact (17) that is movable between a closed position and an open position, the movable arcing contact (16) and the movable permanent contact (17) being dynamically linked together by forming a single movable unit and being electrically connected to the first stationary conductive support (4), and a disconnector (3) including a second stationary conductive support (6) carrying a disconnector contact (18) that is movable between a closed position and an open position, and wherein:the movable disconnector contact (18) is electrically connected with the stationary arcing contact (14) when the movable disconnector contact (18) is in its closed position;
the movable disconnector contact (18) is spaced apart from the stationary arcing contact (14) when the movable disconnector contact (18) is in its open position;
the movable disconnector contact (18) and the movable permanent contact (17) are electrically connected to each other when they are both in their respective closed positions;
the movable disconnector contact (18) and the movable permanent contact (17) are spaced apart from one another when the movable disconnector contact (18) is in its open position; and
the movable disconnector contact (18) and the movable permanent contact (17) are spaced apart from one another when the movable permanent contact (17) is in its open position.

US Pat. No. 10,115,544

SINGULATED KEYBOARD ASSEMBLIES AND METHODS FOR ASSEMBLING A KEYBOARD

APPLE INC., Cupertino, C...

1. A row of interconnected key assemblies comprising:an array of key assemblies, each key assembly comprising:
a chassis having a first retaining feature and a second retaining feature;
a switch housing formed on the chassis;
a key mechanism surrounding the switch housing and engaged with the first retaining feature; and
a buckling dome positioned within an opening defined through the switch housing and engaged with the second retaining feature.

US Pat. No. 10,115,543

KEYBOARD COVER AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A keyboard cover, comprising:a first sheet material having a surface including a plurality of key tops configured of roughened convex surfaces and a base configured of a smooth surface connecting a plurality of the key tops, a plurality of the key tops being projected from the base viewed from the surface; and
a second sheet of porous material covering a rear surface of the first sheet material and having concave parts corresponding to a plurality of the key tops viewed from the rear surface;
wherein the first sheet material includes:
a surface layer composed of a synthetic resin material forming the surface, and
an intermediate layer disposed between the surface layer and the second sheet material and composed of a thermoplastic resin material;
wherein a plurality of the key tops in the first sheet material includes at least one groove disposed along a diagonal line in a plane of the key tops.

US Pat. No. 10,115,539

LUMINATED KEY STRUCTURE AND ELECTRONIC DEVICE WITH THE SAME

Chiun Mai Communication S...

1. A key structure comprising:a substrate having at least one light emitting element disposed on a substrate surface thereof;
a light guiding element being made of optical transmission material and disposed opposite to the substrate; wherein the light guiding element comprises a main body and a light guiding portion, and the main body comprises a first surface and a second surface opposite to the first surface, wherein the light guiding portion projects from the first surface, and the light guiding portion and the first surface cooperatively form a receiving space;
a key body being mad of opaque material and received in the receiving space;
a first reflective film being disposed on the second surface;
a second reflective film being disposed on the substrate surface of the substrate;
wherein when light is emitted from the at least one light emitting element, the light is reflected between the first reflective film and the second reflective film, transmitted to the light guiding portion, and transmitted out of the key structure through the light guiding portion.

US Pat. No. 10,115,537

APPARATUS FOR DETECTING A SWITCH POSITION

Robert Bosch GmbH, Stutt...

1. An apparatus for detecting a configuration of a switch comprising:a first circuit node and a second circuit node configured to connect the apparatus to an AC electric voltage;
a switch connected between the first circuit node and a third circuit node;
a resistor connected between the first circuit node and the third circuit node in parallel with the switch;
a calculation device connected between the second circuit node and a microcomputer device, the calculation device further comprising at least one transistor or filter stage configured to generate digitized values of the AC electric voltage for detection by the microcomputer device; and
the microcomputer device operatively connected to the calculation device and configured to identify the configuration of the switch, the microcomputer device being operatively configured to:
measure a first amplitude of a positive half-cycle of the AC electric voltage during at least one full cycle of the AC electric voltage based on the digitized values generated by the calculation device;
measure a second amplitude of a negative half-cycle of the AC electric voltage during the at least one full cycle of the AC electric voltage based on the digitized values generated by the calculation device;
detect that the switch is open in response to an asymmetry between the first amplitude and the second amplitude of the AC electric voltage; and
detect that the switch is closed in response to a symmetry between the first amplitude and the second amplitude of the AC electric voltage.

US Pat. No. 10,115,536

ELECTROMAGNETIC ACTUATOR AND ELECTRICAL CONTACTOR COMPRISING SUCH AN ACTUATOR

SCHNEIDER ELECTRIC INDUST...

1. An electromagnetic actuator for operation of an electrical contactor, the actuator comprising:a fixed part including:
at least one coil that generates a magnetic field and that is centered on a longitudinal axis,
at least one core that concentrates the magnetic flux, the core being installed within the coil, and including a spreading plate for the magnetic field which defines an active surface which is perpendicular to the longitudinal axis and at least one magnetic flux return element;
an armature that is moveable in translation along the longitudinal axis with respect to the fixed part, between a first position which is remote from the active surface and a second position which is closer to the surface, in response to a load induced by the magnetic field;
at least one elastic return member that restores the armature to a predetermined position, from among the first position and the second position;
wherein the spreading plate includes at least one rib closing magnetic field lines between the spreading plate and the armature, the rib protrudes with respect to the active surface on the armature side, the rib is arranged at a level of one edge of the spreading plate, and the rib includes braces extending in a direction perpendicular to a longest dimension of the rib.

US Pat. No. 10,115,535

ELECTRIC STORAGE DEVICE

TAIYO YUDEN CO., LTD., T...

1. An electric storage device comprising:an electric storage element having a positive electrode and a negative electrode;
a non-aqueous electrolytic solution that contains a non-aqueous solvent primarily constituted by a non-carbonate cyclic ester and a cyclic carbonate ester, an electrolyte containing lithium salt, and a sulfonate ester derivative whose reduction potential is higher than that of the non-carbonate cyclic ester and that of the cyclic carbonate ester; and
an outer container that stores the electric storage element and non-aqueous electrolytic solution,
wherein a volume ratio of the non-carbonate cyclic ester to the cyclic carbonate ester in the non-aqueous solvent is 1/9 or more but 7/3 or less.

US Pat. No. 10,115,533

RECHARGEABLE POWER SOURCE COMPRISING FLEXIBLE SUPERCAPACITOR

UNIVERSITI PUTRA MALAYSIA...

1. A rechargeable power source for an electronic device, characterized in that, the rechargeable power source comprising:a flexible supercapacitor comprising an electrolyte sandwiched between nickel foams electrodeposited with a nanocomposite, wherein the said nanocomposite comprises a conducting polymer, graphene oxide and a metal oxide; and
a charge connection unit comprising a microcontroller having an electrical connection line connecting an energy collecting unit with the flexible supercapacitor.

US Pat. No. 10,115,526

CAPACITOR, CAPACITOR MOUNTING STRUCTURE, AND TAPED ELECTRONIC COMPONENT SERIES

Murata Manufacturing Co.,...

1. A capacitor comprising:a capacitor main body including a first main surface and a second main surface which extend along a longitudinal direction and a width direction, a first side surface and a second side surface which extend along the longitudinal direction and a thickness direction, and a first end surface and a second end surface which extend along the width direction and the thickness direction; and
a first inner electrode and a second inner electrode provided in the capacitor main body and opposing each other via a ceramic section; wherein
in the capacitor main body, a dimension along the thickness direction of a first region where the first and second inner electrodes are provided is t1;
in the capacitor main body, a dimension along the thickness direction of a second region that is positioned on a side of the first main surface relative to the first region is t2;
in the capacitor main body, a dimension along the thickness direction of a third region that is positioned on a side of the second main surface relative to the first region is t3;
a condition of t3/t1>about 0.07 is satisfied;
the ceramic section includes BaTiO3 and Mn;
a content of Mn in the ceramic section is less than about 0.2 mol part with respect to BaTiO3 of 100 mol part;
a distance along the width direction from a portion where both of the first and second inner electrodes are provided to the first side surface is w2 and a distance along the width direction from a portion where both of the first and second inner electrodes are provided to the second side surface is w3;
at least one of w2 and w3 is no more than about 70 ?m; and
at least one of w2 and w3 is no less than about 55 ?m.

US Pat. No. 10,115,525

ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a body including a capacitance portion having dielectric layers formed of a dielectric material;
internal electrodes and a cover portion covering at least one surface of the capacitance portion, the cover portion including cover layers formed of a dielectric material, the cover portion including a plurality of first and second cover layers that are stacked alternately; and
an external electrode disposed on the body, the external electrode connected to the internal electrodes,
wherein average diameters of dielectric grains included in the first and second cover layers are different from each other.

US Pat. No. 10,115,523

CERAMIC ELECTRONIC COMPONENT AND MOUNTING STRUCTURE OF THE SAME

Murata Manufacturing Co.,...

1. A ceramic electronic component comprising:a multilayer body with a rectangular parallelepiped or rectangular parallelepiped shape and including a plurality of ceramic layers, a plurality of first inner electrode layers, and a plurality of second inner electrode layers, the multilayer body including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction orthogonal or substantially orthogonal to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction orthogonal or substantially orthogonal to the lamination direction and the width direction;
a first outer electrode electrically connected to the plurality of first inner electrode layers and located on at least the first end surface of the multilayer body, and a second outer electrode electrically connected to the plurality of second inner electrode layers and located on at least the second end surface of the multilayer body;
a first substrate connection terminal bonded to at least one of the first outer electrode and the multilayer body by a bonding material that electrically insulates the first substrate connection terminal from the first outer electrode, and a second substrate connection terminal bonded to at least one of the second outer electrode and the multilayer body by a bonding material that electrically insulates the second substrate connection terminal from the second outer electrode; and
a first metal terminal electrically connecting the first outer electrode and the first substrate connection terminal, and a second metal terminal electrically connecting the second outer electrode and the second substrate connection terminal; wherein
while the first metal terminal maintains an elastically deformed state, a first end portion of the first metal terminal is bonded to the first outer electrode by an electrically conductive bonding material and a second end portion of the first metal terminal is bonded to the first substrate connection terminal by a bonding section with a different melting point from a melting point of the electrically conductive bonding material; and
while the second metal terminal maintains an elastically deformed state, a first end portion of the second metal terminal is bonded to the second outer electrode by an electrically conductive bonding material and a second end portion of the second metal terminal is bonded to the second substrate connection terminal by a bonding section with a different melting point from a melting point of the electrically conductive bonding material.

US Pat. No. 10,115,522

MULTI-LAYERED DIELECTRIC POLYMER MATERIAL, CAPACITOR, USE OF THE MATERIAL AND FORMATION METHOD THEREOF

ABB Schweiz AG, Baden (C...

1. A multi-layered dielectric polymer material comprising a plurality of dielectric layers, wherein the plurality of dielectric layers comprises an identical base material, and further wherein the base material is compounded with different nucleating agents respectively for at least two of the plurality of dielectric layers.

US Pat. No. 10,115,521

MANUFACTURING METHOD FOR ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. A manufacturing method for an electronic component including a multilayer body formed by laminating an insulator substrate and an insulator layer, a coil including a coil conductor provided on the insulator substrate, and an internal magnetic path penetrating the insulator substrate, the method comprising:forming the coil conductor and a sacrificial conductor provided at a portion where an internal magnetic path of the insulator substrate is to be formed, at the same time on the insulator substrate;
laminating the insulator layer on the insulator substrate so as to cover the coil conductor and the sacrificial conductor; and
exposing the sacrificial conductor by removing part of the insulator layer laminated on the insulator substrate using a polishing process.

US Pat. No. 10,115,519

ELECTRONIC COMPONENT

Murata Manufacturing Co.,...

1. An electronic component comprising:a multilayer body constituted by insulator layers that are laminated in a laminating direction;
a primary coil including n primary coil conductor layers and a parallel primary coil conductor layer each disposed on one of the insulator layer, n being a natural number;
a secondary coil including n secondary coil conductor layers each disposed on one of the insulator layers; and
a tertiary coil including n tertiary coil conductor layers each disposed on one of the insulator layers,
wherein current paths of the primary coil, the secondary coil, and the tertiary coil are substantially equal to one another in length,
the primary coil, the secondary coil, and the tertiary coil constitute a common mode filter,
respective ones of the primary coil conductor layers, the secondary coil conductor layers, and the tertiary coil conductor layers, are arrayed in a mentioned order from one side toward other side in the laminating direction and constitute a coil conductor layer group,
n coil conductor layer groups are arrayed from the one side toward the other side in the laminating direction, and
the parallel primary coil conductor layer is electrically connected to a predetermined primary coil conductor layer in parallel, has a substantially same shape as the predetermined primary coil conductor layer in a plan view which is a one viewed from the laminating direction, and is disposed on the other side in the laminating direction relative to a predetermined tertiary coil conductor layer which is the tertiary coil conductor layer disposed at a farthest position on the other side in the laminating direction.

US Pat. No. 10,115,518

COIL ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component comprising:a substrate;
a coil pattern disposed on at least one of first and second main surfaces of the substrate;
an insulating part disposed on a surface of the coil pattern to prevent short circuits between adjacent patterns in the coil pattern;
a body region filling at least a core region of the coil pattern and having a magnetic material; and
a magnetic flux controlling part coated on a surface of the insulating part and having a material having a saturation magnetic flux density higher than that of a magnetic material contained in the body region,
wherein a content of Fe contained in the magnetic flux controlling part is greater than a content of Fe contained in the body region.

US Pat. No. 10,115,517

COIL ARRANGEMENT FOR GENERATING A ROTATING ELECTROMAGNETIC FIELD AND POSITIONING SYSTEM FOR DETERMINING A POSITION OF AN IDENTIFICATION TRANSMITTER

Volkswagen Aktiengesellsc...

1. A coil arrangement for generating a rotating electromagnetic field, the coil arrangement comprising:at least three coils, each coil having at least one associated coil winding;
a ferromagnetic coil yoke that establishes a magnetic coupling between the at least three coils, and
at least three capacitors, a first capacitor of the at least three capacitors being connected in series to a first coil of the at least three coils, a second capacitor of the at least three capacitors being connected in series to a second coil of the at least three coils and a third capacitor of the at least three capacitors being connected in series to a third coil of the at least three coils,
wherein two or more coil windings, each having a number of windings that may be actuated jointly or separately, are arranged per coil of the at least three coils, and
wherein the coil arrangement further comprises at least three additional capacitors, a first additional capacitor of the at least three additional capacitors being connected in parallel to one of the two or more coil windings of the first coil of the at least three coils, a second additional capacitor of the at least three additional capacitors being connected in parallel to one of the two or more coil windings of the second coil of the at least three coils and a third additional capacitor of the at least three additional capacitors being connected in parallel to one of the two or more coil windings of the third coil of the at least three coils.

US Pat. No. 10,115,512

SWITCHING ARRANGEMENT

TE Connectivity Germany G...

1. A switch assembly comprising:two contacts;
a switch including a contact bridge, a motor connected to the contact bridge, and an armature connected to the contact bridge, the switch having an open position in which the contacts are electrically separated from one another and a closed position in which the contacts are in electrical contact with each other through the contact bridge, the armature having a distal end positioned opposite the contact bridge that is displaced by the motor when the switch transitions from the open to the closed position;
a switch status detector positioned remotely and electrically isolated from the switch, the motor positioned between the contact bridge and the switch status detector; and
a switching device having a switch housing into which the switch and two contacts are positioned, a wall of the switch housing having a signal-permeable wall region, the distal end of the armature is positioned in the switch housing proximate to the signal-permeable wall region and the switch status detector is positioned outside the switch housing proximate to the signal-permeable wall region.

US Pat. No. 10,115,510

COIL FOR A SWITCHING DEVICE WITH A HIGH-FREQUENCY POWER

1. A coil apparatus including a coil former for use in forming an electrical coil comprising several windings, the coil former having a generally conical shape, the coil apparatus comprising:a first, relatively larger end;
a second, relatively smaller end;
a spiral track along the exterior of the coil former, the spiral track configured to accept an electrically conductive wire to thereby form said electrical coil comprising said several windings,
wherein the spiral track across the coil former proximate to the first end has a first diameter and wherein adjacent loops of the spiral track proximate to the first end have a first spacing between said adjacent loops;
wherein the spiral track across the coil former proximate to the second end has a second diameter and wherein adjacent loops of the spiral track proximate to the second end have a second spacing between said adjacent loops of the spiral track proximate to the second end;
wherein the first diameter is larger than the second diameter; and
wherein the first spacing is smaller than the second spacing;
wherein the coil former is adapted to remain within the electrical coil during operation of the electrical coil;
wherein the coil former partly fills an interior cavity of the electrical coil; and
wherein the coil former includes a first cylindrical part, a second cylindrical part, and a conical part disposed between the first cylindrical part and the second cylindrical part.

US Pat. No. 10,115,506

ND—FE—B SINTERED MAGNET AND METHODS FOR MANUFACTURING THE SAME

Beijing Zhong Ke San Huan...

1. A sintered Nd-Fe-B magnet consisting essentially of: rare earth element R, additive element T, iron Fe, and boron B, wherein said magnet comprises a rare-earth rich phase and a main phase of Nd2Fe14B crystalline structure, and wherein the numeric sum of maximum energy product (BH)max in MGOe and intrinsic coercivity Hcj in kOe is no less than 76, i.e., (BH)max(MGOe)+Hcj(kOe)?76,wherein said magnet comprises 28 to 32 wt % rare earth element R, 0-4wt % additive element T, 0.93-1.0 wt % boron B, with the balance of iron Fe, and impurities, wherein R is one or more elements selected from Y, Sc, and fifteen elements of lanthanide series,
wherein T is one or more elements selected from Ti, V, Cr, Mn, Co, Ni, Cu, Zn, Ga, Ge, Al, Zr, Nb, Mo, and Sn,
wherein the average crystalline grain size of said main phase is in a range from 5.0 ?m to 9.1 ?m, and
wherein oxygen content of said magnet is in a range from 1000 to 1625 ppm.

US Pat. No. 10,115,505

CHIP RESISTOR

E I DU PONT DE NEMOURS AN...

1. A method of manufacturing a chip resistor comprising the steps of:(a) applying a conductive paste on an insulating substrate, wherein the conductive paste comprises,
(i) 40 to 80 weight percent (wt. %) of a conductive powder;
(ii) 1 to 14 wt. % of a glass frit,
(iii) 0.01 to 3 wt. % of magnesium oxide (MgO),
(iv) 10 to 55 wt. % of an organic vehicle, and
(v) anorthite (CaAl2Si2O8),
wherein the wt. % is based on weight of the conductive paste;
(b) firing the applied conductive paste to form the front electrodes.

US Pat. No. 10,115,502

INSULATOR AND CONDUCTOR COVER FOR ELECTRICAL DISTRIBUTION SYSTEMS

Eco Electrical Systems, ...

1. A dielectric cover for an insulator and conductor supported by the insulator, the conductor being for carrying a voltage, the insulator being supported by a support structure in an electrical distribution system, the cover comprising:an insulator cover portion configured to cover at least a top portion of the insulator, the insulator cover portion comprising a knob and a ridge extending down from an inside ceiling of the insulator cover portion; and
an arm configured to cover a portion of the conductor extending from the insulator, the arm having a keyhole formed in a ceiling of the arm, the keyhole having a wide portion that fits over the knob in a first position, wherein the keyhole has a narrow portion that restricts vertical movement of the arm in a locked position,
the arm also having a resilient tab that snaps over the ridge in the locked position.

US Pat. No. 10,115,499

CABLE ARRANGEMENT

1. An arrangement of at least two separate twisted-pair cables, comprising a first cable and a second cable which extend adjacently in a substantially parallel manner, and of which each having a stranding group consisting of a twisted conductor pair, wherein the lay length (A, A?, B, B?) of each of the stranding groups varies in the longitudinal direction of the cables, and the lay length (A) of at least one stranding group winding of the stranding group of the first cable differs from the lay length (B) of an adjacent stranding group winding of the stranding group of the second cable by more than 10%, the lay length of the stranding groups varying between a minimum lay length (A) and a maximum lay length (A?), wherein a distance between two adjacent stranding sections of a stranding group with a minimum lay length (A) defines a stranding length (X), wherein the stranding length (X) of a stranding group varies sinusoidally in the longitudinal direction of the cable (L).

US Pat. No. 10,115,494

COMPOSITE BODY, HONEYCOMB STRUCTURAL BODY, AND METHOD FOR MANUFACTURING COMPOSITE BODY

NGK Insulators, Ltd., Na...

1. A honeycomb structural body comprising:a substrate; and
a forming portion formed on the substrate and being composed of a composite phase,
wherein the composite phase is an oxide ceramic containing a perovskite oxide and a metal oxide different from the perovskite oxide, the metal oxide contained in the composite phase being a single metal oxide containing the same metal element as that of the metal element at the B site of the perovskite oxide.

US Pat. No. 10,115,493

SURFACE-MODIFIED CARBON HYBRID PARTICLES, METHODS OF MAKING, AND APPLICATIONS OF THE SAME

1. A method of making surface-modified carbon hybrid particles, the method comprising:milling graphite in a gas-tight sealed mill; and
functionalizing the resulting hybrid carbon by controlled oxidation;
wherein the surface-modified carbon hybrid particles comprise a graphite core coated with amorphous carbon in agglomerate form having a BET surface area of at least 50 m2/g and no greater than 800 m2/g.

US Pat. No. 10,115,492

ELECTRICALLY CONDUCTIVE CARBON NANOTUBE WIRE HAVING A METALLIC COATING AND METHODS OF FORMING SAME

Delphi Technologies, Inc....

1. A multi-strand electrical wire assembly comprising:a plurality of elongate strands consisting essentially of carbon nanotubes having a length of at least 50 millimeters;
a conductive coating covering an outer surface of the plurality of carbon nanotube strands having greater electrical conductivity than the plurality of carbon nanotube strands; and
an electrical terminal attached to an end of the assembly by an attachment means selected from the list consisting of soldering and crimping.

US Pat. No. 10,115,489

EMERGENCY METHOD AND SYSTEM FOR IN-SITU DISPOSAL AND CONTAINMENT OF NUCLEAR MATERIAL AT NUCLEAR POWER FACILITY

Grand Abyss, LLC, Tulsa,...

1. A method for emergency in-situ subsurface isolation of nuclear material at a nuclear power or nuclear storage facility, the method comprising:conveying a mobile radioactive material during an emergency from a source of the radioactive material into a borehole in proximity to, and in flow communication with, the source of the mobile radioactive material and into a prepared first vertical-oriented gravity fracture, the borehole being at a depth suitable for safely isolating the mobile radioactive material, the prepared first vertical-oriented gravity fracture being in a surrounding rock formation located below and in communication with a bottom end of the borehole and available to receive the mobile radioactive material exiting the bottom end of the borehole during the emergency;
wherein the mobile radioactive material passes from the borehole into the prepared first vertical-oriented gravity fracture; and
wherein the mobile radioactive material is not in a containment vessel when entering the borehole;
prior to the conveying, creating the prepared first vertical-oriented gravity fracture by using a slurry containing a weighting material;
wherein the slurry is denser than the surrounding rock formation; and
wherein no mobile radioactive material is in or mixed with the slurry.

US Pat. No. 10,115,488

PASSIVE SAFETY EQUIPMENT FOR A NUCLEAR POWER PLANT

KOREA ATOMIC ENERGY RESEA...

20. A passive safety facility for a nuclear power plant, comprising:a cooling section formed to cool fluid discharged from a nuclear reactor coolant system along with fluid contained within an area between the nuclear reactor coolant system and a containment; and
a circulation inducing jet device configured to receive the fluid discharged from the nuclear reactor coolant system, and formed to jet the received fluid to the cooling section, at least part of which is open toward an inside of the containment to entrain the fluid contained within the area between the nuclear reactor coolant system and the containment by a pressure drop caused while jetting the received fluid so as to jet the entrained fluid along with the received fluid, wherein
the containment is formed to surround the steam generator which is configured to generate steam or the nuclear reactor coolant system which is configured to accommodate the steam generator,
the circulation inducing jet device comprises:
a fluid jetting section connected to the nuclear reactor coolant system to receive the fluid discharged from the nuclear reactor coolant system, and formed to jet the received fluid;
a fluid entraining section formed in an annular shape around the fluid jetting section to entrain the fluid contained within the area between the nuclear reactor coolant system and the containment;
a circulating fluid jetting section configured to surround the fluid jetting section with a portion having an inner diameter larger than that of the fluid jetting section to form the fluid entraining section, and supply the received fluid and the entrained fluid to the cooling section;
a turbine blade rotatably installed at an outlet of the jetting section to induce the jetting of the received fluid; and
a pump impeller connected to the turbine blade to rotate along with the turbine blade, and induce the entrainment of the fluid contained with the area between the nuclear reactor coolant system and the containment through the fluid entraining section.

US Pat. No. 10,115,485

METHOD OF PLANNING AN EXAMINATION, METHOD OF POSITIONING AN EXAMINATION INSTRUMENT, TOMOSYNTHESIS SYSTEM AND COMPUTER PROGRAM PRODUCT

Siemens Healthcare GmbH, ...

1. A method for planning an examination of an examination object by a tomosynthesis machine, the method comprising the following steps:a) capturing raw data of the examination object, the raw data having been acquired from a plurality of defined acquisition angles;
b) reconstructing an auxiliary data set from the raw data;
c) calculating depth data from the auxiliary data set and calculating a number of projections from a perspective of a respectively defined projection center on a basis of the auxiliary data set or on a basis of the raw data, wherein each of the projections contains a number of image points and each of the image points is linked to the depth data associated therewith, and wherein perspectives of the projections are tilted relative to one another at least on a section of a circular path;
d) displaying the projections;
e) enabling at least one projection to be chosen;
f) marking a position of an examination region of the examination object in the at least one projection thus chosen; and
g) calculating a real three-dimensional position of the examination region using the marked position and the depth data thereof.

US Pat. No. 10,115,484

TRACKING MEDICATION INVENTORY USING ONE OR MORE LINKED PRESSURE SENSORS

1. A system for tracking an inventory of medication, the system comprising:one or more medication detecting devices, each of the medication detecting devices including:
a medication container for receiving a first amount of a medication;
a pressure sensor including a pressure sensing portion in sensory contact with the medication portion for measuring a pressure applied by the first amount of medication on the medication portion;
an embedded processor in electronic communication with the pressure sensing component and a sensor communication module;
one or more personal communication devices, the one or more personal communication devices including:
a display,
at least one computer readable storage medium,
a device communication component; and
a processor in communication with the display, the at least one computer readable storage medium, and the device communication module;
a remote database in communication with the one or more medication detecting devices and the one or more personal communication device via the sensor communication module of the one or more medication detecting devices and the device communication module of the personal communication device, the remote database including a processor and one or more computer readable storage mediums;
an interactive user interface displayed on the display of the personal communication device for receiving one or more medication parameters from a user corresponding to a change in pressure detected by the pressure sensing component of each of the one or more medication detecting devices and for displaying information related to the one or more medication detecting devices;
wherein when one of the one or more medication detecting devices detects a pressure change on the pressure sensor, the detected change of pressure is transmitted to the remote database, wherein the remote database processor analyzes the change in pressure from the one or more medication detecting devices and transmits an alert when the detected pressure change corresponds to the medication input parameters inputted by the user.

US Pat. No. 10,115,482

REFLEXIVE EDUCATION: A METHOD FOR AUTOMATED DELIVERY OF EDUCATIONAL MATERIAL LINKED TO OBJECTIVE OR SUBJECTIVE DATA

Koninklijke Philips N.V.,...

1. A health management system comprising:one or more memories at a central location which store a patient profile corresponding to each of a plurality of patients and a plurality of educational content sessions, the educational content sessions being directed toward helping patients achieve a health management goal;
at least one feedback path from each of the patients which provides at least one input; wherein the at least one feedback path includes a biometric device, the at least one input including biometric data, which includes a triggering event, acquired by the biometric device and wirelessly communicated to one or more processors from the biometric device; the one or more processors being at a patient site for each patient and programmed to:
monitor for critical events based on user input and/or biometric data received from the patients;
automatically select a plurality of the content sessions and a flow of the selected educational content sessions for each patient based on the patient profile, the input from the corresponding patient, and on content flow rules, the selected educational content sessions for at least one of the patients including critical event content selected in response to detecting a critical event, and the selected for at least one of the patients including a previously selected educational content session in response to the input from the corresponding patient; and,
communicate the selected educational content sessions into a user interface associated with the corresponding patient;
a display device at each user interface on which the selected educational content sessions are presented to the correspondent patient.

US Pat. No. 10,115,481

READ-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) READ PORT(S), AND RELATED MEMORY SYSTEMS AND METHODS

QUALCOMM Incorporated, S...

1. A memory system, comprising:a memory bit cell, comprising:
a storage circuit configured to store data and comprising:
a positive supply rail;
a negative supply rail; and
one or more inverters each comprising a pull-up P-type Field-Effect Transistor (FET) (PFET) coupled to a pull-down N-type FET (NFET), wherein each pull-up PFET of the one or more inverters is coupled to the positive supply rail, and each pull-down NFET of the one or more inverters is coupled to the negative supply rail; and
one or more PFET access transistors coupled to the storage circuit; and
each of the one or more PFET access transistors comprising a gate configured to be activated by a wordline in response to a read operation to cause the one or more PFET access transistors to pass the data from the storage circuit to a bitline coupled to the memory bit cell;
a bitline driver configured to pre-discharge the bitline coupled to the memory bit cell in response to the read operation; and
a read-assist circuit configured to boost a voltage in the memory bit cell in response to the read operation to assist in transferring the data from the storage circuit to the bitline, the read-assist circuit comprising a positive supply rail positive boost circuit coupled to the positive supply rail of at least one inverter among the one or more inverters, the positive supply rail positive boost circuit configured to positively boost a voltage on the positive supply rail to strengthen the one or more inverters in the storage circuit in response to the read operation.

US Pat. No. 10,115,480

DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (“DDR SDRAM”) DATA STROBE SIGNAL CALIBRATION

QUALCOMM Incorporated, S...

1. A method for controlling memory system calibration, comprising:adjusting a data signal driver circuit to impair impedance matching on a data signal channel during a plurality of system-level memory tests;
performing the plurality of system-level memory tests using a memory controller and a synchronous dynamic random access memory (“SDRAM”), each memory test corresponding to one of a plurality of phase skew values between a data strobe signal and a data signal on the data signal channel, each memory test comprising:
setting a data strobe signal delay for the memory controller to correspond to one of the plurality of phase skew values;
writing a plurality of data words to the SDRAM over the data signal channel;
reading the plurality of data words from the SDRAM over the data signal channel; and
determining an error count for the memory test, the error count indicating data mismatch errors between the plurality of data words read from the SDRAM and the plurality of data words written to the SDRAM;
determining, following the plurality of system-level memory tests, an optimal phase skew value corresponding to a lowest error count among the plurality of system-level memory tests; and
setting the data strobe signal delay for the memory controller to correspond to the optimal phase skew value.

US Pat. No. 10,115,479

MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF VERIFYING REPAIR RESULT OF MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

17. A method of verifying a repair result of a memory device comprising a memory cell array including a normal region having a plurality of memory cells and a redundant region having a plurality of redundant memory cells where the normal region includes a first failed block and the redundant region includes a first redundant block replacing the first failed block and comprising a control circuit including a mapping table storing replacement information regarding the first failed block and the first redundant block, the method comprising:determining whether the normal region further includes a second failed block in a test mode of the memory device;
when the normal region is determined to include the second failed block in the test mode:
writing a first logic value in all the memory cells of the normal region other than memory cells of the first and second failed blocks and in redundant memory cells of the first redundant block;
writing a second logic value different from the first logic value in all the redundant memory cells of the redundant region other than the redundant memory cells of the first redundant block;
adding replacement information regarding the second failed block and a second redundant block in the redundant region to the mapping table, the second redundant block replacing the second failed block; and
verifying a result of replacing the second failed block with the second redundant block based on data read from all of redundant memory cells in the second redundant block.

US Pat. No. 10,115,478

SEMICONDUCTOR MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:a plurality of memory cell arrays each memory cell array including a first region, a second region, and a third region in the second region;
a repair controller suitable for storing a first repair address information, generating a first mode enable signal for accessing the third region by comparing the first repair address information with a row address during a first mode for a repair operation, and disabling the first mode enable signal in response to a refresh command regardless of a result of the comparing the first repair address information with the row address; and
a refresh operation controller suitable for generating a refresh address for performing a refresh operation in response to the refresh command, wherein a first refresh address corresponding to the first region and the second region is generated in response to the refresh command, and a second refresh address corresponding to the third region is generated in response to the first refresh address.

US Pat. No. 10,115,476

ADVANCED PROGRAMMING VERIFICATION SCHEMES FOR MEMORY CELLS

Apple Inc., Cupertino, C...

1. An apparatus, comprising:a plurality of blocks, wherein each block of the plurality of blocks includes a plurality of data storage cells;
circuitry configured to:
measure respective durations of one or more write commands associated with storing data in one or more data storage cells of the plurality of data storage cells in a particular block of the plurality of blocks;
compare the respective durations of the one or more write commands to a predefined duration range; and
identify the particular block as bad in response to a determination that the respective durations of the one or more write commands deviate from the predefined duration range.

US Pat. No. 10,115,475

COMPENSATION CIRCUIT FOR COMPENSATING FOR AN INPUT CHARGE IN A SAMPLE AND HOLD CIRCUIT

NXP USA, Inc., Austin, T...

1. A compensation circuit for compensating for an input charge at a first input of a sample and hold circuit, the input charge for charging a first input capacitor of the sample and hold circuit during sampling an analogue input voltage signal, the compensation circuit comprising:a first buffer having a first buffer input for electrically coupling to the first input of the sample and hold circuit, and a first buffer output;
a first compensation capacitor comprising
a first compensation terminal switchable between the first buffer input and the first buffer output, and
a second compensation terminal switchable between the first buffer output and a reference terminal; and
a control circuit configured to
switch the first compensation terminal to the first buffer output and the second compensation terminal to the reference terminal when the sample and hold circuit is configured for sampling the analogue input voltage signal, for storing a compensation charge into the first compensation capacitor, wherein the compensation charge is substantially equal to the input charge, and
switch the first compensation terminal to the first buffer input and the second compensation terminal to the first buffer output when the sample and hold circuit is configured for holding the analogue input voltage signal, for discharging the first compensation capacitor of the stored compensation charge into the first input of the sample and hold circuit.

US Pat. No. 10,115,474

ELECTRONIC DEVICE WITH A FUSE READ MECHANISM

Micron Technology, Inc., ...

1. A method of operating an electronic device, comprising:precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information,
wherein precharging the fuse read node includes precharging the fuse read node with an intermediate precharging device configured to provide the intermediate voltage instead of a transistor configured to connect the fuse read node to a source providing the input voltage;
connecting the fuse cell to the fuse read node for reading the information; and
determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.

US Pat. No. 10,115,472

REDUCING READ DISTURB EFFECT ON PARTIALLY PROGRAMMED BLOCKS OF NON-VOLATILE MEMORY

International Business Ma...

1. A method in a data storage system including a non-volatile memory array controlled by a controller, the method comprising:in response to receipt of write data to be written to the non-volatile memory array, the controller determining whether a read count of an unfinalized candidate block of storage within the non-volatile memory array satisfies a read count threshold applicable to the unfinalized candidate block; and
in response to determining that the read count of the unfinalized candidate block satisfies the read count threshold, the controller finalizing programming of the unfinalized candidate block and programming an alternative block with the write data, wherein programming the alternative block includes programming a physical page in the alternative block with a data page forming part of a page stripe spanning multiple blocks.

US Pat. No. 10,115,471

STORAGE SYSTEM AND METHOD FOR HANDLING OVERHEATING OF THE STORAGE SYSTEM

Western Digital Technolog...

1. A method for handling overheating of a storage system, the method comprising:performing the following in a storage system comprising a memory, a temperature sensor, a power supply, and a controller, wherein the controller comprises transistors:
executing first computer-readable program code by the controller to:
determine whether a temperature sensed by the temperature sensor is above a first threshold temperature by comparing the temperature sensed by the temperature sensor to the first threshold temperature; and
in response to determining that the temperature sensed by the temperature sensor is above the first threshold temperature, perform a thermal throttling operation to reduce a number of memory operations performed in the memory; and
executing second computer-readable program code by the controller to:
determine whether the thermal throttling operation was successful in lowering the temperature below the first threshold temperature by comparing a temperature sensed by the temperature sensor after performing the thermal throttling operation to the first threshold temperature; and
in response to determining that the thermal throttling operation was unsuccessful in lowering the temperature below the first threshold temperature, lower a voltage supplied by the power supply to the controller, wherein lowering the voltage supplied to the controller reduces temperature by reducing leakage current of the transistors in the controller.

US Pat. No. 10,115,469

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A nonvolatile memory, comprising:a bit line coupled to a first diffusion layer and a switch MOS transistor;
a source line coupled to a second diffusion layer;
a memory gate line coupled to a memory gate electrode;
a control gate line coupled to a control gate electrode;
a first driver which drives the control gate line;
a second driver which drives the memory gate line;
a third driver which drives the switch MOS transistor; and
a fourth driver which drives the source line;
wherein the second and the fourth drivers include MOS transistors whose gate withstand voltages are higher than those of MOS transistors included in the first and the third drivers.

US Pat. No. 10,115,467

ONE TIME ACCESSIBLE (OTA) NON-VOLATILE MEMORY

Jonker LLC, Zephyr Cove,...

1. A method of operating a floating gate based non-volatile memory cell device that operates to store a logic state based on a value of a charge physically present on the floating gate in a memory cell, such that a first amount of charge represents a first logical value, and a second amount of charge represents a second logical value, the improvement comprising:a hybrid read operation that when effectuated:
i. reads the stored memory cell logic state during a first phase;
and
ii. erases the stored memory cell logic state during an immediately subsequent second phase;
iii. senses said stored memory cell logical state by at least one of: 1) integrating a total charge flowing through the device during at least a portion of time of said hybrid read operation; and/or 2) detecting a change in current as a function of at least a portion of time of said hybrid read operation for said memory device;
wherein a threshold voltage of the floating gate based memory cell device is caused to increase during an entirety of said hybrid read operation;
further wherein a stored logic state of the non-volatile memory cell device can be read at most once before it is erased.

US Pat. No. 10,115,466

NONVOLATILE MEMORY SYSTEM THAT ERASES MEMORY CELLS WHEN CHANGING THEIR MODE OF OPERATION

Samsung Electronics Co., ...

1. A method of operating a memory system including a plurality of memory cells, the method comprising:changing an operation mode of first memory cells, among the plurality of memory cells, that operate based on a first operation mode to operate based on a second operation mode;
performing a pre-program operation on the first memory cells in response to changing the operation mode; and
performing a change erase operation on the pre-programmed first memory cells based on a change erase condition, wherein:
in the first operation mode, a first normal erase operation on the first memory cells is performed based on a first erase condition,
in the second operation mode, a second normal erase operation on the first memory cells is performed based on a second erase condition, which differs from the first erase condition,
the change erase condition is different from the first erase condition or the second erase condition, and
the change erase operation differs from each of the first and second normal erase operations and the first normal erase operation differs from the second normal erase operation.

US Pat. No. 10,115,465

FUNCTIONAL DATA PROGRAMMING IN A NON-VOLATILE MEMORY

Micron Technology, Inc., ...

1. A method of operating a memory, comprising:receiving a plurality of digits of data;
determining a value of the plurality of digits of data;
selecting a function to represent the value of the plurality of digits of data, wherein the selected function is a non-binary mathematical function of a cell number of each memory cell within a grouping of memory cells;
determining a desired threshold voltage of each memory cell of the grouping of memory cells in response to the selected function, wherein the desired threshold voltage of a particular memory cell of the grouping of memory cells corresponds to the value of the selected function for the cell number of the particular memory cell; and
programming the particular memory cell to its desired threshold voltage.

US Pat. No. 10,115,464

ELECTRIC FIELD TO REDUCE SELECT GATE THRESHOLD VOLTAGE SHIFT

SanDisk Technologies LLC,...

1. An apparatus, comprising:a NAND string comprising non-volatile memory cells;
a string select line;
a plurality of word lines connected to control gates of the non-volatile memory cells; and
a control circuit in communication with the NAND string, the string select line, and the plurality of word lines, the control circuit configured to:
apply a read pass voltage to a word line adjacent to the string select line;
decrease the read pass voltage on the adjacent word line to a steady state voltage after a selected memory cell on the NAND string is sensed;
increase a voltage on the string select line after the voltage on the adjacent word line is decreased to the steady state voltage; and
float the string select line and the adjacent word line after the voltage on the string select line is increased.

US Pat. No. 10,115,463

VERIFICATION OF A RAM-BASED TCAM

XILINX, INC., San Jose, ...

1. An integrated circuit (IC), comprising:a memory including at least one random access memory (RAM); and
a verification circuit, coupled to the memory, including a W-bit address bus and an N-bit data bus coupled to each of the at least one RAM, a counter coupled to the address bus and operable to generate a W-bit address signal, a register coupled to the address bus and operable to store a W-bit address value, a multiplexer coupled to the data bus and operable to output a selected bit of the data bus, and circuitry configured to decode or check bits stored in the memory based on output of the register and output of the multiplexer.

US Pat. No. 10,115,459

MULTIPLE LINER INTERCONNECTS FOR THREE DIMENSIONAL MEMORY DEVICES AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A structure comprising an electrically conductive structure embedded within at least one dielectric material layer, wherein the electrically conductive structure comprises:a metal portion consisting essentially of an elemental metal or an intermetallic alloy of at least two elemental metals;
a first metallic liner comprising a first metallic material and contacting a bottom surface of the metal portion and at least lower portions of sidewalls of the metal portion; and
a second metallic liner comprising a second metallic material and contacting a top surface of the metal portion,wherein:the first metallic material and the second metallic material differ in composition; and
the first metallic liner and the second metallic liner contact an entirety of all surfaces of the metal portion; andwherein the structure comprises at least one feature selected from:a first feature that the metal portion comprises copper and the second metallic liner consists essentially of aluminum;
a second feature that the metal portion comprises copper and the second metallic liner comprises a material selected from cobalt, cobalt-tungsten and cobalt-tungsten-phosphorus;
a third feature that the first metallic liner comprises a material selected from a conductive metallic nitride and an elemental transition metal;
a fourth feature that the metal portion comprises copper, the first metallic liner comprises titanium and the second metallic liner comprises aluminum; or
the fifth feature that the at least one dielectric material layer comprises an air-gap dielectric layer including at least one cavity filled with vacuum or a gas phase material.

US Pat. No. 10,115,458

PERFORM READ OR WRITE ON A NON-VOLATILE MEMORY HAVING A PENDING READ OR WRITE BASED ON TEMPERATURE THEREOF

Toshiba Memory Corporatio...

1. A memory system comprising:a plurality of non-volatile memories;
one or more temperature sensors each of which is disposed in or adjacent to one of the non-volatile memories; and
a controller for the plurality of non-volatile memories, that is configured to
maintain a temperature increase amount and a reference temperature for each of the non-volatile memories,
select one of the non-volatile memories having a pending command as a next memory to be accessed based on a current temperature, the temperature increase amount, and the reference temperature of the selected non-volatile memory,
access the selected non-volatile memory to perform the pending command, and
with respect to the selected non-volatile memory, update the maintained temperature increase amount based on a difference of the current temperature of the selected non-volatile memory before the selected non-volatile memory is accessed and a temperature of the selected non-volatile memory after the selected non-volatile memory is accessed.

US Pat. No. 10,115,457

THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION BY SENSING COMMON SOURCE LINE CURRENTS

Micron Technology, Inc., ...

1. A method for threshold voltage distribution determination, comprising:applying a first sensing voltage to a selected access line to which a group of memory cells is coupled;
determining a first current on a source line to which the group of memory cells is commonly coupled, the first current corresponding to a first quantity of memory cells of the group that conduct in response to the applied first sensing voltage;
applying a second sensing voltage to the selected access line;
determining a second current on the source line, the second current corresponding to a second quantity of cells of the group that conduct in response to the applied second sensing voltage; and
determining at least a portion of a threshold voltage distribution corresponding to the group of memory cells based, at least in part, on a difference between the first current and the second current.

US Pat. No. 10,115,456

MULTI-STATES NONVOLATILE OPTO-FERROELECTRIC MEMORY MATERIAL AND PROCESS FOR PREPARING THE SAME THEREOF

1. Multi-states nonvolatile opto-ferroelectric memory element comprising:an opto-ferroelectric memory material comprised of:
Pb1-x(Bi0.5Li0.5)x(Ti1-yZry)O3
wherein
x=0.2 to 0.8
y=0.2 to 0.6
said memory material (PBLZT) photovoltaic ferroelectric material includes a single-phase opto-ferroelectric materials, photovoltaic and multi-states ferroelectric memory material.

US Pat. No. 10,115,455

SEMICONDUCTOR DEVICES, CIRCUITS AND METHODS FOR READ AND/OR WRITE ASSIST OF AN SRAM CIRCUIT PORTION BASED ON VOLTAGE DETECTION AND/OR TEMPERATURE DETECTION CIRCUITS

1. A method of operating a semiconductor device that is powered by a first power supply potential, comprising:determining in which of a plurality of voltage windows the first power supply potential is located;
changing at least one voltage window signal when the first power supply potential moves from one voltage window into another of the voltage windows;
detecting a change in the at least one voltage window signal; and
generating at least one read assist signal having a predetermined logic level in response to the at least one voltage window signal; and
altering a read operation to a static random access memory (SRAM) cell in response to the at least one read assist signal having the predetermined logic level.

US Pat. No. 10,115,454

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a memory array which includes a plurality of memory cells arranged in a matrix;
word lines which are provided and correspond respectively to rows of the memory array;
word line drivers which are coupled to ends of the word lines, and activate the word lines by coupling the one ends of the word lines to a first power source, when a corresponding row is selected; and
assist drivers which are coupled to other ends of the word lines, and couple the other ends of the word lines to the first power source in accordance with a voltage of the other ends of the word lines,
wherein each of the assist drivers receives a control signal pulse, and
wherein the control signal pulse is transmitted to the assist drivers through a signal wiring.

US Pat. No. 10,115,452

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a substrate;
a circuit having a transistor formed on the substrate;
an oscillation circuit generating a frequency signal;
a substrate voltage generation circuit generating a substrate voltage in accordance with the frequency signal from the oscillation circuit; and
a control circuit varying a frequency of the frequency signal from the oscillation circuit during a stand-by period of the circuit,
wherein the stand-by period of the circuit includes a stand-by transition period in which transition from an active state to a stand-by state of the circuit is made and a stand-by stable period in which the stand-by state is maintained,
wherein the control circuit sets a frequency of the frequency signal from the oscillation circuit differently between the stand-by transition period and the stand-by stable period, and
wherein the control circuit sets a frequency of the frequency signal from the oscillation circuit during the stand-by transition period to be higher than a frequency of the frequency signal from the oscillation circuit during the stand-by stable period.

US Pat. No. 10,115,451

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. A method of operating an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell;
a first region in electrical contact with said floating body region, located at a surface of said floating body region;
a second region in electrical contact with said floating body region, located at a surface of said floating body region, spaced apart from said first region;
a gate positioned between said first region and said second region; and
a third region in electrical contact with said floating body region, located below said floating body region;
said method comprising:
selecting said third region of at least one of said semiconductor memory cells in at least one of said at least two memory sub-arrays; and
operating said at least one of said memory sub-arrays independently of operation of a remainder of said at least two memory sub-arrays not selected.

US Pat. No. 10,115,450

CASCODE COMPLIMENTARY DUAL LEVEL SHIFTER

International Business Ma...

1. A level shifter comprising:a first circuit section,
a second circuit section in parallel with the first circuit section, and
an inverter between the first circuit section and the second circuit section, wherein the first circuit section comprises:
a first p-channel field effect transistor (FET), a second p-channel FET, a first n-channel FET, and a second n-channel FET connected to each other in series;
a third n-channel FET, a drain of the third n-channel FET being connected to a first connection point at which a drain of the first p-channel FET and a source of the second p-channel FET are connected to each other, a source of the third n-channel FET being connected to a gate of the second p-channel FET;
a third p-channel FET, a gate of the third p-channel FET being connected to a second connection point at which the source of the third n-channel FET and the gate of the second p-channel FET are connected to each other, a drain of the third p-channel FET being connected to a third connection point at which a drain of the second p-channel FET and a drain of the first n-channel FET are connected to each other;
a fourth p-channel FET, a source of the fourth p-channel FET being connected to a gate of the first n-channel FET, a drain of the fourth p-channel FET being connected to a fourth connection point at which a source of the first n-channel FET and a drain of the second n-channel FET are connected to each other; and
a first condenser, ends of the first condenser being respectively connected to a fifth connection point at which the drain of the first p-channel FET and the source of the second p-channel FET are connected to each other, and a sixth connection point at which the source of the first n-channel FET and the drain of the second n-channel FET are connected to each other;
wherein the second circuit section comprises:
a fifth p-channel FET, a sixth p-channel FET, a fourth n-channel FET, and a fifth n-channel FET connected in series, a gate of the fifth p-channel FET being connected to the drain of the first p-channel FET, a drain of the fifth p-channel FET being connected to a gate of the first p-channel FET, a gate of the sixth p-channel FET being connected to the gate of the second p-channel FET, a gate of the fourth n-channel FET being connected to the gate of the first n-channel FET;
a sixth n-channel FET, a drain of the sixth n-channel FET being connected to a seventh connection point at which the drain of the fifth p-channel FET and a source of the sixth p-channel FET are connected to each other, a source of the sixth n-channel FET being connected to the gate of the sixth p-channel FET;
a seventh p-channel FET, a gate of the seventh p-channel FET being connected to an eighth connection point at which the source of the sixth n-channel FET and the gate of the sixth p-channel FET are connected to each other, a drain of the seventh p-channel FET being connected to a ninth connection point at which a drain of the sixth p-channel FET and a drain of the fourth n-channel FET are connected to each other;
an eighth p-channel FET, a source of the eighth p-channel FET being connected to the gate of the fourth n-channel FET, a drain of the eighth p-channel FET being connected to a tenth connection point at which a source of the fourth n-channel FET and a drain of the fifth n-channel FET are connected to each other; and
a second condenser, ends of the second condenser being respectively connected to an eleventh connection point at which the drain of the fifth p-channel FET and the source of the sixth p-channel FET are connected to each other, and a twelfth connection point at which the source of the fourth n-channel FET and the drain of the fifth n-channel FET are connected to each other;
an inverter input terminal of the inverter is connected to a gate of the fourth p-channel FET and a gate of the second n-channel FET;
an inverter output terminal of the inverter is connected to a gate of the eighth p-channel FET and a gate of the fifth n-channel FET;
the seventh connection point constitutes a first output terminal;
the tenth connection point constitutes a second output terminal;
a first voltage is applied to a source of the first p-channel FET and a source of the fifth p-channel FET; and
a second voltage being lower than the first voltage is applied to a source of the second n-channel FET and a source of the fifth n-channel FET, the first voltage or a third voltage being lower than the first voltage and higher than the second voltage is outputted from the first output terminal, the second voltage or a fourth voltage being lower than the first voltage and higher than the third voltage is outputted from the second output terminal.

US Pat. No. 10,115,449

FREQUENCY SYNTHESIS FOR MEMORY INPUT-OUTPUT OPERATIONS

1. An apparatus comprising:a memory array;
a plurality of input/output (I/O) lanes, wherein each of the plurality of I/O lanes is coupled to the memory array and configured to receive a data signal, wherein the data signal received by each of the plurality of I/O lanes comprises timing information and data information, and wherein the data information comprises data to be written into the memory array; and
a plurality of first clock circuits each separate from one another, wherein each of the plurality of first clock circuits is coupled to an associated one of the plurality of I/O lanes, wherein each of the first clock circuits is configured to generate a first internal clock signal based, at least in part, on the timing information of the data signal received by an associated one of the plurality of I/O lanes and to provide the first internal clock signal to the associated one of the plurality of I/O lanes.

US Pat. No. 10,115,448

MEMORY DEVICE FOR REFRESH AND MEMORY SYSTEM INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a memory bank including a plurality of memory blocks, each memory block including a plurality of memory cells arranged in rows and columns;
a row selection circuit configured to select one or more rows such that the memory device performs an access operation and a refresh operation with respect to the memory bank in response to an active command received from a memory controller; and
a refresh controller configured to control the row selection circuit such that the memory device is operated selectively in an access mode in response to the active command or a self-refresh mode in response to a self-refresh command received from the memory controller, and the refresh controller configured to, when entering the self-refresh mode, control the row selection circuit such that the refresh operation is performed first by a burst number in response to a first clock signal having a first clock period, and then in response to a second clock signal having a second clock period longer than the first clock period,
wherein the refresh operation is performed in the access mode in response to the active command,
wherein the refresh operation is performed in the self-refresh mode in response to at least one clock signal, and
wherein the refresh controller includes:
a pull-in counter configured to store a count value changing between a minimum count value and a maximum count value such that the count value is increased whenever the refresh operation for one row of the memory bank is completed and the count value is decreased whenever an average refresh interval time elapses.

US Pat. No. 10,115,444

DATA BIT INVERSION TRACKING IN CACHE MEMORY TO REDUCE DATA BITS WRITTEN FOR WRITE OPERATIONS

QUALCOMM Incorporated, S...

1. A cache memory, comprising:a cache array comprising one or more cache entries, each comprising a cache data field and a bit change track field; and
a cache controller configured to write data in the one or more cache entries of the cache array;
the cache controller configured to:
receive a write request comprising a memory address and a write data word;
generate a bit change track word in the bit change track field in a cache entry among the one or more cache entries in the cache array corresponding to the memory address of the write request, the bit change track word indicating a bit inversion state based on bit inversions determined by a comparison between the write data word and a current cache data word stored in the cache data field in the cache entry;
determine if the write data word is to be stored in an inverted form based on the bit inversion state; and
responsive to determining that the write data word is to be stored in the inverted form, cause the write data word to be stored in association with the memory address of the write request in the inverted form.

US Pat. No. 10,115,443

TECHNIQUES TO IMPROVE SWITCHING PROBABILITY AND SWITCHING SPEED IN SOT DEVICES

National University of Si...

1. A method for switching a magnetization direction of a ferromagnet (FM) layer of a spin orbit torque (SOT) device, comprising:applying an in-plane assist field; and
applying one or more in-plane input current pulses each having a tuned pulse width or a pulse width selected to be within a range of tuned pulse widths, and an intensity, to switch the magnetization direction of the FM layer,
wherein the tuned pulse width or range of tuned pulse widths are selected to avoid a specific pulse width that causes switch-back of the magnetization direction of the FM layer of the SOT device.

US Pat. No. 10,115,442

DEMAND-BASED PROVISIONING OF VOLATILE MEMORY FOR USE AS NON-VOLATILE MEMORY

Microsoft Technology Lice...

1. A computing device comprising:one or more volatile memories logically partitioned into a plurality of pages;
a firmware of the computing device;
one or more processors that cause the computing device to at least:
provide, by the firmware, information indicative of a first subset of the plurality of pages of volatile memory, the first subset comprising one or more pages of volatile memory identified by the firmware as non-volatile storage;
receive, by the firmware, an indication of demand for additional non-volatile storage on the computing device;
update, by the firmware and based at least in part on the received indication, data indicative of pages of memory identified as non-volatile storage to include a second subset of the plurality of pages in addition to the first subset of the plurality of pages; and
provide, by the firmware, information indicative of updates to the data indicative of pages of memory identified as non-volatile storage.

US Pat. No. 10,115,441

ROW DECODER AND MEMORY SYSTEM USING THE SAME

MACRONIX INTERNATIONAL CO...

1. A row decoder, comprising:a plurality of address lines;
a first selection circuit coupled to the address lines and with a latch function, configured to decode address signals on the address lines, enable and latch a first selection signal to select a first word line in a first cell array; and
a second selection circuit coupled to the address lines and without the latch function, configured to decode the address signals on the address lines, enable a second selection signal to select a second word line in a second cell array.

US Pat. No. 10,115,440

WORD LINE CONTACT REGIONS FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY

SANDISK TECHNOLOGIES LLC,...

1. An apparatus comprising:a stack of word line layers comprising word lines for a three-dimensional non-volatile memory array, the stack of word line layers comprising a plurality of tiers;
a plurality of word line switch transistors for transferring word line bias voltages to the word lines;
a plurality of word line contact regions for coupling the word line switch transistors to the word lines, a word line contact region comprising a stepped structure for a tier of the word line layers, wherein a level region separates a word line contact region for a first tier from a word line contact region for a second tier; and
a plurality of connectors coupling the word line switch transistors to the word lines, the connectors comprising vertical conductors, wherein connectors for a single word line contact region comprise vertical conductors disposed within the single word line contact region, at a first side of the single word line contact region, and at a second side of the single word line contact region.

US Pat. No. 10,115,439

ON-DIE TERMINATION OF ADDRESS AND COMMAND SIGNALS

RAMBUS INC., Sunnyvale, ...

1. A memory controller to control the operation of a memory device, the memory controller comprising:a command/address (CA) circuit to drive CA signals onto a CA bus; and
a driver to drive a chip select signal onto the CA bus;
the memory controller to store register values, in the memory device, that represent one or more impedance values of on-die termination (ODT) impedances to apply to respective inputs of the memory device that receive the CA signals, and wherein the register values include one or more register values to selectively enable application of a chip select ODT impedance to an input of the memory device that receives the chip select signal.

US Pat. No. 10,115,438

SENSE AMPLIFIER CONSTRUCTIONS

Micron Technology, Inc., ...

1. A sense amplifier construction comprising:a first n-type transistor and a second n-type transistor extending elevationally outward relative to be vertically offset from the first n-type transistor, the first transistor comprising a first semiconductor material pillar extending along a first gate and comprising a first channel region elevationally between first transistor top and bottom n-type source/drain regions, the second transistor comprising a second semiconductor material pillar extending along a second gate and comprising a second channel region elevationally between second transistor top and bottom n-type source/drain regions;
a third p-type transistor and a fourth p-type transistor extending elevationally outward relative to the third p-type transistor, the third transistor comprising a third semiconductor material pillar extending along a third gate and comprising a third channel region elevationally between third transistor top and bottom p-type source/drain regions, the fourth transistor comprising a fourth semiconductor material pillar extending along a fourth gate and comprising a fourth channel region elevationally between fourth transistor top and bottom p-type source/drain regions;
a lower voltage activation line electrically coupled to each of the top source/drain region of the first transistor and the bottom source/drain region of the second transistor; and
a higher voltage activation line electrically coupled to each of the top source/drain region of the third transistor and the bottom source/drain region of the fourth transistor.

US Pat. No. 10,115,437

STORAGE SYSTEM AND METHOD FOR DIE-BASED DATA RETENTION RECYCLING

Western Digital Technolog...

1. A storage system comprising:a controller; and
a plurality of memory dies in communication with the controller, wherein each of the memory dies comprises its own temperature sensor, wherein at least one of the memory dies is characterized by a relatively lower endurance than at least one other of the memory dies, and wherein the at least one of the memory dies with the relatively lower endurance is positioned farther away from the controller than the at least one other of the memory dies.

US Pat. No. 10,115,436

FILTER MEDIA AND FILTER PRODUCTS FOR ELECTRONIC ENCLOSURES

Seagate Technology LLC, ...

1. An electronic device enclosure comprising:a base and a cover,
at least one data storage disk within the enclosure,
one or more heads for reading or writing data onto the disk, and
a filter in fluid communication with an interior of the enclosure, the filter comprising filter media that includes activated carbon and graphene, wherein the graphene is in the form of graphene particles having a dimension in the range of 2 to 20 microns.

US Pat. No. 10,115,435

METHODS AND SYSTEMS FOR PRIORITIZING PLAYBACK OF MEDIA CONTENT IN A PLAYBACK QUEUE

SPOTIFY AB, Stockholm (S...

1. A method, comprising:at a client device having one or more processors and memory storing instructions for execution by the one or more processors:
playing a first media item from a playback queue, the playback queue comprising a first portion having a plurality of media items with respective positions that define an order in which the media items are to be played;
while playing the first media item:
detecting a first user input indicating selection of a second media item;
in response to the first user input, assigning the second media item to a second portion of the playback queue, comprising adding the second media item to the second portion from a list of search query results, wherein the second portion has playback priority over the first portion; and
detecting a second user input indicating selection of a third media item to be played from the first portion of the playback queue, wherein the third media item is a media item from the plurality of media items of the first portion and the first portion includes one or more additional media items that precede the third media item with respect to the order in which the media items of the first portion are to be played;
in response to the second user input:
ceasing playback of the first media item;
playing the third media item;
removing the third media item from the first portion of the playback queue; and
removing the one or more additional media items that precede the third media item from the first portion of the playback queue while retaining other media items in the first portion that are after the third media item with respect to the order in which the media items of the first portion are to be played; and
after playing the third media item, playing the second media item before playing the other media items in the first portion that are after the third media item with respect to the order in which the media items of the first portion are to be played.

US Pat. No. 10,115,434

METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR EDITING MEDIA CONTENT

NOKIA TECHNOLOGIES OY, E...

1. A method comprising:facilitating receipt of a first media content comprising a first audio track and a first video track, and a second media content comprising a second audio track;
determining a first plurality of audio sections associated with the first audio track and a second plurality of audio sections associated with the second audio track;
performing section mapping between the first plurality of audio sections and the second plurality of audio sections to determine a plurality of mapping audio sections in the second audio track corresponding to the first plurality of audio sections;
determining, in a first audio section of the first plurality of audio sections, a relative position of at least one first video transition with respect to the first audio section;
creating a corresponding at least one second video transition associated with the at least one first video transition with respect to a mapping audio section of the plurality of mapping audio sections, the mapping audio section corresponding to the determined first audio section of the first plurality of audio sections, the corresponding at least one second video transition being created at a same relative position with respect to the mapping audio section as the relative position of the at least one first video transition with respect to the first audio section; and
modifying the first video track based on the relative position of the corresponding at least one second video transition in the mapping audio section to generate a second video track corresponding to the second audio track.

US Pat. No. 10,115,433

SECTION IDENTIFICATION IN VIDEO CONTENT

A9.COM, INC., Palo Alto,...

14. A system, comprising:at least one processor; and
memory storing instructions that, when executed by the at least one processor, cause the system to:
obtain video content from a content source;
obtain content interaction information associated with the video content and corresponding to data reflecting user actions with the video content, the content interaction information comprising historical activity of a plurality of users;
use the content interaction information to identify a portion of the video content;
analyze the portion of the video content to generate an indexed sequence of the portion of the video content; and
modify the video content based at least in part on the indexed sequence to generate modified video content.

US Pat. No. 10,115,432

METHOD AND APPARATUS FOR CONSTRUCTING SENSORY EFFECT MEDIA DATA FILE, METHOD AND APPARATUS FOR PLAYING SENSORY EFFECT MEDIA DATA FILE, AND STRUCTURE OF THE SENSORY EFFECT MEDIA DATA FILE

Myongji University Indust...

1. A method for constructing a sensory effect media data file, the method comprising:receiving a media object including media data;
scanning the media object to extract information representing a property of the media data;
constructing first composition information representing the extracted information representing a property of the media data;
inserting the first composition information into a composition information container field;
receiving a sensory effect object including sensory effect data;
scanning the sensory effect object to extract information representing a property of the sensory effect data;
constructing second composition information representing the extracted information representing a property of the sensory effect data;
inserting second composition information into the composition information container field;
extracting a sample of the media data from the media object;
inserting the extracted sample of the media data into a media data field, the extracted sample representing data associated with a timestamp; and
extracting a sample of the sensory effect data from the sensory effect object;
inserting the extracted sample of the sensory effect data into the media data field;
wherein the extracted sample of the sensory effect data inserted into the media data field comprises timed data from among the sensory effect data, the timed data being data affected by time, and untimed data from among the sensory effect data is included into the composition information container field.

US Pat. No. 10,115,431

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

SONY CORPORATION, Tokyo ...

1. An image processing device, comprising:circuitry configured to:
receive a moving image,
wherein the moving image includes a plurality of frame images, and
wherein each of the plurality of frame images includes at least one object;
extract a first plurality of object images from each of the plurality of frame images;
select, based on a threshold value, a second plurality of object images corresponding to a sequence of movement of the at least one object in the moving image;
control, based on the second plurality of object images, a display device to display a first output image;
receive, at an interface, an edit operation from a user, wherein the edit operation corresponds to selection of a third plurality of object images from the first output image;
generate a second output image based on the edit operation, wherein the second output image comprises the third plurality of object images; and
control the display device to display the second output image.

US Pat. No. 10,115,430

DETECTING MEDIA DEFECTS

International Business Ma...

1. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions readable and/or executable by a processor to cause the processor to perform a method comprising:instructing, by the processor, a drive to detect a written signal burst on a magnetic tape; and
searching, by the processor, a surface of the magnetic tape proximate to the written signal burst for a defect.

US Pat. No. 10,115,428

HAMR MEDIA STRUCTURE HAVING AN ANISOTROPIC THERMAL BARRIER LAYER

WD MEDIA, INC., San Jose...

1. A heat assisted magnetic recording (HAMR) media structure comprising:a magnetic recording layer comprising an array of magnetic grains for storing information;
a heat sink layer disposed below the magnetic recording layer and having a first thermal conductivity;
an anisotropic thermal barrier layer disposed between the magnetic recording layer and the heat sink layer and having a vertical thermal conductivity and an in-plane thermal conductivity,
wherein the anisotropic thermal barrier layer consists of a single material selected from the group consisting of graphite and mica compounds and the ratio of the vertical thermal conductivity to the in-plane thermal conductivity is greater than 3; and
a nucleation layer disposed between the magnetic recording layer and the anisotropic thermal barrier layer, wherein the nucleation layer is selected from the group consisting of SiC, TiN, TiC and RuAl.

US Pat. No. 10,115,427

RECORDING HEAD WITH TRANSFER-PRINTED LASER DIODE UNIT FORMED OF NON-SELF-SUPPORTING LAYERS

Seagate Technology LLC, ...

1. A recording head comprising:a substrate;
a read transducer deposited over the substrate;
a waveguide core deposited over the read transducer;
a near-field transducer at an end of the waveguide core proximate a media-facing surface;
a magnetic write pole and coil deposited over the waveguide core;
a laser diode unit comprising one or more non-self-supporting layers of crystalline material region transfer printed below at least the waveguide core; and
an optical coupler configured to receive light from the laser diode unit and couple the light to the waveguide core, the coupled light causing plasmons to be directed to a recording medium via the near-field transducer.

US Pat. No. 10,115,426

OPTICAL DISC AND METHOD FOR JUDGING WHETHER OPTICAL DISC IS PLACED REVERSELY

LITE-ON TECHNOLOGY CORPOR...

1. A method for judging whether a double-sided optical disc is placed reversely into an optical disc drive, the optical disc drive comprising a first control module which is used to control a first optical pickup head and a second control module which is used to control a second optical pickup head, the first control module comprising the first optical pickup head, a first sled motor, a first radio frequency amplifier, a first driving circuit and a first digital signal processor, the second control module comprising the second optical pickup head, a second sled motor, a second radio frequency amplifier, a second driving circuit and a second digital signal processor, the method comprising steps of:loading the double-sided optical disc;
allowing the first control module to control the first optical pickup head to emit a first laser beam to a first specified area of the double-sided optical disc and receive a first reflected laser beam from the first specified area;
allowing the second control module to control the second optical pickup head to emit a second laser beam to a second specified area of the double-sided optical disc and receive a second reflected laser beam from the second specified area;
if the first reflected laser beam generates an alternate brightness and darkness change and the intensity of the first reflected laser beam processed by the first radio frequency amplifier generates a sinusoidal wave signal and the second reflected laser beam does not generate the alternate brightness and darkness change and the intensity of the second reflected laser beam processed by the second radio frequency amplifier generates a stable direct current signal, confirming that the double-sided optical disc is not placed reversely; and
if the first reflected laser beam does not generate the alternate brightness and darkness change and the intensity of the first reflected laser beam processed by the first radio frequency amplifier generates the stable direct current signal and the second reflected laser beam generates the alternate brightness and darkness change and the intensity of the second reflected laser beam processed by the second radio frequency amplifier generates the sinusoidal wave signal, confirming that the double-sided optical disc is placed reversely.

US Pat. No. 10,115,425

MAGNETIC RECORDING MEDIUM FOR MICROWAVE ASSISTED RECORDING AND MAGNETIC RECORDING DEVICE

FUJIFILM Corporation, Mi...

1. A magnetic recording medium for microwave assisted recording comprising:a magnetic layer including ferromagnetic powder and a binder on a non-magnetic support,
wherein the magnetic layer is a single layer of a magnetic layer exhibiting two or more different intrinsic ferromagnetic resonance frequencies of 30.0 GHz or more,
the magnetic layer comprises two or more different kinds of ferromagnetic powder,
the different kinds of ferromagnetic powder have different coercive forces from each other, and
the coercive forces are 210 kA/m or more.

US Pat. No. 10,115,424

MAGNETIC RECORDING MEDIUM

FUJI ELECTRIC CO., LTD., ...

1. A magnetic recording medium, comprising:a nonmagnetic substrate; and
a magnetic recording layer that comprises a plurality of magnetic layers including:
a first magnetic layer that is provided on the nonmagnetic substrate and that has a granular structure including magnetic crystal grains; and
a second magnetic layer that is provided on the first magnetic layer, that has a granular structure including magnetic crystal grains, and that contains an ordered alloy comprised of:
at least one element selected from the group consisting of Fe and Ni;
at least one element selected from the group consisting of Pt, Pd, Au, Rh and Ir; and
from 0.5 to 20 at % of Ru based on a total amount of the ordered alloy,
wherein the first magnetic layer does not contain any ordered alloy.