US Pat. No. 10,511,062

SYSTEM AND METHOD FOR SELF-ISOLATING ABNORMAL BATTERY

CONTEMPORARY AMPEREX TECH...

1. A system for self-isolating an abnormal battery, comprising: a switch controlling module, a battery detecting module, a data analyzing module and at least two switch battery modules;each of the at least two switch battery modules comprises at least one isolating switch, at least one main circuit switch and a battery, the at least one main circuit switch is connected with the battery in series to form a series circuit, the series circuit is connected in parallel to the at least one isolating switch so as to form one of the at least two switch battery modules, the at least two switch battery modules are connected with each other in series;
the battery detecting module is configured to detect a battery status parameter and provide the detected battery status parameter to the data analyzing module;
the data analyzing module is configured to judge whether an operating status of the battery is normal or not according to the battery status parameter, and provide a signal to the switch controlling module;
the switch controlling module is configured to generate an on/off signal according to the signal provided by the data analyzing module, and apply the on/off signal to the at least one main circuit switch and the at least one isolating switch in one of the at least two switch battery modules, so as to alternatively control on/off of the at least one main circuit switch and the at least one isolating switch in one of the at least two switch battery modules,
the data analyzing module is further configured to: generate a detection preparation instruction before receiving the battery status parameter provided by the battery detecting module, and provide it to the switch controlling module,
the switch controlling module is further configured to: when receiving the detection preparation instruction sent by the data analyzing module, control to switch on all the main circuit switches in the at least two switch battery modules, and control to switch off all the isolating switches in the at least two switch battery modules, so as to connect all the batteries in the at least two switch battery modules in series.

US Pat. No. 10,511,061

LOW TEMPERATURE LIQUID METAL BATTERIES FOR ENERGY STORAGE APPLICATIONS

UNIVERSITY OF KENTUCKY RE...

1. A liquid metal battery comprising a vessel, the vessel holding a first electrode of liquid tin (Sn) and a second electrode of liquid bismuth (Bi) in a co-axial and co-planar ring-disk electrode geometry arrangement, wherein the first electrode and the second electrode are in contact with a eutectic electrolyte blanketed above.

US Pat. No. 10,511,060

ENCODING METHOD AND DEVICE USING RATE-COMPATIBLE, LOW-DENSITY PARITY-CHECK CODE IN COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method of encoding using a low density parity check (LDPC) code in a communication system, the method comprising:inputting information bits for data transmission;
generating parity bits by LDPC encoding the information bits based on a parity-check matrix consisting of a first sub-matrix having a first code rate and a second sub-matrix having a second code for code extension, wherein the second sub-matrix has a stair-wise lower triangular structure in an extension part; and
outputting the information bits and the generated parity bits.

US Pat. No. 10,511,059

ALKALINE POUCH CELL WITH COATED TERMINALS

ZAF Energy Systems, Incor...

1. A battery cell comprising:an electrode assembly including a negative electrode, positive electrode, and separator bathed in an alkaline electrolyte;
a pouch encapsulating the electrode assembly; and
first and second tabs respectively extending from the positive and negative electrodes through the pouch, the first tab having thereon a coating including acrylic paint and the second tab having thereon a coating including lacquer.

US Pat. No. 10,511,058

MULTILAYER CABLE-TYPE SECONDARY BATTERY

LG Chem, Ltd., (KR)

1. A multilayer cable-type secondary battery comprising:a first electrode assembly comprising one or more first inner electrodes and a sheet-type first separation layer-outer electrode complex helically wound to surround outer surfaces of the one or more first inner electrodes;
a separation layer surrounding the first electrode assembly; and
a second electrode assembly comprising one or more second inner electrodes surrounding an outer surface of the separation layer and a sheet-type second separation layer-outer electrode complex helically wound to surround outer surfaces of the one or more second inner electrodes.

US Pat. No. 10,511,057

NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY AND A METHOD FOR PRODUCING THE SAME

TOYOTA JIDOSHA KABUSHIKI ...

1. A method for producing a non-aqueous electrolyte secondary battery, the method comprising:a step of obtaining a positive electrode, a negative electrode and a non-aqueous electrolyte; and
a step of placing the positive electrode, the negative electrode and the non-aqueous electrolyte in a battery case,
wherein,
the non-aqueous electrolyte comprises a fluorine atom-containing supporting salt and a benzothiophene oxide represented by formula (1):

the benzothiophene oxide is added in an amount of 0.2% by weight to 1.0% by weight in the non-aqueous electrolyte,
the negative electrode comprises a negative current collector and a negative electrode material layer placed on the negative current collector, and
the negative electrode material layer has a BET specific surface area of 2.0 m2/g to 4.9 m2/g.

US Pat. No. 10,511,056

SOLID POLYMER ELECTROLYTE AND LITHIUM SECONDARY BATTERY COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A solid polymer electrolyte comprising a polymer including a first repeating unit represented by the following Chemical Formula 1:
wherein, in Chemical Formula 1,
R is hydrogen or an alkyl group having 1 to 3 carbon atoms; and
a is an integer of any one of 1 to 800,
wherein the polymer further includes at least one or more of a second repeating unit represented by the following Chemical Formula 2a and a third repeating unit represented by Chemical Formula 2b:

in Chemical Formula 2a,
R1 is hydrogen or an alkyl group having 1 to 3 carbon atoms;
R2 and R3 are each independently an alkylene group having 1 to 3 carbon atoms;
b is an integer of any one of 1 to 800; and
o is an integer of any one of 10 to 100,

in Chemical Formula 2b,
R4 is or an alkyl group having 1 to 3 carbon atoms;
R5 to R9 are each independently an alkylene group having 1 to 3 carbon atoms;
c is an integer of any one of 1 to 800; and
o1 to o4 are each independently an integer of any one of 1 to 120.

US Pat. No. 10,511,055

METAL PLATING-BASED ELECTRICAL ENERGY STORAGE CELL

Board of Regents, The Uni...

1. An electrochemical storage cell comprising:a battery comprising:
an alkali metal anode having an anode Fermi energy;
an electronically insulating, amorphous, dried solid electrolyte able to conduct alkali metal, having the general formula A3-xHxOX, wherein 0?x?1, A is the alkali metal, and X is at least one halide; and
a cathode comprising a cathode current collector having a cathode Fermi energy lower than the anode Fermi energy; and
a catalytic redox-center-relay material; and
wherein the solid electrolyte further comprises electric dipoles that are oriented parallel to each other, wherein the electrochemical storage cell is operable to:
plate the alkali metal dendrite-free from the solid electrolyte onto the alkali metal anodes; and
plate the alkali metal is on the cathode current collector with the aid of the catalytic redox-center-relay material.

US Pat. No. 10,511,053

SOLID ELECTROLYTE HAVING MAGNESIUM ION CONDUCTIVITY AND MAGNESIUM SECONDARY BATTERY USING THE SAME

PANASONIC INTELLECTUAL PR...

8. A secondary battery comprising:a positive electrode containing a positive electrode active material;
a negative electrode containing a negative electrode active material; and
the solid electrolyte according to claim 1.

US Pat. No. 10,511,052

ELECTROLYTE SHEET

IDEMITSU KOSAN CO., LTD.,...

1. A method for producing a stacked body, the method comprising:applying an electrolyte slurry comprising sulfide-based solid electrolyte particles and a binder that is a resin having a structural unit A in a molecular skeleton to a base material, thereby to form an electrolyte layer; and
transferring the electrolyte layer to an electrode material layer and peeling off the base material from the electrolyte layer,
wherein
the electrolyte slurry has a solid matter concentration of 20 wt % or more and 90 wt % or less;
a ratio of the electrolyte particles in the solid matter is 90 wt % or more and 99.5 wt % or less; and
the base material has a peel force of 20 mN/cm or more and 1500 mN/cm or less:

where R1 to R4 are independently H, F, CF3, CH2CF3, CF2CF3, CF2CF2CF3, OCF2CF2CF3, OCF3 or Cl, and at least one of R1 to R4 is F, CF3, CH2CF3, CF2CF3, CF2CF2CF3, OCF2CF2CF3 or OCF3.

US Pat. No. 10,511,051

LI-WATER SECONDARY ELECTROCHEMICAL BATTERY

1. A secondary lithium-water electrochemical cell comprising:a. a water splitting of hydrogen and oxygen irreversible bi-functional electrode in contact with an inorganic electrolyte;
b. a reversible lithium electrode in the lithium-water electrochemical cell in contact with an organic electrolyte;
c. a lithium salt in organic and inorganic electrolytes; and
d. a Li+-ion conductive membrane in the lithium-water electrochemical cell disposed between the organic electrolyte and the inorganic electrolyte, wherein the secondary lithium-water electrochemical cell is configured to be charged as a Li—O2 cell and discharged as an Li—H2 cell.

US Pat. No. 10,511,049

ELECTROLYTE SYSTEM INCLUDING ALKALI METAL BIS(FLUOROSULFONYL)IMIDE AND DIMETHYOXYETHANE FOR IMPROVING ANODIC STABILITY OF ELECTROCHEMICAL CELLS

GM GLOBAL TECHNOLOGY OPER...

1. An electrochemical cell that cycles lithium-ions having improved or optimized capacity retention and anodic stability comprising:a positive electrode comprising a positive lithium-based electroactive material selected from the group consisting of nickel-manganese-cobalt 811 (NMC811), nickel-manganese-cobalt 622 (NMC 622), and combinations thereof and having a maximum potential greater than or equal to about 5V;
a separator;
a negative electrode comprising a negative electroactive material including lithium; and
an electrolyte system comprising a bound moiety having an ionization potential that is greater than its electron affinity and an electrolyte additive comprising 1H,1H,2H,2H-perfluorooctyltrimethoxysilane;
wherein the bound moiety comprises one or more salts bound to a solvent,
wherein the one or more salts is selected from the group consisting of: lithium bis(fluorosulfonyl)imide (LiFSI), sodium bis(fluorosulfonyl)imide (NaFSI), potassium bis(fluorosulfonyl)imide (KFSI), and combinations thereof and the solvent comprises dimethoxyethane (DME),
wherein the one or more salts have a concentration in the electrolyte system of greater than 5 M and a molar ratio of the one or more salts to the dimethoxyethane (DME) is greater than or equal to about 1 to less than or equal to about 1.5, and
wherein the electrolyte system is substantially free of unbound dimethoxyethane (DME) and unbound bis(fluorosulfonyl)imide (FSI?).

US Pat. No. 10,511,048

METHOD OF PREPARING NEGATIVE ELECTRODE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY USING THE SAME

LG CHEM, LTD., Seoul (KR...

1. A method of preparing a negative electrode active material for a lithium secondary battery, the method comprising steps of:depositing an amorphous silicon layer on a surface of a glass substrate by applying silane gas at a rate of 10 sccm/60 min to 50 sccm/60 min in a temperature range of 500° C. to 700° C. and in a pressure range of 10?8 Torr to 760 Torr (S1) through chemical vapor deposition (CVD) using silane (SiH4) gas as a source (S1);
immersing the glass substrate having the amorphous silicon layer deposited thereon in an acetone solution and then performing ultrasonic milling of the amorphous silicon layer at a power of 50 W to 200 W for 10 minutes to 20 minutes at room temperature using an ultrasonic milling machine to prepare amorphous silicon particles (S2);
dispersing the amorphous silicon particles in a carbon-based precursor solution to prepare a dispersion solution (S3);
spray drying the dispersion solution to prepare a silicon-based composite precursor (S4); and
heat treating the silicon-based composite precursor to form a silicon composite which includes an amorphous carbon coating layer containing at least one amorphous silicon particle in inside thereof (S5).

US Pat. No. 10,511,047

ANODE SPLITTER PLATE AND METHODS FOR MAKING THE SAME

BLOOM ENERGY CORPORATION,...

1. A fuel cell stack system, comprising:a column comprising at least a first fuel cell stack and a second fuel cell stack; and
a reactant feed and return assembly located between the first fuel cell stack and the second fuel cell stack in the column, wherein at least the outer surfaces of the reactant feed and return assembly that contact the respective end plates of the first fuel cell stack and the second fuel cell stack are formed of a material that has a coefficient of thermal expansion (CTE) that differs from the CTE of the respective end plates of the first fuel cell stack and the second fuel cell stack by less than 1.3×10?6K?1 over an operating temperature of the fuel cell stack system.

US Pat. No. 10,511,045

FUEL CELL AND FUEL CELL SYSTEM

Toyota Jidosha Kabushiki ...

1. A fuel cell comprising:a stacked body formed by stacking a plurality of unit cells;
an end plate arranged on at least one end of the stacked body in a stacking direction;
a fuel cell case including an opening portion having an opening formed therein to receive the stacked body, wherein the opening portion has a substantially polygonal outer circumference shape with a plurality of corners, and holes are formed in the opening portion of the fuel cell case; and
a plurality of types of fasteners with different load resistances that fix the end plate to the opening portion of the fuel cell case to close the opening of the fuel cell case, wherein
a fastener, of the plurality of types of fasteners, of a type with a highest load resistance is arranged at at least one of the plurality of corners of the opening portion,
each of the plurality of types of fasteners is configured to extend within a respective one of the holes formed in the opening portion of the fuel cell case and to exert a force on the end plate in a direction towards the stacked body when each of the plurality of types of fasteners fixes the end plate to the opening portion of the fuel cell case, and
the holes formed in the opening portion of the fuel cell case are arranged on the same side of the end plate as the stacked body.

US Pat. No. 10,511,044

ALKALINE HYBRID REDOX FLOW BATTERY WITH HIGH ENERGY DENSITY

Jeffrey Phillips, La Jol...

1. A single cell of a hybrid redox flow battery comprising:a solid nickel hydroxide positive electrode housed in a positive compartment filled with a non-circulated aqueous alkaline electrolyte;
and a substituted anthraquinone based negative active material dissolved in a circulated alkaline electrolyte that is pumped from an external storage tank into a negative electrode compartment of the cell where an oxidation/reduction reaction occurs at a facilitating electrode;
and a physical arrangement whereby the positive and negative electrode compartments are separated by an electronically insulating but ionically conductive membrane.

US Pat. No. 10,511,043

GAS DIFFUSION LAYER FOR FUEL CELL APPLICATIONS

Hyundai Motor Company, S...

1. A fuel cell, comprising:a polymer electrolyte membrane having two side surfaces, wherein each side surface includes:
a catalyst layer coated on the side surface of the polymer electrolyte membrane,
a compressible gas diffusion layer (GDL) stacked on the catalyst layer; and
a bipolar plate on the compressible GDL and comprises a major flow field and a minor flow field,
wherein the compressible GDL comprises a dual layer structure including a microporous layer having a pore size of less than 1 ?m when measured by mercury intrusion, the microporous layer composed of the mixture of carbon powder and a hydrophobic agent; and a macroporous substrate having a pore size of 1 to 300 ?m, the macroporous substrate composed of carbon fiber and a hydrophobic agent, and the compressible GDL has a width direction perpendicular to a major flow field direction of the bipolar plate and a length direction which is in parallel with the major flow field direction of the bipolar plate, and
wherein the compressible GDL is prepared by cutting a rolled GDL material at a certain angle in a range of 60°??<90° with respect to a machine direction of the rolled GDL material as determined by the major flow field direction of the bipolar plate, such that a high stiffness direction of the compressible GDL as the machine direction of the rolled GDL material is not parallel with the length direction of the compressible GDL, the machine direction of the rolled GDL material is the high stiffness direction of the compressible GDL,
wherein the high stiffness direction of the compressible GDL as the machine direction of the rolled GDL material is arranged in one direction, the high stiffness direction of the compressible GDL as the machine direction of the rolled GDL material is not parallel with the length direction of the compressible GDL at an angle (?) in a range of 60 °??<90°, formed by the high stiffness direction of the compressible GDL and the length direction of the compressible GDL and, at the same time, with the major flow field direction of the bipolar plate when the compressible GDL is stacked on the bipolar plate to reduce intrusion of the compressible GDL into flow field channels of the bipolar plate.

US Pat. No. 10,511,042

FUEL CELL UNIT AND VEHICLE HAVING FUEL CELL UNIT

Toyota Jidosha Kabushiki ...

1. A fuel cell unit comprising:a fuel cell having single cells laminated in a laminating direction; and
a converter having at least three combinations of a reactor electrically connected with the fuel cell and a power module electrically connected with the reactor, wherein
a direction in which the at least three reactors are arrayed and a direction in which the at least three power modules are arrayed are parallel with the laminating direction of the single cells.

US Pat. No. 10,511,040

FUEL CELL SYSTEM

NISSAN MOTOR CO., LTD., ...

1. A fuel cell system configured to generate electric power by supplying an anode gas and a cathode gas to a fuel cell, the fuel cell system comprising:a connection line configured to connect the fuel cell to an electric load;
a converter connected to the connection line and a battery, the converter being configured to adjust a voltage of the connection line; and
a controller programmed to:
calculate a target output current of the fuel cell in accordance with a load of the electric load;
carry out a switching control for the converter in accordance with the target output current;
control a flow rate of the cathode gas to be supplied to the fuel cell in accordance with the target output current; and
calculate the generated electric power of the fuel cell on the basis of a previous value of the target output current calculated by the controller and a detected voltage of the connection line,
wherein the controller is programmed to set up an upper limit to the target output current on the basis of a generated electric power of the fuel cell calculated by the controller and a guaranteed minimum voltage of the connection line for ensuring performance of the fuel cell and the electric load.

US Pat. No. 10,511,038

APPARATUS AND METHOD FOR CONTROLLING HYDROGEN PURGING

Hyundai Motor Company, S...

1. An apparatus for controlling hydrogen purging, comprising:a purge valve disposed at an outlet on an anode side of a fuel cell stack and configured to adjust an amount of emission of hydrogen containing impurities; and
a controller programmed to adjust an opening and closing cycle of the purge valve based on a required output or an output current of the fuel cell stack,
wherein the controller is programmed to classify driving states of the fuel cell vehicle into a plurality of driving levels, based on a magnitude of the required output or the output current of the fuel cell stack, to vary the opening and closing cycle of the purge valve to correspond to the plurality of classified driving levels, and to increase an opening time of the purge valve in a transition period longer than opening times of the purge valve in the plurality of driving levels during which the driving level transitions from one of the driving levels to another higher driving level and also the magnitude of the required output or the output current of the fuel cell stack of the driving levels is changed to increase, and
wherein the driving levels include a first level at which the magnitude of the required output or the output current of the fuel cell stack is less than or equal to a reference value preset for the required output or the output current and is higher than zero, a second level at which the magnitude of the required output or the output current of the fuel cell stack is greater than the preset reference value, and the transition period at which the magnitude of current increases from the first level to the second level and the moving average of the current exceeds a threshold.

US Pat. No. 10,511,037

APPARATUS FOR REMOVING MOISTURE OF STACK ENCLOSURE

HYUNDAI MOTOR COMPANY, S...

1. An apparatus for removing moisture of a stack enclosure comprising:a protective case accommodating a fuel cell stack therein, the protective case including:
a lower part at, a bottom side of the protective case; and
an upper part at a top side of the protective case and including a pair of sidewalls and a top surface, wherein the upper part is spaced apart at a predetermined distance from the fuel cell stack such that air flows through a space between the upper part and the fuel cell stack as a convection path inside the protective case;
a radiation heater disposed in the convection path at, the lower part of the protective case, such that the radiation heater enables air heated and discharged from the radiation heater to move thermodynamically toward the top surface of the upper part of the protective case along the convection path; and
a cooler disposed in the convection path at the top surface of the upper part of the protective case to cool the air moving along the convection path from the radiation heater, wherein such that the cooler guides the cooled air to move toward the lower part of the protective case such that moisture condensed from the air heated by the radiation heater and then cooled and condensed by the cooler is collected to be discharged outside the protective case.

US Pat. No. 10,511,036

FUEL CELL MODULE WITH ARRANGED RIDGE SEGMENTS

TOYOTA JIDOSHA KABUSHIKI ...

1. A fuel cell module comprising:a membrane electrode assembly;
a separator; and
a channel forming body disposed between the membrane electrode assembly and the separator, wherein
the channel forming body has:
a gas channel which is provided between a plurality of ridges arrayed on a side of the channel forming body facing the membrane electrode assembly, and through which a gas is supplied to a fuel cell, wherein the plurality of ridges have the same height;
a water conduit which is provided adjacent to the gas channel on a side of the channel forming body facing the separator, and through which water produced from the fuel cell is discharged; and
communication paths that are formed in a partition wall forming each ridge and which provide communication between the gas channel and the water conduit,
wherein each ridge has a central axis extending in the channel extension direction and comprises a plurality of ridge segments arranged in the channel extension direction and separated by communication paths;
when the ridge is seen in a cross-section perpendicular to a channel extension direction, one of left and right upper ends of an external shape of the ridge is shaped so as to be located closer to the central axis of the ridge with respect to another of the left and right upper ends, and
when the ridge is seen in the channel extension direction, portions of the ridge located closer to the center of the ridge in respective ridge segments are formed opposite from each other at left and right upper ends of the external shape of the ridge with the communication paths interposed therebetween and configured such that a gas flow through the gas channel is disturbed in a left-right direction of the left and right upper ends by portions of the ridge located not closer to the center of the ridge at positions where the communication paths are formed in the ridge.

US Pat. No. 10,511,035

RECIRCULATION ARRANGEMENT AND METHOD FOR A HIGH TEMPERATURE CELL SYSTEM

CONVION OY, Espoo (FI)

1. A recirculation arrangement for a high temperature fuel cell system or electrolysis cell system, each cell in the system having an anode, a cathode, and an electrolyte between the anode and the cathode, the recirculation arrangement comprising:at least one ejector for recirculating a fraction of gas exhausted from the anode and for accomplishing a desired flow rate of the recirculated flow, the ejector having at least one nozzle;
means for providing at least one primary feedstock fluid to said nozzle of the ejector, which nozzle has a convergent-divergent flow channel through which the at least one primary feedstock fluid will expand from an initial higher pressure to a lower pressure;
means for providing at least one supplementary fluid to said nozzle of the ejector, the supplementary fluid constituting a majority of a total flow supplied to the nozzle at startup of the system;
means for regulating a respective ratio of at least part of the fluids of the ejector to maintain a desired motive flow and pressure at the nozzle of said ejector in order to accomplish the desired recirculated flow rate; and
means for cutting off the supplementary fluid when a level of system loading is such that the primary feedstock fluid alone maintains the desired motive flow and pressure at an ejector inlet,
wherein the at least one ejector comprises a supersonic ejector,
wherein in the supersonic ejector, motive flow expands in a series of supersonic shocks assisting in mixture of the supplementary fluid with the at least one primary feedstock fluid, the at least one supplementary fluid is water,
wherein an oxygen to-carbon ratio of a mixture of primary and supplementary fluids supplied to the nozzle of the ejector is above a carbon forming threshold when fuel cells are not loaded, and
wherein the flow in said nozzle reaches speed of sound whenever at least one primary feedstock is supplied.

US Pat. No. 10,511,034

GASKET FOR FUEL BATTERY

NOK Corporation, (JP)

1. A gasket for a fuel battery provided in a fuel battery cell in which an intermediate part including an MEA is interposed between a first separator and a second separator, the gasket for the fuel battery comprising:a first gasket main body attached to the first separator;
a second gasket main body attached to the second separator;
wherein the first and second gasket main bodies contact the intermediate part at positions where the first and second gasket main bodies overlap each other in a plan view;
wherein the first and second gasket main bodies each include a pair of bank portions that are unitary with and formed on opposing sides of the respective gasket main body and configured for fixed size stop according to a gasket thickness,
wherein the bank portions for fixed size stop are supported by convex portions which are defined by pressed three-dimensional hollow shapes formed in the first and second separators;
wherein the convex portions are buried in the bank portions for fixed size stop.

US Pat. No. 10,511,033

SOLID OXIDE FUEL CELL

NGK Insulators, Ltd., Na...

1. A solid oxide fuel cell, comprising:a power generation part of the solid oxide fuel cell, comprising: a fuel electrode for allowing a fuel gas to be reacted by bringing the fuel gas into contact therewith; an electrolyte film made of a solid electrolyte provided on the fuel electrode; and an air electrode for allowing a gas containing oxygen to be reacted, the air electrode being provided on the electrolyte film so that the electrolyte film is sandwiched between the fuel electrode and the air electrode;
an interconnector made of dense conductive ceramics and provided so as to be electrically connected to the fuel electrode;
a porous conductive ceramics film formed on a surface of the interconnector,
wherein a maximum joining width, which is a maximum value of lengths of a plurality of portions at which the interconnector and the porous conductive ceramics film are brought into contact with each other on a boundary line which is a line corresponding to an interface between the interconnector and the porous conductive ceramics film in a cross-section including the interconnector and the porous conductive ceramics film, is from 5 ?m or more to 40 ?m or less;
and
the porous conductive ceramics film is a P-type semiconductor film.

US Pat. No. 10,511,030

ANTI-CORROSION STRUCTURE AND FUEL CELL EMPLOYING THE SAME

INDUSTRIAL TECHNOLOGY RES...

1. An anti-corrosion structure, comprising:an aluminum layer;
a first anti-corrosion layer, wherein the first anti-corrosion layer is a nickel-tin-containing alloy layer; and
an intermediate layer disposed between the aluminum layer and the first anti-corrosion layer, wherein the intermediate layer is a nickel-tin-aluminum-containing alloy layer.

US Pat. No. 10,511,028

ELECTROLYTE MEMBRANE, FUEL CELL INCLUDING SAME, BATTERY MODULE INCLUDING FUEL CELL, AND METHOD FOR MANUFACTURING ELECTROLYTE MEMBRANE

LG CHEM, LTD., Seoul (KR...

1. An electrolyte membrane which comprises a lanthanum-gallium-based composite metal oxide, and has a color region of 0.39?x?0.40 and 0.35?y?0.36 based on the CIE (Commission Internationale de l'Eclairage) x, y chromaticity distribution table,wherein the electrolyte membrane manufactured by a method comprising:
preparing a mixture comprising a precursor of a lanthanum-gallium-based composite metal oxide comprising evaporating moisture and heating to induce a combustion reaction;
warming the mixture to a temperature of 800° C. or more and less than 950° C., thereby synthesizing the precursor in the mixture into lanthanum-gallium-based composite metal oxide particles; and
forming the electrolyte membrane by using a slurry comprising the lanthanum-gallium-based composite metal oxide particles,
the synthesized composite metal oxide particles comprise lanthanum-gallium-based composite metal oxide particles which are represented by the following Chemical Formula 1, and secondary phase particles,
a content of the secondary phase particles is 5 wt % or more and 30 wt % or less based on the total weight of the synthesized composite metal oxide particles,
wherein the lanthanum-gallium-based composite metal oxide of the electrolyte membrane is represented by the following Chemical Formula 1:
La1-xQxGa1-yZyO3-?  [Chemical Formula 1]
in Chemical Formula 1,
Q is strontium, Z is magnesium, and 0

US Pat. No. 10,511,027

BATTERIES AND RELATED STRUCTURES HAVING FRACTAL OR SELF-COMPLEMENTARY STRUCTURES

Fractal Antenna Systems, ...

1. A battery comprising:a first electrode including a surface having a plurality of fractal features, wherein the plurality of fractal features include diffusion-limited aggregation (DLA) tree structure, wherein the DLA tree structure comprises a Brownian tree;
a second electrode, wherein the second electrode comprises a plurality of self-complementary features, wherein the plurality of self-complementary features include a conductive portion that includes a conductive material and a non-conductive portion that does not include a conductive material, and wherein the conductive portion and the non-conductive portion have shapes that are self-complementary to one another on an exposed surface of the second electrode; and
an electrolyte, wherein in operation the electrolyte forms a first conductive path ionically connecting the first electrode to the second electrode, and a second conductive path, separate from the first conductive path, connecting the first electrode to the second electrode, wherein an electrical circuit is formed;
wherein the first electrode DLA tree structure forms an interface with the electrolyte.

US Pat. No. 10,511,026

ELECTRODE FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY, NONAQUEOUS ELECTROLYTE SECONDARY BATTERY, BATTERY PACK, AND VEHICLE

Kabushiki Kaisha Toshiba,...

1. A negative electrode active material for a nonaqueous electrolyte battery, comprising:a particle of silicon oxide enveloping particles of silicon;
a carbonaceous substance covering the particle of silicon oxide enveloping particles of silicon; and
a phase comprising a silicate compound mixed with a conductive assistant, the phase being interposed between the particle of silicon oxide enveloping particles of silicon and the carbonaceous substance,
wherein
the silicate compound is at least one compound selected from the group consisting of MgSiO3, Mg2SiO4, TiSiO4, Mn2SiO4, FeSiO3, Fe2SiO4, Co2SiO4, Ni2SiO4, Al2SiO5, ZrSiO4, Y2SiO5, and Y2Si2O7.

US Pat. No. 10,511,025

ELECTRODE MANUFACTURING METHOD

UBE INDUSTRIES, LTD., Ya...

1. A method for manufacturing an electrode, the method comprising forming an electrode mixture layer on a surface of a current collector using an electrode mixture composition containing at least an electrode active material, an aqueous polyimide precursor solution composition, and a crosslinking agent, the aqueous polyimide precursor solution composition being obtained by dissolving a polyamide acid having a repeating unit represented by a formula (1) below in an aqueous solvent together with an imidazole in an amount of 1.6 moles or more per mole of a tetracarboxylic acid component of the polyamide acid, the imidazole having two or more alkyl groups as substituents, and the crosslinking agent having a carbodiimide group or an oxazoline group; and subsequently performing heat treatment to remove the solvent and perform an imidization reaction of the polyamide acid,
wherein in the formula (1), A comprises at least one tetravalent group selected from the group consisting of tetravalent groups represented by formulae (2), (3), and (4) below, and B comprises (i) at least one divalent group selected from the group consisting of divalent groups represented by formulae (5), (6), (7), and (8) below and divalent saturated hydrocarbon groups having 4 to 10 carbon atoms; and (ii) at least one divalent group selected from the group consisting of divalent groups represented by formulae (9) and (10) below,

wherein in the formula (8), X is any of a direct bond, an oxygen atom, a sulfur atom, a methylene group, a carbonyl group, a sulfoxyl group, a sulfone group, a 1,1?-ethylidene group, a 1,2-ethylidene group, a 2,2?-isopropylidene group, a 2,2?-hexafluoroisopropylidene group, a cyclohexylidene group, a phenylene group, a 1,3-phenylenedimethylene group, a 1,4-phenylenedimethylene group, a 1,3-phenylenediethylidene group, a 1,4-phenylenediethylidene group, a 1,3-phenylenedipropylidene group, a 1,4-phenylenedipropylidene group, a 1,3-phenylenedioxy group, a 1,4-phenylenedioxy group, a biphenylenedioxy group, a methylenediphenoxy group, an ethylidenediphenoxy group, a propylidenediphenoxy group, a hexafluoropropylidenediphenoxy group, an oxydiphenoxy group, a thiodiphenoxy group, and a sulfonediphenoxy group, and

wherein in the formula (10), Y is any of a direct bond, an oxygen atom, a sulfur atom, a methylene group, a carbonyl group, a sulfoxyl group, a sulfone group, a 1,1?-ethylidene group, a 1,2-ethylidene group, a 2,2?-isopropylidene group, a 2,2?-hexafluoroisopropylidene group, a cyclohexylidene group, a phenylene group, a 1,3-phenylenedimethylene group, a 1,4-phenylenedimethylene group, a 1,3-phenylenediethylidene group, a 1,4-phenylenediethylidene group, a 1,3-phenylenedipropylidene group, a 1,4-phenylenedipropylidene group, a 1,3-phenylenedioxy group, a 1,4-phenylenedioxy group, a biphenylenedioxy group, a methylenediphenoxy group, an ethylidenediphenoxy group, a propylidenediphenoxy group, a hexafluoropropylidenediphenoxy group, an oxydiphenoxy group, a thiodiphenoxy group, and a sulfonediphenoxy group.

US Pat. No. 10,511,024

ELECTRODE FOR NONAQUEOUS ELECTROLYTE SECONDARY BATTERY AND METHOD OF MANUFACTURING THE SAME

TOYOTA JIDOSHA KABUSHIKI ...

1. An electrode for a nonaqueous electrolyte secondary battery, the electrode comprising:an electrode mixture layer containing a hollow active material particle and a needle-shaped filler particle, wherein
the needle-shaped filler particle consists of cellulose or polyacrylonitrile in the shape of a hollow cylindrical shell having an outer diameter of 0.1 to 10 ?m, an outer cylindrical surface extending along an entire length of the needle-shaped particle, and an inner cylindrical surface extending along the entire length of the needle-shaped particle, the inner cylindrical surface defining a single through-hole of the needle-shaped particle,
the needle-shaped filler particle is arranged on an outer surface of the hollow active material particle such that the outer cylindrical surface of the needle-shaped particle contacts the outer surface of the hollow active material particle,
the hollow active material particle is a secondary particle that includes an outer shell defined by an aggregate of primary particles, a hollow interior portion enclosed and surrounded by the outer shell, and at least one through-hole in the outer shell such that the hollow interior portion is in fluid communication with an exterior of the hollow active particle, and
an average particle size of the hollow active material particle is 3 to 25 ?m.

US Pat. No. 10,511,023

FLUORINATED COAL DERIVED CARBONS AND ELECTRODES FOR USE IN BATTERY SYSTEMS AND SIMILAR

UNIVERSITY OF KENTUCKY RE...

1. An electrode comprising fluorinated coal particles, wherein said particles comprise fluorinated carbon at a ratio of between about CF0.3 and CF1.4.

US Pat. No. 10,511,022

LEAD-BASED ALLOY AND RELATED PROCESSES AND PRODUCTS

RSR TECHNOLOGIES, INC., ...

1. A lead-based alloy comprising, in percent by total alloy weight:0.0090% to 0.0600% bismuth;
0.0075% to 0.0025% antimony;
0.0075% to 0.0125% arsenic;
0.0035% to 0.0060% tin;
up to 0.0100% silver;
up to 0.0010% thallium; and
balance lead and incidental impurities.

US Pat. No. 10,511,020

NICKEL COMPOSITE HYDROXIDE PARTICLE AND PROCESS FOR PRODUCING THE SAME, POSITIVE ELECTRODE ACTIVE MATERIAL FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY AND PROCESS FOR PRODUCING THE SAME, AND NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

SUMITOMO METAL MINING CO....

1. A process for producing a positive electrode active material for a non-aqueous electrolyte secondary battery; comprising the following processes (a) to (c):(a) a process for calcining at least one of nickel hydroxide and nickel oxyhydroxide, which contains nickel as a major component and at least one element selected from the group consisting of transition metal elements other than nickel, group II elements and group XIII elements as a subsidiary component in a nonreducing atmosphere having a temperature of 500° C. to 850° C., to prepare a nickel oxide;
(b) a process for preparing a calcined powder represented by the following formula (1):
LiaNi1-bMbO2  (1)
wherein M is at least one element selected from the group consisting of transition metal elements other than Ni, group II elements and group XIII elements, and a satisfies 1.00?a?1.10, and b satisfies 0.01?b?0.5,
which comprises mixing the nickel oxide with a lithium compound so that the molar ratio of lithium included in the lithium compound to the total moles of nickel, transition metal elements other than nickel contained in the nickel oxide, group II elements and group XIII elements is 1.00 to 1.10, and thereafter calcining the resulting mixture in an oxygen-containing atmosphere at a temperature of 650 to 850° C.; and
(c) a process for preparing powder of lithium-nickel composite oxide, which comprises preparing a slurry comprising the calcined powder in a concentration of 500 to 2000 g/L, washing the calcined powder with water in the form of slurry for a period of time which satisfies the following formula (2):
B/40 wherein A is a period of time for washing with water, of which unit is represented by minute, and B is a concentration of a slurry, of which unit is represented by g/L, and thereafter filtering and drying the slurry.

US Pat. No. 10,511,019

ELECTRODE SOLUTIONS AND ELECTROCHEMICAL CELLS AND BATTERIES THEREFROM

3M INNOVATIVE PROPERTIES ...

1. An electrode solution for a liquid flow battery comprising:an electrolyte comprising a liquid medium and at least one redox active specie, wherein the electrolyte has a density, De; and
a core-shell particulate having a core, a shell and a density Dp, wherein at least a portion of the shell of the core-shell particulate includes an electrically conductive first metal and wherein 0.8De?Dp?1.2De; and
wherein a first redox active specie of the at least one redox active specie and the electrically conductive first metal are different elements.

US Pat. No. 10,511,016

GRAPHENE-PROTECTED LEAD ACID BATTERIES

Global Graphene Group, In...

1. A lead acid battery comprising a negative electrode, a positive electrode comprising lead oxide, and an electrolyte in physical contact with said negative electrode and said positive electrode, wherein said negative electrode comprises a plurality of negative particulates of graphene-protected lead or lead alloy and wherein said negative particulates are formed of a single or a plurality of graphene sheets and a single or a plurality of fine lead or lead alloy particles having a size smaller than 10 ?m, and the graphene sheets and the lead or lead alloy particles are mutually bonded or agglomerated into each of said negative particulates with at least a graphene sheet encapsulating each of said negative particulates, and wherein said graphene is in an amount of at least 0.01% but less than 99% by weight based on the total weight of each of said negative particulates.

US Pat. No. 10,511,015

ELECTRODE FOR ELECTROCHEMICAL DEVICE, METHOD FOR PREPARING THE SAME, AND ELECTROCHEMICAL DEVICE COMPRISING THE SAME

LG CHEM, LTD., Seoul (KR...

1. An electrode for an electrochemical device comprisinga metal electrode, and
a coating layer positioned on the surface of the metal electrode,
wherein the coating layer comprises a two-dimensional semiconductor material, and metal phosphide converted from a part of the two-dimensional semiconductor material, and
wherein the two-dimensional semiconductor material is phosphorene in the form of a monolayer film.

US Pat. No. 10,511,014

BATTERY MODULE AND BATTERY PACK

Kabushiki Kaisha Toshiba,...

1. A battery module comprising five nonaqueous electrolyte batteries electrically connected in series, each of the five nonaqueous electrolyte batteries comprising:a positive electrode;
a negative electrode; and
a nonaqueous electrolyte,
wherein the negative electrode comprises an active material comprising a titanium composite oxide comprising Na and a metal element M in its crystal structure, the metal element M being at least one selected from the group consisting of Zr, Sn, V, Nb, Ta, Mo, W, Fe, Co, Mn, and Al, and
the crystal structure of the titanium composite oxide has symmetry belonging to a space group Cmca or Fmmm.

US Pat. No. 10,511,013

ELECTROCHEMICAL CELL WITH PROTECTED NEGATIVE ELECTRODE

Applied Materials, Inc., ...

1. A method of fabricating a negative electrode for an electrochemical cell, comprising:providing a substrate, said substrate being electrically conductive;
depositing a metal layer on said substrate;
anodizing said metal layer to form a porous layer on said substrate;
depositing a layer of ion conducting material on said porous layer, said layer of ion conducting material extending at least partially into pores of said porous layer;
densifying said layer of ion conducting material;
depositing a layer of alkali metal on the densified layer of ion conducting material;
attaching a temporary electrode to said layer of alkali metal and passing a current between said temporary electrode and said substrate to drive alkali metal through the densified layer of ion conducting material to the surface of said substrate, forming an alkali metal reservoir at the surface of said substrate.

US Pat. No. 10,511,011

ELECTROLYTE IMPREGNATION APPARATUS

LG Chem, Ltd., Seoul (KR...

1. An electrolyte impregnation apparatus comprising:a pressing unit comprising a pressing plate that presses a battery cell in which an electrode assembly and an electrolyte are accommodated; and
an ultrasonic vibration unit installed to a portion or the whole of the pressing plate to apply ultrasonic vibration to the battery cell,
wherein the ultrasonic vibration unit comprises:
an ultrasonic vibration element applying the ultrasonic vibration to the battery cell;
a fixing member for fixing the ultrasonic vibration element to the pressing surface of the pressing plate; and
a protection cover having flexibility disposed on an outer circumferential surface of the fixing member.

US Pat. No. 10,511,006

LAYERED BATTERY MODULE SYSTEM AND METHOD OF ASSEMBLY

CPS TECHNOLOGY HOLDINGS L...

1. A battery module comprising:a lower housing;
a plurality of battery cells, wherein the plurality of battery cells are electrically coupled together to produce a voltage;
a lid assembly disposed over the battery cells and coupled to the lower housing, wherein the lid assembly comprises a lid and a plurality of bus bar interconnects mounted on the lid;
a printed circuit board (PCB) assembly disposed on and coupled to the lid assembly, wherein the PCB assembly comprises a PCB, and wherein the PCB assembly comprises a high current interconnect configured to receive an upward facing bladed component disposed beneath the PCB and a downward facing bladed component disposed above the PCB to mechanically and electrically couple the upward facing bladed component and the downward facing bladed component to one another; and
a cover disposed over and coupled to the lower housing to hermetically seal the battery module.

US Pat. No. 10,511,005

BATTERY PACK AND VEHICLE CONTAINING BATTERY PACK

LG CHEM, LTD., Seoul (KR...

1. A battery pack, comprising:a pack case forming an appearance of the battery pack;
a battery module assembly provided in the pack case and having at least one battery module; and
a service plug configured to electrically connect the battery module assembly or cut off the electric connection of the battery module assembly, the service plug having a plug bus bar directly connected to the battery module assembly, the service plug including:
a plug body mounted to the pack case, the plug bus bar being provided at a lower portion of the plug body; and
a plug cover detachably mounted to the plug body,
wherein the plug body has a bus bar opening provided above the plug bus bar to expose the plug bus bar when the plug cover is separated,
wherein the plug bus bar is coupled to the battery module assembly by means of at least one coupling member, and
wherein the at least one coupling member passes through the bus bar opening when the plug bus bar and the battery module assembly are coupled.

US Pat. No. 10,511,002

BATTERY MODULE

PANASONIC INTELLECTUAL PR...

1. A battery module comprising:a case body for storing a plurality of cells each having an exhaust gas valve;
an exhaust passage for releasing an exhaust gas to an outside of the case body, the exhaust gas having come from the plurality of cells; and
a flow route changing unit disposed in the exhaust passage, the flow route changing unit being used for elongating a flow route of the exhaust gas from an upstream side to a downstream side of the exhaust passage by changing a flow direction of the exhaust gas a plurality of times in a zigzag manner along at least one direction of a width direction and a height direction of the exhaust passage,
wherein the flow route changing unit includes a plurality of plate portions, each of the plurality of plate portions includes a plurality of paths for passing the exhaust gas.

US Pat. No. 10,511,000

BATTERY PACK

SAMSUNG SDI CO., LTD., Y...

1. A battery pack, comprising:a battery with an electrode terminal connected to a lead tab;
a metal holder to accommodate the battery; and
an insulating holder spacing apart the metal holder from the battery, the insulating holder including a coupling part, the coupling part coupling between the insulation holder and the metal holder, and the lead tab being connected to the electrode terminal through an opening in the insulating holder,
wherein the insulating holder has a ring shape that at least partially surrounds a circumference of an end of the battery.

US Pat. No. 10,510,999

CELL COVER FOR SECONDARY BATTERY HAVING BOTTOM SURFACE CONFORMING TO A COOLING PLATE, AND BATTERY MODULE COMPRISING SAME

LG CHEM, LTD., Seoul (KR...

1. A battery module, comprising:a cell cover for a secondary battery, which accommodates at least one secondary battery in an internal space; and
a cooling plate,
wherein the cell cover comprises:
a first side plate and a second side plate facing each other to form opposite side surfaces of the internal space;
a top plate forming a top surface of the internal space and connecting upper edges of the first side plate and the second side plate; and
a first bottom plate extending from a lower edge of the first side plate and a second bottom plate extending from a lower edge of the second side plate to face the first bottom plate, the first bottom plate and the second bottom plate forming a bottom surface of the internal space,
wherein a top surface of the cooling plate comprises a groove, the first bottom plate and the second bottom plate of the cell cover contacting the groove,
wherein the lower edge of the first side plate and the lower edge of the second side plate are in a first plane, and
wherein the first bottom plate and the second bottom plate are inclined downwardly at an angle with respect to the first plane.

US Pat. No. 10,510,996

BATTERY

LG CHEM, LTD., Seoul (KR...

1. A battery comprising:a first surface having a perimeter of a closed curve defined by a first curved side and a second curved side connected to the first curved side;
a second surface having a perimeter of a closed curve defined by a first curved side and a second curved side; and
a volume portion configured to connect the first surface to the second surface, the volume portion having a first surface connecting the first curved side of the first surface to the first curved side of the second surface and a second surface connecting the second curved side of the first surface to the second curved side of the second surface,
wherein the first surface has an area different from that of the second surface.

US Pat. No. 10,510,992

METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a light-emitting device, comprising:providing first and second electrodes over a substrate;
providing a first organic layer over the first electrode and a second organic layer over the second electrode;
providing a third electrode over the second organic layer to form a light-emitting element comprising the second and third electrodes, and the second organic layer;
providing a support over the first electrode and the light-emitting element with a resin layer therebetween;
making a cut overlapping with the first electrode in at least the support;
partly removing the resin layer by using the cut to form an opening overlapping with the first electrode; and
removing the first organic layer remaining on the first electrode after foaming the opening,
wherein the first and second organic layers each contain a light-emitting substance.

US Pat. No. 10,510,989

ELECTROLUMINESCENT DEVICE

SHARP KABUSHIKI KAISHA, ...

1. An electroluminescent device comprising:a flexible base;
a functional layer including an electroluminescent element provided on the base; and
an adjustment layer that has heat dissipating properties and that adjusts a neutral surface of the electroluminescent device,
wherein the adjustment layer is provided on an electroluminescent element side relative to a center of the electroluminescent device in a film thickness direction and adjusts a maximum strain in the functional layer to 1% or less.

US Pat. No. 10,510,986

ENCAPSULATION STRUCTURE FOR FLEXIBLE DISPLAY AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. An encapsulation structure for a flexible display having an OLED lighting device on a flexible substrate, the encapsulation structure disposed on the OLED lighting device, comprising a stack of layers for preventing moist from permeating into the OLED lighting device; wherein the stack of layers comprising at least one first organic layer and at least two inorganic layers wrapping the at least one first organic layer; and two inorganic layers of the stack of layers have interfacing faces that contact each other and separate the at least one first organic layer into a plurality of independent geometric regions; wherein the stack of layers comprise one or more first layer sets stacked together; each first layer set comprises two inorganic layers and a first organic layer wrapped between the two inorganic layers; and the two inorganic layers of each first layer set have interfacing faces that contact each other and separate the first organic layer into a plurality of independent geometric regions; wherein the first organic layer comprises a plurality of independent blocks; each block has a spindle shape whose cross-sectional area decreases from a middle section towards its two lateral ends.

US Pat. No. 10,510,985

POLYMER HARD COAT AND METHODS OF PREPARATION

MOTOROLA MOBILITY LLC, C...

1. A hard coat, comprising:additive particles dispersed in a polymer, wherein the additive particles are silicon dioxide, the hard coat is formed from a dispersion applied to a front side of a polyimide (PI) substrate with a thickness of 0.05 millimeters (mm) and 57.8 wt % silicon dioxide, the dispersion is applied to a back side of the PI substrate with 35.3 wt % silicon dioxide, the hard coat has a haze of at most 0.5% and a transmission of at least 90%, wherein the dispersion comprises a polymerizable monomer, a dispersant, and a solvent, and
the hard coat may be bent to a diameter of at least 10 mm without breaking, bucking or delaminating.

US Pat. No. 10,510,979

COMPOSITE TRANSPARENT ELECTRODE, OLED AND METHOD FOR MANUFACTURING THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting diode, comprising a first electrode, a second electrode, and an organic light-emitting functional layer located between the first electrode and the second electrode, wherein the second electrode is a composite transparent electrode, the composite transparent electrode comprising:a metal layer;
a transparent conducting oxide layer, wherein the transparent conducting oxide layer is located on a side of the metal layer away from the organic light-emitting functional layer; and
a transparent cover layer located between the metal layer and the transparent conducting oxide layer,
wherein the metal layer is electrically connected to the transparent conducting oxide layer;
wherein the transparent cover layer has at least one first through-hole, through which the metal layer is electrically connected to the transparent conducting oxide layer;
wherein the at least one first through-hole comprises a material of the transparent conducting oxide layer therein; and
wherein the at least one first through-hole is a bar-shaped structure.

US Pat. No. 10,510,978

LIGHT EMITTING ELEMENT USING CHARGE GENERATING LAYER FORMED THROUGH SOLUTION PROCESS AND METHOD FOR MANUFACTURING SAME

UNIVERSITY-INDUSTRY COOPE...

1. A light-emitting element comprising an anode, a cathode, a light-emitting layer, and a charge-generating layer, wherein the charge-generating layer comprises a p-type layer of an organic semiconductor and an n-type layer of an oxide semiconductor formed by way of a solution process in a layer-by-layer structure, and wherein a thickness ratio between the p-type layer and the n-type layer ranges from 1:0.5 to 1:2.

US Pat. No. 10,510,975

LIGHT EMITTING DIODE AND LIGHT EMITTING DIODE DISPLAY INCLUDING THE SAME

Samsung Display Co., Ltd....

18. A light emitting diode display, comprising:a substrate;
a thin film transistor on the substrate; and
a light emitting diode connected to the thin film transistor,
wherein:
the light emitting diode includes a first electrode, a second electrode overlapping the first electrode, an emission layer between the first electrode and the second electrode, and an electron injection layer between the second electrode and the emission layer,
the electron injection layer includes a lanthanide element, an alkali metal first element, and a halogen second element,
the lanthanide element is ytterbium (Yb), samarium (Sm), or europium (Eu),
the first element is potassium (K), rubidium (Rb), or cesium (Cs),
the second element is chlorine (Cl), bromine (Br), or iodine (I), and
the first element and the second element are included in the electron injection layer in an amount of 1 vol % to 20 vol %, and the lanthanide element is included in the electron injection layer in an amount of 99 vol % to 80 vol %, based on a total volume of a material including the lanthanide element, the first element, and the second element.

US Pat. No. 10,510,973

COLOR-STABLE ORGANIC LIGHT EMITTING DIODE STACK

Universal Display Corpora...

1. An organic light emitting device, comprising:an anode, and a hole-transport layer;
a hybrid blue emissive stack that includes a fluorescent blue dopant and a phosphorescent blue dopant, the hybrid blue emissive stack disposed over the hole-transport layer, and the hole-transport layer positioned between the anode and the hybrid blue emissive stack;
a charge-generation layer disposed over the hybrid blue emissive stack;
an emissive stack disposed over the charge-generation layer, the emissive stack includes N emissive layers, and N is an integer of at least 3, wherein at least one middle emissive layer in the emissive stack other than the first and the Nth emissive layers emits light in a different color region than the first and the Nth emissive layers, and the difference between the emission peak of the first emissive layer and the emission peak of the Nth emissive layer in the emissive stack is less than about 10 nm;
wherein at least one of the middle emissive layers has a thickness that is ten times a thickness of the first emissive layer; and
wherein the different color region is represented by a peak emission greater than about 10 nm;
an electron-transport layer disposed over the emissive stack; and
a cathode disposed over the electron-transport layer.

US Pat. No. 10,510,969

DISPLAY DEVICE HAVING A PIXEL INCLUDING SEMICONDUCTOR LAYERS HAVING DIFFERENT SEMICONDUCTOR MATERIALS

Japan Display Inc., Toky...

1. A display device including a plurality of pixels arranged on a surface of a substrate, each of the plurality of pixels comprising:a light-emitting element;
a driving transistor;
a selecting transistor; and
a retention capacitor, wherein
the driving transistor has a bottom-gate structure, and includes a semiconductor layer containing a first semiconductor material,
the selecting transistor includes a semiconductor layer containing a second semiconductor material different from the first semiconductor material,
the retention capacitor has a first electrode and a second electrode,
the first electrode doubles as a gate of the driving transistor,
the second electrode is disposed at a lower layer than the first electrode with an insulating layer interposed therebetween and contains the second semiconductor material, and
the selecting transistor has a gate disposed at the same layer as the gate of the driving transistor.

US Pat. No. 10,510,966

ORGANIC LIGHT-EMITTING DEVICE

SAMSUNG ELECTRONICS CO., ...

1. An organic light-emitting device comprising:a first electrode;
a second electrode facing the first electrode; and
an organic layer disposed between the first electrode and the second electrode,
wherein the organic layer comprises an emission layer,
wherein the emission layer comprises a host and a dopant,
wherein the dopant comprises a condensed cyclic compound represented by Formula 1, and
wherein an amount of the dopant is smaller than that of the host:

wherein, in Formula 1, Ar1 is a group represented by Formula 1A, and Ar2 is a group represented by Formula 1B,
in Formula 1A, ring A1 is a group represented by Formula 2A, and ring A2 is a group represented by Formula 2B,
in Formulae 1A, 1B, 2A, and 2B,
X1 is C(R1) or N, X2 is C(R2) or N, X3 is C(R3) or N, X4 is C(R4) or N, X5 is C(R5) or N, X6 is C(R6) or N, X7 is C(R7) or N, and X8 is C(R8) or N,
X11 is selected from S, N[(L11)a11-(R11)b11], Si[(L11)a11-(R11)b11][(L12)a12-(R12)b12], and Ge[(L11)a11-(R11)b11][(L12)a12-(R12)b12],
X21 is C(R21) or N, X22 is C(R22) or N, X23 is C(R23) or N, X24 is C(R24) or N, and X25 is C(R25) or N,
X26 is C(R26), N, or a binding site to Ar1, X27 is C(R27), N, or a binding site to Ar1 X28 is C(R28), N, or a binding site to Ar1, X29 is C(R29), N, or a binding site to Ar1, and X30 is C(R30), N, or a binding site to Ar1,
at least one selected from X21 to X30 is N, and at least one selected from X26 to X30 is a binding site to Ar1,
L11 and L12 are each independently selected from a substituted or unsubstituted C3-C10 cycloalkylene group, a substituted or unsubstituted C1-C10 heterocycloalkylene group, a substituted or unsubstituted C3-C10 cycloalkenylene group, a substituted or unsubstituted C1-C10 heterocycloalkenylene group, a substituted or unsubstituted C6-C60 arylene group, a substituted or unsubstituted C1-C60 heteroarylene group, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group,
a11 and a12 are each independently an integer selected from 0 to 3,
R1 to R12 and R21 to R30 are each independently hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C7-C60 arylalkyl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted C1-C60 heteroaryloxy group, a substituted or unsubstituted C1-C60 heteroarylthio group, a substituted or unsubstituted C2-C60 heteroarylalkyl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —Si(Q1)(Q2)(Q3), —N(Q4)(Q5), and —B(Q6)(Q7),
b11 and b12 are each independently an integer selected from 1 to 3,
the number of a cyano group(s) included in the condensed cyclic compound represented by Formula 1 is 1 or greater, provided that Ar1 comprises at least one cyano group,
* indicates a binding site to a neighboring atom,
at least one substituent selected from the substituted C3-C10 cycloalkylene group, the substituted C1-C10 heterocycloalkylene group, the substituted C3-C10 cycloalkenylene group, the substituted C1-C10 heterocycloalkenylene group, the substituted C6-C60 arylene group, the substituted C1-C60 heteroarylene group, the substituted divalent non-aromatic condensed polycyclic group, the substituted divalent non-aromatic condensed heteropolycyclic group, the substituted C1-C60 alkyl group, the substituted C2-C60 alkenyl group, the substituted C2-C60 alkynyl group, the substituted C1-C60 alkoxy group, the substituted C3-C10 cycloalkyl group, the substituted C1-C10 heterocycloalkyl group, the substituted C3-C10 cycloalkenyl group, the substituted C1-C10 heterocycloalkenyl group, the substituted C6-C60 aryl group, the substituted C6-C60 aryloxy group, the substituted C6-C60 arylthio group, the substituted C7-C60 arylalkyl group, the substituted C1-C60 heteroaryl group, the substituted C1-C60 heteroaryloxy group, the substituted C1-C60 heteroarylthio group, the substituted C2-C60 heteroarylalkyl group, the substituted monovalent non-aromatic condensed polycyclic group, and the substituted monovalent non-aromatic condensed heteropolycyclic group is selected from:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C7-C60 arylalkyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryloxy group, a C1-C60 heteroarylthio group, a C2-C60 heteroarylalkyl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q11)(Q12)(Q13), —N(Q14)(Q15), and —B(Q16)(Q17);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C7-C60 arylalkyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryloxy group, a C1-C60 heteroarylthio group, a C2-C60 heteroarylalkyl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C7-C60 arylalkyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryloxy group, a C1-C60 heteroarylthio group, a C2-C60 heteroarylalkyl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one selected from deuterium, —F, —CI, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C7-C60 arylalkyl group, a C1-C60 heteroaryl group, a C1-C60 heteroaryloxy group, a C1-C60 heteroarylthio group, a C2-C60 heteroarylalkyl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q21)(Q22)(Q23), —N(Q24)(Q25), and —B(Q26)(Q27); and
—Si(Q31)(Q32)(Q33), —N(Q34)(Q35), and —B(Q36)(Q37), and
Q1 to Q7, Q11 to Q17, Q21 to Q27, and Q31 to Q37 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C7-C60 arylalkyl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted C1-C60 heteroaryloxy group, a substituted or unsubstituted C1-C60 heteroarylthio group, a substituted or unsubstituted C2-C60 heteroarylalkyl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,510,961

ORGANIC LIGHT EMITTING HOST MATERIALS

Nitto Denko Corporation, ...

1. A host compound for use in emissive elements of organic light emitting devices, the compound being represented by Formula 1:
wherein R1, R2, R3, R4, R5, and R6 are independently H, C1-C3 alkyl, or C1-3 perfluoroalkyl;
wherein Ar1 and Ar2 are independently optionally substituted 1,4-interphenylene or 1,3-interphenylene, wherein n is 0, 1, or 2; and m is 0, 1, or 2;
HT is

ET is optionally substituted 3,3?-bipyridin-5-yl, optionally substituted quinolin-8-yl, optionally substituted quinolin-5-yl, or optionally substituted quinoxalin-5-yl.

US Pat. No. 10,510,957

SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method of fabricating an electronic device comprising:forming, on a substrate, a first access line layer and a first self-selecting memory stack on the first access line layer, wherein the first self-selecting memory stack comprises a barrier material layer and a first layer of chalcogenide glass for both selection and storage;
etching, in a first etching operation, the first access line layer and the first self-selecting memory stack to form a first set of rows extending in a first direction on the substrate, each row of the first set of rows comprising remaining portions of the first access line layer and the first self-selecting memory stack;
forming a second access line layer and a second self-selecting memory stack on the first set of rows, wherein the second self-selecting memory stack comprises a second layer of chalcogenide glass for both selection and storage;
etching, in a second etching operation, the second access line layer and the second self-selecting memory stack to form a first set of columns extending in a second direction on the first set of rows, each column of the first set of columns comprising remaining portions of the second access line layer and the second self-selecting memory stack; and
etching, in the second etching operation, portions of the first set of rows located between adjacent columns of the first set of columns to form a first set of memory cells, wherein etching the portions of the first set of rows comprises etching a portion of the first memory stack and stopping the second etching operation while etching the barrier material layer of the first memory stack to leave a remaining portion of the barrier material layer of the first memory stack as a shunt for the first access line layer.

US Pat. No. 10,510,953

TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT

Taiwan Semiconductor Manu...

18. A method, comprising:forming a resistive random access memory (RRAM) stack over a semiconductor substrate, the RRAM stack including a bottom electrode, a top electrode over the bottom electrode, and a dielectric layer separating the bottom electrode from the top electrode;
forming a blocking layer over a top surface of the top electrode;
etching back the blocking layer to expose a first part of the top surface of the top electrode while leaving a portion of the blocking layer covering a second part of the top surface of the top electrode; and
forming a contact contacting an upper surface of the blocking layer and contacting the second part of the top surface of the top electrode.

US Pat. No. 10,510,952

STORAGE DEVICE WITH COMPOSITE SPACER AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A storage device, comprising:a first electrode;
a stacked feature over the first electrode and comprising a storage element and a second electrode over the storage element;
first and second spacers positioned respectively on first and second sidewalls of the second electrode of the stacked feature, wherein each of the first and second spacers has a notched top surface and the notched top surface of the first spacer is at a different level than the notched top surface of the second spacer;
a second via plug disposed above the second electrode and including a first sidewall aligned with a top surface of the second electrode and a second sidewall opposite to the first sidewall and misaligned with the top surface of the second electrode; and
a barrier structure embedded in a lateral of the first spacer.

US Pat. No. 10,510,951

LOW TEMPERATURE FILM FOR PCRAM SIDEWALL PROTECTION

Taiwan Semicondutor Manuf...

1. A method for forming a phase change random access memory (PCRAM) device, the method comprising:forming a memory stack over an insulator layer;
performing a first etch process to pattern the memory stack defining a memory cell, wherein the memory cell comprises a top electrode overlying a dielectric layer, wherein the dielectric layer comprises a center region laterally between a first outer region and a second outer region, wherein an etchant used in the first etch process creates a compound in the first and second outer regions, and wherein the compound has a first melting point temperature; and
performing a first deposition process to form a first sidewall spacer over the memory cell, wherein the first sidewall spacer is in direct contact with outer sidewalls of the memory cell, and wherein the first deposition process reaches a first maximum temperature less than the first melting point temperature.

US Pat. No. 10,510,939

THERMOELECTRIC CONVERSION CELL AND THERMOELECTRIC CONVERSION MODULE

MITSUBISHI MATERIALS CORP...

1. A thermoelectric conversion cell comprising:an insulating member having at least one through hole, and having insulation-side threaded portions at respective end parts of the through hole in a through-direction;
a thermoelectric conversion member having at least one thermoelectric conversion element and enclosed in the through hole; and
an electrode member having electrode-side threaded portions corresponding to the insulation-side threaded portions respectively connected to end parts of the insulating member and an electrode part electrically connected to an end part of the thermoelectric conversion member in the through hole.

US Pat. No. 10,510,937

INTERCONNECTION BY LATERAL TRANSFER PRINTING

X-Celeprint Limited, Cor...

1. A transfer print structure, comprising:a destination substrate having a substrate surface and one or more substrate conductors disposed on or in the destination substrate; and
one or more interconnect structures disposed on and protruding from the destination substrate in a direction orthogonal to the substrate surface, each of the one or more interconnect structures comprising one or more notches, each of the one or more notches (i) having an opening on an edge of the interconnect structure and extending at least partially through the interconnect structure in a direction parallel to the substrate surface from the edge of the interconnect structure, (ii) comprising a notch conductor disposed at least partially in the notch and (iii) electrically connected to at least one of the one or more substrate conductors.

US Pat. No. 10,510,936

LIGHT EMITTING DEVICE PACKAGE INCLUDING A LEAD FRAME

SAMSUNG ELECTRONICS CO., ...

1. A light-emitting device package, comprising:a lead frame comprising a first lead and a second lead that include metal and are spaced apart from each other;
a light-emitting device chip mounted on a first area of the lead frame, the first area of the lead frame including a part of the first lead and a part of the second lead;
a molding structure comprising an outer barrier surrounding an outside of the lead frame and an inner barrier, wherein the molding structure fills between the first lead and the second lead; and
a plurality of slots formed in each of the first lead and the second lead, wherein the plurality of slots are filled by the molding structure,
wherein the inner barrier divides the lead frame into the first area and a second area, the second area being located outside of the first area, and
wherein at least one of the plurality of slots penetrates the lead frame from a lower surface to an upper surface of the lead frame, and extends inwardly from an outer periphery of the lead frame when viewed from above.

US Pat. No. 10,510,935

OPTOELECTRONIC COMPONENT HAVING A LEAD FRAME WITH A STIFFENING STRUCTURE

OSRAM Opto Semiconductors...

1. An optoelectronic component comprising at least one optoelectronic semiconductor chip, wherein the at least one optoelectronic semiconductor chip is arranged on top of a leadframe section, the leadframe section comprises a stiffening structure projecting away laterally from the leadframe section, and the leadframe section, the stiffening structure and the at least one optoelectronic semiconductor chip are embedded in an electrically insulating housing, wherein an electrical line is applied on a surface of a top side of the housing, and the electrical line electrically contacts the at least one optoelectronic semiconductor chip.

US Pat. No. 10,510,933

LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF

Seoul Semiconductor Co., ...

1. A light-emitting diode package, comprising:a housing including a top surface opposite a bottom surface;
a light-emitting diode chip disposed in the housing;
a first phosphor configured to emit green light;
a second phosphor configured to emit a first red light; and
a third phosphor configured to emit a second red light,
wherein:
the top surface of the housing include a lower portion, an upper portion and an intermediate portion between the lower portion and the upper portion,
the light-emitting diode chip has a Full Width at Half Maximum (FWHM) less than or equal to about 40 nm,
the first, second, and third phosphors are disposed in a molding part and the molding part is made of materials including at least one of silicone, epoxy, polymethylmethacrylate (PMMA), polyethylene (PE) and polystyrene (PS),
a peak wavelength of the first phosphor ranges from about 520 nm to 570 nm,
at least one of the second and third phosphors is a nitride-based phosphor,
the first red light emitted from the second phosphor and the second red light emitted from the third phosphor have different peak wavelengths in which one of the different peak wavelengths ranges from about 610 nm to about 650 nm and the other different peak wavelength ranges from about 600 nm to 670 nm,
at least one of the first, second, and third phosphors has a different Full Width at Half Maximum (FWHM) from the other of the first, second, and third phosphors, and
a white light is configured to be formed by a synthesis of light emitted from the light-emitting diode chip, the first phosphor, the second phosphor and the third phosphor.

US Pat. No. 10,510,929

LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE

LG INNOTEK CO., LTD., Se...

1. A light emitting device comprising:a light emitting structure including a first conductivity type semiconductor layer, an active layer on the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer on the active layer;
a transmissive electrode layer including a metal oxide layer on the second conductivity type semiconductor layer;
an insulating layer on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer;
a first electrode on the first conductivity type semiconductor;
a second electrode on the second conductivity type semiconductor layer, wherein the first electrode includes a first portion and a second portion, and wherein the first portion of the first electrode contacts the first conductivity type semiconductor layer and has an area of 10% to 95% of a top surface of the first electrode.

US Pat. No. 10,510,927

METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR DEVICE

NICHIA CORPORATION, Anan...

1. A method for producing a nitride semiconductor device, the method comprising:providing a substrate made of a material other than a nitride semiconductor,
wherein the material has a hexagonal crystal structure;
wherein an upper face of the substrate has at least one flat section;
growing a first nitride semiconductor layer on the upper face of the substrate,
wherein the first nitride semiconductor layer is made of monocrystalline AlN;
wherein the first nitride semiconductor layer has an upper face that is a +c plane;
wherein the first nitride semiconductor layer has a thickness in a range of 10 nm to 100 nm;
growing a second nitride semiconductor layer on the upper face of the first nitride semiconductor layer,
wherein the second nitride semiconductor layer is made of InXAlYGa1-X-YN (0?X, 0?Y, X+Y<1);
wherein the second nitride semiconductor layer is grown to have an upper face with at least one flat section after a plurality of upside-down hexagonal pyramid-shaped or upside-down hexagonal frustum-shaped recesses are created in the second nitride semiconductor layer above the at least one flat section of the upper face of the substrate;
wherein the recesses are substantially eliminated before a thickness of the second nitride semiconductor layer grows to 800 nm.

US Pat. No. 10,510,926

ULTRAVIOLET LIGHT EMITTING DIODE AND LIGHT EMITTING DIODE PACKAGE

LG INNOTEK CO., LTD., Se...

1. An ultraviolet light emitting device comprising:a first conductive-type semiconductor layer;
an active layer comprising a multiple quantum barrier and a multiple quantum well and disposed on the first conductive-type semiconductor layer;
a second conductive-type first semiconductor layer disposed on the active layer;
an electron blocking layer disposed between the active layer and the second conductive-type first semiconductor layer; and
a second conductive-type second semiconductor layer disposed between the last quantum wall of the active layer and the electron blocking layer,
wherein the second conductive-type second semiconductor layer includes a p-type Alx1Ga1-x1N layer (0?x1?1) and a p-type InyAlx2Ga1-y-x2N layer (0?x2?1, 0?y?1, 0?x2+y?1).

US Pat. No. 10,510,924

MULTI-HETEROJUNCTION NANOPARTICLES, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME

The Board of Trustees of ...

1. A semiconducting nanoparticle comprising:a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and
two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and
where the first semiconductor and the second semiconductor are chemically different from each other, and the first endcaps contact the first end and the second end tangentially.

US Pat. No. 10,510,922

GROUP III-V QUANTUM DOT AND MANUFACTURING METHOD THEREOF

Zhejiang University, Han...

1. A process for producing group III-V quantum dots, comprising:heating a mixture of group II and group III element precursors in a solution;
adding a group V element precursor to the mixture and heating to form a first solution containing group III-V quantum dot cores;
adding a first group VI element precursor to the first solution to form group III-V/group II-VI core/shell particles;
purifying the group III-V/group II-VI core/shell particles;
dispersing the purified group III-V/group II-VI core/shell particles in a second solution;
adding activation agent and a group II element precursor to the second solution;
heating the second solution; and
adding a second group VI element precursor to the heated second solution to form group III-V/group II-VI/group II-VI core/shell/shell particles.

US Pat. No. 10,510,920

SILANIZED ITO ELECTRODE WITH ITO NANOPARTICLES FOR AQUEOUS SULFIDE DETECTION

King Fahd University of P...

1. An ITONP-modified ITO electrode, comprising:a silanized ITO (indium tin oxide) electrode; and
ITO nanoparticles on the surface of the silanized ITO electrode, wherein the ITO nanoparticles have diameters of 10-210 nm.

US Pat. No. 10,510,916

COMPONENT FOR DETECTING UV RADIATION AND METHOD FOR PRODUCING A COMPONENT

OSRAM OPTO SEMICONDUCTORS...

1. A component for detecting ultraviolet radiation comprising:a semiconductor body comprising a first semiconductor layer of a first charge carrier type, a second semiconductor layer of a second charge carrier type and an intermediate active layer located therebetween,
wherein the semiconductor body is based on AlmGa1-n-mInnN with 0?n?1, 0?m?1 and n+m<1,
wherein the first semiconductor layer is n-doped,
wherein the second semiconductor layer is p-doped,
wherein the active layer is formed with respect to its material composition in such a way that during operation of the component, arriving ultraviolet radiation is absorbed by the active layer for generating charge carrier pairs,
wherein the active layer is relaxed with respect to its lattice constant, and
wherein the first semiconductor layer is strained with respect to its lattice constant.

US Pat. No. 10,510,915

POROUS SILICON NANOWIRE PHOTOVOLTAIC CELL

United Arab Emirates Univ...

1. A porous silicon nanowire photovoltaic cell, comprising:a first electrode;
an p-type silicon layer;
a second electrode comprising a transparent electrode and at least one metal contact;
a photoactive layer comprising a vertical array of porous silicon nanowires partially embedded in an indium tin oxide filler, wherein each said porous silicon nanowires comprises a porous p-type silicon core coated with a layer of n-type silicon, the photoactive layer being positioned between the p-type silicon layer and the second electrode, the second electrode making direct contact with the layer of n-type silicon; and
a down-conversion layer completely filling a space between the second electrode and the indium tin oxide filler of the photoactive layer.

US Pat. No. 10,510,914

TRANSPARENT ENERGY-HARVESTING DEVICES

Board of Trustees of Mich...

1. An energy harvesting system comprising a waveguide, and a sole waveguide redirecting material embedded in the waveguide, the waveguide coupled to either at least one solar photovoltaic array or at least one solar photovoltaic cell,wherein the sole waveguide redirecting material is visibly transparent and selectively harvests and emits light in a near-infrared (NIR) region of the electromagnetic spectrum by having a strongest peak absorbance of light at a wavelength of greater than about 650 nm and a strongest peak emission of light at a wavelength of greater than about 650 nm,
wherein the sole waveguide redirecting material creates luminescence with a quantum yield of greater than about 20%,
wherein the sole waveguide redirecting material is selected from the group consisting of 2-[7-(1,3-dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3,5 heptatrienyl]-1,3,3-trimethyl-3H-indolium iodide (HITCI), 2-[2-[2-Chloro-3-[(1,3-dihydro-3,3-dimethyl-1-propyl-2H-indol-2 ylidene)ethylidene]-1-cyclohexen-1-yl]ethenyl]-3,3-dimethyl-1-propylindolium iodide (IR780), 3-(6-(2,5-dioxopyrrolidin-1-yloxy)-6-oxohexyl)-1,1-dimethyl-2-((E)-2-((E)-3((E)-2-(1,1,3-trimethyl-1H-benzo[e]indol-2(3H)-ylidene)ethylidene)cyclohex-1-enyl)vinyl)-1H-benzo[e]indolium chloride, 1-(6-,(2,5-dioxopyrrolidin-1-yloxy)-6-oxohexyl)-3,3-dimethyl-2-((E)-2-((E)-3-((E)-2-(1, 3,3-trimethylindolin-2-ylidene)ethylidene)cyclohex-1-enyl)vinyl)-3H-indolium chloride (Cy7 NHS ester; “CY”), 1,1-dimethyl-3-(6-oxo-6-(prop-2-ynylamino)hexyl)-2-((1E,3E,5E)-5-(1,1,3-trimethyl-1H-benzo[e]indol-2(3H)-ylidene)penta-1,3-dienyl)-1H-benzo[e]indolium chloride (Cy5.5 alkyne), 1-(5-carboxypentyl)-3,3-dimethyl-2-((E)-2-((E)-3-((E)-2-(1,3,3-trimethylindolin-2-ylidene)ethylidene)cyclohex-1-enyl)vinyl)-3H-indolium chloride (Cy7 carboxylic acid), and combinations thereof,
wherein the energy harvesting system is visibly transparent, having an average visible transmittance of greater than about 50% and a color rendering index of greater than about 85 at normal incidence to the waveguide.

US Pat. No. 10,510,909

BACKSIDE-ILLUMINATED PHOTODETECTOR STRUCTURE AND METHOD OF MAKING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor region comprising:
a first doped region extending from a first top surface of the semiconductor region to a first intermediate level of the semiconductor region, wherein the first doped region is of a first conductivity type, and the first doped region comprises:
a contact region; and
a transverse region, wherein the transverse region comprises a first edge; and
a first reflecting region comprising:
a first portion over and contacting the first top surface of the semiconductor region, wherein the first portion comprises a second edge flushed with the first edge of the transverse region;
a second portion over and contacting a second top surface of the semiconductor region, wherein the second portion is higher than the first portion; and
a sidewall portion connecting the first portion to the second portion.

US Pat. No. 10,510,908

SOLAR CELL PANEL

LG ELECTRONICS INC., Seo...

1. A solar cell panel comprising:a plurality of solar cells comprising at least a first solar cell and a second solar cell; and
a plurality of leads to connect the first solar cell and the second solar cell,
wherein each of the first solar cell and the second solar cell comprises:
a semiconductor substrate;
a first passivation layer on a front surface of the semiconductor substrate;
a second passivation layer on a back surface of the semiconductor substrate;
a first conductivity type region on the first passivation layer at the front surface of the semiconductor substrate;
a second conductivity type region on the second passivation layer at the back surface of the semiconductor substrate;
a first electrode electrically connected to the first conductivity type region, the first electrode comprising a first metal electrode layer including a plurality of finger lines in a first direction and a plurality of first bus bars in a second direction crossing the first direction; and
a second electrode electrically connected to the second conductivity type region, the second electrode comprising a second metal electrode layer including a plurality of second bus bars in the second direction,
wherein the plurality of leads have a diameter or width of 100 to 500 ?m, and comprise 6 or more leads arranged at one surface side of the first or second solar cell,
wherein each of the plurality of leads comprises a core layer having a circular, oval or round shape and a solder layer coated on the entire outer surface of the core layer,
wherein the plurality of leads are connected to the plurality of first bus bars of the first solar cell and the plurality of second bus bars of the second solar cell by the solder layer, respectively,
wherein the solder layer includes a portion adjacent to the first or second electrode, and
wherein a width of the portion gradually increases toward the first or second electrode.

US Pat. No. 10,510,905

POWER SCHOTTKY DIODES HAVING CLOSELY-SPACED DEEP BLOCKING JUNCTIONS IN A HEAVILY-DOPED DRIFT REGION

Cree, Inc., Durham, NC (...

1. A Schottky diode, comprising:a drift region having an upper portion and a lower portion, the drift region doped with dopants having a first conductivity type;
a channel in the upper portion of the drift region, the channel having the first conductivity type;
a first blocking junction and a second blocking junction adjacent the first blocking junction in the upper portion of the drift region, the first and second blocking junctions defining the channel therebetween, the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type, the first and second blocking junctions extending between 1.0 and 2.0 microns into the upper portion of the drift region and being spaced apart from each other by less than 2.0 microns;
a first contact on the upper portion of the drift region; and
a second contact on the lower portion of the drift region and vertically spaced apart from the first contact,
wherein a doping concentration of the drift region is greater than 1.5×1016/cm3.

US Pat. No. 10,510,898

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR

IUCF-HYU (INDUSTRY-UNIVER...

1. A thin film transistor comprising:a substrate;
an active pattern, formed of ZnON, disposed on the substrate;
a protective pattern, formed of ZnO, directly disposed on the active pattern;
a gate electrode overlapping with the active pattern; and
a gate insulating layer, at least one portion of the gate insulating layer in a length direction being disposed between the gate electrode and the active pattern,
wherein the active pattern includes a channel therein.

US Pat. No. 10,510,893

METHOD FOR FABRICATING FINFET ISOLATION STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device, the method comprising:forming a stop layer on a semiconductor substrate;
forming a semiconductor fin on the stop layer;
forming two cells adjacent to each other on the semiconductor fin;
forming a gate conductor on a top of the semiconductor fin at a common boundary that is shared by the two cells;
forming a gate spacer peripherally enclosing the gate conductor;
forming an epitaxial layer at each of both sides of the gate conductor;
etching the gate conductor and the semiconductor fin to form a gap extending from the top of the semiconductor fin to the stop layer, thereby dividing the semiconductor fin into two portions of the semiconductor fin, and forming the epitaxial layer at one side of each of the two portions of the semiconductor fin; and
filling the gap with a dielectric filler.

US Pat. No. 10,510,892

FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES

International Business Ma...

1. A semiconductor device, comprising:one or more fins, each fin comprising:
a top channel portion formed from a channel material;
a middle portion, and
a bottom substrate portion formed from a same material as an underlying substrate, each of the top channel portion and the middle portion having a different width than the bottom substrate portion;
an isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins;
an oxide layer formed between the bottom substrate portion of each fin and the isolation layer, wherein a space extending to a depth below the top surface of the middle portion and above a bottom end of the bottom substrate portion exists between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer; and
a gate dielectric, protruding into the space and in contact with the middle portion, formed over the one or more fins and comprising a portion formed from a material different from the oxide layer.

US Pat. No. 10,510,891

FIELD EFFECT TRANSISTOR CONTACT WITH REDUCED CONTACT RESISTANCE USING IMPLANTATION PROCESS

Taiwan Semiconductor Manu...

1. A structure comprising:an active area on a substrate, the active area comprising a source/drain region, the source/drain region having a silicide layer disposed thereon, the source/drain region comprising:
a first region proximate a top surface of the source/drain region and overlapped with at least a portion of the silicide layer, the first region having a first concentration of germanium, the first region comprising gallium, a peak concentration of gallium being proximate the top surface of the source/drain region, a concentration of gallium decreasing in the source/drain region from the peak concentration of gallium in a direction away from the top surface of the source/drain region; and
a second region disposed between the first region and the substrate, the second region having a second concentration of germanium lower than the first concentration of germanium;
a dielectric layer over the active area; and
a conductive feature extending through the dielectric layer to the active area and contacting the source/drain region at the silicide layer.

US Pat. No. 10,510,889

P-TYPE STRAINED CHANNEL IN A FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate having an n-doped well feature;
an epitaxial silicon germanium fin formed over the n-doped well feature, the epitaxial silicon germanium fin having a lower part and an upper part, wherein the lower part has a lower germanium content than the upper part;
a channel in the epitaxial silicon germanium fin; and
lightly doped source-drain regions formed from the epitaxial silicon germanium fin, the lightly doped source-drain regions extending into the epitaxial silicon germanium fin, the lightly doped source-drain regions comprising a diffusion region having a dopant concentration decreasing from an interface between epitaxial source/drain regions and the epitaxial silicon germanium fin toward the channel, the lightly doped source-drain regions comprising an upper doped region over the diffusion region, the upper doped region having a uniform dopant concentration.

US Pat. No. 10,510,888

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming an alloy semiconductor material layer comprising a first element and a second element on a semiconductor substrate;
forming a mask on the alloy semiconductor material layer to provide a masked portion and an unmasked portion of the alloy semiconductor material layer; and
irradiating the unmasked portion of the alloy semiconductor material layer not covered by the mask with radiation from a radiation source to transform the alloy semiconductor material layer so that a surface region of the unmasked portion of the alloy semiconductor material layer has a higher concentration of the second element than an internal region of the unmasked portion of the alloy semiconductor material layer, wherein the surface region surrounds the internal region.

US Pat. No. 10,510,884

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor device, comprising:providing a semiconductor substrate;
forming a dummy gate on the semiconductor substrate, wherein the dummy gate has a first sidewall and a second sidewall opposite to the first sidewall;
forming a low-k dielectric layer on the first sidewall and the second sidewall of the dummy gate and the semiconductor substrate, wherein the dielectric constant of the low-k dielectric layer is smaller than or equal to 5, and wherein the low-k dielectric layer comprises silicon carbide (SiC) or black diamond;
partially etching the low-k dielectric layer on the second sidewall but not the first sidewall of the dummy gate, and partially etching the low-k dielectric layer on top of the dummy gate, so that the low-k dielectric layer is remained on the first sidewall, but not on the second sidewall of the dummy gate, and remained partially on top of the dummy gate;
depositing a spacer material layer on the low-k dielectric layer, the second sidewall of the dummy gate, and the semiconductor substrate;
etching the spacer material layer and the low-k dielectric layer to form a first spacer structure on the first sidewall and a second spacer structure on the second sidewall, wherein the first spacer structure has a bottom thickness that is greater than that of the second spacer structure, and the first spacer structure has a first spacer material layer and the low-k dielectric layer, but the second spacer structure has a second spacer material layer but does not have the low-k dielectric layer;
etching the semiconductor substrate to form a first recess adjacent to the first spacer structure and a second recess adjacent to the second spacer structure;
forming a first epitaxial layer in the first recess and a second epitaxial layer in the second recess;
forming a drain doping region in the semiconductor substrate adjacent to the first spacer structure and a source doping region in the semiconductor substrate adjacent to the second spacer structure; and
forming a first slot contact on the drain doping region and a second slot contact on the source doping region.

US Pat. No. 10,510,883

ASYMMETRIC SOURCE AND DRAIN STRUCTURES IN SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device, comprising:etching a first and a second source/drain structures on a first and a second fin structures in a first and a second active region, respectively, on a substrate by an etching gas mixture including a sulfur containing passivation gas, wherein the etching gas mixture etches the first source/drain structure at a faster etching rate than etching the second source/drain structure, the etching forming the first source/drain structure in the first active region having a first vertical height less than a second vertical height formed in the second source/drain structure in the second active region, wherein the first source/drain structure is n-type and the second source/drain structure is p-type.

US Pat. No. 10,510,881

METHOD OF PRODUCING A SYMMETRIC LDMOS TRANSISTOR

ams AG, Unterpremstaette...

1. A method of producing a symmetric LDMOS transistor, comprising:forming a well of a first type of conductivity in a semiconductor substrate;
forming wells of a second type of conductivity in the well of the first type of conductivity, the wells of the second type of conductivity being arranged at a distance from one another;
performing an implantation of dopants forming a doped region of the second type of conductivity in the well of the first type of conductivity, the doped region of the second type of conductivity being arranged between the wells of the second type of conductivity at a distance from the wells of the second type of conductivity;
applying source/drain contacts to the wells of the second type of conductivity and arranging a gate dielectric and a gate electrode above regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity, the gate electrode being provided with a gap above the doped region of the second type of conductivity;
forming a body contact region between the wells of the second type of conductivity, the body contact region comprising a series of contact islands arranged on a straight line at the same distance from the wells of the second type of conductivity; and
interconnecting separated portions of the doped region using an interconnecting doped region of the second type of conductivity, the interconnecting doped region being disposed between two contact islands of the series of contact islands.

US Pat. No. 10,510,879

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device, comprising:a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a third semiconductor layer of the first conductivity type provided on the second semiconductor layer;
a plurality of control electrodes provided respectively in a plurality of trenches, the plurality of trenches having depths into the first semiconductor layer from a top surface of the third semiconductor layer, the plurality of control electrodes having ends positioned in the first semiconductor layer;
an insulating region provided between a first control electrode and a second control electrode of the plurality of control electrodes, the first control electrode and the second control electrode being adjacent to each other in a first direction along an interface between the first semiconductor layer and the second semiconductor layer, the insulating region extending in a second direction from the third semiconductor layer toward the first semiconductor layer, the insulating region having an end positioned in the first semiconductor layer, the end of the insulating region being positioned at a level in the second direction lower than the level in the second direction of the ends of the plurality of control electrodes;
a fourth semiconductor layer of the second conductivity type provided between the insulating region and the first semiconductor layer, between the insulating region and the first control electrode, and between the insulating region and the second control electrode;
a first insulating film provided between the first control electrode and the fourth semiconductor layer, the fourth semiconductor layer being in contact with a whole portion of the first insulating film positioned between the first control electrode and the fourth semiconductor layer;
a second insulating film provided between the second control electrode and the fourth semiconductor layer, the fourth semiconductor layer being in contact with a whole portion of the second insulating film positioned between the second control electrode and the fourth semiconductor layer; and
a first electrode connected to the third semiconductor layer and the fourth semiconductor layer.

US Pat. No. 10,510,876

QUANTUM DOPING METHOD AND USE IN FABRICATION OF NANOSCALE ELECTRONIC DEVICES

1. A semiconductor device comprisinga substrate formed of a semiconductor material having a crystallographic orientation selected from the group consisting of <100>, <110>, and <111>, the substrate having a surface layer of atoms with a fixed number of unterminated bonds equal to an atomic surface density defined by the selected crystallographic orientation;
a single atomic layer of atoms of a dopant material attached to the surface layer in a self-limiting process that terminates the fixed number of unterminated bonds and creates a layer of dopant atoms of the same atomic surface density and having the same fixed number of unterminated bonds as the substrate surface layer; and
a plurality of N atomic layers of the semiconductor material disposed over the single atomic layer of atoms of dopant material, the value of N selected to create a specific volume dopant density equal to 1/N*(the atomic surface density divided by a known lattice spacing associated with the selected crystallographic orientation).

US Pat. No. 10,510,874

SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
a fin extending above the substrate; and
a plurality of isolation regions, wherein the fin is arranged between the two of the plurality of isolation regions, and one of the plurality of isolation regions comprises:
a first atomic layer deposition (ALD) layer implanted with an impurity;
a second ALD layer formed in the first ALD layer and implanted with the impurity, wherein a concentration of the impurity in the second ALD layer is higher than a concentration of the impurity in the first ALD layer;
a flowable chemical vapor deposition (FCVD) layer formed in the second ALD layer; and
a third ALD layer formed on the FCVD layer.

US Pat. No. 10,510,873

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate comprising a first semiconductor fin;
a first dielectric fin disposed over the substrate and in direct contact with a first sidewall of the first semiconductor fin, wherein a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin;
an isolation structure in contact with the first semiconductor fin and the first dielectric fin, wherein a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin; and
a metal gate structure crossing the first dielectric fin.

US Pat. No. 10,510,869

DEVICES AND METHODS FOR A POWER TRANSISTOR HAVING A SCHOTTKY OR SCHOTTKY-LIKE CONTACT

SILICET, LLC, Chapel Hil...

1. A power transistor structure comprising:a substrate, including:
a bottom substrate region of a first dopant polarity,
a drift region formed in or on the bottom substrate region, and
a body region;
a gate structure formed in or on the substrate;
a source region adjacent to the gate structure;
a drain region formed in or on the drift region; and
a conducting layer;
wherein the source region and/or the drain region is a contact, located substantially near a surface of the substrate, that establishes a rectifying barrier junction between the substrate and the conducting layer to provide immunity from parasitic bipolar action and thereby reduce or eliminate the amount of snapback in the drain-to-source current-voltage (I-V) characteristic of the power transistor structure; and
wherein non-continuous p+ body contacts are integrated into the source region to prevent the body region from floating.

US Pat. No. 10,510,868

FIN FIELD-EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming first spacers on opposing sidewalls of a first fin, wherein the first fin protrudes above a substrate;
recessing the first fin to form a first recess between the first spacers;
performing a cleaning process after recessing the first fin;
after the cleaning process, performing a baking process to change a profile of the first spacers, wherein the baking process is performed using a gas mixture comprising hydrogen, hydrofluoric acid, and germanium hydride, wherein the baking process curves inner sidewalls of the first spacers facing the first fin; and
forming a first semiconductor material over a top surface of the first fin after the baking process.

US Pat. No. 10,510,865

CAP LAYER AND ANNEAL FOR GAPFILL IMPROVEMENT

Taiwan Semiconductor Manu...

1. A method for semiconductor processing, the method comprising:performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate;
forming a dielectric cap layer on the conformal film;
performing an anneal process on the conformal film;
patterning the conformal film to form a dummy gate;
forming a dielectric layer along opposing sides of the dummy gate; and
removing the dummy gate.

US Pat. No. 10,510,863

POWER DEVICE HAVING A POLYSILICON-FILLED TRENCH WITH A TAPERED OXIDE THICKNESS

MAXPOWER SEMICONDUCTOR, I...

1. A semiconductor device comprising:a silicon-containing semiconductor material having a top surface;
a first trench etched into the top surface to a first depth, the first trench having sidewalls;
a tapered silicon dioxide layer, the tapered silicon dioxide layer comprising portions of the sidewalls of the trench that have been converted to the tapered silicon dioxide layer due to a portion of the silicon-containing semiconductor material being consumed by the tapered silicon dioxide layer, wherein there is greater consumption of the silicon-containing semiconductor material near a bottom of the first trench compared to near a top of the trench,
the tapering of the silicon dioxide layer being formed without etching the silicon dioxide layer;
a conductive material at least partially filling the first trench;
a first electrode overlying the silicon-containing semiconductor material; and
a second electrode, wherein current is conducted between the first electrode and second electrode when the device is turned on.

US Pat. No. 10,510,862

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a semiconductor layer;
a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion in a direction along a surface of the semiconductor layer, and a spacer provided between the first portion and the second portion; and
a first insulating layer provided between the semiconductor layer and the gate electrode, the first insulating layer including a first region containing at least one of a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing at least one of a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region,
wherein the first region is positioned between the first portion and the semiconductor layer,
the second region is positioned between the second portion and the semiconductor layer,
the boundary region is positioned between the spacer and the semiconductor layer, and
the boundary region has a chemical composition different from a chemical composition of the spacer.

US Pat. No. 10,510,859

REDUCED CAPACITANCE COUPLING EFFECTS IN DEVICES

GLOBALFOUNDRIES SINGAPORE...

1. A semiconductor device comprising:a substrate including a circuit component; and
an interlevel dielectric level over the substrate, the interlevel dielectric level including a first dielectric layer, a second dielectric layer over the first dielectric layer, and a plurality of metal lines over the first dielectric layer, the plurality of metal lines partially disposed in the second dielectric layer,
wherein the second dielectric layer is comprised of a ferroelectric material.

US Pat. No. 10,510,855

TRANSISTOR LAYOUT TO REDUCE KINK EFFECT

Taiwan Semiconductor Manu...

1. An integrated chip, comprising:a substrate having interior surfaces that define a trench within an upper surface of the substrate;
an isolation structure comprising one or more dielectric materials within the trench and having sidewalls that define an opening exposing the upper surface of the substrate;
a source region disposed within the upper surface of the substrate and having a first width extending along a first direction;
a drain region disposed within the upper surface of the substrate and having a second width extending along the first direction; and
a gate structure extending over a region of the upper surface that is between the source region and the drain region, wherein the region of the upper surface has a third width that extends along the first direction and that is larger than the first width and the second width.

US Pat. No. 10,510,849

METHOD FOR AUTO-ALIGNED MANUFACTURING OF A VDMOS TRANSISTOR, AND AUTO-ALIGNED VDMOS TRANSISTOR

STMICROELECTRONICS S.R.L....

1. A MOS transistor, comprising:a semiconductor body bounded by a first and a second side, the semiconductor body having a first type of conductivity and an axis of symmetry transverse to the first and second side;
a body region having a second type of conductivity, the body region extends into the semiconductor body from the first side;
a source region having the first type of conductivity, the source region extends into the body region from the first side;
a drain electrode on the second side of the semiconductor body;
a gate electrode that extends into the semiconductor body from the first side, the gate electrode laterally faces the source region and the body region in a symmetrical manner with respect to the axis of symmetry;
one or more structural regions disposed laterally to the gate electrode and are symmetrical with respect to the axis of symmetry, the one or more structural regions having a surface, the surface of the one or more structural regions being spaced farther apart from the second side of the semiconductor body than the first side of the semiconductor body is spaced apart from the second side of the semiconductor body so as to define a step between said surface of the one or more structural regions and the first side of the semiconductor body;
one or more spacers that surround a portion of the first side of the semiconductor body, said one or more spacers being symmetrical with respect to the axis of symmetry and adjacent to the one or more structural regions;
a source electrode in electrical contact with the source region at said portion of the first side surrounded by said one or more spacers, said source electrode being adjacent to the one or more spacers.

US Pat. No. 10,510,848

SUB-FIN SIDEWALL PASSIVATION IN REPLACEMENT CHANNEL FINFETS

Intel Corporation, Santa...

1. An integrated circuit including at least one transistor, the integrated circuit comprising:a substrate;
a semiconductor region including material different from the substrate, the semiconductor region being on a portion of the substrate and under a gate stack, wherein the semiconductor region includes a first portion laterally between portions of the gate stack, and a second portion not laterally between portions of the gate stack;
a first dielectric region and a second dielectric region, the second portion of the semiconductor region being laterally between the first and second dielectric regions, wherein the first and second dielectric regions include a first dielectric material, wherein both a first surface of the first dielectric region facing the gate stack and an opposite second surface of the first dielectric region include the first dielectric material;
a first dielectric layer laterally between the second portion of the semiconductor region and the first dielectric region, and not laterally between the first portion of the semiconductor region and the gate stack; and
a second dielectric layer laterally between the second portion of the semiconductor region and the second dielectric region, and not laterally between the first portion of the semiconductor region and the gate stack,
wherein the first and second dielectric layers include a second dielectric material different from the first dielectric material, and wherein a section of the first dielectric layer is between the first dielectric region and the substrate, the section of the first dielectric layer in direct contact with the first dielectric region.

US Pat. No. 10,510,846

SEMICONDUCTOR DEVICE WITH NEEDLE-SHAPED FIELD PLATE STRUCTURES IN A TRANSISTOR CELL REGION AND IN AN INNER TERMINATION REGION

Infineon Technologies Aus...

1. A semiconductor device, comprising:a semiconductor portion comprising a first surface, a second surface opposite the first surface and a drift structure of a first conductivity type disposed between the first and second surfaces;
a transistor cell region comprising needle-shaped first field plate structures extending from the first surface into the semiconductor portion, and body regions of a second conductivity type opposite the first conductivity type surrounding the first field plate structures in a horizontal plane; and
an inner termination region surrounding the transistor cell region and comprising needle-shaped second field plate structures extending from the first surface into the semiconductor portion, the inner termination region being devoid of regions of the second conductivity type that are spaced from the second surface of the semiconductor portion.

US Pat. No. 10,510,843

INSULATED GATE SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

MITSUBISHI ELECTRIC CORPO...

1. An insulated gate silicon carbide semiconductor device, comprising:a silicon carbide substrate of 4H type having a main surface having an off-angle of more than 0° in an off-direction with respect to a {0001} plane;
a drift layer of a first conductivity type provided on said silicon carbide substrate;
a first base region of a second conductivity type located on a surface side of said drift layer;
a source region of the first conductivity type located in said first base region;
a trench provided so as to be in contact with said source region and to reach a portion of said drift layer beneath said first base region, and having a plurality of trench sidewall surfaces;
a gate insulating film formed in said trench;
a gate electrode buried in said trench through said gate insulating film;
a protective diffusion layer of the second conductivity type provided in said drift layer while being in contact with a bottom of said trench; and
a second base region of the second conductivity type provided in said drift layer while being in contact with said protective diffusion layer, said first base region, and at least-part of at least one of said plurality of trench sidewall surfaces, said second base region having a bottom surface whose depth is equal to a bottom surface of said protective diffusion layer.

US Pat. No. 10,510,841

METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE

SHINDENGEN ELECTRIC MANUF...

1. A method of manufacturing a silicon carbide semiconductor device comprising:an epitaxial layer of a first conductive type;
a first semiconductor region of a first conductive type formed on a surface of the epitaxial layer of the first conductive type, and having higher impurity concentration than that of the epitaxial layer of the first conductive type;
a body region of a second conductive type formed at a position deeper than that of the first semiconductor region of the first conductive type;
a channel region of a second conductive type formed such that
the channel region of the second conductive type
penetrates the first semiconductor region of the first conductive type from a surface of the epitaxial layer of the first conductive type,
reaches the body region of the second conductive type, and
defines
a first part of the first semiconductor region of the first conductive type formed entirely on the body region of the second conductive type and
a second part of the first semiconductor region of the first conductive type formed partially on the body region of the second conductive type, wherein
the first part of the first semiconductor region of the first conductive type and the channel region of the second conductive type define a first boundary surface, and
the second part of the first semiconductor region of the first conductive type and the channel region of the second conductive type define a second boundary surface,
the channel region of the second conductive type having lower impurity concentration than that of the body region of the second conductive type;
a second semiconductor region of a first conductive type formed toward the body region of the second conductive type from the surface of the epitaxial layer of the first conductive type, the second semiconductor region of the first conductive type having higher impurity concentration than that of the first semiconductor region of the first conductive type;
a body contact region of a second conductive type formed such that the body contact region of the second conductive type penetrates the first semiconductor region of the first conductive type from the surface of the epitaxial layer of the first conductive type and reaches the body region of the second conductive type, the body contact region of the second conductive type having higher impurity concentration than that of the body region of the second conductive type; and
a gate electrode formed on at least the channel region of the second conductive type with a gate insulating film interposed therebetween, wherein
the channel region of the second conductive type and the second semiconductor region of the first conductive type are formed at a planar position where the first part of the first semiconductor region of the first conductive type
remains between the channel region of the second conductive type and the second semiconductor region of the first conductive type, and
separates the channel region of the second conductive type from the second semiconductor region of the first conductive type, and
the second boundary surface is positioned on the body region of the second conductive type as viewed in a plan view, wherein the method comprising the steps of:
preparing a silicon carbide semiconductor substrate provided with the epitaxial layer of the first conductive type;
forming the body region of the second conductive type on the surface of the epitaxial layer of the first conductive type such that a depth where a maximum concentration of an impurity of a second conductive type is deeper than a depth position of a bottom surface of the channel region;
forming the first semiconductor region of the first conductive type on a surface of the body region of the second conductive type;
forming the channel region of the second conductive type, the second semiconductor region of the first conductive type and a body contact region of a second conductive type in the first semiconductor region of the first conductive type, the body contact region of the second conductive type penetrating the first semiconductor region of the first conductive type from the surface of the epitaxial layer of the first conductive type and reaches the body region of the second conductive type; and
forming the gate electrode on at least the channel region of the second conductive type with a gate insulating film interposed therebetween, wherein
in the step of forming the channel region of the second conductive type, the second semiconductor region of the first conductive type and the body contact region of the second conductive type, the channel region of the second conductive type, the second semiconductor region of the first conductive type and the body contact region of the second conductive type are formed at a planar position where the first part of the first semiconductor region of the first conductive type remains between the channel region of the second conductive type and the second semiconductor region of the first conductive type, and
the second boundary surface is positioned on the body region of the second conductive type as viewed in a plan view.

US Pat. No. 10,510,838

HIGH SURFACE DOPANT CONCENTRATION FORMATION PROCESSES AND STRUCTURES FORMED THEREBY

Taiwan Semiconductor Manu...

1. A method comprising:forming a source/drain region in an active area on a substrate, the source/drain region having a first dopant concentration;
forming a dielectric layer over the active area and the source/drain region;
after forming the dielectric layer, replacing a dummy gate stack in the dielectric layer with a metal gate stack;
depositing a second dielectric layer over the dielectric layer and the metal gate stack;
forming an opening through the dielectric layer and the second dielectric layer, the opening exposing at least a portion of an upper surface of the source/drain region;
forming a surface dopant region in the source/drain region at the upper surface of the source/drain region, forming the surface dopant region comprising plasma doping the source/drain region through the opening in the dielectric layer and the second dielectric layer, the surface dopant region comprising a second dopant concentration proximate the upper surface of the source/drain region; and
forming a conductive feature in the opening to the surface dopant region in the source/drain region.

US Pat. No. 10,510,835

SEMICONDUCTOR DEVICE WITH LOW RANDOM TELEGRAPH SIGNAL NOISE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a source/drain diffusion area, defined between a first isolation structure and a second isolation structure, including:
a source region;
a drain region; and
a device channel between the source region and the drain region; and
a first doped region disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region, the first doped region separated from at least one of the source region and the drain region, the first doped region being formed on a first portion of the first junction; and
a second doped region disposed along the first junction, the second doped region being formed on a second portion of the first junction separated from the first portion of the first junction such that the first doped region and the second doped region are spaced apart from each other,
wherein the first doped region has a dopant concentration higher than that of the device channel.

US Pat. No. 10,510,831

LOW ON RESISTANCE HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a substrate with a device region;
a transistor in the device region, wherein the transistor includes a gate on the substrate and having first and second gate sidewalls, a first source/drain (S/D) region disposed adjacent to the first gate sidewall, and a second source/drain (S/D) region disposed adjacent to the second gate sidewall;
a drain well disposed below and encompassing the first S/D region;
a body well disposed in the device region, wherein the body well encompasses the second S/D region and extends under a portion of the gate beyond the second gate sidewall; and
a drift well disposed in the substrate, wherein the drift well comprises:
a non-cut out region disposed under a first portion of the first S/D region and the drain well, the non-cut out region extending under the gate to the body well and coupling the first portion of the first S/D region to the body well, the non-cut out region completely encompassing the first portion of the first S/D region, and
a cut out region disposed under a second portion of the first S/D region and the drain well, the cut out region devoid of the drift well, and the cut out region structured to reduce an on resistance of the transistor.

US Pat. No. 10,510,830

N-TYPE POLYSILICON CRYSTAL, MANUFACTURING METHOD THEREOF, AND N-TYPE POLYSILICON WAFER

Sino-American Silicon Pro...

1. An N-type polysilicon crystal, wherein:a resistivity of the N-type polysilicon crystal has a slope when graphed, of which a horizontal axis is referred to as a solidification fraction and a vertical axis is referred to as the resistivity presented by a unit of Ohm-cm (?·cm), and the slope of resistivity is between 0 to ?1.8 at a first solidification fraction value between 0.25 to 0.8; and
a defect area percentage of the N-type polysilicon crystal has a slope when graphed, of which the horizontal axis is referred to as the solidification fraction and the vertical axis is referred to as the defect area percentage (%), and the slope of defect area percentage is less than 2.5 at a second solidification fraction value between 0.4 to 0.8.

US Pat. No. 10,510,827

CAPACITOR HAVING MULTIPLE GRAPHENE STRUCTURES

Taiwan Semiconductor Manu...

1. A capacitor comprising:a first graphene structure having a first plurality of graphene layers;
a dielectric layer over the first graphene structure;
a conductive growth layer over the dielectric layer, wherein the dielectric layer extends laterally past a sidewall of the conductive growth layer; and
a second graphene structure over the conductive growth layer, wherein the second graphene structure has a second plurality of graphene layers, wherein the first graphene structure extends laterally past a sidewall of the second graphene structure.

US Pat. No. 10,510,825

METAL-INSULATOR-METAL CAPACITOR WITH IMPROVED TIME-DEPENDENT DIELECTRIC BREAKDOWN

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a substrate with circuit components;
a back-end-of-line (BEOL) dielectric layer having a plurality of interlevel dielectric (ILD) levels, wherein an ILD level includes a metal ILD level with metal lines and an ILD via contact ILD level with via contacts for interconnection with the circuit components; and
a capacitor level disposed between lower and upper metal levels of lower and upper ILD levels of the BEOL dielectric layer, wherein the capacitor level includes a capacitor, the capacitor comprises a bottom capacitor electrode, a capacitor dielectric disposed on the bottom capacitor electrode, and a top capacitor electrode disposed above the capacitor dielectric, and the top capacitor electrode comprises a sidewall profile with rounded corners at an interface of the top capacitor electrode and the capacitor dielectric.

US Pat. No. 10,510,824

SEMICONDUCTOR DEVICE HAVING RESISTANCE ELEMENTS AND FABRICATION METHOD THEREOF

Mie Fujitsu Semiconductor...

1. A semiconductor device comprising:a first polycrystalline silicon having a negative temperature coefficient and having a first width; and
a second polycrystalline silicon having a positive temperature coefficient and having a second width larger than the first width, wherein:
the first polycrystalline silicon contains first impurities at a first concentration throughout a direction perpendicular to a direction of the first width, in a plan view; and
the second polycrystalline silicon contains the first impurities at the first concentration throughout a direction perpendicular to a direction of the second width, in the plan view.

US Pat. No. 10,510,822

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate having a display area and a non-display area;
a plurality of pixels in the display area;
scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction;
data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction; and
a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and comprising a first dummy data line and a first dummy power pattern extending in parallel to the data lines.

US Pat. No. 10,510,821

DISPLAY DEVICE

Innovation Counsel LLP, ...

1. A display device comprising:a substrate; and
a plurality of pad terminals on the substrate,
wherein each of the plurality of pad terminals comprises a lower conductive layer and an upper conductive layer disposed on the lower conductive layer,
an elastic layer disposed between the lower conductive layer and the upper conductive layer, the elastic layer being an insulating layer, and
at least a portion of the lower conductive layer being electrically connected to at least a portion of the upper conductive layer in a region in which the elastic layer is not arranged,
wherein a thin film transistor comprising a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, a data line connected to the thin film transistor, an organic light-emitting diode comprising a first electrode, an emissive layer, and a second electrode, a touch sensor comprising a plurality of touch electrodes, and a plurality of insulating layers respectively disposed between electrodes are arranged on the substrate, and
wherein the electrodes are the gate electrode, the source electrode, the drain electrode, the first electrode, the second electrode, and the plurality of touch electrodes, and the lower conductive layer and the upper conductive layer being respectively arranged in a same layer as at least one of the electrodes and the data line, and the elastic layer being arranged in a same layer as at least one of the plurality of insulating layers is arranged on the substrate.

US Pat. No. 10,510,819

ELECTRONIC DEVICE AND METHOD OF MAKING THEREOF

DIFTEK LASERS, INC., Wat...

12. A light source comprising:a backplane comprising:
a backplane substrate;
a semiconductor particle formed separately from the backplane substrate and then fixed upon the backplane substrate at a predetermined position;
the semiconductor particle planarized to remove a portion of the semiconductor particle and to expose at a cross-section of the semiconductor particle a planar surface; and
a controllable gated electronic component on or directly beneath the planar surface; and
light emitter electrically connected to the backplane such that the light emitter is electrically connected to the controllable gated electronic component, the electrical connection configured to allow the controllable gated electronic component to control the light emitter.

US Pat. No. 10,510,816

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A display device comprising:a substrate having a display area, and a peripheral area that is outside of the display area and comprises:
a first peripheral area adjacent to the display area;
a first bending area extending from the first peripheral area; and
a second peripheral area extending from the first bending area, and overlapping the first peripheral area when the first bending area is bent;
a display member at the display area for displaying an image, and comprising a first display area, and a second display area that is around the first display area; and
a plurality of align keys on the substrate,
wherein the first peripheral area comprises:
a flat peripheral area corresponding to an area between the first display area and the first bending area; and
a second bending area between the second display area and an end of the substrate, and
wherein the plurality of align keys comprise a first align key at the flat peripheral area, and a second align key at the second peripheral area.

US Pat. No. 10,510,811

COLOR FILTER AND WHITE ORGANIC LIGHT-EMITTING DIODE DISPLAY APPARATUS

SHENZHEN CHINA STAR OPTOE...

10. A WOLED display apparatus, comprising a display panel and a color filter disposed on the display panel;wherein the display panel is a WOLED display pane;
wherein the color filter comprises a red pixel section, a green pixel section, a blue pixel section and a white pixel section, a red photoresist is disposed in the red pixel section, a green photoresist is disposed in the green pixel section, and a blue photoresist is disposed in the blue pixel section;
wherein the white pixel section includes a first sub-section, and a red photoresist, a green photoresist or a blue photoresist is disposed in the first sub-section; and
wherein the white pixel section further includes a second sub-section, there is a red photoresists, a green photoresist or a blue photoresist disposed in the second sub-section, and a color of the photoresist in the second sub-section is different from that of the photoresist in the first sub-section.

US Pat. No. 10,510,807

DISPLAY DEVICE MANUFACTURING METHOD, AND DISPLAY DEVICE

SHARK KABUSHIKI KAISHA, ...

16. A display device comprising:a substrate having a display region in which a plurality of pixels are arranged, each pixel including a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel,
wherein the first subpixel and the second subpixel are arranged in an alternating manner in a first direction;
the third subpixel and the fourth subpixel are arranged in an alternating manner in the first direction;
a column constituted by the first subpixel and the second subpixel, and a column constituted by the third subpixel and the fourth subpixel, are arranged in an alternating manner in a second direction orthogonal to the first direction;
a first light-emitting layer containing a first fluorescent luminescent material is provided in common for the first subpixel and the second subpixel;
a second light-emitting layer containing a second fluorescent luminescent material is provided in common for the second subpixel and the third subpixel;
a third light-emitting layer containing a third luminescent material is provided in common for the third subpixel and the fourth subpixel;
at least two light-emitting layers among the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer include a light-emitting layer provided spanning a plurality of pixels;
an energy level of the second fluorescent luminescent material in a minimum excited singlet state is lower than an energy level of the first fluorescent luminescent material in a minimum excited singlet state and higher than an energy level of the third luminescent material in a minimum excited singlet state;
in the second subpixel, a distance between opposing surfaces of the first light-emitting layer and the second light-emitting layer is less than or equal to a Förster radius;
the third subpixel includes an intermediate layer, the intermediate layer constituted by at least one function layer aside from the light-emitting layers and having a thickness exceeding the Förster radius, and in the third subpixel, the second light-emitting layer and the third light-emitting layer are layered with the intermediate layer interposed therebetween;
in the first subpixel, the first fluorescent luminescent material emits light, and the light emitted from the first fluorescent luminescent material is emitted to the exterior;
in the second subpixel and the third subpixel, the second fluorescent luminescent material emits light, and the light emitted from the second fluorescent luminescent material is emitted to the exterior;
in the fourth subpixel, the third luminescent material emits light, and the light emitted from the third luminescent material is emitted to the exterior;
the first fluorescent luminescent material emits light having a first peak wavelength;
the second fluorescent luminescent material emits light having a second peak wavelength longer than the first peak wavelength; and
the third luminescent material emits light having a third peak wavelength longer than the second peak wavelength.

US Pat. No. 10,510,805

METHODS OF FORMING METAL ON INHOMOGENEOUS SURFACES AND STRUCTURES INCORPORATING METAL ON INHOMOGENEOUS SURFACES

Micron Technology, Inc., ...

1. A memory cell, comprising:a first conductive line extending in a first direction;
a second conductive line comprising tungsten disposed above a seeding line formed of a seeding material comprising an amorphous silicon material, the second conductive line extending in a second direction and crossing the first conductive line, the second direction different from the first direction, the seeding line having a substantially planar top surface, a bottom surface of the seeding line in contact with an electrode surface and a first insulator surface in the first direction, wherein a sidewall of the seeding line is in contact with an adjacent second insulator surface in the second direction, and the second conductive line being in contact with and formed across the substantially planar top surface of the seeding line, the substantially planar top surface having a local step height variation thickness of about 5 nm, the tungsten having a resistivity based at least in part on a grain size distribution, the grain size distribution being based at least in part on the seeding line having the substantially planar top surface and a thickness of the seeding line;
a chalcogenide element interposed between the first and second conductive lines,
wherein the seeding line is interposed between the second conductive line and the chalcogenide element, the seeding line contacting the second conductive line; and
a carbon electrode interposing the chalcogenide element and the seeding line, the carbon electrode in direct contact with the seeding line.

US Pat. No. 10,510,804

SEMICONDUCTOR STRUCTURE INTEGRATED WITH MAGNETIC TUNNELING JUNCTION AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure, comprising:forming a transistor region over a substrate, the transistor region comprising a gate and a first doped region;
forming a magnetic tunneling junction (MTJ) directly over the first doped region, electrically coupling to the transistor region; and
forming a metal via directly over the gate after forming the MTJ, the metal via being at a same level with the MTJ, forming the metal via comprising:
filling conductive material in an opening of a dielectric layer surrounding the MTJ; and
removing a portion of the conductive material and subsequently removing a portion of the dielectric layer until a top surface of the MTJ is exposed.

US Pat. No. 10,510,803

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor memory device, comprising:a magnetic tunneling junction (MTJ) memory structure, having a top electrode and a bottom electrode and a ferromagnetic material forming the MTJ between the top electrode and the bottom electrode;
a first portion of capping layer, disposed above the top electrode;
a first metal line, contacted the top electrode; wherein the first metal line is arranged to pass through the first portion of capping layer; and
a protection layer disposed over the first portion of the capping layer, wherein the protection layer extends along each of two sidewalls of the memory structure from a top surface of the bottom electrode to interfacing a top surface of the top electrode.

US Pat. No. 10,510,802

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first conductive wiring;
at least one first dielectric layer over the first conductive wiring;
at least one second dielectric layer comprises a first layer and a second layer over the at least one first dielectric layer;
a second conductive wiring over the at least one second dielectric layer;
a conductive via electrically connected to the first conductive wiring and the second conductive wiring,
wherein a dielectric constant of the at least one second dielectric layer is higher than a dielectric constant of the at least one first dielectric layer, the dielectric constant of the at least one first dielectric layer is within a range of about 3.5 to about 4.5, the dielectric constant of the at least one second dielectric layer is within a range of about 4 to about 7; and
a memory device comprising:
a first conductive structure under the at least one first dielectric layer;
a second conductive structure over the at least one second dielectric layer; and
a memory cell between the first conductive structure and the second conductive structure, and through the at least one first dielectric layer and the at least one second dielectric layer, wherein the memory cell comprises:
a bottom electrode via over the first conductive structure;
a bottom electrode over and electrically connected to the bottom electrode via;
a top electrode over the bottom electrode
a top electrode via over the top electrode; and
a magnetic tunnel junction (MTJ) between the top electrode and the bottom electrode,
wherein the at least one first dielectric layer is below the bottom electrode and surrounds edges of the bottom electrode via,
wherein the second layer of the at least one second dielectric layer surrounds the entire sidewalls of the top electrode via,
wherein the first layer of the at least one second dielectric layer surrounds sidewalls of the bottom electrode, sidewalls of the MTJ and sidewalls of the top electrode,
wherein both the first layer and the second layer of the at least one second dielectric layer surround the sidewalls of the conductive via.

US Pat. No. 10,510,796

SMALL PIXELS HAVING DUAL CONVERSION GAIN PROVIDING HIGH DYNAMIC RANGE

OmniVision Technologies, ...

1. A group of shared pixels comprising:a first shared pixel comprising a first photodiode and a first transfer gate;
a second shared pixel comprising a second photodiode and a second transfer gate;
a third shared pixel comprising a third photodiode and a third transfer gate;
a fourth shared pixel comprising a fourth photodiode and a fourth transfer gate;
a first floating diffusion shared by the first shared pixel and the second shared pixel;
a second floating diffusion shared by the third shared pixel and the fourth shared pixel;
a capacitor coupled to the first floating diffusion through a first dual conversion gain transistor,
and the second floating diffusion through a second dual conversion gain transistor;
wherein the capacitor is formed having an area covering most of the first shared pixel, the second shared pixel, the third shared pixel, and the fourth shared pixel.

US Pat. No. 10,510,795

SEMICONDUCTOR IMAGE SENSOR

Taiwan Semiconductor Manu...

1. An image sensor integrated chip, comprising:an image sensing element arranged within a substrate;
a first dielectric disposed in one or more trenches within a first side of the substrate, wherein the one or more trenches laterally surround the image sensing element; and
wherein the substrate includes a recessed portion arranged along the first side of the substrate and defined by second sidewalls of the substrate directly over the image sensing element, the second sidewalls of the substrate are angled to meet at a point disposed along a horizontal plane that intersects the first dielectric within the one or more trenches.

US Pat. No. 10,510,794

SEMICONDUCTOR IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

1. A back side illumination (BSI) image sensor comprising:a substrate comprising a front side and a back side opposite to the front side;
a pixel sensor in the substrate;
a logic device disposed over the front side of the substrate;
an isolation structure surrounding the pixel sensor in the substrate;
a dielectric layer over the pixel sensor on the front side of the substrate; and
a plurality of conductive structures disposed in the dielectric layer and arranged to align with the isolation structure,
wherein at least one of the conductive structures is entirely overlapped by the isolation structure in a direction normal to the substrate, and the at least one of the conductive structures is separated from the logic device,
wherein the isolation structure further comprises an insulating material portion and a conductive coating, and sidewalls of the insulating material portion are lined with the conductive coating.

US Pat. No. 10,510,793

UNIFORM-SIZE BONDING PATTERNS

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:an image sensor comprising:
a first substrate having a plurality of photosensitive elements therein;
a first passivation layer over the first substrate;
a first plurality of bonding pads in the first passivation layer, the first plurality of bonding pads representing output signals from the plurality of photosensitive elements, the first plurality of bonding pads having a first width and a first pitch; and
a second plurality of bonding pads in the first passivation layer, the second plurality of bonding pads providing control signals, the second plurality of bonding pads having the first width;
a second substrate bonded to the image sensor, the second substrate comprising:
a second passivation layer over the second substrate; and
a third plurality of bonding pads in the second passivation layer; and
wherein the second substrate is directly bonded to the image sensor such that the first plurality of bonding pads and the second plurality of bonding pads are aligned with respective ones of the third plurality of bonding pads.

US Pat. No. 10,510,791

ELEVATED PHOTODIODE WITH A STACKED SCHEME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first semiconductor die comprising a first semiconductor substrate;
a second semiconductor die bonded to the first semiconductor die; and
a pixel unit disposed in both the first semiconductor die and the second semiconductor die, the pixel unit comprising:
a storage node in the first semiconductor substrate;
a photodiode over and electrically connected to the storage node; and
read out circuitry, wherein the storage node is interposed between the photodiode and the read out circuitry.

US Pat. No. 10,510,778

ARRAY SUBSTRATE, DISPLAY DEVICE AND WEARABLE DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising a plurality of pixel units, wherein each of the pixel units comprises a pixel electrode and a thin film transistor connected to the pixel electrode, the plurality of pixel units forms a display region, and the thin film transistor of each of the pixel units at an edge of the display region is closer to the edge of the display region than the pixel electrode thereof;the array substrate comprises a first arrangement region, a second arrangement region, a third arrangement region and a fourth arrangement region which together form the edge of the display region, wherein
the first arrangement region corresponds to an upper left peripheral portion of the display region, the thin film transistor of each pixel unit in the first arrangement region is on the upper left of the pixel electrode thereof;
the second arrangement region corresponds to an upper right peripheral portion of the display region, the thin film transistor of each pixel unit in the second arrangement region is on the upper right of the pixel electrode thereof;
the third arrangement region corresponds to a lower left peripheral portion of the display region, the thin film transistor of each pixel unit in the third arrangement region is on the lower left of the pixel electrode thereof; and
the fourth arrangement region corresponds to a lower right peripheral portion of the display region, the thin film transistor of each pixel unit in the fourth arrangement region is on the lower right of the pixel electrode thereof;
wherein the array substrate further comprises a plurality of edge pixel units at the upper left peripheral portion, the upper right peripheral portion, the lower left peripheral portion and the lower right peripheral portion of the display region, and a thin film transistor of each edge pixel unit at the upper left peripheral portion, the upper right peripheral portion, the lower left peripheral portion and the lower right peripheral portion of the display region is farther away from a center of the display region than the pixel electrode thereof.

US Pat. No. 10,510,775

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first field effect transistor formed in a first region of a semiconductor substrate; and
a second field effect transistor formed in a second region of the semiconductor substrate, which is different from the first region,
wherein, in the first region, a first insulating film is formed on the semiconductor substrate, and a semiconductor layer is formed on the first insulating film,
wherein the first field effect transistor has:
a first gate electrode formed on the semiconductor layer via a first gate insulating film;
a second insulating film formed on a side surface of the first gate electrode, and formed on the semiconductor layer;
an epitaxial layer formed on the semiconductor layer exposed from the second insulating film, and having an end portion whose thickness is thinner than a thickness of a central portion of the epitaxial layer; and
a third insulating film formed on the side surface of the first gate electrode via the second insulating film such that the third insulating film covers an upper surface of the epitaxial layer in the end portion,
wherein a first extension region, which serves as a part of one of a source region of the first field effect transistor and a drain region of the first field effect transistor, is formed in a first portion of the semiconductor layer, which is covered with the second insulating film and the third insulating film,
wherein a first diffusion layer, which serves as a part of one of the source region of the first field effect transistor and the drain region of the first field effect transistor, is formed at least a portion of the epitaxial layer, which is not covered with the second insulating film and the third insulating film,
wherein an impurity concentration of the first diffusion layer is higher than and impurity concentration of the first extension region,
wherein the semiconductor substrate in the second region is exposed from the first insulating film and the semiconductor layer,
wherein the second field effect transistor has:
a second gate electrode formed on the semiconductor substrate in the second region via a second gate insulating film;
a fourth insulating film formed on a side surface of the second gate electrode, and formed on the semiconductor substrate in the second region; and
a fifth insulating film formed on the side surface of the second gate electrode via the fourth insulating film,
wherein a second extension region, which serves as a part of one of a source region of the second field effect transistor and a drain region of the second field effect transistor, is formed in a first portion of the semiconductor substrate, which is covered with the fourth insulating film and the fifth insulating film,
wherein a second diffusion layer, which serves as a part of the one of the source region of the second field effect transistor and the drain region of the second field effect transistor, is formed in a second portion of the semiconductor substrate in the second region, which is not covered with the fourth insulating film and the fifth insulating film,
wherein an impurity concentration of the second diffusion layer is higher than an impurity concentration of the second extension region,
wherein, in cross-section view, an upper surface of the first diffusion layer is positioned higher than an interface between the semiconductor layer and the first gate insulating film, and
wherein, in cross-section view, an upper surface of the second diffusion layer is positioned lower than or equal to an interface between the semiconductor substrate and the second gate insulating film.

US Pat. No. 10,510,768

3D MEMORY DEVICE WITH U-SHAPED MEMORY CELL STRINGS

Trinandable S.r.l., Mila...

1. A 3D memory device comprising:a substrate;
a plurality of U-shaped memory cells strings each including a buried string portion formed in the substrate, a first, bit line-side string portion or pillar and a second, source line-side string portion or pillar, wherein the buried string portion is connected to a first end of the first string portion and to a first end of the second string portion, each one of the U-shaped memory cells strings including a stack of memory cells along the first string portion and a stack of memory cells along the second string portion;
bit line selectors arranged at a second end of the first string portions opposed to the first end, for the selective connection to respective bit lines;
source line selectors arranged at a second end of the second string portions opposed to the first end, for the selective connection to respective source lines;
first groups of first string portions, wherein in each first group the first string portions are aligned along a first direction to form a respective first row of first string portions;
second groups of second string portions, wherein in each second group the second string portions are aligned along the first direction to form a respective second row of second string portions;
wherein the first rows of first string portions and the second rows of second string portions follow one another, alternately or in pairs, along a second direction transversal to the first direction;
wherein first rows of first string portions and/or second rows of second string portions consecutive along said second direction are spaced apart from each other a respective distance;
the 3D memory device comprising a respective slit between a first row of first string portions and a second row of second string portions being consecutive along said second direction and spaced apart a distance equal to or less than a minimum distance allowed by a resolution of the manufacturing technology, wherein said slit extends in a third direction, orthogonal to said first and second directions, from said second end down to the substrate, said slit interrupting layers forming the bit line selectors and the source line selectors and control gates of the memory cells of the memory cells stacks formed along the first and second string portions; and
wherein said slit has dimension, along said second direction, less than, equal to or higher than said minimum distance, and walls of the slit lying in planes parallel to said first and third directions delimit the first and second string portions.

US Pat. No. 10,510,765

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a memory device, comprising:providing a semiconductor substrate;
forming a plurality of logic well regions and a memory well region in the semiconductor substrate;
forming a charge storage structure on the memory well region;
forming a dummy dielectric layer on the charge storage structure and the logic well regions;
forming a dummy gate layer on the dummy dielectric layer;
forming a gate mask layer on the dummy gate layer;
etching the gate mask layer, the dummy gate layer and the dummy dielectric layer to form a plurality of dummy gate structures, wherein each of the dummy gate structures comprises a remaining portion of the dummy dielectric layer, a remaining portion of the dummy gate layer and a remaining portion of the gate mask layer;
forming a plurality of spacers on sidewalls of the dummy gate structures;
forming a plurality of sources and drains in the logic well regions and the memory well region;
removing the gate mask layer;
removing the remaining portion of the dummy gate layer to form a plurality of openings defined by the spacers; and
filling the openings with a plurality of high-k dielectric layers and a plurality of metal gate electrodes.

US Pat. No. 10,510,763

EMBEDDED NONVOLATILE MEMORY AND FORMING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A nonvolatile memory, comprising:a substrate having a source region and a drain region;
an erase gate over the source region;
a conductive feature over a portion of the substrate that is between the source region and the drain region, wherein the conductive feature comprises polysilicon;
a gate stack over the substrate and between the erase gate and the conductive feature, wherein the gate stack comprises a floating gate, a control gate over the floating gate, and a mask layer over the control gate; and
at least one cap layer over the erase gate, wherein a bottom surface of the at least one cap layer is in a position lower than a top surface of the control gate and a top surface of the at least one cap layer and a top surface of the mask layer are substantially coplanar.

US Pat. No. 10,510,762

SOURCE AND DRAIN FORMATION TECHNIQUE FOR FIN-LIKE FIELD EFFECT TRANSISTOR

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a first fin and a second fin over a substrate, wherein the first fin and the second fin have a fin spacing less than about 25 nm, and further wherein the first fin and the second fin each includes a channel region disposed between a source region and a drain region;
forming a gate structure over the channel regions of the first fin and the second fin; and
performing only one cycle of a cyclic deposition etch process to form a merged epitaxial source feature that spans the source regions of the first fin and the second fin and a merged epitaxial drain feature that spans the drain regions of the first fin and the second fin, wherein the one cycle of the cyclic deposition etch process includes:
a deposition process that forms a semiconductor material over the first fin and the second fin, wherein the deposition process is performed until the semiconductor material in the fin spacing between the first fin and the second fin extends above an initial height of the first fin and the second fin, and
an etching process to planarize the semiconductor material to achieve a substantially flat top surface and substantially flat sidewall surfaces for each of the merged epitaxial source feature and the merged epitaxial drain feature, wherein the etching process is separate from the deposition process.

US Pat. No. 10,510,761

STATIC RANDOM ACCESS MEMORY DEVICE WITH HALO REGIONS HAVING DIFFERENT IMPURITY CONCENTRATIONS

RENESAS ELECTRONICS CORPO...

1. A semiconductor device having a static random access memory, comprising:a storage node including a first storage node and a second storage node storing data;
a first pair of bit lines sending/receiving data;
a read bit line sending data;
a ground interconnection to which a ground potential is applied;
a first element formation region and a second element formation region, each of which is defined by an element isolation insulation film in a predetermined region of a main surface of a semiconductor substrate;
a first access transistor formed in the first element formation region and including a first source-drain region and a second source-drain region that are spaced away from each other and have first conductivity type, the first access transistor including a first access gate electrode positioned above a region interposed between the first source-drain region and the second source-drain region;
a first drive transistor formed in the first element formation region and including a third source-drain region and a fourth source-drain region that are spaced away from each other and have the first conductivity type, the first drive transistor including a first drive gate electrode positioned above a region interposed between the third source-drain region and the fourth source-drain region;
a second drive transistor formed in the first element formation region and including a fifth source-drain region and a sixth source-drain region that are spaced away from each other and have the first conductivity type, the second drive transistor including a second drive gate electrode positioned above a region interposed between the fifth source-drain region and the sixth source-drain region; and
a second access transistor formed in the first element formation region and including a seventh source-drain region and an eighth source-drain region that are spaced away from each other and have the first conductivity type, the second access transistor including a second access gate electrode positioned above a region interposed between the seventh source-drain region and the eighth source-drain region,
wherein the first access transistor includes:
a first halo region having a first impurity concentration and second conductivity type, the first halo region being formed in a region just below the first access gate electrode so as to be adjacent to the first source-drain region electrically connected to a predetermined bit line of the first pair of bit lines, and
a second halo region having a second impurity concentration and the second conductivity type, the second halo region being formed in the region just below the first access gate electrode so as to be adjacent to the second source-drain region electrically connected to the storage node,
wherein the first drive transistor includes:
a third halo region having a third impurity concentration and the second conductivity type, the third halo region being formed in a region just below the first drive gate electrode so as to be adjacent to the third source-drain region electrically connected to the storage node, and
a fourth halo region having a fourth impurity concentration and the second conductivity type, the fourth halo region being formed in the region just below the first drive gate electrode so as to be adjacent to the fourth source-drain region electrically connected to the ground interconnection,
wherein the second drive transistor includes:
a fifth halo region having a fifth impurity concentration and the second conductivity type, the fifth halo region being formed in a region just below the second drive gate electrode so as to be adjacent to the fifth source-drain region electrically connected to the ground interconnection, and
a sixth halo region having a sixth impurity concentration and the second conductivity type, the sixth halo region being formed in the region just below the second drive gate electrode so as to be adjacent to the sixth source-drain region electrically connected to the storage node,
wherein the second access transistor includes:
a seventh halo region having a seventh impurity concentration and the second conductivity type, the seventh halo region being formed in a region just below the second access gate electrode so as to be adjacent to the seventh source-drain region electrically connected to the storage node, and
an eighth halo region having an eighth impurity concentration and the second conductivity type, the eighth halo region being formed in the region just below the second access gate electrode so as to be adjacent to the eighth source-drain region electrically connected to the read bit line,
wherein the second impurity concentration is higher than the first impurity concentration,
wherein the third impurity concentration is higher than the fourth impurity concentration, and
wherein the first impurity concentration and the fourth impurity concentration are set to be different impurity concentrations.

US Pat. No. 10,510,757

SEMICONDUCTOR DEVICE INCLUDING STORAGE ELEMENT

Semiconductor Energy Labo...

1. A semiconductor device comprising:a plurality of storage elements,
wherein one of the plurality of storage elements includes:
a first transistor including:
a first gate electrode;
one of a first source electrode and a first drain electrode; and
the other of the first source electrode and the first drain electrode;
a second transistor including:
a second gate electrode;
one of a second source electrode and a second drain electrode; and
the other of the second source electrode and the second drain electrode; and
a third transistor including:
a third gate electrode;
one of a third source electrode and a third drain electrode; and
the other of the third source electrode and the third drain electrode,
wherein the first transistor is provided in a substrate including a semiconductor material,
wherein the second transistor includes an oxide semiconductor layer,
wherein the first gate electrode and the one of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the other of the first source electrode and the first drain electrode and the one of the third source electrode and the third drain electrode are electrically connected to each other, and
wherein the first transistor operates at a speed higher than that of the second transistor.

US Pat. No. 10,510,754

COMPLIMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) WITH LOW CONTACT RESISTIVITY AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

1. An integrated circuit device comprising:an n-type metal-oxide-semiconductor (NMOS) device comprising:
a first source/drain region;
a first metal contact over the first source/drain region;
a first titanium-containing layer having a portion between the first metal contact and the first source/drain region; and
a p-type metal-oxide-semiconductor (PMOS) device comprising:
a second source/drain region;
a second metal contact over the second source/drain region; and
a second titanium-containing layer between the second metal contact and the second source/drain region, wherein the second titanium-containing layer comprises titanium silicon germanium (Ti(Si)Ge) or titanium digermanium (TiGe2).

US Pat. No. 10,510,752

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor device comprising:forming a semiconductor fin on a substrate;
forming a gate dielectric to cover the semiconductor fin;
forming a dummy gate on the gate dielectric and the semiconductor fin;
forming at least one gate spacer on at least one sidewall of the dummy gate;
removing at least a portion of the semiconductor fin and at least a portion of the gate dielectric uncovered by the dummy gate and the gate spacer and forming a first recess between the gate spacer and the semiconductor fin; and
removing at least another portion of the semiconductor fin covered by the gate dielectric to form a second recess between the gate dielectric and the semiconductor fin.

US Pat. No. 10,510,750

HIGH VOLTAGE INTEGRATION FOR HKMG TECHNOLOGY

Taiwan Semiconductor Manu...

1. An integrated circuit (IC), comprising:a first transistor gate stack disposed in a low voltage region defined on a substrate, wherein the first transistor gate stack comprises a first gate electrode and a first gate dielectric separating the first gate electrode from the substrate; and
a third transistor gate stack disposed in a high voltage region defined on the substrate, wherein the third transistor gate stack comprises a third gate electrode and a third gate dielectric separating the third gate electrode from the substrate, wherein the third gate dielectric comprises an oxide component and a first interlayer dielectric layer.

US Pat. No. 10,510,749

RESISTOR WITHIN SINGLE DIFFUSION BREAK, AND RELATED METHOD

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit (IC), comprising:a plurality of semiconductor fins on a substrate, at least one semiconductor fin being part of at least one finFET;
a single diffusion break (SDB) in a selected one of the plurality of semiconductor fins; and
a resistor positioned within the SDB.

US Pat. No. 10,510,746

SEMICONDUCTOR DEVICE INCLUDING ELECTROSTATIC DISCHARGE PROTECTION PATTERNS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a front-end-of-line region, at least a portion of which is disposed on a substrate, the front-end-of-line region including an electrostatic discharge protection circuit and an integrated circuit electrically connected to the electrostatic discharge protection circuit;
a back-end-of-line region on the front-end-of-line region; and
an electrostatic discharge protection pattern on a scribe region of the substrate,
wherein the electrostatic discharge protection pattern comprises:
a lower pattern extending horizontally and having a side cross-sectional surface defined by a height and a width of the lower pattern, the side cross-sectional surface exposed through a side surface of the back-end-of-line region;
a via electrically connected to the lower pattern and extending perpendicularly to the substrate; and
an upper pattern electrically connected to the via.

US Pat. No. 10,510,745

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising a display region and a peripheral region surrounding the display region, wherein gate lines and data lines crossing the gate lines are arranged at the display region and a static charge shielding unit is arranged at the peripheral region, wherein the array substrate further comprises a static charge releasing line connected to the static charge shielding unit, and the static charge shielding unit is configured to release static charges at the peripheral region through the static charge releasing line,wherein the static charge shielding unit comprises:
a first electrostatic protection line,
a first electrostatic protection unit, and
at least one shielding line,
wherein the first electrostatic protection line and the at least one shielding line are parallel to the gate lines,
a length of the first electrostatic protection line along the gate lines is greater than a length of the display region along the gate lines,
a length of the at least one shielding line along the gate lines is greater than a length of the display region along the gate lines,
the first electrostatic protection line is connected to the static charge releasing line through the first electrostatic protection unit, and
the at least one shielding line is directly connected to the static charge releasing line,
wherein the array substrate further comprises a second electrostatic protection line, a second electrostatic protection unit and a third electrostatic protection unit arranged at the peripheral region, and wherein the second electrostatic protection line is arranged parallel to the gate lines, each data line is connected to the second electrostatic protection line through the second electrostatic protection unit, and the second electrostatic protection line is connected to the static charge releasing line through the third electrostatic protection unit.

US Pat. No. 10,510,741

TRANSIENT VOLTAGE SUPPRESSION DIODES WITH REDUCED HARMONICS, AND METHODS OF MAKING AND USING

Semtech Corporation, Cam...

1. A method of making a semiconductor device, comprising:providing a semiconductor die;
forming a transient voltage suppression (TVS) structure in the semiconductor die;
forming a capacitor over the semiconductor die; and
forming a semiconductor package with the TVS structure and capacitor coupled in parallel.

US Pat. No. 10,510,740

STRAPPING STRUCTURE OF MEMORY CIRCUIT

Taiwan Semiconductor Manu...

1. A memory array comprising:a first memory cell comprising a first pass transistor;
a second memory cell adjacent the first memory cell comprising a second pass transistor;
a first word line strapping line in a first metallization layer and electrically connecting a gate of the first pass transistor to a first word line and a gate of the second pass transistor to the first word line, the first word line being disposed in a second metallization layer over the first metallization layer, wherein the first word line strapping line extends into the first memory cell and the second memory cell, and wherein the first word line strapping line extends over a second word line different than the first word line.

US Pat. No. 10,510,739

METHOD OF PROVIDING LAYOUT DESIGN OF SRAM CELL

TAIWAN SEMICONDUCTOR MANU...

1. A method of providing a layout design of an SRAM cell, comprising:providing a substrate layout comprising a first oxide diffusion area, a second oxide diffusion area, a first polysilicon layout, and a second polysilicon layout, wherein the first oxide diffusion area is parallel to the second oxide diffusion area, the first polysilicon layout is parallel to the second polysilicon layout, the first polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area, and the second polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area;
forming a first pull-up transistor on the first oxide diffusion area and the first polysilicon layout;
forming a first pull-down transistor on the second oxide diffusion area and the first polysilicon layout;
forming a second pull-up transistor on the first oxide diffusion area and the second polysilicon layout; and
forming a second pull-down transistor on the second oxide diffusion area and the second polysilicon layout;
wherein forming the first pull-up transistor on the first oxide diffusion area and the first polysilicon layout comprises:
disposing a first contact layout to overlap a first portion of the first oxide diffusion area; and
disposing a second contact layout to overlap a second portion of the first oxide diffusion area; and
forming the first pull-down transistor on the second oxide diffusion area and the first polysilicon layout comprises:
arranging the first contact layout to overlap a first portion of the second oxide diffusion area; and
disposing a third contact layout on a second portion of the second oxide diffusion area.

US Pat. No. 10,510,736

LIGHT EMITTING STRUCTURE

Apple Inc., Curpentino, ...

1. A display comprising:a display substrate;
a plurality of bottom conductive layers on the display substrate;
an electrode on the display substrate;
a passivation layer spanning across the display substrate and directly over the plurality of bottom conductive layers and the electrode;
a corresponding plurality of LED devices bonded to the plurality of bottom conductive layers, and embedded within the passivation layer;
wherein the passivation layer laterally surrounds each LED device;
an opening in the passivation layer over the electrode; and
a transparent top conductive layer directly over the passivation layer and in contact with at least one of the LED devices and spanning within the opening to contact the electrode.

US Pat. No. 10,510,734

SEMICONDUCTOR PACKAGES HAVING DUMMY CONNECTORS AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:encapsulating a first integrated circuit die in an encapsulant;
forming a redistribution layers (RDL) electrically connected to the first integrated circuit die;
bonding a substrate to the RDL using a plurality of functional connectors, wherein the plurality of functional connectors electrically connects a second integrated circuit die to the first integrated circuit die, and wherein the first integrated circuit die and the second integrated circuit die are disposed on opposing sides of the substrate;
disposing a plurality of dummy connectors between the substrate and the RDL, wherein the plurality of functional connectors extends below the plurality of dummy connectors, and wherein the plurality of functional connectors at least partially encircles the plurality of dummy connectors in a top down view, wherein the plurality of dummy connectors is in physical contact with a same surface of the substrate as the plurality of functional connectors; and
dispensing an underfill between the same surface of the substrate and the RDL, the underfill is further dispensed around the plurality of functional connectors and the plurality of dummy connectors.

US Pat. No. 10,510,733

INTEGRATED DEVICE COMPRISING EMBEDDED PACKAGE ON PACKAGE (POP) DEVICE

QUALCOMM Incorporated, S...

1. A device comprising:a printed circuit board (PCB);
a package on package (PoP) device coupled to the printed circuit board (PCB), wherein the package on package (PoP) device includes:
a first package having a first electronic package component;
a second package coupled to the first package; and
a gap controller configured to provide a spacing between the first electronic package component and the second package, the gap controller includes a spacer and an adhesive layer;
a first encapsulation layer formed between the first package and the second package, wherein the first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer; and
a second encapsulation layer configured to at least partially encapsulates the package on package (PoP) device.

US Pat. No. 10,510,730

STACKED SEMICONDUCTOR STRUCTURE AND METHOD

Taiwan Semiconductor Manu...

1. A device comprising:a first chip comprising:
a first connection pad embedded in a first dielectric layer; and
a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad; and
a second chip comprising:
a second connection pad on a non-bonding side of the second chip, wherein a top surface of the second connection pad is lower than a backside of a substrate of the second chip; and
a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

US Pat. No. 10,510,729

3DIC INTERCONNECT APPARATUS AND METHOD

Taiwan Semiconductor Manu...

1. An apparatus comprising:a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first metal lines formed in the plurality of first dielectric layers over the first substrate, a first surface of the plurality of first dielectric layers facing the first substrate;
a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second metal lines formed in the second dielectric layers over the second substrate;
a conductive element extending from a second surface of the first semiconductor chip to one of the plurality of second metal lines in the second semiconductor chip, the conductive element having a first portion extending through the first substrate, a second portion extending through the plurality of first dielectric layers, and a third portion extending into the plurality of second dielectric layers; and
a plurality of dielectric liners interposed between the conductive element and the first substrate, the plurality of dielectric liners not extending between the conductive element and the plurality of first dielectric layers, the conductive element contacting a portion of the first surface of the plurality of first dielectric layers, wherein the plurality of dielectric liners comprises a first liner and a second liner, wherein the second liner is interposed between the first liner and the first substrate, wherein the first liner is a spacer-shaped structure.

US Pat. No. 10,510,727

SEMICONDUCTOR DEVICE WITH DISCRETE BLOCKS

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:forming a first redistribution layer on a first side of an encapsulant, wherein the encapsulant is planar with both a first semiconductor device and an integrated passive device within a first connection block; and
forming a second redistribution layer on a second side of the encapsulant opposite the first side of the encapsulant, the forming the second redistribution layer electrically connecting the second redistribution layer to the first redistribution layer through a first through substrate via.

US Pat. No. 10,510,726

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a base including interconnects;
a first semiconductor chip including a first semiconductor element portion; and
a second semiconductor chip,
wherein the first semiconductor chip is electrically connected to the second semiconductor chip via at least one of the interconnects,
the second semiconductor chip includes a first region, a first portion, and a second portion,
the first region includes a second semiconductor element portion,
the first portion is continuous with the first region,
the second portion is continuous with the first region and is separated from the first portion in a second direction crossing a first direction,
the first direction is from the base toward the first region,
the second semiconductor chip includes a trench surrounded with the first region, the first portion, and the second portion,
the trench penetrates through the second semiconductor chip in a third direction, the third direction crosses each of the first direction and the second direction, and
the first portion, the second portion, and at least a portion of the first semiconductor chip are positioned between the base and the first region.

US Pat. No. 10,510,720

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Siliconware Precision Ind...

1. An electronic package, comprising:a first substrate;
a first electronic component having a first surface and a second surface opposite to the first surface, the first electronic component being disposed on the first substrate through a plurality of conductive bumps formed on the first surface in a flip-chip manner, wherein the first electronic component is a semiconductor component;
a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the second surface of the first electronic component through a bonding layer, wherein the first conductive elements are different in structure from the second conductive elements, and the bonding layer is in direct contact with the first electronic component and the second substrate; and
a first encapsulant formed between the first substrate and the second substrate and encapsulating the first electronic component, the bonding layer, the first conductive elements and the second conductive elements, wherein the bonding layer is a stress-absorbing layer configured to absorb stresses of an upward pushing force generated by the first encapsulant for the second surface of the first electronic component.

US Pat. No. 10,510,718

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a first die disposed over the substrate;
a second die disposed over the substrate and arranged laterally adjacent to the first die from a cross-sectional perspective, wherein the second die includes a first surface facing the substrate, and a second surface opposite to the first surface;
a molding disposed over the substrate and surrounding the first die and the second die, wherein the molding separates the first die and the second die, and the molding includes a first surface facing the substrate, and a second surface opposite to the first surface;
an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed over the first die, the second die and the molding, the dielectric layer is in contact with the second surface of the molding and the second surface of the second die, and the conductive member is surrounded by the dielectric layer; and a via disposed between the dielectric layer and the substrate, the via extended within the second die.

US Pat. No. 10,510,715

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

16. A semiconductor structure, comprising:a first die including a first edge, a first corner over the first edge and a second corner opposite to the first corner;
a second die disposed over the first die and including a second edge, a third corner over the second edge and a fourth corner opposite to the third corner; and
a dielectric material surrounding the first die and the second die,wherein the first corner is vertically aligned with the third corner, the fourth corner protrudes laterally away from the first die, the second die is rotated about the first corner or about the third corner in relation to the first die from a top view, and the first die and the second die have different shapes or different dimensions.

US Pat. No. 10,510,712

METHODS FOR CONTROLLING WARPAGE IN PACKAGING

Taiwan Semiconductor Manu...

1. A method comprising:placing a plurality of dummy dies in a peripheral region of a carrier, the peripheral region of the carrier being free of device dies;
placing a plurality of device dies in a central region of the carrier, the central region being surrounded by the peripheral region and being free of dummy dies;
molding the plurality of dummy dies and the plurality of device dies in a molding composite to form a composite wafer;
forming electrical connections to respective device dies; and
singulating the composite wafer into a plurality of packages, wherein each of the plurality of packages includes two or more device dies.

US Pat. No. 10,510,711

ANISOTROPIC CONDUCTIVE FILM AND CONNECTED STRUCTURE

DEXERIALS CORPORATION, T...

1. An anisotropic conductive film comprising an insulating adhesive layer and conductive particles arranged in the insulating adhesive layer in a lattice-like manner, whereinwhen among center distances between an arbitrary conductive particle and conductive particles adjacent to the conductive particle, a shortest distance to the arbitrary conductive particle is defined as a first center distance, and a next shortest distance is defined as a second center distance,
the first center distance and the second center distance are each 1.5 to 5 times a particle diameter of the conductive particles, and
regarding an acute triangle formed by an arbitrary conductive particle P0, a conductive particle P1 spaced apart from the arbitrary conductive particle P0 by the first center distance, and a conductive particle P2 spaced apart from the arbitrary conductive particle P0 by the first center distance or the second center distance, an acute angle ? formed between a straight line orthogonal to a direction (hereinafter, referred to as a first array direction) of a straight line passing through the conductive particles P0 and P1 and a direction (hereinafter, referred to as a second array direction) of a straight line passing through the conductive particles P1 and P2 is 18 to 35° , and
when a direction passing through the conductive particles P0 and P2 is defined as a third array direction, the first array direction, the second array direction, and the third array direction are tilted with respect to the longitudinal direction of the anisotropic conductive film, and
an angle formed between the first array direction and the longitudinal direction of the anisotropic conductive film is smaller than an angle formed between the second array direction and the longitudinal direction of the anisotropic conductive film.

US Pat. No. 10,510,710

BUMP-ON-TRACE INTERCONNECT

Taiwan Semiconductor Manu...

1. A semiconductor package comprising:a first semiconductor device comprising:
a first substrate;
a conductive land proximate a first side of the first substrate; and
a conductive pillar, a first surface of the conductive pillar coupled to the conductive land;
a second semiconductor device comprising:
a second substrate; and
a conductive trace on a surface of the second substrate facing the conductive pillar, a sidewall of the conductive trace having a first height; and
a conductive joint between the conductive pillar and the conductive trace, the conductive joint comprising solder, the conductive joint covering the sidewall of the conductive trace by at least half the first height, the conductive pillar being spaced from the conductive trace by a first distance, the first distance being smaller than the first height, the conductive joint covering at least a portion of a first sidewall of the conductive pillar, a second sidewall of the conductive pillar opposing the first sidewall being free of the conductive joint.

US Pat. No. 10,510,709

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor package, comprising:a molding compound, wherein the molding compound comprises concave portions;
through interlayer vias, disposed within and penetrating through the molding compound;
at least one chip disposed within the molding compound, wherein the through interlayer vias are arranged aside and surrounding the at least one chip, the at least one chip has metal posts disposed thereon, the molding compound encapsulates the at least one chip and wraps around the through interlayer vias and the metal posts of the at least one chip, and portions of the metal posts and the through interlayer vias are protruded out of the molding compound; and
a polymeric molding compound disposed on the molding compound, wherein the polymeric molding compound encapsulates the protruded portions of the metal posts and the through interlayer vias, a material of the polymeric molding compound is different from a material of the molding compound, and the polymeric molding compound comprises protrusions fitted into the concave portions of the molding compound.

US Pat. No. 10,510,707

THERMALLY CONDUCTIVE MOLDING COMPOUND STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor package, comprising:attaching a thermal conductivity layer to a chip, the chip having a first surface and a second surface, the thermal conductivity layer being attached to the first surface of the chip, wherein the thermal conductivity layer is configured to provide a path through which heat generated from the chip is dissipated;
attaching a substrate to the second surface of the chip after attaching the thermal conductivity layer to the chip; and
forming a molding compound encapsulating the chip and the thermal conductivity layer.

US Pat. No. 10,510,706

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:at least one semiconductor die;
an insulating encapsulant encapsulating the at least one semiconductor die;
an insulating layer disposed on the at least one semiconductor die and on the insulating encapsulant;
conductive pillars, located on the at least one semiconductor die and inlaid in the insulating layer;
a first seed layer embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the at least one semiconductor die; and
a second seed layer, disposed on the insulating layer and the conductive pillars, wherein the conductive pillars physically separate the first seed layer from the second seed layer.

US Pat. No. 10,510,703

SEMICONDUCTOR DEVICE AND METHOD OF FORMING 3D DUAL SIDE DIE EMBEDDED BUILD-UP SEMICONDUCTOR PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a semiconductor die;
disposing the semiconductor die over a carrier;
disposing a substrate over the carrier;
laminating a prefabricated insulating film onto the substrate; and
mounting the substrate to the carrier with the semiconductor die embedded in the prefabricated insulating film after laminating the insulating film onto the substrate.

US Pat. No. 10,510,702

STACKED RADIO FREQUENCY DEVICES

Skyworks Solutions, Inc.,...

1. A radio frequency switch arrangement comprising:a ground plane;
a stack arranged in relation to the ground plane, the stack including a plurality of switching elements coupled in series with one another, and the stack having first and second ends, the first end including a respective terminal of a first one of the plurality of switching elements; and
a first solder bump coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.

US Pat. No. 10,510,699

BOND STRUCTURES AND THE METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

16. A device comprising:a semiconductor substrate;
integrated circuit devices at a surface of the semiconductor substrate;
a metal pad over and electrically coupling to the integrated circuit devices, wherein the metal pad is configured to prohibit currents flowing through;
an etch stop layer over the metal pad;
a first bond pad overlapping the metal pad, wherein the first bond pad is electrically floating, and entireties of spaces between the first bond pad and the metal pad are free from conductive features therein;
a second bond pad configured to allow currents flowing through, wherein both the first bond pad and the second bond pad comprise bottom surfaces contacting the etch stop layer; and
a package component bonding to the first bond pad and the second bond pad.

US Pat. No. 10,510,697

SEMICONDUCTOR PACKAGE SYSTEM AND METHOD

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:forming a first semiconductor die and a second semiconductor die;
depositing a protective layer over the first semiconductor die and the second semiconductor die;
patterning the protective layer to form a first opening over the first semiconductor die, a second opening over the second semiconductor die, and a third opening over a scribe line;
singulating the first semiconductor die from the second semiconductor die through the third opening;
encapsulating the first semiconductor die and the second semiconductor die with an encapsulant after the singulating;
depositing a seed layer over the encapsulant and within the first opening and the second opening after the encapsulating;
plating a conductive material onto the seed layer over the encapsulant and the first opening; and
singulating the first semiconductor die and the second semiconductor die after the plating the conductive material.

US Pat. No. 10,510,696

PAD STRUCTURE AND MANUFACTURING METHOD THEREOF IN SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming a memory cell on a substrate;
forming a conductive pad region to electrically couple to the memory cell;
depositing a dielectric layer over the conductive pad region;
forming a first passivation layer over the dielectric layer;
etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region;
forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and
etching the second passivation layer to expose a second area of the conductive pad region.

US Pat. No. 10,510,694

RADIO FREQUENCY COMMUNICATION SYSTEMS

Analog Devices, Inc., No...

1. A packaged radio frequency (RF) module comprising:a package substrate;
a first die electrically and mechanically attached to the package substrate, the first die comprising an RF switch;
a second die electrically and mechanically attached to the package substrate, the second die comprising an RF amplifier;
an encapsulating material protecting electrical connections between the first die and the package substrate; and
a lid attached to the package substrate such that the package substrate and the lid at least partially define an air cavity within which the first and the second die are mounted, an active surface of the second die being exposed to the air cavity.

US Pat. No. 10,510,693

SEMICONDUCTOR PACKAGE STRUCTURE

Taiwan Semiconductor Manu...

16. A semiconductor package structure comprising:a first insulating encapsulation;
a second insulating encapsulation disposed on the first insulating encapsulation, wherein a dissipation factor of the first insulating encapsulation is different from that of the second insulating encapsulation;
an RFIC chip encapsulated by the first insulating encapsulation;
a redistribution circuit structure disposed on the first insulating encapsulation and electrically connected to the RFIC chip;
a first patch antenna structure disposed at a lateral side of the RFIC chip and electrically connected to the RFIC chip through the redistribution circuit structure; and
a second patch antenna structure overlapped with the RFIC chip and electrically connected to the RFIC chip through the redistribution circuit structure, wherein the first patch antenna structure and the second patch antenna structure perform wireless communication respectively.

US Pat. No. 10,510,692

SEMICONDUCTOR DEVICE INCLUDING DUMMY CONDUCTIVE CELLS

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a plurality of metal layers comprising a plurality of empty areas and grouped into a plurality pairs of neighboring metal layers;
a plurality of first dummy conductive cells each formed in each of the empty areas in each of the plurality pairs of neighboring metal layers that is overlapped by another empty area or a line in the same pair of neighboring metal layers; and
a plurality groups of second dummy conductive cells, wherein each group of the second dummy conductive cells is formed in each of the empty areas in each of the plurality pairs of neighboring metal layers that is overlapped by a signal line in the same pair of neighboring metal layer.

US Pat. No. 10,510,691

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a first substrate including a first surface and a second surface opposite to the first surface;
a via extending through the first substrate;
a die disposed over the first surface of the first substrate;
a redistribution layer (RDL) disposed over the second surface of the first substrate, and including a dielectric layer over the second surface, a first conductive structure disposed within the dielectric layer and electrically connected to the via, and a second conductive structure disposed within the dielectric layer and electrically isolated from the via;
a second substrate including a third surface and a fourth surface opposite to the third surface;
a conductive bump disposed between the third surface of the second substrate and the RDL and bonding the first conductive structure with the second substrate; and
a first underfill material surrounding the first substrate, the RDL and the conductive bump,
wherein a height of the first conductive structure and a height of the second conductive structure are the same, and one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the first underfill material.

US Pat. No. 10,510,689

SOLDER BALL PROTECTION IN PACKAGES

Taiwan Semiconductor Manu...

1. A method comprising:placing a coated conductive ball on a metal feature, with the metal feature comprised in a chip, wherein the coated conductive ball comprises:
a conductive ball; and
a coating material at least encircling a middle portion of the conductive ball;
aligning the conductive ball to the metal feature, wherein during the aligning an electromagnetic field is applied on the conductive ball by conducting a current into a partially-looped metal trace to reposition the conductive ball relative the metal feature, the partially-looped metal trace is underlying and aligned to the metal feature; and
attaching the coated conductive ball to the metal feature.

US Pat. No. 10,510,688

VIA RAIL SOLUTION FOR HIGH POWER ELECTROMIGRATION

Taiwan Semiconductor Manu...

14. An integrated circuit, comprising:a plurality of gate structures arranged over a substrate between adjacent ones of a plurality of source/drain regions;
a plurality of conductive contacts arranged over the plurality of source/drain regions;
a first conductive interconnect wire arranged over the plurality of conductive contacts;
a second conductive interconnect wire arranged over the first conductive interconnect wire; and
a via rail configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire, wherein the via rail continuously extends directly over the plurality of gate structures, and wherein the first conductive interconnect wire and second conductive interconnect wire extend as continuous structures past opposing sides of the via rail.

US Pat. No. 10,510,684

THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) WITH SUPPORT STRUCTURES

Taiwan Semiconductor Manu...

10. A method of forming an integrated circuit, comprising:providing a first die having a first connecting structure and a support structure;
providing a second die having a second connecting structure;
bringing the first connecting structure into contact with the second connecting structure; and
heating the first connecting structure and the second connecting structure after bringing the first connecting structure into contact with the second connecting structure, wherein heating the first connecting structure and the second connecting structure performs a reflow process that forms a bonding structure from the first connecting structure and the second connecting structure, and wherein the support structure begins to adhere to the second die during the heating of the first connecting structure and the second connecting structure.

US Pat. No. 10,510,683

PACKAGING STRUCTURES FOR METALLIC BONDING BASED OPTO-ELECTRONIC DEVICE AND MANUFACTURING METHODS THEREOF

Tsinghua University, Hai...

1. A packaging structure for an opto-electronic device, comprising:an opto-electronic chip, comprising:
a substrate having a first substrate surface and a second substrate surface opposite to each other;
an opto-electronic device formed on the substrate; and
electrodes for the opto-electronic device which are formed on the first substrate surface; and
a packaging base having a first base surface and a second base surface opposite to each other, and comprising conductive channels extending from the first base surface to the second base surface,
wherein the opto-electronic chip is stacked with the packaging base in such a manner that the first substrate surface faces the packaging base, and the electrodes formed on the first substrate surface of the opto-electronic chip are bonded with corresponding conductive channels in the packaging base, and
wherein the electrodes are included in a metallization formed on the substrate.

US Pat. No. 10,510,682

SEMICONDUCTOR DEVICE WITH SHIELD FOR ELECTROMAGNETIC INTERFERENCE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first die in a molding layer;
a first redistribution structure on a first side of the molding layer and electrically coupled to the first die;
a second redistribution structure on a second side of the molding layer opposing the first side;
a first conductive structure in the molding layer and laterally spaced apart from the first die, wherein the first conductive structure comprises:
a first dielectric region around the first die; and
a first conductive coating on opposing sidewalls of the first dielectric region, the first conductive coating physically contacting the molding layer; and
a via in the molding layer and electrically coupled to the first redistribution structure and the second redistribution structure, wherein the via comprises:
a second dielectric region; and
a second conductive coating on sidewalls of the second dielectric region, wherein the second conductive coating extends further from a center axis of the via than the second dielectric region, the center axis of the via being perpendicular to the first side of the molding layer.

US Pat. No. 10,510,681

SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor die;
an insulative layer surrounding the semiconductor die, wherein the insulative layer includes an edge;
a conductive feature proximal to the edge of the insulative layer and extended through the insulative layer, wherein the conductive feature includes a lateral surface exposed from the edge of the insulative layer; and
an Electromagnetic Interference (EMI) shield in contact with the lateral surface of the conductive feature exposed from the edge of the insulative layer.

US Pat. No. 10,510,679

SEMICONDUCTOR DEVICE WITH SHIELD FOR ELECTROMAGNETIC INTERFERENCE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first die embedded in a molding material, wherein contact pads of the first die are proximate a first side of the molding material, wherein the first die has a plurality of conductive pillars, each of the plurality of conductive pillars electrically coupled to a respective one of the contact pads;
a redistribution structure over the first side of the molding material, wherein a via of the redistribution structure has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, the second dimension being smaller than the first dimension, wherein the first direction and the second direction are in a plane parallel to the first side of the molding material;
a first metal coating along and in physical contact with sidewalls of the first die, the first metal coating disposed between the first die and the molding material, wherein a first conductive pillar of the plurality of conductive pillars is electrically coupled to the first metal coating, wherein the via of the redistribution structure has a first surface closest to the first die, and the first surface of the via physically contacts the first conductive pillar and the first metal coating; and
a second metal coating along sidewalls of the molding material and along a second side of the molding material opposing the first side.

US Pat. No. 10,510,676

SYSTEM AND METHOD FOR ALIGNED STITCHING

Taiwan Semiconductor Manu...

1. A method, comprising:depositing a first dielectric layer over a substrate;
depositing a first photoresist over the first dielectric layer;
exposing the first photoresist to a first light-exposure through a first lithographic mask;
after exposing the first photoresist to the first light-exposure, exposing the first photoresist to a second light-exposure through a second lithographic mask, wherein:
a first overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure;
the first overlap region is interposed between a first active signal region and a second active signal region;
the first active signal region and the second active signal region are disposed in a same die;
the first light-exposure is used to image the first active signal region; and
the second light-exposure is used to image the second active signal region; and
after the exposing the first photoresist to the second light-exposure, developing the first photoresist and patterning the first dielectric layer to form a first mask overlay alignment feature, the first mask overlay alignment feature disposed in the first overlap region.