US Pat. No. 10,367,112

DEVICE FOR DIRECT X-RAY DETECTION

Nokia Technologies Oy, E...

1. An apparatus comprising:a plurality of substantially parallel conductive channels separated from one another by a quantum dot material comprising a plurality of quantum dots separated from one another by ligands having a chain length which is sufficiently short to facilitate transfer of an electron or a hole between neighboring quantum dots,
source and drain electrodes configured to enable a flow of electrical current through the conductive channels, and
a substrate configured to support the conductive channels, quantum dot material and source and drain electrodes, the conductive channels extending substantially perpendicular to the surface of the substrate,
wherein the quantum dot material is configured to generate an electron-hole pair on exposure to incident electromagnetic radiation, and
wherein the conductive channels and quantum dot material are configured such that another one of the electron or the hole of the electron-hole pair is transferred to one of the conductive channels leaving the remaining charge carrier in the quantum dot material, a diffusion length of the remaining charge carrier is limited by a dimension of the conductive channels rather than a thickness of the quantum dot material, the remaining charge carrier exhibiting an electric field which causes a change in electrical current passing through at least one of the conductive channels, the change in electrical current indicative of one or more of the presence and magnitude of the incident electromagnetic radiation.

US Pat. No. 10,367,108

PHOTODETECTION DEVICE AND IMAGING DEVICE

PANASONIC INTELLECTUAL PR...

1. A photodetection device, comprising:a photoelectric converter that generates charge;
a first charge transfer channel that has a first end and a second end, the first end being connected to the photoelectric converter, charge from the photoelectric converter being transferred in the first charge transfer channel in a first direction from the first end toward the second end;
a second charge transfer channel that diverges from the first charge transfer channel at a first position of the first charge transfer channel;
a third charge transfer channel that diverges from the first charge transfer channel at a second position of the first charge transfer channel, the second position being further than the first position from the first end in the first direction;
a first charge accumulator that accumulates charge transferred from the first charge transfer channel through the second charge transfer channel;
a second charge accumulator that accumulates charge transferred from the first charge transfer channel through the third charge transfer channel;
a first gate electrode that switches between transfer and cutoff of charge in the first charge transfer channel; and
at least one second gate electrode that switches between transfer and cutoff of charge in the second charge transfer channel, and that switches between transfer and cutoff of charge in the third charge transfer channel, wherein
a width of the third charge transfer channel is greater than a width of the second charge transfer channel in a plan view.

US Pat. No. 10,367,105

SOLAR CELL, SOLAR CELL MODULE, AND MANUFACTURING METHOD FOR SOLAR CELL

Panasonic Intellectual Pr...

1. A solar cell comprising:a photoelectric converter that includes a light receiving surface and a back surface opposed to the light receiving surface and includes n-type regions and p-type regions which are alternately arranged in a first direction on the back surface; and
an electrode layer that is provided only on the back surface, wherein
the photoelectric converter includes a plurality of sub-cells arranged in a second direction intersecting with the first direction and an isolation region provided between adjacent sub-cells,
the electrode layer includes an n-side electrode which is provided on the n-type regions in a first sub-cell at an end of the plurality of sub-cells and disposed within the first sub-cell, a p-side electrode which is provided on the p-type regions in a second sub-cell at the other end of the plurality of sub-cells and disposed within the second sub-cell, and a plurality of sub-electrodes which are provided over two adjacent sub-cells,
each sub-electrode of the plurality of sub-electrodes comprises:
a plurality of n-side parts which are provided on the n-type regions in one sub-cell of the two adjacent sub-cells;
a plurality of p-side parts which are provided on the p-type regions in the other sub-cell of the two adjacent sub-cells; and
a plurality of connection parts, each connecting one of the plurality of n-side parts and one of the plurality of p-type parts, and
in plan view, the plurality of connection parts are arranged along the first direction and spaced apart from each other over the isolation region, wherein
the photoelectric converter further includes:
a first conductivity type layer on the back surface, which forms the n-type regions;
a second conductivity type layer on the back surface, which forms the p-type regions; and
a third conductivity type layer on the light receiving surface, the third conductivity type layer having a first surface facing the light receiving surface of the substrate, and a second surface opposite to the first surface, and
the isolation region extends from the second surface of the third conductivity type layer to the back surface of the substrate through the third conductivity type layer and the substrate.

US Pat. No. 10,367,104

SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A solar cell, comprising:a semiconductor substrate;
a conductive region on or at the semiconductor substrate;
an electrode electrically connected to the conductive region; and
a passivation layer on a light incident surface of the semiconductor substrate,
wherein the passivation layer comprises a first layer in contact with the light incident surface of the semiconductor substrate and formed of silicon oxynitride for ultraviolet stability,
wherein the first layer comprises a plurality of phases of the silicon oxynitride,
wherein the plurality of phases are formed of the same material of the silicon oxynitride having different compositions,
wherein the plurality of phases comprises a plurality of first phases and a plurality of second phases,
wherein the plurality of first phases have a higher oxygen content and a lower nitrogen content than that of the plurality of the second phases, and
wherein the plurality of first phases and the plurality of second phases are alternatively positioned in a thickness direction of the first layer,
wherein the plurality of first phases are in contact with the semiconductor substrate, and
wherein the plurality of first phases have different oxygen and nitrogen content from each other, or the plurality of second phases have different oxygen and nitrogen content from each other.

US Pat. No. 10,367,103

PHOTOELECTRIC CONVERSION ELEMENT

Ricoh Company, Ltd., Tok...

1. A photoelectric conversion element comprising:a first electrode having opaqueness to light and formed of a metal;
a hole blocking layer provided on the first electrode;
an electron transport layer provided on the hole blocking layer;
a hole transport layer provided on the electron transport layer; and
a second electrode provided on the hole transport layer and having transmissivity to light,
wherein
the hole blocking layer comprises an oxide of the metal in the first electrode, and the hole transport layer comprises a basic compound of formula (1):

wherein R1 and R2 represent a substituted or unsubstituted alkyl group or aromatic hydrocarbon group and may be identical or different, and R1 and R2 may bind with each other to form a substituted or unsubstituted heterocyclic group comprising a nitrogen atom.

US Pat. No. 10,367,101

SCHOTTKY DIODE AND METHOD OF MANUFACTURING THE SAME

GPOWER SEMICONDUCTOR, INC...

1. A Schottky diode, comprising:a substrate;
a first semiconductor layer located on the substrate;
a second semiconductor layer located on the first semiconductor layer, two-dimensional electron gas being formed at an interface between the first semiconductor layer and the second semiconductor layer;
a cathode located on the second semiconductor layer and forming an ohmic contact with the second semiconductor layer;
a first passivation dielectric layer located on the second semiconductor layer;
a field plate groove formed in the first passivation dielectric layer; and
an anode covering the field plate groove and a portion of the first passivation dielectric layer,
wherein a distance between a bottom surface of the field plate groove and the two-dimensional electron gas in a height direction is greater than 5 nm.

US Pat. No. 10,367,098

VERTICAL JFET MADE USING A REDUCED MASKED SET

United Silicon Carbide, I...

1. A vertical JFET, comprising:a) a substrate, the substrate having a top and a bottom vertically, the substrate having a perimeter horizontally;
b) a backside drain connection, the backside drain connection being on the bottom of the substrate; and
c) on the top of the substrate, an active cell region and a termination region, the active cell region and the termination region each comprising a plurality of mesas and a plurality of trenches;
d) wherein each mesa comprises gate-doped regions on the sides of the mesa, a source-doped region at the top of the mesa, and, between the gate-doped regions and below the source-doped region, a channel region;
e) wherein each mesa further comprises, atop the source-doped region, a source contact silicide region; and
f) wherein each trench comprises, at the bottom of the trench, a gate-doped region connecting to the gate-doped regions of the mesa, and atop the gate-doped region of the trench, a gate contact silicide region;
g) the vertical JFET further comprising a gate buss connecting the gate contact silicide regions of the active cell region, and a source buss connecting the source contact silicide regions of the active cell region;
h) wherein the gate contact silicide regions and the source contact silicide regions of the termination region are individually ohmically isolated from each other, from the gate buss, and from the source buss; and
i) wherein the doping levels of the gate-doped regions, the source-doped regions, and the channel regions, and the width of the mesas in the termination region, are selected such that a punch through voltage of the mesas of the termination region is less than a breakdown voltage of a P-N junction between the gate-doped region and the source-doped region of each mesa of the termination region, such that an off-state blocking voltage of the vertical JFET is the sum of the punch-through voltages of the P-N junctions of the gate-doped regions and the source-doped regions of the termination region.

US Pat. No. 10,367,097

LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A liquid crystal display device, comprising:a first substrate and a second substrate spaced apart from each other;
a liquid crystal layer between the first substrate and the second substrate;
a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate;
a first switching element connected to the gate line, the data line, and the first sub-pixel electrode; and
a second switching element connected to the gate line, the first sub-pixel electrode, and the second sub-pixel electrode,
wherein the first switching element has a threshold voltage that is lower than a threshold voltage of the second switching element, and
wherein the first switching element includes a semiconductor layer having a thickness that is 1/y times a thickness of a semiconductor layer of the second switching element, y being a rational number greater than or equal to 3.

US Pat. No. 10,367,096

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, MODULE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductor;
a second conductor;
a third conductor;
a fourth conductor;
a fifth conductor;
a first insulator;
a second insulator;
a third insulator;
a fourth insulator;
a fifth insulator;
a semiconductor; and
an opening,
wherein the second insulator is over the first insulator,
wherein the semiconductor is over the second insulator,
wherein the first conductor and the second conductor are over the semiconductor,
wherein the third conductor is over the first conductor,
wherein the fourth conductor is over the second conductor,
wherein the third insulator is over the first insulator, the semiconductor, the first conductor, the second conductor, the third conductor, and the fourth conductor,
wherein the opening exposes part of the first insulator, part of the semiconductor, part of the first conductor, part of the second conductor, part of the third conductor, and part of the fourth conductor,
wherein the fourth insulator is along a side surface and a bottom surface of the opening,
wherein the fifth insulator is over the fourth insulator,
wherein the fifth conductor comprises a region overlapping with the semiconductor with the fourth insulator and the fifth insulator therebetween, the region being included in the opening,
wherein the first conductor has a shape such that an end portion of the first conductor inwardly extends beyond an end portion of the second third conductor in the opening, and
wherein the second conductor has a shape such that an end portion of the second conductor inwardly extends beyond an end portion of the fourth conductor in the opening.

US Pat. No. 10,367,094

SOURCE/DRAIN STRUCTURE HAVING MULTI-FACET SURFACES

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a semiconductor substrate having a source/drain region and a gate region;
a fin structure disposed over the semiconductor substrate, the fin structure including a first portion having a first height in the source/drain region and a second portion having a second height in the gate region, the second height being different than the first height;
a gate structure disposed over the first portion of the fin structure, the gate structure including a gate dielectric physically contacting the first portion of the fin structure;
a plurality of isolation regions over the semiconductor substrate; and
a source/drain feature disposed over the second portion of the fin structure in the source/drain region, the source/drain feature including:
multiple lower portions that are isolated from each other by a lateral separation; and
a single upper portion over the isolation regions, wherein the single upper portion is merged from the multiple lower portions, wherein the single upper portion has a top surface facing away from a top surface of the isolation regions, wherein the top surface of the single upper portion includes a first flat surface connected to a first multi-facet surface and a second flat surface connected to the first multi-facet surface.

US Pat. No. 10,367,093

METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL

1. An apparatus comprising:a substrate comprising Si;
a fin comprising Si on the substrate;
a gate electrode having a work function metal comprising: W, Ta, Ti, and N;
a first spacer;
a second spacer, wherein the first and second spacers comprise N;
a gate dielectric between: the gate electrode and the fin, the gate electrode and the first spacer, and the gate electrode and the second spacer, wherein the gate dielectric comprises Hf and O,
a source; and
a drain;
wherein:
a portion of the fin under the gate electrode has a first width,
a portion of the fin outside the gate electrode and closer to the drain or source regions has a second width, and
the second width is greater than the first width.

US Pat. No. 10,367,090

SILICON CARBIDE SEMICONDUCTOR DEVICE, POWER MODULE, AND POWER CONVERSION DEVICE

Hitachi, Ltd., Tokyo (JP...

1. A silicon carbide semiconductor device comprising:a semiconductor substrate which includes an n-type substrate containing silicon carbide and an n-type semiconductor layer containing silicon carbide formed over the n-type substrate, the semiconductor substrate having an element region and a first region surrounding the element region in plan view;
a p-type first semiconductor region formed on an upper surface of the semiconductor substrate within the element region;
an n-type source region formed on an upper surface of the first semiconductor region;
a p-type first contact region formed on the upper surface of the first semiconductor region;
a p-type second semiconductor region formed on the upper surface of the semiconductor substrate within the first region and surrounding the element region in plan view;
a p-type second contact region formed on an upper surface of the second semiconductor region and surrounding the element region in plan view;
an n-type drain region formed on a lower surface of the semiconductor substrate;
a gate electrode formed on the upper surface of the first semiconductor region adjacent to the source region via an insulating film;
a first electrode formed on the second contact region; and
a conductive connecting portion formed on the second contact region and electrically connecting the first electrode and the second contact region to each other,
wherein the gate electrode, the source region and the drain region configure a field effect transistor, and
the second semiconductor region and the semiconductor substrate configure a diode.

US Pat. No. 10,367,087

TRANSISTOR STRUCTURE INCLUDING A SCANDIUM GALLIUM NITRIDE BACK-BARRIER LAYER

1. A transistor comprising:a substrate;
a buffer layer disposed on the substrate;
a back-barrier layer on the buffer layer, the back-barrier layer including scandium gallium nitride;
a channel layer disposed on the back-barrier layer; and
a barrier layer disposed on the channel layer.

US Pat. No. 10,367,080

METHOD OF FORMING A GERMANIUM OXYNITRIDE FILM

ASM IP Holding B.V., Alm...

1. A method of forming a germanium oxynitride film comprising:providing a substrate for processing in a reaction chamber;
using a germanium precursor and an oxygen precursor, performing an atomic layer deposition cycle of an oxide comprising germanium onto the substrate; and
before or after performing the atomic layer deposition cycle of the oxide, using a germanium precursor and a nitrogen precursor, performing an atomic layer deposition cycle of a nitride comprising germanium onto the substrate;
wherein the atomic layer deposition cycle of the oxide and the atomic layer deposition cycle of the nitride are repeated as desired in order to form the germanium oxynitride film of a desired thickness and stoichiometry, and
wherein the oxygen precursor and the nitrogen precursor are different.

US Pat. No. 10,367,079

METHOD AND STRUCTURE FOR FINFET COMPRISING PATTERNED OXIDE AND DIELECTRIC LAYER UNDER SPACER FEATURES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate having a fin projecting upwardly through an isolation structure over the substrate;
a gate stack over the isolation structure and engaging the fin;
a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack;
a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity; and
a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials, wherein the second dielectric layer is in physical contact with the gate spacer.

US Pat. No. 10,367,078

SEMICONDUCTOR DEVICES AND FINFET DEVICES HAVING SHIELDING LAYERS

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate; and
a gate structure over the substrate and comprising:
a high-k layer over the substrate;
a shielding layer over the high-k layer; and
an N-type work function metal layer over the shielding layer,
wherein a dielectric constant of the shielding layer is less than a dielectric constant of the high-k layer.

US Pat. No. 10,367,075

APPROACH TO PREVENTING ATOMIC DIFFUSION AND PRESERVING ELECTRICAL CONDUCTION USING TWO DIMENSIONAL CRYSTALS AND SELECTIVE ATOMIC LAYER DEPOSITION

INTERNATIONAL BUSINESS MA...

1. A method of restricting diffusion of miscible materials across a barrier, comprising:forming a plug selectively on each portion of a substrate surface exposed through one or more defects in a 2-dimensional material on the substrate surface; and
forming a solid cover layer on the plug and 2-dimensional material, wherein at least a component of the solid cover layer material is miscible in the substrate material.

US Pat. No. 10,367,073

THIN FILM TRANSISTOR (TFT) WITH STRUCTURED GATE INSULATOR

BOE TECHNOLOGY GROUP CO.,...

1. A thin-film transistor (TFT), comprising:a base substrate;
a gate electrode and a gate insulating layer, disposed on the base substrate; and
an active layer, wherein the gate insulating layer is disposed between the active layer and the gate electrode;
the active layer includes a channel region and a doped region disposed on at least one side of the channel region; and
the gate insulating layer is provided with a protrusion which is disposed between the doped region and the gate electrode,
wherein, the protrusion includes a first protrusion and a second protrusion which are spaced from each other, the doped region includes a first doped region and a second doped region which are respectively disposed on both sides of the channel region,
the first doped region comprises a first lightly doped region and a first heavily doped region, the second doped region comprises a second lightly doped region and a second heavily doped region, and a carrier concentration of the first lightly doped region and the second lightly doped region is smaller than a carrier concentration of the first heavily doped region and the second heavily doped region,
the first protrusion further includes a first exposing portion, an orthographic projection of the first exposing portion on the base substrate exceeds an orthographic projection of the gate electrode on the base substrate;
the second protrusion further includes a second exposing portion, an orthographic projection of the second exposing portion on the base substrate exceeds the orthographic projection of the gate electrode on the base substrate, and the first exposing portion at least partially overlaps with the first lightly doped region, the second exposing portion at least partially overlaps with the second lightly doped region,
the gate insulating layer further includes a spacing region disposed between the first protrusion and the second protrusion, and the spacing region is disposed between the gate electrode and the channel region, the spacing region completely overlaps with the channel region, and
the gate insulating layer includes a planarization portion disposed outside the first protrusion and the second protrusion and overlapped with the first heavily doped region and the second heavily doped region,
a thickness of the protrusion is larger than a thickness of the spacing region and a thickness of the planarization portion.

US Pat. No. 10,367,070

METHODS OF FORMING BACKSIDE SELF-ALIGNED VIAS AND STRUCTURES FORMED THEREBY

Intel Corporation, Santa...

1. A microelectronic structure comprising:a substrate;
a device layer on the substrate;
at least one device within the device layer, wherein the at least one device comprises a gate electrode between a source region and a/drain region;
a first source contact coupled to a first side of the source region;
a first drain contact coupled to a first side of the drain region;
a second source contact coupled to a second side of the source region; and
a second drain contact coupled to a second side of the drain region, wherein the source region and the drain region comprise an epitaxial material, wherein the epitaxial material comprises silicon and germanium.

US Pat. No. 10,367,067

SEMICONDUCTOR DEVICE HAVING AN OXYGEN DIFFUSION BARRIER

Infineon Technologies AG,...

1. A semiconductor device, comprising:a semiconductor body comprising opposite first and second surfaces;
a drift or base zone in the semiconductor body;
an oxygen diffusion barrier comprising SiGe and formed in the semiconductor body, wherein the drift or base zone is located between the first surface and the oxygen diffusion barrier and directly adjoins the oxygen diffusion barrier; and
first and second load terminal contacts, wherein at least one of the first and the second load terminal contacts is electrically connected to the semiconductor body through the first surface.

US Pat. No. 10,367,066

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing a thin film transistor, wherein the thin film transistor is provided with a gate layer, a gate insulation layer, an IGZO (indium gallium zinc oxide) layer, a source, and a drain in sequence from inside to outside, and each of the source and the drain is provided with a first metal layer, a second metal layer, and a third metal layer in sequence from inside to outside, the first metal layer being in contact with the IGZO layer, andwherein the method comprises the following steps:
Step I. sequentially preparing the gate layer, the gate insulation layer, and the IGZO layer on a substrate;
Step II. preparing the source and the drain, and sequentially preparing the first metal layer, the second metal layer, and the third metal layer on each of the gate insulation layer and the IGZO layer;
Step III. preparing passivation layers; and
Step IV. performing high temperature annealing treatment on the passivation layers, indium within the first metal layer diffusing into the IGZO layer to form metal diffusion layers, thereby forming Ohmic contact at interfaces both between the IGZO layer and the source and between the IGZO layer and the drain.

US Pat. No. 10,367,063

SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET INTERCONNECTING A SOURCE REGION AND A DRAIN REGION

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor device, the method comprising:forming a first semiconductor layer over a substrate;
forming a second semiconductor layer over the first semiconductor layer;
forming a third semiconductor layer over the second semiconductor layer;
forming a recess that extends through the second and third semiconductor layers and into the first semiconductor layer; and
forming a silicide that contacts and surrounds the third semiconductor layer following the formation of the recess.

US Pat. No. 10,367,060

III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION

International Business Ma...

1. A method for fabricating a semiconductor device with selective oxidation, the method comprising:depositing a stack of two crystalline semiconductor layers over a base layer, wherein the base layer comprises a semiconductor substrate and a first insulator layer, and wherein the semiconductor substrate is 100 nanometers to 1 micrometer in thickness;
performing shallow trench isolation within the base layer to form a plurality of trenches that expose a set of sides of the two crystalline semiconductor layers;
depositing a second insulator layer into the plurality of trenches of the base layer;
selectively oxidizing a first of the two crystalline semiconductor layers to yield a selectively oxidized layer that serves as an insulator for a second of the two crystalline semiconductor layers, wherein the stack of two crystalline semiconductor layers maintain a layered configuration after oxidation of the first of the two crystalline semiconductor layers;
forming a dummy gate structure, wherein a set of spacers are along sides of the dummy gate structure;
forming source and drain regions in contact with each exposed side of the set of sides of the oxidized first semiconductor layer and the second semiconductor layer of the two crystalline semiconductor layers;
depositing an insulating material;
planarizing the deposited insulator material until the dummy gate structure is exposed;
removing the dummy gate structure;
etching the selectively oxidized crystalline semiconductor layer;
forming a replacement gate layer between a plurality of walls within the set of spacers;
depositing a high-K insulator around the replacement gate layer; and
rendering a second of the two crystalline semiconductor layers as a channel region.

US Pat. No. 10,367,058

CHANNEL STOP IMP FOR THE FINFET DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:providing a substrate structure including a substrate, at least one semiconductor fin on the substrate entirely formed with a same material as the substrate, and an isolation region on opposite sides of the at least one semiconductor fin;
implanting ions into the substrate structure to form a doped region in the at least one semiconductor fin and in the isolation region;
etching back the isolation region to expose a portion of the at least one semiconductor fin; and
after the isolation region has been etched back, performing an annealing process to activate the implanted ions in the doped region,
wherein providing the substrate structure comprises:
providing an initial substrate;
forming a patterned hardmask on the initial substrate;
etching the initial substrate using the patterned hardmask as a mask to form the substrate, the at least one semiconductor fin, and a recess on the opposite sides of the at least one semiconductor fin;
depositing an isolation material filing the recess and covering the hardmask;
planarizing the isolation material in the recess so that the upper surface of isolation material is substantially flush with the upper surface of the hardmask;
etching back the planarized isolation material to expose a side surface of the hardmask; and
removing the hardmask to form the substrate structure.

US Pat. No. 10,367,056

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a first semiconductor region of a second conductivity type selectively provided on a semiconductor substrate of a first conductivity-type;
a second semiconductor region of the second conductivity type surrounding a periphery of the first semiconductor region;
a third semiconductor region of the first conductivity type provided outside of the second semiconductor region;
a fourth semiconductor region of the second conductivity type selectively provided in the third semiconductor region;
a fifth semiconductor region of the second conductivity type selectively provided in one of the first semiconductor region and the second semiconductor region, an impurity concentration of the fifth semiconductor region being higher than that of the second semiconductor region;
a first gate electrode provided on a surface of a portion of the third semiconductor region between the fourth semiconductor region and the second semiconductor region, the first gate electrode provided via a first gate insulating film;
a first electrode contacting the third semiconductor region and the fourth semiconductor region;
a second electrode contacting the fifth semiconductor region;
a sixth semiconductor region of the second conductivity type selectively provided in one of the first semiconductor region and the second semiconductor region, separate from the fifth semiconductor region, an impurity concentration of the sixth semiconductor region being higher than that of the second semiconductor region;
a seventh semiconductor region of the first conductivity type selectively provided in the third semiconductor region, an impurity concentration of the seventh semiconductor region being higher than that of the third semiconductor region, wherein the first electrode is in contact with the seventh semiconductor region; and
a third electrode contacting the sixth semiconductor region, wherein
a first distance between the fourth semiconductor region and the fifth semiconductor region is a drift length of a first element,
a second distance between the seventh semiconductor region and the sixth semiconductor region is a drift length of a second element different from the first element, and
the first distance is longer than the second distance.

US Pat. No. 10,367,054

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a plurality of control gate electrodes arranged in a first direction, the first direction intersecting a surface of a substrate;
a first semiconductor layer extending in the first direction and facing side surfaces of the plurality of the control gate electrodes in a second direction, the second direction intersecting the first direction; and
a gate insulating layer provided between the control gate electrode and the first semiconductor layer,
the first semiconductor layer including:
a first portion extending from an end section on a substrate side of the first semiconductor layer to a central region in the first direction of the first semiconductor layer; and
a second portion positioned further from the substrate than the first portion of the first semiconductor layer, and
the first portion having a first crystal plane orientation; and
the second portion having a second crystal plane orientation which is different from the first crystal plane orientation.

US Pat. No. 10,367,053

APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT

Micron Technology, Inc., ...

1. An apparatus comprising:a transistor area comprising at least one n-channel transistor and at least one p-channel transistor, the at least one n-channel transistor and the at least one p-channel transistor being disposed relative to each other in a first direction;
a resistor area comprising at least one resistor, the resistor area being disposed relative to the transistor area in a second direction, the second direction crossing the first direction; and
a delay circuit comprising a logic circuit and the at least one resistor coupled to the logic circuit, wherein the at least one resistor is disposed relative to the logic circuit in the second direction crossing the first direction;
wherein the logic circuit is between the at least one n-channel transistor and the at least one p-channel transistor in the first direction, and wherein the at least one resistor extending in the first direction greater than a size of the logic circuit.

US Pat. No. 10,367,051

ACTIVE-MATRIX DISPLAY DEVICE

JOLED INC., Tokyo (JP)

1. An active-matrix display device, comprising:a pixel matrix that includes a plurality of pixel cells arranged in rows and columns;
a first global power supply wire that is disposed for each of the columns in the pixel matrix and is connected to each of the plurality of pixel cells in the column; and
a second global power supply wire that is disposed for each of the columns in the pixel matrix and is connected to each of the plurality of pixel cells in the column,
wherein each of the plurality of pixel cells includes a first local power supply wire that is directly connected to the first global power supply wire,
each of the plurality of pixel cells includes a second local power supply wire that is directly connected to the second global power supply wire,
all of the plurality of pixel cells in each column are connected to both the first global power supply wire and the second global power supply wire, and
the first local power supply wire does not overlap the second global power supply wire in a plan view of the pixel matrix.

US Pat. No. 10,367,048

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Japan Display Inc., Mina...

1. A display device comprising:a first insulating substrate including a display area and a drive area;
an emitting layer in the display area;
a protective film covering the emitting layer;
a resin base at a position upper than the protective film;
a first adhesive layer under the resin base, in the display area and the drive area;
a second adhesive layer on the resin base; and
a polarizer provided at a position upper than the resin base,
the second adhesive layer covering the drive area and an end portion of the resin base,
the resin base being located between the first adhesive layer and the second adhesive layer in the drive area,
wherein
the resin base is a light transmitting film,
a third adhesive layer is located between the polarizer and the light transmitting film,
the drive area includes a first side connected to the emitting layer and a second side connected to a drive component driving the emitting layer, and
an end portion of the light transmitting film is located more closely to the second side than an end portion of the polarizer.

US Pat. No. 10,367,043

DISPLAY DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a first flexible substrate;
a second flexible substrate overlapping the first flexible substrate with a display element positioned therebetween;
a terminal electrode provided over the first flexible substrate, the terminal electrode electrically connected to a first part of an external electrode; and
a first layer covering a bottom surface and side surfaces of the first flexible substrate, and a top surface and side surfaces of the second flexible substrate,
wherein an entire outer surface of the first layer is exposed, and
wherein the first layer has a smaller Young's modulus than the first flexible substrate and the second flexible substrate.

US Pat. No. 10,367,042

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a plurality of organic emitting elements;
an element substrate which has a first surface including a display region on which the plurality of organic elements are arranged, the first surface including a peripheral region surrounding the display region;
an IC chip;
a thermal dispersion film on a second surface of the element substrate, the second surface being opposite to the first surface; and
a metal film on the second surface, wherein
in plan view, the element substrate has a first side, a second side, a third side facing the first side, and a fourth side facing the second side, a first length of each of the first and third sides is longer than a second length of each of the second and fourth sides,
the thermal dispersion film overlaps the IC chip in plan view,
the metal film overlaps the display region, and
a first plane area of the thermal dispersion film is smaller than a second plane area of the metal film.

US Pat. No. 10,367,040

DISPLAY PANEL HAVING FORCE SENSING FUNCTION

HON HAI PRECISION INDUSTR...

1. A display panel comprising:a substrate;
at least one thin film transistor (TFT) on the substrate; and
a force sensor configured to detect touch force on the display panel;
wherein the force sensor comprises a first conductive layer on the substrate and a second conductive layer; wherein the first conductive layer is located between the at least one TFT and the substrate; the second conductive layer is located at a side of the substrate away from the at least one TFT.

US Pat. No. 10,367,038

ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF, AND ORGANIC LIGHT-EMITTING DIODE DISPLAY

Shenzhen China Star Optoe...

1. A manufacturing method of organic light-emitting diode display device, wherein comprises:arranging a color conversion layer on the substrate by wet film formation; arranging a thin film transistor array, an anode, a hole injection layer and a hole transport layer, a blue light emitting layer, an electron transport layer, an electron injection layer, and a cathode, sequentially;
wherein the color conversion layer comprises red light conversion units, green light conversion units, and opening units which are arranged separately; the red light conversion unit and the green light conversion unit are both film layers made of an organometallic halide perovskite material; the red light conversion unit and the green light conversion unit absorb respectively blue light emitted from the blue light emitting layer and convert the blue light into red light and green light, and the opening unit transmits the blue light to achieve color display;
wherein the organometallic halide perovskite material is a single material containing an organometallic halide perovskite material or a mixed material containing a plurality of organometallic halide perovskite materials; and
wherein the organometallic halide perovskite material has the structural formula CH3NH3PbA3, wherein A is at least one element of chlorine, bromine, and iodine.

US Pat. No. 10,367,034

LUMINAIRE UTILIZING A TRANSPARENT ORGANIC LIGHT EMITTING DEVICE DISPLAY

ABL IP HOLDING LLC, Cony...

1. A transparent display panel, comprising:(a) an array of display pixels configured on a same substrate, wherein the array has horizontal and vertical dimensions on the substrate and each respective display pixel of the array comprises:
a plurality of separately controllable organic light emitting diodes (OLEDs), each of the OLEDs configured one upon another to form an OLED stack on the substrate, wherein each separately controllable OLED is constructed to emit visible light of a different respective one of three colors,
a first of the plurality of OLEDs being stacked on a light emitting surface of a second of the plurality of OLEDs and the second of plurality of OLEDs being stacked on a light emitting surface of a third of the plurality of OLEDs so that: light from a light emitting surface of the third OLED passes through the second and first OLEDs, light from a light emitting surface of the second OLED passes through the first OLED, and light emerging from a light emitting surface of the first OLED includes light emitted by the first OLED as well as light emitted by the second and third OLEDs; and
(b) a transparent region on the substrate adjacent to the OLED stack of the respective display pixel, wherein the transparent region is configured horizontally and vertically on the substrate in-between the OLED stack of the respective display pixel and the OLED stack of at least another adjacent display pixel in the array, and is formed from a transparent material.

US Pat. No. 10,367,030

PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE

CANON KABUSHIKI KAISHA, ...

1. A device comprising:a substrate which is provided with a photoreceiving portion and a transistor including a gate electrode;
a wiring which is arranged above the substrate;
an insulation film which is arranged between the wiring and the substrate, the insulation film having an opening above the photoreceiving portion, the insulation film containing Si and O;
a region which is arranged in the opening, wherein a material of the region is in contact with the insulating film;
a first portion which is arranged between the region and the photoreceiving portion, the first portion containing Si and N; and
a second portion which is arranged between the insulation film and the substrate, the second portion containing Si and N,
wherein a first distance between the region and the substrate through the first portion is smaller than a second distance between the insulation film and the substrate through the second portion, and a difference between the first distance and the second distance is smaller than a thickness of the gate electrode.

US Pat. No. 10,367,029

IMAGE SENSORS HAVING A SEPARATION IMPURITY LAYER

Samsung Electronics Co., ...

1. An image sensor, comprising:a semiconductor layer of a first conductivity;
a separation impurity layer of the first conductivity, the separation impurity layer in the semiconductor layer and defining a photoelectric conversion region and a readout circuit region;
at least one photoelectric conversion layer of a second conductivity, the at least one photoelectric conversion layer in the semiconductor layer of the photoelectric conversion region and surrounded by the separation impurity layer;
a floating diffusion region of the second conductivity, the floating diffusion region spaced apart from the at least one photoelectric conversion layer and in the semiconductor layer of the photoelectric conversion region;
a transfer gate electrode between the at least one photoelectric conversion layer and the floating diffusion region; and
impurity regions of the second conductivity, the impurity regions in the semiconductor layer of the readout circuit region,
wherein in response to the at least one photoelectric conversion layer being integrated with photo charges, the separation impurity layer has a first potential level around the at least one photoelectric conversion layer and a second potential level on a portion between the at least one photoelectric conversion layer and the impurity regions of the readout circuit region, the second potential level being greater than the first potential level.

US Pat. No. 10,367,027

SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A camera module, comprising:a plurality of lenses;
an imaging device, including:
green pixels including a first green pixel and a second green pixel disposed diagonally in a single line,
wherein the first green pixel is disposed between a first red pixel and a second red pixel in a horizontal direction,
wherein the second green pixel is disposed between a first blue pixel and a second blue pixel in the horizontal direction,
wherein a size of the first blue pixel is smaller than a size of the first green pixel,
wherein a size of the second blue pixel is smaller than the size of the first green pixel, andwherein the plurality of lenses focus an incident light on the camera module.

US Pat. No. 10,367,024

SEMICONDUCTOR IMAGE SENSORS HAVING CHANNEL STOP REGIONS AND METHODS OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a light-receiving element which outputs electric charges in response to incident light; and
a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current that is proportional to the incident light, wherein the drive transistor comprises:
a first gate electrode;
a first channel region under the first gate electrode;
first and second source-drain regions which are disposed at respective ends of the first channel region, the first and second source-drain regions having a first conductivity type;
a first channel step region on a first side of the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type; and
a second channel stop region is on a second side of the first channel region that is opposite the first side of the first channel region,
wherein the first channel region includes a first segment under the first gate electrode that extends in a first direction and a second segment under the first gate electrode that extends in a second direction that intersects the first direction, and
wherein a first end of the first segment directly connects to the first source-drain region, a second end of the first segment directly connects to a first end of the second segment and a second end of the second segment directly connects to the second source-drain region.

US Pat. No. 10,367,023

SEMICONDUCTOR IMAGE SENSOR

Taiwan Semiconductor Manu...

1. An image sensor integrated chip, comprising:an image sensing element arranged within a pixel region of a substrate;
a first dielectric disposed in trenches within a first side of the substrate, wherein the trenches are defined by first sidewalls disposed on opposing sides of the pixel region; and
an internal reflection structure arranged along the first side of the substrate and configured to reflect radiation exiting from the substrate back into the substrate, wherein the substrate includes a recessed portion arranged along the first side of the substrate and defined by second sidewalls of the substrate directly over the image sensing element, the second sidewalls of the substrate are angled to intersect at a point disposed along a horizontal plane that intersects the first sidewalls.

US Pat. No. 10,367,022

SOLID-STATE IMAGING DEVICE, MEMBERS FOR THE SAME, AND IMAGING SYSTEM

CANON KABUSHIKI KAISHA, ...

1. A device comprising:a first semiconductor substrate which is provided with a first transistor and a photoelectric conversion element, the first semiconductor substrate having a first face where the first transistor is provided and having a second face on the opposite side of the first face of the first semiconductor substrate;
a first wiring layer which includes a first wiring being connected to the first transistor, the first wiring being made mainly of copper;
a second semiconductor substrate which is provided with a second transistor, the second semiconductor substrate having a first face where the second transistor is provided and having a second face on the opposite side of the first face of the second semiconductor substrate;
a second wiring layer which includes a second wiring being connected to the second transistor, the second wiring being made mainly of copper;
a first layer which includes a pad being in contact with an external terminal, the pad being made mainly of aluminum; and
a second layer which includes a first portion arranged between the pad and the second semiconductor substrate,
wherein the first wiring layer is arranged between the first semiconductor substrate and the second wiring layer,
wherein the first semiconductor substrate has an opening, the second wiring layer includes a second portion arranged between the opening and the second semiconductor substrate, and the pad is electrically connected to the second portion via the first portion, and
wherein a distance between the first layer and the first face of the second semiconductor substrate is smaller than a distance between the second face of the first semiconductor substrate and the first face of the second semiconductor substrate, and is larger than a distance between the first wiring layer and the first face of the second semiconductor substrate.

US Pat. No. 10,367,020

POLARIZERS FOR IMAGE SENSOR DEVICES

Taiwan Semiconductor Manu...

1. A semiconductor image sensor device, comprising:a semiconductor layer comprising one or more sensing regions configured to sense radiation;
a grid structure, over the semiconductor layer, that comprises one or more cells respectively aligned to the one or more sensing regions; and
a polarizing grating structure in the one or more cells of the grid structure, wherein the polarizing grating structure is configured to polarize light incoming to the semiconductor image sensor device and comprises grating elements with an anti-reflective layer disposed on a metal layer.

US Pat. No. 10,367,016

METHOD FOR MANUFACTURING TFT SUBSTRATE

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing a TFT (Thin-Film Transistor) substrate, comprising steps of:providing a substrate;
utilizing a first photomask process to form a buffer layer, a data line, and a source electrode on the substrate and dispose a first scan line, a second scan line, and a gate electrode on the buffer layer, the data line configured to electrically connect to the source electrode, the second scan line configured to electrically connect to the gate electrode, and the gate electrode being shaped as a bulk and surrounding the source electrode;
utilizing a second photomask process to form a first insulation layer on the buffer layer and the gate electrode, form a second insulation layer on the data line, form a first semiconductor layer on the first scan line and the second scan line, and form a second semiconductor layer on the source electrode;
coating a photoresist material on the substrate, and utilizing a third photomask process to expose the first semiconductor layer by a full exposure applied to the photoresist material on the first semiconductor layer, and to form a first photoresist layer on the second insulation layer and the second semiconductor layer and form a second photoresist layer on the first insulation layer by a half exposure applied to the photoresist material on the second insulation layer and the second semiconductor layer;
making the first semiconductor layer become a conductor to form a first conductor layer, and removing the first photoresist layer;
removing the second photoresist layer after a second conductor layer is formed on the substrate, to form an electrical connection portion on the first conductor layer and the second insulation layer and form a drain electrode on the second semiconductor layer, wherein the electrical connection portion makes the first scan line and the second scan line connected to each other via the first conductor layer.

US Pat. No. 10,367,015

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising a semiconductor film over a substrate, comprising the steps of:forming a first conductor over the substrate;
forming a first insulator over the first conductor;
forming a first hard mask over the first insulator;
forming a first resist mask comprising a first opening, over the first hard mask;
etching the first hard mask using the first resist mask to form a second hard mask comprising a second opening;
etching the first insulator using the second hard mask to form a second insulator comprising a third opening;
forming a second conductor embedded in the second opening and the third opening;
performing polishing treatment on the second hard mask and the second conductor to form a third conductor embedded in the third opening;
forming a fourth conductor over the second insulator and the third conductor;
forming a second resist mask in a pattern over the fourth conductor;
etching the fourth conductor using the second resist mask and an etching gas to form a fifth conductor; and
removing the second resist mask,
wherein the second hard mask is etched with the etching gas.

US Pat. No. 10,367,014

DISPLAY DEVICE, MANUFACTURING METHOD OF DISPLAY DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a display device, comprising the steps of:over a first surface of a first substrate, forming a transistor, a capacitor, a pixel electrode and a first insulating layer;
over a first surface of a second substrate, forming a light-blocking layer, a coloring layer, an insulating layer, a spacer and a second insulating layer;
bonding the first substrate and the second substrate with an adhesive layer to seal the transistor, the capacitor and a display element;
forming a groove portion by performing a first cutting treatment on the second substrate;
forming a protective film in the vicinity of a peripheral portion of the groove portion, the first substrate and the second substrate, the protective film in contact with the first substrate, the first insulating layer, the adhesive layer, the second insulating layer and the second substrate; and
fabricating a plurality of display devices by performing a second cutting treatment on the first substrate.

US Pat. No. 10,367,013

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a substrate;
a first transistor over the substrate, the first transistor including:
a conductive film over the substrate;
a first insulating film over the conductive film;
a first oxide semiconductor film over the first insulating film, the first oxide semiconductor film overlapping with the conductive film;
a first gate insulating film on the first oxide semiconductor film;
a first gate electrode over the first insulating film;
a second insulating film on the first oxide semiconductor film and the first gate electrode; and
a first source electrode and a first drain electrode over and in direct contact with the first oxide semiconductor film through first openings provided in the second insulating film,
wherein the first oxide semiconductor film includes a first region being in directly contact with the first gate insulating film and second regions being in directly contact with the second insulating film, and
wherein each of the second regions of the first oxide semiconductor film has lower resistance than the first region of the first oxide semiconductor film; and
a second transistor over the substrate, the second transistor including:
a second oxide semiconductor film over the first insulating film;
a second gate insulating film on the second oxide semiconductor film;
a second gate electrode over the second gate insulating film;
the second insulating film on the second oxide semiconductor film and the second gate electrode; and
a second source electrode and a second drain electrode over and in direct contact with the second oxide semiconductor film through second openings provided in the second insulating film,
wherein the second oxide semiconductor film includes a first region being in directly contact with the second gate insulating film and second regions being in directly contact with the second insulating film, and wherein each of the second regions of the second oxide semiconductor film has lower resistance than the first region of the second oxide semiconductor film.

US Pat. No. 10,367,011

DISPLAY PANEL AND ARRAY SUBSTRATE THEREOF

Shenzhen China Star Optoe...

1. An array substrate, wherein the array substrate comprises a display region and a peripheral wiring region;wherein the display region comprises a plurality of sub-pixel electrodes arranged in a matrix manner, scanning lines arranged in correspondence with each row of the sub-pixel electrodes, and data lines arranged in correspondence with each column of the sub-pixel electrodes;
wherein in the peripheral wiring region, gate driving circuits are arranged in correspondence with each of the scanning lines and data driving lines are arranged in correspondence with each of the data lines, and the gate driving circuits and the data driving lines are electrically connected to a film region of a chip, each of wires in array connecting the gate driving circuits to the film region of the chip is arranged on different metal layers to improve the electrostatic protection of the array substrate;
wherein a distance between the adjacent wires is in the range of 10 to 30 ?m, a starting point of each of the wires in array connected to the gate driving circuit and an end point connected to the film region of the chip are arranged in the same metal layer.

US Pat. No. 10,367,009

ACTIVE-MATRIX SUBSTRATE

SHARP KABUSHIKI KAISHA, ...

1. An active-matrix substrate comprising:a substrate;
a plurality of first lines disposed on the substrate and extending in a first direction;
a plurality of second lines disposed on the substrate and extending in a second direction different from the first direction;
a transistor disposed correspondingly to each of intersection points of the first lines and the second lines, and connected to a corresponding one of the first lines and a corresponding one of the second lines;
an insulating layer;
an extended conductive film; and
a photoelectric conversion element disposed correspondingly to each of the intersection points of the first lines and the second lines and connected to the transistor;whereinat least one of the first lines and the second lines each have a layered structure with connection to the extended conductive film via a contact hole provided in the insulating layer,
the extended conductive film includes a first-line extended conductive film and a second-line extended conductive film,
the first lines are connected to the first-line extended conductive film,
the second lines are connected to the second-line extended conductive film,
the first-line extended conductive film includes a first-line first extended conductive film connected to the first lines, and a first-line second extended conductive film extending in parallel with the first-line first extended conductive film at a layer level different from the first-line first extended conductive film and connected to the first-line first extended conductive film via a contact hole,
when viewed in a direction perpendicular to the substrate, the first-line first extended conductive film and the first-line second extended conductive film extend in parallel to the first lines in the first direction and substantially overlap the first lines,
when viewed in the direction perpendicular to the substrate, the second-line extended conductive film extends in parallel to the second lines in the second direction and substantially overlap the second lines, and
none of the first-line first extended conductive film, the first-line second extended conductive film, the first lines, the second-line extended conductive film and the second lines overlaps the photoelectric conversion element.

US Pat. No. 10,367,006

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a pixel portion;
a protective circuit comprising a first transistor and a second transistor, each of the first transistor and the second transistor comprising:
a gate electrode;
a gate insulating layer over the gate electrode;
a first oxide semiconductor layer over the gate insulating layer;
a first electrode and a second electrode over the first oxide semiconductor layer; and
a second oxide semiconductor layer provided between the first oxide semiconductor layer and the first electrode;
a first wiring electrically connected to the first electrode of the first transistor, the gate electrode of the first transistor, and the first electrode of the second transistor; and
a second wiring electrically connected to the second electrode of the first transistor, the gate electrode of the second transistor, and the second electrode of the second transistor,
wherein the pixel portion is electrically connected to the protective circuit, and
wherein the first oxide semiconductor layer comprises indium, gallium, and zinc.

US Pat. No. 10,367,005

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first insulator over a first transistor, a channel formation region of the first transistor comprising part of a semiconductor substrate;
a second transistor over the first insulator, a channel formation region of the second transistor comprising an oxide semiconductor;
a second insulator over the second transistor, the second insulator comprising an opening reaching the second transistor;
a first conductor embedded in the opening of the second insulator;
a barrier layer over the first conductor;
a third insulator over the barrier layer and the second insulator; and
a second conductor over the third insulator,
wherein the barrier layer, the third insulator, and the second conductor overlap with each other and function as a capacitor, and
wherein each of the first insulator, the barrier layer, and the third insulator has a barrier property against oxygen and hydrogen.

US Pat. No. 10,367,000

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

12. A method for manufacturing a semiconductor device, comprising:forming a stacked body above a foundation layer, the stacked body including a plurality of first films and a plurality of second films, the first films and the second films including a first film and a second film stacked alternately;
forming a slit which divides the stacked body into a plurality of blocks;
forming a cover film on a bottom of the slit to a height so as to cover at least a lateral side of a lowermost second film on the foundation layer; and
removing the second film positioned above an upper end of the cover film of the second films by etching through the slit after forming the cover film, thereby forming an air gap in a portion from which the second film is removed.

US Pat. No. 10,366,998

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION

Tokyo Electron Limited, ...

1. A method of forming a semiconductor device, the method comprising:providing a substrate defining an initial connection area, the substrate having at least three nanowires positioned within the initial connection area, the nanowires being uncovered, the nanowires having a longitudinal axis that extends in a horizontal direction, the nanowires being positioned in a vertical stack and spaced apart from each other, the nanowires including a first nanowire, a second nanowire, and a third nanowire, the second nanowire being positioned above the first nanowire, and the third nanowire being positioned above the second nanowire;
forming a first electrode that surrounds the first nanowire such that the first nanowire is embedded within the first electrode, the first electrode extending vertically to a top of the initial connection area, the first electrode having a step-shaped cross-section;
forming a second electrode that surrounds the second nanowire such that the second nanowire is embedded within the second electrode, the second electrode extending vertically to the top of the initial connection area; and
forming a third electrode that surrounds the third nanowire such that the third nanowire is embedded within the third electrode, the third electrode extending vertically to the top of the initial connection area.

US Pat. No. 10,366,994

MEMORY DEVICES WHICH INCLUDE MEMORY ARRAYS

Micron Technology, Inc., ...

1. A memory device comprising a memory array, wherein the memory array comprises:a fin having a first source/drain region, a second source/drain region and a channel region between the first source/drain region and the second source/drain region; the first source/drain region extending to a first height; the second source/drain region extending to a second height less than the first height; the channel region extending along a trough between the first source/drain region and the second source/drain region;
a charge-storage device over the first source/drain region and electrically coupled with the first source/drain region;
a first sense/access line along a sidewall of the fin and spaced from the channel region by dielectric material; and
a second sense/access line over the second source/drain region and electrically coupled with the second source/drain region; an uppermost surface of the second sense/access line being beneath an uppermost surface of the first source/drain region.

US Pat. No. 10,366,993

SEMICONDUCTOR STRUCTURE HAVING AIR GAP BETWEEN GATE ELECTRODE AND DISTAL END PORTION OF ACTIVE AREA

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a semiconductor substrate having a major surface;
a trench isolation region in the semiconductor substrate;
an active area surrounded by the trench isolation region in the semiconductor substrate, wherein the active area has a longitudinal axis extending along a first direction;
a first gate electrode buried in the active area and adjacent to a distal end portion of the active area;
a second gate electrode buried in the trench isolation region and adjacent to the distal end portion of the active area; and
an air gap between the second gate electrode and the distal end portion of the active area, wherein the air gap overlaps with an entire thickness of the second gate electrode, wherein the first gate electrode is a memory gate electrode and the second gate electrode is a passing gate electrode, and wherein the air gap is adjacent to the second gate electrode and is not adjacent to the first gate electrode, and wherein the air gap overlaps with an entire thickness of the second gate electrode along a thickness direction that is perpendicular to a top surface of the semiconductor substrate, and wherein the air gap is discontinuous along an extending direction of the second gate electrode under a top view.

US Pat. No. 10,366,990

FIN FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A fin field effect transistor (FinFET), comprising:a gate stack;
a semiconductor fin embedded in the gate stack, the semiconductor fin extending along a widthwise direction of the gate stack, and the semiconductor fin comprising a first concave and a second concave exposed at sidewalls of the gate stack respectively; and
a source and a drain disposed at two opposite sides of the gate stack, wherein the source comprises a first portion laterally protruding into the first concave, the drain comprises a second portion laterally protruding into the second concave.

US Pat. No. 10,366,988

SELECTIVE CONTACT ETCH FOR UNMERGED EPITAXIAL SOURCE/DRAIN REGIONS

International Business Ma...

1. A semiconductor structure comprising:a plurality of semiconductor material fins located on a surface of a substrate;
at least one gate structure straddling over a portion of each semiconductor material fin of said plurality of semiconductor material fins;
unmerged source-side epitaxial semiconductor material portions located on an entirety of each sidewall surface and a topmost surface of each semiconductor material fin on one side of each gate structure;
unmerged drain-side epitaxial semiconductor portions located on an entirety of each sidewall surface and a topmost surface of each semiconductor material fin on another side of each gate structure;
an etch stop structure located between each unmerged source-side epitaxial semiconductor material portion and each unmerged drain-side epitaxial semiconductor material portion, wherein each etch stop structure comprises a bottom material portion and an upper material portion, said bottom material portion of said etch stop structure has a higher etch resistance in a specific etchant as compared to said upper material portion of said etch stop structure, wherein a topmost surface of said bottom material portion of said etch stop structure is coplanar with a topmost surface of said upper material portion of said etch stop structure, and a bottommost surface of said bottom material portion of said etch stop structure is coplanar with a bottommost surface of each semiconductor fin, and wherein an entirety of a bottom surface and sidewall surfaces of said upper material portion of said etch stop structure is in direct physical contact with said bottom material portion of said etch stop structure, and wherein each of said bottom material portions has a sidewall surface that is in direct physically contact with a sidewall surface of one of said unmerged source-side epitaxial semiconductor material portions or one of said unmerged drain-side epitaxial semiconductor material portions;
a recessed dielectric material portion present on said etch stop structure that is located between each unmerged source-side epitaxial semiconductor material portion and each unmerged drain-side epitaxial semiconductor material portion, said recessed dielectric material portion having a topmost surface that is located beneath a topmost surface of each of said unmerged source-side epitaxial semiconductor material portions and each of said unmerged drain-side epitaxial semiconductor material portions, and wherein said topmost surface of said recessed dielectric material portion is coplanar with said topmost surface of the upper material portion of the etch stop structure and the topmost surface of the lower material portion of the etch stop structure;
a source-side metal semiconductor alloy portion located on a surface of each of said unmerged source-side epitaxial semiconductor material portions and the topmost surface of said bottom material portion of said etch stop structure; and
a drain-side metal semiconductor alloy portion located on a surface of each of said unmerged drain-side epitaxial semiconductor material portions and the topmost surface of said bottom material portion of said etch stop structure.

US Pat. No. 10,366,984

DIODE CONNECTED VERTICAL TRANSISTOR

INTERNATIONAL BUSINESS MA...

1. A method of forming an electrical device comprising:forming an electrically conductive surface region on a semiconductor substrate;
forming a transistor device in a first region of the semiconductor substrate comprising a transistor vertically orientated channel, a first transistor source/drain region that is provided by the electrically conductive surface region at a first end of the transistor vertically orientated channel region, and a transistor gate structure that is separated from the first transistor source/drain region of the transistor by a dielectric spacer; and
forming a diode connected transistor device in a second region of the semiconductor substrate comprising a second vertically orientated channel, a first diode source/drain region provided by the electrically conductive surface region at a first end of the diode vertically orientated channel, and a diode gate structure in direct contact with the first diode source/drain region.

US Pat. No. 10,366,983

SEMICONDUCTOR DEVICES INCLUDING CONTROL LOGIC STRUCTURES, ELECTRONIC SYSTEMS, AND RELATED METHODS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a stack structure comprising decks, each deck of the stack structure comprising:
a memory element level comprising memory elements;
a control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region and the N-type channel region overlying the first subdeck structure; and
a base control logic structure in electric communication with the stack structure and comprising control logic devices, the control logic level of each individual deck of the stack structure comprising a word line driver in electrical communication with the memory elements of the memory element level of the individual deck of the stack structure.

US Pat. No. 10,366,982

STRUCTURE WITH EMBEDDED MEMORY DEVICE AND CONTACT ISOLATION SCHEME

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating an integrated circuit, comprising:forming a source and a drain on a fin active region of a semiconductor substrate;
depositing an interlayer dielectric (ILD) layer on the source and drain;
patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively;
forming a dielectric material layer in the first contact hole;
forming a dielectric feature in the first contact hole, wherein the dielectric feature has a bottom surface directly contacting the source and sidewalls directly contacting the dielectric material layer; and
forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively, wherein the forming of the dielectric material layer in the first contact hole includes
depositing the dielectric material layer in the first contact hole; and
performing an anisotropic etching process to remove a bottom portion of the dielectric material layer within the first contact hole such that the source is exposed.

US Pat. No. 10,366,980

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

SOCIONEXT INC., Kanagawa...

1. A semiconductor integrated circuit device, comprising:a semiconductor chip including an internal circuit, a plurality of electrode pads and a plurality of I/O cells, wherein:
the plurality of electrode pads are arranged in a first row, a second row and a third row, the first row being disposed closer to an outermost edge of the semiconductor chip than the second row, and the second row being disposed closer to the outermost edge of the semiconductor chip than the third row,
each of the plurality of electrode pads arranged at least in the first and second rows overlaps corresponding one of the plurality of I/O cells in a plan view,
the plurality of I/O cells are provided on a peripheral region of the semiconductor chip,
each of the plurality of I/O cells includes a protective circuit,
each of the plurality of I/O cells is connected to corresponding one of the plurality of electrode pads,
the protective circuit of each of the plurality of I/O cells includes:
a power source-side protective circuit provided between the corresponding one of the plurality of electrode pads and a power source wiring; and
a ground-side protective circuit provided between the corresponding one of the plurality of electrode pads and a ground wiring, and
the power source-side protective circuit is positioned closer to the outermost edge of the semiconductor chip than the ground-side protective circuit.

US Pat. No. 10,366,977

OVERHEAT PROTECTION CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND VEHICLE THEREWITH

Rohm Co., Ltd., Kyoto (J...

1. An overheat protection circuit, comprising:a NPN transistor;
a power terminal to which a supply voltage is applied;
a transmission path by which the supply voltage is transmitted from the power terminal to a collector of the NPN transistor without passing through a current source;
a voltage divider operable to divide a reference voltage in a voltage division ratio to generate a division voltage, the voltage divider including a switch operable to change the voltage division ratio; and
a comparator operable to compare an emitter voltage of the NPN transistor with the division voltage to switch an output voltage from a normal state to an overheated state, and vice versa, wherein
the switch is operable to be turned on/off in response to the switching of the output voltage between the normal state and the overheated state to change the division voltage.

US Pat. No. 10,366,973

LAYOUT MODIFICATION METHOD FOR EXPOSURE MANUFACTURING PROCESS

TAIWAN SEMICONDUCTOR MANU...

1. A layout modification method for fabricating an integrated circuit, comprising:calculating uniformity of critical dimensions of a first portion and a second portion in a patterned layer using a layout for an exposure manufacturing process to produce a semiconductor device in the integrated circuit, wherein the second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process, wherein the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process;
retrieving an adjusting parameter for modifying the layout;
determining a compensation amount based on the adjusting parameter and the uniformity of the critical dimensions; and
compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.

US Pat. No. 10,366,972

MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a precursor package including a module substrate, a first flip chip die attached to an upper surface of the module substrate, and a first mold compound over and surrounding the first flip chip die, wherein:
the first flip chip die comprises a first device layer, a plurality of first interconnects extending from a lower surface of the first device layer to the upper surface of the module substrate, a first dielectric layer over an upper surface of the first device layer, and a first silicon substrate over the first dielectric layer; and
the first device layer includes a first coupling component that is embedded in the first device layer;
thinning down the first mold compound to expose a backside of the first silicon substrate of the first flip chip die;
removing substantially the first silicon substrate to form a first opening within the first mold compound and provide a first thinned flip chip die with an upper surface, wherein:
the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first thinned flip chip die in both X-direction and Y-direction;
the X-direction and the Y-direction are parallel to the upper surface of the module substrate, and the X-direction and the Y-direction are orthogonal to each other; and
the upper surface of the first thinned flip chip die is exposed at a bottom of the first opening; and
placing a second die in the first opening to stack with the first thinned flip chip die, wherein:
the second die comprises a second coupling component embedded therein; and
the second coupling component is mirrored to the first coupling component.

US Pat. No. 10,366,970

3D SEMICONDUCTOR DEVICE AND STRUCTURE

MONOLITHIC 3D INC., San ...

1. A 3D semiconductor device, the device comprising:a first single crystal layer comprising a plurality of first transistors;
at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;
a plurality of second transistors atop said first single crystal layer;
a plurality of third transistors above said plurality of second transistors;
a top metal layer above said third transistors;
first circuits below said first single crystal layer;
second circuits above said top metal layer;
a first set of connections below said at least one metal layer,
wherein said first set of connections connects said first transistors to said first circuits;
a second set of connections above said top metal layer,
wherein said second set of connections connects said first transistors to said second circuits, and
wherein said first set of connections comprises a through silicon via (TSV); and
a first memory array; and
a second memory array,
wherein said first memory array comprises a first portion of said plurality of second transistors and said second memory array comprises a section portion said plurality of third transistors,
wherein each of said plurality of second transistors comprises a source, a channel and a drain,
wherein said source, said channel, and said drain comprise the same type dopant,
wherein at least one of said plurality of second transistors comprises a polysilicon channel, and
wherein said plurality of second transistors are self-aligned to said plurality of third transistors, having been processed following the same lithography step.

US Pat. No. 10,366,968

INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE

Intel IP Corporation, Sa...

1. A microelectronic device, comprising:a first semiconductor die having a first group of contacts at a first pitch relative to one another, and a second group of contacts at a second pitch relative to one another, the second pitch being less than the first pitch, wherein at least one of the first and second groups of contacts includes an array of contacts extending along both X and Y dimensions of the first semiconductor die;
a molded component extending over the first semiconductor die;
a redistribution layer having a first side coupled to the first semiconductor die, the redistribution layer having first redistribution layer contacts engaging contacts of the first group of contacts, wherein the redistribution layer includes a dielectric layer formed on both the first semiconductor die and the molded component, and further includes conductive structures supported by the dielectric layer;
a second semiconductor die on the opposite side of the redistribution layer from the first semiconductor die, the second semiconductor device having a third group of contacts at the second pitch, the contacts of the third group of contacts coupled directly to respective contacts of the second group of contacts by direct attachments of respective second and third contacts, of which contacts of at least one of the second and third groups of contacts are in the form of metallic pillars that extend through the redistribution layer to engage the contacts of the other group, and without making electrical connection with the redistribution layer;
and
wherein the second semiconductor die is secured on the opposite side of the redistribution layer from the first semiconductor die, and placed within a vertical dimension established by contact balls on that same opposite side of the redistribution layer from the first semiconductor die, and wherein the contact balls are configured for attaching the microelectronic device to an additional structure.

US Pat. No. 10,366,966

METHOD OF MANUFACTURING INTEGRATED FAN-OUT PACKAGE

Taiwan Semiconductor Manu...

1. A method of manufacturing an integrated fan-out (InFO) package, comprising:forming a package array;
sequentially forming a dielectric layer and a core material layer on a first carrier;
removing a portion of the core material layer to form a core layer having a plurality of cavities;
attaching the first carrier, the dielectric layer, and the core layer onto the package array such that the core layer is located between the dielectric layer and the package array;
removing the first carrier from the dielectric layer; and
forming a plurality of first conductive patches on the dielectric layer above the plurality of cavities.

US Pat. No. 10,366,965

CHIP BONDING APPARATUS, CHIP BONDING METHOD AND A CHIP PACKAGE STRUCTURE

Industrial Technology Res...

1. A chip bonding apparatus for bonding a chip and a redistribution structure with each other, the chip bonding apparatus comprising:a pick and place module, suitable for picking up and placing the chip; and
an alignment module, moveably connected to the pick and place module, and the alignment module comprising at least one alignment protrusion, wherein the at least one alignment protrusion extends towards at least one alignment socket included in the redistribution structure, and the at least one alignment socket is configured in a non-point symmetry manner.

US Pat. No. 10,366,960

FAN-OUT PACKAGE AND METHODS OF FORMING THEREOF

Taiwan Semiconductor Manu...

1. A structure comprising:a chip comprising a substrate and a contact pad on the substrate;
a molding compound laterally encapsulating the chip, none of the molding compound being vertically aligned with the chip;
a first dielectric layer overlying the molding compound and the chip;
a first metallization layer having a first portion and a second portion, the first portion of the first metallization layer overlying the first dielectric layer, the second portion of the first metallization layer extending through the first dielectric layer electrically coupled to the contact pad, wherein the second portion of the first metallization layer has a flat top;
a second dielectric layer overlying the first metallization layer and the first dielectric layer; and
a second metallization layer having a first portion and second portion, the first portion of the second metallization layer overlying the second dielectric layer, the second portion of the second metallization layer extending through the second dielectric layer electrically coupled to the first metallization layer, the second portion of the second metallization layer being vertically aligned with the second portion of the first metallization layer.

US Pat. No. 10,366,959

INTEGRATED FAN-OUT STRUCTURE AND METHOD OF FORMING

Taiwan Semiconductor Manu...

1. A device, comprising:a first die, the first die comprising a first substrate and a first dielectric layer overlying the first substrate, an edge of the first substrate being offset from an edge of the first dielectric layer;
a second die positioned next to the first die, the second die comprising a second substrate and a second dielectric layer overlying the second substrate, an edge of the second substrate being offset from an edge of the second dielectric layer;
a redistribution layer overlying the first die and the second die, the redistribution layer comprising a conductor that continuously extends, in a plan view, between a sidewall of the first die and a sidewall of the second die, wherein the conductor is routed across the sidewall of the first die at a first angle, wherein the first angle is measured in the plan view and with respect to a shortest line between the first die and the second die, and the first angle being greater than 0.

US Pat. No. 10,366,957

SEMICONDUCTOR DEVICE

DENSO CORPORATION, Kariy...

1. A semiconductor device comprising:a metal member;
a first semiconductor chip that is disposed on a surface of the metal member and has a first metal layer at a surface facing the metal member;
a second semiconductor chip that is formed of a material having larger Young's modulus than the first semiconductor chip and is disposed at a position different from the first semiconductor chip on the surface of the metal member, the second semiconductor chip having a second metal layer at a surface facing the metal member;
a first solder that is disposed between the metal member and the first metal layer of the first semiconductor chip and connects the metal member and the first metal layer; and
a second solder that is disposed between the metal member and the second metal layer of the second semiconductor chip and connects the metal member and the second metal layer, wherein
a thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder.

US Pat. No. 10,366,952

SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, comprising:forming a porous dielectric layer including a recessed portion;
forming a conductive layer in the recessed portion of the porous dielectric layer;
forming a conformal cap layer on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer; and
performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer and the gap in the conformal cap layer.

US Pat. No. 10,366,951

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

Intel Corporation, Santa...

1. A method of forming an interconnect element to connect between two dies, the method comprising:forming a first layer of a medium including one of glass, ceramic, or silicon;
forming first high density interconnect routing in the first layer;
forming a second layer of the medium in contact with the first layer;
forming second high density interconnect routing in the second layer, the second high density interconnect routing electrically connected to the first high density interconnect routing;
forming a third layer of the medium, the second layer situated between the first and third layers;
forming third high density interconnect routing in the third layer, wherein the interconnect element includes only three layers with high density interconnect routing;
forming first and second pads at a first surface of the medium in electrical contact with the third high density interconnect routing, the first and second pads at least partially exposed at a first surface of the medium; and
electrically connecting first and second dies to the first and second pads, respectively, and the first and second dies to low density interconnect routing of a substrate to which the first die is electrically coupled.

US Pat. No. 10,366,950

BOTTOM-UP SELECTIVE DIELECTRIC CROSS-LINKING TO PREVENT VIA LANDING SHORTS

Intel Corporation, Santa...

1. An interconnect structure comprising:a first interlayer dielectric (ILD);
a first interconnect line extending into the first ILD;
a second interconnect line extending into the first ILD;
a second ILD positioned over the first interconnect line and the second interconnect line;
a via extending through the second ILD and electrically coupled to the first interconnect line, wherein a portion of a bottom surface of the via is positioned over the second interconnect line; and
an isolation layer positioned between the bottom surface of the via and a top surface of the second interconnect line.

US Pat. No. 10,366,949

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE

Shinko Electric Industrie...

1. A wiring substrate comprising:a first wiring structure; and
a second wiring structure stacked on the first wiring structure,
wherein the first wiring structure includes:
a first wiring layer;
a first insulating layer covering the first wiring layer, wherein the first insulating layer includes a first through hole that extends through the first insulating layer in a thickness-wise direction to expose an upper surface of the first wiring layer; and
a via wiring including an upper end surface exposed from an upper surface of the first insulating layer, wherein the first through hole of the first insulating layer is filled with the via wiring,
the second wiring structure includes:
a protective film formed on the upper surface of the first insulating layer;
a second wiring layer including a first wiring pattern, wherein the first wiring pattern is formed on the upper surface of the first insulating layer and the upper end surface of the via wiring; and
a second insulating layer stacked on the upper surface of the first insulating layer and covering the second wiring layer,
the second wiring structure has a wiring density that is higher than a wiring density of the first wiring structure, and
the first wiring pattern of the second wiring layer comprises:
a first metal barrier film formed on the upper surface of the first insulating layer and the upper end surface of the via wiring;
a first metal film formed on the first metal barrier film; and
a first metal layer formed on the first metal film,
wherein the first metal layer includes an entirely roughened side surface and an entirely smooth side surface, and includes an upper surface comprising a partially roughened upper surface and a partially smooth upper surface,
the protective film is formed on the entirely smooth side surface of the first metal layer and the partially smooth upper surface of the first metal layer, and the partially roughened upper surface is partially attached to the second insulating layer,
each of the roughened side surface and the roughened upper surface of the first metal layer has a surface roughness that is smaller than a surface roughness of the first wiring layer, and
the first metal barrier film includes a peripheral portion that projects toward an outer side from the roughened side surface of the first metal layer.

US Pat. No. 10,366,948

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor chip;
a plurality of leads, disposed in a periphery of the semiconductor chip; and
a sealing resin, sealing the semiconductor chip and the leads such that lower surfaces and outer end surfaces of the leads, at sides opposite the semiconductor chip, are exposed;
wherein
lead plating layers arranged to improve solder wettability are formed on the lower surfaces and the outer end surfaces of the leads, and
front surfaces of the lower surfaces of the plurality of leads excluding the lead plating layers are at higher height positions than a lower surface of the sealing resin.

US Pat. No. 10,366,944

METHODS AND APPARATUS FOR SEMICONDUCTOR DEVICE HAVING BI-MATERIAL DIE ATTACH LAYER

TEXAS INSTRUMENTS INCORPO...

1. A device comprising:a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of a surface area of the second surface;
the adhesive layer including first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous; and
the first polymeric compound having a first modulus and the second polymeric compound having a second modulus greater than the first modulus.

US Pat. No. 10,366,943

PACKAGED ELECTRONIC DEVICE HAVING STEPPED CONDUCTIVE STRUCTURE AND RELATED METHODS

Amkor Technology, Inc., ...

1. An electronic package comprising:a substrate having a first conductive element, wherein:
the first conductive element comprises a first stepped portion disposed at a first end of the first conductive element; and
the first stepped portion comprises:
a first groove extending inward from a lower surface of the first conductive element; and
a second groove extending further inward from the first groove towards an upper surface of the first conductive element;
an electronic component coupled to the first conductive element; and
an encapsulant encapsulating the electronic component and a portion of the substrate such that the first stepped portion is exposed outside a first exterior side surface of the encapsulant,wherein:the first conductive element has a first width
the first groove has a second width; and
the second groove has a third width less than the second width.

US Pat. No. 10,366,942

SEMICONDUCTOR DEVICE WITH SEALED SEMICONDUCTOR CHIP

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a resin;
a semiconductor chip which is sealed with the resin and includes a plurality of first pads and a plurality of second pads;
a plurality of first external leads which are arranged outside of the resin;
a plurality of second external leads which are arranged outside of the resin;
a plurality of first internal leads, including a first set, a second set and a center lead, the first set and the second set being arranged on respective sides of the center lead, which are sealed with the resin and are connected with the plurality of first external leads respectively, each of the first set and the second set including a first section, a second section, and a third section, wherein
the plurality of first sections extend in a first direction in a first plane of the semiconductor chip, are arranged spaced apart in a second direction perpendicular to the first direction, and underlay the semiconductor chip,
the center lead includes a first portion and a second portion directly connected the first portion, at least the second portion extending in the first direction,
the plurality of second sections are connected with the plurality of first sections respectively, the plurality of second sections bend towards the second portion of the center lead, and
the plurality of third sections are connected with the plurality of second sections respectively;
a plurality of second internal leads which are sealed with the resin, are connected with the plurality of second external leads respectively, and include a plurality of fourth sections respectively, wherein the plurality of fourth sections bend towards the plurality of third sections;
a plurality of first bonding wires which are sealed with the resin, electrically connect the plurality of first pads and the plurality of third sections respectively; and
a plurality of second bonding wires which are sealed with the resin, electrically connect the plurality of second pads and the plurality of fourth sections respectively.

US Pat. No. 10,366,941

PACKAGE STRUCTURE

Winbond Electronics Corp....

1. A package structure, comprising:a substrate;
a metal pad located on the substrate;
a first polymer layer located on the substrate, the first polymer layer having a first opening, the first opening exposing a portion of a top surface of the metal pad;
a second polymer layer located on the first polymer layer, the second polymer layer having a second opening, the second opening exposing the portion of the top surface of the metal pad and a first top surface of the first polymer layer;
a redistribution layer (RDL), covering the portion of the top surface of the metal pad and extending onto a portion of the first top surface of the first polymer layer and the second polymer layer; and
a third polymer layer, located on the RDL, the third polymer layer having a third opening, the third opening exposing a portion of a top surface of the RDL, wherein the third opening corresponds to the metal pad, and the third opening is greater than the first opening and smaller than the second opening.

US Pat. No. 10,366,935

ARCHITECTURE OF DRIVE UNIT EMPLOYING GALLIUM NITRIDE SWITCHES

OTIS ELEVATOR COMPANY, F...

1. A drive unit for driving a motor, the drive unit comprising:a printed circuit board;
a first gallium nitride switch having a gate terminal, drain terminal and source terminal, the first gallium nitride switch mounted to the printed circuit board;
a second gallium nitride switch having a gate terminal, drain terminal and source terminal, the second gallium nitride switch mounted to the printed circuit board;
a gate driver generating a turn-off drive signal to turn off the first gallium nitride switch and turn off the second gallium nitride switch;
a first turn-off trace on the printed circuit board, the first turn-off trace directing the turn-off drive signal to the gate terminal of the first gallium nitride switch; and
a second turn-off trace on the printed circuit board, the second turn-off trace directing the turn-off drive signal to the gate terminal of the second gallium nitride switch;
wherein an impedance of the first turn-off trace is substantially equal to an impedance of the second turn-off trace;
a first turn-on trace on the printed circuit board, the first turn-on trace directing the turn-on drive signal to the gate terminal of the first gallium nitride switch;
a second turn-on trace on the printed circuit board, the second turn-on trace directing the turn-on drive signal to the gate terminal of the second gallium nitride switch;
wherein an impedance of the first turn-on trace is substantially equal to an impedance of the second turn-on trace;
wherein the gate driver generates a turn-on drive signal to turn on the first gallium nitride switch and turn on the second gallium nitride switch;
a via positioned in one of the first turn-off trace and the second turn-off trace, the via extending through the printed circuit board to render the impedance of the first turn-off trace substantially equal to the impedance of the second turn-off trace.

US Pat. No. 10,366,934

FACE DOWN DUAL SIDED CHIP SCALE MEMORY PACKAGE

Micron Technology, Inc., ...

1. A semiconductor device comprising:an interposer having a first side and a second side opposite of the first side;
a first die having a perimeter located on the first side of the interposer, wherein the first die comprises an active side opposite a back side, the active side of the first die facing the first side of the interposer;
a first window through the interposer, wherein at least a portion of the first window extends outside of the perimeter of the first die;
at least one bond wire electrically connecting the first die to the second side of the interposer through the first window;
a second die having a perimeter located on the second side of the interposer;
a second window through the interposer, wherein at least a portion of the second window extends outside of the perimeter of the second die; and
at least one bond wire electrically connecting the second die to the first side of the interposer through the second window.

US Pat. No. 10,366,933

CASE HAVING TERMINAL INSERTION PORTION FOR AN EXTERNAL CONNECTION TERMINAL

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a base plate;
an insulating substrate provided on an upper surface of said base plate;
a conductive pattern provided on an upper surface of said insulating substrate;
a semiconductor chip mounted on an upper surface of said conductive pattern;
a case surrounding said base plate, said insulating substrate, said conductive pattern, and said semiconductor chip, said case having a terminal insertion portion, which is L-shaped in a plan view, in a peripheral wall portion thereof;
a sealing resin sealing an interior of said case; and
a plate-like external connection terminal provided to said case, including:
a body portion formed as a plate;
a connection portion bent in a direction from one end of said body portion and connected to said conductive pattern,
a terminal portion bent in the direction from the other end of said body, such that the body portion and the terminal portion are L-shaped in plan view; and
an external connection portion configured to connect to an external control board, wherein
said terminal insertion portion enables insertion of said terminal portion of said external connection terminal to thereby enable said connection of said external connection terminal to said conductive pattern, and
with said terminal portion of said external connection terminal being inserted in said terminal insertion portion of said case, a portion of said external connection terminal other than said external connection portion is sealed by said sealing resin.

US Pat. No. 10,366,932

METHOD AND SYSTEM FOR WET CHEMICAL BATH PROCESS

TAIWAN SEMICONDUCTOR MANU...

1. A method for performing a wet chemical process over a semiconductor wafer, comprising:immersing the semiconductor wafer into a hot phosphoric acid;
detecting the concentration of Silica in the hot phosphoric acid at a plurality of preset time points;
determining a process end point time at which the concentration of the Silica is maintained at approximately a fixed value; and
removing the semiconductor wafer from the hot phosphoric acid at the process end point times.

US Pat. No. 10,366,931

NANOSHEET DEVICES WITH CMOS EPITAXY AND METHOD OF FORMING

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks each including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer;
growing a pair of epitaxial regions adjacent to each of the first and the second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions;
covering the first nanosheet stack with a mask; and
forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to one of the epitaxial regions on the second nanosheet stack.

US Pat. No. 10,366,926

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a fin structure;
a shallow trench isolation (STI) adjacent the fin structure;
a gate structure over a portion of the fin structure and the STI, wherein the gate structure comprises a gate dielectric layer, a work function layer over the gate dielectric layer, and a conductive fill material over the work function layer;
spacers along opposing sidewalls of the gate structure, the spacers terminating at ends of the gate structure along a longitudinal axis of the gate structure; and
a first dielectric layer surrounding the gate structure and the spacers in a plan view, the first dielectric layer having a first sidewall and a second sidewall intersecting the longitudinal axis of the gate structure, wherein the work function layer terminates over the STI between the fin structure and the first dielectric layer along the longitudinal axis of the gate structure, wherein the conductive fill directly contacts the first sidewall and the second sidewall of the first dielectric layer from an upper surface of the first dielectric layer to a bottom surface of the first dielectric layer.

US Pat. No. 10,366,924

CHIP CARRIERS AND SEMICONDUCTOR DEVICES INCLUDING REDISTRIBUTION STRUCTURES WITH IMPROVED THERMAL AND ELECTRICAL PERFORMANCE

Infineon Technologies AG,...

1. A chip carrier comprising a redistribution structure, the redistribution structure comprising:a dielectric layer extending in a horizontal direction;
a first electrically conductive layer arranged over the dielectric layer and extending in the horizontal direction, wherein horizontal dimensions of the first electrically conductive layer are greater than vertical dimensions of the first electrically conductive layer;
a trench arranged in the dielectric layer and extending in the horizontal direction, wherein horizontal dimensions of the trench are greater than vertical dimensions of the trench, and wherein the horizontal dimensions of the trench are different than the horizontal dimensions of the first electrically conductive layer;
a filling material filling the trench, wherein the filling material is different from the material of the dielectric layer; and
an electrically conductive via connection extending vertically through the dielectric layer, wherein the first electrically conductive layer is electrically coupled to the via connection.

US Pat. No. 10,366,921

INTEGRATED CIRCUIT STRUCTURE INCLUDING FUSE AND METHOD THEREOF

UNITED MICROELECTRONICS C...

1. An integrated circuit structure comprising a fuse, comprising:a fuse and a first metal interconnect disposed on a substrate and in a first dielectric layer, wherein the first dielectric layer is one single layer;
a patterned dummy disposed on the first dielectric layer, the patterned dummy having a first hole exposing a part of the first dielectric layer right above the fuse without contacting the fuse, wherein the first hole passes through the patterned dummy and only a top part of the first dielectric layer right above the part of the first dielectric layer;
a second metal interconnect disposed in the same level as the patterned dummy, and the second metal interconnect and the patterned dummy being composed of same material, wherein the second metal interconnect connects the fuse by contact plugs through the first dielectric layer, and the contact plugs comprise different materials from the second metal interconnect and the fuse, wherein each of the contact plugs includes a barrier layer containing titanium or titanium nitride and a metal layer while the fuse and the second metal interconnect are composed of a single metal, and the second metal interconnect and the fuse are spaced apart, wherein the second metal interconnect is directly on the contact plugs, and the contact plugs are directly on the fuse, and a surface interface is disposed between the second metal interconnect and the contact plugs, and an another surface interface is disposed between the contact plugs and the fuse;
a passivation layer directly and fully covering the patterned dummy, an exposed sidewall of the top part of the first dielectric layer in the first hole, a top surface of the part of the first dielectric layer in the first hole, a top surface of the second dielectric layer, and an exposed sidewall of the second dielectric layer in the first hole; and
an isolation structure overlapping the fuse disposed underneath thereof and being separated by a dielectric layer therebetween.

US Pat. No. 10,366,918

SELF-ALIGNED TRENCH METAL-ALLOYING FOR III-V NFETS

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming source/drain regions on opposite sides of a gate structure and within a compound semiconductor channel layer, wherein the compound semiconductor channel layer is composed of a III-V compound semiconductor material and is located directly on a compound semiconductor substrate layer and wherein the source/drain regions are n-doped;
forming source/drain contact openings extending through an interlevel dielectric (ILD) layer that overlies the source/drain regions and laterally surrounds the gate structure, each of the source/drain contact openings exposing a portion of one of the source/drain regions;
removing native oxides from the top surface of the exposed portion of each of the source/drain regions to provide a treated source/drain surface;
performing plasma doping to introduce a free radical of an n-type dopant to the treated source/drain surface of each source/drain region, wherein the free-radical of the n-type dopant is selected from the group consisting of Sn radical, Te radicals and Si radicals;
forming, by selective epitaxy, a semiconductor cap only within the source/drain contact openings and extending upwards from the plasma doped and treated source/drain surface of each of the source/drain regions, wherein the removing of the native oxides and the selective epitaxy are performed in a same reactor chamber and wherein the semiconductor cap passivates the plasma doped and treated source/drain surface;
forming a metal layer over exposed surfaces of the ILD layer, the gate structure and each semiconductor cap;
forming metal semiconductor alloy regions within the source/drain contact openings by reacting an entirety of each semiconductor cap with the metal layer, wherein each of the metal semiconductor alloy regions is located at a bottom of one of the source/drain contact openings and in direct contact with a top surface of the exposed portion of one of the source/drain regions; and
forming source/drain contacts within the source/drain contact openings, each of the source/drain contacts contacting a top surface of one of the metal semiconductor alloy regions, wherein the source/drain contacts have a contact resistance that is lower than 5×10?9 ohm-cm2, and wherein the source/drain regions comprise planar source/drain regions located within the compound semiconductor channel layer and raised source/drain regions, the raised source/drain regions having a same type of doping as the planar source/drain regions, and wherein each of the raised source/drain regions comprises a same III-V compound semiconductor material as the planar source/drain regions.

US Pat. No. 10,366,914

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) forming an isolation portion on a semiconductor layer side of an SOI substrate including a support substrate, a buried insulating film formed on the support substrate and a semiconductor layer formed on the buried insulating film, thereby forming an active region partitioned by the isolation portion in the SOI substrate;
(b) selectively forming a first epitaxial layer on an outer end portion of the semiconductor layer in the active region by performing a first selective epitaxial growth process on the SOI substrate; and
(c) after the step (b), selectively forming a second epitaxial layer over the semiconductor layer in the active region and the first epitaxial layer by performing a second selective epitaxial growth process on the SOI substrate,
wherein the active region includes:
a first active region having a width whose length in a first direction is greater than or equal to a first length, and
a second active region having a width whose length in the first direction is less than the first length,
wherein the first selective epitaxial growth process is performed on the first active region, and
wherein the second selective epitaxial growth process is performed on the first active region and the second active region.

US Pat. No. 10,366,912

STAGE APPARATUS AND CHARGED PARTICLE BEAM APPARATUS

Hitachi High-Technologies...

1. A stage apparatus comprising:a first table that supports a sample and moves the sample in a first direction;
a second table that moves the first table in a second direction different from the first direction; and
a first moving mechanism that generates a driving force for moving the first table in the first direction;
a second moving mechanism that generates a driving force for moving the second table in the second direction;
a movable body that supports a stator included in the first moving mechanism; and
a third moving mechanism that moves the movable body so as to follow the movement of the second table in the second movement direction.

US Pat. No. 10,366,911

CARRIER SUBSTRATE FOR CARRYING AN OLED IN MANUFACTURING PROCESS AND MANUFACTURING METHOD FOR THE SAME

Wuhan China Star Optoelec...

1. A carrier substrate for carrying an OLED in manufacturing process, comprising:a substrate; and
an attracted layer disposed on a surface of the substrate, wherein the attracted layer includes a resin layer and multiple magnetic nanoparticles distributed in the resin layer;
wherein a distribution density of the magnetic nanoparticles is gradually increased from an edge location to a center location of the resin layer.

US Pat. No. 10,366,909

THERMAL CHAMBER EXHAUST STRUCTURE AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. An exhaust structure comprising:an intake section comprising a first high thermal conductivity material, the intake section including an inlet;
an output section comprising a second high thermal conductivity material, the output section including an outlet; and
a piping section comprising a third high thermal conductivity material, the piping section comprising a first inner diameter from the intake section to the output section, thereby being configured to communicatively couple the intake section with the output section,
wherein
the exhaust structure is configured to provide a high thermal conductivity path from the inlet to the outlet, the high thermal conductivity path comprising the first high thermal conductivity material, the second high thermal conductivity material, and the third high thermal conductivity material,
the piping section and one of the intake section or the output section are separate components of the exhaust structure mechanically coupled to each other at a section interface, and
the one of the intake section or the output section has a second inner diameter at the section interface, the second diameter having a same value as a value of the first inner diameter.

US Pat. No. 10,366,905

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor chip including a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface;
a conductive substrate onto which the semiconductor chip is die-bonded;
a conductive spacer that has a planar area smaller than that of the first electrode and supports the semiconductor chip on the conductive substrate;
a resin package that seals at least the semiconductor chip and the conductive spacer; and
a bonding material that is provided between the conductive spacer and the first electrode of the semiconductor chip, and has a projecting portion projecting from the conductive spacer and fitting inside the first electrode.

US Pat. No. 10,366,904

ARTICLES HAVING HOLES WITH MORPHOLOGY ATTRIBUTES AND METHODS FOR FABRICATING THE SAME

Corning Incorporated, Co...

1. An article comprising:a glass-based substrate comprising a first surface, a second surface, and at least one hole extending from the first surface, wherein:
the at least one hole comprises an interior wall having a surface roughness Ra that is less than or equal to 1 ?m;
the at least one hole comprises a first opening having a first diameter that is present at the first surface;
a first plane is defined by the first surface of the glass-based substrate based on an average thickness of the glass-based substrate; and
a ratio of a depression depth to the first diameter of the at least one hole is less than or equal to 0.007, wherein the depression depth is measured from the first plane to the first surface at the first opening of the at least one hole;
the at least one hole is a through-hole such that a second opening of the at least one hole having a second diameter is present on the second surface;
a difference between the first diameter and the second diameter is less than or equal to 2 ?m;
a circularity of the at least one hole is less than or equal to 5 ?m;
each of the first diameter and the second diameter is in a range from 5 ?m to 250 ?m; and
an aspect ratio of the average thickness of the glass-based substrate to at least one of the first diameter and the second diameter is in a range from 1:1 to 15:1.

US Pat. No. 10,366,903

TEXTILE PATTERNING FOR SUBTRACTIVELY-PATTERNED SELF-ALIGNED INTERCONNECTS, PLUGS, AND VIAS

Intel Corporation, Santa...

1. An interconnect structure comprising:an interlayer dielectric (ILD) material;
a first interconnect line formed adjacent to the ILD material;
one or more vias formed over a top surface of the first interconnect line, wherein a sidewall of the via is aligned with a sidewall of the first interconnect line, and wherein portions of the top surface of the first interconnect line that are not covered by a via are covered by a dielectric fill material;
one or more dielectric lines formed over a top surface of the ILD material, wherein the one or more dielectric lines extend in a direction orthogonal to a direction the first interconnect line extends; and
a second interconnect line coupled to the first interconnect line by one of the one or more vias, the second interconnect line extending in a direction orthogonal to the first interconnect line, and wherein the one or more dielectric lines have a thickness that is less than a thickness of the second interconnect line.

US Pat. No. 10,366,902

METHODS FOR CYCLIC ETCHING OF A PATTERNED LAYER

Tokyo Electron Limited, ...

1. A method for treating a substrate, comprising:receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer;
exposing the substrate to a passivation/activation plasma to concurrently form a passivation layer on the mask layer and an activation layer on the portions of the intermediate layer;
transitioning the passivation/activation plasma to a desorption plasma to concurrently remove the passivation layer and the activation layer; and
alternating between the passivation/activation plasma and the desorption plasma,
wherein the passivation layer and the activation layer are of different compositions.

US Pat. No. 10,366,901

INTEGRATED STRUCTURES, CAPACITORS AND METHODS OF FORMING CAPACITORS

Micron Technology, Inc., ...

1. A capacitor comprising:a stack of alternating first and second levels supported by a base; the first levels comprising only insulative material, and the second levels comprising insulative pillars extending through conductive material;
a plurality of slots extending through the stack; each of the slots comprised by the plurality of slots having a first end and an opposing second end with a central region between the first and second ends; the plurality of slots being arranged in multiple rows with the second ends of within a first row being spaced from the first ends of slots in a second row by a lateral distance; and
the insulative pillars within the second levels being within the lateral distance between rows of slots, the insulative pillars being of a different composition than the insulative material of the first levels.

US Pat. No. 10,366,900

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming a first dielectric layer over an underlying structure disposed on a substrate, and the underlying structure includes plural structures;
forming a planarization resistance layer over the first dielectric layer;
patterning the planarization resistance layer to form a patterned planarization resistance layer;
forming a second dielectric layer over the first dielectric layer and the patterned planarization resistance layer so that a bottom of a concave of the second dielectric layer is positioned on the patterned planarization resistance layer; and
performing a planarization operation on the second dielectric layer, the patterned planarization resistance layer and the first dielectric layer to remove the first dielectric layer and the second dielectric layer on top surfaces of the plural structures and to remove the patterned planarization resistance layer,
wherein the patterned planarization resistance layer is made of a material different from the first dielectric layer and having a lower etching rate in the planarization operation than the first and second dielectric layers to reduce a dishing amount between the plural structures, wherein the planarization resistance layer includes one or more of SiN, SiON, SiCN, SiC, AlO and AlON, and wherein a difference in height, between the top surfaces of the plural structures after removing the first and second dielectric layers and a lowest portion of an upper surface of the first dielectric layer between the plural structures after removing the planarization resistance layer, is between 1 nano meter and 10 nano meters.

US Pat. No. 10,366,897

DEVICES WITH MULTIPLE THRESHOLD VOLTAGES FORMED ON A SINGLE WAFER USING STRAIN IN THE HIGH-K LAYER

International Business Ma...

1. A method for adjusting a threshold voltage, comprising:controlling an amount of strain in a silicon nitride liner deposited over a transistor to diffuse work function (WF) modulating species from the silicon nitride liner into a gate dielectric in a channel region of the transistor, the amount of strain in the liner being controlled by adjusting deposited liner thickness.

US Pat. No. 10,366,895

METHODS FOR FORMING A SEMICONDUCTOR DEVICE USING TILTED REACTIVE ION BEAM

Infineon Technologies AG,...

1. A method for forming a semiconductor device, the method comprising:forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate;
forming of a first insulating layer inside the trench;
irradiating the first insulating layer with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the first insulating layer is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the first insulating layer is masked by an edge of the trench; and
forming a second insulating layer inside the trench after the irradiation of the first insulating layer to form a combined insulating layer with vertically varying thickness.

US Pat. No. 10,366,894

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING DEVICE, AND RECORDING MEDIUM

KOKUSAI ELECTRIC CORPORAT...

1. A method for manufacturing a semiconductor device, comprising:forming a metal carbide film including a first metal element and a second metal element on a substrate, by time-divisionally performing:
forming a first film containing the first metal element and carbon and not containing the second metal element by time-divisionally performing supplying a first precursor gas containing the first metal element and not containing carbon to the substrate to form a first metal-containing layer and supplying a reaction gas containing carbon and not containing a metal element to the first metal-containing layer; and
forming a second film containing the second metal element and carbon and not containing the first metal element on the first film by time-divisionally performing supplying a second precursor gas containing the second metal element differing from the first metal element and not containing carbon to the first film to form a second metal-containing layer on the first film and supplying the reaction gas to the second metal-containing layer,
wherein the first precursor gas and the second precursor gas are halides.

US Pat. No. 10,366,893

PROCESS FOR MAKING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a silicon carbide semiconductor device, comprising:forming a gate insulating film on a silicon carbide substrate;
forming a polysilicon film on an entire surface of the gate insulating film;
ion implanting one or more dopants selected from a group consisting of N, P, As, Sb, B, Al, and Ar into the polysilicon film that is on the entire surface of the gate insulating film;
before conducting any thermal process on the polysilicon film that has been ion implanted, removing a thickness of 50 nm to 300 nm uniformly from a surface layer of the polysilicon film that has been ion implanted;
selectively forming a mask on the polysilicon film from which the thickness of 50 nm to 300 nm has been removed uniformly;
forming a polysilicon electrode by removing an exposed portion of the polysilicon film that is exposed by the mask via isotropic dry etching;
removing the mask; and
forming an interlayer insulating film on the polysilicon electrode.

US Pat. No. 10,366,888

PATTERN FORMING METHOD

Tokyo Electron Limited, ...

1. A pattern forming method comprising steps of:forming a first organic film by coating an etching target film with a composition including a polymer including a cross-linkable component;
infiltrating an inorganic substance into the first organic film;
cross-linking the polymer;
forming a second organic film on the first organic film after the steps of infiltrating and cross-linking;
forming a second organic film pattern by patterning the second organic film;
forming a first organic film pattern having a pitch reduced to one-half of a pitch of the second organic film pattern by patterning the first organic film by a self-aligned patterning method that uses the second organic film pattern as a core pattern; and
forming an etching target film pattern having a pitch reduced to one-half of a pitch of the first organic film pattern by patterning the etching target film by a self-aligned patterning method that uses the first organic film pattern as a core pattern.

US Pat. No. 10,366,887

METHOD OF USING CHEMICALLY PATTERNED GUIDE LAYERS IN CHEMOEPITAXY DIRECTING OF BLOCK CO-POLYMERS

Brewer Science, Inc., Ro...

1. A method of forming a microelectronic structure, said method comprising: providing a stack comprising:a substrate having a surface; and
one or more optional intermediate layers on said substrate surface;
forming a patternable layer having first and second surfaces, said first surface being on said intermediate layers, if present, or on said substrate surface, if no intermediate layers are present, and said second surface being remote from said first surface, said patternable layer having an initial surface property at said second surface;
exposing said patternable layer to radiation so as to selectively alter said initial surface property to yield an altered surface property at the areas of exposure, forming a patterned layer;
without altering said patterned layer, applying a self-assembling composition to the second surface of said patterned layer, said composition comprising a block copolymer comprising a first block and a second block; and
causing said composition to self-assemble into a self-assembled layer in response to the initial surface property, the altered surface property, or both, wherein said self-assembled layer comprises a first self-assembled region and a second self-assembled region different from said first self-assembled region, wherein:
said initial surface property is a lack of affinity towards one of said first and second blocks over the other of said first and second blocks; and
during said exposing, an affinity to one of said first and second blocks over the other of said first and second blocks develops, said affinity being the altered surface property.

US Pat. No. 10,366,885

LASER IRRADIATION METHOD AND LASER IRRADIATION DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method of manufacturing a semiconductor device comprising:forming a semiconductor film comprising amorphous silicon over a substrate;
irradiating desired regions of the semiconductor film with a plurality of laser beams to crystallize the desired regions of the semiconductor film; and
patterning the crystallized semiconductor film to form a plurality of semiconductor layers, each being comprised in a respective one of a plurality of thin film transistors,
wherein the plurality of laser beams are slantingly incident on an irradiation surface of the semiconductor film.

US Pat. No. 10,366,881

POROUS FIN AS COMPLIANT MEDIUM TO FORM DISLOCATION-FREE HETEROEPITAXIAL FILMS

International Business Ma...

1. A semiconductor device, comprising:a porous fin formed on a monocrystalline substrate;
a hydrogenated surface formed on the porous fin; and
an epitaxial monocrystalline layer formed on the hydrogenated surface, the epitaxial monocrystalline layer including a material other than a material of the monocrystalline substrate and forming a relaxed heteroepitaxial interface with the monocrystalline substrate wherein a thickness of the porous fin and a thickness of the epitaxial monocrystalline layer include a thickness ratio configured to relax strain in the epitaxial monocrystalline layer.

US Pat. No. 10,366,877

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS

Tokyo Electron Limited, ...

1. A substrate processing method comprising:supplying a first cleaning liquid containing water to a first surface of a substrate while the substrate is being rotated, thereby cleaning the first surface of the substrate;
supplying a second cleaning liquid containing water to a second surface of the substrate that is opposite to the first surface of the substrate while the substrate is being rotated and the first cleaning liquid is being supplied to the first surface of the substrate, thereby cleaning the second surface of the substrate;
supplying a rinsing liquid to the first surface of the substrate and the second surface of the substrate while the substrate is being rotated, thereby rinsing the first cleaning liquid and rinsing the second cleaning liquid;
stopping the supplying of the rinsing liquid to the second surface of the substrate at a predetermined time, continuing the rinsing of the first surface of the substrate after stopping the rinsing of the second surface of the substrate and thereafter supplying an organic solvent to the first surface of the substrate to substitute the rinsing liquid on the first surface such that the first surface of the substrate is not exposed to outside air while the substrate is continuously rotated, thereby removing the rinsing liquid remaining on the first surface of the substrate by the organic solvent and removing the rinsing liquid remaining on the second surface of the substrate by a centrifugal force;
supplying a water-repellent agent to the first surface of the substrate while the substrate is being rotated; and
after the supplying the water-repellent agent to the first surface of the substrate, increasing a rotation speed of the substrate thereby drying the substrate.

US Pat. No. 10,366,876

PHOSPHOR-CONTAINING FILM AND BACKLIGHT UNIT

FUJIFILM Corporation, To...

1. A phosphor-containing film, comprising:a first substrate film; and
a phosphor-containing layer at which a plurality of regions containing phosphors are discretely disposed in a resin layer having an impermeability to oxygen, the phosphor having a property that deteriorates upon exposure to oxygen by reacting with the oxygen, and the phosphor-containing layer being disposed on the first substrate film,
wherein the plurality of regions containing phosphors comprise a plurality of first fluorescent regions containing phosphors and a plurality of second fluorescent regions dispersed at different positions in a film thickness direction from positions of the plurality of first fluorescent regions, both the first fluorescent regions and the second fluorescent regions being disposed in the same resin layer having an impermeability to oxygen.

US Pat. No. 10,366,863

DETECTOR SUPPLEMENT DEVICE FOR SPECTROSCOPY SETUP

1. A detector supplement device for integration in a spectroscopy setup, wherein the spectroscopy setup comprises a vacuum chamber, a light source, a sample irradiating a reflected photon beam and a charged particle beam in the same direction of propagation into a radiation detector, whereinthe detector supplement device comprises a Rogowski coil placeable inside the vacuum chamber between the sample and radiation detector, wherein the charged particle beam is guided through the hollow core of the Rogowski coil allowing synchronized measurements of electrical currents due to the charged particle beam correlated to the reflected photon beam, while irradiation of the reflected photon beam and the charged particle beam takes place in the same direction of propagation.

US Pat. No. 10,366,859

ELECTROMAGNETIC INTERFERENCE CONTAINMENT FOR ACCELERATOR SYSTEMS

Varian Medical Systems, I...

1. An apparatus for attachment to a component of a microwave device, comprising:a cage;
a shield within the cage, wherein the shield is in a form of a container, and at least a majority of the shield is spaced away from an interior wall of the cage; and
a connector at the cage, wherein the connector is configured to connect to a cable connection, and wherein the connector is electrically connected to two terminals within the shield;
wherein a voltage between the two terminals has a first voltage value, and a voltage between the shield and the cage has a second voltage value that is higher than the first voltage.

US Pat. No. 10,366,858

ION BEAM DEVICE

Hitachi High-Technologies...

1. An ion beam apparatus comprising: a vacuum chamber; a gas field ion source that is installed in the vacuum chamber and has an emitter tip; an extraction electrode that is disposed to face the emitter tip; gas supply means for supplying a gas to the emitter tip; a focusing lens that focuses an ion beam emitted from the emitter tip; a deflector that deflects the ion beam that has passed through the focusing lens; and a secondary particle detector that irradiates a sample with the ion beam to detect secondary particles emitted from the sample,wherein the gas supply means includes a mixed gas chamber containing two or more types of gases including at least a hydrogen gas and a pipe that connects the vacuum chamber to the mixed gas chamber, and concentration of the hydrogen gas in the mixed gas chamber is equal to or lower than about 4% volume ratio of the hydrogen gas to a total volume of gas in the mixed gas chamber.

US Pat. No. 10,366,856

NANOSCALE FIELD-EMISSION DEVICE AND METHOD OF FABRICATION

CALIFORNIA INSTITUTE OF T...

1. An apparatus including a first field-emission device, the first field-emission device comprising:a substrate;
a first electrode disposed on the substrate, the first electrode having a tip whose radius of curvature is at least 20 nm, wherein the first electrode comprises a first material having a first work function; and
a second electrode disposed on the substrate, the second electrode having a tip whose radius of curvature is at least 20 nm, wherein the second electrode comprises a second material having a second work function that is different than the first work function; and wherein the first electrode and second electrode define a first gap having a first environment that is characterized by an ionization potential;
wherein the first gap has a first separation that enables field emission of electrons from one of the first electrode and second electrode with an electron energy that is less than the ionization potential.

US Pat. No. 10,366,854

CONTACTOR WITH COIL POLARITY REVERSING CONTROL CIRCUIT

TE CONNECTIVITY CORPORATI...

1. A contactor, comprising:a plurality of switches;
a first input circuit for receiving a power-up input signal;
a second input circuit for receiving a trip input signal;
a movable actuator mechanically coupled to switches in the plurality of switches, the actuator moveable between a tripped position and an operational position upon receipt of a power-up input signal on the first input circuit, and moveable between the operational position and the tripped position upon receipt of a trip input signal on the second input circuit;
a coil having first and second ends, the moveable actuator extending through the coil as a core, the coil capable of moving the actuator when either a power-up input signal is received by the first input circuit or a trip input signal is received by the second input circuit;
first and second switches coupled to respective first and second ends of the coil for reversing the polarity of the coil each occurrence of the actuator being actuated,
the first and second switches being switchable to include the coil in the second input circuit when the actuator is in the operational position, wherein when the trip input signal is received on the second input circuit the coil is energized to operate the actuator to transition to the tripped position, and
the first and second switches being switchable to include the coil in the first input circuit when the actuator is in the tripped position, wherein when the power-up input signal is received on the first input circuit the coil is energized to operate the actuator to transition to the operational position;
wherein as the actuator is being actuated the first and second switches change state in preparation to energize the coil to be magnetically polarized in an opposite polarization direction during a next subsequent actuation.

US Pat. No. 10,366,852

POWER RELAY FOR A VEHICLE

1. A power relay for a vehicle, comprising:a housing having a connector base and a housing can mounted on said connector base, said housing can being an injection molded component made of plastic;
two terminal studs for contacting a load circuit and inserted into said connector base;
a coil subassembly disposed in said housing and containing a solenoid coil, an armature, a force-transmission member and a contact bridge, said armature is coupled by said force-transmission member to said contact bridge and can be moved in said housing, under an action of a magnetic field generated by said solenoid coil, such that said contact bridge can be moved reversibly between a closed position, in which said contact bridge bridges said terminal studs in an electrically conducting manner, and an open position, in which said contact bridge is not in contact with said terminal studs; and
said coil subassembly further having a magnet yoke, which has a torsionally stable structure, which is accommodated nonrotatably in said housing can over an entire axial height of said housing can.

US Pat. No. 10,366,848

METHOD FOR PRODUCING ELECTRIC SWITCHGEAR AND ELECTRIC SWITCHGEAR WITH ENHANCED SEAL-TIGHTNESS

SCHNEIDER ELECTRIC INDUST...

1. A method for producing low- or medium-voltage electrical switchgear comprising an electrical component, at least one electrical connector connected electrically to the electrical component and an enclosure delimiting a volume in which the electrical component is received, in which the electrical connector comprises a body which passes through the enclosure,the method comprising a step of fitting a seal in a peripheral groove formed in a wall of the body and
a step of injecting a plastic material around the body of the electrical connector and around the seal,
wherein the injection step consists of injecting the plastic material at a pressure causing an elastic crushing of the seal in the peripheral groove, and
a dimension of at least part of the peripheral groove, measured along a main axis of the electrical connector, is less than a greatest axial dimension of the seal.

US Pat. No. 10,366,847

DEVICE FOR GUIDING A SPRING IN A CONTROL MECHANISM AND ELECTRICAL PROTECTION APPARATUS COMPRISING SAME

SCHNEIDER ELECTRIC INDUST...

1. A device for guiding a spring belonging to a control mechanism having first and second axes of which at least one axis of the first and second axes is linked mechanically to an operating shaft, said device comprising:a compression spring having first and second ends;
a first slideable element including:
a guiding portion for guiding movement of the compression spring during compression and including first and second holes passing lengthwise through the guiding portion, and
a first base including (a) a notch configured to link the first base in an articulated manner to the first axis, and (b) a first bearing surface configured to abut the first end of the compression spring, wherein the first and second holes passing through the guiding portion continue through the first base;
a second slideable element including:
a second base including (a) a notch configured to link the second base in an articulated manner to the second axis, and (b) a second bearing surface configured to abut the second end of the compression spring, and
first and second parallel rods, each rod of the first and second parallel rods having (a) a fixed end being fixed onto said second base, and (b) a free end being mounted to slide through a respective one of the first and second holes and extend out of the first base.

US Pat. No. 10,366,845

MONITORED ADAPTABLE EMERGENCY OFF-SWITCH

1. An emergency off-switch for triggering an emergency switch-off function for safety-related shutdown of an electrical device, comprising:an actuator and at least two electrical contact points which can be connected to one another via a contact bridge, wherein a position of the contact bridge is influenced by the actuator such that the electrical contact points can selectively be opened or closed,
an active operating state, in which the emergency switch-off function can be triggered by moving the contact bridge, and a passive operating state, in which the emergency off-switch is non-functional,
a visualization unit having at least a first and a second display state, wherein the emergency off-switch is visually highlighted in the first display state, and the emergency off-switch is neutrally displayed in the second display state, the visualization unit being designed to adopt the first display state in the active operating state and to adopt the second display state in the passive operating state, and
a monitoring unit which monitors whether the visualization unit is in the first or in the second display state,
wherein, in the first display state, the visualization unit has a defined nominal current and the monitoring unit triggers the emergency switch-off function, when an actual current into the visualization unit is less than the defined nominal current.

US Pat. No. 10,366,843

CARBON FIBER AND PARYLENE STRUCTURAL CAPACITOR

1. A method of manufacturing a structural capacitor comprising:(a) forming a first layer made of a nonconductive structural material into a desired shape of a structural component of an object;
(b) placing a conductive layer including carbon fiber on the first layer;
(c) placing parylene directly on the conductive layer to form a dielectric layer; and
(d) repeating steps (b) and (c) until a desired property is achieved.

US Pat. No. 10,366,838

LAMINATED CERAMIC ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING SAME

MURATA MANUFACTURING CO.,...

1. A method for producing a laminated ceramic electronic component, the method comprising:preparing a laminate having a plurality of dielectric layers and a plurality of internal electrode layers respectively laminated, and having a first main surface and a second main surface opposed to each other in a lamination direction, a first side surface and a second side surface opposed to each other in a width direction orthogonal to the lamination direction, and a first end surface and a second end surface opposed to each other in a length direction orthogonal to the lamination direction and the width direction;
preparing an electroconductive paste containing Cu particles coated with an oxide of Al or Zr; and
applying the electroconductive paste onto the first end surface and the second end surface of the laminate.

US Pat. No. 10,366,832

CAPACITOR AND ELECTRONIC DEVICE HAVING A PLURALITY OF SURFACE ELECTRODES ELECTRICALLY CONNECTED TO EACH OTHER BY AN INTERMEDIATE ELECTRODE

MURATA MANUFACTURING CO.,...

1. A capacitor comprising:a substrate having a first main surface;
a first inner electrode and a second inner electrode disposed above a side of the first main surface, the second inner electrode being arranged so as to face the first inner electrode;
a dielectric layer between the first inner electrode and the second inner electrode;
a first intermediate electrode connected to the first inner electrode at a plurality of first locations;
a plurality of first surface electrodes which are each electrically connected to the first intermediate electrode; and
a second surface electrode electrically connected to the second inner electrode at a plurality of second locations,
wherein a first layer of the capacitor containing the first inner electrode and a second layer of the capacitor containing the first intermediate electrode have different electrode patterns.

US Pat. No. 10,366,831

MULTILAYER CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer capacitor having:a laminate comprising a stack of multiple dielectric layers made of dielectric material and having a first principal face and a second principal face on an opposite side of the first principal face; and
multiple internal electrode layers whose primary component is Ni and which are arranged in parallel with the first principal face and second principal face inside the laminate in such a way that they alternate from opposing sides with the dielectric layers placed in between; wherein,
of the internal electrode layers, at least the internal electrode layer closest to the first principal face and internal electrode layer closest to the second principal face contain in its entirety at least one metal element selected from the group consisting of Pt, Ru, Rh, Re, Ir, Os, and Pd;
of the multiple internal electrode layers, the internal electrode layer closest to the first principal face has a distance of 30 ?m or less from the first principal face; and
of the multiple internal electrode layers, the internal electrode layer closest to the second principal face has a distance of 30 ?m or less from the second principal face,
wherein internal electrode layers away from the first and second principal faces, among the multiple internal electrode layers, contain none of any metal element selected from the group consisting of Pt, Ru, Rh, Re, Ir, Os, and Pd.

US Pat. No. 10,366,830

SURFACE MOUNT ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A surface mount electronic component comprising:an element including a dielectric layer including a first main surface and a second main surface;
a first external electrode disposed on the first main surface;
a second external electrode disposed on the second main surface;
a first metal terminal connected to the first external electrode;
a second metal terminal connected to the second external electrode; and
an exterior material covering at least a portion of the element, the first and second external electrodes, and the first and second metal terminals; wherein
upper and lower surfaces of the exterior material are flat or substantially flat;
the first metal terminal includes:
a first bonding portion connected to the first external electrode;
a first extending portion connected to the first bonding portion and extending in a direction parallel or substantially parallel to the first main surface with a space from the first main surface;
a second extending portion connected to the first extending portion and extending towards the element;
a third extending portion connected to the second extending portion and extending in the direction parallel or substantially parallel to the first main surface;
a fourth extending portion connected to the third extending portion and extending in a mounting direction; and
a first mounting portion connected to the fourth extending portion and mounted on a mounting substrate;
the second metal terminal includes:
a second bonding portion connected to the second external electrode;
a fifth extending portion connected to the second bonding portion and extending in a direction parallel or substantially parallel to the second main surface with a space from the second main surface;
a sixth extending portion connected to the fifth extending portion and extending towards the element;
a seventh extending portion connected to the sixth extending portion and extending in the direction parallel or substantially parallel to the second main surface;
an eighth extending portion connected to the seventh extending portion and extending in the mounting direction; and
a second mounting portion connected to the eighth extending portion and mounted on the mounting substrate;
in the first bonding portion, a distal end of the first bonding portion is disposed in a direction away from the first main surface from an intermediate portion of the first bonding portion towards the distal end, and the first bonding portion is in surface contact with the first external electrode at the intermediate portion located on an opposite side of the distal end;
a first cut-out portion is provided in a portion in which the second extending portion of the first metal terminal and the third extending portion of the first metal terminal intersect with each other;
the second bonding portion includes a bifurcated distal end and is in surface contact with the second external electrode at the bifurcated portion;
a second cut-out portion is provided in the fifth extending portion of the second metal terminal;
a third cut-out portion is provided in a portion in which the sixth extending portion of the second metal terminal and the seventh extending portion of the second metal terminal intersect with each other; and
the first, second and third cut-out portions are covered with the exterior material.

US Pat. No. 10,366,827

IGNITION COIL FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. An ignition coil for an internal combustion engine comprising:a coil main body portion having a primary coil and a secondary coil magnetically coupled to each other;
a cylindrical connecting portion for connecting the coil main body portion and a spark plug; and
a conducting member disposed inside the connecting portion and electrically connecting the coil main body portion and the spark plug; wherein
a convex surface forming portion, which is a portion constituting an inner peripheral convex surface, an inner peripheral surface of which projects toward an inner peripheral side, is disposed in the connecting portion;
the convex surface forming portion has an outer peripheral concave surface, an outer peripheral surface of which is recessed toward the inner peripheral side;
the connecting portion has a boundary portion which is a boundary between the convex surface forming portion and other portions in an axial direction;
in the convex surface forming portion, at least a part of a region where the outer peripheral concave surface is formed has a portion having an area, in a cross-section orthogonal to the axial direction, equal to or smaller than an area of a cross-section orthogonal to the axial direction in the boundary portion, and a thickness of the convex surface forming portion is equal to or thicker than a thickness of the boundary portion; and
a thickness of the convex surface forming portion is equal to or thicker than a thickness of the boundary portion.

US Pat. No. 10,366,820

THIN FILM INDUCTOR

TDK CORPORATION, Tokyo (...

1. A thin film inductor comprising:a coil part formed of at least one coil conductor layer and having terminal electrodes provided at both ends thereof;
a first insulating layer configured to cover the coil part; and
a second insulating layer configured to cover the first insulating layer and having a higher Young's modulus than the first insulating layer, the second insulating layer enclosing an entire outer surface of the first insulating layer, other than in a region of the first insulating layer covered by the terminal electrodes.

US Pat. No. 10,366,812

CONNECTION STRUCTURE OF SUPERCONDUCTING WIRES

Furukawa Electric Co., Lt...

1. A connection structure of superconducting wires comprising:a plurality of superconducting wires are overlapped and connected with each other, each of the plurality of superconducting wires including a substrate and a superconducting layer that are laminated, a non-superconductor being provided at a part of a surface of the superconducting layer of at least one of the superconducting wires and protruding from the surface,
wherein a part of the non-superconductor is embedded in the surface of the superconducting layer,
the superconducting layer has a multilayer structure including an uppermost superconducting layer and at least one superconducting layer other than the uppermost superconducting layer, the uppermost superconducting layer having a thickness greater than a thickness of the at least one superconducting layer other than the uppermost superconducting layer, and
the part of the non-superconductor is embedded in the uppermost superconducting layer and a remaining part of the non-superconductor is protruded from the surface of the superconducting layer.

US Pat. No. 10,366,811

PARALLEL PAIR CABLE

SUMITOMO ELECTRIC INDUSTR...

1. A parallel pair cable, comprising:a pair of insulated wires arranged to be in contact with each other, parallel to each other, and not twisted;
a first resin tape wrapped around the pair of insulated wires;
a shield tape comprising a metal layer longitudinally folded on the outside of the first resin tape;
a drain wire outside the shield tape, wherein the drain wire is arranged to be in electrical contact with the metal layer of the shield tape;
a jacket layer provided around the shield tape and the drain wire; and
a conductive tape helically wrapped on the outside of the shield tape,
wherein the drain wire is arranged on the outside of the conductive tape so that the drain wire is electrically connected to the conductive tape and the shield tape; and
wherein the jacket layer is provided around the conductive tape and the drain wire.

US Pat. No. 10,366,810

EDGE INSULATION STRUCTURE FOR ELECTRICAL CABLE

3M Innovative Properties ...

1. An electrical cable comprising:a plurality of substantially parallel conductors extending along a length, and arranged along a width, of the cable, each conductor substantially surrounded by a shield;
first and second layers disposed on opposite sides of the conductors, each layer folded along the length of the cable toward the other layer, the folds defining first portions of the first and second layers facing each other and comprising a longitudinal edge of the cable, and second portions of the first and second layers facing away from each other; and
a bonding material bonding the first portions of the first and second layers to each other along the length of the cable.

US Pat. No. 10,366,809

INSULATED WIRE, COIL, AND ELECTRIC OR ELECTRONIC EQUIPMENT

FURUKAWA ELECTRIC CO., LT...

1. An insulated wire comprising a thermosetting resin layer on the outer periphery of a conductor, and a thermoplastic resin layer on the outer periphery of the thermosetting resin layer,wherein a total thickness of the thermosetting resin layer and the thermoplastic resin layer is 100 ?m or more and 250 ?m or less, and a degree of orientation of a thermoplastic resin in the thermoplastic resin layer, that is calculated by the following Formula 1, is 20% or more and 90% or less;
Formula 1 Degree of orientation H (%)=[(360??Wn)/360]×100
Wn: A half width of orientation peak in the azimuth angle intensity distribution curve by X-ray diffraction
n: the number of orientation peak at a ? angle of 0° or more and 360° or less.

US Pat. No. 10,366,808

HIGH-VOLTAGE APPARATUS AND METHOD FOR PRODUCING SAME

Siemens Aktiengesellschaf...

1. A high-voltage device, comprising:an internal conductor;
an insulating body surrounding said internal conductor along a longitudinal direction, said insulating body including:
insulating layers configured from a synthetic material that is impregnated with a resin; and
electrically conductive control inserts for providing field control, said electrically conductive control inserts being disposed in a concentric manner around said internal conductor and being spaced apart from one another by means of said insulating layers, at least one of said control inserts is a conductive base layer; and
a contact-making device, at least one of said control inserts is a contact insert that is connected in an electric manner to said internal conductor by means of said contact-making device, said contact-making device having a contact element configured from an electrically conductive material that is connected in an electrical manner to said contact insert, said contact element being fixed by means of an adhesive to said conductive base layer being in electrical contact with said internal conductor.

US Pat. No. 10,366,807

RESIN COMPOSITION FOR AUTOMOTIVE CABLE MATERIAL AND CABLE USING THE SAME

Hyundai Motor Company, S...

1. A resin composition comprising:a mixture of a base resin and a magnesium hydroxide flame retardant;
an antioxidant; and
a lubricant,
wherein the resin composition comprises an amount of about 2 to 5 parts by weight of the antioxidant and an amount of about 0.5 to 2 parts by weight of the lubricant with respect to 100 parts by weight of the mixture,
wherein the mixture comprises an amount of about 40 to 60% by weight of the base resin and an amount of about 60 to 40% by weight of the magnesium hydroxide flame retardant, based on the total weight of the mixture,
wherein a surface of the magnesium hydroxide flame retardant is treated with silane or aliphatic or polymeric fatty acid,
wherein the base resin comprises 100 parts by weight of a high crystalline polypropylene resin, an amount of about 5 to 10 parts by weight of a modified polypropylene and an amount of about 15 to 20 parts by weight of an elastomer,
wherein the high crystalline polypropylene resin comprises an amount of about 60 to 90% by weight of a high crystalline homo polypropylene resin and an amount of about 10 to 40% by weight of a high crystalline block polypropylene resin, based on the total weight of the high crystalline polypropylene resin, and
wherein the base resin further comprises maleic acid in an amount of about 0.1 to 3 parts by weight with respect to 100 parts by weight of the base resin; and an initiator.

US Pat. No. 10,366,801

ELECTRIC CURRENT TRANSMISSION CABLE AND METHOD OF FABRICATING SUCH A CABLE

1. An electric current transmission cable comprising:a non-anodized bare conductor based on aluminum or an aluminum alloy, having a hydrophilic external specific surface configured to be in contact with the atmospheric environment, and an inside volume intended to conduct an electric current,
wherein the external specific surface of the bare conductor has a first roughness parameter, defined as the arithmetic mean deviation, measurable by profilometry, of peaks and valleys in comparison to a predetermined average profile over a reference length or surface, equal to or greater than 1.9 ?m, and
the inside volume of the bare conductor has oxygen doping of its aluminum-based or aluminum alloy-based components at a ratio equal to or greater than 20%, to a depth of at least 300 nm with respect to the external specific surface.

US Pat. No. 10,366,800

METHODS OF PROVIDING ELECTRICALLY-CONDUCTIVE SILVER

EASTMAN KODAK COMPANY, R...

18. A method for providing two or more electrically-conductive silver metal patterns, the method comprising:providing a continuous substrate having a first supporting side and a second opposing supporting side,
providing two or more photosensitive thin film patterns on two or more respective portions on the first supporting side of the continuous substrate from a solution of a photosensitive reducible silver ion-containing composition, comprising:
a) one or more non-hydroxylic-solvent soluble silver complexes, each comprising a reducible silver ion complexed with one or more ?-oxy carboxylates via one or more oxygen atoms and the same reducible silver ion is complexed with an oxime compound via a nitrogen atom,
each of the one or more non-hydroxylic-solvent soluble silver complexes being represented by the following formula (I):
(Ag+)a(L)b(P)c  (I)
wherein L represents the ?-oxy carboxylate; P represents the oxime compound; a is 1 or 2; b is 1 or 2; and c is 1, 2, 3, or 4, provided that when a is 1, b is 1, and when a is 2, b is 2,
solubilized in a b) solvent medium of one or more non-hydroxylic organic solvents; and
c) a photosensitizer that can either reduce the reducible silver ion or oxidize the ?-oxy carboxylate having a reduction potential;
photochemically converting reducible silver ions in each of the two or more photosensitive thin film patterns on the first supporting side of the continuous substrate to provide correspondingly two or more electrically-conductive silver metal-containing patterns on the first supporting side of the continuous substrate;
contacting each of the two or more electrically-conductive silver metal-containing patterns with water or an aqueous or non-aqueous salt solution;
optionally, contacting each of the two or more electrically-conductive silver metal-containing patterns with an aqueous or non-aqueous non-salt solution; and
optionally, drying each of the two or more electrically-conductive silver metal-containing patterns.

US Pat. No. 10,366,791

METHOD AND SYSTEM FOR GLOBAL EPIDEMIC DISEASE OUTBREAK PREDICTION

EMC IP Holding Company LL...

1. A method comprising:receiving a request from a given user to predict disease outbreak information for a given location and a given time;
obtaining, from a plurality of data sources, a first set of disease outbreak patterns for the given location and the given time;
assigning weights to one or more reported diseases in the first set of disease outbreak patterns for the given location, the weights being based at least in part on an authenticity of one or more of the plurality of data sources from which data regarding the one or more reported diseases is obtained;
obtaining a second set of disease outbreak patterns for the given location at one or more historic time periods;
assigning weights to one or more reported diseases in the second set of disease outbreak patterns based at least in part on determining whether data in the second set of disease outbreak patterns correlates with data in the first set of disease outbreak patterns;
obtaining a set of personalized trends for the given user;
assigning weights to the set of personalized trends based at least in part on determining whether user profile attributes in the set of personalized trends correlate with the first set of disease outbreak patterns and the second set of disease outbreak patterns; and
generating at least one personalized alert for the given user based on the assigned weights for the first set of disease outbreak patterns, the second set of disease outbreak patterns, and the set of personalized trends; and
delivering the at least one personalized alert to a computing device associated with the given user over at least one network;
wherein the method is performed by at least one processing device comprising a processor coupled to a memory.

US Pat. No. 10,366,787

PHYSIOLOGICAL ALARM THRESHOLD DETERMINATION

MASIMO CORPORATION, Irvi...

1. A method of reducing nuisance alarms for a physiological parameter by determining an alarm threshold optimized for a specific care unit, the care unit including a plurality of patients being monitored for the physiological parameter, the method comprising:in the care unit, electronically measuring patient specific physiological parameters for the plurality of patients using a plurality of patient monitors;
electronically providing the patient specific physiological parameters to a threshold recommendation system;
receiving at least one recommended parameter specific alarm threshold value, said value responsive to a number of alarms triggered by said patient specific physiological parameters at said at least one recommended parameter specific alarm threshold value;
said at least one recommended parameter specific alarm threshold value calculated to reduce said number of alarms at said care center for said parameter by determining how many alarms are generated for each of a range of threshold values and choosing a threshold value from the range of threshold values that reduces a number of alarms; and
programming at least one of said plurality of patient monitors with a threshold value incorporating information gained by said suggested threshold value.

US Pat. No. 10,366,773

E-FUSE CIRCUIT

SK hynix Inc., Icheon-si...

1. An electrical fuse (E-fuse) circuit comprising:a boot-up controller configured to generate at least one fuse address and a sensing enable signal based on a boot-up signal;
an electrical fuse (E-fuse) array configured to include a plurality of fuse sets, and output fuse data having defect fusing information of the plurality of fuse sets when a word line corresponding to the fuse address is activated;
a fail controller configured to detect failed data from the fuse data, and activate a failed signal when the failed data is detected wherein the failed data is defect of an E-fuse included in the plurality of fuse sets; and
a failed address storage circuit configured to store a failed address corresponding to a fuse-set in which a defect is detected from among the fuse addresses when the failed signal is activated,
wherein the defect fusing information indicates that a failed part has occurred in the E-fuse of the fuse set resulting in the occurrence of the failed data,
wherein the fail controller includes:
a fail processor configured to activate a masking control signal when the failed data is detected from the fuse data; and
a failed signal generator configured to generate the failed signal based on the masking control signal during activation of a test signal.

US Pat. No. 10,366,771

CONTROLLER, MEMORY SYSTEM, AND BLOCK MANAGEMENT METHOD FOR NAND FLASH MEMORY USING THE SAME

Toshiba Memory Corporatio...

1. A memory system comprising:a nonvolatile memory including a plurality of physical blocks; and
a controller circuit electrically connected to the nonvolatile memory, and configured to manage a plurality of logical blocks each of which includes a respective set of physical blocks among the plurality of physical blocks, and execute an erase operation in units of logical blocks, wherein
the controller circuit is configured to:
monitor at least one of an erasing time length and a programming time length of each of physical blocks included in a first logical block among the plurality of logical blocks;
disassemble the first logical block among the plurality of logical blocks, the disassembling including de-allocating the physical blocks included in the first logical block to join a pool of de-allocated physical blocks, the pool of de-allocated physical blocks being a subset of the plurality of physical blocks, when both of a first physical block and a second physical block exist in the first logical block, the first physical block having an erasing time length or a programming time length falling within a first range specified by a first threshold value, and the second physical block having an erasing time length or a programming time length falling outside the first range;
select, from the pool of de-allocated physical blocks, physical blocks having erasing time lengths or programming time lengths belonging to a same time length range;
assemble a new logical block with the selected physical blocks; and
execute, on the basis of an erasing time length or a programming time length corresponding to each of the plurality of logical blocks, wear leveling to level erasing time lengths or programming time lengths of the plurality of logical blocks.

US Pat. No. 10,366,768

MEMORY DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. An operating method of a memory device, comprising:increasing a voltage applied to channels of non-selected strings during a program operation according to an increase of at least one of a target voltage, a verify voltage, and a program time of the program operation; and
programming selected memory cells based on the increased voltage.

US Pat. No. 10,366,767

MEMORY DEVICES CONFIGURED TO PERFORM LEAK CHECKS

Micron Technology, Inc., ...

1. A memory device, comprising:an array of memory cells; and
circuitry for control and/or access of the array of memory cells, the circuitry configured to perform a method comprising:
bringing a selected access line of a program operation to a first voltage;
applying a particular voltage to an unselected access line of the program operation;
while applying the particular voltage to the unselected access line and after bringing the selected access line to the first voltage, sensing a current of the selected access line while applying a reference current to the selected access line;
indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current; and
proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.

US Pat. No. 10,366,762

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a cell string including a plurality of memory cells coupled in series between a common source line and a bit line;
a common source line controller configured to provide a channel current to the cell string through the common source line in a read operation; and
a page buffer configured to sense data stored in a selected memory cell among the plurality of memory cells based on a current of the bit line when the channel current is provided,
wherein the common source line controller precharges the bit line with the channel current supplied to the cell string through the common source line,
wherein, after the bit line is precharged, the page buffer senses the data stored in the selected memory cell based on a voltage of the bit line transmitted to a sensing node.

US Pat. No. 10,366,759

MEMORY DEVICES HAVING SELECTIVELY ELECTRICALLY CONNECTED DATA LINES

Micron Technology, Inc., ...

11. A memory device, comprising:a first string of memory cells selectively connected to a first data line;
a second string of memory cells selectively connected to a second data line;
a first transistor connected in series with the first data line; and
a second transistor connected in series with the second data line and the first transistor;
wherein the first string is connected between a third transistor that selectively connects the first string to a first source and a fourth transistor that selectively connects the first string to the first data line, and wherein the second string is connected between a fifth transistor that selectively connects the second string to a second source and a sixth transistor that selectively connects the second string to the second data line.

US Pat. No. 10,366,756

CONTROL CIRCUIT USED FOR TERNARY CONTENT-ADDRESSABLE MEMORY WITH TWO LOGIC UNITS

UNITED MICROELECTRONICS C...

1. A control circuit for a ternary content-addressable memory comprising:a first logic unit comprising:
a first terminal coupled to a data access terminal of a first storage unit and configured to access a first storage voltage;
a second terminal coupled to a data access terminal of a second storage unit and configured to access a second storage voltage;
a third terminal coupled to a first search line;
a fourth terminal coupled to a second search line;
a fifth terminal coupled to a reference voltage terminal; and
a sixth terminal coupled to a match line; and
a second logic unit comprising:
a first terminal coupled to the data access terminal of the first storage unit;
a second terminal coupled to the data access terminal of the second storage unit;
a third terminal coupled to the first search line;
a fourth terminal coupled to the second search line;
a fifth terminal coupled to a first power supply line; and
a sixth terminal coupled to a second power supply line;
wherein when a first search voltage of the first search line and a second search voltage of the second search line match the first storage voltage and the second storage voltage, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.

US Pat. No. 10,366,755

SEMICONDUCTOR DEVICE INCLUDING TCAM CELL ARRAYS CAPABLE OF SKIPPING TCAM-CELL SEARCH IN RESPONSE TO CONTROL SIGNAL

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a plurality of sub-arrays, each of the sub-arrays including:
a plurality of TCAM (Ternary Content Addressable Memory) cells arranged in rows and columns;
a plurality of search line pairs respectively connected to ones of the TCAM cells arranged in the columns;
a plurality of match lines respectively connected to ones of the TCAM cells arranged in the rows;
a search line driver unit driving the search line pairs in response to a search line enable signal;
a plurality of match amplifier units, each connected to a corresponding one of the match lines and configured to output a search result according to a potential of the corresponding one of the match lines;
a register; and
a control logic unit generating the search line enable signal based on a search command and register data in the register,
wherein the register data indicates whether or not data stored in all the TCAM cells have a don't care value.

US Pat. No. 10,366,754

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH REDUCED POWER CONSUMPTION

RENESAS ELECTRONICS CORPO...

1. A semiconductor integrated circuit including a content addressable memory device, comprising:a memory cell array including:
a first memory cell containing a first part of entry data and a second memory cell containing a second part of the entry data;
a first match line and a second match line coupled to the first memory cell and the second memory cell, respectively; and
a first search line carrying a first part of search data and a second search line carrying a second part of the search data, the first search line and the second search line being coupled to the first memory cell and the second memory cell, respectively;
an equalizer circuit disposed between the first match line and the second match line;
a first precharge circuit being coupled to the first match line, and precharging the first match line to a first potential; and
a second precharge circuit being coupled to the second match line, and precharging the second match line to a second potential different from the first potential,
wherein the first memory cell includes a first comparator circuit comparing the first part of the search data supplied through the first search line and the first part of the entry data,
wherein the second memory cell includes a second comparator circuit comparing the second part of the search data supplied through the second search line and the second part of the entry data,
wherein the equalizer circuit couples, in accordance with a control signal, the first match line and the second match line after the first match line and the second match line are precharged, and
wherein the first search line and the second search line are each supplied with a search signal based on a valid data at the same time as the first match line and the second match line are coupled by the equalizer circuit.

US Pat. No. 10,366,752

PROGRAMMING FOR ELECTRONIC MEMORIES

1. Memory circuitry comprising:a memory cell having a first terminal and a second terminal, the circuitry further comprising a feedback path between said first terminal and said second terminal,
wherein said feedback path is configured to compensate for a slowdown in a resistance transition caused by non-linearity within said memory cell, and thereby brings about a linear state transition within said memory cell between respective memory states, and
wherein said feedback path comprises an operational amplifier and is configured to connect said memory cell in a negative feedback configuration.

US Pat. No. 10,366,751

RESISTANCE MEMORY CELL

Hefei Reliance Memory Lim...

1. A resistance memory cell, comprising:an inert electrode;
an active electrode; and
an electrolyte layer between the active electrode and the inert electrode, and adjacent the active electrode; and
a two-terminal access device adjacent one of the inert electrode and the active electrode, but not between the electrolyte layer and the active electrode;
wherein:
application of a set pulse having a set polarity to the resistance memory cell sets the resistance memory cell to a low-resistance state that is retained after application of the set pulse, and application of a reset pulse having a reset polarity to the resistance memory cell resets the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, the set polarity being opposite to the reset polarity;
application of a read pulse of the reset polarity determines the resistance state of the resistance memory cell;
the two-terminal access device is configured to enable a bi-directional flow of current through the resistance memory cell in response to application of a voltage greater than a threshold voltage;
application of the read pulse of the reset polarity produces a read current having a larger read current ratio between the low-resistance state and the high-resistance state than application of a read pulse of the set polarity; and
the read pulse of the reset polarity is smaller in magnitude than the reset pulse.

US Pat. No. 10,366,750

NONVOLATILE MEMORY DEVICE

Winbond Electronics Corp....

1. A semiconductor memory device, comprising:a memory array, configured to storing data by a reversible and nonvolatile variable resistance element;
an erasure unit, wherein when erasing a selected block of the memory array in response to an external erasure command, the erasure unit configured to set a first flag data indicating whether the selected block is in an erasure state without changing the data in the selected block;
a reading unit, wherein when reading a selected word of the memory array in response to an external reading command, the reading unit configured to output data of the selected word or data indicating the erasing based on the first flag data,
wherein the erasure unit configured to set the first flag data, when the first flag data indicates the erasure state, the data indicating the erasing is output by the reading unit without relation of data stored in the selected word; and
a programming unit, configured to receive an external programming command and programming input data to the selected word of the memory array, the programming unit setting the first flag data to be in a non-erasure state,
wherein the programming unit configured to compare the data stored in the selected word with the input data, programs the input data or reverse conversion data of the input data to the selected word according to a comparing result, and sets a second flag data for determining data for programming,
wherein the programming unit configured to reverse inconsistent data in the selected word according to the comparing result,
a ratio of inconsistency is the relationship between the input data and the data stored in the selected word;
if the ratio of inconsistency between the input data and the data stored in the selected word is 50% or more than 50%, the input data is programmed to the selected word, but only the data of the selected word corresponding to “1” indicating Inconsistency in an EXOR calculation is reversed;
if the ratio of inconsistency is less than 50%, the reverse conversion data is programmed to the selected word, but only the data of the selected word corresponding to “0” indicating consistency in the EXOR calculation is reversed, and the second flag data indicates the input data or the reverse conversion data is already programmed.

US Pat. No. 10,366,749

MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory system comprising:a memory device including a memory cell with a variable resistance value, and a first controller; and
a second controller configured to instruct the memory device to write data having a first value or a second value that is different from the first value,
wherein:
the first controller is configured to compare first read data read from the memory cell when a first voltage is applied to the memory cell with second read data read from the memory cell when a second voltage is applied to the memory cell,
the first voltage is different from the second voltage,
the first read data has the first value or the second value, and
the second read data has the first value or the second value.

US Pat. No. 10,366,748

RESISTANCE VARIABLE MEMORY SENSING USING PROGRAMMING SIGNALS

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of resistance variable memory cells; and
circuitry, coupled to the array of resistance variable memory cells, including a comparator to detect a change in resistance of a memory cell, wherein the memory cell is selected by applying a select signal to a word line coupled to the memory cell, by comparing a signal on a bit line coupled to the memory cell when a programming signal is applied to the memory cell to a signal associated with a reference signal applied to the circuitry while the programming signal is applied to the memory cell, wherein a voltage of the reference signal increases as a current of the programming signal increases and wherein the circuitry indicates that a data state of the memory cell is a data state that is different from the data state associated with the programming signal when the signal associated with the memory cell input into the comparator is from a capacitor.

US Pat. No. 10,366,747

COMPARING INPUT DATA TO STORED DATA

Micron Technology, Inc., ...

1. A method, comprising:comparing first input data to first stored data stored in a first memory cell by applying a first voltage differential across the first memory cell during a first time period;
comparing second input data to second stored data stored in a second memory cell by applying a second voltage differential across the second memory cell during a second time period, wherein the first and second voltage differentials have opposite polarities; and
determining whether the first input data matches the first stored data based on whether the first memory cell snaps back in response to applying the first voltage differential across the first memory cell.

US Pat. No. 10,366,742

MEMORY DEVICE PARALLELIZER

Micron Technology, Inc., ...

1. A memory device, comprising:a plurality of memory banks configured to store data;
an input buffer configured to receive input data and output serial data;
a serial shift register configured to shift in the serial data and to output the serial data in a parallel format as parallel data;
a parallel register that receives the parallel data from the serial shift register and buffered data directly from the input buffer, wherein the parallel register is configured to pass the parallel data and the buffered data to a data write bus to be stored in the plurality of memory banks; and
serial-to-parallel conversion circuitry that controls loading of the parallel register from the serial shift register and the input buffer, wherein the serial-to-parallel conversion circuitry utilizes a first loading signal to load the buffered data into the parallel register and a second loading signal to load the parallel data into the parallel register.

US Pat. No. 10,366,740

APPARATUSES HAVING MEMORY STRINGS COMPARED TO ONE ANOTHER THROUGH A SENSE AMPLIFIER

Micron Technology, Inc., ...

1. An apparatus comprising:a first bitline extending horizontally;
a second bitline being offset vertically from the first bitline and extending horizontally in parallel to the first bitline;
a common plate extending horizontally between the first and second bitlines;
a plurality of first memory cell structures disposed horizontally between the first bitline and the common plate, each of the plurality of first memory cell structures including a first access device and a first capacitor coupled in series between the first bitline and the common plate;
a plurality of second memory cell structures disposed horizontally between the second bitline and the common plate, each of the plurality of second memory cell structures including a second access device and a second capacitor coupled in series between the second bitline and the common plate;
a first sense amplifier coupled to the first bitline;
a second sense amplifier coupled to the second bitline;
a third bitline extending horizontally;
a plurality of third memory cell structures each coupled to the third bitline;
a fourth bitline extending horizontally; and
a plurality of fourth memory cell structures each coupled to the fourth bitline;
wherein the first sense amplifier is further coupled to the third bitline to compare the first and third bitlines with each other; and
wherein the second sense amplifier is further coupled to the fourth bitline to compare the third and fourth bitlines with each other.

US Pat. No. 10,366,738

INTEGRATED MEMORY ASSEMBLIES COMPRISING MULTIPLE MEMORY ARRAY DECKS

Micron Technology, Inc., ...

1. An integrated memory assembly, comprising:a first memory array deck over a second memory array deck;
a first series of conductive lines extending across the first memory array deck, and a second series of conductive lines extending across the second memory array deck;
a first conductive line of the first series and a first conductive line of the second series being coupled with a first component through a first conductive path;
a second conductive line of the first series and a second conductive line of the second series being coupled with a second component through a second conductive path;
the first and second conductive lines of the first series extending through first isolation circuitry to the first and second conductive paths, respectively; the first isolation circuitry including a first transistor which gatedly connects the first conductive line of the first series to the first conductive path, and including a second transistor which gatedly connects the second conductive line of the first series to the second conductive path; the gates of the first and second transistors being coupled with a first isolation driver; and
the first and second conductive lines of the second series extending through second isolation circuitry to the first and second conductive paths, respectively; the second isolation circuitry including a third transistor which gatedly connects the first conductive line of the second series to the first conductive path, and including a fourth transistor which gatedly connects the second conductive line of the second series to the second conductive path; the gates of the third and fourth transistors being coupled with a second isolation driver.

US Pat. No. 10,366,736

MTP-THYRISTOR MEMORY CELL CIRCUITS AND METHODS OF OPERATION

Synopsys, Inc., Mountain...

1. A method of verifying a logic state of a selected data memory cell in an array of interconnected memory cells after programming or erasing the selected data memory cell, comprising:increasing a word line voltage applied to the selected data memory cell and a reference memory cell associated with the selected data memory cell;
latching an output of a first sense amplifier at a delayed time after a logic state of an output of a second sense amplifier is switched responsive to increasing the word line voltage, an amount of time between the switching of the logic state of the output of the second sense amplifier and the delayed time representing separation between a threshold voltage of the reference memory cell and a threshold voltage of the selected data memory cell, wherein:
when verifying programming of the selected data memory cell, the output of the first sense amplifier is an amplified version of an output of the selected data memory cell, and the output of the second sense amplifier is an amplified version of an output of the reference memory cell, and
when verifying erasing of the selected memory cell, the output of the first sense amplifier is an amplified version of the output of the reference memory cell, and the output of the second sense amplifier is an amplified version of the output of the selected data memory cell; and
determining whether the selected data memory cell has been programmed, or has been erased based on a value of the latched output of the first sense amplifier.

US Pat. No. 10,366,735

BOOSTING A DIGIT LINE VOLTAGE FOR A WRITE OPERATION

Micron Technology, Inc., ...

20. An electronic memory apparatus, comprising:a memory cell;
a boost component; and
a controller coupled with the memory cell and the boost component, wherein the controller is operable to:
applying, during a write operation, a first voltage to a digit line coupled with the memory cell;
coupling the boost component to the digit line during the write operation based at least in part on applying the first voltage; and
boosting the digit line to a second voltage during the write operation based at least in part on coupling the boost component to the digit line.

US Pat. No. 10,366,731

MEMORY DEVICES HAVING SPECIAL MODE ACCESS USING A SERIAL MESSAGE

Micron Technology, Inc., ...

1. A memory device comprising a register, a memory array, and a serial interface controller configured to receive and operate using a serial message to access the register that controls operation of the memory array by storing bits, the serial message having a format that comprises:a command field of the serial message configured to enable the serial interface controller to access the register;
a register address field of the serial message immediately following the command field indicating an address of the register; and
a data field of the serial message immediately following the register address field, wherein the data field of the serial message is configured to cause the memory device to operate according to a one time programmable (OTP) access mode.

US Pat. No. 10,366,730

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor system comprising:a semiconductor device configured to generate first group of data and second group of data in response to a command and an address, and
wherein, the semiconductor device configured to sequentially latch the first group of data loaded on a first group of I/O lines and the second group of data loaded on a second group of I/O lines to generate output data in response to a burst length information signal or to simultaneously latch the first and second groups of data loaded on the first and second groups of I/O lines to generate the output data in response to the burst length information signal.

US Pat. No. 10,366,726

INTERLACED MAGNETIC RECORDING IN WITH MULTIPLE INDEPENDENT-ACTUATORS HAVING RESPECTIVE INDEPENDENT HEADS

Seagate Technology LLC, ...

1. A method, comprising:writing a first set of bottom tracks via a first head that is moved via a first actuator over a surface of a disk; and
writing a second set of top tracks interlaced between and partially overlapping the bottom tracks via a second head that is moved via a second actuator over the surface of the disk independently of the first actuator and first head, the first and second actuators rotating about separate axes such that the first and second heads are rotationally offset from each other on the disk surface, the rotational offset allowing the first and second head to write both the bottom tracks and the top tracks simultaneously.

US Pat. No. 10,366,720

OXIDATION RESISTANT SENSOR FOR HEAT-ASSISTED MAGNETIC RECORDING

Seagate Technology LLC, ...

1. An apparatus, comprising:a slider comprising an air bearing surface (ABS) and configured for heat-assisted magnetic recording, the slider comprising:
a writer and a reader at the ABS;
a near-field transducer (NFT) proximate the writer;
an optical waveguide optically coupled to a laser source and the NFT;
a sensor configured to contact and sense thermal asperities of a magnetic recording medium, the sensor formed from one of Ru, Rh, Pd, Os, Ir, and Pt;
a protective coating covering at least a portion of the ABS including the writer, reader, NFT, and sensor; and
the sensor is configured to operate at a temperature that degrades the protective coating and exposes the sensor leaving the sensor unprotected.

US Pat. No. 10,366,719

BOOSTED PREHEAT TRAJECTORY TO OBTAIN DESIRED CLEARANCE BEFORE WRITING TO DISK

Seagate Technology LLC, ...

1. A method, comprising:engaging a resistive clearance heater embedded near an air bearing surface of a read/write head with a boosted current that exceeds a steady-state current, the steady-state current applied to the resistive clearance heater causing the write head to maintain a desired clearance over a disk during reading and writing, the boosted current applied before and after a start of the reading and the writing;
decreasing the boosted current according to a profile that has two or more steps that approximate a monotonically decreasing curve; and
applying the steady-state current to the resistive clearance heater after the start of the reading and the writing.

US Pat. No. 10,366,718

HARD DISK SERVO CONTROL ADAPTIVE NOTCH FILTER USING A RECURSIVE LEAST SQUARES PROCESSOR

Seagate Technology LLC, ...

1. A method comprising:monitoring a signal that provides an indicator of disturbance affecting a hard disk drive, the signal being monitored during an operational track following mode of the hard disk drive;
in response to determining that the indicator of the disturbance satisfies a threshold:
applying a lattice recursive least squares computation to the signal to determine at least one notch frequency; and
using the at least one notch frequency to form a notch filter used by a servo controller loop that positions a read/write head over a disk of the hard disk drive; and
apply the notch filter to the servo control loop for subsequent positioning of the read/write head.

US Pat. No. 10,366,717

MAGNETIC DISK DEVICE AND METHOD OF WRITING RRO CORRECTION DATA

Kabushiki Kaisha Toshiba,...

1. A magnetic disk device comprising:a disk which includes a plurality of servo sectors radially extending in a radial direction and being discretely disposed with a gap in a circumferential direction;
a head which writes data to the disk and reads data from the disk; and
a controller which writes a plurality of pieces of correction data with respect to a repeatable run-out of the disk to a plurality of first sectors disposed between the servo sectors in a first region, and writes the pieces of correction data to a plurality of second sectors disposed between the servo sectors in a second region different from the first region.

US Pat. No. 10,366,714

MAGNETIC WRITE HEAD FOR PROVIDING SPIN-TORQUE-ASSISTED WRITE FIELD ENHANCEMENT

Western Digital Technolog...

1. A magnetic write head for providing spin-torque-assisted write field enhancement,the magnetic write head comprising, within a write gap:
a main pole;
a trailing shield;
a spacer disposed between the main pole and the trailing shield, wherein the spacer is non-magnetic;
a non-magnetic layer disposed between the main pole and the trailing shield; and
a DC-field-generation (DFG) layer adjacent to the spacer and disposed between the spacer and the non-magnetic layer, wherein the DFG layer is magnetic,
wherein the DFG layer is the only magnetic layer within the write gap that is not adjacent to the main pole or the trailing shield.

US Pat. No. 10,366,708

SYSTEMS AND METHODS OF DETECTING SPEECH ACTIVITY OF HEADPHONE USER

BOSE CORPORATION, Framin...

1. A headphone system, comprising:a left earpiece;
a right earpiece;
a left microphone coupled to the left earpiece to receive a left acoustic signal and to provide a left signal derived from the left acoustic signal;
a right microphone coupled to the right earpiece to receive a right acoustic signal and to provide a right signal derived from the right acoustic signal; and
a detection circuit coupled to the left microphone and the right microphone, the detection circuit configured to process both a principal signal and a reference signal through a smoothing algorithm, the principal signal derived from a sum of the left signal and the right signal and the reference signal derived from a difference between the left signal and the right signal, the smoothing algorithm configured to calculate a principal power signal from a decaying weighted average of power of the principal signal over time, to calculate a reference power signal from a decaying weighted average of power of the reference signal over time, and to selectively indicate that the user is speaking based at least in part upon a comparison between the principle power signal and the reference power signal.

US Pat. No. 10,366,707

PERFORMING COGNITIVE OPERATIONS BASED ON AN AGGREGATE USER MODEL OF PERSONALITY TRAITS OF USERS

International Business Ma...

1. A method, in a natural language processing (NLP) system comprising a processor and a memory, the method comprising:receiving, by the NLP system, a plurality of communications associated with a communication system, over a predetermined time period, from a plurality of end user devices;
identifying, by the NLP system, for each communication in the plurality of communications, a user submitting the communication to thereby generate a set of users comprising a plurality of users associated with the plurality of communications;
retrieving, by the NLP system, a user model for each user in the set of users, wherein the user model specifies at least one personality trait of a corresponding user;
generating, by the NLP system, an aggregate user model that aggregates the at least one personality trait of each user in the set of users together to generate an aggregate representation of the personality traits of the plurality of users in the set of users; and
performing, by the NLP system, a cognitive operation based on the aggregate use model.

US Pat. No. 10,366,705

METHOD AND SYSTEM OF SIGNAL DECOMPOSITION USING EXTENDED TIME-FREQUENCY TRANSFORMATIONS

ACCUSONUS, INC., Lexingt...

1. A method of digital signal decomposition to identify components of a source signal comprising a first sound signal from a musical instrument and a second sound signal, comprising:obtaining a first representation of the source signal, during a first time period, comprising a mixture of the first and second sound signals;
calculating a time-frequency transformation of the first representation;
obtaining, during a second time period, a second representation of the source signal, which comprises the first sound signal captured in isolation of the second sound signal and/or the second sound signal captured in isolation of the first sound signal;
calculating a time-frequency transformation of the second representation;
forming an extended time-frequency transformation by combining the first time frequency transformation and the second time-frequency transformation;
applying a decomposition technique to the extended time-frequency transformation to extract one or more decomposed components of the source signal; and
audibly outputting one or more time domain signals related to the one or more decomposed components of the source signal.

US Pat. No. 10,366,704

ACTIVE ACOUSTIC ECHO CANCELLATION FOR ULTRA-HIGH DYNAMIC RANGE

Intel Corporation, Santa...

1. An apparatus comprising:a speaker to generate audio output;
an audio input device to receive audio input and to provide an audio input signal responsive to the audio input at a first sampling rate; and
one or more processors coupled to the speaker and the audio input device, the one or more processors to:
generate an audio output signal having at least a portion thereof corresponding to a first audio frequency range, the portion of the audio output signal, when provided as first audio output from the speaker, to negate a response of the audio input device, at a response negation rate, to second audio output from the speaker in a second audio frequency range, wherein each audio frequency of the first audio frequency range exceeds a maximum audio frequency of the second audio frequency range; and
decimate the audio input signal based on the response negation rate to a second sampling rate less than the first sampling rate to generate a resultant audio input signal.

US Pat. No. 10,366,698

VARIABLE LENGTH CODING OF INDICES AND BIT SCHEDULING IN A PYRAMID VECTOR QUANTIZER

DTS, Inc., Calabasas, CA...

19. A transform-based audio signal decoder comprising:a bitstream-unpacking circuit configured to determine a plurality of encoded values from an encoded bitstream, wherein the bitstream is a digital representation of the frequency domain transform of the input audio signal an encoded value of the plurality of encoded values including a first portion and a second portion, the first portion including an index to an element of an unsigned pyramid that is defined by a vector size and a quantization parameter, and the second portion including a corresponding sign value for each nonzero component of the element of the unsigned pyramid;
an inverse-quantizer circuit that is configured to determine a coefficient block corresponding to the vector size for a resolution corresponding to the quantization parameter from the encoded value of the plurality of encoded values, the coefficient block being determined from the encoded value of the plurality of encoded values by using the first and second portions of the encoded value to identify an element of a signed pyramid that corresponds to the unsigned pyramid for the vector size and quantization parameter, the identified element of the signed pyramid including sign values that are identified from the second portion of the encoded values;
an inverse coefficient-processing circuit configured to determine a plurality of frequency-transform coefficients from a plurality of coefficient blocks determined by the inverse-quantizer circuit for the plurality of encoded values; and
an audio circuit configured to generate an audio signal from the plurality of frequency-transform coefficients.

US Pat. No. 10,366,697

METHOD AND DEVICE FOR ENCODING A HIGH FREQUENCY SIGNAL, AND METHOD AND DEVICE FOR DECODING A HIGH FREQUENCY SIGNAL

HUAWEI TECHNOLOGIES CO., ...

1. A method for encoding a high frequency signal, comprising:determining a signal type of the high frequency signal of a current frame;
when the high frequency signal of the current frame is non-transient and the high frequency signal of a previous frame is transient, smoothing or scaling a time envelope of the high frequency signal of the current frame to obtain a processed time envelope of the high frequency signal of the current frame; and
quantizing and encoding the processed time envelope, frequency information, and signal type information of the high frequency signal of the current frame,
wherein in quantizing and encoding the signal type information, the high frequency band portion of the current frame is indicated as transient type.

US Pat. No. 10,366,696

SPEECH DECODER WITH HIGH-BAND GENERATION AND TEMPORAL ENVELOPE SHAPING

NTT DOCOMO, INC., Tokyo ...

1. A speech decoding device for decoding an encoded speech signal, the speech decoding device comprising:a processor configured to:
separate a bit stream that includes the encoded speech signal into an encoded bit stream and temporal envelope supplementary information, the bit stream received from outside the speech decoding device and the temporal envelope supplementary information comprising an indicator associated with a predetermined parameter;
decode the encoded bit stream to obtain a low frequency component;
transform the low frequency component into a spectral region;
generate a high frequency component by copying, from a low frequency band to a high frequency band, the low frequency component transformed into the spectral region;
adjust the high frequency component generated by the high frequency generating unit to generate an adjusted high frequency component;
analyze the low frequency component transformed into the spectral region to obtain temporal envelope information;
obtain the temporal envelope information by obtaining power of each quadrature mirror filter (QMF) subband sample of the low frequency component transformed into the spectral region;
convert the indicator included in the temporal envelope supplementary information into the predetermined parameter, wherein the predetermined parameter is for adjustment of the temporal envelope information;
adjust the temporal envelope information by adjusting the each QMF subband sample using the predetermined parameter to generate adjusted temporal envelope information; and
shape a temporal envelope of the adjusted high frequency component using the adjusted temporal envelope information.

US Pat. No. 10,366,692

ACCESSORY FOR A VOICE-CONTROLLED DEVICE

Amazon Technologies, Inc....

13. A device comprising:one or more microphones;
one or more speakers;
one or more processors; and
one or more computer-readable media storing computer-executable instructions that, when executed, cause the one or more processors to perform acts comprising:
generating first audio data based at least in part on speech of a user in an environment, the speech captured by the one or more microphones;
sending the first audio data to one or more remote computing devices;
receiving, from the one or more remote computing devices, second audio data for output by the one or more speakers, the second audio data including:
first audio representing audio that is below 20 kHz, and
second audio representing audio that is above 20 kHz, the second audio comprising one or more instructions for instructing an accessory device in the environment to acquire supplemental content; and
outputting the second audio data by the one or more speakers, the second audio data including the first audio for the user to hear and the second audio for instructing the accessory device.

US Pat. No. 10,366,691

SYSTEM AND METHOD FOR VOICE COMMAND CONTEXT

Samsung Electronics Co., ...

1. A multi-input method for controlling a head mounted display, the method comprising:displaying, on a display of the head mounted display, content including an object;
tracking a position of an eye focus in relation to a position on the display;
maintaining a log of the position of the eye focus in relation to the display, and the content in proximity to the position of the eye focus on the display;
determining an area of the eye focus on the display, and associating the area of the eye focus with the object;
receiving a verbal command;
deriving a command based on a detected set of lip movements;
extracting contextual information from at least one of the object associated with the eye focus, the received verbal command, or the derived command;
determining an intended command, based on the extracted contextual information and at least one of the verbal command or the derived command; and
performing the determined intended command.

US Pat. No. 10,366,689

COMMUNICATION ROBOT

KYOCERA Corporation, Kyo...

1. A communication robot comprising:a housing;
a speaker;
a storage; and
a controller, wherein
the storage is configured to store first information including information for a native language of a user and information regarding a country of residence, and second information indicating a plurality of intensity levels of the user's response corresponding to a plurality of motions of the communication robot, respectively, and
when a motion of the communication robot is a motion of emitting a sound including a particular phoneme that is based on a language of the country of residence that is not found in the native language of the user, the controller is configured to increase an intensity level corresponding to the motion of emitting a sound including the particular phoneme, and perform the motion of emitting a sound including the particular phoneme at an increased number of repeats based on the increased intensity level.

US Pat. No. 10,366,688

VOICE CONTROL USER INTERFACE WITH MULTIPLE VOICE PROCESSING MODULES

Google Technology Holding...

1. A computer-implemented method comprising:during operation of a mobile device in a low-power mode in which functionality of a voice recognition engine of the mobile device is reduced:
receiving, at data processing hardware of the mobile device, an utterance of at least an initial portion of a predetermined command phrase, the predetermined command phrase comprising a series of multiple words configured to cause the mobile device to wake-up from the low-power mode in response to detecting each word of the series of multiple words in the utterance;
detecting, by the data processing hardware, the initial portion of the predetermined command phrase in the utterance; and
in response to detecting the initial portion of the predetermined command phrase in the utterance:
determining, by the data processing hardware, whether a remaining portion of the predetermined command phrase is detected in the utterance within a first predetermined period of time after detecting the initial portion of the predetermined command phrase in the utterance; and
activating, by the data processing hardware, a display of the mobile device to present display data for output on the display; and
when the remaining portion of the predetermined command phrase is detected in the utterance within the predetermined period of time, commanding, by the data processing hardware, the mobile device to wake-up from the low-power mode and operate in an awake mode; and
during operation of the mobile device in the awake mode in which full functionality of the speech recognition engine is provided, detecting, by the data processing hardware, a voice command in the received utterance that follows the predetermined command phrase.

US Pat. No. 10,366,676

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device, comprising:a display panel equipped with a plurality of pixels connected with data lines and gate lines;
a data driving circuit configured to provide data voltage to the pixels through the data lines; and
a gate driving circuit configured to drive the gate lines,
wherein a first pixel disposed in n-th pixel line among the plurality of pixels, n being a natural number, comprises:
a light emitting diode;
a driving TFT, whose source is connected to the light emitting diode, configured to control a current flowing the light emitting diode;
a capacitor connecting the source of the driving TFT and a gate of the driving TFT;
a first TFT configured to be controlled by a first gate signal which is transferred through a first gate line and generated by the gate driving circuit to connect the gate of the driving TFT to one of the data lines;
a second TFT configured to be controlled by a second gate signal which is transferred through a second gate line and generated by the gate driving circuit to connect the gate of the driving TFT to an initialization voltage; and
a third TFT configured to be controlled by the second gate signal transferred to a second pixel disposed in (n?1)-th pixel line to connect the source of the driving TFT to a reference voltage,
wherein, in a first portion of a threshold voltage sensing period, a voltage of the source of the driving thin film transistor is configured to rise to a value smaller than a value obtained by subtracting a threshold voltage of the driving thin film transistor from a voltage of the gate of the driving thin film transistor, such that a voltage higher than the threshold voltage is charged to the capacitor, and
wherein, in a second portion of the threshold voltage sensing period, the voltage of the source is configured to rise and the voltage of the gate is configured to rise due to the capacitor, wherein the voltage of the gate is configured to rise less than the voltage of the source is configured to rise such that a voltage close to the threshold voltage is charged to the capacitor.

US Pat. No. 10,366,675

LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING SAME

SHARP KABUSHIKI KAISHA, ...

1. A liquid crystal display device employing a field sequential system, the liquid crystal display device performing color display by dividing one frame period into a plurality of fields and rewriting a screen on a field-by-field basis, the liquid crystal display device comprising:a liquid crystal panel configured to display an image formed of a plurality of pixels;
a gradation value compressing unit configured to generate compressed data by performing a compression process, the compression process being a process of correcting input gradation data such that a difference between a maximum gradation value and a minimum gradation value is reduced; and
a liquid crystal panel driving unit configured to drive the liquid crystal panel based on the compressed data, wherein
the gradation value compressing unit performs the compression process such that values of input gradation data of a plurality of colors change at a same ratio, the plurality of colors corresponding to the plurality of fields,
the gradation value compressing unit determines a value of the compressed data by multiplying a value of the input gradation data by a compression coefficient, the compression coefficient being a value greater than 0 and less than or equal to 1, and
the gradation value compressing unit determines the value of the compression coefficient used upon the compression process, depending on a magnitude of the value of the input gradation data.

US Pat. No. 10,366,673

DISPLAY DEVICE AND IMAGE PROCESSING METHOD THEREOF

LG Display Co., Ltd., Se...

1. A display device, comprising:a display panel including a plurality of pixels formed of red, green, blue, and white sub pixels;
an image processing unit for converting a three-color input image supplied to the red, green, blue, and white sub pixels into four-color image data and for outputing an output image by applying a final gain calculated using a frame gain, a pixel gain, and a block gain of pixels of the three-color input image; and
a timing controller for outputing the output image from the image processing unit to the display panel,
wherein the block gain is calculated using (i) scaled versions of luminance values of the three-color input image and (ii) a position information of the pixels of the three-color input image.