US Pat. No. 10,116,232

COLLOCATION OF RADIATION GENERATOR COMPONENTS FOR LIMITED-SPACE DEVICES

SCHLUMBERGER TECHNOLOGY C...

1. A compact radiation generator for use in a downhole well-logging tool, the compact radiation generator comprising:a housing comprising a cavity and an axis down a length of the housing;
a linear acceleration tube in the cavity that generates radiation when supplied with a sufficiently high voltage; and
a first voltage multiplier ladder in the cavity configured to supply the sufficiently high voltage to the acceleration tube, wherein the first voltage multiplier ladder comprises a first linear part and a second linear part, wherein the first linear part is electrically coupled to and receives power from a transformer and is disposed parallel to the axis of the compact radiation generator and collocated with the second linear part, wherein the first linear part and the second linear part of the first voltage multiplier ladder are connected to one another at a turnover point that is electrically partway through the first voltage multiplier ladder, wherein the transformer is collocated at a same position along the axis as at least a portion of the second linear part or a portion of the acceleration tube.

US Pat. No. 10,116,203

TRANSFORMER INCLUDING A CURRENT INDUCTION DEVICE HAVING AN AMPLIFIER CIRCUIT

1. A transformer comprising:a first transformer;
a second transformer;
a current induction device; and
an amplifier circuit, wherein the current induction device is provided in a load line of the first transformer for detecting an induction current in the load line of the first transformer; wherein an induction output end of the current induction device is connected to a control winding; and the control winding is provided in a winding of the second transformer for generating an induction voltage in the winding of the second transformer so as to supplement the output power of the first transformer;
wherein the amplifier circuit is provided in an induction output line of the current induction device, wherein the amplifier circuit protects a first amplifier circuit and a second amplifier circuit, the first amplifier circuit having a first amplification coefficient value and the second amplifier circuit having a second amplification coefficient value;
wherein a primary coil of the first transformer is connected to a primary coil of the second transformer in series and a secondary coil of the first transformer is connected to a secondary coil of the second transformer in series; and
wherein a three-terminal synchronization rectifier is provided in the induction output line of the current induction device.

US Pat. No. 10,116,184

ROBOT HAVING ISOLATED STATOR AND ENCODER

Persimmon Technologies Co...

1. An apparatus comprising:a housing;
a motor comprising a stator and a rotor, where the stator is connected to the housing;
an environment barrier extending between the stator and the rotor; and
a sealing system connecting the environment barrier with the housing, where the sealing system comprises a first seal interface and a second seal interface, where the first seal interface connects to the housing at a first diameter which is at least partially less than or equal to an inner diameter of the stator, and where the second seal interface connects to the housing at a second diameter which is at least partially greater than or equal to an outer diameter of the stator.

US Pat. No. 10,116,178

ROTOR WITH EMBEDDED PERMANENT MAGNET HAVING ADHESIVE ON ONE SIDE AND COOLING CHANNELS ON THE OTHER SIDE

Mitsubishi Electric Corpo...

1. An embedded permanent magnet rotary electric machine comprising:a stator comprising:
an annular stator core; and
a stator coil that is mounted to said stator core; and
a rotor comprising:
a rotor core that is configured by laminating and integrating electromagnetic steel sheets, and that is fixed to a shaft so as to be disposed rotatably inside said stator core;
a plurality of permanent magnet housing apertures that are disposed circumferentially so as to be respectively formed so as to pass axially through an outer circumferential side of said rotor core; and
permanent magnets that are housed in each of said magnet housing apertures,
wherein:
at least one coolant flow channel is formed so as to pass axially through said rotor core radially inside said magnet housing apertures;
a linking flow channel is formed so as to have a flow channel width that is narrower than a maximum flow channel width of said coolant flow channel, so as to link said coolant flow channel and said magnet housing apertures, and so as to pass axially through said rotor core; and
said permanent magnets are fixed to an inner wall surface of said magnet housing apertures by an adhesive that is disposed only between a wall surface of said permanent magnets that is positioned on a radially inner side or a radially outer side of said permanent magnets and said inner wall surface of said magnet housing apertures so as to expose a region of a wall surface of said permanent magnets that is positioned on a radially inner side that faces said linking flow channel.

US Pat. No. 10,116,177

ROTOR FOR ROTARY ELECTRIC MACHINE

Mitsubishi Electric Corpo...

1. A rotor for a rotary electric machine, comprising:a shaft;
a rotor core through which the shaft passes, for rotating integrally with the shaft; and
a plurality of permanent magnets, each being extended in an axial direction of the rotor core and being fixed to the rotor core along a circumferential direction of the rotor core,
wherein the rotor core comprises:
a first core portion comprising a plurality of core pieces joined together through caulking portions, and a hollow first lightening portion separated away from the shaft in a radial direction of the rotor core; and
a second core portion comprising a plurality of core pieces joined together through caulking portions, and a press-fit portion held in close contact with the first core portion, into which the shaft is press-fitted,
wherein a radial width of a magnetic path of a ring-shaped outer circumferential portion formed by laminating the first core portion and the second core portion changes along the circumferential direction, and
wherein the shaft passing through a center axis line of the hollow first lightening portion of the first core portion is surrounded by a ring through a gap portion therebetween.

US Pat. No. 10,116,176

PERMANENT MAGNET EMBEDDED ELECTRIC MOTOR, COMPRESSOR AND REFRIGERATION AIR CONDITIONER

Mitsubishi Electric Corpo...

1. A permanent magnet embedded electric motor comprising:a stator;
a rotor disposed on an inner diameter side of the stator; and
permanent magnets inserted in a plurality of magnet insertion holes formed in a rotor iron core of the rotor,
wherein
the rotor iron core includes:
a plurality of first slits that are formed on an outer side of the magnet insertion hole, and communicate with the magnet insertion hole;
a plurality of second slits formed at positions opposed to and spaced apart from the first slits;
inter-slit iron core portions formed between the first slits and the second slits;
outer side iron core portions formed between the second slits and an outer circumferential surface of the rotor iron core;
space portions communicating with rotating direction end portions of the magnet insertion hole; and
thin iron core portions that are formed between the space portions and the outer circumferential surface of the rotor iron core, and extend in a rotating direction, and
the rotor iron core has a shape satisfying a relation of H1>H2, where H1 denotes a width of the first slit in a radial direction, and H2 denotes a width of the second slits in a radial direction.

US Pat. No. 10,116,175

ROTARY ELECTRIC MACHINE AND STATOR OF ROTARY ELECTRIC MACHINE

TOYOTA JIDOSHA KABUSHIKI ...

1. A stator of a rotary electric machine, the rotary electric machine comprising a rotor, the rotor comprising a plurality of magnetic poles, the stator comprising:a stator core defining an axial direction and a circumferential direction, the stator core comprising:
a plurality of stacked annular electromagnetic steel plates, each of the annular electromagnetic steel plates comprising a plurality of coupling portions such that the annular electromagnetic steel plates are coupled with one another by the coupling portions, the coupling portions arranged with equal pitches in the circumferential direction, each of the coupling portions arranged with a pitch of an integral multiple of a central angle, the central angle being defined as an angle between two circumferentially adjacent magnetic poles of the same polarity from among the magnetic poles relative to a rotational center of the rotor, and
a plurality of fixing portions projecting radially outward from an outer circumferential surface of the stator core, each of the fixing portions comprising a through-hole extending therethrough in the axial direction, the fixing portions arranged with equal pitches in the circumferential direction, a quantity of the coupling portions being an odd number, each of the fixing portions arranged with either the same pitch as the pitch of each of the coupling portions, or with a pitch corresponding to a divisor of the pitch of each of the coupling portions relative to the rotational center of the rotor; and
a coil wound around teeth of the stator core.

US Pat. No. 10,116,174

SYNCHRONOUS RELUCTANCE ELECTRIC MACHINE

GM Global Technology Oper...

1. A synchronous reluctance electric machine, comprising:a stator including a plurality of electrical windings;
a rotor disposed in a cylindrically-shaped void formed within the stator and including a plurality of steel laminations assembled onto a shaft,
wherein the shaft defines a longitudinal axis,
wherein each of the steel laminations includes a plurality of poles and wherein each of the poles includes a plurality of slots disposed near an outer periphery, and
wherein the slots of the steel laminations are longitudinally aligned; and
a plurality of packets assembled from anisotropic material and disposed in the slots, wherein each of the packets assembled from anisotropic material comprises a stack including a plurality of laminations fabricated from a grain-oriented steel material, wherein the grain-oriented steel material of the plurality of laminations are aligned along a common axis.

US Pat. No. 10,116,173

PARKING ASSISTANCE DEVICE AND PARKING ASSISTANCE METHOD

NISSAN MOTOR CO., LTD., ...

1. A parking assistance device used in a wireless power supply system which performs wireless power supply between a power transmitting coil on a ground side and a power receiving coil on a vehicle side, the parking assistance device comprising:three or more coils aligned in one direction in a plan view of the vehicle, the coils being configured to detect magnetic flux in a height direction of the vehicle which is generated by the power transmitting coil;
a vehicle controller configured to detect misalignment between the power transmitting coil and the power receiving coil in the one direction, based on a decrease in the magnetic flux in the height direction of the vehicle which is detected by the three or more coils; and
an output unit configured to notify a user of a result of the misalignment detection.

US Pat. No. 10,116,172

CHARGING DEVICE AND HAND-HELD DEVICE FOR A SMALL MOBILE ELECTRICAL DEVICE

TRISA HOLDING AG, Trieng...

1. A charging device for contactless transmission of energy for the energy supply of a cordless hand-held device, wherein the charging device comprises:an electronic circuit for feeding an inductive energy transmitter, the circuit being configured to adapt energy fed to the inductive energy transmitter, in accordance with energy taken from the inductive energy transmitter, the circuit comprising:
a primary winding for feeding a hand-held device, wherein the primary winding is part of an oscillation circuit;
a driver circuit for the pulsed feeding of energy into the oscillation circuit in accordance with a driver signal;
a current measuring circuit for producing a current measurement signal corresponding to a current flowing into the oscillation circuit; and
a control device which is configured to detect the current measurement signal and, in accordance with the current measurement signal, to generate the driver signal for the activation of the driver circuit, as a pulse-width modulated signal with a frequency corresponding to a resonance frequency of the oscillation circuit,
wherein the current measuring circuit comprises a measuring shunt and a rectifier circuit for rectifying a voltage occurring across the measuring shunt and for generating the current measurement signal, and the control device comprises a microprocessor or microcontroller comprising an analog input for determining the current measurement signal.

US Pat. No. 10,116,168

WIRELESS POWER TRANSMITTER DEVICE AND WIRELESS POWER RECEIVER DEVICE

HTC Corporation, Taoyuan...

1. A wireless power transmitter device comprising:a transmitter circuit configured to generate a transmitting current;
a transmitter coil electrically connected to the transmitter circuit, wherein the transmitter coil is configured to receive the transmitting current to generate an electromagnetic field to induce a receiving current in a wireless power receiver device;
a transmitter communication unit to receive a report of a received power of the wireless power receiver device therefrom; and
a transmitter control unit electrically connected to the transmitter circuit, the transmitter coil, and the transmitter communication unit, wherein the transmitter control unit is configured to receive the report of the received power from the transmitter communication unit and determine whether a frequency splitting phenomena occurs according to the received power,
wherein the transmitter circuit comprises a plurality of component groups each comprising a plurality of circuit components having different component values and a plurality of selecting circuits each corresponds to one of the component groups;
wherein the transmitter control unit adjusts the configuration of the transmitter circuit by controlling the selecting circuits to select one of the circuit components within each of the component groups to be activated in the transmitter circuit,
wherein when the frequency splitting phenomena occurs, the transmitter control unit adjusts at least one of a configuration of the transmitter coil and a configuration of the transmitter circuit or adjusts a transmitting frequency of the transmitting current.

US Pat. No. 10,116,167

INDUCTIVE POWER TRANSMISSION DEVICE

1. A power transmission device for inductive energy transfer, wherein the power transmission device comprises:a first stage adapted to be connected to a supply input voltage and adapted to convert the supply input voltage to an operating voltage;
a second stage including a resonant circuit connected to the first stage and adapted to generate an oscillating voltage from the operating voltage so as to generate a magnetic field for inductive transfer of energy from the power transmission device to a target device;
a control circuit connected to the second stage, the control circuit being adapted to detect a parameter value of the second stage, the detected parameter indicating whether the target device is being recharged or not, and adapted to start or stop amplification of the resonant circuit based on the detected parameter value;
wherein the resonant circuit is composed by the parallel connection of a capacitor with a winding of a transfer coil and a magnetically coupled sensing coil, both coils being wound around a core and serving as primary coils for inductively transferring energy to the target device including a secondary coil, and
wherein the control circuit is configured to detect the parameter value of the sensing coil;
wherein the second stage further includes a switching element connected to the resonant circuit, the switching element being adapted to amplify the oscillations of the resonant circuit so as to start or stop amplification of the resonant circuit;
wherein the control circuit is adapted to detect an oscillation voltage value of the sensing coil of the resonant circuit and to switch the switching element in-phase with the oscillations of the resonant circuit so as to amplify the oscillation of the resonant circuit, the switching of the switching element being performed as zero-voltage switching amplification of the resonant circuit.

US Pat. No. 10,116,165

POWERGRID OPERATION AND SUPERVISION SYSTEM

GENERAL ELECTRIC TECHNOLO...

1. A system for facilitating operation and monitoring of a power grid system comprising:a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
determining a measured operating condition by monitoring one or more portions of the power grid system;
generating an operation plan for planned outages, wherein the planned outages are determined to satisfy a defined criterion associated with an effect on system operation of the power grid system, wherein the operation plan is based on a predicted operating condition of the power grid system, wherein the predicted operating condition comprises a predicted operation limit for the one or more portions of the power grid system, and wherein the generating the operation plan comprises comparing the predicted operating limit for the one or more portions of the power grid system to the measured operating condition;
determining an action plan based on the operation plan, wherein the action plan comprises a set of tasks to be performed to accomplish the operation plan;
facilitating execution of switching management operations associated with the power grid system by transmitting instructions associated with the set of tasks to an energy management system and a distribution management system; and
maintaining a log record of the set of tasks, the instructions, and task completion times associated with the set of tasks.

US Pat. No. 10,116,164

FLEXIBLE CONTROL ARCHITECTURE FOR MICROGRID RESILIENCY

Siemens Aktiengesellschaf...

1. A control system for controlling an electrical power microgrid including loads and distributed energy resources, the control system comprising:a component control layer including component control devices connected directly to the loads and distributed energy resources;
a middle level control layer including aggregating control devices, each aggregating control device being connected to a respective plurality of the component control devices;
a microgrid control layer including one or more microgrid control devices connected to the aggregating control devices and further comprising a contingency metric computation module for computing a contingency metric indicating a level of operational threat based on characteristics of the electrical power microgrid and its environment;
the control system being configured to operate in a centralized mode when the contingency metric indicates substantially no operational threat, wherein the electrical power microgrid communicates with a main grid, instructions and set points for the loads and distributed energy resources are transmitted from the microgrid control layer to the middle level control layer and the component control layer, and the control system maintains a first level of real time reserve margin;
the control system being further configured to operate in a first intermediate mode when the contingency metric indicates a first intermediate operational threat, wherein the electrical power microgrid is operated partially in an island mode, the instructions and set points for the loads and distributed energy resources are transmitted from the microgrid control layer to the middle level control layer and the component control layer, and the control system maintains a second level of real time reserve margin, wherein the second level of real time reserve margin is lower than the first level of real time reserve margin;
the control system being further configured to operate in a second intermediate mode when the contingency metric indicates a second intermediate operational threat greater than the first intermediate operational threat, wherein the electrical power microgrid is operated in the island mode, the instructions and set points for the loads and distributed energy resources are transmitted from the middle level control layer to the component control layer without receiving instructions and set points from the microgrid control layer, and the control system maintains a minimum real time reserve margin;
the control system being further configured to operate in a decentralized mode when the contingency metric indicates a high operational threat, wherein the electrical power microgrid is operated in the island mode, the component control layer is operated without receiving instructions and set points from the middle level control layer or the microgrid control layer, and the control system maintains no real time reserve margin.

US Pat. No. 10,116,163

UNINTERRUPTIBLE POWER SUPPLY (UPS) DIRECT CURRENT (DC) LOAD LEVELING

GENERAL ELECTRIC COMPANY,...

1. A system comprising:an alternating current (AC)-direct current (DC) converter configured to convert power from an AC supply to a DC bus to provide a first portion of power to a medical imaging load;
an uninterruptible power supply (UPS) coupled to the DC bus, wherein the UPS comprises:
at least one battery cell; and
a DC-DC converter comprising one or more switches and coupled between the at least one battery cell and the DC bus; and
a control system comprising a processor configured to send one or more signals to control operation of the one or more switches to cause the DC-DC converter to control power discharged from the at least one battery cell to the DC bus to provide a second portion of power to the medical imaging load;
wherein the DC bus is directly coupled to the medical imaging load and is configured to provide the first and second portions of power to the medical imaging load as DC power.

US Pat. No. 10,116,160

CHARGING CIRCUIT, AN INDUCTIVE LOAD CONTROL CIRCUIT, AN INTERNAL COMBUSTION ENGINE, A VEHICLE AND A METHOD OF CHARGING A BOOTSTRAP STORAGE ELEMENT

NXP USA, Inc., Austin, T...

1. A charging circuit for a bootstrap charge storage element, the charging circuit comprising:a switch arrangement, configured to connect between a voltage source and the bootstrap charge storage element, wherein
the switch arrangement comprises a first switch and a second switch connected in series, and
said switch arrangement is arranged to allow charging current to flow from the voltage source through the first and second switches to the bootstrap charge storage element to allow the bootstrap charge storage element to charge while both of the first and second switches are turned on;
the first switch comprising a first reverse bias element in parallel to current terminals of the first switch, wherein said first reverse bias element is arranged to prevent current flow from the power supply to the bootstrap charge storage element when the first switch is turned off;
the second switch comprising a second reverse bias element in parallel to current terminals of the second switch, wherein the second reverse bias element is arranged to prevent current flow from the bootstrap charge storage element to the voltage source when the second switch is turned off;
a charge pump coupled to a control terminal of the second switch; and
a control arrangement coupled to the second switch and arranged to prevent turning on of the second switch while the first switch is turned off.

US Pat. No. 10,116,157

METHOD AND DEVICE FOR CHARGING BATTERIES IN MOBILE DEVICES

Xiaomi Inc., Beijing (CN...

1. A method for power charging, comprising:establishing an electrical connection between a first electronic device and a second electronic device;
acquiring, by the second electronic device via the electrical connection, real-time charging voltage information of a battery in the first electronic device, wherein the real-time charging voltage information varies with a charge state of the battery in the first electronic device; and
controlling by the second electronic device, during charging of the battery in the first electronic device by the second electronic device, an output voltage of the second electronic device to charge the battery of the first electronic device according to the real-time charging voltage information,
wherein the real-time charging voltage information for the first electronic device is a real-time internal resistance of the battery in the first electronic device multiplied by a preset current value when the charge state indicates that a present voltage of the battery is smaller than a preset voltage value, wherein an effective internal resistance of the battery varies with the charge state of the battery in the first electronic device; and
the real-time charging voltage information of the battery in the first electronic device is the preset voltage value when the charge state indicates that the present voltage of the battery in the first electronic device is equal to or greater than the preset voltage value.

US Pat. No. 10,116,156

HYBRID BATTERY

SHENZHEN CARKU TECHNOLOGY...

1. A hybrid battery comprising:a first energy storage device (1) for providing a low-current power supply,
a second energy storage device (2) for providing an instantaneous starting current power supply, and
a detection control circuit (5) coupled in parallel with the first energy storage device (1), wherein the detection control circuit (5) detects an output current flowing through the first energy storage device (1),
wherein the detection control circuit (5) is configured to control the first and second energy storage devices to supply power to an automobile according to the output current detected, and wherein when the output current detected is a low current, power is supplied to the automobile by the first energy storage device, and when the output current detected is a high current, power is supplied to the automobile by the second energy storage device, thereby preventing the first energy storage device from being harmed;
wherein negative terminals of the first energy storage device (1) and the second energy storage device (2) are coupled to a negative pole (10), a positive terminal of the first energy storage device (1) is coupled to a first fixed contact (7) of a relay (6), a positive terminal of the second energy storage device (2) is coupled to a second fixed contact (8) of the relay (6), the detection control circuit (5) is coupled to a coil of the relay (6), an input terminal of the relay (6) is coupled to a positive pole (9), and the positive pole (9) and negative pole (10) are coupled to a positive electrode and a negative electrode of an electric load of the automobile, respectively;
wherein the detection control circuit (5) operates in the following manner,
when the output current is a low current, under the control of the detection control circuit, a movable contact (11) of an armature of the relay (6) is connected to the first fixed contact (7) and disconnected from the second fixed contact (8), then the first energy storage device (1) is coupled between the positive pole (9) and the negative pole (10) to supply power to the automobile;
when the output current is a high current, under the control of the detection control circuit, the movable contact (11) of the armature of the relay (6) is disconnected from the first fixed contact (7) but connected to the second fixed contact (8), then the second energy storage device (2) is coupled between the positive pole (9) and the negative pole (10) to supply power to the automobile;
wherein after the movable contact (11) of the armature of the relay (6) is coupled to the second fixed contact (8) for 1 to 10 s, the relay is reset.

US Pat. No. 10,116,149

AUTOMATIC CONTROL SYSTEM FOR A RECHARGEABLE BATTERY SYSTEM

Elite Power Solutions, LL...

1. An automatic battery control system comprising:a) a battery unit;
b) a microprocessor;
c) a battery management system that measures a state of charge of said battery unit and comprises:
i) an over-voltage output that provides an over-voltage signal to said microprocessor when the battery unit has a measured state of charge greater than an upper threshold limit;
ii) an under-voltage output that provides an under-voltage signal to said microprocessor when the battery unit has a measured state of charge less than a lower threshold limit; and
iii) a current flow output that provides a current signal of current flow direction into or out of said battery to said microprocessor;
d) an automatic battery control circuit coupled to the battery management system, the microprocessor and the battery unit and comprising:
i) a relay comprising:
a single relay contactor extending from an input side to an output side;
a transistor; and
ii) a parallel resistor configured in parallel with the relay contactor from said input side to said output side;
iii) a discharge optocoupler coupled between the automatic battery control circuit and the microprocessor;
iv) a charge optocoupler coupled between the automatic battery control circuit and the microprocessor;
v) a difference amplifier that senses a relay potential that is a voltage potential across the parallel resistor and communicates with the discharge optocoupler and charge optocoupler;
wherein the discharge optocoupler sends a signal to the microprocessor when the relay potential from the inlet to outlet side is positive;
wherein the charge optocoupler sends a signal to the microprocessor when the relay potential from the inlet to outlet side is negative;
wherein with the relay contactor open, a reduction in an output side voltage of the output side is indicated by the discharge optocoupler to the microprocessor, and when the battery is above a threshold discharge limit, the relay contactor is closed by said transistor and the battery unit is connected to a load and place the automatic battery control system in a discharge mode; and
wherein with the relay contactor open, an increase in the output side voltage of the output side is indicated by the charge optocoupler to the microprocessor, and when the battery is below a threshold charge limit, the relay contactor is closed by said transistor to connect the battery unit to a charging power source to place the automatic battery control system in a charge mode.

US Pat. No. 10,116,146

NON-CONTACT POWER TRANSMISSION DEVICE AND LOCATION-BASED SERVICE SYSTEM USING THE SAME

Samsung Electro-Mechanics...

1. A non-contact power transmission device comprising:a power transmission unit configured to contactlessly provide electric power;
a controller configured to provide location information of the non-contact power transmission device; and
a communications unit configured to transmit the location information and product information received from a non-contact power reception device to a server, and receive an approval to transmit electric power to the non-contact power reception device from the server.

US Pat. No. 10,116,141

SYSTEM AND METHOD OF ENERGY RESOURCE DELIVERY

ROLLS-ROYCE plc, London ...

1. Apparatus for coordinating energy distribution over a local energy network having at least one generator and a plurality of systems requiring an energy supply for operation, each system in the local network being connected to the at least one generator and/or another system in the network for distribution of energy there-between, the apparatus comprising:an agent for each respective one of the generator and systems, the agent having a data store, a data processor and a data transmitter and receiver for transmission and receipt of data communication with one or more of the other agents,
wherein the data processor of each agent is programmed to recognise a predetermined communication sequence with another agent, where the communication sequence comprises a plurality of communications with the another agent in a plurality of ordered data communication steps required to initiate supply of energy between the generator or system of said agent and the generator or system associated with the another agent, each communication sequence being assigned a future time period for which the energy supply is to be enacted, and wherein the data processor of each agent is programmed to initiate supply of energy between the generator or system of said agent and the generator or system associated with the another agent based on the predetermined communication sequence.

US Pat. No. 10,116,138

WIND POWER PLANT, AND A METHOD FOR CONTROLLING A REACTIVE CURRENT INJECTION IN A WIND POWER PLANT

1. A method for controlling a reactive current injection in a wind power plant during a grid fault, comprising:measuring, at a point of measurement between a plurality of wind turbine generators in the wind power plant and a grid, an amount of reactive current provided by the wind power plant to the grid during the grid fault, wherein the amount of reactive current is produced by the wind plant in response to a required reactive current contribution;
determining a difference between the required reactive current contribution and the amount of reactive current provided by the wind power plant to the grid during the grid fault; and
controlling the plurality of wind turbine generators in the wind power plant to generate additional reactive current according to a reactive current reference generated based on the difference.

US Pat. No. 10,116,136

PRIMARY FREQUENCY CONTROL THROUGH SIMULATED DROOP CONTROL WITH ELECTRIC LOADS

BATTELLE MEMORIAL INSTITU...

1. A frequency control system providing frequency control for an a.c. electrical power grid operating at an electrical frequency using a fleet of electrical loads powered by the electrical power grid, the frequency control system comprising:a system controller comprising an electronic data processing device programmed to assign load-specific threshold frequencies to electrical loads of the fleet of electrical loads, and to assign load-specific threshold frequencies to electrical loads of the fleet of electrical loads based on State of Charge (SOC) values for the electrical loads that measure energy stored in the electrical loads; and
load controllers controlling the electrical loads of the fleet of electrical loads, wherein each load controller comprises a microprocessor or microcontroller programmed to perform load monitoring and control operations for a controlled electrical load of the fleet of electrical loads including (i) comparing a measurement of the electrical frequency with the threshold frequency assigned to the controlled electrical load and (ii) operating the controlled electrical load based on the comparison.

US Pat. No. 10,116,135

METHOD AND APPARATUS FOR VOLTAGE CONTROL IN ELECTRIC POWER SYSTEMS

1. A method of controlling voltage of an electric power system, comprising: providing a system having:a high level substation; a low level substation connected to loads through step transformers; a voltage control module for each substation including a high voltage control module, a low voltage control module, on load tap controllers (OLTC), and turbo generators equipped with automatic voltage regulators; and a reactive power controller comprising a mega-volt-ampere reactive (VAR) export/import control module;
determining the operating mode of the voltage control module based on an actual power network configuration across the high level substation and the low level substation;
calculating a proportional-integral-derivative response of the high voltage control module from a deviation of a voltage variable of the high voltage control module to manipulate set points of the automatic voltage regulators; counteracting potentially destabilizing interactions between the high voltage control module and the low voltage control module by calculating a set point correction coefficient and sending the set point correction coefficient to the low level voltage control module; and controlling the low level voltage substation with a voltage control function;
wherein the set points for the automatic voltage regulators connected to the high level substation are determined by: sensing a high level voltage for the high level substation;
defining a first primary process control variable by constructing a function to calculate average high level bus voltage;
using the primary process control variable to calculate a primary control output of the automatic voltage regulators; defining a second primary process control variable for the export/import control module; defining set points for the export/import control module;
using the second primary process variable and the set points for the export/import control module to calculate a secondary control output of the automatic voltage regulators; and
adding the primary control output and the secondary control output to obtain set points for the automatic voltage regulators.

US Pat. No. 10,116,132

DEVICE FOR EFFICIENT DIRECT CURRENT INTERRUPTION

LSIS CO., LTD., Anyang-s...

1. A direct current (DC) circuit breaker comprising:a first line in which a first high-speed switch and a power semiconductor switch are connected in series;
at least one second line, each of the at least one second line including a plurality of second high-speed switches, a plurality of pairs and a resistor which are connected in series, each of the pairs including a first non-linear resistor and a power fuse connected in parallel with the first non-linear resistor;
a third line including a second non-linear resistor;
a current measuring unit disposed before the first line, the second line, and the third line which are connected in parallel; and
a fast fault detector (FFD) connected to the current measuring unit and configured to transmit an opening signal to the first high-speed switch and the second high-speed switches and the power semiconductor switch,
wherein at least one of the plurality of second high-speed switches are disposed in one end of the pairs, and the other at least one of the plurality of second high-speed switches are disposed in the other end of the pairs,
wherein, in a fault-current interruption mode, the fast fault detector is configured to output a switching control signal such that the first high-speed switch and the second high-speed switch are opened first, and then the power semiconductor switch is opened after a first predetermined time period, and
wherein, when the power semiconductor switch is opened and a second predetermined time period has elapsed, a fault-current is directed to flow to the third line.

US Pat. No. 10,116,130

DISTRIBUTION BOARD, POWER CONSUMPTION MANAGING SYSTEM, AND METHODS FOR MANUFACTURING DISTRIBUTION BOARD AND POWER CONSUMPTION MANAGING SYSTEM

NEC CORPORATION, Tokyo (...

1. A distribution board comprising:a main bar that is connected to a power supply line;
a branch bar that is branched from the main bar, the branch bar supplying power to a load;
a breaker that is electrically connected to the branch bar, the breaker being configured to be electrically connected to the load, the breaker limiting to a predetermined set value a current to be supplied to the load; and
a display unit that is provided to the branched bar or the breaker, the display unit indicating a designation of the load that is planned to be connected to the breaker.

US Pat. No. 10,116,128

UNIVERSAL WALL BOX THREAD REPAIR CLIP

1. A universal wall box thread repair clip, comprising:a front portion having at least a first opening and a second opening that are each sized to threadably engage a wall box screw;
an outer support portion extending from a first side of the front portion and configured to bear against an outer surface of a wall box;
at least one retention leg extending from a second side of the front portion, the second side being opposite the first side of the front portion and having a tooth formed at a distal end of the at least one retention leg; and
wherein the first opening of the front portion is configured to align with a screw hole in a wall box of a first type when the at least one retention leg is engaged with features of the wall box of the first type, and wherein the second opening of the front portion is configured to align with a screw hole in a wall box of a second type when the at least one retention leg is engaged with features of the wall box of the second type, and wherein the features of the wall box of the first type are different than the features of the wall box of the second type.

US Pat. No. 10,116,127

JUNCTION BOXES WITH WRAP-AROUND COMPARTMENTS

Elemental LED, Inc., Ren...

1. A junction box, comprising:a base having a bottom and a sidewall arising from the bottom;
a driver cap, the driver cap having
a top,
sidewalls depending from the top, and
partition portions extending outwardly from the sidewalls, the partition portions being arranged so as to extend to the sidewall of the base and thereby divide the base into at least two compartments that wrap around the driver cap; and
a cover sized and adapted to engage the base and to form a closed enclosure with the base.

US Pat. No. 10,116,124

ION GENERATOR AND METHOD OF MANUFACTURING THE SAME

LG ELECTRONICS INC., Seo...

7. An ion generator, comprising an ion generating module, a high voltage generator applying a high voltage to the ion generating module, and a housing in which the ion generating module and the high voltage generator are installed, wherein the ion generating module comprises: a plastic plate; a copper discharge electrode formed on a first surface of the plastic plate, the copper discharge electrode having at least one discharge needle; a ground electrode formed on an opposite surface of the plastic plate; and a metal coating layer coated on the copper discharge electrode, and wherein the high voltage generator comprises a printed circuit board, a winding-type transformer formed on the printed circuit board, and a transformer housing formed on the printed circuit board and surrounding the winding-type transformer.

US Pat. No. 10,116,123

INSPECTION METHOD AND APPARATUS OF SPARK PLUG INSULATOR

NGK SPARK PLUG CO., LTD.,...

1. An inspection method of an insulator for a spark plug, the insulator having an axial hole formed therethrough in a direction of an axis of the insulator and including a collar portion, a rear body portion located in rear of the collar portion and made smaller in diameter than the collar portion and a leg portion located in front of the collar portion and made smaller in diameter than the collar portion, the inspection method comprising:setting a point in the direction of the axis on the leg portion as a first measurement point and setting a point in the direction of the axis on any portion of the insulator other than the leg portion as a second measurement point;
performing measurement of a distance in a radial direction of the insulator between an outer circumferential surface of the leg portion at the first measurement point and an outer circumferential surface of the any portion of the insulator other than the leg portion at the second measurement point;
causing rotation of the insulator about the axis in a state that at least one of the collar portion and the rear body portion of the insulator is held with a holding member, wherein the measurement is performed at a plurality of positions in a circumferential direction of the insulator, with no contact to the leg portion and the any portion of the insulator other than the leg portion, by changing the position of the measurement in accordance with the rotation of the insulator;
determining, as a circular runout, a difference between maximum and minimum values among results of the measurement of the distance at the plurality of positions; and
making pass/fail judgment of the insulator based on the determined circular runout.

US Pat. No. 10,116,121

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A method of manufacturing a semiconductor device, comprising:a step of forming, on a semiconductor substrate, a mesa stripe including an active layer, and a semiconductor layer covering the mesa stripe;
a masking step of forming, on the semiconductor layer, a mask pattern through which the semiconductor layer is exposed on opposite sides of the mesa stripe;
an isotropic etching step of performing isotropic etching on the semiconductor layer exposed through the mask pattern so that concaves having a circular-arc sectional shape are formed in the semiconductor layer;
an anisotropic etching step of performing anisotropic etching on the semiconductor layer through the mask pattern after the isotropic etching step so that etching progresses to the semiconductor substrate; and
a step of separating the semiconductor substrate into chips after the anisotropic etching step, wherein
the steps of isotropic etching and anisotropic etching form trenches through the semiconductor layer such that bottom surfaces of the trenches are concaves having a circular-arc sectional shape and side surfaces of the trenches are perpendicular to the semiconductor substrate, and
the circular-arc sectional shape of the bottom surfaces of the trenches inhibits splitting of the semiconductor substrate from a point on peripheries of the trenches during the step of separating the semiconductor substrate into chips.

US Pat. No. 10,116,120

SEMICONDUCTOR MULTILAYER FILM MIRROR, VERTICAL CAVITY TYPE LIGHT-EMITTING ELEMENT USING THE MIRROR, AND METHODS FOR MANUFACTURING THE MIRROR AND THE ELEMENT

STANLEY ELECTRIC CO., LTD...

1. A semiconductor multilayer film mirror comprising:a plurality of pairs of an InAlN-based semiconductor film and a GaN-based semiconductor film, where each pair of the InAlN-based semiconductor film and the GaN-based semiconductor film is layered in a cyclic fashion, the InAlN-based semiconductor film having an In composition of less than 18 at %; and
a thin GaN cap layer formed on the InAlN-based semiconductor film and an AlGaN layer formed on the thin GaN cap layer, between each pair of the InAlN-based semiconductor film and the GaN-based semiconductor film.

US Pat. No. 10,116,119

COMPACT LASER DEVICE

KONINKLIJKE PHILIPS N.V.,...

1. A laser device, comprising:between two and four mesas provided on one semiconductor chip and electrically connected in parallel with each; and
a driver configured to electrically drive the mesas,
wherein the driver is configured to provide a defined threshold voltage to the between two to four mesas, and the between two to four mesas are configured so that in response to receiving the defined threshold voltage they emit laser light at the same time as each other, and
wherein each mesas has an active diameter between 7 ?m and 9 ?m,
wherein the semiconductor chip has a side length of less than 150 ?m, and
wherein the laser device is adapted to emit laser light with an optional power, wherein the optical power linearly depends on the provided electrical current when driven at an electrical current between 3 mA and 12 mA.

US Pat. No. 10,116,118

OPTICAL TRANSMITTER AND SEMICONDUCTOR LASER TEMPERATURE CONTROL METHOD

Mitsubishi Electric Corpo...

1. An optical transmitter comprising:a semiconductor laser;
a thermoelement connected with said semiconductor laser, to heat or cool said semiconductor laser with heat generated or cooled by a current;
a thermistor to detect temperature of said semiconductor laser via said thermoelement;
a laser drive circuit to drive said semiconductor laser;
a thermoelement driving circuit to acquire information about the temperature from said thermistor, receive a set value, and control a current flowing through said thermoelement in such a way that the information about the temperature detected by said thermistor becomes equal to the set value; and
a controller to receive monitor current information from the semiconductor laser, temperature information from the thermistor, and laser driving current information from the laser drive circuit,
wherein when a monitor temperature based on the temperature information from the thermistor has become higher than or equal to a preset first threshold on a high temperature side of a temperature threshold of the set value, the controller raises the set value in such a way that the set value becomes equal to the temperature detected by the thermistor or in such a way that a temperature by which the semiconductor laser needs to be cooled by the thermoelement reached a preset second threshold,
when a laser driving current based on the laser driving current information has become larger than or equal to a preset third threshold due to an increase in the set value, the controller corrects the set value so as to lower the set value,
when optical output power based on the monitor current information has become larger than or equal to a preset fourth threshold, the controller corrects and varies the set value after the correction so as to lower the set value,
when the monitor temperature based on the temperature information from the thermistor has become lower than or equal to a preset fifth threshold on a low temperature side of a temperature threshold of the set value, the controller lowers the set value in such a way that the set value becomes equal to the temperature detected by the thermistor or in such a way that a temperature by which the semiconductor laser needs to be heated by the thermoelement reaches a preset sixth threshold, and
when the optical output power based on the monitor current information has become smaller than or equal to a preset seventh threshold do to a decrease in the set value, the controller corrects and varies the set value so as to raise the set value.

US Pat. No. 10,116,117

LD MODULE

FUJIKURA LTD., Tokyo (JP...

1. An LD module, comprising:a multi-mode laser diode, including an active layer, which emits a laser beam from an exit end surface;
a multi-mode fiber, including a core, whose entrance end surface the laser beam enters; and
an optical system provided between the multi-mode laser diode and the multi-mode fiber,
the optical system including:
a collimating lens configured to refract, within a plane parallel to the active layer, the laser beam which is divergent light emitted from the multi-mode laser diode so as to convert the laser beam into parallel light; and
a light-converging lens configured to convert, into convergent light, the parallel light which has exited the collimating lens,
the multi-mode laser diode having an emitter width greater than a diameter, of the core, in the entrance end surface of the multi-mode fiber,
the optical system being configured to converge the laser beam so that a diameter, of the laser beam, in the entrance end surface of the multi-mode fiber becomes smaller than the diameter, of the core, in the entrance end surface of the multi-mode fiber,
the multi-mode laser diode being configured so that a beam parameter product of the laser beam emitted from the multi-mode laser diode shows a local minimal value which changes in accordance with the emitter width of the multi-mode laser diode, the local minimal value being equal to or smaller than a beam parameter product of the multi-mode fiber,
the emitter width of the multi-mode laser diode being set so that the beam parameter product of the laser beam emitted from the multi-mode laser diode is equal to or smaller than the beam parameter product of the multi-mode fiber, the LD module further comprising:
a mirror configured to reflect and guide, to the multi-mode fiber, a laser beam emitted from the multi-mode laser diode,
the multi-mode fiber being provided so that a central axis of the multi-mode fiber is orthogonal to an optical axis of the laser beam emitted from the multi-mode laser diode.

US Pat. No. 10,116,113

PLANAR WAVEGUIDE LASER APPARATUS

Mitsubishi Electric Corpo...

1. A planar waveguide laser apparatus comprising:a planar waveguide comprising a core formed from a laser medium for absorbing pump light and claddings bonded to an upper surface and a lower surface of the core, each cladding having a smaller refractive index than the laser medium;
a pump light generation source for emitting the pump light to a side surface of the core; and
laser light reflection films formed on, out of four side surfaces of the core, two opposite side surfaces that are different from the side surface to which the pump light is emitted by the pump light generation source, wherein
a structure of at least one side surface of two opposite side surfaces, out of four side surfaces of the planar waveguide, that are different from the side surface to which the pump light is emitted by the pump light generation source, the at least one side surface including at least one cladding surface and a core surface, and the structure of the at least one side surface is a ridge structure in which a part of the at least one side surface is recessed.

US Pat. No. 10,116,111

METHOD AND DEVICE FOR FILAMENT-BASED WHITE LIGHT GENERATION

DEUTSCHES ELEKTRONEN-SYNC...

1. A method of generating white light pulses with a white light generation device, comprising the steps of:coupling pump laser pulses into a white light generation crystal,
generating the white light pulses by an optically non-linear conversion of the pump laser pulses in the white light generation crystal,
detecting at least one pulse characteristic of at least one of the pump laser pulses and the white light pulses, wherein the at least one pulse characteristic is capable of indicating a normal working range of the white light generation crystal; and
controlling the white light generation device using a control loop device by adjusting an axial focus position of the pump laser pulses along a propagation axis of a beam in the white light generation crystal in dependency on a deviation of the at least one pulse characteristic of the at least one pulse characteristic and at least one normal working range characteristic indicating the normal working range of the white light generation crystal.

US Pat. No. 10,116,110

ROTOR ARRANGEMENT FOR A SLIP RING ASSEMBLY AND ROTARY COUPLING ARRANGEMENT COMPRISING A ROTOR ARRANGEMENT OF THIS KIND

CARL ZEISS INDUSTRIELLE M...

1. A rotor arrangement for a slip ring assembly, said rotor arrangement comprising a shaft element and at least one contact ring, wherein the shaft element is at least partially in the form of a hollow shaft with a hollow interior and a casing wall, wherein the shaft element has a middle section, wherein each contact ring is arranged on the shaft element in the middle section, wherein the middle section has at least one cutout through the casing wall into the interior, wherein each contact ring is connected to a cable element which is guided through one of the at least one cutout into the interior, and wherein the shaft element has a first end section with an outer circumferential cross section for a rotationally fixed coupling, wherein the middle section is offset in relation to the first end section by a flange, wherein the flange has an outside diameter which is larger than a smallest outside diameter of the first end section and larger than an outside diameter of the middle section, wherein a smallest outside diameter of the first end section is larger than an outside diameter of the middle section, wherein the outer circumferential cross section of the first end section is in the form of a profile cross section, wherein the shaft element is of integral design, wherein the rotor arrangement has more than one contact ring, wherein an insulating ring which electrically insulates adjacent contact rings from one another is arranged between two adjacent contact rings in each case, and wherein a further electrically insulating ring is arranged on the middle section adjacent the flange.

US Pat. No. 10,116,107

CONNECTOR PRODUCTION METHOD AND CONNECTOR

JAPAN AVIATION ELECTRONIC...

1. A connector production method comprising:holding a flat plate conductor with a first insulator;
joining central portions of one or more contacts to the first insulator such that front end portions of the one or more contacts are exposed at a front part of the first insulator and rear end portions of the one or more contacts project from a rear part of the first insulator;
placing a shell made of metal over the first insulator such that the shell covers outer peripheral portions of the one or more contacts;
fixing and electrically connecting the shell to the flat plate conductor; and
forming a second insulator such that the second insulator closes the rear part of the first insulator and a rear part of the shell while the rear end portions of the one or more contacts project from the second insulator.

US Pat. No. 10,116,106

CUSHION-MOUNTED ELECTRICAL OUTLETS

1. A cushion-mountable electrical outlet system for furniture, said electrical outlet system comprising:a generally flat body having a proximal end portion configured to be positioned between a cushion and a panel of a furniture article that is proximate the cushion, said flat body having an upright distal end portion configured to be positioned alongside an upright side edge of the cushion, and said flat body having a deformable region below said upright distal end portion;
an electrical outlet assembly mounted at said distal end portion of said flat body and positionable so as to be accessible to a user supported at the cushion;
an electrical outlet mounted at said electrical outlet assembly and facing generally upwardly; and
an electrical cord in electrical communication with said electrical outlet and exiting said electrical outlet assembly.

US Pat. No. 10,116,105

ILLUMINATED PRINTED CIRCUIT BOARDS FOR CONNECTORS

Apple Inc., Cupertino, C...

1. A tongue of an electrical connector, the tongue comprising:a light-emitting diode;
a first plurality of contacts on a top side of the tongue, each to form an electrical connection with a corresponding contact of a corresponding connector when the corresponding connector and the electrical connector are mated; and
a second plurality of contacts on a bottom side of the tongue, each to form an electrical connection with a corresponding contact of the corresponding connector when the corresponding connector and the electrical connector are mated,
wherein the tongue forms a light guide from the light-emitting diode to a front edge of the tongue such that light provided by the light-emitting diode passes below the first plurality of contacts and above the second plurality of contacts, the light exiting through the front edge of the tongue,
wherein the tongue is arranged to fit in an opening in the corresponding connector when the corresponding connector and the electrical connector are mated, and
wherein the light-emitting diode is located on the tongue.

US Pat. No. 10,116,103

POWER CONNECTOR WITH INTEGRATED DISCONNECT

1. A connector comprising:a. a first half and a second half,
b. a first axis for the first half,
c. a second axis defined for the second half,
d. the first half being able to mate with the second half, and transmit a first group of n electrical signals across from the first half to the second half, and then to a second group of n electrical signals, when the first and the second axis are parallel, but separated by no more than a distance M, where n?1,
e. a first contact, attached to the first half and with its largest dimension perpendicular to the first axis as D, and mounted along the first axis,
f. a second contact, attached to the second half and with its largest dimension perpendicular to the second axis as d, and mounted along the second axis,
g. with (D+d)/2 h. a first electrical energy source having a first and a second terminal, with its first terminal connected to the first contact,
i. a first form-A relay with a first and second switching terminal, and with an energizing coil having a third and fourth terminal,
j. the third terminal of the first relay, connected to the second contact,
k. the second terminal of the first relay, connected to one of the electrical signals from the first group of n signals.

US Pat. No. 10,116,101

CABLE CONNECTOR ASSEMBLY HAVING A THERMISTOR AFFIXED TO A PROTECTIVE COVER AND METHOD OF MAKING THE CABLE CONNECTOR ASSEMBLY

FOXCONN INTERCONNECT TECH...

1. A cable connector assembly comprising:a mating unit;
a cable;
a printed circuit board (PCB) interconnected between the mating unit and the cable;
a protective cover and a thermistor affixed to the protective cover, the protective cover and the thermistor being mounted on the PCB;
a metal shell enclosing the PCB, a rear of the mating unit, and a front of the cable;
an insulative inner cover over-molding the PCB, the metal shell, the rear of the mating unit, and the front of the cable; and
an insulative outer cover over-molding the insulative inner cover; wherein
the thermistor is installed in series with a circuit and used to protect against overcurrent conditions; the thermistor is adhered to the protective cover, thereby permitting any expansion of the thermistor; wherein
the metal shell includes a first shell part and a second shell part fastened together; the first shell part and the second shell parts include main portions having extended arms to wrap around the mating unit, side portions cooperating with the main portions to surround the PCB, and linking portions extending from the corresponding side portions or main portions to fastening portions crimping the cable.

US Pat. No. 10,116,098

ELECTRICAL CONNECTOR HAVING A SHIELDING SHELL AND A METALLIC FRAME EXTENDING REARWARD BEYOND THE SHIELDING SHELL TO SHIELD EXPOSED CONTACT TAILS

FOXCONN INTERCONNECT TECH...

1. An electrical connector comprising:a metallic frame having a main part, a board at a rear of the main part, and an upper shield behind the board;
an upper and lower contact modules arranged at two opposite sides of the metallic frame main part, each contact module having a row of contacts, each contact having a contacting portion, an intermediate portion, and a tail;
an insulator molded to the metallic frame and the contact modules to complete an insulative housing, the insulative housing having a base and a tongue, the tongue exposing respective contacting portions of the upper and lower contact modules to two opposite surfaces thereof;
a shielding shell accommodating the board of the metallic frame and enclosing the insulative housing, the contact tails of at least one of the upper and lower contact modules extending rearward beyond a rear end of the shielding shell; wherein
the upper shield of the metallic frame shields the contact tails of the at least one contact module.

US Pat. No. 10,116,097

SHIELD TERMINAL AND OUTER CONDUCTOR TERMINAL

Sumitomo Wiring Systems, ...

1. A shield terminal, comprising:an inner conductor terminal;
a dielectric configured to accommodate the inner conductor terminal;
an outer conductor terminal configured to surround the dielectric;
a tubular fitting formed in a front end part of the outer conductor terminal in an axial direction;
a resilient contact having a rear end in the axial direction integrally connected to the tubular fitting; and
an interlocking region connected to the front end of the resilient contact and to areas of the tubular fitting offset circumferentially from the resilient contact so that the interlocking region is radially resiliently deflectable with a front end thereof being a free end, wherein
the tubular fitting is formed with a non-interlocking region offset from the resilient contact in a circumferential direction and spaced from the interlocking region in the circumferential direction by a slit.

US Pat. No. 10,116,096

INTERCONNECT SYSTEM WITH FRICTION FIT BACKSHELL

1. An interconnect system, comprising:a connector, the connector comprises a threaded distal coupling portion;
an adapter ring, the adapter ring comprises a threaded proximal coupling portion and a non-threaded distal coupling portion; and
a backshell, the backshell comprises a proximal coupling portion and a port;
wherein the threaded proximal coupling portion of the adapter ring and the threaded distal coupling portion of the connector are mechanically attached;
wherein the non-threaded distal coupling portion of the adapter ring is positioned within the proximal coupling portion of the backshell; and
wherein a wire bundle enters the backshell through the port, passes through the adapter ring, and terminates at the connector.

US Pat. No. 10,116,095

ELECTRICAL CONNECTOR WITH POSITION ASSURANCE DEVICE

Delphi Technologies, Inc....

1. An electrical connector, comprising;a first-housing having two parallel actuation-ribs extending from an outer-surface of the first-housing, said two parallel actuation-ribs aligned parallel to a longitudinal mating-axis of the electrical connector;
a second-housing configured to mate with the first-housing, said second-housing includes two opposing lugs projecting from a top-surface of the second-housing; and
a connector-position-assurance (CPA) device, said CPA device slideably mounted to the second-housing and moveable along the longitudinal mating-axis from a pre-stage-position to a latched-position, said CPA device includes two parallel latching-arms that engage the two opposing lugs at distal-ends of the two parallel latching-arms such that a movement of the CPA device is inhibited in the pre-stage-position, wherein the two parallel latching-arms are in a relaxed-state when in said pre-stage-position, wherein the two parallel actuation-ribs of the first-housing move beyond the two opposing lugs of the second-housing and disengage the two parallel latching-arms from the two opposing lugs by flexing the two parallel latching-arms into a stressed-state when the first-housing is mated with the second-housing, thereby enabling the CPA device to be moved from the pre-stage-position to the latched-position, and wherein the two parallel latching-arms return to the relaxed-state when in the CPA device is in the latched-position, wherein the CPA device further includes locking-ribs extending from an upper-surface of the CPA device, wherein the locking-ribs are configured to inhibit an actuation of an axial connector-lock when the CPA device is in the latched-position.

US Pat. No. 10,116,093

CONNECTOR DEVICE

Sumitomo Wiring Systems, ...

1. A connector device comprising:a motor case including a mounting hole;
a motor-side connector mounted in the mounting hole of the motor case and fixed to the motor case, the motor-side connector including a motor-side terminal;
an inverter case including a roof wall having opposite first and second surfaces and a support hole penetrating through the roof wall, the support hole including a small cross-section part adjacent the first surface and a large cross-section part adjacent the second surface, the large cross-section part having a specified depth from the second surface;
an inverter-side connector having an inverter-side terminal and a flange circumferentially provided on an outer surface of the inverter-side connector, the inverter side connector being mounted in the support hole of the inverter case with the flange mounted in the large cross-section part of the support hole; and
a bracket mounted to the second surface of the roof wall of the inverter case, the bracket having a lock hole surrounding a part of the inverter-side connector projecting from the second surface of the roof wall,
wherein:
the inverter case is configured to be coupled with the motor case so that the motor-side connector and the inverter-side connector are fit to each other,
the flange has a uniform thickness substantially equal to the depth of the large cross-section part of the support hole in the inverter case,
the lock hole of the bracket is smaller than an outer diameter of the flange of the inverter-side connector and larger than an outer cross-section of the part of the inverter-side connector surrounded by the lock hole, and
the flange is cross-sectionally larger than the small cross-section part of the support hole and smaller than the large cross-section part of the support hole so that the inverter-side connector is freely radially movable in the large cross-section part of the support hole without being separable from the support hole.

US Pat. No. 10,116,076

CPU RETAINER MOUNTED UPON PCB

FOXCONN INTERCONNECT TECH...

1. An electrical connector assembly comprising:a printed circuit board defining a front-to-back direction and a transverse direction perpendicular to each other;
an insulative housing mounding upon the printed circuit board and defining a loading cavity therein;
a plurality of contacts disposed in the housing;
a fixing seat mounted upon the printed circuit board by one end of the housing in said front-to-back direction;
a one piece clip mounted upon the printed circuit board by the other end of the housing in said front-to-back direction; and
a load plate and a lever commonly secured to the fixing seat in a rotatable manner; wherein
said clip includes a holding section forming a holding cavity for holding an electronic package therein, and said holding section is moveable between an upstanding position and a horizontal position; wherein
the electronic package is disposed in the loading cavity when said clip is moved to the horizontal position.

US Pat. No. 10,116,052

TUNABLE ANTENNA FOR HIGH-EFFICIENCY, WIDEBAND FREQUENCY COVERAGE

SEMICONDUCTOR COMPONENTS ...

1. A system, comprising:a processor;
a transceiver coupled to the processor; and
an antenna including a central element that connects to one or more of the processor and the transceiver, said antenna further including multiple coupling elements that electromagnetically couple directly to the central element,
wherein each of the multiple coupling elements comprises a separate variable capacitor,
wherein the central element includes a first portion having a first length direction and a second portion having a second length direction, the first length direction extending alongside the second length direction, and a third potion having a length direction that intersects the first length direction and the second length direction;
wherein a first of the multiple coupling elements is arranged in the antenna adjacent to the first and third portions of the central element, and
wherein a second of the multiple coupling elements is arranged in the antenna adjacent to at least the second portion of the central element.

US Pat. No. 10,116,048

ANTENNA WITH ROTATABLE RADIATING ELEMENT

KATHREIN-WERKE KG, Rosen...

1. A telecommunications antenna with a housing comprising a radome and a radiator arranged in the housing, wherein the radiator is mounted on an electroconductive support structure, wherein the electroconductive support structure engages the housing in either one of a rotatable fashion or in a rotatably fixed fashion about an axis through at least one non-electroconductive body and is tensionable in a direction parallel to the axis so that a transition from the rotatable fashion to the rotatably fixed fashion is effected by forming a frictional engagement,wherein the non-electroconductive body is a clamping body and
wherein the non-electroconductive body is tensionable by a fastener engaging in a non-electroconductive bracket section.

US Pat. No. 10,116,047

ANTENNA DEVICE AND COMMUNICATION DEVICE

AMBIT MICROSYSTEMS (SHANG...

1. An antenna device, comprising:a first antenna, wherein the first antenna is disposed in a PCB to radiate signals;
a second antenna, wherein the second antenna is disposed in the PCB to radiate the signals;
wherein the first antenna comprises:
a first ground portion;
a first short portion, wherein the first short portion and the first ground portion are electrically coupled together to form a first storage space, the first storage space has a first notch; and
a first feeding part, wherein the first feeding part is disposed in the first storage space, the first feeding part and the first short portion are not contacted through any metallic conductors, the first feeding part and the first ground portion are not contacted through any metallic conductors.

US Pat. No. 10,116,034

TWIN AXIAL CABLE STRUCTURES FOR TRANSMITTING SIGNALS

Mellanox Technologies, Lt...

1. A method of manufacturing a cable structure for transmitting a differential signal comprising:cutting a pair of open channels through an outer longitudinal surface of a ribbon of material to form an insulative body portion, wherein the channels are parallel to each other and extend a length of the insulative body portion;
inserting within each open channel of the pair of open channels a conductive wire, wherein the conductive wires of the pair of open channels form a pair of conductive wires configured to collectively transmit a differential signal;
disposing a conductive sheet on the insulative body portion, wherein the conductive sheet is configured to shield the pair of conductive wires; and
placing a grounding element in contact with the conductive sheet, wherein the grounding element is configured to conduct electric current away from the conductive sheet.

US Pat. No. 10,116,032

DIELECTRIC RESONATOR, DIELECTRIC FILTER, AND COMMUNICATION APPARATUS

KYOCERA CORPORATION, Kyo...

1. A dielectric resonator, comprising:a dielectric body having a first surface located at an end in a first direction thereof and a second surface which is located at an end in a second direction opposite to the first direction thereof;
a first conductor having a cavity formed therein in which the dielectric body is housed, the first conductor being disposed so as to surround the dielectric body leaving space therefrom, and having a first inner surface including a part opposed to the first surface, and a second inner surface including a part opposed to the second surface;
a second conductor disposed on the first surface, an end in the first direction thereof being electrically connected to the first inner surface;
a third conductor disposed on the second surface, an end in the second direction thereof being electrically connected to the second inner surface;
a fourth conductor disposed between the second conductor and the first conductor in a third direction perpendicular to the first direction, an end in the first direction thereof and an end in the third direction thereof being electrically connected to the first conductor, an end in a direction opposite to the third direction thereof being electrically connected to the second conductor; and
a fifth conductor disposed between the third conductor and the first conductor in a fourth direction perpendicular to the first direction, an end in the fourth direction thereof and an end in the second direction thereof being electrically connected to the first conductor, an end in a direction opposite to the fourth direction thereof being electrically connected to the third conductor.

US Pat. No. 10,115,978

PROTECTIVE EDGE SEAL HAVING ALKALI METAL IONS FOR MEMBRANE ION EXCHANGE

Audi AG, Ingolstadt (DE)...

1. A fuel cell comprising:an anode;
a cathode;
a membrane positioned between the anode and the cathode, the membrane having a peripheral edge region; and
an edge seal including a first plurality of alkali metal ions, the edge seal in contact with the peripheral edge region of the membrane, the peripheral edge region including a second plurality of alkali metal ions from the edge seal;
wherein the membrane includes hydrogen ions coupled with the membrane by proton-sulfonic coupling and an alkali-sulfonic coupling of the alkali metal ions with the membrane is stronger than the proton-sulfonic coupling of the hydrogen ions with the membrane.

US Pat. No. 10,115,970

SEMI-SOLID ELECTRODES WITH POROUS CURRENT COLLECTORS AND METHODS OF MANUFACTURE

24M Technologies, Inc., ...

1. An electrode, comprising:a first porous substrate defining a first pitch and a second porous substrate defining a second pitch stacked together to form a current collector; and
a semi-solid electrode material embedded in the first and second porous substrates, the semi-solid electrode material including a suspension of an active material and a conductive material in a non-aqueous liquid electrolyte,
whereby the stacking of the first porous substrate and the second porous substrate reduces an internal resistance of an electrochemical cell including the electrode.

US Pat. No. 10,115,954

BATTERY MODULE

SAMSUNG SDI CO., LTD., Y...

1. A battery module, comprising:a plurality of battery cells arranged in a first direction, each one of the plurality of battery cells having a terminal portion on an upper surface thereof;
a bus-bar holder positioned on the plurality of battery cells, the bus-bar holder having an opening exposing terminal portions of the plurality of battery cells;
a bus-bar including a bending portion protruding upward and a flat portion contacting the terminal portions of the plurality of battery cells, the bus-bar positioned in the opening of the bus-bar holder, the bus-bar being spaced apart from a circumference of the opening of the bus-bar holder by a predetermined interval, and the bus-bar electrically connecting terminal portions of adjacent battery cells among the plurality of battery cells;
a guide wall extending along the opening in the first direction, the guide wall extending upward above the opening; and
a fixing member on an inner side of the guide wall, the fixing member being at the bending portion of the bus-bar and pressing the bending portion toward the terminal portions of the plurality of battery cells; and
an insulating member between adjacent flat portions of adjacent bus-bars, wherein
the insulating member includes a gas exhausting portion, a height of the gas exhausting portion being lower than that of another area of the insulating member, the gas exhausting portion being between bending portions of the adjacent bus-bars and extending to parallel the bending portions of the adjacent bus-bars.

US Pat. No. 10,115,932

METHOD OF DESIGNING ELECTROLUMINESCENT DEVICE, ELECTROLUMINESCENT DEVICE MANUFACTURED WITH THE DESIGN METHOD, AND METHOD OF MANUFACTURING ELECTROLUMINESCENT DEVICE WITH THE DESIGN METHOD

KONICA MINOLTA, INC., To...

1. A method of designing an electroluminescent device having an emissive layer between a first electrode and a second electrode, the first electrode being a transparent electrode, the emissive layer lying between a first functional layer and a second functional layer, the electroluminescent device having a first transparent member on a side of the first electrode opposite to a side where the emissive layer is provided, the method comprising:preparing a reference device including a construction of the electroluminescent device and a desired analyzed device including a construction of the electroluminescent device;
performing quantum optical analysis, electromagnetic analysis, and ray trace with thicknesses and complex relative permittivities of the first transparent member, the first electrode, the first functional layer, the second functional layer, the emissive layer, and the second electrode as well as a position of a light-emitting point in the emissive layer and a distribution of light-emitting points in the emissive layer being used as design variables;
calculating a “ratio of light extraction efficiency” between the reference device and the analyzed device by computing efficiency of light extraction from the emissive layer into the transparent member or air in both of the reference device and the analyzed device;
finding relation of the thickness and the complex relative permittivity of each of the layers with the “ratio of light extraction efficiency,” the layers forming the reference device and the analyzed device; and
obtaining the respective thicknesses and the respective complex relative permittivities of the first transparent member, the first electrode, the first functional layer, the second functional layer, the emissive layer, and the second electrode as the design variables, based on the relation and an electroluminescence spectrum in air or the first transparent member measured by feeding a current to the reference device.

US Pat. No. 10,115,894

APPARATUS AND METHODS FOR ELECTRICAL SWITCHING

MASSACHUSETTS INSTITUTE O...

1. An apparatus for electrical switching, the apparatus comprising:a crystalline layer having a first side and a second side opposite the first side, the crystalline layer having at least one channel extending from the first side to the second side;
a first electrode disposed on the first side of the crystalline layer, the first electrode having a first solid solubility less than 1% in the crystalline layer; and
a second electrode disposed on the second side of the crystalline layer, the second electrode having a second solid solubility less than 1% in the crystalline layer,
wherein the first electrode comprises an active material to provide at least one metal ion migrating along the at least one channel in response to a first voltage applied across the first electrode and the second electrode.

US Pat. No. 10,115,873

SURFACE-MODIFIED PHOSPHOR AND LIGHT EMITTING DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A surface-modified phosphor comprising:a phosphor matrix comprising
a compound represented by Chemical Formula 1
K2SiF6:Mn4+; and  Chemical Formula 1
a nano-sized phosphor disposed on the phosphor matrix,
wherein the phosphor matrix has a crack, and wherein the crack is filled with the nano-sized phosphor, and
wherein the nano-sized phosphor comprises at least a compound represented by any one of Chemical Formulas 2 and 3,
Li2TiO3:Mn4+, and  Chemical Formula 2
CaAlSiN:Eu2+.  Chemical Formula 3

US Pat. No. 10,115,872

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

TOYODA GOSEI CO., LTD., ...

1. A light emitting device, comprising:a first light emitting element that outputs a first emitted light having a first peak wavelength;
a second light emitting element that outputs a second emitted light having a second peak wavelength; and
a phosphor layer including a plurality of phosphors, which is disposed on the first and second light emitting elements,
wherein the phosphor layer receives the first and second emitted light and outputs a plurality of emitted light based on the plurality of phosphors so as to form a first synthesized emission spectrum that is distributed at a longer wavelength side than the first peak wavelength of the first emitted light and includes an emission spectrum formed by the first and second emitted light, and
wherein the second light emitting element comprises an emission spectrum to reduce a depth of a deepest dip of at least one dip in a second synthesized emission spectrum that is formed by removing an emission spectrum of the second emitted light from the first synthesized emission spectrum.

US Pat. No. 10,115,870

LIGHT EMITTING DEVICE, RESIN PACKAGE, RESIN-MOLDED BODY, AND METHODS FOR MANUFACTURING LIGHT EMITTING DEVICE, RESIN PACKAGE AND RESIN-MOLDED BODY

NICHIA CORPORATION, Anan...

1. A method of manufacturing a plurality of light emitting devices, each comprising a resin package that includes a first lead, a second lead and a resin part, and a light emitting element mounted on the resin package, each resin package including a first outer side surface and a second outer side surface opposing the first outer side surface, the method comprising:providing a structure comprising:
a lead frame including first portions to become the first leads, and second portions to become the second leads, and
a resin-molded body,
wherein the structure includes a plurality of areas, each of which will become one of the resin packages, and each of which has a first outer side corresponding to the first outer side surface of the corresponding resin package, and a second outer side opposing the first outer side and corresponding to the second outer side surface of the corresponding resin package,
wherein each area of said structure has a concave portion on its upper side,
wherein the lead frame is exposed from the resin-molded body at a bottom face of each concave portion, such that a part of one of the first portions and a part of one of the second portions of the lead frame are located at each respective bottom face, separated by a portion of the resin-molded body,
wherein the lead frame has a plurality of first notch parts in which a portion of the resin-molded body is disposed,
wherein, in each area, a respective one of the first notch parts is located between said first portion to become the first lead and said second portion to become the second lead, and extends from the first outer side of said area to the second outer side of said area, and
wherein, in each area, in a plane of an uppermost surface of the lead frame, a width of each first notch part at the first and second outer sides is wider than a width of the first notch part within the bottom face of the concave portion in a direction along the first and second outer sides;
mounting light emitting elements on the bottom faces of the concave portions; and
cutting said structure so as to expose the portion of the resin-molded body disposed in each first notch part, to thereby obtain a plurality of light emitting devices in each of which both the first lead and the second lead are exposed from the resin part and substantially coplanar with a portion of the resin part disposed in the first notch part at each of the first and second outer side surfaces.

US Pat. No. 10,115,866

LIGHT EMITTING DEVICE AND PROJECTOR

Seiko Epson Corporation, ...

1. A light emitting device comprising:a laminated body having an active layer capable of producing light when current is injected thereinto and a first cladding layer and a second cladding layer that sandwich the active layer; and
a first electrode and a second electrode that inject current into the active layer,
wherein the second cladding layer has a ridge section thicker than another portion of the second cladding layer,
the active layer forms an optical waveguide that guides light,
the optical waveguide has a first light exiting surface and a second light exiting surface through which the light exits,
the optical waveguide extends in a direction inclined with respect to a normal to the first light exiting surface and a normal to the second light exiting surface,
the laminated body has a connection area that overlaps with the ridge section when viewed in a direction in which the active layer is laminated on the first cladding layer and is connected to the second electrode,
the ridge section has a first tapered section having a width that increases with distance from a center position that is equidistant from the first light exiting surface and the second light exiting surface toward the first light exiting surface when viewed from the laminated direction and a second tapered section having a width that increases from the center position toward the second light exiting surface when viewed from the laminated direction,
the connection area has a third tapered section having a width that increases from the center position toward the first light exiting surface when viewed from the laminated direction and a fourth tapered section having a width that increases from the center position toward the second light exiting surface when viewed from the laminated direction,
an angle of outer edges of the connection area that specify the width of the third tapered section with respect to a center line of the optical waveguide is greater than an angle of outer edges of the ridge section that specify the width of the first tapered section with respect to the center line when viewed from the laminated direction, and
an angle of outer edges of the connection area that specify the width of the fourth tapered section with respect to the center line is greater than an angle of outer edges of the ridge section that specify the width of the second tapered section with respect to the center line when viewed from the laminated direction.

US Pat. No. 10,115,865

HIGH-PERFORMANCE LED FABRICATION

Soraa, Inc., Fremont, CA...

1. An LED package comprising:a ceramic substrate having a substrate top surface;
a plurality of traces overlaying said substrate top surface;
a plurality of contacts, each contact being electrically connected to one of said traces;
a reflective material disposed over at least a portion of said traces, said reflective material not extending above said plurality of contacts; and
a flip-chip LED die having LED contacts said LED contacts contacting said plurality of contacts.

US Pat. No. 10,115,864

OPTOELECTRONIC DEVICE WITH LIGHT-EMITTING DIODES AND AN IMPROVED RADIATION PATTERN

Aledia, Grenoble (FR)

1. An optoelectronic device comprising:a support comprising a conductive layer;
an electrode,
wherein the conductive layer comprises a portion having a concave or convex shape, and the electrode has a concave or convex shape, respectively; and
at least one light-emitting diode disposed between the portion and the electrode, wherein:
the at least one light-emitting diode comprises at least one cylindrical, conical or tapered semiconductor element in contact with a surface of the portion;
an amplitude of a deflection of the surface between the at least one semiconductor element and the portion is smaller than or equal to 0.5 ?m; and
an amplitude of a deflection of the portion is greater than 1/20th of a chord of the portion.

US Pat. No. 10,115,862

FLUIDIC ASSEMBLY TOP-CONTACT LED DISK

eLux Inc., Vancouver, WA...

1. A top-contact light emitting diode (LED) display, the display comprising:a transparent substrate with a top surface comprising a number of wells;
a top-contact LED formed in each of the number of wells, each LED comprising:
a lower disk comprising a material with a first dopant selected from a group consisting of: a p-dopant, and an n-dopant; the lower disk having a bottom surface and a top surface;
a multiple quantum well (MQW) disk overlying the lower disk top surface;
an upper disk comprising a material with a second dopant, wherein the second dopant is opposite the first dopant; the upper disk having a bottom surface overlying the MQW disk, a top surface and a first diameter;
an electrical insulator disk overlying the upper disk top surface, having a second diameter smaller than the first diameter such that at least a portion of a perimeter of the upper disk extending to an outer edge of the upper disk top surface remains uncovered by the electrical insulator disk; and, a via formed through the electrical insulator disk upper disk, and MQW disk, exposing a center contact region of the lower disk top surface.

US Pat. No. 10,115,861

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

XIAMEN SANAN OPTOELECTRON...

1. A light-emitting diode, comprising:an epitaxial-laminated layer, comprising from bottom to up:
an n-type ohmic contact layer;
a first n-type transition layer;
an n-type etching-stop layer;
a second n-type transition layer;
an n-type confinement layer;
an active layer;
a p-type confinement layer;
a p-type transition layer; and
a p-type window layer;
a p electrode over an upper surface of the p-type window layer;
a metal bonding layer over a bottom surface of the n-type ohmic contact layer, wherein: a portion corresponding to a position of the p electrode extends upwards and passes through the n-type ohmic contact layer and the first n-type transition layer, till the n-type etching-stop layer, thereby forming a current distribution adjustment structure such that injected current does not flow towards the epitaxial-laminated layer right below the p electrode; and
a conductive substrate located over a bottom surface of the metal bonding layer.

US Pat. No. 10,115,859

NITRIDE BASED DEVICES INCLUDING A SYMMETRICAL QUANTUM WELL ACTIVE LAYER HAVING A CENTRAL LOW BANDGAP DELTA-LAYER

Lehigh University, Bethl...

1. A III-nitride based semiconductor device comprising:a substrate;
a first barrier layer comprising a GaN-based material formed over said substrate;
a second barrier layer comprising a GaN-based material disposed over said first barrier layer; and
an InGaN-delta-InN quantum well active layer positioned between said first and second barrier layers, said quantum well active layer comprising:
an inner quantum well delta layer of an InN material, said inner quantum well delta layer having a thickness of approximately 6 ? or less, said first nitride-based material having a first bandgap characteristic; and
a pair of outer quantum well layers, each of said pair of outer quantum well layers being of an InGaN material having an Indium content in the range of about 15% to 35%, said pair of outer quantum well layers sandwiching said inner quantum well delta layer, each of said pair of outer quantum well layers having a respective thickness greater than said thickness of said inner quantum well delta layer and measuring approximately 15 ? to 30 ?;
wherein said InGaN-delta-InN quantum well active layer emits light in a wavelength range of about 500 nm to about 750 nm when the semiconductor device is energized.

US Pat. No. 10,115,858

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

1. A method of fabricating a light emitting diode, the method comprising:providing a substrate;
forming an N-type layer over the substrate;
forming an active layer over the N-type layer;
forming an electronic blocking layer over the active layer; and
forming a P-type layer over the electronic blocking layer, wherein:
the P-type layer comprises a Mg-doped GaN material layer having a Mg impurity concentration of about 2×1019-2×1020 cm?3; and
the P-type layer has a thickness of less than or equal to about 250 ?, and has a surface density of V-type defects of less than or equal to about 5×106 cm?2.

US Pat. No. 10,115,857

METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT OF POLYGON SHAPE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a semiconductor element, comprising:providing a semiconductor wafer including a substrate, a semiconductor structure on the substrate, and electrodes;
forming a cleavage starting portion in the semiconductor wafer, without dividing the semiconductor structure; and
dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer before separating the semiconductor structure, thereby the semiconductor wafer is separated at the cleavage starting portion, wherein
the pressing member includes a tip portion to be pressed on the semiconductor wafer,
the tip portion has a spherical surface, and
each of the plurality of semiconductor elements has a shape of a polygon having five or more angles in a plan view.

US Pat. No. 10,115,855

CONDUCTIVE FOIL BASED METALLIZATION OF SOLAR CELLS

SunPower Corporation, Sa...

1. A method of fabricating a solar cell, the method comprising:forming a first cut portion from a conductive foil;
aligning the first cut portion to a first doped region of a first semiconductor substrate, wherein the first cut portion is aligned substantially parallel to the first doped region, wherein aligning the first cut portion to the first doped region of the first semiconductor substrate comprises placing the first cut portion in an aligner having a plurality of slots; and
bonding the first cut portion to the first doped region.

US Pat. No. 10,115,854

METHOD FOR FORMING A VIRTUAL GERMANIUM SUBSTRATE USING A LASER

NewSouth Innovations Pty ...

1. A method for manufacturing a semiconductor device comprising the steps of:providing a substrate;
forming a germanium layer over the substrate, the germanium layer having a concentration of lattice defects;
depositing a dielectric layer onto the germanium layer; thereafter
exposing a region of the germanium layer to laser light through the dielectric layer; thereafter
removing the dielectric layer; and thereafter
forming at least one semiconductor device on a surface portion of the exposed region of the germanium layer comprising growing a plurality of layers comprising III-V compound materials on the formed germanium layer;
wherein the step of exposing the region of the germanium layer to laser light comprises: generating a continuous-wave laser beam and directing the continuous-wave laser beam towards a first edge of the germanium layer and laterally moving the laser beam along the length of the germanium layer from the first edge to a second edge.

US Pat. No. 10,115,851

SOLAR CELL HAVING A DIELECTRIC REAR FACE COATING AND METHOD FOR PRODUCING SAME

Centrotherm Photovoltaics...

1. A method for production of a solar cell, comprising:arranging a solar cell substrate in a retaining device having at least one retaining collar, being brought to abut against the at least one retaining collar;
inserting the retaining device into a coating device and depositing a dielectric coating on the back side of the solar cell substrate;
applying a planar contact on at least parts of the dielectric coating;
when the planar contact is applied on at least some parts of the dielectric coating, leaving free those areas which have been shaded by the retaining collars during the deposition of the dielectric coating;
configuring the planar contact in such a way that its boundary line has at least one recess; and
configuring and arranging the planar contact in such a way that the at least one recess leaves at least part of those areas which have been shaded by the retaining collars during the deposition of the dielectric coating free from a covering with the planar contact.

US Pat. No. 10,115,850

ROOF INTEGRATED SOLAR PANEL SYSTEM WITH SIDE MOUNTED MICRO INVERTERS

Building Materials Invest...

1. A roof integrated solar power system for generating electrical power from sunlight, the solar power system comprising:a plurality of modules configured to be installed in overlapping courses on a roof, each module including:
a frame having a top surface with an exposure portion to be exposed to sunlight when the module is installed and a headlap portion to be covered by a module in a next higher course of modules when the power system is installed, the exposure portion having opposed ends;
a photovoltaic panel recess formed in the exposure portion of the frame, the photovoltaic panel recess having a first end adjacent one of the opposed ends of the frame and a second end spaced from the other one of the opposed ends of the frame;
a photovoltaic panel having ends, a forward edge, a rear edge, and a top surface and being mounted within the photovoltaic panel recess;
an electronics compartment recess formed in the exposure portion of the frame within the space between the second end of the photovoltaic panel recess and the other one of the opposed ends of the frame;
a micro-inverter and first wiring mounted within the electronics compartment recess; an access panel removably attached to the top of the frame covering the electronics compartment recess, the access panel having a forward edge aligned with the forward edge of the photovoltaic panel and a rear edge aligned with the rear edge of the photovoltaic panel when the access panel is attached to the top of the frame; and
a top surface of the access panel and the top surface of the photovoltaic panel being flush with the top surface of the frame.

US Pat. No. 10,115,849

SOLAR CELL AND METHOD OF FABRICATING THE SAME

LG INNOTEK CO., LTD., Se...

1. A method of fabricating a solar cell, the method comprising:forming a back electrode layer on a substrate;
forming a light absorbing layer on the back electrode layer;
forming a first buffer layer on the light absorbing layer;
forming a second buffer layer on the first buffer layer; and
forming a front electrode layer on the second buffer layer;
wherein the first buffer layer or the second buffer layer comprises at least one of zinc sulfide (ZnS), zinc oxide (ZnO), and zinc hydroxide (Zn(OH)2),
wherein in order to form the buffer layer, the substrate is dipped into the solution in which an ammonia water is dissolved
wherein the forming the first buffer layer, the concentration of the ammonia water is in the range of 1 M to 4 M,
wherein the forming the second buffer layer, the concentration of the ammonia water is in the range of 5 M to 7 M,
wherein a difference in the concentration of ammonia water between the steps of forming the first and second buffer layers is in the range of 3 M to 6 M,
wherein simultaneously with the forming the first buffer layer, the second buffer layer is formed by adjusting the concentration of the ammonia water of the solution,
wherein the second buffer layer is in direct physical contact with the front electrode layer,
wherein the first buffer layer or the second buffer layer has a thickness in a range of about 15 nm to about 50 nm.

US Pat. No. 10,115,848

METHOD OF TRANSFERRING THIN FILM

NATIONAL TSING HUA UNIVER...

1. A method of transferring a thin film, comprising:providing a first element structure, wherein the first element structure includes a first substrate and a functional film layer formed on the first substrate;
completely removing the first substrate, wherein steps of the completely removing the first substrate include conducting an etching step to erode the first substrate and conducting a grinding step to planarize the eroded first substrate, and wherein the etching step and the grinding step are separately and repeatedly conducted until the first substrate is completely removed; and
after completely removing the first substrate, attaching the functional film layer on a second substrate to form a second element structure without flipping the functional film layer;
wherein the first substrate is a soda glass substrate, the functional film layer is a solar cell layer, and the functional film layer includes a back electrode layer, a light absorbing layer, a buffer layer, and a transparent conductive layer, and wherein the light absorbing layer is disposed between the back electrode layer and the transparent conductive layer, and the buffer layer is disposed between the light absorbing layer and the transparent conductive layer.

US Pat. No. 10,115,845

COMPOSITION FOR FORMING SOLAR CELL ELECTRODES AND ELECTRODES FABRICATED USING THE SAME

SAMSUNG SDI CO., LTD., Y...

1. A composition for forming solar cell electrodes, the composition comprising a conductive powder, a glass frit, an organic vehicle, and a surface tension modifier having a surface tension of 40 to 60 mN/m, the composition for forming solar cell electrodes having a tackiness of 60% to 90% represented by the following Expression 1:
wherein, in Expression 1, A represents a minimum shear stress value of shear stress measured while detaching a pair of circular plates, from each other, which have a diameter of 25 mm and have been laminated in parallel to each other by a medium of the composition for forming solar cell electrodes, by applying an external force, and B represents a shear stress value at a point at which an instantaneous rate of change of shear stress with respect to a gap between the plates (d (shear stress)/d (gap)) is 0.05.

US Pat. No. 10,115,844

ELECTRODES COMPRISING NANOSTRUCTURED CARBON

SEERSTONE LLC, Provo, UT...

1. A method of producing a sintered object, comprising:mixing a mass of nanostructured carbon particles with at least one fluid containing a dissolved carbon source to produce a paste;
pyrolyzing the paste such that the dissolved carbon source forms residual solid carbon within a cohesive body of the nanostructured carbon particles; and
sintering the cohesive body of the nanostructured carbon particles with the residual solid carbon at a pressure from about 10 MPa to about 1000 MPa to form contacts between adjacent nanostructured carbon particles to provide an electrical path between at least two remote points of the cohesive body.

US Pat. No. 10,115,843

BROADBAND ANTIREFLECTION COATINGS UNDER COVERGLASS USING ION GUN ASSISTED EVAPORATION

THE BOEING COMPANY, Chic...

1. A method of forming an antireflective coating, comprising:depositing a first layer comprising titanium dioxide and having a first index of refraction within a range of about 2.3 to about 2.7 using ion beam-assisted deposition;
depositing an intermediate layer by e-beam evaporation comprising titanium dioxide on the first layer, the intermediate layer having an index of refraction and a density less than the first layer;
depositing a second layer on the intermediate layer by e-beam evaporation, the second layer having an index of refraction less than the intermediate layer and within a range of about 1.8 to about 2.1; and
depositing a third layer on the second layer, the third layer having an index of refraction within a range of about 1.6 to about 1.8.

US Pat. No. 10,115,840

SOLAR CELL AND METHOD FOR PRODUCING THEREOF

SHIN-ETSU CHEMICAL CO., L...

1. A solar cell comprising:a semiconductor substrate of a first conductivity type comprising main surfaces that are opposite to each other wherein one of the main surfaces is a light-receiving surface, the other main surface is a backside, and the backside of the semiconductor substrate has a region of the first conductivity type and a region of a second conductivity type, being an opposite conductivity type to the first conductivity type;
a first finger electrode composed of a first contact portion joined to the region of the first conductivity type and a first current collector formed on the first contact portion;
a second finger electrode composed of a second contact portion joined to the region of the second conductivity type and a second current collector formed on the second contact portion;
a first bus bar electrode being in electrical contact with the first current collector;
a second bus bar electrode being in electrical contact with the second current collector;
a first insulator film disposed at least in the whole area just under the first bus bar electrode; and
a second insulator film disposed at least in the whole area just under the second bus bar electrode;
wherein the entire area of the first bus bar electrode is disposed on the first insulator film;
the entire area of the second bus bar electrode is disposed on the second insulator film;
the electrical contact between the first current collector and the first bus bar electrode is made on the first insulator film;
the electrical contact between the second current collector and the second bus bar electrode is made on the second insulator film;
the first contact portion is in a continuous line shape at least just under the second insulator film; and
the second contact portion is in a continuous line shape at least just under the first insulator film.

US Pat. No. 10,115,834

METHOD FOR MANUFACTURING AN EDGE TERMINATION FOR A SILICON CARBIDE POWER SEMICONDUCTOR DEVICE

ABB Schweiz AG, Baden (C...

17. A silicon carbide power semiconductor device having a central region and an edge region between a first main side and a second main side opposite to the first main side,wherein an n doped silicon carbide substrate layer is arranged on the second main side,
an n-doped silicon carbide drift layer, which is lower doped than the silicon carbide substrate layer, is arranged on the first main side, in the edge region on the first main side at least one p doped termination layer and an (n??) doped doping reduction layer is arranged, which has lower doping concentration than the drift layer,
wherein the doping reduction layer is arranged in a doping reduction layer depth range between a depth of a doping concentration minimum of the doping reduction layer below the first main side up to a maximum doping reduction layer depth, wherein the depth of the doping concentration minimum of the doping reduction layer is deeper than the maximum termination layer depth, wherein the doping reduction layer depth range is less than 10 ?m, wherein the doping reduction layer comprises a plurality of doping reduction regions, each of which has a depth of the doping concentration minimum of the doping reduction region, a maximum doping reduction region depth and a doping reduction region depth range being the deviation between the maximum doping reduction region depth and the depth of the doping concentration minimum and wherein each doping reduction region depth range is less than 1 ?m.

US Pat. No. 10,115,833

SELF-ALIGNED HETEROJUNCTION FIELD EFFECT TRANSISTOR

International Business Ma...

1. A junction field effect transistor comprising:an insulating carrier substrate;
a base semiconductor substrate formed on the insulating carrier substrate;
a gate region formed on the base semiconductor substrate wherein the gate region forms a junction with the base semiconductor substrate;
a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region;
a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region; and
a gate stack deposited on the gate region, a first source/drain stack deposited on the first source/drain region and a second source/drain stack deposited on the second source/drain region;
wherein at least a portion of the first source/drain stack and a portion of the second source/drain stack overlaps a top surface of the gate stack in the gate region.

US Pat. No. 10,115,831

SEMICONDUCTOR DEVICE HAVING AN OXIDE SEMICONDUCTOR LAYER COMPRISING A NANOCRYSTAL

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode layer;
a gate insulating layer over the gate electrode layer;
an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising:
a first region;
a second region;
a third region between the first region and the second region;
a fourth region between the first region and the third region; and
a fifth region between the second region and the third region;
a first insulating layer over the oxide semiconductor layer, the first insulating layer comprising oxygen;
a source electrode layer over the oxide semiconductor layer; and
a drain electrode layer over the oxide semiconductor layer,
wherein the first region is in contact with the source electrode layer,
wherein the second region is in contact with the drain electrode layer,
wherein the third region is in contact with the first insulating layer,
wherein the fourth region has a thickness less than the third region,
wherein the fifth region has a thickness less than the third region, and
wherein the oxide semiconductor layer comprises a nanocrystal.

US Pat. No. 10,115,830

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising:forming an oxide semiconductor film;
forming a gate insulating film over the oxide semiconductor film;
forming a gate electrode over the gate insulating film;
forming an interlayer insulating film over the oxide semiconductor film and the gate electrode;
performing planarization treatment on the interlayer insulating film;
forming a first opening and a second opening in the interlayer insulating film subjected to the planarization treatment;
forming a first conductive film in the first opening and the second opening and over the interlayer insulating film subjected to the planarization treatment;
forming a second conductive film and a third conductive film by performing planarization treatment on the first conductive film; and
forming a first region and a second region in the oxide semiconductor film by adding an impurity to the second conductive film and the third conductive film,
wherein the first region and the first opening overlap with each other, and
wherein the first region is formed by an impact caused by addition of the impurity to the second conductive film.

US Pat. No. 10,115,829

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising a transistor, the transistor comprising:a gate electrode over a substrate;
an insulating film over the gate electrode;
an oxide semiconductor layer over the insulating film, the oxide semiconductor layer comprising a channel formation region of the transistor overlapping with the gate electrode;
a channel protective layer over the channel formation region;
a source electrode and a drain electrode over the channel protective layer, the source electrode and the drain electrode each electrically connected to the oxide semiconductor layer;
a first titanium oxide between the oxide semiconductor layer and the source electrode; and
a second titanium oxide between the oxide semiconductor layer and the drain electrode,
wherein at least one of the first titanium oxide and the second titanium oxide comprises indium or zinc,
wherein a top inner edge of the first titanium oxide is over the channel protective layer and extends inward from a bottom inner edge of the source electrode, and
wherein a top inner edge of the second titanium oxide is over the channel protective layer and extends inward from a bottom inner edge of the drain electrode.

US Pat. No. 10,115,828

FIELD-EFFECT TRANSISTOR, DISPLAY ELEMENT, IMAGE DISPLAY DEVICE, AND SYSTEM

RICOH COMPANY, LTD., Tok...

1. A field-effect transistor comprising:a gate electrode, which is configured to apply gate voltage;
a source electrode and a drain electrode, which are configured to take electric current out;
an active layer, which is disposed to be adjacent to the source electrode and the drain electrode and includes a n-type oxide semiconductor; and
a gate insulating layer, which is disposed between the gate electrode and the active layer,
wherein the n-type oxide semiconductor is substitutionally doped with at least one cation dopant selected from the group consisting of a divalent cation, a trivalent cation, a tetravalent cation, a pentavalent cation, a hexavalent cation, a heptavalent cation, and an octavalent cation,
wherein the n-type oxide semiconductor includes a metal ion as a component, and a valence of the cation dopant is greater than a valence of the metal ion, and the cation dopant and the metal ion included in the n-type oxide semiconductor are not the same element, and
wherein the source electrode and the drain electrode include a material selected from the group consisting of the following (i) and (ii), in at least contact regions of the source electrode and the drain electrode with the active layer, the material selected from the group consisting of (i) and (ii) being disposed to be in contact with the n-type oxide semiconductor:
(i) metals of Au, Pt and Pd; and
(ii) alloys including at least any one of Au, Pt and Pd.

US Pat. No. 10,115,826

SEMICONDUCTOR STRUCTURE AND THE MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a FINFET, comprising:forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation;
oxidizing the fin structure and the layer to transform the layer into a first oxide layer;
filling insulating material between adjacent fin structures after oxidizing the fin structure and the layer; and
etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure.

US Pat. No. 10,115,825

STRUCTURE AND METHOD FOR FINFET DEVICE WITH ASYMMETRIC CONTACT

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a fin-type active region extruded from a semiconductor substrate;
a gate stack disposed on the fin-type active region;
a source/drain feature formed in the fin-type active region and disposed on a side of the gate stack;
an elongated contact feature landing on the source/drain feature; and
a dielectric material layer disposed on sidewalls of the elongated contact feature and free from ends of the elongated contact feature, wherein the sidewalls of the elongated contact feature are parallel with the gate stack.

US Pat. No. 10,115,824

FORMING A CONTACT FOR A SEMICONDUCTOR DEVICE

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising a PFET and a NFET:a gate stack arranged over a channel region of a semiconductor substrate;
a spacer arranged adjacent to the gate stack;
a first source and drain region of the PFET arranged adjacent to the spacer,
the first source and drain region comprising:
a first doped crystalline semiconductor material arranged on the semiconductor substrate:
a second doped crystalline semiconductor material arranged on the first doped crystalline semiconductor material;
a first liner layer comprising a conductive metallic oxide material arranged on the second doped crystalline semiconductor material; and
a second liner layer comprising a metallic material arranged on the first liner layer;
a second source and drain region of the NFET arranged adjacent to the spacer the second source and drain region comprising:
a third doped crystalline semiconductor material arranged on the semiconductor substrate; and
the second liner layer formed directly on the third doped crystalline semiconductor material; and
a conductive contact material arranged on the second liner layer in the first source and drain region of the PFET and the second source and drain region of the NFET.

US Pat. No. 10,115,823

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a Fin Field-Effect Transistor (Fin FET) device including:
a fin structure extending in a first direction and protruding from an isolation insulating layer, the fin structure and the isolation insulating layer being disposed over a substrate, the fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer;
a gate stack including a gate electrode layer, covering a portion of the fin structure and extending in a second direction perpendicular to the first direction;
a source and a drain, each including a stressor layer disposed over recessed portions formed in the fin structure; and
seed layers disposed in contact with the oxide layer,
wherein the stressor layer is in contact with the seed layer.

US Pat. No. 10,115,822

METHODS OF FORMING LOW BAND GAP SOURCE AND DRAIN STRUCTURES IN MICROELECTRONIC DEVICES

Intel Corporation, Santa...

1. A method of forming a device comprising:forming source/drain regions in a device substrate;
alloying source/drain material of the source/drain regions with tin to reduce its band gap to close to zero, the source/drain material comprising germanium; and
forming source/drain contacts to couple to the source/drain regions, wherein a small band gap of the alloyed region results in small metal contact resistance, wherein the alloyed region comprises Ge0.7Sn0.3, and wherein the device is ambipolar.

US Pat. No. 10,115,821

FDSOI LDMOS SEMICONDUCTOR DEVICE

Avago Technologies Genera...

14. A fully depleted silicon-on-insulator (FDSOI) semiconductor device, comprising:an extended drain region comprising:
a drain region disposed above a first type well;
a first drain extension region disposed above the first type well; and
a second drain extension region disposed above the first type well,
wherein the drain region, the first drain extension region, and the second drain extension region are laterally spaced apart from each other, and
wherein the first drain extension region is electrically coupled with the second drain extension region;
a source region disposed above a second type well and laterally spaced apart from the extended drain region; and
a channel layer disposed above the second type well and disposed laterally between the source region and the extended drain region,
wherein the drain region and the first drain extension region are disposed above and in contact with a bulk region of the FDSOI semiconductor device, and
wherein the source region, the channel layer, and the second drain extension region are disposed above and in contact with a silicon-on-insulator (SOI) region of the FDSOI semiconductor device.

US Pat. No. 10,115,820

VERTICAL TRANSISTORS WITH SIDEWALL GATE AIR GAPS AND METHODS THEREFOR

SanDisk Technologies LLC,...

1. A method comprising:forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction;
forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor comprising a second sidewall gate disposed in the first direction; and
forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber comprising an air gap, wherein forming the air gap chamber comprises:
forming a first sidewall liner on the first sidewall gate and a second sidewall liner on the second sidewall gate;
etching a top edge of the first sidewall gate below a top edge of the first sidewall liner; and
etching a top edge of the second sidewall gate below a top edge of the second sidewall liner,
wherein:
the first sidewall liner comprises a first upper section and the second sidewall liner comprises a second upper section; and
the first upper section bends or pitches towards the second upper section.

US Pat. No. 10,115,818

REDUCING MOSFET BODY CURRENT

SEMICONDUCTOR COMPONENTS ...

1. A bidirectional MOSFET switch having reduced body current, the switch comprising:a body region that is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type, the body region being connected to a body terminal, the source region being connected to a source terminal, and the drain region being connected to a drain terminal;
a buried layer that is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type, the buried layer being coupled to a buried layer terminal;
a gate terminal drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal;
a first configuration switch that disconnects the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage; and
a second configuration switch that connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

US Pat. No. 10,115,817

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A method of manufacturing a semiconductor device, the method comprising:forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a continuous first area and a second area; thereafter
introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer; and thereafter
forming a second semiconductor layer on the first semiconductor layer; and
forming trenches in the second semiconductor layer in the continuous first area.

US Pat. No. 10,115,814

PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS

Alpha and Omega Semicondu...

1. A method for manufacturing a semiconductor power device on a semiconductor substrate comprising:depositing a hard mask atop the semiconductor substrate and patterning the hard mask according to a pre-determined trench configuration;
etching the semiconductor substrate through the patterned hard mask to form a plurality of trenches in the top portion of the semiconductor substrate each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench with the endpoint sidewall extends vertically downward from a top surface to a trench bottom surface;
applying vertical high energy implant to form trench bottom dopant regions below the trench bottom surface followed by removing the hard mask;
depositing an insulation layer for covering trench sidewalls and an insulation layer for covering the trench bottom surfaces;
applying a low energy tilt implant to form a sidewall dopant region along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region to pick-up the trench bottom dopant region to the top surface of the semiconductor substrate; and
forming at least two of the endpoint sidewall body dopant regions in at least two of the endpoint sidewalls that are immediately adjacent to each other as adjacent endpoint sidewall body dopant regions with the adjacent endpoint sidewall body dopant regions extend through an entire semiconductor region between at least two of the endpoint sidewalls and merging the adjacent endpoint sidewall body dopant regions into a joined endpoint sidewall body dopant region to extend vertically downward along an entire length of the endpoint sidewalls of the adjacent trenches to reach and directly contact the laterally extended region of the trench bottom body dopant region.

US Pat. No. 10,115,813

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first III-V compound layer;
a second III-V compound layer over the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located at an interface of the first III-V compound layer and the second III-V compound layer, and wherein the second III-V compound layer is doped providing a contiguous constant composition of the second III-V compound layer;
an opening in a dielectric layer over the second III-V compound layer, wherein the opening continues through the dielectric layer to extends below a top surface of the second III-V compound layer having the contiguous constant composition;
slanted field plates in the opening, wherein the slanted field plates interface the contiguous constant composition wherein the dielectric layer interfaces the contiguous constant composition; and
a gate electrode in the opening and interfacing with the second III-V compound layer and the slanted field plates.

US Pat. No. 10,115,812

SEMICONDUCTOR DEVICE HAVING A SUPERJUNCTION STRUCTURE

Infineon Technologies Ame...

1. A semiconductor device, comprising:a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type situated below the first semiconductor region;
a third semiconductor region of the second conductivity type situated above the first semiconductor region;
a fourth semiconductor region of the first conductivity type situated between the first and the third semiconductor regions;
first and second control trenches extending through the third and the fourth semiconductor regions into the first semiconductor region, each control trench being bordered by a diffusion region of the first conductivity type; and
a superjunction structure situated in the first semiconductor region between the first and the second control trenches so that the superjunction structure does not extend under either the first or the second control trench, the superjunction structure being separated from the third semiconductor region by the fourth semiconductor region and comprising alternating regions of the first and the second conductivity types.

US Pat. No. 10,115,809

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method of manufacturing a semiconductor memory device, the method comprising:forming a channel region by implanting ions into a semiconductor substrate in which active regions and isolation regions are alternately defined parallel to each other, and a support region is defined in a direction perpendicularly crossing the active regions and the isolation regions;
forming first trenches in the isolation regions;
forming an etch mask along inner sidewalls of the first trenches and over the support region;
forming second trenches and a support layer by an etching process using the etch mask; and
forming drain select lines, word lines and source select lines on the semiconductor substrate of the active regions and the isolation regions,
wherein the second trenches are formed under the first trenches and the active regions with a bottom surface lower than a bottom surface of the first trenches wherein the second trenches are not formed in the support region, wherein the support layer is formed in the support region, is perpendicular to the second trenches,
wherein the second trenches are separated by the support layer, and
wherein the support layer is extended under the active regions.

US Pat. No. 10,115,808

FINFET DEVICE AND METHODS OF FORMING

Taiwan Semiconductor Manu...

1. A method comprising:depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate;
forming a first gate spacer along a sidewall of the dummy gate;
plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer;
forming a source/drain region adjacent a channel region of the fin; and
diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region, wherein the first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

US Pat. No. 10,115,805

EXTREMELY THIN SILICON-ON-INSULATOR SILICON GERMANIUM DEVICE WITHOUT EDGE STRAIN RELAXATION

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:forming a strained silicon germanium layer on top of a substrate;
forming at least one patterned hard mask layer on and in contact with at least a first portion of the strained silicon germanium layer; and
oxidizing at least a first exposed portion and a second exposed portion of the strained silicon germanium layer, the oxidizing forming at least one patterned strained silicon germanium area within the strained silicon germanium layer comprising a first oxide end region and a second oxide end region corresponding to first and second exposed portions, respectively, of the strained silicon germanium layer.

US Pat. No. 10,115,800

VERTICAL FIN BIPOLAR JUNCTION TRANSISTOR WITH HIGH GERMANIUM CONTENT SILICON GERMANIUM BASE

INTERNATIONAL BUSINESS MA...

1. A method of manufacturing a bipolar junction transistor (BJT) structure comprising:providing a substrate having a first semiconductor layer, a silicon germanium layer and a second semiconductor layer sequentially stacked on the substrate;
pattern etching through the second semiconductor layer and recessing the silicon germanium layer to form a plurality of vertical fins spaced apart in a first direction and extending in a second direction crossing the first direction, each of the plurality of vertical fins comprising a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on the first semiconductor layer;
forming first spacers on sidewalls of the plurality of vertical fins;
directionally etching away exposed silicon germanium layer above the first semiconductor layer;
depositing a germanium oxide layer to conformally coat exposed top and sidewall surfaces of the plurality of vertical fins and the first semiconductor layer;
performing condensation annealing followed by silicon oxide strip;
removing the first spacers, remaining germanium oxide layer and the hard mask pattern of each of the plurality of vertical fins;
depositing a dielectric material over the first semiconductor layer to fill all spaces among the plurality of vertical fins; and
forming an emitter contact, a base contact and a collector contact connected to the second semiconductor pattern, the silicon germanium pattern and the first semiconductor layer, respectively, in the dielectric material.

US Pat. No. 10,115,796

METHOD OF PULLING-BACK SIDEWALL METAL LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a first trench, a second trench, and a third trench extending through a dielectric layer over a substrate, wherein the first trench and the second trench have a first width, and further wherein the third trench has a second width that is greater than the first width;
forming a material layer in the first trench, the second trench, and the third trench;
forming a sacrificial layer over the material layer, wherein the sacrificial layer fills the first trench and the second trench while partially filling the third trench, wherein a height of the sacrificial layer in the first trench, a height of the sacrificial layer in the second trench, and a height of the sacrificial layer in the third trench are substantially the same;
forming a patterning layer over the sacrificial layer in the third trench, wherein the patterning layer fills a remaining portion of the third trench;
recessing the sacrificial layer in the first trench and the second trench, wherein a height of sacrificial layer remaining in the first trench is substantially the same as a height of sacrificial layer remaining in the second trench;
recessing the material layer in the first trench and in the second trench, wherein a height of the material layer remaining in the first trench is substantially the same as a height of the material layer remaining in the second trench; and
completely removing the patterning layer, the sacrificial layer remaining in the first trench and the second trench, and the sacrificial layer in the third trench.

US Pat. No. 10,115,795

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a semiconductor substrate having a square shape in plan view;
an active portion provided in the semiconductor substrate;
a peripheral portion provided around the active portion; and
a resistive field plate provided in the peripheral portion and surrounding the active portion,
wherein the resistive field plate comprises:
an outer-peripheral-side resistive field plate surrounding the active portion;
an inner-circumferential-side resistive field plate surrounding the active portion, disposed between the outer-peripheral-side resistive field plate and the active region, and being spaced apart from the outer-peripheral-side resistive field plate; and
an intermediate resistive field plate provided between the inner-circumferential-side resistive field plate and the outer-circumferential-side resistive field plate and electrically coupling the inner-circumferential-side resistive field plate to the outer-circumferential-side resistive field plate,
wherein the intermediate resistive field plate comprises:
a first intermediate resistive field plate; and
a plurality of second intermediate resistive field plates,
wherein one end of the first intermediate resistive field plate is coupled to the inner-circumferential-side resistive field plate, and another end of the first intermediate resistive field plate is coupled to the outer-circumferential-side resistive field plate,
wherein the first intermediate resistive field plate connects the inner-circumferential-side resistive field plate and the outer-circumferential-side resistive field plate to each other, and has first portions separated from each other in a first direction and connection portions connecting the first portions to each other, each of the first portions extending in a second direction orthogonal to the first direction, and
wherein the second intermediate resistive field plates have end portions respectively connected with first end portions of the first portions of the first intermediate resistive filed plate on one side of the first portions of the first intermediate resistive filed plate, have end portions opened on a side opposite to the end portions of the second intermediate resistive field plates connected with the first end portion of the first portions of the first intermediate resistive filed plate, and respectively extend at least with a curvature.

US Pat. No. 10,115,793

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
a first semiconductor layer having a first conductivity type and formed in the semiconductor substrate;
a second semiconductor layer having a second conductivity type different from the first conductivity type and formed in the semiconductor substrate located between the first semiconductor layer and the second main surface;
a plurality of element portions provided in the first main surface of the semiconductor substrate to be spaced apart from each other in a first direction in plan view and extend in a second direction orthogonal to the first direction; and
a plurality of interposed portions provided in the first main surface of the semiconductor substrate to be interposed between the element portions in plan view,
wherein each of the element portions has:
a first trench provided in one of boundary portions between the element portion and the interposed portions to extend from the first main surface in the second direction in plan view and reach a middle point in the first semiconductor layer;
a second trench provided in the other of the boundary portions between the element portion and the interposed portions to extend from the first main surface in the second direction in plan view and reach a middle point in the first semiconductor layer;
a third trench provided between the first and second trenches to extend from the first main surface in the second direction in plan view and reach a middle point in the first semiconductor layer;
a first trench electrode embedded in the first trench via a first insulating film;
a second trench electrode embedded in the second trench via a second insulating film;
a third trench electrode embedded in the third trench via a third insulating film;
a first semiconductor region having the second conductivity type and formed in the first main surface of the semiconductor substrate located between the first and third trenches to come in contact with the first and third insulating films;
a second semiconductor region having the second conductivity type and formed in the first main surface of the semiconductor substrate located between the second and third trenches to come in contact with the second and third insulating films;
a first coupling portion provided between the first and third trenches to extend in the second direction in plan view and reach a middle point in the first semiconductor region;
a second coupling portion provided between the second and third trenches to extend in the second direction in plan view and reach a middle point in the second semiconductor region; and
a plurality of third semiconductor regions each having the first conductivity type and formed in the first main surface of the semiconductor substrate located between the first coupling portion and the third trench and between the second coupling portion and the third trench in contact relation with the third insulating film to be shallower than the first and second coupling portions and spaced apart at a regular interval in the second direction in plan view,
wherein each of the interposed portions has a fourth semiconductor region having the second conductivity type and reaching the first semiconductor layer from the first main surface, and
wherein, with regard to two of the element portions which are adjacent to each other in the first direction with the interposed portion being interposed therebetween, one of the third semiconductor regions formed in one of the adjacent two element portions is disposed in the first direction from a region interposed between two of the third semiconductor regions formed in the other of the adjacent two element portions which are adjacent to each other in the second direction.

US Pat. No. 10,115,791

SEMICONDUCTOR DEVICE INCLUDING A SUPER JUNCTION STRUCTURE IN A SIC SEMICONDUCTOR BODY

Infineon Technologies AG,...

1. A semiconductor device, comprising:a body region of a first conductivity type in a SiC semiconductor body of a second conductivity type; and
a super junction structure in the SiC semiconductor body, and comprising a drift zone section of the second conductivity type and a compensation structure of the first conductivity type,
wherein the compensation structure adjoins the body region and includes compensation sub-structures consecutively arranged along a vertical direction perpendicular to a surface of the SiC semiconductor body,
wherein the compensation sub-structures include a first compensation sub-structure and a second compensation sub-structure,
wherein a resistance of the second compensation sub-structure between opposite ends of the second compensation sub-structure along the vertical direction is at least five times larger than a resistance of the first compensation sub-stricture between opposite ends of the first compensation sub-structure along the vertical direction.

US Pat. No. 10,115,790

ELECTRONIC DEVICE INCLUDING AN INSULATING STRUCTURE

SEMICONDUCTOR COMPONENTS ...

1. A process of forming an electronic device comprising:patterning a substrate to define a trench and a first anchor having a proximal portion and a distal portion, wherein
the first anchor extends from a sidewall of the trench,
the sidewall is closer to the proximal portion than to the distal portion, and
the proximal portion has a width that is less than a width of the distal portion; and
forming an insulating structure within the trench and adjacent to the first anchor.

US Pat. No. 10,115,788

SEMICONDUCTOR DEVICES WITH HORIZONTAL GATE ALL AROUND STRUCTURE AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device having a horizontal gate all around structure, the semiconductor device comprising:a fin that is disposed on a substrate and includes
a source-facing side and a drain-facing side,
an anti-punch-through (APT) layer above and physically contacting the substrate,
a barrier layer above and physically contacting the APT layer, wherein the barrier has a different composition from the substrate,
a metal gate above the barrier layer, and
a nanowire above the metal gate;
a source located alongside the fin's source-facing side and projecting upward from the barrier layer to a location above the nanowire, such that a portion of the barrier layer is sandwiched between the APT layer and the source; and
a drain located alongside the fin's drain-facing side and projecting upward from the barrier layer to a location above the nanowire, such that the nanowire extends horizontally from physical contact with the source to physical contact with the drain.

US Pat. No. 10,115,786

CAPACITOR AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A capacitor, comprising:a bottom electrode on a substrate;
a middle electrode on the bottom electrode, wherein in a cross-section view, the middle electrode comprises a first H-shape, a second H-shape adjacent to the first H-shape, and a first horizontal portion connecting the first H-shaped and the second H-shape, wherein the first H-shape comprises two vertical portions and a second horizontal portion and the two vertical portions are orthogonal to a top surface of the substrate and a bottom surface of the first horizontal portion is substantially coplanar with a bottom surface of the two vertical portions;
a first dielectric layer between the bottom electrode and the middle electrode, wherein the first dielectric layer fully covers a bottom surface of the second horizontal portion; and
a top electrode on the middle electrode, wherein the bottom electrode has a flat bottom surface spanning entire width of the capacitor.

US Pat. No. 10,115,785

MEMORY CELLS AND DEVICES

Xerox Corporation, Norwa...

1. A memory cell comprising a flexible substrate layer and a layer comprising a crosslinked mixture of an acrylic polyol, an alkylene urea-glyoxal resin, and an acid catalyst, wherein said acrylic polyol possesses an OH equivalent weight of from about 300 to about 1,500, and a glass transition temperature of from about ?20° C. to about 90° C.

US Pat. No. 10,115,784

SEMICONDUCTOR DEVICE, MIM CAPACITOR AND ASSOCIATED FABRICATING METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a first dielectric layer over the semiconductor substrate;
a second dielectric layer over the first dielectric layer;
a via extending through the second dielectric layer;
a bottom conductive layer conformably formed at a bottom and along side walls of the via;
a third dielectric layer conformably formed over the bottom conductive layer;
an upper conductive layer conformably formed over the third dielectric layer; and
an upper contact formed over and coupled to the upper conductive layer and filling the via;
wherein the upper conductive layer provides a diffusion barrier between the upper contact and the third dielectric layer.

US Pat. No. 10,115,783

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SIGNAL TRANSMITTING/RECEIVING METHOD USING THE SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a semiconductor substrate;
an internal circuit provided on the semiconductor substrate;
a plurality of external connection pads provided on the semiconductor substrate and electrically connected to the internal circuit to transmit and receive signals to and from an outside of the semiconductor device;
an inductor provided on the semiconductor substrate and including the internal circuit and the plurality of external connection pads and connected to the internal circuit;
a shield member provided on the semiconductor substrate and positioned among the inductor, the internal circuit, and the plurality of external connection pads;
a power supply circuit provided on the semiconductor substrate; and
a power supply receiving inductor for supplying power to the internal circuit,
wherein the power supply receiving inductor is connected to the power supply circuit and supplies power to the internal circuit via the power supply circuit, and
wherein the plurality of external connection pads include a power supply external connection pad and a plurality of signal external connection pads.

US Pat. No. 10,115,781

ORGANIC LIGHT-EMITTING DIODE DISPLAY

Chunghwa Picture Tubes, L...

1. An organic light-emitting diode display comprising:a pixel array substrate comprising:
a first substrate having a plurality of pixel regions arranged in an array and a peripheral region surrounding the pixel regions;
a plurality of pixel units located in the pixel regions, each of the pixel units comprising:
a switch transistor having an input electrode, a control electrode, and an output electrode;
a driver transistor having an input electrode, a control electrode, and an output electrode, wherein the output electrode of the switch transistor is electrically coupled to the control electrode of the driver transistor; and
a pixel electrode electrically coupled to the output electrode of the driver transistor;
a plurality of data lines located on the first substrate and electrically coupled to the input electrodes of the switch transistors;
a plurality of scan lines located on the first substrate and electrically coupled to the control electrodes of the switch transistors;
a plurality of constant voltage lines located on the first substrate and electrically coupled to the input electrodes of the driver transistors;
a constant voltage source located on the peripheral region of the first substrate, the constant voltage source providing a constant voltage to the constant voltage lines; and
a conductive pattern located on the first substrate and overlapped with the control electrode of each of the driver transistors;
a second substrate opposite to the first substrate;
an organic light-emitting diode layer located between the second substrate and the pixel electrodes; and
a common electrode layer located between the second substrate and the organic light-emitting diode layer and overlapped with the control electrodes of the driver transistors, wherein a film layer where the control electrodes of the driver transistors are located is between the first substrate and a film layer where the input electrodes of the driver transistors are located, the film layer where the input electrodes of the driver transistors are located is between a film layer where the conductive pattern is located and the film layer where the control electrodes of the driver transistors are located, the film layer where the conductive pattern is located is between the organic light-emitting diode layer and the film layer where the input electrodes of the driver transistors are located, and the conductive pattern is in electrical and physical contact with the common electrode layer.

US Pat. No. 10,115,780

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate comprising a first display region having a first width in a first direction, a second display region having a second width smaller than the first width in the first direction, a peripheral region at a periphery of the first and second display regions, and a dummy region in the peripheral region;
a first pixel in the first display region;
a second pixel in the second display region;
a first control line connected to the first pixel, the first control line extending along the first direction in the first display region;
a second control line connected to the second pixel, the second control line extending along the first direction in the second display region; and
a dummy line connected to the second control line, the dummy line being in the dummy region,
wherein the second control line is at a first conductive layer on a first insulating layer, the first insulating layer is on the substrate, the dummy line is at a second conductive layer on a second insulating layer, and the second insulating layer is on the first conductive layer.

US Pat. No. 10,115,779

DISPLAY UNIT

Sony Corporation, (JP)

1. A display unit comprising:a first pixel including a first organic EL device configured to emit green light, and a first driving circuit configured to drive the first organic EL device;
a second pixel including a second organic EL device configured to emit blue light, and a second driving circuit configured to drive the second organic EL device;
a third pixel including a third organic EL device configured to emit red light, and a third driving circuit configured to drive the third organic EL device; and
a control line connected to each of the first driving circuit, the second driving circuit, and the third driving circuit,
wherein the second driving circuit is located between the first driving circuit and the third driving circuit,
wherein the first driving circuit includes a first driving transistor, a first sampling transistor, and a first capacitor having a first electrode and a second electrode, the first capacitor being connected to a gate electrode of the first driving transistor, the first electrode is disposed over the second electrode,
wherein the second driving circuit includes a second driving transistor, a second sampling transistor, and a second capacitor having a first electrode and a second electrode, the second capacitor being connected to a gate electrode of the second driving transistor, the first electrode is disposed over the second electrode,
wherein the third driving circuit includes a third driving transistor, a third sampling transistor, and a third capacitor having a first electrode and a second electrode, the third capacitor being connected to a gate electrode of the third driving transistor, the first electrode is disposed over the second electrode,
wherein the second organic EL device has a blue light emission area overlapping the second capacitor in a plan view,
wherein a distance between a channel region of the first driving transistor and the blue light emission area is larger than a distance between the first electrode of the first capacitor and the blue light emission area, and
wherein a distance between a channel region of the third driving transistor and the blue light emission is larger than a distance between the first electrode of the third capacitor and the blue light emission area.

US Pat. No. 10,115,778

ELECTRO-OPTICAL APPARATUS, MANUFACTURING METHOD FOR ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC DEVICE

SEIKO EPSON CORPORATION, ...

1. A light-emitting device, the light-emitting device comprising:a light-reflective layer;
an opposing electrode;
a functional layer including a light-emitting layer, the functional layer being disposed between the light-reflective layer and the opposing electrode;
a first pixel electrode disposed between the light-reflective layer and the functional layer;
a second pixel electrode disposed between the light-reflective layer and the functional layer;
a third pixel electrode disposed between the light-reflective layer and the functional layer;
an insulating layer having a first insulating layer, a second insulating layer, and a third insulating layer,
wherein the first insulating layer is disposed between the first pixel electrode and the light-reflective layer,
wherein the first insulating layer and the third insulating layer are disposed between the second pixel electrode and the light-reflective layer,
wherein the first insulating layer, the second insulating layer, and the third insulating layer are disposed between the third pixel electrode and the light-reflective layer,
wherein the second insulating layer is disposed between the first insulating layer and the third insulating layer in a region that the third pixel electrode overlaps the light-reflective layer,
wherein the third insulating layer physically contacts the first insulating layer in a region that the second pixel electrode overlaps the light-reflective layer, and
wherein at least part of an edge of the second insulating layer is covered by the third insulating layer, and
wherein at least one of the first, second and third insulating layers is made of a material different from others of the first, second and third insulating layers.

US Pat. No. 10,115,777

DISPLAY DEVICE

Japan Display Inc., Toky...

6. A display device comprising:a plurality of pixel electrodes including a first pixel electrode;
a bank covering an edge part of the first pixel electrode, and a region between adjacent pixel electrodes;
a first electrode arranged separated from the first pixel electrode and above the bank;
a first organic layer arranged above the first pixel electrode, above the first electrode and above the bank;
a second organic layer arranged above the first organic layer overlapping the first pixel electrode;
a third organic layer arranged above the second organic layer, above the first organic layer overlapping the first electrode, and above the first organic layer overlapping the bank;
an opposing electrode arranged above the third organic layer overlapping the first pixel electrode; and
a second electrode arranged above the third organic layer overlapping the first electrode, wherein
a region stacked with the first pixel electrode, the first organic layer, the second organic layer, the third organic layer and the opposing electrode corresponds to a region of a light emitting element, and
a region stacked with the first electrode, the first organic layer, the third organic layer and the second electrode corresponds to a region of a light receiving element.

US Pat. No. 10,115,776

ORGANIC LIGHT EMITTING DISPLAY DEVICES

Samsung Display Co., Ltd....

1. An electroluminescent device, comprising:a substrate;
a plurality of first electrodes located on the substrate to be spaced apart from each other;
a pixel defining layer disposed on the substrate to expose portions of the first electrodes;
an intermediate layer disposed on the pixel defining layer and the first electrodes;
an emitting layer disposed on the intermediate layer to overlap the first electrode;
a second electrode disposed on the emitting layer; and
wherein the intermediate layer has a first pattern overlapping the portion of the plurality of first electrodes exposed by the pixel defining layer, a second pattern being sloped to confine at least a portion of the emitting layer, and a third pattern overlapping a portion of the substrate between adjacent first electrodes that are spaced apart from each other;
wherein a charge from each first electrode advances to the emitting layer through the first pattern;
wherein at least one of the second and third patterns has a different property from a remaining portion of the intermediate layer;
wherein the different property is at least one selected from the group consisting of an electrical conductivity smaller than the first pattern, an electrical resistance greater than the first pattern, an ink-affinity smaller than the first pattern, and a surface energy smaller than the first pattern; and
wherein the at least one of the second and third patterns has a chemical element diffused from the pixel defining layer to be fixed in the at least one of the second and third patterns.

US Pat. No. 10,115,775

OLED DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS

BOE Technology Group Co.,...

1. A method for manufacturing an organic light-emitting diode (OLED) display device comprising:forming an array comprising first electrodes on a base substrate, wherein an area to which the first electrodes correspond is a display area;
forming pixel defining layers in intervals, with each of the pixel defining layers disposed between two adjacent first electrodes so that a width of a cross section of each pixel defining layer is relatively larger at a middle portion and reduced gradually towards an upper portion and towards a lower portion, and a side surface of the lower portion of the pixel defining layer and an upper surface of the first electrode intersect with each other and form an angle smaller than 90° therebetween;
forming organic light-emitting layers respectively on the first electrodes between the pixel defining layers; and
forming a second electrode which is at least provided on the organic light-emitting layers,
wherein each of the pixel defining layers is a single-layered structure and made of a same material, and
a thickness of each of the organic light-emitting layers formed is not smaller than a height of a widest position at the middle portion of each of the pixel defining layers;
wherein the forming the pixel defining layers comprises:
forming a photoresist on the base substrate on which the first electrodes are formed;
irradiating light, which passes through a mask plate, on the photoresist at a predetermined first incident angle with respect to a direction perpendicular to the base substrate, to perform first exposure to the photoresist; and
irradiating light, which passes through the mask plate, onto the photoresist at a predetermined second incident angle with respect to the direction perpendicular to the base substrate, to perform second exposure to the photoresist, and developing to remove the photoresist corresponding to the display area and hence exposing the first electrodes, wherein lines in which an incident direction of the light in the first exposure is located and lines in which an incident direction of the light in the second exposure is located are respectively arranged on opposite sides of normal lines which respectively pass through centers of the first electrodes exposed, so that the width of the cross section of each pixel defining layer formed is relatively larger at the middle portion and reduced gradually towards the upper portion and towards the lower portion, and the predetermined first incident angle and the predetermined second incident angle are both larger than 0° and smaller than 90°.

US Pat. No. 10,115,773

HYBRID HIGH ELECTRON MOBILITY TRANSISTOR AND ACTIVE MATRIX STRUCTURE

International Business Ma...

1. A high electron mobility field-effect transistor comprising:an inorganic semiconductor layer;
a gate electrode;
first and second ohmic contacts operatively associated with the inorganic semiconductor layer, and
an organic gate barrier layer operatively associated with the gate electrode, the organic gate barrier layer being positioned between the gate electrode and the inorganic semiconductor layer and including one or more organic semiconductor layers operative to block electrons and holes.

US Pat. No. 10,115,772

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device comprising a resistance random access memory in which transistors and resistance change elements that are coupled in series to the transistors are arranged over a semiconductor substrate,wherein the resistance change element comprises a first electrode that applies a positive voltage when being transited from a low resistance state to a high resistance state, a second electrode that faces the first electrode, and a resistance change layer that is sandwiched between the first electrode and the second electrode and comprises an oxide of transition metal,
wherein the resistance change layer contains nitrogen, and
wherein the concentration of nitrogen on the first electrode side in the resistance change layer is higher than that on the second electrode side,
wherein the concentration of nitrogen contained in the resistance change layer continuously declines from the first electrode side to either: the second electrode side, or a distance from the first electrode side at which the concentration of nitrogen reaches approximately zero.

US Pat. No. 10,115,771

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a substrate;
a first wiring extending in a first direction;
a second wiring being provided between the substrate and the first wiring extending in the first direction, the second wiring being located away from the first wiring in a second direction crossing the first direction and perpendicular to the substrate;
a third wiring being provided between the first wiring and the second wiring, the third wiring extending in a third direction crossing the first and the second directions, the third direction being parallel to the substrate;
a first variable resistance element being provided between the first wiring and the third wiring;
a second variable resistance element being provided between the second wiring and the third wiring;
a first contact extending in the second direction, one end of the first contact being connected to the first wiring, and a length between the first contact and the third wiring in the first direction being a first length and a length between the first contact and the second wiring in the first direction being a second length shorter than the first length;
a second contact being located below the second wiring in the second direction, one end of the second contact being connected to the other end of the first contact, and the second contact extending in the second direction; and
a third contact being connected to the second wiring, the third contact extending in the second direction, and a length between the second contact and the third contact in the first direction being a third length longer than the second length.

US Pat. No. 10,115,770

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NONVOLATILE MEMORY

SanDisk Technologies LLC,...

1. A method comprising:forming a dielectric material and a first sacrificial material above a substrate;
forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material;
forming a first hole in the second sacrificial material, the first hole disposed in a first direction;
forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction;
forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole;
forming a second hole in the second sacrificial material;
forming a second portion of the nonvolatile memory material on a sidewall of the second hole;
forming a local bit line in the second hole; and
forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer, wherein the method further comprising: forming a plurality of alternating dielectric material layers and first sacrificial material layers above the substrate and disposed adjacent the second sacrificial material; forming a plurality of word line layers above the substrate via the first hole, each of the plurality of word line layers disposed in the second direction; and forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the local bit line and a corresponding one of the word line layers.

US Pat. No. 10,115,769

RESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

MACRONIX INTERNATIONAL CO...

1. A resistive random access memory (ReRAM) device, comprising:a first dielectric layer disposed on a substrate and covering a gate oxide structure on the substrate, and the first dielectric layer comprising:
a first insulating layer disposed on the substrate; and
a stop layer disposed on the first insulating layer and directly contacting a top surface of the gate oxide structure, wherein the stop layer is a hydrogen controlled layer;
a first conductive connecting structure disposed on the substrate and penetrating the first dielectric layer; and
a ReRAM unit disposed on the first conductive connecting structure.

US Pat. No. 10,115,768

LIGHT EMITTING DEVICE AND DISPLAY DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a first light emitting element to emit from a first front surface a first light having a peak wavelength in a range from 440 nm to 485 nm, the first front surface having a polygonal shape with five or more sides and being substantially perpendicular to a front-rear direction of the light emitting device;
a second light emitting element to emit from a second front surface a second light having a peak wavelength in a range from 495 nm to 573 nm, the second front surface having a polygonal shape with five or more sides and being substantially perpendicular to the front-rear direction;
a third light emitting element including a third front surface, a bottom surface opposite to the third front surface in the front-rear direction, and a side surface connecting the third front surface and the bottom surface, the third light emitting element being configured to emit from the third front surface a third light having a peak wavelength in a range from 440 nm to 485 nm, the third front surface having a polygonal shape with five or more sides and being substantially perpendicular to the front-rear direction;
a fluorescent material provided on the third front surface of the third light emitting element and having a fluorescent side surface extending along the front-rear direction;
a film provided to surround the side surface of the third light emitting element and the fluorescent side surface of the fluorescent material;
a first lens provided over the first front surface of the first light emitting element;
a second lens provided over the second front surface of the second light emitting element; and
a third lens provided over the third front surface of the third light emitting element, the film being provided between the third light emitting element and the third lens.

US Pat. No. 10,115,767

DUAL LIGHT EMISSION MEMBER, DISPLAY APPARATUS HAVING THE SAME AND LIGHTING APPARATUS HAVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a substrate comprising:
a first area at which an image is displayed in a first direction with light, and
a second area at which an image is displayed in a second direction opposite to the first direction with light, wherein a portion of the substrate at the second area is light-transmissive;
a first light-emitting member on the substrate and disposed in the first area of the substrate; and
a lens commonly disposed over the first area and the second area of the substrate so as to cover the first light-emitting member,
wherein
at the first area, the light with which the image is displayed in the first direction passes through the lens, and
at the second area, the light with which the image is displayed in the second direction opposite to the first direction passes through the substrate.

US Pat. No. 10,115,766

STRETCHABLE DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a plurality of light-emitting diodes;
a stretchable substrate comprising:
a flat portion including a flat surface; and
a plurality of protrusions protruding from the flat portion, wherein each of the protrusions is stretchable and has an inclined surface with respect to the flat surface, and at least some light-emitting diodes of the plurality of light-emitting diodes are disposed on the inclined surface, wherein an inclination angle of the inclined surface is variable with respect to extension or reduction of the stretchable substrate; and
a plurality of thin film transistors disposed inside the stretchable substrate and connected to the light-emitting diodes.

US Pat. No. 10,115,765

X-RAY FLAT-PANEL DETECTOR AND METHOD FOR PREPARING THE SAME, AND WHITE INSULATING MATERIAL

BOE TECHNOLOGY GROUP CO.,...

1. An X-ray flat-panel detector, comprising:a thin-film transistor substrate;
an insulating reflection layer, which is provided on the thin-film transistor substrate and has a diffuse reflection function, wherein the insulating reflection layer is provided with a contact hole through which a source electrode of the thin-film transistor substrate is exposed, the insulating reflection layer being made of a white insulating material containing, by weight percentage, 80%-98% of a resin matrix and 2%-20% of a light-beam diffuse reflection functional material powder;
a pixel electrode, which is provided on the insulating reflection layer, wherein the pixel electrode is electrically connected to the source electrode of the thin-film transistor substrate via the contact hole;
a photodiode, which covers the pixel electrode;
an electrode, which is provided on the photodiode; and
an X-ray conversion layer, which is provided on the electrode.

US Pat. No. 10,115,764

MULTI-BAND POSITION SENSITIVE IMAGING ARRAYS

RAYTHEON COMPANY, Waltha...

1. A light detection device, comprising:a first array of pixels formed from a first layer of semiconductor material having a bandgap corresponding to a first range of wavelengths, the first array of pixels disposed along a focal plane, each pixel of the first array of pixels configured as a position sensing pixel and to output one or more first signals in proportion to a position of photons incident thereon that are within the first range of wavelengths, the one or more first signals referenced to a ground common;
a first contact disposed on at least a portion of each pixel of the first array of pixels;
at least one barrier layer disposed on a surface of the first layer of semiconductor material;
a second array of pixels monolithically formed on the first array of pixels and formed from a second layer of semiconductor material disposed on a first portion of a surface of the at least one barrier layer, the second layer of semiconductor material having a bandgap corresponding to a second range of wavelengths different from the first range of wavelengths, the second array of pixels disposed along the focal plane, each pixel of the second array of pixels configured as an image sensing pixel and to generate one or more second signals in proportion to a number of photons incident thereon that are within the second range of wavelengths, the one or more second signals referenced to the ground common, wherein the pixels of the second array are sized to be smaller than the pixels of the first array;
a second contact disposed on at least a portion of each pixel of the second array of pixels; and
a third contact disposed on a second portion of the surface of the at least one barrier layer,
wherein the second array of pixels are formed on and disposed outwardly from the first array of pixels such that a plurality of pixels of the second array are associated with and spatially co-registered along the same axis of an optical path of incident photons with each pixel of the first array of pixels, the first and second arrays of pixels arranged along respective planes that are parallel to each other and to the focal plane and that are perpendicular to the optical path, such that the incident photons travel along the optical path from the first array of pixels to the second array of pixels.

US Pat. No. 10,115,763

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A semiconductor device, comprising:a first substrate including a pixel array and first connection pads;
a second substrate bonded to the first substrate, the second substrate including second connection pads and a logic circuit for driving the pixel array, wherein the first connection pads are located at a different level in the semiconductor device than the second connection pads; and
connection wirings that electrically connect the first connection pads to the second connection pads,
wherein, in a plan view, pairs including one of the first connection pads and one of the second connection pads form a connection pad array, and
wherein, in the plan view, at least one of the first connection pads partially overlaps at least one of the second connection pads.

US Pat. No. 10,115,762

SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF MANUFACTURING THEREOF, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A solid-state image pickup device comprising:a plurality of pixels, each of which includes a photoelectric conversion portion and a pixel transistor formed in a front surface side of a substrate, wherein a rear surface side of the substrate is set as a light receiving plane of the photoelectric conversion portion; and
an element, which becomes a passive element or an active element, which is disposed in the front surface side of the substrate so as to be superimposed on the photoelectric conversion portion.

US Pat. No. 10,115,761

SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF

Sony Semiconductor Soluti...

1. An imaging device comprising:a gate electrode of a first transfer transistor between a floating diffusion unit and a first photoelectric conversion region;
a gate electrode of a second transfer transistor between the floating diffusion unit and a second photoelectric conversion region;
a gate electrode of a selection transistor between a first semiconductor region and a second semiconductor region;
a gate electrode of an amplification transistor between the second semiconductor region and a third semiconductor region; and
an element separation region adjacent to the first photoelectric conversion region,
wherein the gate electrode of the first transfer transistor extends over a part of the element separation region, and
wherein the first photoelectric conversion region includes a first portion having a first conductivity-type and a second portion having a second conductivity-type.

US Pat. No. 10,115,760

PIXEL CELL AND ITS METHOD FOR APPLYING VOLTAGE GENERATED IN A PHOTOSENSOR TO A GATE CAPACITANCE AND ALTERNATELY RESETTING THE APPLIED VOLTAGE

Fraunhofer-Gesellschaft z...

1. A pixel cell, comprising:an output;
a photosensor designed in order to generate as a function of a radiation in a first measurement cycle a first measurement current and in a second measurement cycle a second measurement current;
an output node;
a current storage device designed so that in a first operating mode a current can be impressed by the current storage device as a function of the first measurement current and that in a second operating mode the current storage device is designed to hold the impressed current so that the impressed current can be recorded at the output node; and
a switching unit designed in order to form in a readout cycle a difference of the impressed current and the second measurement current at the output node and to couple the output node to output.

US Pat. No. 10,115,758

ISOLATION STRUCTURE FOR REDUCING CROSSTALK BETWEEN PIXELS AND FABRICATION METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a semiconductor device, the method comprising:forming a first trench in a semiconductor substrate;
forming a dielectric layer covering the semiconductor substrate, wherein the dielectric layer has a trench portion located in the first trench of the semiconductor substrate;
forming a reflective material layer on the trench portion of the dielectric layer; and
etching the reflective material layer to form an isolation structure, wherein the isolation structure comprises a bottom portion in a second trench formed by the trench portion of the dielectric layer and a top portion located on the bottom portion of the isolation structure, wherein a top surface of the top portion of the isolation structure is in a position higher than a top surface of the semiconductor substrate.

US Pat. No. 10,115,757

IMAGE SENSOR AND ELECTRONIC DEVICE HAVING THE SAME

SK Hynix Inc., Gyeonggi-...

1. An image sensor comprising:a substrate comprising a photoelectric conversion element;
a pixel lens formed over the substrate and comprising a plurality of light condensing layers in which a lower layer has a larger area than an upper layer;
a color filter layer covering an entire surface of the pixel lens; and
an anti-reflection structure formed over the color filter layer, wherein the anti-reflection structure prevents reflection of incident light,
wherein each of the plurality of light condensing layers has a flat surface, and the lower layer exposed by the upper layer has a smaller width than the wavelength of the incident light, and
wherein the upper layer has a smaller effective refractive index than the lower layer, and the upper layer and the lower layer are formed of a same material.

US Pat. No. 10,115,756

SOLID-STATE IMAGE PICKUP DEVICE AND IMAGE PICKUP SYSTEM HAVING LIGHT SHIELDING PORTION WITH FIRST AND SECOND FILMS ON RESPECTIVE UNDER FACE AND UPPER FACE SIDES

CANON KABUSHIKI KAISHA, ...

1. A solid-state image pickup device, comprising:an image pickup pixel having a first photoelectric conversion portion and a first transistor for reading out a signal based on a charge generated in the photoelectric conversion portion;
a focus detection pixel having a second photoelectric conversion portion, a second transistor for reading out a signal based on a charge generated in the second photoelectric conversion portion, and a light shielding portion formed in a first wiring layer and having an opening, the second photoelectric conversion portion having a light receiving face that receives light through the opening;
a first film containing titanium and being provided on an under face side of the light shielding portion and not extending through the opening;
a second film containing titanium nitride and being provided on an upper face side of the light shielding portion and not extending through the opening and below a first insulating film, the upper face side being positioned farther apart from the light receiving face than from the under face side;
a third film containing titanium and being provided between the first film and the second photoelectric conversion portion; and
a wiring line for the first transistor and the second transistor provided above the first transistor and the second transistor,
wherein a thickness of the second film is larger than that of the first film in height direction,
wherein the wiring line and a structure having the light shielding portion, the first film, the second film, and the third film are provided in the same layer, and
wherein the second film is formed between the light shielding portion and a second wiring layer above the first wiring layer.

US Pat. No. 10,115,755

SOLID-STATE IMAGE PICKUP DEVICE, IMAGE PICKUP SYSTEM USING SOLID-STATE IMAGE PICKUP DEVICE, AND METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE

Canon Kabushiki Kaisha, ...

1. A solid-state image pickup device comprising:a plurality of pixels, each of the plurality of pixels including:
a first transfer transistor configured to transfer carriers stored at a first semiconductor region of a first conductive type disposed in a substrate to a second semiconductor region of the first conductive type disposed in the substrate;
a second transfer transistor configured to transfer the carriers held at the second semiconductor region to a third semiconductor region of the first conductive type disposed in the substrate, and
an amplification transistor configured to output a signal based on a potential of the third semiconductor region; and
a metal film
including
a first bottom surface located above an upper surface of a gate electrode of the first transfer transistor,
a second bottom surface located above the first semiconductor region, and
a third bottom surface located above the second semiconductor region,
wherein
with respect to a distance in a direction perpendicular to a surface of the substrate, a first distance between the second bottom surface and the surface of the substrate and a second distance between the third bottom surface and the surface of the substrate are each smaller than a third distance between the upper surface of the gate electrode and the surface of the substrate.

US Pat. No. 10,115,754

IMAGE PICKUP DEVICE AND IMAGE PICKUP SYSTEM

CANON KABUSHIKI KAISHA, ...

1. An image pickup device, comprising:a pixel region including a plurality of pixels;
a well region in which the plurality of pixels are provided;
first and second well wires configured to supply a potential to the well region, the first and second well wires being arranged in the pixel region;
first and second well contacts connected to the well region, the first and second well contacts being connected in the first well wire at a first interval; and
third and fourth well contacts connected to the well region, the third and fourth well contacts being connected in the second well wire at a second interval larger than the first interval,
a number of pixels arranged in the second interval is larger than a number of pixels arranged in the first interval.

US Pat. No. 10,115,752

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A solid-state imaging device comprising:a pixel array unit including a plurality of pixels, wherein the plurality of pixels are in a two-dimensionally array in the pixel array unit,
wherein each pixel of the plurality of pixels comprises:
a first photoelectric conversion unit configured to generate a signal charge based on light absorbed of a first color component; and
a second photoelectric conversion unit configured to generate a signal charge that corresponds to an amount of incident light,
wherein the second photoelectric conversion unit comprises a photodiode, and
wherein the plurality of pixels comprise:
a first pixel configured to:
photoelectrically convert light of the first color component with the first photoelectric conversion unit, and
photoelectrically convert light of a third color component with the second photoelectric conversion unit,
wherein the light of the third color component passes through a first color filter and the first photoelectric conversion unit, and
wherein light of a second color component passes through the first color filter;
a second pixel configured to:
photoelectrically convert the light of the first color component with the first photoelectric conversion unit, and
photoelectrically convert light of a fifth color component with the second photoelectric conversion unit,
wherein the light of the fifth color component passes through a second color filter and the first photoelectric conversion unit,
wherein light of a fourth color component passes through the second color filter; and
a third pixel configured to:
photoelectrically convert the light of the first color component with the first photoelectric conversion unit, and
photoelectrically convert light of a sixth color component with the second photoelectric conversion unit,
wherein the light of the sixth color component passes through the first photoelectric conversion unit; and
wherein the first color component and the sixth color component are mixed to generate white (W),
wherein:
 the first color filter and the second color filter are below the first photoelectric conversion unit on a light incident side;
 the first color component is green (G);
 the second color component is red (R);
 the third color component is red (R);
 the fourth color component is blue (B);
 the fifth color component is blue (B); and
 the sixth color component is magenta (Mg).

US Pat. No. 10,115,751

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a pixel which includes:
first and second active regions each formed in a first main surface of a semiconductor substrate and surrounded by an isolation region in plan view;
a photodiode formed in the first active region; and
a transfer transistor formed in the first active region to transfer charges generated by the photodiode,
wherein, in the semiconductor substrate, a p-type semiconductor region is formed so as to include the first and second active regions in plan view,
wherein, over the p-type semiconductor region in the second active region, a contact portion for supplying a grounding potential is formed and electrically coupled to the p-type semiconductor region,
wherein the photodiode has a first n-type semiconductor region which is formed in the p-type semiconductor region in the first active region,
wherein the transfer transistor has a second n-type semiconductor region which is formed in the p-type semiconductor region in the first active region to function as a drain region of the transfer transistor,
wherein the first n-type semiconductor region functions also as a source region of the transfer transistor, and
wherein, in the second n-type semiconductor region, a gettering element is introduced while, in the p-type semiconductor region in the second active region, the gettering element is not introduced.

US Pat. No. 10,115,750

SENSORS INCLUDING COMPLEMENTARY LATERAL BIPOLAR JUNCTION TRANSISTORS

International Business Ma...

1. A method of fabricating a sensor for detecting radiation comprising:obtaining a substrate including a substrate layer, a semiconductor layer, and an electrically insulating layer between and adjoining the substrate layer and the semiconductor layer;
forming a first lateral bipolar junction transistor having a first polarity on said substrate, the first lateral bipolar junction transistor being configured to generate an output signal indicative of a change in stored charge in the electrically insulating layer resulting from ionizing radiation;
forming a second lateral bipolar junction transistor having a second polarity opposite to the first polarity on said substrate, the second bipolar junction transistor being configured to amplify the output signal of the first bipolar junction transistor, the first and second bipolar junction transistors being formed adjacent to one another on the substrate, and
forming an electrical connection between an output terminal of the first lateral bipolar junction transistor and a base of the second lateral bipolar junction transistor.

US Pat. No. 10,115,749

ARRAY SUBSTRATES AND THE MANUFACTURING METHOD THEREOF

Wuhan China Star Optoelec...

1. A manufacturing method of array substrates, comprising:depositing a conductive layer on a substrate, and forming three poles of at least one thin film transistor (TFT), a first signal line, and a second signal line by etching the conductive layer via a first mask, wherein the first signal line comprises a first portion and a second portion respectively at two sides of the second signal line;
depositing an intermediate layer in sequence, and forming a first connecting bridge connecting the first portion and the second portion by etching the intermediate layer via a second mask; and
depositing a conductive electrode, and forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via a third mask.

US Pat. No. 10,115,748

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURE METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE

Shenzhen China Star Optoe...

1. A manufacture method of a thin film transistor array substrate, wherein the manufacture method of the thin film transistor array substrate comprises:providing a substrate, and the substrate comprises a first surface and a second surface, which are oppositely located;
forming a gate, and the gate is located on the first surface;
forming a first insulative layer, and the first insulative layer covers on the gate;
forming a metal oxide semiconductor layer on the first insulative layer;
implementing ion implantation to two end regions of the metal oxide semiconductor layer, and the two end regions of the metal oxide semiconductor layer after the ion implantation respectively are a source and a drain, and a region of the metal oxide semiconductor layer without the ion implantation is an active layer;
forming a second insulative layer, and the second insulative layer covers the source, the drain and the active layer;
opening a via employed to expose the source or the drain in the second insulative layer;
forming a pixel electrode, and the pixel electrode is located on the second insulative layer, and is connected with the source or the drain through the via;
wherein the step of opening a via employed to expose the source or the drain in the second insulative layer comprises:
opening a first via and a second via in the second insulative layer, and the first via is located corresponding to the source, and the second via is located corresponding to the drain;
correspondingly, the step of forming a pixel electrode, and the pixel electrode is located on the second insulative layer, and is connected with the source or the drain through the via comprises:
forming a pixel electrode, and the pixel electrode is located on the second insulative layer, and the pixel electrode is connected with the drain through the second via;
the manufacture method of the thin film transistor array substrate further comprises:
forming a first electrode, and the first electrode is connected with the source through the first via;
wherein the step of opening a first via and a second via in the second insulative layer, and the first via is located corresponding to the source, and the second via is located corresponding to the drain comprises:
covering the second insulative layer with a second photoresist layer;
patterning the second photoresist layer to remove the second photoresist layer correspondingly right above the source and the drain to expose a portion of the second photoresist layer;
employing the patterned second photoresist layer as a mask to etch the second photoresist layer to open the first via and the second via in the second insulative layer;
stripping the second photoresist layer; and
wherein the pixel electrode and the first electrode are manufactured in the same process:
forming a transparent conductive layer, and the transparent conductive layer covers the second insulative layer, the source and the drain;
patterning the transparent conductive layer to preserve the transparent conductive layer located on the source and the drain, and a transparent conductive layer connected with the transparent conductive layer located on the drain, wherein the transparent conductive layer located on the source is the first electrode, and the transparent conductive layer located on the drain is the pixel electrode.

US Pat. No. 10,115,747

METHOD OF PRODUCING COMPONENT BOARD

SHARP KABUSHIKI KAISHA, ...

1. A method of producing a component board comprising:a separation film forming process for forming a separation film on a supporting substrate;
a component support forming process for forming a component support for forming a component support on the separation film;
a thin film component forming process for forming a thin film component on the component support;
a light applying process for applying light to the separation film for accelerating a removal of the component support;
a determining process for determining whether a degree of adhesion between the separation film and the component support is high or low based on image data obtained through capturing of an image of the separation film; and
a removing process for removing the component support from the supporting substrate if the degree of adhesion is determined low in the determining process.

US Pat. No. 10,115,745

TFT ARRAY SUBSTRATE AND METHOD OF FORMING THE SAME

Shenzhen China Star Optoe...

1. A method of forming a thin-film transistor (TFT) array substrate, comprising:forming a semi-conductor layer on a substrate, wherein the semi-conductor layer is a single continuous layer of a semi-conductor material formed on the substrate;
forming a gate insulating layer on the semi-conductor layer, such that the gate insulating layer covers a first part of the semi-conductor layer with a second part of the semi-conductor layer being exposed as being not covered by the gate insulating layer, wherein the first part and the second part are both integral parts of the semi-conductor layer and adjoin each other;
forming a gate electrode on the gate insulating layer;
forming an ILD layer on the semi-conductor layer so as to cover the gate insulating layer and the gate electrode, wherein the ILD layer comprises a SiNx layer that is in direct contact with the second part of the semi-conductor layer;
annealing the ILD layer so that hydrogen in the ILD layer is diffused into the second part of the semi-conductor layer to form a pixel electrode with the second part of the semi-conductor layer that is not covered by the gate insulating layer;
forming contact holes in the ILD layer and the gate insulating layer so as to expose spaced portions of the first part of the semi-conductor layer, and forming an opening in the ILD layer so as to expose a portion of the pixel electrode; and
forming a source electrode and a drain electrode on the ILD layer, wherein the source electrode electrically connects the semi-conductor layer through a first one of the contact holes, and the drain electrode electrically connects the semi-conductor layer and pixel electrode through a second one of the contact holes and the opening, respectively;
wherein the second part of the semi-conductor layer that is diffused with hydrogen of the ILD layer is an integral part of the semi-conductor layer and is in direct contact and connection with the first part of the semi-conductor layer so that the pixel electrode is directly connected to the first part of the semi-conductor layer that is not diffused with hydrogen.

US Pat. No. 10,115,743

ANALOG CIRCUIT AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor;
a second transistor comprising an oxide semiconductor layer including a channel region;
a third transistor;
an insulating layer including an opening over the first transistor, the second transistor, and the third transistor;
a color filter over the insulating layer;
a light-emitting element including a first electrode over the color filter; and
a capacitor;
a signal line; and
a power supply line;
wherein one of a source and a drain of the first transistor is directly connected to the signal line,
wherein the other one of the source and the drain of the first transistor is directly connected to a gate of the second transistor and one terminal of the capacitor,
wherein the other one terminal of the capacitor is directly connected to one of the source and the drain of the second transistor, one of a source and a drain of the third transistor, and the light-emitting element,
wherein the other one of the source and the drain of the second transistor is directly connected to the power supply line,
wherein the opening does not overlap with the color filter and an edge portion of the opening does not align with an edge portion of the color filter,
wherein the oxide semiconductor layer comprises In, Ga, and Zn, and
wherein the first electrode is directly connected to the one of the source and the drain of the second transistor through the opening.

US Pat. No. 10,115,742

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A transistor comprising:a first gate electrode;
an oxide semiconductor film, the oxide semiconductor film including a drain region;
a second gate electrode;
an insulating film over the oxide semiconductor film, the insulating film including an opening; and
a drain electrode over the insulating film, the drain electrode being in contact with the drain region in the opening,
wherein the first gate electrode and the second gate electrode are electrically connected to each other,
wherein, under a first condition, a difference between a minimum value and a maximum value of field-effect mobility of the transistor is less than or equal to 15 cm2/Vs, and
wherein the first condition is that voltages applied to the first gate electrode and the second gate electrode are in a range from 3 V to 10 V and a voltage applied to the drain region of the oxide semiconductor film is 20 V.

US Pat. No. 10,115,741

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first circuit comprising a first transistor and a capacitor electrically connected to a drain of the first transistor; and
a second circuit comprising a second transistor and a node electrically connected to a gate of the second transistor,
wherein:
the first transistor comprises a first semiconductor layer and a first back gate,
the second transistor comprises a second semiconductor layer,
the first circuit is configured to write data by turning on the first transistor, and to retain the data in the capacitor by turning off the first transistor,
the second circuit is configured to supply a potential at which the first transistor is turned off to the first back gate by turning on the second transistor, and to retain the potential in the node by turning off the second transistor, and
a threshold voltage of the second transistor is higher than a threshold voltage of the first transistor when a potential of the first back gate is set to the same as a potential of a source or a gate of the first transistor.

US Pat. No. 10,115,739

DISPLAY UNIT AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A display unit, comprising:a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor,
wherein one channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.

US Pat. No. 10,115,737

CHARGE STORAGE REGION IN NON-VOLATILE MEMORY

SanDisk Technologies LLC,...

1. A memory cell, comprising:a semiconductor channel;
a tunnel dielectric;
a charge storage region comprising: a first p-type silicon region adjacent the tunnel dielectric, a second p-type silicon region, an n-type silicon region between the first and second p-type silicon regions, a first dielectric region between the first p-type silicon region and the n-type silicon region, a second dielectric region between the n-type silicon region and the second p-type silicon region;
a conductive control gate; and
a control gate dielectric between the control gate and the charge storage region, the charge storage region being between the tunnel dielectric and the control gate dielectric, the second p-type silicon region being adjacent to the control gate dielectric.

US Pat. No. 10,115,736

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NAND NON-VOLATILE MEMORY DEVICES WITH SIDE SOURCE LINE AND MECHANICAL SUPPORT

SanDisk Technologies LLC,...

1. A method of fabricating a monolithic three dimensional memory structure, the method comprising:forming a stack of alternating word line and dielectric layers above a substrate;
forming a source line above the substrate;
forming a memory hole extending through the alternating word line and dielectric layers and the source line; and
forming a mechanical support element on the substrate adjacent to the memory hole, the mechanical support element extending through the source line.

US Pat. No. 10,115,735

SEMICONDUCTOR DEVICE CONTAINING MULTILAYER TITANIUM NITRIDE DIFFUSION BARRIER AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A semiconductor device, comprising:a silicon surface;
a titanium silicide layer contacting the silicon surface;
a first titanium nitride layer located over the titanium silicide layer;
a titanium oxynitride layer contacting the first titanium nitride layer;
a second titanium nitride layer contacting the titanium oxynitride layer; and
a metallic fill material portion located over the second titanium nitride layer.

US Pat. No. 10,115,733

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a connecting member having a through hole;
a first insulating film provided on the connecting member;
a stacked body provided on the first insulating film, the stacked body including electrode films and second insulating films, each of the electrode films and each of the second insulating films being alternately stacked;
a semiconductor pillar extending in a stacking direction of the electrode films and the second insulating films, piercing through the stacked body and the first insulating film, the semiconductor pillar being electrically connected to the connecting member;
a third insulating film provided between the semiconductor pillar and the stacked body; and
a support portion disposed in the through-hole of the connecting member.

US Pat. No. 10,115,732

THREE DIMENSIONAL MEMORY DEVICE CONTAINING DISCRETE SILICON NITRIDE CHARGE STORAGE REGIONS

SANDISK TECHNOLOGIES LLC,...

1. A structure comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
a memory stack structure extending through a memory opening in the alternating stack and comprising memory elements laterally surrounding a vertical semiconductor channel, wherein:
each of the memory elements comprise, from outside to inside, a blocking dielectric portion that is a region of a continuous blocking dielectric layer, a charge trapping material portion having a vertical sidewall portion and comprising silicon nitride, and a tunneling dielectric portion that is a region of a continuous tunneling dielectric layer directly contacting the continuous blocking dielectric layer, wherein a continuous interface between the continuous blocking dielectric layer and the alternating stack vertically extends through multiple electrically conductive layers of the alternating stack, and a continuous interface between the continuous tunneling dielectric layer and the vertical semiconductor channel vertically extends through the multiple electrically conductive layers of the alternating stack;
each of the insulating layers includes an upper recessed annular rim, a lower recessed annular rim, and an annular center portion located between the upper and lower recessed annular rims, wherein the annular center portion protrudes inward toward a vertical axis of the memory opening relative to the upper and lower recessed rims; and
each of the charge trapping material portions is vertically spaced from one another, and does not contact any other of the charge trapping material portions.

US Pat. No. 10,115,731

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer;
a stacked body including a plurality of electrode layers stacked on the interconnect layer,
a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and
an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body,
the semiconductor layer including a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region being in contact with the conductive layer.

US Pat. No. 10,115,730

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING STRUCTURALLY REINFORCED PEDESTAL CHANNEL PORTIONS AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface;
a memory opening extending through the alternating stack;
a pedestal channel portion located at a bottom portion of the memory opening, comprising a semiconductor material, and contacting a top surface of the semiconductor surface; and
a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion, wherein the memory stack structure comprises a memory film and a vertical semiconductor channel located inside the memory film,
wherein:
a maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure, the entire interface includes all surfaces at which the pedestal channel portion directly contacts the memory stack structure; and
the maximum lateral extent of the pedestal channel portion is provided above a horizontal plane including a top surface of the bottommost electrically conductive layer among the electrically conductive layers or below a horizontal plane including a bottom surface of a bottommost electrically conductive layer.

US Pat. No. 10,115,728

LASER SPIKE ANNEALING FOR SOLID PHASE EPITAXY AND LOW CONTACT RESISTANCE IN AN SRAM WITH A SHARED PFET AND NFET TRENCH

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device, the method comprising:forming a first semiconductor fin opposite a surface of a substrate;
forming a second semiconductor fin opposite the surface of the substrate and adjacent to the first semiconductor fin;
prior to forming a replacement metal gate (RMG), forming a first doped region over portions of the first semiconductor fin and a second doped region over portions of the second semiconductor fin;
forming a dielectric layer over the first and second doped regions;
after forming the RMG, forming a shared trench in the dielectric layer exposing portions of the first and second doped regions;
concurrently amorphizing the exposed first and second doped regions; and
concurrently recrystallizing the amorphized first and second doped regions.

US Pat. No. 10,115,727

METHOD FOR MANUFACTURING A MICROELECTRONIC CIRCUIT AND CORRESPONDING MICROELECTRONIC CIRCUIT

Fraunhofer-Gesellschaft z...

1. A method for manufacturing a microelectronic circuit, comprising:providing a substrate,
producing a source contact, a bulk contact and a drain contact each for a transistor and for a memory transistor,
producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,
producing, in a common step, a metal layer of the transistor and a metal layer of the memory transistor,
producing the metal layer and the insulating layer of the memory transistor as parts of a MOS capacitor,
producing at least one capacitor as part of the memory transistor,
producing a gate contact connected to the metal layer of the transistor, and
producing a gate contact connected to a metal layer of the capacitor of the memory transistor.

US Pat. No. 10,115,726

METHOD AND SYSTEM FOR FORMING MEMORY FIN PATTERNS

Tokyo Electron Limited, ...

1. A method for patterning a substrate, the method comprising:forming a multi-line layer above a memorization layer on a substrate, the multi-line layer including a region having a pattern of alternating lines of three materials that differ chemically from each other by having different etch resistivities relative to each other, the three materials include material A, material B, and material C, the pattern of alternating lines of three materials includes a repeating sequence of A-B-C-B-A-B-C-B in that materials alternate in a direction parallel to a working surface of the substrate, each line of material extending from a top surface of the multi-line layer to a bottom surface of the multi-line layer;
forming a first etch mask above the multi-line layer, the first etch mask defining first trenches that uncover a first portion of the multi-line layer such that defined first trenches elevationally intersect multiple lines from the pattern of alternating lines;
etching through uncovered portions of material A and portions of the memorization layer directly underneath the uncovered portions of material A using the first etch mask;
forming a second etch mask above the multi-line layer, the second etch mask defining second trenches that uncover a second portion of the multi-line layer such that defined second trenches elevationally intersect multiple lines from the pattern of alternating lines;
etching through uncovered portions of material C and portions of the memorization layer directly underneath the uncovered portions of material C using the second etch mask; and
etching through material B and portions of the memorization layer directly underneath material B while the multi-line layer is uncovered.

US Pat. No. 10,115,725

STRUCTURE AND METHOD FOR HARD MASK REMOVAL ON AN SOI SUBSTRATE WITHOUT USING CMP PROCESS

International Business Ma...

1. A device, comprising:a semiconductor-on-insulator (SOI) substrate having an SOI layer, a BOX layer and a substrate layer;
a pad nitride layer deposited on a top surface of the SOI layer;
a trench formed in the SOI substrate, wherein the trench extends into the substrate layer;
a node dielectric layer deposited on a bottom and sidewalls of the first trench;
a liner layer deposited on the node dielectric layer;
a first conductive material deposited in the trench, wherein a top surface of the first conductive material is below a bottom surface of the SOI layer and above a top surface of the substrate layer, wherein a top surface of the node dielectric layer and a top surface of the liner layer are coplanar with the top surface of the first conductive material; and
a second conductive material deposited on the top surface of the first conductive material, wherein a top surface of the second conductive material is below the top surface of the SOI layer and below a bottom surface of the pad nitride layer.

US Pat. No. 10,115,724

DOUBLE DIFFUSION BREAK GATE STRUCTURE WITHOUT VESTIGIAL ANTENNA CAPACITANCE

International Business Ma...

1. A semiconductor structure comprising:a double diffusion break region located between a first device region and a second device region, wherein the double diffusion break region includes a sacrificial gate material and wherein an interlevel dielectric material is present adjacent to each side of the sacrificial gate material and beneath at least a portion of the sacrificial gate material.

US Pat. No. 10,115,723

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES EMPLOYING PLASMA-DOPED SOURCE/DRAIN STRUCTURES AND RELATED METHODS

QUALCOMM Incorporated, S...

1. A complementary metal oxide semiconductor (CMOS) device, comprising:a substrate;
a semiconductor material structure disposed above the substrate, the semiconductor material structure comprising one or more channel structures, each channel structure comprising:
a semiconductor material having a first end portion and a second end portion;
a source in the first end portion, the source comprising a first plasma-doped portion comprising a dopant above a solid state solubility of the semiconductor material structure of the semiconductor material at the first end portion;
a drain in the second end portion of the semiconductor material, the drain comprising a second plasma-doped portion comprising a dopant above the solid state solubility of the semiconductor material structure of the semiconductor material at the second end portion; and
a channel disposed between the source and the drain; and
a gate material disposed adjacent to the channel.

US Pat. No. 10,115,716

DIE BONDING TO A BOARD

SEMICONDUCTOR COMPONENTS ...

1. A method of bonding a plurality of die having a plurality of metal layers on a die surface to a board or metal lead frame, comprising:placing a first die onto a solderable surface of the board or the metal lead frame, the first die comprising at least three metal layers, the board comprising one of a ceramic board or substrate board, or a metal lead frame wherein a top metal die layer is disposed against the solderable surface of the first die;
first reflowing at least one of first and second metal die layers of the first die at a first reflow temperature in a range of 220 degrees C. to 260 degrees C. for a first period to form a first alloy to create a bond between the first die and the board or metal lead frame; and
maintaining heat at the first reflow temperature for a second period to reflow the board or metal lead frame and the first and second metal die layers to form a second alloy
placing a second die onto the solderable surface of the board or the metal lead frame, the second die comprising at least three metal layers, wherein a top metal die layer is disposed against the solderable surface of the second die;
second reflowing at least one of first and second metal die layers of the second die at the first reflow temperature in the range of 220 degrees C. to 260 degrees C. for the first period to form the first alloy to create a bond between the second die and the board or metal lead frame; and
maintaining heat at the first reflow temperature for the second period to reflow the board or metal lead frame and the first and second metal die layers of the second die to form the second alloy,
wherein the first and second alloys have melting temperature temperatures that are higher than 260 degrees C.

US Pat. No. 10,115,715

METHODS OF MAKING SEMICONDUCTOR DEVICE PACKAGES AND RELATED SEMICONDUCTOR DEVICE PACKAGES

Micron Technology, Inc., ...

1. A method of fabricating a semiconductor device package, comprising:providing a fan out wafer comprising semiconductor-device-package locations at a base level, each semiconductor-device-package location comprising:
at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the at least two mutually spaced semiconductor dice and extending between adjacent semiconductor-device-package locations; and
electrically conductive traces extending over active surfaces of the at least two semiconductor dice and laterally beyond peripheries of the at least two semiconductor dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric material;
stacking laterally offset semiconductor dice on at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice;
electrically connecting the laterally offset semiconductor dice to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations by forming wire bonds extending from a respective bond pad of an overlying semiconductor die of the laterally offset semiconductor dice to an adjacent bond pad of an underlying semiconductor die of the laterally offset semiconductor dice and by forming a wire bond extending from a respective bond pad of a lowest semiconductor die of the laterally offset semiconductor dice to an adjacent via of the electrically conductive vias or to an adjacent trace of the electrically conductive traces; and
singulating the semiconductor-device-package locations having stacks of semiconductor dice thereon from the fan out wafer.

US Pat. No. 10,115,714

SEMICONDUCTOR DEVICE AND OPTICAL COUPLING DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a substrate having a first surface side and a second surface side opposite the first surface side, the first surface side including a first surface region at a first end of the substrate in a first direction and a second surface region on a second end of the substrate in the first direction opposite the first end;
a wiring pattern on the second surface side of the substrate;
a first terminal and a second terminal on the substrate in the first surface region;
a third terminal and a fourth terminal on the substrate in the second surface region;
a first semiconductor element having a first surface, the first semiconductor element being bonded to the substrate on the first surface side between the first and second surface regions;
a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element;
a first bonding wire connecting the first terminal and anode terminal of the second semiconductor element;
a second bonding wire connecting the second terminal and a cathode terminal of the second semiconductor element;
a third semiconductor element bonded to the substrate on the first surface side between the first semiconductor element and the second surface region;
a third bonding wire connecting the first semiconductor element and the third semiconductor element, the third bonding wire being connected to a pad on the first surface of the first semiconductor element;
a silicone gel covering an upper surface of the second semiconductor element and contacting a portion of the first surface of the first semiconductor device; and
a resin portion covering the silicone gel, the first semiconductor element, the third semiconductor element, the first bonding wire, the second bonding wire, the third bonding wire, the first surface region, and the second surface region, wherein
the resin portion has a durometer-measured hardness greater than a durometer-measured hardness of the silicone gel,
the first semiconductor element includes a light receiving element facing the first surface of the first semiconductor element,
the second semiconductor element includes a light emitting element that emits light at the lower surface of the second semiconductor element, and
the silicone gel is opaque at a wavelength of light emitted by the light emitting element.

US Pat. No. 10,115,713

OPTOELECTRONIC ASSEMBLY AND METHOD OF OPERATING AN OPTOELECTRONIC ASSEMBLY

OSRAM Opto Semiconductors...

1. An optoelectronic assembly comprising:a semiconductor chip comprising:at least one first component that emits a first electromagnetic radiation;
a first photosensitive component that controls the first component electrically connected in parallel with the first component and comprises a first radiation-sensitive region arranged in a beam path of the first electromagnetic radiation, wherein the first photosensitive component connected in parallel with the first component is an automatic control of the first component such that the photosensitive component connected in parallel with the first component results in the automatic control without needing to provide an associated open loop control, and the first component and the first photosensitive component are integrated into the semiconductor chip;
a first carrier on which the first component and the first photosensitive component are arranged, wherein on the first carrier a first contact region is configured, a second contact region electrically insulated from the first contact region is configured on the first carrier, the first component comprises a carrier layer and a functional layer deposited on the carrier layer, the carrier layer is configured in an electrically conductive manner, the first photosensitive component is arranged on the first component, a first electrical contact of the first component and a first electrical contact of the first photosensitive component are electrically coupled by a first contact pad, the first contact pad is electrically coupled to the first contact region by a first bond wire, a second electrical contact of the first component is arranged at a bottom side of the first component and is electrically and physically coupled to the second contact region, a second electrical contact of the first photosensitive component is physically connected to the electrically conductive carrier layer of the first component and is electrically coupled to the second contact region, and between the first component and the first photosensitive component and between the first contact pad and the carrier layer, an insulator is formed; and
at least a second component that emits a second electromagnetic radiation and comprises a second photosensitive component electrically connected in parallel with the second component and a second radiation-sensitive region, wherein the second radiation-sensitive region is arranged in the beam path of the second electromagnetic radiation, the second radiation-sensitive region of the second photosensitive component is arranged in the beam path of the first electromagnetic radiation, a second beam filter is arranged in the beam path between the first component and the second photosensitive component, the second beam filter blocking the first electromagnetic radiation, and the second photosensitive component is coated with a beam-filter material of the second beam filter, and
wherein the first radiation-sensitive region of the first photosensitive component is arranged outside of a beam path of the second electromagnetic radiation.

US Pat. No. 10,115,711

VERTICAL LIGHT EMITTING DIODE WITH MAGNETIC BACK CONTACT

International Business Ma...

1. A structure comprising:an opening located in a display substrate;
a first contact structure lining at least one sidewall of the opening and a bottom wall of the opening and present on a topmost surface of the display substrate;
a first magnetic material located on a portion of the first contact structure that is located on the bottom wall of the opening;
a second magnetic material located on a surface of the first magnetic material;
a vertical light emitting diode located on a surface of the second magnetic material and having a topmost surface that is located entirely below a topmost surface of the first contact structure that is located on the topmost surface of the display substrate; and
a pair of second contact structures, wherein one of the pair of second contact structures is in direct contact with a topmost surface of the vertical light emitting diode, and another of the pair of second contact structures is in direct contact with a surface of the first contact structure.

US Pat. No. 10,115,710

PACKAGE INCLUDING A PLURALITY OF STACKED SEMICONDUCTOR DEVICES, AN INTERPOSER AND INTERFACE CONNECTIONS

1. A package, comprising:a first dynamic random access memory (DRAM) semiconductor device, a second DRAM semiconductor device, and a third DRAM semiconductor device stacked in a first direction above a first surface of an interposer;
a first wiring formed in the interposer providing an electrical connection essentially orthogonal to and between the first surface and a second surface, opposite the first surface, of the interposer;
a first external connection formed on the second surface of the interposer, the first wiring electrically connected at a central portion of the first external connection, the first external connection configured to receive a first power supply potential;
the first DRAM semiconductor device includes a first through via, the first through via providing an electrical connection between a first surface and a second surface of the first DRAM semiconductor device;
the second DRAM semiconductor device includes a second through via, the second through via providing an electrical connection between a first surface and a second surface of the second DRAM semiconductor device;
the third DRAM semiconductor device includes a third through via, the third through via providing an electrical connection between a first surface and a second surface of the third DRAM semiconductor device;
a first interface connection formed between the first DRAM semiconductor device and the second DRAM semiconductor device providing an electrical connection between the first and second through vias;
a second interface connection formed between the second DRAM semiconductor device and the third DRAM semiconductor device providing an electrical connection between the second and third through vias;
a third interface connection formed between the interposer and the first DRAM semiconductor device providing an electrical connection between the first wiring and the first through via, the first wiring providing an electrical connection between the third interface connection and the first external connection;
a second wiring formed in the interposer providing an electrical connection essentially orthogonal to and between the first surface and the second surface, opposite the first surface, of the interposer; and
a second external connection formed on the second surface of the interposer, the second wiring electrically connected at a central portion of the second external connection, the second external connection configured to receive a first data signal.

US Pat. No. 10,115,709

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Micron Technology, Inc., ...

1. An apparatus, comprising:a first chip and a second chip; each of the first and second chips comprising:
a multilevel wiring structure including a first level wiring layer, a second level wiring layer and an insulating film between the first level wiring layer and the second level wiring layer; and
a redistribution wiring layer over the multilevel wiring structure, the redistribution wiring layer including a redistribution wiring and a pad electrically coupled to the redistribution wiring;
wherein the first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip, and the pad of the first chip faces the pad of the second chip; the pad of the first chip being vertically spaced from the pad of the second chip by an intervening insulative region; the redistribution wiring of the second chip being electrically coupled to the redistribution wiring of the first chip through a bonding region; the pad of the first chip being electrically coupled to the pad of the second chip through the redistribution wiring of the first chip and the redistribution wiring of the second chip; and
wherein:
the first redistribution wiring includes first bonding pads;
the second redistribution wiring includes second bonding pads;
the first bonding pads are not overlapped by the second chip;
the second bonding pads are not overlapped by the first chip; and
the first chip is shifted relative to the second chip by a distance “a”, wherein the bonding region includes a first coupling region from the first chip and second coupling region from the second chip; and wherein the first coupling region is offset from the pad of the first chip by a distance of a/2, and the second coupling region is offset from the pad of the second chip by the distance of a/2.

US Pat. No. 10,115,708

SEMICONDUCTOR PACKAGE HAVING A REDISTRIBUTION LINE STRUCTURE

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor chip having first bonding pads which are arranged in two rows on a middle portion of a first active surface;
a second semiconductor chip having substantially the same size as the first semiconductor chip, and having second bonding pads which are arranged in two rows on a middle portion of a second active surface;
redistribution lines formed on the first active surface, and corresponding to the first bonding pads, respectively, the redistribution lines each having a redistribution line pad, a wire bonding pad, and coupling lines electrically coupling the redistribution line pad, the wire bonding pad and the corresponding first bonding pad; and
bumps formed on the second bonding pads of the second semiconductor chip, respectively,
wherein the location of the second bonding pads in relation to the second semiconductor chip is the same as the location of the corresponding first bonding pads in relation to the first semiconductor chip,
wherein the first semiconductor chip and the second semiconductor chip are stacked such that the first active surface and the second active surface face each other, and are disposed to be offset from each other, and
wherein the bumps are bonded to the redistribution line pads of the redistribution lines, respectively.

US Pat. No. 10,115,707

ADHESIVE FILM AND SEMICONDUCTOR PACKAGE USING ADHESIVE FILM

FURUKAWA ELECTRIC CO., LT...

1. An adhesive film, which comprises: (A) a bismaleimide resin; (B) a radical initiator; and (C) a coupling agent that contains a (meth)acrylic group, wherein at least one of the following applies:(1) radical initiator (B) has a one-hour half-life temperature of 140° C. or higher, or
(2) a filler (D) is present, having a content of 75 percent or higher by mass based on 100 percent by mass in the adhesive film.

US Pat. No. 10,115,705

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor package comprising:a first semiconductor device electrically connected to a second semiconductor device, wherein:
the first semiconductor device comprises a first surface, and the first surface comprises at least a first portion and a second portion that does not overlap with the first portion, wherein the first portion is a portion of the first surface that is not under the second semiconductor device; a first encapsulant material surrounding side edges of the first semiconductor device; a first dielectric layer above the first encapsulant material and the first portion; at least one redistribution layer (RDL) above the first dielectric layer; a second dielectric layer above the at least one RDL and the second portion, wherein:
a maximum thickness of the second dielectric layer above the second portion and adjacent to the second semiconductor device is less than a sum of the thicknesses of the first dielectric layer above the first portion, the at least one RDL, and the second dielectric layer above the at least one RDL; and
a passivation layer directly above the first surface, wherein:
the passivation layer directly contacts both the first dielectric layer and the first surface, and
the passivation layer directly contacts both the second dielectric layer and the first surface.

US Pat. No. 10,115,704

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that of the first surface, a first electrode on the first surface, a second electrode on the second surface, and a first contact electrically connecting the first electrode and the second electrode;
a second semiconductor chip having a third surface that faces the first surface, a fourth surface on a side of the second semiconductor chip opposite to that of the third surface, and a third electrode on the fourth surface;
a metal wire that electrically connects the third electrode to the first electrode;
a first insulating layer that is on the second surface of the first semiconductor chip and includes a first opening;
a first conductive layer that is in the first opening and on a part of the first insulating layer and is electrically connected to the second electrode;
a second conductive layer that is directly in contact with the first conductive layer;
a second insulating layer that is on the first insulating layer and the second conductive layer and includes a second opening;
a third conductive layer that is in the second opening and is electrically connected to the second conductive layer; and
a first external terminal in direct contact with the third conductive layer, wherein
no wiring substrate is present between the first semiconductor chip and the first external terminal.

US Pat. No. 10,115,703

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first semiconductor substrate;
a second semiconductor substrate facing the first semiconductor substrate;
a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;
a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;
a first insulating layer disposed on an edge portion of the first semiconductor substrate and the first pad electrode;
a second insulating layer disposed on an edge portion the second semiconductor substrate and the second pad electrode;
a base metal layer disposed on the second insulating layer and a center portion of the second pad electrode, the base metal layer having a stepped first surface and a planar second surface opposite the stepped first surface;
a first metal layer disposed over the first semiconductor substrate and facing the second semiconductor substrate;
a second metal layer disposed on the base metal layer and facing the first metal layer, the second metal layer having a planar first surface in contact with the base metal layer, and a planar second surface opposite the planar first surface;
a third metal layer disposed between the first metal layer and the second metal layer;
a first alloy layer disposed between the first metal layer and the third metal layer comprising a component of the first metal layer and a component of the third metal layer; and
a second alloy layer disposed between the second metal layer and the third metal layer, comprising a component of the second metal layer and a component of the third metal layer,
wherein the first metal layer includes a stepped surface adjacent to and in contact with the first alloy layer, the stepped surface of the first metal layer including edge portions that extend beyond a central portion thereof.

US Pat. No. 10,115,700

POWER MODULE, ELECTRICAL POWER CONVERSION DEVICE, AND DRIVING DEVICE FOR VEHICLE

Hitachi, Ltd., Tokyo (JP...

1. A power module, comprising:a first switching device; and
a second switching device connected in parallel to the first switching device and having a threshold voltage higher than that of the first switching device,
the second switching device being mounted at a first location at which a temperature of the power module during operation is higher than a temperature of the power module at a second location at which the first switching device is mounted,
wherein each of the first switching device and the second switching device is an SiC-MOSFET.