US Pat. No. 10,170,412

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

Invensas Corporation, Sa...

1. An apparatus, comprising:conductive elements of a conductive layer on a bottom side of a package;
wire bond wires coupled to and extending from first upper surface portions of the conductive elements;
a microelectronic element coupled to second upper surface portions of the conductive elements through conductive contact structures;
a wire bond wire of the wire bond wires interconnected for electrical conductivity to a conductive contact structure of the conductive contact structures by a conductive element of the conductive elements for a redistribution on the bottom side of the package; and
a dielectric layer contacting the wire bond wires and side portions of the microelectronic element to define at least one dimension of the package, the conductive layer at least partially defining the bottom side of the package.

US Pat. No. 10,170,411

AIRGAP PROTECTION LAYER FOR VIA ALIGNMENT

International Business Ma...

1. A method for via alignment, comprising:depositing a pinch off layer to close off openings to first airgaps between interconnect structures;
forming a protection layer in divots formed in the pinch off layer; and
etching the pinch off layer using the protection layer as an etch stop to form and align a via and expose the interconnect structures through the via.

US Pat. No. 10,170,410

SEMICONDUCTOR PACKAGE WITH CORE SUBSTRATE HAVING A THROUGH HOLE

Samsung Electro-Mechanics...

1. A semiconductor package, comprising:a frame comprising a through hole;
an electronic component disposed in the through hole;
a metal layer disposed on either one or both of an inner surface of the through hole and an upper surface of the electronic component;
a redistribution portion disposed below the frame and the electronic component; and
a conductive layer electrically connected to the metal layer,
wherein the redistribution portion comprises an insulating layer formed of an insulating material, and a wiring layer provided in the insulating layer, and
wherein the insulating layer extends to a space formed by a portion of the metal layer formed on an inner surface of the frame and an outer surface of the electronic component.

US Pat. No. 10,170,409

PACKAGE ON PACKAGE ARCHITECTURE AND METHOD FOR MAKING

INTEL CORPORATION, Santa...

1. A method of fabricating a package assembly, the method comprising:forming a package-on-package (POP) land by partially embedding a prefabricated via bar in a region on a first side of a mold compound and extended to a location between the first side of the mold compound and a second side of the mold compound disposed opposite to the first side, wherein the prefabricated via bar extends across a plurality of package assemblies including a first package assembly and a second package assembly separated from the first package assembly, and wherein a die is at least partially embedded in the mold compound and has an active side proximal to the first side of the mold compound;
removing material of the mold compound to expose a portion of the POP land in a region on the second side of the mold compound after the forming of the POP land; and
depositing at least one of a conductive material, a passivation layer, or a noble metal on the exposed portion of the POP land.

US Pat. No. 10,170,408

MEMORY CIRCUITS AND ROUTING OF CONDUCTIVE LAYERS THEREOF

Taiwan Semiconductor Manu...

1. A memory circuit, comprising:at least one memory cell for storing a datum, the memory cell being coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line;
a first conductive layer arranged at a first level, the first conductive layer comprising a first landing pad and a second landing pad, the first landing pad forming a landing site formed in the first conductive layer and on which a via lands, the via connecting the first conductive layer to a second conductive layer;
the second conductive layer coupled to the first conductive layer and arranged at a second level different from and over the first level, the second conductive layer being routed to define the first voltage line and the second voltage line, the first voltage line and the second voltage line extending in a first direction, wherein the first voltage line and the second voltage line are located within the second conductive layer; and
a third conductive layer coupled to the second conductive layer and arranged at a third level different from the first level and the second level, the third level over the second level, the third conductive layer being routed to define the word line, the word line extending in a second direction perpendicular to the first direction, wherein the bit line is located within the first conductive layer adjacent to the first landing pad, wherein the bit line in the first conductive layer extends past a periphery of the at least one memory cell in the first direction, wherein the bit line bar is located within the first conductive layer adjacent to the second landing pad, and wherein the bit line bar in the first conductive layer extends past the periphery of the at least one memory cell in the first direction.

US Pat. No. 10,170,406

TRACE/VIA HYBRID STRUCTURE AND METHOD OF MANUFACTURE

INTERNATIONAL BUSINESS MA...

1. A method of forming an interconnect comprising:providing a sacrificial trace structure using an additive forming method;
forming a seed metal layer on the sacrificial trace structure;
removing the sacrificial trace structure, wherein the seed metal layer remains;
forming an interconnect metal layer on the continuous seed layer;
forming a dielectric material on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of said interconnect metal layer are exposed to provide said interconnect extending through said dielectric material;
forming a solder bump on said ends of the interconnect metal layer; and
bonding said solder bump to a substrate including at least one microprocessor.

US Pat. No. 10,170,405

WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:an insulating layer; and
a wiring layer buried in the insulating layer at a first surface of the insulating layer,
the wiring layer including a first portion and a second portion, the first portion being narrower and thinner than the second portion, the first portion including a first surface exposed at the first surface of the insulating layer, the second portion including a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer, the opening being open at a second surface of the insulating layer opposite to the first surface thereof,
wherein the wiring layer includes a first surface exposed at the first surface of the insulating layer, a second surface opposite to the first surface of the wiring layer, and a side surface, and
wherein a surface roughness of the second surface of the wiring layer and the side surface of the wiring layer is greater than a surface roughness of the first surface of the wiring layer.

US Pat. No. 10,170,404

MONOLITHIC 3D INTEGRATION INTER-TIER VIAS INSERTION SCHEME AND ASSOCIATED LAYOUT STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:forming a first interconnect structure over a first substrate, wherein the first interconnect structure includes a plurality of first interconnect elements;
forming a second substrate over the first substrate such that the first interconnect structure is disposed between the first substrate and the second substrate;
forming a via that extends vertically through the second substrate, wherein the via is formed to be electrically coupled to the first interconnect structure; and
forming a dummy gate over the second substrate, wherein the dummy gate is formed to be electrically coupled to the via.

US Pat. No. 10,170,402

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface;
a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate; and
a plurality of wires electrically connected with the plurality of terminals, respectively,
wherein, in plan view, the first semiconductor chip is mounted over the upper surface of the wiring substrate such that the plurality of terminals of the wiring substrate is exposed from the first semiconductor chip,
wherein, in plan view, the plurality of terminals is arranged along a first side of the first main surface of the first semiconductor chip,
wherein the plurality of terminals has a plurality of first terminals, and a second terminal,
wherein, in plan view, the second terminal has a first part located on a virtual line comprised of an arrangement of the plurality of first terminals, and a second part not located on the virtual line,
wherein each of the plurality of wires has a ball part, and a stitch part,
wherein, in plan view, a width of the ball part is larger than a width of the stitch part,
wherein the plurality of wires has a plurality of first wires, and a second wire,
wherein, the plurality of first wires are connected to the plurality of first terminals, respectively, via the stitch part,
wherein the second wire is connected to the second part of the second terminal via the ball part, and
wherein a distance from the first side of the first main surface of the first semiconductor chip to the second part of the second terminal is greater than a distance from the first side of the first main surface of the first semiconductor chip to each of the first terminals in a direction perpendicular to the first side of the first main surface of the first semiconductor chip.

US Pat. No. 10,170,400

MULTI-FINGER TRANSISTOR AND SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A multi-finger transistor comprising:a plurality of gate fingers arranged in an active region on a semiconductor substrate;
a plurality of source fingers and a plurality of drain fingers which are alternately arranged in said active region in such a way as to sandwich said gate fingers therebetween, respectively;
a gate pad disposed outside said active region, said gate fingers being connected to said gate pad via a gate bus;
a source pad disposed in a region which is located outside said active region and on a side where said gate pad is disposed with respect to said active region, said source fingers being connected to said source pad;
a drain pad disposed in a region which is located outside said active region and which is located at an opposite side of said gate pad across said active region, said drain fingers being connected to said drain pad;
and a source via grounding said source pad, wherein
said multi-finger transistor further comprises a circuit suppressing a variation in voltage current distribution, said circuit connecting said gate fingers to each other, or connecting said source fingers to each other with a resistive member having a resistance higher than said source fingers, in a region which is located outside said active region and on a side where said drain pad is disposed, and
said multi-finger transistor is configured so as to be linearly symmetric with respect to a direction of propagation of a signal from said gate pad at a position of said gate pad.

US Pat. No. 10,170,399

CAPPED THROUGH-SILICON-VIAS FOR 3D INTEGRATED CIRCUITS

Board of Regents, The Uni...

1. A three dimensional (3D) integrated circuit comprising a plurality of electrically connected chips, at least one chip comprisinga wafer;
a back-end-of-line (BEOL) layer deposited on the wafer;
a chip through-silicon-via (TSV) in the wafer, the chip TSV containing a conductive material;
a chip cap layer disposed over the chip TSV and between the chip TSV and the BEOL layer, wherein the chip cap layer is configured to reduce via extrusion of conductive material located in the chip TSV during operation of the chip; and
an interposer on which the plurality of electrically connected chips are located, wherein the interposer comprises a plurality of interposer TSVs and a interposer cap layer configured to reduce via extrusion of conductive material located in the interposer TSV during fabrication or operation of the circuit, or both.

US Pat. No. 10,170,398

THREE-DIMENSIONAL INTEGRATED CIRCUIT

INDUSTRY-ACADEMIC COOPERA...

1. A three-dimensional integrated circuit divided into a plurality of groups, the three-dimensional integrated circuit comprising:a plurality of through-silicon vias (TSVs) vertically penetrating the three-dimensional integrated circuit and comprised in each of the groups; and
two or more redundant through-silicon vias (RTSVs) vertically penetrating the three-dimensional integrated circuit and comprised in each of the groups,
wherein an RTSV of two or more RTSVs in one group of the plurality of groups is configured to receive a signal of a first failed TSV of a plurality of TSVs in the one group and process the signal of the first failed TSV in the RTSV of the two or more RTSVs in the one group when a number of failed TSVs among the plurality of TSVs in the one group does not exceed a repairable number, and wherein each of the failed TSVs does not normally perform a function as an electrode, and the repairable number is a number of RTSVs capable of replacing functions of the failed TSVs in the one group, and
wherein the RTSV of the two or more RTSVs in the one group is configured to receive the signal of the first failed TSV of the plurality of TSVs in the one group, process the signal of the first failed TSV in the RTSV of the two or more RTSVs in the one group, receive a signal of a second failed TSV of the plurality of TSVs in the one group and output the signal of the second failed TSV to an RTSV of two or more RTSVs in another group of the plurality of groups such that a function of the second failed TSV is performed by the RTSV in the another group when the number of failed TSVs among the plurality of TSVs in the one group exceeds the repairable number, the another group being adjacent to the one group.

US Pat. No. 10,170,396

THROUGH VIA STRUCTURE EXTENDING TO METALLIZATION LAYER

Taiwan Semiconductor Manu...

1. A method of forming an integrated circuit, comprising:forming an intermetal dielectric layer over a substrate;
forming a metal via and a metal line in the intermetal dielectric layer using a dual-damascene process, the metal line formed in a metal one layer (M1);
after forming the intermetal dielectric layer, removing portions of the intermetal dielectric layer to form an opening through the intermetal dielectric layer;
after removing portions of the intermetal dielectric layer, filling the opening with a conductive material to form a through via (TV), the through via extending through the intermetal dielectric layer and at least a portion of the substrate, the through via having a top surface co-planar with a top surface of the metal line; and
after forming the through via, forming one or more dielectric layers over the through via.

US Pat. No. 10,170,395

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first semiconductor module housing a first semiconductor element and a third semiconductor element;
a second semiconductor module housing a second semiconductor element and a fourth semiconductor element, the second semiconductor element having a switching voltage threshold that is lower than a switching voltage threshold of the first semiconductor element of the first semiconductor module, and the fourth semiconductor element having a switching voltage threshold that is higher than a switching voltage threshold of the third semiconductor element of the first semiconductor module; and
a first busbar that connects an external terminal of the first semiconductor element of the first semiconductor module to an external terminal of the second semiconductor element of the second semiconductor module in parallel to a first common terminal; and
a second busbar that connects an external terminal of the third semiconductor element of the first semiconductor module to an external terminal of the fourth semiconductor element of the second semiconductor module in parallel to a second common terminal, wherein
an inductance of a current path from the first common terminal to the first semiconductor element in the first semiconductor module is lower than an inductance of a current path from the first common terminal to the second semiconductor element in the second semiconductor module, and
an inductance of a current path from the second common terminal to the third semiconductor element of the first semiconductor module is higher than an inductance of a current path from the second common terminal to the fourth semiconductor element of the second semiconductor module.

US Pat. No. 10,170,394

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

10. A semiconductor device comprising:a laminated substrate having a circuit board;
a semiconductor chip having electrodes on a front surface, and a rear surface fixed to the circuit board;
a terminal having a wiring portion with a plate shape, and a leading end portion with a hollow shape extending from the wiring portion, the wiring portion and the leading end portion being integrally formed of one conductive member, the leading end portion having a front open end forming an end of the terminal and a rear open end where a part of the leading end portion continues to the wiring portion; and
a joining material which electrically and mechanically connects the electrode and the front open end of the leading end portion,
wherein the front open end of the leading end portion is located to face the electrode, and is closed by the joining material entered into the front open end, and
a space is arranged between the front open end of the terminal and the electrode so that the joining material enters the front open end of the leading end portion and the space to connect the leading end portion to the electrode.

US Pat. No. 10,170,392

WAFER LEVEL INTEGRATION FOR EMBEDDED COOLING

INTERNATIONAL BUSINESS MA...

1. A device, comprising:a silicon wafer, comprising:
channel structures formed on a first surface of a silicon first wafer, wherein the channel structures respectively comprise radial channels that extend from central fluid distribution areas; and
integrated circuits formed on a second surface of the silicon first wafer that opposes the first surface; and
a manifold wafer bonded to the first surface of the silicon wafer, wherein portions of the manifold wafer enclose the radial channels and wherein inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas.

US Pat. No. 10,170,389

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A method of forming a semiconductor die assembly, the method comprising:electrically coupling a plurality of first semiconductor dies together in a single stack;
electrically coupling the single stack of first semiconductor dies to a second semiconductor die such that the stack of first semiconductor dies is centered with respect to the second semiconductor die along at least one axis, the second semiconductor die having a peripheral portion that extends laterally outward beyond at least one side of the stack of first semiconductor dies, and wherein the stack of first semiconductor dies forms a first thermal path that transfers heat away from the second semiconductor die;
depositing an underfill material between the first semiconductor dies, wherein the underfill material extends from between the first semiconductor dies onto the peripheral portion of the second semiconductor die;
adhering, via the underfill material, a thermal transfer feature to the peripheral portion of the second semiconductor die adjacent to at most a first side and a second side of the single stack of first semiconductor dies and spaced laterally apart from the at most first and second sides of the single stack of first semiconductor dies, wherein the thermal transfer feature is a blank silicon member, and wherein the thermal transfer feature forms a second thermal path away from the second semiconductor die that is separate from the first thermal path; and
thermally contacting a thermally conductive casing with the thermal transfer feature at an elevation generally corresponding to that of a topmost one of the first semiconductor dies in the stack of first semiconductor dies, wherein the blank silicon member extends continuously vertically from the underfill material on the peripheral portion to the elevation generally corresponding to that of the topmost one of the first semiconductor dies.

US Pat. No. 10,170,388

SURFACE PASSIVATION HAVING REDUCED INTERFACE DEFECT DENSITY

INTERNATIONAL BUSINESS MA...

1. A method of passivating a surface of a semiconductor, the method comprising:forming a semiconductor layer on a substrate;
contacting a surface of the semiconductor layer with a sulfur source comprising thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer;
forming a dielectric layer on the sulfur passivation layer; and
annealing the dielectric layer at a temperature of about 390 degrees Celsius for about 30 minutes;
wherein a minimum interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2 eV?1.

US Pat. No. 10,170,387

TEMPORARY BONDING SCHEME

Taiwan Semiconductor Manu...

15. A structure comprising:an integrated circuit device;
a molding compound encapsulating the integrated circuit device, the molding compound having a major surface; and
a thermoplastic material within the molding compound having a concentration of from 1 ppm to 100 ppm at the major surface.

US Pat. No. 10,170,386

ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component package comprising:a frame having a cavity;
an electronic component disposed in the cavity of the frame;
a first metal layer disposed on an inner wall of the cavity of the frame;
a second metal layer disposed on a lower surface of the frame;
a third metal layer disposed on an upper surface of the frame;
an encapsulant encapsulating at least a portion of the electronic component; and
a redistribution layer disposed below the frame and the electronic component,
wherein a lower surface of the encapsulant is substantially coplanar with lower surfaces of the electronic component, the first metal layer and second metal layer.

US Pat. No. 10,170,385

SEMICONDUCTOR DEVICE AND METHOD OF FORMING STACKED VIAS WITHIN INTERCONNECT STRUCTURE FOR FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a semiconductor die;
an encapsulant deposited over and around the semiconductor die;
a first insulating layer formed over the semiconductor die and encapsulant including a first opening formed through the first insulating layer;
a first conductive layer formed over a top surface of the first insulating layer and extending through the first opening to the encapsulant;
a second insulating layer formed over the semiconductor die and encapsulant including a second opening formed through the second insulating layer, wherein a size of the second opening at the first conductive layer is approximately equal to a size of the first opening, and the second opening is aligned with the first opening;
a second conductive layer formed over a top surface of the second insulating layer and extending through the second opening to the first conductive layer;
a third opening formed through the encapsulant, first conductive layer, and second conductive layer, wherein a size of the third opening at the first conductive layer is smaller than the size of the first opening and the size of the second opening; and
a solder material deposited in the third opening to form a conductive via, wherein the solder material in the third opening is exposed from a top surface of the encapsulant opposite the first conductive layer.

US Pat. No. 10,170,384

METHODS AND APPARATUS PROVIDING A GRADED PACKAGE FOR A SEMICONDUCTOR

TEXAS INSTRUMENTS INCORPO...

1. A method comprising:generating a graded package for encapsulating a die by spatially varying package material of the graded package based on a package grading design, wherein the generating of the graded package includes:
moving a printhead to a first location of the graded package;
printing at least one of a first material or a first combination of materials at the first location;
moving the printhead to a second location of the graded package; and
printing at least one of a second material or a second combination of materials at the second location, the second material being different from the first material and the second combination being different than the first combination.

US Pat. No. 10,170,383

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:an insulating board;
a circuit pattern disposed on the insulating board;
a semiconductor chip connected to the circuit pattern;
a case disposed on and entirely to one side of the insulating board to surround the circuit pattern and the semiconductor chip; and
a cured resin disposed in the case to seal the circuit pattern and the semiconductor chip, wherein
the case includes a surface portion directly opposing and adjacent to a surface portion of the insulating board, and
no bonding material other than the resin is disposed between the opposing and adjacent surface portions.

US Pat. No. 10,170,382

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package comprising:a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad;
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and
a resin layer disposed between the encapsulant and the second interconnection member and contacting at least portions of side surfaces of the protrusion bump,
wherein the first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pad,
the first interconnection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer and contacting the second interconnection member, and
the resin layer contacts at least portions of side surfaces of the third redistribution layer.

US Pat. No. 10,170,381

SEMICONDUCTOR WAFER AND METHOD OF BACKSIDE PROBE TESTING THROUGH OPENING IN FILM FRAME

SEMICONDUCTOR COMPONENTS ...

1. A method of making a semiconductor device, comprising:providing a semiconductor wafer including a non-active surface;
forming a conductive layer over the non-active surface;
providing a wafer holder;
forming a first opening through the wafer holder;
mounting the semiconductor wafer to the wafer holder with the conductive layer on the non-active surface oriented toward the wafer holder; and
probe testing the semiconductor wafer by contacting the conductive layer through the first opening in the wafer holder.

US Pat. No. 10,170,380

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a display region and a peripheral circuit region located outside the display region,
wherein a first gate line, a first data line and a pixel region adjacent to the first gate line and the first data line are arranged in the display region; the pixel region includes a first pixel electrode and a first thin film transistor, and the first thin film transistor includes a first gate electrode connected to the first gate line, a first source electrode connected to the first data line and a first drain electrode connected to the first pixel electrode;
wherein the array substrate further comprises a test unit arranged in the peripheral circuit region, the test unit comprising:
a second gate line and a second data line intersecting with each other, wherein when the array substrate is in a working state, a first signal inputted to the second gate line is identical with a second signal inputted to the first gate line, and a third signal inputted to the second data line is identical with a fourth signal inputted to the first data line;
a second testing pixel electrode arranged close to the intersection of the second gate line and the second data line;
a second testing thin film transistor arranged at the intersection of the second gate line and the second data line, wherein the second testing thin film transistor includes a second gate electrode connected to the second gate line, a second source electrode connected to the second data line and a second drain electrode connected to the second testing pixel electrode, wherein a first test port exposed outside of the display region is provided for the second gate electrode, a second test port exposed outside of the display region is provided for the second source electrode, and a third test port exposed outside of the display region is provided for the second drain electrode,
wherein, the display region is further provided with a first common electrode line and a first common electrode connected to the first common electrode line;
the test unit further includes: a second common electrode line and a second testing common electrode connected to the second common electrode line, wherein the second testing common electrode and the first common electrode are arranged on a same layer and are identical in material and shape; and the second testing common electrode is connected to a third test lead through a first transparent conductive connecting line which is located on the same layer with the second testing common electrode, wherein one end of the first transparent conductive connecting line is connected to the second testing common electrode and the other end of the first transparent conductive connecting line is connected to the third test lead, and the first transparent conductive connecting line and the second testing common electrode are identical in material,
wherein, the first transparent conductive connecting line is intersected with the second common electrode line in a plan view of the array substrate.

US Pat. No. 10,170,379

WAFER PROCESSING SYSTEM

DISCO CORPORATION, Tokyo...

1. A wafer processing system for processing wafers one at a time, the wafer processing system comprising:a plurality of trays each configured to accommodate a wafer;
a conveyor configured to transfer the wafers accommodated in the trays;
first and second tray holding apparatuses arranged to be spaced from each other along the conveyor, the first and second tray holding apparatuses unloading the trays from the conveyor and loading the unloaded trays onto the conveyor;
first and second apparatuses provided for the first and second tray holding apparatuses, respectively, the first and second apparatuses including processing means configured to process the wafers transferred by the conveyor, and loading/unloading means configured to unload a wafer from or load a wafer onto one of the trays that is held by the first or second tray holding apparatus; and
a pair of rail members, with one of said rail members formed on each side of the conveyor, wherein each of said rail members includes first and second accommodation grooves therein, and further wherein said pair of first accommodation grooves are configured and arranged to accommodate downward movement of said first tray holding apparatus and said pair of second accommodation grooves are configured and arranged to accommodate downward movement of said second tray holding apparatus.

US Pat. No. 10,170,378

GATE ALL-AROUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming a stacked structure of a plurality of first semiconductor layers, a plurality of second semiconductor layers, and a plurality of third semiconductor layers alternately stacked in a first direction over a substrate, wherein the first, second and third semiconductor layers are made froth different materials;
patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction;
removing a portion of the second and third semiconductor layers between adjacent first semiconductor layers of the first fin structure to form a first nanowire structure;
removing a portion of the first and third semiconductor layers between adjacent second semiconductor layers of the second fin structure to form a second nanowire structure;
forming first gate structures wrapping around first nanowires of the first nanowire structure at a first region of the first nanowires; and
forming second gate structures wrapping around second nanowires of the second nanowire structure at a first region of the second nanowires,
wherein the first and second gate structures include gate electrodes, and
wherein when viewed in a cross section taken along a third direction substantially perpendicular to the first direction and the second direction a height of the first nanowires along the first direction is not equal to a distance of a spacing along the first direction between immediately adjacent second nanowires.

US Pat. No. 10,170,376

DEVICE AND FORMING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A device, comprising:a first vertical nanowire disposed on a substrate, wherein the first vertical nanowire comprises a silicon germanium channel part, wherein the first vertical nanowire comprises a bottom silicon source/drain part directly contacting the substrate, a top silicon source/drain part on the bottom silicon source/drain part, and the silicon germanium channel part between the top silicon source/drain part and the bottom silicon source/drain part, wherein the material of the silicon germanium channel part is different from the materials of the bottom silicon source/drain part and the top silicon source/drain part;
a second vertical nanowire disposed on the substrate next to the first vertical nanowire, wherein the second vertical nanowire comprises a silicon channel part; and
a gate encircling the silicon germanium channel part and the silicon channel part.

US Pat. No. 10,170,375

FINFET DEVICES WITH UNIQUE FIN SHAPE AND THE FABRICATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor device, comprising:forming a first layer over a substrate, the first layer spanning across both a first region and a second region;
forming a second layer over the first layer;
etching the first and second layers to form a plurality of openings in the first region and the second region, wherein the plurality of openings extend vertically through the first layer and the second layer;
forming a dielectric layer in the openings in the first region but not in openings of the second region; and
forming an insulating layer between the first and second layers in the second region.

US Pat. No. 10,170,374

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:at least one n-channel;
at least one p-channel;
at least one first high-k dielectric sheath surrounding the n-channel;
at least one second high-k dielectric sheath surrounding the p-channel, the first high-k dielectric sheath and the second high-k dielectric sheath comprising different high-k dielectric materials;
a first metal gate electrode surrounding and in contact with the first high-k dielectric sheath; and
a second metal gate electrode surrounding and in contact with the second high-k dielectric sheath, wherein the first and second metal gate electrodes are made of the same material.

US Pat. No. 10,170,372

FINFET CMOS WITH SI NFET AND SIGE PFET

International Business Ma...

1. A complementary metal oxide semiconductor (CMOS) device, comprising:pedestals with vertical sidewalls formed from a buried dielectric layer;
a SiGe fin and a Si fin, each formed on the pedestals, the SiGe fin and the Si fin including a same or substantially the same width dimension, wherein the pedestals extend wider than the SiGe fin and the Si fin for the entire length of the fins; and
epitaxial source and drain regions including a first epitaxial region grown from the SiGe fin and a second epitaxially region grown from the Si fin.

US Pat. No. 10,170,371

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS

International Business Ma...

1. A fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, comprising:a plurality of vertical fins within a perimeter of a fin pattern region on a substrate;
a step formed in the substrate surrounding the plurality of vertical fins;
a doped region within the perimeter of the fin pattern region below the plurality of vertical fins, wherein the depth of the doped region is less than the height of the step;
a dielectric layer on the step and at least a portion of the plurality of vertical fins; and
a gate dielectric layer on at least a portion of the sidewalls of the plurality of vertical fins and on the dielectric layer, wherein the gate dielectric layer extends over at least a portion of the step.

US Pat. No. 10,170,370

CONTACT RESISTANCE CONTROL IN EPITAXIAL STRUCTURES OF FINFET

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:fin regions on a substrate;
shallow trench isolation (STI) regions between the fin regions;
a replacement gate structure over the fin regions and the STI regions;
a merged epitaxial region; and
a capping layer, on the merged epitaxial region, with a top surface having a vertical dimension between a highest point and a lowest point less than about 5 nm.

US Pat. No. 10,170,369

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor device, comprising:providing a substrate having thereon a trench isolation region and a plurality of fin structures extending along a first direction, wherein the plurality of fin structures protrude from a top surface of the trench isolation region;
blanket depositing a polysilicon layer over the substrate;
forming a poly cut opening and a dummy opening in the polysilicon layer;
blanket coating an organic dielectric layer (ODL) over the substrate, wherein the ODL fills into the poly cut opening and the dummy opening;
blanket depositing a hard mask layer on the ODL;
forming a plurality of photoresist line patterns comprising a first photoresist line pattern and a second photoresist line pattern extending along a second direction on the hard mask layer, wherein the first photoresist line pattern overlaps with the poly cut opening, and the second photoresist line pattern is disposed in proximity to the dummy opening, and does not overlap with the dummy opening; and
transferring the plurality of photoresist line patterns to the polysilicon layer, thereby forming a plurality of poly lines extending along the second direction.

US Pat. No. 10,170,368

FABRICATING FIN-BASED SPLIT-GATE HIGH-DRAIN-VOLTAGE TRANSISTOR BY WORK FUNCTION TUNING

International Business Ma...

1. A method for creating an asymmetrical split-gate structure, the method comprising:forming a first device over a semiconductor substrate, the first device having first source drain regions formed adjacent a first set of spacers;
forming a second device over the semiconductor substrate, the second device having second source/drain regions formed adjacent a second set of spacers;
forming a first gate stack between the first set of spacers of the first device and a second gate stack between the second set of spacers of the second device;
depositing a hard mask over the first and second gate stacks;
etching a first section of the first gate stack to create a first gap region and a second section of the second gate stack to create a second gap region;
forming a third gate stack within the first gap region of the first gate stack, the third gate stack having a different number of layers than the first gate stack, and a fourth gate stack within the second gap region of the second gate stack such that dual gate stacks are defined for each of the first and second devices; and
annealing the dual gate stacks of the first and second devices to form first and second replacement metal gate stacks, respectively.

US Pat. No. 10,170,367

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:patterning a plurality of mandrels over a mask layer;
forming an etch coating layer on top surfaces of the mask layer and the mandrels;
depositing a dielectric layer over the mask layer and the mandrels with a deposition process, a first deposition rate of the deposition process along sidewalls of the mandrels being greater than a second deposition rate of the deposition process along the etch coating layer, a first thickness of the dielectric layer along the sidewalls of the mandrels being greater than a second thickness of the dielectric layer along the etch coating layer;
removing horizontal portions of the dielectric layer; and
patterning the mask layer using remaining vertical portions of the dielectric layer as a first etching mask.

US Pat. No. 10,170,366

SEMICONDUCTOR DEVICE HAVING DUMMY GATES AND METHOD OF FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a plurality of active fins protruding from a substrate and extending in a first direction;
a first device isolation layer disposed at a first side of the active fins;
a second device isolation layer disposed at a second side of the active fins, wherein the second side is opposite to the first side;
a normal gate extending across the active fins in a second direction crossing the first direction;
a first dummy gate extending across the active fins and the first device isolation layer in the second direction;
a second dummy gate extending across the second device isolation layer in the second direction,
wherein the second dummy gate is disposed within a boundary of the second device isolation layer and the second dummy gate is spaced apart from the second side of the active fins, and
wherein a top surface of the second device isolation layer is higher than a top surface of the first device isolation layer and top surfaces of the active fins; and
a third dummy gate extending across the first device isolation layer in the second direction,
wherein the third dummy gate is disposed within a boundary of the first device isolation layer and the third dummy gate is spaced apart from the first side of the active fins.

US Pat. No. 10,170,365

WRAP AROUND SILICIDE FOR FINFETS

Taiwan Semiconductor Manu...

1. A method comprising:forming a gate stack on a first portion of a semiconductor fin, wherein the semiconductor fin overlaps a semiconductor strip;
forming template dielectric regions on opposite sides of a second portion of the semiconductor fin;
forming a recess between the template dielectric regions, wherein the forming the recess comprises etching a top portion of the second portion of the semiconductor fin;
laterally expanding the recess to make the recess wider; and
epitaxially growing a source/drain region in the recess, wherein the source/drain region has substantially vertical sidewalls, and is wider than respective underlying portion of the semiconductor strip.

US Pat. No. 10,170,364

STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE

International Business Ma...

1. A method for forming strained fins, comprising:forming a staircase fin structure in a substrate with narrow top portions for fins;
epitaxially growing raised source and drain regions over the fins; and
performing a pre-amorphization implant to generate defects in the substrate to induce strain and to couple the strain into the top portions of the fins.

US Pat. No. 10,170,363

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. An interconnection structure of a semiconductor integrated circuit device comprising:a first conductive pattern having a first width and a first length;
a second conductive pattern arranged over the first conductive pattern, the second conductive pattern having a second width and a second length being different from the first length;
a dielectric layer interposed between the first conductive pattern and the second conductive pattern; and
a contact part configured to simultaneously make contact with the first conductive pattern and the second conductive pattern,
wherein the second conductive pattern is configured to expose an edge portion of the first conductive pattern, and the contact part is configured to make contact with the an edge portion of the second conductive pattern and the exposed edge portion of the first conductive pattern.

US Pat. No. 10,170,362

SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE CONTACT STRUCTURE AND METHOD OF FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a substrate, comprising a first active region and a plurality of second active regions;
a shallow trench isolation, disposed in the substrate and between the first active region and the second active regions;
a bit line contact opening, disposed in the first active region and the shallow trench isolation;
a bit line contact structure, disposed in the bit line contact opening and contacts the first active region; and
a spacer disposed in the bit line contact opening, wherein the spacer has a sidewall directly contacting one of the second active regions;
a mask layer disposed on the second active regions and exposing the bit line contact opening;
wherein the spacer extends beneath the mask layer to contact the first active region.

US Pat. No. 10,170,361

THIN FILM INTERCONNECTS WITH LARGE GRAINS

International Business Ma...

1. An integrated circuit, comprising:a surface of the integrated circuit, the surface comprising a semiconductor;
a via-line-via interconnect formed from a metal and comprising:
a first via formed in the surface;
a line formed integrally with the first via and orientated perpendicularly relative to the first via, wherein the line and the first via share at least one common grain, and wherein the line is further formed on the surface and orientated parallel to the surface, wherein a thickness of the line is defined in a dimension perpendicular to the surface, and a line width of the line is defined in a dimension parallel to the surface and is within the range of two nanometers to eighty nanometers, wherein an average grain size of the metal of the line is greater than or equal to at least half of a line width of the line, wherein the line has a tapered cross section, and wherein the thickness of the line remains constant; and
a second via formed integrally with the line and orientated perpendicular relative to the line, wherein the line and the second via share at least one common grain, and wherein the line is positioned between the first via and the second via and between the surface and the second via,
such that the via-line-via interconnect exhibits grain continuity and material continuity between the first via and the line and between the line and the second via, where the grain continuity is evident in the line sharing a respective common grain with each of the first via and the second via; and
an insulator deposited on the surface and surrounding the interconnect, wherein the insulator is formed from a material that is different from a material from which the surface is formed.

US Pat. No. 10,170,360

REFLOW ENHANCEMENT LAYER FOR METALLIZATION STRUCTURES

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:providing an opening in a dielectric-containing substrate;
forming a reflow enhancement layer in the opening and atop the dielectric-containing substrate;
forming a layer of a contact metal or metal alloy on the reflow enhancement layer;
performing a reflow anneal to completely fill a remaining volume of the opening with the contact metal or metal alloy of the layer of contact metal or metal alloy; and
removing the layer of contact metal or metal alloy, and the reflow enhancement layer located outside of the opening, wherein a portion of the layer of contact metal or metal alloy, and a portion of the reflow enhancement layer remain within the opening, and wherein the portion of the layer of contact metal or metal alloy that remains in the opening has a sidewall that is in direct physical contact with an inner sidewall of the portion of the reflow enhancement layer that remains in the opening.

US Pat. No. 10,170,359

DIFFUSION BARRIER LAYER FORMATION

International Business Ma...

1. A method of forming a titanium nitride diffusion barrier, the method comprising:exposing a deposition surface to a first pulse of a titanium-containing precursor gas to initiate a nucleation of the titanium nitride diffusion barrier in the deposition surface, wherein the deposition surface comprises sidewalls and a bottom of a contact opening;
exposing the deposition surface to a first pulse of a nitrogen-rich plasma to form a first titanium nitride layer with a first nitrogen concentration in the deposition surface, the first titanium nitride layer comprises a lower portion of the titanium nitride diffusion barrier;
exposing the first titanium nitride layer to a second pulse of the titanium-containing precursor gas to continue the nucleation of the titanium nitride diffusion barrier; and
exposing the first titanium nitride layer to a second pulse of the nitrogen-rich plasma to form a second titanium nitride layer with a second nitrogen concentration directly above and in contact with the first titanium nitride layer, the second titanium nitride layer comprises an upper portion of the titanium nitride diffusion barrier, wherein the second nitrogen concentration of the second titanium nitride layer is substantially increased by the second pulse of the nitrogen-rich plasma, the increased nitrogen concentration of the second titanium nitride layer lowers a reactivity of the upper portion of the titanium nitride diffusion barrier to prevent fluorine diffusion, and wherein the second pulse of the nitrogen-rich plasma has a substantially longer duration than the first pulse of the nitrogen rich plasma,
wherein the titanium nitride diffusion barrier comprises the first and the second titanium nitride layers; and
wherein the first pulse of the nitrogen-rich plasma has a duration of approximately 5 seconds and the second pulse of the nitrogen-rich plasma has a duration of approximately 60 seconds.

US Pat. No. 10,170,358

REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS

INTERNATIONAL BUSINESS MA...

1. An interconnect structure comprising:an interlevel dielectric layer on an electrically conductive feature;
an opening in the interlevel dielectric layer, the opening including a first width at a first depth into the interlevel dielectric layer, and a second width at a second depth that is greater than the first depth, wherein the second width is less than the first width of the opening and includes a portion of the opening that extends through the entirety of the interlevel dielectric layer into contact with the electrically conductive feature;
a conformal metal nitride layer present on vertical and horizontal surfaces of the opening, wherein the metal nitride layer is present directly on the interlevel dielectric layer;
a shield liner present over vertical sidewalls of the opening directly on the conformal metal nitride layer, wherein the conformal metal nitride layer is present between the interlevel dielectric layer and the shield liner; and
a contact extending through the opening into direct contact with the shield liner, the conformal metal nitride layer, and the electrically conductive feature, wherein a gouge is present at the interface of the contact and the electrically conductive feature.

US Pat. No. 10,170,357

SOI WAFER MANUFACTURING PROCESS AND SOI WAFER

SUMCO CORPORATION, Tokyo...

1. An SOI wafer manufacturing process, comprising:a first step of implanting light element ions to a surface of at least one of a first substrate made of silicon single crystal and a second substrate made of silicon single crystal to form, in the at least one of the first substrate and the second substrate, a modified layer in which the light element ions are present in solid solution;
a second step of forming an oxide film on a surface of at least one of the first substrate and the second substrate;
a third step of bonding the first substrate and the second substrate in a manner such that the modified layer and the oxide film are located between the first substrate and the second substrate; and
a fourth step, performed after the third step, of thinning the first substrate to obtain an active layer, wherein,
in the second step, the oxide film is deposited by accelerating and emitting ionized Si and oxygen to the at least one of the first substrate and the second substrate while heating the at least one of the first substrate and the second substrate, and
in the third step, the first substrate and the second substrate are bonded together at a normal temperature by emitting an ion beam or a neutral atomic beam to surfaces to be bonded of the first substrate and the second substrate under vacuum to activate the surfaces and subsequently by contacting the surfaces to be bonded with each other under vacuum.

US Pat. No. 10,170,356

SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF

ZING SEMICONDUCTOR CORPOR...

1. A manufacturing method of silicon on insulator substrate, comprising the steps of: providing a first semiconductor substrate;forming a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer;
irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer;
providing a second substrate;
growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer;
bonding the first wafer with the second wafer face to face;
annealing the first wafer and second wafer at a deuterium atmosphere such that the doping layer is transferred to a plurality of deuterium-doped bubbles;
separating a part of the first wafer from the second wafer to remain;
forming a deuterium doped layer on the second wafer, wherein the pluralities of deuterium-doped bubbles are in the deuterium doped layer; and
heating the second wafer to a temperature between 600 centigrade degrees and 1200 centigrade degrees once again after separating the part of the first wafer from the second wafer.

US Pat. No. 10,170,355

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first dielectric layer disposed over a substrate;
a plurality of metal wirings surrounded by the first dielectric layer;
a second dielectric layer disposed over a portion of the first dielectric layer, wherein a portion of the second dielectric layer is disposed in a first recess between two adjacent metal wirings of the plurality of metal wirings; and
a third dielectric layer disposed over the first dielectric layer, the second dielectric layer, and the plurality of metal wirings, wherein a portion of the third dielectric layer is disposed in the first recess between the two metal wirings,
wherein the portion of the third dielectric layer comprises an upper portion and a lower portion, the upper portion being above the second dielectric layer and the lower portion being below the second dielectric layer.

US Pat. No. 10,170,354

SUBTRACTIVE METHODS FOR CREATING DIELECTRIC ISOLATION STRUCTURES WITHIN OPEN FEATURES

Tokyo Electron Limited, ...

1. A method for partially filling an open feature on a substrate, comprising:receiving a substrate having a layer with at least one open feature formed therein, the open feature penetrating into the layer from an upper surface and including sidewalls extending to a bottom of the open feature;
over-filling the open feature with an organic coating that covers the upper surface of the layer and extends to the bottom of the open feature;
removing a portion of the organic coating to expose the upper surface of the layer and recessing the organic coating to a pre-determined depth from the upper surface to create an organic coating plug of pre-determined thickness at the bottom of the open feature; and
converting the chemical composition of the organic coating plug to create an inorganic plug,
wherein the organic coating includes a polymeric material or co-polymeric material containing a carbonyl functionality, and
wherein removing the portion of the organic coating includes performing a wet etch process comprising:
exposing the organic coating to ultraviolet (UV) radiation to increase the solubility of the as-formed organic coating in a developing solution; and
controllably etching the organic coating to the pre-determined depth by exposing the organic coating to the developing solution.

US Pat. No. 10,170,351

TRANSFERRING APPARATUS AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing an integrated circuit device using a transferring apparatus,wherein the transferring apparatus comprises:
a rail connected to a frame;
a travelling part including a wheel that travels along the rail and a loading part below the rail for loading an object below the rail; and
a particle collection receptacle provided at a side of the rail and configured to collect particles generated due to friction between the wheel and the rail when the wheel travels along the rail, the method including:
moving the travelling part to the object;
picking up the object with the loading part thereby loading the object on the loading part;
using the travelling part to move the object to a chamber; and
forming a semiconductor device using the object.

US Pat. No. 10,170,348

PRODUCTION SYSTEM FOR PRINTING ELECTRONIC DEVICES

KONICA MINOLTA, INC., To...

1. A printing production system for an electronic device, whereina transport chamber provided with a robot transport line in which a self-traveling robot that transports a base material in a sheet-fed manner in a free state travels is provided,
a plurality of processing chambers for forming the electronic device on the base material by printing are provided on at least one side of the transport chamber,
a plurality of base material transfer areas, each of the base material transfer areas performs loading of the base material to a respective processing chamber of the processing chambers from the self-traveling robot and unloading of the base material to the self-traveling robot from the respective processing chamber,
the transport chamber and each of the base material transfer areas communicate with each other through respective openings that allow loading and unloading of the base material to be performed, a one-way air flow is formed in each of the respective openings moving to a side where the respective processing chamber is located from a side where the transport chamber is located, and
the one-way air flow in the each of the respective openings is formed by making an adjustment such that an air pressure in the transport chamber becomes higher than an air pressure in each of the base material transfer areas, wherein an air pressure P1 in the clean room, an air pressure P2 in the base material transfer areas, and an air pressure P3 in the transport chamber satisfy a relationship: P1

US Pat. No. 10,170,347

SUBSTRATE PROCESSING SYSTEM

TOKYO ELECTRON LIMITED, ...

1. A substrate processing system for performing a process with respect to a plurality of substrates, comprising:an annular process chamber configured to accommodate the plurality of substrates and to perform a predetermined process on the plurality of substrates, the annular process chamber having an inner lateral surface and an outer lateral surface;
a cassette mounting part configured to mount a cassette which accommodates the plurality of substrates;
a substrate transfer mechanism configured to transfer the plurality of substrates between the annular process chamber and the cassette mounting part; and
a gate valve is installed in the inner lateral surface of the annular process chamber facing the substrate transfer mechanism,
wherein the plurality of substrates is concentrically disposed within the annular process chamber in a plane view,
wherein the substrate transfer mechanism is disposed in a space surrounded by the inner lateral surface of the annular process chamber, and
wherein a vacuum transfer chamber is installed adjacent to the annular process chamber in the space surrounded by the inner lateral surface of the annular process chamber, and the substrate transfer mechanism is disposed within the vacuum transfer chamber.

US Pat. No. 10,170,346

RESIN SEALING APPARATUS AND RESIN SEALING METHOD

TOWA CORPORATION, Kyoto-...

1. A resin sealing apparatus for providing resin sealing for a component to be sealed by a sealing resin which is cured in a cavity, comprising:an upper mold on which a substrate is disposed, a component to be sealed being attached to the substrate;
a lower mold provided to face the upper mold;
a cavity provided at least in the lower mold;
a bottom surface member forming an inner bottom surface of the cavity;
a side surface member forming a side surface of the cavity;
an opening provided in the side surface member and corresponding to an outer circumference of the bottom surface member;
an opening circumferential edge portion provided in the side surface member and having an inner edge shape formed to correspond to an outer edge of an end surface planar shape, an end surface of the sealing resin having the end surface planar shape;
an inclined surface portion provided in the side surface member and inclined to expand upwardly from the opening circumferential edge portion,
a frame-like member provided to surround a mold having at least the upper mold and the lower mold;
a space surrounded by the frame-like member and including the cavity;
a seal member for shutting off the space from ambient air; and
a pressure reducing mechanism for reducing pressure of the space with the space being shut off from the ambient air, wherein
the side surface member is fitted to the outer circumference of the bottom surface member so as to be slidable on the outer circumference, and
during a period from when the space is shut off from the ambient air to when a step of clamping the upper mold and the lower mold is completed, the pressure of the space shut off from the ambient air is reduced by the pressure reducing mechanism.

US Pat. No. 10,170,345

SUBSTRATE PROCESSING APPARATUS

Ebara Corporation, Tokyo...

1. A substrate processing apparatus comprising:a substrate processing table;
a processing device configured to perform a predetermined processing on the substrate processing table;
a nozzle configured to drop a fluid at a position that corresponds to a fluid dropping position set on the substrate processing table and is lower than a top surface of the processing device;
a nozzle moving mechanism configured to move the nozzle above the processing device between a retreat position set outside the substrate processing table and the fluid dropping position; and
a nozzle tip retreating mechanism configured to bring a tip end of the nozzle into a retreated state above the top surface of the processing device when the nozzle moves between the fluid dropping position and the retreat position,
wherein the nozzle tip retreating mechanism is an extension/contraction mechanism that extends and contracts the tip end of the nozzle.

US Pat. No. 10,170,344

WASHING DEVICE AND WASHING METHOD

EBARA CORPORATION, Tokyo...

1. A washing device comprising:a substrate rotation mechanism configured to hold a substrate and rotate the substrate about a central axis of the substrate as a rotary axis; a rinse supply; a chemical supply, wherein the chemical liquid is different than the rinse liquid;
a first single tube nozzle configured to discharge the rinse liquid from the rinse liquid supply as a first washing liquid toward an upper surface of the substrate held by the substrate rotation mechanism; and
a second single tube nozzle configured to discharge the chemical liquid from the chemical liquid supply as a second washing liquid toward the upper surface of the substrate held by the substrate rotation mechanism,
wherein the first single tube nozzle is placed to discharge the first washing liquid so that the first washing liquid lands in front of the center of the substrate and the landed first washing liquid flows on the upper surface of the substrate toward the center of the substrate,
a liquid flow on the upper surface of the substrate after landing of the first washing liquid discharged from the first single tube nozzle passes through the center of the substrate,
the second single tube nozzle is placed to discharge the second washing liquid so that the second washing liquid lands in front of the center of the substrate and the landed second washing liquid flows on the upper surface of the substrate toward the center of the substrate,
a second liquid flow on the upper surface of the substrate after landing of the second washing liquid discharged from the second single tube nozzle passes through the center of the substrate,
discharging of the first washing liquid by the first single tube nozzle and discharging of the second washing liquid by the second single nozzle are simultaneously performed, and
the first single tube nozzle supplies the first washing liquid so that a liquid-landing position of the first washing liquid is located in an area up to a 180° rotation in a reverse direction of a rotational direction of the substrate from the liquid-landing position of the second washing liquid.

US Pat. No. 10,170,343

POST-CMP CLEANING APPARATUS AND METHOD WITH BRUSH SELF-CLEANING FUNCTION

TAIWAN SEMICONDUCTOR MANU...

1. An apparatus for performing a post Chemical Mechanical Polish (CMP) cleaning, the apparatus comprising:a chamber configured to receive a wafer in need of having CMP residue removed;
a spray unit configured to apply a first cleaning solution to at least one surface of the wafer;
a brush cleaner configured to scrub the at least one surface of the wafer; and
at least one inner tank disposed in the chamber for storing a second cleaning solution that is used to clean the brush cleaner;
wherein the at least one inner tank comprises an inner compartment and an outer compartment, wherein the inner compartment is configured to store the second cleaning solution and receive the brush cleaner, and the outer compartment is configured to receive the second cleaning solution overflowing from the inner compartment.

US Pat. No. 10,170,342

FLOW CONTROLLED LINER HAVING SPATIALLY DISTRIBUTED GAS PASSAGES

Applied Materials, Inc., ...

1. A liner assembly, comprising:a lower liner having an outer surface, an inner surface defining a processing volume, an upper surface connecting the outer surface to the inner surface, and a plurality of gas passages connecting the outer surface to the processing volume, each of the plurality of gas passages comprising a first portion connected to a second portion, each first portion opening to the outer surface of the lower liner and each second portion having an upper end open to the upper surface and a lower end connected to the first portion; and
an upper liner disposed adjacent to the lower liner, the upper liner including a plurality of flow guides aligned with the plurality of gas passages.

US Pat. No. 10,170,341

RELEASE FILM AS ISOLATION FILM IN PACKAGE

Taiwan Semiconductor Manu...

1. A method comprising:forming a release film over a carrier;
attaching a device over the release film through a die-attach film;
encapsulating the device in an encapsulating material;
performing a planarization on the encapsulating material to expose the device;
forming redistribution lines to electrically couple to the device;
detaching the device and the encapsulating material from the carrier while the die-attach film remains attached to the device;
after the detaching of the device and the encapsulating material from the carrier, removing the die-attach film to expose a back surface of the device; and
applying a thermal conductive material on the back surface of the device.

US Pat. No. 10,170,338

VERTICAL NANORIBBON ARRAY (VERNA) THERMAL INTERFACE MATERIALS WITH ENHANCED THERMAL TRANSPORT PROPERTIES

Northrop Grumman Systems ...

1. A method of manufacturing a thermal interface material (TIM), comprising the steps of:growing a vertically aligned carbon nanotube (VACNT) array on a substrate;
placing the VACNT array in an electrolyte solution;
anodically treating the VACNT to longitudinally cleave the carbon nanotubes (CNTs) into vertical graphene oxide nanoribbons (GONRs); and
processing the GONRs to remove oxygen and create an array of vertically aligned graphene nanoribbons (VERNA).

US Pat. No. 10,170,337

IMPLANT AFTER THROUGH-SILICON VIA (TSV) ETCH TO GETTER MOBILE IONS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:disposing a mask on a substrate;
etching the mask to form an opening in the mask;
etching a trench in the substrate beneath the opening in the mask;
implanting a dopant, by an implantation technique, in an area of the substrate beneath the opening of the mask such that the dopant extends within the substrate from a substantially vertical sidewall of the trench and substantially horizontal bottom endwall of the trench, the dopant capable of gettering mobile ions that can contaminate the substrate; and
simultaneous with implanting the dopant, implanting a source/drain region of an nFET device adjacent the trench with an element selected from the group consisting of arsenic and phosphorous.

US Pat. No. 10,170,334

REDUCTION OF DISHING DURING CHEMICAL MECHANICAL POLISH OF GATE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a gate structure over the semiconductor substrate; and
a plurality of chemical mechanical polish (CMP) resistant structures embedded in a top surface of the gate structure, the CMP resistant structures having a CMP resistance property different from a CMP resistance property of the gate structure,
wherein the gate structure comprises a base portion and a plurality fins protruding from the base portion, and each of the fins is connected to the base portion,
wherein the CMP resistant structures and the fins are arranged in an alternating manner along a first lengthwise direction,
wherein the CMP resistant structures extend along a second lengthwise direction which is different from the first lengthwise direction.

US Pat. No. 10,170,332

FINFET THERMAL PROTECTION METHODS AND RELATED STRUCTURES

Taiwan Semiconductor Manu...

14. A method, comprising:providing a substrate including a plurality of fins and interposing dielectric features;
after providing the plurality of fins and interposing dielectric features, forming a dummy channel on an end of each of the plurality of fins, wherein the dummy channel has a different composition than each of the plurality of fins;
recessing the interposing dielectric features to expose the dummy channel;
after recessing the interposing dielectric features, forming a dummy gate stack over the exposed dummy channel and forming source/drain regions in each of the plurality of fins;
depositing a first inter-layer dielectric (ILD) layer on the substrate including the plurality of fins;
planarizing the first ILD layer to expose the dummy gate stack;
after planarizing the first ILD layer, removing the dummy gate stack and etching the dummy channel to form a recess in each of the plurality of fins; and
forming a material in the recess in each of the plurality of fins.

US Pat. No. 10,170,331

STACKED NANOWIRES

International Business Ma...

1. A method of forming silicon germanium (SiGe) nanowires, the method comprising the steps of:forming a stack of alternating silicon (Si) and SiGe layers on a wafer;
patterning fins in the stack;
selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape, wherein the SiGe layers in the fins are selectively thinned using an anisotropic wet etching process, and wherein the anisotropic wet etching process results in a v-shaped notching of the SiGe layers in the fin stack;
burying the fins in an oxide material; and
annealing the fins under conditions sufficient to diffuse germanium (Ge) from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires.

US Pat. No. 10,170,329

SPACER FORMATION FOR SELF-ALIGNED MULTI-PATTERNING TECHNIQUE

Tokyo Electron Limited, ...

1. A method of forming a spacer pattern on a substrate, the method comprising:providing a substrate with a plurality of spacer cores having a conformal coating of spacer material thereon wherein the conformal coating includes bottom portions on the substrate between the plurality of spacer cores, sidewall portions on sidewalls of the plurality of spacer cores, top portions on top surfaces of the plurality of spacer cores, and shoulder portions joining the sidewall portions and the top portions;
performing a spacer freeze treatment process that forms a buildup of byproducts on the shoulder portions of the conformal coating while leaving the top and bottom portions exposed;
performing an etch and clean process on the substrate to remove the exposed top and bottom portions of the conformal coating and to remove the plurality of spacer cores to substantially leave the sidewall portions as the spacer pattern, wherein the buildup of byproducts serves as a protective layer to reduce etching of the sidewall portions; and
controlling one or more process parameters of the spacer freeze treatment process and the etch and clean process in order to achieve one or more spacer formation objectives selected from a target height of the spacer pattern, a target maximum facet depth on the spacer pattern, a target critical dimension of the spacer pattern, a target maximum height difference between the plurality of spacer cores and the spacer pattern, a target uniformity of the spacer pattern, and a target maximum amount of spacer footings in the spacer pattern.

US Pat. No. 10,170,327

FIN DENSITY CONTROL OF MULTIGATE DEVICES THROUGH SIDEWALL IMAGE TRANSFER PROCESSES

International Business Ma...

1. A method for fabricating multigate devices comprising:forming a mandrel on a semiconductor substrate;
forming a first sidewall composed of a first material directly in contact with the mandrel previously formed on the semiconductor substrate; and
forming a second sidewall composed of a second material that is different from the first material directly in contact with the mandrel, wherein the second sidewall is opposite the first sidewall on the same mandrel.

US Pat. No. 10,170,326

WAFER ELEMENT WITH AN ADJUSTED PRINT RESOLUTION ASSIST FEATURE

INTERNATIONAL BUSINESS MA...

1. A wafer element fabrication method, comprising:patterning photoresist (PR) over an anti-reflective coating (ARC) disposed over a planarization layer (PL) and a substrate,
the patterning comprising forming the PR into PR device element and adjusted print resolution assist feature (APRAF) sections having first and second dimensions, respectively;
removing portions of the ARC and the PR device element and APRAF sections such that ARC device element and APRAF posts remain underneath remainders of the PR device element and APRAF sections having third and fourth dimensions based on the first and second dimensions, respectively;
removing the remainders of the PR device element and APRAF sections and portions of the PL such that PL device element and APRAF posts remain underneath the ARC device element and APRAF posts; and
removing the ARC device element and APRAF posts such that the PL device element and APRAF posts remain with fifth and sixth dimensions based on the third and fourth dimensions, respectively.

US Pat. No. 10,170,325

HARDMASK COMPOSITION AND METHOD OF FORMING PATTERN BY USING THE HARDMASK COMPOSITION

Samsung Electronics Co., ...

1. A hardmask composition comprising:a 2-dimensional carbon nanostructure containing about 0.01 atom % to about 40 atom % of oxygen, an intensity ratio of a D mode peak to a G mode peak obtained by Raman spectroscopy of the 2-dimensional carbon nanostructure being 2 or lower; and
a solvent, wherein
a fraction of sp2 carbon is equal to or a multiple of a fraction of sp3 carbon in the 2-dimensional carbon nanostructure.

US Pat. No. 10,170,324

TECHNIQUE TO TUNE SIDEWALL PASSIVATION DEPOSITION CONFORMALITY FOR HIGH ASPECT RATIO CYLINDER ETCH

Lam Research Corporation,...

1. A method of forming an etched feature in a substrate comprising dielectric material, the method comprising:(a) generating a first plasma comprising an etching reactant, exposing the substrate to the first plasma, and partially etching the feature in the substrate;
(b) after (a), depositing a protective film on sidewalls of the feature, wherein the protective film is deposited through a plasma assisted atomic layer deposition reaction comprising:
(i) exposing the substrate to a first deposition reactant and allowing the first deposition reactant to adsorb onto the sidewalls of the feature;
(ii) after (i), exposing the substrate to a second plasma comprising a second deposition reactant, wherein exposing the substrate to the second plasma drives a surface reaction between the first deposition reactant and the second deposition reactant, thereby forming the protective film on the sidewalls of the feature; and
(c) repeating (a)-(b) until the feature is etched to a final depth, wherein the protective film deposited in (b) substantially prevents lateral etch of the feature during (a), and wherein the feature has an aspect ratio of about 5 or greater at its final depth.

US Pat. No. 10,170,323

TECHNIQUE TO DEPOSIT METAL-CONTAINING SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH

Lam Research Corporation,...

1. A method of etching a feature in a dielectric-containing stack on a substrate, the method comprising:(a) generating a first plasma comprising an etching reactant, exposing the substrate to the first plasma, and partially etching the feature in the dielectric-containing stack;
(b) after (a), depositing a protective film on sidewalls of the feature, the protective film comprising a metal, wherein the protective film comprises an electrically conductive film; and
(c) repeating (a)-(b) until the feature is etched to a final depth, wherein the protective film deposited in (b) substantially prevents lateral etch of the feature during (a), and wherein the feature has an aspect ratio of about 5 or greater at its final depth.

US Pat. No. 10,170,322

ATOMIC LAYER DEPOSITION BASED PROCESS FOR CONTACT BARRIER LAYER

TAIWAN SEMICONDUCTOR MANU...

9. A method comprising:forming a contact opening in a dielectric layer;
performing at least one first cycle of a first nitrogen-containing plasma pulse and a first purge, thereby nitridizing surfaces of the dielectric layer that define the contact opening;
performing at least one second cycle of a titanium-containing pulse, a second purge, a second nitrogen-containing plasma pulse, and a third purge, thereby forming a titanium nitride layer on the nitridized surfaces of the dielectric layer that define the contact opening; and
forming a cobalt layer on the titanium nitride layer.

US Pat. No. 10,170,321

ALUMINUM CONTENT CONTROL OF TIAIN FILMS

Applied Materials, Inc., ...

1. A method of depositing a TiAlN film on a substrate surface, the method comprising:exposing the substrate surface to a titanium precursor to form a titanium-containing film on the substrate surface;
purging unreacted titanium precursor from the substrate surface;
exposing the titanium-containing film on the substrate surface to a nitrogen reactant to form a TiN film on the substrate surface;
purging unreacted nitrogen reactant from the substrate surface; and
exposing the TiN film on the substrate surface to an aluminum precursor to form a TiAlN film, wherein the titanium precursor comprises substantially only TiBr4.

US Pat. No. 10,170,320

FEATURE FILL WITH MULTI-STAGE NUCLEATION INHIBITION

Lam Research Corporation,...

1. A method comprising:providing a substrate including a feature having one or more feature openings and a feature interior; and
performing a multi-stage inhibition treatment comprising exposing the feature to a plasma generated from a treatment gas in multiple stages and multiple intervals, with successive stages separated by one of the multiple intervals, wherein one or more of a plasma source power, a substrate bias power, or a treatment gas flow rate is reduced at the start of each interval and increased at the end of the interval, and wherein the inhibition treatment preferentially inhibits nucleation of a metal at the feature openings.

US Pat. No. 10,170,318

SELF-ALIGNED CONTACT AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

15. A device comprising:a gate stack over a semiconductor structure, the semiconductor structure having a first source/drain region, a second source/drain region, and a channel region interposed between the first source/drain region and the second source/drain region, the gate stack being over the channel region;
a gate mask over the gate stack, the gate mask comprising:
a first dielectric layer over the gate stack, the first dielectric layer having a first Cl content;
a second dielectric layer over the first dielectric layer, the second dielectric layer having a second Cl content, the first Cl content being different from the second Cl content; and
a third dielectric layer over the second dielectric layer, a first portion of the third dielectric layer having a lower etch rate than a second portion of the third dielectric layer; and
a capping layer over the gate mask.

US Pat. No. 10,170,317

SELF-PROTECTIVE LAYER FORMED ON HIGH-K DIELECTRIC LAYER

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a first gate structure and a second gate structure formed on a substrate; wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further comprises:
a gate dielectric layer;
a self-protective layer having metal phosphate; and
the first work function metal on the self-protective layer.

US Pat. No. 10,170,316

CONTROLLING THRESHOLD VOLTAGE IN NANOSHEET TRANSISTORS

International Business Ma...

1. A semiconductor device comprising:a nanosheet stack over a substrate, the nanosheet stack comprising a first nanosheet vertically stacked over a second nanosheet;
an inner nitride layer on a surface of each nanosheet; and
a doped transition metal layer on each inner nitride layer formed from alternating pulses of a first precursor comprising a transition metal and a second precursor comprising an aluminum carbide.

US Pat. No. 10,170,314

PULSED LASER ANNEAL PROCESS FOR TRANSISTOR WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN

Intel Corporation, Santa...

1. A transistor, comprising:a semiconductor substrate including a channel region disposed below a gate stack; and
semiconductor source/drain regions coupled to the channel region and disposed on opposite ends of the channel region with the gate stack disposed there between, wherein the semiconductor source/drain regions comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth, the super-activated dopant region having a higher activated dopant concentration than the activated dopant region, wherein the melt depth is substantially the same along the entirety of the semiconductor source/drain regions, and wherein the higher activated dopant concentration is a constant over the super-activated dopant region while the activated dopant concentration is not a constant over activated dopant region.

US Pat. No. 10,170,313

SYSTEMS AND METHODS FOR A TUNABLE ELECTROMAGNETIC FIELD APPARATUS TO IMPROVE DOPING UNIFORMITY

Taiwan Semiconductor Manu...

8. A dopant tool comprising:a chamber sized to contain a wafer;
a plasma generator to accelerate particles toward a wafer support structure; and
an electromagnetic structure disposed between the plasma generator and the wafer support structure, the electromagnetic structure encircling the wafer support structure, wherein the electromagnetic structure comprises a plurality of electromagnetic elements whose positions are movable independently of each other.

US Pat. No. 10,170,312

SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer, comprising:providing the semiconductor wafer with a first dopant concentration of a dopant having a first conductivity type;
forming a polysilicon layer over the front surface;
forming an oxide layer over a back surface of the semiconductor wafer;
removing the polysilicon layer from the front surface; and
depositing the epitaxial layer at the front surface with a second dopant concentration of the dopant having the first conductivity type under a predetermined temperature, the second dopant concentration being lower than the first dopant concentration,
wherein a defect density in a center portion of the semiconductor wafer is below 1E9/cm3 from a cross sectional perspective after depositing the epitaxial layer at the front surface.

US Pat. No. 10,170,311

METHOD FOR HANDLING THIN BRITTLE FILMS

International Business Ma...

1. A method comprising:providing a structure comprising:
a spalled layer having a first side and a second side; anda tape layer formed on the first side of the spalled layer, wherein the tape layer is provided at below a first temperature range, wherein the structure comprises providing a stressor layer on the first side of the spalled layer, and a providing the tape layer as a handle layer on the stressor layer;applying a temporary substrate layer to the second side of the spalled layer,
wherein the temporary substrate layer is applied at a second temperature range, and
wherein at least a portion of the second temperature range is lower than the first temperature range;
after applying the temporary substrate layer, separating the tape layer from the spalled layer; and
after separating the tape layer from the spalled layer, separating the stressor layer from the spalled layer.

US Pat. No. 10,170,310

METHOD OF FORMING PATTERNED STRUCTURE

UNITED MICROELECTRONICS C...

1. A method of forming a patterned structure, comprising:forming a dielectric layer and a material layer on a substrate sequentially;
forming a hard mask layer on the material layer, wherein the material of the hard mask layer is identical to the material of the dielectric layer;
forming a first patterned mask on the hard mask layer and performing a first etching process using the first patterned mask as a mask for forming at least one first opening in the hard mask layer, wherein the first opening exposes at least a part of the material layer;
removing the first patterned mask after the first etching process;
forming a second patterned mask on the hard mask layer and performing a second etching process using the second patterned mask as a mask after the first etching process for forming at least one second opening in the hard mask layer, wherein the second opening exposes at least a part of the material layer, and the second opening partially overlaps the first opening;
performing a third etching process to the material layer with the hard mask layer having the first opening and the second opening as a mask for removing the material layer exposed by the first opening and the second opening; and
performing a fourth etching process to the dielectric layer and the hard mask layer after the third etching process for removing the hard mask layer and forming a trench in the dielectric layer.

US Pat. No. 10,170,308

FABRICATING SEMICONDUCTOR DEVICES BY CROSS-LINKING AND REMOVING PORTIONS OF DEPOSITED HSQ

International Business Ma...

1. A method of manufacturing a semiconductor device, comprising:forming a hydrogen silesquioxane (HSQ) layer on a semiconductor substrate;
forming a cap layer on the HSQ layer;
cross-linking a portion of the HSQ layer under the cap layer;
removing another portion of the HSQ layer which was not cross-linked;
forming a dielectric layer on the substrate, wherein the dielectric layer is positioned between the HSQ layer and the semiconductor substrate;
forming at least one opening exposing a portion of the semiconductor substrate through the cap layer, HSQ layer and dielectric layer; and
epitaxially growing a III-V semiconductor material from the exposed portion of the semiconductor substrate, wherein the III-V semiconductor material occupies a vacant area left by the removal of the other portion of the HSQ layer was not cross-linked;
wherein the removing comprises introducing a developer through the at least one opening to remove the other portion of the HSQ layer which was not cross-linked.

US Pat. No. 10,170,307

METHOD FOR PATTERNING SEMICONDUCTOR DEVICE USING MASKING LAYER

Taiwan Semiconductor Manu...

1. A method comprising:forming a first mask layer on a substrate;
patterning first spacers over the first mask layer;
forming an anti-reflective layer over the first spacers;
forming an etch stop layer over the anti-reflective layer;
forming a second mask layer over the etch stop layer;
patterning first openings in the second mask layer, each of the first openings overlying respective pairs of the first spacers;
after patterning the first openings, patterning second openings in the second mask layer, each of the second openings overlying respective pairs of the first spacers;
extending the first and second openings through the anti-reflective layer and between the respective pairs of the first spacers;
forming a reverse material over the second mask layer and in the first and second openings;
removing the anti-reflective layer, the etch stop layer, the second mask layer, and portions of the reverse material; and
patterning the first mask layer using the first spacers and remaining portions of the reverse material as a first etching mask.

US Pat. No. 10,170,306

METHOD OF DOUBLE PATTERNING LITHOGRAPHY PROCESS USING PLURALITY OF MANDRELS FOR INTEGRATED CIRCUIT APPLICATIONS

Taiwan Semiconductor Manu...

1. A method comprising:forming mandrels comprising a first mandrel strip, wherein the first mandrel strip comprises a first portion and a second portion separated from each other by a first opening;
depositing a blanket spacer layer over the first mandrel strip;
etching horizontal portions of the blanket spacer layer to form spacers, wherein the first opening is filled by a portion of the spacers;
etching the first portion and the second portion of the first mandrel strip to form a second opening and a third opening encircled by the mandrels and the spacers; and
using the mandrels and the spacers as an etching mask to etch a target layer, with trenches formed in the target layer.

US Pat. No. 10,170,305

SELECTIVE FILM GROWTH FOR BOTTOM-UP GAP FILLING

Taiwan Semiconductor Manu...

1. A method comprising:etching a portion of a semiconductor material between isolation regions to form a trench;
forming a first semiconductor seed layer extending on a bottom surface and sidewalls of the trench;
etching-back the first semiconductor seed layer until a top surface of the first semiconductor seed layer is lower than top surfaces of the isolation regions;
performing a first selective epitaxy to grow a first semiconductor region from the first semiconductor seed layer; and
forming an additional semiconductor region over the first semiconductor region to fill the trench.

US Pat. No. 10,170,303

GROUP IIIA NITRIDE GROWTH SYSTEM AND METHOD

1. A method for growing a gallium nitride (GaN) structure comprising:providing a template having a surface; and
growing at least a first GaN layer on the template using a first sputtering process, wherein the first sputtering process includes:
growing the at least first GaN layer under at least two surface conditions, wherein the two surface conditions include a gallium-rich surface condition and a gallium-lean surface condition, wherein the gallium-rich surface condition includes a gallium-to-nitrogen ratio having a first value that is greater than 1, wherein the gallium-lean surface condition includes the gallium-to-nitrogen ratio having a second value that is less than the first value;
alternating between the two surface conditions for at least a first growing under a first of the two surface conditions, a second growing under a second of the two surface conditions after the first growing, and a third growing under the first of the two surface conditions after the second growing.

US Pat. No. 10,170,302

SUPERLATTICE LATERAL BIPOLAR JUNCTION TRANSISTOR

International Business Ma...

1. A method for forming a bipolar junction transistor, comprising:patterning an extrinsic base on a superlattice stack including a plurality of alternating layers of semiconductor material on a substrate;
etching an intrinsic base in the superlattice stack; and
growing a collector and emitter adjacent to the intrinsic base on opposite sides of the intrinsic base.

US Pat. No. 10,170,301

ADHESION OF POLYMERS ON SILICON SUBSTRATES

INTERNATIONAL BUSINESS MA...

1. A method for adhering a polymer to a surface of a substrate, the method comprising:forming a substrate;
forming a modified surface of the substrate, where the modified surface comprises X—H terminations;
forming a polymer on the modified surface of the substrate, the polymer comprising a self-crosslinkable organic planarization layer (OPL) comprising hydroxyl, alkene, or alkyne functional group functional groups; and
chemically bonding the polymer to the modified surface of the substrate.

US Pat. No. 10,170,300

PROTECTIVE FILM FORMING METHOD

Tokyo Electron Limited, ...

1. A protective film forming method, comprising steps of:depositing an oxide film of either an organic metal compound or an organic metalloid compound on a flat surface region between adjacent recessed shapes formed in a surface of a substrate; and
removing a lateral portion of the oxide film deposited on the flat surface region by etching.

US Pat. No. 10,170,299

METHOD TO REDUCE TRAP-INDUCED CAPACITANCE IN INTERCONNECT DIELECTRIC BARRIER STACK

Applied Materials, Inc., ...

1. A method for forming an interconnect on a substrate, comprising:depositing a continuous barrier layer on the substrate formed from SiOC;
depositing a transition layer on the barrier layer formed from SiCN after depositing the continuous barrier layer; and
depositing an etch-stop layer on the transition layer formed from AlN after depositing the transition layer, wherein the transition layer shares a first common element with every layer contacting a bottom surface of the transition layer, and wherein the transition layer shares a second common element with every layer contacting a top surface of the transition layer, the first common element different from the second common element.

US Pat. No. 10,170,298

HIGH TEMPERATURE SILICON OXIDE ATOMIC LAYER DEPOSITION TECHNOLOGY

APPLIED MATERIALS, INC., ...

1. A method of depositing a film, the method comprising:exposing a wafer surface to a silicon precursor that adsorbs onto the wafer surface, the silicon precursor comprising R3Si:NY3, wherein each R is independently selected from hydrogen, Cl, Br, I, a linear or branched C1-C10 alkyl group, a linear or branched C1-C10 alkoxy group, and a C6-C10 aryl group, and each Y is independently selected from the group consisting of Cl, Br, I, a linear or branched C1-C10 alkylsilyl group, and a C6-C10 aryl group;
heating the wafer surface to a temperature in the range of about 450° C. to about 650° C. to decompose the adsorbed silicon precursor on the wafer surface to form a monolayer or sub-monolayer silicon film; and
exposing the monolayer or sub-monolayer silicon film and wafer surface to an oxygen source, wherein the oxygen source reacts with the monolayer or sub-monolayer silicon film to form a monolayer or sub-monolayer SiO2 film.

US Pat. No. 10,170,296

TIN PULL-BACK AND CLEANING COMPOSITION

BASF SE, Ludwigshafen (D...

1. A composition, comprising the following components a)-f), based on total weight of the composition:a) 0.05-4 wt. % of an aliphatic or aromatic sulfonic acid;
b) 0.1 to 10 wt % of an inhibitor selected from the group consisting of imidazolidinones, imidazolidines, and 2-oxazolidinones;
c) 5 to 50 wt % of an aprotic solvent;
d) 1 to 60 wt % of a glycol ether;
e) water; and
an oxidant,
wherein a weight ratio of the aprotic solvent to the water is from 1:10 to 2:1 and wherein the oxidant is present in a volume ratio of components a) to e)to the oxidant ranging from 65:1 to 8:1.

US Pat. No. 10,170,295

FLUX RESIDUE CLEANING SYSTEM AND METHOD

Taiwan Semiconductor Manu...

11. A method comprising:softening an outer region of a flux residue formed around conductive connectors interposed between a wafer and a die by immersing the wafer and the die in a first chemical, the wafer having a first side, the die being disposed on the first side of the wafer;
after the softening the outer region of the flux residue, removing the outer region of the flux residue to expose an inner region of the flux residue by discharging a first chemical spray in a first spray chamber, the first chemical spray impinging on the flux residue, the removing the outer region of the flux residue comprising rotating the wafer during the impinging the first chemical spray upon the wafer in the first spray chamber;
after the removing the outer region of the flux residue, softening the inner region of the flux residue formed around conductive connectors interposed between the wafer and the die by immersing the wafer and the die in a second chemical, the second chemical comprising a surfactant; and
after the softening the inner region of the flux residue, removing the inner region of the flux residue by discharging a second chemical spray in a second spray chamber, the first chemical spray or the second chemical spray or both comprising deionized water.

US Pat. No. 10,170,293

ENHANCED LIGHTING CERAMIC METAL-HALIDE LAMP ASSEMBLY

1. An enhanced lighting ceramic metal-halide lamp assembly, the assembly comprising:an at least partially transparent container defined by an inner surface, an outer surface, a pair of sealed conductive ends, and an inner volume defined by a vacuum;
a plurality of ceramic arc tubes disposed in the inner volume of the at least partially transparent container, the ceramic arc tubes being filled with an ionizable gaseous mixture;
a ballast disposed in the inner volume of the ceramic arc tubes, the ballast comprising at least one electrode generating an electric arc through the ionizable gaseous mixture;
whereby the electric arc vaporizes the gaseous mixture to generate illumination;
whereby the ceramic arc tube produces about 630 watts of power when illuminating;
a wire extending between the pair of sealed conductive ends of the at least partially transparent container, the wire carrying an electrical current through the ballast;
two U-shaped coupling mechanisms integral to the wire, the two U-shaped coupling mechanisms connecting each of the ceramic arc tubes to one of the sealed conductive ends of the container, the two U-shaped coupling mechanisms defined by a conductive material, the two U-shaped coupling mechanisms being generally resilient;
whereby the two U-shaped coupling mechanisms provide conductivity and a buffering clearance between the ceramic arc tubes and the sealed conductive ends of the container; and
at least one fastening bracket defined by a first end and a second end, the first end engaging the inner surface of the at least partially transparent container for stabilizing the ceramic arc tubes, the second end engaging the ceramic arc tubes.

US Pat. No. 10,170,292

METHOD AND APPARATUS FOR INJECTION OF IONS INTO AN ELECTROSTATIC ION TRAP

Thermo Fisher Scientific ...

1. An apparatus for injecting ions into an electrostatic trap, comprising:an ion source for generating ions;
an ion store downstream of the ion source for receiving ions that have been generated in the ion source;
a non-trapping ion guide downstream of the ion store for receiving ions that have been released by the ion store and for accelerating the received ions into an orbital electrostatic trap downstream of the ion guide; and
a pulser configured to provide a voltage pulse in the ion guide for increasing the average velocity of the ions at the exit of the ion guide from the average velocity of the ions at the entrance to the ion guide, wherein a delay is arranged between releasing the ions from the ion store and providing the voltage pulse to the ion guide such that for ions of the same m/z forming an ion packet, the duration of the ion packet as it enters the electrostatic trap is substantially shorter than when the ion packet enters the ion guide from the ion store.

US Pat. No. 10,170,291

APPARATUS FOR ON-LINE MONITORING PARTICLE CONTAMINATION IN SPECIAL GASES

Industrial Technology Res...

1. An apparatus for on-line monitoring particle contamination in a special gas, comprising:a single particle inductively coupled plasma mass spectrometry (sp-ICPMS); and
a gas exchange device, coupled to the sp-ICPMS and comprising:
a corrosion resistant outer tube; and
a polytetrafluoroethylene (PTFE) inner tube, disposed inside the corrosion resistant outer tube, a gap being formed between the corrosion resistant outer tube and the PTFE inner tube, and a length of the PTFE inner tube being 1 meter or more, wherein
the gap is applied for flowing an argon gas, and the PTFE inner tube is applied for flowing the special gas.

US Pat. No. 10,170,289

PHOTOTUBE AND METHOD OF MAKING IT

Shenzhen Genorivision Tec...

1. A phototube suitable for detecting a photon, the phototube comprising:an electron ejector configured for emitting electrons in response to an incident photon;
a detector configured for collecting the electrons and providing an output signal representative of the incident photon;
an electrode configured for applying a voltage to drive the electrons to the detector;
one or more sidewalls forming an envelope of a hole between the electrode and the detector, wherein the electron ejector is inside the hole and bonded to the electrode, wherein the hole is in a substrate; and
a metal wall at the one or more sidewalls, wherein the metal wall is configured for applying a voltage to drive the electrons away from the sidewalls.

US Pat. No. 10,170,287

TECHNIQUES FOR DETECTING MICRO-ARCING OCCURRING INSIDE A SEMICONDUCTOR PROCESSING CHAMBER

Taiwan Semiconductor Manu...

1. A system comprising:a radio frequency (RF) generator configured to output a RF signal;
a transmission line coupled to the RF generator;
a plasma chamber coupled to RF generator via the transmission line, wherein the plasma chamber is configured to generate a plasma based on the RF signal; and
a micro-arc detecting element configured to determine whether a micro-arc has occurred in the plasma chamber based on the RF signal;
wherein the micro-arc detecting element comprises:
a magnetic-field sensor configured to generate a magnetic-field signal based on the RF signal passing through the transmission line; and
analysis circuitry configured to evaluate the magnetic-field signal to determine whether the micro-arc has occurred in the plasma chamber.

US Pat. No. 10,170,284

PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method comprising:preparing a plasma processing apparatus, the plasma processing apparatus comprising:
a chamber;
a lower electrode disposed in the chamber;
an upper electrode disposed in the chamber and facing the lower electrode;
a focus ring disposed in the chamber and surrounding a peripheral edge of the lower electrode; and
a plurality of annular coils disposed on an upper portion of the upper electrode and being concentric with a substrate to be placed on the lower electrode, one of the annular coils being disposed outside the peripheral edge of the lower electrode, the others of the annular coils being disposed inside the peripheral edge of the lower electrode;
placing the substrate on the lower electrode, with a peripheral edge of the substrate surrounded by the focus ring;
introducing process gas into the chamber;
applying high-frequency power across the upper electrode and the lower electrode to generate plasma of the process gas;
generating a magnetic field by supplying a current only to the one of the annular coils to level an interface of a plasma sheath on an upper portion of the substrate with the interface of the plasma sheath on an upper portion of the focus ring for reducing the occurrence of tilting in a pattern formed on the substrate by etching with the plasma, wherein a horizontal component of the magnetic field generated from the one of the annular coils has the highest value outside the peripheral edge of the substrate; and
varying the current to be supplied to the one of the annular coils according to a worn state of the focus ring.

US Pat. No. 10,170,283

FOCUS RING FOR PLASMA PROCESSING APPARATUS

COORSTEK KK, Tokyo (JP)

1. A focus ring made of silicon comprising:a plurality of arc-shaped members, each of the plurality of arc-shaped members including a flat plate portion having an arc shape, open-topped first depressions formed at both circumferential ends of the flat plate portion, a stepped portion formed with an open-topped second depression at an inner circumferential side of the flat plate portion, and convex fitting portions formed on bottom surfaces of the first depressions;
a plurality of connecting members connecting the plurality of arc-shaped members to form a ring shape without an adhesive, each of the plurality of connecting members including a plate-like main body having an arc shape to be accommodated within the first depressions of the adjacent arc-shaped members, a stepped portion formed with an open-topped depression at an inner circumferential side of the plate-like main body, and concave fitting portions formed in a lower surface of the plate-like main body and configured to engage with the respective convex fitting portions of the adjacent arc-shaped members,
wherein a thickness between an upper surface of the connecting member and a bottom surface of the concave fitting portion of the connecting member is greater than a thickness between an upper surface of the arc-shaped member and a bottom surface of the second depression of the arc-shaped member; and
wherein the plurality of arc-shaped members is disposed to be in contact with one another at opposing end portions of the arc-shaped members, thereby forming a ring shape, and the connecting members are accommodated in the first depressions of the adjacent arc-shaped members, and wherein the plurality of arc-shaped members is connected with the connecting members whereby the concave fitting portions of the connecting members are engaged with the convex fitting portions of the arc-shaped members,
wherein the concave fitting portions of the connecting members are not positioned above end surfaces of the opposing end portions of the adjacent arc-shaped members, and
wherein when the connecting member engages the arc-shaped members, a gap is formed between the convex fitting portion of the arc-shaped member and the concave fitting portion of the connecting member, the gap being equal to or greater than 50 ?m and equal to or less than 100 ?m.

US Pat. No. 10,170,282

INSULATED SEMICONDUCTOR FACEPLATE DESIGNS

Applied Materials, Inc., ...

1. A semiconductor processing chamber faceplate comprising:a conductive plate defining a plurality of apertures; and
a plurality of inserts, wherein each aperture of the plurality of apertures contains an insert of the plurality of inserts, wherein each insert of the plurality of inserts defines at least two channels there through, wherein each channel of the at least two channels independently extends vertically from a first end of an associated insert to a second end of the associated insert, wherein each channel of the at least two channels is radially offset from a central axis through the insert defining the at least two channels, and wherein the at least two channels are radially offset from one another about the central axis;
a plurality of first o-rings positioned within annular channels at least partially defined by the conductive plate within the plurality of aperture;
wherein a portion of each first o-ring of the plurality of first o-rings is seated within a first annular groove defined along a region of a corresponding insert between a top and bottom of the corresponding insert.

US Pat. No. 10,170,280

PLASMA REACTOR HAVING AN ARRAY OF PLURAL INDIVIDUALLY CONTROLLED GAS INJECTORS ARRANGED ALONG A CIRCULAR SIDE WALL

Applied Materials, Inc., ...

1. A plasma reactor comprising:a cylindrical vacuum chamber enclosure;
an RF plasma source power applicator and an RF source power generator coupled to said applicator;
plural passages extending in a radial direction through said vacuum chamber enclosure and being spaced apart along a circumference of said vacuum chamber enclosure;
a process gas supply;
a succession of detachable gas flow lines spaced from and outside of said vacuum chamber enclosure and arranged end-to-end around the circumference of said vacuum chamber enclosure, and a gas supply line coupled between said succession of detachable gas flow lines and said process gas supply;
plural external gas flow valves outside of said vacuum chamber enclosure and coupled between successive ones of said gas flow lines at respective locations spaced apart relative to said circumference of said vacuum chamber enclosure, each of said valves having: (a) a controlled gas output port individually coupled to a respective one of said plural passages, (b) a valve control input governing gas flow through said controlled gas output port, (c) an input flow-through port connected to a first one of a corresponding pair of said gas flow lines, (d) an output flow-through port connected to the other one of the corresponding pair of said gas flow lines, (e) a flow-through passage between said input and output flow-through ports, wherein each of said gas flow lines is separately disconnectable from the valve to which it is connected;
a workpiece support within said vacuum chamber enclosure having a support surface for supporting a workpiece; and
a gas valve configuration controller controlling the valve control input of each of said valves.

US Pat. No. 10,170,279

MULTIPLE COIL INDUCTIVELY COUPLED PLASMA SOURCE WITH OFFSET FREQUENCIES AND DOUBLE-WALLED SHIELDING

Applied Materials, Inc., ...

1. A plasma reactor comprisinga window assembly;
first and second coil antennas adjacent said window assembly;
a first current distributor coupled to said first coil antenna and a second current distributor coupled to said second coil antenna;
first and second RF feed terminals;
first and second RF power sources coupled to said first and second RF feed terminals respectively;
a conductive feed plate lying in a plane above said first and second coil antennas and coupled to said second RF feed terminal, and a plurality of axial rods coupled between a peripheral annular zone of said conductive feed plate and said second current distributor;
a conductive ground plate in a plane between said conductive feed plate and said first current distributor; and
a first radial conductive feed rod lying in a plane above said conductive ground plate and having an inner end coupled to said first current distributor and an outer end coupled to said first RF feed terminal.

US Pat. No. 10,170,278

INDUCTIVELY COUPLED PLASMA SOURCE

APPLIED MATERIALS, INC., ...

1. An inductively coupled plasma apparatus, comprising:a bottom wall comprising a hub having a plurality of radially outwardly directed spokes and a ring having a corresponding plurality of radially inwardly directed spokes, wherein each radially inwardly directed spoke lies along a common radius as a corresponding one of the plurality of radially outwardly directed spokes, wherein the hub and the ring are each electrically conductive, and wherein the hub has a central opening aligned with a central axis of the inductively coupled plasma apparatus;
a plurality of capacitors, one each disposed between and coupling respective ends of each radially outwardly directed spoke and corresponding radially inwardly directed spoke;
a top wall spaced apart from and above the bottom wall, wherein the top wall has a central opening aligned with the central axis, and wherein the top wall is electrically conductive;
a sidewall electrically connecting the ring to the top wall; and
a tube electrically connecting the hub to the top wall, the tube having a central opening aligned with the central axis.

US Pat. No. 10,170,277

APPARATUS AND METHODS FOR DRY ETCH WITH EDGE, SIDE AND BACK PROTECTION

Applied Materials, Inc., ...

1. An apparatus for processing a substrate, comprising:a chamber body having a chamber sidewall and a bottom defining a processing volume;
a supporting assembly disposed in the processing volume, wherein the supporting assembly comprises a raised portion for supporting the substrate during processing;
a plasma source configured to generating or supplying a plasma in the processing volume;
an edge protection plate movably disposed in the processing volume above and spaced apart from the supporting assembly, wherein the edge protection plate has a center opening formed in a central region and the center opening has substantially vertical walls, wherein the center opening has a size to shield only an edge of the substrate during processing, wherein the edge protection plate further includes a plurality of through holes formed therein, wherein the through holes are configured to allow a first plurality of supporting legs passing therethrough from the supporting assembly and the edge protection plate is spaced apart from the chamber sidewalls; and
an edge shield disposed against a periphery of the edge protection plate and spaced apart from the support assembly and the chamber sidewalls, the edge shield covering a vertical sidewall of the edge protection plate.

US Pat. No. 10,170,276

METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A PATTERN DENSITY-OUTLIER-TREATMENT FOR OPTIMIZED PATTERN DENSITY UNIFORMITY

TAIWAN SEMICONDUCTOR MANU...

1. A method of semiconductor device fabrication, comprising:receiving an integrated circuit (IC) layout pattern including a plurality of templates;
identifying, from the plurality of templates, a first template having a first layout pattern with a first pattern density (PD) and a second template having a second layout pattern with a second PD less than the first PD;
splitting the first template into a plurality of subset templates, wherein each subset template of the plurality of subset templates includes a portion of the first layout pattern, and wherein each subset template has a subset PD that satisfies a PD target;
performing a PD uniformity (PDU) optimization to the second template; and
performing multiple individual electron beam (e-beam) lithography exposure processes with an e-beam lithography tool to a semiconductor substrate, using respective ones of the subset templates, thereby patterning the semiconductor substrate.

US Pat. No. 10,170,275

CRYOGENIC SPECIMEN PROCESSING IN A CHARGED PARTICLE MICROSCOPE

FEI Company, Hillsboro, ...

1. A method comprising:directing a charged-particle beam onto a portion of a specimen, situated in a vacuum chamber and maintained at a cryogenic temperature so as to perform a surface modification thereof;
providing a thin film monitor in the vacuum chamber and maintaining at least a detection surface thereof at a cryogenic temperature; and
using the thin film monitor to measure a precipitation rate of frozen condensate in the vacuum chamber,
wherein when either the precipitation rate falls below a first pre-defined threshold, the surface modification is initiated, or when the precipitation rate rises above a second pre-defined threshold, the surface modification is interrupted, or both.

US Pat. No. 10,170,272

SYSTEM AND METHOD FOR USE IN ELECTRON MICROSCOPY

1. An electron beam shaping unit for use in electron beam column, the electron beam shaping unit is configured for affecting multi electron wave function and comprising a mask unit configured for affecting propagation of electrons therethrough to thereby form at far field thereof a propagating electron beam having radial shape as determined by MENL function being an eigen function determined by a multi-electron Hartree-Fock Hamiltonian.

US Pat. No. 10,170,270

ION SOURCE

WISCONSIN ALUMNI RESEARCH...

1. An ion source device for producing an ion beam, comprising:a housing having an opening;
a first electrode within the housing and having a first side facing the opening, the first electrode is configured to provide a first electric field toward the opening; and
a second electrode having an end within the housing, the second electrode is configured to maintain one, or both of, a presence of electrons or a seed plasma between the first electrode and the opening when the first electric field is absent.

US Pat. No. 10,170,268

DISCRETE DYNODE ELECTRON MULTIPLIER FABRICATION METHOD

Harris Corporation, Melb...

1. A process of manufacturing a discrete-dynode electron multiplier (DDEM) comprising the steps of:mounting at least one insulator block to a monolithic conductor block;
forming a series of ion-optics geometrical structures in the monolithic conductor block, each ion-optics geometrical structure having a smallest dimension of less than 1 millimeter;
forming an opening in the monolithic conductor block; and
connecting a circuit board to the DDEM by positioning a fastener through the opening in the monolithic conductor block and through an opening in the circuit board.

US Pat. No. 10,170,266

WIRE-WOUND FUSE RESISTOR AND METHOD FOR MANUFACTURING SAME

1. A wire-wound fuse resistor, comprising:an insulating rod having a first end and a second end;
a metal wire having a wire head and a wire tail, being helically wound around the insulating rod from the first end to the second end, and being cut at a middle portion thereof to form a first winding wire connecting with the wire head and a second winding wire connecting with the wire tail, wherein the first winding wire and the second winding wire are separated from each other;
a connection part disposed at the cut portion for electrical connection between the first winding wire and the second winding wire, wherein the melting temperature of the connection part is lower than that of the first winding wire and the second winding wire; and
a first cap and a second cap respectively disposed to encapsulate the first end and the second end, in which the wire head and the wire tail are respectively soldered onto surfaces of the first cap and the second cap respectively at the first cap and the second cap, and the first cap and the second cap are respectively electroplated with a first cap electroplated layer and a second cap electroplated layer, wherein the first electroplated layer on the first cap, the second electroplated layer on the second cap and the connection part are formed in the same process, and wherein the connection part is cut off depending on a predetermined melting temperature or melting speed of the wire-wound fuse reistor.

US Pat. No. 10,170,265

LEAKAGE CURRENT PROTECTION DEVICE

Chengli Li, Suzhou (CN)

1. A leakage current protection device, comprising:a top cover, a base, and an electrical and mechanical assembly disposed therein, the electrical and mechanical assembly comprising:
a circuit board;
one or more moving contact plates, for electrically connecting and disconnecting a load circuit;
an auxiliary switch, for electrically connecting and disconnecting an auxiliary circuit;
a reset shaft, wherein an upper portion of the reset shaft is configured to be connected to a reset button, a lower portion of the reset shaft includes a hook, a bottom end of the reset shaft is set against one end of a reset spring, and another end of the reset spring is set against the base;
a disconnect mechanism, wherein an upper portion of the disconnect mechanism has a hook which is configured to be engageable in a vertical direction with the hook of the reset shaft;
a trip coil and a trip plunger disposed in the trip coil, which are disposed on a side of the disconnect mechanism and controlled by electrical circuitry on the circuit board,
wherein the disconnect mechanism is driven by the trip plunger to move horizontally to cause the hook of the reset shaft and the hook of the disconnect mechanism to disengage from each other,
wherein the disconnect mechanism further includes a pushing end disposed at its top, and one or more lifting levers, wherein the pushing end of the disconnect mechanism controls the auxiliary switch and the one or more lifting levers control the one or more moving contact plates.

US Pat. No. 10,170,264

INFORMATION DISPLAY SYSTEM FOR SWITCHING DEVICE, SWITCHING DEVICE, AND METHOD

ABB Schweiz AG, Baden (C...

1. An information display system for a switching device having an operating handle, the information display system comprising:a cover having a first side including an opening having the operating handle disposed therethrough, the cover first side defining a first section and a second section thereon, the first section defining a first longitudinal axis extending perpendicularly therethrough, the second section perpendicular to the first longitudinal axis; and
a faceplate including an opening to receive the operating handle therethrough, selectively secured to the first side in one of a plurality of rest positions and configured to carry information about the switching device, wherein in each one of the plurality of rest positions, at least a portion of the second section of the cover is overlapped by the faceplate, at least a portion of the first section is aligned with the opening, and the operating handle is disposed through the opening;
wherein the faceplate is rotatable with respect to the cover about the first longitudinal axis.

US Pat. No. 10,170,262

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHODS OF MANUFACTURE AND DESIGN STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A MEMS structure, comprising:fixed actuator electrodes and a contact point;
a MEMS beam over the fixed actuator electrodes and the contact point; and
an array of actuator bumps in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from contacting an actuator portion of the fixed actuator electrodes, wherein the array of actuator bumps are in direct contact with and extending from at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes, and the array of actuator bumps are composed of a dielectric material.

US Pat. No. 10,170,261

CONTACT DEVICE AND ELECTROMAGNETIC CONTACTOR USING SAME

1. A contact device comprising:a main contact mechanism that includes a pair of main fixed contacts separated from each other, a main movable contact disposed so as to be contacted with and separated from the pair of main fixed contacts, and a main contact support portion elastically supporting the main movable contact;
an auxiliary contact mechanism that is disposed at a different position from a position of the main contact mechanism, and that includes a pair of auxiliary fixed contacts separated from each other, an insulating auxiliary contact holding member supporting the main contact support portion and having an auxiliary movable contact disposed therein so as to be contacted with and separated from the pair of auxiliary fixed contacts, and an auxiliary contact support portion supporting the auxiliary contact holding member;
a contact housing portion that houses the main contact mechanism and the auxiliary contact mechanism; and
a movable iron core with which the auxiliary contact support portion is fixed,
wherein
the auxiliary contact support portion and the main contact support portion are formed as a movable shaft to move the main movable contact and the auxiliary movable contact, and
the auxiliary contact support portion and the main contact support portion are divided from each other and connected together via the auxiliary contact holding member so that the main contact support portion connects the main movable contact and the insulating auxiliary contact holding member, and the auxiliary contact support portion connects the insulating auxiliary contact holding member and the movable iron core.

US Pat. No. 10,170,260

ELECTROMAGNETIC RELAY

OMRON Corporation, Kyoto...

1. An electromagnetic relay comprising:a base;
an electromagnet block having a spool in which a through hole opening at a flange portion is formed, the electromagnet block being mounted on an upper surface of the base;
a movable iron piece configured to be rotatable based on excitation and non-excitation of the electromagnet block;
a movable contact piece configured to be rotatable integrally with the movable iron piece;
a movable contact fixed to a free end of the movable contact piece; and
a fixed contact fixed to a fixed contact terminal, and disposed so as to be connected with and separable from the movable contact along with rotation of the movable contact piece, wherein
an insulating rib is formed in a projecting manner on at least one of an inward facing surface of a spacer integrally formed with the movable iron piece and an outward facing surface of the flange portion such that the insulating rib intercepts a straight line which connects a magnetic pole portion which is one end portion of an iron core which projects from the through hole and the fixed contact or the fixed contact terminal with a shortest distance.

US Pat. No. 10,170,256

CIRCUIT BREAKER EQUIPPED WITH AN EXTENSIBLE EXHAUST COVER

GENERAL ELECTRIC TECHNOLO...

1. A medium-, high-, or very high-voltage circuit breaker, comprising at least one arc-control chamber and an outer casing defining a space in which the arc-control chamber is arranged, said arc-control chamber comprising:a first set of electrical contacts and a second set of electrical contacts, arranged at least in such a manner as to enable closing and opening operations of the circuit breaker;
an arc blast nozzle; and
a discharge cap forming a portion of an outer wall of the arc-control chamber, the discharge cap being situated in the space and internally defining a gas-flow chamber situated at least in part downstream from the blast nozzle with which the gas-flow chamber communicates, said discharge cap being suitable for including one or more openings for discharging a gas from the gas-flow chamber towards said space; and
a support that is electrically insulating and that mechanically connects the arc-control chamber to an end wall of the outer casing of the circuit breaker;
wherein the discharge cap comprises at least one portion that is movable under an effect of a gas pressure in the gas-flow chamber, so that a volume of the discharge cap is extensible.

US Pat. No. 10,170,255

VACUUM CAPACITOR SWITCH WITH PRE-INSERTION CONTACT

1. A vacuum capacitor switch with a pre-insertion contact, comprising:a vacuum enclosure;
a first contact system includes a moving contact and a stationary contact structure, said stationary contact structure includes a stationary contact support and a stationary contact, said stationary contact support includes a substantial bowl shaped cross section with angled side walls, said stationary contact extends from a bottom of said stationary contact support, said stationary contact structure is retained inside said vacuum enclosure at substantially at one end thereof, said angled side walls form an acute angle with a lengthwise axis of said vacuum enclosure; and
a second contact system includes a moving contact rod, a floating contact rod and a biasing device, said floating contact rod is retained at the other one end of said vacuum enclosure, said biasing device is retained on the other end of said vacuum enclosure, substantially one end of said floating contact rod is retained by said biasing device, the other end of said floating contact rod is biased toward the one end of said vacuum enclosure, said moving contact is retained on said moving contact rod, said biasing device includes a bracket and a threaded adjuster, said bracket is secured to said vacuum enclosure, said threaded adjuster is retained by said bracket, said floating contact rod is threadably engaged with said threaded adjuster, said floating contact rod is axially adjustable relative to said bracket, wherein a load is electrically connected between said stationary contact and said floating rod.

US Pat. No. 10,170,252

MICRO-SWITCH AND METHOD OF MANUFACTURE

JOHNSON ELECTRIC S.A., M...

1. An electric micro-switch comprising a switching mechanism having two stationary electric contacts and at least one counter contact engaged in a spring holder, wherein each stationary contact has a profiled section, and the profiled section has a longitudinal arched extension, a bent portion formed in the longitudinal arched extension and having an outer surface that is, at least in section, formed in a rounded manner, and a contact region defined on the outer surface of the bent portion, a longitudinal direction of the two stationary electric contacts is transverse to a longitudinal direction of the counter contact, the two stationary electric contacts and the spring holder are not coplanar, and a longitudinal extension of the counter contact is perpendicular to the longitudinal extension of the stationary electric contact.

US Pat. No. 10,170,251

CARBON NANOSHEETS

The Governors of the Univ...

1. A method of forming a carbon nanosheet, the method comprising exfoliating crystalline cellulose followed by carbonizing the crystalline cellulose to create carbonized crystalline cellulose, wherein the crystalline cellulose comprises crystalline cellulose hemp fibrils.

US Pat. No. 10,170,250

DYE SENSITIZED PHOTOELECTRIC CONVERSION DEVICE

King Fahd University of P...

1. A dye sensitized photoelectric conversion device, comprising:a layer, comprising:
an anode,
a semiconductor, and
a light absorbing compound;
an iodine redox couple electrolytic solution, and
a passive substrate, comprising:
a cathode,
wherein the semiconductor and the light absorbing compound are between the anode and the cathode,
wherein the light absorbing compound is chemisorbed on the semiconductor;
wherein the semiconductor is a metal oxide, and
wherein the light absorbing compound has formula (I):
wherein A1 is a divalent thiophene group of formula (I?)A2 is a divalent 5-membered heterocyclic group of formula (II?), (III?), (IV?), or (V?):
A3 is an aromatic hydrocarbon chromophore of formula (VI?), (VII?), or (VIII?)

wherein R1 is H, OH, C1-C6 alkyl, Cl, Br, F, or I, m is 1 and n is 0 or 1.

US Pat. No. 10,170,249

MULTI-LAYER CAPACITOR PACKAGE

International Business Ma...

1. A substrate assembly comprising:a first ceramic layer;
a first layer of one or more electrodes connected to the first ceramic layer;
a first high dielectric constant layer connected to the first layer of one or more electrodes,
wherein a quantity of ceramic particles in the first high dielectric constant layer is adjusted to control a dielectric constant of the first high dielectric constant layer,
wherein the ceramic particles are selected from the group consisting of strontium titanate and barium titanate,
wherein the first high dielectric constant layer has a thickness ranging from 1 ?m to 10 ?m;
a second layer of one or more electrodes connected to the first high dielectric constant layer;
a second high dielectric constant layer connected to the first layer of one or more electrodes;
a third layer of one or more electrodes connected to the second high dielectric constant layer;
a second ceramic layer connected to the third layer of one or more electrodes;
two or more holes, wherein each of the two or more holes is formed through at least one ceramic layer, at least one layer of one or more electrodes, and at least one high dielectric constant layer;
electrically conductive structures formed in the two or more holes,
wherein each of the electrically conductive structures is physically connected to at least one of the electrodes, thereby forming at least three sets,
wherein each of the sets is physically separated from at least one of the other sets; and an electrically conductive surface pad at a termination of the two or more holes.

US Pat. No. 10,170,248

STRUCTURE AND METHODS OF FORMING THE STRUCTURE

Micron Technology, Inc., ...

1. An apparatus, comprising:a three-dimensional (3D) memory cell region; and
a peripheral region adjacent to the memory cell region to supply at least one voltage to the 3D memory cell region, the peripheral region including:
a first conductive level, a second conductive level above the first conductive level and a third conductive level above the second conductive level, each of the conductive levels stepped back from an upper surface end portion of an underlying one of remaining ones of the conductive levels; and
first and second dielectric levels, each dielectric level disposed between respective adjacent conductive levels, each of the dielectric levels not covering at least some part of the upper surface end portion of an underlying conductive level.

US Pat. No. 10,170,247

MULTILAYER CAPACITOR AND INSTALLATION STRUCTURE OF MULTILAYER CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer capacitor comprising:a multilayer capacitor main body which includes first and second main surfaces, first and second side surfaces, and first and second end surfaces, the first and second main surfaces extending in a length direction and a width direction, the first and second side surfaces extending in the length direction and a thickness direction, and the first and second end surfaces extending in the width direction and the thickness direction;
a first inner electrode extending in the length direction and the thickness direction and including a first effective portion, a first extending portion, and a second extending portion, the first extending portion being connected to the first effective portion and extending to the second main surface, and the second extending portion being connected to the first effective portion and extending to the second main surface;
a second inner electrode extending in the length direction and the thickness direction and including a second effective portion and a third extending portion, the second effective portion facing the first effective portion in the width direction, and the third extending portion being connected to the second effective portion, not facing the first inner electrode, and extending to the second main surface;
a first terminal electrode which is connected to an exposed portion of the first extending portion at the second main surface and extends across a portion of the second main surface on a side of the first end surface in the length direction and the first end surface;
a second terminal electrode which is connected to the second extending portion at the second main surface and extends across a portion of the second main surface on a side of the second end surface in the length direction and the second end surface; and
a third terminal electrode which is connected to an exposed portion of the third extending portion at the second main surface and extends across a portion of the second main surface between the first terminal electrode and the second terminal electrode in the length direction; wherein
a minimum distance in a direction along the first extending portion and the second extending portion between the first effective portion and the second main surface is shorter than any of a dimension in the thickness direction of the first extending portion, a dimension in the thickness direction of the second extending portion, and a dimension in the thickness direction of the third extending portion;
a minimum distance in a direction along the third extending portion between the second effective portion and the second main surface is shorter than any of the dimension in the thickness direction of the first extending portion, the dimension in the thickness direction of the second extending portion and the dimension in the thickness direction of the third extending portion;
the first effective portion includes a first projecting portion, and a minimum distance between a center region of the first inner electrode and the second main surface is greater than a minimum distance between the first projecting portion and the second main surface;
the first inner electrode is spaced away from the first and second end surfaces;
the first projecting portion projects toward the second main surface in a region where the first extending portion, the second extending portion and the third extending portion are not provided in the length direction when viewed from the width direction;
the second effective portion includes a second projecting portion which projects toward the second main surface in a region where the first extending portion, the second extending portion and the third extending portion are not provided in the length direction when viewed from the width direction;
the first projecting portion is facing the second projecting portion in the width direction;
the first projecting portion and the second projecting portion are arranged at least between the first extending portion and the third extending portion when viewed from the width direction; and
the first projecting portion and the second projecting portion extend across from an edge of the first extending portion on a side of the second end surface in the length direction to an edge of the third extending portion on a side of the first end surface in the length direction when viewed from the width direction.

US Pat. No. 10,170,246

CAPACITOR COMPONENT WITH METALLIC PROTECTION PATTERN FOR IMPROVED MECHANICAL STRENGTH AND MOISTURE PROOF RELIABILITY

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor component comprising:a body including a plurality of dielectric layers having a stacked structure, and first and second internal electrodes which are alternately disposed while having the dielectric layer interposed therebetween; and
first and second external electrodes formed on an outer surface of the body, and connected to the first and second internal electrodes, respectively,
wherein the body includes an active region having capacity by the first and second internal electrodes and a cover region located above and below the active region,
the cover region includes a protection pattern of a metal material having a plate shape connected to the first external electrode or the second external electrode,
the protection pattern does not overlap with an internal electrode having a different polarity among the first and second internal electrodes in a stacking direction of the first and second internal electrodes, and
the protection pattern has a shape having a width greater than that of either of the first and second internal electrodes.

US Pat. No. 10,170,245

METHOD OF MANUFACTURING MULTIPLAYER CAPACITOR

SAMSUNG ELECTRO-MECHANICS...

1. A method of manufacturing a multilayer capacitor, comprising:preparing a sheet;
forming a plurality of inner electrodes on the sheet;
cutting the sheet;
forming a laminate by laminating portions of the cut sheet;
forming a sealing portion on two lateral surfaces of the laminate; and
forming an external terminal on upper and lower surfaces of the laminate,
wherein each of the inner electrodes has at least two lead portions being respectively exposed to the upper and lower surfaces of the laminate,
wherein the inner electrodes include a fist inner electrode and a second inner electrode, the first inner electrode is exposed to the first lateral surface and unexposed from the second lateral surface, and the second inner electrode is exposed to the second lateral surface and unexposed from the fist lateral surface,
wherein the sealing portion which encapsulates the first inner electrode and a second portion which encapsulates the second inner electrode, the fist portion is disposed on the fist lateral surface and the second portion is disposed on the second lateral surface, and
wherein the sealing portion has insulating characteristics.

US Pat. No. 10,170,244

FABRICATION OF POROUS SILICON ELECTROCHEMICAL CAPACITORS

INTEL CORPORATION, Santa...

1. A method of making a charge storage structure, the method comprising:forming pores in a low-purity silicon substrate to form a low purity porous silicon structure wherein the low purity silicon substrate has a purity of 99.999 percent or less purity of silicon; and
forming an electrochemical capacitor comprising one of (1) a first low purity porous silicon structure and a second low purity porous silicon structure separated by an electrical insulator comprising a dielectric material, or (2) a first low purity porous silicon section and a second low purity porous silicon section separated by an electrical insulator comprising a dielectric material.

US Pat. No. 10,170,243

MULTILAYER CERAMIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer ceramic capacitor comprising:a multilayer body including a plurality of dielectric layers that are stacked on one another, a first main surface and a second main surface facing each other, a first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other;
inner electrodes stacked such that the inner electrodes and the plurality of dielectric layers are alternately arranged;
outer electrodes disposed on at least the first end surface and the second end surface; wherein
the inner electrodes include a first inner electrode, a second inner electrode, a third inner electrode, a fourth inner electrode, and a fifth inner electrode;
the first inner electrode, the second inner electrode, the third inner electrode, the fourth inner electrode, and the fifth inner electrode are disposed on different planes;
the first inner electrode includes a first end and a second end, the first end of the first inner electrode extending to the first end surface;
the second inner electrode includes a first end and a second end, the first end of the second inner electrode extending to the second end surface;
the third inner electrode is arranged alternately with each of the first inner electrode and the second inner electrode;
the third inner electrode includes a first end and a second end that do not extend to the first end surface or to the second end surface;
the fourth inner electrode is located between the first inner electrode or the second inner electrode that is closest to the first main surface and the fifth inner electrode;
the fourth inner electrode is located between the first inner electrode or the second inner electrode that is closest to the second main surface and the fifth inner electrode;
the fourth inner electrode includes a first portion located near the first end surface and a second portion located near the second end surface, the first portion and the second portion of the fourth inner electrode are spaced apart from each other in a center portion of the multilayer body in a length direction of the multilayer body, the first portion and the second portion of the fourth inner electrode do not extend to the first end surface or to the second end surface;
the fifth inner electrode is located closest to the first main surface of the multilayer body, and is located closest to the second main surface of the multilayer body;
the fifth inner electrode includes a first portion located near the first end surface and a second portion located near the second end surface, the first portion and the second portion of the fifth inner electrode are spaced apart from each other in the center portion of the multilayer body in the length direction of the multilayer body, an end of the first portion of the fifth inner electrode, which is closer to the first end surface, extends to the first end surface, an end of the second portion of the fifth inner electrode, which is closer to the second end surface, extends to the second end surface;
a first auxiliary electrode is disposed on a same plane as the first inner electrode and spaced apart from the first inner electrode;
a second auxiliary electrode is disposed on a same plane as the second inner electrode and spaced apart from the second inner electrode;
a third auxiliary electrode is disposed on a same plane as the third inner electrode and includes a first portion and a second portion spaced apart from each other with the third inner electrode therebetween;
a fourth auxiliary electrode is disposed on a same plane as the fourth inner electrode and includes a first portion and a second portion such that the first portion and the second portion of the fourth auxiliary electrode are spaced apart from the first portion and the second portion of the fourth inner electrode, respectively;
the first auxiliary electrode extends to the second end surface;
the second auxiliary electrode extends to the first end surface;
the first portion of the third auxiliary electrode extends to the first end surface;
the second portion of the third auxiliary electrode extends to the second end surface;
the first portion of the fourth auxiliary electrode extends to the first end surface;
the second portion of the fourth auxiliary electrode extends to the second end surface.

US Pat. No. 10,170,242

COMPOSITE ELECTRONIC COMPONENT, METHOD OF MANUFACTURING THE SAME, BOARD FOR MOUNTING THEREOF, AND PACKAGING UNIT THEREOF

SAMSUNG ELECTRO-MECHANICS...

1. A composite electronic component comprising:a composite body including a capacitor and an electrostatic discharge (ESD) protection device coupled to each other, the capacitor including a ceramic body in which a plurality of dielectric layers and internal electrodes are stacked with a respective dielectric layer interposed between the internal electrodes, and the ESD protection device including first and second electrodes disposed on the ceramic body, a discharging part disposed between the first and second electrodes, and a protective layer disposed on the first and second electrodes and the discharging part to substantially cover the entirety of upper surfaces of the first and second electrodes and the discharging part;
an input terminal disposed to cover an entirety of a first end surface of the composite body in a length direction of the composite body, partially disposed on a surface of the protective layer in a thickness direction, and connected to internal electrodes of the capacitor and the first electrode; and
a ground terminal disposed to cover an entirety of a second end surface of the composite body in the length direction, partially disposed on a surface of the protective layer in a thickness direction, and connected to internal electrodes of the capacitor and the second electrode,
wherein the protective layer ends, in the length direction, at a respective end surface of the composite body.

US Pat. No. 10,170,241

MULTILAYER ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. A multilayer electronic component, comprising:a multilayer body comprising stacked insulating layers and internal coil parts disposed on the insulating layers;
external electrodes disposed on an outer portion of the multilayer body and connected to the internal coil parts; and
a material layer disposed on an outer surface of an outermost internal coil part among the internal coil parts and having a specific resistance that is lower than a specific resistance of the internal coil parts,
wherein the outermost coil part is disposed adjacent to a side surface of the multilayer body.

US Pat. No. 10,170,240

METHOD FOR FORMING A FRAME CORE HAVING A CENTER LEG FOR AN INDUCTIVE COMPONENT AND FRAME CORE PRODUCED ACCORDINGLY

1. A method for forming a frame core having a center leg for an inductive component, wherein the frame core is formed integrally with the center leg, and wherein an air gap is molded into the center leg during the formation of the frame core.

US Pat. No. 10,170,239

MAGNETIC COIL MANUFACTURING

ROLF PRETTL, Tuebeingen ...

1. A method of manufacturing a magnetic coil for a magnetic actuator, the method comprising the following steps:providing a coil carrier comprising a tubular section and a collar, wherein the coil carrier is arranged for accommodating a coil winding,
providing a magnet pot comprising a defined inner contour which is adapted to the coil carrier,
inserting the coil carrier in the magnet pot, wherein the collar of the coil carrier rests on a seating surface of the magnet pot,
punching the collar with a punch that cooperates with the magnet pot, wherein, at the collar, a flange contour is formed such that an outline is defined by the inner contour of the magnet pot,
arranging the coil carrier in the magnet pot, wherein the flange contour is arranged in a fashion recessed with respect to the seating surface, and
at least sectionally filling the magnet pot with a filler material, wherein the flange contour provides a barrier for the filler material.

US Pat. No. 10,170,238

HAND TOOL DEVICE HAVING AT LEAST ONE CHARGING COIL

ROBERT BOSCH GMBH, Stutt...

1. A hand tool device, comprising:at least one charging coil for inductive charging which includes at least one coil core which is at least partially made of a ceramic material and which is provided for transmitting energy, and at least one wound electrical conductor;
wherein the coil core is configured as a composite component, has at least two magnetic field bundling elements including an upper part bundling element and a lower part bundling element which are made of a ceramic material, and are at least partially formed by a film which glues the upper part bundling element and the lower part bundling element, wherein the upper part bundling element has a diameter that is three times a diameter of the lower part bundling element,
wherein the film is attached to an upper side of the at least one magnetic field bundling element, and the at least one wound electrical conductor is arranged on a lower side of the at least one magnetic field bundling element, wherein the upper side is facing away from the at least one magnetic field bundling element in a first direction and the lower side is facing away from the at least one magnetic field bundling element in a second direction, wherein the first direction is opposite to the second direction,
wherein the entire at least one magnetic field bundling element is surrounded by the film,
wherein the coil core has a toroid shape,
wherein the magnetic field bundling element has a toroid shape,
wherein the magnetic field bundling element surrounds the wound electrical conductor only on an upper side and an inner side,
wherein the coil core is at least partially made of a soft elastic material,
wherein the coil core is made of at least one sintered powder or pellets.

US Pat. No. 10,170,237

PLATE-SHAPED LEAKAGE STRUCTURE AS AN INSERT IN A MAGNETIC CORE

1. A plate-shaped leakage structure as an insert in a magnetic core having a magnetic field direction for an inductive component, the plate-shaped leakage structure having a length direction, a width direction and a thickness direction representing mutually perpendicular directions, wherein the length directions indicates a direction along which the dimension of the plate-shaped leakage structure is longer than dimension along the width and thickness directions, wherein the plate-shaped leakage structure comprises:a first leakage structure portion, a second leakage structure portion, and a third leakage structure portion arranged along the length direction such that the first to third leakage structure portions combine to form a main plane, the main plane being normal to the thickness direction, wherein each of the first to third leakage structure portions is formed of a first material which comprises a ferrite material;
a first spacer formed of a second material which, as opposed to the first material, has a lower magnetic permeability, wherein the first spacer passes through the plate-shaped leakage structure along the thickness direction and the width direction, thereby separating the first leakage structure portion from the second leakage structure portion along the length direction, and
a second spacer formed of the second material, wherein the second spacer passes through the plate-shaped leakage structure along the thickness direction and the width direction, thereby separating the second leakage structure portion from the third leakage structure portion along the length direction,
wherein each of the first and second spacers are sintered into the plate-shaped leakage structure and separate the leakage structure portions by a distance smaller than a thickness of the plate-shaped leakage structure measured along the thickness direction thereof, and
wherein said first, second, and third leakage structure portions each have a bearing surface formed on the main plane with each of the bearing surfaces covered by a magnetic core section and positioned within the magnetic core of the inductive component with the magnetic field direction being perpendicular to the bearing surfaces and the main plane of the plate-shaped leakage structure.

US Pat. No. 10,170,236

COIL UNIT

Toyota Jidosha Kabushiki ...

1. A coil unit comprising:a first case and a second case facing each other in a predetermined direction, the first case and the second case defining an accommodation space inside when joined with each other;
a ferrite plate, a coil and a shield member that are arranged in the accommodation space; and
a seal member attached to the second case for taking a wiring member outside from an inside of the accommodation space, the wiring member being electrically connected to the coil, wherein
the first case includes a first plate portion, a first circumferential wall portion provided so as to be upright from a periphery of the first plate portion, and a first joint face located at a distal end of the first circumferential wall portion in a direction in which the first circumferential wall portion is upright, and the first case is configured such that magnetic fluxes pass through the first case,
the second case includes a second plate portion arranged to face the first plate portion, a second circumferential wall portion provided so as to be upright from a periphery of the second plate portion, and a second joint face located at a distal end of the second circumferential wall portion in a direction in which the second circumferential wall portion is upright, and the second case is configured to block magnetic fluxes,
the first case and the second case define the accommodation space when the first joint face and the second joint face are joined with each other,
the ferrite plate is arranged in the accommodation space such that a thickness direction of the ferrite plate is parallel to the predetermined direction,
the coil is arranged between the first plate portion and the ferrite plate such that a winding axis of the coil is parallel to the predetermined direction,
the shield member is arranged between the second plate portion and the ferrite plate so as to support the ferrite plate,
at least part of a portion at which the first joint face and the second joint face are joined with each other is located closer to the second plate portion than a position of the ferrite plate in a direction parallel to the predetermined direction,
the second case further includes a protruding portion and a through-hole, the protruding portion protrudes outward from a position of the second circumferential wall portion when viewed in the direction parallel to the predetermined direction, the through-hole extends through the protruding portion and the second circumferential wall portion so as to communicate with the accommodation space, the wiring member and the seal member are arranged inside the through-hole,
an inner periphery of the second case, which defines the through-hole, includes a large-diameter portion and a small-diameter portion, the large-diameter portion is provided at an end opposite from a side on which the accommodation space is located and at a position that does not overlap with the second joint face when viewed in the direction parallel to the predetermined direction, the small-diameter portion connects the large-diameter portion with the accommodation space, the small-diameter portion is smaller in inside diameter than the large-diameter portion, and
the seal member is arranged inside the large-diameter portion.

US Pat. No. 10,170,235

REACTOR

AUTONETWORKS TECHNOLOGIES...

1. A reactor comprising:a coil formed by winding a wire about an axis; and
a magnetic core having a portion disposed inside the coil,
wherein the magnetic core includes a terminal-equipped outer core component, the terminal-equipped outer core component including:
a side main portion protruding from the coil and constituting a magnetic circuit;
a terminal fitting connected to an end portion of the wire;
a side resin-molded portion configured to integrally hold the side main portion and the terminal fitting, wherein:
the terminal-equipped outer core component includes a fixing portion that is formed of a resin of the side resin-molded portion and that holds the terminal fitting, the fixing portion being oriented on an external front face of the side of the side resin-molded portion, the external front face extending perpendicular to a direction parallel to the axis, and
the fixing portion includes a shaft portion that is inserted into at least one fixing hole provided in the terminal fitting and a head portion that extends continuous with the shaft portion in the direction parallel to the axis, and that has a portion larger than a minimum diameter of the fixing hole, such that the terminal fitting is attached to the external front face through the shaft portion.

US Pat. No. 10,170,234

COIL DEVICE CAPABLE OF PERFORMING A WIRE CONNECTION

TDK CORPORATION, Tokyo (...

1. A coil device comprising:a magnetic core having a winding core wound by a wire to form a coil;
a first flange and a second flange having a substantially planar shape and integrally formed at both ends in the winding axis direction of the winding core; and
a terminal electrode attached on an outer end surface of the first flange formed at an end in a winding axis direction of the winding core, wherein the terminal electrode comprises:
an attachment piece contacted with the outer end surface of the first flange;
a wire connection rising piece integrally risen from one end in a longitudinal direction of the attachment piece along a side surface in a first axis direction of the first flange; and
a connection piece formed integrally with an upper end side of the wire connection rising piece and having a welded ball connected to a lead part of the wire by laser welding, and wherein
a laser shielding member is arranged between the welded ball and the magnetic core,
the side surface in the first axis direction of the first flange includes:
a rising piece facing plane facing the wire connection rising piece in such a manner as to be contactable with the wire connection rising piece to position the connection piece; and
a terminal space concave part caved inside from the rising piece facing plane to form a space between the terminal space concave part and the wire connection rising piece,
the shielding member is formed integrally with the wire connection rising piece of the terminal electrode,
the shielding member is held in space between the welded ball and the terminal space concave part of the magnetic core,
the first flange has notches dented more largely than the second flange so that an outer shape size of the first flange is smaller than that of the second flange,
the rising piece facing plane and the terminal space concave part are formed on the notches, and
the wire connection rising piece is located inside the notches.

US Pat. No. 10,170,232

TOROID INDUCTOR WITH REDUCED ELECTROMAGNETIC FIELD LEAKAGE

QUALCOMM Incorporated, S...

1. A coupled toroid inductor comprising:a first toroid inductor and a second toroid inductor, wherein the first toroid inductor is separate from and co-planar with the second toroid inductor along a multi-layer dielectric substrate, the first and/or second toroid inductors comprising:
(i) a plurality of first turns configured in a first ring shape, the plurality of first turns comprising:
a plurality of first upper interconnects, wherein the plurality of first upper interconnects includes individual substantially rectangular trace segments on a first metal layer of the multi-layer dielectric substrate;
a plurality of first lower interconnects, wherein the plurality of first lower interconnects includes individual substantially rectangular trace segments on a second metal layer of the multi-layer dielectric substrate; and
a plurality of first vias coupled to the plurality of first upper interconnects and to the plurality of first lower interconnects; and
(ii) a plurality of second turns at least partially intertwined with the plurality of first turns, wherein the plurality of second turns is configured in a second ring shape, the plurality of second turns comprising:
a plurality of second upper interconnects, wherein the plurality of second upper interconnects includes individual substantially rectangular trace segments on the first metal layer of the multi-layer dielectric substrate;
a plurality of second lower interconnects, wherein the plurality of second lower interconnects includes individual substantially rectangular trace segments on the second metal layer of the multi-layer dielectric substrate; and
a plurality of second vias coupled to the plurality of second upper interconnects and to the plurality of second lower interconnects,
wherein the at least partial intertwining of at least some of the first turns and second turns form an enclosure for the multi-layer dielectric substrate configured to reduce electromagnetic field leakage from the toroid inductor.

US Pat. No. 10,170,231

CHOKE AND CHOKE CORE

1. A choke with two coils and a core in an interleaved circuit connected to a common signal source and having a first switch and a second switch, comprising:a core having lateral legs with each of the lateral legs having a first magnetic reluctance or resistance and comprising a first material with a first cross section and a middle leg having a second magnetic reluctance or resistance comprising a second material with a second cross section, said core forming two loops with the middle leg as a common section;
a first coil placed around a first one of the lateral legs, said first coil coupled to the common signal source and the first switch;
a second coil placed around a second one of the lateral legs, said second coil coupled to the common signal source and the second switch;
wherein the second cross section of the middle leg is less than twice the first cross section of the lateral legs;
wherein the first and second materials are different and the second material of the middle leg has a higher magnetic permeability than a magnetic permeability of the first material of the lateral legs;
wherein the first magnetic reluctance or resistance of each of the lateral legs is at least twenty times greater than the second magnetic reluctance or resistance of the middle leg; and
wherein the coupling factor of the first and second coils is less than five percent,
whereby the choke and the interleaved circuit is capable of being made compact with small losses and low weight.

US Pat. No. 10,170,229

CHIP ELECTRONIC COMPONENT AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A chip electronic component comprising:an insulating substrate;
a first coil part disposed on one surface of the insulating substrate;
a second coil part disposed on the other surface of the insulating substrate opposing the one surface of the insulating substrate;
a via connecting the first and second internal coil parts to each other while penetrating through the insulating substrate;
first and second via pads disposed on the one surface and the other surface of the insulating substrate, respectively, so as to cover the via; and
a first dummy pattern disposed in a region of the one surface of the insulating substrate adjacent to the first via pad, and a second dummy pattern disposed in a region of the other surface of the insulating substrate adjacent to the second via pad,
wherein the first and second dummy patterns are physically and electrically separated from each other,
portions of the first and second via pads facing the first and second dummy patterns, respectively, are formed to have a curved surface, and
the first and second dummy patterns are formed to have a curved shape, depending on a shape of the first and second via pads, respectively.

US Pat. No. 10,170,227

ELECTOMAGNETIC DRIVER

DENSO CORPORATION, Kariy...

1. An electromagnetic driver comprising:a stationary core;
a movable core located to face the stationary core with a variable gap relative to the stationary core, the movable core being configured to be reciprocable relative to the stationary core;
a spring configured to urge the movable core to be away from the stationary core; and
a coil configured to generate magnetic flux when energized,
wherein the stationary core comprises:
a main magnetic circuit through which a first component of the magnetic flux flows,
the main magnetic circuit being configured such that:
first pulling force generated based on the first component of the magnetic flux flowing through the main magnetic path pulls the movable core in a reciprocation direction of the movable core; and
the first pulling force increases with a reduction of a dimension of the gap; and
an auxiliary magnetic circuit through which a second component of the magnetic flux flows,
the auxiliary magnetic circuit being configured such that:
second pulling force generated based on the second component of the magnetic flux flowing through the auxiliary magnetic path pulls the movable core in the reciprocation direction of the movable core; and
the second pulling force with the dimension of the gap being within a first range is changed to be higher than the second pulling force with the dimension of the gap being within a second range, the second range being smaller than the first range.

US Pat. No. 10,170,226

SPOOL ARRANGEMENT

1. A spool arrangement comprising a spool member having a coil embedded in a spool housing made of plastic material and protection means comprising at least two parts together forming a receiving volume, said spool member being located in said receiving volume, wherein said parts form protective walls on all sides of said receiving volume, and wherein said coil is wound on a core, said core having an longitudinal axis, said axis intersecting two end faces of said spool housing wherein said protective walls rest against said end faces only and form a gap with remaining parts of said spool housing.

US Pat. No. 10,170,225

PERMANENT MAGNET AND ROTATING MACHINE INCLUDING THE SAME

TDK CORPORATION, Tokyo (...

1. A permanent magnet comprising a periodic structure in which concentrations of Fe and T change alternately,wherein T is at least one of Co or Ni, optionally with one or more additional transition metal elements,
the concentrations change with a period of 3.3 nm or less, and
a concentration difference of Fe in the concentration change is 5 at % or more.

US Pat. No. 10,170,224

LOW TEMPERATURE FABRICATION OF LATERAL THIN FILM VARISTOR

International Business Ma...

1. A lateral thin film varistor device, comprising:a substrate;
a dielectric layer on the substrate;
two electrodes on the dielectric layer and spaced apart from each other in a first, lateral direction; and
a continuous, varistor layer on the dielectric layer and located between, and in contact with, the two electrodes, and comprising regions of a first metal oxide layer, and regions of a second metal oxide layer, and wherein:
the regions of the first metal oxide layer alternate with the regions of the second metal oxide layer in the lateral direction between the two electrodes,
the regions of the second metal oxide layer project outside the regions of the first metal oxide layer in a second, transverse direction perpendicular to the lateral direction, and
two of the regions of the first metal oxide layer are located laterally outside the regions of the second metal oxide layer, in contact with the two electrodes.

US Pat. No. 10,170,223

CHIP RESISTOR AND CHIP RESISTOR ASSEMBLY

SAMSUNG ELECTRO-MECHANICS...

1. A chip resistor comprising:a base substrate having first and second surfaces opposing each other;
first and second resistor layers separated from each other and disposed on the first surface of the base substrate;
first and second terminals disposed respectively on end portions of the base substrate opposite each other in a longitudinal direction, and connected respectively to first sides of the first and second resistor layers; and
third and fourth terminals disposed between the first and second terminals, and respectively connected to second sides of the first and second resistor layers that respectively oppose the first sides of the first and second resistor layers,
wherein the third and the fourth terminals face each other in a width direction of the base substrate, the width direction being perpendicular to the longitudinal direction.

US Pat. No. 10,170,221

FENCE STANDARD

GALLAGHER GROUP LIMITED, ...

1. A fence standard, comprising:an elongate shaft; and
a wire support made of electrically non-conductive material, comprising:
an elongate support member including a first end and a second end, and a longitudinal axis between the first end and the second end; and
an open ended loop made of a length of material bending around to double onto or cross over itself and result in overlapping opposing sections having a gap therebetween to permit passage of a wire into the center of the loop in use, wherein one of the opposing sections includes an end of the loop, and the end of the loop lies within an outer periphery of the other opposing section of the loop,
wherein the length of material forming the open ended loop extends from the first end of the elongate support member in a first direction away from the longitudinal axis before bending around above the first end, and
wherein the elongate support member includes a guide surface facing away from the first direction, the guide surface leading outwardly from the longitudinal axis along a direction from the second end to the first end,
wherein the wire support is connected to the shaft by the elongate support member.

US Pat. No. 10,170,218

IGNITION SUPPRESSION CIRCUITING TECHNOLOGY

ISCT LLC, Madisonville, ...

1. A cable system comprising:a cable, said cable having a sheath with an axial pathway running a length of said cable between a first end of said cable and a second end of said cable;
said cable having one or a plurality of electrically conductive wires running through said axial pathway of said sheath for said length of said cable;
said cable having a fluid conduit engaged with or within said sheath and running said length of said cable, said fluid conduit having a sidewall surrounding an axial passage thereof;
wherein said length of said cable is engageable to communicate electricity through said conductive wires between said first end and said second end of said cable and to concurrently communicate a fire suppressant within said fluid conduit, between said first end of said cable and said second end of said cable;
said electrically conductive wires and said fluid conduit at one end of said cable, engageable with a junction box;
a suppressant chamber configured for attachment with said junction box;
said suppressant chamber having a connection for sealed engagement of said axial passage of said fluid conduit, with an internal cavity of said suppressant chamber;
said internal cavity forming a reservoir of a fire suppressant communicated through said axial passage of said fluid conduit from a fire suppressant supply;
said electrically conductive wires having an insulation coating circumferentially engaged thereon, said insulation having a first melting temperature; and
said suppressant chamber being formed of material having a second melting temperature, said first melting temperature exceeding said second melting temperature, whereby said suppressant chamber melts and causes an emission of said fire suppressant from within said internal cavity, only when a temperature of said conductive wires within said junction box or an interior of said junction box, exceeds said second melting temperature.

US Pat. No. 10,170,217

EDGE INSULATION STRUCTURE FOR ELECTRICAL CABLE

3M Innovative Properties ...

1. An edge insulated electrical cable comprising:an electrical cable having a conductive material disposed near a longitudinal edge and susceptible to making electrical contact at the edge, wherein the cable is folded along the length of the cable, the fold defining a first portion facing a second portion, the second portion comprising the longitudinal edge of the cable, and
a bonding material bonding the second portion to the first portion along the length of the cable.

US Pat. No. 10,170,216

EDGE INSULATION STRUCTURE FOR ELECTRICAL CABLE

3M Innovative Properties ...

1. A cable comprising:a plurality of substantially parallel conductors extending along a length and arranged along a width of the cable;
a dielectric unitary block disposed at a longitudinal edge, and extending along the length, of the cable, the unitary block spaced apart from the conductors;
first and second non-conductive polymeric layers disposed on opposite first and second sides of the conductors and the unitary block, the first and second non-conductive polymeric layers including cover portions and pinched portions arranged such that, in cross-section, the cover portions of the first and second non-conductive polymeric layers in combination substantially surround each conductor and at least a portion of the unitary block, and the pinched portions of the first and second non-conductive polymeric layers in combination form pinched portions of the cable at least on one side of the unitary block; and
an adhesive layer bonding the first non-conductive polymeric layer to the second non-conductive polymeric layer at least in the pinched portions of the cable.

US Pat. No. 10,170,214

ECO-FRIENDLY THERMOPLASTIC RESIN COMPOSITION HAVING EXCELLENT ELECTRO-PLATING PROPERTY

Korea Kumho Petrochemical...

1. A thermoplastic resin composition, comprising:10 to 35 wt % of a first graft copolymer resin in which 55 to 65 parts by weight of a diene-based rubber polymer and 35 to 45 parts by weight of a monomer mixture, in which an aromatic vinyl monomer and a vinyl cyanide monomer are mixed in a weight ratio of 60 to 80:20 to 40 respectively, are graft-polymerized;
1 to 12 wt % of a second graft copolymer resin in which 45 to 55 parts by weight of a diene-based rubber polymer and 45 to 55 parts by weight of a monomer mixture, in which an aromatic vinyl monomer and a vinyl cyanide monomer are mixed in a weight ratio of 60 to 80:20 to 40 respectively, are graft-polymerized;
10 to 30 wt % of a first copolymer resin in which an aromatic vinyl monomer and a vinyl cyanide monomer are copolymerized in a weight ratio of 60 to 80:20 to 40 respectively;
30 to 75 wt % of a polycarbonate resin; and
2 to 8 wt % of a conductive filler.

US Pat. No. 10,170,211

SYSTEM AND METHOD FOR COLLECTING 3HE GAS FROM HEAVY WATER NUCLEAR REACTORS

1. A method of collecting 3He from a nuclear reactor, the method comprising:a. providing heavy water at least part of which is exposed to a neutron flux of the reactor;
b. providing a cover gas in fluid communication with the heavy water;
c. operating the nuclear reactor whereby thermal neutron activation of deuterium in the heavy water produces tritium (3H) and at least some of the tritium produces 3He gas by ??decay and at least a portion of the 3He gas escapes from the heavy water and mixes with the cover gas;
d. extracting an outlet gas stream, the outlet gas stream comprising a mixture of the cover gas and the 3He gas; and
e. separating the 3He gas from the outlet gas stream using at least one of a thermal diffusion process, a fractional diffusion process, a heat flush process, a superleak process and a differential absorption process.

US Pat. No. 10,170,210

DEVICE SYSTEM FOR MILITARY AND/OR HUMANITARIAN OPERATIONS, IN PARTICULAR A MOBILE DECONTAMINATION SYSTEM

KAERCHER FUTURETECH GMBH,...

1. A mobile decontamination system for at least one of radioactive decontamination, disinfection or detoxification, the mobile decontamination system comprising:a plurality of power-operated units including at least one pump for recirculating, conveying or discharging liquids, a heater, and a process controller for controlling the at least one pump and the heater,
a water tank,
cleaning agents or decontaminants,
a load-bearing base plate having a defined placement surface, and
a retaining structure fastened on the defined placement surface and designed to hold the plurality of power-operated units, the water tank, and the cleaning agents or decontaminants on the load-bearing base plate during transport of the mobile decontamination system,
wherein the retaining structure is formed from a plurality of self-supporting, structurally identical, cuboid-shaped frames which are arranged next to each other or on top of each other and which are fastened to the load-bearing base plate,
wherein each frame of the plurality of self-supporting, structurally identical, cuboid-shaped frames, comprises:
eight corner pieces disposed at corners of each frame; and
twelve frame edge profile elements disposed along edges that extend between the corners of each frame, wherein each frame edge profile element includes a cross-section of material that spans between and contacts an adjacent and opposing pair of corner pieces, and wherein the eight corner pieces and the twelve frame edge profile elements together enclose a defined cuboid-shaped storage volume for each frame,
wherein the plurality of power-operated units are fixedly installed in respective ones of the defined storage volume per frame, and wherein the plurality of power-operated units are operable while fixedly installed.

US Pat. No. 10,170,209

FLOATING NUCLEAR POWER REACTOR WITH A SELF-COOLING CONTAINMENT STRUCTURE

1. A floating nuclear power reactor, comprising:a floating vessel having a bottom positioned beneath the water level of a body of water, sides extending upwardly from said bottom, and an upper end which is positioned above the water level of the body of water;
a nuclear power reactor supported on said vessel;
at least a portion of said nuclear power reactor being submerged in the body of water;
said nuclear power reactor having a lower end, an upstanding side wall, and an upper end;
a water passageway, having inner and outer ends, extending through said floating vessel and into said nuclear power reactor;
a normally closed hatch movably associated with said water passageway;
said hatch being movable between a normally closed position and an open position;
said hatch, when in said closed position, closing said water passageway;
said hatch, when in said open position, permitting water from the body of water to flow inwardly through said water passageway into said nuclear power reactor;
a latch associated with said hatch which is movable from a latched position to an unlatched position;
said latch, when in said latched position, maintaining said hatch in said closed position;
said latch, when in said unlatched position, permitting said hatch to move from said closed position to said open position;
and a condition responsive actuator positioned within said nuclear power reactor which causes said latch to move from said latched position to said unlatched position upon a condition within said nuclear power reactor reaching a predetermined level.

US Pat. No. 10,170,208

ELECTROMAGNETIC COIL BOBBIN USED IN REACTOR AS WELL AS INNER BOBBIN AND OUTTER SHELL

1. An electromagnetic coil bobbin used in reactor, comprising an inner bobbin and an outer shell which form a cylindrical structure, wherein an annular cavity for containing a coil winding is formed by said outer shell and said inner bobbin, and the inner bobbin is located in an inner hole of the outer shell;said inner bobbin and said outer shell each comprise a main body of which the material is metal and cut-off grooves provided on the main body, the cut-off grooves on the inner bobbin run through inner and outer walls as well as front and rear end faces of the inner bobbin, and the cut-off grooves on the outer shell run through inner and outer walls as well as front and rear end faces of the outer shell,
wherein, there are at least two cut-off grooves on both the inner bobbin and the outer shell, the cut-off grooves on the inner bobbin are uniformly distributed on the inner bobbin, the cut-off grooves on the outer shell are uniformly distributed on the outer shell, and said cut-off grooves are each provided with an insulating connection strip therein, and
wherein:
a clamping slot or clamping projection is provided on the portions of the outer shell on both sides of each cut-off groove on said outer shell, the length direction of said clamping slot or clamping projection is parallel to the axial direction of the outer shell, the clamping slot or clamping projection is originated from one end of the outer shell, and the insulating connection strips on said outer shell are insulating clamping strips connected to the clamping slot or clamping projection on the portions of the outer shell on both sides of the same cut-off groove on the outer shell, and/or
both ends of said inner bobbin are provided with annular outer edges, the axis of said outer edges and the axis of the main body are collinear, and the inner hole of the outer edge is connected to the end of the inner bobbin; the cut-off grooves on the inner bobbin extend to the end of the outer edge, the external diameter of said outer shell is not greater than the external diameter of the outer edge, the outer shell is clamped between two outer edges, and an insulating layer is provided between each outer edge and the end of corresponding outer shell.

US Pat. No. 10,170,202

MEMORY SYSTEM

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:a semiconductor storage device including a plurality of blocks; and
a controller configured to
(i) instruct the semiconductor storage device to perform a read operation on data written to a block of the semiconductor storage device to determine whether or not to designate the block as a partial bad block if, after instructing the semiconductor storage device to perform a write operation on the block to write the data, status information read from the semiconductor storage device indicates that the write operation failed, and
(ii) designate the block as a partial bad block if read data that is returned from the semiconductor storage device in response to the instruction to perform the read operation has errors that are correctable, and as a bad block if read data that is returned from the semiconductor storage device in response to the instruction to perform the read operation has errors that are not correctable,
wherein the controller is configured to manage a partial bad block differently from a bad block,
wherein the controller is configured to instruct the semiconductor storage device to increase a threshold number of errors for determining that the write operation failed prior to a subsequent write operation on the block designated as a partial bad block, and
wherein the controller, after the subsequent write operation on the block designated as a partial bad block, sends a command for decreasing the threshold number of errors to the semiconductor storage device.

US Pat. No. 10,170,201

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A data storage device comprising:a memory device including memory regions classified into a plurality of memory groups, each of the plurality of memory groups corresponding to a plurality of read bias voltage groups, each of the plurality of read bias voltage groups including read bias voltage sets, each of the read bias voltage sets including read bias voltages which are expected to be respectively positioned between threshold voltage distributions of memory cells of the memory regions; and
a controller configured to:
perform, for a target memory region a read retry operation based on a first read bias voltage group corresponding to a memory group in which the target memory region is included,
select at least one of remaining read bias voltage groups excluding the first read bias voltage group among the plurality of read bias voltage groups, according to a result of the read retry operation, and
perform an additional read retry operation for the target memory region based on the at least one of remaining read bias voltage groups.

US Pat. No. 10,170,200

MEMORY DEVICE AND METHOD FOR TESTING A MEMORY DEVICE

Infineon Technologies AG,...

1. A memory device, comprising:a plurality of data word memories; and
a test controller configured to:
read a data word stored in a data word memory of the plurality of data word memories,
check the read data word to detect an error of the memory device,
determine a complementary data word of the data word in response to a determination that no error of the memory device is detected in the check of the read data word,
store the complementary data word in the data word memory,
read the complementary data word from the data word memory, and
check the read complementary data word to detect an error of the memory device.

US Pat. No. 10,170,199

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

International Business Ma...

1. A system comprising:a multiple input signature register (MISR), wherein the MISR is logically coupled to digital outputs of a content addressable memory (CAM) (CAM match outputs), is logically coupled to digital inputs of a random access memory (RAM) (RAM inputs), and is logically coupled to digital outputs of an array built-in self-test (ABIST) controller circuit (ABIST outputs);
wherein the MISR comprises a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer (MUX) circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or (XOR) circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), wherein each of the outer XOR circuits is logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits,
wherein each of the L1 latch circuits comprises a first data input, a first scan input, and a first output, and
wherein each of the L2 latch circuits comprises a second data input, a second scan input, and a second output;
wherein the MISR is logically configured to receive the CAM match outputs on the first data inputs of the L1 latch circuits;
wherein the MISR is logically configured to address the RAM via the first outputs of the L1 latch circuits and the RAM inputs;
wherein the MISR is logically configured to receive the ABIST outputs via the MUX circuits and the inner XOR circuits on the first scan inputs of the L1 latch circuits;
wherein the MISR is logically configured to output compression data (L2 scan out data) via the second outputs of the L2 latch circuits; and
wherein the MISR is logically configured to provide feedback data via the outer XOR circuits;
wherein the CAM is logically coupled to a compare mask circuit, and
wherein the compare mask circuit is logically configured to direct the CAM to output one bit of the CAM match outputs at a time;
wherein the MISR is further logically configured, in response to receiving a digital control input signal, to address the RAM via the first outputs of the L1 latch circuits and the RAM inputs and via CAM match wordlines on the first outputs of the L1 latch circuits, wherein the CAM match wordlines correspond to the CAM match outputs;
wherein the MISR is further logically configured, in response to receiving a first type of digital signal from one of the ABIST outputs, to test even numbered CAM match outputs (even CAM match data) among the CAM match outputs against a first set of the ABIST outputs; and
wherein the MISR is further logically configured, in response to receiving a second type of digital signal from one of the ABIST outputs, to test odd numbered CAM match outputs (odd CAM match data) among the CAM match outputs against a second set of the ABIST outputs.

US Pat. No. 10,170,198

DATA STORAGE AND METHOD OF OPERATING THE SAME

Samsung Electronics Co., ...

1. A data storage comprising:at least one nonvolatile memory device; and
a controller operatively connected to the at least one nonvolatile memory device,
wherein the controller is configured to receive binary data from a host through a side-band interface,
wherein the controller includes a buffer configured to store the binary data,
wherein the controller is configured to execute the binary data according to a request from the host to execute a test operation,
wherein the data storage is an on-board SSD in which the at least one nonvolatile memory device and the controller are mounted on a board,
wherein the binary data is divided according to a property of the test operation to provide divided binary data and is received from the host, and
wherein a size of the divided binary data is equal to or smaller than a size of the buffer.

US Pat. No. 10,170,197

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:first to Nth non-volatile memory areas, each including a plurality of cells positioned at cross points between row lines and column lines;
a storage circuit including a plurality of unit latches suitable for storing data transferred from the first to Nth non-volatile memory areas, wherein the number of the plurality of unit latches corresponds to the number of the plurality of cells that are included in one of the first to Nth non-volatile memory areas; and
an operation control circuit suitable for controlling setup information of first to Nth operation modes to be programmed in the first to Nth non-volatile memory areas, respectively, during a rupture mode, and controlling a data transferred from the first non-volatile memory area to be written in the unit latches and controlling a data transferred from one of the second to Nth non-volatile memory areas to be over-written in the unit latches in response to an operation mode change request, during a boot-up mode.

US Pat. No. 10,170,196

APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN 3D NON-VOLATILE MEMORY OPERATIONS

Micron Technology, Inc., ...

6. A system comprising:a memory device; and
an additional device coupled to the memory device to cause the memory device to perform a memory operation, the memory device including:
a memory cell string including memory cells and a select transistor, the memory cell string including a body associated with the memory cells and the select transistor;
a control gate associated with the memory cell string;
a select gate associated with the select transistor;
a data line coupled to the body of memory cell string;
a source coupled to the body of memory cell string; and
a module configured to:
apply a first voltage having a positive value to the control gate in at least a portion of a first stage and a positive value in at least a portion of a second stage of an operation performed on a selected memory cell among the memory cells, wherein the module is configured to determine a value of information stored in the selected memory cell in the first stage of the operation;
apply a second voltage having a first value in at least a portion of the first stage and a second value in at least a portion of the second stage to the select gate; and
apply a third voltage having a positive value to at least one of the data line and the source in at least a portion of the second stage.

US Pat. No. 10,170,195

THRESHOLD VOLTAGE SHIFTING AT A LOWER BIT ERROR RATE BY INTELLIGENTLY PERFORMING DUMMY CONFIGURATION READS

International Business Ma...

1. A method of adapting read voltage thresholds of a physical page in a block of memory in a non-volatile memory, the method comprising:in response to selection of the block for adaptation of at least one read voltage threshold applicable to the physical page, the controller issuing a dummy read operation to the block to ensure the physical page is in a lower bit error rate (BER) state;
the controller waiting for a calibration read wait period following the dummy read operation; and
the controller thereafter performing a calibration read operation for the physical page and adapting at least one read voltage threshold for the physical page based on results of the calibration read operation.

US Pat. No. 10,170,194

ASYMMETRICAL MULTI-GATE STRING DRIVER FOR MEMORY DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a first group of conductive materials interleaved with a first group of dielectric materials;
a first pillar extending through the first group of conductive materials and the first group of dielectric materials;
memory cells located along the first pillar;
a conductive contact coupled to a conductive material of the first group of conductive materials; and
a second pillar extending through a second group of conductive materials and a second group of dielectric materials, the second pillar including a first portion, a second portion, and a third portion, and a fourth portion, the second and third portions located between the first and fourth portions, and the second portion located between the first and third portions, wherein
the first portion is coupled to a conductive region, and
the fourth portion is coupled to the conductive contact, and the second portion has a doping concentration less than a doping concentration of each of the first and fourth portions.

US Pat. No. 10,170,193

APPARATUS AND METHODS OF OPERATING MEMORY FOR NEGATIVE GATE TO BODY CONDITIONS

Micron Technology, Inc., ...

1. A method of operating a memory, comprising:applying a first voltage level to a first voltage node electrically connected to a first end of a string of series-connected memory cells;
applying a second voltage level to a second voltage node electrically connected to a second end of the string of series-connected memory cells;
applying a third voltage level to a control gate of a first memory cell of the string of series-connected memory cells while applying the first voltage level to the first voltage node and while applying the second voltage level to the second voltage node, wherein the third voltage level is less than the first voltage level and less than the second voltage level; and
applying a fourth voltage level to a control gate of a second memory cell of the string of series-connected memory cells while applying the third voltage level to the control gate of the first memory cell, wherein the fourth voltage level is less than the third voltage level, and wherein the first memory cell is closer to the first voltage node than the second memory cell.

US Pat. No. 10,170,192

NONVOLATILE MEMORY DEVICE

Samsung Electronics Co., ...

1. A nonvolatile memory device comprising:a memory cell array including a plurality of planes;
a plurality of page buffers arranged corresponding to each of the plurality of planes; and
a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers, wherein
each of the plurality of page buffers comprises a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal, and
the control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.

US Pat. No. 10,170,191

ELECTRONIC MEMORY DEVICE HAVING TWO PORTIONS THAT CAN BE DECOUPLED

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory array including a plurality of individually addressable logic sectors among at least one of first and second portions, wherein the first and second portions share columns;
a decoupling switch configured to decouple the first and second portions;
a common source select line to select an individually addressable logic sector among the: plurality of individually addressable logic sectors, the common source select line shared by a plurality of logic sections included in the individually addressable logic sector;
first and second drain selectors configured to select separate respective adjacent physical sectors of the selected individually addressable logic sector; and
at least two wordlines from the plurality of logic sections, respectively;
wherein the at least two wordlines are coupled to one another; and
wherein each physical sector of the separate physical sectors is individually addressable based on a selection of the common source select line, the corresponding drain selector among the first and second drain selectors, and a wordline.

US Pat. No. 10,170,190

MEMORY CONTROLLER HAVING RECLAIM CONTROLLER AND METHOD OF CONTROLLING OPERATION OF THE MEMORY CONTROLLER

Samsung Electronics Co., ...

1. A method of operating a memory controller for controlling a non-volatile memory device, the method comprising:transmitting, by the memory controller, a read command and a read address to the non-volatile memory device;
performing a read operation on memory cells connected to a selected word line in a selected string of a selected memory block of the non-volatile memory device, according to the read command and the read address;
counting a selected read count of the selected string in the selected memory block; and
performing a reclaim operation to move data, stored in the selected memory block, to another memory block based on the selected read count.

US Pat. No. 10,170,189

APPARATUS AND METHODS INCLUDING SOURCE GATES

Micron Technology, Inc., ...

1. A memory array, comprising:multiple strings of charge storage devices, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns, each of the multiple strings coupled to a common source through both a source gate device and a source select gate device;
wherein each source gate device includes a gate, and is configured to partially control conduction between the pillar of the respective string and the common source, wherein each source select gate device includes a gate and is also configured to partially control conduction between the pillar of the respective string and the common source,
wherein the gates of the source gate devices associated with each of the multiple strings of charge storage devices are coupled together to be controlled in common; and
wherein the gates of source select gate devices associated with a first group of strings of the multiple strings of charge storage devices are coupled together to be controlled in common, wherein the first group of strings is less than all of the multiple strings of charge storage devices.

US Pat. No. 10,170,188

3D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS

Micron Technology, Inc., ...

1. An apparatus comprising:a data line;
a first memory cell string including first memory cells located in different levels of the apparatus;
first access lines to access the first memory cells;
a first select gate coupled between the data line and the first memory cell string;
a first select line to control the first select gate;
a second memory cell string including second memory cells located in different levels of the apparatus;
second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines;
a second select gate coupled between the data line and the second memory cell string; and
a second select line to control the second select gate, wherein the first select line is in electrical contact with the second select line;
a third select gate coupled in series with the first select gate between the data line and the first memory cell string;
a third select line to control the third select gate;
a fourth select gate coupled in series with the second select gate between the data line and the second memory cell string; and
a fourth select line to control the fourth select gate, wherein the third select line is in electrical contact with the fourth select line;
a fifth select gate coupled in series with the first and third select gates between the data line and the first memory cell string;
a fifth select line to control the fifth select gate;
a sixth select gate coupled in series with the second and fourth select gates between the data line and the second memory cell string; and
a sixth select line to control the sixth select gate, wherein the fifth select line is in electrical contact with the sixth select line.

US Pat. No. 10,170,187

APPARATUSES AND METHODS USING NEGATIVE VOLTAGES IN PART OF MEMORY WRITE READ, AND ERASE OPERATIONS

Micron Technology, Inc., ...

1. A method comprising:storing information, during a first stage of a write operation, in a selected memory cell among memory cells of a memory cell string, the memory cells of the string formed over a substrate and located in different levels of a device in a direction perpendicular from substrate, the memory cell string including a body of the memory cells, the body of the memory cells located outside the substrate;
determining, during a second stage of the write operation, whether a value of the information stored in the selected memory cell reaches a target value;
applying a negative voltage to at least a portion of the body of the memory cell string during a time interval between the first and second stages of the write operation, wherein applying the negative voltage to at least the portion of the body of the memory cell string comprises applying the negative voltage through at least a portion of a source coupled to the body of the memory cell string; and
decoupling the negative voltage from the body of the memory string in the second stage of the write operation during determining of whether the value of the information stored in the selected memory cell reaches the target value.

US Pat. No. 10,170,186

HIGH-DENSITY EEPROM ARRAYS UTILIZING STACKED FIELD EFFECT TRANSISTORS

International Business Ma...

1. A semiconductor device, comprising:a substrate;
a first transistor located on top of the substrate and connected to a first terminal;
a second transistor located on top of the first transistor and connected in parallel to the first transistor and connected to a second terminal, where the first and second transistors share a common floating gate and a common output terminal; and
an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.

US Pat. No. 10,170,185

HYBRID MEMORY AND MTJ BASED MRAM BIT-CELL AND ARRAY

Intel Corporation, Santa...

1. An apparatus comprising:a capacitor having a first terminal and a second terminal;
a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to a bit line (BL), and a drain/source terminal coupled to the first terminal of the capacitor;
a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and
a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to a source line (SL), and a drain/source terminal coupled to the second terminal of the resistive memory element device, wherein the BL and SL are raised and lowered respectively or vice versa to write a state in the resistive memory element.

US Pat. No. 10,170,184

RESISTIVE MEMORY APPARATUS AND SETTING METHOD FOR RESISTIVE MEMORY CELL THEREOF

Winbond Electronics Corp....

1. A setting method for a resistive memory cell, comprising:performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished;
after the first verifying operation is finished, determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and
after the second verifying operation is finished, determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.

US Pat. No. 10,170,183

METHOD OF STORING AND RETRIEVING DATA FOR A RESISTIVE RANDOM ACCESS MEMORY (RRAM) ARRAY WITH MULTI-MEMORY CELLS PER BIT

Micron Technology, Inc., ...

1. A method of storing and retrieving data for a resistive random access memory array, comprising:subdividing the resistive random access memory array into a plurality of memory bits, with each memory bit comprising more than two memory cells;
programming an individual memory bit by substantially simultaneously changing resistive states of the more than two memory cells within the individual memory bit; and
reading the individual memory bit by determining summed current through all memory cells within the individual memory bit, wherein each memory cell is uniquely addressed by the combination of a wordline and a bitline, and wherein all the memory cells in a memory bit are addressed by paired wordlines and an individual bitline.

US Pat. No. 10,170,182

RESISTANCE CHANGE MEMORY DEVICE CONFIGURED FOR STATE EVALUATION BASED ON REFERENCE CELLS

IMEC vzw, Leuven (BE)

1. A memory device comprising:a plurality of memory cells arranged in an array, wherein each memory cell comprises a memory element configured to be switched between at least two resistance states; and
a plurality of word lines and a plurality of bit lines crossing each other, wherein each of the memory cells is formed at a crossing between one of the word lines and one of the bit lines,
wherein the memory cells are configured to be connected to a source line,
wherein each bit line has a bit line capacitance and is configured to store a charge associated with a state of a selected memory element,
wherein at least two memory cells electrically connected between one of the word lines and at least two different bit lines are configured as reference cells, wherein one of the reference cells is in a high resistance state and the other of the reference cells is in a low resistance state, and
wherein the at least two different bit lines electrically connected to the reference cells are interconnected by an equalizing switch configured to equalize charges associated with bit line capacitances of the at least two bit lines; and
a memory controller configured to select any of the word lines as a reference word line, such that different ones of the word lines can be used as reference word lines at different times.