US Pat. No. 10,714,963

CHARGING SYSTEM, CHARGING METHOD, AND DEVICE

GUANGDONG OPPO MOBILE TEL...

1. A charging system for a terminal, comprising a power adapter, the adapter comprising a first rectifier, the first rectifier rectifying an input alternating current to output a first voltage with a first pulsating waveform, wherein the power adapter further comprises:a switch unit, configured to modulate the first voltage according to a control signal;
a transformer, configured to output a second voltage with a second pulsating waveform according to the modulated first voltage;
a second rectifier, configured to rectify the second voltage to output a third voltage with a third pulsating waveform;
a first charging interface, coupled with the second rectifier;
a first current sampling circuit, configured to sample a current outputted by the second rectifier to obtain a current sampling value, wherein the first current sampling circuit comprises an operational amplifier with an adjustable amplification factor; and
a control unit, coupled to the first current sampling circuit and the switch unit respectively, and configured to output the control signal to the switch unit, to adjust the amplification factor of the operational amplifier according to a charging mode, and to adjust a duty ratio of the control signal according to the current sampling value, such that the third voltage meets a charging requirement;
the system further comprises a terminal, the terminal comprises a second charging interface and a battery, the second charging interface is coupled to the battery, wherein the second charging interface is configured to apply the third voltage to the battery when the second charging interface is coupled to the first charging interface.

US Pat. No. 10,714,960

UNIFORM WIRELESS CHARGING DEVICE

Intel Corporation, Santa...

1. A wireless charging device, comprising:a resonator having an inline capacitor and coil windings that include an inner winding having first and second inner coupling points and an outer winding having first and second outer coupling points, the resonator configured to generate a magnetic field; and
a controller that is configured to control a selective connection of:
in a first mode of operation, the first and second inner coupling points of the inner winding to a power source to power to the resonator, and the first outer coupling point to the second outer coupling point via the inline capacitor; and
in a second mode of operation, the first and second outer coupling points of the outer winding to the power source to power the resonator, and the first inner coupling point to the second inner coupling point via the inline capacitor.

US Pat. No. 10,714,957

CHARGE STATE CONTROL SYSTEM AND DEVICE

1. A charge state control hardware device for controlling current sent to a separate consumer device which contains a battery and control software, comprising:a microprocessor;
a transistor relay circuit which is controlled by the microprocessor to open or close a relay;
a first connector for connection between the consumer device and the transistor relay circuit;
a second connector for connection to a charger; and
a communication device for communication of a command from the control software on the consumer device to the microprocessor;
wherein the microprocessor receives the command and opens or closes the relay based on the command.

US Pat. No. 10,714,943

POWER MANAGEMENT METHOD, ELECTRONIC DEVICE, AND POWER ADAPTER

GUANGDONG OPPO MOBILE TEL...

1. A power management method, applied in an electronic device charged by a power adapter via a charging cable, and comprising:determining a temperature of a charging interface, including: detecting temperature values of a plurality of contact plates in the charging interface by a plurality of temperature measurement elements within a plurality of time periods, in which the temperature values have a one-to-one correspondence with the plurality of time periods, the plurality of contact plates have a one-to-one correspondence with the plurality of temperature measurement elements, and the plurality of contact plates are configured to transmit charging current; and averaging the temperature values to determine the temperature of the charging interface, wherein the charging interface comprises at least one of an interface of the power adapter for electric connection with the charging cable, an interface of the charging cable for electric connection with the power adapter, an interface of the charging cable for electric connection with the electronic device, and an interface of the electronic device for electric connection with the charging cable; and
managing power of the electronic device according to the temperature of the charging interface, including: when the temperature of the charging interface is greater than or equal to a first temperature threshold, sending an instruction to the power adapter via the charging cable for instructing the power adapter to reduce a current value of charging current or reduce a voltage value of the charging current, in which the first temperature threshold is between 15° C. and 45° C. at which a charging is allowed to be performed.

US Pat. No. 10,714,935

SUBSCRIBER-DRIVEN SYSTEM FOR MANAGING EVENTS IN AN ELECTRICAL GRID

INTERNATIONAL BUSINESS MA...

1. A method of managing electrical consumption, comprising:providing a computer infrastructure, being operable to:
send, by a smart meter of a subscriber, a Session Initiation Protocol (SIP) register message to a remote register in a network;
monitor, by the smart meter, electrical consumption and potential critical electrical events of at least one electrical device connected to the smart meter;
record, by the smart meter, the electrical consumption and a critical electrical event of the at least one electrical device at a client specified location, wherein the critical electrical event comprises at least one of a malfunction, a problem, and an electrical fault with the at least one electrical device;
send, by the smart meter, a SIP notify message comprising presence information of the critical electrical event of the at least one electrical device at the client specified location, to a remote presence server in the network, wherein the presence server is configured to store presence information of the smart meter and a subscriber device of the subscriber;
receive, by the smart meter, from a remote watcher device in communication with the presence server, at least one rule set by the subscriber wherein the at least one rule comprises at least one action to take in response to the critical electrical event; and
perform, by the smart meter, the at least one action to take in response to the critical electrical event to initiate changes to the at least one electrical device.

US Pat. No. 10,714,930

DIGITAL ELECTRICITY USING CARRIER WAVE CHANGE DETECTION

VoltServer, Inc., East G...

1. A power-distribution system for regulating transfer of energy from a source on a transmitter side of a transmission line to a load on a receiver side of the transmission line, where a transmission-line electrical fault can be detected, and the source electrically isolated from the transmission line before substantial human or equipment damage is incurred, comprising:a controller on the transmitter side of the power-distribution system responsive to one or more sensors that provide feedback to the controller, including providing at least a signal indicative of the voltage across the transmitter side of the transmission line;
a source-disconnect device operable by the controller, for electrically isolating the source from the transmission line; and
a signal-generator circuit configured to superimpose a carrier waveform with a source-output waveform on the transmission line, where the carrier waveform has a frequency that is substantially higher than the source-output waveform frequency, wherein
the controller includes a processor and computer-readable memory in communication with the processor, wherein the computer-readable memory stores software code to determine the normal impedance of the transmission line from measurement or by utilizing a preset held in the computer-readable memory, and for detecting a transmission-line fault, as indicated by a change in carrier waveform reflections or energy content of the carrier waveform because of a change in the normal impedance of the transmission line, and wherein the computer-readable memory further stores software code that generates a command to cause the controller to open the source-disconnect device upon detection of the fault on the transmission line.

US Pat. No. 10,714,922

CABLE GLAND COMPRESSION LIMITER

EATON INTELLIGENT POWER L...

1. A cable gland assembly comprising:a gland nut defining a longitudinal axis, the gland nut comprising an interior wall defining a gland nut opening, wherein the interior wall comprises a stop having a step;
a bushing disposed within the gland nut opening proximate the stop, wherein the bushing defines a bushing opening configured to receive a cable therein;
a sleeve moveably disposed at least partially within the gland nut opening adjacent the bushing, wherein the sleeve comprises a collar; and
a body defining a body opening configured to receive at least a portion of the cable therein, the body configured to couple to the gland nut, wherein upon tightening of the gland nut to the body, the gland nut moves along the longitudinal axis compressing the bushing between the gland nut and the sleeve and around the cable, and wherein when the collar of the sleeve engages with the step of the stop, further compression of the bushing is restricted.

US Pat. No. 10,714,914

STRIPPING APPARATUS AND STRIPPING STATION

HONDA MOTOR CO., LTD., T...

1. A stripping apparatus configured to strip an insulation coating from a conducting wire material cross-section of which orthogonal to a longitudinal direction has a rectangular shape, the stripping apparatus comprising:an upper mold provided with a stripping blade configured to strip the insulation coating;
a lower mold configured to support the conducting wire material from a lower side thereof;
a pressing member configured to prevent displacement of the conducting wire material; and
a rotation mechanism configured to rotate the conducting wire material around a rotational axis that is parallel to an axial center of the conducting wire material,
wherein the stripping blade has a substantially rectangular parallelepiped shape, and at least a pair of two opposing faces of the stripping blade have a stripping function to strip the insulation coating,
wherein the lower mold is configured to support two of the conducting wire materials and the upper mold is configured to position the stripping blade between the two conducting wire materials, and
wherein with the stripping blade positioned between the two conducting wire materials, the two opposing faces having the stripping function are configured to simultaneously strip insulation coatings of the two conducting wire materials that are disposed on the lower mold to hold the stripping blade therebetween.

US Pat. No. 10,714,891

PROJECTOR, ELECTRONIC DEVICE HAVING PROJECTOR AND ASSOCIATED MANUFACTURING METHOD

HIMAX TECHNOLOGIES LIMITE...

11. An electronic device, comprising:a projector, comprising:
a substrate;
a laser module, wherein the laser module is positioned on the substrate, and a laser diode of the laser module is not packaged within a can; and
a lens module, for receiving a laser beam from the laser diode of the laser module to generate a projected image of the projector to a region of a surrounding environment; and
a camera module, for capturing the region of the surrounding environment to generate image data; and
a processor, for analyzing the image data to obtain depth information of the image data;
wherein the laser module comprises a submount having the laser diode mounted thereon, and the submount is adhered to the substrate;
wherein the laser diode is under a center of the lens module, but the submount is not under the center of the lens module; and the laser diode is an edge emitting laser diode, and the laser diode is bonded on a side plane of the submount so that the laser diode directly generates the laser beam to the center of the lens module.

US Pat. No. 10,714,888

PULSED ELECTROMAGNETIC-WAVE GENERATOR AND MEASURING APPARATUS

Ricoh Company, Ltd., Tok...

1. A pulsed electromagnetic-wave generator comprising:an excitation light source;
a laser resonator which excitation light from the excitation light source enters;
a pulse generating unit configured to generate a pulsed light group including at least two or more pulses with different frequencies (?) and different oscillation timings (t) in one excitation process of the excitation light source, an oscillation frequency difference (??) between the pulses in the pulsed light group being an integral multiple of a Free Spectral Range (FSR) of the laser resonator; and
a wavelength converting unit which the pulsed light group enters, and that is configured to generate a pulsed electromagnetic wave in which a wavelength of each pulse in the pulsed light group is converted.

US Pat. No. 10,714,887

COMPACT LASER CAVITY AND METHODS OF MANUFACTURE

Arete Associates, Northr...

1. A method comprising:introducing light onto a resonant optical path of a bulk component non-planar ring resonator, wherein the non-planar ring resonator consists of an even number of reflections on the resonant optical path, the resonator including a bulk component reflector having a first optical power and a gain element;
wherein the resonator has a primary resonator plane of the resonant optical path, the resonator has at least one reflection outside of the primary resonant plane, and the resonator further includes a configuration for polarization output coupling;
activating the gain element to an operational point;
while the gain element is at the operational point, observing an indication of resonator instability from the introduced light;
based on the observing the indication of resonator instability, adjusting a round trip magnification along the optical path of the resonator to greater than 0.9 via a technique selected from the list consisting of:
modifying a heat flux through at least one surface of the gain element;
modifying the first optical power of the bulk component reflector to a second optical power.

US Pat. No. 10,714,868

WATERPROOF CONNECTOR FOR A BOARD

AutoNetwoeks Technologies...

1. A waterproof connector for a board, the waterproof connector to be connected to a female connector formed with a terminal accommodating portion accommodating a female terminal fitting and an outer tube spaced from and surrounding the terminal accommodating portion to define an insertion space therebetween, comprising:a male connector housing formed with a rear wall, a forwardly open tubular inner receptacle projecting forward from the rear wall, the inner receptacle fit in a sealed state into the insertion space between the terminal accommodating portion and the outer tube of the female terminal fitting, and a forwardly open outer receptacle projecting from the rear wall and spaced outward from the inner receptacle to define a clearance between the outer receptacle and the inner receptacle around an entire periphery thereof, the outer tube being configured to fit between the inner receptacle and the outer receptacle, the outer receptacle being mountable on a printed board; and
a male terminal fitting having one end provided in the inner receptacle and the other end connected to a circuit formed on the printed board.

US Pat. No. 10,714,859

RECEPTACLE ELECTRICAL CONNECTOR

Advanced Connectek Inc., ...

1. A receptacle electrical connector, comprising:a plurality of first terminals;
a plurality of second terminals;
a main insulator, having a plurality of first terminal grooves and a plurality of second terminal grooves, wherein each of the first terminals assembled and accommodated in the corresponding first terminal groove is fitted with the corresponding first terminal groove and in face-to-face contact, each of the second terminals assembled and accommodated in the corresponding second terminal groove is fitted with the corresponding second terminal groove and in face-to-face contact, wherein a first convex end of each of the first terminals is tapered, and a first concave end of each of the first terminal grooves is tapered so as to accommodate the corresponding first convex end of the first terminal, and wherein a second convex end of each of the second terminals is tapered, and a second concave end of each of the second terminal grooves is tapered so as to accommodate the second convex end of the corresponding second terminal;
a secondary insulator, engaged with the main insulator, so as to limit each of the first terminals in the corresponding first terminal groove and limit each of the second terminals in the corresponding second terminal groove;
a shielding plate, disposed between the first terminals and the second terminals; and
a shielding shell, surrounding the main insulator.

US Pat. No. 10,714,831

DUAL MODE COMMUNICATIONS DEVICE WITH REMOTE RADIO HEAD AND METHODS FOR USE THEREWITH

1. A communication device, comprising:a dual-band antenna array configured to transmit first radio frequency (RF) signals to a remote device in an RF band and to transmit first millimeter wave (MMW) signals to the remote device in a MMW frequency band, wherein the MMW frequency band is above the RF band;
a base transceiver station configured to generate a consolidated steering matrix in accordance with the transmission of the first RF signals to the remote device in the RF band; and
a remote radio head (RRH) configured to convert the consolidated steering matrix to a converted steering matrix that facilitates the transmission of the first MMW signals to the remote device in the MMW frequency band, and further configured to generate the first MMW signals in accordance with the converted steering matrix;
wherein the RRH is further configured to receive second RF signals, via the dual-band antenna array, from the remote device in the RF band and to recover a feedback matrix from the second RF signals; and
wherein the base transceiver station generates the consolidated steering matrix based on the feedback matrix.

US Pat. No. 10,714,828

MICROWAVE ANALOG CANCELLATION FOR IN-APERTURE SIMULTANEOUS TRANSMIT AND RECEIVE

RAYTHEON COMPANY, Waltha...

1. A transmit-receive phased array system for simultaneously transmitting and receiving, comprising:a transmit input for receiving a signal to be transmitted;
a transmit output, operatively coupled to the transmit input, for producing a signal for an antenna element;
a receive input, for receiving a signal from the antenna element;
a receive output, for producing an analog corrected receive signal, the receive output operatively coupled to the receive input through a receive signal path;
an adjustable filter having:
an input operatively coupled to the transmit input, and
an output operatively coupled to the receive signal path;
a digitizer operatively coupled to, and configured to digitize signals from:
the receive output,
the input of the filter,
the output of the filter, and
the receive signal path,
to form corresponding digitized signals; and
a processing circuit, configured to:
control the adjustable filter so as to partially cancel parasitic leakage from the transmit input to the receive output,
wherein:
the adjustable filter is an analog finite impulse response filter, and
the analog finite impulse response filter is implemented as a tapped delay line,
wherein the tapped delay line comprises:
a plurality of power dividers, each having:
an input;
a first output; and
a second output;
a plurality of delay elements, each connected to a respective power divider of the plurality of power dividers; and
a plurality of multipliers for respective tap weights, each connected to a respective power divider of the plurality of power dividers,
a second delay element of the plurality of delay elements providing a delay twice as great as a delay provided by a first delay element of the plurality of delay elements, and
the second delay element providing a delay twice as great as a delay provided by a third delay element of the plurality of delay elements.

US Pat. No. 10,714,827

SPHERICAL DIELECTRIC LENS SIDE-LOBE SUPPRESSION IMPLEMENTED THROUGH REDUCING SPHERICAL ABERRATION

The Boeing Company, Chic...

1. A radio frequency (RF) antenna configured to reduce RF side-lobes caused by spherical aberration, such that the RF antenna comprises:an RF source configured to transmit RF energy in an optical path defined between the RF source and an exit point from the RF antenna;
a plug in the optical path after the RF source, such that the plug comprises a monolithic and optically active, with respect to RF energy, material, that comprises three sections of different shapes; and
a spherical lens in the optical path after the plug.

US Pat. No. 10,714,817

ANTENNA DEVICE FOR A RADAR DETECTOR HAVING AT LEAST TWO RADIATION DIRECTIONS, AND MOTOR VEHICLE HAVING AT LEAST ONE RADAR DETECTOR

Audi AG, Ingolstadt (DE)...

1. An antenna device for a radar detector, comprising:a circuit board having an electrically insulating substrate having a first side and a second side opposite the first side, wherein a respective electrically conductive layer is positioned on each of the first and second sides of the electrically insulating substrate, and wherein the electrically conductive layer positioned on the first side of the electrically insulating substrate forms at least one main antenna and at least one feeder cable electrically coupled to the at least one main antenna, the at least one main antenna being a patch antenna; and
at least one antenna structure integrated with the electrically insulating substrate, wherein the at least one antenna structure integrated with the electrically insulating substrate comprises a plurality of cutouts which are formed in the electrically insulating substrate and arranged in a waveguide, wherein an electrically conductive material is arranged at least partially in each cutout, and wherein the feeder cable formed by the electrically conductive layer positioned on the first side of the electrically insulating substrate is further electrically coupled to the electrically conductive material of at least one cutout of the plurality of cutouts, and is configured for simultaneously feeding an electromagnetic wave into the at least one main antenna and the at least one antenna structure integrated with the electrically insulating substrate.

US Pat. No. 10,714,813

ELECTRONIC DEVICE INCLUDING COVER HAVING ANTENNA MODULE COUPLED THERETO

Samsung Electronics Co., ...

1. An electronic device having a space formed between a front face and a rear face thereof, the electronic device comprising:a first cover disposed on the front face;
a second cover disposed on the rear face;
a frame surrounding a periphery of the first cover and a periphery of the second cover;
at least one antenna module coupled to a first face of the second cover; and
a printed circuit board disposed in the space, and having a front face coupled to a face of the at least one antenna module and electrically connected to the at least one antenna module.

US Pat. No. 10,714,809

ANTENNA FOR VEHICLE

AGC INC., Tokyo (JP)

1. An antenna for a vehicle configured to be attached to an internal side of a window glass for a vehicle, for receiving electric waves from a vehicle front side, the antenna comprising:a retention unit comprising a bonding part configured to bond the antenna to a surface of the internal side of the window glass, the bonding part defining a plane parallel to the surface of the internal side of the window glass when attached to the internal side of the window glass;
a first radiator having a shape of a plate, at least a part of the first radiator being arranged separated from the plane, wherein the first radiator includes a plate having a three-layers structure including:
a dielectric substrate having a shape of a plate,
a feeding element arranged on one main surface of the dielectric substrate, and
a radiating element arranged on another main surface of the dielectric substrate; and
a second radiator arranged separated from the first radiator, and arranged so as to sandwich at least a part of the first radiator between the second radiator and the plane,
wherein the retention unit retains the first radiator and the second radiator, and
an angle formed by the plane and a surface of the first radiator on a side facing the plane is an acute angle,
wherein in the first radiator, the feeding element is arranged on a second radiator side of the dielectric substrate,
wherein the radiating element is arranged on a window glass side of the dielectric substrate,
wherein the feeding element is a conductive film forming a micro strip line,
wherein the radiating element is a conductive film from which a slot extending in a first direction is cut out,
wherein positions of the micro strip line and the slot are determined so that when the micro strip line is projected onto the conductive film from which the slot is cut out, a part of the micro strip line overlaps with a part of the slot,
wherein the antenna for the vehicle is attached to the window glass for the vehicle so that the first direction, in which the slot extends, is a horizontal direction, and
wherein the second radiator is arranged so as to overlap with the slot in the horizontal direction.

US Pat. No. 10,714,805

HIGHER SIGNAL ISOLATION SOLUTIONS FOR PRINTED CIRCUIT BOARD MOUNTED ANTENNA AND WAVEGUIDE INTERFACE

Milmosa Networks, Inc., ...

1. A waveguide mounted onto a dielectric substrate so as to enclose around a periphery of an antenna and contain radiation produced by the antenna along a path that is coaxial with a centerline of the waveguide, the waveguide comprising:a first portion comprising a first cross sectional area that is substantially polygonal that transitions to a second cross sectional area that is substantially conical, wherein a shape of the radiation produced by the antenna is altered by the first portion as the radiation propagates through the first portion;
a second portion comprising an elongated tubular member coupled with the first portion; and
a dielectric block disposed within the waveguide, the dielectric block comprising a square section and a conical section.

US Pat. No. 10,714,799

FUEL-CELL VEHICLE

TOYOTA JIDOSHA KABUSHIKI ...

1. A fuel-cell vehicle comprising:a fuel cell;
a secondary battery;
a radiator;
a circulation flow passage configured to cause a coolant to circulate between the fuel cell and the radiator;
a bypass flow passage passing through the secondary battery, one end of the bypass flow passage being connected to the circulation flow passage on an upstream side of the radiator and the other end of the bypass flow passage being connected to the circulation flow passage on a downstream side of the radiator;
a switching valve configured to switch a direction in which the coolant flows between a radiator side and a bypass flow passage side, the switching valve being provided at a junction between the circulation flow passage and the bypass flow passage on an upstream side of the radiator;
a first temperature sensor configured to measure a coolant temperature, the coolant temperature being a temperature of a coolant passed through the fuel cell;
a second temperature sensor configured to measure a secondary battery temperature, the secondary battery temperature being the temperature of the secondary battery; and
a controller configured to switch the switching valve to the bypass flow passage side when the coolant temperature is lower than a predetermined temperature threshold value and the coolant temperature is higher than the secondary battery temperature, and
wherein when the coolant temperature is not lower than the predetermined temperature threshold value and the coolant temperature is not higher than the secondary battery temperature, the controller being configured to switch the switching valve to the radiator side.

US Pat. No. 10,714,781

MOVING BODY

Toyota Jidosha Kabushiki ...

1. A moving body comprising:a compressor that compresses and discharges an oxidant gas supplied to a fuel cell stack;
intercooler that cools the oxidant gas discharged from the compressor; and
a fuel cell stack supplied with the oxidant gas cooled in the intercooler,
wherein the moving body includes a stack frame, a compressor bracket, and an intercooler bracket, the fuel cell stack is mounted to the stack frame, the compressor bracket is secured to the stack frame, the compressor is mounted to the compressor bracket, the intercooler bracket is secured to the stack frame, and the intercooler is mounted to the intercooler bracket,
wherein the intercooler bracket includes a pair of arms extending from the stack frame,
wherein the arms each have a distal end side where the intercooler is mounted to each of the arms,
wherein the arms each have a base end side where the intercooler bracket is secured to the stack frame, and a connecting portion that connects the pair of arms is integrally formed with the pair of arms.

US Pat. No. 10,714,757

CURRENT COLLECTOR, ELECTRODE PLATE INCLUDING THE SAME AND BATTERY

CONTEMPORARY AMPEREX TECH...

1. A current collector, comprisingan insulation layer;
at least one conductive layer located above at least one surface of the insulation layer, wherein the insulation layer is used to support the at least one conductive layer, the at least one conductive layer is used to support an electrode active material layer, and the at least one conductive layer each has a thickness of D2, wherein 300 nmD22 ?m; and
a first protective layer provided on a surface of each of the at least one conductive layer facing towards the insulation layer, wherein the first protective layer is made of a material selected from a group consisting of metal and metal oxide, or combinations thereof, the metal is at least one of nickel, chromium, nickel-based alloy, or copper-based alloy, and the metal oxide is at least one of aluminum oxide, cobalt oxide, chromium oxide, or nickel oxide; and
a second protective layer provided on a surface of the at least one conductive layer facing away from the insulation layer, wherein the second protective layer is made of a metallic material, which is selected from a group consisting of metal and metal oxide, or combinations thereof, the metal is at least one of nickel, chromium, nickel-based alloy, copper-based alloy, or combinations thereof, and the metal oxide is aluminum oxide or nickel oxide,
wherein the first protective layer has a thickness of D3, the second protective layer has a thickness of D3?, the thickness D3? of the second protective layer is larger than the thickness D3 of the first protective layer; and ½ D3?D3? D3?.

US Pat. No. 10,714,749

HIGH RATE LITHIUM COBALT OXIDE POSITIVE ELECTRODE MATERIAL AND MANUFACTURING METHOD THEREOF

HUNAN SHANSHAN ENERGY TEC...

1. A high-rate lithium cobaltate cathode material for a liquid state lithium ion battery, the high-rate lithium cobaltate cathode material comprising lithium cobaltate with or without a doping element M and a fast ionic conductor Li?M??O?, wherein:an element M? in Li?M??O? is one or more of Ti, Zr, Y, V, Nb, Mo, Sn, In, La, or W, 1???4, 1???5, and 2???12,
the lithium cobaltate with or without the doping element M is represented by Li1+yCo1?xMxO2, the doping element M is one or more of Mg, Al, Si, Sc, Ni, Mn, Ga, or Ge, 0?x?0.1, and ?0.01?y?0.01,
the high-rate lithium cobaltate cathode material is represented by a chemical formula of Li1+yCo1?xMxO2•zLi?M??O?, and 0.005?z?0.01,
the high-rate lithium cobaltate cathode material comprises a multi-channel network formed by the fast ionic conductor Li?M??O?,
the lithium cobaltate with or without the doping element M, as primary particles, is melted integrally with the fast ionic conductor Li?M??O? so as to form secondary particles, and the lithium cobaltate with or without the doping element M is embedded in the multi-channel network formed by the fast ionic conductor Li?M??O?.

US Pat. No. 10,714,690

AUTO-POLYMERIZATION ELECTRIC STORAGE MATERIAL BASED ON DOPAMINE, PREPARATION METHOD THEREOF AND APPLICATION TO ELECTRIC STORAGE DEVICE THEREOF

SOOCHOW UNIVERSITY, Suzh...

1. A preparation method of a self-polymerization electric storage material, comprising the following steps:mixing a dopamine hydrochloride solution having a pH of 8 to 9 with copper sulfate pentahydrate and hydrogen peroxide to obtain a mixed solution;
then forming a film with the mixed solution and annealing, to obtain the self-polymerization electric storage material.

US Pat. No. 10,714,673

TRANSDUCERS WITH IMPROVED IMPEDANCE MATCHING

Google LLC, Mountain Vie...

1. A device comprising:a touch screen; and
a transducer coupled to the touch screen, the transducer comprising:
a piezoelectric beam, supporting on at least one major surface a polymer of Shore A hardness less than 30;
a mechanical ground; and
at least two supports coupling the mechanical ground and the piezoelectric beam at opposite lateral ends of the beam in an arrangement that permits pivotal movement of the beam about the supports and reduces translational movement about the supports;
wherein each support comprises an elastomer having a Shore A hardness more than 40 and a Shore D hardness less than 100; and
wherein the beam and the touch screen are coupled at one of the at least one major surface.

US Pat. No. 10,714,641

MULTILAYER TRANSPARENT POLYESTER FILM, METHOD FOR MANUFACTURING SAID FILM AND USE OF SAID FILM IN PARTICULAR IN THE BACKSHEETS OF PHOTOVOLTAIC PANELS

TORAY FILMS EUROPE, Sain...

1. Transparent multilayered film, biaxially stretched, comprising at least 2 layers of polyester including a core layer and at least one outer layer, wherein:i) at least the core layer contains at least a transparent biaxially oriented polyester PE1 that is a polyester PE?:
comprising an alkali metal phosphate in a concentration of 1.3 mole/ton to 3.0 mole/ton, and phosphoric acid in a concentration of 0.4 to 1.5 times (per mole) the concentration of the alkali metal phosphate, and
in which an increase of COOH in PE1 between before and after a wet-heating treatment performed at 155° C. for 4 hours under saturated steam is 90 eq./ton or less,
ii) the at least one outer layer comprises at least a biaxially oriented polyester PE2, and particles formed during formation of PE2 by reaction between at least one metallic compound and at least a monomer or oligomer unit of a precursor PE2? of PE2, wherein the metallic compound that is able to react with the at least one monomer or oligomer unit of the precursor PE2?, in order to form the particles, is selected from a group consisting of metallic salts of carboxylic acids, organophosphates derived from phosphoric acid, and blends thereof,
the particles have a d50 in ?m of from 1.5 to 3, and
the PE2 is obtained by solid state post-condensation from the precursor PET?;
iii) at least one of the at least one outer layers comprises at least the PE2 and at least the PE1; and
iv) at least one of the core layer and the at least one outer layer(s) includes a photo stabilizer.

US Pat. No. 10,714,624

THIN-FILM TRANSISTOR FABRICATION METHOD FOR REDUCING SIZE OF THIN-FILM TRANSISTOR AND PIXEL AREA

WUHAN CHINA STAR OPTOELEC...

1. A thin-film transistor fabrication method, comprising the following steps:Step S1: providing a glass base plate and forming a flexible backing on the glass base plate;
Step S2: forming a moisture/oxygen barrier layer that is set on and covers the flexible backing;
Step S3: forming a buffer layer that is set on and covers the moisture/oxygen barrier layer;
Step S4: forming a source electrode that is stacked on the buffer layer;
Step S5: forming a separation layer that is stacked on the source electrode and exposes at least one side portion of the source electrode;
Step S6: forming a drain electrode that is set on and covers the separation layer;
Step S7: forming an oxide semiconductor channel layer, a gate insulation layer, and a gate electrode;
wherein the oxide semiconductor channel layer is arranged on one side of the organic separation layer and the drain electrode and sequentially contacts a portion of an upper surface of the drain electrode, a side surface of the drain electrode and the organic separation layer, and a portion of an upper surface of the source electrode; the gate insulation layer is arranged on the oxide semiconductor channel layer and the gate electrode is arranged on the gate insulation layer;wherein:Step S2 comprises a process that comprises first growing a hexagonal boron nitride film on a copper foil and transferring the hexagonal boron nitride film so grown to the flexible backing, wherein the process is repeated multiple times to form the moisture/oxygen barrier layer;
Step S4 comprises a process that comprises first growing a single-layered graphene film on a copper foil and transferring the single-layered graphene film to the buffer layer, wherein the process is repeated twice to form a double-layered graphene film, and subjecting the double-layered graphene film to patterning to form the source electrode; and
Step S6 comprises a process that comprises first growing a single-layered graphene film on a copper foil and transferring the single-layered graphene film to the separation layer, wherein the process is repeated twice to form a double-layered graphene film, and subjecting the double-layered graphene film to patterning to form the drain electrode.

US Pat. No. 10,714,609

SEMICONDUCTOR DEVICE WITH STRIPE-SHAPED TRENCH GATE STRUCTURES, TRANSISTOR MESAS AND DIODE MESAS

Infineon Technologies AG,...

1. A semiconductor device, comprising:a plurality of gate trenches formed in a semiconductor body, each of the gate trenches in the plurality vertically extending from a first surface of the semiconductor body and extending lengthwise parallel to one another;
transistor cells and diode regions formed in a mesa of the semiconductor body between neighboring ones of the gate trenches;
a drift region in the semiconductor body beneath the gate trenches;
wherein each transistor cell comprises a source zone and a body region,
wherein each diode region comprises a contact portion and a shielding portion,
wherein for each of the transistor cells, the source zone forms a first p-n junction with the body region, and the body region forms a second p-n junction with the drift region,
wherein for each of the diode regions, the contact portion extends to the first surface, and the shielding portion forms a third p-n junction with the drift region, the contact portion has a higher mean net dopant concentration than the shielding portion, and the shielding portion extends under bottoms of the neighboring ones of the gate trenches,
wherein for each of the diode regions, the contact portion continuously extends from the first surface to an interface with the shielding portion, and the shielding portion continuously extends from the interface to the third p-n junction, and
wherein for each of the diode regions, the interface is spaced further apart from the first surface than the second p-n junction of an immediately adjacent transistor cell.

US Pat. No. 10,714,607

HIGH ELECTRON MOBILITY TRANSISTOR

UNITED MICROELECTRONICS C...

1. A high electron mobility transistor (HEMT), comprising:a buffer layer on a substrate;
a carrier transit layer on the buffer layer;
a carrier supply layer on the carrier transit layer, wherein the carrier supply layer comprises a concentration gradient of aluminum (Al) and a concentration of Al decreases toward a boundary between the carrier transit layer and the carrier supply layer;
a gate electrode on the carrier supply layer; and
a source electrode and a drain electrode adjacent to two sides of the gate electrode.

US Pat. No. 10,714,604

QUANTUM DOT DEVICES WITH MULTIPLE DIELECTRICS AROUND FINS

Intel Corporation, Santa...

1. A quantum dot device, comprising:a base;
a fin extending away from the base, wherein the fin includes a quantum well layer;
a first dielectric material around a bottom portion of the fin;
a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material; and
a gate above the fin, wherein the gate is at least partially above the second dielectric material.

US Pat. No. 10,714,598

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming fin structures over a substrate;
forming a dummy gate structure over the fin structures;
forming sidewall spacers on opposing sides of the dummy gate structure;
removing the dummy gate structure, thereby exposing channel regions of the fin structures; and
forming a gate dielectric layer over the exposed channel regions of the fin structures:
forming a conductive layer over the gate dielectric layer;
forming a cap later over the conductive layer;
performing an ion implantation operation on the channel regions of the fin structures;
after the ion implantation operation, forming a gate electrode,
wherein the ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the channel regions of the fin structures.

US Pat. No. 10,714,593

FABRICATION OF STRAINED VERTICAL P-TYPE FIELD EFFECT TRANSISTORS BY BOTTOM CONDENSATION

INTERNATIONAL BUSINESS MA...

1. A strained vertical p-type field effect transistor, comprising:a bottom source/drain region on a substrate;
an interlayer dielectric spacer on the substrate and on opposite sides of the bottom source/drain region;
a vertical fin on the bottom source/drain region;
a bottom spacer on the interlayer dielectric spacer and on opposite sides of the vertical fin; and
a gate dielectric layer on the vertical fin, bottom spacer, and interlayer dielectric spacer.

US Pat. No. 10,714,586

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device including a field effect transistor, comprising:a source/drain region;
a source/drain silicide layer formed on the source/drain region;
an interlayer dielectric layer;
a first contact disposed in the interlayer dielectric layer over the source/drain silicide layer; and
a second contact disposed over the first contact, wherein:
the first contact includes a first metal layer and an adhesive layer disposed between the first metal layer and the interlayer dielectric layer,
an upper surface of the first metal layer is covered by a silicide layer,
a side face of the silicide layer is covered by the adhesive layer,
the silicide layer includes a same metal element as the first metal layer, and
the second contact partially penetrates in the silicide layer such that a bottom of the second contact is located at a middle of the silicide layer.

US Pat. No. 10,714,585

GATE-ALL-AROUND FIELD-EFFECT-TRANSISTOR DEVICES AND FABRICATION METHODS THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a gate-all-around (GAA) field-effect-transistor (FET) device, comprising:providing a base substrate and forming a plurality of first stacked structures on the base substrate, wherein each first stacked structure includes a first sacrificial layer and a first semiconductor layer formed on the first sacrificial layer;
forming a first dummy gate structure across the plurality of first stacked structures, and a first sidewall spacer on each sidewall surface of the first dummy gate structure, wherein the first dummy gate structure is formed on a portion of the base substrate and covers a portion of a top surface and a portion of each sidewall surface of the plurality of first stacked structures;
forming a first source/drain doped layer in the plurality of first stacked structures on each side of the first dummy gate structure and separated from the first dummy gate structure by a first sidewall spacer;
forming a dielectric structure on the base substrate to cover the plurality of first stacked structures and the first source/drain doped layer, wherein the dielectric structure exposes a top surface of the first dummy gate structure and a top surface of each first sidewall spacer;
removing the first dummy gate structure to form a first trench in the dielectric structure;
removing a portion of the first sacrificial layer exposed in the first trench to form a first via under the first semiconductor layer, wherein sidewalls of the first via expose a portion of the sidewalls of the first source/drain doped layer;
forming a first barrier layer directly on a portion of the sidewalls of the first source/drain doped layer exposed by the first via; and
forming a first gate structure to fill the first trench and the first via.

US Pat. No. 10,714,577

ETCH STOP LAYER FOR USE IN FORMING CONTACTS THAT EXTEND TO MULTIPLE DEPTHS

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a first field-effect transistor in a first device region;
a second field-effect transistor in a second device region;
a first dielectric layer over the first device region and the second device region, the first dielectric layer including a recess defining a step at a transition between the first device region and the second device region;
a second dielectric layer arranged within the recess in the first dielectric layer;
a third dielectric layer arranged over the first dielectric layer in the first device region and over the second dielectric layer in the second device region; and
a first contact extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer in the second device region, the first contact coupled to the second field-effect transistor.

US Pat. No. 10,714,550

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS HAVING PROTECTED EMISSION LAYER

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting display apparatus, comprising:a substrate including a display area and a non-display area surrounding the display area;
a first bank disposed on the substrate and having a plurality of openings that correspond to a plurality of sub-pixels;
a second bank separated from the first bank and disposed within the non-display area; and
an insulating layer disposed under the first bank and the second bank and having an opening disposed between the first bank and the second bank such that the opening of the insulating layer separates a first portion of the insulating layer that is disposed under the first bank from a second portion of the insulating layer that is disposed under the second bank,
wherein there are no openings disposed in the insulating layer between the sub-pixels of the plurality of sub-pixels.

US Pat. No. 10,714,545

METHOD FOR MANUFACTURING TOUCH CONTROL DISPLAY SCREEN

Wuhan China Star Optoelec...

1. A method for manufacturing a touch control display screen, comprising:a step S20 of forming a first insulation layer on a thin film encapsulation layer;
a step S30 of forming a bridge layer on the first insulation layer;
s step S40 of forming a second insulation layer on the bridge layer;
a step S50 of using a mask to perform a mask process on the second insulation layer, so as to pattern the first insulation layer and the second insulation layer, and to form a first contact hole in the second insulation layer;
a step S60 of forming a touch control electrode layer on the second insulation layer; and
a step S70 of forming a protection layer on the touch control electrode layer,
wherein the thin film encapsulation layer includes one organic encapsulation layer and two inorganic encapsulation layers, the touch control display screen includes a first display area and a second display area, and the step S50 includes:
a step S51 of coating a photoresist on a surface of the second insulation layer;
a step S52 of using a multi-transmittance mask plate to perform an exposure treatment on the photoresist, and performing a development treatment on the photoresist, such that the photoresist is patterned to generate a first development region and a second development region that are spaced apart from each other,
wherein the first development region is in the first display area, and the second development region is in the second display area;
a step S53 of performing an etching treatment for the second development region, such that a combined thickness of the first insulation layer and the second insulation layer in the second development region is equal to a thickness of the second insulation layer in the first development region;
a step S54 of performing an ashing treatment on the photoresist to remove the photoresist in the first development region and to reduce a thickness of the photoresist that is not exposed;
a step S55 of performing an etching treatment for the first development region and the second development region, such that the first insulation layer and the second insulation layer are patterned, and the first contact hole is formed in the second insulation layer; and
a step S56 of removing the photoresist.

US Pat. No. 10,714,539

ORGANIC LIGHT-EMITTING DISPLAY DEVICE

Samsung Display Co., Ltd....

1. An organic light-emitting display device comprising:a plurality of pixel electrodes, each corresponding to one of at least a first pixel, a second pixel, and a third pixel;
a pixel-defining layer covering an edge of each of the pixel electrodes and exposing a central portion of each of the pixel electrodes;
an intermediate layer over the pixel electrode, the intermediate layer comprising an emission layer;
an opposite electrode over the intermediate layer;
an encapsulation layer over the opposite electrode;
a lens layer over the encapsulation layer, the lens layer comprising a plurality of condensing lenses; and
a touch electrode layer disposed between the encapsulation layer and the lens layer,
wherein the lens layer comprises a first lens layer and a second lens layer between the first lens layer and the encapsulation layer, the second lens layer having a refractive index less than the refractive index of the first lens layer, and wherein the second lens layer comprises a concave portion concave in a direction toward the encapsulation layer and a non-concave portion located outside the concave portion, and the first lens layer comprises a filling portion filling the concave portion and a non-filling portion located outside the filling portion,
wherein each of the non-concave portion of the second lens layer and the non-filling portion of the first lens layer overlaps the pixel-defining layer,
wherein each of the non-concave portion of the second lens layer and the non-filling portion of the first lens layer does not overlap the central portion of each of the pixel electrodes exposed by the pixel-defining layer,
wherein the encapsulation layer comprises at least one inorganic encapsulation layer and at least one organic encapsulation layer, wherein the lens layer is directly disposed on the encapsulation layer.

US Pat. No. 10,714,534

THREE TERMINAL ISOLATION ELEMENTS AND METHODS

SanDisk Technologies LLC,...

1. A method comprising:forming a memory cell comprising a memory element coupled in series with an isolation element,
wherein the isolation element comprises a vertical thin-film transistor and a threshold selector device that comprises a solid electrolyte region and an ion source region.

US Pat. No. 10,714,503

DISPLAY DEVICE INCLUDING TRANSISTOR AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first gate electrode;
a first insulating layer over the first gate electrode;
an oxide semiconductor layer over the first insulating layer;
a source electrode electrically connected to the oxide semiconductor layer;
a drain electrode electrically connected to the oxide semiconductor layer;
a second insulating layer over the oxide semiconductor layer; and
a second gate electrode over the second insulating layer,
wherein the first insulating layer comprises silicon oxide and a region in contact with the oxide semiconductor layer,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc,
wherein the second insulating layer comprises silicon oxide and a region in contact with the oxide semiconductor layer,
wherein the source electrode comprises a region overlapping with the first gate electrode,
wherein the drain electrode comprises a region overlapping with the first gate electrode,
wherein in a channel length direction of the oxide semiconductor layer, the second gate electrode is smaller than the oxide semiconductor layer, and
wherein a side surface of the oxide semiconductor layer comprises a region which is not covered with the source electrode or the drain electrode.

US Pat. No. 10,714,493

SEMICONDUCTOR PLUG PROTECTED BY PROTECTIVE DIELECTRIC LAYER IN THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME

YANGTZE MEMORY TECHNOLOGI...

7. A method for forming a three-dimensional (3D) memory device, comprising:forming a first dielectric deck comprising a first plurality of interleaved sacrificial layers and dielectric layers on a substrate;
forming a first opening extending vertically through the first dielectric deck;
forming a semiconductor plug in a lower portion of the first opening;
forming a protective dielectric layer on the semiconductor plug;
forming a sacrificial layer on the protective dielectric layer in the first opening;
forming a second dielectric deck comprising a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck;
forming a second opening extending vertically through the second dielectric deck to expose the sacrificial layer in the first opening;
removing the sacrificial layer in the first opening;
forming a memory film on the protective dielectric layer and along sidewalls of the first and second openings;
forming a third opening through the memory film and the protective dielectric layer in the lower portion of the first opening; and
forming a semiconductor channel over the memory film and in the third opening to contact the semiconductor plug.

US Pat. No. 10,714,490

THREE-DIMENSIONAL MEMORY DEVICE HAVING BENT BACKSIDE WORD LINES

YANGTZE MEMORY TECHNOLOGI...

1. A three-dimensional (3D) memory device, comprising:a substrate;
a semiconductor layer above and extending laterally beyond at least one edge of the substrate;
a plurality of interleaved conductive layers and dielectric layers above a front side of the semiconductor layer and extending below a back side of the semiconductor layer; and
a plurality of memory strings each extending vertically through the interleaved conductive layers and dielectric layers and in contact with the semiconductor layer.

US Pat. No. 10,714,464

METHOD OF SELECTIVELY TRANSFERRING LED DIE TO A BACKPLANE USING HEIGHT CONTROLLED BONDING STRUCTURES

GLO AB, Lund (SE)

1. A method of transferring devices to a target substrate, comprising:providing a supply coupon comprising a combination of a source substrate and devices thereupon;
providing a target substrate that includes bonding sites;
forming first bonding material portions on one of surfaces of the devices or surfaces of the bonding sites of the target substrate;
coining the first bonding material portions to form first bonding material pads having a flatter bonding surface than that of the first bonding material portions;
bonding a first set of the first bonding material pads with respective bonding structures to form a first set of bonded material portions, wherein the first set of the first bonding material pads is located on one of a first set of devices or the first set of bonding sites of the target substrate, and the bonding structures are located on another one of the first set of devices or the first set of the bonding sites of the target substrate, wherein the step of bonding the first set of the first bonding material pads with respective the first set of bonding structures comprises selectively reflowing the first set of the first bonding pads of the first set of devices without reflowing a second set of the first bonding material pads of the second set of devices, and wherein the selective reflowing is performed by irradiating a laser beam on the first set of the first bonding material pads; and
detaching the first set of devices from the source substrate, wherein the first set of the devices is bonded to the bonding sites of the target substrate by the first set of bonded material portions, while a remaining second set of devices remains on the source substrate.

US Pat. No. 10,714,457

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A device comprising:a first integrated circuit die comprising a first conductive feature, a first insulating layer around the first conductive feature, and a bond pad on the first conductive feature and the first insulating layer;
a second integrated circuit die comprising a second conductive feature and a second insulating layer around the second conductive feature; and
a conductive bonding layer connecting the bond pad to the second conductive feature, a reflow temperature of the conductive bonding layer being lower than a reflow temperature of the bond pad,
wherein the second insulating layer is physically separated from the bond pad by a void, sidewalls of the conductive bonding layer and a top surface of the bond pad being exposed to the void.

US Pat. No. 10,714,451

TILING STRUCTURE TYPE LIGHT APPARATUS FOR ORGANIC LIGHT EMITTING DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting diode (OLED) lighting apparatus of a tiling structure, comprising:a first flexible OLED panel in which a bezel area and a part of a light emitting area are bent;
a second flexible OLED panel in which a bezel area arranged adjacent to the bezel area of the first flexible OLED panel is bent;
a fastening member to couple the first and second flexible OLED panels; and
a light guide plate which is arranged on the fastening member and guides a light which is emitted from a bent side of the first flexible OLED panel upward.

US Pat. No. 10,714,450

METHOD OF BONDING TERMINAL OF SEMICONDUCTOR CHIP USING SOLDER BUMP AND SEMICONDUCTOR PACKAGE USING THE SAME

JMJ Korea Co., Ltd., Buc...

1. A method of bonding a terminal of a semiconductor chip using a solder bump, the method comprising:preparing a semiconductor chip with an aluminum (Al) pad terminal formed thereon (S-1);
forming the solder bump on the Al pad terminal through a primary solder (S-2);
attaching the solder bump and a metal structure to each other via a secondary solder with a higher melting point than a melting point of the primary solder (S-3), wherein the secondary solder is positioned between the solder bump and the metal structure;
performing a heat treatment in a state in which the solder bump and the secondary solder are attached to each other at a heat treatment temperature determined based on the melting point of the secondary solder (S-4); and
mixing the primary solder and the secondary solder that are melted during the heat treatment and converting a resulting mixture into a tertiary solder including only one solder layer having a re-melting point higher than the melting point of the primary solder (S-5),
wherein the forming the solder bump (S-2) comprises forming an intermetallic compound (IMC) on a portion of the solder bump adjacent to the Al pad terminal to be distributed by a predetermined region during formation of the solder bump,
wherein the IMC includes Al.

US Pat. No. 10,714,446

APPARATUS WITH MULTI-WAFER BASED DEVICE COMPRISING EMBEDDED ACTIVE AND/OR PASSIVE DEVICES AND METHOD FOR FORMING SUCH

Intel Corporation, Santa...

6. A method comprising:forming a substrate;
fabricating a first active device adjacent to the substrate;
forming a first set of one or more layers to interconnect with the first active device;
forming a second set of one or more layers;
fabricating a second active or passive device adjacent to the second set of one or more layers;
forming a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets;
dry etching a surface of the second wafer such that pads are exposed; and
forming solder bumps on the exposed pads.

US Pat. No. 10,714,444

ANISOTROPIC CONDUCTIVE FILM

DEXERIALS CORPORATION, T...

1. An anisotropic conductive film having a regular disposition region in which conductive particles are disposed regularly in an insulating resin binder,wherein the anisotropic conductive film is formed on a release film, and
a standard region including no sections with more than a prescribed number of consecutive omissions in conductive particles is present in the regular disposition region over a prescribed width in a short-side direction of the anisotropic conductive film and at least a prescribed length in a long-side direction of the anisotropic conductive film.

US Pat. No. 10,714,436

SYSTEMS AND METHODS FOR ACHIEVING UNIFORMITY ACROSS A REDISTRIBUTION LAYER

Lam Research Corporation,...

1. A method for fabricating a redistribution layer, the method comprising:depositing a dielectric layer on top of a pad located on a substrate;
creating at least one via within the dielectric layer, wherein the dielectric layer has at least two intermediate portions and the at least one via extending therebetween;
depositing a barrier and seed layer on top the dielectric layer, wherein said depositing forms a film on the at least one via and on top of the at least two intermediate portions;
providing a layer of photoresist on top of the film of the barrier and seed layer, wherein the photoresist layer extends into the at least one via;
patterning the photoresist layer over the at least one via, wherein the patterning exposes at least a portion of an upper surface of the barrier and seed layer adjacent to the at least one via;
overfilling the redistribution layer within the at least one via and laterally extending the redistribution layer on top of the exposed upper surface of the barrier and seed layer, wherein said overfilling defines a localized bump over the at least one via and the redistribution layer has a height that is less than a height of the patterned photoresist layer; and
selectively removing the localized bump of the redistribution layer, wherein the localized bump is selectively removed while the height of the patterned photoresist layer is maintained.

US Pat. No. 10,714,434

INTEGRATED MAGNETIC INDUCTORS FOR EMBEDDED-MULTI-DIE INTERCONNECT BRIDGE SUBSTRATES

Intel Corporation, Santa...

1. A semiconductor device package, comprising:an inductor coil in a semiconductor package substrate;
a magnetic material in interstices of the inductor coil;
a recess that projects a footprint onto at least a portion of the inductor coil; and
an embedded multi-die interconnect bridge (EMIB) die in the recess.

US Pat. No. 10,714,433

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a wafer comprising a crystal orientation represented by a family of Miller indices comprising , wherein i2+j2+k2 =2;
a circuit layer; and
a first chip mounted on the wafer through the circuit layer, wherein a first edge of the first chip is arranged in a direction, the direction is not parallel to the crystal orientation, and the first chip includes a plurality of conductive pads facing and electrically connected to the circuit layer.

US Pat. No. 10,714,431

SEMICONDUCTOR PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING

UTAC Headquarters Pte. Lt...

1. A method for forming a semiconductor package, comprising:providing a base carrier defined with an active region and a non-active region, the base carrier has first and second major surfaces;
forming a fan-out redistribution structure over the first major surface of the base carrier;
mounting a die having first and second major surfaces onto the base carrier over the fan-out redistribution structure after formation of the fan-out redistribution structure, the first major surface of the die is an active surface of the die and the second major surface of the die is an inactive surface of the die, wherein the die comprises elongated die contacts protruding from the active surface of the die, the die contacts corresponding to conductive pillars, wherein the die contacts are in electrical communication with the fan-out redistribution structure;
forming an encapsulant having a first major surface and a second major surface opposite to the first major surface, wherein the first major surface is proximate to the inactive surface of the die, wherein the encapsulant surrounds the die contacts and sidewalls of the die; and
forming an electromagnetic interference (EMI) shielding layer, wherein the EMI shielding layer lines the first major surface and sides of the encapsulant.

US Pat. No. 10,714,424

METHOD OF FORMING METAL INTERCONNECTION

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a first conductor;
a dielectric layer disposed on the first conductor;
a via conductor disposed in the dielectric layer and extending to the first conductor such that the via conductor physically contacts the first conductor;
a second conductor disposed in the dielectric layer and on the via conductor; and
a barrier layer interposed between the via conductor and the dielectric layer, and between the second conductor and the dielectric layer, wherein the barrier layer includes a metal and at least two elements included in the dielectric layer.

US Pat. No. 10,714,414

PLANARIZING RDLS IN RDL—FIRST PROCESSES THROUGH CMP PROCESS

Taiwan Semiconductor Manu...

1. A device comprising:a first dielectric layer;
a first redistribution line and a second redistribution line in the first dielectric layer;
an adhesive film over and contacting both a first top surface of the first dielectric layer and a second top surface of the first redistribution line;
a device die over and adhered to the adhesive film; and
an encapsulating material encapsulating the device die therein, wherein the encapsulating material contacts the first top surface of the first dielectric layer.

US Pat. No. 10,714,406

ELECTRONIC POWER MODULE AND ELECTRICAL POWER CONVERTER INCORPORATING SAME

INSTITUT VEDECOM, Versai...

1. Electronic power module having an architecture with 3D stacking, comprising first and second dielectric substrates that are intended to come into thermal contact with first and second heat sinks, respectively, at least one pair of first and second stacked electronic power switching chips and a common intermediate substrate, said first and second electronic power switching chips being sandwiched between said first dielectric substrate and said common intermediate substrate and between said common intermediate substrate and said second dielectric substrate, respectively, wherein said common intermediate substrate is a metal element formed as a single piece and comprises a central portion for implanting said electronic power switching chips, and a thermal conduction portion that is in thermal contact with said first dielectric substrate and/or said second dielectric substrate.

US Pat. No. 10,714,402

SEMICONDUCTOR CHIP PACKAGE FOR IMPROVING FREEDOM OF ARRANGEMENT OF EXTERNAL TERMINALS

SONY CORPORATION, Tokyo ...

1. A semiconductor chip package, comprising:a semiconductor chip that comprises:
a first surface and a second surface opposed to the first surface;
a circuit part; and
a plurality of electrodes configured to supply a voltage to the circuit part;
a resin layer in a periphery of the semiconductor chip;
a substrate that faces the first surface of the semiconductor chip and the resin layer, wherein the substrate has optical transparency;
a rewiring layer on a side of the second surface of the semiconductor chip, wherein the rewiring layer is across an entire region of the second surface; and
a plurality of external terminals on the side of the second surface of the semiconductor chip, wherein each external terminal of the plurality of external terminals is electrically coupled to one electrode of the plurality of electrodes through the rewiring layer.

US Pat. No. 10,714,395

FIN ISOLATION STRUCTURE FOR FINFET AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:a substrate having adjacent first and second fins protruding from the substrate;
an isolation feature between and adjacent to the first fin and the second fin; and
a fin isolation structure between the first fin and the second fin, comprising:
a first insulating layer partially embedded in the isolation feature;
a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer;
a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer; and
a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

US Pat. No. 10,714,392

OPTIMIZING JUNCTIONS OF GATE ALL AROUND STRUCTURES WITH CHANNEL PULL BACK

International Business Ma...

1. A method of forming a nanosheet device, the method comprising the steps of:forming an alternating series of first nanosheets comprising a first material and second nanosheets comprising a second material as a stack on a wafer;
forming at least one dummy gate on the stack;
forming spacers along opposite sidewalls of the at least one dummy gate;
patterning the stack into at least one fin stack beneath the at least one dummy gate;
etching the at least one fin stack to selectively pull back the second nanosheets in the at least one fin stack forming pockets in the at least one fin stack;
filling the pockets with a strain-inducing material comprising an epitaxial material;
forming source and drains on opposite sides of the at least one fin stack;
burying the at least one dummy gate in a dielectric material;
selectively removing the at least one dummy gate forming at least one gate trench in the dielectric material;
selectively removing, through the at least one gate trench, either the first nanosheets or the second nanosheets from the at least one fin stack; and
forming at least one replacement gate in the at least one gate trench.

US Pat. No. 10,714,386

INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING METAL OXIDE ADHESIVE LAYER

Intel Corporation, Santa...

1. A microelectronic assembly, comprising:a first dielectric layer, wherein the first dielectric layer comprises 60% or more filler;
a metal oxide layer in contact with the first dielectric layer, wherein a thickness of the metal oxide layer is between 4 nanometers and 40 nanometers;
a conductive layer in contact with the metal oxide layer; and
a second dielectric layer in contact with the conductive layer, wherein the second dielectric layer comprises 60% or more filler.

US Pat. No. 10,714,383

INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming an interconnect structure, the method comprising:depositing a first etch stop layer (ESL) over a first dielectric layer;
depositing a second dielectric layer over the first ESL;
patterning a first opening in the second dielectric layer and the first ESL, the first opening exposing the first dielectric layer, patterning the first opening forming a first damaged region in the first dielectric layer and a second damaged region in the second dielectric layer;
forming a first conductive feature in the first opening;
removing the second damaged region to form a first gap between the first conductive feature and the second dielectric layer; and
removing the first damaged region to form a second gap between the first conductive feature and the first dielectric layer.

US Pat. No. 10,714,375

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEIKO EPSON CORPORATION, ...

1. A semiconductor device comprising:a semiconductor layer;
a first conductivity type first well that is arranged in a first region of the semiconductor layer;
a first conductivity type first impurity diffusion region that is arranged in the first well;
a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer;
a second conductivity type second well that is arranged so as to surround the second impurity diffusion region in the semiconductor layer:
an insulating film that is arranged on the second impurity diffusion region;
an electrode that is arranged on the insulating film; and
a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

US Pat. No. 10,714,371

METHOD AND APPARATUS FOR LITHOGRAPHY IN SEMICONDUCTOR FABRICATION

TAIWAN SEMICONDUCTOR MANU...

10. A lithographic system, comprising:a vacuum vessel having a first vacuum pressure;
a housing positioned in the vacuum vessel and having a second vacuum pressure that is higher than the first vacuum pressure, wherein the housing has an opening;
a reticle chuck positioned in the housing and having an effective surface for holding a reticle, wherein the effective surface is exposed through the opening;
an exposure tool configured to generate high-brightness light toward the reticle for reflection; and
a wafer stage configured to support a semiconductor wafer so as to allow the semiconductor wafer to receive the high-brightness light reflected from the reticle;
wherein the housing comprises:
a top housing member;
a lateral housing member extending from the top housing member and terminating at a lower edge which is located on a predetermined plane, wherein the effective surface of the reticle chuck is located between the predetermined plane and the top housing member; and
a lower housing member connected to the lower edge, wherein the opening is formed on the lower housing member, and a projection of the lower housing member in a direction that is perpendicular to the effective surface is located outside of the effective surface.

US Pat. No. 10,714,357

METHODS FOR IMPROVED CRITICAL DIMENSION UNIFORMITY IN A SEMICONDUCTOR DEVICE FABRICATION PROCESS

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a device layer over a substrate;
forming a hard mask layer over the device layer, wherein forming the hard mask layer over the device layer includes forming the hard mask layer directly on the device layer;
forming a patterned protector layer over the hard mask layer, wherein forming the patterned protector layer over the hard mask layer includes forming the patterned protector layer directly on the hard mask layer;
forming a patterning layer over the patterned protector layer;
removing a first portion of the patterning layer to expose a first portion of the patterned protector layer and a first portion of the hard mask layer;
removing the first portion of the hard mask layer to expose a first portion of the device layer and a first portion of the substrate;
removing a second portion of the patterning layer; and
removing the first portion of the device layer.

US Pat. No. 10,714,345

PLASMA ASSISTED DOPING ON GERMANIUM

LAM RESEARCH CORPORATION,...

1. A method for forming a junction in a germanium (Ge) layer of a substrate, comprising:arranging the substrate in a processing chamber;
supplying a doping plasma gas mixture to the processing chamber including a phosphorus (P) gas species and an antimony (Sb) gas species;
striking plasma in the processing chamber for a predetermined doping period; and
annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.

US Pat. No. 10,714,329

PRE-CLEAN FOR CONTACTS

Taiwan Semiconductor Manu...

1. A method, comprising:forming a dielectric layer over a contact region on a substrate;
etching the dielectric layer to form a contact opening to expose the contact region; and
pre-cleaning the exposed contact region to remove a residual material formed by the etching, wherein the pre-cleaning comprises:
exposing the contact region to an inductively coupled radio frequency (RF) plasma;
applying, with a direct current power supply unit (DC PSU), a bias voltage to the substrate; and
applying a magnetic field to the inductively coupled RF plasma to collimate ions from the inductively coupled RF plasma.

US Pat. No. 10,714,322

IRMS SAMPLE INTRODUCTION SYSTEM AND METHOD

Thermo Fisher Scientific ...

1. A method of introducing a sample into an Isotope Ratio Spectrometer, comprising steps of(a) generating sample ions in a solvent matrix in an ionization source;
(b) removing at least a proportion of the solvent matrix from the sample ions in a desolvation chamber, so as to produce a flow of sample ions along with non-ionized solvent and solvent ions into a separation chamber;
(c) applying voltages to electrodes in the separation chamber to apply an AC and/or a DC electric field to the flow of ions along with solvent vapors, so as to direct wanted sample ions, having a first mass to charge ratio or range of mass to charge ratios, along a first flow path towards an outlet of the separation chamber, whilst unwanted solvent ions, other ions, and non-ionized solvent are directed away from the said separation chamber outlet, the unwanted solvent ions and other ions having a second mass to charge ratio or range of mass to charge ratios, different to the said first mass to charge ratio or range of ratios; and
(d) decomposing the sample ions to molecular products once they have passed through the outlet of the separation chamber and into a reaction chamber; and
(e) providing molecular products of the decomposed sample ions to the Isotope Ratio Spectrometer.

US Pat. No. 10,714,315

SEMICONDUCTOR REACTION CHAMBER SHOWERHEAD

ASM IP Holdings B.V., Al...

1. A showerhead comprising:a base plate comprising a least a portion of an exhaust channel and having an opening and a plurality of base plate slots;
a middle plate positioned within the opening and having a plurality of middle plate slots and protrusions, the protrusions each comprising a protrusion slot; and,
an upper plate comprising a top surface having a plurality of cooling fins formed therein, a first gas hole and a second gas hole,
wherein the first gas hole conveys a first gas into a first gas cavity and the second gas hole conveys a second gas into a second gas cavity,
wherein each of the plurality of base plate slots is concentrically aligned with the plurality of middle plate slots,
wherein the first gas cavity is defined between the upper plate and the middle plate and the second gas cavity is defined between the middle plate and the base plate,
wherein the first gas cavity and the second gas cavity are fluidly coupled to the exhaust channel,
wherein a first gas purge channel extends from the first gas cavity, wherein the first gas purge channel feeds into a first plenum, wherein the first plenum is coupled to a first valve,
wherein a second gas purge channel extends from the second gas cavity, wherein the second gas purge channel feeds into a second plenum, wherein the second plenum is coupled to a second valve,
wherein one of the first and second valves is configured to provide a purge gas into the first or second gas cavity,
wherein the other of the first and second valves is configured to provide a negative pressure to the first or second gas cavity,
wherein the first gas purge channel extends from the first gas cavity through an opening that is separate from the first gas hole,
wherein the second gas purge channel extends from the second gas cavity through an opening that is separate from the second gas hole,
wherein the first and second gas purge channels do not convey the first gas or the second gas into the first and second gas cavities,
wherein the first gas cavity is in fluid communication with the first gas hole and the second gas cavity is in fluid communication with the second gas hole,
wherein the protrusions extend into the base plate slots,
wherein a gap is formed between each protrusion and each base plate slot and the gap is in fluid communication with the second gas cavity,
wherein the protrusion slots are in fluid communication with the first gas cavity,
wherein the protrusion slots comprise a first radius extending through a portion of the protrusion and a second radius that is smaller than the first radius extending through another portion of the protrusion,
wherein the protrusions extend to at least a bottom surface of the base plate slots, and
wherein the gap terminates at the bottom surface.

US Pat. No. 10,714,313

HIGH FREQUENCY AMPLIFIER APPARATUSES

1. A high-frequency amplifier apparatus suitable for generating power for plasma excitation, the apparatus comprising:two Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors each having a drain terminal and a source terminal that is connected to a ground connection point, wherein the LDMOS transistors are embodied alike and are arranged as a package;
a circuit board that lies flat on a metal cooling plate and is connected to the cooling plate, wherein the cooling plate is connectable to ground by a plurality of ground connections, wherein the package is arranged on the circuit board;
a power transformer including a primary winding connected to the drain terminals of the two LDMOS transistors; and
a signal transformer including a secondary winding having a first end and a second end, wherein
the secondary winding is connected at the first end to a first gate terminal of one of the two LDMOS transistors by one or more first resistive elements, and
the secondary winding is connected at the second end to a second gate terminal of the other of the two LDMOS transistors by one or more second resistive elements; and
wherein each of the first gate terminal and second gate terminal is connected to ground by one or more voltage-limiters.

US Pat. No. 10,714,307

NEUTRAL ATOM IMAGING SYSTEM

KLA-Tencor Corporation, ...

12. A neutral atom imaging system, comprising:a neutral helium imaging sub-system, wherein the neutral helium imaging sub-system comprises:
a neutral atom source configured to generate a beam of neutral atoms and direct the beam to a sample;
an ionizer configured to collect neutral atoms scattered from the surface of the sample and to ionize the collected neutral atoms to generate ionized atoms;
a selector configured to receive the ionized atoms from the ionizer and to selectively filter the ionized atoms;
one or more ion optics; and
a detector, wherein the one or more ion optics are configured to receive selected ionized atoms from the selector and focus the selected ionized atoms onto the detector, wherein the detector is configured to generate one or more images of the sample based on received selected ionized atoms; and
a controller comprising a memory and one or more processors, the controller configured to receive the one or more images from the detector and determine one or more characteristics of the sample based on the one or more images.

US Pat. No. 10,714,299

THERMOELECTRICALLY-COOLED X-RAY SHIELD

The Boeing Company, Chic...

1. A system for x-ray backscatter inspection, the system comprising:an interior cavity;
a non-conductive fluid contained within the interior cavity;
a power source within the interior cavity and submerged in the non-conductive fluid;
an x-ray cathode within the interior cavity, submerged in the non-conductive fluid, and coupled to the power source;
an x-ray anode within the interior cavity, submerged in the non-conductive fluid, and positioned to receive an electron emission from the x-ray cathode to generate an x-ray emission; and
a thermoelectric cooler surrounding the interior cavity and operable to draw heat from the non-conductive fluid, wherein the thermoelectric cooler comprises a heat dissipation layer forming an exterior surface of the system and a heat absorption layer disposed opposite the heat dissipation layer.

US Pat. No. 10,714,294

METAL PROTECTIVE LAYER FOR ELECTRON EMITTERS WITH A DIFFUSION BARRIER

KLA-Tencor Corporation, ...

1. An apparatus comprising:an emitter, wherein the emitter has a diameter of 100 nm or less;
a protective cap layer disposed on an exterior surface of the emitter, wherein the protective cap layer includes molybdenum; and
a diffusion barrier between the emitter and the protective cap layer, wherein the diffusion barrier includes TiN, carbon, B4C, or boron.

US Pat. No. 10,714,285

ELECTROMECHANICAL SWITCHING DEVICE UTILIZING CONTACTS ON ALUMINUM CONDUCTORS AND METHOD OF ADHESION

1. A method of making an electrical switching device, comprising:percussion welding a first contact to a first substrate to form a first static contact assembly,
percussion welding a second contact to a second substrate to form a second static contact assembly, and
percussion welding third and fourth contacts to a third substrate to form a movable contact assembly,
arranging the first and second static contact assemblies relative to each other such that the first static contact assembly is separated by a gap from the second contact assembly,
arranging the movable contact assembly such that the movable contact assembly is movable between an engaged position where the movable contact assembly makes an electrical connection between the first static contact assembly and the second static contact assembly, and a disengaged position where the movable contact assembly does not make the electrical connection between the first static contact assembly and the second static contact assembly,
connecting the movable contact assembly to an activator that when actuated, moves the movable contact assembly to the engaged position, and
connecting the movable contact assembly to a spring that moves the movable contact assembly to the disengaged position when the activator is not actuated,
wherein the first contact, the second contact, the third contact, and the fourth contact each comprise silver,
wherein the first substrate, the second substrate, and the third substrate each comprise aluminum, and
wherein the first contact, the second contact, the third contact, and the fourth contact each include, prior to the percussion welding, a projection that focuses an arc during the percussion welding.

US Pat. No. 10,714,284

DIAL APPARATUS AND IMAGING APPARATUS

CANON KABUSHIKI KAISHA, ...

1. A dial apparatus comprising:an operation member to be rotatably operated;
a contact member including at least three contact portions and configured to rotate as the operation member rotates; and
a substrate provided with a signal pattern provided on each of a plurality of concentric circles with a center at a rotation center of the operation member,
wherein the dial apparatus outputs a binary code when each of the plurality of contact portions contacts each of the plurality of signal patterns as the operation member rotates,
wherein the plurality of signal patterns includes a reference signal area connected to a reference potential, a first signal area configured to output a first signal, and a second signal area configured to output a second signal,
wherein the plurality of signal patterns has a first signal pattern provided with the reference signal area and a second signal pattern provided with the first signal area,
wherein the first signal pattern is provided with the second signal area in an area other than the reference signal area of the first signal pattern,
wherein a first contact portion of the plurality of contact portions contacts the reference signal area of the first signal pattern provided with the second signal area,
wherein a second contact portion of the plurality of contact portions contacts the reference signal area of the first signal pattern provided with the second signal area;
wherein a third contact portion of the plurality of contact portions contacts the second signal pattern provided with the first signal area,
wherein a contact of the first contact portion with the reference signal area of the first signal pattern and a contact of the second contact portion with the second signal area of the first signal pattern are simultaneously performed,
wherein a contact of the second contact portion with the reference signal area of the first signal pattern and a contact of the first contact portion with the second signal area of the first signal pattern are simultaneously performed, and
wherein a contact of the third contact portion with the second signal pattern and a contact of the first contact portion or the second contact portion with the reference signal area of the first signal pattern are simultaneously performed.

US Pat. No. 10,714,275

ILLUMINATED VISIBLE BREAK

Eaton Intelligent Power L...

1. An assembly for use in an electrical power distribution system, the assembly comprising:a housing comprising an interior space;
an electrical apparatus in the interior space, the electrical apparatus comprising an electrical connection mechanism that is configured to move between at least two positions;
an illumination port on the housing;
an observation port through the housing, the observation port being configured to allow visual observation of the electrical connection mechanism in the interior space from an exterior of the housing; and
an optical guide in the housing, wherein the optical guide is configured to receive light from the illumination port, and the optical guide is configured to deliver light from the illumination port to the interior space to thereby illuminate the electrical connection mechanism.

US Pat. No. 10,714,261

MULTILAYER CERAMIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A multilayer ceramic capacitor comprising:a laminate including a plurality of dielectric layers and a plurality of internal electrode layers that are alternately laminated in a height direction, and including a first principal surface and a second principal surface that are opposite to each other in the height direction, a first side surface and a second side surface that are opposite to each other in a width direction orthogonal or substantially orthogonal to the height direction, and a first end surface and a second end surface that are opposite to each other in a length direction orthogonal or substantially orthogonal to both the height direction and the width direction;
a first external electrode that covers the first end surface; and
a second external electrode that covers the second end surface; wherein
the plurality of internal electrode layers include a plurality of first internal electrode layers connected to the first external electrode and a plurality of second internal electrode layers connected to the second external electrode;
the first external electrode includes a first base electrode layer on a side of the laminate and a first plating film on the first base electrode layer;
the second external electrode includes a second base electrode layer on a side of the laminate and a second plating film on the second base electrode layer;
each of the plurality of first internal electrode layers and the first base electrode layer are connected through a first alloy layer including a metal from which each of the plurality of first internal electrode layers is made and a metal from which the first base electrode layer is made;
each of the plurality of second internal electrode layers and the second base electrode layer are connected through a second alloy layer including a metal from which each of the plurality of second internal electrode layers is made and a metal from which the second base electrode layer is made;
the first alloy layer continuously covers the first end surface in a portion exposing the plurality of first internal electrode layers in a direction parallel or substantially parallel to an in-plane direction of the first end surface;
the second alloy layer continuously covers the second end surface in a portion exposing the plurality of second internal electrode layers in a direction parallel or substantially parallel to an in-plane direction of the second end surface;
a plane parallel or substantially parallel to both of the height direction and the length direction and including a center portion of the laminate in the width direction is a first plane;
a plane parallel or substantially parallel to both the width direction and the length direction and including a center portion of the laminate in the height direction is a second plane;
a ridge of the laminate in a portion connecting between the first end surface and the first principal surface is a first ridge;
a ridge of the laminate in a portion connecting between the first end surface and the second principal surface is a second ridge;
a ridge of the laminate in a portion connecting between the first end surface and the first side surface is a third ridge;
a ridge of the laminate in a portion connecting between the first end surface and the second side surface is a fourth ridge;
a ridge of the laminate in a portion connecting between the second end surface and the first principal surface is a fifth ridge;
a ridge of the laminate in a portion connecting between the second end surface and the second principal surface is a sixth ridge;
a ridge of the laminate in a portion connecting between the second end surface and the first side surface is a seventh ridge; and
a ridge of the laminate in a portion connecting between the second end surface and the second side surface is an eighth ridge;
a curvature radius R1 of the first ridge on the first plane, a curvature radius R2 of the second ridge on the first plane, a curvature radius R3 of the third ridge on the second plane, and a curvature radius R4 of the fourth ridge on the second plane are all about 5.4 ?m or more and about 10 ?m or less;
a curvature radius R5 of the fifth ridge on the first plane, a curvature radius R6 of the sixth ridge on the first plane, a curvature radius R7 of the seventh ridge on the second plane, and a curvature radius R8 of the eighth ridge on the second plane are all about 5.4 ?m or more and about 10 ?m or less;
the first external electrode extends from the first end surface to portions of the first principal surface, the second principal surface, the first side surface, and the second side surface toward the first end surface so as to cover the first ridge, the second ridge, the third ridge, and the fourth ridge; and
the second external electrode extends from the second end surface to portions of the first principal surface, the second principal surface, the first side surface, and the second side surface toward the second end surface so as to cover the fifth ridge, the sixth ridge, the seventh ridge, and the eighth ridge.

US Pat. No. 10,714,257

WINDING BOBBIN AND WINDING COMPONENT

HIOKI DENKI KABUSHIKI KAI...

1. A winding bobbin comprising:a bobbin main body constructed in a ring shape so as to be capable of housing a ring-shaped core; and
a plurality of partitions that are provided at intervals in a circumferential direction of the bobbin main body and are formed so as to protrude from a surface of the bobbin main body,
wherein a winding is formed by winding a conductive wire in winding regions on the surface that are partitioned by the partitions, and
the partitions each include:
a flange that is formed of a U-shaped plate that protrudes from the surface at three positions out of four positions that are an outer circumference, an inner circumference, and two sides of the bobbin main body, with one position omitted; and
a protrusion that is formed so as to protrude from at least one out of two opening-side ends of the flange.

US Pat. No. 10,714,251

PRECISION TRANSFORMER FOR ANTENNA ELEMENTS

RAYTHEON COMPANY, Waltha...

1. A transformer assembly comprising:a first toroidal core transformer having a first core and a first primary winding and a first secondary winding each wound around the first core; and
a second toroidal core transformer having a second core and a second primary winding and a second secondary winding each wound around the second core, the second core being twisted 180 degrees relative to the first core along an axis in plane of the second core, the first and second primary windings being connected in parallel with one another, the first and second secondary windings being connected in parallel with one another, a first half of the first secondary winding being connected in series with a second half of the second secondary winding, and a second half of the first secondary winding being connected in series with a first half of the second secondary winding.

US Pat. No. 10,714,249

3D PRINTER WITH HOVERING PRINTING HEAD OR PRINTING BED

Airbus Operations GmbH, ...

1. A three-dimensional (3D) printing device, comprising:printing material;
a printing bed;
a superconductor;
a printing head arrangement configured to print the printing material onto the printing bed, wherein either the printing head arrangement or the printing bed is attached for movement with the superconductor;
a magnetic field generator configured to generate a magnetic field
a movement device configured to move the magnetic field generator in at least one direction, perpendicular to a force-locking direction between the superconductor and the magnetic field generator, the movement device comprising at least one linear motor; and
a control device;
wherein the magnetic field generator and the superconductor are configured to couple in a force-locking manner by frozen magnetic flux between the magnetic field generator and the superconductor; and
wherein the control device is configured to control a magnetic field strength of the magnetic field generator.

US Pat. No. 10,714,246

RARE EARTH PERMANENT MAGNET AND METHOD FOR MANUFACTURING THEREOF

Hyundai Motor Company, S...

1. A method for manufacturing a rare earth permanent magnet, comprising steps of:manufacturing an NdFeB sintered magnet;
disposing, on a surface of the NdFeB sintered magnet, a grain boundary diffusion material in the form of a mixed powder comprising an alloy powder containing Re1aMb and Re2 hydride; and
heating the grain boundary diffusion material to diffuse at least one of Re1, Re2, and M into a grain boundary part inside the sintered magnet or a grain boundary part region of a sintered magnet main phase grain,
where Re1 and Re2 are each rare earth elements selected from the group consisting of dysprosium, terbium, neodymium, praseodymium, and holmium, M is one or more metal compounds selected from the group consisting of copper, zinc, tin, and aluminum, 0.1 wherein the grain boundary diffusion material contains Cu in an amount of 0.25 to 1 wt %, based on a total weight of the grain boundary diffusion material, and the alloy powder containing Cu is formed at particle diameter of 2 to 10 ?m, and
wherein the disposed grain boundary diffusion material forms a layer and the thickness of the layer is 5 ?m to 150 ?m.

US Pat. No. 10,714,243

VARIABLE RESISTANCE CIRCUIT, OSCILLATOR CIRCUIT, AND SEMICONDUCTOR DEVICE

SEIKO EPSON CORPORATION, ...

1. A variable resistance circuit comprising:a first resistance sub-circuit having:
a first resistor;
a first switch circuit connected in series to one end of the first resistor; and
a second switch circuit connected in parallel to a series circuit of the first resistor and the first switch circuit; and
a second resistance sub-circuit connected in series with the first resistance sub-circuit, the second resistance sub-circuit having:
a second resistor; and
a third switch circuit connected in parallel to the second resistor,
wherein, when one of the first and second switch circuits is turned on, the other of the first and second switch circuits is turned off, the first and second resistance sub-circuits form a ladder resistor circuit, and a switch circuit connected in series with the second resistor is not provided in the second resistance sub-circuit.

US Pat. No. 10,714,238

JOINT FOR SUPERCONDUCTING WIRE

HITACHI, LTD., Tokyo (JP...

1. A joint for superconducting wires, comprising:a plurality of superconducting wires each coated with a metal sheath;
a wire support element configured to support the superconducting wires;
a first sintered body configured to fix the superconducting wires on the wire support element; and
a second sintered body configured to join the coated superconducting wires,
wherein the superconducting wires, the first sintered body, and the second sintered body contain MgB2,
end parts of the superconducting wires and the first sintered body are polished, and
the second sintered body is disposed along a polished surface on the end parts of the superconducting wires and the first sintered body.

US Pat. No. 10,714,228

METHOD FOR PRODUCING A MICROSTRUCTURE COMPONENT, MICROSTRUCTURE COMPONENT AND X-RAY DEVICE

SIEMENS HEALTHCARE GMBH, ...

1. A method for producing a microstructure component, comprising:inserting a plurality of punctiform injection structures in a grid in a first substrate direction and inserting a second substrate direction, standing at right angles to the first substrate direction, into a first surface of a wafer-like silicon substrate;
lengthening, in a first etching step, the punctiform injection structures into drilled holes in a depth direction of the silicon substrate;
at least partly removing, in a second etching step, a second surface of the silicon substrate, lying opposite the first surface, for rear-side opening of the drilled holes; and
pouring in a third etching step, an etching medium, effective anisotropically, alternately through the drilled holes from both surfaces of the silicon substrate, so that drilled holes arranged next to one another in the first substrate direction connect to form a column running in the first substrate direction.

US Pat. No. 10,714,220

FUEL CHANNEL FOR A NUCLEAR BOILING WATER REACTOR

9. A fuel channel for a fuel assembly for a nuclear power boiling water reactor, the fuel channel defining a length direction which in use corresponds substantially to the vertical direction, wherein the fuel channel comprises:at least one first sheet of a Zr-based material, said at least one first sheet having a first thickness, wherein said first thickness is constant throughout each first sheet;
at least one second sheet of a Zr-based material, said at least one second sheet having a second thickness, wherein said second thickness is constant throughout each second sheet and said second thickness is less than said first thickness; and
said at least one first sheet and said at least one second sheet being shaped to form said fuel channel, wherein said at least one first sheet forms a lower part of the fuel channel and said at least one second sheet forms a higher part of the fuel channel, said at least one first sheet joined with said at least one second sheet to form a joint arranged where said at least one first sheet has been joined with said at least one second sheet, wherein said joint also forms a joint between said lower part and said higher part,
wherein the fuel channel has a first cross sectional inner area in the higher part, the first cross sectional inner area is larger than a second cross sectional inner area in the lower part,
wherein the joint is located between said lower part and said higher part wherein the lower part constitutes 20-75% of the length of the fuel channel.

US Pat. No. 10,714,217

SYSTEMS AND METHODS FOR ENABLING CUSTOMERS TO OBTAIN VISION AND EYE HEALTH EXAMINATIONS

1. A system for providing a remotely assisted eye examination, comprising:a diagnostic center including ophthalmic equipment comprising a set of instruments that are utilized in administering an eye examination to a customer that includes vision acuity tests, wherein:
an equipment controller is in communication with at least a portion of the ophthalmic equipment and permits multiple individuals to control the ophthalmic equipment during the eye examination;
the equipment controller includes, or communicates with, a vision examination controller that is in communication with vision examination equipment, the vision examination equipment at least including an auto-phoropter and eye chart;
an onsite device that is operated by an onsite individual located at the diagnostic center;
a first remote device that is operated by a first remote individual;
a second remote device that is operated by a second remote individual; and
wherein the ophthalmic equipment and test administration associated with the eye examination is controlled by each of the onsite individual, the first remote individual, and the second remote individual during the eye examination, and administering the eye examination to the customer at a diagnostic center includes:
establishing, during the eye examination, a first real-time video conference connection between the diagnostic center and the first remote device over a network to enable the first remote individual and the customer to communicate during the eye examination;
establishing, during the eye examination, a second real-time video conference connection between the diagnostic center and the second remote device over the network to enable the second remote individual and the customer to communicate during the eye examination;
receiving, at the equipment controller during the eye examination, commands from the multiple individuals to permit each of the multiple individuals to control the ophthalmic equipment during the eye examination, wherein receiving commands from the multiple individuals includes:
receiving, at the equipment controller during the eye examination, first commands from the first remote device that is operated by the first remote individual located remotely with respect to the diagnostic center, wherein the first commands are transmitted to the equipment controller in response to one or more selections received via a graphical user interface displayed on the first remote device and the first commands are at least utilized by the vision examination controller to control a portion of the vision examination equipment during the eye examination, the first commands being transmitted to the equipment controller over the network and enabling the first remote individual to remotely switch lenses of the auto-phoropter; and
receiving, at the equipment controller during the eye examination, second commands from the second remote device that is operated by the second remote individual located remotely with respect to the diagnostic center, wherein the second commands are transmitted to the equipment controller in response to one or more selections received via a graphical user interface displayed on the second remote device and the second commands are at least utilized by the vision examination controller to control a portion the vision examination equipment during the eye examination, the second commands being transmitted to the equipment controller over the network;
administering, by the multiple individuals during the eye examination, a plurality of eye tests to the customer during the eye examination based, at least in part, on control of the ophthalmic equipment included in the vision examination equipment, wherein administering the plurality of tests includes:
administering, by the onsite individual, one or more eye tests to the customer;
administering, by the first remote individual over the first real-time video conference connection, one or more eye tests to the customer; and
administering, by the second remote individual over the second real-time video conference connection, one or more eye tests to the customer; and
generating evaluation data based on the plurality of eye tests.

US Pat. No. 10,714,216

METHOD AND SYSTEM FOR INCREASING ACCURACY OF HYGIENE COMPLIANCE DETERMINATIONS

SwipeSense, Inc., Chicag...

16. A computer implemented method for increasing accuracy of hygiene compliance in medical facilities, the method comprising:determining received signal strength between a tag and one or more location beacons;
transmitting the received signal strength to a hygiene compliance datastore;
determining one or more of tag accelerometer data, orientation data, heading data, or tag movement data;
transmitting the one or more of the tag accelerometer data, the orientation data, the heading data, or the tag movement data to the hygiene compliance datastore;
processing, by a computer, data stored in the hygiene compliance datastore;
determining hygiene compliance based at least on the processed data;
determining positions of a plurality of location beacons in a coordinate system;
transmitting the positions of the plurality of location beacons to the hygiene compliance datastore;
determining possible and impossible movement paths of the tag;
transmitting the possible and impossible movement paths of the tag to the hygiene compliance datastore;
determining one or more of usage of logs, timestamps associated with the tag, or timestamps associated with a use of a hygiene dispenser;
transmitting the one or more of the usage of logs, the timestamps associated with the tag, or the timestamps associated with the use of a hygiene dispenser to the hygiene compliance datastore;
processing, by the computer, the data stored in the hygiene compliance datastore; and
determining the hygiene compliance based at least on the processed data.

US Pat. No. 10,714,212

ANALYTE METER

Ascensia Diabetes Care Ho...

24. A method of transferring data relating to a measurement of an analyte from a fluid sample from a testing device to a mobile device, the testing device including a first wireless transceiver, a testing sensor interface including a port for accepting the insertion of a test sensor, and an illumination panel surrounding the port, the illumination panel emitting light in a first color to highlight the port prior to insertion of the test sensor in the port, and emitting light in one of a plurality of other colors to communicate data relating to the measurement of the analyte, the method comprising:storing an application received via a network connection to the mobile device;
executing the application on the mobile device;
pairing the testing device with the mobile device using the application;
emitting light in a second color to indicate pairing of the testing device with the mobile device;
wirelessly sending the data via the testing device to the mobile device; and
displaying on the mobile device the data on a display of the mobile device.

US Pat. No. 10,714,211

APPARATUS AND METHOD FOR IMPROVING CHEMICAL PROCESS EFFICIENCY AND PROMOTING SHARING OF CHEMISTRY INFORMATION

CHANGZHOU SANTAI TECHNOLO...

1. An apparatus for improving chemical process efficiency and promoting sharing of chemistry information, applied to obtaining and querying characteristic information and chemistry information of the target compound or the target compound system, as well as generating and/or executing a chemical process of the target compound or the target compound system, the apparatus comprises a processor further comprising an execution module, a knowledge base module, a control module and a query and trade analysis module, whereinthe execution module, applied to generating and/or executing a chemical process designed by a user or obtained through an electronic transaction, of the target compound or the target compound system;
the knowledge base module, applied to storing the chemistry information of the target compound and/or the target compound system, each type of the chemical process of each target compound and/or each target compound system has an assessed efficiency value, the assessed efficiency value is a reference basis for a chemical process transaction;
the control module, applied to communicating and controlling the execution module, the knowledge base module, and the query and trade analysis module wherein the control module directs the query and trade analysis module to receive the characteristic information of the target compound or the target compound system, and search for the matched chemistry information of the target compound or the target compound system in the knowledge base module of the apparatus, and in the knowledge base module of other devices and/or the remote central database server connected into the internet through the knowledge base module of the apparatus, followed by delivering the retrieved matched chemical processes of the target compound or the target compound system to the execution module to execute the chemical process of the target compound or the target compound system;
the query and trade analysis module, further includes a matching unit, a transaction unit, and an analysis unit, wherein
the matching unit, applied to searching the knowledge base module of the apparatus, a plurality of other knowledge base modules connected into a network, or a remote central database server for matched chemistry information and/or matched chemical process of the target compound and/or the target compound system through obtained characteristic information of the target compound and/or the target compound system;
the transaction unit, applied to obtaining the matched chemistry information and/or matched chemical process of the target compound and/or the target compound system through electronic transaction, initiated by the user;
the analysis unit, applied to executing an assessment and analysis to the efficiency of the executed chemical process after executing the chemical process, the chemical process is either designed by the user or obtained through electronic transaction;
wherein the user updates and/or improves the obtained matched chemical processes, after the transaction unit obtains the matched chemical process through electronic transaction according to the user's request, followed by being executed by the execution module, if the matching unit has retrieved the chemical process information matching the target compound and/or the target compound system; and after finishing performing the chemical processes updated or improved by the user, the analysis unit will evaluate the efficiency of the user updated or improved chemical process performed this time accordingly, and perform a comparison of the efficiency value based on the user updated and/or improved chemical process performed this time with the matched efficiency value of the chemical process stored in the knowledge base before generating a analysis report, followed by a plurality of according operations performed by the control module and based on an analysis and comparison result of the assessed efficiency value of the user updated and/or improved chemical process performed this time higher than the matched assessed efficiency value of the chemical process stored in the knowledge base, the user will be prompted and guided to perform an update operation to the knowledge base.

US Pat. No. 10,714,206

SELECTORS ON INTERFACE DIE FOR MEMORY DEVICE

Micron Technology, Inc., ...

1. An interface chip comprising:a first memory channel coupled to a first die;
a second memory channel coupled to a second die;
a first terminal corresponding to the first memory channel;
a second terminal corresponding to the second memory channel;
a test input/output (IO) circuit coupled to a tester via a probe;
a built in self test (BIST) circuit comprising an algorithmic pattern generator; and
a first test channel selector associated with the first memory channel and a second test channel selector associated with the second memory channel, the first test channel selector configured to selectively couple, based on at least one respective value of at least one control signal, the test IO circuit, the BIST circuit and the first terminal to the first memory channel, the second test channel selector configured to selectively couple, based on at least one respective other value of the at least one control signal, the test IO circuit, the BIST circuit and the second terminal to the second memory channel.

US Pat. No. 10,714,204

SHIFT REGISTER UNIT, DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

CHONGQING BOE OPTOELECTRO...

1. A shift register unit, comprising:a reset signal terminal, a first voltage terminal, a second voltage terminal, a third voltage terminal, a clock signal terminal, a signal input terminal, and a signal output terminal;
a first node control circuit configured to transfer a reset signal at the reset signal terminal to a first node in response to the reset signal at the reset signal terminal being active;
a second node control circuit configured to transfer an inactive voltage at the first voltage terminal to the first node in response to a potential at a second node being active;
an energy-storing circuit configured to store a voltage across the first node and the first voltage terminal;
a first voltage pull circuit configured to transfer the inactive voltage at the first voltage terminal to the second node and the signal output terminal in response to a first supply voltage signal at the second voltage terminal and a potential at the first node being active;
a second voltage pull circuit configured to transfer the inactive voltage at the first voltage terminal to the second node and the signal output terminal in response to a second supply voltage signal at the third voltage terminal and the potential at the first node being active; and
an output circuit configured to transfer a clock signal at the clock signal terminal to the signal output terminal in response to the potential at the second node being active.

US Pat. No. 10,714,199

PUF LATCH FOR OTP MEMORY ARRAYS AND METHOD OF OPERATION

Synopsys, Inc., Mountain...

1. A physically unclonable function (PUF) circuit, comprising:a first one-time programmable (OTP) memory cell;
a second OTP memory cell; and
a latch circuit connected to the first and second OTP memory cells, the latch circuit configured to:
initiate programming of the first and second OTP memory cells;
detect a faster programming OTP memory cell of the first and second OTP memory cells;
inhibit programming of a slower programming OTP memory cell of the first and second OTP memory cells; and
store a first bit value when the first OTP memory cell is the faster programming OTP memory cell and a second bit value when the second OTP memory cell is the faster programming OTP memory cell.

US Pat. No. 10,714,197

MEMORY DEVICE AND PROGRAM VERIFICATION METHOD THEREOF

MACRONIX INTERNATIONAL CO...

1. A program verification method adapted for a memory device, the program verification method comprising:reading a previous page to obtain a first read data;
writing input data to a current page;
reading the previous page or the current page to obtain a second read data; and
analyzing at least one of the first read data and the second read data to determine whether to back up at least one of the first read data and the input data to a redundant block of the memory device.

US Pat. No. 10,714,195

READ DISTURB DETECTION AND RECOVERY WITH ADAPTIVE THRESHOLDING FOR 3-D NAND STORAGE

SK Hynix Inc., Gyeonggi-...

1. A non-volatile data storage device, comprising:a plurality of memory cells arranged in blocks; and
a memory controller coupled to the plurality of memory cells for controlling data write and read in the plurality of memory cells;
wherein the memory controller is configured to:
receive a read command to read a first block, the first block being associated with a first read count and a first read threshold, wherein the first read count represents a number of read operations of the first block that has been performed, and the first read threshold represents a number of read operations that triggers a read test operation;
set the first read threshold as a target read threshold;
determine whether the first read count is equal to zero;
in response to determining that the first read count is equal to zero, select a second read threshold as the target read threshold, wherein selecting the second read threshold includes:
performing a test read to determine a number of bit errors associated with a plurality of blocks associated with the first block;
selecting the second read threshold based on the number of bit errors; and
setting the second read threshold as the target read threshold;
perform a read operation of the first block;
increment the first read count;
determine whether the first read count exceed the target read threshold;
in response to determining that the first read count is equal to a multiple of the target read threshold:
perform a test read operation to determine a number of bit errors associated with the plurality of blocks associated with the first block;
determine whether the number of bit errors exceeds an error threshold, the error threshold being selected based on the number of bit errors;
in response to determining that the number of bit errors exceeds the error threshold:
perform a read reclaim operation in the plurality of blocks associated with the first block; and
clear the first read count associated with the first block.

US Pat. No. 10,714,193

DATA STORAGE APPARATUS AND METHOD FOR PREVENTING DATA ERROR USING THE SAME

SILICON MOTION, INC., Zh...

1. A data storage apparatus, comprising:a memory, comprising a plurality of blocks; and
a memory controller coupled to the memory and configured to perform the following operations:
recording a read count of a target block of the memory;
performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and
programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.

US Pat. No. 10,714,189

ATOMICITY MANAGEMENT IN AN EEPROM

PROTON WORLD INTERNATIONA...

1. A method, comprising:performing a write operation by steps including:
initializing a first flag to a first value and storing the first value of the first flag in an EEPROM;
initializing a second flag to a second value and storing the second value of the second flag in an EEPROM;
erasing a memory location in the EEPROM;
writing data into the memory location in the EEPROM; and
writing into the EEPROM a third value of the first flag and a fourth value of the second flag after completing writing the data into the memory location in the EEPROM.

US Pat. No. 10,714,188

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A memory device, comprising:a memory cell array including a first memory block,
the first memory block including a first sub block and a second sub block,
the first sub block including a first memory unit and a second memory unit,
the first memory unit including a first drain side selective transistor, a plurality of first memory cells, a first source side selective transistor, a plurality of second memory cells, and a first connecting portion that connects the first memory cells and the second memory cells in series,
the second memory unit including a second drain side selective transistor, a plurality of third memory cells, a second source side selective transistor, a plurality of forth memory cells and a second connecting portion that connects the third memory cells and the fourth memory cells in series;
the second sub block including a third memory unit and a fourth memory unit,
the third memory unit including a third drain side selective transistor, a plurality of fifth memory cells, a third source side selective transistor, a plurality of sixth memory cells and a third connecting portion that connects the fifth memory cells and the sixth memory cells in series;
the fourth memory unit including a fourth drain side selective transistor, a plurality of seventh memory cells, a fourth source side selective transistor, a plurality of eighth memory cells and a fourth connecting portion that connects the seventh memory cells and the eighth memory cells in series;
a first bit line electrically connected to the first drain side selective transistor and the third drain side selective transistor;
a second bit line electrically connected to the second drain side selective transistor and the fourth drain side selective transistor;
a plurality of first word lines electrically connected to the first memory cells, the third memory cells, the fifth memory cells, and the seventh memory cells, respectively,
a plurality of second word lines electrically connected to the second memory cells, the fourth memory cells, the sixth memory cells, and the eighth memory cells respectively;
a first source side line electrically connected to the first source side selective transistor and the second source side selective transistor;
a second source side line connected to the third source side selective transistor and the fourth source side selective transistor; and
a control circuit configured to apply a first voltage to the first bit line and the second bit line, a second voltage which is lower than the first voltage to the first source side line, a third voltage which is higher than the second voltage to the second source side line, a fourth voltage which is lower than the second voltage to the plurality of first word lines and the plurality of second word lines, while erase operation to the first sub block is operated.

US Pat. No. 10,714,185

EVENT COUNTERS FOR MEMORY OPERATIONS

Micron Technology, Inc., ...

1. A counter, comprising:a plurality of sensing components, each respective sensing component configured to sense a respective event and comprising a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event, wherein the second capacitor is configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor; and
a comparator comprising a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events, the comparator configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

US Pat. No. 10,714,182

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a bit line;
a source line;
a memory string that is provided between the bit line and the source line, and that includes a plurality of memory cells electrically connected in series, the plurality of memory cells including:
a first memory cell,
a second memory cell, the first memory cell being provided between the source line and the second memory cell,
a third memory cell, the second memory cell being provided between the source line and the third memory cell, and
a fourth memory cell, the third memory cell being provided between the source line and the fourth memory cell;
first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively;
a voltage generation circuit configured to generate at least three kinds of voltages, the three kinds of voltages including a first voltage, a second voltage, and a third voltage;
a first circuit configured to:
output the first voltage or one of the second voltage and the third voltage to a first wire, and
output the first voltage or the one of the second voltage and the third voltage to a second wire;
a second circuit configured to output the other one of the second voltage and the third voltage to a third wire and a fourth wire;
a third circuit configured to connect the first and second wires or the third and fourth wires to the first and second word lines, respectively; and
a fourth circuit configured to connect the first and second wires or the third and fourth wires to the third and fourth word lines, respectively.

US Pat. No. 10,714,177

MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING

Micron Technology, Inc., ...

1. A memory cell, comprising:a first memory element positioned between a first electrode and a second electrode, the first memory element being programmable to store a first logic value or a second logic value; and
a second memory element positioned between the second electrode and a third electrode, the second memory element being programmable, independent from the first memory element, to store the first logic value or the second logic value.

US Pat. No. 10,714,174

RESISTIVE MEMORY DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Icheon (K...

1. A resistive memory device, comprising:a normal cell array suitable for including a plurality of memory cells and generating a cell current according to a resistance state of a memory cell selected among the plurality of memory cells based on an input address;
a reference cell array suitable for including a plurality of sub-arrays each including a predetermined number of memory cells, and generating a reference current according to a combination of resistance states of memory cells of a sub-array, the sub-array being selected among the plurality of sub-arrays based on a reference selection signal, each of the plurality of sub-arrays including a reference cell and a plurality of neighboring cells disposed around the reference cell, each of the plurality of neighboring cells being programmed into one of a first resistance state and a second resistance state;
a sense amplifier circuit suitable for sensing and amplifying a signal indicative of data of the selected memory cell based on the cell current and the reference current during a read operation; and
a reference cell selector suitable for generating the reference selection signal, the sub-array in the reference cell array corresponding to a position of the selected memory cell in the normal cell array.

US Pat. No. 10,714,169

SYSTEM AND METHOD FOR PROGRAMMING NON-VOLATILE MEMORY DURING BURST SEQUENTIAL WRITE

SanDisk Technologies LLC,...

1. An apparatus, comprising:a plurality of non-volatile memory cells and word lines, each of the plurality of non-volatile memory cells being associated with one of the word lines and configured to retain a threshold voltage within a common range of threshold voltages defining a threshold window;
the plurality of non-volatile memory cells including a plurality of multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into a plurality of bands of threshold voltages representing the plurality of bits and each having a band width, the plurality of bands of threshold voltages including a lowest band denoting an erased state and a plurality of increasing bands; and
a control circuit in communication with the plurality of non-volatile memory cells and word lines, the control circuit configured to:
program a first set of the data into the plurality of multi-bit cells associated with selected word lines in a single-bit mode with each of the plurality of multi-bit cells storing one bit using a pair of first target states representing the one bit being one of the erased state and a tight intermediate state having a distribution of the threshold voltage being no wider than the band width of a single one of the plurality of increasing bands,
program a second set of the data into the plurality of multi-bit cells associated with selected word lines in a multi-bit mode with each of the plurality of multi-bit cells storing the plurality of bits.

US Pat. No. 10,714,167

APPARATUSES HAVING MEMORY STRINGS COMPARED TO ONE ANOTHER THROUGH A SENSE AMPLIFIER

Micron Technology, Inc., ...

1. An apparatus comprising:a first bitline extending horizontally;
a second bitline being offset vertically from the first bitline and extending horizontally in parallel to the first bitline;
a common plate extending horizontally between the first and second bitlines;
a plurality of first memory cell structures disposed horizontally between the first bitline and the common plate, each of the plurality of first memory cell structures including a first access device and a first capacitor coupled in series between the first bitline and the common plate, the first capacitor having a first electrode and a second electrode, the first electrode being configured as an upwardly-opening container structure; and
a plurality of second memory cell structures disposed horizontally between the second bitline and the common plate, each of the plurality of second memory cell structures including a second access device and a second capacitor coupled in series between the second bitline and the common plate, the second capacitor having a third electrode and a fourth electrode, the third electrode being configured as a downwardly-opening container structure, the first capacitor and the second capacitor being mirror images or each other across the common plate.

US Pat. No. 10,714,166

APPARATUS AND METHODS FOR DECODING MEMORY ACCESS ADDRESSES FOR ACCESS OPERATIONS

Micron Technology, Inc., ...

1. A memory, comprising:an array of memory cells comprising a plurality of blocks of memory cells;
a plurality of driver circuitries, each driver circuitry of the plurality of driver circuitries connected to a respective block of memory cells of the plurality of blocks of memory cells through a respective plurality of switches; and
block select circuitry having a single output, wherein the output of the block select circuitry is selectively connected to each driver circuitry of the plurality of driver circuitries;
wherein connection of the output of the block select circuitry to any driver circuitry of the plurality of driver circuitries comprises connection of the output of the block select circuitry to a respective control gate of each switch of the respective plurality of switches for that driver circuitry.

US Pat. No. 10,714,161

SEMICONDUCTOR DEVICE

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a memory region selection circuit suitable for generating a plurality of memory region select signals based on a memory region address signal and a mode identification signal, and activating one or more memory region select signals among the plurality of memory region select signals during a first mode, or activating two or more memory region select signals among the plurality of memory region select signals during a second mode;
a column selection circuit suitable for generating a plurality of column select signals based on a column address signal and the mode identification signal, and changing the plurality of column select signals during the first mode, or retaining the plurality of column select signals during the second mode; and
a plurality of memory regions of which one or more memory regions are accessed during the first mode or two or more memory regions are accessed during the second mode, based on the plurality of memory region select signals and the plurality of column select signals,
wherein the column selection circuit generates and retains the plurality of column select signals for a current unit operation time, and changes and retains the plurality of column select signals for a next unit operation time, per input of the column address signal during the first mode, and
wherein the column select circuit generates and retains the plurality of column select signals for the current unit operation time per input of the column address signal during the second mode.

US Pat. No. 10,714,160

WAVE PIPELINE

Micron Technology, Inc., ...

1. A memory comprising:an array of memory cells;
a clock signal path to provide a clock signal;
a plurality of data paths each comprising a sensing device to sense data from the array of memory cells in response to the clock signal, each data path of the plurality of data paths having a different length, and a first data path of the plurality of data paths having a first length and each of the other data paths of the plurality of data paths having a length shorter than the first length; and
a single return clock signal path to provide a single return clock signal initiated at the sensing device of the first data path of the plurality of data paths, the single return clock signal to trigger data out of the sensing device of each data path of the plurality of data paths to align the data out of the sensing device of each data path of the plurality of data paths with the single return clock signal.

US Pat. No. 10,714,159

INDICATION IN MEMORY SYSTEM OR SUB-SYSTEM OF LATENCY ASSOCIATED WITH PERFORMING AN ACCESS COMMAND

Micron Technology, Inc., ...

1. A method, comprising:receiving, from a host, a read command for a set of data at a memory device;
determining that the set of data is absent from a buffer within the memory device; and
sending, to the host, an indication of a time delay for the host to observe before issuing a subsequent access command based at least in part on the set of data being absent from the buffer, wherein sending the indication of the time delay for the host to observe comprises transmitting one or more pulses on a pin of the memory device.

US Pat. No. 10,714,158

TWO-STEP DATA-LINE PRECHARGE SCHEME

Micron Technology, Inc., ...

1. A system comprising:a memory device comprising:
first and second bit lines;
a first transistor configured to selectively apply a voltage reference to the first bit line in response to a control signal;
a second transistor configured to selectively apply the voltage reference to the second bit line in response to the control signal; and
a control circuit configured to supply the control signal to the first and second transistors, the control circuit comprising:
a third transistor configured to selectively apply a first voltage to gates of the first and second transistors as the control signal in response to a first command signal at a first time; and
a fourth transistor configured to selectively apply a second voltage higher than the first voltage to the gates of the first and second transistors as the control signal in response to a second command signal at a second time following the first time to reduce a precharge time of the first and second bit lines,
wherein the second voltage is greater than gate oxide withstand voltages of the first and second transistors.

US Pat. No. 10,714,154

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR DEVICE

RENESAS ELELCTRONICS CORP...

1. A semiconductor device, comprising:an external power supply terminal to be coupled to an external power supply;
a plurality of bit line pairs to be coupled with memory cells;
a plurality of sense amplifier circuits with which the bit line pairs are respectively provided;
a shared source line on a high potential side and a shared source line on a low potential side to be coupled with the sense amplifier circuits; and
a sense amplifier driver circuit to supply a potential to the shared source line on the high potential side,
wherein the sense amplifier driver circuit includes an NMOS transistor having a drain coupled to the external power supply terminal and a source coupled to the shared source line on the high potential side and a first PMOS transistor having a source coupled to a first potential point with a first potential lower than the external potential supplied from the external power supply terminal and a drain coupled to the shared source line on the high potential side, and
wherein the first potential is a power supply potential of the sense amplifier circuit.

US Pat. No. 10,714,153

REVERSED BIAS COMPENSATION FOR SENSE AMPLIFIER OPERATION

Micron Technology, Inc., ...

1. An apparatus comprising:a flip-flop circuit comprising a first transistor and a second transistor; and
a biasing circuit coupled to a first gate of the first transistor and a second gate of the second transistor, wherein the biasing circuit is configured to:
couple the second gate of the second transistor to a first signal line and the first gate of the first transistor to a second signal line in a first configuration; and
couple the first gate of the first transistor and the second gate of the second transistor to a first voltage line in a second configuration.

US Pat. No. 10,714,151

LAYERED SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREFOR

ULTRAMEMORY INC., Tokyo ...

1. A layered semiconductor wafer comprising, layered therein:a plurality of semiconductor wafers each including a semiconductor chip;
a reserve semiconductor wafer including a reserve semiconductor chip which is used as a reserve for the semiconductor chip; and
a control wafer including a control chip which includes a storage unit and controls operating states of the plurality of semiconductor chips and an operating state of the reserve semiconductor chip on a basis of information stored in the storage unit,
wherein information, which is related to a defected semiconductor chip among the plurality of the semiconductor wafers including the semiconductor chip and the reserve semiconductor wafer including the reserve semiconductor chip, is stored in the storage unit of the control chip overlapped to the defective semiconductor chip in the control wafer.

US Pat. No. 10,714,150

FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY

Micron Technology, Inc., ...

1. A memory system, comprising:multiple DRAM memory die stacked above a substrate,
wherein each die includes multiple partitions which operate independently from other partitions, and
wherein multiple vertically interconnected partitions of the stack are interconnected to form multiple respective memory vaults; and
a controller supported by the substrate and configured to interface with a first memory vault through a first group of data interface contacts, to interface with the second memory vault through a second group of data interface contacts, and to interface with at least the first and second memory vaults through a shared group of command interface contacts.

US Pat. No. 10,714,149

SEMICONDUCTOR PACKAGE WITH CLOCK SHARING AND ELECTRONIC SYSTEM INCLUDING THE SAME

Samsung Electronics Co., ...

1. A semiconductor package comprising:a lower package including a lower package substrate and a memory controller on the lower package substrate;
an upper package stacked on the lower package, the upper package including an upper package substrate and a memory device on the upper package substrate; and
a plurality of vertical interconnections electrically connecting the lower package to the upper package,
wherein the semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, and branch the first data clock signal into n ways such that the first data clock signal is provided to corresponding n pads of the memory device, where n is a natural number that is equal to or greater than 2.

US Pat. No. 10,714,146

RECORDING DEVICE, RECORDING METHOD, REPRODUCING DEVICE, REPRODUCING METHOD, AND RECORDING/REPRODUCING DEVICE

SONY CORPORATION, Tokyo ...

1. A recording device comprising:an image/audio recording unit for adding a time code to moving image data obtained by imaging a state in which a person who writes a description is explaining while writing a description in a description portion, and audio data corresponding to the moving image data to record the data in a recording unit; and
an index-image recording unit for processing the moving image data, determining a written portion in the description portion, generating index image data for displaying, as an index description, portions determined as the written portion, and recording the index image data in a recording unit,
wherein, to the index image data, a value of the time code corresponding to description time is added as a timestamp, in association with pixels constituting the index description.

US Pat. No. 10,714,136

ALTERNATIVE DESIGNS FOR MAGNETIC RECORDING ASSISTED BY TWO SPIN HALL EFFECT (SHE) LAYERS IN THE WRITE GAP

Headway Technologies, Inc...

1. A Spin Hall Effect (SHE) assisted magnetic recording (SHAMR) structure, comprising:(a) a main pole (MP) configured to generate a magnetic write field in a MP tip with a front side at an air bearing surface (ABS), and having a local magnetization that is proximate to a MP trailing side and substantially in a direction of a write gap (WG) flux field across an adjoining WG and between the MP tip across and a trailing shield;
(b) the trailing shield (TS) with a front side at the ABS, and a local magnetization proximate to a bottom surface that faces the MP, and substantially in a direction of the WG flux field; and
(c) a first Spin Hall Effect layer (SHE1) formed in the WG and on the MP trailing side, and having a top surface adjoining an insulation layer, and comprised of a Spin Hall Angle (SHA) material, wherein the SHE1 is configured to generate a first transverse spin transfer torque that tilts the local MP magnetization to a direction that is more parallel to the MP write field thereby enhancing the MP write field when a first current (I1) is applied between the MP trailing side and SHE1;
(d) the insulation layer; and
(e) a second Spin Hall Effect layer (SHE2) formed on the insulation layer and having a top surface that contacts the TS bottom surface, and comprised of a SHA material, wherein the SHE2 is configured to generate a second transverse spin transfer torque that tilts the local TS magnetization to a direction that is more orthogonal to the ABS to increase a TS return field when a second current (I2) is applied between the TS and SHE2.

US Pat. No. 10,714,135

AIR-BEARING SURFACE DESIGNS WITH A CURVED TRAILING AIR FLOW DAM

Western Digital Technolog...

1. A slider, comprising:a leading edge having a first end and a second end;
a trailing edge having a first end and a second end;
an outer-diameter edge extending between the first end of the leading edge and the first end of the trailing edge;
an inner-diameter edge extending between the second end of the leading edge and the second end of the trailing edge;
an outer-diameter trailing air flow dam; and
an inner-diameter trailing air flow dam,
wherein, in an air-bearing surface (ABS) view of the slider:
at least a portion of the outer-diameter trailing air flow dam extends in a first direction from a trailing edge pad toward the outer-diameter edge,
wherein the first direction is not parallel to the trailing edge, and
at least a portion of the inner-diameter trailing air flow dam extends in a second direction from the trailing edge pad toward the inner-diameter edge, wherein the second direction is not parallel to the trailing edge.

US Pat. No. 10,714,134

APPROXIMATED PARAMETER ADAPTATION

Seagate Technology LLC, ...

12. A method comprising:producing, by a circuit including a Soft-Output Viterbi Algorithm (SOVA) detector configured to process an input signal using a selected set of channel parameters and using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the selected set of channel parameters as branch biases of the SOVA detector to perform processing of the input signal;
approximating a second set of channel parameters of a second adaptation algorithm for use by the circuit as the selected set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm;
processing the input signal using the second set of channel parameters as the selected set of channel parameters; and
the first adaptation algorithm being a minimum mean squared error (MMSE) adaptation algorithm and the second adaptation algorithm being a Minimum Bit-Error Rate (MBER) adaptation algorithm.

US Pat. No. 10,714,133

DATA STORAGE DEVICE CAPABLE OF OVERRIDING A SERVO COMMAND TO AVOID AN OVERCURRENT CONDITION

Western Digital Technolog...

1. A data storage device comprising:a disk;
a head;
a first actuator configured to actuate the head over the disk;
a second actuator configured to rotate the disk;
a first control circuit configured to generate a servo command; and
a second control circuit configured to:
receive the servo command from the first control circuit;
control the first actuator or the second actuator using the servo command; and
override the servo command to avoid an overcurrent condition.

US Pat. No. 10,714,132

MAGNETIC FLUX GUIDING DEVICES ALL AROUND MAIN POLE DESIGN WITHOUT LEADING SHIELD AND SIDE SHIELDS IN ASSISTED WRITING APPLICATIONS

Headway Technologies, Inc...

1. A perpendicular magnetic recording (PMR) writer, comprising:(a) a main pole (MP) having a pole tip with a leading side and a trailing side, the leading side adjoins a lead gap (LG) at an air bearing surface (ABS), and the trailing side has a track width and adjoins a write gap (WG) at the ABS, and the MP trailing side at the ABS is at a first plane that is orthogonal to the ABS;
(b) a side gap (SG) which contacts a side of the MP tip formed between the trailing side and leading side on each side of a center plane that bisects the MP tip in a direction orthogonal to the ABS and the first plane;
(c) a shield structure comprising a first trailing shield (TS) on the WG, and a second TS on the first TS and contacting the first plane on portions thereof proximate to a WG side on each side of the center plane; and
(d) a flux guiding (FG) device that is formed in each of the WG, SG, and LG and known as FGWG, FGSG, and FGLG, respectively, and wherein each of the FG devices comprises a flux guiding layer (FGL) and is configured so that a FGL magnetization in FGWG, FGSG, and FGLG flips to a direction substantially opposing a flux field in the WG, SG, and LG, respectively, when a current (Ib) of sufficient current density is applied across the WG, SG, and LG so that reluctance is increased in each of the WG, SG, and LG thereby enhancing a write field from the MP tip on a magnetic medium; and
(e) at least one of a first non-magnetic conductor (NMC1) with an inner side that adjoins a side of the FGLG that faces away from the MP leading side, and a second non-magnetic conductor (NMC2) with an inner side that adjoins a side of each FGSG that faces away from a MP tip side, and wherein NMC1 is configured to enable the current Ib to flow across the LG, and wherein NMC2 is configured to enable the current Ib to flow across each SG.

US Pat. No. 10,714,129

WRITER WITH RECESSED SPIN FLIPPING ELEMENT IN THE MAIN POLE SURROUNDING GAP

Headway Technologies, Inc...

1. A microwave assisted magnetic recording (MAMR) writer, comprising:(a) a main pole (MP) with a leading side and a trailing side, the leading side adjoins a leading gap at an air bearing surface (ABS), and the trailing side has a track width and adjoins a write gap at the ABS;
(b) a side gap which contacts a side of the main pole formed between the trailing side and leading side on each side of a center plane that is equidistant from each main pole side;
(c) the leading gap that adjoins a bottom portion of each side gap and contacts the leading side of the main pole;
(d) a shield structure comprising a first trailing shield (TS) that is a hot seed (HS) layer on the write gap, a side shield contacting each side gap, and a leading shield adjoining a bottom surface of the leading gap; and
(e) a first spin torque oscillator (STO) formed in at least each side gap, and wherein each first STO is recessed a first height from the ABS, and comprises:
(1) an inner non-spin preserving layer that contacts the main pole;
(2) a middle flux guiding layer (FGL) configured to have a magnetization that is driven into a precessional state when a current Ib of sufficient magnitude is applied in a direction from the shield structure towards the main pole, the precessional state is responsible for a reduction in magnetic flux between at least the MP and the side shields; and
(3) an outer spin preserving layer on an opposite side of the FGL with respect to the inner non-spin preserving layer.

US Pat. No. 10,714,128

MAGNETIC WRITE HEAD WITH DUAL RETURN POLE

Western Digital Technolog...

1. A heat-assisted magnetic recording (HAMR) write head, comprising:an air-bearing surface (ABS);
a main pole extending to the ABS;
a first return pole extending to the ABS and disposed, at the ABS, between the main pole and a leading side of the magnetic write head;
a waveguide extending to the ABS and disposed, at the ABS, between the first return pole and the main pole;
a near-field transducer extending to the ABS and disposed, at the ABS, between the waveguide and the main pole; and
a second return pole disposed between the main pole and a trailing side of the magnetic write head, wherein the second return pole comprises a tapered portion adjacent to the ABS, wherein the tapered portion extends in a direction toward the main pole, and wherein a distance between the main pole and the second return pole is between approximately 600 nm and approximately 1000 nm.

US Pat. No. 10,714,126

MAGNETIC RECORDING HEAD AND DISK DEVICE INCLUDING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetic recording head comprising:a slider having an air bearing surface that faces a surface of a recording medium;
a main magnetic pole including a fore-end portion that extends towards the air bearing surface and configured to generate recording magnetic fields in a first direction that is perpendicular to the surface of the recording medium;
a write shield magnetic pole located across from the fore-end portion of the main magnetic pole to form a write gap that extends therebetween in a second direction and forming a magnetic core in conjunction with the main magnetic pole;
a coil configured to excite a magnetic flux in the magnetic core;
first and second spin-torque oscillators in the write gap and arranged along a third direction with a spacing therebetween, wherein the third direction is parallel to the surface of the recording medium and perpendicular to the first direction;
an insulating layer inside the write gap between the first and second spin-torque oscillators; and
a current circuit electrically connected to the first and second spin-torque oscillators via the main magnetic pole and the write shield magnetic pole and configured to supply current to oscillate one of the first and second spin-torque oscillators, wherein
the first spin-torque oscillator includes
a first conductive layer formed from a non-magnetic metal,
a first magnetic flux control layer formed from a magnetic metal and provided on the first conductive layer, and
a second conductive layer formed from a non-magnetic metal and provided between the first magnetic flux control layer and the write shield magnetic pole, and
the second spin-torque oscillator includes
a third conductive layer formed from a non-magnetic metal,
a second magnetic flux control layer formed from a magnetic metal and provided on the third conductive layer, and
a fourth conductive layer formed from a non-magnetic metal and provided between the second magnetic flux control layer and the fore-end portion of the main magnetic pole.

US Pat. No. 10,714,125

METHOD OF MANUFACTURING A MAGNETIC RECORDING HEAD

SANDISK TECHNOLOGIES LLC,...

1. A method of manufacturing a magnetic recording head, comprising:forming a side shield template structure;
forming a main pole recess region in the side shield template structure;
forming a non-magnetic gap material layer in the main pole recess region;
forming a main pole over the non-magnetic gap material layer; and
replacing the side shield template structure with a side shield.

US Pat. No. 10,714,124

STORAGE DEVICE AND STORAGE METHOD

TOSHIBA MEMORY CORPORATIO...

1. A storage device comprising:a selection circuit that selects one mapping rule from a plurality of mapping rules in which each of bit labels having a bit length of (n+1) or more is mapped to n M-ary symbols, when M is defined as an integer of 3 or more and n is defined as an integer of 2 or more;
a first conversion circuit that converts a data block in data into an M-ary symbol sequence using the selected one mapping rule;
a second conversion circuit that converts the converted M-ary symbol sequence into an M-step pulse width signal;
a recording medium that records converted M-step pulse width signal; and
a readback circuit that equalizes the signal read from the recording medium to the M-ary symbol sequence and restores the data.

US Pat. No. 10,714,121

DISTINGUISHING USER SPEECH FROM BACKGROUND SPEECH IN SPEECH-DENSE ENVIRONMENTS

VOCOLLECT, INC., Pittsbu...

1. A method of speech recognition, the method comprising:receiving at a microphone of a speech recognition device (SRD) an audio input;
identifying, via a hardware processor of the SRD which is communicatively coupled with the microphone, a vocalization of a human language in the received audio input; and
categorizing, via the hardware processor, the received vocalization of a human language, based on a speech difference between the received vocalization of human language and an audio mix which is stored in a memory of the SRD, the memory communicatively coupled with the hardware processor, as either one of:
a first vocalization originating from a user of the SRD in response to determining that an absolute value of the speech difference is less than a speech rejection threshold stored in the memory; or
a second vocalization originating from a background, in response to determining that the absolute value of the speech difference is greater than the speech rejection threshold, wherein the background speech is a non-user background speech in the vicinity of the SRD or a background environmental sound.

US Pat. No. 10,714,120

MULTISENSORY SPEECH DETECTION

Google LLC, Mountain Vie...

1. A method comprising:detecting, by data processing hardware of a mobile device, movement of the mobile device from a first pose to a second pose, the second pose corresponding to the mobile device in a talking pose proximate to a part of a user of the mobile device;
in response to detecting the movement of the mobile device from the first pose to the second pose:
initiating, by the data processing hardware, execution of an audio recording process using a microphone of the mobile device; and
notifying, by the data processing hardware, the user of the mobile device when execution of the audio recording process starts by:
generating a visual notification that indicates to the user when execution of the audio recording process starts; and
displaying the visual notification on a user interface of the mobile device, wherein the visual notification comprises a microphone graphic;
receiving, at the data processing hardware, a speech utterance of the user captured by the microphone during execution of the audio recording process; and
generating, by the data processing hardware, a transcription of the speech utterance captured by the microphone during the audio recording process.

US Pat. No. 10,714,119

COMMUNICATION DEVICE AND COMMUNICATION SYSTEM

Plantronics, Inc., Santa...

1. A communication device for a communication system, the communication device having at leastan I/O interface for connection with one or more audio sources to at least receive an input audio signal;
a user audio output;
an audio processor to provide an output audio signal to the user audio output from the input audio signal; and
a reporting module, configured to analyze the input audio signal and to determine, whether at least one acoustic safety incident is given, upon which the reporting module is configured to generate metadata of the acoustic safety incident wherein
the reporting module is further configured to capture an input audio snippet of the input audio signal upon determination of the acoustic safety incident.

US Pat. No. 10,714,118

AUDIO COMPRESSION USING AN ARTIFICIAL NEURAL NETWORK

Facebook, Inc., Menlo Pa...

1. A method comprising:by a first client computing device, establishing a communication session to a second client computing device;
by the first client computing device, accessing a first audio signal;
by the first client computing device, compressing the first audio signal using a compression portion of a first artificial neural network particularly trained to compress a first user's voice using one or more voice signals of the first user, wherein:
the first artificial neural network is generated during the communication session when an artificial neural network customized to the first user is unavailable;
the first artificial neural network comprises an input layer, a middle layer, and an output layer;
the compression portion of the first artificial neural network comprises all layers of the first artificial neural network between the input layer of the first artificial neural network and the middle layer of the first artificial neural network, inclusive;
each layer of the first artificial neural network comprises one or more nodes;
the middle layer of the first artificial neural network comprises fewer nodes than any other layer of the first artificial neural network; and
a first compressed audio signal based on the first audio signal comprises an output of the middle layer of the first artificial neural network;
by the first client computing device, sending the first compressed audio signal to the second client computing device, wherein:
a decompression portion of the first artificial neural network is stored on the second client computing device, wherein, when the first artificial neural network was generated during the communication session, the decompression portion of the first artificial neural network is sent to the second client computing device during the communication session; and
the decompression portion of the first artificial neural network stored on the second client computing device comprises all layers of the first artificial neural network between the middle layer of the first artificial neural network and the output layer of the first artificial neural network, inclusive;
by the first client computing device, receiving from the second client computing device a second compressed audio signal, wherein the second compressed audio signal was compressed using a compression portion of a second artificial neural network separately trained to compress a second user's voice using one or more voice signals of the second user; and
by the first client computing device, decompressing the second compressed audio signal using a decompression portion of the second artificial neural network stored on the first client computing device, wherein:
the second artificial neural network comprises an input layer, a middle layer, and an output layer;
the decompression portion of the second artificial neural network comprises all layers of the second artificial neural network between the middle layer of the second artificial neural network and the output layer of the second artificial neural network, inclusive;
each layer of the second artificial neural network comprises one or more nodes;
the middle layer of the second artificial neural network comprises fewer nodes than any other layer of the second artificial neural network; and
a decompressed audio signal based on a second audio signal comprises an output of the output layer of the second artificial neural network.

US Pat. No. 10,714,115

DYNAMIC PLAYER SELECTION FOR AUDIO SIGNAL PROCESSING

Sonos, Inc., Santa Barba...

1. A media system comprising a first playback device and a second playback device, the media system comprising:the first playback device comprising:
one or more microphones;
a network interface;
a processor;
a non-transitory computer-readable medium;
program instructions stored on the non-transitory computer-readable medium that, when executed by the processor, cause the first playback device to perform functions comprising:
receiving an indication of an available amount of computational power of the second playback device; and
based on the received indication of the available amount of computational power of the second playback device, sending, to the second playback device, a set of audio signals received by the one or more microphones of the first playback device, wherein the set of audio signals includes at least one voice input;
the second playback device comprising:
a network interface;
a processor;
a non-transitory computer-readable medium;
program instructions stored on the non-transitory computer-readable medium that, when executed by the processor, cause the second playback device to perform functions comprising:
receiving, from the first playback device, the set of audio signals received by the one or more microphones of the first playback device;
processing the set of audio signals using a first set of audio processing algorithms to determine a set of signal measures corresponding to the set of audio signals;
based on the set of signal measures, identifying, from the set of audio signals, at least two audio signals that are to be re-processed using a second set of audio processing algorithms so as to improve the respective signal measures of the at least two audio signals;
re-processing the at least two audio signals using the second set of audio processing algorithms;
combining the re-processed at least two audio signals into a combined audio signal; and
sending the combined audio signal to a network device.

US Pat. No. 10,714,113

AUDIO DECODING DEVICE, AUDIO CODING DEVICE, AUDIO DECODING METHOD, AUDIO CODING METHOD, AUDIO DECODING PROGRAM, AND AUDIO CODING PROGRAM

NTT DOCOMO, INC., Tokyo ...

1. A speech decoding device that decodes an encoded speech signal and outputs a speech signal, the speech decoding device comprising:a low frequency decoder that receives and decodes a code sequence including encoded information of a low frequency signal to obtain the low frequency signal;
a high frequency decoder that receives first information from the low frequency decoder and generates a high frequency signal based on the first information;
a high frequency temporal envelope shape determiner that determines a temporal envelope shape of the generated high frequency signal based on second information sent from an encoding device;
a high frequency temporal envelope modifier that modifies the temporal envelope shape of the generated high frequency signal based on the temporal envelope shape determined by the high frequency temporal envelope shape determiner and outputs the modified high frequency signal; and
a low frequency/high frequency signal combiner that receives the low frequency signal from the low frequency decoder, receives the high frequency signal, whose temporal envelope shape is modified, from the high frequency temporal envelope modifier and combines the low frequency signal and the high frequency signal, whose temporal envelope shape is modified, to obtain a speech signal to be output,
wherein the high frequency temporal envelope modifier modifies the temporal envelope shape of the generated high frequency signal using a high frequency signal generated in a time segment identical to that of the generated high frequency signal and outputs the modified high frequency signal, when the high frequency temporal envelope shape determiner determines the temporal envelope shape to be flat, and utilizes time envelope information of a high frequency signal determined by power of the high frequency signal generated by the high frequency decoder, during decoding of an encoded speech signal and obtaining of a speech signal.

US Pat. No. 10,714,112

METHOD AND APPARATUS FOR DECODING A BITSTREAM INCLUDING ENCODED HIGHER ORDER AMBISONICS REPRESENTATIONS

Dolby Laboratories Licens...

1. A method for decoding a bitstream that includes encoded HOA representations, said method comprising:evaluating a value of a bit KindOfCodedPredIds;
evaluating, based on the value of the bit KindOfCodedPredIds, a first array ActivePred, wherein each element of the first array ActivePred indicates if, for a corresponding direction, a prediction is performed;
determining, based on the evaluation of the first array ActivePred, elements of a vector ptype;
evaluating a second array PredDirSigIds, wherein elements of the second array PredDirSigIds denote indices of directional signals to be used for active predictions, wherein the evaluation is based on a variable NumActivePred; and
determining, based on the vector Ptype and the elements of the second array PredDirSigIds, elements of a matrix PEND denoting indices from which directional signals of a prediction for a direction is to be performed.

US Pat. No. 10,714,111

ENHANCED ADAPTIVE AUDIO RENDERING TECHNIQUES

Microsoft Technology Lice...

1. A computing device, comprising:a processor;
a computer-readable storage medium in communication with the processor, the computer-readable storage medium having computer-executable instructions stored thereupon which, when executed by the processor, cause the processor to:
receive contextual data indicating a number of audio objects associated with capabilities of an encoder in communication with the computing device;
select a spatialization technology from a plurality of spatialization technologies, wherein individual spatialization technologies of the plurality of spatialization technologies are each associated with a threshold number of audio objects, wherein the selected spatialization technology is associated with the threshold number of objects that correlates with the number of audio objects associated with capabilities of the encoder;
cause the encoder to generate a rendered output signal based on an input signal comprising object-based audio and channel-based audio processed by the selected spatialization technology; and
cause a communication of the rendered output signal from the encoder to one or more speakers of an endpoint device.

US Pat. No. 10,714,109

METHODS AND APPARATUS FOR BUFFERING AND COMPRESSION OF DATA

Cirrus Logic, Inc., Aust...

1. A device, comprising:an allocation module, for determining one or more metrics of each of a plurality of data streams;
a compression module, for compressing each of the plurality of data streams and generating a plurality of compressed data streams, the compression module applying a compression ratio that varies as a function of the metrics determined by the allocation module; and
a buffer memory, for storing the plurality of compressed data streams, wherein the buffer memory comprises Y rows, each row being X bits wide, wherein X and Y are integers, and wherein data values stored in each row correspond to samples of said plurality of data streams acquired at an instance in time, wherein the compression ratios for each of the plurality of data streams are selected such that a row of the buffer memory is fully occupied with samples of said plurality of data streams acquired at an instance in time.

US Pat. No. 10,714,107

LINEAR PREDICTION COEFFICIENT CONVERSION DEVICE AND LINEAR PREDICTION COEFFICIENT CONVERSION METHOD

NTT DOCOMO, INC., Tokyo ...

1. A linear prediction coefficient conversion device that converts first linear prediction coefficients calculated at a first sampling frequency F1 to second linear prediction coefficients at a second sampling frequency F2 (where F1 calculate, on the real axis of the unit circle, autocorrelation coefficients from the power spectrum; and
convert the autocorrelation coefficients to the second linear prediction coefficients at the second sampling frequency.

US Pat. No. 10,714,106

JITTER BUFFER CONTROL, AUDIO DECODER, METHOD AND COMPUTER PROGRAM

Fraunhofer-Gesellschaft z...

1. A jitter buffer control for controlling a provision of a decoded audio content on the basis of an input audio content,wherein the jitter buffer control is configured to select a frame-based time scaling or a sample-based time scaling in a signal-adaptive manner, such that a decision whether a frame-based time scaling or a sample-based time scaling is used is adapted to the characteristics of the audio signal, and
wherein the jitter buffer control is implemented using a hardware apparatus, or using a computer, or using a combination of a hardware apparatus and a computer.

US Pat. No. 10,714,105

AUDIO FINGERPRINTING

Gracenote, Inc., Emeryvi...

1. An apparatus comprising:a vector generator to:
determine first and second groups of frequencies in a plurality of frequencies from spectral data derived from audio data, the first group including frequencies different from frequencies in the second group of frequencies, each of the frequencies of the first group being higher than each of the frequencies in the second group,
identify a first subgroup of frequencies in the first group of frequencies based on energy values of the first group, each of the frequencies of the first subgroup having energy values that are greater than energy values of other frequencies in the first group,
identify a second subgroup of frequencies in the second group of frequencies based on energy values of the second group, each of the frequencies of the second subgroup having energy values that are greater than energy values of other frequencies in the second group, and
generate a vector that assigns a first value to the frequencies in the first subgroup and assigns a second value to the frequencies in the second subgroup;
a scrambler to generate permutations of the vector, the permutations differently arranging instances of the first and second values;
a coder to generate a sequence that indicates an instance of the first value or of the second value within a corresponding permutation of the permutations; and
a fingerprint generator to generate a fingerprint of the audio data based on the sequence, wherein the generation and decoding of the fingerprint is to conserve computing resources.

US Pat. No. 10,714,103

APPARATUS FOR ENCODING AND DECODING OF INTEGRATED SPEECH AND AUDIO

ELECTRONICS AND TELECOMMU...

1. An encoding method of an input signal performed by at least one processor, the encoding method comprising:determining a frame of the input signal whether the frame is a speech frame or an audio frame;
encoding the core band of the input signal in a speech encoder based CELP coding scheme when the frame is the speech frame, and
encoding the core band of the input signal in an audio encoder based MDCT coding scheme when the frame is the audio frame; and
generating a bitstream including the encoded core band of the input signal,
wherein the core band is a low frequency band which is not expanded in a frequency band of the input signal,
wherein a high frequency band is generated from the core band based on a frequency band expander in a decoding process, and
wherein the input signal is processed by using information for compensating a change of a frame unit between the speech frame and the audio frame when a switching occurs between the speech frame and the audio frame in a decoding process about the input signal.

US Pat. No. 10,714,101

TARGET SAMPLE GENERATION

Qualcomm Incorporated, S...

1. A device comprising:an encoder configured to:
identify a target channel and a reference channel based on a channel mismatch value;
generate a modified target channel based on the channel mismatch value and the target channel;
determine a temporal correlation value indicative of a temporal correlation between a first signal associated with the reference channel and a second signal associated with the modified target channel;
compare the temporal correlation value to a threshold; and
generate, based on the comparison, missing target samples of a target frame of the modified target channel using a target frame based on the modified target channel, wherein the first signal corresponds to a portion of the reference frame, and wherein the second signal corresponds to a portion of the target frame, and wherein the missing target samples of the target frame of the modified target channel are generated based on random noise filtered from a past set of samples of the modified target channel in response to the determination that the temporal correlation value fails to satisfy the threshold.

US Pat. No. 10,714,100

AUDIO SIGNAL DECODING

Qualcomm Incorporated, S...

1. An apparatus comprising:a receiver configured to receive at least one encoded signal that includes one or more inter-channel bandwidth extension (BWE) parameters; and
a decoder configured to:
generate a mid channel time-domain high-band signal by performing bandwidth extension based on the at least one encoded signal;
generate, based on the mid channel time-domain high-band signal and the one or more inter-channel BWE parameters, a first channel time-domain high-band signal and a second channel time-domain high-band signal, wherein the first channel time-domain high-band signal is generated selectively based on an adjustment spectral shape parameter responsive to whether the one or more inter-channel BWE parameters include the adjustment spectral shape parameter;
generate a target channel signal based at least in part on the first channel time-domain high-band signal; and
generate a reference channel signal based at least in part on the second channel time-domain high-band signal.

US Pat. No. 10,714,098

SELECTIVE FORWARD ERROR CORRECTION FOR SPATIAL AUDIO CODECS

Dolby Laboratories Licens...

1. A method for providing forward error correction data for use when packets are lost in a multi-channel audio signal, the method comprising:buffering blocks of an audio stream into a frame of audio, the audio stream comprising a plurality of audio channels;
applying a transformation to each block of the frame of audio, the transformation compacting the energy of each block into a plurality of transformed channels, the first transformed channel for each block containing the most energy and subsequent transformed channels containing decreasing amounts of energy;
encoding the transformed frame;
transmitting, over a network, the encoded frame in a packet;
encoding the first transformed channel of the transformed frame at a lower bit rate than the encoding used for the transmitted packet; and
transmitting, over the network, the lower bit rate-encoded channel in a packet that is subsequent to the transmitted packet, wherein, when the lower bit rate-encoded channel is used as the forward error correction data to reconstruct a lost packet, the lower bit rate-encoded channel is combined with packet loss concealment versions of the subsequent transformed channels, the packet loss concealment versions being from a packet that is prior to the transmitted packet.

US Pat. No. 10,714,097

METHOD AND APPARATUS FOR CONCEALING FRAME ERROR AND METHOD AND APPARATUS FOR AUDIO DECODING

SAMSUNG ELECTRONICS CO., ...

1. A frame error concealment method comprising:when a current frame is classified as an error frame, performing a frequency domain error concealment processing on the current frame to generate spectral coefficients of the current frame;
generating a time domain signal of the current frame based on a time-frequency inverse transform; and
when the current frame is classified as the error frame or a next good frame after the error frame, performing a corresponding time domain error concealment processing on the time domain signal of the current frame by using a mode from among a plurality of modes including at least one mode associated with repetition and smoothing,
wherein the mode from among the plurality of modes is selected according to whether the current frame is stationary.

US Pat. No. 10,714,094

VOICEPRINT RECOGNITION MODEL CONSTRUCTION

Alibaba Group Holding Lim...

1. A computer-implemented method, comprising:receiving a first voice input from a user during a first session of the user interacting with a voice recognition system of a service system that implements a particular service with a corresponding security requirement;
obtaining one or more predetermined keywords wherein the one or more predetermined keywords include at least a minimum number of required keywords, the minimum number of required keywords being based on the corresponding security requirement for training a voiceprint recognition model;
searching the first voice input to determine whether the one or more predetermined keywords occur in the first voice input;
determining, from the first voice input, that the user spoke at least one of the one or more predetermined keywords during the first session of the user interacting with the voice recognition system of the service system;
in response to determining that the user spoke at least one of the one or more predetermined keywords during the first session of the user interacting with the voice recognition system of the service system, training the voiceprint recognition model based on one or more voice segments corresponding respectively to the one or more predetermined keywords;
receiving a second voice input from the user during a second session of the user interacting with the voice recognition system of the service system; and
responsive to obtaining, prior to receiving the second voice input, all of the required keywords based on the corresponding security requirement, verifying an identity of the user based on the second voice input received during the second session using the voiceprint recognition model generated from the one or more voice segments from the first session of the user interacting with the voice recognition system of the service system.

US Pat. No. 10,714,093

HOTWORD DETECTION ON MULTIPLE DEVICES

Google LLC, Mountain Vie...

1. A computer-implemented method comprising:receiving, by a first computing device, from a second computing device that is in a vicinity of the first computing device, data indicating that the second computing device is configured to respond to a particular, predefined hotword;
receiving, by the first computing device, audio data of an utterance that includes a particular, predefined hotword;
based on receiving, from the second computing device that is in the vicinity of the first computing device, the data indicating that the second computing device is configured to respond to the particular, predefined hotword, providing, to a third computing device, data indicating that the first computing device received the particular, predefined hotword, data indicating that the second computing device is in the vicinity of the first computing device, and the data indicating that the second computing device is configured to respond to the particular, predefined hotword; and
based on receiving, from the third computing device, an instruction to perform a command that follows the particular, predefined hotword, performing, by the first computing device, the command.

US Pat. No. 10,714,088

SPEECH RECOGNITION DEVICE AND METHOD OF IDENTIFYING SPEECH

HON HAI PRECISION INDUSTR...

1. A speech recognition device comprising:a speech acquiring unit configured to acquire speech input;
a speech outputting unit;
a camera unit configured to acquire images; and
a processor configured to:
obtain the speech input acquired by the speech acquiring unit;
obtain the images acquired by the camera unit and chronologically link the obtained speech and the obtained images together;
compare the obtained speech to a speech database to confirm matching speech and a confidence level of the matching speech, wherein the confidence level of the speech represents an accuracy of the matching speech to the obtained speech;
determine whether the confidence level of the matching speech exceeds a predetermined confidence level; and
output the matching speech when the confidence level of the matching speech exceeds the predetermined confidence level.

US Pat. No. 10,714,083

VOICE COMMANDS ACROSS DEVICES

Google LLC, Mountain Vie...

1. A computer-implemented method, the method comprising:receiving first voice input data from a first computing device associated with a user account, the first voice input data comprising a first voice command captured at the first computing device;
receiving second voice input data from a second computing device associated with the user account, the second voice input data comprising a second voice command captured at the second computing device;
determining an intended voice command based on the obtained first and second voice input data;
determining a first target computing device based on the intended voice command; and
providing first instructions associated with the intended voice command to the first target computing device for execution,
wherein determining the first target computing device is further based on a first comparison of commands available to the user on the first computing device and the intended voice command and a second comparison of commands available to the user on the second computing device and the intended voice command.

US Pat. No. 10,714,082

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM

SONY CORPORATION, Tokyo ...

1. An information processing apparatus comprising:an identifying portion that identifies a word uttered according to a predetermined utterance method, from within utterance information of a user, as an unknown word;
an image generating portion that generates an image that indicates whether an utterance by the user corresponds to the predetermined utterance method; and
a processing portion that performs processing to register the unknown word that has been identified,
wherein the image includes a threshold value image that displays a threshold value indicating to the user that the uttered word is identified as the unknown word when the predetermined utterance method is satisfied, and
wherein the identifying portion, the image generating portion, and the processing portion are each implemented via at least one processor.

US Pat. No. 10,714,079

METHODS AND SYSTEM FOR ANALYZING CONVERSATIONAL STATEMENTS AND PROVIDING FEEDBACK IN REAL-TIME

MOTOROLA SOLUTIONS, INC.,...

2. A method for analyzing conversational statements and providing feedback in real-time, the method comprising:receiving, by a natural-language electronic processing device, audio stream data including a natural-language statement recorded by a communication device;
converting, by a natural-language electronic processing device, the natural-language statement into a logical analysis format representation;
performing, by a natural-language electronic processing device, an automatic logical analysis on the logical analysis format representation of the natural-language statement to identify one or more candidate output resolutions and identify supplemental data that can confirm the one or more candidate output resolutions,
wherein each candidate output resolution of the one or more candidate output resolutions relates to an assessment of a factual accuracy of the natural-language statement;
accessing, by a natural-language electronic processing device, the identified supplemental data and evaluating the one or more candidate output resolutions based at least in part on the supplemental data;
eliminating at least one of the one or more candidate output resolutions based at least in part on the supplemental data;
identifying a plurality of candidate output resolutions that are not eliminated after evaluating the one or more possible output resolutions based at least in part on the supplemental data;
generating a formula identifying a criteria that will differentiate between the plurality of candidate output resolutions that are not eliminated;
generating, by a natural-language electronic processing device, a feedback message to be output by the communication device, the feedback message being indicative of the evaluation of the one or more candidate output resolutions, by converting the generated formula into a natural-language feedback message;
transmitting the natural-language feedback message as a recommended follow-up question to be displayed on the communication device;
monitoring the received audio stream data for a second natural-language statement responding to the natural-language feedback message; and
further evaluating the plurality of candidate output resolutions based on the second natural-language statement.

US Pat. No. 10,714,076

INITIALIZATION OF CTC SPEECH RECOGNITION WITH STANDARD HMM

Sony Interactive Entertai...

1. A method for improved initialization of speech recognition systems, the method comprising;a) mapping a central state of each frame in a trained Hidden Markov Model (HMM) to Connectionist Temporal Classification (CTC) labeled nodes and mapping one or more non-central states of each frame to CTC-blank nodes to generate a CTC-labeled HMM, wherein each central state represents a phoneme, wherein mapping consists of either generation of a new node network model with identical connections and transition weights as a previous model but new labels or relabeling an existing node network model with new labels;
b) training the CTC-labeled HMM using a cost function wherein the cost function is not part of a CTC cost function;
c) training the CTC-labeled HMM using a CTC cost function to produce a CTC node Deep Learning Neural network; and
d) generating new frame and label information from the CTC-node network.

US Pat. No. 10,714,075

LANGUAGE MODEL BIASING MODULATION

Google LLC, Mountain Vie...

1. A computer-implemented method comprising:receiving, by an automated speech recognizer (ASR) that is configured to use a language model that has previously been biased for use in transcribing utterances, audio data corresponding to an utterance;
determining that, when the audio data was received, a particular context that is associated with biasing the language model was still applicable;
in response to determining that the particular context that is associated with biasing the language mode was still applicable when the audio data was received, generating, by the ASR, a transcription of the utterance using the language model that has previously been biased for use in transcribing utterances; and
providing a representation of the transcription for output.

US Pat. No. 10,714,068

MOUTHPIECE WITH WHISTLING MECHANISM

David Hopson, Cypress, T...

1. An apparatus, wherein:the apparatus is curved in top view, has a U-shape in side cross-section, and comprises a first side portion, a bottom portion, and a second side portion, wherein the first side portion and the second side portion are configured to fit upper teeth of a human being with the first side portion being on an outer curve of the curve in top view and the second side portion being on an inner curve of the curve in top view;
wherein the first side portion has an outer face and the outer face comprises at least one decorative member;
wherein the bottom portion comprises at least one slot that is capable of producing a whistling sound when air passes through said slot, wherein said slot has an inlet opening at a back of the bottom portion adjacent the second side portion and an outlet opening at a front of the bottom portion adjacent the first side portion or at a bottom side of the bottom portion;
wherein said outer face is substantially vertical from a top of said first side portion to a top of said bottom portion;
wherein said bottom side of said bottom portion is substantially perpendicular to said outer face; and
wherein said apparatus is configured to be fully contained within a mouth of said human being when the U-shape is fitted over said upper teeth of said human being.

US Pat. No. 10,714,066

CONTENT CONTROL DEVICE AND STORAGE MEDIUM

YAMAHA CORPORATION, Hama...

1. A content control device comprising:a plurality of controls respectively assigned to a plurality of parameters for controlling properties of a content containing sound, each of the plurality of controls outputting a first indicated value in accordance with an operation amount of the respective control; and
a processor configured to:
obtain a second indicated value;
acquire predetermined setting information for determining a range of each of the respective first indicated values of the plurality of parameters; and
set the respective first indicated values of the plurality of parameters in accordance with the second indicated value and the setting information to control the properties of the content.

US Pat. No. 10,714,063

DRUMHEAD TUNING RIM SYSTEM AND METHOD OF USE

Bedson Drum Co., Edmonds...

1. A drumhead tuning rim system comprising at least one drumhead tuning rim apparatus for securing and tuning a drumhead on a drum shell of a drum, the drumhead tuning rim apparatus comprising:a cable tension dial assembly configured for operably engaging a rim of the drum so as to increase or decrease tension on the rim, the rim being configured for seating over the drumhead on the drum shell, the cable tension dial assembly comprising a rotatably installed take-up shaft;
a plurality of low friction lug assemblies configured to be installed spaced about the drum shell; and
a single continuous tensioning cable configured for alternately passing about the lug assemblies substantially about the drum shell and for winding about the take-up shaft for operably engaging the cable tension dial assembly so as to selectively raise or lower the overall pitch of the drumhead.

US Pat. No. 10,714,061

GO DRUM

1. A compact drum kit comprising:a multi-sided body having a hollow interior defined by an upper snare drum surface, a bottom, a kick drum surface and a sound hole;
a plurality of upward extending component mounting shafts mounted in the hollow interior of the body and protruding through a plurality of openings in the body;
a plurality of leg shafts mounted in the hollow interior of the body and protruding through at least one opening in the body;
one or more percussion modules that attach to one or more of the plurality of component mounting shafts, wherein each percussion module produces a sound in response to being struck or scraped; and
a kick pedal including a beater positioned to strike a first side of the three or more sides and produce a sound.

US Pat. No. 10,714,059

METHOD FOR MANUFACTURING PICKCATCHER SYSTEM

1. A method of manufacturing a pickcatcher device, comprising:manufacturing a circular tilted frame having an inner and outer diameter;
manufacturing a circular screen, also having an inner and outer diameter, to be inserted within the circular tilted frame in a non-movable snug-fit;
fabricating the circular tilted frame to have a circular string-facing surface and a circular instrument-facing surface, wherein an entirety of the circular string-facing surface is formed to be opposite to an entirety of the circular instrument-facing surface;
fabricating the entirety of the string-facing surface to be substantially flat and thus occupying a first plane;
fabricating the entirety of the instrument-facing surface to be substantially flat and thus occupying a second plane;
fabricating the circular tilted frame so that the first and second planes are tilted relative to each other and not parallel;
preparing the instrument-facing surface of the circular tilted frame to be suitable for attachment to a surface of an instrument;
fabricating the circular tilted frame in a size suitable for insertion within and covering a top of a soundhole within the instrument; and
fabricating the circular screen to be suitable to fit within the instrument-facing surface of the circular tilted frame.

US Pat. No. 10,714,047

HEAD-MOUNTED DISPLAY DEVICE AND METHOD OF CHANGING LIGHT TRANSMITTANCE OF THE SAME

Samsung Electronics Co., ...

1. A method of changing a light transmittance of a head-mounted display device including a display and an optical lens, the method comprising:identifying an application displayed on the display of the head-mounted display device in front of a portion of the optical lens;
identifying a first light transmittance based on a type of the application or a type of a content of the application;
changing, by a processor, a light transmittance of the optical lens to the first light transmittance; and
displaying the content of the application on the display while the light transmittance of the optical lens is maintained in the first light transmittance.

US Pat. No. 10,714,044

GOA CIRCUIT AND DISPLAY DEVICE

1. A gate driver on array (GOA) circuit, comprising a plurality of cascaded sub-circuits, wherein an n-th sub-circuit of the sub-circuits comprises:a control module electrically connected to a positive scan control terminal, a negative scan control terminal, an (n?2)th scan terminal, an (n+2)th scan terminal, an (n+1)th clock terminal, an (n?1)th clock terminal, a high voltage terminal, and a low voltage terminal;
an output module electrically connected to the high voltage terminal, the low voltage terminal, an n-th clock terminal, an n-th scan terminal, and a controllable terminal;
a pull-up supplement module comprising a supplement switch and an auxiliary switch, wherein the supplement switch is electrically connected to the auxiliary switch, the high voltage terminal, the control module, and the output module, and the auxiliary switch is electrically connected to the supplement switch, the high voltage terminal, the control module, and the output module; and
a leakage switch electrically connected to the control module, the output module, the supplement switch, the auxiliary switch, and the low voltage terminal;
wherein the control module comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; wherein the first switch is electrically connected to the (n?2)th scan terminal, the positive scan control terminal, the second switch, the sixth switch, the supplement switch, and the auxiliary switch; wherein the second switch is electrically connected to the (n+2)th scan terminal, the negative scan control terminal, the first switch, the sixth switch, the supplement switch, and the auxiliary switch; wherein the third switch is electrically connected to the positive scan control terminal, the (n+1)th clock terminal, the fourth switch, and the fifth switch; wherein the fourth switch is electrically connected to the negative scan control terminal, the (n?1)th clock terminal, the third switch, and the fifth switch; wherein the fifth switch is electrically connected to the high voltage terminal, the third switch, the fourth switch, the sixth switch, the leakage switch, and the output module; and wherein the sixth switch is electrically connected to the low voltage terminal, the first switch, the second switch, the fifth switch, the supplement switch, the auxiliary switch, the output module, and the leakage switch; and
wherein the output module comprises a relay unit, a pull-up unit, a pull-down unit, a detection unit, a first energy storing element, and a second energy storing element; wherein the relay unit is electrically connected to the high voltage terminal, the supplement switch, the auxiliary switch, and the pull-up unit; wherein the relay unit, the supplement switch, and the auxiliary switch are commonly connected to form a first node; wherein the pull-up unit is electrically connected to the relay unit, the n-th clock terminal, and the n-th scan terminal; wherein the pull-down unit is electrically connected to the n-th scan terminal, the low voltage terminal, the leakage switch, and the control module; wherein the detection unit is electrically connected to the n-th scan terminal, the low voltage terminal, the controllable terminal, the pull-down unit, the leakage switch, and the control module; wherein the pull-down unit, the detection unit, the leakage switch, and the control module are commonly connected to a second node; wherein the first energy storing element is electrically connected between the first node and the low voltage terminal; and wherein the second energy storing element is electrically connected between the second node and the low voltage terminal.

US Pat. No. 10,714,038

DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A display device comprising an active matrix substrate,wherein the active matrix substrate includes:
a plurality of gate lines;
a plurality of sub-gate lines that are provided in such a manner that one or more sub-gate lines are provided with respect to each of the gate lines, the sub-gate lines extending in a direction that intersects at right angles with a direction in which the gate lines extend;
first driving circuitry that is provided in a frame area and scans the gate lines; and
a second driving circuitry that is provided in the frame area and scans the sub-gate lines,
wherein each of the sub-gate lines is connected with the gate line corresponding thereto in a display area,
the first driving circuitry supplies a scanning signal to each of the gate lines via both ends of the gate line, and
the second driving circuitry includes n driving circuits (n is a natural number) that supply the scanning signal to each of the sub-gate lines, via at least one end of the sub-gate line.

US Pat. No. 10,714,037

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a display unit in which a plurality of sub-pixels are arranged in a matrix along row and column directions; and
a signal processor configured to output output signals for causing the display unit to display an image based on input signals for the image in which pixel data including three colors of red, green, and blue is arranged in a matrix,
wherein the sub-pixels comprise a first sub-pixel for red, a second sub-pixel for green, a third sub-pixel for blue, and a fourth sub-pixel for white,
wherein either the first sub-pixel or the third sub-pixel is interposed between the second sub-pixel and the fourth sub-pixel arranged in one direction of the row direction and the column direction,
wherein the signal processor is configured to output the output signals to assign, to a set of the sub-pixels included in the display unit, color components assigned to two pieces of the pixel data arranged in the one direction in the input signals,
wherein the set of the sub-pixels is made up of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel arranged along the row direction, and
wherein the signal processor is configured to assign a first color component to the fourth sub-pixel and second color components to the first sub-pixel, the second sub-pixel, and the third sub-pixel, the first color component being a part or the whole of a white component included in one piece of the pixel data among the color components included in the two pieces of the pixel data, the second color components being components other than the first color component of the color components included in the two pieces of the pixel data,
wherein scanning for driving the sub-pixels in the display unit is performed along the column direction,
wherein white at the highest luminance reproducible by a combination of the first sub-pixel, the second sub-pixel, and the third sub-pixel is higher in luminance than white at the highest luminance reproducible by the fourth sub-pixel,
wherein the first color component is a part of white component included in one of the two pieces of the pixel data arranged in the row direction in the input signals, the one piece of the pixel data being closer to an arrangement position in the row direction of the fourth sub-pixel in the set of the sub-pixels,
wherein the colors of the sub-pixels are arranged in a staggered manner,
wherein the signal processor is configured to, when the signal processor receives the input signals including the one piece of the pixel data and another piece of the pixel data next to the one piece of the pixel data in the row direction each piece of which is pixel data for causing a corresponding pixel to be relatively bright, assign color components not included in the first color component among the color components included in the one piece of the pixel data to the first sub-pixel, the second sub-pixel, and the third sub-pixel located corresponding to the other piece of the pixel data, and
wherein the signal processor is configured to, when the signal processor receives the input signals including the one piece of the pixel data for causing a corresponding pixel to be relatively bright and the other piece of the pixel data for causing a corresponding pixel to be relatively dark, assign the color components not included in the first color component among the color components included in the one piece of the pixel data to the first sub-pixel, the second sub-pixel, and the third sub-pixel aligned, in a direction of the scanning, with the fourth sub-pixel assigned the first color component.

US Pat. No. 10,714,035

DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a timing controller configured to receive an image signal from an external source, identify a color pattern of the image signal and set an output enable value corresponding to the identified color pattern, wherein the color pattern is identified based on whether the image signal comprises each of a plurality of colors and the output enable value comprises a first output enable value when the color pattern is a monochromatic pattern and a second output enable value different from the first output enable value when the color pattern is a white pattern; and
a scan driver configured to receive the output enable value and generate a first scan signal having a first turn-on signal and a second scan signal adjacent to the first scan signal and having a second turn-on signal,
wherein the scan driver adjusts an interval between the first turn-on signal and the second turn-on signal based on the output enable value.

US Pat. No. 10,714,028

METHODS AND APPARATUS FOR CONTROLLING DISPLAY BACKLIGHT

Apple Inc., Cupertino, C...

1. A converter circuit configured to convert a source of direct current from a first voltage level to a second voltage level that is different than the first voltage level, the converter circuit comprising:an input port configured to receive an input voltage at the first voltage level;
an output port at which an output voltage at the second voltage level is generated;
a first inductor having a first terminal coupled to the input port and a second terminal coupled to the output port;
a first switch having a first terminal coupled to the first inductor and a second terminal coupled to a ground power supply line;
a first current sensing resistor connected in series with the first switch; and
a controller configured to receive a first sensing signal from the first current sensing resistor and to selectively turn off the first switch in response to detecting that the amount of current flowing through the first switch exceeds a predetermined peak current level.

US Pat. No. 10,714,024

DISPLAY DEVICE AND DRIVING METHOD THEREOF

Semiconductor Energy Labo...

1. A liquid crystal display device comprising:a first substrate;
a scan line extending in a first direction and having a region in contact with an upper surface of the first substrate;
a common line extending in the first direction;
a first insulating film having a region over and in contact with the scan line;
a first wiring having a first region extending in a second direction which intersects the first direction and a second region over the scan line and the first insulating film;
a first pixel;
a second pixel adjacent to the first pixel with the common line positioned therebetween;
a third pixel adjacent to the first pixel with the first wiring positioned therebetween;
a second substrate facing the first substrate; and
a spacer provided between the first substrate and the second substrate, the spacer having a region overlapping with the scan line,
wherein each of the first pixel, the second pixel, and the third pixel comprises:
a semiconductor layer having a channel formation region of a transistor;
a first conductive film having a region over and in contact with the first insulating film, the first conductive film being electrically connected to the semiconductor layer, wherein the common line does not overlap with the first conductive film;
a first electrode over the first conductive film, the first electrode being electrically connected to the transistor;
a second electrode over the first conductive film, the first electrode and the second electrode overlapping with each other with a second insulating film provided between the first electrode and the second electrode; and
a liquid crystal layer over the first electrode and the second electrode,
wherein the second electrode of the first pixel and the second electrode of the second pixel are parts of a second conductive film provided in the first pixel and the second pixel,
wherein the second conductive film is electrically connected to the common line, and
wherein the first wiring does not overlap with the second conductive film.

US Pat. No. 10,714,022

INFORMATION PROCESSING APPARATUS AND PROGRAM

SONY CORPORATION, Tokyo ...

1. An electronic device comprising:a battery configured to supply power; and
circuitry configured to
detect brightness and output an illuminance value corresponding to the detected brightness;
derive a luminance set value for controlling a light signal setting luminance of a light source based on the illuminance value corresponding to the detected brightness and one luminance level set by a user among a plurality of luminance levels, wherein the luminance set value is derived by deriving a slope specific to the one luminance level, multiplying the slope by the illuminance value, and adding a lower limit of the luminance set value specific to the one luminance level, wherein the slope is computed based on a difference between the lower limit of the luminance set value and a luminance set value determined in advance to correspond to the one luminance level and a difference between the illuminance value and a minimum illuminance value corresponding to the lower limit of the luminance set value;
derive power consumption consumed from the battery in the light source based on the luminance set value; and
control a display to display information relating to the power consumption, the luminance set value and the one luminance level set among the plurality of luminance levels.

US Pat. No. 10,714,019

BRIGHTNESS COMPENSATION METHOD FOR DISPLAY APPARATUS, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A brightness compensation method for a display apparatus, the display apparatus comprising n rows of display units, where n is an integer no less than 2, wherein the brightness compensation method comprises: for each row of display units,turning on the row of display units S times during a display time of one frame of image;
inputting, to each display unit in the row of display units, a pixel data signal of the frame of image corresponding to the display unit, when the row of display units are turned on for the i-th time; and
inputting a compensation signal to a to-be-compensated display unit in the row of display units, and controlling other display unit than the to-be-compensated display unit in the row of display units to present black, when the row of display units are turned on for each time other than the i-th time;
wherein both S and i are integers, S?2, 1?i?S; for every two adjacent rows of display units, a time interval between same turning-ons of the latter row and the former row is the same;
wherein S equals to 3;
a time interval t1 between the first turning-on and the second turning-on of the row of display units equals to

a time interval t2 between the second turning-on and the third turning-on of the row of display units equals to

where L1, L2 and L3 are brightness values respectively outputted by a first display unit, a second display unit, and a third display unit in the case that the first display unit, the second display unit and the third display unit are applied with a same pixel data, respectively, and L1>L2>L3, T is the display time of one frame of images, the second display unit is the to-be-compensated display unit in the second turning-on, the third display unit is the to-be-compensated display unit in the second turning-on and the third turning-on, and the first display unit is other display unit than the to-be-compensated display unit.

US Pat. No. 10,714,018

SYSTEM AND METHOD FOR LOADING IMAGE CORRECTION DATA FOR DISPLAYS

Ignis Innovation Inc., W...

1. A method of loading image correction data for a display system used in a final product, including a memory store, comprising:determining initial correction data for the display system to correct for initial non-uniformity prior to assembly in the final product;
storing the initial correction data in a remote memory separate from the display system and the final product;
assembling the final product including the display system, and the memory store remote from the display system;
downloading the initial correction data from the remote memory and storing the initial correction data in the memory store on the final product during the assembly of the final product; and
transmitting the initial correction data from the memory store to the display system for correcting the display system.

US Pat. No. 10,714,012

DISPLAY DEVICE, ARRAY SUBSTRATE, PIXEL CIRCUIT AND DRIVE METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit, comprising a reset sub-circuit, a drive control sub-circuit, a power supply sub-circuit, a storage sub-circuit, a drive sub-circuit, and a light-emitting element, whereinthe reset sub-circuit is respectively coupled to a first scanning terminal, a reset terminal, a second scanning terminal, a reference power source terminal, a first control point and a second control point, and is configured to write an input voltage of the reset terminal into the first control point based on a scanning signal of the first scanning terminal and to write an input voltage of the reference power source terminal into the second control point based on a scanning signal of the second scanning terminal;
the drive control sub-circuit is respectively coupled to a third scanning terminal, a data terminal and the first control point, and is configured to write an input voltage of the data terminal into the first control point based on a scanning signal of the third scanning terminal;
the power supply sub-circuit is respectively coupled to a first power source terminal, the second scanning terminal, the second control point, a third control point and a fourth control point, and is configured to supply a voltage of the first power source terminal to the second control point based on the scanning signal of the second scanning terminal and to enable the third control point to communicate with the fourth control point;
the storage sub-circuit is respectively coupled to the first control point and the second control point, and is configured to store a voltage of the first control point and a voltage of the second control point;
the drive sub-circuit is respectively coupled to the first control point, the second control point and the third control point, and is configured to discharge electricity under the control of the voltage of the first control point and the voltage of the second control point; and
the light-emitting element is respectively coupled to the fourth control point and a second power source terminal, and is configured to emit light under the control of a voltage of the fourth control point,
wherein the reset sub-circuit comprises,
a first transistor, wherein a control electrode of the first transistor is coupled to the first scanning terminal, a first electrode of the first transistor is coupled to the reset terminal, and a second electrode of the first transistor is coupled to the first control point, and
a second transistor, wherein a control electrode of the second transistor is coupled to the second scanning terminal, a first electrode of the second transistor is coupled to the reference power source terminal, and a second electrode of the second transistor is coupled to the second control point,
wherein the drive sub-circuit comprises:
a third transistor, wherein a control electrode of the third transistor is coupled to the third scanning terminal, and a first electrode of the third transistor is coupled to the data terminal; and
a fourth transistor, wherein a first electrode of the fourth transistor is coupled to a second electrode of the third transistor, and a control electrode of the fourth transistor is coupled to a second electrode of the fourth transistor and then is coupled to the first control point,
wherein the second is the N-type transistor, and the first transistor, the third transistor and the fourth transistor are P-type transistors,
wherein in a reset of the pixel circuit, the third and the fourth transistor are configured to be turned off, and the first transistor and the second transistor are configured to be turned on so that the input voltage of the reset terminal is written into the first control point and the input voltage of the reference power source terminal is written into the second control point.

US Pat. No. 10,714,000

DISPLAY DEVICE, METHOD FOR CONTROLLING THE SAME, WEARABLE DEVICE

BEIJING BOE DISPLAY TECHN...

1. A display device, comprising:an organic light-emitting structural layer;
a first and a second control assembly at both sides of the organic light-emitting structural layer; and
a control circuit,
wherein the first control assembly comprises a first color filter layer and a first control electrode layer arranged on the first color filter layer, and the first color filter layer directly contacts both the organic light-emitting structural layer and the first control electrode layer, the second control assembly comprises a second color filter layer and a second control electrode layer arranged on the second color filter layer, and the second color filter layer directly contacts both the organic light-emitting structural layer and the second control electrode layer,
the first color filter layer comprises a plurality of first color filter regions and a plurality of first light-transmissible regions arranged alternately, the second color filter layer comprises a plurality of second color filter regions and a plurality of second light-transmissible regions arranged alternately,
each of the plurality of first color filter regions is arranged to correspond to one of the plurality of second light-transmissible region, and each of the plurality of second color filter regions is arranged to correspond to one of the plurality of first light-transmissible region,
the first control electrode layer comprises a plurality of first electrodes and a plurality of second electrodes arranged alternately, each of the plurality of first electrodes directly contacts one or two of the plurality of second electrodes,
the second control electrode layer comprises a plurality of third electrodes and a plurality of fourth electrodes arranged alternately, each of the plurality of third electrodes directly contacts one or two of the plurality of fourth electrodes,
each of the plurality of first electrodes is arranged on one of the plurality of first color filter regions corresponding to the each of the plurality of first electrodes and light transmittance of the each of the plurality of first electrodes is changeable under an effect of a first voltage,
each of the plurality of second electrodes is arranged on one of the plurality of first light-transmissible regions corresponding to the each of the plurality of second electrodes and light transmittance of the each of the plurality of second electrodes is changeable under an effect of a third voltage,
each of the plurality of third electrodes is arranged on one of the plurality of second color filter regions corresponding to the each of the plurality of third electrodes and light transmittance of the each of the plurality of third electrodes is changeable under an effect of a fifth voltage,
each of the plurality of fourth electrodes is arranged on one of the plurality of second color filter regions corresponding to the each of the plurality of third electrodes and light transmittance of the each of the plurality of fourth electrodes is changeable under an effect of a seventh voltage, and
the control circuit is connected to the plurality of first electrodes, the plurality of second electrodes, the plurality of third electrodes, and the plurality of fourth electrodes, and is configured to apply the first voltage to the seventh voltage to the plurality of first electrodes, the plurality of second electrodes, the plurality of third electrodes, and the fourth electrodes, respectively, so as to control the light transmittance of the first electrodes, the light transmittance of the second electrodes, the light transmittance of the third electrodes, and the light transmittance of the fourth electrodes, respectively.

US Pat. No. 10,713,997

CONTROLLING IMAGE DISPLAY VIA MAPPING OF PIXEL VALUES TO PIXELS

Valve Corporation, Belle...

1. A method comprising:acquiring, by one or more processors of one or more computing systems, video frame data that includes pixel value information for an associated video frame, wherein the pixel value information includes pixel values for a plurality of unidimensional pixel arrays of the associated video frame, and wherein each unidimensional pixel array is an addressable pixel column or an addressable pixel row;
encoding the video frame data by:
determining, by the one or more processors, a first position for a primary display region of a display panel on which to display the associated video frame, and multiple second positions for multiple secondary display regions of the display panel, and identifying a pixel value-to-pixel mapping to use for each of the multiple secondary display regions;
identifying, by the one or more processors, a first portion of the associated video frame corresponding to the determined first position of the primary display region, and multiple second portions of the associated video frame corresponding to the multiple secondary display regions, each of the multiple second portions including two or more unidimensional pixel arrays of the plurality of unidimensional pixel arrays; and
modifying, for each of the multiple second portions, and for each of one or more first unidimensional pixel arrays of the two or more unidimensional pixel arrays included in the second portion, pixel values to use for the second portion in the encoded video frame data by assigning pixel values from the first unidimensional pixel array to pixels of one or more second unidimensional pixel arrays of the two or more unidimensional pixel arrays included in the second portion that are adjacent to the first unidimensional pixel array, so that the modified pixel values to use for the second portion include multiple pixel clusters according to the pixel value-to-pixel mapping for the second portion that each have a single pixel value for all pixels in the pixel cluster;
transmitting the encoded video frame data to at least one controller for the display panel; and
displaying, under control of the at least one controller, the encoded video frame data on the display panel, including using pixel values of the first portion of the associated video frame to control display of pixels in the primary display region at the first position of the display panel, and using the modified pixel values for each of the multiple second portions to control display of pixels in the multiple secondary display regions at the multiple second positions of the display panel.

US Pat. No. 10,713,994

DISPLAY APPARATUS AND DRIVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A display apparatus, comprising:a display comprising a plurality of display modules;
one or more display drivers; and
a processor configured to:
identify a maximum power level from among a plurality of power levels respectively corresponding to the plurality of display modules;
control the one or more display drivers to control an input current to each of the plurality of display modules based on the maximum power level and a gray scale value of a portion of an image on the display corresponding to each of the plurality of display modules; and
display the image on the display using the plurality of display modules.

US Pat. No. 10,713,990

DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising a display base, the display base provided with a first effective display region, and the display base further comprising a plurality of pixel driving circuits arranged in N rows and multiple columns in the first effective display area, N being an integer greater than 1; the display substrate further comprising a bent portion disposed on at least one side of the display base; the display substrate further comprising a gate driving circuit disposed on the bent portion; the gate driving circuit configured to provide a gate driving signal to the N rows pixel driving circuits disposed on the first effective display region, respectively,wherein the display substrate further comprises a plurality of pixel driving circuits arranged in N rows and multiple columns on the bent portion, and the gate driving circuit is further configured to provide a gate driving signal to the N rows of pixel driving circuits disposed on the bent portion, respectively;
the gate driving circuit comprise N stages of gate driving units;
a (2n?1)-th stage gate driving unit and a 2n-th stage gate driving unit are disposed in a same row; the (2n?1)-th stage gate driving unit and the 2n-th stage gate driving unit are disposed between a (2n?1)-th row pixel driving circuit on the bent portion and a 2n-th row pixel driving circuit on the bent portion;
a gate driving signal output terminal of the (2n?1)-th stage gate driving unit is connected to the (2n?1)-th row pixel driving circuit on the bent portion, and is configured to provide a gate driving signal to the (2n?1)-th row pixel driving circuit on the bent portion;
a gate driving signal output terminal of the 2n-th stage gate driving unit is connected to the 2n-th row pixel driving circuit on the bent portion, and is configured to provide a gate driving signal to the 2n-th row pixel driving circuit on the bent portion;
the (2n?1)-th stage gate driving unit is further connected to a (2n?1)-th row pixel driving circuit on the display base, and is configured to provide a gate driving signal to the (2n?1)-th row pixel driving circuit on the display base;
the 2n-th stage gate driving unit is further connected to a 2n-th row pixel driving circuit on the display base, and is configured to provide a gate driving signal to the 2n-th row pixel driving circuit on the display base; and
n is a positive integer and 2n is less than or equal to N.

US Pat. No. 10,713,985

INSPECTING METHOD OF LIGHT EMITTING DIODE AND APPARATUS FOR INSPECTING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A method of inspecting light emitting elements, the method comprising:disposing a first electrode and a second electrode on a substrate;
applying a solution including a plurality of light emitting elements floating freely within a solvent on the first electrode and the second electrode;
applying a first voltage across the first electrode and the second electrode so as to cause the plurality of light emitting elements to emit light;
photographing the light emitted from the plurality of light emitting elements and generating first image data therefrom; and
determining a density of the plurality of light emitting elements using the first image data.

US Pat. No. 10,713,980

WINDOW MOUNTABLE ILLUMINATED SIGN ASSEMBLY

1. A window mountable illuminated sign assembly comprising:a sign housing with a rear surface, an upper end, a lower end opposing the upper end of the sign housing, and a sidewall having an upper sidewall edge spanning a perimeter thereon;
an electrical circuit disposed within the sign housing and electrically and operably coupled to a plurality of light emitting diodes (LEDs) operably configured to project light and oriented in a front-facing orientation;
a flange coupled to and surrounding the upper sidewall edge, the flange of a flexible and deformable polymeric material and having a sidewall with an inner surface and a distal flange edge;
a translucent front panel directly coupled to the inner surface of the sidewall of the flange, having a front surface opposing the rear surface of the sign housing and interposed between the rear surface of the sign housing and the distal flange edge, and having a lettered and contrasting indicia disposed on the front surface of the front panel;
a plurality of suction cup fasteners coupled to the sign housing, each defining a concave cut cavity facing the front-facing orientation;
a first plurality of suction cup arms, each with one of the plurality of suction cup fasteners coupled thereto, and a second plurality of suction cup arms, each with one of the plurality of suction cup fasteners coupled thereto; and
a first plurality of sign sidewall edge recesses defined on the sidewall of the sign housing, each sized and shaped to receive one of the first plurality of suction cup arms and second plurality of sign sidewall edge recesses defined on sidewall of the sign housing, each sized and shaped to receive one of the second plurality of suction cup arms, wherein the first and second plurality of suction cup arms dispose the plurality of suction cup fasteners in a configuration with the front panel interposed between the plurality of suction cup fasteners and an inside surface of the sign housing.

US Pat. No. 10,713,974

DISPLACEMENT TRANSDUCER ARRANGEMENT AND CRASH TEST DUMMY

1. A displacement transducer arrangement for measuring intrusions in a crash test dummy, having a first mounting and a second mounting, wherein a distance between the first mounting and the second mounting is variable, wherein there is a displacement transducer for measuring the distance (D) between the first mounting and second mounting, and wherein the first mounting and second mounting are connected to each other by a scissor-jack mechanism, wherein the displacement transducer is arranged in the direction of extension (E) between first mounting and second mounting to the side of the scissor-jack mechanism.

US Pat. No. 10,713,972

JOB PROCEDURE DISPLAY APPARATUS, METHOD OF CONTROLLING JOB PROCEDURE DISPLAY APPARATUS AND NON-TRANSITORY, COMPUTER READABLE STORAGE MEDIUM

FUJITSU LIMITED, Kawasak...

1. A display apparatus comprising:a display configured to display any of a plurality of job screens, each of the plurality of job screens corresponding to any of one or more job procedures, the one or more job procedure being associated with an assembly of an apparatus;
a touch panel disposed on the display, the touch panel being configured to detect an operation by a user;
a processor coupled directly or indirectly to the touch panel, the processor being configured to
receive a position of an operation by the user from the touch panel, the position corresponding to any coordinates on the touch panel,
identify a first region on the touch panel in accordance with the received position, the first region being any of a plurality of divided regions on whole area of the touch panel, the plurality of divided regions being transparently overlapped over a first job screen displayed on the display in a way that each of the plurality of divided regions is defined by a static boundary extended over whole of the display, the first job screen indicating a first job procedure, the first job procedure being any of the one or more of job procedures, the plurality of divided regions including at least a first divided region and a second divided region, the first divided region corresponding to a first command for going to a job screen corresponding to a preceding job procedure, the second divided region corresponding to a second command for going to a job screen corresponding to a second job procedure, the preceding job procedure being a job procedure one before the first job procedure, the second job procedure being different from the preceding job procedure and the first job procedure, and
display, in response to the identifying the first region, a new job screen on the display in a way that each of the plurality of divided regions is transparently overlapped over the new job screen, wherein each of the plurality of divided regions is defined by a static boundary extended over whole of the new job screen.

US Pat. No. 10,713,969

TRAILER SWAY DEMONSTRATOR

U-HAUL INTERNATIONAL, INC...

1. An apparatus for simulating a vehicle traveling on a road and towing a trailer, the apparatus comprising in combination:a motorized belt including a surface movable at a variable speed in a longitudinal direction;
a support frame for supporting the motorized belt;
a model towing vehicle positioned on the belt movable surface and including one or more steerable wheels that can be turned to steer the model towing vehicle laterally and a servo motor adapted to turn the one or more steerable wheels laterally in response to a servo control signal, wherein the model towing vehicle is coupled to the support frame via a coupling arm so that the model towing vehicle can move laterally on the motorized belt when the motorized belt is in motion in the longitudinal direction;
a model trailer adapted for coupling to the rear end of the model towing vehicle and including removable weights for simulating weight distribution in a life size trailer; and
a steering control assembly including a steering control mechanism and a servo driver configured to provide the servo control signal to control the servo motor in response to operation of the steering control mechanism;
whereby when the motorized belt moves in the longitudinal direction, an operator can operate the steering control mechanism to steer the model towing vehicle laterally with respect to the motorized belt.

US Pat. No. 10,713,967

WEAPONS TRAINING SYSTEM AND METHODS FOR OPERATING SAME

1. A combat simulation system comprising:a plurality of simulation weapons, each weapon configured to selectively emit a respective encoded emission of a light beam;
a plurality of wearable sensors configured to detect said respective encoded emission from one or more of said plurality of simulation weapons, each of said plurality of sensors communicatively paired with a corresponding one of said plurality of simulation weapons;
a plurality of user devices including one or more mobile devices, each configured to determine a user's location by a positioning system;
an administration computing device comprising a tangible computer-readable medium storing program code segments, the program code segments configured to cause a processor to perform a method, the method comprising:
administering a simulated mission; monitoring user locations, user operating parameters, and status of mission objectives during a simulated mission; and
enabling dynamic control of the simulated mission including user operating parameters, simulated event objects, and mission parameters associated with the simulated mission; and
displaying a plurality of graphical images indicative of information and parameters associated with the simulated mission including the monitored user locations, the displaying including an interface configured to selectively, (1) zoom in and out on a map view module; (2) adjust parameters associated with a selected simulated event object; (3) add mission event objects; (4) view player locations; (5) view player statistics and player operating metrics (6) view mission statistics and mission operating metrics; (7) adjust ammo on a selected player's weapon; and (8) partially disable a selected player's weapon; and
enabling use of a user's simulation weapon after partial disablement upon receiving notification that a user has performed a sequence comprising: (1) slapping a magazine of the simulated weapon upward; (2) pulling a charging handle of the simulated weapon in a rearward direction; (3) releasing the charging handle; and (4) tapping a forward assist assembly of the simulated weapon,
wherein said positioning system of said one or more mobile devices is configured to send the conditions of the plurality of wearable sensors and the plurality of weapons to the administrative computing device; and
a controller in operable communication with said plurality of simulator weapons, said plurality of wearable sensors,
whereby said controller is configured to identify each specific weapon which produces a respective encoded light detected by at least one of the plurality of wearable sensors.

US Pat. No. 10,713,964

SYSTEM AND METHOD FOR FACILITATING CREATION OF AN EDUCATIONAL TEST BASED ON PRIOR PERFORMANCE WITH INDIVIDUAL TEST QUESTIONS

Bilal Ismael Shammout, D...

1. A system for facilitating creation of a test based on prior performance with individual test questions, the system comprising:one or more physical processors programmed to execute computer program instructions which, when executed, cause the one or more physical processors to:
generate a user interface configured to receive a set of parameters for the test, the set of parameters comprising a subject matter of the test, one or more question categories for the test, and a questionee group for which the test is intended;
receive, via the user interface, a first user input from a user indicating the subject matter, the one or more question categories, and the questionee group;
obtain, based on the first user input, a set of questions that correspond to the subject matter, the one or more question categories, and the intended questionee group;
obtain, for individual questions of the set of questions, performance information associated with the question, wherein the performance information comprises a question performance metric value associated with the question that is calculated based on prior performance of one or more questionees with the question;
display, via the user interface, a selectable listing of the set of questions;
receive, via the selectable listing of the user interface, a first selection of a first question from among the set of questions, the first question having a first question performance metric value;
add the first question to the test based on the first selection;
responsive to the selection of the first question, automatically calculate a test performance metric value associated with the test based on at least the first question performance metric value;
cause the test performance metric value to be provided via the user interface;
receive, via the user interface, a second selection of a second question from among the set of questions, the second question having a second question performance metric value;
add the second question to the test based on the second selection;
responsive to the selection of the second question, automatically calculate an updated test performance metric value associated with the test based on the second question performance metric value;
cause the updated test performance metric value to be provided via the user interface;
receive a second user input from the user indicating test criteria for the test, wherein the test criteria includes a test performance benchmark value that corresponds to the updated test performance metric value;
determine whether the test satisfies the test criteria based on the first question, the second question, and/or the updated test performance metric value;
responsive to a determination that the test does not satisfy the test criteria, identify in real-time a second set of questions recommended for inclusion in the test based on at least the updated test performance metric value, the test performance benchmark value, and performance information for each of the second set of questions such that inclusion of one or more of the second set of questions will result in satisfaction of the test criteria;
automatically display via the user interface a notification that the test does not satisfy the test criteria and a recommendation to include one or more of the identified second set of questions in the test;
obtain a predefined composition of categories of subject matter to be provided to the intended questionee group, wherein the predefined composition of categories of subject matter is based on a syllabus provided to students who are members of the intended questionee group;
identify a third set of questions to be added to the test based on the predefined composition of categories of subject matter; and
provide a recommendation to add one or more questions from the third set of questions.