US Pat. No. 10,461,255

ORGANIC LIGHT EMITTING DIODE DISPLAY

Samsung Display Co., Ltd....

1. An organic light emitting diode (OLED) display comprising:a first substrate;
an organic light emitting element disposed on the first substrate;
a first adhesive layer disposed on the organic light emitting element, covering sides of the organic light emitting element;
a second adhesive layer disposed on the first adhesive layer, and the entirety of which does not contact the organic light emitting element; and
a second substrate disposed on the second adhesive layer,
wherein the first adhesive layer and the second adhesive layer include a thermally curable resin or a photocurable resin, respectively,
wherein the second adhesive layer comprises more than about 5 to about 50 parts by weight of a hygroscopic material based on 100 parts by weight of the thermally curable resin or the photocurable resin, and
wherein the first adhesive layer includes a bisphenol-based epoxy resin as the thermally curable resin or the photocurable resin.

US Pat. No. 10,461,252

RESISTIVE RANDOM ACCESS MEMORY

National Sun Yat-Sen Univ...

1. A resistive random access memory comprising:a first electrode;
a second electrode separate from the first electrode;
an enclosing layer forming a first via-hole; and
an oxygen-containing resistance changing layer arranged for the first via-hole, wherein the first and second electrodes and the enclosing layer jointly enclose the oxygen-containing resistance changing layer, wherein each of the first electrode, the second electrode and the enclosing layer is made of an element not containing oxygen, wherein each of the first electrode, the second electrode and the enclosing layer abuts with the oxygen-containing resistance changing layer, wherein the enclosing layer is mounted on one of the first and second electrodes, and
wherein the oxygen-containing resistance changing layer is formed from oxides doped with chlorine and is completely located in the first via-hole, wherein the first electrode is not parallel to the second electrode, wherein the enclosing layer encloses the first electrode but does not enclose the second electrode, and wherein the enclosing layer is in contact with a bottom face of the second electrode.

US Pat. No. 10,461,247

INTEGRATED MAGNETIC RANDOM ACCESS MEMORY WITH LOGIC DEVICE HAVING LOW-K INTERCONNECTS

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a substrate defined with at least first, second and third regions, wherein the substrate includes a first interlevel dielectric (ILD) layer;
a first upper dielectric layer disposed over the first ILD layer, wherein the first upper dielectric layer serves as a lower portion of a via level of a second ILD layer above the first ILD layer, the first upper dielectric layer includes a bottom electrode trench disposed in the second region and an alignment trench disposed in the third region, the bottom electrode trench exposes a metal line in the first ILD layer, the alignment trench has an alignment trench depth which is deeper than a bottom electrode trench depth of the bottom electrode trench, and the alignment trench extends into the first ILD layer;
a bottom electrode disposed in the bottom electrode trench;
a bottom electrode alignment mark disposed in the alignment trench; and
a magnetic tunnel junction (MTJ) element disposed on the bottom electrode,
wherein the bottom electrode comprises a bottom electrode material disposed in the bottom electrode trench, and the bottom electrode alignment mark comprises the bottom electrode material disposed in the alignment trench.

US Pat. No. 10,461,246

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A memory device, comprising:a bottom electrode;
a resistance switching element over the bottom electrode;
a top electrode over the resistance switching element;
an interlayer dielectric layer surrounding the resistance switching element;
a first spacer between the interlayer dielectric layer and a sidewall of the resistance switching element, wherein a bottom surface of the first spacer is over a top surface of the bottom electrode; and
a metal-containing compound layer between the interlayer dielectric layer and the sidewall of the resistance switching element.

US Pat. No. 10,461,245

MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A magnetic memory device comprising:a stack structure which is formed on an underlying area and includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer;
a protective insulating film covering the stack structure and provided along upper and side surfaces of the stack structure; and
an interlayer insulating film covering upper and side surfaces of the protective insulating film,
wherein:
a portion of the protective insulating film formed on the side surface of the stack structure is thicker than a portion of the protective insulating film formed on the upper surface of the stack structure,
the protective insulating film includes a first protective insulating film formed along the side surface of the stack structure, and a second protective insulating film covering the stack structure and the first protective insulating film,
a side surface of the first magnetic layer, a side surface of the nonmagnetic layer, and a side surface of the second magnetic layer are provided continuously without a step,
the first protective insulating film covers the side surfaces of the first magnetic layer, the nonmagnetic layer, and the second magnetic layer, and
an oxygen concentration at a boundary between the first protective insulating film and the second protective insulating film is higher than that within the first protective insulating film and that within the second protective insulating film.

US Pat. No. 10,461,244

LAMINATED STRUCTURE AND SPIN MODULATION ELEMENT

TDK CORPORATION, Tokyo (...

1. A laminated structure, comprising:a ferromagnetic layer; and
a multiferroic layer formed on one surface of the ferromagnetic layer,
wherein a surface of the multiferroic layer on the ferromagnetic layer side includes a first region, a crystalline phase of which is rhombohedral, and a second region, a crystalline phase of which is tetragonal,
a proportion of the first region occupying the surface is 30% or more and 70% or less, and
a proportion of the second region occupying the surface is 30% or more and 70% or less.

US Pat. No. 10,461,241

METHOD FOR MANUFACTURING RECTANGULAR PARALLELEPIPED-SHAPED SINGLE CRYSTAL, RECTANGULAR PARALLELEPIPED-SHAPED SINGLE CRYSTAL, METHOD FOR MANUFACTURING CERAMICS, CERAMICS, PIEZOELECTRIC ELEMENT, PIEZOELECTRIC DEVICE, AND ELECTRONIC DEVICE

Canon Kabushiki Kaisha, ...

1. A rectangular parallelepiped-shaped single crystal containing sodium niobate of a perovskite structure as a main component, whereinthe rectangular parallelpiped-shaped single crystal contains bismuth in an amount of 0.05 mol or more and 0.15 mol or less per mole of the sodium niobate,
a Na/Nb ratio of the rectangular parallelepiped-shaped single crystal is 0.82 or more and 1.00 or less, and
a ratio of a longest side length (Lmax) to a shortest side length (Lmin) of the rectangular parallelepiped is in a range of Lmax/Lmin of 4.0?Lmax/Lmin?8.5.

US Pat. No. 10,461,240

PIEZOELECTRIC SENSORS AND METHODS FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A piezoelectric sensor, comprising a first electrode layer, a second electrode layer and a piezoelectric thin film layer between the first electrode layer and the second electrode layer, the piezoelectric sensor further comprising:a first functional module and a second functional module, both of which are connected to the second electrode layer, wherein the first functional module is configured to sense a pressure applied to the piezoelectric sensor in a first direction, and the second functional module is configured to sense a pressure applied to the piezoelectric sensor in a second direction, and the first direction and the second direction are perpendicular to each other.

US Pat. No. 10,461,238

THERMOELECTRIC CONVERSION STRUCTURE AND METHOD FOR MAKING THE SAME

NEC Corporation, Tokyo (...

1. A thermoelectric conversion structure, comprising:a plurality of thermoelectric conversion unit structures, wherein each thermoelectric conversion unit structure comprises a magnetic fine particle comprising a magnetic material that exhibits a spin Seebeck effect and an electromotive body that covers the magnetic fine particle,
wherein the electromotive bodies of the plurality of thermoelectric conversion unit structures are connected to each other,
the plurality of thermoelectric conversion unit structures forms an aggregate, and
all surfaces of each of the magnetic fine particles are in direct physical contact with the aggregate.

US Pat. No. 10,461,236

THERMOELECTRIC GENERATOR

KABUSHIKI KAISHA TOSHIBA,...

1. A thermoelectric generator comprising:a thermoelectric device that converts heat energy into electric energy; and
a DC to DC converter that converts an input voltage applied by the thermoelectric device to a voltage higher than the input voltage applied by the thermoelectric device, wherein
the input voltage applied by the thermoelectric device is higher than a voltage which is half an open voltage of the thermoelectric device,
the DC to DC converter includes:
a first switch which is ON/OFF-controlled in accordance with a switch control signal whose ON time is variable;
an inductor connected to the first switch;
a second switch that switches between a state where a current is supplied from the thermoelectric device to the inductor and a state where no current is supplied from the thermoelectric device to the inductor; and
a sample and hold circuit that samples the open voltage of the thermoelectric device when the second switch is in the state where no current is supplied from the thermoelectric device to the inductor, and holds the sampled open voltage of the thermoelectric device,
the input voltage applied by the thermoelectric device increases or decreases in accordance with the ON time,
the ON time is subjected to feedback control such that the input voltage applied by the thermoelectric device approaches to a value obtained by multiplying the held open voltage of the thermoelectric device by a gain, and
the gain is determined based on an output resistance of the thermoelectric device, a parasitic resistance of the inductor, a parasitic resistance of the first switch, and a parasitic resistance of the second switch.

US Pat. No. 10,461,235

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a semiconductor device, the method comprising:disposing a substrate metal film on an upper surface of a substrate made of a metal;
disposing a first element metal film on a lower surface of a first element;
disposing a second element metal film on a lower surface of a second element;
after disposing the substrate metal film, the first element metal film and the second element metal film, bonding the first element and the second element to the substrate so that an upper surface of the substrate metal film is in contact with a lower surface of the first element metal film and a lower surface of the second element metal film;
after bonding the first element and the second element to the substrate, oxidizing at least a portion of a region of the upper surface of the substrate metal film other than regions in contact with the first element metal film and the second element metal film; and
after oxidizing the at least portion of the region of the upper surface of the substrate metal film other than the regions in contact with the first element metal film and the second element metal film, disposing a wiring electrically connecting the first element and the second element, across and above a region including the region oxidized in the oxidizing step.

US Pat. No. 10,461,233

LIGHT EMITTING DEVICE PACKAGE AND LIGHTING DEVICE

LG INNOTEK CO., LTD., Se...

1. A light emitting device package, comprising:a first lead frame;
a light emitting device disposed on the first lead frame;
a second lead frame spaced apart from the first lead frame in a first direction;
a protective device disposed on the second lead frame; and
a body coupled to the first and second lead frames,
wherein the body including a cavity exposing a portion of an upper surface of the first lead frame and an upper surface of the second lead frame,
wherein the cavity includes first to fourth inner side surfaces which are inclined, respectively,
wherein the first inner side surface faces the second inner side surface in the first direction,
wherein the third inner side surface faces to the fourth inner side surface in a second direction,
wherein the first to fourth inner side surfaces face the first to fourth sides of the light emitting device, respectively,
wherein the cavity has a first bottom surface that exposes a part of an upper surface of the first lead frame; a second bottom surface on which a part of an upper surface of the second lead frame is exposed and on which the protection device is disposed; and a third bottom surface on which a part of the upper surface of the second lead frame is exposed and spaced apart from the second bottom surface,
wherein the first lead frame comprises a first stepped portion disposed along an edge of a lower surface thereof and at least one first through hole,
wherein the first through hole includes a second stepped portion disposed at an inner side thereof,
wherein the cavity includes a first recess portion exposing the second lead frame and a second recess portion exposing the first lead frame,
wherein the second lead frame comprises a third stepped portion disposed along an edge of a lower surface thereof, and a mounting region of the protective device which is not overlapped in a vertical direction and spaced apart from the third stepped portion,
wherein a part of the second recess portion is overlapped with the third stepped portion in the vertical direction,
wherein a minimum distance between the first recess portion and the second recess portion is greater than a length of one side of the light emitting device, and
wherein the first recess portion is not overlapped with a second side of the light emitting device in the first direction.

US Pat. No. 10,461,232

CONDENSATION REACTION-TYPE DIE BONDING AGENT, LED LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME

CITIZEN WATCH CO., LTD., ...

1. A condensation reaction-type die bonding agent for bonding an LED device provided on its surface with device electrodes having connection surfaces covered by gold, said die bonding agent comprising:(A) a polysilsesquioxane solid in state at room temperature having trisiloxy units (TA) expressed by R1SiO3/2 where, R1 indicates one group selected from the group comprised of C1 to C15 alkyl groups, a phenyl group, and a benzyl group, and having hydroxyl groups;
(B) a polysilsesquioxane liquid in state at room temperature having 65 mol % to 100 mol % trisiloxy units (TB) expressed by R2SiO3/2 where, R2 indicates one group selected from the group comprised of C1 to C15 alkyl groups, a phenyl group, and a benzyl group, and having —OR2 where, R2 indicates one group selected from the group comprised of C1 to C15 alkyl groups, a phenyl group, and a benzyl group; and
(C) a condensation reaction catalyst.

US Pat. No. 10,461,229

PACKAGE FOR ULTRAVIOLET EMITTING DEVICES

RayVio Corporation, Hayw...

1. A device comprising:a light emitting diode comprising a semiconductor structure comprising an active layer disposed between an n-type region and a p-type region, wherein the active layer emits UV radiation;
a mount, wherein the light emitting diode is disposed on the mount, the mount comprising a support structure that surrounds the light emitting diode;
the support structure defining a cavity within which the light emitting diode is located, the support structure providing a first surface surrounding a top of the cavity;
a transparent optic disposed over the light emitting diode, the transparent optic comprising tabs extending from a top portion of the optic, where the tabs rest on the first surface of the support structure; and
the optic being a pre-formed solid structure that is positioned within the cavity such that the optic only takes up a portion of the cavity, wherein there is a gap between sidewalls of the cavity and the optic, the optic tapering inward as it approaches the light emitting diode within the cavity.

US Pat. No. 10,461,226

SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor light emitting device package comprising:a substrate;
a semiconductor light emitting device on the substrate; and
an encapsulation layer which covers the semiconductor light emitting device,
wherein the encapsulation layer comprises:
a plurality of ring portions which are disposed sequentially from an edge toward a center of the substrate, in a plan view; and
a center portion which is surrounded by an innermost one of the plurality of ring portions,
wherein the semiconductor light emitting device package further comprises a dam structure which extends along an outer sidewall of an outermost one of the plurality of ring portions, and
wherein the dam structure is substantially transparent.

US Pat. No. 10,461,225

METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE INCLUDING SEALING MATERIALS WITH PHOSPHOR PARTICLES

TOYODA GOSEI CO., LTD., ...

1. A method of manufacturing a light-emitting device, the method comprising:providing a case comprising a recessed portion and mounting a light-emitting element on a bottom of the recessed portion;
putting a first sealing material comprising a first phosphor particle into the recessed portion;
putting a second sealing material comprising a second phosphor particle on the first sealing material in the recessed portion;
precipitating the second phosphor particle before curing the second sealing material; and
curing the first sealing material and the second sealing material after the precipitating of the second phosphor particle,
wherein the second phosphor particle is located above the first phosphor particle after the first and second sealing materials cure,
wherein the precipitating of the second phosphor particle is conducted so as to form a layer of the second phosphor particle at a bottom of the second sealing material before the curing of the first sealing material and the second sealing material, and
wherein the first phosphor particle and the second phosphor particle are different in a degree of precipitation.

US Pat. No. 10,461,223

SEMICONDUCTOR DEVICE

Epistar Corporation, Hsi...

1. A semiconductor device, comprising:a semiconductor stack comprising a surface; and
an electrode structure comprising an electrode pad formed on the surface, wherein the electrode structure further comprises a first extending electrode, a second extending electrode and a third extending electrode connecting to the electrode pad, and the first extending electrode is closer to a periphery of the surface than the third extending electrode is, and the second extending electrode is between the first extending electrode and the third extending electrode;
wherein, from a top view of the semiconductor device, the first extending electrode, the second extending electrode and the third extending electrode respectively comprise a first curve having a first angle ?1, a second curve having a second angle ?2 and a third curve having a third angle ?3, wherein ?3>?2>?1 .

US Pat. No. 10,461,222

LIGHT-EMITTING ELEMENT COMPRISING SAPPHIRE SUBSTRATE WITH CONVEX PORTIONS

NICHIA CORPORATION, Anan...

1. A light-emitting element comprising:a sapphire substrate having a c-plane at a main surface thereof; and
a semiconductor layer located on a main surface side of the sapphire substrate,
wherein the sapphire substrate comprises:
a first convex portion located at the main surface and having two longitudinal sides along a first m-axis of the sapphire substrate,
a second convex portion located at the main surface and having two longitudinal sides along a second m-axis of the sapphire substrate, and
a third convex portion located at the main surface and having two longitudinal sides along a third m-axis of the sapphire substrate,
wherein the second m-axis is rotated counterclockwise by 120° from the first m-axis, and the third m-axis is rotated counterclockwise by 120° from the second m-axis,
wherein a first line extending through the third convex portion and parallel to the third m-axis passes through the first convex portion in a plan view;
wherein a second line extending parallel to the second m-axis and tangent to an end of the first convex portion at a second-convex-portion side does not pass through the third convex portion; and
wherein the first convex portion and the third convex portion are on opposite sides of the second line.

US Pat. No. 10,461,221

SEMICONDUCTOR DEVICE WITH IMPROVED LIGHT PROPAGATION

Sensor Electronic Technol...

1. A semiconductor structure comprising:a layer transparent to radiation having a target wavelength, wherein radiation of the target wavelength enters the transparent layer through a first side and exits the transparent layer through a second side, and wherein the second side comprises a profiled surface, the profiled surface including a plurality of vacancies fabricated in the material of the layer, wherein each vacancy comprises side walls configured for at least partial diffusive scattering of the radiation of the target wavelength, wherein an average thickness of each of the plurality of vacancies is approximately one tenth of an average distance between adjacent vacancies in the plurality of vacancies.

US Pat. No. 10,461,215

METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light-emitting device, the method comprising:directly bonding a plurality of light-emitting elements to a collective light-transmissive member having a plate shape, each light-emitting element comprising a plurality of electrodes;
subsequently, forming stud bumps on each electrode of each light-emitting element;
subsequently, dividing the collective light-transmissive member to obtain a plurality of light-transmissive members on each of which one or more of the light-emitting elements are bonded; and
subsequently, mounting the light-emitting elements on or above a mounting base by a flip-chip technique.

US Pat. No. 10,461,214

METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE

TOYODA GOSEI CO., LTD., ...

1. A method for producing a Group III nitride semiconductor light-emitting device, the method comprising:forming an oxide film containing Al atoms, N atoms, and O atoms by uniformly oxidizing an entire surface of at least one substrate of an AlN substrate and an AlGaN substrate;
forming a first Group III nitride layer on the oxide film;
forming a first conductive type first semiconductor layer on the first Group III nitride layer;
forming a light-emitting layer on the first semiconductor layer; and
forming a second conductive type second semiconductor layer on the light-emitting layer,
wherein, in the forming the first Group III nitride layer, the AlN layer or the AlGaN layer is formed as the first Group III nitride layer under a condition that a temperature of the substrate is 1200° C. to 1450° C.,
wherein, in the forming the oxide film, AlON or AlGaON is formed as the oxide film for inverting a polarity, and the polarity is inverted between the substrate and the first Group III nitride layer formed on the oxide film by the oxide film, and
wherein, in the forming the oxide film, octahedral crystals of O and Al are formed as the oxide film.

US Pat. No. 10,461,213

METHOD OF MANUFACTURING SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A method of manufacturing a solar cell, the method comprising:forming a photoelectric converter including an amorphous semiconductor layer;
forming an electrode connected to the photoelectric converter; and
performing a post-treatment by providing light to the photoelectric converter and the electrode,
wherein, in the performing of the post-treatment, a plasma lighting system (PLS) is used as a light source, and a processing temperature is within a range from about 100° C. to about 300° C.,
wherein a cover substrate is located on a front surface of the light source, and
wherein the cover substrate includes a plurality of substrates having different indices of refraction.

US Pat. No. 10,461,212

METHOD FOR PROCESSING SILICON MATERIAL

NewSouth Innovations Pty ...

1. A method for manufacturing a photovoltaic device, the method comprising the steps of:providing a substrate that comprises a silicon p-n junction;
annealing the substrate at a temperature between 500° C. and 700° C. in the presence of a hydrogen source for a first predetermined period of time to allow hydrogen atoms to penetrate into silicon material of the silicon p-n junction; and
exposing the substrate to electromagnetic radiation while the substrate is kept at a temperature between 150° C. and 400° C. in a manner such that photons with an energy higher than that of a bandgap of the silicon material are provided at a radiation intensity of at least 20 mW/cm2 and an excess of minority carriers is created in the silicon material;
wherein, during the steps of annealing the substrate and exposing the substrate to electromagnetic radiation, electrically active defects in the silicon material are passivated.

US Pat. No. 10,461,211

PROCESS FOR PRODUCING AN ARRAY OF MESA-STRUCTURED PHOTODIODES

1. A process for producing an array of mesa-structured photodiodes, including at least the following steps:a) producing a layer, referred to as the useful layer, including an upper face and an opposite lower face, resting on a carrier layer via the lower face, including a stack of a first zone located at the upper face and having a first doping type, and of a second zone located between the first zone and the carrier layer having a second doping type, opposite the first type;
b) producing an etch mask positioned on said upper face, formed of a plurality of pads, referred to as etch pads which are distinct from one another;
c) wet-etching a part of the useful layer located between the etch pads, thus forming a plurality of mesa-structured photodiodes, each having an upper surface on which one of said etch pads rests, said wet etch being adapted so that the upper surface of each photodiode has a mean lateral dimension that is smaller than that of the corresponding etch pad, thus forming a recess between the etch pad and the corresponding photodiode;
d) conformally depositing, on the etch pads and the photodiodes, a passivation layer made of at least one dielectric or semiconductor material, with deposition conditions chosen so that the passivation layer has a local thickness that is less than or equal to 200 nm below the recess, and a columnar polycrystalline structure, the columns of which extend longitudinally along the thickness of the passivation layer with a constant transverse dimension, and are separated laterally from one another by grain boundaries;
e) removing the etch pads by chemical dissolution, thus leaving the upper surface exposed, a surface, referred to as the lateral surface of the photodiodes, which surrounds the upper surface, being covered by the passivation layer;
f) producing electrically conductive pads on and in contact with the upper surface.

US Pat. No. 10,461,208

SOLAR CELL AND METHOD FOR PRODUCING SAME

REC SOLAR PTE. LTD., Sin...

1. A method for fabricating a rear contacted heterojunction intrinsic thin layer solar cell wherein the rear side is formed by at least:providing a silicon substrate with a front surface and a rear surface;
depositing a continuous thin layer of intrinsic amorphous silicon over the entire rear surface of the silicon substrate, the intrinsic amorphous silicon layer having a front surface adjacent to the rear surface of the silicon substrate and the intrinsic amorphous silicon layer having a back surface opposite to the front surface of the intrinsic amorphous silicon layer;
depositing a separation layer comprising an electrically insulating material wherein the separation layer is deposited through a mask such that it covers separation portions of the back surface of the intrinsic amorphous silicon layer;
depositing an emitter layer comprising a doped semiconducting material of a first doping polarity wherein the emitter layer is deposited through a mask such that it covers an emitter portion of the back surface of the intrinsic amorphous silicon layer adjacent to the separation portions;
depositing a base layer comprising a doped semiconducting material of a second doping polarity opposite to the first doping polarity and with higher doping concentration than the silicon substrate wherein the base layer is deposited though a mask such that it covers a base portion of the back surface of the intrinsic amorphous silicon layer adjacent to the separation portions.

US Pat. No. 10,461,206

SOLAR PHOTOVOLTAIC-THERMAL SYSTEM

Changzhou Almaden Co., Lt...

1. A solar photovoltaic-thermal system comprising:a solar cell assembly comprising a transparent glass front cover, a transparent encapsulating material, a transparent glass back sheet and a photovoltaic component situated between the transparent glass front cover and the transparent glass back sheet and encapsulated by the transparent encapsulating material;
a plurality of light guides, located below the transparent glass back sheet of the solar cell assembly and each having a plane with a slant angle with respect to the transparent glass back sheet, an arc surface or a parabolic surface; and
a light reflecting plate disposed below the solar cell assembly and the light guides, wherein the light reflecting plate, two adjacent light guides and the transparent glass back sheet form a fully enclosed space and confine a light collection cavity;
a heat exchanger disposed in the light collection cavity; and
an outer frame;wherein the transparent glass back sheet is supported only by the outer frame and the light guides, andwherein the heat exchanger is not vertically shaded by the photovoltaic component, and the heat exchanger is heated by radiation heat and conduction heat from the light collection cavity.

US Pat. No. 10,461,204

DEFORMABLE PAPER ORIGAMI OPTOELECTRONIC DEVICES

KING ABDULLAH UNIVERSITY ...

1. A deformable optoelectronic device comprising:a paper substrate comprising a plurality of fold segments arranged in a deformable pattern;
first and second electrode layers attached to a surface of the substrate; and
plural semiconductor nanowire layers configured to detect light and act as photodetectors,
wherein the plural semiconductor nanowire layers are electrically connected, along parallel branches, between the first and second electrode layers, each branch including a subset of the plural semiconductor nanowire layers electrically connected in series, and
wherein the substrate is folded along plural fold lines to form a 3-dimensional structure.

US Pat. No. 10,461,203

SEMICONDUCTOR DEVICES, A FLUID SENSOR AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE

Infineon Technologie AG, ...

1. A semiconductor device, comprising:a quantum well layer stack comprising a plurality of first quantum well layers and a plurality of second quantum well layers, wherein first quantum well layers of the plurality of first quantum well layers and second quantum well layers of the plurality of second quantum well layers are arranged alternatingly on a first semiconductor layer structure,
wherein the first quantum well layers of the plurality of first quantum well layers comprise silicon-germanium and the second quantum well layers of the plurality of second quantum well layers comprise silicon,
wherein the first quantum well layers of the plurality of first quantum well layers and the second quantum well layers of the plurality of second quantum well layers have a thickness of below 100 nm, and
wherein the quantum well layer stack is configured to emit light with a light emission maximum at a wavelength of between 2 ?m and 10 ?m or to absorb light with a light absorption maximum at a wavelength of between 2 ?m and 10 ?m.

US Pat. No. 10,461,202

IN-PLANE RESONANT-CAVITY INFRARED PHOTODETECTORS WITH FULLY-DEPLETED ABSORBERS

The Government of the Uni...

1. A hybrid waveguide comprising a III-V resonant-cavity infrared detector (RCID) photodiode ridge integrated with a waveguide,the waveguide comprising:
a first cladding layer disposed on a substrate;
a core layer disposed on the first cladding layer; and
a second cladding layer disposed on the core layer;
the core layer and second cladding layer being patterned to form air or dielectric regions on each lateral side of the hybrid waveguide, the air or dielectric regions being configured to laterally confine light propagating in the waveguide such that propagation is in a single lateral mode;
and the RCID ridge comprising:
a p+ bottom contact layer disposed on an upper surface of the second cladding layer;
a p-type region disposed on a first area of an upper surface of the bottom contact layer;
an absorber region having a thickness of less than 100 nm disposed on an upper surface of the p-type region;
an n-type region disposed on an upper surface of the absorber region; and
an n+ top contact layer disposed on an upper surface of the n-type region;
the hybrid waveguide further comprising a first distributed Bragg reflector (DBR) grating at a first end and a second DBR grating at a second end, the first and second DBR gratings forming a resonant cavity within the RCID photodiode extending along a length of the hybrid waveguide, the resonant cavity having a resonant wavelength ?R; and
wherein the RCID photodiode is configured to detect infrared light propagating within the hybrid waveguide, the resonant cavity formed by the first and second DBR gratings being configured to increase an effective absorption path of light having at the resonant wavelength ?R travelling through the hybrid waveguide.

US Pat. No. 10,461,200

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

United Microelectronics C...

1. A semiconductor structure, comprising:a substrate;
a light sensing device, disposed in the substrate; and
a light-guiding structure, located above the light sensing device, having a top surface and a bottom surface opposite to each other, wherein the bottom surface is closer to the substrate than the top surface and a position of a minimum width of the light-guiding structure is located between the top surface and the bottom surface.

US Pat. No. 10,461,197

SPUTTERING TARGET, OXIDE SEMICONDUCTOR, OXYNITRIDE SEMICONDUCTOR, AND TRANSISTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:an oxynitride semiconductor layer comprising:
a plurality of first regions; and
a second region,
wherein each region of the plurality of first regions comprises an element M,
wherein the element M is one or more of Al, Si, Y, B, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu,
wherein each region of the plurality of first regions comprises an insulating material as a first main component,
wherein the second region comprises a conductive material as a second main component,
wherein the second region comprises indium,
wherein each region of the plurality of first regions is surrounded by the second region in plan view, and
wherein the plurality of first regions and the second region are arranged in a mosaic pattern.

US Pat. No. 10,461,194

THRESHOLD VOLTAGE CONTROL USING CHANNEL DIGITAL ETCH

International Business Ma...

1. A method for fine-tuning a threshold voltage of a nanosheet structure, the method comprising:forming a nanosheet stack including a plurality of sacrificial layers and a plurality of nanowires;
forming a sacrificial gate structure over the nanosheet stack;
partially etching one or more of the plurality of sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers;
removing the sacrificial gate structure;
removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires;
forming an oxidation channel directly contacting the exposed surface of each of the plurality of nanowires on only either a top side or a bottom side of each of the plurality of nanowires; and
removing the oxidation channels to form a recess on each of the plurality of nanowires.

US Pat. No. 10,461,191

SEMICONDUCTOR DEVICE WITH UNDERCUTTED-GATE AND METHOD OF FABRICATING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A method of fabricating a semiconductor device, comprising following operations:(i) providing a semiconductor substrate having an active area, a shallow trench isolation (STI) structure surrounding the active area, and a doped region located in the active area;
(ii) etching the semiconductor substrate to form a first protrusion structure, a source semiconductor feature, a drain semiconductor feature, and an etched STI structure, wherein the etched STI structure comprises a first portion and a second portion, the second portion of the etched STI structure has a top surface that is higher than a top surface of the first protrusion structure, and the top surface of the first protrusion structure is higher than a top surface of the first portion of the etched STI structure;
(iii) etching the first protrusion structure to form a second protrusion structure, wherein the second protrusion structure has an undercut at a periphery of the active area;
(iv) conformally forming a dielectric layer over the second protrusion structure; and
(v) forming a gate structure crossing over the second protrusion structure, wherein the gate structure extends in a first direction, and the undercut extends in a second direction that is substantially perpendicular to the first direction.

US Pat. No. 10,461,190

METHOD FOR REDUCING CONTACT RESISTANCE IN SEMICONDUCTOR STRUCTURES

Taiwan Semiconductor Manu...

1. A method, comprising:forming a fin over a substrate;
forming, on the fin, a gate structure having a sidewall;
forming a sidewall spacer adjacent to the sidewall;
doping a source/drain (S/D) region adjacent to the sidewall spacer;
depositing a layer of doped amorphous material over the gate structure, the sidewall spacer, and the S/D region; and
crystallizing a portion of the layer of doped amorphous material to form a region of crystallized material that comprises a doping concentration higher than a doping concentration of the S/D region.

US Pat. No. 10,461,188

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor device, comprising:providing a substrate structure, wherein the substrate structure comprises:
a substrate having a first device region and a second device region,
a first dummy gate structure at the first device region,
a second dummy gate structure at the second device region, and
a Lightly Doped Drain (LDD) region below the first dummy gate structure,
wherein the first dummy gate structure comprises:
a first dummy gate dielectric layer at the first device region,
a first dummy gate on the first dummy gate dielectric layer, and
a first spacer layer at a side wall of the first dummy gate, and
wherein the second dummy gate structure comprises:
a second dummy gate dielectric layer at the second device region,
a second dummy gate on the second dummy gate dielectric layer, and
a second spacer layer at a side wall of the second dummy gate;
removing the first dummy gate;
etching back the first spacer layer to reduce a thickness of the first spacer layer such that the thickness of the first spacer layer is smaller than a thickness of the second spacer layer;
removing an exposed portion of the first dummy gate dielectric layer to form a first trench;
removing the second dummy gate after removing the first dummy gate;
removing an exposed portion of the second dummy gate dielectric layer to form a second trench;
depositing a gate dielectric layer to cover a bottom portion and a side wall of the first trench and a bottom portion and a side wall of the second trench; and
before depositing the gate dielectric layer, forming a gate oxide layer only at the bottom portion of the first trench.

US Pat. No. 10,461,186

METHODS OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED CONTACTS AND THE RESULTING STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming a transistor, an isolation region, and an additional isolation region, wherein the transistor has a first end and a second end opposite the first end and comprises: a semiconductor fin that extends vertically between a lower source/drain region in a substrate and an upper source/drain region and horizontally from adjacent the first end of the transistor to adjacent the second end of the transistor; a spacer layer on the lower source/drain region around the semiconductor fin; a gate on the spacer layer around the semiconductor fin; and a source/drain sidewall spacer on the gate around the upper source/drain region and a cap layer on the upper source/drain region, wherein the isolation region extends from within the substrate through the spacer layer and is positioned laterally adjacent to the second end of the transistor, and wherein the additional isolation region is on the spacer layer and positioned laterally adjacent to the first end of the transistor;
forming a dielectric layer on the transistor, the isolation region and the additional isolation region; and
forming a gate contact that extends vertically through the dielectric layer and into the isolation region, the gate contact being positioned laterally immediately adjacent to the gate at the second end of the transistor and having a bottom above a level of the spacer layer.

US Pat. No. 10,461,185

ASSEMBLIES HAVING CONDUCTIVE STRUCTURES ALONG PILLARS OF SEMICONDUCTOR MATERIAL

Micron Technology, Inc., ...

1. An assembly, comprising:pillars of semiconductor material over a base, the pillars of semiconductor material being arranged in rows that extend along a first direction;
the rows further comprising an intervening spacing regions between the pillars of semiconductor material such that the intervening spacing regions alternate with the silicon pillars within each of the rows,
the pillars of semiconductor material having top surfaces at a first maximum height above the base, and the intervening spacing regions comprising spacing structures having top surfaces at a second maximum height above the base, the second maximum height being below the first maximum height;
the rows being spaced from each other by gap regions;
conductive structures within the gap regions between the rows, the conductive structures each extending along the first direction along a plurality of the pillars of semiconductive material, two of the conductive structures being within each of the gap regions and being spaced apart from one another by a separating region, the separating region having a bottom surface that undulates across semiconductor segments and insulative segments, a height of each of the semiconductor segments being higher than that of each of the insulative segments relative to the base;
channel regions within the pillars of semiconductor material;
gates within the conductive structures; and
transistors, with each of the transistors comprising one of the channel regions and at least one of the gates.

US Pat. No. 10,461,183

ULTRA HIGH VOLTAGE SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE CAPABILITIES

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first layer over a semiconductor substrate;
a drain region in the first layer, the drain region comprising
a drain rectangular portion;
a first drain end portion contiguous with the drain rectangular portion and extending from the drain rectangular portion away from a center of the drain region; and
a second drain end portion contiguous with the drain rectangular portion and extending from the drain rectangular portion away from the center of the drain region; and
a source region spaced a distance from and surrounding the drain region in the first layer,
wherein the first drain end portion and the second drain end portion have a same doping type and each of the first drain end portion and the second drain end portion have different doping concentrations from the drain rectangular portion.

US Pat. No. 10,461,182

DRAIN CENTERED LDMOS TRANSISTOR WITH INTEGRATED DUMMY PATTERNS

TEXAS INSTRUMENTS INCORPO...

1. A drain extended transistor, comprisinga plurality of substantially parallel transistor finger structures formed in an active region of a semiconductor substrate, the plurality of transistor finger structures including: a plurality of body region fingers; a plurality of source fingers; a plurality of oxide fingers, a plurality of drain fingers; a plurality of drift region fingers, and a plurality of gate fingers;
individual ones of the plurality of body region fingers including a body region that extends along a first direction into a semiconductor substrate, the body region including: majority carrier dopants of a first type; and a channel portion;
individual ones of the plurality of source fingers including a source region that extends along the first direction into the semiconductor substrate from a first side of the semiconductor substrate, the source region adjacent a first side of the channel portion of the body region, the source region including majority carrier dopants of a second type;
individual ones of the plurality of drain fingers including a drain region that extends along the first direction into the semiconductor substrate from the first side, the drain region including: majority carrier dopants of the second type, and a first end;
individual ones of the plurality of oxide fingers including an oxide structure that extends along the first side of the semiconductor substrate, the oxide structure including: a first end spaced along a second direction from the channel portion of the body region; and a second end adjacent the first end of the drain region, the second direction being orthogonal to the first direction;
individual ones of the plurality of drift region fingers including a drift region, the drift region including majority carrier dopants of the second type, the drift region extending along the first direction into the semiconductor substrate from the first side, the drift region extending along the second direction from the channel portion of the body region to the drain region; the drift region including a drift region portion separated from the first side along the first direction by at least a portion of the oxide structure; and
individual ones of the plurality of gate fingers including a gate structure, the gate structure including: a gate dielectric layer formed over the first side of the substrate; and a gate electrode on the gate dielectric layer at least partially above the channel portion of the body region;
wherein one of the drain fingers is positioned at a center of the drain extended transistor along the second direction.

US Pat. No. 10,461,178

METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an array substrate, comprising steps of:forming patterns of a gate metal layer and a gate insulating layer successively on a base plate;
forming a pattern of a semiconductor layer, wherein the semiconductor layer comprises a first oxide layer and a second oxide layer stacked on the first oxide layer, the first oxide layer is an insulative oxide layer and the second oxide layer is a semiconductive oxide layer, and the first oxide layer is located between the gate insulating layer and the second oxide layer;
forming a pattern of a source and drain metal layer; and
the first oxide layer including a first active region and a first pixel electrode region, the second oxide layer including a second active region and a second pixel electrode region, subjecting the second pixel electrode region of the second oxide layer to plasma treatment, to convert the second pixel electrode region of the second oxide layer into a conductor to form a pixel electrode.

US Pat. No. 10,461,175

TFT-CONTAINING BACKPLATE AND METHOD FOR FABRICATING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A method or fabricating a TFT-containing backplate, comprising: forming a top-gate TFT on a substrate, wherein the top-gate TFT comprises a gate insulating layer which comprises a negative silicone light shielding material,wherein forming the top-gate TFT on the substrate comprises:
depositing a first metal layer on the substrate, and patterning the first metal layer to form a source and a drain;
depositing a metal oxide layer on the substrate on which the source and the drain have been formed;
depositing a first insulating layer on the metal oxide layer, and patterning the first insulating layer by self-alignment exposure to form the gate insulating layer which has an inverted trapezoid cross-sectional shape; and
depositing a second metal layer to form a gate on the gate insulating layer.

US Pat. No. 10,461,173

METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR FORMING SOURCE AND DRAIN REGIONS IN A VERTICAL FIELD EFFECT TRANSISTOR

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a fin above a semiconductor substrate;
forming a structure on a middle portion of each sidewall of the fin, whereby a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; and
forming a first epitaxial region on at least the top of the fin for forming a top source/drain (S/D) region, and a second epitaxial region on the lower portion of each sidewall and on the semiconductor substrate for forming a bottom S/D region, such that the bottom S/D region comprises an elevated subregion on the lower portion of each sidewall of each fin, wherein the elevated subregion is vertically aligned with the top S/D region.

US Pat. No. 10,461,170

METHOD OF FORMING MOSFET STRUCTURE

Taiwan Semiconductor Manu...

1. A method comprising:providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer;
providing a gate layer adjacent to the epitaxial layer and the cap layer;
providing a dielectric layer above the cap layer and the gate layer;
forming a trench above the cap layer by patterning a portion of the dielectric layer above the cap layer, wherein sidewalls of the trench comprise the gate layer and the dielectric layer above the gate layer;
filling the trench with a protection layer; and
removing the protection layer.

US Pat. No. 10,461,169

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a metal gate electrode structure and an insulating layer over a semiconductor substrate, wherein the insulating layer surrounds the metal gate electrode structure; and
nitrifying a first top portion of the metal gate electrode structure to transform the first top portion into a metal nitride layer while nitrifying a second top portion of the insulating layer to transform the second top portion of the insulating layer to a dielectric nitride layer.

US Pat. No. 10,461,168

SEMICONDUCTOR DEVICE FOR COMPENSATING INTERNAL DELAY, METHODS THEREOF, AND DATA PROCESSING SYSTEM HAVING THE SAME

Samsung Electronics Co., ...

1. A method of manufacturing a Fin Field Effect Transistor (FinFET), the method comprising:providing a substrate;
forming an elevated source and an elevated drain on the substrate;
forming a first dielectric layer on the substrate, the first dielectric layer including a gate oxide layer and a high-k dielectric layer disposed on the gate oxide layer, the high-k dielectric layer being U-shaped;
forming a metal buffer layer on the first dielectric layer, the metal buffer layer being U-shaped;
forming a metal gate on the metal buffer layer, the metal gate contacting the metal buffer layer; and
forming a second dielectric layer on the substrate after generating at least a first opening next to the first dielectric layer such that the second dielectric layer contacts the first dielectric layer, wherein
a dielectric constant of the second dielectric layer is less than that of the first dielectric layer, and
a first portion of the first dielectric layer is disposed between the metal buffer layer and the second dielectric layer, and blocks the metal buffer layer to contact the second dielectric layer.

US Pat. No. 10,461,166

ELECTRICAL CONTACT

National University of Si...

1. An electrical contact comprising:(a) a top electrode comprising a non-Newtonian liquid metal alloy; and
(b) a bottom electrode comprising a self-assembled monolayer of molecules (SAM) formed on a metal substrate,
wherein the surface of the SAM layer of the bottom electrode contacting the top electrode is a template-stripped non-patterned surface and the electrical contact has no edge effect;
and the surface of the liquid metal alloy contacting the SAM layer is contained in a polymer insulator and the area of the electrical contact between the liquid metal alloy surface and the SAM layer is determined by modulating the diameter of the liquid metal alloy surface contacting the SAM layer, the diameter being between 15 ?m and 55 ?m.

US Pat. No. 10,461,165

SEMICONDUCTOR DEVICE AND METHOD OF FORMATION

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, comprising:forming a first tube material over a first channel material, the first channel material over a dielectric layer;
forming a second channel material over the first tube material such that the second channel material is in contact with the first channel material;
removing at least some of the dielectric layer from under the first channel material to form a first gate opening;
forming a gate in the first gate opening under the first channel material and around the second channel material; and
performing an annealing operation to form a dielectric tube from the first tube material and to form a channel from the first channel material and the second channel material, wherein the channel surrounds the dielectric tube to enclose an outer perimeter of the dielectric tube.

US Pat. No. 10,461,159

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, the method comprising the steps of:(a) forming a second nitride semiconductor layer on a first nitride semiconductor layer;
(b) forming a third nitride semiconductor layer on the second nitride semiconductor layer;
(c) forming a fourth mesa-type nitride semiconductor layer on the third nitride semiconductor layer;
(d) forming a gate insulating film on the fourth mesa-type nitride semiconductor layer; and
(e) forming a gate electrode on the gate insulating film;
wherein the second nitride semiconductor layer has an electron affinity equal to or larger than electron affinity of the first nitride semiconductor layer,
wherein the third nitride semiconductor layer has an electron affinity smaller than the electron affinity of the first nitride semiconductor layer,
wherein the fourth nitride semiconductor layer has an electron affinity equal to or smaller than the electron affinity of the second nitride semiconductor layer, and
wherein the step (d) includes the steps of:
(d1) forming a first film including a first insulator on the fourth mesa-type nitride semiconductor layer by a sputtering process using a target including the first insulator; and
(d2) forming a second film including a second insulator on the first film by a CVD process.

US Pat. No. 10,461,158

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating film, comprising the steps of:(a) forming a dummy gate electrode of a MISFET over the semiconductor layer;
(b) after the step (a), forming an offset spacer over a side surface of the dummy gate electrode;
(c) after the step (b), forming a side wall over the side surface of the dummy gate electrode via the offset spacer;
(d) after the step (c), forming an interlayer insulating film so as to cover the dummy gate electrode, the offset spacer and the side wall;
(e) after the step (d), exposing an upper surface of the dummy gate electrode and an upper surface of the offset spacer by polishing the interlayer insulating film;
(f) after the step (e), removing the offset spacer in order to form a first opening beside the dummy gate electrode;
(g) after the step (f), forming a first impurity region having a first conductivity type in the semiconductor substrate by an ion implantation method through the first opening;
(h) after the step (g), forming a second impurity region having a second conductivity type opposite to the first conductivity type in the semiconductor layer by an ion implantation method through the first opening; and
(i) after the step (h), replacing the dummy gate electrode with a metal material, thereby to form a metal gate electrode of the MISFET.

US Pat. No. 10,461,157

FLAT GATE COMMUTATED THYRISTOR

ABB Schweiz AG, Baden (C...

1. A turn-off power semiconductor device comprising:a semiconductor wafer having a first main side and a second main side opposite to the first main side;
a plurality of thyristor cells, each of the plurality of thyristor cells comprising in the order from the first main side to the second main side:
(a) a cathode region of a first conductivity type;
(b) a base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region;
(c) a drift layer of the first conductivity type forming a second p-n junction with the base layer; and
(d) an anode layer of the second conductivity type separated from the base layer by the drift layer,
wherein each thyristor cell comprises: a gate electrode which is arranged lateral to the cathode region and forms an ohmic contact with the base layer; a cathode electrode arranged on the first main side and forming an ohmic contact with the cathode region; and an anode electrode arranged on the second main side and forming an ohmic contact with the anode layer,
wherein interfaces between the cathode regions and the cathode electrodes and interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar, and
wherein the base layer includes a gate well region extending from its contact with the gate electrode to a depth (dW) which is at least half of a depth (dC) of the cathode region,
wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 ?m from the cathode region, and
the base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein a ratio between the density of first conductivity type impurities and the net doping concentration in the compensated region is at least 0.4.

US Pat. No. 10,461,155

EPITAXIAL REGION FOR EMBEDDED SOURCE/DRAIN REGION HAVING UNIFORM THICKNESS

GLOBALFOUNDRIES INC., Gr...

9. A method of forming a source/drain region comprising:forming a first spacer material layer on a P-type field effect transistor (PFET) region of a substrate and an N-type field effect transistor (NFET) region of the substrate, the NFET region including a gate structure positioned on the substrate;
forming a mask above the first spacer material layer in the PFET region;
forming an opening in the first spacer material layer and the substrate adjacent to the gate structure in the NFET region;
removing the mask;
forming a first epitaxial region in at least a portion of the opening;
forming a second spacer material layer on the first spacer material layer and on a portion of an uppermost surface of the first epitaxial region adjacent to the gate structure;
removing a first portion of the first epitaxial region using the second spacer material layer as a mask, wherein after removing the first portion a remaining portion of the first epitaxial region includes a substantially uniform sidewall thickness; and
forming a second epitaxial region abutting the remaining portion of the first epitaxial region in the opening to form the source/drain region.

US Pat. No. 10,461,148

MULTILAYER BURIED METAL-INSULTOR-METAL CAPACITOR STRUCTURES

International Business Ma...

1. A method comprising:providing an insulator layer overlying a semiconductor substrate;
forming a plurality of alternating first conductive layers and second conductive layers on the insulator layer;
forming at least one dielectric layer between each of the alternating first conductive layers and second conductive layers;
forming a first trench at a first location through a first portion of the plurality of the alternating first conductive layers and second conductive layers and the at least one dielectric layer; and
etching the first trench selective to the plurality of alternating first conductive layers and second conductive layers, wherein the first conductive layers are etched faster than the second conductive layers to form a first modified trench, wherein the first conductive layers are recessed relative to the center of the first trench greater than the second conductive layers, wherein each of the plurality of the recessed first conductive layers and the second recessed second conductive layers are in continuous contact with the at least one dielectric layer between each of the alternating recessed first conductive layers and the second recessed second conductive layers.

US Pat. No. 10,461,145

METHOD FOR FABRICATING MAGNETIC CORE

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a magnetic core, comprising:depositing a magnetic layer on a dielectric layer;
forming a first photoresist layer on the magnetic layer and patterning the first photoresist layer;
etching the magnetic layer through the patterned first photoresist layer, wherein a first section of the magnetic layer exposed by the patterned first photoresist layer remains on the dielectric layer after etching the magnetic layer;
removing the patterned first photoresist layer;
forming a second photoresist layer on the magnetic layer and patterning the second photoresist layer such that the patterned second photoresist layer has a curve portion;
etching the magnetic layer through the patterned second photoresist layer such that the curve portion of the patterned second photoresist layer suspends without support above the magnetic layer; and
removing the patterned second photoresist layer.

US Pat. No. 10,461,143

TRANSISTOR SUBSTRATE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING THE TRANSISTOR SUBSTRATE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a pixel electrode;
a common electrode overlapping the pixel electrode;
a light emitting layer positioned between the pixel electrode and the common electrode;
a base substrate;
a data line disposed on the base substrate;
a conductive layer disposed on the base substrate and being spaced from the data line;
a semiconductor layer overlapping the conductive layer, being spaced from the conductive layer, and comprising a source electrode and a drain electrode, wherein the source electrode is electrically connected to the data line, and wherein the drain electrode is electrically connected to the pixel electrode; and
a gate electrode overlapping the semiconductor layer,
wherein the base substrate is a single layer structure or a multilayer structure having a polymer.

US Pat. No. 10,461,138

ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

BOE Technology Group Co.,...

1. An organic light-emitting display device, comprising:a substrate;
a plurality of pixel definition strips disposed on the substrate, wherein the plurality of pixel definition strips are spaced apart from and arranged in parallel with each other, and two adjacent pixel definition strips among the plurality of pixel definition strips and a portion of the substrate between the two adjacent pixel definition strips constitute a pixel definition groove; and
an organic light-emitting functional layer disposed in the pixel definition groove, wherein the organic light-emitting functional layer comprises a plurality of sub organic light-emitting functional layers which are insulated with each other and arranged along an extension direction of the plurality of pixel definition strips.

US Pat. No. 10,461,137

ORGANIC ELECTROLUMINESCENT DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME

BOE Technology Group Co.,...

1. An organic electroluminescent display panel, comprising a substrate, and a pixel defining layer and a light emitting layer on the substrate, wherein:the pixel defining layer comprises a first pixel defining layer on the substrate, a second pixel defining layer on the first pixel defining layer, and a third pixel defining layer between the first pixel defining layer and the second pixel defining layer;
the first pixel defining layer comprises a plurality of first opening areas, each of which defines a sub-pixel light emitting area, and the light emitting layer is arranged in the plurality of first opening areas;
the second pixel defining layer comprises a plurality of second opening areas, each of which defines a virtual pixel area comprising at least two adjacent sub-pixel light emitting areas in a same color; and
the third pixel defining layer comprises a plurality of third opening areas corresponding to the plurality of first opening areas in a one-to-one manner, and each of the plurality of third opening areas is not larger than a corresponding first opening area;
wherein respective virtual pixel areas defined by the plurality of second opening areas comprise a same number of sub-pixel light emitting areas; and virtual pixel areas containing red sub-pixel light emitting areas, virtual pixel areas containing green sub-pixel light emitting areas, and virtual pixel areas containing blue sub-pixel light emitting areas are disposed alternately in each row of the respective virtual pixel areas; and
wherein sidewalls of respective first opening areas, respective second opening areas, and respective third opening areas are sloped, top areas of the respective first opening areas and the respective third opening areas are smaller than their corresponding bottom areas, and top areas of the respective second opening areas are greater than their corresponding bottom areas.

US Pat. No. 10,461,135

FLEXIBLE DISPLAY PANEL AND FABRICATION METHOD THEREOF, AND FLEXIBLE DISPLAY DEVICE

Shanghai Tianma Micro-Ele...

11. A flexible display device including a flexible display panel, wherein the flexible display panel comprises:a stacked structure having a plurality of layers comprising a flexible substrate, a light-emitting device layer, and a polarizing layer stacked in a preset order;
at least one upper-side resistive force-sensitive electrode disposed on a layer above a neutral plane of the stacked structure; and
at least one lower-side resistive force-sensitive electrode disposed on a layer below the neutral plane, wherein:
each upper-side resistive force-sensitive electrode includes a first resistive force-sensitive electrode and a second resistive force-sensitive electrode,
each lower-side resistive force-sensitive electrode includes a third resistive force-sensitive electrode and a fourth resistive force-sensitive electrode,
the first resistive force-sensitive electrode, the second resistive force-sensitive electrode, the third resistive force-sensitive electrode, and the fourth resistive force-sensitive electrode are electrically connected to form a bridge circuit,
the bridge circuit further includes a positive terminal, a negative terminal, a first voltage terminal, and a second voltage terminal,
one end of the first resistive force-sensitive electrode being electrically connected to one end of the third resistive force-sensitive electrode,
one end of the second resistive force-sensitive electrode being electrically connected to one end of the fourth resistive force-sensitive electrode,
another end of the first resistive force-sensitive electrode being electrically connected to another end of the fourth resistive force-sensitive electrode,
another end of the third resistive force-sensitive electrode being electrically connected to another end of the second resistive force-sensitive electrode,
a connection node between the first resistive force-sensitive electrode and the third resistive force-sensitive electrode is connected to one of the positive terminal and the negative terminal,
a connection node between the second resistive force-sensitive electrode and the fourth resistive force-sensitive electrode is connected to the other one of the positive terminal and the negative terminal,
a connection node between the first resistive force-sensitive electrode and the fourth resistive force-sensitive electrode is connected to the first voltage terminal, and
a connection node between the third resistive force-sensitive electrode and the second resistive force-sensitive electrode is connected to the second voltage terminal.

US Pat. No. 10,461,133

LIGHT EMITTING DISPLAY DEVICE INCLUDING AN INFRARED RAY LIGHT EMITTING DIODE

Samsung Display Co., Ltd....

1. A light emitting display device comprising:a first electrode on a substrate;
a second electrode overlapping the first electrode;
a red emission layer, a green emission layer, a blue emission layer, and an infrared ray emission layer between the first electrode and the second electrode and emitting light of different wavelengths from each other;
a green resonance auxiliary layer between the green emission layer and the first electrode; and
a blocking layer between the green resonance auxiliary layer and the green emission layer,
wherein the infrared ray emission layer and the green resonance auxiliary layer comprise the same material,
the green emission layer comprises a green light emitting dopant, and
a Lowest Unoccupied Molecular Orbital (LUMO) energy of the blocking layer is larger than a LUMO energy of the green light emitting dopant.

US Pat. No. 10,461,131

QUANTUM DOT LED AND OLED INTEGRATION FOR HIGH EFFICIENCY DISPLAYS

Apple Inc., Cupertino, C...

1. A display comprising:a tandem hybrid pixel including an organic light emitting diode (OLED) subpixel and a quantum dot light emitting diode (QD-LED) subpixel;
a common hole transport layer in the OLED subpixel and the QD-LED subpixel;
a common quantum dot layer over the common hole transport layer in the QD-LED subpixel and in the OLED subpixel;
a semi-common charge generation layer over the common quantum dot layer in the OLED subpixel;
a first cathode over the common quantum dot layer in the QD-LED subpixel;
a semi-common hole transport layer over the semi-common charge generation layer in the OLED subpixel;
an organic emission layer over the semi-common hole transport layer in the OLED subpixel;
a semi-common electron transport layer over the organic emission layer in the OLED subpixel; and
a semi-common second cathode over the semi-common electron transport layer in the OLED subpixel.

US Pat. No. 10,461,130

IMAGE DEVICE INCLUDING PHOTOELECTRIC CONVERSION LAYER

PANASONIC INTELLECTUAL PR...

1. An imaging device comprising unit pixels, each unit pixel including:a photoelectric conversion unit including
a first electrode including a first conducting material,
a second electrode facing the first electrode,
a photoelectric conversion layer between the first and second electrodes, the photoelectric conversion layer including a first photoelectric conversion material, and
an electron-blocking layer between the first electrode and the photoelectric conversion layer, the electron-blocking layer including an electron-blocking material; and
a signal detection circuit electrically connected to the first electrode, wherein
the electron-blocking material has an ionization potential higher than both a work function of the first conducting material and an ionization potential of the first photoelectric conversion material,
the photoelectric conversion unit is adapted to be applied with a voltage between the first electrode and the second electrode, and the photoelectric conversion unit has a characteristic, responsive to the voltage within a range from a first voltage to a second voltage, showing that a density of current passing between the first electrode and the second electrode when light is incident on the photoelectric conversion layer becomes substantially equal to that when no light is incident on the photoelectric conversion layer, and
a difference between the first voltage and the second voltage is 0.5 V or more.

US Pat. No. 10,461,129

DEVICE FOR DETECTING ELECTROMAGNETIC RADIATION CONSISTING OF ORGANIC MATERIALS

ISORG, Grenoble (FR)

1. An electromagnetic radiation detection device comprising: at least one row of photoresistors, each photoresistor comprising an active portion comprising organic semiconductor materials; emitters of the electromagnetic radiation; and a waveguide; wherein the waveguide comprises at least one surface intended to be in contact with at least one object, the photoresistors being distributed along an edge of said surface, the emitters being located along said edge.

US Pat. No. 10,461,123

LIGHT EMITTING DEVICE AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A light emitting device, comprising:a substrate;
a light emitting element on the substrate, the light emitting element having a first end portion and a second end portion arranged in a longitudinal direction;
one or more partition walls disposed on the substrate, the one or more partition walls being spaced apart from the light emitting element;
a first reflection electrode adjacent the first end portion of the light emitting element;
a second reflection electrode adjacent the second end portion of the light emitting element;
a first contact electrode directly connected to the first reflection electrode and the first end portion of the light emitting element;
an insulating layer on the first contact electrode, the insulating layer having an opening exposing the second end portion of the light emitting element and the second reflection electrode to the outside; and
a second contact electrode on the insulating layer, the second contact electrode being connected to the second reflection electrode and the second end portion of the light emitting element through the opening.

US Pat. No. 10,461,120

DISPLAY DEVICE AND METHOD FOR PRODUCING A DISPLAY DEVICE

OSRAM Opto Semiconductors...

1. A pixel headlight comprising:a carrier; and
a semiconductor layer sequence having a major face facing the carrier, the semiconductor layer sequence comprising a first semiconductor layer, a second semiconductor layer, and an active region arranged between the first semiconductor layer and the second semiconductor layer, the active region adapted to generate radiation and form a plurality of pixels;
wherein the semiconductor layer sequence comprises a recess that extends from the major face of the semiconductor layer sequence through the active region into the first semiconductor layer and is provided for electrical contacting of the first semiconductor layer; and
wherein the carrier comprises a plurality of switches that are integrated into the carrier, each switch provided for controlling at least one pixel.

US Pat. No. 10,461,118

METHOD FOR MAKING CMOS IMAGE SENSOR INCLUDING PHOTODIODES WITH OVERLYING SUPERLATTICES TO REDUCE CROSSTALK

ATOMERA INCORPORATED, Lo...

15. A method for making a CMOS image sensor comprising:forming a plurality of laterally adjacent photodiodes on a semiconductor substrate by
forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type,
forming a first well around a periphery of the retrograde well also having the second conductivity type,
forming a second well within the retrograde well having the first conductivity type, and
forming first and second superlattices respectively overlying each of the first and second wells, each of the first and second superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

US Pat. No. 10,461,108

IMAGING DEVICE

Hitachi, Ltd., Tokyo (JP...

1. An imaging device comprising:a modulator with a first pantoscopic grating pattern, the modulator configured to modulate light intensity by passage through the first pantoscopic grating pattern;
an image sensor configured to convert light passing through the modulator, to image data, and output the image data; and
an image processor configured to conduct image processing of restoring an image with the use of the image data output from the image sensor,
wherein the first pantoscopic grating pattern is configured to comprise multiple basic patterns, and
each of the basic patterns has the shape of a concentric circle, and
wherein the modulator comprises a first polarization plate and a second polarization plate,
the first polarization plate is disposed closer to a surface configured to serve as an input face of the modulator,
the second polarization plate is disposed closer to a rear surface configured to serve as an output face of the modulator, and
the first polarization plate and the second polarization plate have polarizing axes determined on the basis of an arrangement of the basic patterns.

US Pat. No. 10,461,107

IMAGE PICKUP ELEMENT, IMAGE PICKUP DEVICE, MANUFACTURING DEVICE AND METHOD

Sony Corporation, Tokyo ...

1. An image pickup element comprising:a non-planar layer between a microlens and a filter, the filter and the microlens touch the non-planar layer,
wherein a refractive index of the microlens is greater than a refractive index of the non-planar layer, the refractive index of the non-planar layer is greater than a refractive index of the filter.

US Pat. No. 10,461,101

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:an oxide semiconductor layer over a first insulating film;
the oxide semiconductor layer comprising a first region and a second region;
a transistor over an insulating surface, the transistor including:
a source electrode layer and a drain electrode layer;
a second insulating film over the first region; and
a gate electrode layer over the first region with the second insulating film therebetween;
a transparent conductive film overlapping with the second region;
a dielectric between the second region and the transparent conductive film; and
a capacitor comprising
the second region;
the transparent conductive film; and
the dielectric serving as a dielectric of the capacitor,
wherein the dielectric is in direct contact with a side edge surface of the second insulating film, a first electrode of the capacitor, and a second electrode of the capacitor.

US Pat. No. 10,461,096

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display apparatus comprising:a substrate having a central area and a peripheral area disposed adjacent to the central area, the central area comprising a display area;
at least one semiconductive layer or one conductive layer in the display area;
a first insulating layer disposed in the peripheral area of the substrate, the first insulating layer covering at least one of the at least one semiconductive layer or the one conductive layer;
at least one pattern corresponding to a region of the first insulating layer;
a cover layer on the first insulating layer and covering the at least one pattern in the peripheral area, the cover layer comprising an insulating material; and
an encapsulating layer on the display area, at least one layer of the encapsulating layer is spaced apart from the cover layer.

US Pat. No. 10,461,095

FERROELECTRIC NON-VOLATILE MEMORY

SanDisk Technologies LLC,...

1. A non-volatile storage element comprising:a control gate;
a blocking layer comprising a ferroelectric material;
a charge storage region; and
a tunneling layer,
wherein the blocking layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer, and
wherein the blocking layer comprises doped hafnium oxide including crystal grains that may be switched between a first polarization state to a second polarization state.

US Pat. No. 10,461,094

3D MEMORY DEVICE

Trinandable S.r.l., Mila...

8. A three-dimensional, 3D, memory device comprising:a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an alignment of strings of memory cells extending along a first direction, said rows following one another along a second direction, wherein each string of memory cells comprises a stack of memory cells, said strings of memory cells of the stack extending along a third direction from a first end to a second end;
a source region at the second end of the strings of memory cells;
wherein rows of strings of memory cells consecutive along said second direction are spaced apart from each other of a pitch and arranged in “zigzag” along said second direction;
wherein between pairs of said rows of strings of memory cells consecutive along said second direction a slit is formed which extend in said third direction from said first end to said source region; and
wherein said slit has size, along said second direction, less than, equal to or greater than said pitch, sufficient for the formation, in said slit, of an electrical contact to the source region.

US Pat. No. 10,461,093

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a plurality of conducting layers and a plurality of insulating layers that are alternately disposed above a semiconductor substrate;
a plurality of pillars that extend through the alternately-disposed layers of the conductive layers and the insulating layers in a first direction which crosses a surface of the semiconductor substrate, the plurality of pillars being arranged in a second direction along the surface of the semiconductor substrate; and
a plate that extends through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, extends in the second direction, and is disposed apart from the plurality of pillars in a third direction along the surface of the semiconductor substrate, the third direction being different from the second direction,
wherein the plate has convex portions and non-convex portions alternately arranged on a side of the plate in the second direction, the convex portions and the non-convex portions both extend through the alternately-disposed layers of the conductive layers and the insulating layers in the first direction, and the convex portions and at least part of the plurality of pillars are arranged in a staggered manner.

US Pat. No. 10,461,092

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a stacked body including:
a first stacked unit and a second stacked unit stacked above the first stacked unit, each of the first and second stacked units including a plurality of electrode layers alternately stacked with a plurality of first insulating layers therebetween, and
an intermediate insulating layer provided above the first stacked unit and below the second stacked unit; and
a columnar member piercing the stacked body in a stacking direction of the stacked body, the columnar member including an intermediate columnar part inside the intermediate insulating layer; wherein
a diameter of the intermediate columnar part in a first direction perpendicular to the stacking direction is broadened downwardly to a predetermined depth in a diameter broadening portion of the columnar member, a sidewall of the diameter broadening portion of the columnar member having a curved shape in a cross section along the stacking direction, the diameter of the intermediate columnar part being broadened downwardly on both sides of the diameter broadening portion in the first direction, and wherein
the predetermined depth does not reach any electrode layers functioning as word lines in the first stacked unit, memory cells being provided at intersections of the word lines and the columnar member.

US Pat. No. 10,461,090

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a substrate;
a plurality of first conductive films stacked in a first direction above the substrate and extend in a second direction intersecting the first direction and in a third direction intersecting the first direction and the second direction;
a memory columnar body extending in the first direction and having a side surface covered by the plurality of first conductive films; and
a first structure extending in the second direction and dividing the plurality of first conductive films in the third direction, a length of the first structure in the second direction being greater than a length of the first structure in the third direction, and the length of the first structure in the second direction being equal to or greater than a length of the plurality of first conductive films in the second direction,
each of the memory columnar body and the first structure comprising:
a memory insulating film provided on a side surface of at least one of the plurality of first conductive films; and
a first semiconductor layer provided on a side surface of the memory insulating film.

US Pat. No. 10,461,088

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:forming a gate stack and a conductive layer over a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region isolated from each other by an isolation structure in the semiconductor substrate, the gate stack is formed over the first region, and the conductive layer is formed over the second region and the isolation structure;
forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer;
forming a mask layer over the negative photoresist layer and the conductive layer, wherein the mask layer has trenches over the second portion of the conductive layer, wherein the mask layer over the conductive layer is thicker than the mask layer over the negative photoresist layer;
removing the second portion through the trenches;
removing the mask layer; and
removing the negative photoresist layer.

US Pat. No. 10,461,084

COMPACT SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED NUMBER OF CONTACTS, METHODS OF OPERATING AND METHODS OF MAKING

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:a link or string of semiconductor memory cells, wherein each said semiconductor memory cell comprises:
a floating body region for storing charge indicating a state of said semiconductor memory cell; and
a back-bias region;
wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels;
wherein said link or string comprises at least one contact configured to electrically connect said semiconductor memory cells to at least one control line;
wherein a number of said at least one contact is the same as or less than a number of said semiconductor memory cells in said link or string; and
a control circuitry configured to apply said voltage to said back-bias region.

US Pat. No. 10,461,080

METHOD FOR MANUFACTURING A FINFET DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:etching a semiconductor substrate of a wafer to form at least one fin;
forming an insulation structure around the fin;
recessing the fin;
epitaxially growing an epitaxial channel structure over the recessed fin;
removing a portion of the epitaxial channel structure over a top surface of the insulation structure;
performing a non-contact-type cleaning operation to clean a top surface of the wafer after removing said portion of the epitaxial channel structure;
cleaning the top surface of the wafer using hydrogen fluoride after removing said portion of the epitaxial channel structure; and
recessing the insulation structure such that the epitaxial channel structure protrudes from the recessed insulation structure.

US Pat. No. 10,461,067

THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES

GLOBALFOUNDRIES INC., Gr...

1. A device comprising:integrated circuit (IC) chips, comprising a logic chip and at least one memory stack adjacent the logic chip, attached to an upper surface of a substrate;
a lid thermally connected to an upper surface of the IC chips by a first thermal interface material (TIM1);
a slit formed through the lid by punch and die at a boundary between the logic chip and each memory stack;
a heat sink thermally connected to the lid by a second thermal interface material (TIM2);
at least one co-axial hole formed in the lid and the heat sink; and
a vertical heat pipe extending through each co-axial hole for direct thermal contact with an IC chip and the heat sink.

US Pat. No. 10,461,066

STRUCTURE AND METHOD FOR HYBRID OPTICAL PACKAGE WITH GLASS TOP COVER

Maxim Integrated Products...

1. An optical package, comprising:a package substrate comprising at least one of: at least one die attach pad, at least one vent hole configured to prevent pop-corning of the panel level substrate or at least one pedestal;
an application specific integrated circuit (ASIC) die disposed on the package substrate, the application specific integrated circuit die including a detector;
at least one non-optical sensor die disposed on the package substrate;
a pre-molded polymer panel unit cell disposed on and coupled to the package substrate using a first adhesive film element, the pre-molded polymer panel unit cell including multiple sidewalls that form an outer perimeter and a middle sidewall that defines two cavities, the ASIC die disposed in a first cavity and the at least one non-optical sensor die disposed in a second cavity, the middle sidewall configured to restrict cross talk between the application specific integrated circuit die and the at least one non-optical sensor die, the middle sidewall further comprising a shelf-structure; and
an individual glass cover disposed on the pre-molded polymer panel unit cell, where the glass cover is transparent to an electro-magnetic spectral region detected by the ASIC die and the at least one non-optical sensor die, the individual glass cover adhesively bonded directly to the pre-molded polymer panel unit cell using a second adhesive film element, the individual glass cover adhesively bonded directly to the shelf-structure using a third adhesive film element.

US Pat. No. 10,461,065

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device, the method comprising:mounting a plurality of light emitting elements on a collective substrate;
arranging at least one light transmissive member for each light emitting device on an upper surface of each of the plurality of light emitting elements;
arranging a first protruding member that surrounds the plurality of light emitting elements on an upper surface of the collective substrate;
arranging a second protruding member between the plurality of light emitting elements on the upper surface of the collective substrate;
after the arranging the first protruding member and the second protruding member, forming a cover member that covers an upper end of the second protruding member, the light emitting elements, and a lateral surface of the light transmissive member in a region surrounded by the first protruding member; and
singulating the light emitting devices by dividing the cover member, the second protruding member, and the collective substrate at a portion including the second protruding member;
wherein an upper end of the second protruding member is located in the region surrounded by the first protruding member so as to be lower than an upper end of the first protruding member but higher than the upper surface of each of the light emitting elements, and
wherein the second protruding member is harder than the cover member.

US Pat. No. 10,461,060

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH REDISTRIBUTION LAYERS

Taiwan Semiconductor Manu...

1. A chip package, comprising:a semiconductor die;
a protective layer surrounding the semiconductor die;
an interface between the semiconductor die and the protective layer; and
a conductive layer over the protective layer and the semiconductor die, wherein the conductive layer has a first portion and a second portion, the first portion is closer to an inner portion of the semiconductor die than the second portion, the first portion is in direct contact with the second portion, the second portion extends across the interface, and in a top view of the conductive layer, the second portion has a line width greater than that of the first portion.

US Pat. No. 10,461,059

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH IMPROVED THERMAL PERFORMANCE AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A semiconductor die assembly, comprising:a thermally conductive casing;
a package substrate comprising a plurality of first raised bond pads that each have a first vertical height, wherein the package substrate and the thermally conductive casing together define an enclosure;
an interposer having a front side surface and an opposing back side surface, the back side surface attached to the thermally conductive casing within the enclosure and the front side surface comprising a plurality of second raised bond pads that each have a second vertical height;
a stack of semiconductor dies having a stack height disposed between the front side surface of the interposer and the package substrate within the enclosure; and
a plurality of conductive members interposed between the plurality of first raised bond pads and the plurality of second raised bond pads, wherein each conductive member of the plurality of conductive members include a solder bump having a third vertical height, and wherein a sum of the first, second, and third vertical heights is about equal to or greater than the stack height of the stack of semiconductor dies.

US Pat. No. 10,461,058

METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC DEVICE USING DEVICE CHIP

SHASHIN KAGAKU CO., LTD.,...

1. A method of manufacturing electronic devices comprising:a preparation step for preparing a first substrate having a first adhesive layer and a second substrate having a second adhesive layer, the first adhesive layer including a surface where a plurality of device chips are adhered;
a first take-out step for making at least part of the device chips on the first substrate come into contact with and adhere to at least part of a selective adhesive region on a third adhesive layer of a first drum and for separating the at least part of the device chips from the first substrate by rotating the first drum; and
a first transfer step for making the device chips on the selective adhesive region come into contact with and adhere to the second adhesive layer and for separating the device chips from the selective adhesive region by rotating the first drum.

US Pat. No. 10,461,057

DUAL-INTERFACE IC CARD MODULE

NXP B.V., Eindhoven (NL)...

1. A dual-interface integrated circuit card module, the module comprising:a substrate having first and second opposing surfaces;
a contact pad on the first surface of the substrate;
an integrated circuit on the second surface of the substrate, the integrated circuit having electrical connections to the contact pad through the substrate; and
a pair of antenna pads for providing electrical contact, disposed in recesses in the second surface of the substrate and electrically connected to corresponding antenna connections on the integrated circuit,
wherein the recesses pass through the substrate, the antenna pads being attached to a back surface of the contact pad with a non-conductive material, the non-conductive material in contact with the antenna pads and the contact pad, and the non-conductive material providing an insulating layer between the antenna pads and the contact pad.

US Pat. No. 10,461,055

CU ALLOY CORE BONDING WIRE WITH PD COATING FOR SEMICONDUCTOR DEVICE

NIPPON MICROMETAL CORPORA...

1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; and
a Pd coating layer formed on a surface of the Cu alloy core material, wherein
the bonding wire contains at least one or more first elements selected from Sb, Bi and Se,
a concentration of the first elements in total is 0.1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire, and
Sb?10 ppm by mass; and Bi?1 ppm by mass, and
the bonding wire contains at least one or more second elements selected from Ni, Zn, Rh, In, Ir, Pt, Ga and Ge, and
a concentration of each of the second elements is 0.011% by mass or more and 1.2% by mass or less relative to the entire wire.

US Pat. No. 10,461,052

COPPER STRUCTURES WITH INTERMETALLIC COATING FOR INTEGRATED CIRCUIT CHIPS

Monolithic Power Systems,...

1. An integrated circuit (IC) chip comprising:a substrate comprising an integrated circuit;
a metal pad disposed on the substrate and electrically connects to the integrated circuit;
a redistribution layer that electrically connects to the metal pad;
a copper pillar that is disposed on and electrically connects to the redistribution layer;
a solder bump that is disposed on and electrically connects to the copper pillar; and
a tin-copper intermetallic coating that is formed on a surface of the copper pillar and the redistribution layer.

US Pat. No. 10,461,050

BONDING PAD STRUCTURE OF A SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor chip;
a metal electrode formed on a surface of the semiconductor chip; and
metal wiring connected to the metal electrode via a bonding part,
wherein an outer peripheral of the metal wiring is covered with a metal layer consisting of a metal or an alloy different from a constituent metal of the metal electrode,
the bonding part has an alloy region harder than the metal wiring, and
the metal layer is formed on an upper surface and a lower surface of at least the metal wiring, and a part of the lower surface contacts the bonding part.

US Pat. No. 10,461,049

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor substrate;
an aluminum electrode provided on the semiconductor substrate;
a metallic film for a solder joint provided on the aluminum electrode; and
an organic protective film provided on the aluminum electrode and apart from the metallic film,
wherein an interval between the organic protective film and the metallic film is equal to or greater than half of a thickness of the organic protective film.

US Pat. No. 10,461,047

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

Intel Corporation, Santa...

1. A semiconductor structure, comprising:a substrate having an insulating layer disposed thereon, the substrate having a perimeter;
a metallization structure disposed on the insulating layer, the metallization structure comprising conductive routing disposed in a dielectric material stack, wherein an uppermost layer of the metallization structure comprises first and second pluralities of conductive pads thereon;
a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing;
a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring; and
a metal-free region of the dielectric material stack surrounding the second metal guard ring, the metal-free region disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

US Pat. No. 10,461,043

METHOD OF MANUFACTURING AN ELECTROMAGNETIC SHIELD

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a precursor package having a plurality of integrated circuit (IC) modules, wherein:
an inter-module area is horizontally in between two adjacent IC modules of the plurality of IC modules; and
each of the plurality of IC modules comprises a module substrate and at least one electronic component that is attached to a top surface of the module substrate and encapsulated by a mold compound, wherein the module substrate comprises a ground plane formed within the module substrate, and a plurality of first input/output (I/O) contacts formed at a bottom surface of the module substrate;
placing the precursor package onto a chemical resistant tape, such that the plurality of first I/O contacts of each module substrate are sealed and against the chemical resistant tape;
performing a sweller process on the precursor package, which resides over the chemical resistant tape;
performing a desmear process on the precursor package, which resides over the chemical resistant tape;
removing the chemical resistant tape to expose the plurality of first I/O contacts;
singulating the precursor package at each inter-module area to form a plurality of individual IC modules, each of which comprises the module substrate;
placing the individual IC modules onto a top surface of a carrier tape, such that the plurality of first I/O contacts of each individual IC module are sealed and against the carrier tape; and
applying a shielding structure completely over a top surface and side surfaces of each of the plurality of individual IC modules to form a plurality of shielded IC modules, wherein the shielding structure is electrically coupled to the ground plane within the corresponding module substrate.

US Pat. No. 10,461,040

MATCHED CERAMIC CAPACITOR STRUCTURES

APPLE INC., Cupertino, C...

1. A capacitor device comprising:a first capacitor comprising a first and a second electrical termination and first and second stacks of electrodes; and
a second capacitor comprising a third and a fourth electrical termination and third and fourth stacks of electrodes, wherein the first stack is disposed atop the third stack, the third stack is disposed atop the second stack, and the second stack is disposed atop the fourth stack;
wherein the first stack comprises:
a first set of electrodes, each respective electrode of the first set comprising a respective tab that couples each respective electrode to the first electrical termination; and
a second set of electrodes, each respective electrode of the second set comprising a respective tab that couples each respective electrode to the second electrical termination, wherein each electrode of the second set is disposed between two electrodes of the first set of electrodes;
the second stack comprises:
a third set of electrodes, each respective electrode of the third set comprising a respective tab that couples each respective electrode to the first electrical termination; and
a fourth set of electrodes, each respective electrode of the fourth set comprising a respective tab that couples each respective electrode to the second electrical termination, wherein each electrode of the fourth set is disposed between two electrodes of the third set of electrodes;
the third stack comprises:
a fifth set of electrodes, each respective electrode of the fifth set comprising a respective tab that couples each respective electrode to the third electrical termination; and
a sixth set of electrodes, each respective electrode of the sixth set comprising a respective tab that couples each respective electrode to the fourth electrical termination, wherein each electrode of the sixth set is disposed between two electrodes of the fifth set of electrodes; and
the fourth stack comprises:
a seventh set of electrodes, each respective electrode of the seventh set comprising a respective tab that couples each respective electrode to the third electrical termination; and
an eighth set of electrodes, each respective electrode of the eighth set comprising a respective tab that couples each respective electrode to the fourth electrical termination, wherein each electrode of eighth set is disposed between two electrodes of the seventh set of electrodes; and
wherein a body of the capacitor device comprises a right prism shape that comprises:
a square base comprising a bottom of the body of the capacitor device;
a first side comprising the first electrical termination;
a second side distinct from the first side, comprising the second electrical termination;
a third side distinct from the first and the second side, comprising the third electrical termination; and
a fourth side distinct from the first, the second, and the third side, comprising the fourth electrical termination.

US Pat. No. 10,461,039

MARK, METHOD FOR FORMING SAME, AND EXPOSURE APPARATUS

NIKON CORPORATION, Tokyo...

1. A method for producing a device comprising:forming a pre-pattern on a mark formation area of a substrate;
applying a polymer layer containing a block copolymer to the pre-pattern;
allowing the polymer layer, applied to the pre-pattern, to form a self-assembled area;
selectively removing a portion of the self-assembled area;
forming an alignment mark by using the self-assembled area from which the portion of the self-assembled area has been removed;
illuminating the alignment mark formed on the substrate with an illumination light;
detecting the alignment mark by receiving a light from the alignment mark with a detector; and
changing a polarization state of the illumination light.

US Pat. No. 10,461,038

METHODS OF ALIGNMENT MARKING SEMICONDUCTOR WAFERS, AND SEMICONDUCTOR PACKAGES HAVING PORTIONS OF ALIGNMENT MARKINGS

Micron Technology, Inc., ...

1. A method for alignment marking a semiconductor wafer, comprising:defining die locations associated with the semiconductor wafer, and defining alignment mark locations between the die locations;
forming first alignment marks within the alignment mark locations at a first level of processing associated with the semiconductor wafer; the first alignment marks comprising first segments extending primarily along a first direction, and comprising second segments extending primarily along a second direction substantially orthogonal to the first direction;
forming second alignment marks within the alignment mark locations at a second level of processing associated with the semiconductor wafer; the second level of processing being subsequent to the first level of processing; the second alignment marks comprising third segments extending primarily along the first direction, and comprising fourth segments extending primarily along the second direction; and
forming a texture within the alignment mark locations, the texture having a pattern other than lines extending along either the first or second direction.

US Pat. No. 10,461,030

PAD STRUCTURES AND WIRING STRUCTURES IN A VERTICAL TYPE SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A pad structure of a vertical type semiconductor device, comprising:a plurality of conductive patterns stacked in a vertical direction from a top surface of a substrate, the plurality of conductive patterns including a first group including a plurality of first conductive patterns and a plurality of second conductive patterns for confirming process disposed between the plurality of first conductive patterns included in the first group; and
a plurality of insulation patterns between the plurality of conductive patterns in the vertical direction,
wherein edge portions of the plurality of conductive patterns stacked including a first stepped shape portion having first steps in a first direction, the first direction being an extension direction of the plurality of first and second conductive patterns, and a second stepped shape portion having second steps in a second direction substantially perpendicular to the first direction, and
wherein one of the plurality of first conductive patterns has a first exposed region on a first top surface thereof that is adjacent to a first edge thereof in the first direction,
one of the plurality of second conductive patterns, which is immediately below the one of the plurality of first conductive patterns, has a second exposed region on a second top surface thereof that is adjacent to a second edge thereof in the first direction,
a first length of the first exposed region in the first direction is different from a second length of the second exposed region in the first direction, and
the one of the plurality of first conductive patterns has a first edge shape without a dent at the first edge thereof, and the one of the plurality of second conductive patterns has a second edge shape with a dent at one side of the second edge thereof such that a protrusion corresponding to the second exposed region is provided.

US Pat. No. 10,461,027

SEMICONDUCTOR DEVICE INCLUDING VIA PLUG AND METHOD OF FORMING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a lower insulating layer on a substrate;
a conductive pattern in the lower insulating layer;
a middle insulating layer on the lower insulating layer and the conductive pattern;
a via control region in the middle insulating layer, the via control region having a lower etch rate than the middle insulating layer;
an upper insulating layer on the middle insulating layer and the via control region; and
a via plug passing through the via control region and connected to the conductive pattern.

US Pat. No. 10,461,025

LOW COST METALLIZATION DURING FABRICATION OF AN INTEGRATED CIRCUIT (IC)

Skyworks Solutions, Inc.,...

1. An integrated circuit comprising:a wafer having a front surface and a back surface;
a via hole etched on the wafer;
a metal layer deposited along walls of the via hole, the metal layer electrically connects the front surface and the back surface; and
a seed metal layer deposited on the back surface of the wafer, the seed metal layer deposited prior to a photoresist layer and thickened after removal of the photoresist layer.

US Pat. No. 10,461,024

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a laminated substrate including an insulating substrate and a circuit board provided on a main surface of the insulating substrate, the circuit board including a first circuit pattern;
a hollow case provided on an outer edge of the laminated substrate, the laminated substrate being surrounded by the hollow case in a plan view of the semiconductor device;
a first lead frame having a first end soldered directly to the first circuit pattern, and another end provided outside the case, the first lead frame extending through the case such that the first end is located inward of an inside surface of the case and the second end is located outward of an outside surface of the case; and
a semiconductor element soldered directly to the first lead frame inside the case.

US Pat. No. 10,461,018

INTEGRATED MULTI-CHAMBER HEAT EXCHANGER

Lockheed Martin Corporati...

1. A method of cooling a component with a heat exchanger configured to provide multi-mode cooling, the method comprising:arranging the heat exchanger adjacent to the component, wherein the heat exchanger comprises a first inlet, a first outlet, a second inlet, a second outlet, and a plurality of channels, wherein the plurality of channels includes a first set of channels configured to provide cooling in a first cooling mode using a first coolant medium and a second set of channels configured to provide cooling in a second cooling mode using a second coolant medium having different thermal properties than the first coolant medium;
circulating the first coolant medium through the first set of channels such that the first coolant medium flows between the first inlet and the first outlet; and
circulating the second coolant medium through the second set of channels such that the second coolant medium flows between the second inlet and the second outlet.

US Pat. No. 10,461,014

HEAT SPREADING DEVICE AND METHOD

Taiwan Semiconductor Manu...

19. A method comprising:attaching a die stack to an interposer, the die stack comprising active devices, the interposer comprising interconnect structures, the interconnect structures of the interposer being electrically coupled to the active devices of the die stack after the attaching the die stack to the interposer;
encapsulating the die stack with an encapsulant;
forming a dummy through substrate via (TSV) in the die stack;
plating dummy metallization on the dummy TSV, the die stack, and the encapsulant;
forming a conductive feature on the dummy metallization, wherein the dummy TSV, the dummy metallization, and the conductive feature are electrically isolated from the active devices of the die stack and the interconnect structures of the interposer;
dispensing a thermal interface material around the conductive feature and on the dummy metallization; and
attaching a heat spreader to the die stack with the thermal interface material, the thermal interface material, the dummy metallization, and the conductive feature thermally coupling the heat spreader to the dummy TSV.

US Pat. No. 10,461,011

MICROELECTRONICS PACKAGE WITH AN INTEGRATED HEAT SPREADER HAVING INDENTATIONS

Intel Corporation, Santa...

13. A method of manufacturing a microelectronics package, the method comprising:attaching a first die, a second die, and a third die to a substrate;
forming a first indentation in a first surface of an integrated heat spreader;
forming a second indentation in the integrated heat spreader; and
attaching the integrated heat spreader to the first die, the second die, and the third die such that:
the first indentation is located in between the first die and the second die, and
the second indentation is located in between the third die and the first die and the second die.

US Pat. No. 10,461,009

3DIC PACKAGING WITH HOT SPOT THERMAL MANAGEMENT FEATURES

Taiwan Semiconductor Manu...

1. A package comprising:a die stack comprising:
a plurality of first dies; and
a second die bonded to the plurality of first dies, wherein a first portion of the second die is disposed directly under the plurality of first dies, and wherein a second portion of the second die extends laterally past sidewalls of the plurality of first dies; and
a package substrate, wherein the die stack is bonded to a top surface of the package substrate by a plurality of conductive connectors, and wherein the package substrate comprises:
a conductive line extending continuously from the plurality of conductive connectors to a thermal interface material (TIM) at the top surface of the package substrate; and
a solder resist, wherein the solder resist covers a first portion of the conductive line and does not cover a second portion of the conductive line, and wherein the TIM extends through the solder resist to contact the second portion of the conductive line.

US Pat. No. 10,461,008

ELECTRONIC COMPONENT PACKAGE HAVING STRESS ALLEVIATION STRUCTURE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer;
a semiconductor chip disposed on the wiring part;
a frame disposed on the wiring part, having upper and lower surfaces opposing each other, and including a component disposition region defined by an inner wall of the frame surrounding the semiconductor chip; and
an encapsulant filling at least a portion of the component disposition region,
wherein a portion of the inner wall of the frame has first and second protrusions, made of an insulating material and disposed on opposite sides of the semiconductor chip, protruding toward the semiconductor chip,
each of the first and second protrusions has an upper surface, a lower surface opposing the upper surface, and an end surface connecting the upper and lower surfaces of a respective one of the first and second protrusions and opposing the inner wall of the frame, the semiconductor chip disposed between the end surfaces of the first and second protrusions,
the upper surface of the frame and the upper surface of each of the first and second protrusions have a first step, and the lower surface of the frame and the lower surface of each of the first and second protrusions have a second step,
the encapsulant extends continuously from the upper surface of the frame to the second step and passes the first step, a space between the first protrusion and the semiconductor chip, and a space between the second protrusion and the semiconductor chip, and
no electrically conductive pattern is disposed directly on the upper surface or the lower surface of each of the first and second protrusions to be electrically connected to the semiconductor chip.

US Pat. No. 10,461,007

SEMICONDUCTOR PACKAGE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING

Intel Corporation, Santa...

1. A microelectronics package, comprising:a substrate having a top substrate surface and a substrate outer periphery, the top substrate surface having an electronic component mounted thereon and the top substrate surface having a conductive trace along at least a portion of the substrate outer periphery;
a molding compound provided over the top substrate surface, having a bottom molding surface, a top molding surface, and a molding sidewall substantially overlying the substrate outer periphery;
a metallic sheet provided over the top molding surface; and
epoxy provided on the molding sidewall, wherein the epoxy includes conductive particles, and wherein the epoxy is electrically coupled to the metallic sheet, wherein the electronic component is a first electronic component, and wherein the microelectronics package further comprises:
a second electronic component; and
a conductive structure electrically connected to the conductive trace and the
metallic sheet, and disposed between the first electronic component and the second electronic component in a trench formed in the molding extending from the bottom molding surface to the top molding surface.

US Pat. No. 10,461,005

SEMICONDUCTOR PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a dielectric layer having a first surface and a second surface opposite to the first surface; and
a conductive post disposed in the dielectric layer, the conductive post comprising a first portion and a second portion disposed above the first portion, the second portion of the conductive post being recessed from the second surface of the dielectric layer,
wherein the second surface of the dielectric layer has an arithmetic average surface roughness (Ra) value, and wherein the Ra value is greater than approximately 450 nanometers (nm).

US Pat. No. 10,460,997

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method of manufacturing a semiconductor device, comprising:providing a semiconductor substrate, wherein the semiconductor substrate comprises at least one fin structure;
forming a patterned mask layer on the fin structure, wherein the patterned mask layer comprises an opening corresponding to a part of the fin structure in a vertical direction;
performing an etching process with the patterned mask layer as a mask for forming a trench in the fin structure;
performing a pullback process to the patterned mask layer for enlarging the opening of the patterned mask layer; and
forming an isolation structure in the trench and the enlarged opening of the patterned mask layer.

US Pat. No. 10,460,996

FIN FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for fabricating a fin field effect transistor (FinFET), comprising:providing a plurality of discrete fins on a semiconductor substrate;
forming a dummy gate across a length portion of the fins and covering portions of top and sidewall surfaces of the fins;
forming an interlayer dielectric layer, covering the dummy gate and the fins;
forming an opening in the interlayer dielectric layer by removing the dummy gate;
forming a gate dielectric layer in the opening and on the interlayer dielectric layer;
forming a barrier layer on the gate dielectric layer;
removing a portion of the gate dielectric layer on the interlayer dielectric layer and a portion of the barrier layer on the interlayer dielectric layer;
performing an annealing treatment after removing the portion of the gate dielectric layer on the interlayer dielectric layer and the portion of the barrier layer on the interlayer dielectric layer;
removing a remaining portion of the barrier layer in the opening after performing the annealing treatment; and
forming a metal gate in the opening.

US Pat. No. 10,460,995

METHOD OF MANUFACTURE OF A FINFET DEVICE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:depositing a first dummy gate stack and a second dummy gate stack, wherein the first dummy gate stack has a first channel length and the second dummy gate stack has a second channel length different from the first channel length;
depositing an interlayer dielectric around the first dummy gate stack and the second dummy gate stack;
planarizing the first dummy gate stack, the second dummy gate stack and the interlayer dielectric;
after planarizing the first dummy gate stack, implanting ions into the interlayer dielectric to form an implanted region;
after implanting ions into the interlayer dielectric, removing the first dummy gate stack and the second dummy gate stack to form a first opening and a second opening, wherein the removing the first dummy gate stack and the second dummy gate stack reduces a height of the interlayer dielectric; and
filling the first opening and the second opening with a conductive material.

US Pat. No. 10,460,991

RESIN PACKAGE SUBSTRATE PROCESSING METHOD

DISCO CORPORATION, Tokyo...

1. A resin package substrate processing method for processing a resin package substrate including a mold resin in which a filler having a plurality of filler particles is mixed, said resin package substrate processing method comprising:a fixing step of fixing said resin package substrate through an expandable adhesive tape to an annular frame having an inside opening in the condition where said resin package substrate is positioned in said inside opening of said annular frame;
a dividing step of applying a laser beam having an absorption wavelength to said mold resin of said resin package substrate, to said mold resin after performing said fixing step, thereby forming a plurality of division grooves and dividing said resin package substrate into a plurality of chips;
an interchip distance increasing step of expanding said adhesive tape after performing said dividing step, thereby increasing the distance between any adjacent ones of said chips to a distance greater than or equal to a maximum diameter of said filler particles caught between said adjacent chips; and
a cleaning step of supplying a cleaning liquid to said resin package substrate after performing said interchip distance increasing step, thereby removing said filler particles caught between said adjacent chips,
whereby when each chip is picked up from said adhesive tape, falling of said filler particles from each chip is prevented.

US Pat. No. 10,460,983

METHOD FOR MANUFACTURING A BONDED SOI WAFER

SHIN-ETSU HANDOTAI CO.,LT...

1. A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, comprising, in sequential order, the steps of:depositing a polycrystalline silicon layer on the bonding surface side of the base wafer,
polishing a surface of the polycrystalline silicon layer,
forming the insulator film on the bonding surface of the bond wafer,
forming an ion-implanted layer in the bond wafer,
bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and
thinning the bonded bond wafer by delaminating along the ion-implanted layer in the bond wafer to form an SOI layer; wherein,
as the base wafer, a silicon single crystal wafer having a resistivity of 100 ?·cm or more is used,
the step for depositing the polycrystalline silicon layer further comprises a stage for previously forming an oxide film on the surface of the base wafer on which the polycrystalline silicon layer is deposited,
the polycrystalline silicon layer is deposited by a method consisting of two growth stages, a first growth performed at a first temperature of 900° C. or more and 1010° C. or less, and a second growth performed at a second temperature of 1100° C. or more to deposit the polycrystalline silicon layer thicker than in the first growth,
deposition of the polycrystalline silicon layer is performed using trichlorosilane as a source gas at atmospheric pressure in the first growth and the second growth,
the oxide film is formed by wet cleaning,
the oxide film has a thickness of 0.3 nm or more and 10 nm or less, and
the polycrystalline silicon layer has a thickness of 2 ?m or more when the base wafer and the bond wafer are bonded.

US Pat. No. 10,460,982

FORMATION OF SEMICONDUCTOR DEVICES WITH DUAL TRENCH ISOLATIONS

International Business Ma...

1. A method for fabricating a semiconductor device with dual trench isolations, comprising:forming a deep trench located between a first region associated with a first array of transistors and a second region associated with a second array of transistors;
forming a first shallow trench located between transistors within the first array and a second shallow trench located between transistors within the second array; and
forming, by a single dielectric material fill process, a deep trench isolation (DTI) region in the deep trench, a first shallow trench isolation (STI) region in the first shallow trench, and a second STI region in the second shallow trench.

US Pat. No. 10,460,976

SUBSTRATE TRANSFER DEVICE AND SUBSTRATE TRANSFER METHOD

TOKYO ELECTRON LIMITED, ...

1. A substrate transfer device, comprising:at least one first supporting portion and at least one second supporting portion configured to support a substrate from below the substrate;
an elevating mechanism configured to elevate the at least one second supporting portion up and down between a first position higher than a height of the at least one first supporting portion, which is maintained fixed, and a second position lower than the height of the at least one first supporting portion;
a control unit configured to control the elevating mechanism; and
a detecting unit configured to detect an external surface of the at least one second supporting portion,
wherein the control unit determines whether the at least one second supporting portion is in a required elevation state based on a detection result of the detecting unit,
the detecting unit includes a light projecting unit configured to irradiate light, and a light receiving unit configured to receive the light irradiated from the light projecting unit, and
the control unit controls the detecting unit to overlap an optical axis of the light with the at least one second supporting portion.

US Pat. No. 10,460,975

VACUUM CHUCK, BEVELING/POLISHING DEVICE, AND SILICON WAFER BEVELING/POLISHING METHOD

SUMCO CORPORATION, Tokyo...

1. A vacuum chuck comprising:a vacuum chuck stage comprising a circular vacuum surface;
a vacuum protection pad provided to the vacuum surface;
an annular or arc-shaped concave portion dividing the vacuum surface into a central region located closer to a center of the vacuum surface and an outer circumferential region located on an outer circumferential side; and
radially-extending concave portions formed in the central region, wherein
the vacuum protection pad has through holes in communication with the radially-extending concave portions, and
the vacuum protection pad is bonded to the vacuum surface at the central region excluding the radially-extending concave portions and is unbonded to the vacuum surface in the outer circumferential region.

US Pat. No. 10,460,972

METHOD OF DETACHING SEMICONDUCTOR MATERIAL FROM A CARRIER AND DEVICE FOR PERFORMING THE METHOD

Infineon Technologies AG,...

1. A method of detaching semiconductor material from a carrier, the method comprising:providing a carrier having attached thereto a layer of semiconductor material, wherein the layer comprises an edge portion;
deflecting the carrier in an area of the carrier, on which the edge portion of the layer of semiconductor material is attached, in a direction having an angle greater than zero with respect to a surface of the layer of semiconductor material; and
guiding an air stream onto the edge portion of the layer of semiconductor material, wherein the air stream impacts on a deflected portion of the carrier, thereby removing only the edge portion of the semiconductor material from the carrier.

US Pat. No. 10,460,965

SUSCEPTOR

MARUWA CO., LTD., Owaria...

1. A susceptor having an upper surface on which a wafer is placed and a lower surface arranged on a side opposite to the upper surface, and configured to be rotated about a spindle which extends in a vertical direction, wherein:a bearing formed of a recessed section receiving the spindle is formed on the lower surface,
the bearing has a shape where the bearing is tip-narrowed toward the upper surface from the lower surface, and
a gap is formed in a side wall of the bearing such that the gap projects toward the outside of the bearing from a fitting surface between the bearing and the spindle in a horizontal direction perpendicular to the vertical direction,
wherein the fitting surface between the bearing and the spindle accounts for 80% or more of an area of a portion of a side surface of the spindle inserted into the bearing,
wherein a distal end portion of the spindle has a tapered shape, and
wherein the spindle engages the bearing at a downstream end of the distal end portion of the spindle where a size of the spindle agrees with a size of the bearing,
wherein the spindle is made of metal having higher thermal conductivity than a material of the susceptor.

US Pat. No. 10,460,964

SUBSTRATE LIQUID PROCESSING APPARATUS AND METHOD, AND COMPUTER-READABLE STORAGE MEDIUM STORED WITH SUBSTRATE LIQUID PROCESSING PROGRAM

Tokyo Electron Limited, ...

1. A substrate liquid processing apparatus comprising:a liquid processing chamber of which a top is opened, and configured to process a substrate with a processing liquid;
a processing liquid supply source connected to the liquid processing chamber through a processing liquid supply path provided with a first flow rate controller, and configured to supply the processing liquid to the liquid processing chamber through the processing liquid supply path;
a diluent supply source connected to the liquid processing chamber through a diluent supply path provided with a second flow rate controller, and configured to supply a diluent for diluting the processing liquid to the liquid processing chamber through the diluent supply path;
a controller configured to control the first flow rate controller and the second flow rate controller;
a concentration sensor connected to the controller, and provided on a circulation path of which both ends are connected with the liquid processing chamber, the concentration sensor being configured to detect a concentration of the processing liquid;
an atmospheric pressure sensor connected to the controller and configured to detect an atmospheric pressure,
wherein the controller is programmed to:
identify a set atmospheric pressure and a set concentration of the processing liquid, respectively;
detect the concentration of the processing liquid and the atmospheric pressure using the concentration sensor and the atmospheric pressure sensor, respectively;
when the detected atmospheric pressure is not equal to the set atmospheric pressure, correct the set concentration of the processing liquid according to the detected atmospheric pressure; and
when the detected concentration of the processing liquid is not equal to the set concentration of the processing liquid, control the second flow rate controller of the diluent supply path such that an amount of the diluent supplied from the diluent supply source to the liquid processing chamber is adjusted, thereby allowing the detected concentration of the processing liquid to become the set concentration of the processing liquid.

US Pat. No. 10,460,962

SUBSTRATE PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus, comprising:a holding plate provided with a first through hole and configured to hold a substrate;
a rotation driving unit configured to rotate the holding plate;
a lift pin provided above the holding plate and configured to support the substrate from below;
a liquid supply unit provided to pass through the first through hole and configured to supply a liquid to a rear surface of the substrate held by the holding plate; and
an elevating device configured to move the lift pin and the liquid supply unit up and down between at a neighboring position where the lift pin and the liquid supply unit are adjacent to the holding plate and the substrate is held and at a distanced position where the lift pin and the liquid supply unit are distanced upwards from the holding plate and the substrate is carried out,
wherein the elevating device comprises a first lifting member configured to move the lift pin to the distanced position,
the first lifting member is in a disconnected state with respect to the lift pin when the lift pin and the liquid supply unit are located at the neighboring position, and
when the lift pin and the liquid supply unit are moved from the neighboring position to the distanced position, the first lifting member is turned from the disconnected state to a connected state where the first lifting member is connected to the lift pin, and the elevating device raises only the lift pin without raising the liquid supply unit for a time during which the first lifting member is moved up to a preset position, where the lift pin comes into contact with the rear surface of the substrate, while being connected to the lift pin, and raises the lift pin and the liquid supply unit for a time during which the first lifting member is raised from the preset position to the distanced position.

US Pat. No. 10,460,959

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A manufacturing method of a package structure, comprising:providing a carrier;
bonding a semiconductor chip on the carrier, wherein the semiconductor chip comprises a plurality of conductive pads exposed at an active surface of the semiconductor chip;
forming an insulating material layer over the carrier and encapsulating the semiconductor chip after the semiconductor chip is bonded on the carrier, wherein the insulating material layer comprises a first surface and a second surface opposite to the first surface, a thickness of the insulating material layer is greater than a thickness of the semiconductor chip, and the plurality of conductive pads are covered by the insulating material layer;
patterning the first surface of the insulating material layer to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer;
forming a plurality of conductive posts in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip, and the plurality of conductive posts extend onto the first surface of the insulating layer;
forming a plurality of conductive vias in the second openings, wherein the plurality of conductive vias extend onto the first surface of the insulating layer;
forming a redistribution layer over the first surface of the insulating material layer, wherein the redistribution layer is electrically connected to the plurality of conductive posts and the plurality of conductive vias;
de-bonding the carrier; and
forming a plurality of conductive terminals on the second surface of the insulating material layer, wherein the plurality of conductive terminals is electrically connected to the redistribution layer through the plurality of conductive vias.

US Pat. No. 10,460,958

METHOD OF MANUFACTURING EMBEDDED PACKAGING WITH PREFORMED VIAS

Invensas Corporation, Sa...

1. A method of forming a microelectronic assembly, comprising:forming a structure including a microelectronic element having a front surface, edge surfaces bounding the front surface, and contacts at the front surface, and substantially rigid metal posts extending in a first direction, the posts disposed between at least one of the edge surfaces and a corresponding edge of the structure, each metal post having a sidewall separating first and second end surfaces of such metal post from one another, the sidewalls of the metal posts having a root mean square (rms) surface roughness of less than about 1 micron; and then,
forming an encapsulation having a thickness extending in the first direction between first and second surfaces of the encapsulation, the encapsulation contacting at least the edge surfaces of the microelectronic element and the sidewalls of the metal posts, wherein the metal posts extend at least partly through the thickness, and the encapsulation electrically insulates adjacent metal posts from one another;
depositing an insulation layer overlying the first surface of the encapsulation and having a thickness extending away from the first surface of the encapsulation;
forming connection elements directly adjacent and extending away from the first end surfaces of the metal posts and through the thickness of the insulation layer, wherein at least some connection elements have cross sections smaller than respective cross sections of the metal posts from which the connection elements extend;
depositing an electrically conductive redistribution structure on the insulation layer, the redistribution structure electrically connecting at least some metal posts with the contacts of the microelectronic element; and
forming terminals at a first side of the microelectronic assembly adjacent to the first surface of the encapsulation, wherein at least some of the at least some connection elements electrically connect at least some of the first end surfaces with corresponding terminals.

US Pat. No. 10,460,955

METHODOLOGY FOR ANNEALING GROUP III-NITRIDE SEMICONDUCTOR DEVICE STRUCTURES USING NOVEL WEIGHTED COVER SYSTEMS

The United States of Amer...

1. A method for preventing the escape of nitrogen from a Group-III nitride semiconductor covered with an annealing cap during annealing, the method comprising:covering the annealing cap on the Group-III nitride semiconductor with a weighted cover system comprising a protective cover placed on top of the capped Group-III nitride semiconductor; and
annealing the Group-III nitride semiconductor while covered with the weighted cover system at a temperate in excess of 1250° C. for at least 30 minutes,
wherein the weighted cover system provides a sufficient force for preventing the escape of nitrogen from the capped Group-III nitride semiconductor and delamination of the annealing cap from the Group-III nitride semiconductor during said annealing; and
wherein the protective cover has sufficient flexibility and sufficient force applied to permit it to conform to the bow or warpage of the capped semiconductor and to maintain intimate contact with the capped semiconductor surface during the annealing.

US Pat. No. 10,460,948

STRESS ASSISTED WET AND DRY EPITAXIAL LIFT OFF

International Business Ma...

1. A method, comprising:providing a sacrificial release layer on a base substrate;
forming a device layer on the sacrificial release layer;
depositing a metal stressor layer on the device layer;
creating a curvature in the device layer and causing the device layer to bend away from the base substrate at a first edge of the device layer such that the device layer remains in contact with the sacrificial release layer at least at a second opposing edge of the device layer;
etching the sacrificial release layer from an end surface thereof as the device layer is caused to bend away from the first edge and as the sacrificial release layer is exposed; and
releasing the device layer and the metal stressor layer from the base substrate.

US Pat. No. 10,460,946

NATURALLY OXIDIZED FILM REMOVING METHOD AND NATURALLY OXIDIZED FILM REMOVING DEVICE

TOKYO ELECTRON LIMITED, ...

1. A method of removing a natural oxide film formed on a surface of a semiconductor layer containing a compound of indium and an element other than indium as a main ingredient, comprising:supplying a first etching gas which is ?-diketone to the semiconductor layer and heating the semiconductor layer to remove an oxide of the indium constituting the natural oxide film; and
supplying a second etching gas to the semiconductor layer and heating the semiconductor layer to remove an oxide of the element other than indium constituting the natural oxide film.

US Pat. No. 10,460,944

FULLY DEPLETED SEMICONDUCTOR ON INSULATOR TRANSISTOR WITH ENHANCED BACK BIASING TUNABILITY

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming a fully depleted semiconductor on insulator device, comprising:
forming a buried dielectric layer over a substrate;
forming a partial structure in which a semiconductor layer is coupled to and over the buried dielectric layer, and a gate structure is coupled to and over the semiconductor layer; and
flipping the partial structure into a flipped orientation with the buried dielectric layer over the semiconductor layer and the semiconductor layer over the gate structure, and removing the substrate to expose buried dielectric layer;
in the flipped orientation, forming a back-gate stack coupled to the buried dielectric layer, comprising forming a back-gate conductor layer of the back-gate stack coupled to and over the buried dielectric layer, forming a ferroelectric material layer coupled to and over the back-gate conductor layer, and forming a back-gate contact layer coupled to and over the ferroelectric material layer.

US Pat. No. 10,460,943

INTEGRATED STRUCTURES HAVING GALLIUM-CONTAINING REGIONS

Micron Technology, Inc., ...

1. An integrated structure, comprising:a conductive gate;
a charge-storage region under the conductive gate;
a tunneling region under the charge-storage region;
a semiconductor-containing channel region under and directly against the tunneling region, the semiconductor-containing channel region comprising monocrystalline silicon and being part of a monocrystalline-silicon substrate that extends laterally outward beyond the charge-storage region along a cross-section; and
wherein the tunneling region includes a dielectric material consisting essentially of SiO2 directly adjacent a gallium-containing material and directly adjacent the semiconductor-containing channel region.

US Pat. No. 10,460,938

METHOD FOR PATTERNING A SUBSTRATE USING A LAYER WITH MULTIPLE MATERIALS

Tokyo Electron Limited, ...

1. A method of patterning a substrate, the method comprising:forming mandrels on a target layer of a substrate, the mandrels being comprised of at least two layers of material, the mandrels including a bottom layer comprised of a first material, and a top layer comprised of a second material different than the first material, the target layer being comprised of a fifth material;
forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers comprised of a third material;
depositing a fill material on the substrate that at least partially fills open spaces defined between the sidewall spacers, the fill material being comprised of a fourth material, wherein the first material, the third material and the fourth material have different etch resistivities compared to each other for one or more particular etch chemistries;
forming a mask on the fill material, the mask defining one or more openings providing uncovered portions of the fill material;
executing an etch process that (i) etches the one or more uncovered portions of the fill material to provide one or more uncovered portions of the top layer of the mandrels, and that (ii) etches the one or more uncovered portions of the top layer of the mandrels, and
subsequent to executing the etch process, executing a chemical-mechanical polishing step that uses the bottom layer of the mandrels as a planarization stop material layer, the chemical-mechanical polishing step removing the third material above a top surface of the bottom layer of the mandrels; and
etching the target layer using the bottom layer and the fill material as a combined etch mask.

US Pat. No. 10,460,936

PHOTO-ASSISTED DEPOSITION OF FLOWABLE FILMS

APPLIED MATERIALS, INC., ...

1. A processing chamber, comprising:a chamber lid;
a UV transparent window disposed in the chamber lid;
a chamber body defining a processing space, the processing space containing a substrate support;
a first UV transparent divider having a plurality of openings;
a gas volume formed between the UV transparent window and the first UV transparent divider, the gas volume fluidly coupled to a first flow channel through which at least one first gas enters the processing chamber;
a distribution volume separated from the gas volume by the first UV transparent divider, the distribution volume being fluidly coupled to a second flow channel through which at least one second gas enters the distribution volume; and
a source of UV radiation directed towards the gas volume, the UV transparent window disposed directly between the source of UV radiation and the gas volume.

US Pat. No. 10,460,933

TWO-STEP PROCESS FOR GAPFILLING HIGH ASPECT RATIO TRENCHES WITH AMORPHOUS SILICON FILM

APPLIED MATERIALS, INC., ...

1. A method for manufacturing a semiconductor device, comprising:positioning a substrate having at least one opening formed in a substrate surface thereof in a processing chamber, wherein the at least one opening is defined by sidewalls and a bottom surface;
conformally depositing a silicon liner layer over the substrate surface and the sidewalls and the bottom surface of the at least one opening;
filling the at least one opening with a flowable silicon film; and
curing the silicon liner layer and the flowable silicon film, wherein the silicon liner layer and the flowable silicon film each comprises amorphous silicon.

US Pat. No. 10,460,932

SEMICONDUCTOR DEVICE WITH AMORPHOUS SILICON FILLED GAPS AND METHODS FOR FORMING

ASM IP Holding B.V., Alm...

1. A method for producing a semiconductor device, comprising:providing in a deposition chamber a substrate having a gap;
depositing an amorphous silicon film onto the substrate having a thickness sufficient to fill the gap, wherein depositing an amorphous silicon film comprises:
heating the substrate to a deposition temperature between 300 and 500° C.; and
providing a feed gas that comprises a first silicon reactant into the deposition chamber, wherein the first reactant deposits silicon forming the amorphous silicon film,
wherein the amorphous silicon film has a hydrogen concentration between 0.1 and 10 at. %,
wherein the amorphous silicon film filling the gap defines voids within the gap; and
reducing a size of, or eliminating, the voids by annealing the amorphous silicon film at a temperature between 500 and 700° C.

US Pat. No. 10,460,931

SEMICONDUCTOR TRANSISTOR HAVING SUPERLATTICE STRUCTURES

Robert Bosch GmbH, Stutt...

1. A transistor, comprising:a substrate of a first doping type;
an epitaxy layer of the first doping type above the substrate;
a channel layer of a second doping type, which differs from the first doping type, above the epitaxy layer;
a plurality of trenches in the channel layer, which have a gate electrode situated within the trenches and are bordered by a source terminal of the first doping type above the channel layer;
a plurality of shielding areas of the second doping type situated below the gate electrode;
wherein the shielding areas form together an interconnection of shielding areas below the trenches and several of the shielding areas are jointly guided to terminals for contacting the shielding areas,
wherein a grid is made up of first cells, which are formed from the channel terminal of the second doping type for contacting the channel layer and a source terminal bordering the channel terminal, the first cells being bordered by trenches, the grid having gaps into which second cells are inserted, which have the terminals for the shielding areas for contacting the interconnection of the shielding areas.

US Pat. No. 10,460,927

METHODS OF FABRICATING A SIOCN LAYER USING A FIRST AND SECOND CARBON PRECURSOR, THE FIRST CARBON PRECURSOR BEING DIFFERENT FROM THE SECOND CARBON PRECURSOR

SAMSUNG ELECTRONICS CO., ...

1. A method of forming a SiOCN material layer, the method comprising:providing a substrate;
providing a silicon precursor onto the substrate;
providing an oxygen reactant onto the substrate;
providing a first carbon precursor onto the substrate;
providing a second carbon precursor onto the substrate; and
providing a nitrogen reactant onto the substrate,
wherein the first carbon precursor and the second carbon precursor are different materials, and
wherein:
the nitrogen reactant and the second carbon precursor are the same material, the silicon precursor and the first carbon precursor include the same material, providing the silicon precursor and providing the first carbon precursor are performed simultaneously, and providing the nitrogen reactant and providing the second carbon precursor are performed simultaneously, or
the silicon precursor and the second carbon precursor are the same material, and providing the silicon precursor and providing the second carbon precursor are performed simultaneously.

US Pat. No. 10,460,925

METHOD FOR PROCESSING SEMICONDUCTOR DEVICE

United Microelectronics C...

1. A method for processing a semiconductor device, wherein the semiconductor device comprises a protruding structure on a substrate, the protruding structure having a nitride spacer at a sidewall, and an epitaxial layer is formed in the substrate adjacent to the protruding structure, the method comprising:removing the nitride spacer on the protruding structure, wherein a portion of the epitaxial layer under the nitride spacer is further exposed;
performing a dilute hydrofluoric acid (DHF) cleaning process over the substrate after removing the nitride spacer, wherein a top surficial portion of the epitaxial layer is removed; and
performing a standard clean (SC) process over the substrate, wherein a native oxide layer is formed on an expose surface of the epitaxial layer.

US Pat. No. 10,460,924

PROCESS FOR PRODUCING A GALLIUM ARSENIDE SUBSTRATE WHICH INCLUDES MARANGONI DRYING

FREIBERGER COMPOUND MATER...

1. A process for producing a surface-treated gallium arsenide substrate, the process comprising the following sequence of steps:a) oxidation treatment of at least one surface of a gallium arsenide substrate in dry condition by means of UV radiation and/or ozone gas;
b-i) contacting the at least one surface of the gallium arsenide substrate with an alkaline aqueous solution;
b-ii) contacting the at least one surface of the gallium arsenide substrate with water;
b-iii) contacting the at least one surface of the gallium arsenide substrate with an acidic aqueous solution comprising ozone as an oxidizing agent, wherein the ozone concentration in the acidic aqueous solution is between 10 ppm and 100 ppm;
b-iv) contacting the at least one surface of the gallium arsenide substrate with water, wherein the water at least initially contains a pH value modifying additive comprising NH3 in an amount to make the water sufficiently basic to remove oxides or prevent oxide formation on the at least one surface; and
c) Marangoni drying of the gallium arsenide substrate.

US Pat. No. 10,460,923

APPARATUS AND METHOD FOR TREATING SUBSTRATE

SEMES CO., LTD., Chungch...

1. A method for liquid-treating a substrate, comprising:a first treatment liquid supplying operation of supplying a first treatment liquid to a treatment location of the substrate, wherein the first treatment liquid includes hydrofluoric acid; and
a wetting operation of, after the first treatment liquid supplying operation, supplying a wetting liquid onto the substrate, wherein the wetting liquid is water,
wherein the wetting operation includes:
a simultaneous supply operation of supplying the wetting liquid to a first location while the first treatment liquid is supplied, and
wherein the first location is a location spaced apart from the treatment location.

US Pat. No. 10,460,922

METHOD AND APPARATUS FOR SUBSTRATE TRANSFER IN A THERMAL TREATMENT CHAMBER

Applied Materials, Inc., ...

1. A method for managing a thermal treatment chamber, comprising:staggering transfer of a first substrate, and a second substrate to a respective first slot, and a respective second slot of a carrier in the thermal treatment chamber via a transfer opening formed in the thermal treatment chamber, the first substrate and the second substrate each having a respective specified anneal time;
moving the carrier to a lowermost position in the thermal treatment chamber using an elevator mechanism coupled to the carrier after each of the first substrate and the second substrate have been transferred; and
timing movement of the carrier from the lowermost position to a position adjacent to the transfer opening using the elevator mechanism such that each of the first substrate and the second substrate are transferred out of the thermal treatment chamber at a respective determined time period for anneal.

US Pat. No. 10,460,921

HIGH LATERAL TO VERTICAL RATIO ETCH PROCESS FOR DEVICE MANUFACTURING

Applied Materials, Inc., ...

1. A system to manufacture an electronic device, comprising:a non-transitory machine-readable storage medium containing instructions which when executed by the system cause the system to perform operations, comprising:
etching a layer stack over a substrate using a photoresist pattern deposited on the layer stack as a first mask,
curing the photoresist pattern, wherein the curing comprises forming a hardened crust layer on a top portion of the photoresist pattern using an ultraviolet light produced by a plasma with the photoresist pattern exposed directly to the plasma without etching the photoresist pattern, wherein the plasma is generated from a process gas comprising a gas selected from a group consisting of C4F6, C4F8, SF6, CF4, and SO2,
slimming the cured photoresist pattern, and
etching the layer stack using the slimmed photoresist pattern as a second mask, wherein the curing and the etching are performed in the same plasma etch chamber.

US Pat. No. 10,460,915

ROTATABLE SUBSTRATE SUPPORT HAVING RADIO FREQUENCY APPLICATOR

APPLIED MATERIALS, INC., ...

1. A plasma processing system comprising:a processing chamber comprising:
a first electrode, wherein the first electrode at least partially defines a plasma cavity within the processing chamber, and
a second electrode, wherein the second electrode defines a plurality of apertures through the second electrode, and wherein the second electrode at least partially defines the plasma cavity within the processing chamber;
a plasma source electrically coupled with the first electrode and configured to generate a plasma within the plasma cavity; and
a substrate support assembly including:
a shaft assembly comprising a rotatable shaft surrounding a central conductive shaft, and an electrically insulative shaft positioned between the central conductive shaft and the rotatable shaft,
a pedestal coupled to the central conductive shaft of the shaft assembly, and
a first rotary connector coupled to the shaft assembly, wherein the first rotary connector comprises a rotatable radio frequency applicator, the rotatable radio frequency applicator comprising:
a first coil member surrounding a rotatable shaft member that is electromagnetically coupled to the shaft assembly during operation, the first coil member being rotatable with the rotatable shaft member during operation,
a second coil member surrounding the first coil member, the second coil member being stationary relative to the first coil member, wherein the first coil member electromagnetically couples with the second coil member when the rotatable radio frequency applicator is energized and provides a radio frequency power to the pedestal through the shaft assembly;
a first ground member coupling the first coil member with a rotatable portion of the shaft assembly; and
a second ground member coupling the second coil member with a stationary portion of the shaft assembly.

US Pat. No. 10,460,913

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

HITACHI HIGH-TECHNOLOGIES...

1. A plasma processing apparatus comprising:a processing chamber which is disposed inside a vacuum container;
a sample stage which is disposed inside the processing chamber and has a top surface for placing a wafer to be processed thereon;
an electric field generating part which generates an electric field supplied into the processing chamber;
a coil which generates a magnetic field for generating plasma inside the processing chamber by an interaction with the electric field; and
a controller which increases or decreases an intensity of the plasma inside the processing chamber by repeatedly causing the intensity of the magnetic field generated by the coil to be at a first value and a second value lower than the first value in respective predetermined intervals,
wherein the wafer is processed while the plasma is repeatedly generated and diffused.

US Pat. No. 10,460,905

BACKSCATTERED ELECTRONS (BSE) IMAGING USING MULTI-BEAM TOOLS

KLA-Tencor Corporation, ...

1. An apparatus, comprising:an electron source;
a beamlet control mechanism configured to produce a plurality of beamlets utilizing electrons provided by the electron source, the beamlet control mechanism further configured to deliver one of the plurality of beamlets toward a target at a time-instance, wherein the beamlet control mechanism comprises at least one of an aperture plate, an aperture array, or one or more blanking devices; and
a detector configured to produce an image of the target at least partially based on electrons backscattered out of the target, wherein the detector is further configured to receive electrons backscattered out of the target for two or more beamlets delivered toward the target at two or more time-instances, wherein the detector is further configured to produce the image of the target at least partially based on a sum of the received backscattered electrons.

US Pat. No. 10,460,901

COOLING SPIRAL GROOVE BEARING ASSEMBLY

General Electric Company,...

1. A bearing assembly comprising:a shell;
a shaft defining a bore therein and rotatably disposed within the shell; and
a cooling tube disposed within the bore of the shaft, the cooling tube including at least one turbulence-inducing feature.

US Pat. No. 10,460,900

X-RAY TUBE DEVICE AND X-RAY CT APPARATUS

Hitachi, Ltd., Tokyo (JP...

1. An X-ray tube device comprising:an anode that is irradiated with an electron beam, thereby emitting X-rays;
a rotary bearing that rotatably supports the anode;
a solid lubrication film which is formed on a front surface of the rotary bearing so as to be mixed with a ferromagnet; and
an attractor that attracts, with a magnetic force, the solid lubrication film that peels off the rotary bearing;
wherein the attractor contains a permanent magnet and the permanent magnet is disposed at a position having a temperature that does not exceed the Curie temperature of the permanent magnet; and
wherein the attractor contains a ferromagnet that is disposed to be in contact with the permanent magnet.

US Pat. No. 10,460,894

GAS CIRCUIT BREAKER

MITSUBISHI ELECTRIC CORPO...

1. A gas circuit breaker comprising:a first tank filled with an insulating gas;
a fixed contact provided inside the first tank;
a movable contact provided inside the first tank and movable between a position in contact with the fixed contact and a position separated from the fixed contact;
a nozzle that ejects the insulating gas toward the fixed contact when the movable contact moves in a first direction, the first direction being a direction in which the movable contact moves from the position in contact with the fixed contact to the position separated from the fixed contact;
a cylindrical body, provided inside the first tank, that guides the gas ejected from the nozzle in a second direction, the second direction being a direction opposite to the first direction; and
a second tank connected to the first tank in the second direction, wherein
the second tank has a cylindrical shape centering on an axis extending in a direction perpendicular to the first direction as a central axis,
the first tank includes an opening formed on one end side thereof along an axis extending in the first direction, said opening being separated from the cylindrical body, and
the insulating gas elected from the nozzle is elected in the first tank and flows into the second tank via the opening.

US Pat. No. 10,460,892

SINGULATED KEYBOARD ASSEMBLIES AND METHODS FOR ASSEMBLING A KEYBOARD

APPLE INC., Cupertino, C...

1. A keyboard assembly, comprising:a feature plate;
a key assembly including a key mechanism and a keycap, the key mechanism being coupled to the keycap and facilitating translation of the keycap in response to a user input, the key mechanism defining an opening and including a protrusion extending into the opening;
a chassis affixed to the feature plate, the chassis comprising a key assembly retaining feature, the protrusion of the key mechanism being coupled to the key assembly retaining feature.

US Pat. No. 10,460,891

KEYBOARD DEVICE AND ELECTRONIC APPARATUS

NEC PERSONAL COMPUTERS, L...

1. A keyboard device comprising:a first sheet-like member;
a membrane sheet disposed on an upper surface of the first sheet-like member;
a second sheet-like member disposed on an upper surface of the membrane sheet and supports the membrane sheet between the first sheet-like member and the second sheet-like member while being movable in an in-plane direction;
a connection member connecting the first sheet-like member and the second sheet-like member;
a plurality of key tops vertically movable and supported by a guide mechanism on an upper surface side of the second sheet-like member and brings the membrane sheet into contact with the second sheet-like member or separates the contact from the second sheet-like member;
a frame member partitioning adjacent key tops and having a lower surface to which the upper surface of the second sheet-like member is bonded and fixed; and
a support between the first sheet-like member and the second sheet-like member and regulates an interval between the first sheet-like member and the second sheet-like member to a dimension larger than a plate thickness of the membrane sheet.

US Pat. No. 10,460,888

DEFEATER ASSEMBLY

1. A cable operated mechanical defeater, said cable operated mechanical defeater comprising in combination:A. a rod assembly, said rod assembly comprising:
a. a first rod guide, said rod guide comprising a first flat plate having a first edge, said first edge containing a top perpendicular tab with a centered opening, a middle perpendicular tab with a centered opening, and a bottom perpendicular tab with a centered opening;
b. a top rod, said top rod comprising a first L-shape, with a foot of said first L-shape perpendicular to said first flat plate said top rod having a top end and a bottom end;
c. a top extension spring, said top extension spring being attached by a first end to said top of said top rod, an opposite end of said top extension spring being releasably attached to said top perpendicular tab;
d. a bottom extension spring, said bottom extension spring being attached to said bottom of said top rod by a first end and said bottom extension spring being attached to a cable at a second end, a first end of said cable being attached to a top arm of a cam lever assembly;
B. said cam lever assembly comprising
a. a base mounting bracket comprising a second L-shaped flat plate having a first edge and a second edge, said first edge having two openings therethrough for insertion of machine screws and said second edge having a middle slot therein;
b. an adjustable mounting bracket comprising a moveable first flat plate, said first flat plate mounted on said base mounting bracket by bolts, said base mounting bracket having a top edge and a bottom edge, a first side edge and a second side edge, said adjustable mounting bracket having two perpendicular tabs at said first side edge, and at least two slotted openings in said second side edge, a stop plate centered in said first flat plate, and a mounting post projecting perpendicular to said adjustable mounting bracket, near said second side edge;
c. rotatably mounted on said mounting post, a cam lever, said cam lever having a first end and a second end, there being a pivot arm rotatably mounted on said second end, said cam lever first end having a defeater striker integrally mounted thereon;
C. an adjustable hook, said adjustable hook having
a. an adjustable hook mounting bracket, said adjustable hook mounting bracket being a third L-shaped flat plate having a first panel and a second panel, said first panel having at least two separated, elongated slots near a top edge and near a bottom edge, and said adjustable hook mounting bracket having an elongated slot near an edge of said second panel,
b. a disconnect hook, said disconnect hook being mounted on the L of said second L-shaped plate;
c. a defeater, said defeater attachable to a latch of a disconnect operating handle.

US Pat. No. 10,460,880

CAPACITORS HAVING ENGINEERED ELECTRODES WITH VERY HIGH ENERGY DENSITY AND ASSOCIATED METHOD

GranBlueTech, L.L.C., Bu...

1. An apparatus comprising:a capacitor that includes:
an anode; and
a cathode,
wherein the cathode has a surface facing the anode that is covered by a first dielectric film having a dielectric constant of at least ten,
wherein the anode has a surface facing the cathode that includes a refractory material,
wherein the cathode is formed by a process that includes photolithography,
wherein the capacitor maintains a vacuum in a region that separates the surface of the anode that includes a refractory material and the first dielectric coating on the cathode, and
wherein the cathode surface maintains an operational emission current of less than one ampere per square meter.

US Pat. No. 10,460,869

MULTI-SERIES CONTINUOUS-FLOW MAGNETOELECTRIC COUPLING PROCESSING SYSTEM AND APPLICATIONS THEREOF

Jiangnan University, Wux...

1. A multi-series continuous-flow magnetoelectric coupling processing system, comprising:more than two stages of induction units, wherein each stage of the induction unit comprises:
a closed iron core,
a primary coil, wound around one side of the closed iron core, and
a secondary coil, wound around an opposite side of the closed iron core and arranged in an induction voltage chamber, wherein the secondary coil comprises an insulation pipe for circulation of a feed liquid, and two ends of the insulation pipe are exposed from the induction voltage chamber and respectively act as a feeding hole and a discharge hole;
a high frequency power supply, in connection with the primary coils of the more than two stages of the induction units and providing excitation voltage for each of the primary coils; and
a feed liquid container, in series connection with the insulation pipes of the more than two stages of the induction units to form a feed liquid circulation loop.

US Pat. No. 10,460,862

MAGNESIUM DIBORIDE SUPERCONDUCTING THIN-FILM WIRE AND METHOD FOR PRODUCING SAME

HITACHI, LTD., Tokyo (JP...

1. A magnesium diboride superconducting thin-film wire, comprising:a long substrate;
a magnesium diboride thin film formed on the long substrate, wherein the magnesium diboride thin film includes magnesium diboride columnar crystal grains; and
a transition metal element layer formed on the magnesium diboride thin film, wherein the transition metal layer is diffused into grain boundaries of the magnesium diboride columnar crystal grains;
wherein:
the magnesium diboride thin film has a microtexture such that the magnesium diboride columnar crystal grains stand densely together on a surface of the long substrate, and
the transition metal element layer is formed from a predetermined transition metal element that has a body-centered cubic lattice structure.

US Pat. No. 10,460,856

BUS MOUNTS, POWER DISTRIBUTION SYSTEMS, AND METHODS FOR MOUNTING BUSES IN POWER DISTRIBUTION SYSTEMS

SIEMENS INDUSTRY, INC., ...

1. A power distribution system, comprising:a bus bar;
a frame member;
a support block formed from a non-conductive material and having a first side and an opposite second side;
one or more first fasteners extending beyond the second side and mechanically coupled to the bus bar;
one or more second fasteners extending beyond the first side and mechanically coupled to the frame member; and
a first insulator located between the first side of the support block and the frame member, wherein the one or more first fasteners do not extend through the first insulator and the one or more second fasteners extend through the first insulator.

US Pat. No. 10,460,853

POWER CABLE AND BUS BAR WITH TRANSITIONAL CROSS SECTIONS

Flex-Cable, Howard City,...

1. A cable assembly comprising:a continuous electrical conductor formed of multi-strands of an electrically conductive material;
a first section of said continuous electrical conductor in which said multi-strands of electrical conductor material are twisted and together form a circular or oval cross section;
a third section of said continuous electrical conductor in which said multi-strands of electrical conductor material are untwisted and individually flattened and together form a square or rectangular cross section; and
a second section of said continuous electrical conductor forming a transitional area in which the cross section of said continuous electrical conductor changes from the circular or oval cross section of said first section to the square or rectangular cross section of said third section.

US Pat. No. 10,460,849

LIGHTWEIGHT, HIGH-CONDUCTIVITY, HEAT-RESISTANT, AND IRON-CONTAINING ALUMINUM WIRE, AND PREPARATION PROCESS THEREOF

CENTRAL SOUTH UNIVERSITY,...

1. A lightweight, high-conductivity, heat-resistant, and iron-containing aluminum wire comprising the following components in percentage by weight:B 0.04-0.10 wt. %;
Zr 0.10-0.15 wt. %;
Fe 0.10-0.20 wt. %;
La 0.05-0.30 wt. %; and
inevitable titanium, vanadium, chromium, and manganese with a total content less than 0.01 wt. %, and aluminum as the remaining.

US Pat. No. 10,460,842

INTERACTIVE AND ANALYTICAL SYSTEM THAT PROVIDES A DYNAMIC TOOL FOR THERAPIES TO PREVENT AND CURE DEMENTIA-RELATED DISEASES

UMETHOD HEALTH, INC., Ra...

1. A method for providing a therapy to a patient to improve cognitive health of the patient, the method comprising:using at least one processor and at least one memory for:
receiving patient information including two or more of personal and family background data, pre-existing conditions, current medications, genomic data, and diagnostic information, the diagnostic information relating to biological mechanisms that define dementia-related diseases as a medical condition or risk of dementia-related diseases;
receiving therapy plan information, the therapy plan information comprising a plurality of individual therapy plans, each individual therapy plan specifying an individual biological mechanism targeted for physiological adjustment, variations found in an effect on the targeted biological mechanism as a function of the patient information, and data quantifying a probability of success of the individual therapy plan;
generating an aggregate therapy plan, the aggregate therapy plan targeting adjustment of a plurality of biological mechanisms using a combination of the individual therapy plans, the aggregate therapy plan comprising an aggregate probability reflecting a likelihood of achieving all targeted adjustments;
receiving diagnostic and testing data associated with the patient, the diagnostic and testing data captured after the patient has undergone treatment according to the aggregate therapy plan;
for each individual therapy plan in the aggregate therapy plan:
determining a value corresponding to the individual biological mechanism in the patient based on the received diagnostic and testing data;
performing a comparison of the value to a recommended range for the value, and
based on the comparison, dynamically adjusting the individual therapy plan for the biological mechanism when the value is within the recommended range; and
generating, for the patient, an adjusted aggregate therapy based on the individual therapy plan adjustments;
administering the adjusted aggregate therapy via communicable links to a mobile device of a therapy provider, wherein the adjusted aggregate therapy enables improvement in the cognitive health of the patient; and
adjusting the therapy plan information based on success of the individual therapy plans of the patient and of other patients;
and
further administering the adjusted aggregate therapy by the therapy provider.

US Pat. No. 10,460,838

AUTOMATED ANATOMICALLY-BASED REPORTING OF MEDICAL IMAGES VIA IMAGE ANNOTATION

INTERNATIONAL BUSINESS MA...

1. Non-transitory computer-readable medium including instructions that, when executed by an electronic processor, cause the electronic processor to perform a set of functions, the set of functions comprising:receiving a first annotation for a medical image;
automatically determining a location within an electronic structured report associated with the first annotation based on a predetermined mapping;
automatically populating the location of the electronic structured report based on the first annotation with medical data associated with the annotation; and
updating the first annotation displayed within the medical image to display the first annotation in a first manner different from a second manner used to display a second annotation within the medical image not mapped to any location within the electronic structured report.

US Pat. No. 10,460,834

SYSTEMS AND METHODS FOR FACILITATING HEALTH RESEARCH USING A PERSONAL WEARABLE DEVICE WITH RESEARCH MODE

Apple Inc., Cupertino, C...

1. A wearable device having an associated user ID, the device comprising:one or more sensors adapted for detecting one or more health parameters of a user when the device is worn by the user;
a wireless communication link adapted for near field/local communication with one or more computing devices including communications for pairing with the one or more computing devices and communications for transmitting one or more health parameters to the one or more computing devices;
user interface for receiving user input and for outputting information indications; and
a control unit for controlling operation of the wearable device in differing modes including:
a standard mode in which the wearable device pairs and communicates with at least one computing device associated with the user ID when within a wireless communication range of the at least one computing device to facilitate communication of a plurality of health data comprising detections of the one or more health parameters obtained from the one or more sensors, and
a health research mode in which the wearable device communicates by secure authenticated communication with at least one other computing device associated with a third party ID associated with a health researcher of a health research study in which the user is a participant, wherein in the health research mode, the wearable device communicates a first set of health data of the plurality of health data that is relevant to the health research study, wherein the communication of the first set of health data is pre-authorized by the user.

US Pat. No. 10,460,824

SEMICONDUCTOR APPARATUS WITH REDUCED RISKS OF CHIP COUNTERFEITING AND NETWORK INVASION

Hiroshi Watanabe, Yokoha...

1. A semiconductor apparatus comprising:a semiconductor chip comprising:
a modular region comprising a plurality of modular areas each comprising a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses; and
a test circuit retrieving the redundant addresses intrinsic to the semiconductor chip by using a special test mode provided by a physical-chip-identification measuring device, wherein a distribution of the retrieved redundant addresses is randomly formed related to a part or an entirety of the modular area of the modular region, wherein the distribution of the retrieved redundant addresses is irreversible, wherein a random number represents physical properties intrinsic to the semiconductor chip and provides a copy protection wherein when another semiconductor chip uses the distribution of the retrieved redundant addresses the another semiconductor chip will malfunction, and
wherein the test circuit outputs the random number generated from the distribution of the retrieved redundant addresses according to a specification code received from the physical-chip-identification measuring device.

US Pat. No. 10,460,816

SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS

Sandisk Technologies LLC,...

1. An apparatus, comprising:a memory structure, comprising:
a plurality of memory cells, and
a write circuit to apply a single programming pulse to a group of memory cells in response to a command; and
command processing logic configured to complete the command in response to the single programming pulse and mark the group for background verification.

US Pat. No. 10,460,812

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device, comprising:a memory cell array including a first memory block,
the first memory block including a first sub block and a second sub block,
the first sub block including a first memory unit and a second memory unit,
the first memory unit including a first drain side selective transistor, a plurality of first memory cells, a first source side selective transistor, a plurality of second memory cells, and a first connecting portion that connects the first memory cells and the second memory cells in series,
the second memory unit including a second drain side selective transistor, a plurality of third memory cells, a second source side selective transistor, a plurality of forth memory cells and a second connecting portion that connects the third memory cells and the fourth memory cells in series;
the second sub block including a third memory unit and a fourth memory unit,
the third memory unit including a third drain side selective transistor, a plurality of fifth memory cells, a third source side selective transistor, a plurality of sixth memory cells and a third connecting portion that connects the fifth memory cells and the sixth memory cells in series;
the fourth memory unit including a fourth drain side selective transistor, a plurality of seventh memory cells, a fourth source side selective transistor, a plurality of eighth memory cells and a fourth connecting portion that connects the seventh memory cells and the eighth memory cells in series;
a first bit line connected to the first drain side selective transistor and the third drain side selective transistor;
a second bit line connected to the second drain side selective transistor and the fourth drain side selective transistor;
a plurality first word lines connected to gates of the first memory cells, gates of the third memory cells, gates of the fifth memory cells, and gates of the seventh memory cells, respectively,
a plurality second word lines connected to gates of the second memory cells, gates of the fourth memory cells, gates of the sixth memory cells, and gates of the eighth memory cells respectively;
a first source side select gate line connected to a gate of the first source side selective transistor and a gate of the second source side selective transistor;
a second source side select gate line connected to a gate of the third source side selective transistor and a gate of the fourth source side selective transistor; and
a control circuit which applies a first voltage to the first bit line and the second bit line, a second voltage which is lower than the first voltage to the first source side select gate line, a third voltage which is higher than the second voltage to the second source side select gate line, a fourth voltage which is lower than the second voltage to the plurality of first word lines and the plurality of second word lines, while erase operation to the first sub block is operated.

US Pat. No. 10,460,804

VOLTAGE-CONTROLLED RESISTIVE DEVICES

Massachusetts Institute o...

1. A memristive element comprising:a conductive material layer disposed in a x-y plane, the conductive material layer being configured to reversibly uptake an amount of at least one ionic species;
a first electrode coupled proximate to a first end of the conductive material layer;
a second electrode coupled proximate to a second end of the conductive material layer, opposite to the first end;
a gate dielectric layer disposed over the conductive material layer, the gate dielectric layer being configured to supply to, or receive from, the conductive material layer, an amount of the at least one ionic species; and
a gate electrode layer disposed over, and in electrical communication with, the gate dielectric material layer;
an inert metal underlayer disposed in electrical communication with the conductive material layer and coupled to the first electrode and the second electrode to shunt a portion of a current flowing between the first electrode and the second electrode;
the gate electrode layer, the gate dielectric layer, and the conductive material layer being configured such that:
a first potential difference applied in a first direction between the gate electrode layer and the conductive material layer modifies a proportionate amount of the at least one ionic species in a portion of the conductive material layer to generate a first memristive state comprising a first lateral resistive state between the first electrode and the second electrode;
a second potential difference applied in a second direction between the gate electrode layer and the conductive material layer modifies a proportionate amount of the at least one ionic species in a portion of the conductive material layer to generate a second memristive state comprising a second lateral resistive state between the first electrode and the second electrode that is different from the first lateral resistive state; and
the memristive element persists in the first memristive state or the second memristive state in response to discontinuance of the first potential difference or the second potential difference, respectively.

US Pat. No. 10,460,799

METHOD OF READING RESISTIVE MEMORY DEVICE

SK hynix Inc., Icheon-si...

1. A method of reading a resistive memory device comprising:preparing a memory cell including a selection element and a variable resistance element, the selection element exhibiting a snap-back behavior on a current-voltage sweep curve for the memory cell;
determining first and second read voltages to be applied to the memory cell within a voltage range in which the selection element maintains a turned-on state, the second read voltage being lower than the first read voltage and the second read voltage being selected in a voltage range in which the selection element exhibits the snap-back behavior;
applying the first read voltage to the memory cell to measure a first cell current;
applying the second read voltage to the memory cell to measure a second cell current; and
determining a resistance state stored in the memory cell based on the first cell current and the second cell current.

US Pat. No. 10,460,793

SEMICONDUCTOR MEMORY DEVICE HAVING CLOCK GENERATION SCHEME BASED ON COMMAND

Samsung Electronics Co., ...

1. A semiconductor memory device comprising:a command decoder configured to decode a command for writing data at a memory cell or reading data from a memory cell;
an internal data clock generating circuit configured to adjust phase of a data clock with a system clock in response to the command, wherein a frequency of the system clock is lower than a frequency of the data clock; and
a pattern generator configured to generate an error detect code (EDC) hold pattern, used for a clock data recovery operation, in response to the command and to output the EDC hold pattern to an external device through EDC hold pattern pins.

US Pat. No. 10,460,783

MAGNETIC STORAGE DEVICE

Toshiba Memory Corporatio...

1. A magnetic storage device comprising:a magnetic wire including a linear magnetic body having first and second magnetic domains whose magnetization directions are variable;
a magnetoresistance element having a first resistance according to the magnetization direction of the first magnetic domain or a second resistance according to the magnetization direction of the second magnetic domain; and
a read circuit that compares the first resistance of the magnetoresistance element with the second resistance of the magnetoresistance element,
wherein the read circuit outputs first data when the first resistance and the second resistance correspond to the same low or high resistance state and outputs second data when the first resistance and the second resistance correspond to different low/high resistance states.

US Pat. No. 10,460,782

INTEGRATED CIRCUITS HAVING SINGLE STATE MEMORY REFERENCE CELLS AND METHODS FOR OPERATING THE SAME

GLOBALFOUNDARIES INC., G...

19. An integrated circuit comprising:a plurality of operational magneto-resistive random access memory (MRAM) cells arranged in an array of rows and columns; and
a plurality of read circuits, wherein each read circuit is associated with a respective MRAM cell and comprises:
an operational power supply node coupled to an operational ground node by an operational bit line, wherein each respective operational MRAM cell is coupled to the operational bit line between the operational power supply node and the operational ground node;
a reference power supply node coupled to a reference ground node by a reference bit line, wherein the reference power supply node is independent of the operational power supply node to apply a constant operational bias current to the operational bit line while a reference bias current is applied to the reference bit line and is scanned from an initial value through intermediate values to an end value;
a reference memory cell coupled to the reference bit line between the reference power supply node and the reference ground node; and
a sense amplifier coupled to the operational bit line between the operational power supply node and the selected operational memory cell and coupled to the reference bit line between the reference power supply node and the reference memory cell.

US Pat. No. 10,460,779

MRAM REFERENCE CELL WITH SHAPE ANISOTROPY TO ESTABLISH A WELL-DEFINED MAGNETIZATION ORIENTATION BETWEEN A REFERENCE LAYER AND A STORAGE LAYER

CROCUS TECHNOLOGY INC., ...

1. An apparatus, comprising:a reference magnetic tunnel junction to produce a reference signal, the reference magnetic tunnel junction with a high aspect ratio including a reference layer in an annealed state to establish permanent magnetization along a minor axis and a storage layer with magnetization along a major axis, wherein the storage layer magnetization is substantially perpendicular to the magnetization along the minor axis, the magnetization orientation between the minor axis and the major axis being maintained by shape anisotropy caused by the high aspect ratio.

US Pat. No. 10,460,778

PERPENDICULAR MAGNETIC TUNNEL JUNCTION MEMORY CELLS HAVING SHARED SOURCE CONTACTS

SPIN MEMORY, INC., Fremo...

1. A magnetic device, comprising:a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor, wherein each of the transistors includes a drain terminal, a source terminal, and a gate terminal, wherein each of the p-MTJ cells has a cylindrical shape;
a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells;
a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, wherein a second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset; and
a first common source line coupled to the drain terminal of each transistor in the first subset.

US Pat. No. 10,460,774

APPARATUS AND METHOD CAPABLE OF REMOVING DUPLICATION WRITE OF DATA IN MEMORY

SK hynix Inc., Gyeonggi-...

1. An apparatus for controlling memory, the apparatus comprising:a memory device; and
a controller functionally coupled to the memory device;
a deduplication table for storing compressed data, a physical block address of the memory device in which non-compressed data corresponding to the compressed data has been written and a count value indicative of a write number of the data,
wherein the controller is suitable for:
compressing program data of a logical block address received in a data write operation;
searching for the compressed data in the deduplication table;
if the compressed data is new, writing the program data in the physical block address of the memory device; and
registering a new entry comprising the compressed data and the physical block address with the deduplication table, the compressed data comprising a hash value obtained by a hash algorithm,
wherein the controller is suitable for:
converting the program data with the logical block address into a hash value;
reading data stored in the physical block address of the memory device mapped to a retrieved hash value if the hash value is searched for in the deduplication table;
comparing the program data with the read data;
assigning another physical block address for writing the program data in the memory device if, as a result of the comparison, it is determined that the program data and the read data are different;
writing the program data in the assigned another physical block address of the memory device; and
additionally registering a new entry comprising the hash value and said another physical block address with the deduplication table, and
wherein the controller is suitable for:
selecting the physical block address mapped to a hash value having a greatest counter value if data is searched for in the deduplication table;
reading data written in the physical block address of the memory device;
selecting another physical block address mapped to a hash value having a counter value of next priority if read data is different from the program data; and
reading data written in said another physical block address of the memory device.

US Pat. No. 10,460,768

BASE UNIT AND DISK DRIVE APPARATUS

NIDEC CORPORATION, Kyoto...

1. A base unit for use in a disk drive apparatus in which a gas with a density lower than that of air is sealed in a housing space defined by a base member and a cover fixed to each other, the base unit comprising:the base member that supports a motor rotatable about a central axis extending in a vertical direction; and
a connector electrically connected to a wire in the housing space; wherein the base member includes:
a recessed portion extending in radial directions and recessed upward from a lower surface of the base member; and
a hole extending through the recessed portion in the vertical direction;
the recessed portion includes a recessed portion loop-shaped surface defining a loop-shaped surface in the radial direction;
the connector is located on a lower side of the recessed portion to cover the hole;
an adhesive is located between the connector and the recessed portion; and
a minimum value of a gap distance in the radial direction between an outer end of the connector and an inner end of the recessed portion in which the outer end of the connector and the inner end of the recessed portion are opposed to each other with the adhesive therebetween is greater than a minimum value of a gap in the vertical direction distance between an upper surface of the connector and the recessed portion loop-shaped surface, in which the upper surface of the connector and the recessed portion loop-shaped surface are opposed to each other with the adhesive therebetween; wherein
the adhesive includes a filler; and
the adhesive extends all the way around the hole.

US Pat. No. 10,460,763

GENERATING AUDIO LOOPS FROM AN AUDIO TRACK

Adobe Inc., San Jose, CA...

1. In a digital media environment comprising pre-recorded electronic audio tracks, a computer-implemented method of generating audio loops, comprising:identifying, by at least one processor of a client device, a plurality of portions of an audio track, wherein each portion of the plurality of portions is a possible audio loop comprising a common beginning beat, and each portion of the plurality of portions comprises a different number of beats;
determining, by the at least one processor, a score for each portion of the plurality of portions of the audio track by determining a similarity of an audio profile of the beginning beat and an audio profile of an ending beat of each portion;
selecting a portion of the audio track from the plurality of portions of the audio track based on the determined score for each portion; and
generating, by the at least one processor, an audio loop using the selected portion of the audio track.

US Pat. No. 10,460,762

CANCELLING ADJACENT TRACK INTERFERENCE SIGNAL WITH DIFFERENT DATA RATE

Seagate Technology LLC, ...

1. An apparatus comprising:a circuit configured to:
receive first underlying data corresponding to a first signal with a first rate;
receive a second signal with a second rate corresponding to second underlying data;
interpolate the first underlying data to generate a plurality of interpolated signals;
determine, for the first signal, a first channel pulse response shape with the first rate;
determine an interference component signal based on the plurality of interpolated signals and the first channel pulse response shape; and
cancel interference in the second signal using the interference component signal to generate a cleaned signal.

US Pat. No. 10,460,760

SHINGLED MAGNETIC RECORDING STORAGE SYSTEM

SEAGATE TECHNOLOGY LLC, ...

1. A method comprising:determining that an off-track write has occurred during writing data to a shingled magnetic recording (SMR) band in a storage device;
identifying unsafe written data in response to determining that the off-track write has occurred;
determining that caching space is available upon identifying the unsafe written data;
continue writing data to the SMR band without a write retry upon determining that caching space is available; and
caching exclusively the unsafe written data to the determined available caching space.

US Pat. No. 10,460,756

MAGNETIC TAPE DEVICE AND HEAD TRACKING SERVO METHOD EMPLOYING TMR ELEMENT SERVO HEAD AND MAGNETIC TAPE WITH CHARACTERIZED MAGNETIC LAYER

FUJIFILM Corporation, To...

1. A magnetic tape device comprising:a magnetic tape; and
a servo head,
wherein the servo head is a magnetic head including a tunnel magnetoresistance effect type element as a servo pattern reading element,
the magnetic tape includes a non-magnetic support, and a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic support,
the magnetic layer includes a servo pattern,
a center line average surface roughness Ra measured regarding a surface of the magnetic layer is equal to or smaller than 2.0 nm,
a logarithmic decrement acquired by a pendulum viscoelasticity test performed regarding the surface of the magnetic layer is equal to or smaller than 0.050, and
?SFD in a longitudinal direction of the magnetic tape calculated by Expression 1 is equal to or smaller than 0.50,
?SFD=SFD25° C.?SFD?190° C.  Expression 1
in Expression 1, the SFD25° C. is a switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of 25° C., and the SFD?190° C. is a switching field distribution SFD measured in a longitudinal direction of the magnetic tape at a temperature of ?190° C.

US Pat. No. 10,460,751

STRIPE HEIGHT LAPPING CONTROL STRUCTURES FOR A MULTIPLE SENSOR ARRAY

WESTERN DIGITAL (FREMONT)...

1. A magnetic read transducer comprising:a first read sensor;
a second read sensor;
a third read sensor;
a first electronic lapping guide associated with the first read sensor to control a stripe height of the first read sensor;
a second electronic lapping guide associated with the second read sensor to control the stripe height of the second read sensor; and
a third electronic lapping guide associated with the third read sensor to control the stripe height of the third read sensor,
wherein the first electronic lapping guide is connected to a common ground connector, and wherein the third electronic lapping guide is connected to a common pad.

US Pat. No. 10,460,747

FREQUENCY BASED AUDIO ANALYSIS USING NEURAL NETWORKS

Google LLC, Mountain Vie...

1. A method for training a neural network that includes a plurality of neural network layers on training data,wherein the neural network is configured to receive linear scale frequency domain features of an audio sample and to process the frequency domain features to generate a neural network output for the audio sample,
wherein the neural network comprises (i) an input convolutional layer that is configured to map linear scale frequency domain features to logarithmic scaled frequency domain features, wherein the mapping from linear scale frequency domain features to logarithmic scaled frequency domain features is defined by one or more convolutional layer filters of the input convolutional layer, and (ii) one or more other neural network layers having respective layer parameters that are configured to process the logarithmic scaled frequency domain features to generate the neural network output, and
wherein the method comprises:
obtaining training data comprising, for each of a plurality of training audio samples, linear scale frequency domain features of the training audio sample and a known output for the training audio sample; and
training the neural network on the training data to adjust the values of the parameters of the other neural network layers and to adjust the one or more convolutional layer filters that define the mapping from linear scale frequency domain features to logarithmic scaled frequency domain features to determine an optimal logarithmic convolutional mapping of linear scale frequency domain features to logarithmic-scaled frequency domain features.

US Pat. No. 10,460,746

SYSTEM, METHOD, AND DEVICE FOR REAL-TIME LANGUAGE DETECTION AND REAL-TIME LANGUAGE HEAT-MAP DATA STRUCTURE CREATION AND/OR MODIFICATION

MOTOROLA SOLUTIONS, INC.,...

1. A method of real-time language detection and language heat map data structure modification, the method comprising:receiving, at an electronic computing device from a first electronic audio source, first audio content;
identifying, by the electronic computing device, a first geographic location of the first audio content as one of a location of the first electronic audio source and a sound localization process calculated as a function of the location of the first electronic audio source;
determining, by the electronic computing device, that the first audio content includes first speech audio;
identifying, by the electronic computing device from the first audio content, a first language in which the first speech audio is spoken and creating a first association between the first geographic location and the first language;
accessing, by the electronic computing device, a real-time language heat-map data structure including at least a second association between the first geographical location and a second language different from the first language;
modifying, by the electronic computing device based on the first audio content, the real-time language heat-map data structure to include the created first association;
taking a further action, by the electronic computing device, as a function of the modified real-time language heat-map data structure comprising at least one of: (i) electronically displaying at least a modified portion of the modified real-time language heat-map data structure at an electronic display coupled to the electronic computing device, (ii) transmitting at least the modified portion of the modified real-time language heat-map data structure to another electronic computing device for further processing, (iii) electronically transmitting a dispatch instruction to a user having a skill or a need in the first language to the first geographic location, and (iv) electronically transmitting a notification to a user having a skill or a need in the first language including identifying the first geographic location and the first language;
identifying a time and/or date associated with receipt of the first audio content; and
modifying a historical language heat-map data structure associated with the time and/or date to include the first association, wherein the historical language heat-map data structure includes a plurality of associations across sequential times and/or dates that track a particular language cluster as it moves across a geographic region.

US Pat. No. 10,460,742

DIGITAL FILTERBANK FOR SPECTRAL ENVELOPE ADJUSTMENT

Dolby International AB, ...

1. An apparatus for processing an audio signal, the apparatus comprising:an input interface for receiving real-valued time-domain samples;
a digital filterbank including an analysis part and a synthesis part, wherein the analysis part converts the real-valued time-domain samples to complex-valued subband samples, and the synthesis part converts the complex-valued subband samples to time-domain output samples;
a first phase shifter for shifting a phase of the complex-valued subband samples by an amount;
a spectral envelope adjuster for modifying at least a portion of a spectral envelope of the audio signal by applying gains to the complex-valued subband samples;
a second phase shifter for unshifting a phase of the complex-valued subband samples by the amount; and
an output interface for outputting the time-domain output samples,
wherein the analysis part includes Ma=32 analysis filters formed by complex-exponential modulation of a prototype filter having a length of N=640, and the analysis part further includes a decimator for maximally decimating the real-valued time-domain input samples,
wherein the synthesis part includes Ms=64 synthesis filters formed by complex-exponential modulation of the prototype filter, and the synthesis part further includes an interpolator for interpolating the complex-valued subband samples,
wherein the amount of shifting and unshifting is chosen to reduce a complexity of the digital filterbank,
wherein the digital filterbank has a system delay D that represents a latency of a signal passing through the analysis part followed by the synthesis part, and D is smaller than the prototype filter length N, and
wherein the apparatus is implemented with one or more hardware elements.

US Pat. No. 10,460,737

METHODS, APPARATUS AND SYSTEMS FOR ENCODING AND DECODING OF MULTI-CHANNEL AUDIO DATA

Dolby Laboratories Licens...

1. A method for decoding an encoded bitstream of multi-channel audio data and associated metadata, the method comprising:decoding the encoded bitstream of multi-channel audio data into multi-channel audio data;
detecting that the multi-channel audio data includes a first Ambisonics format;
transforming the first Ambisonics format of the multi-channel audio data to a second Ambisonics format representation of the multi-channel audio data, wherein the transforming maps the first Ambisonics format of the multi-channel audio data into the second Ambisonics format representation of the multi-channel audio data; and
wherein the detecting is based on at least part of the associated metadata that indicates existence of the first Ambisonics format of the multi-channel audio data.

US Pat. No. 10,460,728

EXPORTING DIALOG-DRIVEN APPLICATIONS TO DIGITAL COMMUNICATION PLATFORMS

Amazon Technologies, Inc....

5. A method, comprising:receiving a launch condition associated with a dialog-driven application from a user, wherein the dialog-driven application is implemented in an application management service; and
causing the launch condition to be registered with one or more digital communication platforms distinct from the application management service, wherein the registration makes the dialog-driven application at the application management service accessible via the one or more digital communication platforms, wherein the registration configures individual ones of the one or more digital communication platforms to perform:
detecting the launch condition in a natural language input to the digital communication platform; and
responsive to the detection, causing data of further natural language input to be routed according to the registration from the digital communication platform to the application management service.

US Pat. No. 10,460,722

ACOUSTIC TRIGGER DETECTION

Amazon Technologies, Inc....

1. A method for selective transmission of sampled audio data to a speech processing server according to detection of an acoustic trigger being represented in the audio data, the method comprising:receiving sampled audio data based on an acoustic signal acquired at one or more microphones in an acoustic environment;
processing the sampled audio data to locate instances of the acoustic trigger in the acoustic signal, the processing of the sampled audio data including
computing a sequence of feature vectors from the sampled audio data, each feature vector in the sequence being associated with a time in the acoustic signal and representing spectral characteristics of the acoustic signal in a vicinity of said time,
for each time of a succession of times, assembling a set of feature vectors each corresponding to a time offset at predetermined offset from said time, providing the set of feature vectors as an input to an artificial neural network, and computing an output from the neural network corresponding to said time, and
processing the outputs from the neural network for the succession of times to determine time locations corresponding to occurrences of the trigger in the acoustic signal;
selecting portions of the sampled audio data for transmission to the speech processing server according to locations of the located instances of the trigger;
transmitting the selected portions of the sampled audio data to the speech processing server;
wherein computing the output of the neural network includes performing a series of data transformations, multiple of the data transformations each including
forming an input to the transformation as a combination of an output from a prior transformation in the series and one or more time delayed outputs from the prior transformations, the input having a number of input data elements,
computing intermediate data elements from the input data elements as a linear transformation of the input data elements, the intermediate data elements having a number of intermediate elements smaller than the number of input data elements, and
determining output elements of the data transformation as a linear transformation of the intermediate data elements followed by an element-wise non-linear transformation, the output elements having a number of output elements greater than the number of intermediate elements.

US Pat. No. 10,460,714

BROADBAND ACOUSTIC ABSORBERS

United States of America ...

1. An apparatus, comprising:acoustic absorber panels located on a plurality of sides of a body to be acoustically dampened, wherein each acoustic absorber panel comprises:
at least one cubic retainer, wherein the cubic retainer is open to a surrounding gaseous environment and capable of receiving sound waves to be acoustically dampened, the cubic retainer comprising:
at least one solid side; and
at least one perforated side permitting sound waves in the surrounding gaseous environment to enter the cubic retainer; and
an acoustic absorber layer disposed within the cubic retainer and comprised of a plurality of reeds, wherein:
the plurality of reeds each comprise a first end, a second end, and a length disposed between the first end and the second end;
the plurality of reeds are natural reeds, synthetic reeds, or a combination of natural and synthetic reeds;
the plurality of reeds are fixed at one end, wherein the length of each of the reeds is substantially perpendicular to the sound waves entering the cubic retainer; and
the plurality of reeds are each open on at least one end to the surrounding gaseous environment;
wherein sound waves entering the cubic retainer are acoustically dampened by the acoustic absorber layer.