US Pat. No. 10,396,400

ELECTROLYTE FOR LITHIUM BATTERY AND LITHIUM BATTERY INCLUDING THE ELECTROLYTE

Samsung SDI Co., Ltd., Y...

1. An electrolyte for a lithium battery, the electrolyte comprising:an organic solvent; and
a compound represented by Formula 1:

wherein, in Formula 1,
X1 to X4 are each independently oxygen (O) or nitrogen (N),
A1 to A4 each independently denote a chemical bond, an unsubstituted or substituted C1-C10 alkylene group, an unsubstituted or substituted C6-C10 arylene group, an unsubstituted or substituted C7-C10 arylalkylene group, an unsubstituted or substituted C2-C10 heteroarylene group, an unsubstituted or substituted C3-C10 heteroarylalkylene group, or an unsubstituted or substituted C4-C10 carbocyclic group, wherein at least one of A1 to A4 is (CH2)a, where a is independently 2 to 4
at least one of R1 to R4 is —C(R5)?Y1, where Y1 is C(R6)(R7), and R5 to R7 are each independently a hydrogen, a C1-C10 alkyl group, a C1-C10 alkoxy group, a C6-C10 aryl group, a C7-C10 arylalkyl group, a C6-C10 aryloxy group, a C2-C10 heteroaryl group, a C3-C10 heteroarylalkyl group, a C2-C10 heteroaryloxy group, a C4-C10 carbocyclic group, or a halogen atom, and
the remaining R1 to R4 are each independently a hydrogen, a C1-C10 alkyl group, a C1-C10 alkoxy group, a C6-C10 aryl group, a C7-C10 arylalkyl group, a C6-C10 aryloxy group, a C2-C10 heteroaryl group, a C3-C10 heteroarylalkyl group, a C2-C10 heteroaryloxy group, a C4-C10 carbocyclic group, or a halogen atom.

US Pat. No. 10,396,398

SECONDARY BATTERY

Samsung SDI Co., Ltd., Y...

1. A secondary battery, comprising:a cathode;
an anode; and
an electrolyte between the cathode and the anode,
wherein the electrolyte includes:
a first electrolyte layer including a first polymer, a first lithium salt, and a first particle inorganic material having an average particle diameter (D50) of less than 500 nm; and
a second electrolyte layer including a second polymer, a second lithium salt, and a second particle inorganic material having an average particle diameter (D50) of 500 nm or greater,
wherein the first electrolyte layer is in a direction facing the anode.

US Pat. No. 10,396,396

LITHIUM-ION CONDUCTIVE GARNET AND METHOD OF MAKING MEMBRANES THEREOF

Corning Incorporated, Co...

1. A method of making a Li-ion conductive cubic garnet, comprising:forming a nitrate source aqueous solution comprising a first nitrate source and a nitrate dopant source;
contacting the nitrate source aqueous solution and a carbohydrate source and heating in a first heating step to form a nano-particle ash;
a second heating step of the nano-particle ash to produce a garnet nanoprecursor;
pelletizing the garnet nanoprecursor to form a Li-ion conductive cubic garnet pellet; and
a third heating step of the garnet pellet to form a dense Li-ion conductive cubic garnet membrane.

US Pat. No. 10,396,393

HIGH SILICA CONTENT SUBSTRATE SUCH AS FOR USE IN THIN-FILM BATTERY

Corning Incorporated, Co...

1. A fused quartz substrate comprising:a first major surface having a surface area greater than 1 mm2;
a second major surface opposite the first major surface;
an outer perimeter surface extending between the first major surface and the second major surface;
at least 90% by weight silica;
an average thickness between the first major surface and the second major surface of less than 500 ?m; and
a width and a length that are less each than 100 m and greater than 1 mm;
a first group of a plurality of raised elongate features formed in the first major surface and extending in the direction of the width, wherein each raised elongate feature of the first group has a length and a width and the length is at least ten times larger than width, wherein the width of each elongate feature of the first group is between 10 mm and 2 ?m; and
a second group of a plurality of raised elongate features formed in the first major surface and extending in the direction of the length, wherein at least some of the raised elongate features of the second group intersect a raised elongate feature of the first group, wherein each raised elongate feature of the second group has a length and a width and the length is at least ten times larger than width, wherein the width of each elongate feature of the second group is between 10 mm and 2 ?m;
wherein at least some of the raised elongate features of the first group and of the second group extend from the surface a distance of at least 10 angstroms beyond the lowest portion of the first major surface;
wherein the surface area of the first major surface is at least 1.5 times the area of the cross-sectional shape defined by the outer perimeter surface of the substrate.

US Pat. No. 10,396,390

FUEL CELL STACK FOR VEHICLE

HONDA MOTOR CO., LTD., T...

1. A fuel cell stack for a vehicle, comprising:a stack body in which a plurality of power generating cells configured to generate electric power by electrochemical reaction of fuel gas and oxidant gas are stacked; and
a stack casing housing the stack body and mounted within a vehicle, the stack casing comprising:
an upper panel which constitutes an upper surface part of the stack casing, the upper panel including:
an outer plate; and
an inner plate arranged between the outer plate and the stack body in a height direction along a height of the vehicle to constitute a flow passage between the outer plate and the inner plate such that the flow passage communicates with an interior of the stack casing and an exterior of the stack casing.

US Pat. No. 10,396,388

SYSTEM AND METHOD FOR STORING AND RELEASING ENERGY

HYDROGENIOUS TECHNOLOGIES...

1. A system for releasing energy in a form of hydrogen comprising:an unloading unit for unloading hydrogen from a loaded carrier medium;
a heat generation unit for generating heat;
a heat storage unit for storing the heat generated by means of the heat generation unit, wherein the heat storage unit is connected with the unloading unit in order to supply heat;
a power generation unit for generating electric power, wherein the power generation unit is connected with the heat generation unit in order to supply electric power for heat generation, wherein the heat from the heat storage unit is delivered directly to the unloading unit.

US Pat. No. 10,396,385

ION EXCHANGING MEMBRANE, METHOD FOR MANUFACTURING THE SAME, AND ENERGY STORAGE DEVICE COMPRISING THE SAME

KOLON INDUSTRIES, INC., ...

1. An ion exchange membrane comprising:a porous support including a plurality of pores; and
an ion conductor filling the pores of the porous support,
wherein the porous support includes micropores having a size of 31 to 1000 ?m, and wherein the micropores having a size of 31 to 1000 ?m constitute 1 to 20% of the total volume of the plurality of pores.

US Pat. No. 10,396,381

THERMOELECTRIC COOPERATION CONTROL METHOD FOR SOFC SYSTEM BASED ON FRACTIONAL ORDER SLIDING MODE VARIABLE STRUCTURE

HUAZHONG UNIVERSITY OF SC...

1. A thermoelectric cooperative control method for a SOFC (solid oxide fuel cell) system based on fractional order sliding mode variable structure, comprising the following steps:S1. Collecting parameters of system states and output under combinations of different input parameters of the SOFC system, acquiring an influence function of steady-state power, temperature, efficiency response characteristics and bypass valve opening BP within a full load interval on efficiency optimization, as well as an efficiency optimization function within a specified load switching interval and under a time-delay condition by a system identification method;
S2. Acquiring a local optimal steady-state operation function, a global optimal function under the steady state developed and formed, and a power tracking function with different switching intervals and different time-delay conditions based on the influence function of steady-state power, temperature, efficiency response characteristics and bypass valve opening BP within a full load interval on efficiency optimization, as well as an efficiency optimization function within a specified load switching interval and under a time-delay condition;
S3. Calculating a sliding mode interval according to the optimal steady-state operation function, the global optimal function under the steady state developed and formed as well as the efficiency optimization function within the specified load switching interval and under a time-delay condition;
S4. Calculating a series reaching law function according to the sliding mode interval, the steady-state power and efficiency response characteristics within a full load interval, an efficiency optimization function within a specified load switching interval and under a time-delay condition as well as a modified optimization function within different switching load intervals and under different time-delay conditions;
S5. Eliminating chattering of the series reaching law function through a fractional order optimization method, and solving the reaching law by calculation.

US Pat. No. 10,396,378

DEVICE AND METHOD FOR IMPROVING STACK PERFORMANCE OF FUEL CELL SYSTEM

Hyundai Motor Company, S...

1. A device for improving stack performance of a fuel cell system, comprising:a fuel cell controller configured to operate a stack of a normal-pressure fuel cell system,
wherein when the fuel cell controller determines that an operating state of the stack is normal and a current intake air pressure is decreased as a result of monitoring the current intake air pressure, a current output, and an exterior air temperature of the stack, the fuel cell controller is configured to increase the amount of air to be supplied into the stack by adjusting a range of a theoretical air ratio which is a theoretical ratio of an air amount to a coolant temperature in the stack,
wherein the fuel cell controller is configured to control a coolant target temperature to maintain a water balance in the stack when the range of the theoretical air ratio is changed.

US Pat. No. 10,396,377

FUEL CELL DEVICE

KYOCERA Corporation, Kyo...

1. A fuel cell device comprising:a fuel cell configured to generate power using a fuel gas and an oxygen-containing gas, the power supplied to an external load;
a fuel gas supply device configured to supply the fuel gas to the fuel cell;
an oxygen-containing gas supply device configured to supply the oxygen-containing gas to the fuel cell;
a combusted space where the fuel gas not used for power generation and wasted from the fuel cell is combusted;
an igniter configured to combust the fuel gas not used for power generation and wasted from the fuel cell; and
a controller configured to control operation of the fuel gas supply device, the oxygen-containing gas supply device, and the igniter,
wherein the controller is configured to allow the fuel gas supply device and the oxygen-containing gas supply device to change supply amounts of the fuel gas and the oxygen-containing gas in accordance with changes in power as required by the external load, and
wherein the controller is further configured to allow the fuel gas supply device and the oxygen-containing gas device to supply the fuel gas and the oxygen-containing gas supplied to the fuel cell in a decreased supply amount less than a supply amount to be set in accordance with a decreased power as required by the external load, and configured to cause the igniter to start operation if the power required by the external load decreases and flameout of the combustion in the combusted space is recognized.

US Pat. No. 10,396,376

FUEL CELL VEHICLE CONTROL METHOD AND FUEL CELL VEHICLE CONTROL APPARATUS

NISSAN MOTOR CO., LTD., ...

1. A fuel cell vehicle control method executed in a fuel cell vehicle having a fuel cell, an air supply device that supplies air to the fuel cell, a drive motor that drives a fuel cell vehicle using power from the fuel cell, and a transmission provided in a power transmission path between the drive motor and drive wheels, the method changing an output current depending on a required generated power of the fuel cell, and adjusting an air supply flow rate of the air supply device depending on the change of the output current, the method comprising:setting the required generated power of the fuel cell to power lower than the required generated power immediately prior to an inertia phase when a gearshift operation of the transmission is under the inertia phase of an upshift operation; and
controlling the air supply flow rate to an inertia phase supply flow rate higher than the air supply flow rate set in response to a decrease of the output current of the fuel cell during the inertia phase.

US Pat. No. 10,396,375

SYSTEM AND METHOD FOR CONDITION MONITORING OF REDOX FLOW BATTERIES USING DATA ANALYTICS

INTERNATIONAL BUSNIESS MA...

1. A method for predicting maintenance of a redox flow battery, the method comprising:receiving, from a plurality of sensors, data regarding characteristics of the redox flow battery, wherein the characteristics identify the state of a parameter of the redox flow battery and comprise electrical characteristics, environmental characteristics, and battery level characteristics;
forming an estimated state parameter for the redox flow battery by weighting each of the characteristics and aggregating the weighted characteristics, wherein the estimated state parameter indicates an operational state of the redox flow battery;
the forming an estimated state parameter comprising utilizing a model that is trained using a plurality of sensor measurements from a plurality of different sensors measuring different characteristics of the redox flow battery and taken at known state parameters of the redox flow battery to weight characteristics and estimate state parameters, wherein to weight the characteristics is based upon an accuracy of a value provided by the sensor corresponding to the characteristic, the accuracy being determined using a machine learning algorithm;
determining, using the processor, a maintenance action for the redox flow battery using the estimated state parameter, wherein the determining comprises analyzing the estimated state parameter against historical work order data and in view of utilities operation information to identify a maintenance action corresponding to the estimated state parameter; and
providing a recommendation of the determined maintenance action.

US Pat. No. 10,396,374

FUEL CELL COOLING SYSTEM

DENSO CORPORATION, Kariy...

1. A fuel cell cooling system circulating a refrigerant in a fuel cell, an air cooler and a radiator by a circulation pump, cooling down the fuel cell by controlling the radiator to dissipate a heat transmitted from the fuel cell to the refrigerant and cooling down an air supplied to the fuel cell by the air cooler, the fuel cell cooling system comprising:an air temperature sensor configured to sense an air detection temperature that is a temperature of the air that flows out of the air cooler and is supplied to the fuel cell;
a computer, including a hardware processor and a non-transitory storage medium storing instructions for execution by the hardware processor such that the computer is at least programmed to:
estimate an air estimation temperature that is the temperature of the air that flows out of the air cooler and is supplied to the fuel cell, based on a temperature of a refrigerant flowing into the air cooler, a power supply quantity that is a quantity of a power supplied to the circulation pump, a temperature of the air flowing into the air cooler and a flow volume of the air; and
determine that a circulation flow volume of the refrigerant is in an abnormal state where the circulation flow volume is smaller than a predetermined flow volume when the air detection temperature sensed by the air temperature sensor is higher than the air estimation temperature estimated by the computer by a value greater than or equal to a predetermined value.

US Pat. No. 10,396,372

ELECTROLYTIC SOLUTION CIRCULATION TYPE BATTERY

Sumitomo Electric Industr...

1. An electrolytic solution circulation type battery comprising:a tank which stores an electrolyte to be circulated to a battery cell; and
a pressure adjustment mechanism configured to adjust the pressure of a gas phase portion in the tank,
wherein the pressure adjustment mechanism includes a pressure adjustment bag which is provided outside the tank and expands or contracts in response to changes in pressure of the gas phase portion in the tank,
the pressure adjustment bag communicates through a duct with the gas phase portion in the tank that contains the electrolyte,
the pressure adjustment bag is made of a layered material including a corrosion protection layer and an oxygen barrier layer disposed on an outer periphery thereof,
the corrosion protection layer is formed of a resin selected from the group including polyvinyl chloride, polypropylene, polyethylene, and polytetrafluoroethylene, and
the oxygen barrier layer is formed of an organic material selected from the group including ethylene-vinyl alcohol copolymers, polyvinylidene chloride resins, polyvinyl alcohol resins, and nylon 6,
wherein the electrolytic solution circulation type battery further includes a box which contains the pressure adjustment bag and bears the internal pressure of the pressure adjustment bag due to expansion, and a size of the box is smaller than a maximum volume to which the pressure adjustment bag can be expanded,
wherein the size of the box is 80% or more and 98% or less of the maximum volume to which the pressure adjustment bad can be expanded, and
wherein at least part of the box is formed of a transparent member.

US Pat. No. 10,396,370

PASSIVE TORTUOUS PATH DRAIN

GM GLOBAL TECHNOLOGY OPER...

1. A drain for a directing fluid flow from an enclosure,the drain comprising:
a drain body having a front face and a back face, the front face defining a curved trenched channel having a first curved channel end and a second curved channel end, the curved trenched channel having a loop shape that defines a central elevated section and a peripheral elevated section, the front face also defining a second trenched channel, the drain body defining at least one egress opening in fluid communication with the second trenched channel, the first curved channel end and the second curved channel end in fluid communication with the second trenched channel, the drain adapted to be positioned adjacent to a drain opening in an enclosure such that liquid flows from the drain opening to the curved trenched channel and then to the second trenched channel exiting through the egress opening; and
a retention feature that holds the drain to the enclosure, the retention feature extending from the central elevated section.

US Pat. No. 10,396,369

FUEL CELL STACK

NISSAN MOTOR CO., LTD., ...

1. A fuel cell stack, comprising:a plurality of cell modules each comprising an integrally stacked plurality of single cells;
a sealing plate intervened between cell modules of the plurality of cell modules;
a manifold that penetrates the plurality of cell modules and the sealing plate between cell modules in a stacking direction to distribute reaction gas, wherein
each single cell of the plurality of single cells comprises a membrane electrode assembly with a peripheral frame and a pair of separators holding the peripheral frame and the membrane electrode assembly therebetween,
the sealing plate has approximately a same length and width as a single cell of the plurality of single cells,
the sealing plate comprises a sealing member that is disposed around the manifold between the sealing plate and a cell module to seal the manifold, and the sealing member comprises an extended portion that extends toward the manifold such that an end face of the extended portion is flush with an inner wall of the manifold.

US Pat. No. 10,396,365

DIATOMACEOUS ENERGY STORAGE DEVICES

Printed Energy Pty Ltd, ...

1. A supercapacitor comprising an asymmetric pair of electrodes contacting an electrolyte, wherein each of the electrodes comprises a plurality of frustules, wherein one of the electrodes comprises a zinc oxide, and wherein each of the frustules of the other of the electrodes is coated with carbon nanotubes (CNTs).

US Pat. No. 10,396,363

COPPER FOIL, NEGATIVE ELECTRODE CURRENT COLLECTOR AND NEGATIVE ELECTRODE MATERIAL FOR NON-AQUEOUS SECONDARY BATTERY

1. A copper foil including zinc in a content range of 0.02% by mass to 2.7% by mass in the total mass of the entire copper foil,wherein the regions in thicknesses direction from both surfaces of the copper foil that occupy 5% by mass in the total mass of the entire copper foil are referred to as the respective external layers, and a region between one external layer and the other external layer is referred to as an internal layer,
the internal layer comprises copper as a main element and includes 100 ppm or more in total of small-amount elements, and includes zinc at 10% or more in the total mass of zinc included in the entire copper foil;
wherein the small-amount elements in the internal layer comprise:
20 to 470 ppm of carbon,
5 to 600 ppm of sulfur,
15 to 600 ppm of chlorine and
about 397 to 600 ppm of nitrogen.

US Pat. No. 10,396,362

ELECTRODE ACTIVE MATERIAL SLURRY, PREPARATION METHOD THEREOF, AND ALL-SOLID SECONDARY BATTERY COMPRISING THE SAME

Hyundai Motor Company, S...

1. An electrode active material slurry comprising:a clustered complex and a slurry,
wherein the clustered complex comprises an electrode active material, a solid electrolyte, a conductive material, and a first binder, and the slurry comprises a solvent and a second binder,
wherein the first binder is applied on a surface of the electrode active material, and the second binder is present between the electrode active materials,
wherein the first binder comprises polytetrafluoroethylene (PTFE).

US Pat. No. 10,396,361

NONAQUEOUS LITHIUM-TYPE POWER STORAGE ELEMENT

Asahi Kasei Kabushiki Kai...

1. A nonaqueous lithium power storage element comprising a positive electrode, a negative electrode, a separator and a lithium ion-containing nonaqueous electrolytic solution, whereinthe negative electrode has a negative electrode power collector, and a negative electrode active material layer containing a negative electrode active material, provided on one or both sides of the negative electrode power collector,
the positive electrode has a positive electrode power collector, and a positive electrode active material layer containing a positive electrode active material, provided on one or both sides of the positive electrode power collector,
in the solid 7Li-NMR spectrum of the positive electrode active material layer, the relationship 1.04?b/a?5.56 is satisfied, where “a” is the peak area from ?40 ppm to 40 ppm obtained by measuring with a repeated latency of 10 seconds, and “b” is the peak area from ?40 ppm to 40 ppm obtained by measuring with a repeated latency of 3,000 seconds,
the positive electrode active material layer contains a lithium compound other than the positive electrode active material,
the positive electrode active material is an activated carbon, and
the lithium compound is at least one selected from the group consisting of lithium carbonate, lithium oxide and lithium hydroxide.

US Pat. No. 10,396,358

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A nonaqueous electrolyte secondary battery comprising:a positive electrode comprising a positive electrode active material layer;
a negative electrode comprising a negative electrode active material layer;
a separator interposed between the positive electrode active material layer and the negative electrode active material layer; and
a nonaqueous electrolyte solution,whereinthe positive electrode active material layer contains a positive electrode active material and an inorganic phosphate compound that contains an alkali metal and/or an alkaline-earth metal, and
a phosphate ion scavenger that scavenges a phosphate ion is disposed between the positive electrode active material layer and the negative electrode active material layer and/or in the negative electrode active material layer, and wherein
the inorganic phosphate compound is Li3PO4, and
the phosphate ion scavenger is at least one metal oxide particle selected from the group consisting of ZrO2, TiO2, and BaTiO3.

US Pat. No. 10,396,352

NON-AQUEOUS ELECTROLYTE BATTERY, METHOD FOR MANUFACTURING SAME, AND NON-AQUEOUS ELECTROLYTE BATTERY SYSTEM

Maxell Holdings, Ltd., K...

1. A non-aqueous electrolyte battery comprising an electrode body in which a positive electrode and a negative electrode are laminated with a separator interposed therebetween, and a non-aqueous electrolyte,wherein the negative electrode has a laminated body including a metal base layer that does not form an alloy with Li, and Al active layers respectively bonded to both faces of the metal base layer,
Li—Al alloys are formed at least on surface sides of the Al active layers,anda Li content is 3 to 48 at % when a total of and Al in the Al active layer is taken as 100 at %.

US Pat. No. 10,396,351

NEGATIVE ELECTRODE MATERIAL FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY AND METHOD OF PRODUCING NEGATIVE ELECTRODE ACTIVE MATERIAL PARTICLES

SHIN-ETSU CHEMICAL CO., L...

1. A negative electrode material for a non-aqueous electrolyte secondary battery, comprisingnegative electrode active material particles comprising a silicon compound expressed by SiOx, where 0.5?x?1.6, and a coating layer composed of an organic polymer coating the silicon compound, wherein
the silicon compound contains Li2SiO3 inside, and
the organic polymer comprises at least one of polyacrylic acid and an alkali metal salt thereof, and carboxymethyl cellulose and an alkali metal salt thereof.

US Pat. No. 10,396,350

METHOD FOR MANUFACTURING ELECTRODE FOR LITHIUM ION BATTERY

ZEON CORPORATION, Chiyod...

1. A method for manufacturing an electrode for a lithium ion battery, in which a squeegee roll squeegees powder containing an electrode active material, which is supplied on a substrate, to form a powder layer, and a pair of press rolls compacts the powder layer onto the substrate while conveying the substrate downwardly in a vertical direction to manufacture an electrode sheet, the method comprising:a supplying step for supplying the powder stored in a hopper directly onto the substrate from the hopper;
a powder layer forming step for forming the powder layer onto the substrate by squeegeeing and leveling the powder supplied on the substrate using the squeegee roll that is arranged at a position with a squeegee angle ? ranging from 0° to 60°, which is an angle between a vertical line that intersects a rotating axis of one of the press rolls and a line that connects the rotating axis with a rotating axis of the squeegee roll, the squeegeeing and leveling the powder being performed on the substrate; and
a compacting step for compacting the powder layer onto the substrate by the pair of the press rolls, wherein the powder layer formed by the powder layer forming step has density that ranges from 105% to 150% of bulk density of the powder.

US Pat. No. 10,396,349

SEMI-SOLID FLOW LI/O2 BATTERY

1. A lithium oxygen battery comprising a lithium anode and a non-aqueous semi-solid flowable catholyte, said non-aqueous semi-solid flowable catholyte comprising an electrolyte, dissolved oxygen and carbonaceous particles.

US Pat. No. 10,396,348

NEGATIVE ELECTRODE MATERIAL FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY, METHOD OF PRODUCING NEGATIVE ELECTRODE MATERIAL FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY, AND NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY

SHIN-ETSU CHEMICAL CO., L...

1. A negative electrode material for a non-aqueous electrolyte secondary battery, comprising a conductive powder composed of silicon-based active material particles coated with a conductive carbon film, whereinthe conductive carbon film exhibit a d-band having a peak half width of 100 cm?1 or more, the d-band being determined from a Raman spectrum of the conductive carbon film, the silicon-based active material particles are particles of a silicon oxide expressed by SiOx where 0.5?x?1.6,
the silicon-based active material particles comprise silicon fine crystals dispersed in a silicon oxide, the silicon fine crystals having a crystallite size ranging from 1 to 9 nm, and
the conductive carbon film has a two-layer structure comprising a first carbon film being in contact with an outer surface of the silicon-based active material particles and a second carbon film being in contact with an outer surface of the first carbon film, the first carbon film being composed of a carbon material containing 70 mass % or more of a carbon compound having 3 or more carbon atoms, the second carbon film being composed of a carbon material containing 70 mass % of more of a carbon compound having 1 to 2 carbon atoms, wherein
the total carbon amount of the first carbon film and the second carbon film is in the range of 1 to 40 mass % with respect to the silicon-based active material particles.

US Pat. No. 10,396,345

APPARATUS AND METHOD FOR MANUFACTURING ELECTRODE

LG CHEM, LTD., Seoul (KR...

1. A method for manufacturing an electrode, the method comprising:a step of preparing a collector;
a coating step of applying an electrode active material to one surface or both surfaces of the collector to manufacture an initial electrode; and
a first cutting step of cutting the initial electrode coated with the electrode active material to manufacture a plurality of middle-stage electrodes,
wherein each of the middle-stage electrodes comprises two coating portions that are areas coated with the electrode active material and a non-coating portion that is an area which is not coated with the electrode active material, the coating portions are spaced apart from each other,
wherein, in the first cutting step, the initial electrode is cut so that for at least one of the plurality of middle-stage electrodes, the two coating portions have an overall length that is different than an overall length of two coating portions for at least one other middle-stage electrode, and
wherein, in each of the middle-stage electrodes, each of the two coating portions has a same length.

US Pat. No. 10,396,344

DRYING METHOD AND BATTERY MANUFACTURING METHOD

TOYOTA JIDOSHA KABUSHIKI ...

1. A drying method that dries an electrode layer including a binder and a solvent, the drying method comprising:a first step of blowing a gas onto a first area of the electrode layer to volatilize the solvent, the electrode layer being coated on a base material; and
a second step of blowing a gas onto a second area of the electrode layer to volatilize the solvent, the second area being located around the first area,
wherein the first area and the second area are arranged in a staggered manner,
in the first step, by non-uniformly volatilizing the solvent, the binder diffuses such that a concentration of the binder in the first area is higher than a concentration of the binder in the second area on a surface of the electrode layer, and
in the second step, by non-uniformly volatilizing the solvent, the binder diffuses such that the concentration of the binder in the first area is lower than the concentration of the binder in the second area on the surface of the electrode layer.

US Pat. No. 10,396,339

BI-METAL BATTERY TAB

Apple Inc., Cupertino, C...

1. A battery, comprising:a conductive tab fixed to the battery and in electrical communication with a battery cell terminal of a battery cell of the battery, the conductive tab positioned partially external to the battery cell, the conductive tab comprising:
a socket segment composed at least in part of a first metal; and
a pin segment composed at least in part of a second metal, the pin segment comprising a pin surface positioned at least partially within the socket segment and in contact with at least a first socket wall of the socket segment,
wherein the conductive tab is configured to electrically connect the battery to an external component to provide power from the battery, and wherein the conductive tab including the socket segment and the pin segment remain fixed to the battery when the battery is not connected to the external component.

US Pat. No. 10,396,331

LAMINATE, SECONDARY BATTERY, BATTERY PACK, AND VEHICLE

KABUSHIKI KAISHA TOSHIBA,...

1. A laminate comprising:an active material layer that comprises a plural of active material particles;
a separator that is layered on the active material layer, and comprises a first surface and a second surface opposed to the first surface; and
an organic electrolyte,
wherein the separator comprises particles comprising an inorganic compound having lithium ion conductivity at 25° C. of 1×10?10 S/cm or more, and a ratio (L/Rmax) of a thickness L to a radius Rmax satisfies 0 where the radius Rmax is a radius of the active material particle having a maximum particle size among the active material particles facing the first surface of the separator, and the thickness L is distance from an interface between the active material particle having a maximum particle size and the first surface of the separator to the second surface of the separator,
and wherein a ratio of an amount of the organic electrolyte to a total amount of the particles and the organic electrolyte is within a range of 1% by mass to 10% by mass.

US Pat. No. 10,396,329

BATTERY SEPARATOR MEMBRANE AND BATTERY EMPLOYING SAME

Dioxide Materials, Inc., ...

1. A battery comprising a separator membrane, the separator membrane comprising an ion-conducting polymeric composition comprising a copolymer of Ra-Rs and Rb, wherein:(a) Ra is a vinylbenzyl group;
(b) Rb is substituted ethene having the structural formula:

where R1-R4 are each independently selected from the group consisting of hydrogen, halogens, linear alkyls, branched alkyls, cyclic alkyls, heteroalkyls, aryls, heteroaryls, alkylaryls, and heteroalkylaryls;
(c) Rs is a positively charged amine group or a positively charged phosphene group;
(d) the copolymer comprises at least 3% of Ra by weight;
(e) the copolymer comprises at least 3% of Rb by weight;
(f) Ra and Rb are different chemical constituents; and
(g) Ra-Rs is not vinylpyridine.

US Pat. No. 10,396,321

BATTERY PACK SPACER

TOYOTA JIDOSHA KABUSHIKI ...

1. A battery pack spacer which is arranged between adjacent single cells in a battery pack constructed by arranging a plurality of single cells in a predetermined arrangement direction, each of the single cells including terminals which protrude in a direction perpendicular to the arrangement direction, the battery pack spacer comprising:a first region; and
a second region,
wherein
the direction in which the terminals protrude is set as a first direction,
a direction opposite to the first direction is set as a second direction,
in the first direction and the second direction of the battery pack spacer arranged between the single cells, the spacer is divided into the first region and the second region,
the first region includes an end portion in the first direction and occupies half of an entire region of the spacer in the second direction from the end portion in the first direction,
the second region includes an end portion in the second direction and occupies half of the entire region of the spacer in the first direction from the end portion in the second direction, and
wherein a wedge-shaped space is formed in the battery pack spacer, so that a width of the space, as viewed along the arrangement direction, is widest at the end portion in the second direction, and gradually narrows toward the end portion in the first direction until no space is formed in the end portion in the first direction so the second region has higher compressibility in the arrangement direction than the first region.

US Pat. No. 10,396,315

HOLLOW-CORE ROLLED-ELECTRODE BATTERY CELL

Microsoft Technology Lice...

1. A battery cell comprising:a pair of electrodes wound together around a hollow core;
a plurality of electrode tabs, each coupled to a separate one of the electrodes; and
a flexible outer wrapper enclosing the pair of electrodes, the flexible outer wrapper forming openings corresponding to the hollow core, and each of the plurality of electrode tabs radially protruding through an outer surface of the flexible outer wrapper.

US Pat. No. 10,396,314

MANUFACTURING METHOD FOR ORGANIC ELECTROLUMINESCENT PANEL AND ORGANIC ELECTROLUMINESCENT PANEL

JOLED INC., Tokyo (JP)

1. A manufacturing method for an organic electroluminescent panel that includes an organic electroluminescent element for each sub-pixel, the manufacturing method comprising:recoating a first organic material layer and a second organic material layer to manufacture the organic electroluminescent element, wherein the first organic material layer and the second organic material layer include common principal components,
wherein, after the first organic material layer is recoated, an insolubilization process is performed for the first organic material layer to provide a change to a structure of molecules included in the first organic material layer, and the second organic material layer is recoated to the first organic material layer after the insolubilization process is performed,
forming a plurality of line banks and a plurality of banks on a substrate,
wherein each line bank of the plurality of line banks extends in a row direction on the substrate and is parallel to each other,
wherein each bank of the plurality of banks extends in a column direction on the substrate such that the each bank of the plurality of banks connects end portions of at least two line banks of the plurality of line banks, and
wherein the first organic material layer and the second organic material layer are recoated in a gap between two line banks of the plurality of line banks.

US Pat. No. 10,396,313

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A manufacturing method of a display device, comprising:forming pixels on a mother substrate comprising a display area and a non-display area;
attaching a polarization film stretched in a first direction and a second direction opposite to the first direction on the mother substrate having the pixels thereon; and
cutting at least a portion of the polarization film along a third direction,
wherein the third direction forms an acute angle with the first direction toward an outside of the polarization film.

US Pat. No. 10,396,312

ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. An organic light emitting diode (OLED) display comprising:a substrate;
an organic light emitting diode disposed on the substrate;
a first inorganic layer disposed on the substrate and covering the organic light emitting diode, an edge of the first inorganic layer directly contacting the substrate;
a second inorganic layer disposed on the first inorganic layer and contacting the first inorganic layer at an edge of the second inorganic layer, the second inorganic layer entirely and directly contacting the first inorganic layer;
an organic layer disposed on the second inorganic layer and covering a relatively smaller area than the second inorganic layer; and
a third inorganic layer disposed on the organic layer, covering a relatively larger area than the organic layer, and contacting the first inorganic layer and the second inorganic layer at an edge of the third inorganic layer.

US Pat. No. 10,396,309

DISPLAY DEVICE AND FABRICATING METHOD THEREOF

LG DISPLAY CO., LTD., Se...

1. A display device comprising:a lower substrate;
a thin film transistor arranged on a display area of the lower substrate;
a planarization film arranged on the thin film transistor;
a light emitting layer arranged on the planarization film;
pads arranged on a non-display area of the lower substrate;
an encapsulation layer arranged on the light emitting layer to cover a side of the planarization film, and including an inorganic protection film or an inorganic-organic composite film; and
an anti-film layer arranged on the pads to cover a portion of the non-display area from the pads to the encapsulation layer, and to contact the encapsulation layer,
wherein the anti-film layer prevents the inorganic protection film or the inorganic-organic composite film on the light emitting layer from being formed on the pads, and
wherein an anti-film material constituting a molecule of the anti-film layer is a self-assembling layer, and includes:
a head part bonded to a surface of the pads;
a chain extended from one side of the head part; and
a tail part connected to an end at one side of the chain.

US Pat. No. 10,396,308

ORGANIC EL DISPLAY PANEL

JOLED INC., Tokyo (JP)

1. An organic electroluminescence (EL) display panel, comprising:a substrate;
a multi-layered wiring laminate disposed on the substrate and including wiring and a plurality of insulating layers, the wiring disposed on at least one of the insulating layers and extending to a vicinity of an outer periphery of the multi-layered wiring laminate;
an organic EL element array disposed on the multi-layered wiring laminate and including organic EL elements that are connected to the wiring;
a first inorganic insulating layer disposed at least on the organic EL element array and extending outside the outer periphery of the multi-layered wiring laminate in plan view;
a resin sealing layer disposed on the first inorganic insulating layer, the resin sealing layer covering the organic EL element array in plan view and having an outer periphery above a resin insulating layer that is a highest layer among the insulating layers; and
a second inorganic insulating layer disposed at least on the resin sealing layer, the second inorganic insulating layer extending outside the outer periphery of the resin sealing layer in plan view and being in contact with the first inorganic insulating layer in a thickness direction.

US Pat. No. 10,396,306

ELECTROLUMINESCENT DEVICE CAPABLE OF IMPROVING LUMINOUS EFFICIENCY BY PREVENTING A LEAKAGE CURRENT AND IMPROVING ELECTRON TRANSPORT PROPERTIES AND A DISPLAY DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. An electroluminescent device, comprisinga first electrode;
a hole transport layer disposed on the first electrode;
an emission layer disposed on the hole transport layer and comprising at least two light emitting particles;
a first electron transport layer disposed on the emission layer and comprising at least two inorganic-organic composite particles;
a second electron transport layer disposed on the first electron transport layer and comprising at least two inorganic oxide particles; and
a second electrode disposed on the second electron transport layer,
wherein the first electron transport layer has a lower work function than the second electron transport layer.

US Pat. No. 10,396,305

ORGANIC EL DEVICE, AND DISPLAY APPARATUS AND LIGHTING APPARATUS USING THE SAME

Canon Kabushiki Kaisha, ...

1. An organic EL device comprising, in the following order:a substrate;
a reflection electrode;
an organic compound layer; and
a light extraction electrode,
wherein the reflection electrode serves as a cathode and the light extraction electrode serves as an anode,
wherein the organic compound layer includes a first light-emitting layer which is electron trapping type and a second light-emitting layer disposed between the first light-emitting layer and the light extraction electrode,
wherein the first light-emitting layer emits blue light,
wherein the second light-emitting layer emits light whose wavelength is longer than a wavelength of the blue light from the first light-emitting layer, and
wherein an optical distance between the reflection electrode and the first light-emitting layer is a distance of constructive interference for the light of the first light-emitting layer.

US Pat. No. 10,396,304

ORGANIC EL DISPLAY DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE

Japan Display Inc., Toky...

1. An organic EL display device comprising:a glass substrate;
an organic EL layer formed on an upper side of the glass substrate;
a support substrate glued on a lower side of the glass substrate via a first adhesive;
a glass-made counter substrate covering the organic EL layer; and
a polarizing plate glued on an upper side of the counter substrate via a second adhesive,
wherein first recessed portions or first projecting portions are formed on the glass substrate at a side thereof facing the support substrate,
wherein the first recessed portions or a space between each of the first projecting portions is filled with the first adhesive, and
wherein second recessed portions or second projecting portions are formed on the counter substrate at a side thereof facing the polarizing plate.

US Pat. No. 10,396,303

ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE

Japan Display Inc., Mina...

1. An organic electroluminescence display device, comprising:a plurality of light emitting elements;
a sealing film covering the plurality of light emitting elements, and having a top surface which is an inorganic film made of a first inorganic material;
a protective film made of an organic material, the protective film covering the sealing film; and
a close-fitting layer made of a second inorganic material, and located between the top surface of the sealing film and the protective film,
wherein
the first inorganic material has higher moisture-barrier properties than the second inorganic material,
adhesion between the second inorganic material and the organic material is higher than adhesion between the first inorganic material and the organic material,
an edge portion of the inorganic film overlaps with an edge portion of the close-fitting layer in a plan view,
the edge portion of the close-fitting layer overlaps with an edge portion of the protective film in the plan view,
the sealing film includes an organic film under the inorganic film and a second inorganic film under the organic film,
the edge portion of the inorganic film is in direct contact with an edge portion of the second inorganic film, and
the edge portion of the close-fitting layer overlaps with the edge portion of the second inorganic film, in the plan view.

US Pat. No. 10,396,302

ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE

Japan Display Inc., Toky...

1. An electroluminescence display device, comprising:a first pixel electrode;
a second pixel electrode provided in the same layer as the first pixel electrode;
a counter electrode provided on the first pixel electrode and the second pixel electrode;
a first organic light emitting layer provided between the first pixel electrode and the counter electrode, the first organic light emitting layer emitting light having a first wavelength;
a second organic light emitting layer provided between the second pixel electrode and the counter electrode, the second organic light emitting layer emitting light having a second wavelength;
an electron blocking layer between the first pixel electrode and the first organic light emitting layer and between the second pixel electrode and the second organic light emitting layer; and
a hole blocking layer between the first organic light emitting layer and the counter electrode and between the second organic light emitting layer and the counter electrode,
wherein
the first organic light emitting layer contains a host material, a first dopant material and a first assist dopant material,
the second organic light emitting layer contains the host material that is the same as that of the first organic light emitting layer, a second dopant material and a second assist dopant material,
each of the first organic light emitting layer and the second organic light emitting layer is encapsulated by the electron blocking layer and the hole blocking layer, and
the electron blocking layer and the hole blocking layer are in contact with each other at a region between the first organic light emitting layer and the second organic light emitting layer.

US Pat. No. 10,396,301

ORGANIC SOLAR CELL WITH VERTICAL ACTIVE LAYERS

1. An organic photovoltaic device comprising:a substrate;
at least first and second active layers, each active layer (1) having at least one organic material and (2) including a first surface that receives light and a second surface that directly contacts the substrate, the second surface being opposite to the first surface; and
at least first, second, and third electrodes supported by the substrate, wherein (1) the first and second electrodes each have a surface, being substantially perpendicular to the substrate, that contacts the first active layer, (2) the second and third electrodes each have a surface, being substantially perpendicular to the substrate, that contacts the second active layer, (3) the first and third electrodes have a same polarity, and (4) the second electrode has an opposite polarity to the first and third electrodes.

US Pat. No. 10,396,300

CARBON NANOTUBE DEVICE WITH N-TYPE END-BONDED METAL CONTACTS

International Business Ma...

1. A field effect transistor comprising:a substrate;
a gate dielectric formed on the substrate;
a channel material formed on the gate dielectric, the channel material comprising carbon nanotubes; a patterned resist layer comprising openings formed therein, the openings exposing portions of the gate dielectric and end portions of the carbon nanotubes under the patterned resist layer, wherein exposed tips of the carbon nanotubes at the end portions are oxidized, and wherein the patterned resist layer comprises hydrogen silsesquioxane;
metal contacts formed at least within the openings, the metal contacts comprising a portion contacting the oxidized exposed tips of the carbon nanotubes and the portions of the gate dielectric exposed within the openings, wherein the portion of the metal contacts contacting the oxidized exposed tips of the carbon nanotubes scavenge oxygen from the oxidized exposed tips of the carbon nanotubes forming a bond between material of the metal contacts and the carbon nanotubes, where the portion of the metal contacts comprises a bottom surface that is planar with a bottom surface of the end portions of the carbon nanotubes, and wherein a region of the portion of the metal contacts comprises a top surface that is above a bottom surface of the patterned resist layer and disposed between sidewalls of the patterned resist layer, and wherein the top surface is planar with or below a top surface of the patterned resist layer; and
a dielectric layer comprising a planar top surface, wherein the dielectric layer is formed in contact with a plurality of portions of a top surface of the patterned resist layer, a plurality of sidewalls of each of the metal contacts, and the top surface of the region of the portion of each of the metal contacts.

US Pat. No. 10,396,297

MATERIALS FOR ELECTRONIC DEVICES

Merck Patent GmbH, (DE)

1. A material comprising a compound P which is a complex of bismuth and a compound A of a formula (A-II) or (A-III)
where the variables that occur are:
Z is the same or different at each instance and is CR1;
Ar1 is the same or different at each instance and is an aromatic ring system which has 6 to 60 aromatic ring atoms and is optionally substituted by one or more R1 radicals, or a heteroaromatic ring system which has 5 to 60 aromatic ring atoms and is optionally substituted by one or more R1 radicals; Ar1 groups here are optionally bonded to one another via R1 radicals;
Ar2 is an aromatic ring system which has 6 to 20 aromatic ring atoms and may be substituted by one or more R1 radicals, or a heteroaromatic ring system which has 5 to 20 aromatic ring atoms and is optionally substituted by one or more R1 radicals;
R1 is the same or different at each instance and is selected from H, D, F, CN, Si(R2)3, straight-chain alkyl or alkoxy groups having 1 to 10 carbon atoms, branched or cyclic alkyl or alkoxy groups having 3 to 10 carbon atoms, aromatic ring systems having 6 to 40 aromatic ring atoms and heteroaromatic ring systems having 5 to 40 aromatic ring atoms; where the alkyl and alkoxy groups mentioned, the aromatic ring systems mentioned and the heteroaromatic ring systems mentioned may each be substituted by one or more R2 radicals;
R2 is the same or different at each instance and is selected from H, D, F, CN, alkyl groups having 1 to 20 carbon atoms, aromatic ring systems having 6 to 40 aromatic ring atoms and heteroaromatic ring systems having 5 to 40 aromatic ring atoms; and where the alkyl groups, aromatic ring systems and heteroaromatic ring systems mentioned is optionally substituted by F or CN;
n is 0 or 1; and
where the scope of the formula (A-II) excludes compounds of the following formula (B)

in which the new variables that occur are:
V is CR1;
Ar3 is the same or different at each instance and is an aromatic ring system which has 6 to 30 aromatic ring atoms and is optionally substituted by one or more R1 radicals, or a heteroaromatic ring system which has 5 to 30 aromatic ring atoms and is optionally substituted by one or more R1 radicals; Ar3 groups here are optionally bonded to one another via R1 radicals.

US Pat. No. 10,396,296

ORGANIC LIGHT-EMITTING DEVICE

Samsung Display Co., Ltd....

1. An organic light-emitting device, comprising:a first electrode, a second electrode facing the first electrode, and a plurality of light-emitting units disposed in a stack between the first and second electrodes, each light emitting unit including an emission layer; and
a charge generation layer, including an n-type charge generation layer and a p-type charge generation layer, disposed between each adjacent pair of light-emitting units, wherein:
a wavelength of maximum intensity of light emitted from one of the light-emitting units is different from the wavelength of maximum intensity of light emitted from another of the light-emitting units,
at least one n-type charge generation layer consists of a metal-containing material having a work function of about 2.0 eV to about 4.5 eV, the metal-containing material being a metal, a metal oxide, a metal halide, or a combination thereof, and
at least one p-type charge generation layer includes a hole transport material,
at least one light-emitting unit adjacent to the p-type charge generation layer including the hole transport material includes a hole transport region,
the hole transport region includes a hole transport layer,
an absolute value of a highest occupied molecular orbital (HOMO) energy level of the hole transport material being greater than about 5.5 eV, and an absolute value of a lowest unoccupied molecular orbital (LUMO) energy level of the hole transport material being less than that of a LUMO energy level of a hole transport layer of a light-emitting unit adjacent to the p-type charge generation layer.

US Pat. No. 10,396,295

CONDENSED CYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A condensed cyclic compound represented by Formula 1:Ar1-(L1)a1-Ar2  Formula 1

wherein, in Formulae 1, 2-3, and 3-1,
Ar1 is a group represented by Formula 2-3,
Ar2 is a group represented by Formula 3-1,
L1 is selected from a substituted or unsubstituted C6-C60 arylene group, a substituted or unsubstituted C1-C60 heteroarylene group, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group,
a1 is selected from 0, 1, 2, and 3,
X21 is selected from O, S, and Se,
X31 is selected from a single bond, O, S, N(R33), C(R33)(R34), Si(R33)(R34), Ge(R33)(R34), and P(?O)(R33),
A21, A31, and A32 are each independently selected from a C5-C30 carbocyclic group and a C1-C30 heterocyclic group,
R21 to R23 and R31 to R34 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C7-C60 aryl alkyl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted C2-C60 heteroaryl alkyl group, a substituted or unsubstituted C1-C60 hetero aryloxy group, a substituted or unsubstituted C1-C60 hetero arylthio group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —N(Q1)(Q2), —Si(Q1)(Q2)(Q3), and —B(Q1)(Q2),
R22 and R23 are optionally linked to form a substituted or unsubstituted C5-C30 carbocyclic group or a substituted or unsubstituted C1-C30 heterocyclic group,
R33 and R34 are optionally linked via a first linking group to form a substituted or unsubstituted C5-C30 carbocyclic group or a substituted or unsubstituted C1-C30 heterocyclic group,
b21, b31, and b32 are each independently selected from 1, 2, 3, 4, 5, 6, 7, and 8,
Q1 to Q3 are each independently selected from:
hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, substituted with at least one selected from deuterium, a C1-C60 alkyl group, and a C6-C60 aryl group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C7-C60 arylalkyl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a C2-C60 heteroaryl alkyl group, a C1-C60 hetero aryloxy group, a C1-C60 hetero arylthio group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group; and
a C6-C60 aryl group, substituted with at least one selected from deuterium, a C1-C60 alkyl group, and a C6-C60 aryl group, and
indicates a binding site to a neighboring atom.

US Pat. No. 10,396,294

CARBAZOLE COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A carbazole compound represented by Formulae 1A or 1B
wherein in Formulae 1A and 1B,
A is -(L1)a1-(E1)b1,
L1 is selected from a substituted or unsubstituted C6-C60 arylene group, and a substituted or unsubstituted C1-C60 heteroarylene group;
in Formula 1A, E1 is selected from:
a pyrrolyl group, an imidazolyl group, a pyrazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoimidazolyl group, a thiazolyl group, an isothiazolyl group, a benzothiazolyl group, an isoxazolyl group, an oxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, a carbazolyl group, an imidazopyrimidinyl group, and an imidazopyridinyl group; and
a pyrrolyl group, an imidazolyl group, a pyrazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoimidazolyl group, a thiazolyl group, an isothiazolyl group, a benzothiazolyl group, an isoxazolyl group, an oxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, a carbazolyl group, an imidazopyrimidinyl group, and an imidazopyridinyl group, each substituted with at least one Ar1,
wherein Ar1 is selected from
a phenyl group, a pentalenyl group, an indenyl group, a naphthyl group, an azulenyl group, a heptalenyl group, an indacenyl group, an acenaphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenalenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthrenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a naphthacenyl group, a picenyl group, a perylenyl group, a pentaphenyl group, a hexacenyl group, a pyrrolyl group, an imidazolyl group, a pyrazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoxazolyl group, a benzoimidazolyl group, a furanyl group, a benzofuranyl group, a thiophenyl group, a benzothiophenyl group, a thiazolyl group, an isothiazolyl group, a benzothiazolyl group, an isoxazolyl group, an oxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, a dibenzofuranyl group, a dibenzothiophenyl group, a benzocarbazolyl group, a dibenzocarbazolyl group, an imidazopyrimidinyl group, and an imidazopyridinyl group; and
a phenyl group, a pentalenyl group, an indenyl group, a naphthyl group, an azulenyl group, a heptalenyl group, an indacenyl group, an acenaphthyl group, a fluorenyl group, a spiro-fluorenyl group, a phenalenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthrenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a naphthacenyl group, a picenyl group, a perylenyl group, a pentaphenyl group, a hexacenyl group, a pyrrolyl group, an imidazolyl group, a pyrazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzoxazolyl group, a benzoimidazolyl group, a furanyl group, a benzofuranyl group, a thiophenyl group, a benzothiophenyl group, a thiazolyl group, an isothiazolyl group, a benzothiazolyl group, an isoxazolyl group, an oxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, a dibenzofuranyl group, a dibenzothiophenyl group, a benzocarbazolyl group, a dibenzocarbazolyl group, an imidazopyrimidinyl group, and an imidazopyridinyl group, each substituted with at least one of a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof and a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C1-C20 alkoxy group, a phenyl group, a naphthyl group, an anthracenyl group, a pyrenyl group, a phenanthrenyl group, a fluorenyl group, a carbazolyl group, a benzocarbazolyl group, a dibenzocarbazolyl group, a pyridinyl group, a pyrimidinyl group, a pyrazinyl group, a pyridazinyl group, a triazinyl group, a quinolinyl group, an isoquinolinyl group, a phthalazinyl group, a quinoxalinyl group, a cinnolinyl group, and a quinazolinyl group;
in Formula 1B, E1 is a substituted or unsubstituted electron transporting-cyclic group or a substituted or unsubstituted carbazolyl group, each of which includes at least one N as a ring-forming atom;
wherein in Formulae 1A and 1B,
a1 is selected from integers of 1 to 5;
b1 is 1 or 2, provided that when b1 is 2, two groups E1 are identical to or different from each other;
R1 is selected from a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C2-C20 alkenyl group, a substituted or unsubstituted C2-C20 alkynyl group, and a substituted or unsubstituted C1-C20 alkoxy group;
R2 to R4 are each independently selected from a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C2-C20 alkynyl group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C1-C20 alkoxy group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, —N(Q11)(Q12), —Si(Q13)(Q14)(Q15), and —B(Q16)(Q17);
c1 to c3 are each independently 0 to 2;
at least one of substituents of the substituted C6-C60 arylene group, the substituted C1-C60 heteroarylene group, the substituted electron transporting-cyclic group, the substituted carbazolyl group, the substituted C1-C20 alkyl group, the substituted C2-C20 alkenyl group, the substituted C2-C20 alkynyl group, the substituted C3-C10 cycloalkyl group, the substituted C1-C10 heterocycloalkyl group, the substituted C3-C10 cycloalkenyl group, the substituted C1-C10 heterocycloalkenyl group, the substituted C6-C60 aryl group, the substituted C6-C60 aryloxy group, the substituted C6-C60 arylthio group, the substituted C1-C60 heteroaryl group, the substituted monovalent non-aromatic condensed polycyclic group, and the substituted monovalent non-aromatic condensed heteropolycyclic group are selected from
a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, and C1-C20 alkoxy group;
a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, and a C1-C20 alkoxy group, each substituted with at least one of a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q21)(Q22), —Si(Q23)(Q24)(Q25), and —B(Q26)(Q27);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one of a deuterium atom, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, and a C1-C20 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q31)(Q32), —Si(Q33)(Q34)(Q35), and —B(Q36)(Q37); and
—N(Q41)(Q42), —Si(Q43)(Q44)(Q45) and —B(Q46)(Q47),
wherein Q11 to Q17, Q21 to Q27, Q31 to Q37, and Q41 to Q47 are each independently selected from a hydrogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C1-C20 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group,
provided that, in Formula 1A, R2 in the number of c1 are all different from A.

US Pat. No. 10,396,291

COMPOUND FOR ORGANIC ELECTRONIC ELEMENT, ORGANIC ELECTRONIC ELEMENT USING THE SAME, AND AN ELECTRONIC DEVICE THEREOF

DUK SAN NEOLUX CO., LTD.,...

1. A compound of Formula 1:
wherein,
Ar1 to Ar3 are each independently selected from the group consisting of a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxy group; and a C6-C30 aryloxy group,
L is

m and o are each an integer of 0 to 4, n is an integer of 0 to 3,
R1 and R2 are each independently selected from the group consisting of deuterium; halogen; a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxy group; a C6-C30 aryloxy group; -L?-N(Ra)(Rb); and a combination thereof, wherein R1 and/or R2 are plural and one or two pair(s) of any two adjacent groups of R1 and/or any two adjacent groups of R2 are linked together to form a benzene ring,
R3 is selected from the group consisting of deuterium; halogen; a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxy group; a C6-C30 aryloxy group; and a combination thereof, wherein any two adjacent groups of R3 are optionally linked together to form a ring,
L? is selected from the group consisting of single bond; a C6-C60 arylene group; a fluorenylene group; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P,
Ra and Rb are each independently selected from the group consisting of C6-C60 aryl group; a fluorenyl group; a fused ring formed by a C3-C60 aliphatic ring and a C6-C60 aromatic ring; and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P,
each of the above aryl group, fluorenyl group, heterocyclic group, fused ring group, alkyl group, alkenyl group, alkynyl group, alkoxy group, aryloxy group, arylene group and fluorenylene group may be substituted with one or more substituents selected from the group consisting of deuterium; halogen; a silane group; a siloxane group; a boron group; a germanium group; a cyano group; a nitro group; a C1-C20 alkylthio group; a C1-C20 alkoxy group; a C1-C20 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C6-C20 aryl group; a C6-C20 aryl group substituted with deuterium; a fluorenyl group; a C2-C20 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a C3-C20 cycloalkyl group; a C7-C20 arylalkyl group; and a C8-C20 arylalkenyl group.

US Pat. No. 10,396,289

SPIRO ORGANIC COMPOUNDS, MATERIAL COMPRISING THE SAME FOR ORGANIC ELECTROLUMINESCENCE DEVICES, AND ORGANIC ELECTROLUMINESCENCE DEVICE COMPRISING THE MATERIAL

NANJING TOPTO MATERIALS C...

1. An organic compound of General Formula 1:
wherein in General Formula (1), SPIRO is a unit represented by General Formula (2) below:

Ar1 and Ar3 are the same or different, and are selected from the group consisting of benzene optionally substituted with one or more radicals R5, biphenyl optionally substituted with one or more radicals R5, naphthalene optionally substituted with one or more radicals R5, phenanthrene optionally substituted with one or more radicals R5, fluorene optionally substituted with one or more radicals R5, dibenzofuran optionally substituted with one or more radicals R5, dibenzothiophene optionally substituted with one or more radicals R5, substituted or unsubstituted spirobifluorene, and a combination of 2, 3, 4, or 5 of these groups;
Ar2 is absent or selected from the group consisting of benzene optionally substituted with one or more radicals R5, biphenyl optionally substituted with one or more radicals R5, naphthalene optionally substituted with one or more radicals R5, phenanthrene optionally substituted with one or more radicals R5, fluorene optionally substituted with one or more radicals R5, spirobifluorene optionally substituted with one or more radicals R5, dibenzofuran optionally substituted with one or more radicals R5, and dibenzothiophene optionally substituted with one or more radicals R5;
R5 is selected from the group consisting of (i) H, D, F, Cl, Br, I, CN, Si(R2)3, (ii) a linear alkyl, alkoxy or thioalkyl having 1 to 31 carbon atoms, (iii) a branched alkyl, cycloalkyl, branch alkoxy, or branched thioalkyl having 3 to 31 carbon atoms, (iv) benzene, naphthalene, phenanthrene, fluorene, spirobifluorene, dibenzofuran, dibenzothiophene, and a combination of 2, 3, 4, or 5 of these groups, (v) an aryloxy having 5 to 40 aromatic ring atoms, and (vi) an aralkyl having 5 to 40 aromatic ring atoms, wherein when there are a plurality of R5's in General Formula (1), R5's are the same or different;
R2 is selected from the group consisting of (i) H, D, F, Cl, Br, I, CN, (ii) a linear alkyl, alkoxy or thioalkyl having 1 to 40 carbon atoms, (iii) a branched alkyl, cycloalkyl, branched alkoxy, or branched thioalkyl having 3 to 40 carbon atoms, (iv) benzene, naphthalene, phenanthrene, fluorene, spirobifluorene, dibenzofuran, dibenzothiophene, and a combination of 2, 3, 4, or 5 of these groups, (v) an aryloxy having 5 to 60 aromatic ring atoms, and (vi) an aralkyl having 5 to 60 aromatic ring atoms; and
R1, R3, and R4 are the same or different, and are selected from the group consisting of (i) H, D, F, Cl, Br, I, CN, Si(R2)3, (ii) a linear alkyl, alkoxy or thioalkyl having 1 to 40 carbon atoms (iii) a branched alkyl, cycloalkyl, branched alkoxy, or branched thioalkyl having 3 to 40 carbon atoms, (iv) benzene, naphthalene, phenanthrene, fluorene, spirobifluorene, dibenzofuran, dibenzothiophene, and a combination of 2, 3, 4, or 5 of these groups, (v) an aryloxy having 5 to 60 aromatic ring atoms, and (vi) an aralkyl having 5 to 60 aromatic ring atoms.

US Pat. No. 10,396,288

ORGANIC ELECTROLUMINESCENT ELEMENT AND ELECTRONIC DEVICE

IDEMITSU KOSAN CO., LTD.,...

40. A compound is represented by any of formulae (3-1) and (4-2):
wherein:
R1 and R2 each independently represent a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 20 ring carbon atoms, a group represented by —Si(R101)(R102)(R103), a substituted or unsubstituted aryl group having 6 to 30 ring carbon atoms, or a substituted or unsubstituted heteroaryl group having 5 to 30 ring atoms; and
R11 to R18, R25 to R27, R29 to R33, and R35 to R36 each independently represents a hydrogen atom, a fluorine atom, a cyano group, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 20 ring carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 20 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 30 ring carbon atoms, a substituted or unsubstituted alkylthio group having 1 to 20 carbon atoms, a substituted or unsubstituted arylthio group having 6 to 30 ring carbon atoms, a group represented by —Si(R101)(R102)(R103), a group represented by —N(R104)(R105), a substituted or unsubstituted aryl group having 6 to 30 ring carbon atoms, a substituted or unsubstituted heteroaryl group having 5 to 30 ring atoms, or a group represented by —Z—Ra;
R101 to R105 each independently represent a hydrogen atom, a substituted or unsubstituted alkyl group having 1 to 20 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 20 ring carbon atoms, a substituted or unsubstituted aryl group having 6 to 50 ring carbon atoms, or a substituted or unsubstituted heteroaryl group having 5 to 50 ring atoms;
the group represented by —Z—Ra, and is represented by any of formulae (a) to (c):

Z1 to Z3 each independently represent a single bond, a substituted or unsubstituted arylene group having 6 to 30 ring carbon atoms, a substituted or unsubstituted heteroarylene group having 5 to 30 ring atoms, or a divalent linking group in which 2 to 4 groups selected from the arylene group and the heteroarylene group are linked together;
L1 and L2 each independently represent a single bond, a substituted or unsubstituted arylene group having 6 to 30 ring carbon atoms, a substituted or unsubstituted heteroarylene group having 5 to 30 ring atoms, or a divalent linking group in which 2 to 4 groups selected from the arylene group and the heteroarylene group are linked together;
Ar2 and Ar3 each independently represent a substituted or unsubstituted aryl group having 6 to 30 ring carbon atoms, or a substituted or unsubstituted heteroaryl group having 5 to 30 ring atoms;
HAr represents a substituted or unsubstituted heteroaryl group having 5 to 30 ring atoms; and
Ar4 represents a substituted or unsubstituted aryl group having 14 to 30 ring carbon atoms,
provided that one to three selected from R11 to R18, R25 to R27, and R29 to R30 of formula (3-1), and one or two selected from R11 to R18, R31 to R33, and R35 to R36 of formula (4-2) each represent a group represented by —Z—Ra.

US Pat. No. 10,396,286

REGIOREGULAR PYRIDAL[2,1,3]THIADIAZOLE ?-CONJUGATED COPOLYMERS FOR ORGANIC SEMICONDUCTORS

The Regents of the Univer...

1. A method of preparing a regioregular donor-acceptor copolymer, comprising:regioselectively preparing a monomer, wherein the monomer comprises a donor moiety having a first electron affinity in combination with an acceptor moiety having a second electron affinity; and
reacting the monomer to produce a donor-acceptor copolymer that comprises a regioregular conjugated main chain section, wherein the combination of the donor moiety having the first electron affinity and the acceptor moiety having the second electron affinity is selected so as to induce charge transfer between the donor moiety and the acceptor moiety in the donor-acceptor copolymer, wherein:
the charge carrier mobility of the regioregular donor-acceptor copolymer is greater than the charge carrier mobility of a regiorandom donor-acceptor copolymer of similar composition.

US Pat. No. 10,396,285

APPARATUS AND METHOD FOR DETECTING PRESENCE OF ATTENUATION IN OLED DEVICE

BOE Technology Group Co.,...

1. An apparatus for detecting a presence of an attenuation in an organic light emitting display (OLED) device, comprising:a difference function construction circuit, configured for constructing a first light brightness difference function ƒ1(x), according to a difference between a light brightness of the OLED device under a first luminous constraint and a light brightness of the OLED device under a second luminous constraint, before aging of the OLED device; constructing a second light brightness difference function ƒ2(x), according to a difference between a light brightness of the OLED device under the first luminous constraint and a light brightness of the OLED device under the second luminous constraint, after aging of the OLED device; wherein the first luminous constraint comprises a variable magnetic field, the second luminous constraint comprises a constant microwave and a variable magnetic field, and x is an intensity of the variable magnetic field;
an integrating circuit, configured for integrating the first light brightness difference function ƒ1(x), to obtain a first integration result Ena, and integrating the second light brightness difference function ƒ2(x), to obtain a second integration result Ea, within an intensity range of the variable magnetic field;
a comparing circuit, configured for comparing
wherein, Lna is a light brightness of a pre-aging OLED device under a non-luminous constraint, and La is a light brightness of a post-aging OLED device under the non-luminous constraint; anda determining circuit, configured for determining the presence of an intrinsic attenuation in a light emitting material of a light emitting layer in the OLED device, according to a comparison result between

US Pat. No. 10,396,283

METHOD FOR PRODUCING VAPOR DEPOSITION MASK, VAPOR DEPOSITION MASK PREPARATION BODY, METHOD FOR PRODUCING ORGANIC SEMICONDUCTOR ELEMENT, METHOD FOR PRODUCING ORGANIC EL DISPLAY, AND VAPOR DEPOSITION MASK

Dai Nippon Printing Co., ...

1. A method for producing a vapor deposition mask including a metal mask in which a metal mask opening is formed and a resin mask in which a resin mask opening corresponding to a pattern to be produced by vapor deposition is formed at a position overlapping with the metal mask opening, the metal mask and the resin mask being stacked, the method comprising:a step of preparing a vapor deposition mask preparation body in which the metal mask is provided on one surface of a resin plate for obtaining the resin mask, and a protective sheet with peel strength not less than about 0.0004 N/10 mm and less than about 0.2 N/10 mm in conformity with JIS Z-0237:2009 is provided on the other surface of the resin plate;
a step of irradiating, with respect to the vapor deposition mask preparation body, the resin plate with laser light from the metal mask side to form the resin mask opening corresponding to the pattern to be produced by vapor deposition in the resin plate; and
a step of peeling off the protective sheet from the resin mask in which the resin mask opening corresponding to the pattern to be produced by vapor deposition is formed.

US Pat. No. 10,396,282

MASK FRAME ASSEMBLY FOR THIN LAYER DEPOSITION, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING DISPLAY APPARATUS BY USING THE MASK FRAME ASSEMBLY

Samsung Display Co., Ltd,...

1. A mask frame assembly through which a deposition material to be deposited on a substrate passes, the mask frame assembly comprising:a frame comprising an opening; and
a mask coupled to the frame,
wherein:
the mask comprises:
a main body part having a first thickness and comprising a pattern part and at least one first alignment key, the pattern part comprising pattern holes through which the deposition material passes; and
a support part having a second thickness greater than the first thickness and contacting the frame and comprising at least one second alignment key;
a lower surface of the main body part is higher than a plane connecting two opposing lower surfaces of the support part contacting the frame;
an upper surface of the main body part and an upper surface of the support part are arranged in the same plane; and
the at least one first alignment key and the at least one second alignment key are aligned to correspond to each other in a length direction of the mask.

US Pat. No. 10,396,281

METHODS FOR FORMING ARRAYS OF SMALL, CLOSELY SPACED FEATURES

Micron Technology, Inc., ...

1. A method of semiconductor processing, comprising:forming a mandrel on an underlying substrate, comprising:
on a first level of the substrate, forming a grid of intersecting lines of material over an upper surface of the substrate, the grid of intersecting lines comprising first lines extending along a first direction and second lines extending along a second direction that crosses the first direction, the first and second lines extending to a first elevation above the upper surface of the substrate; and
on a second level of the substrate, forming pillars on the substrate that extend upwards- from intersections of the intersecting lines to a second elevation above the upper surface of the substrate; and
forming spacers on the substrate at sidewalls of the mandrel, the spacers being formed on sidewalls of the intersecting lines and on sidewalls of the pillars, wherein forming spacers comprises:
blanket depositing a layer of spacer material over the mandrel;
and directionally etching the layer of spacer material to define the spacers at the sidewalls of the mandrel.

US Pat. No. 10,396,280

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR SAME

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:a plurality of first interconnections extending in a first direction;
a second interconnection extending in a second direction different from the first direction; and
a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film comprising silicon and a semiconductor layer comprising two or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium,
wherein a concentration of the selected elements included in the semiconductor layer changes along a third direction from the first interconnections to the second interconnection.

US Pat. No. 10,396,277

MAGNETIC MEMORY DEVICES

Samsung Electronics Co., ...

1. A magnetic memory device, comprising:a lower interlayer insulating layer on a substrate; and
a plurality of magnetic tunnel junction patterns on the lower interlayer insulating layer, the plurality of magnetic tunnel junction patterns isolated from direct contact with each other in a first plane extending parallel to a top surface of the substrate,
wherein the lower interlayer insulating layer includes an upper surface, the upper surface of the lower interlayer insulating layer including a recessed surface and a top surface, the recessed surface at least partially defining an inner sidewall and a bottom surface of a recess region in the lower interlayer insulating layer between adjacent magnetic tunnel junction patterns of the plurality of magnetic tunnel junction patterns, such that the recessed surface at least partially defines the recess region,
wherein the inner sidewall of the recess region is inclined at an acute angle with respect to the top surface of the substrate, and the bottom surface of the recess region has a shape that is convex toward the top surface of the substrate, in a plane extending perpendicular to the top surface of the substrate.

US Pat. No. 10,396,276

ELECTRIC-CURRENT-GENERATED MAGNETIC FIELD ASSIST TYPE SPIN-CURRENT-INDUCED MAGNETIZATION REVERSAL ELEMENT, MAGNETORESISTANCE EFFECT ELEMENT, MAGNETIC MEMORY AND HIGH-FREQUENCY FILTER

TDK CORPORATION, Tokyo (...

1. An electric-current-generated magnetic field assist type spin-current-induced magnetization reversal element comprising:a first ferromagnetic metal layer with a varying magnetization direction;
spin-orbit torque wiring that (1) adjoins the first ferromagnetic metal layer, (2) extends in a second direction in a plane orthogonal to a first direction normal to the first ferromagnetic metal layer and (3) comprises a pure spin current generation portion and low resistance portion; and
electric-current-generated magnetic field assist wiring that is arranged so as to be electrically insulated from the first ferromagnetic metal layer and in which flows an electric current for forming a magnetic field that assists magnetization reversal of the first ferromagnetic metal layer: wherein:
the spin-orbit torque wiring is configured to reverse the magnetization direction of the first ferromagnetic layer by inducing spin orbit torque in the first ferromagnetic layer;
the pure spin current generation portion adjoins the first ferromagnetic metal layer and is capable of reversing the magnetization direction of the first ferromagnetic layer by inducing the spin orbit torque in the first ferromagnetic layer; and
the low resistance portion comprises a material having a lower electrical resistance than the pure spin current generation portion.

US Pat. No. 10,396,275

MAGNETIC MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A magnetic memory device, comprises:a first magnetic tunnel junction pattern and a second magnetic tunnel junction pattern that are horizontally spaced apart from each other on a substrate;
a first bit line disposed on the first magnetic tunnel junction pattern;
a first select element disposed in the substrate,
wherein the first bit line is electrically connected to the first select element through the first magnetic tunnel junction pattern;
a second bit line disposed below the second magnetic tunnel junction pattern;
a second select element disposed in the substrate,
wherein the second bit line is electrically connected to the second select element through the second magnetic tunnel junction pattern; and
a first top electrode and a second top electrode respectively disposed on the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern,
wherein each of the first top electrode and the second top electrode comprises a metal nitride pattern and a metal pattern disposed on the metal nitride pattern, the metal nitride pattern being thinner than the metal pattern,
wherein each of the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern comprises a non-magnetic metallic capping layer that directly contacts the metal nitride pattern,
wherein the non-magnetic metallic capping layer has a single sublayer, and
wherein each of the first top electrode and the second top electrode has an increasing width toward the non-magnetic metallic capping layer.

US Pat. No. 10,396,274

SPIN ELECTRONICS ELEMENT AND METHOD OF MANUFACTURING THEREOF

TOHOKU UNIVERSITY, Senda...

1. A method of manufacturing a spintronics element from a plurality of laminated layers, comprising the steps of(a) forming a plurality of laminated layers in a first manufacturing equipment;
(b) forming a first wafer in the first manufacturing equipment, including applying a protection layer directly on a non-magnetic uppermost layer of the plurality of laminated layers so that the protection layer prevents alteration of characteristics of the uppermost layer; and
(c) exposing the first wafer to an atmosphere outside of the first manufacturing equipment, the atmosphere including H2O, a partial pressure of H2O in said atmosphere being equal to or larger than 10?4 Pa;
(d) putting the first wafer in a second manufacturing equipment after said step (c); and
(e) in the second manufacturing equipment, removing an upper portion of the protection layer so as to leave at least one atomic layer of the protection layer, said at least one atomic layer being a transition layer formed in an interface between the non-magnetic uppermost layer and the protection layer.

US Pat. No. 10,396,273

FACILITY AND METHOD FOR MANUFACTURING TORQUE SENSOR SHAFT

USUI CO., LTD., Shizuoka...

1. Equipment for manufacturing a torque sensor shaft by forming a magnetostrictive region including a metallic glass coating in a predetermined pattern on a side face of a hollow or solid shaft-shaped workpiece, whereinthe magnetostrictive region has a formation part, which is disposed between opposing first and second ends of the shaft-shaped workpiece,
the shaft-shaped workpiece is rotatably attached on a conveying pallet,
the conveying pallet is successively conveyed to each of work devices including a preheating device for the shaft-shaped workpiece, a thermal spraying device configured to form a metallic glass coating on the side face of the shaft-shaped workpiece, a masking device configured to provide a covering corresponding to the pattern on the coating, and a shot blasting device configured to provide shot blasting directed toward the metallic glass coating including the covering,
preheating, thermal spraying, masking, and shot blasting are performed on the shaft-shaped workpiece while rotating the shaft-shaped workpiece on the conveying pallet at each of the work devices, and
when on the conveying pallet, the first and second ends of the shaft-shaped workpiece are covered by first and second cylindrical covers respectively, and
the shaft-shaped workpiece is of such length that the formation part of the shaft-shaped workpiece is exposed between opposing end faces of the first and second cylindrical covers.

US Pat. No. 10,396,272

DISPLAY DISTORTION FOR ALIGNMENT WITH A USER GAZE DIRECTION

INTERNATIONAL BUSINESS MA...

7. A device, comprising:at least one memory storing computer-executable instructions; and
at least one processor configured to access the at least one memory and execute the computer-executable instructions to:
identify a device-based event;
determine that the device-based event satisfies one or more criteria for distorting the display;
determine a gaze direction of a user of the device;
determine distortion elements to activate based at least in part on the gaze direction of the user; and
activate the distortion elements to cause a display coupled to the device to distort and align with the gaze direction of the user, wherein the at one processor is configured to activate the distortion elements by executing the computer-executable instructions to cause an electric fields to be applied to a plurality of electroactive polymer (EAP) portions disposed in a plurality of layers, wherein application of the electric field causes the plurality of EAP portions to deform, wherein the plurality of EAP portions comprised at least two EAP portions that are disposed in different layers and that overlap non-orthogonally, and wherein the different layers are electrically isolated from one another.

US Pat. No. 10,396,271

PIEZOELECTRIC ELEMENT, METHOD OF FORMING PIEZOELECTRIC ELEMENT, AND ULTRASONIC DEVICE

Seiko Epson Corporation, ...

1. A piezoelectric element comprising:a substrate;
a piezoelectric body that is provided on the substrate and that has a curved exterior in a plan view;
a first wiring that is provided from a first position on the piezoelectric body to the substrate; and
a second wiring that is provided from a second position on the piezoelectric body to the substrate,
wherein an angle formed by a normal direction of an exterior at the first position and a normal direction of an exterior at the second position is more than 90 degrees and is equal to or less than 270 degrees.

US Pat. No. 10,396,270

VIBRATION ACTUATOR THAT IS EASY IN CONDUCTION INSPECTION

Canon Kabushiki Kaisha, ...

1. A vibration actuator in which a vibration element and a driven element contact each other, and the driven element and the vibration element move relatively,the vibration element comprising:
an elastic body of which a main component comprises a material which is electrically insulating, dielectric, or semi-conductive; and
an electromechanical energy conversion element that is joined to the elastic body,
the electromechanical energy conversion element comprising:
a piezoelectric body;
a first electrode that is provided on a surface of the piezoelectric body, by which surface the piezoelectric body is joined to the elastic body, the first electrode having a closed loop structure;
at least two second electrodes that are provided in a manner opposed to the first electrode via the piezoelectric body; and
at least two conduction paths each having a conductor arranged in a through-hole formed in the piezoelectric body or a groove formed in a side surface of the piezoelectric body,
wherein the at least two conduction paths respectively and individually connect the at least two second electrodes to the first electrode.

US Pat. No. 10,396,269

INTERCONNECT STRUCTURES FOR ASSEMBLY OF SEMICONDUCTOR STRUCTURES INCLUDING SUPERCONDUCTING INTEGRATED CIRCUITS

Massachusetts Institute o...

1. A multi-layer semiconductor structure, comprising:a first semiconductor structure having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces;
a second semiconductor structure having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces, wherein at least one of the first and second semiconductor structures is a superconducting semiconductor structure; and
one or more interconnect structures, each of the interconnect structures disposed between the first and second semiconductor structures and coupled to respective ones of the interconnect pads provided on the first and second semiconductor structures, and each of the interconnect structures including a plurality of interconnect sections, wherein at least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material;
wherein each of the interconnect structures has first and second opposing portions and includes:
a first interconnect section having first and second opposing portions, wherein the first portion of the first interconnect section corresponds to the first portion of the interconnect structure;
a second interconnect section having first and second opposing portions, wherein the first portion of the second interconnect section is disposed over the second portion of the first interconnect section; and
a third interconnect section having first and second opposing portions, wherein the first portion of the third interconnect section is disposed over the second portion of the second interconnect section, and the second portion of the third interconnect section corresponds to the second portion of the interconnect structure;
wherein the first interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials; and
wherein the third interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials;
wherein each of the conductive layers has a different, respective melting point;
wherein:
the first interconnect section of the first semiconductor structure consists of a first superconducting layer, a second superconducting layer disposed on the first superconducting layer, and a third conductive layer disposed on the second superconducting layer,
the second interconnect section of the first semiconductor structure consists of a superconducting bump disposed on the third layer of the first interconnect section; and
the third interconnect section of the first semiconductor structure consists of a fourth superconducting layer, a fifth superconducting layer disposed on the fourth superconducting layer, and a sixth conductive layer disposed on the fifth superconducting layer;
wherein at least one of the first, second, and third interconnect sections comprise an interface with a second one of the first, second, and third interconnect sections corresponding to a multi-melt interface that includes at least one superconducting and/or a partially superconducting material.

US Pat. No. 10,396,268

QUBIT NETWORK NON-VOLATILE IDENTIFICATION

INTERNATIONAL BUSINESS MA...

1. A method of forming a superconducting chip comprising:providing resonant units having resonant frequencies, Josephson junctions being in the resonant units;
causing one or more of the Josephson junctions to have a shorted tunnel barrier; and
causing one or more of the Josephson junctions to have no shorted tunnel barrier, wherein the resonant frequencies are designed to fall within a frequency band for each of the resonant units having the no shorted tunnel barrier in the Josephson junctions.

US Pat. No. 10,396,267

THERMOELECTRIC CONVERSION ELEMENT AND METHOD OF MANUFACTURING THE SAME, AND HEAT RADIATION FIN

NEC Corporation, Tokyo (...

1. A heat radiation fin, comprising:a supporting structure;
a magnetic body jointed to said supporting structure and having a magnetization directed in a first direction; and
an electromotive body exhibiting a spin orbit coupling and jointed to said magnetic body wherein said supporting structure includes:
a base member to be coupled to an object to be cooled; and
a plurality of fin members having a plate shape and coupled to said base member, and
wherein a joint surface on which said magnetic body and said supporting structure are jointed and a joint surface on which said magnetic body and said electromotive body have concavities and convexities,
wherein said joint surface has a shape in which a plurality of unit faces is arrayed in a second direction perpendicular to said first direction, and
wherein each of said unit faces is a non-flat face obtained by moving a first generating which is not straight line located in a flat face perpendicular to said first direction, in said first direction.

US Pat. No. 10,396,266

THERMOCOUPLE RIBBON AND ASSEMBLY

1. A thermocouple ribbon comprising:a) a pair of flat conductors constructed from a pair of dissimilar alloys, wherein the conductors are flat throughout their entire length, thereby minimizing an overall thickness of the thermocouple ribbon;
b) an upper layer of polyimide film laminating the pair of flat conductors; and
c) a lower layer of polyimide film laminating the pair of flat conductors,
the upper layer and the lower layer of polyimide film each comprising a layer of polyimide and a layer of fluorinated ethylene propylene fluoropolymer, wherein the upper layer and the lower layer of polyimide film provide a vacuum seal integrity along the entire length of the thermocouple ribbon, wherein each layer of fluorinated ethylene propylene fluoropolymer is a same thickness in both the upper layer and the lower layer of polyimide film, and further wherein a thickness of each layer of polyimide is equivalent to the thickness of each layer of fluorinated ethylene propylene fluoropolymer,
wherein the vacuum seal integrity is created by heating the upper layer and the lower layer of the polyimide film to increase the temperature of each of the layers of fluorinated ethylene propylene fluoropolymer to a melting point of the fluorinated ethylene propylene fluoropolymer, and upon cooling, the layers of fluorinated ethylene propylene fluoropolymer solidify and bond the thermocouple ribbon together.

US Pat. No. 10,396,262

LIGHT EMITTING DEVICE AND SUBSTRATE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a plurality of light emitting elements, each comprising an upper electrode and a lower electrode, the plurality of light emitting elements including:
a first light emitting element configured to emit light of a first color, and
a second light emitting element configured to emit light of a second color different from the first color; and
a substrate on which the light emitting elements are disposed, the substrate comprising a plurality of wiring patterns disposed at an upper surface of the substrate, each wiring pattern corresponding to a respective one of the light emitting elements;
wherein each of the wiring patterns comprises:
a first conductive pattern comprising:
a light emitting element mounting region to which the lower electrode of a corresponding one of the light emitting elements is connected, the light emitting element mounting region being defined by a first side, a second side, a third side, and a fourth side in a plan view, and
a contact region connected to a portion of the first side of the light emitting element mounting region; and
a second conductive pattern surrounding a portion of the first side where the contact region is not present, an entirety of the second side, and a portion of or an entirety of the third side, wherein a first end portion of the second conductive pattern at the third side is positioned nearer to the fourth side than a second end portion of the second conductive pattern at the first side is to the fourth side;
wherein the plurality of wiring patterns includes:
a first wiring pattern that corresponds to the first light emitting element, and
a second wiring pattern that corresponds to the second light emitting element,
wherein the third side of the second wiring pattern faces the first side of the first wiring pattern; and
wherein the contact region of the first wiring pattern and the second conductive pattern of the second wiring pattern are connected to each other via at least one first wire, and the second conductive pattern of the first wiring pattern and the upper electrode of the second light emitting element are connected to each other via at least one second wire.

US Pat. No. 10,396,261

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE

Nichia Corporation, Anan...

1. A method of manufacturing a light emitting device, the method comprising: providing a substantially flat plate-shaped base member formed of an insulating material which in plan view includes at least one first portion having an upper surface on which a conductive pad is disposed, and a second portion surrounding the at least one first portion and having inner lateral surfaces;mounting at least one light emitting element on the conductive pad disposed on the at least one first portion;
shifting a relative positional relationship between the at least one first portion and the second portion in an upper-lower direction to form at least one recess defined by: an upper surface of the at least one first portion defining a bottom surface of the at least one recess, and at least portions of the inner lateral surfaces of the second portion defining lateral surfaces of each of the at least one recess; and
bonding the at least one first portion and the second portion with each other;
wherein a pair of the conductive pads are mounted on the at least one first portion; and
wherein the at least one light emitting element is electrically connected to both of the pair of the conductive pads by respective wires.

US Pat. No. 10,396,257

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device, comprising:providing a mold with a mold recess having a bottom and an inner peripheral surface that defines the mold recess and that is connected to the bottom, the bottom including a bottom projection and a bottom recess surrounding the bottom projection to define the bottom projection that has a projection top surface and a projection peripheral surface opposing the inner peripheral surface, the projection top surface defining a part of the bottom;
mounting a light emitting element on the bottom projection in the mold recess such that a light extraction surface of the light emitting element faces the projection top surface and such that an outer peripheral surface of the light emitting element opposes the inner peripheral surface of the mold recess;
providing a covering material in the mold recess to cover the inner peripheral surface of the mold recess, the outer peripheral surface of the light emitting element, and the projection peripheral surface;
removing the mold to provide a recess in the covering material; and
providing a light-transmissive material in the recess in the covering material.

US Pat. No. 10,396,249

SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING THE SAME

NICHIA CORPORATION, Anan...

1. A semiconductor light emitting element comprising:a semiconductor laminated body including an n-type semiconductor layer and a p-type semiconductor layer, which is formed above an upper surface of the n-type semiconductor layer;
a first metal film provided on an upper surface of the p-type semiconductor layer;
a second metal film having an upper surface and a lower surface extending in a lateral direction, and having a lateral surface extending from the upper surface to the lower surface, the second metal film covering a surface of the first metal film, and provided in contact with the upper surface of the p-type semiconductor layer;
a third metal film having an upper surface and a lower surface extending in a lateral direction, and having a lateral surface extending from the upper surface to the lower surface, the third metal film provided within a portion of the upper surface of the second metal film such that the third metal film is in contact with the second metal film;
a metal oxide film including an oxide of a metal material that is the same as a metal material constituting the second metal film, the metal oxide film covering the lateral surface and the upper surface of the second metal film outside the third metal film in a plan view; and
an insulation film that is made of an oxide to cover a surface of the metal oxide film,
wherein insular regions are provided on a portion of the upper surface of the second metal film in an area directly under the lower surface of the third metal film, the insular regions comprising an oxide of a metal material that is the same as an oxide of a metal material constituting the metal oxide film.

US Pat. No. 10,396,247

LIGHT-EMITTING DEVICE PACKAGE

LG INNOTEK CO., LTD., Se...

14. A light-emitting device package, comprising:a package body;
at least one light-emitting device above the package body;
an adhesive layer between the at least one light-emitting device and the package body;
a dam portion disposed on an upper surface of the package body to form an adhesive-layer-accommodating portion, the adhesive-layer-accommodating portion accommodating the adhesive layer therein;
first and second wire bonding pads disposed to be spaced apart from each other around the adhesive-layer-accommodating portion; and
first and second wires connecting first and second electrodes of the at least one light-emitting device and the first and second wire bonding pads to each other respectively,
wherein a cross section of the adhesive-layer-accommodating portion comprises:
a bottom surface being the upper surface of the package body; and
side surfaces extending from the bottom surface, the side surfaces being disposed to be inclined at an acute angle with respect to a plane including an optical axis,
wherein the adhesive-layer-accommodating portion includes an opening having a first width at a top side thereof,
wherein the first width is smaller than a second width of the bottom surface, and
wherein the package body includes a cavity, and the at least one light-emitting device, the adhesive layer, and the adhesive-layer-accommodating portion are located in the cavity.

US Pat. No. 10,396,242

SEMICONDUCTOR LIGHT EMITTING DEVICE

Nichia Corporation, Anan...

1. A semiconductor light emitting device comprising:a substrate that has a main surface that comprises a plurality of protrusions in a two-dimensionally repeated pattern;
a plurality of semiconductor layers disposed on the main surface of the substrate and comprising a GaN based semiconductor; and
an ohmic electrode disposed on a top layer of the semiconductor layers and comprising a plurality of openings,
wherein each of the protrusions has a side surface that is inclined to a stacking plane of the semiconductor layers and configured to scatter or diffract light generated in the semiconductor layers, and
wherein at least one side surface of the protrusions is located in each of the openings in plan view of the semiconductor light emitting device.

US Pat. No. 10,396,241

DIFFUSION REVEALED BLOCKING JUNCTION

Apple Inc., Cupertino, C...

1. A light emitting diode comprising:laterally opposite sidewalls;
a first cladding layer spanning between the laterally opposite sidewalls, and doped with a first dopant type;
an active layer over the first cladding layer and spanning between the laterally opposite sidewalls;
a second cladding layer over the active layer and spanning between the laterally opposite sidewalls, and doped with a second dopant type opposite the first dopant type; and
a co-doped region embedded within the first cladding layer and spanning between the laterally opposite sidewalls, and including dopants of the first dopant type and the second dopant type;
a current injection region within the laterally opposite sidewalls; and
a current confinement region laterally surrounding the current injection region, and spanning along the laterally opposite sidewalls, wherein the current confinement region comprises a dopant concentration of the first dopant type extending through the first cladding layer; and
wherein the current confinement region dopant concentration extends through and overlaps the co-doped region to form a net second dopant type blocking junction within the first cladding layer, and the current confinement region dopant concentration surrounds a net first dopant type region of the co-doped region that is within first cladding layer and overlaps the current injection region.

US Pat. No. 10,396,238

PRINTABLE INORGANIC SEMICONDUCTOR STRUCTURES

X-Celeprint Limited, Cor...

1. A method of making an inorganic semiconductor structure suitable for micro-transfer printing, comprising:providing a source substrate;
forming a semiconductor layer on the source substrate, wherein the semiconductor layer has a first side and a second side opposite the first side and adjacent to the substrate;
removing a portion of the semiconductor layer to form a cantilever extension;
forming a first electrical contact on the semiconductor layer;
forming a second electrical contact on the cantilever extension;
removing a portion of the semiconductor layer surrounding each pair of first and second electrical contacts to form a trench surrounding a semiconductor element made from the semiconductor layer, the semiconductor element having a substrate side in contact with the source substrate and a handle side opposite the substrate side;
providing a sacrificial layer covering the first and second electrical contacts and covering at least a portion of the handle side of the semiconductor element and filling a portion of the trench;
providing an interlayer over the sacrificial layer, the interlayer having different chemical selectivity than the sacrificial layer, wherein a portion of the interlayer contacts the source substrate at the base of the trench to form an anchor;
adhering the interlayer to a handle substrate;
removing the source substrate to expose the substrate side of the semiconductor element;
forming a tether bridging the exposed substrate side of the semiconductor element to the anchor; and
removing the sacrificial layer, thereby forming a printable semiconductor structure partially released from the handle substrate and physically secured to the anchor by the tether.

US Pat. No. 10,396,234

PACKAGE STRUCTURE OF LONG-DISTANCE SENSOR AND PACKAGING METHOD OF THE SAME

Lingsen Precision Industr...

1. A package structure of a long-distance sensor, the package structure comprising:a substrate having a bearing surface;
a light-emitting chip disposed on the bearing surface;
a sensing chip disposed on the bearing surface and separated from the light-emitting chip;
two packaging gel bodies covering the light-emitting chip and the sensing chip respectively and separated from each other; and
a cap disposed on the bearing surface and the packaging gel bodies, fastened to the bearing surface and the packaging gel bodies by adhesive, and provided with a light-emitting hole located above the light-emitting chip and a light-receiving hole located above the sensing chip;
wherein a top surface of each of the packaging gel bodies has a lens portion and a shoulder portion; the cap comprises a transverse section provided with the light-emitting hole and the light-receiving hole; the transverse section of the cap is directly fastened to the shoulder portions of the top surfaces of the packaging gel bodies by the adhesive.

US Pat. No. 10,396,233

SOLAR CELL AND SOLAR CELL MODULE

Panasonic Intellectual Pr...

1. A solar cell comprising:a single-crystal silicon substrate;
a first silicon oxide layer disposed directly on a first principal surface of the silicon substrate and including phosphorus as an impurity;
a first amorphous silicon layer disposed in contact with the first silicon oxide layer;
a transparent electrode disposed on the first amorphous silicon layer; and
a non-transparent metal electrode disposed on the transparent electrode, wherein
the silicon substrate, the first silicon oxide layer, the first amorphous silicon layer, the transparent electrode, and the non-transparent metal electrode are stacked in the recited order,
the first principal surface of the silicon substrate comprises a diffusion region having a first phosphorus concentration higher than a second phosphorous concentration of a region of the silicon substrate other than the first principal surface, and
the first amorphous silicon layer comprises: a first intrinsic amorphous silicon layer being substantially intrinsic and disposed on and in direct contact with the first silicon oxide layer; and a first conductive amorphous silicon layer disposed on and in direct contact with the first intrinsic amorphous silicon layer and comprising a dopant of a first conductivity type.

US Pat. No. 10,396,230

BACKSIDE CONTACT SOLAR CELLS WITH SEPARATED POLYSILICON DOPED REGIONS

SUNPOWER CORPORATION, Sa...

1. A solar cell comprising:a substrate having a front side and a backside;
a first dielectric layer disposed on the backside of the substrate;
a P-type doped polysilicon region; and
an N-type doped polysilicon region that is adjacent to the P-type doped polysilicon region,
wherein the P-type and N-type doped polysilicon regions are disposed on the first dielectric layer, and the P-type doped polysilicon region is physically separated from the N-type doped polysilicon region.

US Pat. No. 10,396,227

METHOD FOR FABRICATING A SOLAR MODULE OF REAR CONTACT SOLAR CELLS USING LINEAR RIBBON-TYPE CONNECTOR STRIPS AND RESPECTIVE SOLAR MODULE

REC SOLAR PTE. LTD., Sin...

1. A method for fabricating a solar module, the method comprising:providing a plurality of rear contact solar cells having emitter contacts and base contacts on a rear surface of a semiconductor substrate and soldering pad arrangements applied on emitter contacts and on base contacts,
wherein each soldering pad arrangement comprises one or more soldering pads arranged linearly and
wherein the soldering pad arrangements are arranged on the rear surface of the semiconductor substrate asymmetrically with respect to a longitudinal axis of the semiconductor substrate;
separating each of the rear contact solar cells into first and second cell portions along a line perpendicular to the longitudinal axis of the semiconductor substrate;
arranging the plurality of first and second cell portions of the rear contact solar cells alternately along a line such that the second cell portions are arranged in a 180° orientation with respect to the first cell portions and such that soldering pad arrangements of emitter contacts and of base contacts of first cell portions are aligned with soldering pad arrangements of base contacts and of emitter contacts of second cell portions, respectively;
electrically connecting the plurality of first and second cell portions of the rear contact solar cells in series by
arranging a linear ribbon-type connector strip on top of a linear soldering pad arrangement of an emitter contact of each first cell portion and on top of an aligned linear soldering pad arrangement of a base contact of a second cell portion neighboring the respective first cell portion on one side, and by
arranging a linear ribbon-type connector strip on top of a linear soldering pad arrangement of a base contact of the respective first cell portion and on top of an aligned linear soldering pad arrangement of an emitter contact of a second cell portion neighboring the respective first cell portion on an opposite side, and by
electrically connecting the connector strips to the underlying soldering pad arrangements.

US Pat. No. 10,396,224

SOLAR CELL INTEGRATED FILM MATERIAL

Chukoh Chemical Industrie...

1. A solar cell integrated film material comprising:a film material comprising a heat-resistant fabric and a fluorocarbon resin layer formed on both sides of the heat-resistant fabric;
a solar cell comprising a weather resistant layer;
a glass fiber sheet provided between the film material and the solar cell;
a first bonding layer provided between the film material and the glass fiber sheet; and
a second bonding layer provided between the glass fiber sheet and the solar cell,
wherein the weather resistant layer is an outermost layer of the solar cell,
a surface of the other outermost layer of the solar cell directly adheres to the second bonding layer and the second bonding layer directly adheres to the glass fiber sheet, and
the first bonding layer consists of a first adhesive resin or a mixture of a first adhesive resin and silicon dioxide particles, and the second bonding layer consists of a second adhesive resin, wherein the first and second adhesive resins are the same.

US Pat. No. 10,396,223

METHOD FOR MAKING CMOS IMAGE SENSOR WITH BURIED SUPERLATTICE LAYER TO REDUCE CROSSTALK

ATOMERA INCORPORATED, Lo...

1. A method for making a CMOS image sensor comprising:forming a superlattice on a semiconductor substrate having a first conductivity type, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
forming a plurality of laterally adjacent photodiodes on the superlattice by
forming a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate,
forming a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type,
forming a first well around a periphery of the retrograde well having the first conductivity type, and
forming a second well overlying the retrograde well having the first conductivity type.

US Pat. No. 10,396,214

METHOD OF FABRICATING ELECTROSTATICALLY ENHANCED FINS AND STACKED NANOWIRE FIELD EFFECT TRANSISTORS

International Business Ma...

1. A semiconductor structure comprising:a vertical stack of semiconductor nanowires located atop a surface of a base layer, wherein the base layer has a concave upper surface located adjacent the vertical stack of semiconductor nanowires; and
a semiconductor material protruding portion located on a sidewall surface of each of the semiconductor nanowires.

US Pat. No. 10,396,208

VERTICAL TRANSISTORS WITH IMPROVED TOP SOURCE/DRAIN JUNCTIONS

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a top source/drain junction of a vertical transistor, the method comprising:forming a structure comprising a bottom source/drain, a fin channel comprising a semiconductor material and extending vertically from the bottom source/drain, and a gate arranged around the fin channel, the gate comprising a dielectric layer, a gate metal, a top spacer arranged on a top surface of the gate, and a bottom spacer arranged on a bottom surface of the gate;
etching to form a recess in a top surface of the semiconductor material of the fin channel, the recess having sidewalls that contact a top surface of the top spacer and form oblique angles with respect to sidewalls of the fin channel and sidewalls of the top spacer, and the semiconductor material of the fin channel covering sidewalls of the top spacer;
forming a top source/drain on the fin channel and within the recess;
doping the top source/drain with a dopant; and
annealing to diffuse the dopants from the top source/drain into the fin channel.

US Pat. No. 10,396,196

SEMICONDUCTOR DEVICES

VANGUARD INTERNATIONAL SE...

1. A semiconductor device, comprising:a semiconductor layer disposed over a substrate;
a doped region disposed in the semiconductor layer;
a device region disposed on the doped region, and comprising a source, a drain and a gate;
a first isolation structure disposed in the semiconductor layer and surrounding the doped region, wherein the device region is in the first isolation structure;
a second isolation structure surrounding the first isolation structure and spaced apart from the first isolation structure; and
a terminal disposed between the first isolation structure and the second isolation structure, and being equipotential with the source, wherein the terminal is outside the first isolation structure.

US Pat. No. 10,396,195

SEMICONDUCTOR DEVICE AND METHOD MANUFACTURING THE SAME

Hyundai Motor Company, S...

1. A semiconductor device, comprising:an n? type layer disposed at a first surface of a substrate;
a trench, an n type region, and a p+ type region disposed on the n? type layer;
a p type region disposed on the n type region;
an n+ type region disposed on the p type region;
a gate insulating layer disposed in the trench;
a gate electrode disposed on the gate insulating layer;
an insulating layer disposed on the gate electrode;
a source electrode disposed on the insulating layer, the n+ type region, and the p+ type region; and
a drain electrode disposed at a second surface of the substrate,
wherein the n type region includes a first portion in contact with the side surface of the trench and extending parallel to an upper surface of the substrate and a second portion in contact with the first portion, separated from the side surface of the trench, and extending in a direction vertical to the upper surface of the substrate.

US Pat. No. 10,396,182

SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING

International Business Ma...

1. A method of forming a silicon germanium-on-insulator (SGOI) material, said method comprising:forming a structure comprising, from bottom to top, a germanium-on-insulator substrate and an amorphous silicon layer, wherein the germanium-on-insulator substrate comprises a germanium layer located directly on a surface of an insulator layer, and wherein the amorphous silicon layer is located directly on a topmost surface of the germanium layer;
forming an opening extending through said amorphous silicon layer and said germanium layer of said germanium-on-insulator substrate;
forming a dielectric structure within said opening, wherein said dielectric structure has a topmost surface coplanar with a topmost surface of said amorphous silicon layer, and a sidewall surface that contacts a sidewall surface of the amorphous silicon layer, and a sidewall surface of the germanium layer; and
converting said structure into a silicon germanium-on-insulator material by annealing said structure containing said dielectric structure within an entirely inert ambient annealing environment, wherein during said annealing silicon atoms from said amorphous silicon layer diffuse into the germanium layer and intermix with germanium atoms in said germanium layer of said germanium-on-insulator substrate to form a silicon germanium layer directly on said surface of said insulator layer.

US Pat. No. 10,396,181

FORMING STACKED NANOWIRE SEMICONDUCTOR DEVICE

INTERNATIONAL BUSINESS MA...

1. A method for forming a nanowire semiconductor device, the method comprising:forming a nanowire stack comprising a first nanowire and a second nanowire arranged on the first nanowire;
forming a sacrificial gate over the nanowire stack;
forming a sacrificial spacer adjacent to the sacrificial gate;
removing one or more portions of the first nanowire to form a first cavity;
removing the sacrificial spacer;
depositing a layer of spacer material adjacent to the sacrificial gate and in the first cavity;
removing a portion of the layer of spacer material to form a spacer adjacent to the sacrificial gate and the first nanowire;
removing one or more portions of the second nanowire to form a second cavity; and
epitaxially growing a source/drain region in the second cavity from the one or more portions of the second nanowire.

US Pat. No. 10,396,180

METHOD FOR FORMING APPARATUS COMPRISING TWO DIMENSIONAL MATERIAL

EMBERION OY, Espoo (FI)

1. A method for forming a field effect transistor, said method comprising:providing a release layer with a smooth surface on a carrier substrate;
depositing source, gate and drain electrodes on the release layer;
depositing a mouldable polymer overlaying the source, gate and drain electrodes on the release layer, so that the source, gate and drain electrodes and the mouldable polymer form a planar surface against the smooth surface of the release layer;
removing the carrier substrate and the release layer;
providing a dielectric on the planar surface overlying the gate electrode and at least part of the source and drain electrodes;
depositing a layer of two dimensional material on the dielectric;
providing a first contact between the source electrode and the two dimensional material so that the contact provides a direct current path between the source electrode and the two dimensional material; and
providing a second contact between the drain electrode and the two dimensional material so that the contact provides a direct current path between the drain electrode and the two dimensional material.

US Pat. No. 10,396,176

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

Intel Corporation, Santa...

1. A method for fabricating a transistor comprising:forming a blocking material on a semiconductor fin;
disposing a dummy gate on at least a first portion of the blocking material, wherein the dummy gate and the blocking material comprise different surface chemistries;
selectively forming a conformal layer on an entirety of the dummy gate, wherein the conformal layer has an etch selectivity with respect to the blocking material and wherein the conformal layer is not formed on at least a second portion of the blocking material;
removing exposed portions of the blocking material by an etch wherein the conformal layer protects the dummy gate during the etch;
forming an interlayer dielectric material adjacent to a sidewall of the conformal layer and exposing the dummy gate;
removing the dummy gate and a portion of the blocking material to expose a third portion of the semiconductor fin;
disposing a gate dielectric on the third portion of the semiconductor fin and a gate electrode on the gate dielectric; and
forming, prior to selectively forming the conformal layer, a blocking self-assembled monolayer on at least a portion of the blocking material, wherein said removing the dummy gate and the portion of the blocking material further comprises removing a portion of the blocking self-assembled monolayer.

US Pat. No. 10,396,164

SEMICONDUCTOR CRYSTAL SUBSTRATE WITH FE DOPING

FUJITSU LIMITED, Kawasak...

1. A semiconductor crystal substrate, comprising:a first buffer layer formed of a nitride semiconductor over a substrate;
a second buffer layer formed of a nitride semiconductor on the first buffer layer;
a first semiconductor layer formed of a nitride semiconductor on or over the second buffer layer; and
a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer,
wherein an iron (Fe) concentration of the first buffer layer is higher than a carbon (C) concentration of the first buffer layer,
a C concentration of the second buffer layer is higher than an Fe concentration of the second buffer layer throughout the second buffer layer in a thickness direction of the second buffer layer, and
the Fe concentrations of the first and second buffer layers peak at an interface between the first and second buffer layers.

US Pat. No. 10,396,155

SEMICONDUCTOR DEVICE WITH RECESSED SOURCE/DRAIN CONTACTS AND A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a device above an active region defined in a semiconducting substrate, said device comprising a first gate structure, a first spacer formed adjacent said first gate structure, and first conductive source/drain contact structures positioned adjacent said first gate structure and separated from said first gate structure by said first spacer;
forming a first patterned mask layer above said first conductive source/drain contact structures, said first patterned mask layer having a first opening positioned above a first portion of said first conductive source/drain contact structures at a first axial position along said first gate structure and a second opening positioned above a second portion of said first conductive source/drain contact structures at a second axial position along said first gate structure;
performing a first etch process through said first patterned mask layer to define first and second cavities below said first and second openings, respectively, wherein said first etch process removes portions of said first conductive source/drain contact structures;
forming a dielectric cap layer in said first and second cavities; and
forming a first conductive contact contacting said first gate structure in said first axial position.

US Pat. No. 10,396,150

VERTICAL POWER TRANSISTOR DIE WITH ETCHED BEVELED EDGES FOR INCREASING BREAKDOWN VOLTAGE

MaxPower Semiconductor, I...

1. A vertical transistor die comprising:a cell array in a first semiconductor material of a first conductivity type;
one or more electrodes formed on a top surface of the die having wire-bonding pad opening areas for wire bonding to package terminals;
a bottom electrode, wherein all electrical connections to the transistor are made via the wire-bonding pad opening areas and via the bottom electrode;
a beveled portion etched through the first semiconductor material and surrounding the cell array, the beveled portion of the first semiconductor material extending from a top surface of the die outward toward the bottom surface, wherein the beveled portion forms an outward slanting edge portion of the first semiconductor material of the die;
a passivating layer formed over the beveled portion as an outer layer at the edge of the die, wherein no conductive material overlies any portion of the passivating layer over the beveled portions;
a bottom semiconductor layer of a second conductivity type; and
a buffer layer of the first conductivity type overlying the bottom semiconductor layer, wherein the first semiconductor material is formed overlying the buffer layer, wherein the buffer layer has a dopant concentration higher than a dopant concentration in the first semiconductor material, and wherein the beveled portion is etched through the first semiconductor material and at least into the buffer layer.

US Pat. No. 10,396,137

TESTING TRANSFER-PRINT MICRO-DEVICES ON WAFER

X-Celeprint Limited, Cor...

1. A method of making and testing transfer-printable micro-devices on a source wafer, comprising:providing the source wafer comprising a plurality of sacrificial portions spatially separated by anchors, the source wafer comprising one or more test contact pads;
providing at least one micro-device disposed entirely over each of the plurality of sacrificial portions, each of the at least one micro-device physically connected to at least one of the anchors;
providing one or more electrical test connections from each of the at least one micro-device to a corresponding test contact pad;
testing the at least one micro-device disposed over each of the plurality of sacrificial portions through the one or more test connections to determine one or more functional micro-devices and one or more faulty micro-devices; and
removing at least a portion of the one or more test connections.

US Pat. No. 10,396,135

OLED SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting display (OLED) substrate, comprising a plurality of pixel regions, at least one of the plurality of pixel regions provided with a pixel driving circuit, and comprising a display region and a connection region; wherein,the OLED substrate comprises:
a base;
a reflective electrode layer disposed on the base, wherein the reflective electrode layer comprises a plurality of reflective electrodes, each of which is correspondingly disposed in one display region;
a pixel defining layer disposed on the reflective electrode layer, wherein the pixel defining layer is provided with a first opening corresponding to the display region and a second opening corresponding to the connection region;
a light-emitting material layer disposed in the first opening;
a display electrode continuously disposed on the light-emitting material layer and in the second opening, wherein the display electrodes in the respective pixel regions are electrically insulated from each other,
wherein the display electrode in each of the at least one pixel region is electrically coupled to the pixel driving circuit in the pixel region through the second opening, and
a barrier layer surrounding one pixel region provided with a pixel driving circuit is disposed on the pixel defining layer, wherein the barrier layer has a thickness of about 20 to 500 nm, and an angle between a top surface of the barrier layer away from the pixel defining layer and a side surface of the barrier layer is greater than or equal to about 60° such that the display electrode is broken at the side surface of the barrier layer to separate a display electrode in the one pixel region from a display electrode in an adjacent pixel region.

US Pat. No. 10,396,133

TWO-WAY ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A two way organic light emitting diode display device including red, green and blue sub-pixels defined at an array substrate, comprising:a plurality of driving thin film transistors each driving corresponding each of the red, green and blue sub-pixels;
an organic light emitting diode disposed at each sub-pixel and including an anode layer electrically connected to each thin film transistor at the red, green and blue sub-pixels, an organic light emitting layer disposed on the anode layer and emitting white light, and a cathode layer disposed on the organic light emitting layer;
an encapsulating substrate encapsulating the plurality of driving thin film transistors and the organic light emitting diode; and
red, green and blue color filters corresponding to each of the red, green and blue sub-pixels and disposed on the encapsulating substrate,
wherein the anode layer includes a first electrode, a first color control layer corresponding to the red sub-pixel and disposed on the first electrode, a second color control layer corresponding to the green sub-pixel and disposed on the first electrode, a third color control layer corresponding to the blue sub-pixel and disposed on the first electrode, a second electrode disposed on the first, second and third color control layers,
wherein the white light passes through the anode layer and is converted to red, green and blue light in a first direction and passes through the red, green and blue color filters and is converted to red, green and blue light in a second direction, opposite to the first direction.

US Pat. No. 10,396,132

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a display element;
a wavelength conversion element disposed on the display element and comprising a plurality of first wavelength conversion layers and a plurality of second wavelength conversion layers arranged in a first predetermined pattern;
a transparent frame disposed on the wavelength conversion element and having a plurality of air gaps defined on a surface facing the wavelength conversion element, wherein the air gaps are recessed in a thickness direction; and
a color filter element disposed on the transparent frame and comprising a plurality of first wavelength filter layers, a plurality of second wavelength filter layers, and a plurality of third wavelength filter layers arranged in a second predetermined pattern,
wherein the first and second wavelength filter layers are arranged to overlap the first and second wavelength conversion layers, respectively, and
wherein the air gaps are arranged to overlap the first and second wavelength conversion layers.

US Pat. No. 10,396,131

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus comprising:a substrate;
a pixel electrode over the substrate;
a pixel-defining layer comprising an opening that exposes at least a portion of the pixel electrode;
an intermediate layer, which is over the portion of the pixel electrode exposed by the opening and comprises an organic emission layer;
a counter electrode over the intermediate layer; and
an encapsulating structure, which is over the counter electrode and comprises at least one inorganic layer and at least one organic layer, wherein the at least one inorganic layer is in the opening and extends outside the opening, and wherein the at least one organic layer comprises quantum dots and is formed in the opening such that a thickness of the encapsulating structure in the opening is greater than a thickness of the encapsulating structure outside the opening.

US Pat. No. 10,396,130

DISPLAY SUBSTRATE INCLUDING SUB-ELECTRODES HAVING TRAPEZIUM SHAPE AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a display substrate, wherein the display substrate comprises a first electrode formed on a base substrate, the display substrate comprises a plurality of sub-pixels, the first electrode comprises a plurality of sub-electrodes corresponding to the plurality of sub-pixels respectively, wherein the display substrate further comprises: a pixel definition layer arranged on the base substrate on which the plurality of sub-electrodes has been formed, wherein the pixel definition layer is made of an opaque material, and comprises light-transmissible openings corresponding to the sub-electrodes respectively, and an overlapping area between an orthogonal projection of each of the openings on the base substrate and an orthogonal projection of a sub-electrode corresponding to the opening on the base substrate is within a predetermined range, wherein a distance between two crossing points of a first line and each sub-electrode changes when the first line extending in a first direction moves in a second direction within an area of each of the sub-electrodes, the first direction is perpendicular to the second direction, the overlapping area is an effective light-emitting area of each sub-pixel corresponding to a respective sub-electrode, the openings of the pixel definition layer are of an identical shape, each of the openings is a rectangle, each of two opposite sides of the rectangle is parallel to the first direction, the sub-electrodes are trapeziums, and each of two parallel sides of each of the trapeziums is parallel to the first direction, wherein the method comprises:determining a predetermined requirement of the effective light-emitting area of each sub-pixel; and
forming the pixel definition layer on the base substrate on which the plurality of sub-electrodes has been formed, wherein a location of the pixel definition layer on the display substrate is controlled in the second direction, to control the overlapping area between the orthogonal projection of each of the openings on the base substrate and the orthogonal projection of the sub-electrode corresponding to the opening on the base substrate to be within a predetermined range, and the effective light-emitting area of the sub-pixel is enabled to satisfy the predetermined requirement by the overlapping area being the effective light-emitting area of the sub-pixel corresponding to the sub-electrode.

US Pat. No. 10,396,129

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. An organic light-emitting display device comprising:a substrate;
a pixel disposed on the substrate and including a plurality of subpixels;
an overcoat layer disposed on the substrate, the overcoat layer including microlenses having a plurality of concave portions concavely formed from an upper surface of the overcoat layer;
an organic electroluminescent device disposed on the overcoat layer;
a bank pattern disposed on the overcoat layer and configured to define a light-emitting area of the plurality of subpixels; and
light filter layers respectively disposed in each of the plurality of subpixels,
wherein some of the plurality of subpixels include both microlenses and the respective light filter layer, and the remaining subpixels of the plurality of subpixels include only the light filter layer,
wherein the organic electroluminescent device disposed in the some of the plurality of subpixels is directly contacted with a surface of the microlenses, and
wherein the organic electroluminescent device disposed in the remaining subpixels is directly contacted with the overcoat layer.

US Pat. No. 10,396,128

ANTI-REFLECTIVE OPTICAL FILM AND BENDABLE DISPLAY APPARATUS INCLUDING THE OPTICAL FILM

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a display panel configured to display an image, the display panel including a folding axis extending in a first direction; and
an optical film disposed over the display panel, the optical film comprising a circular polarizer comprising at least two phase retarders and one polarizer, wherein each of the at least two phase retarders has a slow axis and a fast axis,
wherein the optical film is delineated into four quadrants by the folding axis and a virtual axis extending in a second direction perpendicular to the first direction, and
wherein slow axes of each of the at least two phase retarders are located in a same quadrant of the four quadrants of the optical film.

US Pat. No. 10,396,125

CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

Micron Technology, Inc., ...

1. A method, comprising:forming a first memory cell pillar and a second memory cell pillar on a substrate, wherein the first memory cell pillar and the second memory cell pillar are separated by a first gap; and
partially filling the first gap with a gap-seal dielectric to form a seal region wherein the seal region is formed above a buried void that is in contact with at least a portion of opposing side walls of each of the first memory cell pillar and the second memory cell pillar, wherein the seal region comprises abutting portions formed in the first gap; and forming an isolation region above a bottom surface of the seal region between the abutting portions in the first gap.

US Pat. No. 10,396,119

UNIT PIXEL OF IMAGE SENSOR, IMAGE SENSOR INCLUDING THE SAME AND METHOD OF MANUFACTURING IMAGE SENSOR

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a unit pixel of an image sensor, the method comprising:forming a photoelectric conversion region in a substrate;
forming, in the substrate, a first floating diffusion region spaced apart from the photoelectric conversion region of the substrate, and a second floating diffusion region spaced apart from the first floating diffusion region;
forming a first recess spaced apart from the first floating diffusion region and the second floating diffusion region by removing a portion of the substrate from a first surface of the substrate;
filling the first recess to form a dual conversion gain (DCG) gate that extends perpendicularly or substantially perpendicularly from the first surface of the substrate; and
forming a conductive layer to fill an inside of the first recess.

US Pat. No. 10,396,115

SEMICONDUCTOR DEVICE, SOLID-STATE IMAGE SENSOR AND CAMERA SYSTEM

Sony Corporation, Tokyo ...

1. A light detecting device, comprising:a first substrate having a first surface and a second surface opposite the first surface;
a pixel array unit comprising a plurality of photoelectric conversion elements, wherein the pixel array unit is included in the first substrate;
a second substrate vertically integrated with the first substrate such that the second surface of the first substrate faces the second substrate;
circuitry included in the second substrate, the circuitry configured to at least (a) generate first signals to control operation of the plurality of photoelectric conversion elements, or (b) process second signals corresponding to outputs of the plurality of photoelectric conversion elements;
a first via disposed at least partially within the first substrate and located outside the pixel array unit, the first via extending from the first surface of the first substrate and positioned to establish at least a portion of a first signal path between the first substrate and the second substrate for at least one of the first signals or at least one of the second signals; and
a second via disposed at least partially within the first substrate and located outside the pixel array unit, the second via extending from the first surface of the first substrate and positioned to establish at least a portion of a second signal path between the first substrate and the second substrate for at least one of the first signals or at least one of the second signals, wherein:
the pixel array unit has a first edge side and a second edge side,
the first via is located on the first edge side,
the second via is located on the second edge side, and
the first edge side is perpendicular to the second edge side.

US Pat. No. 10,396,113

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS INCLUDING A PHOTOELECTRIC CONVERSION UNIT DISPOSED BETWEEN ANOTHER PHOTOELECTRIC CONVERSION UNIT AND A PHOTOELECTRIC CONVERSION FILM

Sony Semiconductor Soluti...

1. An imaging device comprising:a substrate having a first side and a second side as a light-incident side, the substrate including:
a first photoelectric conversion unit, and
a second photoelectric conversion unit;
a wiring layer disposed adjacent to the first side of the substrate;
a photoelectric conversion film disposed over the second side of the substrate; and
portions of a conductive material disposed between the photoelectric conversion film and the substrate,
wherein
the conductive material is electrically connected to the substrate,
at least a portion of the second photoelectric conversion unit is disposed between the first photoelectric conversion unit and the photoelectric conversion film, and
the substrate is disposed between the photoelectric conversion film and the wiring layer.

US Pat. No. 10,396,111

PACKAGE FOR AN OPTICAL SENSOR, OPTICAL SENSOR ARRANGEMENT AND METHOD OF PRODUCING A PACKAGE FOR AN OPTICAL SENSOR

ams AG, Unterpremstaette...

1. A package for an optical sensor, comprising:an optically opaque enclosure to be mounted onto a substrate;
an optical element; and
an aperture in the enclosure,
wherein
the enclosure forms a cavity in combination with the substrate,
the optical element comprises an optically translucent polymer,
the formulation of the polymer achieves optical filter properties of the optical element,
the aperture attaches the optical element to the enclosure,
the polymer comprises an epoxy resin,
an epoxy resin composition comprises the epoxy resin, a curing agent, and a colorant, the colorant comprising a dye, a pigment, a nano-particle, an ink, a paint, a colored chemical or food coloring or a combination thereof,
the aperture has a conical geometric shape to attach the optical element to the enclosure,
the optical element is arranged at an underside of the enclosure, the underside facing towards the substrate, and the optical element has conical shape and points towards the substrate,
the enclosure comprises a top layer and two side layers, and
the optical element is inside of and extends beyond an inside surface of the top layer of the enclosure,
the enclosure comprises an opaque material, the enclosure and the opaque material sealing the cavity,
the substrate having a low wettability configured for reduced sticking to the polymer.

US Pat. No. 10,396,110

REDUCTION OF TFT INSTABILITY IN DIGITAL X-RAY DETECTORS

Carestream Health, Inc., ...

1. A digital radiographic detector comprising:a two-dimensional array of imaging pixels, each imaging pixel comprising a photo-sensitive element and a switching element;
read-out circuits electrically coupled to the two-dimensional array of imaging pixels to generate a radiographic image by reading out image data from the two-dimensional array of imaging pixels; and
a housing enclosing the two-dimensional array of imaging pixels and the read-out circuits,
wherein each switching element in the two-dimensional array of imaging pixels comprises an active layer formed from indium-gallium-zinc oxide having a thickness less than about 7 nm.

US Pat. No. 10,396,108

SOLID-STATE IMAGING ELEMENT, SOLID-STATE IMAGING ELEMENT MANUFACTURING METHOD, AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A solid-state imaging element comprising:a photodiode that performs photoelectric conversion on a basis of an amount of incident light;
a photoelectric conversion film that performs photoelectric conversion on the basis of the amount of incident light;
a diffusion layer that has a second polarity and stores an electric charge derived from the photoelectric conversion by the photoelectric conversion film, the second polarity being different from a first polarity of the photodiode; and
an impurity layer that includes impurities having the first polarity,
wherein the photodiode and the diffusion layer are disposed on a same substrate in parallel with each other, and
wherein the impurity layer is disposed below the diffusion layer.

US Pat. No. 10,396,100

ARRAY SUBSTRATE, DISPLAY PANEL AND PIXEL PATCHING METHOD

Shenzhen China Star Optoe...

1. An array substrate, comprising a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors (TFTs), a plurality of pixel electrodes, and a plurality of conductive members, wherein the plurality of data lines and the plurality of gate lines are to cross each other to enclose a plurality of pixel regions, the plurality of conductive members are insulated from each other, and each of the conductive members of the plurality of conductive members corresponds to two adjacent pixel regions of the plurality of pixel regions;in each of the pixel regions of the plurality of pixel regions, a control terminal of a respective TFT is electrically connected with a corresponding gate line of the plurality of gate lines, an input terminal of the respective TFT is electrically connected with a corresponding data line of the plurality of data lines, and an output terminal of the respective TFT is electrically connected with a corresponding pixel electrode of the plurality of pixel electrodes; the output terminal comprises a body, and a first contact and a second contact which are connected with the body, the first contact and one conductive member of the plurality of conductive members extending into a corresponding pixel region of the plurality of pixel regions are disposed to overlap each other and are insulated from each other, the second contact and another conductive member of the plurality of conductive members extending into the corresponding pixel region of the plurality of pixel regions are disposed to overlap each other and are insulated from each other.

US Pat. No. 10,396,096

TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A transistor array panel, comprisinga substrate;
a gate line and a data line on the substrate;
a transistor on the substrate; and
a pixel electrode connected to the transistor,wherein the transistor includes:a gate electrode connected to the gate line,
a semiconductor layer on the gate electrode,
a source electrode on the semiconductor layer and connected to the data line, and
a drain electrode on the semiconductor layer and connected to the pixel electrode,
wherein the semiconductor layer includes:
a first portion overlapping the source electrode,
a second portion overlapping the drain electrode, and
a third portion between the first portion and the second portion,wherein:a thickness of the first portion is a minimum thickness of a portion where the source electrode and the semiconductor layer are overlapped,
a thickness of the second portion is a minimum thickness of a portion where the drain electrode and the semiconductor layer are overlapped,
a thickness of the third portion is a minimum thickness of a portion where the semiconductor is exposed between the source electrode and the drain electrode,
the thickness of the first portion, the thickness of the second portion, and the thickness of the third portion are significantly different from one another,
the thickness of the first portion is equal to a thickness of the semiconductor layer overlapping the data line, and
the thickness of the third portion is less than the thickness of each of the first portion and the second portion.

US Pat. No. 10,396,092

VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A vertical memory device comprising:a substrate;
a gate stack structure on the substrate, the gate stack structure including conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction such that cell regions and inter-cell regions are alternately arranged in the vertical direction;
a channel structure on the substrate, the channel structure penetrating through the gate stack structure in the vertical direction; and
a charge trap structure between the gate stack structure and the channel structure, the charge trap structure and the conductive structures defining memory cells at the cell regions, the charge trap structure configured to selectively store charges, the charge trap structure including an anti-coupling structure in the inter-cell regions for reducing a coupling between the memory cells that neighbor each other in the vertical direction, wherein
the charge trap structure includes a block pattern, a tunnel insulation pattern, and a charge trap pattern,
the block pattern contacts the gate stack structure and extends in the vertical direction,
the tunnel insulation pattern has a cylinder shape,
the tunnel insulation pattern encloses that channel structure and contacts the channel structure,
the charge trap pattern includes a plurality of traps for storing the charges,
the charge trap pattern is between the block pattern and the tunnel insulation pattern,
the charge trap pattern includes a first pattern covering the block pattern and a second pattern covering the tunnel insulation pattern, and
the anti-coupling structure is enclosed by the first pattern and the second pattern in the inter-cell regions.

US Pat. No. 10,396,091

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a plurality of control gate electrodes stacked in a first direction above a substrate;
a first semiconductor layer that extends in the first direction and faces the plurality of control gate electrodes;
a gate insulating layer provided between the control gate electrode and the first semiconductor layer;
a first contact connected to an upper end of the first semiconductor layer;
a second semiconductor layer connected to a lower end of the first semiconductor layer and extending in a second direction intersecting the first direction;
a second contact connected to the second semiconductor layer at its lower end and extending in the first direction, an upper end of the second contact being further from the substrate than an upper surface of the second semiconductor layer; and
a first conductive layer provided above the second contact, an upper surface of the first conductive layer being nearer to the substrate than an upper end of the first contact and a lower surface of the first conductive layer being further from the substrate than a lower end of the first contact, wherein
in the second direction, an end of the first conductive layer closest to the first contact is positioned on a closer side to the first contact than an end of the second contact closest to the first contact, and
the first conductive layer and the second contact are not connected to each other.

US Pat. No. 10,396,088

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

19. A three-dimensional semiconductor memory device, comprising:a stack structure including insulating layers and electrodes that are alternately stacked on a substrate;
a horizontal semiconductor pattern between the substrate and the stack structure;
vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and
a first common source plug and a second common source plug at opposite sides of the stack structure, respectively,
the horizontal semiconductor pattern including a first sidewall adjacent to the first common source plug and a second sidewall adjacent to the second common source plug, and
a first distance between the first sidewall and the first common source plug being different from a second distance between the second sidewall and the second common source plug.

US Pat. No. 10,396,087

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a stacked body including a plurality of electrode layers stacked with an insulating body interposed along a stacking direction;
at least two first insulating layers extending in a first direction crossing the stacking direction and being provided in the stacked body from an upper end of the stacked body to a lower end of the stacked body;
at least one second insulating layer extending in the first direction and being provided in the stacked body from the upper end of the stacked body to partway through the stacked body between one of the first insulating layers and another one of the first insulating layers; and
a plurality of semiconductor layers extending in the stacking direction and being provided in the stacked body between the second insulating layer and the one of the first insulating layers and between the second insulating layer and the other one of the first insulating layers,
the semiconductor layers having a first width in the first direction at a first position of the stacking direction, a second width in the first direction at a second position of the stacking direction, and a third width in the first direction at a third position of the stacking direction,
the second position being a position between the first position and the third position,
the second width being wider than the first width and the third width, and
the second insulating layer being provided in a region including a location of a maximum width of the semiconductor layers.

US Pat. No. 10,396,083

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a substrate including an active region that extends in a first direction;
a bit line structure running across the active region in a second direction different from the first direction;
a first spacer on a first sidewall of the bit line structure, the first spacer including:
a first sub-spacer on the first sidewall of the bit line structure;
a second sub-spacer spaced apart from the first sub-spacer;
a first air gap between the first sub-spacer and the second sub-spacer; and
a third sub-spacer covering a portion of the first air gap; and
a storage node structure including a storage node contact contacting the active region and a landing pad on the storage node contact, and both the storage node contact and the landing pad covering the first spacer,
wherein the third sub-spacer is disposed on the second sub-spacer at a first vertical point vertically distant from the substrate by a first height, and is disposed on a sidewall of the first sub-spacer at a second vertical point vertically distant from the substrate by a second height, and the second height is higher than the first height; and
wherein a lower surface of the third sub-spacer is on an upper surface of the second sub-spacer in a direction perpendicular to the substrate.

US Pat. No. 10,396,078

INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DRAIN EPITAXIAL REGION AND METHOD OF FORMING SAME

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit structure comprising:a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin;
a first source/drain epitaxial region substantially surrounding at least a portion of the first fin;
a spacer substantially surrounding the first source/drain epitaxial region, the spacer including a void in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and
a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

US Pat. No. 10,396,066

ELECTRO-STATIC DISCHARGE TRANSISTOR ARRAY APPARATUS

SEMICONDUCTOR MFG. INTL. ...

1. An electro-static discharge (ESD) transistor array apparatus, comprising:a semiconductor substrate, the semiconductor substrate comprising:
a semiconductor layer,
a doped region on the semiconductor layer, and
a substrate contact region,
wherein the doped region and the substrate contact region are isolated, and the substrate contact region comprises at least a first contact region part separately disposed on two sides of the doped region;
multiple gates arranged in parallel on the doped region, where a direction of extension of the multiple gates is in parallel with a direction of extension of the first contact region part; and
a dissipation layer contact member disposed on each gate of the multiple gates along the direction of extension of the gate, wherein a density of the dissipation layer contact member decreases with a decrease in a distance from the gate on which the dissipation layer contact member is located to the first contact region part on a corresponding side.

US Pat. No. 10,396,062

MICRO LIGHT EMITTING DIODE DISPLAY PANEL

PlayNitride Inc., Tainan...

1. A micro light emitting diode display panel, comprising:a substrate including a plurality of pixel regions arranged in a display area;
a plurality of control elements, disposed on the substrate and in the display area; and
a plurality of light emitting units, disposed on the substrate and in the display area, wherein each of the light emitting units is electrically connected to one of the control elements, and each of the light emitting units comprises a plurality of micro light emitting diodes, wherein the plurality of micro light emitting diodes at least have a red micro light emitting diode, a green micro light emitting diode and a blue micro light emitting diode, and a shortest distance between the green micro light emitting diode and the one of the control elements is less than a shortest distance between the blue micro light emitting diode and the one of the control elements,
wherein the pixel regions comprise a plurality of first pixel regions and a plurality of second pixel regions, the first pixel regions are sequentially arranged in a first direction, the second pixel regions are sequentially arranged in the first direction, and the first pixel regions and the second pixel regions are alternately arranged in a second direction perpendicular to the first direction, wherein an arrangement between one of the control elements and one of the light emitting units in each of the first pixel regions is different from an arrangement between one of the control elements and one of the light emitting units in each of the second pixel regions.

US Pat. No. 10,396,055

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES

Intel Corporation, Santa...

1. A method comprising:forming a stack comprising multiple integrated circuit (IC) dies including a first IC die and a second IC die;
coupling to the first IC die a first end of a first wire;
anchoring a second end of the first wire to the stack, wherein the first wire comprises the second end and a first portion including the first end;
while the first end is coupled to the first IC die and the second end is anchored to the stack, disposing a package material around the multiple IC dies and the first portion;
after disposing the package material around the multiple IC die, separating the second end from the first portion, including exposing another end of the first portion at a first surface of the package material; and
coupling the first IC die to the second IC die, including forming a redistribution layer on the first surface, wherein the redistribution layer is coupled to the second IC die and to the other end of the first portion.

US Pat. No. 10,396,054

BONDING ALIGNMENT TOOL

TAIWAN SEMICONDUCTOR MANU...

1. An apparatus, comprising:a bonding system configured to bond at least two wafers, the bonding system having a flag-out mechanism configured to remove a plurality of flags from an area between the at least two wafers;
sensors configured to detect data related to a flag-out condition of the flags of the plurality of flags, wherein the data comprises one or more time durations for removing the flags of the plurality of flags; and
at least one processor configured to receive inputs from the sensors, to calculate at least one value related to flag-out timing, and to drive a display indicating an alignment of the at least two wafers, wherein
a first wafer of the at least two wafers comprises at least two alignment markings, and the bonding system is configured to align the first wafer of the at least wafers with a second wafer of the at least two wafers based on the at least two alignment markings, and wherein the at least one processor is configured to:
calculate a velocity by which each alignment marker of the at least two alignment markers is removed,
generate an indicator of misalignment of the at least two wafers based on the calculated velocity, and
determine the at least two wafers are misaligned based on a difference between the velocities by which the each alignment marker of the at least two alignment markers is removed.

US Pat. No. 10,396,051

MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME

INTERNATIONAL BUSINESS MA...

13. A method, comprising:providing a chip having a barrier and adhesion layer;
forming a seed layer directly on the barrier and adhesion layer;
forming a first copper layer on the seed layer;
forming a first intermediate layer directly on the first copper layer;
forming a second copper layer on first intermediate layer;
forming a second intermediate layer in direct contact with the second copper layer;
forming a third copper layer in direct contact with the second intermediate layer; and
forming a barrier protective layer at an interface between the first intermediate layer and the second copper layer,
wherein the barrier and adhesion layer is Titanium Tungsten and the barrier protective layer is nickel.

US Pat. No. 10,396,048

CONTACT HOLE STRUCTURE AND FABRICATING METHOD OF CONTACT HOLE AND FUSE HOLE

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a dielectric layer, comprising a silicon oxide layer and a silicon nitride layer over the silicon oxide layer;
a conductive pad disposed in the dielectric layer;
a mask layer disposed on the dielectric layer; and
a contact hole formed in the dielectric layer and the mask layer, the contact hole being directly over the conductive pad and exposing the conductive pad, wherein the contact hole comprises a first portion and a second portion, wherein the first portion is over the second portion and has a width larger than a width of the second portion.

US Pat. No. 10,396,033

FIRST POWER BUSES AND SECOND POWER BUSES EXTENDING IN A FIRST DIRECTION

QUALCOMM Incorporated, S...

1. An apparatus, comprising:a first plurality of first power buses extending in a first direction and within a first range, the first range extending in a second direction;
a second plurality of first power buses extending in the first direction and within the first range, the first plurality of first power buses and the second plurality of first power buses being powered at a first supply voltage;
a plurality of second power buses extending in the first direction within the first range and a second range, the second range extending in the first direction, the plurality of second power buses being powered at a second supply voltage,
wherein the first plurality of first power buses, the second plurality of first power buses, and the plurality of second power buses are in a conductive layer, and
the plurality of second power buses is between the first plurality of first power buses and the second plurality of first power buses, in the first direction.

US Pat. No. 10,396,032

SEMICONDUCTOR STRUCTURES

Semiconductor Manufacturi...

1. A semiconductor structure, comprising:a semiconductor substrate;
a plurality of first underlying metal layers and a plurality of second underlying metal layers formed in the substrate, the plurality of the first underlying metal layers being interlaced with the plurality of the second underlying metal layers;
a plurality of first metal layers formed on a surface of the substrate, a cross-sectional shape of the first metal layers having a narrower upper edge and a wider lower edge;
a plurality of second metal layers formed on the surface of the substrate, a cross-sectional shape of the second metal layers having a wider upper edge and a narrower lower edge, wherein:
the plurality of the first metal layers are interlaced with the plurality of the second metal layers;
the narrower upper edge of the plurality of first metal layers is leveled with the wider upper edge of the plurality of second underlying metal layers; and
the wider lower edge of the plurality of first metal layers is leveled with the narrower lower edge of the plurality of second underlying metal layers; and
a plurality of sidewall structures formed on the surface of the substrate, each between a first metal layer and a second metal layer.

US Pat. No. 10,396,030

SEMICONDUCTOR DEVICE, LAYOUT DESIGN METHOD FOR THE SAME AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a first electrode including a first main portion, and a first extension that extends from the first main portion; and
a dielectric layer which surrounds a sidewall and a bottom surface of the first main portion,
wherein the first main portion includes a first portion having a first depth, and a second portion having a second depth deeper than the first depth.

US Pat. No. 10,396,020

METHOD OF MANUFACTURING BOARD

FUJITSU LIMITED, Kawasak...

1. A method of manufacturing a board, comprising:forming a first resin layer on a first surface of a plate-shaped member having a first wiring pattern, the first surface having the first wiring pattern;
forming a third resin layer on a second surface of a plate-shaped member having a second wiring pattern and opposite to the first surface, the second surface having the second wiring pattern;
stacking a second resin layer on the first resin layer;
stacking a fourth resin layer on the second resin layer;
fixing a first component to the second resin layer in which a third wiring pattern formed on a third surface of the first component is buried by pressing the first component to the second resin layer; and
fixing a second component to the fourth resin layer in which a fourth wiring pattern formed on a fourth surface of the second component is buried by pressing the second component to the fourth resin layer,
the second resin layer is selected based on a remaining copper rate indicating a ratio of an area of the third wiring pattern to an area of a surface on which the third wiring pattern is formed,
the fourth resin layer is selected based on a remaining copper rate indicating a ratio of an area of the fourth wiring pattern to an area of a surface on which the fourth wiring pattern is formed,
the first resin layer is selected based on a remaining copper rate indicating a ratio of an area of the first wiring pattern to an area of a surface on which the first wiring pattern is formed, and
the third resin layer is selected based on a remaining copper rate indicating a ratio of an area of the second wiring pattern to an area of a surface on which the second wiring pattern is formed.

US Pat. No. 10,396,018

MULTI-PHASE HALF BRIDGE DRIVER PACKAGE AND METHODS OF MANUFACTURE

Infineon Technologies AG,...

1. A semiconductor package, comprising:a plurality of half bridges each comprising a first power transistor die disposed over a second power transistor die;
a separate first metal lead attached to a bottom side of the first power transistor die and to a top side of the second power transistor die of each half bridge;
a separate or single second metal lead attached to a top side of the first power transistor die of each half bridge; and
a mold compound in which each half bridge and each metal lead are embedded,
wherein each first metal lead protrudes from a side face of the mold compound to form a half bridge output terminal,
wherein each second metal lead protrudes from a side face of the mold compound to form a first half bridge power terminal,
wherein at least part of a bottom side of the second power transistor die of each half bridge is not covered by the mold compound at a first main face of the mold compound to form a second half bridge power terminal,
wherein at least part of each second metal lead is not covered by the mold compound at a second main face of the mold compound opposite the first main face,
wherein each first metal lead has a notch which exposes one or more bond pads at the top side of the second power transistor die attached to that first metal lead.

US Pat. No. 10,396,017

LEAD FRAME

SHINKO ELECTRIC INDUSTRIE...

1. A lead frame comprising:a frame part;
a lead extending inward from the frame part and having a front surface and a back surface; and
an external connection terminal formed at a part of the lead in an extension direction and protruding from the back surface of the lead,
wherein the lead includes a pentagonal shape in a cross-section where the front surface of the lead faces upward, the pentagonal shape having a quadrangular main body part and a triangular protrusion protruding from a lower surface of the main body part, and the external connection terminal is directly coupled at one end side to the frame part, and the protrusion is formed at the lead in an inner region extending inwardly relative to the frame part from another end side of the external connection terminal opposite to the one end side directly coupled to the frame part toward a tip end of the lead disposed distally relative to the frame part.

US Pat. No. 10,396,016

LEADFRAME INDUCTOR

TEXAS INSTRUMENTS INCORPO...

1. A device, comprising:a die including a circuit therein;
a first leadframe connected to the die, the first leadframe having a plurality of leads on outer edges thereof; and
a second leadframe in a form of an electrically conductive clip at least partially encompassing the die, the die being positioned between the first and second leadframes, the second leadframe having one or more turns that form at least one inductor, and the second leadframe being connected to the first leadframe to electrically couple the at least one inductor with the circuit.

US Pat. No. 10,396,011

THERMALLY ENHANCED SEMICONDUCTOR PACKAGE AND PROCESS FOR MAKING THE SAME

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a precursor package including a module substrate, a thinned flip chip die, and a mold compound component, wherein:
the thinned flip chip die comprises a device layer with electronic components, a dielectric layer over an upper surface of the device layer, and a plurality of interconnects extending from a lower surface of the device layer and coupled to an upper surface of the module substrate;
the mold compound component resides over the upper surface of the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity above the upper surface of the thinned flip chip die; and
the mold compound component is not over the thinned flip chip die;
depositing a thermally conductive film over at least the upper surface of the thinned flip chip die at a bottom of the cavity; and
applying a thermally enhanced mold compound component over at least a portion of the thermally conductive film to fill the cavity.

US Pat. No. 10,396,010

ONBOARD CONTROL DEVICE

HITACHI AUTOMOTIVE SYSTEM...

1. An onboard control device, comprising:a circuit board;
a member provided to face the circuit board;
a heat generating electronic component mounted on a side of the member;
a heat dissipating material provided between the heat generating electronic component and the member;
a sealing resin configured that when filled the sealing resin is between the circuit board and the member in a direction orthogonal to a major surface of the circuit board, and substantially seals the circuit board and the heat generating electronic component,
wherein a space between the member and the circuit board is at least a part of a range where the heat dissipating material is not provided, and narrower than a range where the heat dissipating material is provided; and
the member comprises a projecting portion projecting toward the circuit board in at least a part of the range where the heat dissipating material is not provided, wherein
the projection portion functions as a breakwater for the heat dissipating material.

US Pat. No. 10,396,009

HEAT DISSIPATION MATERIAL AND METHOD OF MANUFACTURING THEREOF, AND ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THEREOF

FUJITSU LIMITED, Kawasak...

1. An electronic device comprising:a heating element;
a heat dissipation element; and
a heat dissipation material configured to be placed between the heating element and the heat dissipation element, and to include
a plurality of linearly-structured objects of carbon atoms including a first terminal part and a second terminal part,
a first diamond-like carbon layer configured to cover the first terminal part of each of the plurality of linearly-structured objects,
a coating film covering a side surface for the first diamond-like carbon layer and the plurality of linearly-structured objects, and
a filler layer configured to be permeated between the plurality of linearly-structured objects.

US Pat. No. 10,396,006

MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

NXP USA, Inc., Austin, T...

1. A method for producing a molded air cavity package, the method comprising:providing a base flange having a flange frontside, a flange backside opposite the flange frontside as taken along a centerline of the molded air cavity package, and retention posts extending from the flange frontside in a direction opposite the flange backside;
further providing a leadframe comprising retention tabs and package leads;
positioning the base flange adjacent the leadframe such that the retention posts are received through openings provided in the retention tabs; and
after positioning the base flange adjacent the leadframe, forming a molded package body bonded to the base flange and enveloping, at least in substantial part, the retention posts and the retention tabs.

US Pat. No. 10,396,003

STRESS TUNED STIFFENERS FOR MICRO ELECTRONICS PACKAGE WARPAGE CONTROL

Micron Technology, Inc., ...

1. A method of forming a semiconductor device assembly, the method comprising:determining a first warpage of a first semiconductor device assembly comprised of a semiconductor device, a substrate, and a mold compound;
tuning a stiffener member based on the first warpage in order to form a second semiconductor device assembly having a second warpage, the second semiconductor device assembly comprised of the semiconductor device, the substrate, the mold compound, and the stiffener member;
forming the second semiconductor device assembly comprised of the semiconductor device positioned on the substrate, the mold compound encapsulating at least the semiconductor device, and the stiffener member;
wherein tuning the stiffener member further comprises configuring the stiffener member to have a desired coefficient of thermal expansion; and
wherein tuning the stiffener member further comprises varying a density of the stiffener member to obtain the desired coefficient of thermal expansion.

US Pat. No. 10,395,978

METHOD OF PATTERNING TARGET LAYER

IMEC vzw, Leuven (BE)

1. A method of patterning a target layer, the method comprising:forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines;
filling the gaps with a sacrificial material;
forming a hole by removing the sacrificial material along a portion of one of the gaps, the hole extending across the gap and exposing the target layer in the gap;
filling the hole with a fill material to form a block portion extending across the gap;
removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, the one of the gaps being interrupted in the longitudinal direction by the block portion; and
transferring a pattern including the material lines and the block portion into the target layer.

US Pat. No. 10,395,959

SUBSTRATE TRANSPORT

Brooks Automation, Inc., ...

21. A substrate transport comprising:a housing forming an interior environment for housing at least one substrate in a first atmosphere, the housing including
an opening to the interior environment,
a fluid reservoir forming a fluidic barrier non-contacting seal with a second atmosphere different from and external to the first atmosphere where the fluid reservoir is a consumable of the fluidic barrier non-contacting seal that seals contactless the interior environment from the second atmosphere,
a door configured to close the opening, where when the opening is closed the housing is configured to maintain the first atmosphere within the interior environment, and
a redundant seal arrangement disposed on at least one of the housing and the door, the redundant seal arrangement including at least a first seal disposed around a periphery of the opening and at least a second seal where the second seal is disposed between the first seal and the fluidic barrier non-contacting seal.

US Pat. No. 10,395,954

METHOD AND DEVICE FOR COATING A PRODUCT SUBSTRATE

EV Group E. Thallner GmbH...

1. A method for coating a substrate surface, the method comprising:providing a product substrate including (i) a plurality of projections having respective projecting surfaces and (ii) a plurality of recesses that are located between the plurality of projections, wherein functional units are at least partially arranged in the plurality of recesses, said functional units including at least one of a microelectronic system or a micromechanical system,
providing a carrier substrate with a coating material applied to a surface thereof,
contacting the projecting surfaces of the product substrate with the coating material applied to the surface of the carrier substrate,
applying a force load to transfer a portion of the coating material from the surface of the carrier substrate to the projecting surfaces of the product substrate, wherein said force load includes a first force applied to a side of the carrier substrate facing away from the projecting surfaces, said force load applied after and/or during the contacting of the projecting surfaces with the coating material, and
separating the carrier substrate from the product substrate such that the portion of the coating material transferred to the product substrate remains at least partially on the projecting surfaces, wherein separating the carrier substrate from the product substrate includes successively stripping the carrier substrate from the plurality of projections.

US Pat. No. 10,395,943

PATTERNING METHOD, METHOD FOR PRODUCING PROCESSED SUBSTRATE, METHOD FOR PRODUCING OPTICAL COMPONENT, METHOD FOR PRODUCING CIRCUIT BOARD, AND METHOD FOR PRODUCING ELECTRONIC COMPONENT

Canon Kabushiki Kaisha, ...

1. A patterning method comprising:placing a photocurable composition on a substrate;
bringing the photocurable composition into contact with a mold having an uneven pattern;
irradiating the photocurable composition with light to form a cured film;
separating the cured film from the mold;
forming a reverse layer on the cured film to which the uneven pattern of the mold has been transferred;
while recessed portions of the uneven pattern of the cured film are filled with the reverse layer, removing a part of the reverse layer to expose raised portions of the uneven pattern; and
etching the photocurable composition layer to form a reverse pattern using the reverse layer in the recessed portions as a mask,
wherein the photocurable composition contains at least a polymerizable compound (A) component and a photopolymerization initiator (B) component, the (A) component has a mole fraction weighted average molecular weight of 200 or more and 1000 or less, the (A) component has an Ohnishi parameter (OP) of 3.80 or more, and the Ohnishi parameter (OP) of the (A) component is a mole fraction weighted average of N/(NC?NO), N denotes a total number of atoms in a molecule, NC denotes a number of carbon atoms in the molecule, and NO denotes a number of oxygen atoms in the molecule.

US Pat. No. 10,395,927

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR MFG. INTL. ...

1. A method for manufacturing a semiconductor device, comprising:forming an etchable material layer on a substrate;
forming multiple openings on the etchable material layer by means of a patterning processing to determine a position of a core;
etching the substrate at bottoms of the multiple openings so that the bottoms of the multiple openings extend into the substrate;
depositing a material of a core to fill the multiple openings;
etching the material of the core to expose the etchable material layer;
removing the etchable material layer to leave multiple cores;
depositing spacers;
over etching the spacers to expose the multiple cores, and etching a part of the substrate, wherein an etching depth of the etched part of the substrate is the same as a depth to which the openings extend into the substrate; and
removing the multiple cores.

US Pat. No. 10,395,897

VIRTUAL IMPEDANCE AUTO MATCHING METHOD

NEWPOWERPLASMA CO., LTD.,...

1. A virtual impedance auto matching method in which, virtual matching is performed by connecting an impedance matcher to a computing device before the impedance matcher is put into a process, the impedance matcher being installed between an RF generator that generates an RF signal that oscillates at a high frequency and a plasma chamber to match impedance of an output terminal of the RF generator with impedance of the plasma chamber, the virtual impedance auto matching method comprising the steps of:(a) deciding an input parameter of the RF generator and a load condition parameter of the plasma chamber according to a process type, a process recipe, and each process step of the process recipe;
(b) applying an RF ON signal to the impedance matcher based on the input parameter of the RF generator for each process step;
(c) determining whether initial preset positions of a load vacuum variable capacitor and a tuning vacuum variable capacitor constituting the impedance matcher are within a matching range;
(d) applying the RF OFF signal to the impedance matcher and generating an alarm signal indicating deviation from the matching range, when step (c) is not satisfied;
(e) starting matching by operating the impedance matcher when step (c) is satisfied;
(f) deciding the initial preset positions of the load vacuum variable capacitor and the tuning vacuum variable capacitor by analyzing a magnitude error and a phase error with respect to 50+j0 according to an impedance change for each process step where the matching is successful, when the matching is completed; and
(g) performing step (a) to step (f) for each process step and sending the initial preset positions of the load vacuum variable capacitor and the tuning vacuum variable capacitor for each process step to the impedance matcher.

US Pat. No. 10,395,858

REPLACEABLE TRIGGER COMPONENTS

Snap-on Incorporated, Ke...

1. A trigger retention mechanism for a device having a housing and a depressible trigger, wherein the housing includes a housing wall having interior and exterior surfaces, the trigger retention mechanism comprising:a trigger body and a trigger stem extending from the trigger body;
a bushing having a flange, a tube extending from the flange, and ridges circumferentially disposed on the tube, wherein the flange is adapted to be disposed proximal to the exterior surface, wherein the tube slidably receives the trigger stem, and wherein the ridges are adapted to create a friction-fit interaction between the bushing and the housing; and
a fastener adapted to be releasably coupled to the bushing proximal to the interior surface and substantially prevent axial movement of the bushing relative to the housing.

US Pat. No. 10,395,856

BUS TYPE SWITCH SOCKET BRACKET

SHENZHEN POWER2CONTROL SM...

1. A bus type switch socket bracket comprising:a bracket body (1) comprising at least one control panel mounting hole (7), the control panel mounting hole (7) comprising an bare metal contact pad (3) arranged on sides thereof and connected with a metal body (2) embedded in the bracket body (1): wherein the bare metal contact pad (3) serves as a bus access port which is provided low-voltage direct current power supply, communication and control lines of various control panels mounted on the bracket body (1).

US Pat. No. 10,395,852

TITANIUM OXIDE CRYSTAL BODY AND POWER STORAGE DEVICE ELECTRODE INCLUDING TITANIUM OXIDE CRYSTALLINE BODY

Nippon Chemi-Con Corporat...

1. A titanium oxide crystalline body formed in a flat plate shape and comprising a magneli phase on an edge surface of a facet surface of the titanium oxide crystalline body.

US Pat. No. 10,395,816

MAGNETIC DEVICE FABRICATION METHOD

Ajoho Enterprise Co., Ltd...

1. A magnetic device fabrication method, comprising the steps of:(A) using a mold to process an electrically insulative first substrate into a first plate member with a plurality of protruding blocks;
(B) forming a plurality of conductors in each of said protruding block of said first plate member;
(C) using a mold to process an electrically insulative second substrate into a second plate member;
(D) forming a plurality of conducting contact in one side of said second plate member of said second substrate, enabling said conducting contacts to be arranged in rows;
(E) using a mold to process a magnetic material into at least one magnetic core each having at least one positioning slot cut through opposing top and bottom surface thereof and two opposing positioning sidewalls disposed at two opposite lateral sides relative to said at least one positioning slot;
(F) attaching said at least one magnetic core to said first plate member to couple said at least one positioning slot of said at least one magnetic core to said protruding blocks of said first plate member respectively, enabling two opposite said protruding blocks at two opposite lateral sides of said first plate member to be respectively abutted against respective two opposing said positioning sidewalls that are disposed at two opposite lateral sides of said at least one magnetic core;
(G) attaching said second plate member of said second substrate to said at least one magnetic core and said protruding blocks of said first plate member, enabling said conducting contacts in said second plate member to be respectively kept in contact with the respective said conductors in the respective said protruding blocks; and
(H) obtaining a finished magnetic device.

US Pat. No. 10,395,794

HIGH VOLTAGE ELECTRIC TRANSMISSION CABLE

NEXANS, Courbevoie (FR)

1. An over head cable comprising:at least one composite strength member having one or more reinforcing elements at least partly embedded in an organic matrix;
a metal coating surrounding said at least one composite strength member, said metal coating welded directly to itself along its seams so as to be completely sealed tube all around the at least one composite strength member so that the sealed metal coating prevents thermal oxidation of the organic matrix of the at least one composite strength member along the cable; and
at least one conducting element surrounding said sealed metal coating, said conducting element having an assembly of metal wires;
wherein the electrical cable further comprises at least one electrically insulating layer positioned between the sealed metal coating and the composite strength member or members, and
wherein the thickness of the sealed metal coating is between 150 and 3000 ?m so as to be sufficient to protect said composite strength member from environmental degradation and also thin enough to remain flexible enough such that said cable can operate as said over head cable.

US Pat. No. 10,395,791

ELECTRICALLY CONDUCTIVE NANOWIRE LITZ BRAIDS

President and Fellows of ...

1. A litz braid comprising:a plurality of wires bundled together so that each wire takes a turn near the center of the bundle, wherein at least one of the wires comprises
a high-strength nanowire core;
a first electrically conductive metal layer that is bonded to an outer surface of the high-strength nanowire core; and
an insulating layer that is bonded to an outer surface of the first electrically conductive metal layer; and
wherein said at least one of the wires have a diameter of less than 10 micrometers.

US Pat. No. 10,395,789

X-RAY FILTER FOR X-RAY POWDER DIFFRACTION

Brookhaven Science Associ...

1. A filter system comprising:a first plate, wherein the first plate includes a center, an x-ray absorbing material and walls defining first slits, wherein the first slits include arc shaped openings through the first plate starting from the center and wherein the arc shaped openings arc radially from the center, form a spiral, and are staggered when viewed radially from respective centers of respective plates, the walls of the first plate configured to absorb at least some of first x-rays when the first x-rays are incident on the x-ray absorbing material, and to output second x-rays;
and a second plate spaced from the first plate, wherein the second plate includes the x-ray absorbing material and walls defining second slits, wherein the second slits include arc shaped openings through the second plate, the walls of the second plate configured to absorb at least some of second x-rays and to output third x-rays; an area detector positioned so as to receive the third x-rays;
and an x-ray source configured to direct fourth x-rays at a sample, such that at least some of fourth x-rays are diffracted by the sample to produce the first x-rays;
and a motor configured to rotate the first and second plates about a central axis of the fourth x-rays.

US Pat. No. 10,395,785

TRANSPORTABLE MONITORING SYSTEM

NUSCALE POWER, LLC, Corv...

1. A nuclear reactor module monitoring system, comprising:a reactor module housed in a reactor bay;
multiple monitoring devices configured to monitor the reactor module; and
a transportable mounting structure attached to a wall of the reactor bay, the transportable mounting structure including:
an attachment structure configured to move the transportable mounting structure along the wall of the reactor bay;
a hinge connected to the transportable mounting structure;
two horizontally elongated arms each attached at a first end to the hinge and extending radially out from the hinge in oppositely inclining angles, and each attached at a second end to different ones of the monitoring devices, the two arms configured to both:
rotate about the hinge into an extended position and move the attached monitoring devices out away from the wall of the reactor bay towards an exterior surface of the reactor module in preparation for a monitoring operation; and
rotate about the hinge into a retracted position and move the monitoring devices away from the exterior surface of the reactor module back towards the wall of the reactor bay upon completion of the monitoring operation.

US Pat. No. 10,395,778

RF CURRENT DRIVE FOR PLASMA ELECTRIC GENERATION SYSTEM

THE REGENTS OF THE UNIVER...

1. A method of driving plasma ions and electrons in a field reversed configuration (FRC) magnetic field comprising the steps ofgenerating an FRC about an rotating elongate annular layer of plasma of ions and electrons axially extending within a cylindrical chamber along the longitudinal axis of the chamber, the plasma having a density of 1014 per cubic centimeters or more and wherein the ions in the rotating layer of plasma orbit in betatron orbits normal to the longitudinal axis of the chamber, and
penetrating the rotating layer of plasma with an electric potential wave rotating in the same direction as the azimuthal velocity of ions in the rotating layer of plasma and having a wavelength one or more orders of magnitude greater than the radius of the chamber.

US Pat. No. 10,395,775

APPARATUS AND METHOD FOR RECOMMENDING OPERATION PATH

ELECTRONICS AND TELECOMMU...

1. A method for determining an intravenous pathway for a surgical instrument, the method comprising:generating a blood vessel graph model based on a patient's anatomical information;
defining at least one start point and at least one destination point for the intravenous pathway;
determining a number of jump nodes, a number of branch nodes, and a number of cross nodes in each candidate path; and
determining an optimal path from among the candidate surgical paths based on the number of jump nodes, the number of branch nodes, and the number of cross nodes in each candidate path,
wherein the jump node is a location along the pathway in which the pathway transfers from an artery to a vein, or transfers from a vein to an artery, the branch node is a location along the pathway at which a single vein or artery branches into a plurality of veins or arteries, and the cross node is a location along the pathway at which the pathway passes in front of or behind a vein or an artery.

US Pat. No. 10,395,773

AUTOMATIC CHARACTERIZATION OF AGATSTON SCORE FROM CORONARY COMPUTED TOMOGRAPHY

INTERNATIONAL BUSINESS MA...

1. A method comprising:segmenting a plurality of coronary computed tomography images into a plurality of segments corresponding to features of coronary anatomy, wherein segmenting the plurality of coronary computed tomography images comprises applying an atlas;
based on the plurality of segments, extracting a plurality of calcium candidates from the plurality of coronary computed tomography images by thresholding;
locating coronary calcification in the coronary computed tomography images by applying a trained classifier to the plurality of calcium candidates;
computing an Agatson score from the located calcification.

US Pat. No. 10,395,771

COMPUTER-AIDED TELEMEDICAL EVALUATION

1. A telemedical evaluation method, comprising:receiving a video comprising a number of frames of a subject in motion;
identifying a species of the subject;
identifying a plurality of anatomical features of the subject based on the species of the subject;
determining a gait cycle pattern for individual ones of the plurality of anatomical features of the subject by tracking motion of the individual ones of the plurality of anatomical features in the video over at least a portion of the number of frames of the video;
evaluating a first gait cycle pattern to identify lameness in one end of the subject based on a first amplitude over a first period of the first gait cycle pattern that is different than a second amplitude of a second period of the first gait cycle pattern;
comparing at least a portion of the first gait cycle pattern to at least a portion of a second gait cycle pattern to further identify the lameness at one side of the one end of the subject; and
providing an evaluation of the subject in the video based on the lameness in the one side of the one end of the subject.

US Pat. No. 10,395,770

SYSTEMS AND METHODS FOR MONITORING A PATIENT

General Electric Company,...

12. A method for monitoring a condition of a patient, the method comprising:receiving physiological data from a patient;
presenting a health-monitoring window in an operator display, the health-monitoring window including a set of graph regions, each of the graph regions of the set having a background and a parameter signal line appearing over the background, the parameter signal line being plotted with respect to horizontal and vertical axes of the health-monitoring window, the horizontal axis representing time and the vertical axis representing a patient parameter that is based on the physiological data;
wherein, for at least sonic of the graph regions, the method also includes:
determining that the patient parameter of a corresponding graph region is significant for a designated time;
providing one or more of a reference color or a reference hatching to the background of the corresponding graph region for the designated time, the reference color including at least one of a plurality of potential reference colors, the background for the designated time having a fixed position with respect to the parameter signal line such that an area of the background having the reference color moves along the horizontal axis with the parameter signal line as time progresses, wherein the reference color is selected from the potential reference colors based on whether the patient parameter is above an upper limit or below a lower limit, the reference color above the upper limit and the reference color below the lower limit have respective wavelengths, the wavelengths being separated by at least 30 nanometers (nm), wherein the reference color is configured to change based on the significance of the patient parameter.

US Pat. No. 10,395,767

METHOD AND APPARATUS FOR MANAGING MEDICAL DATA

SAMSUNG ELECTRONICS CO., ...

1. A method of managing medical data, performed by a medical data management apparatus, the method comprising:sensing an error event of a medical diagnosis device;
obtaining image data by capturing images of at least one of a medical image apparatus located in an operating room, an object located in the operating room, and a user input of the medical diagnosis device with respect to a first period of time before the error event is sensed;
obtaining log data with respect to the first period of time before the error event is sensed; and
storing the image data and the log data in a memory of the medical data management apparatus,
wherein the medical image apparatus includes the medical diagnosis device configured to perform a medical diagnosis and a console device configured to control and manage the medical diagnosis device.

US Pat. No. 10,395,766

DIAGNOSTIC PROCESS ANALYSIS SYSTEM

Hitachi, Ltd., Tokyo (JP...

1. A diagnostic process analysis system that analyzes cost-effectiveness of a diagnostic process by using a database storing clinical data including patient information, medical concept information indicating medical concepts, and text data, the system comprising a computer programmed to:accept input of a first diagnostic process,
extract, from the text data, relevance information indicating relevance between different medical concepts regarding the medical concept information of respective data pieces of the clinical data that are previously defined;
calculate importance scores of the data pieces of the clinical data by using the relevance information indicating the relevance between different medical concepts regarding the medical concept information of respective data pieces of the clinical data that are previously defined;
extract a second diagnostic process having a relevance to the first diagnostic process, which has been accepted, higher than a predetermined threshold based on the importance scores;
perform clustering on the patient information of the clinical data based on the second diagnostic process and the calculated importance scores to generate patient groups; and
calculate a clinical index and a cost of the second diagnostic process for each of the patient groups;
wherein the text is medical literatures;
wherein extracting the relevance information includes extracting evidence levels from study levels indicated by the medical literatures;
wherein calculating the importance scores includes calculating the importance scores of the data pieces of the clinical data based on the evidence levels and co-occurrence degrees between the medical concepts obtained by extracting the relevance information;
wherein a co-occurrence degree between a plurality of medical concepts is a number of medical literatures that each include all of the plurality of medical concepts;
wherein diagnostic processes that do not have relevance higher than the predetermined threshold based on the importance scores are eliminated from further consideration; and
wherein one or more second diagnostic processes having relevance higher than the predetermined threshold are further considered by using the calculated clinical indices and costs of the one or more second diagnostic processes for the patient groups, combinations of diagnostic processes are evaluated, and a combination of diagnostic processes to be improved is identified.

US Pat. No. 10,395,765

MOBILE MONITORING AND PATIENT MANAGEMENT SYSTEM

ZOLL MEDICAL CORPORATION,...

1. A patient management system, comprising:communications circuitry configured to receive physiological information relating to a plurality of patients from a plurality of monitoring medical devices, each of which is worn by one of the plurality of patients; and
a computing device communicatively coupled to the communications circuitry comprising a user interface and at least one processor configured to:
receive the physiological information from the plurality of monitoring medical devices via the communications circuitry;
process the received physiological information to associate physiological information received from the at least one of the plurality of monitoring medical devices with one of the plurality of patients;
analyze the physiological information for the one of the plurality of patients to identify an appropriate course of treatment for the one of the plurality of patients; and
display, via the user interface, an indication regarding the identified appropriate course of treatment for the one of the plurality of patients, wherein the indication comprises information about whether the one of the plurality of patients will benefit from using a therapeutic medical device that is configured to deliver a therapy to the one of the plurality of patients upon detecting an underlying arrhythmia condition.

US Pat. No. 10,395,763

MEDICAL INFORMATION TERMINAL

CANON KABUSHIKI KAISHA, ...

1. A portable medical information terminal capable of displaying medical information which is personal information of a patient comprising:at least one processor; and
at least one memory storing (a) the medical information including a plurality of items, (b) a plurality of information display threshold values corresponding to respective places where the medical information terminal is moved, (c) a plurality of information concealing levels corresponding to each of the plurality of items included in the medical information, and (d) a program including instructions to be executed by the at least one processor to perform a method comprising:
in a case where the medical information is browsed by a user, obtaining position information indicating a current position of the portable medical information terminal;
determining, as a current information display threshold value, an information display threshold value corresponding to the place identified based on the obtained position information from among the plurality of information display threshold values stored in the at least one memory; and
causing a display unit to not display a description content of an item when an information concealing level of the item is set at more than the determined current information display threshold value, from among the plurality of items, or causing the display unit to display a description content of an item when an information concealing level of the item is set at not more than the determined current information display threshold value, from among the plurality of items,
wherein each of the plurality of information display threshold values stored in the at least one memory is a threshold value capable of displaying about the description contents of all or a part of the plurality of items.

US Pat. No. 10,395,751

AUTOMATED TESTING SYSTEM AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

5. An operating method of a system comprising:providing a system under test (SUT) having a hardware array of flash storages, partitions including logical volumes, a kernel subsystem including an operating system, and an application layer including services, applications, systems, or a combination thereof;
segmenting the SUT into subsystems;
driving, by test drivers, tests to be performed on the SUT;
generating, by test fixtures, test data sets corresponding to the test drivers;
segmenting the SUT into subsystems, including a first segmented subsystem and a second segmented subsystem;
creating test cases in accordance with the test drivers and the test data sets, including creating a test case to drive a different test using a different text fixture on each segmented subsystem;
tracking, by observers, test results of the test cases, wherein the test results include metrics; and
storing historical data of the test cases in archives;
wherein a result of the test driven on the first segmented subsystem is applied as an input to the test driven on the second segmented subsystem.

US Pat. No. 10,395,747

REGISTER-TRANSFER LEVEL DESIGN ENGINEERING CHANGE ORDER STRATEGY

CADENCE DESIGN SYSTEMS, I...

1. A system for modifying at least one memory unit, comprising:a computer hardware arrangement configured to:
determine a location of at least one first memory built-in self-test (MBIST) logic block in the at least one memory unit;
remove the at least one first MBIST logic block from the at least one memory unit; and
insert at least one second MBIST logic block into the at least one memory unit at the location.

US Pat. No. 10,395,742

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a plurality of memory cells arranged in a matrix on a semiconductor substrate,
wherein each of the plurality of memory cells includes:
a protruding portion being a part of the semiconductor substrate, protruding from an upper surface of the semiconductor substrate, and extending in a first direction along a main surface of the semiconductor substrate;
a first gate electrode formed over an upper surface of the protruding portion interposing a first insulating film and extending in a second direction orthogonal to the first direction;
a second gate electrode formed adjacent to a side wall of the first gate electrode interposing a second insulating film including a charge storage portion, formed over the upper surface of the protruding portion interposing the second insulating film, and extending in the second direction;
a drain region formed in the upper surface of the protruding portion adjacent to the first gate electrode; and
a source region formed in the upper surface of the protruding portion adjacent to the second gate electrode, and
wherein, when performing an erase operation, among the plurality of memory cells, in a first memory cell on which erasing is not performed, the drain region and the source region are not applied with a voltage, and the second gate electrode is applied with a positive voltage.

US Pat. No. 10,395,741

NONVOLATILE MEMORY DEVICE

Samsung Electronics Co., ...

1. A nonvolatile memory device comprising:a cell string including a plurality of memory cells connected to a bit line; and
a page buffer connected to the bit line via a sensing node and connected to the cell string via the bit line, wherein:
the page buffer includes a first latch that stores bit line setup information and a second latch that stores forcing information,
the first latch is configured to output the bit line setup information to the sensing node, by being connected to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch by being connected to the sensing node, and
the page buffer further comprises a first transistor, which is placed between the first latch and the sensing node and coupled with the first latch, and a second transistor, which is placed between the second latch and the sensing node and coupled with the second latch.

US Pat. No. 10,395,740

MEMORY AS A PROGRAMMABLE LOGIC DEVICE

Micron Technology, Inc., ...

1. A memory, comprising:a data line;
a plurality of strings of series-connected memory cells selectively connected to the data line;
a plurality of first access lines, wherein each first access line of the plurality of first access lines is coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; and
a plurality of second access lines, wherein each second access line of the plurality of second access lines is coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
wherein a particular second access line of the plurality of second access lines is coupled to the control gate of the respective memory cell of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells, and not coupled to a control gate of any memory cell of a different string of series-connected memory cells of the plurality of strings of series-connected memory cells.

US Pat. No. 10,395,739

SEMICONDUCTOR MEMORY DEVICE WITH PLURALITY OF WRITE LOOPS INCLUDING WRITE AND VERIFY OPERATIONS

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a plurality of word lines;
a plurality of bit lines;
a plurality of memory cells provided to correspond to intersections of the word lines and the bit lines;
a word line driving circuit that applies a voltage to a selected word line among the plurality of word lines;
a sense amplifier circuit that detects data of the memory cells; and
a controller that controls the word line driving circuit and the sense amplifier circuit,
the memory cell connected to the selected word line being written with data using a write sequence including a plurality of write loops each including a write operation of applying a write voltage to the selected word line by the word line driving circuit and a verify operation of detecting data of the memory cell by the sense amplifier circuit, and
the controller determining an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.

US Pat. No. 10,395,736

RESISTIVE RANDOM ACCESS MEMORY DEVICE

WINBOND ELECTRONICS CORP....

1. A resistive memory for storing data by reversible and nonvolatile variable resistive elements comprising:a memory array comprising a plurality of memory cells arranged in columns and rows, each memory cell comprising one variable resistive element and one access transistor connected to the variable resistive element, wherein gates of the access transistors in each column are connected to a word line, first electrodes of the variable resistive elements in each row are connected to a bit line, and second electrodes of the variable resistive elements in each row are connected to a source line,
wherein the source line comprises a first source line extending in a direction that is parallel to the bit line and a second source line derived from the first source line, and
wherein the second source line extends in a direction that is orthogonal to the bit lines and are shared by several memory cells.

US Pat. No. 10,395,735

ELECTRONIC DEVICE AND METHOD INCLUDING MEMORY WITH FIRST AND SECOND WRITE CURRENTS

SK hynix Inc., Icheon-si...

1. An electronic device, comprising a semiconductor memory that includes:a first write circuit configured for generating a first current;
a first selection circuit configured for coupling the first write circuit to a first line based on a column selection signal;
a second write circuit configured for generating a second current;
a second selection circuit configured for coupling the second write circuit to a second line based on a row selection signal;
a memory cell including a variable resistance element coupled to the first line and a selection element coupled between the variable resistance element and the second line, coupled between the first line and the second line; and
a voltage control circuit configured for limiting a voltage level of the second line with a predetermined voltage when the selection element is turned on and a voltage level of the second line is greater than the predetermined voltage during a write operation of the memory cell,
wherein the first line includes a bit line and the second line includes a word line,
wherein the word line supplies the second current to the memory cell to turn on/off the selection element.

US Pat. No. 10,395,734

METHOD AND APPARATUS FOR DETERMINING A CELL STATE OF A RESISTIVE MEMORY CELL

International Business Ma...

1. A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states, the device comprising:a sensing circuit configured to sense a sensing voltage of the resistive memory cell and to output a resultant value in response to the sensing voltage which is indicative of the actual cell state,
a settling circuit, including a plurality of current mirrors, configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states,
a prebiasing circuit configured to pre-bias a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage, and
a resistance circuit including a plurality of resistors connected in series and coupled in parallel to the resistive memory cell, wherein the resistance circuit is configured to reduce an effective resistance seen by the prebiasing circuit,
wherein the settling circuit and the resistance circuit are configured to form a plurality of current-resistor pairs being switchable to define a linear range of detection currents corresponding to the certain target voltages, each of the plurality of current-resistor pairs including one current mirror of the plurality of current mirrors and one resistor.

US Pat. No. 10,395,731

MEMORY CELLS, MEMORY SYSTEMS, AND MEMORY PROGRAMMING METHODS

Micron Technology, Inc., ...

1. A memory system comprising:a plurality of memory cells individually comprising:
a plurality of electrodes; and
a memory element between the electrodes of the individual memory cell, and wherein the memory element comprises dielectric material and is configured to have different electrical resistances corresponding to different memory states of the individual memory cell;
wherein the memory element of one of the memory cells comprises at least one electrically conductive structure within the dielectric material of the one memory cell at one of a plurality of different moments in time, and the electrically conductive structure is configured to provide the memory element of the one memory cell with a decreased electrical resistance corresponding to one of the memory states;
wherein the memory element of the one memory cell has an increased electrical resistance corresponding to another of the memory states at another of the moments in time; and
wherein the dielectric material of another of the memory cells is in a permanently broken down state which permanently provides the memory element of the another memory cell with the decreased electrical resistance corresponding to the one memory state.

US Pat. No. 10,395,722

READING FROM A MODE REGISTER HAVING DIFFERENT READ AND WRITE TIMING

Intel Corporation, Santa...

1. A memory device, comprising:a mode register to store configuration information to control operation of the memory device, wherein a write of configuration information directly to the mode register by a host takes less time than a read of the configuration information directly from the mode register by the host; and
a communication register separate from the mode register to provide data for a read of the configuration information by the host from the mode register, wherein in response to a request by the host to read the mode register, the mode register to copy the configuration information from the mode register to the communication register, to enable the host to read the configuration information from the communication register instead of directly from the mode register.

US Pat. No. 10,395,721

MEMORY DEVICES CONFIGURED TO PROVIDE EXTERNAL REGULATED VOLTAGES

Micron Technology, Inc., ...

1. A memory device, comprising:one or more external inputs configured to receive a supply voltage having a first voltage level;
a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level, wherein the voltage regulator comprises a power management integrated circuit (PMIC) that includes one or more registers configured to store information corresponding to the output voltage, wherein the output voltage comprises a plurality of output voltages, and wherein the information comprises a corresponding voltage level for each of the plurality of output voltages, a tolerance corresponding to each of the plurality of output voltages, a first order in which the plurality of output voltages are powered up, first delays corresponding to the first order, a second order in which the plurality of output voltages are powered down, and second delays corresponding to the second order;
one or more memories configured to receive the output voltage from the voltage regulator; and
one or more external outputs configured to receive the output voltage from the voltage regulator and to supply the output voltage to one or more connected devices.

US Pat. No. 10,395,720

PSEUDO STATIC RANDOM ACCESS MEMORY AND REFRESH METHOD THEREOF

Winbond Electronics Corp....

1. A refresh method for a pseudo static random access memory (SRAM), comprising:providing a basic clock signal;
at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal;
at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal; and
receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.

US Pat. No. 10,395,718

CHARGE MIRROR-BASED SENSING FOR FERROELECTRIC MEMORY

Micron Technology, Inc., ...

1. A method of operating a memory cell, comprising:extracting a first charge stored in the memory cell through a charge mirror;
extracting a second charge stored in an amplification capacitor through the charge mirror based at least in part on extracting the first charge stored in the memory cell, wherein the amplification capacitor is in coupled with the memory cell via the charge mirror; and
comparing a voltage associated with the amplification capacitor to a reference voltage, wherein the voltage of the amplification capacitor is based at least in part on the second charge being extracted from the amplification capacitor.

US Pat. No. 10,395,715

SELF-REFERENCING MEMORY DEVICE

Micron Technology, Inc., ...

1. An electronic memory apparatus, comprising:a ferroelectric memory cell storing a charge and coupled with a digit line;
a state signal circuit selectively coupled with the digit line, the state signal circuit configured to extract at least a portion of the charge from the ferroelectric memory cell based on a first signal of the digit line; and
a reference signal circuit selectively coupled with the digit line, the reference signal circuit configured to generate a reference signal based at least in part on a second signal of the digit line different from the first signal, wherein the reference signal circuit further comprises a reference capacitor having a capacitor value that is at least twice a capacitor value of a charge capacitor of the state signal circuit.

US Pat. No. 10,395,713

ONE-TRANSISTOR SYNAPSE CELL WITH WEIGHT ADJUSTMENT

International Business Ma...

1. A method comprising:providing a memory circuit, said memory circuit comprising:
a plurality of word lines;
a plurality of bit lines intersecting said plurality of word lines at a plurality of cross points;
a plurality of signal lines; and
a plurality of memory transistor synapse cells located at said plurality of cross points, each of said cells comprising:
a memory transistor having a gate;
a pulse shaping unit coupled to a given one of said signal lines and said gate of said memory transistor;
a logic gate having inputs coupled to a corresponding one of said word lines and a corresponding one of said bit lines, and having an output coupled to said pulse shaping unit; and
a pass gate arrangement coupled to said memory transistor, said corresponding one of said word lines, said corresponding one of said bit lines, and said output of said logic gate;
applying pulses to said gate of said memory transistor for weight adjustment during an update operation, using said pulse shaping unit, said logic gate, and said pass gate arrangement; and
interconnecting said memory transistor to said corresponding one of said bit lines during an inference operation, using said pulse shaping unit, said logic gate, and said pass gate arrangement, wherein, in said providing step:
said logic gate comprises an AND gate;
said memory transistor comprises an n-type field effect transistor having first and second drain-source terminals; and
said pass gate arrangement comprises:
a first pass gate p-type field effect transistor having a first drain-source terminal coupled to said corresponding one of said word lines, a second drain-source terminal coupled to said first one of said drain-source terminals of said memory transistor, and a gate coupled to said output of said AND gate;
a pass gate n-type field effect transistor having a first drain-source terminal coupled to ground, a second drain-source terminal coupled to said second drain-source terminal of said first pass gate p-type field effect transistor, and a gate coupled to said output of said AND gate; and
a second pass gate p-type field effect transistor having a first drain-source terminal coupled to said second one of said drain-source terminals of said memory transistor, a second drain-source terminal coupled to said corresponding one of said bit lines, and a gate coupled to said output of said AND gate.