US Pat. No. 10,170,692

SEMICONDUCTOR DEVICE WITH INTEGRATED MAGNETIC TUNNEL JUNCTION

IMEC vzw, Leuven (BE)

1. A semiconductor device, comprising:a first metallization layer;
a first dielectric layer formed on the first metallization layer;
a second metallization layer formed on the first dielectric layer;
a second dielectric layer formed on the second metallization layer;
a third metallization layer formed on the second dielectric layer,
wherein the first metallization layer is electrically connected to the second metallization layer by a first via formed in the first dielectric layer, and
wherein the second metallization layer is electrically connected to the third metallization layer by a via formed in the second dielectric layer; and
a magnetic tunnel junction (MTJ) device formed in the first dielectric layer and extending into the second metallization layer, the MTJ device including a top electrode and a bottom electrode,
wherein the bottom electrode of the MTJ device is electrically connected to the first metallization layer,
wherein the second via directly connects the top electrode of the MTJ device to the third metallization layer, and
wherein the height of the MTJ device exceeds the length of the first via formed in the first dielectric layer.

US Pat. No. 10,170,691

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method for fabricating an electronic device, comprising:forming a variable resistance element at a first temperature; and
forming a magnetic correction layer over a pinned layer at a second temperature,
wherein the second temperature is lower than the first temperature,
wherein the variable resistance element includes a free layer provided over a substrate, a pinned layer provided over the free layer, a tunnel barrier layer interposed between the free layer and the pinned layer, and
wherein the magnetic correction layer has a magnetization direction which is anti-parallel to the pinned layer,
wherein the forming of the magnetic correction layer comprises:
(a) cooling the substrate to the second temperature;
(b) forming a first layer over the cooled substrate;
(c) forming a second layer over the first layer,
(d) repeating the forming of the first layer and the forming of the second layer M number of times; and
(e) recooling the substrate to a third temperature,
wherein the third temperature is 0K-75K, inclusive, and
where M is a positive integer.

US Pat. No. 10,170,690

HYBRID-FL WITH EDGE-MODIFIED COUPLING

SAMSUNG ELECTRONICS CO., ...

1. A magnetic memory device, comprising:a free magnetic layer comprising:
a first magnetic material layer comprising a first magnetic anisotropy;
a second magnetic material layer comprising a second magnetic anisotropy, the second magnetic anisotropy being less than the first magnetic anisotropy; and
a coupling layer disposed between the first magnetic material layer and the second magnetic material layer, the coupling layer comprising
a center,
an edge extending between an edge of the first magnetic material layer and an edge of the second magnetic material layer,
a magnetic section extended between the center and a predetermined distance from the center, and
a non-magnetic section extended between the predetermined distance from the center and the edge of the coupling layer,
wherein the non-magnetic section has an increasing thickness from the predetermined distance to the edge of the coupling layer,
wherein the non-magnetic section fills a space defined by a bottom surface of the first magnetic material layer, a top surface of the second magnetic material layer and a side surface of the magnetic section of the coupling layer.

US Pat. No. 10,170,688

MAGNETIC FIELD SENSOR BASED ON TOPOLOGICAL INSULATOR AND INSULATING COUPLER MATERIALS

INTERNATIONAL BUSINESS MA...

1. A method of forming a sensor, the method comprising:forming a first electrode region;
forming a second electrode region;
forming a detector region;
electrically coupling the detector region to the first electrode and the second electrode;
forming the detector region to include a first layer comprising a topological insulator;
the topological insulator having an insulating region in a body of the topological insulator;
the topological insulator further having a conducing path along a surface of the topological insulator, wherein a steady state condition of the topological insulator comprises the insulation region acting as an insulator and the conducting path along the surface of the topological insulator acting as a current conductor; and
forming the detector region to further include a second layer comprising a first insulating magnetic coupler;
wherein the detector region comprises a third layer comprising a second insulating magnetic coupler;
wherein a magnetic field applied to the detector region is sufficient to change the steady state condition of the topological insulator by developing energy gaps in the conducting path along the surface of the topological insulator that are sufficient to change a resistance of the conducting path.

US Pat. No. 10,170,687

SPIN TORQUE MAJORITY GATE DEVICE

IMEC vzw, Leuven (BE)

1. A majority gate device, comprising:a plurality of input zones;
an output zone; and
a magnetic tunneling junction (MTJ) formed in each of the input zones and the output zone, the MTJ comprising a non-magnetic layer interposed between a free layer stack and a hard layer, the free layer stack comprising:
a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, and
a magnetic layer formed directly on and in physical contact with the bulk PMA layer,
wherein the non-magnetic layer is formed on the magnetic layer,
wherein each of the bulk PMA layer and the seed layer serves as a common layer for each of the input zones and the output zone.

US Pat. No. 10,170,686

ELECTRIC ENERGY HARVESTER USING ULTRASONIC WAVE

1. An electric energy generator system comprising:an ultrasonic-wave emission device configured to generate an ultrasonic-wave and emit the ultrasonic-wave; and
an electric energy generator device configured to generate an electric energy upon a receipt of the emitted ultrasonic-wave,
wherein the electric energy generator device comprises:
a substrate;
an electrode on the substrate;
a first friction-charged member on the electrode;
a spacer disposed on the substrate and configured to surround the electrode and the first friction-charged member; and
a second friction-charged member disposed on the spacer to be spaced from the first friction-charged member,
wherein the second friction-charged member repeatedly contacts or is separated from the first friction-charged member, and
wherein a closed inner space is defined between the first friction-charged member and the second friction-charged member and the spacer.

US Pat. No. 10,170,685

PIEZOELECTRIC MEMS MICROPHONE

The Regents of The Univer...

1. A packaged microphone comprising:a microphone comprising:
a substrate; and
a transducing element having a transducer acoustic compliance, the transducing element comprising a first electrode layer, a piezoelectric layer deposited over the first electrode layer, and a second electrode layer deposited over the piezoelectric material, wherein the first electrode layer is patterned on the substrate, the piezoelectric layer is patterned on the first electrode layer, and the second electrode layer is patterned on the piezoelectric layer; and
a casing mounted to the microphone and having a back wall, wherein a space between the back wall and the transducing element at least partially defines a back cavity having a back cavity acoustic compliance, the casing dimensioned to achieve a predetermined ratio between the transducer and back cavity acoustic compliances.

US Pat. No. 10,170,682

DIELECTRIC ELASTOMER ACTUATOR

The Regents of the Univer...

1. A dielectric elastomer actuator (DEA) comprising:an elastomeric film presenting a first side and a second side, opposing the first side;
wherein the elastomeric film includes a first section, a second section, and a transition section disposed in an axial direction, between the first section and the second section;
an electrode material layer disposed on the transition section and at least one of the first section and the second section, on each of the first side and the second side, wherein the electrode material layer is electrically conductive;
wherein the first section and the second section are restrained in a pre-stretched configuration in each of the axial direction and a lateral direction, perpendicular to the axial direction;
wherein the transition section is not restrained in a pre-stretched configuration in the axial direction and is partially restrained in a pre-stretched configuration in the lateral direction as a function of the restraint of the first section and the second section in the pre-stretched configuration;
wherein the transition section is configured to elongate in the axial direction in response to the application of a voltage to the electrode material layers, such that the first section and the second section move away from one another, in the axial direction; and
wherein the transition section is configured to contract in the axial direction in an absence of a voltage applied to the electrode material layers, such that the first section and the second section move toward one another, in the axial direction.

US Pat. No. 10,170,681

LASER ANNEALING OF QUBITS WITH STRUCTURED ILLUMINATION

International Business Ma...

1. A method for forming a qubit, the method comprising:forming a Josephson junction between two capacitive plates; and
annealing the Josephson junction with a thermal source, wherein the thermal source is a laser that generates a Gaussian beam, wherein an axicon lens is exposed to the Gaussian beam, and wherein annealing the Josephson junction alters a resistance of the Josephson junction.

US Pat. No. 10,170,680

QUBITS BY SELECTIVE LASER-MODULATED DEPOSITION

INTERNATIONAL BUSINESS MA...

17. A qubit device, comprising:a Josephson junction; and
a shunt capacitor coupled to the Josephson junction, the shunt capacitor including a shape modified, post-production, to adjust a qubit characteristic for the qubit device.

US Pat. No. 10,170,679

JOSEPHSON JUNCTION WITH SPACER

International Business Ma...

1. A circuit configured to act as a Josephson junction, comprising:a junction stack on a substrate, the junction stack including:
a portion of a first superconductor electrode;
an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack;
a first portion of a second superconductor electrode on top of the interface layer; and
a spacer separating the portion of the first superconductor electrode from a second portion of the second superconductor electrode that is outside the junction stack, the second portion of the second superconductor electrode contacting the substrate on at least two sides of the spacer.

US Pat. No. 10,170,678

THERMOMECHANICAL CYCLE FOR THERMAL AND/OR MECHANICAL ENERGY CONVERSION USING PIEZOELECTRIC MATERIALS

The Regents of the Univer...

1. A method for generating electrical energy, comprising:(a) increasing an electric field applied to a piezoelectric component from EL to EH, maintaining a temperature of the piezoelectric component at TC, and maintaining a mechanical stress applied to the piezoelectric component at ?L;
(b) increasing the mechanical stress applied to the piezoelectric component from ?L to ?H, increasing the temperature of the piezoelectric component from TC to TH, and maintaining the electric field applied to the piezoelectric component at EH;
(c) decreasing the electric field applied to the piezoelectric component from EH to EL, maintaining the temperature of the piezoelectric component at TH, and maintaining the mechanical stress applied to the piezoelectric component at ?H;
(d) decreasing the mechanical stress applied to the piezoelectric component from ?H to ?L, decreasing the temperature of the piezoelectric component from TH to TC, and maintaining the electric field applied to the piezoelectric component at EL; and
repeatedly cycling through operations (a)-(d).

US Pat. No. 10,170,677

THERMOELECTRIC GENERATOR SYSTEM

Panasonic Corporation, O...

1. A thermoelectric generator system comprising a plurality of thermoelectric generator units including first and second thermoelectric generator units, each of which includes a plurality of tubular thermoelectric generators,wherein each of the plurality of tubular thermoelectric generators has an outer peripheral surface, an inner peripheral surface and a flow path defined by the inner peripheral surface, and generates electromotive force in an axial direction of each said tubular thermoelectric generator based on a difference in temperature between the inner and outer peripheral surfaces,
each of the first and second thermoelectric generator units further includes:
a container housing the plurality of tubular thermoelectric generators inside, the container having fluid inlet and outlet ports through which a fluid flows inside the container, and a plurality of openings into which the respective tubular thermoelectric generators are inserted;
a fluid conduit connected between the fluid outlet port of the container of the first thermoelectric generator unit and the fluid inlet port of the container of the second thermoelectric generator unit, through which fluid from the first thermoelectric generator unit is communicated into the second thermoelectric generator unit which is downstream of the first thermoelectric generator unit,
wherein the fluid conduit defines a first medium path communicating with the fluid inlet and outlet ports of the container in the first thermoelectric generator unit and the fluid inlet and outlet ports of the container in the second thermoelectric generator unit; and
a plurality of electrically conductive members providing electrical interconnection for the plurality of tubular thermoelectric generators, and the thermoelectric generator system further includes a buffer vessel which is arranged between the first and second thermoelectric generator units, the buffer vessel having a first opening communicating with the respective flow paths of the plurality of tubular thermoelectric generators in the first thermoelectric generator unit and a second opening communicating with the respective flow paths of the plurality of tubular thermoelectric generators in the second thermoelectric generator unit,
wherein the buffer vessel defines a second medium path between the respective flow paths of the plurality of tubular thermoelectric generators in the first thermoelectric generator unit and the respective flow paths of the plurality of tubular thermoelectric generators in the second thermoelectric generator unit,
wherein in the second medium path, fluid flows downstream from inside the plurality of tubular thermoelectric generators in the first thermoelectric generator unit through the buffer vessel and to inside the plurality of tubular thermoelectric generators in the second thermoelectric generator unit, and
wherein in the first medium path, fluid flows downstream from an area inside the container of the first thermoelectric generator unit that is outside the plurality of tubular thermoelectric generators in the first thermoelectric generator unit, through the fluid conduit outside of the container of the first thermoelectric generator unit, and to an area that is inside the container of the second thermoelectric generator unit and outside the plurality of tubular thermoelectric generators in the second thermoelectric generator unit.

US Pat. No. 10,170,673

LED PACKAGE STRUCTURE AND MULTILAYER CIRCUIT BOARD

LITE-ON OPTOTECHNOLOGY (C...

1. An LED package structure, comprising:a multilayer circuit board, comprising:
a conductive layer having a first surface and a second surface opposite to the first surface, a mounting region of the conductive layer being arranged on the first surface;
a first resin layer disposed on the first surface and having a first opening, the first opening exposing the mounting region of the conductive layer; and
a first circuit layer disposed on the first resin layer and having a first electrode and a second electrode separated from the first electrode, the first electrode having a second opening, the second opening exposing the mounting region of the conductive layer;
an LED chip passing through the second opening of the first circuit layer and the first opening of the first resin layer to mount on the mounting region of the conductive layer, the LED chip being electrically connected to the second electrode of the first circuit layer by wire bonding; and
a cover disposed on the first resin layer and covering the LED chip and the first circuit layer.

US Pat. No. 10,170,671

METHODS OF FILLING A FLOWABLE MATERIAL IN A GAP OF AN ASSEMBLY MODULE

1. A method to fill an flowable material into a gap region in a semiconductor assembly module comprising:forming multiple semiconductor units on a substrate to create an array module;
attaching the array module to a backplane having circuitry to form the semiconductor assembly module having multiple gap regions inside the semiconductor assembly module and edge gap regions surround an edge of the semiconductor assembly module;
dispensing a flowable material on an edge of the semiconductor assembly module;
providing a high acting pressure environment to force the flowable material into the semiconductor assembly module gap regions;
creating voids in the gap region of the semiconductor assembly module by reducing the high acting pressure and;
applying heat or a photon energy to harden the flowable material to retain the harden flowable material and the voids in the gap regions.

US Pat. No. 10,170,669

LIGHT EMITTING DEVICE AND METHOD OF PRODUCING THE SAME

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a resin package comprising:
a plurality of leads that includes:
a first lead having an upper surface, and
a second lead having an upper surface, and
a resin body that includes:
a first resin portion having at least one inner lateral wall surface,
a second resin portion,
a third resin portion disposed between the first lead and the second lead and having an upper surface, and
a resin connection portion,
the plurality of leads and the at least one inner lateral wall surface of the first resin portion defining a recess,
the upper surface of the first lead, the upper surface of the second lead and the upper surface of the third resin portion located at a bottom of the recess,
at the bottom of the recess, the second resin portion being in contact with a portion of the upper surface of the third resin portion and surrounding an element mounting region, and
the resin connection portion connecting the first resin portion and the second resin portion at the bottom of the recess;
at least one light emitting element disposed on the element mounting region at the bottom of the recess of the resin package; and
a light-reflective member disposed between the inner lateral wall surface and the second resin portion in the recess.

US Pat. No. 10,170,668

SOLID STATE LIGHTING DEVICES WITH IMPROVED CURRENT SPREADING AND LIGHT EXTRACTION AND ASSOCIATED METHODS

Micron Technology, Inc., ...

1. A solid state lighting (SSL) device, comprising:a solid state emitter (SSE) having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials, wherein the second semiconductor material has an emission surface;
a first contact on the first semiconductor material;
a second contact on the second semiconductor material and opposite to the first contact, the second contact having a plurality of interconnected conductive fingers; and
an insulative feature extending from the first contact at least partially into the first semiconductor material, the insulative feature having a plurality of interconnected insulative fingers, wherein the insulative feature comprises a transparent dielectric material having a backside;
the SSL device further comprises a reflective material at the backside of the transparent dielectric material;
each conductive finger is superimposed over a corresponding insulative fingers;
the SSE comprises non-contact areas outboard the area beneath the second contact; and
the insulative feature is configured to: (a) eliminate a direct current path orthogonal to the emission surface between the first and second contacts and (b) increase current spreading in the non-contact areas.

US Pat. No. 10,170,667

SEMICONDUCTOR OPTICAL DEVICE

Sony Corporation, Tokyo ...

1. A semiconductor optical device having a multilayer structure including a first compound semiconductor layer having a first conductivity type, an active layer, and a second compound semiconductor layer having a second conductivity type different from the first conductivity type,wherein a first electrode is formed on the first compound semiconductor layer through a contact layer,
wherein the contact layer has a thickness of four or less atomic layers, and
wherein when an interface between the contact layer and the first compound semiconductor layer is an xy-plane, a lattice constant along an x-axis of crystals constituting an interface layer which is a part of the first compound semiconductor layer in contact with the contact layer is x1, a lattice constant along a z-axis is z1, a length along the x-axis in one unit of crystals constituting the contact layer is xc?, and a length along the z-axis is zc?,
(zc?/xc?)>(z1/x1)is satisfied.

US Pat. No. 10,170,666

LED LIGHT SOURCE MODULE AND DISPLAY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A light-emitting diode (LED) light source module comprising a light emitting stacked body, the light emitting stacked body comprising:a base insulating layer;
a first light emitting layer, a second light emitting layer, a third light emitting layer sequentially stacked on the base insulating layer, and configured to emit light having different wavelengths, each of the first light emitting layer, the second light emitting layer, and the third light emitting layer comprising a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer;
a first interlayer insulating layer disposed between the first light emitting layer and the second light emitting layer; and
a second interlayer insulating layer disposed between the second light emitting layer and the third light emitting layer,
wherein the light emitting stacked body is divided into pixel regions defined by a partition structure passing through the first light emitting layer, the second light emitting layer, the third light emitting layer, the first interlayer insulating layer, and the second interlayer insulating layer, and
each of the pixel regions comprises:
a common electrode passing through the base insulating layer, the first light emitting layer, the second light emitting layer, the first interlayer insulating layer, and the second interlayer insulating layer, and connected to the first conductivity-type semiconductor layer of each of the first light emitting layer, the second light emitting layer, and the third light emitting layer;
a first individual electrode passing through the base insulating layer, and connected to the second conductivity-type semiconductor layer of the first light emitting layer;
a second individual electrode passing through the base insulating layer, the first light emitting layer, and the first interlayer insulating layer, and connected to the second conductivity-type semiconductor layer of the second light emitting layer; and
a third individual electrode passing through the base insulating layer, the first light emitting layer, the second light emitting layer, the first interlayer insulating layer, and the second interlayer insulating layer, and connected to the second conductivity-type semiconductor layer of the third light emitting layer.

US Pat. No. 10,170,664

SURFACE MOUNT EMISSIVE ELEMENTS

eLux, Inc., Vancouver, W...

1. A surface mount light emitting diode (SMLED) comprising:a top surface;
a bottom comprising a globally flat planar surface;
a first electrical contact formed exclusively on the top surface and configured as a ring;
a second electrical contact formed exclusively on the top surface within a first electrical contact ring perimeter;
a single post connected to and extending from the bottom surface
a first semiconductor layer, with a dopant selected from a first group consisting of an n-dopant or a p-dopant;
a second semiconductor layer, with the unselected dopant from the first group;
a multiple quantum well (MQW) layer interposed between the first semiconductor layer and the second semiconductor layer;
wherein the first semiconductor layer and MQW layer are a stack underlying the first electrical contact, in the shape of a ring; and,
wherein the second semiconductor layer has a disk shape with a center portion underlying the second electrical contact.

US Pat. No. 10,170,663

SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor light emitting device package, comprising:a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer;
a plurality of bumps disposed on a first surface of the light emitting structure and electrically connected to the first or the second conductivity-type semiconductor layer;
a reflective layer disposed on the first surface of the light emitting structure, disposed on at least a portion of side surfaces of the light emitting structure, and disposed on at least a portion of bump side surfaces of the plurality of bumps;
a wavelength conversion layer disposed on a second surface of the light emitting structure opposite the first surface of the light emitting structure; and
a light transmissive substrate disposed on the wavelength conversion layer,
wherein each of the side surfaces of the light emitting structure is in contact with the reflective layer and the wavelength conversion layer.

US Pat. No. 10,170,662

METHOD FOR MANUFACTURING CIRCUIT BOARD, METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE, AND LIGHT-EMITTING DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a circuit board comprising:a first process;
a second process;
a third process;
a fourth process; and
a fifth process,
wherein the first process comprises a step of providing a circuit and an electrode on a first surface of a first substrate,
wherein the second process comprises a step of providing a reflective layer on the first surface side of the first substrate or a second surface side of a second substrate,
wherein the third process comprises a step of attaching the first surface and the second surface to each other with a bonding layer therebetween to face each other so that the reflective layer overlaps with the electrode and the reflective layer surrounds part of the electrode,
wherein the fourth process comprises a step of irradiating at least part of the reflective layer with laser light from a side opposite to the electrode such that a periphery of a region of the first substrate is irradiated with laser light or a periphery of a region of the second substrate is irradiated with laser light, and
wherein the fifth process comprises a step of removing at least the region of the first substrate or at least the region of the second substrate by pulling the region of the first substrate or the region of the second substrate.

US Pat. No. 10,170,661

INTEGRATED PHOTODETECTOR WAVEGUIDE STRUCTURE WITH ALIGNMENT TOLERANCE

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming a waveguide structure; and
forming a photodetector fully landed on the waveguide structure,
wherein the forming the photodetector comprises:
forming a dielectric material directly on a planar top surface of the waveguide structure;
forming a polycrystalline material directly on a top surface of the dielectric material;
forming an upper hardmask material directly on a top surface and sidewalls of the polycrystalline material, wherein the upper hardmask material and the dielectric material are a same material which form an encapsulating material directly contacting a lower surface, the top surface and the sidewalls of polycrystalline material and which fully encapsulates and fully seals the photodetector; and
crystallizing the polycrystalline material through an annealing process,
wherein the upper hardmask material and the dielectric material are both oxide material or nitride material directly on a bottom surface, the top surface and the sidewalls of the polycrystalline material.

US Pat. No. 10,170,660

DIGITAL ALLOY GERMANIUM HETEROJUNCTION SOLAR CELL

International Business Ma...

1. A photovoltaic device, comprising:a digital alloy buffer layer including a plurality of alternating layers of semiconductor material, wherein the digital alloy buffer layer includes a mass variance adjusted by isotropic enrichment in the digital alloy buffer layer to increase thermal conductivity of the digital alloy buffer layer;
an absorption layer epitaxially grown directly on the digital alloy buffer layer;
an intrinsic layer formed on the absorption layer;
a doped layer formed on the intrinsic layer; and
a metal contact formed on the doped layer.

US Pat. No. 10,170,659

MONOLITHICALLY INTEGRATED THIN-FILM ELECTRONIC CONVERSION UNIT FOR LATERAL MULTIJUNCTION THIN-FILM SOLAR CELLS

International Business Ma...

1. An integrated thin-film lateral multi junction solar device, comprising:a substrate;
a plurality of stacks extending vertically from the substrate, each stack comprising layers, wherein each stack is electrically isolated against another stack, each stack comprising:
an energy storage device above the substrate;
a solar cell above the energy storage device,
a transparent medium above the solar cell, and
a micro-optic layer of spectrally dispersive and concentrating optical devices above the transparent medium, wherein the micro-optic layer is a combination of refractive and/or diffractive optical elements;
a first power converter connected between the energy storage device and a power bus; and
a second power converter connected between the solar cell and the power bus,
wherein different solar cells of different stacks have different absorption characteristics, and
wherein the different absorption characteristics of the different solar cells are based on different energy band-gaps of semiconductors building the solar cell.

US Pat. No. 10,170,657

SOLAR CELL HAVING AN EMITTER REGION WITH WIDE BANDGAP SEMICONDUCTOR MATERIAL

SunPower Corporation, Sa...

1. A solar cell, comprising:a single crystalline silicon substrate;
a doped amorphous silicon layer disposed directly on a thin oxide layer disposed on a surface of the single crystalline silicon substrate, wherein the doped amorphous silicon layer is an emitter region sufficiently thin to minimize optical absorption, and wherein the doped amorphous silicon layer is doped throughout an entirety of the doped amorphous silicon layer; and
a conductive contact disposed directly on, and conductively coupled to, the doped amorphous silicon layer, wherein the conductive contact has a metallic material in direct contact with the doped amorphous silicon layer.

US Pat. No. 10,170,655

ENERGY HARVESTING DEVICE WITH PREFABRICATED THIN FILM ENERGY ABSORPTION SHEETS AND ROLL-TO-SHEET AND ROLL-TO-ROLL FABRICATION THEREOF

International Business Ma...

1. A roll-to-sheet method for fabricating energy harvesting devices comprising:unrolling a plurality of prefabricated thin film energy absorption sheets from a plurality of corresponding rolls of the prefabricated thin film energy absorption sheets into which the prefabricated thin film energy absorption sheets have been wound;
laminating the prefabricated thin film energy absorption sheets together after unrolling, resulting in more than one of the prefabricated thin film energy absorption sheets being laminated together;
after lamination, drilling a plurality of vias through the prefabricated thin film energy absorption sheets that have been laminated together;
filling the vias with a conductive material; and
dividing the thin film sheets into the energy harvesting devices after drilling and filling the vias,
wherein the prefabricated thin film energy absorption sheets absorb electromagnetic energy.

US Pat. No. 10,170,652

METAMORPHIC SOLAR CELL HAVING IMPROVED CURRENT GENERATION

THE BOEING COMPANY, Chic...

1. A lattice mismatched metamorphic semiconductor device having at least one subcell, the at least one subcell comprising:a base layer;
an emitter layer in electrical connectivity with the base layer, wherein the base layer and emitter layer form a p-n junction in a photovoltaic cell or other optoelectronic device;
a low bandgap absorber region disposed in either or both of the base layer and emitter layer, wherein the low bandgap absorber region has a higher photogeneration and a lower bandgap than surrounding semiconductor layers;
wherein the low bandgap absorber region forms tensile and compressive regions having alternating smaller and larger lattice constants than that of an average lattice constant of the lattice mismatched metamorphic semiconductor device;
wherein the low bandgap absorber region does not form a quantum well,
wherein the subcell further comprises one or more small-lattice-constant strain-compensation regions adjacent to the low bandgap absorber region, wherein a lattice constant of the one or more strain compensation regions is less than the lattice constant of the low bandgap absorber region, wherein strain in the low bandgap absorber region is balanced by strain in the opposite direction by the strain compensation regions, the strain compensation regions having a larger bandgap than the low bandgap absorber region,
wherein the low bandgap absorber region comprises: a 1-dimensional geometric configuration comprising one or more of a linear feature, a curved line, a plurality of discontinuous line-like features, or combinations thereof and wherein the strain compensation regions having a larger bandgap than the low bandgap absorber region encapsulating the 1-dimensional geometric configurations.

US Pat. No. 10,170,648

SEMICONDUCTOR NANOCRYSTAL, AND METHOD OF PREPARING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A nanocrystal comprising:a core consisting of a Group III element, P, and a Group II element; and
a shell overcoating the core and comprising ZnSeS multi-layers consisting of Zn, Se, and S, wherein a single monolayer directly disposed on a surface of the core in the shell comprises a compound of the formula ZnSexS(1-x),
wherein an average ratio of x:(1?x) in the single monolayer ranges from about 5:1 to about 20:1,
wherein the shell further comprises at least two additional single monolayers each comprising a compound of the formula ZnSeyS(1-y), wherein 0 wherein the at least two additional single monolayers have a Se:S concentration ratio gradient between the at least two additional single monolayers,
wherein the Se:S concentration ratio gradient comprises an increasing concentration of Se and a decreasing concentration of S in a direction from the core to a predetermined single monolayer; and a decreasing concentration of Se and an increasing concentration of S in a direction from the predetermined single monolayer to an outermost single monolayer, wherein the predetermined single monolayer is located between the single monolayer directly disposed on the surface of the core and the outermost single monolayer, and
wherein the nanocrystal has a luminous efficiency “QY” of greater than 70 percent.

US Pat. No. 10,170,647

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

LG ELECTRONICS INC., Seo...

1. A solar cell module comprising:a semiconductor substrate;
a plurality of first electrodes and a plurality of second electrodes which are formed to be separated from each other on a back surface of the semiconductor substrate;
an insulating member including a first auxiliary electrode connected to the plurality of first electrodes and a second auxiliary electrode connected to the plurality of second electrodes; and
an interconnector connected to the first auxiliary electrode and the second auxiliary electrode for connecting adjacent two solar cells of a plurality of solar cells;
wherein the plurality of first electrodes and the first auxiliary electrode are connected to each other using a conductive adhesive including a resin layer and conductive metal particles distributed in the resin layer, and the plurality of second electrodes and the second auxiliary electrode are connected to each other using the conductive adhesive,
wherein the plurality of first and second electrodes are insulated from each other through an insulating layer, or the first and second auxiliary electrodes are insulated from each other through the insulating layer, and the insulating layer bonds the insulating member to the semiconductor substrate,
wherein the resin layer included in the conductive adhesive and the insulating layer contain the same resin material,
wherein the insulating layer includes light reflection particles to reflect incident light, and
wherein the interconnector is positioned between two semiconductor substrates of the adjacent two solar cells and is not overlapped with the two semiconductor substrates when viewed from a direction perpendicular to a major surface of the two semiconductor substrates and the interconnector further has a non-overlapped portion that is not overlapped with the insulating member.

US Pat. No. 10,170,646

SOLAR CELL MODULE

LG ELECTRONICS INC., Seo...

1. A solar cell module comprising:a plurality of solar cells each including a semiconductor substrate, an emitter region forming a p-n junction along with the semiconductor substrate, a first electrode connected to the emitter region, and a second electrode connected to a back surface of the semiconductor substrate; and
a plurality of wiring members connected to the first electrode or the second electrode of each solar cell and configured to electrically connect the plurality of solar cells in series,
wherein a number of the plurality of wiring members connected to the first electrode or the second electrode of each solar cell is 6 to 30, and the plurality of wiring members have a circular cross-section,
wherein each first electrode includes:
a plurality of front fingers configured to extend in one direction in parallel with one another;
a plurality of pads formed at crossings of the plurality of front fingers and the plurality of wiring members; and
a plurality of connection electrodes configured to connect the plurality of pads in a direction crossing the plurality of front fingers,
wherein a length of each of the plurality of pads in a length direction of the plurality of front fingers is more than a line width of the plurality of wiring members, and a width of each of the plurality of pads in a length direction of the plurality of wiring members is more than a line width of the plurality of front fingers,
wherein a number of the plurality of pads connected to any one of the plurality of wiring members is smaller than a number of the plurality of front fingers connected to the any one of the plurality of wiring members,
wherein each connection electrode has a width smaller than the line width of the plurality of wiring members, and
wherein each connection electrode and each wiring member are parallel so that each wiring member respectively covers each connection electrode.

US Pat. No. 10,170,645

ORGANIC VEHICLE FOR ELECTROCONDUCTIVE PASTE

1. An electroconductive paste for use in solar cell technology comprising:about 60-90 wt % of metallic particles comprising silver, based upon total weight of the electroconductive paste;
about 1-10 wt % glass frit, based upon total weight of the electroconductive paste; and
about 1-20 wt % of an organic vehicle, based upon total weight of the electroconductive paste, the organic vehicle comprising:
about 1-10 wt % of a polyvinyl pyrrolidone (PVP) binder, based upon total weight of the organic vehicle,
about 1-20 wt % of a surfactant, based upon total weight of the organic vehicle,
about 50-70 wt % of an organic solvent comprising terpineol, based upon total weight of the organic vehicle, and
about 1-10 wt % ethyl cellulose, based upon total weight of the organic vehicle,
wherein the electroconductive paste is suitable for screen printing onto a substrate.

US Pat. No. 10,170,644

PROCESSES FOR UNIFORM METAL SEMICONDUCTOR ALLOY FORMATION FOR FRONT SIDE CONTACT METALLIZATION AND PHOTOVOLTAIC DEVICE FORMED THEREFROM

INTERNATIONAL BUSINESS MA...

1. A photovoltaic device comprising:a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one lying on top of the other, wherein an upper exposed surface of the semiconductor substrate represents a front side surface of the semiconductor substrate;
a plurality of patterned antireflective coatings on the front side surface of the semiconductor substrate to provide a grid pattern including a busbar region located between finger regions, wherein the busbar region comprises at least a real line interposed between at least two dummy lines, and wherein the finger regions each comprise at least a real line located between at least two dummy lines; and
a material stack comprising at least one metal layer located on the semiconductor substrate in the busbar region and the finger regions.

US Pat. No. 10,170,643

METHOD FOR MANUFACTURING BARRIER FILM WITH ENHANCED MOISTURE RESISTANCE AND BARRIER FILM MANUFACTURED BY THE SAME

Hyundai Motor Company, S...

1. A method of manufacturing a barrier film with improved moisture resistance comprising:(a) forming an oxide thin film on a substrate by deposition; and
(b) high-pressure thermal treating the oxide thin film using gas at a temperature of from about 50 to 500° C. and at a pressure of from about 20 to 50 atm, wherein the high-pressure thermal treatment of step (b) is carried out from about 30 minutes to 3 hours,
wherein the oxide thin film is formed by sequentially depositing SiO2 and ZrO2 on the substrate by sputtering deposition.

US Pat. No. 10,170,642

SOLAR CELLS WITH IMPROVED LIFETIME, PASSIVATION AND/OR EFFICIENCY

SunPower Corporation, Sa...

1. A solar cell, the solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, the solar cell comprising:a dielectric region over a silicon substrate, wherein a portion of the silicon substrate has a dopant concentration of approximately less than or equal to 2×1018 cm?3, wherein the first emitter region is a N-type doped polysilicon region;
a first emitter region having metal impurities formed over the dielectric region; and
a first metal contact formed over the first emitter region;
a second emitter region having metal impurities formed over the dielectric emitter region, wherein the second emitter region is formed at least partially over the first emitter region, and wherein the first and second emitter regions are formed on a same side of the solar cell; and
a second metal contact formed over the second emitter region, wherein the second emitter region is a P-type doped polysilicon region.

US Pat. No. 10,170,641

VERTICAL PIN DIODE

ELECTRONICS AND TELECOMMU...

1. A vertical positive-intrinsic-negative (pin) diode comprising:a semiconductor substrate in which a P-type region, an intrinsic region, and an N-type region are formed therein to be sequentially disposed in a vertical direction;
a first electrode formed on one surface of the semiconductor substrate to be in electrical contact with the P-type region;
a second electrode formed on another surface of the semiconductor substrate to be in electrical contact with the N-type region;
a first waveguide layer formed of a metallic material on the one surface of the semiconductor substrate; and
a second waveguide layer formed of a metallic material on the other surface of the semiconductor substrate,
wherein the P-type region and the N-type region are respectively disposed in an upper portion and a lower portion of the semiconductor substrate to be opposite to each other, and
wherein the first waveguide layer and the second waveguide layer are layers for guiding radio waves in predetermined direction.

US Pat. No. 10,170,640

FINFET TRANSISTOR GATE AND EPITAXY FORMATION

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a semiconductor fin on a substrate;
forming a buffer layer on a surface of the substrate and adjacent to the semiconductor fin;
forming a semiconducting layer on the buffer layer to define a fin height of the semiconductor fin; and
replacing the buffer layer with a dielectric layer.

US Pat. No. 10,170,639

3D MEMORY

Micron Technology, Inc., ...

1. A vertical memory comprising:a stack of memory cells, each cell of the stack extending between two respective vertically spaced dielectric tiers, each cell comprising:
a control gate having a vertical surface;
a charge storage structure having a vertical surface facing the vertical surface of the control gate;
a barrier film between the charge storage structure and the control gate, the barrier film having a first vertical surface facing the vertical surface of the control gate and a second vertical surface opposite the first vertical surface and facing the vertical surface of the charge storage structure, wherein the barrier film is situated entirely within a horizontal dimension between the vertical surface of the control gate and the vertical surface of the charge storage structure;
a first dielectric extending between the first vertical surface of the barrier film and the charge storage structure; and
a second dielectric extending between the first vertical surface of the barrier film and the control gate, wherein at least one of the first dielectric and the second dielectric further extends between the charge storage structure and the two respective vertically spaced dielectric tiers, and wherein at least one of the first dielectric and the second dielectric further extends between the barrier film and the two respective vertically spaced dielectric tiers.

US Pat. No. 10,170,638

NANOSHEET SUBSTRATE ISOLATED SOURCE/DRAIN EPITAXY BY DUAL BOTTOM SPACER

International Business Ma...

1. A semiconductor structure comprising:a plurality of stacked and suspended semiconductor channel material nanosheets located above a semiconductor substrate;
a functional gate structure surrounding a portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets;
a source/drain (S/D) region on each side of the functional gate structure and physically contacting sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets; and
a dual spacer structure located on surfaces of the semiconductor substrate that are located adjacent the functional gate structure, wherein the dual spacer structure separates the source/drain region from the semiconductor substrate.

US Pat. No. 10,170,637

PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE

INTERNATIONAL BUSINESS MA...

1. A method of forming as semiconductor device comprising:forming a first replacement gate structure of light sensitive material is present on a channel region portion of the stack of suspended nanowires;
replacing the first replacement gate structure of the light sensitive material with a second replacement gate structure of a semiconductor gate material;
applying a surface treatment process to at least sidewall surfaces of the second replacement gate structure to convert a portion of the semiconductor gate material to a dielectric spacer on said at least the sidewall surfaces of the second replacement gate structure; and
replacing the second replacement gate structure with a functional gate structure.

US Pat. No. 10,170,636

GATE-TO-BULK SUBSTRATE ISOLATION IN GATE-ALL-AROUND DEVICES

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a fin including a first semiconductor material on a substrate, wherein the first semiconductor material includes silicon germanium having a first concentration of germanium in the silicon germanium;
a nanowire over the fin, the nanowire including a second semiconductor material, wherein the second semiconductor material includes silicon germanium having a second concentration of germanium in the silicon germanium; and
wherein the first concentration is at least 10% less than the second concentration;
a first layer of oxide material on exposed portions of the nanowire and a second layer of oxide material on the fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness; and
a gate stack over a channel region of the nanowire, the gate stack including a gate dielectric layer on the nanowire and directly on the second layer of oxide material, a workfunction metal on the gate dielectric layer, and a gate conductor on the workfunction metal.

US Pat. No. 10,170,635

SEMICONDUCTOR DEVICE, DISPLAY DEVICE, DISPLAY APPARATUS, AND SYSTEM

RICOH COMPANY, LTD., Tok...

1. A semiconductor device comprising:a base;
a gate electrode to which a gate voltage is applied;
a source electrode and a drain electrode through which an electric current is generated according to the gate voltage being applied to the gate electrode;
a semiconductor layer made of an oxide semiconductor;
a gate insulating layer inserted between the gate electrode and the semiconductor layer, wherein
the semiconductor layer includes a channel-forming region and a non-channel-forming region, each having
an insulating-layer-facing face facing the gate insulating layer, and
a base-facing face facing the base layer and opposite to the insulating-layer-facing face,
the channel-forming region is in contact with the source electrode and the drain electrode, and
the non-channel-forming region is in contact with the source electrode and the drain electrode.

US Pat. No. 10,170,634

WIRE-LAST GATE-ALL-AROUND NANOWIRE FET

INTERNATIONAL BUSINESS MA...

1. A nanowire field effect transistor (FET) device comprising:a first source/drain region and a second source/drain region, each on an upper surface of a bulk semiconductor substrate, the bulk semiconductor substrate including a single layer of semiconductor material extending from a base to the upper surface, the single layer excluding an insulator layer between the base and the upper surface;
a gate region interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate;
a plurality of nanowires only in the gate region, the nanowires suspended above the semiconductor substrate and defining gate channels of the nanowire FET device; and
a gate structure including a gate electrode in the gate region and sidewalls spacers on sidewalls of the gate electrode that directly contact the upper surface of the bulk semiconductor substrate, the gate electrode formed directly on the upper surface of the bulk semiconductor substrate and contacting an entire surface of each nanowire.

US Pat. No. 10,170,633

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising the steps of:forming an oxide semiconductor film over a substrate;
forming a conductive film over the oxide semiconductor film;
heating the conductive film formed over the oxide semiconductor film;
forming a first resist mask over the conductive film;
etching the conductive film using the first resist mask to form a source electrode and a drain electrode;
forming a second resist mask over the oxide semiconductor film after etching the conductive film;
etching the oxide semiconductor film using the second resist mask,
forming a gate insulating film over the oxide semiconductor film; and
forming a gate electrode over the gate insulating film.

US Pat. No. 10,170,632

SEMICONDUCTOR DEVICE INCLUDING OXIDE SEMICONDUCTOR LAYER

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor including a first oxide semiconductor layer; and
a second transistor including a second oxide semiconductor layer,
wherein the second transistor includes a first gate electrode below the second oxide semiconductor layer and a second gate electrode above the second oxide semiconductor layer,
wherein the second oxide semiconductor layer includes a first region and a second region,
wherein the second region overlaps with a source or a drain electrode of the second transistor,
wherein a thickness of the first region is smaller than a thickness of the second region, and
wherein the first transistor is electrically connected to a pixel electrode, and the pixel electrode is formed using the same material as the second gate electrode.

US Pat. No. 10,170,631

MANUFACTURING METHODS OF OXIDE THIN FILM TRANSISTORS

Wuhan China Star Optoelec...

1. A manufacturing method of oxide thin film transistors (TFTs), comprising:providing a substrate and forming an oxide semiconductor active layer on the substrate;
depositing an insulation dielectric layer on the active layer;
applying an annealing process to components formed after the insulation dielectric layer is deposited;
wherein the insulation dielectric layer comprises at least SiOx thin layer directly connected to the active layer; and
wherein the insulation dielectric layer further comprises a SiNX thin layer deposited on the SiOx thin layer.

US Pat. No. 10,170,630

MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

Semiconductor Energy Labo...

1. A manufacturing method of a semiconductor device comprising:forming a transistor comprises a gate electrode;
forming a cylindrical semiconductor consisting of an oxide semiconductor on and in contact with the gate electrode;
forming a gate insulating film covering a side surface and a top surface of the cylindrical semiconductor; and
forming a first conductor covering the side surface of the cylindrical semiconductor with the gate insulating film therebetween.

US Pat. No. 10,170,629

FIELD-EFFECT TRANSISTOR AND THE MANUFACTURING METHOD

Shenzhen China Star Optoe...

1. A method for manufacturing a field-effect transistor, comprising:depositing a first insulating layer on a substrate;
forming a source electrode and a drain electrode on the first insulating layer;
forming a carbon quantum dots active layer covering the source electrode and the drain electrode; and
forming a second insulating layer and a gate electrode on the carbon quantum dots active layer sequentially;
wherein forming the carbon quantum dots active layer covering the source electrode and the drain electrode comprises:
dissolving the carbon quantum dots in octane to form a first mixed solution;
coating the first mixed solution on the first insulating layer, the source electrode and the drain electrode by a spin coating technology to form the carbon quantum dots film layer; and
vacuum baking the carbon quantum dots film to form the carbon quantum dots active layer covering the source electrode and the drain electrode;
wherein the first insulating layer depositing on a substrate further comprises:
forming a first material layer on the substrate by a chemical vapor deposition method, the first material layer is a silicon oxide layer, an alumina layer, a silicon nitride layer, or a mixed layer of silicon oxide, aluminum oxide and silicon nitride;
soaking and rinsing the first material layer with a second mixed solution; and
drying the first material layer after soaking and rinsing to form the first insulating layer.

US Pat. No. 10,170,628

METHOD FOR FORMING AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) DEVICE HAVING REDUCED PARASITIC CAPACITANCE AND CONTACT RESISTANCE DUE TO WRAP-AROUND STRUCTURE OF SOURCE/DRAIN REGIONS

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, comprising:forming first spacers on sides of a gate structure and second spacers on the first spacers;
etching a semiconductor layer below the gate structure using the second spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure;
forming undercuts in a buried dielectric layer below the semiconductor layer; and
epitaxially growing source and drain regions wrapped around the semiconductor layer from a top of the semiconductor layer and into the undercuts on an opposite side of the semiconductor layer.

US Pat. No. 10,170,627

NANOWIRE TRANSISTOR WITH SOURCE AND DRAIN INDUCED BY ELECTRICAL CONTACTS WITH NEGATIVE SCHOTTKY BARRIER HEIGHT

Acorn Technologies, Inc.,...

1. A nanowire transistor, comprising:a gate circumferentially surrounding and displaced from a semiconductor nanowire channel by an electrically insulating gate oxide, the semiconductor nanowire channel having no intentional doping;
a source at a first end of the nanowire channel, and a drain at a second end of the nanowire channel, the source and drain each comprising undoped semiconductor material; and
a first metal contact circumferentially surrounding the source and providing an electrically conductive path to the source, and a second metal contact circumferentially surrounding the drain and providing an electrically conductive path to the drain,
wherein the first metal contact electrostatically induces free charge carriers in the source, the first metal contact is separated from the gate by an insulating material layer or a gap, and the second metal contact is separated from the gate by an insulating material layer or a gap.

US Pat. No. 10,170,626

TRANSISTOR PANEL HAVING A GOOD INSULATION PROPERTY AND A MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A transistor panel, comprising:a channel region including a first oxide of a first metal;
a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source region and the drain region, and wherein the channel region is connected to the source region and the drain region;
an insulation layer disposed on the channel region;
an upper electrode disposed on the insulation layer;
an interlayer insulation layer disposed on the upper electrode, the source region and the drain region; and
a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source region and the drain region, wherein the first portion of the barrier layer contacts each of the source region and the drain region,
wherein the upper electrode and the barrier layer each comprise a second metal, and
the barrier layer does not overlap the upper electrode in a direction perpendicular to a top surface of the upper electrode.

US Pat. No. 10,170,624

NON-PLANAR TRANSISTOR

UNITED MICROELECTRONICS C...

1. A non-planar transistor, comprising:a fin structure disposed on a substrate, wherein the fin structure comprises an upper portion, a concave portion and a lower portion, and the concave portion is disposed between the upper portion and the lower portion;
a gate structure disposed on the fin structure;
a first spacer structure disposed on a sidewall of the gate structure, wherein the first spacer structure comprises a first spacer and a second spacer, the first spacer is disposed between the gate structure and the second spacer, and a height of the first spacer is different from a height of the second spacer;
a source/drain region disposed in a semiconductor layer at a side of the first spacer structure, wherein the material of the semiconductor layer is different from the material of the fin structure;
a shallow trench isolation (STI) surrounding the fin structure; and
a second spacer structure disposed on the shallow trench isolation, wherein a part of the semiconductor layer is disposed on the fin structure, and the second spacer structure comprises a third spacer and a fourth spacer, wherein the third spacer is disposed between the fourth spacer and the semiconductor layer on the fin structure, and the third spacer is disposed between the semiconductor layer and the shallow trench isolation, wherein a height of the third spacer is different from a height of the fourth spacer, and the semiconductor layer covers an outer sidewall of the third spacer in a cross-section.

US Pat. No. 10,170,623

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor device, comprising:providing a plurality of mandrels on a substrate, each of the mandrels spaced from each other on a planar surface of the substrate;
removing a portion of the mandrels and a portion of the substrate to form a trench across the mandrels, the trench having a bottom surface lower than the planar surface;
forming a plurality of spacers not sealing the whole trench formed on the planar surface of the substrate, the spacers only covering sidewalls of the mandrels and the trench;
after completely removing the mandrels, using the spacers as a mask to form a plurality of fin shaped structures on the substrate and a plurality of shallow trenches surrounding the fin shaped structures; and
removing a portion of the spacers to form a spacing layer on the sidewalls of the trench, wherein the spacing layer has a top surface being lower than a top surface of the fin shaped structures.

US Pat. No. 10,170,622

SEMICONDUCTOR DEVICE INCLUDING MOS TRANSISTOR HAVING SILICIDED SOURCE/DRAIN REGION AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit structure comprising:a semiconductor substrate;
a gate structure over the semiconductor substrate;
a spacer on a sidewall of the gate structure;
a silicon germanium region including a first silicon germanium region and a second silicon germanium region;
the first silicon germanium region being located in the substrate, and the first silicon germanium region having a first germanium percentage,
the second silicon germanium region lying over the first silicon germanium region, and the second silicon germanium region having a second germanium percentage higher than the first germanium percentage; and
a metal silicide region over the second silicon germanium region,
wherein the spacer has a side surface and bottom surface extending from a lower end of the side surface, the bottom surface of the spacer facing the substrate,
the silicon germanium region has an inclined surface,
one part of the inclined surface of the silicon germanium region intersects the side surface of the spacer at a level above the lower end of the side surface, and
another part of the inclined surface of the silicon germanium region intersects the bottom surface of the spacer at a second location spaced from the lower end of the side surface of the spacer in a direction towards the gate structure, such that the silicon germanium region contacts the spacer along both the side surface and the bottom surface of the spacer.

US Pat. No. 10,170,621

METHOD OF MAKING A TRANSISTOR HAVING A SOURCE AND A DRAIN OBTAINED BY RECRYSTALLIZATION OF SEMICONDUCTOR

1. Method of making a transistor, comprising:forming a gate and a first dielectric spacer in contact with the side walls of the gate, on a first region of a first layer that will form the transistor channel, the first layer being a crystalline semiconducting layer;
forming first portions of crystalline semiconductor on second regions of the first layer that will form part of the transistor source and drain;
making at least the second regions of the first layer amorphous and doping them;
recrystallizing at least the semiconductor in the second regions of the first layer and activating the dopants present at least in the semiconductor of the second regions of the first layer;
removing the first portions;
forming a second dielectric spacer in contact with the lateral walls of the gate such that the thickness of the second dielectric spacer is more than the thickness of the first dielectric spacer;
forming second portions of doped crystalline semiconductor on the second regions of the first layer such that at least said second portions and the second regions of the first layer together form the source and drain of the transistor.

US Pat. No. 10,170,620

SUBSTANTIALLY DEFECT FREE RELAXED HETEROGENEOUS SEMICONDUCTOR FINS ON BULK SUBSTRATES

International Business Ma...

1. A semiconductor structure comprising:a bulk semiconductor substrate of a first semiconductor material;
a plurality of spaced apart fin pedestal structures of a second semiconductor material located on said bulk semiconductor substrate of said first semiconductor material, wherein said second semiconductor material is different from said first semiconductor material;
a pair of spaced apart semiconductor fins of said second semiconductor material located on each fin pedestal structure, wherein one of said semiconductor fins of said pair of spaced apart semiconductor fins has a sidewall surface that is vertically aligned with a sidewall surface of a first end of each of said fin pedestal structures and another of said semiconductor fins of said pair of spaced apart semiconductor has a sidewall surface that is vertically aligned with a sidewall surface of a second end of each of said fin pedestal structures;
a first dielectric material structure located between each semiconductor fin of said pair of semiconductor fins, said first dielectric material structure is located on an exposed topmost surface of each of said fin pedestal structures; and
a second dielectric material structure located between each fin pedestal structure and present on said bulk semiconductor substrate, wherein said first and second dielectric material structures comprise a dielectric material having an upper undoped region and a lower doped region, and wherein said lower doped region of the first dielectric material structure has a topmost surface that is coplanar with a topmost surface of said lower doped region of said second dielectric material structure, and wherein said upper doped region of the first dielectric material structure has a topmost surface that is coplanar with a topmost surface of said upper doped region of said second dielectric material structure.

US Pat. No. 10,170,618

VERTICAL TRANSISTOR WITH REDUCED GATE-INDUCED-DRAIN-LEAKAGE CURRENT

International Business Ma...

14. A vertical transport fin field effect transistor, comprising:a bottom source/drain layer at the surface of the substrate;
one or more channels on the bottom source/drain layer, where the channels extend away from the bottom source/drain layer;
an extension region between each of the one or more channels and the bottom source/drain layer;
a gate structure on each of the one or more channels; and
a top source/drain segment on the top surface of each of the one or more channels, wherein either each of the top source/drain segments or the bottom source/drain layer has a bandgap in the range of about 1.0 eV to about 1.2 eV, and the other of the bottom source/drain layer or each of the top source/drain segments has a bandgap in the range of about 0.7 eV to about 0.9 eV.

US Pat. No. 10,170,615

SEMICONDUCTOR DEVICE INCLUDING A LATERAL TRANSISTOR

Infineon Technologies Aus...

1. A semiconductor device, comprising:a drift contact region;
a drain region of a first conductivity type, the drift contact region and the drain region being arranged in a first direction parallel to a first main surface of a semiconductor substrate;
a layer stack comprising a drift layer of the first conductivity type and a compensation layer of a second conductivity type, the drain region being electrically connected with the drift layer;
a body region of the second conductivity type;
a connection region of the second conductivity type extending from the first main surface of the semiconductor substrate and into the layer stack, the connection region being electrically connected with the compensation layer; and
a buried semiconductor portion beneath the layer stack and in electrical contact with the connection region,
wherein the buried semiconductor portion does not fully overlap with the drift layer,
wherein in the first direction, the layer stack is interposed between the drain region and the drift contact region and the drift contact region is interposed between the layer stack and the body region.

US Pat. No. 10,170,613

SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a first transistor disposed on the semiconductor substrate, the first transistor including:
a first semiconductor layer;
an active region in the first semiconductor layer; and
a first conductive layer underlying the first semiconductor layer; and
a second transistor disposed on the semiconductor substrate, the second transistor including:
a second semiconductor layer;
another active region in the second semiconductor layer; and
a second conductive layer underlying the second semiconductor layer and electrically isolated from the first conductive layer.

US Pat. No. 10,170,612

EPITAXIAL BUFFER LAYERS FOR GROUP III-N TRANSISTORS ON SILICON SUBSTRATES

Intel Corporation, Santa...

1. A semiconductor material stack, comprising:a silicon substrate having a first lattice constant;
a group III-N device layer disposed over the silicon substrate, the group III-N device layer having a second lattice constant different than the first lattice constant;
a buffer disposed between the silicon substrate and the group III-N device layer, wherein the buffer includes an AlxIn1-xN layer, with x being less than unity; a top barrier layer formed above the group III-N device layer;
N-type group III-N source and drain regions disposed on the top barrier layer;
a gate electrode disposed between the N-type group III-N source and drain regions, wherein the top barrier layer has a first thickness between the gate electrode and the group III-N device layer and a second, greater, thickness between the N-type group III-N source and drain regions and the group III-N device layer, and
a third thickness between a spacer region disposed between the gate electrode and each of the group III-N source and drain regions and the group III-N device layer, wherein the third thickness is intermediate to the first thickness and the second thickness and a gate dielectric disposed below the gate electrode and adjacent to sidewalls of the gate electrode.

US Pat. No. 10,170,611

T-GATE FIELD EFFECT TRANSISTOR WITH NON-LINEAR CHANNEL LAYER AND/OR GATE FOOT FACE

HRL Laboratories, LLC, M...

1. A high electron mobility transistor (HEMT) comprising:a source contact spaced apart from a drain contact by a distance in a first direction;
a gate disposed between the source and drain contacts extending in a second direction perpendicular to the first direction comprising a gate head and a gate foot;
a first surface and a second surface of a channel;
a top barrier layer forming a 2DEG in the channel, wherein a surface of the source contact contacts a first surface of the channel and a first surface of the top barrier layer, and a surface of the drain contact contacts a second surface of the channel and a second surface of the top barrier layer, the first surface and the second surface of the channel facing away from one another;
wherein the gate foot comprises a curved section, and a contour width of the gate foot is greater than a superficial width of the gate head,
the first and second surfaces of the channel having sections with curved shapes related to the shape of the curved section of the gate foot, and
the curved section of the gate foot does not include a straight section.

US Pat. No. 10,170,565

IMAGING DEVICE, METHOD FOR DRIVING IMAGING DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. An imaging device comprising:a photoelectric conversion element;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor; and
a first capacitor,
wherein one terminal of the photoelectric conversion element is directly connected to one of a source electrode and a drain electrode of the first transistor,
wherein the other terminal of the photoelectric conversion element is directly connected to a first power supply line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the sixth transistor,
wherein the other of the source electrode and the drain electrode of the first transistor is directly connected to one terminal of the first capacitor,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the other terminal of the first capacitor,
wherein the one of the source electrode and the drain electrode of the third transistor is electrically connected to a gate electrode of the fourth transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is directly connected to one of a source electrode and a drain electrode of the fifth transistor,
wherein the gate electrode of the fourth transistor is directly connected to the other terminal of the first capacitor,
wherein the other of the source electrode and the drain electrode of the fifth transistor is directly connected to a second power supply line, and
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor.

US Pat. No. 10,170,564

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate, the manufacturing method of a semiconductor device comprising:forming an n-type gallium nitride layer on a gallium nitride monocrystalline substrate having a threading dislocation density of less than 1E+7 cm?2; and
forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, the impurities including at least one element selected from among magnesium, beryllium, calcium and zinc, wherein
at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.

US Pat. No. 10,170,563

GALLIUM NITRIDE SEMICONDUCTOR DEVICE WITH IMPROVED TERMINATION SCHEME

Alpha and Omega Semicondu...

1. A gallium nitride based semiconductor power device comprising:a top gallium nitride layer comprises a plurality of guard rings disposed in a peripheral area of the top gallium nitride layer wherein the guard rings comprise a plurality of trenches having substantially a same depth opened in an upper portion of the top gallium nitride layer filled with a P-doped gallium-based epitaxial layer therein and wherein the guard rings surrounding a first electrode of the semiconductor power device comprises a metal layer covering over a middle portion of a top surface of the top gallium nitride layer; and
a heavily doped bottom gallium nitride epitaxial layer extending beyond an outer edge of the top gallium nitride layer wherein an extended portion of the bottom gallium nitride epitaxial layer having an exposed top surface not covered by the top gallium nitride layer and wherein a second electrode of the semiconductor power device is disposed directly on the exposed top surface of the extended portion of the bottom gallium nitride layer.

US Pat. No. 10,170,562

SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device, comprising:a first conductive-type SiC semiconductor layer having a front surface and a rear surface;
an anode electrode having a multi-layered structure being in contact with the front surface of the SiC semiconductor layer; and
a cathode electrode formed on the rear surface of the SiC semiconductor layer, wherein
a Schottky junction is formed between the anode electrode and the front surface of the SiC semiconductor layer,
fine recesses are formed only in a SiC semiconductor layer side of a Schottky junction portion between the anode electrode and the front surface of the SiC semiconductor layer,
a part of the anode electrode is embedded in the fine recesses, and
the fine recesses have a depth not greater than 20 nm and are irregularly arranged on the SiC semiconductor layer.

US Pat. No. 10,170,561

DIAMOND SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A diamond semiconductor device comprising:a first diamond semiconductor layer of a first conductivity type having a main surface;
a second diamond semiconductor layer of an i-type or a second conductivity type provided on the main surface of the first diamond semiconductor layer, and having a first side surface with a plane orientation of a {111};
a third diamond semiconductor layer of the first conductivity type provided on the first side surface; and
a fourth diamond semiconductor layer of the second conductivity type provided on the main surface of the first diamond semiconductor layer and on a side surface of the second diamond semiconductor layer, at a side opposite to a side of the third diamond semiconductor layer.

US Pat. No. 10,170,560

SEMICONDUCTOR DEVICES WITH ENHANCED DETERMINISTIC DOPING AND RELATED METHODS

ATOMERA INCORPORATED, Lo...

1. A semiconductor device comprising:a semiconductor substrate;
a plurality of stacked groups of layers on the semiconductor substrate, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region, the dopant having a fall-off steeper than 3.3 nm/decade.

US Pat. No. 10,170,558

LOCALIZED AND SELF-ALIGNED PUNCH THROUGH STOPPER DOPING FOR FINFET

International Business Ma...

1. A method for doping punch through stoppers (PTSs), comprising:recessing a dielectric layer to form gaps between a top portion of the dielectric layer and a spacer formed on sidewalls of fins to expose the fins in the gaps; and
doping the fins through the gaps to form PTSs in the fins, wherein a doped region extends from a bottom surface of the PTSs into a substrate, wherein each fin is formed of a material compound that is different from the substrate.

US Pat. No. 10,170,557

THYRISTOR WITH IMPROVED PLASMA SPREADING

ABB Schweiz AG, Baden (C...

1. A thyristor device comprising:a semiconductor wafer having a first main side and a second main side opposite to the first main side;
a first electrode layer, which is arranged on the first main side;
a second electrode layer, which is arranged on the first main side and which is electrically separated from the first electrode layer;
a third electrode layer, which is arranged on the second main side;
wherein the semiconductor wafer includes the following layers;
a first emitter layer of a first conductivity type, the first emitter layer being in electrical contact with the first electrode layer;
a first base layer of a second conductivity type different from the first conductivity type, wherein the first base layer is in electrical contact with the second electrode layer, and wherein the first base layer and the first emitter layer form a first, p-n junction;
a second base layer of the first conductivity type, the second base layer and the fist base layer forming a second p-n junction;
a second emitter layer of the second conductivity type, wherein the second emitter layer is in electrical contact with the third electrode layer, and
wherein the second emitter layer and the second base layer form a third p-n junction.
wherein the thyristor device comprises a plurality of discrete emitter shorts, each emitter short penetrating through the first emitter layer to electrically connect the first base layer with the first electrode layer,
wherein in an orthogonal projection onto a plane parallel to the first main side, a contact area covered by an electrical contact of the first electrode layer with the first emitter layer and the emitter shorts includes areas in the shape of lanes in which no emitter shorts are arranged,
wherein the width of the lanes is at least two times the average distance between centers of emitter shorts next to each other in the contact area,
the lanes are curved, and in the orthogonal projection onto the plane parallel to the first main side, the lanes extend from an edge of the contact area adjacent to the second electrode layer in a direction away from the second electrode layer.

US Pat. No. 10,170,556

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device manufacturing method, comprising:preparing a semiconductor substrate of a first conductivity type;
forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate;
forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate;
forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction;
covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film;
after the covering the side wall of each of the first ditches, forming gate electrodes inside the first ditches and the second ditches;
forming a first semiconductor region of a second conductivity type different from the first conductivity type over a side wall of each of the first ditches; and
forming a source region of the first conductivity type in an upper surface portion of the semiconductor layer,
wherein, in the first ditches adjacently arranged in the first direction, distances between an upper surface of the grate electrodes and a bottom surface of the second insulating film are different.

US Pat. No. 10,170,555

INTERMETALLIC DOPING FILM WITH DIFFUSION IN SOURCE/DRAIN

Taiwan Semiconductor Manu...

1. A method comprising:etching a substrate to form a first semiconductor strip;
forming a first dummy gate structure over a first channel region of the first semiconductor strip, the first dummy gate structure being perpendicular to the first semiconductor strip;
etching a first recess in the first semiconductor strip on a first side of the first dummy gate structure;
etching a second recess in the first semiconductor strip on a second side of the first dummy gate structure;
forming a first intermetallic doping film in the first recess and the second recess;
diffusing a first dopant of the first intermetallic doping film into the first semiconductor strip proximate the first recess and into the first semiconductor strip proximate the second recess;
epitaxially growing a source/drain region in the first recess; and
epitaxially growing a source/drain region in the second recess.

US Pat. No. 10,170,554

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a gate structure on a substrate, the gate structure comprising:
a gate dielectric layer, disposed on the substrate;
a raised source/drain region adjacent to the gate structure, the raised source/drain region comprising a tip region under the gate structure;
a channel region under gate dielectric layer of the gate structure; and
a protection layer, wherein:
the protection layer is interposed between the substrate and the raised source/drain region, and
an atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region, and the atom stacking arrangement of the protection layer is an amorphous state having a higher degree of lattice disorder than that of the substrate and the raised source/drain region, and the protection layer has a first end portion with the amorphous state formed between the tip region under the gate structure and the channel region under the gate dielectric layer.

US Pat. No. 10,170,552

CO-INTEGRATION OF SILICON AND SILICON-GERMANIUM CHANNELS FOR NANOSHEET DEVICES

INTERNATIONAL BUSINESS MA...

1. A method for forming nanosheet semiconductor devices, comprising:forming a first stack in a first device region comprising layers of a first channel material and layers of a sacrificial material;
forming a second stack in a second device region comprising layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material; and
etching away the sacrificial material using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner, wherein the liner protects the second channel material from the wet etch.

US Pat. No. 10,170,551

SIDEWALL IMAGE TRANSFER NANOSHEET

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a nanosheet stack on a substrate, the nanosheet stack comprising:
a sacrificial nanosheet layer on the substrate; and
a nanosheet layer on the sacrificial nanosheet layer;
an etch stop layer on the nanosheet stack;
a mandrel on the etch stop layer;
sidewalls adjacent to sidewalls of the mandrel; and
a fill layer on exposed portions of the etch stop layer.

US Pat. No. 10,170,550

STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming an alternating stack of disposable material portions and semiconductor material portions on a substrate;
forming a disposable gate structure straddling, and contacting sidewalls of, said alternating stack;
removing said disposable material portions selective to said semiconductor material portions and said disposable gate structure;
forming a first gate structure between each vertically neighboring pair among said semiconductor material portions, said first gate structure including a first gate dielectric and a first gate electrode;
forming a planarization dielectric layer around said disposable gate structure;
forming a gate cavity by removing said disposable gate structure selective to said planarization dielectric layer; and
forming a second gate structure within said gate cavity, said second gate structure including a second gate dielectric and a second gate electrode, wherein said forming the first gate structure comprises forming, after removing said disposable material portions, a first gate dielectric layer on surfaces of said semiconductor material portions, forming a first gate conductor layer on said first gate dielectric layer, anisotropically etching said first gate conductor layer and said first gate dielectric layer employing a combination of said disposable gate structure and said semiconductor material portions as an etch mask, and isotropically etching remaining portions of said first gate conductor layer and said first gate dielectric layer between said vertically neighboring pair among said semiconductor material portions.

US Pat. No. 10,170,549

STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET

Samsung Electronics Co., ...

1. A method for fabricating a nanosheet stack structure having one or more sub-stacks, the method comprising:growing an epitaxial crystalline initial stack of the one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are each kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing such that the non-sacrificial layers B and C remain metastable and without relaxation during processing, and wherein the sacrificial layer A is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A;
proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that hold the nanosheets in place after selective etch of the sacrificial layers; and
selectively removing sacrificial layers A from all non-sacrificial layers B and C, while the remaining layers B and C in the stack are held in place by the pillar structures, so that after removal of the sacrificial layers A, each of the sub-stacks contains the non-sacrificial layers B and C, the sacrificial layer A differing from the non-sacrificial layers B and C such that removal of the sacrificial layer A leaves the non-sacrificial layer B and the non-sacrificial layer C in all of the plurality of sub-stacks and such that no sub-stack includes the non-sacrificial layer B in the absence of the non-sacrificial layer C and no sub-stack includes the non-sacrificial layer C in the absence of the non-sacrificial layer B, the sacrificial layer A being at least three times as thick as the non-sacrificial layer B and as the non-sacrificial layer C.

US Pat. No. 10,170,548

INTEGRATED CAPACITORS WITH NANOSHEET TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:depositing alternating nanosheet layers and sacrificial layers onto a substrate;
simultaneously forming fins in a capacitor region and fins in a device region, wherein the fins in the capacitor region have a greater width than the fins in the device region;
selectively etching the sacrificial layers to form an undercut in the capacitor region and complete removal in the device region;
doping the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region;
depositing a high k dielectric layer onto the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region, and on the nanosheet layers in the device region; and
forming top and bottom electrodes in the capacitor region.

US Pat. No. 10,170,545

MEMORY ARRAYS

Micron Technology, Inc., ...

1. A memory array, comprising:a semiconductor substrate;
a trench extending into the substrate and proximate a transistor, the trench comprising an upper portion over a lower portion;
a liner along an interior wall of the lower and upper portions of the trench, the liner comprising a transition configuration between the lower and upper portions of the trench, the transition configuration comprising a curved configuration and the liner comprising the only transition configuration for the lower and upper portions of the trench; and
an electrically insulative material in the lower and upper portions of the trench.

US Pat. No. 10,170,543

VERTICAL FIN FIELD EFFECT TRANSISTOR WITH AIR GAP SPACERS

International Business Ma...

1. A method of forming a fin field effect transistor device with air gaps, comprising:forming a vertical fin on a substrate;
forming an inner protective cap on the vertical fin;
forming an outer protective cap on the inner protective cap;
forming a source/drain layer in contact with the vertical fin;
forming a sacrificial bottom spacer on each side of the vertical fin, and on the source/drain layer; and
forming a spacer cap layer on the sacrificial bottom spacer.

US Pat. No. 10,170,541

SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF ELECTRODES AND SUPPORTERS

Samsung Electronics Co., ...

1. A semiconductor device comprising:a plurality of electrode structures on a substrate, the plurality of electrode structures having side surfaces; and
an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures, respectively, the upper supporter group including a plurality of upper supporters, at least some of the plurality of upper supporters each having an upper surface and a lower surface, the at least some of the plurality of upper supporters having a thickness between the upper surface and the lower surface, respectively,
wherein a first one of the upper surface and the lower surface has a curved profile, and a second one of the upper surface and lower surface has a flat profile, and
at least some of the plurality of upper supporters have the thickness that decreases towards the plurality of electrode structures.

US Pat. No. 10,170,540

CAPACITORS

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming separate wiring lines on a substrate, with spacing between adjacent separate wiring lines;
forming air gaps within the spacing by depositing capping material on the separate wiring lines and the spacing between the adjacent separate wiring lines;
forming a dielectric material over the capping material;
forming a trench in the dielectric material and over plural ones of the adjacent separate wiring lines, wherein the forming the trench opens the air gaps by removing a surface of the capping material; and
depositing conductive material within the opened air gaps through the trench.

US Pat. No. 10,170,539

STACKED CAPACITOR WITH ENHANCED CAPACITANCE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a first conductive layer over the semiconductor substrate;
a second conductive layer over the first conductive layer;
a dielectric layer between the first conductive layer and the second conductive layer;
a cap layer over the second conductive layer;
a first contact via through the cap layer, the second conductive layer and the dielectric layer, and electrically connected to the first conductive layer, wherein a bottom of the first contact via stops at an upper surface of the first conductive layer; and
a second contact via through the cap layer, and electrically connected to the second conductive layer, wherein a bottom of the second contact via stops at an upper surface of the second conductive layer.

US Pat. No. 10,170,537

CAPACITOR STRUCTURE COMPATIBLE WITH NANOWIRE CMOS

International Business Ma...

1. A method of forming an electrical device comprising:forming a stacked structure of at least a first semiconductor material layer and a second semiconductor material layer, wherein a material of the first and second semiconductor material layers have different oxidation rates;
oxidizing a sidewall of the stacked structure to form an oxide layer, wherein a first thickness of a first portion of the oxide layer that is present on the first semiconductor material layer is different from a second thickness of a second portion of the oxide layer that is present on the second semiconductor material layer;
removing the first or second portion of the oxide layer having a lesser thickness to provide an exposed surface of the stacked structure;
forming a replacement structure on a first portion of the stacked structure;
forming an epitaxial semiconductor material on the exposed surface of the stacked structure, wherein portions of the stacked structure having the epitaxial semiconductor material has a greater width than portions of the stacked structure not including the epitaxial semiconductor material;
forming an epitaxial crystalline semiconductor material on end portions of the stacked structure on opposing sides of the replacement structure;
forming a dielectric layer on exposed portions of the stacked structure having the epitaxial semiconductor material; and
forming a conductive material on the dielectric layer.

US Pat. No. 10,170,536

MAGNETIC MEMORY WITH METAL OXIDE ETCH STOP LAYER AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a first passivation layer over the substrate;
a second passivation layer over the first passivation layer;
a magnetic layer in the second passivation layer; and
an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer is in contact with the magnetic layer, and the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide.

US Pat. No. 10,170,535

ACTIVE-MATRIX TOUCHSCREEN

X-Celeprint Limited, Cor...

1. An active-matrix touchscreen having a touch area in which the active-matrix touchscreen is responsive to touches, the touchscreen comprising:a substrate;
a system controller;
a plurality of spatially separated independent touch elements disposed in a two-dimensional array within the touch area on and in contact with the substrate, each touch element comprising:
a mutual-capacitive touch sensor comprising at least two electrical conductors in a common layer on and in contact with the substrate, the two electrical conductors forming a capacitor; and
a touch controller circuit on and in contact with the substrate for providing one or more sensor-control signals to the touch sensor and for receiving a sense signal responsive to the one or more sensor-control signals from the touch sensor, wherein each touch sensor operates independently of any other touch sensor of the plurality of touch elements, wherein the two electrical conductors of each touch element are electrically separate from the two electrical conductors of any other touch element,
wherein the touch controller circuit of one or more of the plurality of spatially separated independent touch elements is disposed between the respective touch sensors of two or more of the plurality of spatially separated independent touch elements over the substrate.

US Pat. No. 10,170,534

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate;
a plurality of display elements in a display area of the substrate, wherein each of the plurality of display elements includes a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode;
a drive circuit on an outer side of the display area and including a thin film transistor;
a first insulating layer on the drive circuit;
a first power supply line layer on the first insulating layer and overlapping the drive circuit;
a second insulating layer on the first power supply line layer; and
a connection electrode layer on the second insulating layer, wherein the connection electrode layer electrically connects the first power supply line layer to the opposite electrode.

US Pat. No. 10,170,533

DISPLAY DEVICE, METHOD FOR DRIVING THE SAME, AND ELECTRONIC APPARATUS

SONY CORPORATION, Tokyo ...

1. A display device comprising:a pixel array unit having pixels arranged in a matrix, at least one of the pixels having an electro-optical element, a first capacitor, a second capacitor, a first transistor configured to supply a data signal from a data line to the first capacitor, and a second transistor configured to flow a drive current to the electro-optical element;
a data signal line extending in a first direction; and
a scan line extending in a second direction perpendicular to the first direction,
wherein,
the first capacitor has a first electrode and a second electrode overlapped with the first electrode partly,
the second capacitor has a third electrode and a fourth electrode overlapped with the third electrode partly,
the first electrode is disposed in a first layer,
the fourth electrode is disposed in a second layer which is different from the first layer, and the second layer is disposed over the first layer,
the first electrode is electrically connected to a control terminal of the second transistor,
the second electrode is electrically connected to a first current terminal of the second transistor,
the third electrode is electrically connected to an anode electrode of the electro-optical element, and
the second electrode and the third electrode are electrically connected.

US Pat. No. 10,170,532

EL DISPLAY PANEL, POWER SUPPLY LINE DRIVE APPARATUS, AND ELECTRONIC DEVICE

Sony Corporation, Tokyo ...

1. An electroluminescence display device comprising:a plurality of pixel circuits arranged in a matrix form having a column and a row; and
a peripheral circuit configured to drive the pixel circuits,
wherein the pixel circuits includes:
a first pixel circuit configured to drive a first electroluminescence element, and
a second pixel circuit adjacent to the first pixel circuit along a column direction and configured to drive a second electroluminescence element,
wherein the peripheral circuits includes:
a first buffer circuit including a first transistor and a second transistor serially connected between a first node and a second node, and configured to alternatively output a high potential and a low potential, to the first pixel circuit via a first extraction wire,
a second buffer circuit including a third transistor and a fourth transistor serially connected between a third node and a fourth node, and configured to alternatively output a high potential and a low potential, to the second pixel circuit via a second extraction wire,
a first line connected to the first node of the first buffer circuit and the third node the second buffer circuit, and
a second line connected to the second node of the first buffer circuit and the fourth node the second buffer circuit,
wherein the first line and the second line is disposed on an input side of first buffer circuit.

US Pat. No. 10,170,531

ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING REACTION BLOCKING MEMBER ON COMMON VOLTAGE LINE

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode display comprising:a substrate divided into a pixel area, and a peripheral area enclosing the pixel area;
an organic light emitting diode which is in the pixel area, and comprises a first electrode, an organic emission layer and a second electrode;
a switching element which is in the pixel area, and controls the organic light emitting diode;
a protective layer covering the switching element;
a pixel defining layer which defines the pixel area in which the organic light emitting diode is disposed;
a common voltage line which is in the peripheral area, and transmits a common voltage to the second electrode; and
a reaction blocking part which is in the peripheral area and overlaps the common voltage line, the reaction blocking part comprising a same material as the first electrode,
wherein in the peripheral area:
a side surface of the common voltage line which is furthest from the pixel area is exposed by each of the protective layer and the pixel defining layer, and
the reaction blocking part which comprises the same material as the first electrode overlaps an entirety of the exposed side surface of the common voltage line which is furthest from the pixel area.

US Pat. No. 10,170,530

DISPLAY DEVICE INCLUDING FIRST AND SECOND SUBSTRATES, ONE INCLUDING A PAD ELECTRODE

Japan Display Inc., Mina...

1. A display device comprising:a first substrate including an insulating substrate with a first through hole, a pad electrode positioned above the insulating substrate, and a signal line electrically connected to the pad electrode;
a second substrate opposed to the first substrate;
a sealant which adheres the first substrate and the second substrate;
a line substrate including a connection line and disposed below the insulating substrate; and
a conductive material which electrically connects the pad electrode and the connection line, wherein
the pad electrode and the first through hole overlap the sealant,
a first part of the first through hole does not overlap the pad electrode and overlaps the sealant, and a second part of the first through hole overlaps both of the pad electrode and the sealant, and
the sealant is less absorptive than is the insulating substrate as to a wavelength less than 350 nm.

US Pat. No. 10,170,529

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising the steps of:preparing a processed member, the processed member comprising:
an organic resin layer over a substrate; and
an element layer comprising a transistor over the organic resin layer;
irradiating the organic resin layer with a linear beam through the substrate by using a first apparatus, the first apparatus comprising:
a laser oscillator configured to emit a laser light;
an optical device configured to extend the laser light; and
a lens configured to condense the laser light into the linear beam; and
separating the organic resin layer from the substrate by using a separation apparatus after irradiating the organic resin layer with the linear beam,
wherein the separation apparatus comprises a roller, and
wherein the organic resin layer and the element layer are rolled up by the roller at the step of separating the organic resin layer from the substrate.

US Pat. No. 10,170,528

DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display panel comprising:a driver circuit;
a signal line electrically connected to the driver circuit; and
a pixel electrically connected to the signal line, the pixel comprising:
a first display element comprising a first conductive film;
a second conductive film comprising a region overlapping with the first conductive film;
an insulating film comprising a region between the first conductive film and the second conductive film;
a pixel circuit electrically connected to the second conductive film and the signal line, the pixel circuit comprising a first transistor comprising silicon in a channel formation region; and
a second display element electrically connected to the pixel circuit,
wherein the insulating film comprises a first opening,
wherein the first conductive film comprises a second opening,
wherein the second opening overlaps the second display element, and
wherein the second conductive film is electrically connected to the first conductive film in the first opening.

US Pat. No. 10,170,527

ORGANIC LIGHT EMITTING DIODE DISPLAY

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode display, comprising:a substrate including a pixel region and a peripheral region enclosing the pixel region;
a scan line on the substrate and transferring a scan signal;
a data line crossing the scan line and transferring a data voltage;
a switching transistor disposed in the pixel region and electrically connected to the scan line and the data line;
a driving transistor disposed in the pixel region and electrically connected to the switching transistor;
a pixel-area passivation layer disposed on the switching transistor and the driving transistor;
a pixel electrode disposed on the pixel-area passivation layer;
a pixel partition wall layer disposed on the pixel-area passivation layer and having a pixel opening overlapping the pixel electrode;
an organic light emission layer disposed in the pixel opening and disposed on the pixel electrode;
a common electrode disposed on the organic light emission layer and the pixel partition wall layer;
a common voltage line disposed in the peripheral region and electrically connected to the common electrode;
a peripheral passivation layer disposed in the peripheral region and contacting a side wall of the common voltage line;
a peripheral driving voltage line disposed in the peripheral region and which transfers a driving voltage ELVDD;
a driving voltage pad to which the driving voltage ELVDD is applied from the outside;
a driving voltage connecting part connecting the driving voltage pad and the peripheral driving voltage line,
wherein the driving voltage pad is disposed at the same layer as the common voltage line.

US Pat. No. 10,170,524

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:an input/output device comprising a display portion and a touch sensor, the input/output device having a first region, a second region adjacent to the first region, and a third region adjacent to the second region;
a member over the input/output device, the member having a first part and a second part;
a first fixing portion configured to fix an end of the first region of the input/output device and an end of the first part of the member;
a second fixing portion configured to fix an end of the third region of the input/output device; and
a roll-up portion connected to an end of the second part of the member and the second fixing portion,
wherein the second part of the member is located over the second region and the third region of the input/output device in an unfolded state,
wherein the roll-up portion is configured to roll up the second part of the member in a folded state, and
wherein the input/output device reversibly exists in the folded state and the unfolded state.

US Pat. No. 10,170,520

NEGATIVE-CAPACITANCE STEEP-SWITCH FIELD EFFECT TRANSISTOR WITH INTEGRATED BI-STABLE RESISTIVE SYSTEM

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a negative capacitance steep-switch transistor comprising:receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, a shallow trench isolation (STI) layer disposed upon the substrate, and an inter-layer dielectric disposed on the trench contact and the cap;
forming a source/drain recess in the inter-layer dielectric extending to the trench contact;
forming a gate recess in the inter-layer dielectric extending to the gate;
depositing a ferroelectric material within the gate recess;
forming a source/drain contact within the source/drain recess in contact with the trench contact;
forming a gate contact within the gate recess in contact with the ferroelectric material;
forming a contact recess in a portion of the source/drain contact;
depositing a bi-stable resistive system (BRS) material in the contact recess in contact with the portion of the source/drain contact; and
forming a metallization layer contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

US Pat. No. 10,170,519

MAGNETORESISTIVE ELEMENT AND MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A magnetoresistive element comprising:a first metal layer having a body-centered cubic structure;
a second metal layer having a hexagonal close-packed structure on the first metal layer;
a metal nitride layer on the second metal layer;
a first magnetic layer on the metal nitride layer;
an insulating layer on the first magnetic layer; and
a second magnetic layer on the insulating layer.

US Pat. No. 10,170,518

SELF-ASSEMBLED PATTERN PROCESS FOR FABRICATING MAGNETIC JUNCTIONS USABLE IN SPIN TRANSFER TORQUE APPLICATIONS

Samsung Electronics Co., ...

1. A method for providing a plurality of magnetic junctions on a substrate and usable in a magnetic device, the method comprising:providing a patterned seed layer, the patterned seed layer including a plurality of magnetic seed islands interspersed with an insulating matrix;
providing at least a portion of a magnetoresistive stack after the step of providing the patterned seed layer, the magnetoresistive stack including at least one magnetic segregating layer, the at least one magnetic segregating layer including at least one magnetic material and at least one insulator;
annealing the at least the portion of the magnetoresistive stack such that the at least one magnetic segregating layer segregates such that a plurality of portions of at least one magnetic material align with the plurality of magnetic seed islands and such that a plurality of portions of the at least one insulator align with the insulating matrix.

US Pat. No. 10,170,517

METHOD FOR FORMING IMAGE SENSOR DEVICE

Taiwan Semiconductor Manu...

1. A method for forming an image sensor device on a substrate, comprising:(a) recessing a portion of the substrate thereby forming a first shallow trench;
(b) forming a spacer layer surrounding at least part of a sidewall of the first shallow trench;
(c) forming a first deep trench that extends below the first shallow trench by further recessing the substrate while using the spacer layer as an intact mask thereby shrinking a width of the first deep trench;
(d) removing the spacer layer;
(e) forming a second oxide layer over the sidewall of the first shallow trench;
(f) forming a second liner layer in the substrate surrounding the first shallow trench; and
(g) filling the first shallow trench with a first isolation material thereby forming a first shallow trench isolation (STI) feature in the substrate.

US Pat. No. 10,170,515

IMPLANTATION PROCESS FOR SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other;
performing a first implantation process on the substrate from the first surface to form a first shallow implantation region in the substrate adjacent to the first surface;
forming a device on the first surface adjacent to the first shallow implantation region;
performing a thinning process on the second surface of the substrate; and
performing a second implantation process on the substrate from the second surface to form a first deep implantation region and a second deep implantation region in the substrate adjacent to the second surface, wherein the first deep implantation region is formed to adjoin the first shallow implantation region, the second implantation process is performed such that at least a portion of the second deep implantation region is separated from the first deep implantation region, and the second deep implantation region is formed to peripherally surround the first deep implantation region.

US Pat. No. 10,170,514

IMAGE SENSOR

CMOSIS BVBA, Antwerp (BE...

1. An image sensor comprising an array of pixels and control logic which is arranged to control operation of the pixels, each of the pixels comprising:a pinned photodiode;
a first sense node;
a second sense node;
a transfer gate connected between the pinned photodiode and the first sense node;
a first reset transistor connected between a voltage reference line and the second sense node;
a second reset transistor connected between the first sense node and the second sense node; and
a buffer amplifier having an input connected to the first sense node;the image sensor further comprising:a first reset control line connected between the control logic and the first reset transistor in each of a plurality of pixels of the array;
a second reset control line connected between the control logic and the second reset transistor in each of the plurality of pixels of the array;
wherein the control logic is arranged to selectively operate the pixels in a low conversion gain mode and in a high conversion gain mode and in each of the conversion gain modes the control logic is arranged to operate one of the first reset control line and the second reset control line to continuously switch on one of the first reset transistor and the second reset transistor during a readout period of an operational cycle of the pixels and;wherein, in each of the conversion gain modes the control logic is arranged to operate the first reset control line and the second reset control line such that the first reset transistor and the second reset transistor are switched on during a non-readout period of the operational cycle of the pixels;wherein for the low conversion gain mode;
the second reset transistor is switched on during a readout period, and the first reset control line is operated to switch on the first reset transistor to reset the first sense node and
for the high conversion pain mode;
the first reset transistor is switched on during a readout period, and the second reset control line is operated to switch on the second reset transistor to reset the first sense node.

US Pat. No. 10,170,512

UNIFORM-SIZE BONDING PATTERNS

Taiwan Semiconductor Manu...

15. A method comprising:forming an image sensor comprising:
depositing a first passivation layer over a first substrate, the first substrate having a plurality of photosensitive elements therein;
forming a first plurality of bonding pads in the first passivation layer, the first plurality of bonding pads having a first width and a first pitch; and
forming a second plurality of bonding pads in the first passivation layer, the second plurality of bonding pads having the first width, the second plurality of bonding pads being grouped into clusters, the second plurality of bonding pads having a second pitch between neighboring clusters and the first pitch between adjacent bonding pads in a first cluster, the first pitch being smaller than the second pitch;
forming a second substrate comprising:
forming a second passivation layer over a second substrate; and
forming a third plurality of hybrid bonding pads in the second passivation layer; and
bonding the second substrate is to the image sensor such that the first plurality of bonding pads and the second plurality of bonding pads are coupled with respective ones of the third plurality of bonding pads.

US Pat. No. 10,170,510

COLOR SEPARATION ELEMENT ARRAY, IMAGE SENSOR INCLUDING THE SAME, AND ELECTRONIC DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A color separation element array comprising:a transparent layer; and
a plurality of color separation elements provided in the transparent layer and configured to separate an incident light into a color light according to wavelength bands,
wherein the plurality of color separation elements comprise a first element having a first refractive index and a second element arranged in one side of the first element in a horizontal direction and having a second refractive index.

US Pat. No. 10,170,506

LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME

Shenzhen China Star Optoe...

1. A method for producing a low temperature poly-silicon (LTPS) array substrate, comprising:forming a gate of a thin-film transistor (TFT) on a substrate;
forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one in which an upper surface of the insulating layer is a plane;
exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer;
forming a source and a drain of the TFT on the polycrystalline silicon layer;
forming a pixel electrode on the insulating layer and a part of the drain;
forming a plain passivation layer on a source-drain electrode layer, which is fabricated from the source and the drain, and forming contact vias in the plain passivation layer for exposing surfaces of the gate and the drain, and the contact vias being disposed outside the polycrystalline silicon layer; and
forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is electrically connected to the gate via the contact via;
wherein before the insulating layer is formed on the substrate, a pre-operation is carried out to form a buffer layer on a portion of the substrate that is not covered by the gate such that an upper surface of the buffer layer and an upper surface of the gate collectively form a plane, and the pre-operation comprises the following steps:
forming the buffer layer and a negative photoresist layer on the substrate in sequence;
exposing one side of the substrate on the opposite side of the gate for removing a portion of the negative photoresist layer disposed right above the gate; and
removing the buffer layer disposed right above the gate such that a portion of the buffer layer is preserved on the portion of the substrate that is not covered by the gate; and
wherein the step of “exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer” comprises the following sub-steps:
exposing one side of the substrate on the opposite side of the gate for only preserving the first positive photoresist layer disposed on a first section disposed right above the gate;
injecting P-type impurity ions into the semiconductor layer outside the first section;
exposing one side of the substrate on the opposite side of the gate for forming the first positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; and
removing the first positive photoresist layer disposed on the second section.

US Pat. No. 10,170,505

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display apparatus comprising:a substrate comprising a display area and a peripheral area outside the display area;
a display unit over an upper surface of the substrate to correspond to the display area; and
a protective film comprising a protective film base and an adhesive layer, the protective film being attached to a lower surface of the substrate by the adhesive layer,
wherein the protective film base comprises a first protective film base corresponding at least to the display area, and a second protective film base having a physical property that is different from a physical property of the first protective film base and corresponding to at least a part of the peripheral area, and
wherein the second protective film base has a light transmittance that is greater than a light transmittance of the first protective film base.

US Pat. No. 10,170,504

MANUFACTURING METHOD OF TFT ARRAY SUBSTRATE, TFT ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A TFT array substrate, comprising a thin film transistor and a pixel electrode formed on a base substrate, the pixel electrode being electrically connected with a drain electrode of the thin film transistor,wherein
the array substrate further comprises a light-shielding pattern provided above the thin film transistor;
the array substrate further comprises: a passivation layer provided between the thin film transistor and the pixel electrode, and a passivation layer via hole penetrating the passivation layer;
the array substrate further comprises a light-shielding conductive metal layer formed of a same material as the light-shielding pattern, and an entirety of the light-shielding conductive metal layer is provided in the passivation layer via hole; and
the pixel electrode is electrically connected with the drain electrode of the thin film transistor through the light-shielding conductive metal layer.

US Pat. No. 10,170,503

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL PANEL

Wuhan China Star Optoelec...

1. A thin film transistor array substrate, comprising: a substrate, a silicon thin film transistor formed on the substrate, an oxide semiconductor transistor, and a capacitor; the silicon thin film transistor and the oxide semiconductor transistor having a top gate structure; the capacitor and the silicon thin film transistor or the capacitor and the oxide semiconductor transistor being overlapping arrangement;wherein, the thin film transistor array substrate comprises:
a polysilicon layer and a semiconductor oxide layer provided and spaced on the substrate;
a gate insulating layer covering the polysilicon layer and the semiconductor oxide layer;
a first gate, a first metal layer, and a second gate provided and spaced on the gate insulating layer, the first gate being provided on the polysilicon layer, the second gate being provided on the semiconductor oxide layer;
an etch stop layer covering the first gate, the first metal layer, and the second gate, the etch stop layer comprising a first insulating layer and a second insulating layer provided by stacking;
a source-drain metal layer provided on the etch stop layer, the source-drain metal layer comprising a first source, a first drain, a second source, and a second drain, the first source and the first drain being respectively contacted with the polysilicon layer, the second source and the second drain being respectively contacted with the semiconductor oxide layer;
wherein, the polysilicon layer, the gate insulating layer, the first gate, the etch stop layer, the first source, and the first drain form the silicon thin film transistor; the semiconductor oxide layer, the gate insulating layer, the second gate, the etch stop layer, the second source, and the second drain form the oxide semiconductor transistor;
wherein, the silicon thin film transistor further comprises a floating gate;
wherein, the floating gate is provided between the first insulating layer and the second insulating layer, the floating gate is located on the first gate;
wherein, the first gate and the second gate are formed using the same mask process.

US Pat. No. 10,170,502

TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A transistor array panel comprising:a substrate;
a buffer layer positioned on the substrate;
a semiconductor layer positioned on the buffer layer;
an intermediate insulating layer positioned on the semiconductor layer;
an upper conductive layer positioned on the intermediate insulating layer;
a lower conductive layer positioned between the substrate and the buffer layer,
wherein the semiconductor layer includes a first contact hole,
wherein the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole,
wherein the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole,
wherein the buffer layer comprises a third contact hole positioned over and exposing the lower conductive layer,
wherein the intermediate insulating layer comprises a fourth contact hole positioned in an overlapping relationship with the third contact hole,
wherein the lower conductive layer comprises a different material from a material of the semiconductor layer, and
wherein the upper conductive layer is in contact with an upper surface of the buffer layer in the fourth contact hole, and is in contact with an upper surface of the lower conductive layer in the third contact hole.

US Pat. No. 10,170,501

DISPLAY PANEL

INNOLUX CORPORATION, Mia...

1. A display panel, comprising:a substrate comprising a display region and a non-display region adjacent to the display region; and
a thin film transistor disposed on the non-display region of the substrate, wherein the thin film transistor comprises:
a semiconductor layer disposed over the substrate;
a first insulating layer disposed over the semiconductor layer;
a first metal layer disposed over the first insulating layer, and the first metal layer comprises a first branch portion and a second branch portion, wherein the first branch portion and the second branch portion are electrically connected to each other;
a second insulating layer disposed over the first insulating layer;
a plurality of first via holes and a plurality of second via holes penetrating through the first insulating layer and the second insulating layer, wherein the first branch portion and the second branch portion are disposed between the plurality of first via holes and the second via holes; and
a second metal layer disposed over the second insulating layer, wherein the second metal layer comprises a first portion electrically connected to the semiconductor layer through the plurality of first via holes and a second portion electrically connected to the semiconductor layer through the plurality of second via holes,
wherein a minimum distance between one of the first via holes and the first branch portion is a first distance, and a minimum distance between one of the second via holes and the second branch portion is a second distance, and the second distance is different from the first distance,
wherein the first metal layer serves as a gate electrode of the thin film transistor and the second metal layer serves as a source/drain electrode of the thin film transistor.

US Pat. No. 10,170,500

TRANSISTOR, LIQUID CRYSTAL DISPLAY DEVICE, AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display device comprising:a transistor comprising a gate electrode, a source electrode, a drain electrode, and a semiconductor layer;
a first wiring electrically connected to the gate electrode, the first wiring extending in a first direction;
a second wiring electrically connected to the source electrode, the second wiring extending in a second direction and intersecting the first wiring;
a pixel electrode electrically connected to the drain electrode; and
a capacitor wiring having a first part extending in parallel with the first direction, and second and third parts each extending in parallel with the second direction,
wherein the pixel electrode has a first edge portion overlapping with the first part of the capacitor wiring, a second edge portion overlapping with the second part of the capacitor wiring, and a third edge portion overlapping with the third part of the capacitor wiring,
wherein the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, and
wherein the semiconductor layer overlaps with an entirety of the pixel electrode.

US Pat. No. 10,170,499

FINFET DEVICE WITH ABRUPT JUNCTIONS

International Business Ma...

1. A method of forming a FinFET device comprising:providing a plurality of semiconductor fins on a surface of an insulator layer;
forming a plurality of gate structures orientated perpendicular to and straddling each semiconductor fin of said plurality of semiconductor fins;
providing a dielectric spacer on vertical sidewalls of each gate structure;
removing, entirely by an anisotropic etch, an entirety of each semiconductor fin and a portion of said insulator layer, not protected by said gate structures and said dielectric spacers, wherein said removing provides semiconductor fin portions located on pedestal insulator portions of said insulator layer;
forming a source-side doped semiconductor material portion on one exposed vertical sidewall of each semiconductor fin portion and a drain-side doped semiconductor portion on another exposed vertical sidewall of each semiconductor fin portion; and
diffusing, by annealing, a dopant from said source-side doped semiconductor material portion into each semiconductor fin portion to form a source region along an entirety of said one exposed vertical sidewall of each semiconductor fin portion, and a dopant from said drain-side doped semiconductor material portion into each semiconductor fin portion to form a drain region along an entirety of said another exposed vertical sidewall of each semiconductor fin portion, said source region and said drain region are laterally separated from each other by a channel region of said semiconductor fin portion, and wherein a first junction between the source region and the channel region has a first dopant concentration gradient of less than 6 nm per decade, and a second junction between the drain region and the channel region has a second dopant concentration gradient of less than 6 nm per decade.

US Pat. No. 10,170,498

STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

International Business Ma...

1. A method for fabricating a FinFET device comprising:providing a first long silicon fin for n-type FinFET devices and a first long silicon germanium fin for p-type FinFET devices on a strain relaxation buffer (SRB) substrate;
cutting the first long silicon fin forming a first and a second cut silicon fin, each of the first and second cut silicon fins having a vertical face at a fin end of the respective cut silicon fin, wherein the vertical faces of the first and second cut silicon fins are oriented facing each other;
cutting the first long silicon germanium fin forming a first and a second cut silicon germanium fins, each of the first and the second cut silicon germanium cut fin having a vertical face at a fin end of the respective cut silicon germanium fin, wherein the vertical faces of the first and second cut silicon germanium fins are oriented facing each other;
forming a tensile dielectric structure which bridges the vertical faces of the first and second cut silicon fins to maintain tensile strain in the first and second cut silicon fins; and
forming a compressive dielectric structure which bridges the vertical faces of the first and second cut silicon germanium fins to maintain compressive strain in the first and second cut silicon germanium fins.

US Pat. No. 10,170,497

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE AND METHOD FOR OPERATING AN ELECTRONIC DEVICE

1. A method for manufacturing an electronic device, the method comprising:providing a carrier comprising a hollow chamber structure within the carrier;
forming a first trench structure extending from a surface of the carrier to the hollow chamber structure such that an electrically isolated region is formed over the hollow chamber structure; and
forming at least one second trench structure extending from the surface of the carrier into a second region of the carrier, the second region of the carrier being laterally adjacent to the electrically isolated region, the second trench structure being at least a part of an electronic component provided in the second region of the carrier.

US Pat. No. 10,170,495

STACKED MEMORY DEVICE, OPTICAL PROXIMITY CORRECTION (OPC) VERIFYING METHOD, METHOD OF DESIGNING LAYOUT OF STACKED MEMORY DEVICE, AND METHOD OF MANUFACTURING STACKED MEMORY DEVICE

Samsung Electronics Co., ...

1. A method of manufacturing a stacked memory device, the method comprising:designing a layout of the stacked memory device, the layout including a first pattern;
calculating value of shift of the first pattern according to a first location of the first pattern in the layout;
obtaining a difference value between the first location of the first pattern and a second location of a second pattern formed through a first optical proximity correction (OPC) with respect to the first pattern;
determining, by a processor that executes software instructions, whether a second OPC is to be performed, based on the value of shift and the difference value;
when the processor determines that the second OPC is to be performed, forming a third pattern through the second OPC;
forming a mask, based on the second pattern or third pattern formed through the second OPC; and
forming the stacked memory device through a lithographic process using the mask.

US Pat. No. 10,170,494

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A stacked semiconductor memory device comprising:a stacked body comprising:
a plurality of underlying metal films comprising:
a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %,
a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or
a tungsten film;
a plurality of metal films provided on the underlying metal films and in contact with the underlying metal films, the metal films containing at least one of tungsten and molybdenum, and having a main orientation of (100) or (111); and
a plurality of insulator films,
wherein
the underlying metal films are provided between a lower surface of the metal films and the insulator films, and the underlying metal films are not provided on an upper surface of the metal-films, and
at least one of the plurality of insulator films contacts at least one of the plurality of underlying metal films and at least one the plurality of metal films.

US Pat. No. 10,170,493

ASSEMBLIES HAVING VERTICALLY-STACKED CONDUCTIVE STRUCTURES

Micron Technology, Inc., ...

1. An assembly, comprising:a stack of alternating first and second levels; the first levels comprising insulative material, and the second levels comprising conductive material; the assembly including channel material structures extending through the stack, and including insulative panel structures extending through the stack; the conductive material within the second levels having outer edges; the outer edges having proximal regions near the insulative panel structures and distal regions spaced from the insulative panel structures by the proximal regions; and
interface material along the outer edges of the conductive material, the interface material having a first composition along the proximal regions of the outer edges, and having a second composition along the distal regions of the outer edges; the first composition being different than the second composition.

US Pat. No. 10,170,492

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A memory device, comprising:a semiconductor substrate;
a first conductive layer, disposed on the semiconductor substrate;
a plurality insulating layers, disposed on the first conductive layer;
a plurality of second conductive layers, alternatively stacked with the insulating layers and insulated from the first conductive layer;
at least one contact plug comprising a first conductive material, passing through the insulating layers and the second conductive layers, insulated from the second conductive layers and electrically contacting to the first conductive layer; and
at least one dummy plug, formed in an opening passing through a bottommost layer of the insulating layers and the second conductive layers, corresponding to the at least one contact plug, wherein the at least one dummy plug comprises a dielectric isolation layer formed on a sidewall and a bottom of the opening and a second conductive material fully filling the opening and insulated from the second conductive layers and the first conductive layer.

US Pat. No. 10,170,491

MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER

Micron Technology, Inc., ...

1. A memory comprising:a vertical pillar coupled to a source; and
a dielectric etch stop tier over the source, the dielectric etch stop tier comprising a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the dielectric etch stop tier and separating the dielectric etch stop tier into multiple dielectric tiers.

US Pat. No. 10,170,490

MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS

Micron Technology, Inc., ...

1. An apparatus comprising:a piece of semiconductor material formed over a substrate;
a pillar extending through the piece of semiconductor material;
a select gate located along a first portion of the pillar;
memory cells located along a second portion of the pillar; and
transistors coupled to the select gate through a portion of the piece of semiconductor material, the transistors including sources and drains, the transistors including gates electrically uncoupled to each other, and at least a portion of the piece of semiconductor material forms the sources and drains of the transistors, and a portion of the select gate.

US Pat. No. 10,170,489

HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:first, second, third, and fourth high-voltage transistors arranged on a main surface of a semiconductor substrate, the first and second high-voltage transistors being adjacent each other in a gate-width direction, the third and fourth high-voltage transistors being adjacent each other in the gate-width direction, the first and third high-voltage transistors being adjacent each other in a gate-length direction, the second and fourth high-voltage transistors being adjacent each other in the gate-length direction, and each of the transistors having a gate electrode, and a gate electrode contact formed on the gate electrode; and
a conductive line provided on a portion of an element isolation region, the conductive line positioned between the first and third transistors and between the second and fourth transistors,
wherein the gate electrode contact is formed on a fringe portion formed by extending an end portion of the gate electrode onto the element isolation region in the gate-width direction.

US Pat. No. 10,170,488

NON-VOLATILE MEMORY OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANF...

1. A semiconductor device, comprising:a substrate having a surface;
a plurality of isolation structures disposed in the substrate to at least define a first region, a second region, and a third region on the substrate;
a floating gate memory cell disposed in the first region, wherein the floating gate memory cell comprises:
an erase gate structure disposed on the surface of the substrate;
a first floating gate structure and a second floating gate structure recessed in the substrate and located at two opposite sides of the erase gate structure;
a first word line disposed on the surface of the substrate, wherein the first word line is adjacent to the first floating gate structure opposite to the erase gate structure;
a common source disposed in the substrate between the first floating gate structure and the second floating gate structure;
a second word line disposed on the surface of the substrate, wherein the second word line is adjacent to the second floating gate structure opposite to the erase gate structure;
a first spacer disposed between the first floating gate structure and the first word line; and
a second spacer disposed between the second floating gate structure and the second word line;
a first device disposed in the second region; and
a second device disposed in the third region.

US Pat. No. 10,170,487

DEVICE HAVING AN INTER-LAYER VIA (ILV), AND METHOD OF MAKING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A three-dimensional integrated circuit comprising:a first transistor on a first level;
a word line coupled to the first transistor;
a first via coupled to the first transistor;
a second transistor on a second level different from the first level;
another word line coupled to the second transistor; and
a second via coupled between the first transistor and the second transistor.

US Pat. No. 10,170,486

SEMICONDUCTOR STORAGE DEVICE COMPRISING PERIPHERAL CIRCUIT, SHIELDING LAYER, AND MEMORY CELL ARRAY

Semiconductor Energy Labo...

1. A semiconductor storage device comprising:a first transistor;
a conductive film over the first transistor; and
a plurality of second transistors each comprising a channel region,
wherein a channel region of the first transistor comprises silicon,
wherein each of the plurality of channel regions of second transistors comprises an oxide semiconductor, and
wherein entirety of the plurality of second transistors overlaps with the conductive film.

US Pat. No. 10,170,485

THREE-DIMENSIONAL STACKED JUNCTIONLESS CHANNELS FOR DENSE SRAM

International Business Ma...

1. A method, comprising:forming a heteroepitaxial stack of layers of a p-doped material, an n-doped material, and a sacrificial material;
patterning the heteroepitaxial stack;
forming a dummy gate on the patterned heteroepitaxial stack;
forming sidewall spacers on the dummy gate;
removing the sacrificial material from between the layers of p-doped material and n-doped material;
depositing a dielectric isolation material adjacent the sidewall spacers and between the layers of p-doped material and n-doped material;
removing the dummy gate to form a gate opening;
removing the dielectric isolation material from between the layers of p-doped material and n-doped material;
depositing a gate dielectric on surfaces in the gate opening and on the layers of p-doped material and n-doped material under the gate opening;
depositing a workfunction metal on the gate dielectric;
filling the gate opening with a fill metal; and
forming contacts to the layers of p-doped material and n-doped material;
wherein the deposited gate dielectric on the layers of p-doped material and n-doped material and the deposited workfunction metal define junctionless field effect transistor devices.

US Pat. No. 10,170,483

SEMICONDUCTOR DEVICE, STATIC RANDOM ACCESS MEMORY CELL AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A static random access memory (SRAM) cell comprising:two pull-up (PU) transistors, two pass-gate (PG) transistors, and two pull-down (PD) transistors, wherein the PU transistors and the PD transistors are configured to form two cross-coupled inverters, the PG transistors are electrically connected to the cross-coupled inverters, and at least one of the PU transistors, the PG transistors, and the PD transistors comprises:
a semiconductor fin comprising at least one channel portion;
an epitaxy structure over the semiconductor fin;
at least one isolation structure adjacent to the semiconductor fin; and
a plurality of dielectric fin sidewall structures on opposite sides of the epitaxy structure and over the isolation structure.

US Pat. No. 10,170,481

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor memory device comprising:a substrate, wherein the substrate comprises a memory cell region and a periphery region;
a plurality of bit lines, disposed on the substrate, within the memory cell region;
a gate, disposed on the substrate, within the periphery region;
a spacer layer covering the bit lines and a sidewall of the gate; and
a first spacer disposed on the sidewall and an opposite sidewall of the gate and covering the spacer layer.

US Pat. No. 10,170,480

METHODS FOR MANUFACTURING A FIN-BASED SEMICONDUCTOR DEVICE INCLUDING A METAL GATE DIFFUSION BREAK STRUCTURE WITH A CONFORMAL DIELECTRIC LAYER

TAIWAN SEMICONDUCTOR MANU...

16. A method of forming a fin-like field-effect transistor (FinFET) device, the method comprising:forming a first active region and a second active region on a substrate, such that the first active region and the second active region are spaced apart from each other in a first direction;
forming a first group of fins in the first active region and a second group of fins in the second active region, such that each fin of the first and second groups of fins extends along a second direction substantially perpendicular to the first direction;
forming one or more gates over the first active region and the second active region along the first direction, the one or more gates including a first isolation gate and a functional gate;
forming a first sidewall spacer along the first isolation gate; and
forming a source/drain feature on a side of the first sidewall spacer and extending into the substrate to a first depth,
wherein the first isolation gate includes a dielectric layer and a metal gate layer, the first isolation gate formed in a trench in the substrate, the dielectric layer conformed to a side surface of the first sidewall spacer and extending along the first sidewall spacer and into the substrate such that the dielectric layer physically contacts the first sidewall spacer, the source/drain feature, and the substrate at a bottom of the trench, the metal gate layer extending into the substrate to a second depth that is greater than the first depth.

US Pat. No. 10,170,479

FABRICATION OF VERTICAL DOPED FINS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS

International Business Ma...

1. A complementary metal oxide semiconductor (CMOS) device with punch-through stops/wells, comprising:one or more vertical fin(s) on a substrate in a first region and one or more vertical fin(s) on the substrate in a second region, wherein the first region is adjacent to the second region;
a first dopant source on the one or more vertical fin(s) in the first region, wherein the first dopant source extends along a portion of the length of each of the one or more vertical fins in the first region;
a second dopant source on the one or more vertical fin(s) in the second region, wherein the second dopant source extends along a portion of the length of each of the one or more vertical fins in the second region;
a first doped region in the substrate forming a first punch-through stop/well below the first dopant source, wherein the first punch-through stop/well includes a first dopant at a concentration in the range of about 1×1017/cm3 to about 1×1019/cm3;
a second doped region in the substrate forming a second punch-through stop/well below the second dopant source, wherein the second punch-through stop/well includes a second dopant at a concentration in the range of about 1×1017/cm3 to about 1×1019/cm3;
an isolation spacer on the first dopant source and the second dopant source, wherein the thickness of the first dopant source and second dopant source are in the range of about 50 nm to about 150 nm; and
a gate dielectric layer on at least a portion of the isolation spacer, at least a portion of the one or more vertical fins) in the first region, and at least a portion of the one or more vertical fin(s) in the second region.

US Pat. No. 10,170,478

SPACER FOR DUAL EPI CMOS DEVICES

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor comprising:forming a first semiconductor device comprising two or more first gate stacks formed on a first substrate, and forming a second semiconductor device comprising two or more second gate stacks formed on the first substrate, the first semiconductor device including a first fin region having first source-drain areas and the second semiconductor device including a second fin region having second source-drain areas, the first source-drain area and the second source drain area each comprising a horizontal surface on an upper surface of the respective source-drain area:
depositing a wet-etch resistant spacer material on the first and second semiconductor devices;
removing a portion of the wet-etch resistant spacer material from the first fin region and the second fin region with anisotropic spacer reactive ion etch such that remaining portions of the wet-etch resistant spacer material form first wet-etch resistant spacers having a first thickness on the first semiconductor device and second wet-etch resistant spacers having a second thickness equal to the first thickness on the second semiconductor device;
depositing a first nitride liner on the first and second semiconductor devices;
depositing a dielectric layer on the first nitride liner;
planarizing the dielectric layer;
selectively removing the dielectric layer from between the first wet-etch resistant spacer material in the first fin region and the second wet-etch resistant spacer in the second fin region;
depositing a second nitride liner on the first and second semiconductor devices and selectively removing the second nitride liner from the first semiconductor device;
growing a first epitaxial layer on the first source-drain area by an epitaxial growth process such that the first epitaxial layer extends the length of the first source-drain area and covers the horizontal surface of the first source-drain area except areas covered by the first gate stack and the first wet-etch resistant spacer material;
depositing a third nitride liner on the first and second semiconductor devices and selectively removing the third nitride liner from the second semiconductor device; and
growing a second epitaxial layer on the second source-drain area by a second epitaxial growth process.

US Pat. No. 10,170,477

FORMING MOSFET STRUCTURES WITH WORK FUNCTION MODIFICATION

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first transistor of a first type comprising a first channel region material and a first gate electrode, the first gate electrode comprising gate materials including a work function material and a work function modifying material; and a second transistor of a second type comprising a second channel region material and a second gate electrode, the second gate electrode comprising gate materials including the work function material; wherein the work function modifying material is lanthanum oxide; the work function modifying material is applied to a dielectric layer; the work function material for the first and second gate electrodes are identical; and the work function modifying material is configured to change the threshold voltage of the first transistor; and an insulator layer between the first transistor and the second transistor, wherein a first portion of the insulator layer includes the work function material and a second portion of the insulator layer includes the work function material and the work function modifying material, wherein the first channel region and the second channel region extends through a horizontal insulator layer.

US Pat. No. 10,170,476

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY

INTERNATIONAL BUSINESS MA...

1. A method of manufacturing a semiconductor structure, comprising:forming an N-well in a p-type substrate;
forming a P-well in the substrate;
forming a PFET device on the N-well at a front side of the substrate;
forming an NFET device on the P-well at the front side of the substrate;
forming an isolation region at the front side of the substrate and contacting both the N-well and the P-well; and
forming a through wafer via (TWV) extending from a back side of the substrate to a bottom surface of the isolation region,
wherein the P-well is devoid of a substrate contact at the front side of the substrate; and
the N-well comprises an N-well contact at the front side of the substrate.

US Pat. No. 10,170,474

TWO DIMENSION MATERIAL FIN SIDEWALL

International Business Ma...

1. A semiconductor structure fabrication method comprising:forming neighboring fins associated with a semiconductor substrate, the neighboring fins separated by a fin well;
forming a fin cap upon each neighboring fin;
forming a well-plug within a bottom portion of the fin well such that sidewall portions of the neighboring fins are exposed to an upper portion of the fin well; and
forming a 2D material upon the sidewall portions of the neighboring fins.

US Pat. No. 10,170,472

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

16. An integrated circuit device, comprising:a substrate comprising adjacent first and second substrate regions;
active fins protruding from the substrate in the first and second substrate regions and extending parallel to one another in a first direction;
first and second gate electrodes extending co-linearly in a second direction that intersects the first direction, wherein the first and second gate electrodes are electrically isolated and extend on first and second active fins of the active fins in the first substrate region to define first and second transistors, respectively;
first and second wordlines extending in parallel on the first and second substrate regions; and
first and second wordline contacts connecting the first and second gate electrodes to the first and second wordlines, respectively,
wherein the first and second transistors in the first substrate region are between the first and second wordline contacts.

US Pat. No. 10,170,471

BULK FIN FORMATION WITH VERTICAL FIN SIDEWALL PROFILE

International Business Ma...

1. A semiconductor device, comprising:a base layer; and
a plurality of fins atop the base layer, wherein:
each fin comprises:
an undoped silicon oxide fin layer atop the base layer;
a doped silicon oxide fin layer atop the undoped silicon oxide fin layer;
a silicon fin layer atop the doped silicon oxide fin layer; and
a hard mask cap atop the silicon fin layer;
each fin has a uniform width along a height of the respective fin along a first direction;
the height spans from an upper surface of the base layer to an upper surface of the hard mask cap; and
the first direction is a direction that intersects a first fin and a second fin of the plurality of fins.

US Pat. No. 10,170,470

SWITCHING DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A switching device, comprising:a semiconductor substrate;
a plurality of gate trenches provided in an upper surface of the semiconductor substrate;
bottom insulating layers covering bottom surfaces of the gate trenches;
gate insulating layers covering side surfaces of the gate trenches; and
gate electrodes arranged in the gate trenches and insulated from the semiconductor substrate by the bottom insulating layers and the gate insulating layers,
wherein
a device region is a region in the upper surface in which the plurality of gate trenches is provided,
the device region includes a peripheral portion provided at a periphery of the device region and a center portion surrounded by the peripheral portion, the gate insulating layers being located in the peripheral portion and the center portion,
the gate insulating layers in the center portion have a first thickness and a first dielectric constant,
one or more of the gate insulating layers in the peripheral portion has, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant, and
the semiconductor substrate comprises:
a first region being of a first conductivity type and in contact with the gate insulating layers in the center portion and the peripheral portion;
a body region being of a second conductivity type and in contact with the gate insulating layers under the first region in the center portion and the peripheral portion; and
a second region being of the first conductivity type and in contact with the gate insulating layers under the body region in the center portion and the peripheral portion.

US Pat. No. 10,170,469

VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

International Business Ma...

1. A semiconductor structure comprising:a first vertical field-effect transistor comprising a first threshold voltage; and
at least a second vertical field-effect transistor comprising a second threshold voltage that is different from the first threshold voltage,
wherein each of the first vertical field-effect transistor and the second vertical field-effect transistor comprises
a source layer and a drain layer, wherein each drain layer is formed in a region of the first vertical field-effect transistor and second vertical field-effect transistor, respectively, above the source layer,
substrate in contact with the source layer,
a first spacer layer on the source layer,
a second spacer layer, where a portion of the drain layer extends over the second spacer, and
metal gate in contact with sidewalls of the epitaxially grown channel layer, a top surface of the first spacer layer, and a bottom surface of the second spacer layer.

US Pat. No. 10,170,467

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three dimensional (3D) semiconductor memory device, comprising:a semiconductor substrate, having a first protruding portion;
a first transistor formed in the semiconductor substrate, comprising:
a first source line, disposed in the semiconductor substrate and partially extending below the first protruding portion;
a first gate line configured to surround and cover the first protruding portion and electrically separated from the first source line and the first protruding portion; and
a first drain electrode formed on and connecting to the first protruding portion;
a plurality of conductive planes stacked on the semiconductor substrate and electrically separated from each other;
a first conductive pillar passing through the conductive planes and connecting to the first drain electrode;
a first memory layer disposed between the conductive planes and the first conductive pillar; and
a plurality of memory cells formed at a plurality points of intersection correspondingly formed between the conductive planes, the first conductive pillar and the memory layer; and connected in series by the first conductive pillar.

US Pat. No. 10,170,466

DEVICE HAVING AN ACTIVE CHANNEL REGION

HEWLETT-PACKARD DEVELOPME...

1. A transistor comprising:a substrate;
a drain in the substrate;
a source in the substrate;
a channel between the drain and the source, the channel surrounding the drain and having a channel length to width ratio; and
a gate over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

US Pat. No. 10,170,465

CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE

International Business Ma...

9. A method of forming a vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:forming a bottom spacer layer on a substrate;
forming a dummy gate layer on the bottom spacer layer;
forming a top spacer layer on the dummy gate layer;
forming one or more fin trenches, where at least one of the one or more fin trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a vertical fin in at least one of the one or more fin trenches;
forming one or more diode trenches, where at least one of the one or more diode trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a first semiconductor segment in a lower portion of at least one of the one or more diode trenches; and
forming a second semiconductor segment in an upper portion of the at least one of the one or more diode trenches with the first semiconductor segment, wherein the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

US Pat. No. 10,170,464

COMPOUND SEMICONDUCTOR DEVICES HAVING BURIED RESISTORS FORMED IN BUFFER LAYER

International Business Ma...

1. A semiconductor device, comprising:a semiconductor substrate;
a buffer layer disposed on the semiconductor substrate, wherein the buffer layer comprises a first buffer layer and a second buffer layer, wherein the first buffer layer comprises a first layer of epitaxial compound semiconductor material that is epitaxially grown on the semiconductor substrate, wherein the second buffer layer comprises a second layer of epitaxial compound semiconductor material that is epitaxially grown on the first buffer layer, wherein the first and second layers of epitaxial compound semiconductor material are formed of different compositions of compound semiconductor material;
an active device layer disposed on the buffer layer, wherein the active device layer comprises a layer of epitaxial semiconductor material that is epitaxially grown on the buffer layer;
a contact plug disposed within a contact opening formed in the second buffer layer; and
a buried resistor disposed within a cavity formed within the first buffer layer below the second buffer layer and the active device layer, wherein a portion of the cavity within the first buffer layer comprises an undercut region which undercuts a portion of the second buffer layer surrounding the contact plug within the contact opening formed in the second buffer layer such that a portion of the buried resistor within the undercut region of the cavity is disposed underneath a bottom surface of the second buffer layer;
wherein the contact plug is connected to the buried resistor;
wherein the buffer layer serves to match a lattice constant of the semiconductor substrate to a lattice constant of the layer of epitaxial semiconductor material of the active device layer.

US Pat. No. 10,170,463

BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

INTERNATIONAL BUSINESS MA...

1. A method for fabricating two transistors, comprising:forming a first semiconductor fin and a second semiconductor fin, where each of the first and second semiconductor fins comprises a doped lower portion;
forming lower spacers around the first and second semiconductor fins, the lower spacer around the first semiconductor fin having a height lower than a height of the lower spacer around the second semiconductor fin;
forming a gate stack around the first semiconductor fin and the second semiconductor fin;
wherein the height of the lower spacer around the first semiconductor fin rises below a level of the doped lower portion of the first semiconductor fin and wherein the height of the lower spacer around the second semiconductor fin rises above a level of the doped lower portion of the second semiconductor fin;
forming an upper spacer around the first and second semiconductor fin and over the gate stacks;
etching away the gate stack around the second semiconductor fin; and
forming an extrinsic base around the second semiconductor fin and under the upper spacer in a region exposed by etching away the gate stack.

US Pat. No. 10,170,462

DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising a display panel including an active area where an image is displayed and a pad area corresponding to a non-display area, the display device comprising:a first substrate and a second substrate, which face each other;
an organic light emitting diode arranged on the first substrate in the active area;
a signal pad arranged on the first substrate in the pad area;
a connection electrode connected with one side of the signal pad; and
a flexible circuit film connected with the connection electrode,
wherein the signal pad includes a plurality of lines arranged by interposing an insulating film therebetween, and the plurality of lines are electrically connected with each other, and
wherein the signal pad includes at least two lines of a first line arranged on the same layer as a gate line arranged in the active area, a second line arranged on the same layer as a data line arranged in the active area, and a third line arranged on the same layer as a pixel electrode arranged in the active area.

US Pat. No. 10,170,461

ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

Taiwan Semiconductor Manu...

1. A method of testing a semiconductor device, the semiconductor device comprising:a semiconductor substrate;
a interconnect structure disposed over the semiconductor substrate;
a first conductive pad disposed over the interconnect structure;
a second conductive pad disposed over the interconnect structure and spaced apart from the first conductive pad;
a third conductive pad disposed over the interconnect structure and spaced apart from the first and second conductive pads;
a fourth conductive pad disposed over the interconnect structure and spaced apart from the first, second, and third conductive pads;
a first ESD protection element, including a first fuse, electrically coupled between the first and second conductive pads;
a second ESD protection element, including a second fuse, electrically coupled between the third and fourth conductive pads;
a first device under test (DUT) electrically coupled between the first and third conductive pads; and
a second DUT electrically coupled between the second and fourth conductive pads;
the method comprising:
subjecting the semiconductor device to an electrostatic discharge (ESD) prone environment during manufacturing or testing of the semiconductor device;
after subjecting the semiconductor device to the ESD prone environment, blowing away the first fuse and blowing away the second fuse; and
after blowing away the first and second fuses, conducting an electro-migration test by applying electrical stress to the first DUT or to the second DUT.

US Pat. No. 10,170,460

VOLTAGE BALANCED STACKED CLAMP

International Business Ma...

1. An apparatus for balancing voltages, comprising:a voltage supply pin operatively connected to a voltage divider, wherein the voltage supply pin supplies a total voltage to the voltage divider;
a stacked circuit operatively connected to the voltage divider, wherein the stacked circuit comprises a first layer and a second layer, wherein the first layer is not coupled to the second layer, and the voltage divider distributes the total voltage as to the stacked circuit;
a voltage grounder operatively connected to the voltage divider and wherein the first layer and the second layer comprise:
a group of inverters within the first layer operatively connected to a first n-type channel field effect transistor (NFET), wherein the group of inverters within the first layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the first n-type channel field effect transistor (NFET); and
a group of inverters within the second layer operatively connected to a second n-type channel field effect transistor (NFET), wherein the group of inverters within the second layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the second n-type channel field effect transistor (NFET); and
a third node, wherein the third node is point (principal nodes or junctions) coupled to a first p-type field effect transistor (PFET) at a gate terminal of the first PFET, the second inverter, and the third inverter of the first layer.

US Pat. No. 10,170,457

COWOS STRUCTURES AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:attaching a first die and a second die to an interposer;
attaching a first substrate to a first surface of the first die and a first surface of the second die, the first substrate comprising silicon, the first surface of the first die being opposite to a second surface of the first die that is attached to the interposer, and the first surface of the second die being opposite to a second surface of the second die that is attached to the interposer;
forming a plurality of electrical connectors over the interposer, each electrical connector of the plurality of electrical connectors being electrically connected to a respective through via of a plurality of through vias comprised in the interposer, wherein the first substrate physically supports the interposer during the forming of the plurality of electrical connectors;
bonding the interposer to a second substrate using the plurality of electrical connectors; and
attaching a heat dissipation lid to the second substrate, the interposer being disposed in an inner cavity of the heat dissipation lid.

US Pat. No. 10,170,456

SEMICONDUCTOR PACKAGES INCLUDING HEAT TRANSFERRING BLOCKS AND METHODS OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer and laterally spaced apart from each other;
a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer;
an encapsulant filling spaces between the heat transferring block and the first and second semiconductor chips and covering sidewalls of the first and second semiconductor chips; and
a heat dissipation layer connected to a top surface of the heat transferring block opposite to the interconnection layer and extending to cover a top surface of the encapsulant,
wherein the heat transferring block emits heat trapped in a region of the encapsulant between the first and second semiconductor chips,
wherein the heat transferring block comprises a through via to emit the heat, and
the through via is electrically isolated from the interconnection layer and the first and second semiconductor chips.

US Pat. No. 10,170,454

METHOD AND APPARATUS FOR DIRECT TRANSFER OF SEMICONDUCTOR DEVICE DIE FROM A MAPPED WAFER

1. A system for performing a direct transfer of a plurality of semiconductor die from a first substrate to a second substrate, the system comprising:a first conveyance mechanism to convey the first substrate;
a second conveyance mechanism to convey the second substrate;
a transfer mechanism disposed adjacent to the first conveyance mechanism to effectuate the direct transfer;
a controller including one or more processors communicatively coupled with the first conveyance mechanism, the second conveyance mechanism, and the transfer mechanism, the controller having executable instructions, which when executed, cause the one or more processors to perform operations including:
determining positions of the plurality of semiconductor die based at least in part on map data, the map data describing the positions of the plurality of semiconductor die of a semiconductor wafer,
conveying at least one of the first substrate or the second substrate such that the first substrate, the second substrate, and the transfer mechanism are in a direct transfer position, and
activating the transfer mechanism to perform the direct transfer of the plurality of semiconductor die.

US Pat. No. 10,170,451

SEMICONDUCTOR DEVICE METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:encapsulating a semiconductor die, a first set of through vias, and a reference via with an encapsulant;
exposing the first set of through vias and the reference via with a planarization process on a first side of the semiconductor die;
connecting the first set of through vias on a second side of the semiconductor die opposite the first side to a second semiconductor die; and
after the connecting the first set of through vias, exposing a first surface of the reference via with a singulation process.

US Pat. No. 10,170,450

METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES

IMEC vzw, Leuven (BE)

1. A method for bonding and interconnecting a first IC device arranged on a first substrate to a second IC device arranged on a second substrate, wherein each IC device comprises a dielectric bonding layer at its outer surface, and wherein each IC device further comprises one or more metal contact structures, the method comprising:producing at least one cavity in the outer surface of the first IC device, the cavity traversing at least the dielectric bonding layer of the first IC device;
aligning the first substrate with respect to the second substrate, and forming a substrate assembly by direct bonding between the dielectric bonding layers, so that in the substrate assembly the cavity formed in the first IC device overlaps a metal contact structure of the second IC device;
after bonding, optionally thinning the first substrate;
producing a Through Substrate Via (TSV) opening in the first substrate, the TSV opening overlapping the cavity;
forming an aggregate opening comprising the TSV opening and the cavity, thereby exposing at least part of the metal contact structure of the second IC device;
after the formation of an isolation liner on at least part of the sidewalls of the aggregate opening, producing a metal interconnection plug in the aggregate opening, that contacts the metal contact structure of the second IC device, and forms at least part of an interconnection path between the metal contact structure of the second IC device and a metal contact structure of the first IC device, wherein the first IC device comprises a stack of dielectric layers with the dielectric bonding layer being present on top of the stack of dielectric layers, wherein the cavity further traverses one or more of the stack of dielectric layers, wherein the first IC device comprises a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion, and wherein the stack of dielectric layers comprises a stack of intermetal dielectric layers in the BEOL portion, or in the BEOL portion as well as in the FEOL portion of the first IC device.

US Pat. No. 10,170,449

DEFORMABLE CLOSED-LOOP MULTI-LAYERED MICROELECTRONIC DEVICE

International Business Ma...

1. A deformable closed-loop multi-layered microelectronic device comprising:a top layer comprising at least a first section and a second section, wherein the first section and the second section of the top layer are pivotable with respect to each other to deform the top layer;
a bottom layer comprising at least a first section and a second section, wherein the first section of the bottom layer is vertically aligned with the first section of the top layer and the second section of the bottom layer is vertically aligned with the second section of the top layer, wherein the first section and the second section of the bottom layer are pivotable with respect to each other to deform the bottom layer; and
a middle layer disposed between the top layer and the bottom layer, the middle layer comprising at least a first section and a second section, wherein the first section and the second section of the middle layer are pivotable with respect to each other to deform the middle layer,
wherein the middle layer comprises a first pivot provided to a first terminal end of the first section of the middle layer for allowing the first section to rotate about the first pivot, wherein the first terminal end of the first section of the middle layer is vertically sandwiched between a first terminal end of the first section of the top layer and a first terminal end of the first section of the bottom layer; and
wherein the first pivot is connected to the first terminal end of the first section of the bottom layer through a first adhesive and connected to the first terminal end of the first section of the top layer through a second adhesive, such that the first section of the bottom layer and the first section of the top layer are pivotable in a substantially synchronized manner to deform the bottom layer and the top layer in a substantially synchronized manner.

US Pat. No. 10,170,448

APPARATUS AND METHOD OF POWER TRANSMISSION SENSING FOR STACKED DEVICES

Micron Technology, Inc., ...

1. An apparatus comprising:a substrate;
a plurality of dies, each die of the plurality of dies comprising:
a circuit;
a first conductive via through each die, configured to provide a power supply voltage;
an on-die bus coupled to the first conductive via and configured to provide the power supply voltage from the first conductive via to the circuit;
a second conductive via through each die; and
a switch disposed between the on-die bus and the second conductive via, configured to selectively couple the on-die bus to the second conductive via,
a first conductive path across the substrate and the plurality of dies, configured to provide the power supply voltage to the first conductive via, the first conductive path comprising:
a first bump between the substrate and the plurality of dies, coupled to a corresponding first conductive via of a die of the plurality of dies adjacent to the substrate and the first bump configured to provide the power supply voltage to the corresponding first conductive via;
a plurality of the first pillars configured to couple the first conductive vias of adjacent dies of the plurality of dies to each other; and
the plurality of first conductive vias; and
a second conductive path across the substrate and the plurality of dies, the second conductive path comprising:
a second bump between the substrate and the plurality of dies, coupled to a corresponding second conductive via of the die of the plurality of dies adjacent to the substrate;
a plurality of second pillars configured to couple the second conductive vias of adjacent dies of the plurality of dies to each other; and
the plurality of the second conductive vias.

US Pat. No. 10,170,447

ADVANCED CHIP TO WAFER STACKING

International Business Ma...

1. A method of forming a 3D chip stack comprising:forming a first bonding layer on a top surface of a first wafer, the first wafer comprising first chips having an upper surface coplanar with the top surface of the first wafer;
forming a second bonding layer on a top surface of a second wafer, the second wafer comprising second chips having an upper surface coplanar with the top surface of the second wafer;
separating the second chips from the second wafer;
placing the separated second chips in loading bays of a vacuum chuck, wherein a location of each of the loading bays is in a corresponding position to each of the first chips on the first wafer, the separated second chips are held in the loading bays using vacuum suction to a surface of the separated second chips opposite the second bonding layer, and each loading bay of the vacuum chuck comprises a plurality of moveable columns together providing a curved contact surface to hold the separated second chips;
bonding the second chips to the first chips by contacting the second bonding layer to the first bonding layer and using a bonding process creating a third bonding layer, wherein the third bonding layer includes the first bonding layer and the second bonding layer; and
depositing a dielectric over the bonded first chips and second chips.

US Pat. No. 10,170,446

STRUCTURES AND METHODS TO ENABLE A FULL INTERMETALLIC INTERCONNECT

INTERNATIONAL BUSINESS MA...

1. A method forming an interconnect structure, the method comprising:depositing a first solder bump on a chip;
depositing a second solder bump on a laminate, the second solder bump comprising a nickel copper colloid;
joining the chip to the laminate;
depositing an underfill material around the first solder bump and the second solder bump; and
performing a reflow process at a temperature that is lower than a temperature used to join the chip to the laminate to convert the first solder bump and the second solder bump to an all intermetallic interconnect.

US Pat. No. 10,170,444

PACKAGES FOR SEMICONDUCTOR DEVICES, PACKAGED SEMICONDUCTOR DEVICES, AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A package for a semiconductor device, comprising:an integrated circuit die mounting region;
a molding material disposed around the integrated circuit die mounting region;
an interconnect structure disposed over the molding material and the integrated circuit die mounting region, the interconnect structure comprising a plurality of contact pads;
a connector coupled to each of the plurality of contact pads, wherein two or more connectors each comprises a first portion having a ball shape including a rounded top and sides and a second portion having a raised edge vertically further from a respective contact pad than the first portion, the second portion having vertical sidewalls and a planar top surface protruding from the rounded top of the first portion, wherein a material composition of the second portion has a same material composition as the first portion, wherein the first portion is in contact with a respective contact pad of the plurality of contact pads, wherein the second portion comprises an alignment feature, and wherein the first portion and second portion comprises a eutectic material; and
a raised insulating material layer disposed over at least one of the connectors having an alignment feature, the raised insulating material layer having a same shape as the alignment feature, the raised insulating material layer comprising an oxide of the material composition of the second portion.

US Pat. No. 10,170,443

DEBONDING CHIPS FROM WAFER

International Business Ma...

1. A debonding device comprising:a first member provided with a recess for receiving a carrier body, the carrier body including a first plate, a second plate, and a plurality of semiconductor chips, the semiconductor chips being sandwiched between the first plate and the second plate, the first plate being opposed to a bottom of the recess; and
a second member having a location figured to change with respect to the first member, wherein
the second member holds the second plate using a vacuum suction in a position; and
the first member is provided with an inlet to introduce gas into a gap between the first plate and the second plate.

US Pat. No. 10,170,441

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
an alignment mark adjacent to a surface of the substrate;
a plurality of pillars protruding from the substrate; and
a seal wall protruding from the surface of the substrate and surrounding the alignment mark, wherein the seal wall is between the plurality of pillars and the alignment mark, and the plurality of pillars are configured into at least two different groups wherein a group has an average height different from an average height of an another group.

US Pat. No. 10,170,440

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THEREOF

EPISTAR CORPORATION, Hsi...

1. A semiconductor device, comprising,a semiconductor die comprising a stacking structure, a first bonding pad with a flat top side in a cross-sectional view, positioned away from the stacking structure, and a second bonding pad, wherein a shortest distance between the first bonding pad and the second bonding pad is less than 150 microns;
a carrier comprising a connecting surface;
a third bonding pad and a fourth bonding pad on the connecting surface of the carrier; and
a conductive connecting layer comprising
a first conductive part formed between the first bonding pad and the third bonding pad, and comprising a first conductive material having a first shape with a width;
a second conductive part formed between the second bonding pad and the fourth bonding pad, and comprising the first conductive material; and
a blocking part covering the first conductive part and comprising a second conductive material having a second shape with a diameter less than the width in the cross-sectional view,
wherein the first shape has a height greater than the diameter, and
wherein the first conductive part fully covers the top flat side in the cross-sectional view.

US Pat. No. 10,170,435

GUARD RING STRUCTURE AND METHOD FOR FORMING THE SAME

MEDIATEK SINGAPORE PTE. L...

1. A method for forming a seal ring structure, comprising:providing a semiconductor substrate having a first doping region formed over a top portion thereof, wherein the semiconductor substrate has a first dopant type and the first doping region has the first dopant type or a second dopant type opposite to the first dopant type;
forming a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers comprises a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions and extending along a second direction perpendicular to the first direction;
performing an etching process to the first doping region using the patterned photoresist layers as an etching mask, removing the first doping region not covered by the patterned photoresist layers and forming a plurality of patterned first doping regions, wherein each of the patterned first doping regions comprises a plurality of parallel strip portions extending along the first direction and a plurality of bridge portions formed between the parallel strip portions and extending along the second direction perpendicular to the first direction;
removing the patterned photoresist layers;
forming an isolation region between and adjacent to the patterned first doping regions; and
forming a plurality of interconnect elements over the semiconductor substrate, respectively covering one of the patterned first doping regions thereunder.

US Pat. No. 10,170,434

WARPAGE CONTROL IN PACKAGE-ON-PACKAGE STRUCTURES

Taiwan Semiconductor Manu...

1. A package comprising:a bottom package comprising:
a package component; and
a device die over and bonded to the package component;
an adhesive layer over a top surface of the device die, wherein the adhesive layer comprises a slanted sidewall, a planar top surface, and a curved corner joining the slanted sidewall to the planar top surface;
a rigid plate over and contacting the planar top surface of the adhesive layer;
a molding compound, wherein at least a lower portion of the device die is in the molding compound; and
a top package bonded to the bottom package through solder regions penetrating through the molding compound.

US Pat. No. 10,170,433

INSULATED CIRCUIT BOARD, POWER MODULE AND POWER UNIT

Mitsubishi Electric Corpo...

1. An insulated circuit board comprising:an insulated substrate;
a first electrode formed on one main surface of the insulated substrate and having a polygonal shape in plan view; and
a second electrode formed on the other main surface opposite to the one main surface of the insulated substrate and having a polygonal shape in plan view,
a thin portion being formed in a corner portion, the corner portion being a region occupying, with regard to directions along outer edges from a vertex of at least one of the first and second electrodes in plan view, a portion of a length of the outer edges, so that the thin portion occupies only a portion of an entire length of the outer edges, the thin portion having a thickness smaller than a thickness of a region of the at least one of the first and second electrodes other than the thin portion,
the thin portion in the at least one of the first and second electrodes having a planar shape surrounded by first and second sides orthogonal to each other as portions of the outer edges from the vertex, and a curved portion away from the vertex of the first and second sides.

US Pat. No. 10,170,431

ELECTRONIC CIRCUIT PACKAGE

TDK CORPORATION, Tokyo (...

1. An electronic circuit package comprising:a substrate having a main surface, the main surface having a first region and a second region located on a same plane as the first region;
a first electronic component mounted on the first region;
a second electronic component mounted on the second region;
a mold resin that covers the main surface of the substrate so as to embed the first and second electronic components therein;
a magnetic film formed on the mold resin; and
a metal film formed on the mold resin, wherein the metal film covers the first electronic component with an intervention of the magnetic film while the metal film covers the second electronic component without an intervention of the magnetic film.

US Pat. No. 10,170,430

INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A method of fabricating an integrated fan-out package, the method comprising:attaching an integrated circuit component onto a carrier through a die attach film,
forming an insulating encapsulation on the carrier to laterally encapsulate the integrated circuit component and the die attach film, wherein an uplifted segment of the die attach film is lifted during forming the insulating encapsulation, and the uplifted segment raises toward sidewalls of the integrated circuit component; and
forming a redistribution circuit structure on the integrated circuit component and the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit component.

US Pat. No. 10,170,429

METHOD FOR FORMING PACKAGE STRUCTURE INCLUDING INTERMETALLIC COMPOUND

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a package structure, comprising:forming a first bump over a substrate;
placing an integrated circuit die comprising a second bump over the substrate, wherein the second bump is placed on the first bump;
reflowing the first bump and the second bump to form a solder joint and bond the integrated circuit die and the substrate together through the solder joint, wherein a first intermetallic compound is formed between the solder joint and the first bump, and a second intermetallic compound is formed between the solder joint and the second bump;
annealing the solder joint, the first bump and the second bump to react the solder joint with the first bump and the second bump until the first intermetallic compound and the second intermetallic compound become connected to each other; and
migrating a remaining portion of the solder joint to the first bump or the second bump during a high-temperature storage test or a temperature cycling test.

US Pat. No. 10,170,428

CAVITY GENERATION FOR EMBEDDED INTERCONNECT BRIDGES UTILIZING TEMPORARY STRUCTURES

Intel Corporation, Santa...

1. A method comprising:fabricating a package substrate;
placing at least one temporary structure in a first location on the package substrate;
subsequent to placing the at least one temporary structure in the first location on the package substrate, applying a first dielectric material to the package substrate, to surround at least a portion of the at least one temporary structure;
subsequent to applying the first dielectric material to the package substrate, removing the at least one temporary structure from the package substrate to generate a cavity in the package substrate, wherein a portion of the first dielectric material remains over the cavity subsequent to removing the temporary structure;
removing the portion of the first dielectric material from over the cavity;
subsequent to removing the portion of the first dielectric material from over the cavity, bonding an interconnect bridge in the cavity, the interconnect bridge including a plurality of interconnections;
applying a second dielectric material to the package substrate; and
installing a plurality of contacts to a surface of the package substrate, the plurality of contacts being coupled with the interconnect bridge.

US Pat. No. 10,170,427

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

7. A semiconductor device comprising:a gate stack over a semiconductor fin;
a source/drain region adjacent to the gate stack; and
a first contact to the source/drain region, wherein the first contact has a curved surface, the curved surface extending above a top surface of the gate stack.

US Pat. No. 10,170,426

MANUFACTURING METHOD OF WIRING STRUCTURE AND WIRING STRUCTURE

FUJITSU LIMITED, Kawasak...

1. A wiring structure, comprising:a first insulating film including a connection hole;
a second insulating film which is on the first insulating film and includes a wiring trench;
a first conductive material which fills an inside of the connection hole; and
a second conductive material which fills an inside of the wiring trench, wherein
the first conductive material is made of a first graphene layer which includes stacked plural graphenes formed in a direction along a bottom surface of the connection hole,
the second conductive material is made of a second graphene layer which includes stacked plural graphenes formed in a direction along a bottom surface of the wiring trench, and
the first graphene layer and the second graphene layer are directly connected to each other.

US Pat. No. 10,170,425

MICROSTRUCTURE OF METAL INTERCONNECT LAYER

INTERNATIONAL BUSINESS MA...

1. A method of forming a metal interconnect layer, the method comprising:forming an opening in a dielectric layer;
forming an embedded metal layer fully filled in the opening, wherein the embedded metal layer is in direct contact with a bottom surface of the dielectric layer;
forming an overburden layer over a top surface of the embedded metal layer and the dielectric layer;
disposing a metal passivation layer in direct contact with a surface of the overburden layer, the metal passivation layer comprising a metal selected only from a group of: cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), nickel (Ni), tungsten (W), any alloy including only Co, Ru, Ti, or W thereof, nitrides of only Co, Ru, Ti, Ni, or W, and any combination thereof;
performing an anneal at a temperature exceeding 100 degrees centigrade and below 300 degrees centigrade; and
performing a chemical-mechanical planarization (CMP) to remove the metal passivation layer and the overburden layer.

US Pat. No. 10,170,424

COBALT FIRST LAYER ADVANCED METALLIZATION FOR INTERCONNECTS

International Business Ma...

1. A method for fabricating an advanced metal conductor structure comprising:providing a pattern in a dielectric layer, wherein the pattern includes a set of features in the dielectric for a set of metal conductor structures and an adhesion promoting layer in the set of features;
depositing a ruthenium metal layer disposed on the adhesion promoting layer;
using a physical vapor deposition process to deposit a cobalt layer disposed on the ruthenium layer;
performing a thermal anneal which reflows the cobalt layer to fill a first portion of the set of features leaving a second, remaining portion of the set of features unfilled; and
depositing a second metal layer to fill the second, remaining portion of the set of features, wherein the second metal is a metal other than cobalt, wherein a thickness of the reflowed cobalt layer from the ruthenium layer to a bottom of the second metal layer and a thickness of the second metal layer after planarization are substantially equal.

US Pat. No. 10,170,423

METAL CAP INTEGRATION BY LOCAL ALLOYING

International Business Ma...

1. An interconnect structure, comprising:a dielectric layer having a top surface;
a plurality of open-ended trenches extending within the dielectric layer;
interconnects comprising copper within the open-ended trenches, a plurality of interconnects of the interconnect structure having top surfaces that are substantially coplanar with the top surface of the dielectric layer;
a plurality of metal alloy caps for preventing electromigration, each of the metal alloy caps being integral with one of the interconnects and comprising an alloy of copper and at least one of titanium, ruthenium and cobalt, wherein the metal alloy caps exhibit a stoichiometry of at least one part titanium, ruthenium or cobalt per one part of copper.

US Pat. No. 10,170,422

POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY

Taiwan Semiconductor Manu...

18. A method of forming an integrated chip, comprising:forming a plurality of gate structures extending in a second direction over an active area within a substrate;
forming a first middle-end-of-the-line (MEOL) structure and a second MEOL structure extending in the second direction over the active area and interleaved between the plurality of gate structures along a first direction perpendicular to the second direction, wherein the second MEOL structure extends a non-zero distance past the first MEOL structure along the second direction;
forming a first power rail extending in the first direction, wherein the first power rail is coupled to the second MEOL structure by a first conductive path comprising a conductive contact directly below the first power rail;
forming a first metal wire extending in the first direction over the first MEOL structure;
forming a metal strap coupled to the first metal wire; and
forming a second power rail extending in the first direction over the first power rail, wherein the second power rail is coupled to the first MEOL structure along a second conductive path comprising the first metal wire and the metal strap.

US Pat. No. 10,170,421

LOGIC SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A logic semiconductor device, comprising:a plurality of active patterns extending in a first direction and being spaced apart from each other in a second direction, the first and second directions being perpendicular to each other;
an isolation layer defining the active patterns;
a plurality of gate patterns extending in the second direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the first direction and at least one of the gate patterns being on the plurality of active patterns;
active contacts connected to upper portions of the active patterns adjacent to the gate patterns;
a plurality of sub-wirings integrally connected to the active contacts, the sub-wirings extending in the first direction; and
wirings extending in the second direction over the sub-wirings.

US Pat. No. 10,170,420

PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:a semiconductor substrate;
a first interconnect layer over the semiconductor substrate, the first interconnect layer comprising: a first dielectric material having a conductive body embedded therein, the conductive body comprising a first sidewall, a second sidewall, and a bottom surface, and a spacer element having a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body; and
a second interconnect layer overlying the first interconnect layer comprising a second dielectric material having at least one via therein, the at least one via filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer;
wherein a height of the spacer element is greater than a height of the conductive body.

US Pat. No. 10,170,419

BICONVEX LOW RESISTANCE METAL WIRE

International Business Ma...

1. A semiconductor structure comprising:a dielectric material layer having at least one opening located in said dielectric material layer, said at least one opening physically exposing a pair of curved sidewalls of said dielectric material layer and having a biconvex shape comprising a lower portion having a first width, a middle portion having a second width, and an upper portion having a third width, wherein the second width is greater than the first and third widths;
a diffusion barrier liner located in said at least one opening and contacting at least said pair of curved sidewalls of said dielectric material layer;
a reflow enhancement liner located on said diffusion barrier liner; and
a metallic region located on said reflow enhancement liner, said metallic region having a pair of curved outermost sidewalls, said biconvex shape and comprising a lower metallic region portion having a first metallic region width, a middle metallic region portion having a second metallic region width, and an upper metallic region portion having a third metallic region width, wherein the second metallic region width is greater than the first and third metallic region widths.

US Pat. No. 10,170,418

BACKSIDE DEVICE CONTACT

International Business Ma...

1. A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, the method comprising:forming a trench in the device layer;
forming a sacrificial plug in the trench;
removing the handle wafer to reveal the buried insulator layer;
partially removing the buried insulator layer to expose the sacrificial plug at a bottom of the trench;
removing the sacrificial plug;
performing backside processing of the buried insulator layer;
filling the trench with a conductor to form a contact plug;
coupling a final substrate to the buried insulator layer such that the contact plug contacts metallization of the final substrate.

US Pat. No. 10,170,417

SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a dielectric layer on the substrate and comprising a recess feature therein;
a metal layer in the recess feature, wherein the metal layer has an oxygen content less than about 0.1 atomic percent; and
a tungsten layer in the recess feature and in contact with the metal layer.

US Pat. No. 10,170,416

SELECTIVE BLOCKING BOUNDARY PLACEMENT FOR CIRCUIT LOCATIONS REQUIRING ELECTROMIGRATION SHORT-LENGTH

International Business Ma...

1. A semiconductor structure comprising:a first insulating layer deposited over a semiconductor substrate;
trenches formed by etching the first insulating layer, the trenches configured to receive copper (Cu) wiring, wherein the Cu wiring is selectively recessed in one or more of the trenches resulting in recessed Cu wiring regions and non-recessed Cu wiring regions, the recessed Cu wiring regions corresponding to circuit locations calling for electromigration (EM) short-length;
self-aligned conducting caps formed over the one or more trenches where the Cu wiring has been selectively recessed; and
a first via directly contacting a top surface of the Cu wiring in the non-recessed Cu wiring regions.