US Pat. No. 10,991,690

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, wherein the base comprises:
a substrate,
a fin protruding from the substrate, and
at least two channel laminates sequentially located on the fin, where each channel laminate of the at least two channel laminates comprises a sacrificial layer and a channel layer located on the sacrificial layer;
forming a gate structure across the channel laminates, wherein the gate structure covers a part of a top and a part of sidewalls of the channel laminates;
etching the channel laminates on two sides of the gate structure to form, in the channel laminates, a groove that exposes the fin and to remove a portion of the sacrificial layer, wherein:
after the groove is formed, a part of the channel layer is exposed on two sides of a remaining sacrificial layer below the gate structure;
the fin, the channel layer adjacent to the fin and the remaining sacrificial layer encircle a first trench;
adjacent channel layers and a remaining sacrificial layer between the channel layers encircle a second trench, wherein the quantity of the channel laminates is two, and along a direction perpendicular to sidewalls of the gate structure, a lateral depth of the second trench measured from an edge of the channel layer is greater than a lateral depth of the first trench measured from the edge of the channel layer, or the quantity of the channel laminates is greater than or equal to three, and along the direction perpendicular to the sidewalls of the gate structure, the lateral depth of the second trench is greater than the lateral depth of the first trench, and lateral depths of second trenches decrease gradually along a direction from a top of the gate structure to a bottom of the gate structure;
forming first spacers in the first trench and the second trench; and
forming a source-drain doping layer in the groove after forming the first spacers.

US Pat. No. 10,991,689

ADDITIONAL SPACER FOR SELF-ALIGNED CONTACT FOR ONLY HIGH VOLTAGE FINFETS

GLOBALFOUNDRIES U.S. INC....

1. An integrated circuit, comprising:a first region including a pair of first fin-type field effect transistors (FinFETs) on a substrate;
a second region including a pair of second FinFETs on the substrate, each of the first FinFETs and the second FinFETs including a metal gate having a first spacer extending linearly along each side of the metal gate, and wherein each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET;
a second spacer adjacent to a portion of each first spacer of the pair of first FinFETs and adjacent to an interlayer dielectric between the pair of first FinFETs;
a first contact extending between the metal gates of the pair of first FinFETs to a first source/drain region, the first contact completely surrounded by the second spacer such that the first contact is free of contact with the interlayer dielectric; and
a second contact extending between the metal gates of the pair of second FinFETs to a second source/drain region, the second contact in contact with the first spacer adjacent the metal gates of the pair of second FinFETs.

US Pat. No. 10,991,688

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a gate stack, disposed on a substrate, the gate stack comprises a gate dielectric layer and a gate electrode on the gate dielectric layer;
a first doped region having a first conductivity type, located in the substrate at a first side of the gate stack;
a second doped region having the first conductivity type, located in the substrate at a second side of the gate stack, wherein the first doped region and second doped region are not covered by the gate dielectric layer;
a first lightly doped region having the first conductivity type, located in the substrate between the gate stack and the first doped region;
a second lightly doped region having the first conductivity type, located in the substrate between the gate stack and the second doped region; and
a buried doped region having the first conductivity type, buried in the substrate below the first lightly doped region and the second lightly doped region, extended from the first doped region to the second doped region, and separated from the gate stack by a distance,
wherein the first conductivity type is n-type, and the buried doped region is in physical contact with the first doped region and the second doped region,
wherein the buried doped region is separated from the first lightly doped region and the second lightly doped region by p-type doped regions therebetween.

US Pat. No. 10,991,687

FINFET VARACTOR WITH LOW THRESHOLD VOLTAGE AND METHOD OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a FinFET varactor, the method comprising:performing a first implantation process with a first type dopant on a fin to form a first doped region in the fin, wherein the fin has a first portion disposed between a second portion and a third portion, and further wherein the first doped region spans the first portion of the fin, the second portion of the fin, and the third portion of the fin;
performing a second implantation process with a second type dopant on the fin to form a second doped region in the first doped region in the first portion of the fin, wherein the second type dopant is different than the first type dopant and the second doped region is disposed between a first sub-portion of the first doped region in the first portion of the fin and a second sub-portion of the first doped region in the first portion of the fin;
forming a gate structure over the first portion of the fin;
performing a third implantation process with the second type dopant on the fin to form a fourth doped region in the first doped region in the second portion of the fin and a fifth doped region in the first doped region in the third portion of the fin, wherein the first sub-portion of the first doped region in the first portion of the fin and the second doped region each extend between the fourth doped region and the fifth doped region; and
tuning the first implantation process and the second implantation process to achieve:
a first dopant concentration profile of the first type dopant having a first bell shape from the first sub-portion of the first doped region in the first portion of the fin to the second doped region to the second sub-portion of the first doped region in the first portion of the fin,
a second dopant concentration profile of the second type dopant having a second bell shape from the first sub-portion of the first doped region in the first portion of the fin to the second doped region to the second sub-portion of the first doped region in the first portion of the fin, and
the first bell shape is different than the second bell shape.

US Pat. No. 10,991,686

SUPER CMOS DEVICES ON A MICROELECTRONICS SYSTEM

SCHOTTKY LSI, INC., Moun...

1. A memory device, comprising:an array of memory cells having a first number of rows and a second number of columns, each memory cell being formed at a cross section of one of the first number of rows and one of the second number of columns;
a plurality of word interconnects and a plurality of bit interconnects, each bit interconnect electrically coupled to a respective column of memory cells, each word interconnect electrically coupled to a respective row of memory cells, wherein each memory cell includes a respective Schottky barrier diode (SBD) electrically coupled to and configured to be driven by a respective one of the plurality of word interconnects and a respective one of the plurality of bit interconnects;
a peripheral interface circuit including a plurality of address buffers, the peripheral interface circuit configured to address the memory cells in the array via the plurality of word interconnects and the plurality of bit interconnects; and
a sense amplifier coupled to one or more of the plurality of bit interconnects, the sense amplifier configured to read data stored in the array of memory cells;
wherein each of the plurality of bit interconnects is electrically coupled to the sense amplifier via a sense SBD having a cathode and an anode that are coupled to the respective bit interconnect and the sense amplifier, respectively.

US Pat. No. 10,991,685

ASSEMBLING OF CHIPS BY STACKING WITH ROTATION

INTERNATIONAL BUSINESS MA...

1. A method, comprising:preparing a plurality of chip layers, each comprising at least one chip block, each chip block comprising a plurality of electrodes assigned a same function;
sequentially stacking the plurality of the chip layers to form at least one stack of overlapping chip blocks, each stack holding a plurality of groups of vertically arranged electrodes with shifts in horizontal plane;
forming, for at least one of the plurality of groups, a through hole into the plurality of the chip layers to expose electrode surfaces of vertically arranged electrodes in the at least one of the plurality of groups; and
filling the through hole with conductive material.

US Pat. No. 10,991,684

3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED TO PROVIDE REDUNDANCY SITES

Micron Technology, Inc., ...

1. A circuit comprising:a first die; and
a second die,
wherein the first die and the second die are stacked,
wherein the circuit is partitioned into a plurality of columns that are perpendicular to each of the stacked dies,
wherein the circuit is configured to replicate data stored in a first column of the plurality of columns to a second column of the plurality of columns, and
wherein the second column is configured to store the data as a redundant site of the data.

US Pat. No. 10,991,683

METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT, AND OPTOELECTRONIC COMPONENT

OSRAM OLED GmbH, Regensb...

1. A method of manufacturing an optoelectronic component comprising:A) providing a substrate,
B) providing a metallic liquid arranged in a structured manner and in direct mechanical contact on the substrate and comprising at least one first metal,
C) providing semiconductor chips each having a metallic termination layer on their rear side, the metallic termination layer comprising at least one second metal different from the first metal, and
D) self-organized arranging the semiconductor chips on the metallic liquid so that the first metal and the second metal form at least one intermetallic compound having a higher re-melting temperature than the melting temperature of the metallic liquid, wherein the intermetallic compound is a connecting layer between the substrate and the semiconductor chips,
wherein the substrate has a plurality of landing areas each configured to accommodate a semiconductor chip,
the metallic liquid is arranged on all landing areas,
subsequently, at least part of the landing areas is covered with a covering layer so that the semiconductor chips arrange themselves in a self-organized manner exclusively on the uncovered landing areas, and
the covered landing areas remain free of the semiconductor chips.

US Pat. No. 10,991,682

ELECTRONIC DEVICE

InnoLux Corporation, Mia...

1. An electronic device, comprising:a substrate;
a first auxiliary electrode and a second auxiliary electrode formed on the substrate;
an organic layer formed on the first auxiliary electrode;
a plurality of thin film transistors formed on the organic layer; and
a plurality of electronic units electrically connected to the plurality of thin film transistors;
wherein the plurality of electronic units comprises a first electronic unit corresponding to a sub-pixel, a second electronic unit corresponding to another sub-pixel, the first auxiliary electrode and the second auxiliary electrode are electrically connected to the first electronic unit and the second electronic unit;
wherein the second auxiliary electrode is electrically insulate from the first auxiliary electrode.

US Pat. No. 10,991,681

THREE-DIMENSIONAL PACKAGE STRUCTURE

CYNTEC CO., LTD., Hsinch...

1. A method to form an electronic module, the method comprising:providing a substrate, wherein a plurality of electronic devices are disposed over the substrate;
forming a unitary packaging body to encapsulate the plurality of electronic devices and at least one portion of the substrate, wherein a first conductive element and a second conductive element are disposed on and in contact with the unitary packaging body; and
disposing an energy storage element over the unitary packaging body, wherein the energy storage element comprises a magnetic body and a coil disposed inside the magnetic body, wherein a first electrode and a second electrode of the energy storage element are disposed on the magnetic body, wherein the magnetic body is disposed over the unitary packaging body with the first electrode and the second electrode being electrically connected to and in contact with the first conductive element and the second conductive element disposed on the unitary packaging body, respectively.

US Pat. No. 10,991,680

COMMON SOURCE LAND GRID ARRAY PACKAGE

ALPHA AND OMEGA SEMICONDU...

1. A semiconductor package comprising:a land grid array substrate comprising
a first metal layer;
a second metal layer;
a third metal layer;
a plurality of vias; and
a resin enclosing the second metal layer;
a first vertical double-diffused metal-oxide semiconductor field-effect transistor (VDMOSFET) chip comprising a source electrode and a gate electrode located at a top surface of the first VDMOSFET chip and a drain electrode located at a bottom surface of the first VDMOSFET chip;
a second VDMOSFET chip comprising a source electrode and a gate electrode located at a top surface of the first VDMOSFET chip and a drain electrode located at a bottom surface of the first VDMOSFET chip; and
a molding encapsulation enclosing the first VDMOSFET chip and the second VDMOSFET chip;
wherein the second metal layer is between the first metal layer and the third metal layer;
wherein the first metal layer comprises a first metal pad, a second metal pad, a source pad, and a gate pad;
wherein the drain electrode of the first VDMOSFET chip is attached to the first metal pad of the first metal layer by a first conductive adhesive;
wherein the drain electrode of the second VDMOSFET chip is attached to the second metal pad of the first metal layer by a second conductive adhesive;
wherein the source electrode of the first VDMOSFET chip is electrically connected to the source pad of the first metal layer; and the gate electrode of the first VDMOSFET chip is connected to the gate pad of the first metal layer;
wherein the source electrode of the second VDMOSFET chip is electrically connected to the source pad of the first metal layer; and the gate electrode of the second VDMOSFET chip is electrically connected to the gate pad of the first metal layer; and
wherein the second metal layer comprises a first letter U shaped pad and a second letter U shaped pad.

US Pat. No. 10,991,678

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

LG Chem, Ltd.

1. A method for manufacturing a semiconductor device comprising the steps of:die-bonding a first semiconductor chip including a first die bonding film in the lower portion onto a substrate; and
die-bonding a second semiconductor chip containing a second die bonding film in the lower portion on the first semiconductor chip,
wherein the second die bonding film is die-bonded so as to mold a region not overlapping with a region of the first semiconductor chip in the lower region of the second semiconductor chip,
wherein the first semiconductor chip is disposed in a recess extending into the second die bonding layer, and the second die bonding layer comprises a continuous layer,
wherein the first die bonding layer and the second die bonding layer includes an adhesive layer containing an epoxy resin and a curing agent,
wherein the adhesive layer contained in the second die-bonding layer has a viscosity before curing of 3000 Pa·s or less at 130° C., and
wherein the adhesive layer contained in the second die-bonding layer includes a low-elastic, high-molecular weight resin that is blended with the epoxy resin, the low-elastic, high-molecular weight resin exhibiting viscoelasticity after formation of the crosslinked structure.

US Pat. No. 10,991,677

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...

1. A semiconductor package comprising:a first semiconductor chip including,
a plurality of first through-electrodes,
a plurality of first top contact pads being respectively connected to the plurality of first through-electrodes, and
a plurality of first bottom contact pads being respectively connected to the plurality of first through-electrodes;
a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip;
a plurality of first connection bumps on a bottom surface opposing the top surface of the first semiconductor chip, each of the plurality of first connection bumps including,
a first solder layer on a substrate,
a first diffusion barrier layer comprising nickel (Ni) and being on the first solder layer, and
a first pillar layer comprising copper (Cu), being on the first diffusion barrier layer, and contacting a first bottom contact pad of the plurality of first bottom contact pads; and
a plurality of second connection bumps between the top surface of the first semiconductor chip and a lowermost second semiconductor chip of the plurality of second semiconductor chips, the lowermost second semiconductor chip including,
a plurality of second through-electrodes, and
a plurality of second bottom contact pads being respectively connected to the plurality of second through-electrodes,
wherein each of the plurality of second connection bumps includes,
a second solder layer on a first top contact pad of the plurality of first top contact pads of the first semiconductor chip, and
a second pillar structure on the second solder layer and contacting a second bottom contact pad of the plurality of second bottom contact pads,
wherein the first pillar layer has a first width in a first direction parallel to the top surface of the first semiconductor chip, the first diffusion barrier layer has a second width in the first direction, and the second width is greater than the first width,
wherein the first width of the first pillar layer is in a range of 20 ?m and 40 ?m and the second width of the first diffusion barrier layer is in a range of 20 ?m and 45 ?m, and
wherein a first height of the plurality of first connection bumps between the first bottom contact pad of the first semiconductor chip and the substrate is in a range of 15 ?m and 60 ?m and is greater than a second height of the plurality of second connection bumps between the first top contact pad of the first semiconductor chip and the second bottom contact pad of the lowermost second semiconductor chip, the first height and the second height being measured in a second direction perpendicular to the first direction.

US Pat. No. 10,991,675

3D SEMICONDUCTOR DEVICE AND STRUCTURE

Monolithic 3D Inc., Klam...

1. A method to construct a 3D system, the method comprising:providing a base wafer; and then
transferring a first memory wafer on top of said base wafer; and then
thinning said first memory wafer; and then
transferring a second memory wafer on top of said first memory wafer; and then
thinning said second memory wafer; and
transferring a memory control on top of said second memory wafer; and then
thinning said memory control,
wherein said first memory wafer comprises a cut-layer, and
wherein said thinning of said first memory wafer comprises using said cut-layer to control the thickness of said first memory wafer.

US Pat. No. 10,991,674

ELECTRONIC ASSEMBLY AND ELECTRONIC SYSTEM WITH IMPEDANCE MATCHED INTERCONNECT STRUCTURES

1. An electronic assembly, comprising:an interconnect carrier comprising an electrically insulating core and at least two electrically conducting layers formed at the electrically insulating core;
a first integrated circuit chip mounted at a first side of the interconnect carrier;
a second integrated circuit chip mounted at a second side of the interconnect carrier, wherein the second side is opposite to the first side; and
an interconnection structure electrically connecting the first integrated circuit chip with the second integrated circuit chip;
wherein the electric interconnection structure extends around the insulating core and comprises at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided.

US Pat. No. 10,991,673

ELECTRONIC DEVICE

Kabushiki Kaisha Toshiba,...

1. An electronic device, comprising:two or more first chips, each first chip including a interconnect member; and
three or more chips including at least one second chip and at least one third chip, the second chip including a second conductive member, the third chip including a third conductive member,
the second conductive member of the second chip being electrically connected to the third conductive member of the third chip via the interconnect member of one first chip.

US Pat. No. 10,991,672

CU ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICE

NIPPON MICROMETAL CORPORA...

1. A Cu alloy bonding wire for a semiconductor device, wherein the total of abundance ratios of crystal orientations <110> and <111> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis to crystal orientations on a wire surface is 40% or more and 90% or less in average area percentage.

US Pat. No. 10,991,671

MULTI-PIECE WIRING SUBSTRATE, ELECTRONIC COMPONENT HOUSING PACKAGE, AND ELECTRONIC DEVICE

Kyocera Corporation, Kyo...

1. A multi-piece wiring substrate comprising:a matrix substrate comprising
a first main surface,
a second main surface opposite to the first main surface,
a third main surface disposed between the first main surface and the second main surface, the third main surface comprising a mount portion for mounting an electronic component, and a connection conductor for connecting to the electronic component,
an arrangement of a plurality of wiring substrate regions,
a margin region surrounding the plurality of wiring substrate regions, and
a dividing groove on the first main surface and the second main surface along a boundary between the wiring substrate regions and a boundary between the wiring substrate regions and the margin region;
a through-hole disposed across the boundary between the wiring substrate regions or the boundary between the wiring substrate regions and the margin region, and which penetrates from the first main surface to the second main surface; and
an external connection conductor at each corner of the wiring substrate regions on the second main surface, wherein
an auxiliary conductor is disposed around the through-hole on the third main surface, the auxiliary conductor comprises a wide conductor on a side connected to the connection conductor and a narrow conductor on a side not connected to the connection conductor, and the wide conductor is disposed across the boundary of the wiring substrate regions adjacent to each other.

US Pat. No. 10,991,669

SEMICONDUCTOR PACKAGE USING FLIP-CHIP TECHNOLOGY

MediaTek Inc., Hsin-Chu ...

1. A semiconductor package, comprising:a semiconductor device bonded to a base through a first conductive structure, wherein the semiconductor device comprises:
a carrier substrate comprising a base material and a first conductive trace;
a second conductive structure above the carrier substrate, wherein a portion of the second conductive structure is in direct contact with the first conductive trace and is below a portion of the base material;
a semiconductor die mounted above the first conductive trace, wherein a pad of the semiconductor die is connected to the second conductive structure and is wider than the first conductive trace; and
a molding compound surrounding the second conductive structure and in contact with the first conductive trace.

US Pat. No. 10,991,668

CONNECTION PAD CONFIGURATION OF SEMICONDUCTOR DEVICE

Synaptics Incorporated, ...

1. A semiconductor device comprising:a semiconductor substrate;
a bump; and
a connection pad connected to the bump and disposed between the semiconductor substrate and the bump, the connection pad having one or more slits,
wherein the one or more slits comprise a plurality of first slits arrayed in a longitudinal direction of the connection pad and wherein each of the plurality of first slits has first geometric centers positioned on a first straight line extending in the longitudinal direction.

US Pat. No. 10,991,667

ISOLATION STRUCTURE FOR BOND PAD STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:a semiconductor substrate having a back-side surface and a front-side surface opposite the back-side surface;
a bond pad extending through the semiconductor substrate;
a shallow trench isolation (STI) structure disposed along the front-side surface of the semiconductor substrate; and
a bond pad isolation structure disposed within the semiconductor substrate, wherein the bond pad isolation structure extends from the front-side surface to the back-side surface of the semiconductor substrate, wherein the bond pad isolation structure continuously extends around the bond pad, and wherein at least a portion of the STI structure is spaced laterally between opposing sidewalls of the bond pad isolation structure.

US Pat. No. 10,991,665

PACKAGE-LEVEL NOISE FILTERING FOR EMI RFI MITIGATION

Intel Corporation, Santa...

21. A method of forming a planar filtering circuit in a foundation layer, comprising:forming a seed layer over the foundation layer;
depositing a photoresist layer over the seed layer;
patterning the photoresist layer to form a plurality of inductor and capacitor openings through the photoresist layer;
depositing a conductive material into the plurality of inductor and capacitor openings to form an equivalent circuit of inductors and capacitors;
removing the photoresist layer; and
removing exposed portions of the seed layer.

US Pat. No. 10,991,664

INTEGRATED FUSE

STMicroelectronics (Rouss...

1. A semiconductor wafer, comprising:first zones containing integrated circuits, said first zones each having a substrate and at least one sealing ring at a periphery of the substrate, said at least one sealing ring formed at least in part by a conductive contact wall;
wherein the first zones are separated from each other by second zones defining cutting lines between first zones;
wherein at least one integrated circuit includes:
at least one electrically conductive fuse extending between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines adjacent to the integrated circuit, the at least one electrically conductive fuse passing through an opening in a bottom of the conductive contact wall of said at least one sealing ring and straddling said adjacent cutting line;
wherein a portion of the at least one electrically conductive fuse that passes through the opening in the bottom of the conductive contact wall of said at least one sealing ring is electrically isolated from said conductive contact wall of at least one sealing ring and from the substrate;
wherein a portion of the fuse straddling said adjacent cutting line is configured to be sliced, said at least one electrically conductive fuse changing from an electrical on state to an electrical off state upon slicing of the straddling portion caused by cutting along said adjacent cutting line.

US Pat. No. 10,991,662

ISOLATION CAVITIES IN SEMICONDUCTOR DEVICES

Skyworks Solutions, Inc.,...

1. A semiconductor device comprising:a transistor implemented over an oxide layer;
one or more electrical connections to the transistor;
one or more dielectric layers formed over at least a portion of the one or more electrical connections;
an electrical element disposed over the one or more dielectric layers, the electrical element being in electrical communication with the transistor via the one or more electrical connections;
a patterned form of sacrificial material covering at least a portion of the electrical element; and
an interface layer covering at least a portion of the one or more dielectric layers and the sacrificial material.

US Pat. No. 10,991,661

RADIO-FREQUENCY ISOLATION USING BACKSIDE CAVITIES

Skyworks Solutions, Inc.,...

1. A method for fabricating a semiconductor device, the method comprising:providing a transistor device formed over an oxide layer formed on a semiconductor substrate;
removing at least part of the semiconductor substrate;
applying an interface material below at least a portion of the oxide layer;
removing a portion of the interface material to form a trench; and
at least partially covering the interface material and the trench with a substrate layer to form a cavity.

US Pat. No. 10,991,660

SEMICONDUCTOR PACKAGE HAVING HIGH MECHANICAL STRENGTH

ALPHA ANC OMEGA SEMICONDU...

1. A semiconductor wafer comprising:a semiconductor substrate having a front surface and a back surface opposite the front surface of the semiconductor substrate;
a metal layer having a front surface and a back surface opposite the front surface of the metal layer, the front surface of the metal layer being directly attached to the back surface of the semiconductor substrate;
an adhesive layer having a front surface and a back surface opposite the front surface of the adhesive layer, the front surface of the adhesive layer being directly attached to the back surface of the metal layer;
a rigid supporting layer having a front surface and a back surface opposite the front surface of the rigid supporting layer, the front surface of the rigid supporting layer being directly attached to the back surface of the adhesive layer; and
a plurality of contact pads directly attached to the front surface of the semiconductor substrate;
wherein a thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate;
wherein the rigid supporting layer is stiffer than a tape material;
wherein the thickness of the semiconductor substrate is equal to or less than 50 microns;
wherein a majority portion of the semiconductor substrate is made of a silicon material;
wherein the thickness of the rigid supporting layer is in a range from 50 microns to 300 microns;
wherein a thickness of the metal layer is thinner than the thickness of the semiconductor substrate; and
wherein the thickness of the metal layer is in a range from 1 micron to 15 microns.

US Pat. No. 10,991,659

SUBSTRATE-LESS INTEGRATED COMPONENTS

Apple Inc., Cupertino, C...

1. A package comprising:a top surface, a bottom surface, and sidewalls;
a component encapsulated in a molding compound;
a routing substrate laterally adjacent to the component and encapsulated in the molding compound;
wherein the bottom surface comprises the molding compound, the component terminals and the routing substrate terminals; and
solder bumps directly on component terminals and the routing substrate terminals along the bottom surface.

US Pat. No. 10,991,658

ELECTRONIC ELEMENT MODULE AND METHOD FOR MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. An electronic element module, comprising:a substrate comprising ground wirings;
at least one electronic element mounted on a first surface of the substrate;
a sealing portion embedding the at least one electronic element therein and disposed on the substrate;
connection conductors partially disposed on side surfaces of the substrate and having lower ends connected to the ground wirings; and
a shielding portion disposed along the sealing portion, and connected to the connection conductors,
wherein the connection conductors are disposed between insulating layers of the substrate and the shielding portion.

US Pat. No. 10,991,657

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a semiconductor device, the method comprising:obtaining a pattern density of an integrated circuit (IC) design layout;
obtaining a pattern density of an alignment mark pattern of the IC design layout by calculating a ratio of a non-recessed area of the alignment mark pattern to a combination of a recessed area and the non-recessed area of the alignment mark pattern;
comparing the pattern density of the alignment mark pattern of the IC design layout with the pattern density of the IC design layout;
adjusting the pattern density of the alignment mark pattern of the IC design layout according to a result of the comparing; and
patterning a material layer according to the IC design layout after adjusting the pattern density of the alignment mark pattern.

US Pat. No. 10,991,656

SEMICONDUCTOR DEVICE PACKAGE

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a first substrate;
a second substrate disposed over the first substrate; and
a surface mount device (SMD) component disposed between the first substrate and the second substrate, wherein the SMD component comprises a plurality of connection electrodes electrically connecting the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from each other, and wherein the connection electrodes are spaced apart from the first substrate.

US Pat. No. 10,991,655

E-FUSE AND MANUFACTURING METHOD THEREOF, AND MEMORY CELL

SHENZHEN WEITONGBO TECHNO...

1. A method for manufacturing an e-fuse, comprising:providing a semiconductor substrate, the semiconductor substrate comprising a preset active region;
forming an isolating region on the semiconductor substrate, wherein the isolating region and the preset active region have a height difference and are connected by at least one side wall;
forming a negative electrode and a positive electrode on the preset active region; and
forming a fuse link on the side wall for connecting the negative electrode and the positive electrode.

US Pat. No. 10,991,653

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor substrate including a bulk layer;
a buried oxide layer provided on the bulk layer;
an inductor provided above a main surface side of the semiconductor substrate; and
a first ground shield which is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer,
wherein, in plan view of the semiconductor substrate, a region below the inductor includes:
a first region in which both the buried oxide layer and a surface single crystal layer are provided; and
a second region in which neither the buried oxide layer nor the surface single crystal layer is provided,
wherein the first ground shield is provided below the buried oxide layer in the first region, and
wherein the semiconductor device further includes a second ground shield which is an impurity region formed in the bulk layer in the second region.

US Pat. No. 10,991,652

ENERGY STORAGE INTERPOSER DEVICE WITH CONDUCTIVE NANOSTRUCTURES

1. An interposer device for electrically and mechanically interconnecting a first electrical circuit element and a second electrical circuit element, said interposer device having a first side to be electrically and mechanically connected to said first electrical circuit element, and a second side, opposite the first side, to be electrically and mechanically connected to said second electrical circuit element, wherein said interposer device comprises:a first conductor pattern on the first side of said interposer device, said first conductor pattern defining a portion of said interposer device to be covered by said first electrical circuit element when said first electrical circuit element is electrically and mechanically connected to said first conductor pattern;
a second conductor pattern on the second side of said interposer device to be electrically and mechanically connected to said second electrical circuit element, said second conductor pattern being electrically coupled to said first conductor pattern; and
at least one nanostructure energy storage device arranged within the portion of said interposer device to be covered by said first electrical circuit element, the at least one nanostructure energy storage device comprising:
at least a first plurality of conductive nanostructures;
a conduction controlling material embedding each conductive nanostructure in said first plurality of conductive nanostructures;
a first electrode connected to each conductive nanostructure in said first plurality of nano structures; and
a second electrode separated from each conductive nanostructure in said first plurality of conductive nanostructures by said conduction controlling material,
wherein at least one of said first electrode and said second electrode is connected to said first conductor pattern to allow electrical connection of said nanostructure energy storage device to said first electrical circuit element.

US Pat. No. 10,991,650

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a semiconductor element;
a conductive plate having a front surface on which the semiconductor element is mounted;
a sealing resin internally encapsulating at least the front surface of the conductive plate and the semiconductor element, the sealing resin being made of a hard resin; and
an external connection terminal having two ends, one of which is connected to the conductive plate and the other of which is entirely exposed outside the sealing resin, wherein
the external connection terminal has a buckling portion between the two ends, the buckling portion being entirely within the sealing resin for reducing stress to be applied to the conductive plate, the buckling portion having a single buckling point, and being constituted of an upper portion that is one side from the buckling point and a lower portion that is an other side from the buckling point, each of the upper and lower portions having a linear shape, the upper and lower portions forming a V shape, positions of the two ends of the external connection terminal overlapping when viewed from a direction orthogonal to a surface of the conductive plate.

US Pat. No. 10,991,648

REDISTRIBUTION LAYER STRUCTURE AND SEMICONDUCTOR PACKAGE

NANYA TECHNOLOGY CORPORAT...

7. A semiconductor package, comprising:a first die;
a second die;
a first RDL structure disposed on the first die; and
a second RDL structure disposed on the second die, wherein
the first RDL structure and the second RDL structure respectively comprise an RDL structure comprising:
a first pad, a second pad, a third pad, and a fourth pad separated from each other;
a first switch device comprising a first conductive layer and a second conductive layer separated from each other, wherein the first conductive layer is coupled to the first pad, and the second conductive layer is coupled to the third pad;
a second switch device comprising a third conductive layer and a fourth conductive layer separated from each other, wherein the third conductive layer is coupled to the first pad, and the fourth conductive layer is coupled to the fourth pad;
a third switch device comprising a fifth conductive layer and a sixth conductive layer separated from each other, wherein the fifth conductive layer is coupled to the second pad, and the sixth conductive layer is coupled to the third pad; and
a fourth switch device comprising a seventh conductive layer and an eighth conductive layer separated from each other, wherein the seventh conductive layer is coupled to the second pad, and the eighth conductive layer is coupled to the fourth pad, and
the first RDL structure and the second RDL structure are located between the first die and the second die and coupled to each other.

US Pat. No. 10,991,647

PRINTED CIRCUIT BOARD AND PACKAGE STRUCTURE HAVING THE SAME

Samsung Electro-Mechanics...

1. A printed circuit board comprising:an insulating material comprising a plurality of bump pads embedded in a first surface thereof;
a first insulating layer stacked on the first surface of the insulating material and comprising a plurality of opening portions corresponding to and exposing the plurality of bump pads; and
a second insulating layer stacked on the first insulating layer and comprising a first cavity exposing the plurality of opening portions.

US Pat. No. 10,991,646

FLEXIBLE CIRCUIT BOARD FOR DISPLAY

Silicon Works Co., Ltd., ...

1. A flexible circuit board for a display, comprising:a base film divided into a product region and a test connection region based on a cutting line;
integrated circuit contact pads arranged at one side of an integrated circuit region which is defined in the product region, and formed for electrical contact with an integrated circuit;
panel contact pads arranged between the integrated circuit contact pads and the cutting line, and formed for electrical contact with a display panel;
test pads formed in the test connection region;
connection patterns electrically connecting the integrated circuit contact pads and the panel contact pads, respectively, and divided into a first connection pattern, which is selected at least one among the connection patterns, and remaining connection patterns, which are not selected as the first connection pattern; and
extension patterns extending from the remaining connection patterns and electrically connected to the test pads, respectively,
wherein the extension patterns are formed integrally with the connection patterns, respectively, and have a width narrower than the connection patterns.

US Pat. No. 10,991,645

WIRING SUBSTRATE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:a substrate;
an oxide film including an oxide of one or both of titanium (Ti) and zirconium (Zr), the oxide film being formed on a surface of the substrate;
an alloy film including an alloy of one or any combination of nickel (Ni), cobalt (Co) and tungsten (W) with copper (Cu), the alloy film being formed on the oxide film; and
a Cu layer formed on the alloy film,
wherein the substrate, the oxide film, the alloy film, and the Cu layer are layered in this order.

US Pat. No. 10,991,641

CANTILEVERED LEADFRAME SUPPORT STRUCTURE FOR MAGNETIC WIRELESS TRANSFER BETWEEN INTEGRATED CIRCUIT DIES

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit package comprising:a first die attach pad and a second die attach pad, the first die attach pad including a first set of cantilevered fingers and the second die attach pad including a second set of cantilevered fingers, each of the first set of cantilevered fingers terminating at a first distal end and each of the second set of cantilevered fingers terminating at a second distal end;
a first die on the first die attach pad, the first die including a first portion on the first distal end, the first die including at least one coil; and
a second die on the second die attach pad, the second die including a second portion on the second distal end, the second die including at least one coil; wherein each of the first set of cantilevered fingers and each of the second set of cantilevered fingers include five fingers, wherein the distal ends of two fingers of each of the first set of cantilevered fingers and each of the second set of cantilevered fingers are opposite to each other, and wherein one finger extends in a space between the distal ends of the two fingers, wherein a distal end of the one finger is adjacent to an edge along a length of the first die or the second die respectively.

US Pat. No. 10,991,639

COMPLIANT PIN FIN HEAT SINK WITH BASE INTEGRAL PINS

International Business Ma...

1. A compliant pin fin heat sink comprising:a plurality of separate flexible base plates;
a plurality of elastomeric flow blockers joining the plurality of separate flexible base plates;
a plurality of pins extending from each of the flexible base plates and formed integral with each of the flexible base plates; and
a flexible top plate connected to and spaced from the flexible base plates, the plurality of pins disposed between the flexible base plates and the flexible top plate and the flexible base plates and flexible top plate having a thickness of from 0.2 mm to 0.5 mm;
wherein the compliant pin fin heat sink including the flexible top plate and the flexible base plates is flexible in an area of the compliant pin fin heat sink containing the plurality of pins to conform the compliant pin fin heat sink to contours of a contact surface under a load applied to the flexible top plate,
wherein the plurality of elastomeric flow blockers define flow channels that enclose the plurality of pins between the flexible base plates and the flexible top plate,
wherein each row of pins within each plurality of pins is offset from each adjacent row of pins within that plurality of pins.

US Pat. No. 10,991,629

METHOD OF FORMING PROTECTION LAYER IN FINFET DEVICE

Taiwan Semiconductor Manu...

1. A method for forming a fin-based transistor, comprising:forming a fin on a substrate;
overlaying at least an upper portion of the fin by an oxide layer and a protection layer, wherein the protection layer is formed above the oxide layer;
doping at least the upper portion of the fin by using an ion implantation process, wherein the protection layer protects against damage to at least the upper portion of the fin and the oxide layer during the ion implantation process;
forming a dummy gate stack overlaying respective central portions of the protection layer, the oxide layer, and the fin, wherein the central portions of the protection layer and the oxide layer serve as a gate dielectric layer of the fin-based transistor;
removing side portions of the protection layer and the oxide layer that are not overlaid by the dummy gate stack;
recessing side portions of the fin that are not overlaid by the dummy gate stack; and
forming source and drain features in the recessed side portions of the fin.

US Pat. No. 10,991,624

WAFER PROCESSING METHOD INCLUDING APPLYING A POLYOLEFIN SHEET TO A WAFER

DISCO CORPORATION, Tokyo...

1. A wafer processing method for dividing a wafer along a plurality of division lines to obtain a plurality of individual device chips, the division lines being formed on a front side of the wafer, the wafer processing method comprising:a preparing step of preparing a ring frame having an inside opening for accommodating the wafer;
a providing step of positioning the wafer in the inside opening of the ring frame and providing a polyolefin sheet having no adhesive layer on a back side of the wafer and on a back side of the ring frame, such that the polyolefin sheet is in direct contact with the back side of the wafer and the back side of the ring frame;
a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet after performing the polyolefin sheet providing step, thereby uniting the wafer and the ring frame through the polyolefin sheet by thermocompression bonding to form a frame unit in a condition where the front side of the wafer and a front side of the ring frame are exposed upward;
a dividing step of applying a laser beam to the wafer along each division line, the laser beam having an absorption wavelength to the wafer, after performing the uniting step, thereby forming a division groove in the wafer along each division line to divide the wafer into the individual device chips; and
a pickup step of cooling the polyolefin sheet in each region of the polyolefin sheet corresponding to each device chip, pushing up each device chip from the polyolefin sheet side to pick up each device chip from the polyolefin sheet after performing the dividing step.

US Pat. No. 10,991,623

WAFER PROCESSING METHOD

DISCO CORPORATION, Tokyo...

1. A wafer processing method for processing a wafer having a substrate and a device layer formed on a front side of the substrate, the device layer being partitioned by a plurality of crossing streets to thereby define a plurality of separate regions where a plurality of devices are respectively formed, the wafer processing method comprising:a mask forming step of forming a mask on a back side of the substrate, so as to form an etched groove along each street through a thickness of the substrate from the back side of the substrate to the front side of the substrate;
a plasma etching step of performing plasma etching from a back side of the wafer through the mask to the substrate after performing the mask forming step, thereby forming the etched groove in the substrate along each street so that the etched groove has a depth equal to the thickness of the substrate; and
a device layer dividing step of applying a laser beam to the device layer along each street from a front side of the wafer before performing the plasma etching step and the mask forming step, thereby forming a device layer dividing groove corresponding to the etched groove along each street and extending through a thickness of the dividing step from the front side of the water to the front side of the substrate,
wherein a width of the etched groove at the front side of the substrate is larger than a width of the device layer dividing groove at the front side of the substrate.

US Pat. No. 10,991,620

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

19. A semiconductor device, comprising:a plurality of gates extending in a first direction on a substrate, each gate of the plurality of gates including a gate insulation layer, a gate electrode, and a first spacer;
a plurality of first contact plugs contacting the substrate between adjacent ones of the plurality of gates, the plurality of first contact plugs being spaced apart from sidewalls of corresponding ones of the plurality of gates;
an insulation structure covering upper surfaces of the plurality of gates, the insulation structure including a liner pattern and an insulation pattern; and
a second contact plug through the insulation pattern and liner pattern under the insulation pattern, the second contact plug contacting an upper surface of a corresponding gate electrode between adjacent first contact plugs among the plurality of first contact plugs,
wherein the liner pattern has a U-shape having a recess, the insulation pattern filling the recess, and the liner pattern separating between the insulation pattern and the upper surfaces of the plurality of gates, and
wherein a width in a second direction perpendicular to the first direction of the insulation structure is greater than a width in the second direction of each of the plurality of gates.

US Pat. No. 10,991,619

TOP VIA PROCESS ACCOUNTING FOR MISALIGNMENT BY INCREASING RELIABILITY

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device to account for misalignment, comprising:forming a top via on a first conductive line formed on a substrate;
after forming the top via, forming a plurality of liners using a first dielectric material, including forming first and second liners to a first height along sidewalls of the top via;
forming a plurality of dielectric layers, including forming first and second dielectric layers on the first conductive line to the first height and adjacent to the first and second liners, respectively;
recessing the top via to a second height; and
forming an additional dielectric layer on the recessed top via to the first height using a second dielectric material, wherein the first and second dielectric materials are selected to compensate for potential misalignment between the first conductive line and the top via.

US Pat. No. 10,991,615

SUBSTRATE PROCESSING APPARATUS AND METHOD FOR REMOVING SUBSTRATE FROM TABLE OF SUBSTRATE PROCESSING APPARATUS

EBARA CORPORATION, Tokyo...

1. A method for removing a substrate supported on a table from the table, comprising:a step of moving a plurality of lift pins toward the substrate to a first position at a first speed, the first position being a position where the plurality of lift pins make contact with an outer peripheral portion of the substrate, or a position where the plurality of lift pins is about to make contact with the outer peripheral portion of the substrate;
a step of detaching the substrate, which has been vacuum-sucked onto the table, from the table;
a step of moving the plurality of lift pins from the first position to a second position at a second speed, the second position being a position where the substrate is separated from the table with the outer peripheral portion of the substrate being supported by the plurality of lift pins, the second speed being slower than the first speed,
wherein each of the lift pins includes: a substrate guide surface extending perpendicular to a surface of the substrate supported on the table; and a substrate holding surface extending from the substrate guide surface outwardly in a radial direction of the lift pin; and
wherein when lift pins move from the first position to the second position at the second speed, the substrate guide surfaces of the lift pins face an outermost peripheral edge of the substrate, and the substrate holding surfaces of the lift pins support the outer peripheral portion of the substrate.

US Pat. No. 10,991,614

SUSCEPTOR FOR HOLDING A SEMICONDUCTOR WAFER WITH AN ORIENTATION NOTCH DURING THE DEPOSITION OF A LAYER ON A FRONT SIDE OF THE SEMICONDUCTOR WAFER AND METHOD FOR DEPOSITING THE LAYER BY USING THE SUSCEPTOR

Siltronic AG, Munich (DE...

1. A susceptor for receiving a semiconductor wafer having an orientation notch during the deposition of a layer on a front side of the semiconductor wafer, comprising:a susceptor ring and a susceptor base, the susceptor ring comprising a placement area for placing the semiconductor wafer in the edge region of a back side of the semiconductor wafer and a step-shaped outer delimitation of the susceptor ring adjoining the placement area,
wherein the susceptor has four positions arranged radially at which the structure of the susceptor differs from the structure of the susceptor at four further positions arranged radially, the spacing from one of the four positions to the next of the four positions being 90° and the spacing from one of the four positions to the next further position being 45°, one of the four positions being a notch position at which the structure of the susceptor differs from the structure of the susceptor at the three other of the four positions of the susceptor, wherein at the notch position of the susceptor there is a protruberance of the placement area in an inward direction and a protruberance of the outer delimitation in the inward direction, and wherein eithera) a radial width W of the placement area of the susceptor ring at the three other positions of the four positions of the susceptor is less than at the notch position of the susceptor and less than at the further four positions of the susceptor, orb) a height H of the outer delimitation of the susceptor ring at the three other positions of the four positions of the susceptor is greater than at the notch position of the susceptor and greater than at the further four positions of the susceptor, orc) a thickness D of the susceptor at the three other positions of the four positions of the susceptor is less than at the notch position of the susceptor and less than at the further four positions of the susceptor, ord) a radial width B of the outer delimitation of the susceptor ring at the three other positions of the four positions of the susceptor is less than at the notch position of the susceptor and less than at the further four positions of the susceptor, ore) the outer delimitation of the susceptor ring decreases from a height H2 to a height H1 at the three other positions of the four positions of the susceptor from the inner edge of the outer delimitation to the outer edge of the outer delimitation, and stays at the height H1 at the notch position of the susceptor and the further four positions of the susceptor.

US Pat. No. 10,991,613

SUBSTRATE HOLDING APPARATUS, SUBSTRATE SUCTION DETERMINATION METHOD, SUBSTRATE POLISHING APPARATUS, SUBSTRATE POLISHING METHOD, METHOD OF REMOVING LIQUID FROM UPPER SURFACE OF WAFER TO BE POLISHED, ELASTIC FILM FOR PRESSING WAFER AGAINST POLISHING PAD, SU

EBARA CORPORATION, Tokyo...

1. A substrate suction determination method of a substrate holding apparatus, the method comprising:generating negative pressure in a second area formed between a top ring main body and an elastic film in a substrate holding apparatus and pressurizing a first area by feeding fluid into the first area different from the second area, which is formed between the top ring main body and the elastic film; and
performing determination of whether the substrate is sucked to the elastic film based on a measurement value corresponding to a volume of the fluid fed into the first area or corresponding to pressure in the first area, wherein
when the determination is performed, exhaust from the first area is not performed.

US Pat. No. 10,991,609

METHOD AND SUBSTRATE HOLDER FOR THE CONTROLLED BONDING OF SUBSTRATES

EV GROUP E. THALLNER GMBH...

1. A method for bonding a first substrate with a second substrate at respective mutually facing contact faces of the first and second substrates, the method comprising:holding the first substrate to a first holding surface of a first holding device having a plurality of fixing elements, and holding the second substrate to a second holding surface of a second holding device having a plurality of fixing elements,
respectively fixing the first and second substrates to the first and second holding surfaces by switching on the plurality of fixing elements of the first and second holding devices, and
curving at least one of the contact faces of the first and second substrates before contacting of the contact faces of the first and second substrates,
wherein after the contacting of the contact faces of the first and second substrates, switching off each fixing element that is arranged uniaxially along a single contacting axis of at least one of the first or second holding devices, and keeping switched on the remaining fixing elements of the at least one of the first or second holding devices, so that the first and second substrates are first joined together only uniaxially along the contacting axis, and
wherein the remaining fixing elements of the at least one of the first or second holding devices are thereafter switched off, so that the first and second substrates are joined together over a whole area.

US Pat. No. 10,991,607

RETICLE TRANSFER SYSTEM AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:moving an internal buffer in a local system to adjust a boundary between a first service area of the local system and a second service area of the local system, wherein a first lithography apparatus is in the first service area, wherein a second lithography apparatus was in the second service area prior to moving the internal buffer, and wherein the second lithography apparatus is in the first service area after moving the internal buffer;
moving a first reticle from the first lithography apparatus to the second lithography apparatus with a carrier, wherein the carrier and the internal buffer are independently moveable along the local system;
loading a second reticle from the first lithography apparatus into the carrier; and
transporting the second reticle from the local system to a global system.

US Pat. No. 10,991,606

PURGE STOCKER

Murata Machinery, Ltd., ...

1. A purge stocker having a plurality of shelf zones each including a plurality of purge shelves each configured to purge inside of a storage container placed thereon with purge gas, the purge stocker comprising:a flow-rate adjuster configured to adjust a flow rate of the purge gas supplied to the purge shelves for each shelf zone;
a conveying device configured to convey the storage container; and
a controller configured to control conveyance of the storage container by the conveying device, wherein
the controller,
when the number of scattered empty shelves is equal to or larger than a predetermined shelf count that is the number of the purge shelves included in each shelf zone, performs a shelf-changing control of causing the conveying device to transfer the storage container such that an empty shelf zone in which all of the purge shelves included therein are empty is newly formed.

US Pat. No. 10,991,603

APPARATUS AND METHOD FOR TREATING SUBSTRATE

SEMES CO., LTD., Chungch...

1. An apparatus for treating a substrate, the apparatus comprising:a chamber;
a substrate support unit on which the substrate is placed, the substrate support unit being provided in the chamber;
an ozone gas supply unit configured to supply an ozone gas;
a dispensing nozzle configured to dispense, onto the substrate, an ozone treatment fluid containing the ozone gas supplied from the ozone gas supply unit;
a lamp unit configured to irradiate light to the substrate; and
a deionized-water supply unit configured to supply deionized water to the dispensing nozzle,
wherein the dispensing nozzle includes a mixing space in which the deionized water supplied from the deionized-water supply unit and the ozone gas supplied from the ozone gas supply unit are mixed, and
wherein the ozone gas supplied from the ozone gas supply unit through an ozone inflow passage is introduced into the mixing space and brought into contact with the deionized water in the mixing space.

US Pat. No. 10,991,600

PROCESS CHAMBER AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME

Samsung Electronics Co., ...

1. A process chamber comprising:a first housing;
a first substrate support member in the first housing;
a second housing on the first housing;
a second substrate support member in the second housing; and
a fixing bar disposed beside the first and second housings,
wherein the first housing comprises:
a first bottom wall having a first insert hole receiving the fixing bar;
a first top wall facing the first bottom wall;
a first side wall connected between the first bottom wall and the first top wall and having a first opening to provide a substrate in the first housing; and
a first sliding door disposed between the fixing bar and the first opening and configured to close and open the first opening, the first sliding door connected to the first support member,
wherein the second housing comprises:
a second top wall having a second insert hole receiving the fixing bar;
a second bottom wall between the second top wall and the first top wall; and
a second side wall connected between the second top wall and the second bottom wall and having a second opening to provide the substrate in the second housing; and
a second sliding door disposed between the fixing bar and the second opening and configured to close and open the second opening, the second sliding door connected to the second support member,
wherein each of the first side wall and the second side wall have a right supply hole and a left supply hole disposed on both sides of the first and second substrate support member to provide a fluid in the first housing and the second housing,
wherein each of the first side wall and the second side wall have a right exhaust hole and left exhaust hole adjacent to the right supply hole and the left supply hole respectively to extract the fluid in the first housing and the second housing,
wherein the first and second sliding doors are provided in the first and second housing in a first direction, and
wherein the right supply hole, the left supply hole, the right exhaust hole, and the left exhaust hole extend in a second direction perpendicular to the first direction.

US Pat. No. 10,991,597

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE USING AN ADHESIVE LAYER

SAMSUNG ELECTRONICS CO, L...

1. A method of fabricating a semiconductor device, comprising:disposing an adhesive layer on a first surface of a first semiconductor substrate to surround connection terminals of the first semiconductor substrate, the first semiconductor substrate including a base substrate; a circuit layer provided on the base substrate and including transistors; and the connection terminals on the circuit layer, the connection terminals exposed on the first surface of the first semiconductor substrate and including solder ball or a solder bump,
providing a carrier substrate on the first surface of the first semiconductor substrate, the adhesive layer disposed between the carrier substrate and the first surface of the first semiconductor substrate;
separating the carrier substrate from a surface of the adhesive layer while the adhesive layer is still attached to the connection terminals and the first surface of the first semiconductor substrate; and
performing a sawing process on the surface of the adhesive layer formerly attached to the carrier substrate.

US Pat. No. 10,991,596

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base;
forming, on the base, a to-be-etched material layer, a core material layer located on the to-be-etched material layer, and a hard mask (HM) material layer located on the core material layer;
patterning the HM material layer to form a plurality of discrete HM layers, wherein after the HM layers are formed, a plurality of openings is formed between adjacent HM layers;
etching the core material layer between adjacent HM layers, forming, in the core material layer, a plurality of first grooves exposing the to-be-etched material layer, and using the remaining core material layer as a core layer, wherein the etching the core material layer between the adjacent HM layers comprises:
forming a flattened layer on the core material layer exposed from the HM layer, wherein the flattened layer covers the top of the HM layer;
forming a second pattern layer on the flattened layer, wherein the second pattern layer has a plurality of opening patterns, a side wall of an opening pattern located between adjacent HM layers is level with a side wall of the opening, or, an opening pattern located between adjacent HM layers exposes the flattened layer that is above the opening and is above a part of the top of HM layers on two sides of the opening; and
sequentially etching the flattened layer and the core material layer along the opening pattern;
forming a side wall layer on a side wall of the first groove and a side wall of the HM layer;
after the side wall layer is formed, removing the HM layer and the core layer at the bottom of the HM layer, and forming, in the core layer, a plurality of second grooves exposing the to-be-etched material layer; and
removing the to-be-etched material layer at the bottom of the first groove and the second groove by using the side wall layer and the remaining core layer as masks, and forming a target pattern in the remaining to-be-etched material layer.

US Pat. No. 10,991,594

METHOD FOR AREA-SELECTIVE ETCHING OF SILICON NITRIDE LAYERS FOR THE MANUFACTURE OF MICROELECTRONIC WORKPIECES

TOKYO ELECTRON LIMITED, ...

1. A method of processing microelectronic workpieces, comprising:delivering a substrate for a microelectronic workpiece into a plasma processing chamber, the substrate having a silicon nitride layer;
exposing selected regions of the silicon nitride layer to hydrogen ions and/or radicals by forming a first plasma formed of a first plasma gas containing hydrogen and directing plural beams from the first plasma onto the selected regions of the silicon nitride layer to modify the selected regions with hydrogen ions and/or radicals in the plural beams to form modified selected regions of the silicon nitride layer; and
after the exposing the selected regions to hydrogen ions and/or radicals, exposing the modified selected regions to a second plasma formed of a second plasma gas containing fluorine to remove the modified selected regions of the silicon nitride layer; and
removing the substrate from the plasma processing chamber.

US Pat. No. 10,991,592

MODIFIED ETCH-AND-DEPOSIT BOSCH PROCESS IN SILICON

1. A modified Bosch process for building/restoring deep straight walled through-holes of silicon in silicon gas distribution plates, including a beginning silicon deposition cycle comprising:injecting silicon nanoparticles into an atmospheric pressure inductively coupled plasma (AP-ICP) discharge for vaporization and supersonic ejection with an argon plasma beam;
focusing a resulting supersonic ejection of vaporized silicon nanoparticles and argon plasma beam into an entrance of a deep straight-walled through-holes in a silicon wafer or plate;
launching a bias capacitively coupled plasma (CCP) discharge local to an exit of the deep straight-walled through-holes by coupling down through such passages to a bottom CCP discharge generated by a gas permeable RF-powered mesh positioned beneath the silicon wafer or plate;
wherein, a portion of a silicon vapor flow in a thin penetrating supersonic plasma beam dissipates in the bias CCP discharge such that fast vaporized nanoparticles are diverted and slowed down for transitioning into condensed liquid silicon droplets;
wherein the condensed liquid silicon droplets precipitate inside and onto sidewalls of the deep straight-walled through-holes in the silicon wafer or plate and solidify in a solid accretion.

US Pat. No. 10,991,590

ETCHING METHOD AND PLATING SOLUTION

KABUSHIKI KAISHA TOSHIBA,...

1. A method of forming a porous layer, comprising:forming a mask layer on one main surface of a substrate such that the main surface is partially covered by the mask layer; and
thereafter, forming a porous layer comprising a noble metal on a surface made of a semiconductor by displacement plating, a plating solution used in the displacement plating comprising a noble metal source, hydrogen fluoride, and an adjusting agent adjusting a pH value or zeta potential, the noble metal source producing an ion comprising the noble metal in water, and the plating solution having a pH value in a range of 1 to 6,
wherein
the surface made of the semiconductor is a region of the main surface not covered by the mask layer,
the adjusting agent comprises at least one of a nonionic surfactant and an anionic surfactant or a polymeric additive, and
the zeta potential at an interface between the mask layer and the plating solution is in a range of 0 to ?100 mV.

US Pat. No. 10,991,588

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device manufacturing apparatus comprising:a processing target holder configured to hold a workpiece with includes a first metal;
a first catalyst holder configured to hold a first catalyst, the first catalyst promoting formation of a metal oxide film of the first metal onto a surface of the workpiece by contact with the workpiece;
a second catalyst holder configured to hold a second catalyst, the second catalyst promoting elution of the metal oxide film into a treatment liquid by contact with or being moved closer to at least a part of the surface of the metal oxide film,
wherein the first catalyst holder and the second catalyst holder are independently controlled.

US Pat. No. 10,991,586

IN-SITU TUNGSTEN DEPOSITION WITHOUT BARRIER LAYER

APPLIED MATERIALS, INC., ...

1. A processing method comprising:exposing a substrate surface to a boron precursor to form an amorphous boron layer, the substrate surface being substantially free of a barrier layer;
exposing the amorphous boron layer to a first metal precursor to convert the amorphous boron layer to a first metal layer; and
forming a second metal layer on the first metal layer by exposing the first metal layer to a second metal precursor,wherein the processing method is performed without exposing the substrate surface to an air break.

US Pat. No. 10,991,584

METHODS AND STRUCTURES FOR CUTTING LINES OR SPACES IN A TIGHT PITCH STRUCTURE

International Business Ma...

1. A method for manufacturing a semiconductor device, comprising:forming a hardmask layer on a substrate;
forming a plurality of spacers on the hardmask layer, wherein the plurality of spacers comprise a first set of spacers and a second set of spacers;
reducing a height of each spacer of the second set of spacers to be less than a height of each spacer of the first set of spacers;
removing one or more spacers from at least one of the first set of spacers and the second set of spacers;
transferring a pattern of remaining spacers to the hardmask layer to form a plurality of patterned hardmask portions;
transferring a pattern of the plurality of patterned hardmask portions to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate;
forming a plurality of mandrels on the hardmask layer, wherein the plurality of spacers are formed on sides of the plurality of mandrels; and
depositing a mandrel material on the hardmask layer to fill in vacant areas formed by the reducing of the height of each spacer of the second set of spacers.

US Pat. No. 10,991,577

METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE FOR A GALLIUM NITRIDE CHANNEL DEVICE

IMEC VZW, Leuven (BE)

1. A method of forming a semiconductor structure for a III-N semiconductor channel device, the method comprising:forming a buffer structure on a Si-substrate, wherein forming said buffer structure comprises:
forming a nucleation layer of AlN on the Si-substrate;
forming a lower transition layer of (Al)GaN on the nucleation layer;
forming a superlattice on said lower transition layer, said superlattice comprising at least one superlattice block, each superlattice block comprising a repetitive sequence of superlattice units, each superlattice unit comprising a plurality of layers, said plurality of layers comprising a first layer and a second layer formed on said first layer, wherein said first layer is a carbon-doped AlxGa1-xN layer and said second layer is a carbon-doped AlyGa1-yN layer, wherein x and y differ from each other, 0?x?1 and 0?y?1, wherein said first layer and second layer is epitaxially grown at a temperature of 980° C. or lower and wherein the first layer and the second layer have a carbon-doping concentration ranging from 1019cm?3 to 1020cm?3; and
forming an upper transition layer of carbon-doped GaN on said superlattice, wherein the carbon-doped GaN has a carbon-doping concentration ranging from 1019 cm?3 to 1020 cm?3; and
forming a III-N semiconductor channel layer on said upper transition layer of said buffer structure, wherein said channel layer is epitaxially grown at a temperature ranging from 1010° C. to 1040° C. and is grown to a thickness of 1 ?m or smaller.

US Pat. No. 10,991,576

CRYSTALLINE SEMICONDUCTOR LAYER FORMED IN BEOL PROCESSES

Taiwan Semiconductor Manu...

13. A device, comprising:a first dielectric layer;
a crystalline magnesium oxide layer over the first dielectric layer;
a crystalline semiconductor layer over the crystalline magnesium oxide layer;
a gate structure at least partially overlapping the crystalline semiconductor layer; and
a source or drain region contacting the crystalline semiconductor layer.

US Pat. No. 10,991,574

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a semiconductor device, the method comprising:forming a three-dimensional (3D) structure on a substrate;
forming an adsorption control layer to cover an upper portion of the 3D structure; and
forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer,
wherein an adsorption on the adsorption control layer is less than an adsorption on the lower portion of the 3D structure,
wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

US Pat. No. 10,991,572

MANUFACTURING METHOD FOR SEMICONDUCTOR APPARATUS

Semiconductor Manufacturi...

1. A manufacturing method for a semiconductor apparatus, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises:
a substrate and an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer has an opening for forming a gate;
depositing a gate metal layer on the semiconductor structure to fill the opening entirely, wherein the gate metal layer contains impurity, the gate metal layer comprises a first part in the opening and a second part on the first part, the second part covers a top of the opening, the second part is further formed on the interlayer dielectric layer;
removing a portion of the second part;
after removing the portion of the second part, forming an impurity adsorption layer on the gate metal layer;
performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer, wherein a temperature of the first annealing treatment falls within a range of 800° C. to 1000° C.; and
removing the impurity adsorption layer after the first annealing treatment is performed, wherein a remaining portion of the second part, a portion of the interlayer dielectric layer, and a portion of the first part are further removed, a remaining portion of the first part is used as a metal gate.

US Pat. No. 10,991,570

SEMICONDUCTOR WAFER CLEANING APPARATUS

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor wafer cleaning apparatus, comprising:a spin base having a through hole;
a spindle extending through the through hole and having an upper surface and a rotational axis;
a clamping member covering the through hole and connected to the spindle, wherein a gap that communicates with the through hole is formed between the spin base and the clamping member, wherein the clamping member covers the whole upper surface of the spindle; and
a first sealing ring and a second sealing ring positioned adjacent to the gap and located farther away from the spindle than the gap, wherein the first sealing ring and the second sealing ring are arranged along the rotational axis, wherein the spin base has a flange formed at an edge of the through hole, and the gap is formed between the flange and a bottom surface of the clamping member, the first sealing ring is located below the clamping member, and, in the vertical direction, the height of the flange is equal to the height of the first sealing ring.

US Pat. No. 10,991,568

ION RESONANCE EXCITATION OPERATION METHOD AND DEVICE BY APPLYING A QUADRUPOLAR ELECTRIC FIELD COMBINED WITH A DIPOLAR ELECTRIC FIELD

BEIJING INSTITUTE OF TECH...

1. An ion resonance excitation operation method by applying a quadrupolar electric field combined with a dipolar electric field for an ion trap mass analyzer, comprising:applying a main radio frequency signal having a first frequency and a first amplitude to any pair of plates of the ion trap mass analyzer; and
applying a quadrupolar excitation signal having a second frequency and a second amplitude to any pair of plates and applying a reverse phase dipolar excitation signal having a third frequency to any pair of plates, wherein the second amplitude is from 0.1% to 1.2% of the first amplitude.

US Pat. No. 10,991,567

QUADRUPOLE DEVICES

MICROMASS UK LIMITED, Wi...

1. A method of operating a quadrupole device comprising:operating the quadrupole device in a first mode of operation;
passing ions into the quadrupole device while the quadrupole device is operated in the first mode of operation; and then
operating the quadrupole device in a second mode of operation;
wherein operating the quadrupole device in the second mode of operation comprises applying one or more drive voltages to the quadrupole device, wherein the one or more drive voltages comprise a repeating voltage waveform, and wherein operating the quadrupole device in the second mode of operation comprises initially applying the one or more drive voltages to the quadrupole device at a selected phase or range of phases of the voltage waveform;
wherein operating the quadrupole device in the first mode of operation comprises applying one or more reduced drive voltages or not applying one or more drive voltages to the quadrupole device; and
wherein the voltage waveform is configured to have a continuous phase value range at which the drive voltage is zero, and wherein the selected phase or range of phases coincides with the continuous phase value range at which the drive voltage is zero.

US Pat. No. 10,991,564

MASS SPECTROMETRY PROBES AND SYSTEMS FOR IONIZING A SAMPLE

Purdue Research Foundatio...

1. A method for analyzing a biological molecule, the method comprising:providing a mass spectrometry probe comprising a paper substrate in which a portion of the paper substrate is coated with an electrically conductive material that is not a biological molecule or a solvent, in a manner that a plurality of nanoscale features protrude from the paper substrate, the plurality of nanoscale features configured to act as a plurality of electrodes and upon application of a voltage of 3 volts or less, providing a field strength high enough to cause field emission of microscale solution droplets at the plurality of nanoscale features at a voltage that does not cause fragmentation of the biological molecule; connecting the mass spectrometry probe to a voltage source, wherein the voltage source is configured to generate a voltage of 3 volts or less; contacting the mass spectrometry probe with the biological molecule; ionizing the biological molecule that has contacted the mass spectrometry probe; and analyzing the ionized biological molecule in a mass spectrometer.

US Pat. No. 10,991,563

MOLECULAR IMAGING OF BIOLOGICAL SAMPLES WITH SUB-CELLULAR SPATIAL RESOLUTION AND HIGH SENSITIVITY

Virgin Instruments Corpor...

1. An apparatus for molecular imaging of biological samples, the apparatus comprising:a) a first optical port configured to receive a first pulsed optical beam that is directed in an optical path along an optical axis;
b) a transparent target positioned in the optical path along the optical axis, the transparent target comprising a first surface having an electrically conductive surface that supports a biological sample under analysis and a second surface;
c) a moveable target mount that is mechanically attached to the transparent target and configured to translate the transparent target to a plurality of predetermined locations;
d) a first optical focusing element positioned in the optical path along the optical axis and configured to focus the first pulsed optical beam to a first predetermined diameter at the first surface of the transparent target having the electrically conductive surface that supports the biological sample under analysis;
e) a second optical port configured to receive a second pulsed optical beam that is directed in a second optical path along the optical axis;
f) a second optical focusing element positioned in the second optical path along the optic axis and configured to focus the second pulsed optical beam to a second predetermined diameter at the electrically conductive surface on the transparent target that supports the biological sample under analysis;
g) a time-of-flight mass spectrometer comprising an ion accelerator having a central axis that is substantially coaxial with the optical axis so that ions generated by the first and second pulsed optical beams are accelerated by the ion accelerator; and
h) a controller having an output that is electrically connected to a control input of the time-of-flight mass spectrometer and having a second output that is electrically connected to a control input of the transparent target stage, wherein the controller instructs the time-of-flight mass spectrometer to acquire mass spectral data at the plurality of predetermined locations, thereby generating a molecular image of the biological sample under analysis.

US Pat. No. 10,991,562

LOW CROSS-TALK FAST SAMPLE DELIVERY SYSTEM BASED UPON ACOUSTIC DROPLET EJECTION

Micromass UK Limited, Wi...

1. An ion source for a mass spectrometer comprising:a transducer arranged and adapted to focus acoustic energy onto a surface of a sample fluid without said transducer directly contacting said sample fluid, wherein said transducer is arranged and adapted to eject one or more droplets from said sample fluid in a substantially controlled manner, and wherein said one or more droplets comprise a majority of un-ionised droplets; and
an ionisation device arranged and adapted to ionise a volume of liquid comprising said one or more droplets ejected from said sample fluid by said transducer.

US Pat. No. 10,991,561

MASS SPECTROMETER VACUUM INTERFACE METHOD AND APPARATUS

Thermo Fisher Scientific ...

1. A skimmer apparatus for use in a mass spectrometer vacuum interface and having an internal surface and a skimmer aperture for skimming plasma therethrough to provide a skimmed plasma downstream of the skimmer aperture,the skimmer apparatus having a recess in the internal surface for receiving a channel-forming member so as to be in conductive contact with the skimmer apparatus, whereby the channel-forming member is electrically neutral relative to the skimmer apparatus when disposed in the recess, wherein when disposed in the recess the channel-forming member defines one or more channels between the recess and the channel-forming member for separating within the skimmer apparatus a portion of the skimmed plasma adjacent the internal surface of the skimmer apparatus from the remainder of the skimmed plasma.

US Pat. No. 10,991,559

METHOD FOR QUANTITATIVE ANALYSIS OF POLYMER USING MALDI MASS SPECTROMETRY, AND METHOD FOR MANUFACTURING SAMPLE FOR MALDI MASS SPECTROMETRY FOR QUANTITATIVE ANALYSIS OF POLYMER

LG Chem, Ltd.

1. A method for quantitative analysis of a polymer using MALDI mass spectrometry, comprising:preparing a specimen by electrospraying a polymer sample, which is a mixed solution of a polymer compound, a matrix and a solvent, from a main nozzle onto a sample plate through a mask,
wherein a thickness deviation in the specimen is 30% or less, and
the mask comprises a hole through which the polymer sample is passed to the sample plate during the electrospraying.

US Pat. No. 10,991,554

PLASMA PROCESSING SYSTEM WITH SYNCHRONIZED SIGNAL MODULATION

TOKYO ELECTRON LIMITED, ...

1. A system for using plasma to treat a substrate, comprising:a substrate holder disposed within a plasma processing system, and arranged to support a substrate;
a first signal generator for coupling a first signal at a first frequency to plasma in the plasma processing system, the plasma comprising a plasma sheath;
a second signal generator for coupling a second signal at a second frequency to the plasma in the plasma processing system, the second frequency being less than the first frequency, wherein the second signal is a low frequency (LF) sinusoidal waveform having the second frequency;
a timing circuit configured to define an amplitude modulation signal as comprising a series of pulses each synchronized with a corresponding negative cycle of the LF sinusoidal waveform during expansion of the plasma sheath, wherein a pulse width of each of the series of pulses comprises a duration less than half of the period of the second frequency of the LF sinusoidal waveform; and
an amplitude modulation circuit for modulating the first signal between a high amplitude state and a low amplitude state in response to the amplitude modulation signal, the first signal being in the high amplitude state during negative cycles of the LF sinusoidal waveform.

US Pat. No. 10,991,552

COOLING MECHANISM UTILIZED IN A PLASMA REACTOR WITH ENHANCED TEMPERATURE REGULATION

Applied Materials, Inc., ...

1. A method for regulating temperature of a coil antenna assembly disposed above a processing chamber, the method comprising:rotating a plurality of air circulators disposed adjacent to the coil antenna assembly in a coil antenna enclosure;
directing ambient air into the coil antenna enclosure from one or more perforations formed in a sidewall of the coil antenna enclosure;
guiding the ambient air to a center region of the coil antenna assembly through a central opening formed in a baffle plate disposed underneath the coil antenna assembly; and
directing air out of the coil antenna enclosure.

US Pat. No. 10,991,551

CLEANING METHOD AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A cleaning method comprising:(a) supplying a cleaning gas into a processing chamber;
(b) applying a radio frequency (RF) power for plasma generation to one of a first electrode on which a substrate is to be mounted and a second electrode disposed to be opposite to the first electrode in the processing chamber;
(c) applying a negative voltage to an edge ring disposed to surround the substrate; and
(d) generating plasma from the cleaning gas and performing a cleaning process using the plasma.

US Pat. No. 10,991,549

ANTENNA AND PLASMA DEPOSITION APPARATUS

Tokyo Electron Limited, ...

10. A plasma deposition apparatus, comprising:an antenna configured to provide VHF radio frequency waves; and
a process chamber in which plasma is generated based on the VHF radio frequency waves to perform a deposition process,
wherein the antenna includes;
a first waveguide configured to guide the VHF radio frequency waves; and
a second waveguide configured to guide the VHF radio frequency waves supplied from the first waveguide, the second waveguide having a pair of metal reflective plates therein facing each other across a longitudinal distance along the second waveguide,
wherein a tip end of the first waveguide is coupled to the second waveguide at a sideways point thereof between the metal reflective plates, and
wherein a distance between the metal reflective plates is ?g/4+?g·n/2, ?g being a wavelength of the VHF radio frequency waves in the second waveguide, and n being an integer greater than or equal to zero.

US Pat. No. 10,991,547

METHOD AND DEVICE FOR A CARRIER PROXIMITY MASK

Applied Materials, Inc., ...

1. A method of forming a variable etch depth profile in a substrate, comprisingproviding a substrate;
providing a carrier, the carrier comprising a first carrier body coupled with a second carrier body, the substrate coupled between the first carrier body and the second carrier body, the first carrier body having one or more openings to expose work areas of the substrate, the one or more openings having edges;
convolving a first edge of the edges in a first opening with a beam from a processing tool to create a convolved beam, the convolved beam to etch a work area of the substrate exposed by the first opening to create a variable etch depth profile in the substrate proximate to the first edge; and
increasing a current density of the beam as the beam transitions from a masked area of the substrate to an edge of the first carrier body.

US Pat. No. 10,991,544

CHARGED PARTICLE BEAM DEVICE, OBJECTIVE LENS MODULE, ELECTRODE DEVICE, AND METHOD OF INSPECTING A SPECIMEN

1. A charged particle beam device for inspecting a specimen, comprising:a beam source for emitting a charged particle beam;
an electrode for influencing the charged particle beam; and
a damping unit provided on the electrode for damping vibrations of the electrode,
wherein the damping unit is mounted at the electrode and not between the electrode and another object that can vibrate relative to each other,
wherein the damping unit is a mass damper that comprises a damping mass and an elastic element arranged at least partially between the damping mass and the electrode, and
wherein the damping unit is configured to dampen predetermined vibration modes of the electrode.

US Pat. No. 10,991,543

CHARGED PARTICLE BEAM DEVICE

Hitachi High-Tech Corpora...

1. A charged particle beam device comprising:an objective lens for converging a charged particle beam emitted from a charged particle source;
a sample stage having a first driving mechanism for moving a sample to be irradiated with the charged particle beam between a first position and a second position more separated from the objective lens than the first position;
a detection surface for detecting charged particles emitted from the sample; and
a second driving mechanism for moving the detection surface between within a movable range of the sample between the first position and the second position and out of the movable range of the sample.

US Pat. No. 10,991,542

CHARGED PARTICLE BEAM DEVICE

Hitachi High-Tech Corpora...

1. A charged particle beam device comprising:a detector that detects charged particles obtained on the basis of irradiation of a specimen with a charged particle beam emitted from a charged particle source; and
a control unit that processes a signal obtained on the basis of output of the detector, wherein
the control unit is an image processing device that integrates a plurality of frame images to generate an integrated image, and
the control unit performs, before irradiation of the charged particle beam for generating the integrated image, statistical processing on gray level values of frames in a predetermined region of an image generated on the basis of the output of the detector, the number of the frames subject to the statistical processing being smaller than the number of the frames of the integrated image, and
executes signal processing that corrects a difference between a statistical value obtained by the statistical processing and reference data relating to gray level values of the image, thereby generating the integrated image.

US Pat. No. 10,991,536

ELECTRICAL CONNECTION BOX

Sumitomo Wiring Systems, ...

1. An electrical connection box for a vehicle, including: an insertion housing into which a plurality of fuses are to be inserted; a plurality of fuse terminals for connecting the fuses in the insertion housing to a substrate; and a holding member that is arranged opposing a surface of the insertion housing and holds the fuse terminals, whereinthe holding member includes a holding plate having a plurality of notches for holding at least one of the plurality of fuse terminals and a gripping portion opposite of the insertion housing, the gripping portion being tube shaped and disposed between a pair of the plurality of fuse terminals, and
the gripping portion has a finger placement portion used for gripping.

US Pat. No. 10,991,532

CONTACT DEVICE AND ELECTROMAGNETIC RELAY MOUNTED WITH SAME

PANASONIC INTELLECTUAL PR...

1. A contact device comprising:a contact block including:
a fixed contact, and
a movable contactor including a movable contact formed to come into and out of contact with the fixed contact, the movable contact formed on a first side of the movable contactor;
a driving block including a driving shaft which moves the movable contactor, the driving block configured to drive the driving shaft so that the movable contact can come into and out of contact with the fixed contact along a driving direction along the driving shaft; and
a yoke disposed on a second side of the movable contactor and fixed to the movable contactor, the second side of the movable contactor facing the first side of the movable contactor in the driving direction;
wherein one of the yoke and the movable contactor includes a projection projected along the driving direction, and the other of the yoke and the movable contactor includes an insertion hole in which to insert the projection.

US Pat. No. 10,991,530

PORTABLE OBJECT COMPRISING A NEAR-FIELD CONNECTION DEVICE

The Swatch Group Research...

1. A portable object comprising a near-field communication device, the communication device comprising:an electronic chip;
an antenna including ends configured to connect electrically to the electronic chip to form an electrical circuit;
a mechanical control element configured to be displaced between two predefined positions including an active position wherein the communication device is activated and a passive position wherein the communication device is deactivated;
a mechanical switch configured to switch between an open state and a closed state in response to a displacement of the mechanical control element between the two predefined positions, wherein the mechanical switch is a Reed switch;
a permanent magnet configured to move relative to the Reed switch and configured to modify a state of the Reed switch in response to a displacement of the mechanical control element; and
an elastic restoring element configured to return the mechanical control element automatically from the active position to the passive position.

US Pat. No. 10,991,529

GAS-BLAST CIRCUIT BREAKER

Hitachi, Ltd., Tokyo (JP...

1. A gas-blast circuit breaker comprising:a driving-side main contact and a driven-side main contact placed in a gas tank to face each other and configured to operate for opening and closing a circuit;
a driving-side arc contact and a driven-side arc contact placed to face each other and configured to operate for opening and closing the circuit;
a puffer shaft to which the driving-side arc contact is coupled;
a puffer cylinder fixed at a location outside the puffer shaft coaxially with the puffer shaft, the puffer cylinder having an end provided with the driving-side main contact;
an insulating nozzle fixed to the end of the puffer cylinder, the insulating nozzle providing a space in which an arc is generated when the circuit is opened by the driving-side arc contact and the driven-side arc contact;
a driver configured to drive the puffer shaft; and
a puffer chamber in which arc-extinguishing gas being to be supplied to the space is stored, wherein
the insulating nozzle is coupled to a driving rod,
the driving rod is connected to a driven rod via a lever,
the driven rod is electrically connected to the driven-side arc contact, and
an elastic electrically conductive material is provided on an outer surface of the insulating nozzle, the outer surface of the insulating nozzle facing an inner surface of the driving-side main contact, the inner surface of the driving-side main contact facing radially inward toward the driving-side arc contact, wherein a surface of the elastic electrically conductive material is arranged in contact with the inner surface of the driving-side main contact, wherein
the elastic electrically conductive material is a resin or a metal,
a reinforcing member is provided on an outer surface of the elastic electrically conductive material, and
the elastic electrically conductive material is fixed by being sandwiched by the insulating nozzle and the reinforcing member.

US Pat. No. 10,991,523

KEYBOARD DEVICE

Chicony Electronics Co, ,...

1. A keyboard device, comprising:a base plate; and
a plurality of keyswitches disposed on the base plate, at least one of the keyswitches comprising:
a keycap located over the base plate;
two linkages connected between the base plate and the keycap and configured to guide movements of the keycap toward and away from the base plate; and
two magnetic attraction members rotatably connected to the linkages respectively and configured to attract each other,
wherein when the magnetic attraction members abut against each other, the keycap is at a highest position relative to the base plate, and when the keycap moves toward the base plate from the highest position, the magnetic attraction members are separated from each other.

US Pat. No. 10,991,521

LOCKING DEVICE FOR CIRCUIT BREAKER OPERATION DEVICE

ShangHai Liangxin Electri...

1. A locking mechanism for a circuit breaker operating device, comprising a housing, and a button mounted in a button slot of the housing, wherein the housing is provided therein with a locking member, and the locking member is configured for locking or unlocking the button, wherein the locking member comprises a first lock button, wherein the first lock button is mounted in the housing via a first shaft and is rotatable about the first shaft, a first limiting boss is provided on one side of the first lock button, the button is provided with a first limiting step corresponding to the first limiting boss, a first locking boss is provided on an upper surface on an other side of the first lock button, the housing is provided with a first limiting slot hole corresponding to the first locking boss, a first torsion spring is mounted to the housing, and the first torsion spring has one end resting on a lower surface of the first lock button located on a right side of the first shaft.

US Pat. No. 10,991,518

VACUUM-CAPACITOR APPARATUS AND METHOD

GranBlueTech, L.L.C., Bu...

1. An apparatus comprising:a capacitor that includes:
a first electrode; and
a second electrode,
wherein at least one of the first electrode and the second electrode has a surface that is coated with a dielectric film having a dielectric constant of at least ten, and
wherein the device maintains a vacuum in a region that separates the first electrode and the second electrode.

US Pat. No. 10,991,516

SOLID ELECTROLYTIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A solid electrolytic capacitor comprising:a plurality of capacitor elements laminated in parallel; and
a resin sealing the plurality of capacitor elements,
wherein
each of the plurality of capacitor elements includes:
a valve action metal base;
an oxide film dielectric layer on a surface of the valve action metal base; and
a cathode layer on a surface of the oxide film dielectric layer, and
a first thickness of the oxide film dielectric layer of at least one first capacitor element of the plurality of capacitor elements is greater than a second thickness of the oxide film dielectric layer of a second capacitor element of the plurality of capacitor elements, and
a first area of the cathode layer of the at least one first capacitor element and a second area of the second capacitor element of the plurality of capacitor elements are substantially the same.

US Pat. No. 10,991,515

SOLID ELECTROLYTIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A solid electrolytic capacitor comprising:a plurality of laminated units, each unit of the plurality of laminated units including:
a valve action metal substrate including a porous layer on a surface thereof, the valve action metal substrate having an anode section-side end surface;
a dielectric layer on a surface of the porous layer;
a solid electrolyte layer on the dielectric layer; and
a carbon layer on the solid electrolyte layer;
a metal foil between the laminated units, wherein the metal foil has a surface coated with carbon and the carbon-coated surface of the metal foil is in direct contact with the carbon layer;
a coating resin sealing the plurality of laminated units and the metal foil;
an anode outer electrode on a surface of the coating resin and directly connected to the anode section-side end surface of the valve action metal substrate; and
a cathode outer electrode on the surface of the coating resin and directly connected to the metal foil.

US Pat. No. 10,991,512

CAPACITOR COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor component, comprising:a lamination portion in which first and second internal electrodes are disposed to face each other in a first direction and separated from each other by a dielectric layer;
a body comprising the lamination portion and first and second connection portions disposed on both sides of the lamination portion in a second direction and connected to the first and second internal electrodes, respectively; and
first and second external electrodes disposed on the first and second connection portions, respectively,
wherein the first and second connection portions each comprise a metal layer comprising nickel and disposed on the lamination portion and a ceramic layer disposed on the metal layer, and
a length, in the first direction, of the ceramic layer is less than a length, in the first direction, of the lamination portion.

US Pat. No. 10,991,511

DIELECTRIC COMPOSITION AND ELECTRONIC COMPONENT

TDK CORPORATION, Tokyo (...

1. A dielectric composition including a complex oxide represented by a formula of AaBbC4O15+? as a main component, in which“A” at least includes Ba, “B” at least includes Zr, “C” at least includes Nb, “a” is 3.05 or more, and “b” is 1.01 or more.

US Pat. No. 10,991,510

DIELECTRIC MEMBRANE AND DIELECTRIC ELEMENT

TDK CORPORATION, Tokyo (...

1. A dielectric membrane comprising:a metal oxide, as a main component, having a cubic crystal structure expressed by a general formula (Ba, Ca)(Ti, Zr)O3,
wherein a relationship in a membrane thickness direction of both degree of orientation of (100) plane>degree of orientation of (110) plane and degree of orientation of (111) plane>degree of orientation of (110) plane is satisfied.

US Pat. No. 10,991,507

IGNITION COIL FOR INTERNAL COMBUSTION ENGINE

Mitsubishi Electric Corpo...

1. An ignition coil for an internal combustion engine, the ignition coil comprising:a center core arranged on an inner side of a primary coil and an inner side of a secondary coil;
a side core arranged on an outer side of the primary coil and an outer side of the secondary coil, and combined with the center core to form a closed magnetic circuit;
one or a plurality of gaps provided between the center core and the side core, or in the side core; and
a magnet arranged in each of the gaps,
wherein a sum of sizes of cross-sectional areas of the respective magnets is set to be greater than or equal to a lower limit and less than an upper limit of a size of a cross-sectional area of a portion of the center core around which the primary coil is wound, and wherein the lower limit is three times the size of the cross-sectional area of the portion of the center core and the upper limit is seven times the size of the cross-sectional area of the portion of the center core.

US Pat. No. 10,991,501

TRANSFORMER AND POWER SUPPLY DEVICE INCLUDING THE SAME

SOLUM CO., LTD., Yong-in...

1. A transformer comprising:a base including a first portion and a second portion having terminal pins penetrating the second portion; and
a coil assembly providing on the base and including a magnetic core, a first coil part and a second coil part disposed in the magnetic core,
wherein the first coil part includes:
a laminated substrate including insulating layers and conductive patterns; and
pin holes penetrating a portion of the laminated substrate,
wherein the terminal pins are disposed in the pin holes,
wherein the second coil part includes a conductive wire and a plurality of insulating layers surrounding the conductive wire,
wherein the base further includes a third portion and a sidewall vertically protruding from a bottom surface of the first portion, the sidewall includes a coil lead-out hole,
wherein the sidewall is disposed between the first portion and the third portion,
wherein the first portion is disposed between the second portion and the third portion,
wherein at least one of ends of the second coil part is led out toward the third portion through the coil lead-out hole.

US Pat. No. 10,991,493

RARE EARTH MAGNET

TDK CORPORATION, Tokyo (...

1. A rare earth magnet comprising main phase grains having an R2T14B type crystal structure, and comprisingR: 29.5 to 35.0 mass %; B: 0.87 to 0.98 mass %; M: 0.03 to 1.7 mass %; Cu: 0.01 to 1.5 mass %; Fe: substantial remaining part; total content of element(s) other than Fe occupying the remaining part: 5.0 mass % or less,
wherein M is Ga: 0.03 to 1.5 mass %; and one or more elements selected from the group consisting of Al, Si, Ge and Sn, and
wherein
an atom concentration ratio A (A=?Ga/?Ga) of the main phase grains is 1.50 or more, where ?Ga and ?Ga are respectively a highest concentration of Ga and a lowest concentration of Ga in one main phase grain, and
an absolute value of thermal demagnetization factor is 0.5% or less.

US Pat. No. 10,991,491

PERMANENT MAGNET, AND MOTOR AND POWER GENERATOR USING THE SAME

KABUSHIKI KAISHA TOSHIBA,...

1. A permanent magnet comprising a sintered compact, the sintered compact comprising:a composition expressed by the following composition formula:
RpFeqMrCusCo100-p-q-r-s wherein, R is at least one element selected from the group consisting of rare-earth elements, and 50 at % or more of the element R is Sm,M is at least one element selected from the group consisting of Zr, Ti, and Hf,
p is a number satisfying 10 q is a number satisfying 30 r is a number satisfying 1.78 s is a number satisfying 3.5 a metallic structure including a cell phase having a Th2Zn17 crystal phase, and a cell wall phase surrounding the cell phase,
wherein a Fe concentration (C1) in the cell phase is in a range from 30.1 at % to 32.3 at %, and a difference (C1?C2) between the Fe concentration (C1) in the cell phase and a Fe concentration (C2) in the cell wall phase is in a range from 12.2 at % to 23.0 at %,
wherein the sintered compact has a density of 8.22×103 kg/m3 or more and 8.31×103 kg/m3 or less, and
wherein a coercive force of the permanent magnet is 870 kA/m or more.

US Pat. No. 10,991,490

POROUS STABILIZED BEDS, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME

University of Florida Res...

1. A monolithic solid produced by the process comprising:disposing a mixture of a plurality of first metal particles and second particles in a reactor, wherein first metal particles are magnetic particles and the second particles are not magnetic particles;
wherein the first particles have an average particle size of about 40 micrometers to about 100 micrometers, and the first particles are from about 10 wt % to about 90 wt % of the mixture;
wherein the second particles have an average particle size of about 20 micrometers to about 100 micrometers, and the second particles are from about 10 wt % to about 90 wt % of the mixture;
fluidizing the mixture in a reactor;
applying a magnetic field, an electrical field, or a combination of a magnetic field and an electrical field to the mixture; and
heating the mixture at a temperature of from about 300° C. to about 2,000° C. to produce the monolithic solid.

US Pat. No. 10,991,489

INSULATION SYSTEM FOR A TOOL, TOOL, AND METHOD FOR MOUNTING THE INSULATION SYSTEM ON THE TOOL

Robert Bosch GmbH, Stutt...

1. An insulation system for a tool, comprising:an extension configured to electrically insulate an output unit of the tool from a detachably receivable tool element of the tool, the output unit extending outwardly from a housing of the tool and configured to drive the detachably receivable tool element to perform a mechanical process on a workpiece, wherein the extension is configured to extend between the output unit and the detachably receivable tool element along a longitudinal axis, with a first end portion of the extension operably connected to the output unit and a second end portion of the extension spaced apart from the first end portion along the longitudinal axis and operably connected to the detachably receivable tool element; and
a housing configured to electrically insulate the output unit in a direction radially outwardly of the output unit relative to the longitudinal axis.

US Pat. No. 10,991,488

SHED HOUSING

JIANGSU SHENMA ELECTRIC C...

1. A shed housing for covering an insulator including at least one shed, comprising a receiving cavity to allow an upper surface and a lower surface of the shed to be received in the receiving cavity,wherein the shed housing comprises an upper shed housing body and a lower shed housing body, a concave dovetail groove is provided on the lower surface of the upper shed housing body, a protrusion corresponding to the concave dovetail groove is provided on an outer edge of the lower shed housing body, through joining the protrusion with the concave dovetail groove, the upper shed housing body is joined with the lower shed housing body to form the receiving cavity,
wherein the shed housing is provided with a mounting hole through which the insulator passes, and an opening corresponding to the mounting hole, the opening communicates the mounting hole with an outer edge of the shed housing, the mounting hole communicates with the receiving cavity, a first connecting portion and a second connecting portion cooperating with each other are arranged respectively on both ends of the opening, and when the first connecting portion is connected to the second connecting portion, the shed housing is closed along a circumferential direction,
wherein a first groove is provided on a portion of the first connecting portion located on the upper shed housing body, and a first strap is provided on a portion of the second connecting portion located on the upper shed housing body,
wherein the first groove is provided with at least one first protrusion and the first strap is provided with at least one first through hole fitting the at least one first protrusion, and
wherein the first protrusion cooperates with the first through hole to connect the first strap with the first groove and close the shed housing along a circumferential direction.

US Pat. No. 10,991,487

CABLE AND PRODUCING METHOD THEREFOR

HITACHI METALS, LTD., To...

1. A cable, comprising:a linear shape conductor;
a first electrical insulating member coating a periphery of the conductor;
a shield comprising a plating layer coating a surface of the first electrical insulating member;
a second electrical insulating member coating a surface of the shield; and
an exposed shield portion provided in at least one end portion of the cable with the second electrical insulating member being removed therefrom and the shield being exposed therein during termination,
wherein an adhesion strength between the shield and the second electrical insulating member in the exposed shield portion is lower than an adhesion strength between the shield and the second electrical insulating member in an other part of the surface of the shield, wherein an arithmetic average roughness Ra of the surface of the shield in the other part thereof is in a range of not lower than 0.5 ?m and not higher than 10 ?m.

US Pat. No. 10,991,485

COAXIAL CABLE

HITACHI METALS, LTD., To...

1. A coaxial cable, comprising:an inner conductor;
an insulator covering a circumference of the inner conductor;
a shield layer covering a circumference of the insulator; and
a sheath covering a circumference of the shield layer,
wherein the inner conductor is composed of first metal strands that are twisted each other in such a manner that a cross-sectional shape of the inner conductor is circular,
wherein the shield layer comprises a winding shield layer including second metal strands spirally wound around the insulator, and a shield tape layer comprising a shield tape including a resin tape and a metal layer provided on one side of the resin tape, the shield tape being spirally wound around the winding shield layer with the metal layer being located inwardly radially in such a manner that the metal layer is being in contact with the winding shield layer,
wherein the winding shield layer has a gap in at least one location between the second metal strands adjacent to each other in a circumferential direction, and a sum of each of distances w between the second metal strands adjacent to each other via the gap is not more than an outer diameter d of the second metal strand in a cross-section perpendicular to a longitudinal direction.

US Pat. No. 10,991,483

ASSEMBLED WIRE, METHOD OF PRODUCING THE SAME, AND ELECTRICAL EQUIPMENT USING THE SAME

ESSEX FURUKAWA MAGNET WIR...

1. A high-frequency assembled wire, comprising:an assembled conductor composed of a plurality of conductor strands each having a rectangular cross-section, stacked and arranged each other across an interlayer insulating layer;
an insulating outer layer that coats the assembled conductor including the interlayer insulating layer; and
an adhesion layer comprising a thermoplastic resin having a thickness of 3 ?m or more and 8 ?m or less between the assembled conductor and the insulating outer layer,
wherein
the adhesion layer is composed of a resin comprising polyetherimide, polyethersulfone, or polyphenyl sulfone, and
the interlayer insulating layer is composed of a resin comprising polyethylene terephthalate, polyethylene naphthalate, polyamide 6T, or polyamide 9T, and
the insulating outer layer is composed of a resin comprising a thermoplastic resin having a melting point of 270° C. or more selected from polyphenylenesulfide, polyetheretherketone, modified polyetheretherketone, or thermoplastic polyimide.

US Pat. No. 10,991,481

POLYMER-COATED WIRES

Zeus Industrial Products,...

1. An insulated electrical conductor, comprising:an electrical conductor comprising an oxide layer on at least part of a surface of the electrical conductor; and
an insulating coating on at least a portion of the oxide layer,
wherein:
a combination of the electrical conductor and the insulating coating has been subjected to heat treatment after the insulating coating is applied to at least the portion of the oxide layer, the heat treatment comprising heating to a temperature at or greater than the melting temperature of the insulating coating; and
the insulated electrical conductor exhibits adhesion between the insulating coating and one or more of the electrical conductor and the oxide layer such that the insulating coating is not strippable from the electrical conductor after the heat treatment.

US Pat. No. 10,991,474

SHIELDING ASSEMBLIES FOR INFUSION SYSTEMS

Bracco Diagnostics Inc., ...

1. An infusion system comprising:a first shielding compartment defining a first opening configured to receive a strontium-rubidium radioisotope generator that generates radioactive eluate via elution;
a first door covering the first shielding compartment that is configured to contain the strontium-rubidium radioisotope generator, wherein the first door is configured to provide access to the first shielding compartment when open and provide a further barrier to radioactive radiation when closed, the first door being attached via a hinge and being configured to rotate about the hinge to open and close in a vertically upward direction;
a second shielding compartment defining a second opening configured to receive a waste bottle, the second opening facing vertically upwardly and being accessible via a top surface of the second shielding compartment;
a second door covering the second shielding compartment that is configured to contain the waste bottle, wherein the second door is configured to provide access to the second shielding compartment when open and provide a further barrier to radioactive radiation when closed;
two tubing passageways formed in a perimeter surface of the first opening, each of the two tubing passageways having a depth configured to prevent pinching or crushing of a corresponding tubing line routed therethrough when the first door is closed thereover,
wherein the second opening is at a higher elevation than the first opening.

US Pat. No. 10,991,473

METHOD OF MANUFACTURING A NUCLEAR FUEL ASSEMBLY

THORIUM POWER, INC., McL...

1. A method of manufacturing a fuel assembly for use in a core of a nuclear power reactor, the method comprising:manufacturing each of a plurality of elongated fuel elements by:
mixing powdered fuel material with powdered metal non-fuel material, wherein the powdered fuel material comprises fissile material,
sintering the mixed powdered fuel material and metal non-fuel material to create a fuel core stock,
surrounding the fuel core stock with a cladding material, and
co-extruding the fuel core stock and cladding material to create the fuel element, the fuel element having a spirally twisted, multi-lobed profile that defines a plurality of spiral ribs, the multi-lobed profile comprising lobe tips and intersections between adjacent lobes, the cladding being thicker at the tips than at the intersections; and
mounting the plurality of elongated fuel elements to a frame of the fuel assembly,
wherein a moderator:fuel ratio in a region of the fuel elements defined by a shroud of the fuel assembly is 2.5 or less.

US Pat. No. 10,991,471

EMERGENCY CORE COOLING SYSTEM AND BOILING WATER REACTOR PLANT USING THE SAME

Kabushiki Kaisha Toshiba,...

1. An emergency core cooling system for a boiling water reactor plant, the plant including:a reactor pressure vessel containing a core
a containment vessel having:
a dry well containing the reactor pressure vessel,
a wet well containing a suppression pool in a lower part thereof, and a wet well gas phase in an upper part thereof,
a LOCA vent pipe connecting the dry well and the suppression pool,
an outer well disposed outside of the dry well and the wet well, adjacent to the dry well via a dry well common wall, and adjacent to the wet well via a wet well common wall, and
a scrubbing pool storing water, disposed in the outer well,
the emergency core cooling system comprising:
at least three active safety divisions each including only one motor-driven active safety system;
at least one passive safety division each including a passive safety system;
an emergency power source disposed in each of the active safety divisions to supply electric power to the motor-driven active safety system; and
the passive safety system including at least an advanced passive containment cooling system disposed in the passive safety division, wherein
only two active safety divisions out of the at least three active safety divisions each includes a low pressure flooder system that is also used as a residual heat removal system as the only one motor-driven active safety system,
the active safety divisions except for the only two active safety divisions, each of which includes the low pressure flooder system that is also used as the residual heat removal system, includes an air-cooled injection system as the only one motor-driven active safety system,
the air-cooled injection system includes:
a motor-driven pump;
a suction pipe providing water from the suppression pool to the motor-driven pump;
an injection pipe configured to inject water from the motor-driven pump into the reactor pressure vessel;
an air fin cooler having a fan and a tube bundle of cooling tubes, the fan being configured to blow external air to the tube bundle;
cooling water flowing in the cooling tubes;
a circulation pump to circulate the cooling water;
a circulation pipe configured to circulate the cooling water between the motor-driven pump and the air fin cooler to cool the motor-driven pump, and
the advanced passive containment cooling system being configured to be able to cool the containment vessel and satisfy N?2 safety criterion when a loss of coolant accident has occurred and the air-cooled injection system is activated considering a single failure for one of the residual heat removal system and on-line maintenance for the other residual heat removal system,
the advanced passive containment cooling system includes:
a cooling pool storing water, the cooling pool being disposed outside the containment vessel;
a heat exchanger including an inlet plenum, an outlet plenum and heat transfer tubes, at least part of the heat exchanger being submerged in the water in the cooling pool;
a gas supply pipe connected to the inlet plenum of the heat exchanger at one end and to a gas phase part of the containment vessel at another end, the gas supply pipe being configured to guide gases in the containment vessel into the heat exchanger;
a condensate return pipe connected to the outlet plenum of the heat exchanger at one end and to the containment vessel at another end, the condensate return pipe being configured to guide condensate in the heat exchanger into the containment vessel; and
a gas vent pipe connected to the outlet plenum of the heat exchanger at one end and submerged in the scrubbing pool in the outer well at another end, the gas vent pipe being configured to vent non-condensable gases in the heat exchanger into the outer well.

US Pat. No. 10,991,469

COOLING APPARATUS FOR MOLTEN CORE MATERIAL

KOREA ATOMIC ENERGY RESEA...

1. A cooling apparatus for a molten core material, comprising:two or more cooling material containers disposed under a reactor vessel including a nuclear reactor core, and including a cooling material therein;
a first screen disposed under the two or more cooling material containers and including two or more first through-holes;
a second screen disposed under the first screen and including two or more second through-holes; and
a third screen disposed under the second screen and including two or more third through-holes,
wherein an average size of the two or more first through-holes is greater than an average size of the two or more second through-holes,
wherein the average size of the two or more second through-holes is greater than an average size of the two or more third through-holes, and
wherein any two first through-holes among the two or more first through-holes have different sizes, any two second through-holes among the two or more second through-holes have different sizes, or any two third through-holes among the two or more third through-holes have different sizes.

US Pat. No. 10,991,468

LOAD-FOLLOWING NUCLEAR REACTOR SYSTEM USING THERMAL EXPANSION-BASED NEUTRON REFLECTOR MOVEMENT AND FUEL ASSEMBLY INTERVAL ADJUSTMENT MECHANISMS AND LIQUID METAL PRIMARY COOLANT

Clear Inc., Tokyo (JP)

1. A reduced size nuclear power generation system comprising:a reactor core including a plurality of fuel assemblies, wherein
each fuel assembly is formed from a plurality of fuel rods each prepared by enclosing a metallic fuel into a cladding tube, the metallic fuel containing one or both of
uranium (U)-235 and U-238, and
plutonium (Pu)-239;
a nuclear reactor vessel housing the reactor core;
a primary coolant including any one of metallic sodium (Na), lead (Pb), tin (Sn), and lead-bismuth (Pb—Bi), the primary coolant being put in the nuclear reactor vessel and heated by the reactor core;
a reduced size nuclear reactor including
a neutron reflector arranged around the reactor core in a surrounding fashion, and at least one of a neutron reflector movement mechanism and a fuel assembly interval adjustment mechanism, which are provided in order to control a nuclear reaction in the reactor core, wherein
the neutron reflector has neutron reflection efficiency which establishes a critical state in the core reactor while maintaining an effective multiplication factor of neutrons radiated from the reactor core equal to or above unity,
each of the neutron reflector movement mechanism and the fuel assembly interval adjustment mechanism includes a mechanism containing any of a liquid and a gas, which has a larger thermal expansion rate than that of the neutron reflector, and being configured to convert an amount of volume thermal expansion of any of the liquid and the gas into an amount of linear thermal expansion of any of the liquid and the gas,
the reflector movement mechanism is joined to the neutron reflector and configured to change an interval between the neutron reflector and the reactor core by a displacement attributed to the volume thermal expansion converted into the amount of linear thermal expansion corresponding to a temperature in the nuclear reactor vessel and thereby to change the neutron reflection efficiency,
the fuel assembly interval adjustment mechanism is joined to a member to set an interval between the plurality of fuel assemblies in the reactor core and configured to change the interval between the plurality of fuel assemblies by the displacement attributed to the volume thermal expansion converted into the amount of linear thermal expansion corresponding to the temperature in the nuclear reactor vessel and to change a neutron effective multiplication factor by using the changed interval, and
a load-following control depending on the temperature is enabled by at least one of the neutron reflector movement mechanism and the fuel assembly interval adjustment mechanism;
a secondary coolant;
a heat exchanger configured to perform heat exchange of heat of the primary coolant heated in the reactor core with the secondary coolant; and
a turbine power generation system configured to convert heat of the secondary coolant into electric power.

US Pat. No. 10,991,466

DISTRIBUTED CORRELATION AND ANALYSIS OF PATIENT THERAPY DATA

SAS INSTITUTE INC., Cary...

1. An apparatus comprising a processor component and a storage to store instructions that, when executed by the processor component, cause the processor component to:retrieve, from a diagnosis database, patient diagnosis records of a training set of patients and a testing set of patients;
for each patient diagnosis record associated with a patient of the training set or the testing set that includes at least one indication of a diagnosis made within a first time period, perform operations comprising:
generate a corresponding diagnosis group record;
correlate each diagnosis indicated in the patient diagnosis record as made within the first time period to a diagnosis group; and
for each diagnosis group correlated to at least one diagnosis indicated as made within the first time period, generate in the corresponding diagnosis group record an indication of at least one diagnosis in the diagnosis group made within the first time period;
retrieve, from a medication database, patient medication records of the training set and the testing set;
for each patient medication record associated with a patient of the training set or the testing set that includes at least one indication of at least one medication provided to the patient within a second time period, perform operations comprising:
generate a corresponding medication class record;
correlate each medication indicated in the patient medication record as provided to the patient within the second time period to a medication class; and
for each medication class correlated to at least one medication indicated as provided to the patient within the second time period, generate in the corresponding medication class record an indication of at least one medication in the medication class provided to the patient within the second time period;
for each patient of the training set of patients for which a corresponding diagnosis group record is generated and for which a corresponding medication class record is generated, identify at least one correlation between at least one diagnosis group and at least one medication class;
for each diagnosis group for which at least one correlation is identified, train a set of models that correlate the diagnosis group to at least one medication class based on the at least one identified correlation, wherein each model of the set of models comprises a neural network; and
for each patient of the testing set of patients for which a corresponding diagnosis group record is generated and for which a corresponding medication class record is generated, perform operations comprising:
employ each model of each set of models to make at least one prediction of at least one diagnosis group as indicated in the corresponding diagnosis group record based on at least one medication class indicated in the corresponding medication class record;
compare the at least one prediction to the corresponding diagnosis group record to derive a tally of at least one of true positives or false positives for each prediction; and
for each diagnosis group for which a set of models is trained, select one model of the set of models based on the tally of at least one of true positives or false positives of each model of the set of models.

US Pat. No. 10,991,465

SYSTEMS AND METHODS FOR PERFORMING COMPUTER-SIMULATED EVALUATION OF TREATMENTS ON A TARGET POPULATION

HeartFlow, Inc., Redwood...

1. A computer-implemented method for performing computer-simulated evaluation of treatments, the method comprising:for each of a plurality of patients, receiving one or more patient-specific anatomical and/or physiological models, the one or more patient-specific models including a model of at least a portion of a vasculature of the respective patient;
selecting, from the plurality of patients, a set of patients that have one or more common characteristics;
identifying an experimental group of patients from the set of patients;
for each patient in the experimental group,
modifying at least one model of the respective one or more patient-specific models to obtain at least one modified patient-specific model that models an effect of an evaluation treatment on the respective patient, and
calculating a value of an evaluation endpoint based on the respective at least one modified patient-specific model, the evaluation endpoint being indicative of a health or medical characteristic of a patient; and
comparing the calculated values of the evaluation endpoint with one or more control values of the evaluation endpoint for patients that satisfy the one or more selection criterion.

US Pat. No. 10,991,464

CARDIAC MAPPING SYSTEM AND METHOD FOR VOLTAGE-BASED EVALUATION OF ELECTROGRAMS

St. Jude Medical, Cardiol...

1. A computer implemented method for evaluating an electrogram containing a plurality of data samples each having a voltage, the computer implemented method comprising:selecting an activity interval for the electrogram;
defining a plurality of windows, each window of the plurality of windows being a length of time defined by the activity interval;
calculating respective energy levels for each window of the plurality of windows of the electrogram;
defining a first bin and a second bin;
assigning the respective energy levels and corresponding windows to one of the first bin and the second bin;
calculating a value based on a ratio of the respective energy levels in the first bin to a total number of the plurality of windows;
mapping the value to a three dimensional map of a heart; and
presenting the map to a user on a display to indicate fractionation of the electrogram.

US Pat. No. 10,991,463

COMPUTER-IMPLEMENTED SYSTEM AND METHODS FOR PREDICTING THE HEALTH AND THERAPEUTIC BEHAVIOR OF INDIVIDUALS USING ARTIFICIAL INTELLIGENCE, SMART CONTRACTS AND BLOCKCHAIN

1. A method for making artificial intelligence based medical treatment plan recommendations comprising the steps of:providing an electronic device including a processor and an artificial intelligence system;
storing healthcare data of a patient in a blockchain database, wherein the healthcare data of the patient includes one or more existing conditions and one or more conditions not previously present in a therapy regime of the patient, one or more limiting factors, and a compliance record for the existing condition;
wherein the one or more limiting factors includes existing drugs and therapies of the patient, lifestyle behaviors of the patient, and any other information which limits the ability of the patient to access or complete a therapy;
retrieving the healthcare data of the patient from the blockchain database;
the artificial intelligence system determining a therapeutic behavior pattern of the patient utilizing a combination of the compliance record for the existing condition and the one or more limiting factors;
the artificial intelligence system determining one or more therapies for the one or more conditions not previously present in the therapy regime of the patient based on the healthcare data of the patient;
the artificial intelligence system ranking the one or more therapies based on the likelihood of the therapy treating the one or more existing conditions and the one or more conditions not previously present in the therapy regime of the patient based on the compliance record and the one or more limiting factors;
the artificial intelligence system determining one or more cost quotes for the one or more therapies and displaying the one or more cost quotes;
receiving selection of a not yet implemented therapy and a cost quote for the selected not yet implemented therapy by a user;
the blockchain database creating a smart contract for the execution of the selected not yet implemented therapy;
one or more parts of the healthcare data of the patient being allocated for viewing by one or more healthcare providers at the onset of a medical care visit;
updating the healthcare data of the patient on the blockchain database with health records and service notes from the medical care visit; and
automatically transferring payment according to the terms of the smart contract to a healthcare provider in the form of a native cryptocurrency immediately at the completion of the medical visit.

US Pat. No. 10,991,462

SYSTEM AND METHOD OF CONTROLLING EXTERNAL APPARATUS CONNECTED WITH DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A method for controlling one or more external apparatuses, the method being performed by a mobile device and comprising:obtaining an input command of a user;
identifying the one or more external apparatuses communicable with and controllable by the mobile device, from a plurality of external apparatuses;
providing the input command and apparatus information of the one or more external apparatuses, to a server;
receiving, from the server, a control information for controlling a first external apparatus among the one or more external apparatuses, the control information being generated based on whether a control condition for controlling the first external apparatus is satisfied;
determining whether the control condition is satisfied based on the received control information; and
transmitting a control command to the first external apparatus based on the determination,
wherein the control condition for allowing a user-desired operation to be performed according to a user's intention is determined based on the apparatus information and the user's intention, and the user's intention is determined in consideration of the input command.

US Pat. No. 10,991,461

ASSESSING THE CURRENT STATE OF A PHYSICAL AREA OF A HEALTHCARE FACILITY USING IMAGE ANALYSIS

General Electric Company,...

1. A system, comprising:a memory that stores computer executable components;
a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise:
an environment recognition component configured to identify an area of a healthcare facility included in image data captured of the healthcare facility;
an environment characterization component configured to identify medical resources included in the area based on the image data, wherein the medical resources comprise one or more medical supplies;
an environment assessment component configured to determine resource utilization information associated with usage of the medical resources at the healthcare facility and cost information regarding costs associated with the usage, wherein the resource utilization information comprises supply usage information regarding usage of the one or more medical supplies, and wherein the cost information comprises supply cost information associated with the usage of the one or more medical supplies,
wherein the supply usage information identifies a clinical success rate associated with usage of a first medical supply of the one or more medical supplies and a second clinical success rate associated with usage of an alternative medical supply; and
an augmented reality component configured to generate and display overlay data comprising the resource utilization information and the cost information for projection on a display of a device over a current view of the area as viewed on or through the display.

US Pat. No. 10,991,460

METHOD AND SYSTEM FOR IDENTIFICATION OF CEREBROVASCULAR ABNORMALITIES

NEUROANALYTICS PTY LTD., ...

1. A method for identifying cerebrovascular abnormalities in a cerebral region of a subject, the method comprising:extracting one or more CNN features of the circulatory system in the cerebral region using a virtual representation of the cerebral region;
grouping, based on the CNN features, the circulatory system in the cerebral region into a blood vessel type and a non-blood vessel type;
deriving one or more additional features associated with the blood vessels;
classifying each point of the blood vessel into one of a non-branching, diverging and converging type using a graph convolution network;
selecting a region of interest in the virtual representation of the cerebral region, wherein the region of interest comprises the one or more points of the blood vessel; and
identifying the cerebrovascular abnormalities using the extracted one or more features associated with the blood vessel or the classification of the blood vessel or both at the region of interest.

US Pat. No. 10,991,459

PERFORMANCE MONITORING SYSTEMS AND METHODS

adidas AG, Herzogenaurac...

1. A method of conducting a fitness activity challenge comprising:collecting first electronic fitness data related to a first fitness activity on a portable electronic device, the portable electronic device including a microprocessor, a display screen, a user input, a satellite positioning system receiver, and a wireless communication transceiver;
collecting second electronic fitness data related to a second fitness activity on a second portable electronic device, the second portable electronic device including a microprocessor, a display screen, a user input, a satellite positioning system receiver, and a wireless communication transceiver;
generating comparison data by comparing the first electronic fitness data and the second electronic fitness data, wherein the comparison data comprises relative positions of the portable electronic device and the second portable electronic device as determined by the satellite positioning system receivers of the respective portable electronic device and second portable electronic device; and
displaying the comparison data on the display screen of the portable electronic device during the first fitness activity.

US Pat. No. 10,991,458

SYSTEM AND METHOD FOR DETECTING ACTIVATION OF A MEDICAL DELIVERY DEVICE

AMGEN INC., Thousand Oak...

1. A system for determining that a medical delivery device capable of administering a medication to a patient has been activated, the system comprising at least an electronic device, the electronic device comprising:an image sensor configured to capture images; and
a user interface configured to display content,
the system further comprising:
one or more processors adapted to interface with the image sensor and the user interface, wherein the one or more processors are configured to:
receive a first set of image data from the image sensor,
analyze the first set of image data to determine that a medical delivery device is ready to deliver the medication to the patient, wherein the medical delivery device is one of an autoinjector, an on-body injector, an inhaler, a drip chamber, an eye dropper, a nasal spray, or a nebulizer,
receive a second set of image data from the image sensor,
analyze the second set of image data to detect a characteristic of the medical delivery device indicative that the medical delivery device has been activated, wherein the characteristic of the medical delivery device is at least one of a characteristic of a needle shield, a characteristic of a chamber that stores the medication, a shape of the medical delivery device, a characteristic of an activation button, a characteristic of a safety feature, or a component that becomes exposed upon activation of the medical delivery device,
cause the user interface to indicate that the medical delivery device has been activated, and
cause a remote server to update a medical record corresponding to the patient.

US Pat. No. 10,991,457

HEALTHCARE COVERAGE MATCHING AND VERIFICATION

HEALTH MANAGEMENT SYSTEMS...

1. A system for facilitating processing of medical information, comprising:a frontend graphical user interface (GUI) to receive a healthcare coverage application comprising client demographics that include at least two of the following: a last name, a first name, a birthdate, an identification number, an address and a request type associated with a client;
a first processor communicatively coupled to the frontend GUI; and
a second processor communicatively coupled to the frontend GUI,
wherein a matching component is implemented in the first processor and configured to process the client demographics in the healthcare coverage application, access an eligibility database using a lightweight data-interchange format and determine, based on a first set of criteria, a matching database record that corresponds to the healthcare coverage application,
wherein a verification component is implemented in the second processor and configured to communicate with a healthcare provider using electronic data interchange (EDI) transactions, identify, based on a second set of criteria, a medical policy that corresponds to the matching database record, and verify the medical policy in a verification database,
wherein the matching component and the verification component are implemented as separate and independently configurable components to enable their separate and concurrent usage, and are communicatively connected to the frontend GUI in a parallel configuration,
wherein the verification component processes a first request at substantially same time as the matching component processes a second request that is subsequent to the first request, and
wherein the frontend GUI, the matching component and the verification component are enabled to asynchronously access their respective databases.

US Pat. No. 10,991,447

CLOCK FREQUENCY COUNTING DURING HIGH-VOLTAGE OPERATIONS FOR IMMEDIATE LEAKAGE DETECTION AND RESPONSE

SanDisk Technologies LLC,...

1. A method for detecting faults in a memory system, the method comprising:performing an operation on at least one memory cell of the memory system, wherein the operation is defined as having a voltage source from a charge pump, and during performance of the operation:
receiving a first clock cycle count for a first pulse of the charge pump associated with the at least one memory cell, and storing the first clock cycle count in a first register,
transferring the first clock cycle count from the first register to a second register and storing the first clock cycle count in the second register,
receiving a second clock cycle count for a second pulse of the charge pump, and storing the second clock cycle count in the first register, and
determining whether a fault will occur based on a difference between the first clock cycle count and the second clock cycle count.

US Pat. No. 10,991,445

MEMORY SUB-SYSTEM INCLUDING AN IN-PACKAGE SEQUENCER TO PERFORM ERROR CORRECTION AND MEMORY TESTING OPERATIONS

Micron Technology, Inc., ...

1. A method comprising:transmitting, by a sequencer component, a notification to a controller that indicates that the sequencer component includes functionality to perform an error correction operation to cause the controller to transmit data comprising raw data to the sequencer component that is external to the controller without performing an encoding operation on the raw data at the controller;
receiving, by a processing device of the sequencer component, the data from the controller that is external to the sequencer component, wherein the sequencer component resides in a package that is separate from the controller;
performing, by the processing device of the sequencer component, the error correction operation on the data received from the controller that is external to the sequencer component to generate a code word associated with the data; and
storing the code word at a memory component coupled with the sequencer component.

US Pat. No. 10,991,444

TIERED READ REFERENCE CALIBRATION

Western Digital Technolog...

1. An apparatus, comprising:a first semiconductor die comprising non-volatile memory cells and a first plurality of pathways; and
a second semiconductor die comprising one or more control circuits and a second plurality of pathways, wherein the one or more control circuits are configured to transfer signals through pathway pairs of the first plurality of pathways and the second plurality of pathways, wherein the one or more control circuits are further configured to:
read data in the non-volatile memory cells using read reference voltages, wherein the one or more control circuits are configured to receive the data in parallel from the first semiconductor die through the second plurality of pathways;
calibrate read reference voltages for reading the non-volatile memory cells; and
use the calibrated read reference voltages to read data in the non-volatile memory cells.

US Pat. No. 10,991,443

MEMORY APPARATUS AND DATA READ METHOD

TOSHIBA MEMORY CORPORATIO...

1. A memory apparatus, comprising:a nonvolatile semiconductor memory device;
an error correction circuit configured to
perform error detection in first data on a processing unit size basis, and
perform error correction on the first data in response to its necessity;
a memory circuit configured to store second data on the processing unit size basis;
a data distribution circuit configured to:
transfer third data read from the nonvolatile semiconductor memory device to the error correction circuit as the first data and
transfer the third data to the memory circuit as the second data on the processing unit size basis; and
a processing circuit configured to read the second data from the memory circuit and process the second data in response to the error correction circuit detecting an uncorrectable error in the first data.

US Pat. No. 10,991,442

MEMORY DEVICE WITH A FUSE PROTECTION CIRCUIT

Taiwan Semiconductor Manu...

1. A fuse protection circuit comprising:detection circuitry; and
protection circuitry configured to protect a memory circuit by coupling one of a supply line and a program line to a ground when the detection circuitry senses an electro-static discharge (ESD) current, where the ESD current flows through the other of the supply line and the program line.

US Pat. No. 10,991,441

ERASE-WRITE CYCLING METHOD OF A FLASH DEVICE

Shanghai Huali Microelect...

1. A flash device endurance test method, wherein the method comprises at least the following steps:step 1: providing a flash device to be tested, the flash device comprising a plurality of memory cells, wherein the memory cells are first to fourth memory cells, the plurality of memory cells comprising multiple ports of a same test condition or of different test conditions;
step 2: connecting the ports of the same test condition to a same pulse generation unit, and connecting the ports of the different test conditions to different pulse generation units, wherein the multiple ports comprise: a CG1 terminal formed by a connection between control gates of the first and second memory cells; a CG2 terminal formed by a connection between control gates of the third and fourth memory cells; an SG1 terminal formed by a connection between selective gates of the first and second memory cells; an SG2 terminal formed by a connection between selective gates of the third and fourth memory cells; a CSL terminal formed by a connection between source terminals of the first to fourth memory cells; a BL1 terminal formed by a connection between drain terminals of the first and third memory cells; a BL2 terminal formed by a connection between drain terminals of the second and fourth memory cells; and a PW terminal formed by a connection between P-well terminals of the third and fourth memory cells,
wherein the SG1 terminal and the SG2 terminal are connected to a first same pulse generation unit the PW terminal, the CG2 terminal, the BL1 terminal, and the CSL terminal are connected to a second same pulse generation unit and the CG1 terminal and the BL2 terminal are connected to the different pulse generation units;
step 3: generating, by the pulse generation units in step 2, synchronous pulse voltage signals of N cycles, wherein one time of erasing-writing of the flash device is considered to be one of the cycles; and
step 4: testing threshold voltages of erasing and writing states of the flash device in each cycle.

US Pat. No. 10,991,440

PERFORMING READ OPERATION PRIOR TO TWO-PASS PROGRAMMING OF STORAGE SYSTEM

Micron Technology, Inc., ...

1. A system comprising:a memory; and
a processing device, operatively coupled with the memory, to:
read data from a first portion of a memory cell of a plurality of memory cells;
perform a first programming pass on another memory cell of the plurality of memory cells by providing new data to the another memory cell; and
perform a second programming pass on the memory cell by providing additional data to the first portion of the memory cell based on the reading of the data from the first portion of the memory cell, wherein the first programming pass and the second programming pass correspond to a two-pass programming operation associated with the plurality of memory cells.

US Pat. No. 10,991,439

MEMORY DEVICE AND AN OPERATING METHOD OF A MEMORY DEVICE

SK hynix Inc., Icheon-si...

1. A method for operating a memory device, the method comprising:performing an erase voltage application operation of erasing memory cells by applying an erase voltage to a source line of a memory block;
performing a first erase verify operation of determining whether a threshold voltage of the memory cells is lower than a first erase verify voltage;
when it is determined that the first erase verify operation of the memory blocks has been passed, performing a second erase verify operation of determining whether the threshold voltage of the memory cells is higher than a second erase verify voltage; and
when it is determined that the second erase verify operation of the memory cells has been passed, setting a last reset erase voltage as a start erase voltage,
wherein the first erase verify operation is performed in a unit of a plurality of memory blocks and the second verify operation is performed in a unit of a plurality of physical pages.

US Pat. No. 10,991,438

METHOD AND MEMORY USED FOR REDUCING PROGRAM DISTURBANCE BY ADJUSTING VOLTAGE OF DUMMY WORD LINE

Yangtze Memory Technologi...

1. A method for reducing program disturbance of a memory, the memory comprising an upper deck and a lower deck, the upper deck being formed above the lower deck, the upper deck comprising a first upper dummy word line, the lower deck comprising a first lower dummy word line, the method comprising:adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and
adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

US Pat. No. 10,991,437

SEMICONDUCTOR MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND MEMORY SYSTEM

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:an internal voltage supplier configured to supply an internal power supply voltage to be used for an operation of the semiconductor device;
a voltage level controller configured to control the internal voltage supplier;
a memory cell array including a plurality of memory cells; and
a peripheral circuit configured to perform an operation for the memory cell array,
wherein the voltage level controller is configured to determine whether a voltage level change condition of the semiconductor device is satisfied and configured to control the internal voltage supplier to change a voltage level of the internal power supply voltage based on a result of the determining, and
wherein the voltage level controller comprises:
a command input circuit configured to receive a command to control the operation of the semiconductor device;
a sub-operation control signal generator configured to generate a plurality of sub-operation control signals to control the peripheral circuit to perform a plurality of sub-operations corresponding to the command;
a set value storage configured to store a plurality of set values to be used for the operation of the semiconductor device;
a voltage control condition storage configured to store at least one condition, the at least one condition with ability to change the voltage level of the internal power supply voltage; and
a voltage control signal generator configured to determine whether the at least one condition is satisfied based on the plurality of sub-operation control signals, the plurality of set values, and the command.

US Pat. No. 10,991,436

DYNAMIC DELAY OF NAND READ COMMANDS

Micron Technology, Inc., ...

17. A non-transitory machine-readable medium for increasing a probability of a parallel read within a memory die of a non-volatile memory device, the machine-readable medium storing instructions, which when executed by a machine, causes the machine to perform operations comprising:receiving a first read command requesting data stored on a first plane of a first die of the memory device;
determining that a second read command for a second plane of the first die is not awaiting execution;
responsive to determining that a second read command for the second plane of the first die is not awaiting execution, delaying execution of the first read command and setting a timer for a delay time period;
receiving, prior to expiry of the timer, a second read command requesting data stored on the second plane of the first die of the memory device; and
responsive to receiving a second host read command, causing execution of the first read command and the second read command in parallel.

US Pat. No. 10,991,435

VERTICAL FLASH MEMORY CELL WITH SELECTOR FOR FAST READ

Intel Corporation, Santa...

1. A memory cell comprising:a vertical flash transistor further comprising a metal gate node, a semiconductor layer, a source node electrically coupled to said semiconductor layer and a drain node electrically coupled to said semiconductor layer;
a first two-terminal selector device, said first two-terminal selector device having a voltage-dependent resistance that changes in response to a channel resistance of said vertical flash transistor, wherein a first terminal of said first two-terminal selector device is electrically coupled to said drain node of said vertical flash transistor; and
a second two-terminal selector device, said second two-terminal selector device having a voltage-dependent resistance that changes in response to a channel resistance of said vertical flash transistor, wherein a first terminal of said second two-terminal selector device is electrically coupled to said source node of said vertical flash transistor;
wherein said memory cell is configured to operate in one of an ON-state and an OFF-state by modulating said channel resistance of said vertical flash transistor.

US Pat. No. 10,991,434

SERIAL INTERFACE CIRCUIT, SEMICONDUCTOR DEVICE AND SERIAL-PARALLEL CONVERSION METHOD

LAPIS Semiconductor Co., ...

1. A serial interface circuit receiving a serial signal, which includes a bit string in a serial form, and converting the bit string included in the serial signal into a parallel form to obtain a parallel bit group, the serial interface circuit comprising:a timing signal generation part generating first to nth timing signals respectively indicating timings that differ by 1 bit cycle of the bit string, wherein n is an integer equal to or greater than 2;
a first conversion part holding each bit in the bit string included in the serial signal at timings of first to tth timing signals among the first to nth timing signals and outputting a held bit group as a standby bit group, wherein t is an integer less than n;
a standby output part acquiring the standby bit group at a timing of any one of (t+1)th to nth timing signals among the first to nth timing signals and outputting the acquired standby bit group as a part of the parallel bit group; and
a second conversion part holding each bit in the bit string included in the serial signal at timings of the (t+1)th to nth timing signals and outputting a held bit group as an other part of the parallel bit group.

US Pat. No. 10,991,433

METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY BY LIMITING TIME GAP BETWEEN ERASE AND PROGRAM

Silicon Storage Technolog...

1. A memory device comprising:a plurality of non-volatile memory cells;
a controller configured to:
receive a first command for erasing and programming a first group of the memory cells,
determine that the first group of the memory cells can be programmed within substantially 10 seconds of erasure of the first group of the memory cells,
erase the first group of memory cells in a group erase operation,
program the first group of memory cells within substantially 10 seconds of the group erase operation,
receive a second command for erasing and programming a second group of the memory cells,
determine that the second group of the memory cells cannot be programmed within substantially 10 seconds of erasure of the second group of the memory cells,
divide the second group of the memory cells into a plurality of subgroups of the memory cells, wherein each one of the subgroups can be programmed within substantially 10 seconds of erasure of the respective one subgroup of the memory cells, and
for each of the subgroups of the memory cells:
erase the subgroup of memory cells in a subgroup erase operation, and
program the subgroup of memory cells within substantially 10 seconds of the subgroup erase operation.

US Pat. No. 10,991,432

STORAGE DEVICE AND METHOD OF OPERATING THE SAME

SK hynix Inc., Icheon-si...

1. A method of operating a memory device configured to perform a program operation on a first memory cell coupled to a selected word line, the method comprising:determining, after the program operation on the first memory cell has been performed, whether a threshold voltage of a second memory cell coupled to a same bit line to which the first memory cell is coupled to a word line adjacent to the selected word line corresponds to an erased status; and
applying to the first memory cell, when the threshold voltage of the second memory cell corresponds to the erased status, an additional program voltage higher by a preset voltage than a program voltage last applied during the program operation.

US Pat. No. 10,991,431

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a first wiring;
a first memory transistor connected to the first wiring;
a first transistor connected between the first wiring and the first memory transistor;
a second transistor connected between the first wiring and the first transistor;
a second wiring connected to a gate electrode of the first memory transistor;
a third wiring connected to a gate electrode of the first transistor;
a fourth wiring connected to a gate electrode of the second transistor; and
a control circuit configured to execute an erase operation that erases data of the first memory transistor; wherein
from a first timing of the erase operation to a second timing after the first timing, the control circuit:
maintains a voltage difference between the first wiring and the third wiring at a predetermined value;
maintains a voltage difference between the third wiring and the fourth wiring at a predetermined value;
controls a voltage of the first wiring to become larger than a voltage of the third wiring;
controls the voltage of the third wiring to become larger than a voltage of the fourth wiring; and
controls a timing from which the voltage of the third wiring increases from an initial voltage to become different from a timing from which the voltage of the fourth wiring increases from the initial voltage.

US Pat. No. 10,991,430

NON-VOLATILE MEMORY CELL COMPLIANT TO A NEAR MEMORY COMPUTATION SYSTEM

eMemory Technology Inc., ...

1. A non-volatile memory cell comprising:a storage transistor having a first terminal, a second terminal, and a gate terminal;
wherein during a program operation:
the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell;
the second terminal of the storage transistor is floating;
the gate terminal of the storage transistor is coupled to a program voltage; and
the program voltage is greater than the data voltage;
wherein during a read operation:
the first terminal of the storage transistor receives a read voltage;
the gate terminal of the storage transistor is coupled to a bias voltage; and
the second terminal of the storage transistor outputs a weighting voltage;
wherein the program voltage is greater than the read voltage, and the read voltage is greater than the bias voltage.

US Pat. No. 10,991,429

WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY

SANDISK TECHNOLOGIES LLC,...

1. A memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory stack structures comprising blocks of memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel, and the electrically conductive layers comprise word lines for the memory stack structures;
a word line decoder circuitry including switches for activating a respective word line for the memory stack structures, and located underneath the array of memory stack structures and above the substrate;
a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure electrically contacting a node of a respective device in the word line decoder circuitry;
bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures; and
upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers;
wherein each electrically conductive layer includes a respective number of holes therethrough within each block of memory stack structures, and wherein the respective number of holes for a given electrically conductive layer is the same as a total number of electrically conductive layers underlying the given electrically conductive layer.

US Pat. No. 10,991,428

TERNARY CONTENT ADDRESSABLE MEMORY

INTERNATIONAL BUSINESS MA...

1. A memory architecture comprising:one or more ternary content addressable memory (TCAM) fields;
a plurality of match lines ML1 . . . MLn; and
control logic that scores a closeness of a match between bits as a weighted percentage as applied to each TCAM field,
wherein the control logic merges records on individual match lines of the plurality of match lines ML1 . . . MLn using wildcards to accumulate context with associated pointers from the merged match lines to an original record.

US Pat. No. 10,991,427

MEMORY PROGRAMMING METHODS AND MEMORY SYSTEMS

Micron Technology, Inc., ...

1. A memory system comprising:a plurality of memory cells individually comprising:
a memory element configured to have a plurality of different memory states at a plurality of different moments in time;
first and second electrodes configured to apply a plurality of different voltage potentials across the memory element of the respective memory cell to change the memory element of the respective memory cell from a first of the memory states to a second of the memory states; and
a plurality of access devices configured to apply different bias voltages to the second electrodes of respective ones of the memory cells during the application of the voltage potentials across the memory elements of the respective memory cells.

US Pat. No. 10,991,426

MEMORY DEVICE CURRENT LIMITER

TAIWAN SEMICONDUCTOR MANU...

1. A memory device, comprising:a memory array including a plurality of memory cells arranged in rows and columns;
a closed loop bias generator configured to output a column select signal to the memory array;
a current limiter configured to receive an output of the closed loop bias generator, the current limiter coupled to a plurality of the columns of the memory array and comprising a cascode of first and second connected NMOS transistors; and
wherein the closed loop bias generator is further configured to clamp a drain-source voltage of the second NMOS transistor of the current limiter.

US Pat. No. 10,991,425

ACCESS LINE GRAIN MODULATION IN A MEMORY DEVICE

Micron Technology, Inc., ...

1. A method, comprising:forming a set of materials for memory cell stacks in a cross-point memory array
forming, above the set of materials, a barrier material;
planarizing a top surface of the barrier material; and
forming, after planarizing the top surface and above the planarized top surface of the barrier material, a metal layer for an access line of the cross-point memory array.

US Pat. No. 10,991,424

ELECTRONIC DEVICE, MEMORY DEVICE, AND METHOD OF OPERATING MEMORY DEVICE

SK hynix Inc., Icheon (K...

1. An electronic device including a memory device and a memory controller configured to control the memory device, the memory device comprising:a memory cell array including a variable resistance memory cell coupled to and disposed between a first conductive line and a second conductive line that intersect with each other; and
a peripheral circuit configured to provide a write pulse or a read pulse to the variable resistance memory cell through the first conductive line,
wherein the peripheral circuit controls the write pulse to have one of a first polarity and a second polarity that are opposite to each other, and controls the read pulse to have a polarity corresponding to a greater value of first and second amorphization start current values of the variable resistance memory cell, the first amorphization start current value being determined by a first write pulse having the first polarity, the second amorphization start current value being determined by a second write pulse having the second polarity.

US Pat. No. 10,991,423

FLYING AND TWISTED BIT LINE ARCHITECTURE FOR DUAL-PORT STATIC RANDOM-ACCESS MEMORY (DP SRAM)

Taiwan Semiconductor Manu...

1. A memory device comprising:an array of memory cells comprising a first subarray and a second subarray;
a first bit line extending along a column of the array, from a first end of the column, and terminating between the first and second subarrays, wherein the first bit line is electrically coupled to memory cells of the first subarray, but not the second subarray, in the column;
a second bit line extending along the column, from the first end of the column to a second end of the column opposite the first end, wherein the second bit line is electrically coupled to memory cells of the second subarray, but not the first subarray, in the column;
a first multiplexer electrically coupled to the first and second bit lines; and
a third bit line extending along the column, from the first end of the column, and terminating between the first and second subarrays, wherein the third bit line is electrically coupled to the memory cells of the first subarray, but not the second subarray, in the column.

US Pat. No. 10,991,422

DATA STORAGE DEVICE USING A HOST MEMORY BUFFER FOR SINGLE-LEVEL CELL STORAGE AND CONTROL METHOD FOR NON-VOLATILE MEMORY

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:a non-volatile memory, having single-level cells and multi-level cells; and
a controller, operating the non-volatile memory as requested by a host,
wherein:
the controller requests the host to allocate a system memory of the host to provide a host memory buffer;
the controller temporarily stores write data issued by the host in the host memory buffer;
the controller flushes the write data temporarily stored in the host memory buffer to the multi-level cells of the non-volatile memory without passing the single-level cells of the non-volatile memory;
the controller manages a mapping table to record logical addresses of data stored in the different memory cells of the host memory buffer;
according to a logical address of the write data, the controller searches the mapping table; and
when the logical address of the write data has been recorded in the mapping table, the controller uses the write data to overwrite a space in the host memory buffer that stores an old data version of the logical address.

US Pat. No. 10,991,421

COMPLEMENTARY DUAL-MODULAR REDUNDANCY MEMORY CELL

Bar-Ilan University, Ram...

1. A memory cell, comprising:a data write input, configured to input data levels for storing in said memory cell;
a data read output;
an indicator output;
a first bitcell connected to said data write input and said data read output, configured to store a first data level input from said data write input and to output a first read data level to said data read output; and
a second bitcell connected to said data write input, configured to store a second data level input from said data write input to output a second read data level; and
a comparator associated with said first bitcell, said second bitcell and said indicator output, configured to compare a data level read from said first bitcell and a data level read from said second bitcell and to provide, at said indicator output, an indicator when said first read data level and said second read data level are non-complementary,
wherein said first bitcell comprises a write transistor and a read transistor, and wherein: a first diffusion connection of said write transistor is connected to said data write input, a gate connection of said write transistor is connected to a write trigger input, a first diffusion connection of said write transistor is connected to a first comparator input, a second diffusion connection of said write transistor is connected to a write trigger input, and a second diffusion connection of said write transistor is connected to a gate connection of said read transistor to form a first storage node; and
said second bitcell comprises a write transistor and a read transistor, and wherein: a first diffusion connection of said write transistor is connected to said data write input, a gate connection of said write transistor is connected to said write trigger input, a first diffusion connection of said write transistor is connected to a second comparator input, a second diffusion connection of said write transistor connected to said write trigger input, and a second diffusion connection of said write transistor is connected to a gate connection of said read transistor to form a second storage node.

US Pat. No. 10,991,420

SEMICONDUCTOR DEVICE INCLUDING DISTRIBUTED WRITE DRIVING ARRANGEMENT AND METHOD OF OPERATING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor memory device comprising:a column of segments, each segment including bit cells;
a local write bit (LWB) line;
a local write bit_bar (LWB_bar) line;
a global write bit (GWB) line;
a global write bit_bar (GWBL_bar) line;
each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and
a distributed write driving arrangement including:
a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and
a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and
wherein:
the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line;
maximum speed is a parameter representing maximum operational speed of a corresponding circuit;
footprint is a parameter representing an area consumed by a corresponding circuit; and
the local write driver and the global write driver are configured so as to correspondingly exhibit one of the following descriptions:
the local write driver is configured for substantially the same maximum speed as compared to the global write driver, and the local write driver is configured with substantially the same footprint as compared to the global write driver; or
the local write driver is configured for a lower maximum speed as compared to the global write driver, and the local write driver is configured with a smaller footprint as compared to the global write driver.

US Pat. No. 10,991,419

SEMICONDUCTOR DEVICES AND METHODS OF HANDLING DATA LIFETIME CODES USED THEREIN

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a code comparison circuit configured to compare an output code generated based on a command with a set code to generate a detection signal controlling a predetermined operation; and
a code adjuster configured to adjust the output code in response to the detection signal to generate an adjustment code, wherein the code adjuster counts down the output code to generate the adjustment code if the detection signal is enabled.

US Pat. No. 10,991,418

SEMICONDUCTOR MEMORY DEVICE COMPRISING AN INTERFACE CONFORMING TO JEDEC STANDARD AND CONTROL DEVICE THEREFOR

ZENTEL JAPAN CORPORATION,...

1. A control device for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the semiconductor memory device comprising:a plurality of banks, connected to one another by an internal data bus, and each bank being separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, each bank comprising a plurality of subarrays, and each subarray comprising a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines;
a read/write control circuit, controlling reading of data from the semiconductor memory device and writing of data to the semiconductor memory device; and
a transfer control circuit, controlling data transfer inside the semiconductor memory device and setting to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface;
wherein the transfer command comprises a word line activation command for activating a word line without activating the sense amplifiers, and the transfer control circuit invalidates a ZQ calibration command of the JEDEC standard, and sets a bit value assigned to the ZQ calibration command to be usable as a bit value of the word line activation command.

US Pat. No. 10,991,417

AUTO-PRECHARGE MANAGEMENT IN A CONTROLLER

XILINX, INC., San Jose, ...

1. A system comprising:a plurality of masters configured to issue transactions to access a memory component, wherein each master of the plurality of masters is associated with a different thread, and wherein the memory component includes a plurality of rows;
a queue configured to receive the transactions from the plurality of masters; and
a controller configured to issue a command to access a row of the plurality of rows in response to receiving a first issued transaction of the issued transactions, wherein the first issued transaction is issued by a first master of the plurality of masters,
and wherein the controller is further configured to issue an auto-precharge command to close the row associated with the first issued transaction if the queue includes no more transactions for a bank associated with the row,
and wherein the controller is further configured to prevent issuing an auto-precharge command to keep the row associated with the first issued transaction open if a second issued transaction in the queue, subsequent to the first issued transaction, is from a master that is different from the first master and if the controller receives data associated with keeping the row associated with the first issued transaction open.

US Pat. No. 10,991,416

CAPACITANCE-BASED COMPENSATION CIRCUITRY

Micron Technology, Inc., ...

1. A device, comprising:compensation circuitry characterized by a capacitance applied to a clocking signal to generate a compensated clocking signal; and
first logic circuitry configured to:
receive a first transition of the clocking signal from an external processor, wherein the clocking signal comprises the first transition and subsequent transitions between a logic low threshold voltage and a logic high threshold voltage; and
output an enable signal to the compensation circuitry in response to receiving the first transition, wherein the compensation circuitry is configured to apply the capacitance in response to receiving the enable signal to the subsequent transitions of the clocking signal after the first transition of the clocking signal to generate the compensated clocking signal.

US Pat. No. 10,991,415

SEMICONDUCTOR DEVICE PERFORMING IMPLICIT PRECHARGE OPERATION

Micron Tehcnology, Inc., ...

1. An apparatus comprising:a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and
a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.

US Pat. No. 10,991,414

GRANULAR REFRESH RATE CONTROL FOR MEMORY DEVICES BASED ON BIT POSITION

Western Digital Technolog...

1. A method comprising:storing each bit of a B-bit word in a different sub-array of a memory device, wherein each of the bits is associated with a bit position in the B-bit word and each of the bits is stored in a respective sub-array according to its respective bit position with the most significant bit in a first sub-array and the least significant bit in a second sub-array, and wherein the memory device comprises a plurality of sub-arrays;
determining a refresh interval for a plurality of the bit positions including a first refresh interval for the most significant bit and a second refresh interval for the least significant bit based upon a relative importance of the plurality of the bit positions to a performance of a machine learning or signal processing task involving the B-bit word, wherein the refresh interval is based upon a fidelity metric and a resource metric, the first refresh interval is shorter than the second refresh interval;
refreshing the plurality of sub-arrays based upon the refresh interval determined for the plurality of bit positions, wherein refreshing an individual sub-array of the plurality of sub-arrays includes reading data from memory cells of the individual sub-array and writing the data back to the memory cells; and
dynamically updating the refresh interval for the plurality of bit positions upon receiving a new fidelity metric or a new resource metric.

US Pat. No. 10,991,413

MEMORY WITH PROGRAMMABLE DIE REFRESH STAGGER

Micron Technology, Inc., ...

1. A memory system, comprising:a plurality of memory devices, each of the plurality of memory devices including a command/address input circuit separate from command/address input circuits of other memory devices of the plurality of memory devices, each of the plurality of memory devices belonging to a corresponding one of a plurality of groups, each group associated with a different time delay for initiating refresh operations for memory devices of the group,
wherein at least one memory device of the plurality of memory devices is configured to:
detect the group of the plurality of groups to which the at least one memory device belongs; and
after receiving a command to initiate a refresh operation, delay initiating the refresh operation by a time delay corresponding to the detected group.

US Pat. No. 10,991,412

STORAGE DEVICE AND METHOD FOR OPERATING STORAGE DEVICE

Samsung Electronics Co., ...

1. A method for operating a storage device, the method comprisingmonitoring characteristic degradation rates of a plurality of blocks included in a cell array of a nonvolatile memory to generate a monitoring result;
designating the plurality of blocks into groups based on the monitoring result;
determining refresh periods for each of the groups;
performing refresh on the groups in accordance with the determined refresh periods;
continually monitoring the characteristic degradation rates of the plurality of blocks to update the monitoring result; and
moving one or more blocks of plurality of blocks between the groups based on the monitoring result.

US Pat. No. 10,991,411

METHOD AND APPARATUSES FOR PERFORMING A VOLTAGE ADJUSTMENT OPERATION ON A SECTION OF MEMORY CELLS BASED ON A QUANTITY OF ACCESS OPERATIONS

Micron Technology, Inc., ...

1. A method, comprising:determining a respective quantity of access operations performed on each section of a plurality of sections of a memory device, each section of the plurality of sections comprising memory cells associated with one of a plurality of word lines of the section that are configured to selectively control coupling of the memory cells with a plurality of digit lines of the respective section;
determining to perform a voltage adjustment operation based at least in part on a total quantity of access operations performed on the plurality of sections;
selecting a section from the plurality of sections for the voltage adjustment operation based at least in part on determining to perform the voltage adjustment operation, wherein the selecting comprises selecting the section having the highest determined respective quantity of access operations performed; and
performing the voltage adjustment operation on the memory cells of the selected section by activating each of the plurality of word lines of the selected section.

US Pat. No. 10,991,409

ENCODER FOR MEMORY SYSTEM AND METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A system comprising:a memory device including a plurality of storage areas; and
a controller including an encoder suitable for:
receiving data bits and position information regarding a storage area among the plurality of storage areas in which the data bits are to be stored;
determining a number of multiple random sequences to be used based on the position information;
scrambling the data bits using the determined number of multiple random sequences, to generate a plurality of scrambled sequences;
selecting a scrambled sequence among the plurality of scrambled sequences, the selected scrambled sequence having the lowest number of a particular logic value among the plurality of scrambled sequences; and
outputting the selected scrambled sequence for storage in the storage area of the memory device.

US Pat. No. 10,991,408

MAGNETIC RANDOM ACCESS MEMORY STRUCTURE AND MANUFACTURING METHOD OF THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a magnetic random access memory (MRAM) structure, the method comprising:forming a magnetic tunneling junction (MTJ) structure in a first region;
forming a dielectric stack over the first region and a second region different from the first region;
etching an upper portion of the dielectric stack in the first region and the second region; and
performing a planarization operation over the remaining portion of the dielectric stack in the first region and the second region.

US Pat. No. 10,991,407

MAGNETORESISTIVE MEMORY DEVICE INCLUDING A HIGH DIELECTRIC CONSTANT CAPPING LAYER AND METHODS OF MAKING THE SAME

WESTERN DIGITAL TECHNOLOG...

1. A voltage controlled magnetic anisotropy (VCMA) magnetoelectric memory device comprising a VCMA magnetoelectric memory cell, wherein the VCMA magnetoelectric memory cell comprises: a first electrode; a second electrode that is spaced from the first electrode; a magnetic tunnel junction located between the first electrode and the second electrode, the magnetic tunnel junction comprising a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer; a voltage controlled magnetic anisotropy (VCMA) dielectric capping layer having a dielectric constant greater than 10 and located between the free layer and the second electrode; and wherein the VCMA dielectric capping layer is thicker than the nonmagnetic tunnel barrier layer and has a higher dielectric constant than the nonmagnetic tunnel barrier layer, such that an electric field is generated in the VCMA dielectric capping layer during the application of a voltage between the first electrode and the second electrode.

US Pat. No. 10,991,406

METHOD, SYSTEM AND DEVICE FOR MAGNETIC MEMORY

Arm Limited, Cambridge (...

1. A bit-cell circuit, comprising: one or more non-volatile magnetic memory devices individually comprising:a first magnetic tunnel junction component including a first terminal, the first magnetic tunnel junction component abutting a first surface of a metal layer; and
a second magnetic tunnel junction component including a second terminal, the second magnetic tunnel junction component abutting a second surface, opposite from the first surface, of the metal layer, wherein the metal layer comprises a spin-orbit-torque (SOT) continuous metal layer including a first end and a third terminal at the first end;
wherein the first magnetic tunnel junction component stores a first signal and/or state responsive to a voltage applied between the third terminal and the first terminal and wherein the second magnetic tunnel junction component stores a second signal and/or state responsive to a voltage applied between the third terminal and the second terminal, and wherein a magnetization vector orientation of one of the first and second magnetic tunnel junction components changes while maintaining a magnetization vector orientation of another of the first and second magnetic tunnel junction components when storing the first signal and/or state or the second signal and/or state.

US Pat. No. 10,991,405

SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a flag shifting circuit configured to generate a first shifted flag signal by shifting a first flag signal by a second latency period, the first flag signal generated based on a first operation clock signal, and configured to generate a second shifted flag signal by shifting a second flag signal by a first latency period, the second flag signal generated based on a second operation clock signal; and
an auto-pre-charge control circuit configured to generate an auto-pre-charge signal by shifting the first shifted flag signal and the second shifted flag signal by a recovery period based on the first operation clock signal and the second operation clock signal.

US Pat. No. 10,991,404

LOOPBACK STROBE FOR A MEMORY SYSTEM

Micron Technology, Inc., ...

1. A memory system comprising:a plurality of memory devices coupled in series, wherein the plurality of memory devices comprises:
a first memory device configured to:
transmit a loopback strobe signal based at least in part on a strobe signal for the first memory device, wherein a frequency of the loopback strobe signal is a fraction of the frequency of the strobe signal; and
transmit a loopback data signal based at least in part on the strobe signal, wherein a frequency of the loopback data signal is the fraction of the frequency of the strobe signal.

US Pat. No. 10,991,402

SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device comprising:a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command; and
a control chip including a second controller configured to control whether or not to shift the first controller to the wait state, based on a number of memory chips operating to overlap with one another.

US Pat. No. 10,991,401

INPUT/OUTPUT CIRCUIT, MEMORY DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. An input/output circuit comprising:a data pattern detector configured to output an up resistance control code and a down resistance control code according to whether input data has a consecutively varied pattern or an inconsecutively varied pattern; and
an output circuit configured to have resistance controlled in response to the up resistance control code and the down resistance control code, amplify the input data, and output the amplified data to an input/output pad,
wherein the data pattern detector identifies that the input data has the inconsecutively varied pattern, based on at least two consecutive bits of the input data are of a same value.

US Pat. No. 10,991,400

INTEGRATED CIRCUIT

SK hynix Inc., Gyeonggi-...

1. An integrated circuit, comprising:one or more first sections in which first to Nth data, where N is an integer greater than or equal to 2, corresponding to one command are transferred through one line;
two or more second sections in which the first to Nth data are serial-to-parallel converted 1:N and transferred through N lines; andtwo or more third sections in which the first to Nth data are serial-to-parallel converted 1:2 and transferred through two lines,wherein, whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections, andwherein select data among the first to Nth data is inverted and transferred in at least one third section among the two or more third sections.

US Pat. No. 10,991,399

ALIGNMENT OF ALTERNATE DIALOGUE AUDIO TRACK TO FRAMES IN A MULTIMEDIA PRODUCTION USING BACKGROUND AUDIO MATCHING

DELUXE ONE LLC, Burbank,...

1. A computer-implemented audio alignment system comprisinga data storage device configured to ingest and store one or more video files thereon, wherein the one or more video files comprise one or more respective audio soundtracks; and
one or more processors configured with instructions to
receive an alternate audio file associated with a video file of the one or more video files, wherein the alternate audio file comprises an alternate audio soundtrack with dialogue audio and non-dialogue audio and the video file comprises a film and an original language audio soundtrack, wherein the original language audio soundtrack comprises dialogue audio and non-dialogue audio;
filter to remove the dialogue audio from the alternate audio soundtrack and from the original language soundtrack;
align the non-dialogue audio from the alternate audio soundtrack with the non-dialogue audio from the original language audio soundtrack based on a filtered alternate audio soundtrack and a filtered original language soundtrack; and
align the alternate audio soundtrack with the film based on the alignment of the non-dialogue audio from the alternate audio soundtrack with the non-dialogue audio from the original language audio soundtrack.

US Pat. No. 10,991,398

AUTOMATED VIDEO BUMPER SYSTEM

Lumanary Inc., San Jose,...

1. A method to process video data, the method comprising:using at least one processor, accessing a file including a video payload and metadata, the metadata including a publication identifier identifying a publication entity;
using the at least one processor, using the publication identifier, identifying a bumper video segment and retrieving the bumper video segment from a storage device;
using the at least one processor, concatenating the video payload with the bumper video segment to create a concatenated video in which the bumper video segment either precedes or proceeds the video payload;
using the publication identifier, identifying at least one third-party video service to which to publish the concatenated video; and
transmitting the concatenated video, together with publication credentials, to the third-party video service.

US Pat. No. 10,991,397

MASKING IN VIDEO STREAM

GENETEC INC., St-Laurent...

1. A method for combining a mask with a selectively progressing video stream, the method comprising:receiving a selection of at least one mask with a mask zone that obscures at least a portion of the video stream;
receiving a selection to emplace the at least one mask at a first location within the video stream;
receiving a selection to enable a tracking icon to move the at least one mask to a second location within the video stream while the video stream progresses, wherein the video stream progression is started by receiving the selection to enable the tracking icon used to move the at least one mask; and
generating a combined output of the video stream and the selective emplacement and movement of the at least one mask during the video stream progression.

US Pat. No. 10,991,396

SYSTEMS AND METHODS FOR MODIFYING VIDEOS BASED ON MUSIC

GoPro, Inc., San Mateo, ...

1. A system for modifying videos based on music, the system comprising:one or more physical processors configured by machine-readable instructions to:
access music information defining a music track, the music track providing an accompaniment for video content, the music track having one or more music events, the individual music events corresponding to different moments within the music track, wherein the one or more music events are classified based on intensities within multiple frequency ranges of one or more pulses occurring within the music event;
select one or more visual effects for the one or more music events within the music track based on the classification of the one or more music events; and
apply the one or more visual effects to the video content, the one or more visual effects applied to one or more moments within the video content aligned to the one or more music events within the music track.

US Pat. No. 10,991,395

METHOD FOR REAL TIME VIDEO PROCESSING INVOLVING CHANGING A COLOR OF AN OBJECT ON A HUMAN FACE IN A VIDEO

Snap Inc., Santa Monica,...

1. A computer-implemented method comprising:identifying, by one or more processors, one or more pixels to be recolored within an object depicted in an image, the one or more pixels are within a region having a prespecified shape, wherein identifying the one or more pixels to be recolored includes determining an intensity value of the one or more pixels to be recolored relative to an intensity value of a pixel at a center of the region;
computing, by the one or more processors, a new pixel value as a function of intensity values of a collection of pixels within the region that is within a given distance of the one or more pixels to be recolored; and
modifying, by the one or more processors, at least a portion of the image by applying the new pixel value to the one or more pixels to be recolored.

US Pat. No. 10,991,394

IN-BAND DATA RECOGNITION AND SYNCHRONIZATION SYSTEM

TIVO SOLUTIONS INC., San...

1. A method comprising:receiving first event identification data and instructions for performing one or more actions;
receiving closed-caption data associated with a content stream, wherein the closed-caption data is displayed in one of a plurality of closed-caption modes;
determining the closed-caption mode of the plurality of closed-caption modes in which the closed-caption data is displayed;
computing, based on the closed-caption data and using a computation method specific to the determined closed-caption mode, second event identification data;
determining whether the received first event identification data matches the computed second event identification data; and
in response to determining that the received first event identification data matches the computed second event identification data, performing the one or more actions, wherein the one or more actions include at least skipping over a segment of the multimedia content stream.

US Pat. No. 10,991,393

ELECTRONIC DEVICE AND METHOD OF MANAGING A PLAYBACK RATE OF A PLURALITY OF IMAGES

SAMSUNG ELECTRONICS CO., ...

1. A method for controlling a playback rate of a plurality of images using an electronic device, the method comprising:obtaining the plurality of images through a camera;
obtaining motion data of at least one region of interest (ROI) in the plurality of images, wherein a position of the ROI in the plurality of images corresponds to a position of at least one object included in the ROI;
identifying an image quality of the at least one ROI in the plurality of images based on at least one of a blur intensity or a contrast of the at least one ROI in the plurality of images;
identifying a key moment image from among the plurality of images based on the obtained motion data and the identified image quality;
determining at least one playback rate for the plurality of images based on the obtained motion data and a temporal distance of each of the plurality of images from the key moment image; and
displaying the plurality of images based on the at least one playback rate.

US Pat. No. 10,991,391

CIRCUITS AND METHODS FOR MODIFYING THE WRITE CURRENT WAVEFORM TO IMPROVE TRACK DENSITY IN HDD

Headway Technologies, Inc...

5. A method for writing encoded data to a hard disk drive comprising the steps of:optimizing the write current in a low current range;
adjusting the overshoot currents amplitudes dependent upon an encoded data width;
generating a pseudorandom signal pattern for varying the overshoot current amplitudes dependent upon an encoded data width; and
equalizing erase widths for all the encoded data widths of the encoded data.

US Pat. No. 10,991,390

HEAD ASSEMBLY WITH SUSPENSION SYSTEM FOR A TAPE EMBEDDED DRIVE

Western Digital Technolog...

1. A head assembly for reading or writing to tape media in a tape drive, the head assembly comprising:a support structure;
a head bar comprising at least one read head and at least one write head, the head bar less than half a width of the tape media; and
a suspension system connecting the head bar to the support structure and configured to move the head bar across the width of the tape media, the suspension system comprising:
a first piezoelectric actuator configured to pull in a first configuration and push in a second configuration;
a second piezoelectric actuator configured to push in the first configuration and pull in the second configuration;
a frame connected to the support structure; and
a plurality of suspension wires attaching the head bar to the frame;
wherein the first piezoelectric actuator connects a first side of the head bar to a first side of the frame, and the second piezoelectric actuator connects a second side of the head bar to a second side of the frame, the second side of the head bar opposite the first side of the head bar.

US Pat. No. 10,991,389

DATA STORAGE DEVICE COUPLING/DECOUPLING ACTUATOR ARM TO/FROM AN ACTUATOR

Western Digital Technolog...

1. A data storage device comprising:a first disk surface;
a first actuator arm;
a first head connected to a distal end of the first actuator arm;
a second disk surface;
a second actuator arm;
a second head connected to a distal end of a second actuator arm;
an actuator;
a first coupler configured to couple the first actuator arm to the actuator;
a second coupler configured to couple the second actuator arm to the actuator; and
control circuitry configured to:
store a plurality of access commands in a command queue;
sort the access commands into an execution order based on a selective coupling of the first and second actuator arms to the actuator; and
execute at least one of the access commands based on the execution order in order to access at least one of the first and second disk surfaces using at least one of the first and second heads.

US Pat. No. 10,991,388

SUSPENSION FOR DISK DEVICE HAVING A DAMPER MEMBER FOR SUPPRESSING WOBBLE OF A FLEXURE

NHK SPRING CO., LTD., Ka...

1. A suspension for a disk device, the suspension comprising:a load beam comprising a first surface, a second surface on an opposite side to the first surface, and a first opening and a second opening which penetrate from the first surface through to the second surface;
a flexure comprising a tongue disposed along the first surface, on which a slider is mounted, and a first outrigger and a second outrigger disposed on respective outer sides of the tongue along a width direction thereof; and
a first damper member and a second damper member, which are attached to the second surface,
wherein:
the first outrigger comprises a first arm disposed on a first surface side, and a first branch portion extending from the first arm through the first opening, a distal end of the first branch portion being interposed between the second surface and the first damper member, and
the second outrigger comprises a second arm disposed on the first surface side, and a second branch portion extending from the second arm through the second opening, a distal end of the second branch portion being interposed between the second surface and the second damper member.