US Pat. No. 10,141,335

SEMICONDUCTOR CIP INCLUDING REGION HAVING RECTANGULAR-SHAPED GATE STRUCTURES AND FIRST METAL STRUCTURES

Tela Innovations, Inc., ...

1. A semiconductor chip, comprising:gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a gate horizontal grid, the gate horizontal grid including at least seven gate gridlines, each gate structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, each gate gridline having at least one gate structure layout shape positioned thereon, wherein adjacently positioned ones of the gate structures are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each of the gate structures having a width of less than or equal to about 45 nanometers, wherein each pair of the gate structures that are positioned in and end-to-end manner are separated from each other by a line end-to-line end gap of less than or equal to about 193 nanometers;
a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, the first-metal structure layout shapes positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each of the first-metal structures having at least one adjacent first-metal structure positioned next to each of its sides at a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the first-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers;
at least six contact structures formed within the region of the semiconductor chip, the at least six contact structures formed in part utilizing corresponding at least six contact structure layout shapes as an input to a lithography process, the at least six contact structures formed in physical and electrical contact with corresponding ones of at least six of the gate structures, each of the at least six contact structure layout shapes having a substantially rectangular shape and a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structure layout shapes positioned and sized to form its corresponding contact structure to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,
wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region, wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit.

US Pat. No. 10,141,334

SEMICONDUCTOR CHIP INCLUDING REGION HAVING RECTANGULAR-SHAPED GATE STRUCTURES AND FIRST-METAL STRUCTURES

Tela Innovations, Inc., ...

1. A semiconductor chip, comprising:gate structures formed within a region of the semiconductor chip, the gate structures positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein adjacent gate gridlines are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each gate structure in the region having a substantially rectangular shape with a width of less than or equal to about 45 nanometers and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate structure positioned thereon, wherein each pair of gate structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers, wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region;
a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure in the region having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each first-metal structure in the region having at least one adjacent first-metal structure positioned next to each of its sides in accordance with a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of first-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers; and
at least six contact structures formed within the region of the semiconductor chip, wherein at least six gate structures within the region have a respective top surface in physical and electrical contact with a corresponding one of the at least six contact structures, each of the at least six contact structures having a substantially rectangular shape with a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structures positioned and sized to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,
wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit, wherein the logic circuit includes electrical connections that collectively include first-metal structures positioned on at least five of the at least eight first-metal gridlines.

US Pat. No. 10,141,332

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING HOLE PENETRATING STACK STRUCTURE

SK Hynix Inc., Gyeonggi-...

1. A method for manufacturing a semiconductor device, the method comprising:repeatedly stacking a first material layer and a second material layer to form a first stack structure;
forming a first hole passing through the first stack structure;
forming an overlay measurement pattern in the first hole, wherein the overlay measurement pattern includes a different material from the first material layer and the second material layer;
forming an etch stop layer in the first hole and over the overlay measurement pattern;
repeatedly stacking a third material layer and a fourth material layer over the first stack structure to form a second stack structure; and
forming a second hole passing through the second stack structure to expose the etch stop layer,
wherein the first hole includes an air-gap surrounded by the overlay measurement pattern and disposed below the etch stop layer.

US Pat. No. 10,141,331

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SUPPORT PILLARS UNDERNEATH A RETRO-STEPPED DIELECTRIC MATERIAL AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stack comprises a memory array region and a terrace region;
memory stack structures extending through the memory array region of the alternating stack, wherein each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel contacting an inner sidewall of the respective memory film; and
support pillar structures extending through the terrace region of the alternating stack,
wherein the support pillar structures have different heights from each other;
wherein each of the support pillar structures has a respective topmost surface that is coplanar with a top surface of a respective one of the insulating layers in the alternating stack; and
wherein each of the support pillar structures comprises a dummy vertical semiconductor channel that is identical to the vertical semiconductor channels in material composition.

US Pat. No. 10,141,330

METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES, SEMICONDUCTOR DEVICES, AND ELECTRONIC SYSTEMS

Micron Technology, Inc., ...

1. A method of forming a semiconductor device structure, comprising:forming a stack structure comprising stacked tiers, each of the stacked tiers comprising a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure;
forming a patterned hard mask structure over the stack structure;
forming dielectric structures within openings in the patterned hard mask structure;
forming a photoresist structure over the dielectric structures and the patterned hard mask structure;
subjecting the photoresist structure, the dielectric structures, and the stack structure to a series of material removal processes to selectively remove portions of the photoresist structure, portions of the dielectric structures not covered by remaining portions of the photoresist structure, and portions of the stack structure not covered by one or more of the patterned hard mask structure and the remaining portions of the photoresist structure to form apertures extending to different depths within the stack structure;
forming dielectric structures over side surfaces of the stack structure within the apertures, upper surfaces of the dielectric structures substantially coplanar with an upper surface of the patterned hard mask structure; and
forming conductive contact structures longitudinally extending to bottoms of the apertures.

US Pat. No. 10,141,328

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three-dimensional (3D) memory device, comprising:a substrate;
a ridge-shaped stack, including a plurality of conductive strips stacked on the substrate along a first direction;
a memory layer, stacked on a vertical sidewall of the ridge-shaped stack along a second direction that forms a non-straight angle with the first direction, and having a first narrow sidewall with a first long side extending along the first direction and a first narrow side extending along the second direction;
a channel layer, stacked on the memory layer along the second direction, the channel layer having a portion recessed in a third direction by an etch back process to form a second narrow sidewall having a second long side extending along the first direction and a second narrow side extending along the second direction, wherein the first narrow sidewall is separated from the second narrow sidewall along the third direction, and the third direction forms a non-straight angle with both the first direction and the second direction; and
a capping layer stacked on the second narrow sidewall along the third direction.

US Pat. No. 10,141,327

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a first insulating layer disposed on a semiconductor substrate;
a first semiconductor layer disposed on the semiconductor substrate;
a plurality of memory cells arranged three-dimensionally above the first insulating layer and disposed above the first semiconductor layer;
a plurality of conductive layers stacked in a first direction that intersects a surface of the semiconductor substrate;
a second insulating layer covering a side surface of a lowermost layer of the plurality of conductive layers;
an oxide layer disposed on a side surface of the first semiconductor layer and contacting the second insulating layer; and
a high permittivity layer provided between the first insulating layer and the second insulating layer, a permittivity of the high permittivity layer being higher than that of the first insulating layer and the high permittivity layer directly contacting the side surface of the first semiconductor layer.

US Pat. No. 10,141,324

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a main surface;
a first nonvolatile memory cell and a second nonvolatile memory cell formed on the main surface of the semiconductor substrate;
the first nonvolatile memory cell including a first memory transistor for storing data having a first memory gate electrode and a first select transistor for selecting the first memory transistor having a first select gate electrode; and
the second nonvolatile memory cell including a second memory transistor for storing data having a second memory gate electrode and a second select transistor for selecting the second memory transistor having a second select gate electrode;
wherein the first select gate electrode and the second select gate electrode extend in a first direction so as to be disposed next to each other in a second direction substantially perpendicular to the first direction in a plan view,
wherein the first memory gate electrode extends in the first direction so as to be disposed along a sidewall of the first select gate electrode,
wherein the second memory gate electrode extends in the first direction so as to be disposed along a sidewall of the second select gate electrode,
wherein the first memory gate electrode and the second memory gate electrode are disposed between the first select gate electrode and the second select gate electrode,
wherein the first memory gate electrode has a first contact portion extending in the second direction to provide an electrical contact to a first interconnect,
wherein the second memory gate electrode has a second contact portion extending in the second direction to provide an electrical contact to a second interconnect,
wherein the first contact portion is spaced apart from the second contact portion in the first direction in the plan view, and
wherein a first portion of the first contact portion and a second portion of the second contact portion are overlapped with each other in the second direction in the plan view.

US Pat. No. 10,141,323

NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

16. A non-volatile memory array, comprising:a first pair of memory cell wherein the first pair of memory cell further comprises:
a first MOSFET having a first gate region; and
a second MOSFET having a second gate region; and
a second pair of memory cell adjacent to the first pair of memory cell, wherein the second pair of memory cell includes a third MOSFET having a third gate region and a fourth MOSFET;
wherein the second MOSFET of the first pair of memory cell and third MOSFET of the second pair of memory cell are connected to a same bit line; and
wherein the first gate region and the second gate region of the first pair of memory cell extend over and connect to a first active region providing a first word line and the third gate region of the second pair of memory cell extends over and connects to a second active region providing a second word line different than the first word line.

US Pat. No. 10,141,321

METHOD OF FORMING FLASH MEMORY WITH SEPARATE WORDLINE AND ERASE GATES

Silicon Storage Technolog...

1. A method of forming a non-volatile memory cell comprising:forming, in a substrate of a first conductivity type, spaced apart first and second regions of a second conductivity type, defining a channel region there between;
forming a floating gate disposed over and insulated from a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region;
forming a tunnel oxide layer around the sharp edge;
forming an erase gate over and insulated from the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer; and
forming a word line gate disposed over and insulated from a second portion of the channel region which is adjacent to the second region, wherein the forming of the word line gate is entirely performed after the forming of the tunnel oxide layer and the forming of the erase gate.

US Pat. No. 10,141,319

LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY

UNITED MICROELECTRONICS C...

1. A layout pattern of a static random access memory, comprising:a first inverter and a second inverter cross-coupled for data storage, each inverter including a pull-up device (PL) and a pull-down device (PD);
each inverter comprising a step-shaped structure disposed on a substrate, the step-shaped structure comprising a first part and a second part arranged along a first direction, and a bridge part connected to the first part and the second part, the bridge part is arranged along a second direction, wherein the first direction is perpendicular to the second direction, in addition, the first part is disposed at one side of the bridge part, and the second part is disposed at the opposite side of the bridge part along the first direction, and wherein the first part crosses over a first diffusion region, and the second part crosses over a second diffusion region to form the pull-down device (PD), wherein the first part crosses over a third diffusion region to form the pull-up device (PL);
each inverter has an inverter output, the inverter output connecting a first pass gate structure and a second pass gate structure disposed on the substrate, the first pass gate structure and the first part of the step-shaped structure being arranged along a same direction and comprising a same symmetry axis, the second pass gate structure and the second part of the step-shaped structure being arranged along a same direction and comprising a same symmetry axis, wherein the first pass gate structure crosses over the second diffusion region to form a first pass gate device (PG1), and the second pass gate structure crosses over the first diffusion region to form a second pass gate device (PG2), wherein a drain of the PG1 is connected to a drain of the PG2, and the bridge part of each step-shaped structure of each inverter is disposed between the first pass gate structure and the second pass gate structure; and
each inverter output comprising an extending contact structure at least crossing over one of the first diffusion region, the second diffusion region and the third diffusion region.

US Pat. No. 10,141,317

METAL LAYERS FOR A THREE-PORT BIT CELL

QUALCOMM Incorporated, S...

1. A method comprising:patterning a first metal layer at a bit cell;
patterning a second metal layer between the first metal layer and a third metal layer, the second metal layer including two read word lines coupled to the bit cell; and
patterning the third metal layer, the third metal layer including a write word line coupled to the bit cell.

US Pat. No. 10,141,315

SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:an array of memory cells formed in a semiconductor, the array comprising:
a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising:
a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;
a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, and the buried region is discontinuous along one direction;
wherein said floating body region stores a charge level indicative of a state of the memory cell selected from at least first and second states;
wherein said buried region is configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said buried region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and
first control circuitry configured to provide electrical signals to said buried region.

US Pat. No. 10,141,314

MEMORIES AND METHODS TO PROVIDE CONFIGURATION INFORMATION TO CONTROLLERS

Micron Technology, Inc., ...

1. A memory system, comprising:a memory controller; and
a memory module coupled to the memory controller, wherein the memory module comprises:
a memory package of a first type, wherein the memory package of the first type includes a first memory die and a second memory die coupled to the first memory die wherein the first memory die and second memory die are separate dies, the memory package of the first type configured to receive an external signal for the second memory die and further configured to couple the external signal to the second memory die through the first memory die; and
a signal presence detect unit including a memory module and configured to receive a configuration signal and to provide configuration data associated with a memory package of a second type to the memory controller in response to the configuration signal, wherein the configuration data includes control signal timings for accessing one or more memory dies in the memory package of the second type, wherein the control signal timings provided from the signal presence detection unit to the memory controller include timing relationships between clock enable, chip select, and on-die termination signals, wherein the memory package of the second type is configured to provide the external signal directly to a respective second memory die, the memory controller being configured to interface with the memory package of the first type utilizing the control signal timings of the second type, based, at least in part, on the configuration data of the second type and further configured to provide the external signal for the second memory die to the memory package of the first type.

US Pat. No. 10,141,310

SHORT CHANNEL EFFECT SUPPRESSION

TAIWAN SEMICONDUCTOR MANU...

18. A semiconductor device comprising:a p-type region comprising:
a first set of fin structures, the fin structures of the first set varying in size, the fin structures of the first set each comprising:
a bottommost portion;
a channel portion disposed above the bottommost portion and having an n-type dopant at a first concentration; and
an epitaxially grown anti-punch-through feature extending from the bottommost portion to the channel portion and having an n-type dopant throughout at a second concentration greater than the first concentration, wherein the anti-punch-through feature of a first fin structure of the first set extends to a different depth than the anti-punch-through feature of a second fin structure of the first set;
a plurality of p-type transistors formed on the fin structures of the first set, the p-type transistors having varying dimensions; and
a number of isolation features positioned such that a top surface of the isolation features is below a first portion of each of the anti-punch-through features and above a second portion of each of the anti-punch-through features.

US Pat. No. 10,141,307

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:an isolation insulating layer disposed over a substrate;
a first fin structure and a second fin structure, both disposed over the substrate, the first and second fin structures extending in a first direction in plan view, upper portions of the first and second fin structures being exposed from the isolation insulating layer;
a first gate structure disposed over parts of the first and second fin structures, the first gate structure extending in a second direction crossing the first direction;
first fin sidewall spacers covering a lower portion of the exposed first fin structure, and second fin sidewall spacers covering a lower portion of the exposed second fin structure; and
a source/drain structure formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation insulating layer, and wrapping side surfaces and a top surface of each of the exposed first and second fin structures, wherein:
a void is formed between the source/drain structure and the isolation insulating layer,
one of the first fin sidewall spacers and one of the second fin sidewall spacers are disposed in the void, and
an entirety of side surface of the one of the first fin sidewall spacers and an entirety of side surface of the one of the second fin sidewall spacers are exposed in the void.

US Pat. No. 10,141,306

SYSTEMS, METHODS, AND APPARATUS FOR IMPROVED FINFETS

QUALCOMM Incorporated, S...

1. A finFET comprising:a plurality of fins separated from each other to form a plurality of gaps between adjacent fins of the plurality of fins;
an oxide material located in the plurality of gaps, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material; and
wherein the first density is greater than the second density.

US Pat. No. 10,141,301

CROSS-DOMAIN ESD PROTECTION

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:a triggering arrangement coupled to a first reference voltage node, the triggering arrangement having an output node for a triggering indication; and
interface circuitry coupled to a second reference voltage node different from the first reference voltage node, wherein the interface circuitry comprises a transistor having a body electrode biased to the output node of the triggering arrangement;
a second transistor coupled between the transistor and a third reference voltage node, wherein:
a gate electrode of the second transistor is biased to a triggering node of the triggering arrangement; and
the triggering indication at the output node is a logical inverse of a signal at the triggering node.

US Pat. No. 10,141,299

SEMICONDUCTOR DEVICE WITH PROTECTIVE ELEMENT PORTION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first semiconductor region of a second conductivity type selectively provided in a surface layer of a first principal surface of a semiconductor substrate of a first conductivity type;
an element structure of a semiconductor element provided in the first semiconductor region;
a second semiconductor region of the first conductivity type selectively provided in the first semiconductor region, the second semiconductor region constituting the element structure of the semiconductor element;
a third semiconductor region of the second conductivity type selectively provided to penetrate the first semiconductor region in a depth direction and to surround the element structure of the semiconductor element at a depth equal to or deeper than a depth of the first semiconductor region, the third semiconductor region having an impurity concentration that is higher than that of the first semiconductor region;
a fourth semiconductor region of the second conductivity type selectively provided in the surface layer of the first principal surface of the semiconductor substrate to be spaced apart from the first semiconductor region;
a fifth semiconductor region of the first conductivity type selectively provided in the fourth semiconductor region;
a sixth semiconductor region of the second conductivity type selectively provided to penetrate the fourth semiconductor region in the depth direction and to be at a depth equal to or deeper than a depth of the fourth semiconductor region, the sixth semiconductor region having an impurity concentration that is higher than that of the fourth semiconductor region;
a first electrode that is electrically connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; and
a second electrode that is connected to a second principal surface of the semiconductor substrate.

US Pat. No. 10,141,296

DUMMY FIN CELL PLACEMENT IN AN INTEGRATED CIRCUIT LAYOUT

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit, comprising:a semiconductor device formed over a substrate;
a first plurality of dummy fin structures over a first portion of the substrate, wherein each of the first plurality of dummy fin structures has a first gate structure having a first gate width, and the first plurality of dummy fin structures being based on a first standard dummy fin cell; and
a second plurality of dummy fin structures over a second portion of the substrate, wherein each of the second plurality of dummy fin structures has a second gate structure having a second gate width different from the first gate width, and the second plurality of dummy fin structures being based on a second standard dummy fin cell,
wherein the second portion surrounds the semiconductor device and the first portion surrounds the second portion.

US Pat. No. 10,141,293

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...

1. A semiconductor package, comprising:a package base substrate having first to fourth edges;
a plurality of bonding pads disposed on upper surface of the package base substrate, wherein first to fourth portions of the bonding pads are disposed adjacent to the first to fourth edges of the package base substrate, respectively;
a plurality of connection pads disposed on lower surface of the package base substrate;
four identical semiconductor chips disposed on upper surface of the package base substrate, each of the semiconductor chips including a plurality of first chip pads adjacent to a first edge of the semiconductor chip, and each of the first to fourth semiconductor chips being rotated by ninety degrees relative to adjacent semiconductor chips and thereby, first edges of the first to fourth semiconductor chips facing the first to fourth edges of the package base substrate respectively; and
bonding wires electrically connecting the first chip pads of the first to fourth semiconductor chips to the first to fourth portions of bonding pads respectively,
wherein each of semiconductor chips further includes a second chip pad, and the second chip pads of the first semiconductor chip and the third semiconductor chip are electrically connected by a first matching wire, and the second chip pads of the second semiconductor chip and the fourth semiconductor chip are electrically connected by a second matching wire.

US Pat. No. 10,141,291

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, including:attaching a carrier wafer having a first wafer width to a front side of a die wafer having a second wafer width, the first wafer width being substantially identical to the second wafer width, the die wafer having a thickness of about 700 ?m when attaching to the carrier wafer;
thinning a back side of the die wafer, the back side of the die wafer being opposite to the front side of the die wafer;
singulating the carrier wafer and the die wafer concurrently when die wafer having the second wafer width, whereby singulated dies attached to singulated carrier dies are formed; and
bonding the singulated dies attached to singulated carrier dies to a bottom wafer, wherein a back side of each of the singulated dies is facing a front side of the bottom wafer.

US Pat. No. 10,141,288

SURFACE MOUNT DEVICE/INTEGRATED PASSIVE DEVICE ON PACKAGE OR DEVICE STRUCTURE AND METHODS OF FORMING

Taiwan Semiconductor Manu...

1. A package structure comprising:an integrated circuit die embedded in an encapsulant;
a redistribution structure on the encapsulant and electrically coupled to the integrated circuit die, the redistribution structure comprising:
a metallization layer distal from the encapsulant and the integrated circuit die, wherein the metallization layer is an uppermost metallization layer of the redistribution structure, and
a dielectric layer on the metallization layer, wherein the dielectric layer is an uppermost dielectric layer of the redistribution structure;
a first under metallization structure on the dielectric layer, the first under metallization structure comprising:
a first under-terminal metallization including a first extending portion and a second extending portion, wherein the first extending portion extends through a first opening of the dielectric layer to a first pattern of the metallization layer, wherein the second extending portion extends through a second opening of the dielectric layer to a second pattern of the metallization layer, wherein the first under-terminal metallization further includes a first upper portion on an upper surface of the dielectric layer distal the encapsulant, the first upper portion extending continuously from the first extending portion to the second extending portion; and
a second under-terminal metallization including a third extending portion and a fourth extending portion, wherein the third extending portion extends through a third opening of the dielectric layer to a third pattern of the metallization layer, wherein the fourth extending portion extends through a fourth opening of the dielectric layer to a fourth pattern of the metallization layer, wherein the second under-terminal metallization further includes a second upper portion on the upper surface of the dielectric layer distal the encapsulant, the second upper portion extending continuously from the third extending portion to the fourth extending portion, wherein the first opening, the second opening, the third opening, and the fourth opening are physically separated from each other; and
a Surface Mount Device and/or Integrated Passive Device (SMD/IPD) attached to the first under metallization structure, wherein the SMD/IPD has a first connector formed of a first conductive material, wherein the first connector physically contacts the first extending portion and the second extending portion of the first under-terminal metallization, wherein the first conductive material extends continuously from the first extending portion to the second extending portion.

US Pat. No. 10,141,285

EXTERNALLY INDUCED CHARGE PATTERNING USING RECTIFYING DEVICES

Palo Alto Research Center...

1. A system for forming charge patterns on micro objects, said system comprising:a micro object including a rectifying device, the rectifying device exhibiting an asymmetric current-voltage (I-V) response curve, the micro object includes a substrate, and wherein the rectifying device is formed on or in the substrate; and
a device external to the micro object, configured to generate an electric or magnetic field to induce a flow of charge through the rectifying device, wherein the device external to the micro object induces the flow of charge through the rectifying device using capacitive or magnetic coupling, and wherein the device external to the micro object which generates the electric or magnetic field, uses at least a part of the electric or magnetic field to generate charge patterns, and wherein motion is induced as an interaction of the electric or magnetic field, induced charge and the micro-object.

US Pat. No. 10,141,283

SINTERABLE BONDING MATERIAL AND SEMICONDUCTOR DEVICE USING THE SAME

1. A sinterable bonding material comprising a silver filler and an organic base compound as a sintering promoter, wherein the silver filler comprises a flake-shaped filler, and wherein the organic base compound is a nitrogen containing hetero ring compound having an amidine moiety and/or a guanidine moiety.

US Pat. No. 10,141,280

MECHANISMS FOR FORMING PACKAGE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A package structure, comprising:a semiconductor die; and
a substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween, wherein:
the first bonding structure and the second bonding structure are next to each other,
the second bonding structure is wider than the first bonding structure,
the first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump,
the first UBM structure is between the first solder bump and the semiconductor die,
the first solder bump has a first end and a second end opposite to the first end,
the second end is in direct contact with the first UBM structure,
the second end is wider than the first end,
the second bonding structure has a second UBM structure and a second solder bump,
the second solder bump has a third end and a fourth end opposite to the third end,
the fourth end is in direct contact with the second UBM structure,
the third end of the second solder bump is as wide as the first end of the first solder bump,
the second UBM structure has a continuous linear portion extending across an entirety of the fourth end of the second solder bump,
the second UBM structure has a sidewall portion surrounding the continuous linear portion and extending along a side surface of the second solder bump,
the third end of the second solder bump and the first end of the first solder bump are substantially positioned at a plane that is parallel to a main surface of the substrate,
the second UBM structure is between the second solder bump and the semiconductor die, and
the second UBM structure has a maximum width larger than that of the first UBM structure, and the second solder bump has a maximum width larger than that of the first solder bump.

US Pat. No. 10,141,279

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A semiconductor device, comprising:a semiconductor substrate;
a conductor provided on a main surface of the semiconductor substrate;
an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor; and
an external connection terminal connected to the portion of the conductor exposed from the opening, wherein
in a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.

US Pat. No. 10,141,277

MONOLITHIC DECOUPLING CAPACITOR BETWEEN SOLDER BUMPS

International Business Ma...

1. An integrated circuit, comprising:pads formed on a back end of the line surface;
decoupling capacitor stacks monolithically formed about the pads, each decoupling capacitor stack including dielectric layers, and a first conductive layer and a second conductive layer disposed between the dielectric layers, the first and second conductive layers including respective materials having different etch selectivities;
and solder balls formed on respective ones of the pads and connecting to respective ones of the first and second conductive layers to reduce noise and voltage spikes between the solder balls.

US Pat. No. 10,141,274

SEMICONDUCTOR CHIP WITH ANTI-REVERSE ENGINEERING FUNCTION

International Business Ma...

1. An anti-reverse engineering semiconductor structure, comprising:a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, said first wiring level closest to said semiconductor substrate and said last wiring level furthest from said semiconductor substrate, said stack of wiring levels including an intermediate wiring level between said first wiring level and said last wiring level, said semiconductor substrate and said first wiring level comprising active devices, wherein each wiring level of said stack of wiring levels comprises a dielectric layer containing electrically conductive wire;
active devices contained in said semiconductor substrate and said first wiring level, each wiring level of said stack of wiring levels comprising a dielectric layer containing electrically conductive wire;
a liner on sidewalls and a bottom of a trench extending from said intermediate wiring level, through said first wiring level into said semiconductor substrate, such that said trench comprises an open space;
a cap sealing a top of said open space of said trench, wherein each of said liner and said cap is configured to be damaged during a reverse engineering process such that said trench is exposed to said at least one wiring level of said stack of wiring levels; and
a chemical agent filling said open space of said trench, wherein said liner and said cap are chemically inert to said chemical agent, wherein portions of said at least one wiring level of said stack of wiring levels are not chemically inert to said chemical agent or a reaction product of said chemical agent, and wherein upon said liner or said cap being damaged during said reverse engineering process, said chemical agent is configured to damage wires, dielectric layers, dielectric materials, and said active devices of said at least one wiring level of said stack of wiring levels.

US Pat. No. 10,141,273

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a wiring substrate including a first surface, a plurality of first terminals formed on the first surface, and a second surface opposite to the first surface;
a first semiconductor chip which includes a first front surface, a plurality of first front electrodes formed on the first front surface, a first rear surface opposite to the first front surface, a plurality of first rear electrodes formed on the first rear surface, and a plurality of through electrodes electrically connecting the plurality of first front electrodes to the plurality of first rear electrodes, and is mounted on the wiring substrate so that the first front surface faces the first surface of the wiring substrate; and
a second semiconductor chip which includes a second front surface, a plurality of second front electrodes formed on the second front surface, and a second rear surface opposite to the second front surface, and is mounted on the first semiconductor chip so that the second front surface faces the first rear surface of the first semiconductor chip,
wherein the plurality of first terminals of the wiring substrate and the plurality of first front electrodes of the first semiconductor chip are electrically connected to each other via a plurality of first protrusion electrodes,
wherein the plurality of first rear electrodes of the first semiconductor chip and the plurality of second front electrodes of the second semiconductor chip are electrically connected to each other via a plurality of second protrusion electrodes,
wherein the plurality of first rear electrodes are formed in a first region of the first rear surface of the first semiconductor chip,
wherein a first metal pattern is formed in a second region on a peripheral side of the first rear surface relative to the first region,
wherein a protrusion height of the first metal pattern with respect to the first rear surface is smaller than a protrusion height of each of the plurality of first rear electrodes with respect to the first rear surfaces, and
wherein a first separation distance between the first rear surface of the first semiconductor chip and the second front surface of the second semiconductor chip in an outer periphery of the second region is smaller than a second separation distance between the first rear surface of the first semiconductor chip and the second front surface of the second semiconductor chip in the first region.

US Pat. No. 10,141,272

SEMICONDUCTOR APPARATUS, STACKED SEMICONDUCTOR APPARATUS AND ENCAPSULATED STACKED-SEMICONDUCTOR APPARATUS EACH HAVING PHOTO-CURABLE RESIN LAYER

SHIN-ETSU CHEMICAL CO., L...

1. A semiconductor apparatus comprising: a semiconductor device; an on-semiconductor-device metal pad electrically connected to the semiconductor device; a metal interconnect electrically connected to the semiconductor device; a through electrode electrically connected to the metal interconnect; a solder bump electrically connected to the metal interconnect; a first insulating layer on which the semiconductor device is placed; a second insulating layer formed on the semiconductor device; a third insulating layer formed on the second insulating layer, whereinthe through electrode penetrates at least the second insulating layer,
the metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second insulating layer, and the metal interconnect penetrates the second insulating layer from the upper surface of the second insulating layer and is electrically connected to the through electrode at an lower surface of the second insulating layer,
the first insulating layer is formed by a photo-curable dry film or a photo-curable resist coating film,
the second insulating layer is formed by the photo-curable dry film, and
the third insulating layer is formed by the photo-curable dry film or a photo-curable resist coating film; wherein
the photo-curable dry film has a photo-curable resin layer composed of a photo-curable resin composition containing: resin, crosslinking agents, a photo acid generator and a solvent, or
the photo-curable resist coating film is a photo-curable resin layer composed of a photo-curable resin composition containing: resin, crosslinking agents, a photo acid generator and a solvent.

US Pat. No. 10,141,271

SEMICONDUCTOR DEVICE HAVING ENHANCED HIGH-FREQUENCY CAPABILITY AND METHODS FOR MAKING SAME

COOLSTAR TECHNOLOGY, INC....

1. A method of reducing electromagnetic interference in a semiconductor device, comprising:forming at least one functional circuit in a substrate of the semiconductor device; and
forming an integrated micro-shielding structure in the semiconductor device, the integrated micro-shielding structure extending vertically through the substrate between a front surface and a back surface of the substrate and surrounding the at least one functional circuit, the integrated micro-shielding structure being configured to reduce at least one of radio frequency (RF) emissions in the semiconductor device and RF coupling between different functional parts of the at least one functional circuit;
wherein forming the integrated micro-shielding structure comprises:
forming at least a first trench in the front surface of the substrate and extending partially through the substrate;
forming a first conductive layer on at least a bottom and sidewalls of the first trench;
forming at least a second trench in the back surface of the substrate and extending partially through the substrate, the second trench underlying at least a portion of the first trench, respective depths of the first and second trenches being configured such that the first and second trenches are separated from one another by a prescribed vertical spacing; and
forming a second conductive layer on at least a bottom and sidewalls of the second trench;
wherein the prescribed vertical spacing between the first and second trenches is configured to be smaller than a wavelength of RF signals being isolated by the integrated micro-shielding structure.

US Pat. No. 10,141,270

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

Amkor Technology, Inc., ...

1. A semiconductor device comprising:a substrate having a top substrate surface, a bottom substrate surface, and lateral substrate surfaces extending between the top and bottom substrate surfaces;
a metal plane on the top substrate surface, the metal plane comprising first and second apertures extending completely and vertically through the metal plane;
a semiconductor die on the top substrate surface and positioned within the first aperture of the metal plane, the semiconductor die having a top die surface, a bottom die surface, and lateral die side surfaces extending between the top and bottom die surfaces, wherein the bottom die surface is coupled to the top substrate surface; and
an encapsulating material that encapsulates at least a portion of the lateral die side surfaces and at least a portion of the top substrate surface, wherein the encapsulating material extends through the second aperture of the metal plane,
wherein:
the second aperture is entirely laterally bounded by the metal plane; and
the second aperture is free of electronic components.

US Pat. No. 10,141,265

BENT-BRIDGE SEMICONDUCTIVE APPARATUS

Intel IP Corporation, Sa...

1. A bent-bridge semiconductive apparatus comprising:a first semiconductive device;
a silicon bridge that is integrally part of the first semiconductive device, wherein the silicon bridge is deflected out of planarity with respect to the first semiconductive device, and
electrical connection selected from the group consisting of an electrical bump and a redistribution layer coupled to the first semiconductive device at metallization on an active surface thereof.

US Pat. No. 10,141,260

INTERCONNECTION STRUCTURE AND METHOD FOR FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming an interconnection structure, comprising:forming a dielectric structure over a non-insulator structure;
forming a hole in the dielectric structure to expose the non-insulator structure;
forming a first diffusion barrier layer into the hole in the dielectric structure using a first deposition process;
forming a second diffusion barrier layer over the first diffusion barrier layer using a second deposition process that is different from the first deposition process;
removing a first portion of the second diffusion barrier layer from a bottom of the hole; and
forming a metal over the first diffusion barrier layer.

US Pat. No. 10,141,257

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A semiconductor integrated circuit device, comprising:(a) a first interconnect made of a first metal film and formed over a main surface of a semiconductor substrate;
(b) a first barrier insulating film formed on the first interconnect such that the first barrier insulating film contacts a top surface of the first interconnect;
(c) a first interlayer insulating film formed over the first barrier insulating film;
(d) a first via hole formed in the first interlayer insulating film and the first barrier insulating film such that the first via hole connects with the first interconnect;
(e) a first interconnect trench formed in the first interlayer insulating film over the first via hole and connected with the first via hole;
(f) a second interconnect formed by filling a second metal film in the first interconnect trench and the first via hole;
(g) a third interconnect made of a third metal film and formed over the second interconnect and the first interlayer insulating film;
(h) a second barrier insulating film formed on the third interconnect such that the second barrier insulating film contacts a top surface of the third interconnect;
(i) a second interlayer insulating film formed over the second barrier insulating film;
(j) a second via hole formed in the second interlayer insulating film and the second barrier insulating film such that the second via hole connects with the third interconnect;
(k) a second interconnect trench formed in the second interlayer insulating film over the second via hole and connected with the second via hole; and
(l) a fourth interconnect formed by filling a fourth metal film in the second interconnect trench and the second via hole,
wherein the second interlayer insulating film has an etching stopper film,
wherein the etching stopper film is arranged nearer to a bottom surface of the fourth interconnect than to a top surface of the third interconnect and a top surface of the fourth interconnect,
wherein the first interlayer insulating film does not have an etching stopper film,
wherein the second interlayer insulating film is thicker than the first interlayer insulating film,
wherein a depth of the second interconnect trench is greater than a depth of the first interconnect trench,
wherein a depth of the second via hole is greater than a depth of the first via hole,
wherein a dielectric constant of the first interlayer insulating film is lower than a dielectric constant of the second interlayer insulating film,
wherein the first barrier insulating film includes silicon, carbon and nitrogen,
wherein the second barrier insulating film includes silicon, carbon and nitrogen, and
wherein the etching stopper film includes silicon and nitrogen.

US Pat. No. 10,141,255

CIRCUIT BOARDS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package substrate, comprising:an upper conductive pattern disposed on a top surface of the semiconductor package substrate, the upper conductive pattern including bonding pads and upper electric patterns; and
a lower conductive pattern disposed on a bottom surface of the semiconductor package substrate, the lower conductive pattern including ball lands and a lower electric pattern,
wherein the bonding pads are disposed in an upper window region of the top surface and at least one of the bonding pads is electrically connected to at least one of the upper electric patterns, and the lower electric pattern is disposed in a lower window region and is electrically connected to at least one of the bonding pads and at least one of the ball lands,
wherein the lower window region is defined by outer boundaries of the lower electric pattern along at least two perpendicular directions, and the upper window region is defined as an overlapped region with the lower window region, and
wherein the upper electric patterns and the lower electric pattern include the same metallic material, and a ratio of the area occupied by the lower electric pattern in the lower window region to the area occupied by the upper conductive pattern in the upper window region is less than or equal to 1.5.

US Pat. No. 10,141,228

FINFET DEVICE HAVING SINGLE DIFFUSION BREAK STRUCTURE

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a fin-shaped structure on a substrate;
a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion;
a gate structure on the first portion; and
a contact etch stop layer (CESL) adjacent to the gate structure and extending to cover and directly contacting a top surface of the SDB structure.

US Pat. No. 10,141,222

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS THROUGH INTERCONNECT STRUCTURES AND ENCAPSULANT OF WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a carrier;
providing a semiconductor die;
disposing a first interconnect structure over an active surface of the semiconductor die;
disposing the semiconductor die over the carrier with the active surface of the semiconductor die oriented toward the carrier;
forming a second interconnect structure over a second surface of the semiconductor die opposite the active surface;
forming a first insulating layer over the second interconnect structure;
forming a protective layer on the first insulating layer;
forming a via in order through the protective layer, second interconnect structure, first interconnect structure, and partially into the carrier;
removing the protective layer after forming the via;
removing the carrier after forming the via;
forming a first conductive layer in the via and extending over the semiconductor die directly on a major surface of the first insulating layer; and
forming an opening in the first insulating layer, wherein the first conductive layer extends into the opening to contact the second interconnect structure.

US Pat. No. 10,141,220

VIA PATTERNING USING MULTIPLE PHOTO MULTIPLE ETCH

Taiwan Semiconductor Manu...

1. A method comprising:forming a dielectric layer;
forming a trench in the dielectric layer;
forming a photo resist having a first portion over the dielectric layer, and a second portion in the trench;
forming a first mask layer over the photo resist;
forming a first opening in the first mask layer; and
etching the photo resist and the dielectric layer to extend the first opening to a bottom of the dielectric layer.

US Pat. No. 10,141,212

AUTOMATED MATERIAL HANDLING SYSTEM FOR SEMICONDUCTOR MANUFACTURING BASED ON A COMBINATION OF VERTICAL CAROUSELS AND OVERHEAD HOISTS

Murata Machinery Ltd., K...

7. A system comprising:an overhead rail in a semiconductor fabrication plant;
an overhead hoist transport (OHT) vehicle coupled to the overhead rail, wherein the OHT vehicle comprises:
a body;
a gripper configured to hold a material unit;
a hoist coupled to the movable stage and to the gripper;
a moveable stage coupled to the hoist and the body, wherein the OHT transport vehicle is configured to move the moveable stage along a horizontal axis to positions exterior to the body on either side of the body of OHT transport vehicle;
wherein the movable stage is configured to move along the horizontal axis from a first position within to the body to a second position that is exterior to the body of the OHT vehicle and adjacent to a side of the OHT vehicle; and
wherein the hoist is configured to move the gripper along a vertical axis to a position that is directly below the moveable stage;
wherein the hoist is configured to move the gripper along a vertical axis to a position that is directly below the moveable stage when the moveable stage is in the first position;
wherein the hoist is configured to move the gripper along a vertical axis to a position that is directly below the moveable stage when the moveable stage is in the second position that is adjacent to a side of the OHT vehicle;
wherein the OHT vehicle is configured to move the material unit from a starting position to an ending position, wherein the starting position comprises a horizontal starting position and a vertical starting position, and the ending position comprises a horizontal ending position and a vertical ending position;
wherein the hoist is configured to move the gripper vertically to a work station; and
wherein the movable stage and the hoist are configured to work in concert to move the gripper to a fixed shelf.

US Pat. No. 10,141,208

VACUUM PROCESSING APPARATUS

Canon Anelva Corporation,...

1. A vacuum processing apparatus comprising:a vacuum vessel in which vacuum processing can be performed;
a substrate holder capable of holding a substrate;
a tilting unit capable of making said substrate holder pivot about a pivotal axis and tilting the substrate held by said substrate holder with respect to a process source provided in said vacuum vessel;
a cooling device provided in said substrate holder and configured to act together with a compression device provided outside said vacuum vessel to cool the substrate held by said substrate holder; and
a rotary joint provided in said tilting unit and including a supply path configured to supply a coolant gas from said compression device to said cooling device and an exhaust path configured to exhaust the coolant from said cooling device to said compression device,
wherein said rotary joint comprises:
a fixed portion fixed to said vacuum vessel;
a pivotal portion provided so as to pivot with respect to said fixed portion and fixed to said substrate holder; and
a gas guide path provided in one of said fixed portion and said pivotal portion and configured to communicate a space region formed between the supply path and the exhaust path and guide the coolant gas that has leaked from one of the supply path and the exhaust path in the space region, where said fixed portion faces said pivotal portion and the supply path and the exhaust path are separated, to an outside of said rotary joint.

US Pat. No. 10,141,205

APPARATUS AND METHOD FOR CLEANING SEMICONDUCTOR WAFER

ACM Research (Shanghai) I...

1. An apparatus for cleaning semiconductor wafer comprising:a brush module having a brush head for providing mechanical force on a surface of a wafer;
a swing arm of which an end mounts the brush module, wherein the brush module is vertically disposed and includes a brush base, a bearing, a flexible component, at least one damper, a mounting section, a brush shell and a coil spring, the brush head is mounted on the brush base, an end of the bearing connects with the brush base and the other end of the bearing penetrates into the brush shell and connects to a side of the flexible component, the other side of the flexible component connects with the damper which is mounted on the brush shell, the coil spring is received in the brush shell, an end of the coil sing is fixed on the side of the flexible component and the other end of the coil spring is fixed on the mounting section which is the top plate of the brush shell and opposite to the flexible component, the brush shell is fixed at the end of the swing arm, an elastic deformation of the coil spring generates a press force that the brush head acts on the surface of the wafer, and the elastic deformation of the coil spring is determined by a height of a process position of the brush module;
a rotating actuator connected with the other end of the swing arm, the rotating actuator driving the swing arm to swing across the whole surface of the wafer, which brings the brush head moving across the whole surface of the wafer; and
an elevating actuator connected with the other end of the swing arm, the elevating actuator driving the swing arm to rise or descend, which brings the brush module rising or descending.

US Pat. No. 10,141,203

ELECTRICAL INTERCONNECT STRUCTURE FOR AN EMBEDDED ELECTRONICS PACKAGE

General Electric Company,...

1. An electronics package comprising:an upper insulating layer;
at least one electrical component positioned within an opening in the upper insulating layer;
a patterned contact layer comprising at least one electrical connection formed on a first surface of the upper insulating layer;
a lower insulating layer coupled to the upper insulating layer and the at least one electrical component;
an upper interconnect layer formed on a second surface of the upper insulating layer and electrically coupled to the patterned contact layer; and
a lower interconnect layer formed on the lower insulating layer and electrically coupled to the upper interconnect layer and the at least one electrical component.

US Pat. No. 10,141,202

SEMICONDUCTOR DEVICE COMPRISING MOLD FOR TOP SIDE AND SIDEWALL PROTECTION

QUALCOMM Incorporated, S...

12. An apparatus comprising:a substrate;
a plurality of metal layers and dielectric layers coupled to the substrate;
a pad coupled to one of the plurality of metal layers;
a passivation layer on a surface of the plurality of metal layers and dielectric layers and coupled to the pad;
a first metal redistribution layer above the passivation layer and coupled to the pad;
a first insulation layer between the passivation layer and the first metal redistribution layer;
a second insulation layer at least partially above the first metal redistribution layer, wherein the second insulation layer further comprises a side formed by a trough;
an under bump metallization (UBM) layer above the second insulation layer, coupled to the first metal redistribution layer via a cavity in the second insulation layer; and
a means for protecting the apparatus from cracking during a cutting process, the means for protecting covering a first surface of the apparatus, at least a side portion of the apparatus including the side of the second insulation layer, and a portion of the UBM layer,
wherein at least a portion of the second insulation layer is between the first metal redistribution layer and the means for protecting,
wherein the side of the second insulation layer is spaced apart from a plane including both an exterior sidewall of the means for protecting and an exterior sidewall of the plurality of metal layers and dielectric layers by a portion of the means for protecting.

US Pat. No. 10,141,190

MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A method of manufacturing a semiconductor device comprising:forming a multilayer structure by stacking first insulating films and second insulating films or metal films;
forming a hole through the multilayer structure in a stacking direction;
forming a block insulating film, a charge storage film, and a tunnel insulating film on an inner surface of the hole;
forming the semiconductor layer containing the impurity on the tunnel insulating film on the inner surface of the hole;
forming an oxide film on the semiconductor layer containing an impurity;
performing a heat treatment on the semiconductor layer to diffuse part of the impurity into the oxide film with hydrogen plasma treatment on the oxide film or ultraviolet irradiation on the oxide film; and
removing the oxide film after the heat treatment.

US Pat. No. 10,141,184

METHOD OF PRODUCING SELF-SUPPORTING NITRIDE SEMICONDUCTOR SUBSTRATE

TOHOKU UNIVERSITY, Miyag...

1. A method of producing a free-standing nitride semiconductor substrate, comprising: a first step of forming a buffer layer of a nitride semiconductor that is one of GaN, AlN, InGaN, and InN on a main surface of a single crystalline substrate;a second step of forming a crystallized layer including a plurality of growth islands each of which is a hexagonal platelet with an N-polar upper surface, by annealing the buffer layer and thereby converting the buffer layer into a single crystal;
a third step of fabricating a continuous layer including the plurality of growth islands by promoting the lateral growth of the plurality of growth islands along the main surface of the single crystalline substrate and thereby performing coalescence of the plurality of growth islands;
a fourth step of forming a boule of the nitride semiconductor on the continuous layer by performing the crystal growth of the nitride semiconductor with an N-polar upper surface on the continuous layer;
a fifth step of removing the single crystalline substrate from the boule; and
a sixth step of fabricating a plurality of free-standing nitride semiconductor substrates by cutting the boule,
wherein the single crystalline substrate is made of a single crystalline ScAlMgO4,
wherein
the nitride semiconductor is one of GaN, InGaN, and InN, and
the fourth step includes steps of (a) forming an AlN layer on the continuous layer, (b) oxidizing a surface of the AlN layer, (c) nitriding the surface of the AlN layer which has been oxidized, and (d) performing the crystal growth of the nitride semiconductor with an N-polar upper surface on the AlN layer.

US Pat. No. 10,141,177

MASS SPECTROMETER USING GASTIGHT RADIO FREQUENCY ION GUIDE

1. A mass spectrometer, comprising:(a) a vacuum recipient containing ion handling elements, the vacuum recipient having a plurality of walls which define a gastight volume and comprise at least one of an entrance and exit, wherein different portions of an ion path pass at least one of the entrance and exit and run through the gastight volume; and
(b) a gastight radio frequency ion guide having an ion passage along an axis and being mounted gastight to at least one of the entrance and exit as to extend the gastight volume and continue the ion path in its ion passage outside the vacuum recipient,
wherein the gastight radio frequency ion guide is located outside the vacuum recipient in an environment of ambient pressure in order to lower pumping requirements for the mass spectrometer.

US Pat. No. 10,141,174

METHOD FOR EXAMINING A GAS BY MASS SPECTROMETRY AND MASS SPECTROMETER

Carl Zeiss SMT GmbH, Obe...

1. A method, comprising:producing ions by ionizing a gas;
storing at least some of the ions in an FT ion trap; and
detecting at least some of the ions in the FT ion trap,
wherein at least one of the following holds:
i) producing the ions comprises exposing the ions to an IFT excitation based on a mass-to-charge ratio of the ions;
ii) storing the ions in the FT ion trap comprises exposing the ions to an IFT excitation based on a mass-to-charge ratio of the ions; and
iii) before detecting the ions in the FT ion trap, exposing the ions to an IFT excitation based on a mass-to-charge ratio of the ions, and
wherein:
a degree of excitation and/or a phase angle of the IFT excitation are varied between a first excitation frequency and a second excitation frequency; and
both the first excitation frequency and the second excitation frequency deviate from a predetermined excitation frequency by no more than 10%.

US Pat. No. 10,141,172

SYNCHRONISED VARIATION OF SOURCE CONDITIONS OF AN ATMOSPHERIC PRESSURE CHEMICAL IONISATION MASS SPECTROMETER COUPLED TO A GAS CHROMATOGRAPH TO IMPROVE STABILITY DURING ANALYSIS

MICROMASS UK LIMITED, Wi...

1. A mass spectrometer comprising:a gas chromatography separation device;
an atmospheric pressure ionisation ion source; and
a control system arranged and adapted:
(i) to operate said atmospheric pressure ionisation ion source at one or more first settings for a first period of time whilst one or more solvents elute from said gas chromatography separation device during a solvent front free of analytes which is prior to the elution of one or more analytes from said gas chromatography separation device; and then
(ii) to operate said atmospheric pressure ionisation ion source at one or more second different settings for a second subsequent period of time whilst said one or more analytes elute from said gas chromatography separation device.

US Pat. No. 10,141,170

DEVICE FOR MASS SPECTROMETRY

TOFWERK AG, Thun (CH)

1. A device for mass spectrometry comprising:a) an ionization source;
b) a mass analyzer fluidly coupled to the ionization source;
c) an electronic data acquisition system for processing signals provided by the mass analyzer;whereas the electronic data acquisition system comprisesd) at least one analog-to-digital converter producing digitized data from the signals obtained from the mass analyzer;
e) a fast processing unit receiving the digitized data from said analog-to-digital converter;whereinf) the fast processing unit is programmed to continuously, in real time inspect the digitized data for events of interest measured by the mass spectrometer, wherein said inspection is based on a filter definition, the filter definition comprising at least one region of interest including a selection of values of m/Q and further comprising at least one filter criterion to be applied to the at least one region of interest, wherein the selection of values of m/Q is a subsection of all values of m/Q of an entire mass spectrum; and
g) the electronic data acquisition system is programmed to forward the digitized data representing mass spectra relating to events of interest for further analysis and to reject the digitized data representing mass spectra not relating to events of interest.

US Pat. No. 10,141,168

METHOD FOR CHARACTERISING A SAMPLE BY MASS SPECTROMETRY IMAGING

IMABIOTECH, Loos (FR)

1. A process for identifying by mass spectrometry imaging (MSI) a molecule of interest in a sample of interest, the process comprising:analyzing a spatial arrangement of a plurality of ions in the sample of interest from MSI data of said ions in said sample to determine morphometric features and/or texture features associated with said ions in said sample, the morphometric features defining geometrical patterns formed by a presence of said ions and mathematical dimensions of the geometrical patterns, the texture features defining an arrangement of the geometrical patterns in said sample;
comparing the morphometric and/or texture features associated with the plurality of ions in said sample of interest with morphometric and/or texture data associated with a plurality of ions in a reference sample;
identifying at least one characteristic ion of the sample; and
identifying the molecule corresponding to said identified ion.

US Pat. No. 10,141,166

METHOD OF REAL TIME IN-SITU CHAMBER CONDITION MONITORING USING SENSORS AND RF COMMUNICATION

Applied Materials, Inc., ...

1. A reactor for processing a workpiece, the reactor comprising:a chamber comprising:
a cylindrical sidewall;
a ceiling;
a floor; and
a pedestal for supporting a workpiece inside said chamber;
plural wireless sensors each having a wireless transceiver and secured to said chamber and fixed in locations inside said chamber;
a process controller outside of said chamber and connected to said chamber to govern process parameters in said chamber, wherein said cylindrical sidewall, said ceiling, and said floor are conductive such that said chamber blocks wireless communication channels between respective ones of said sensors and said process controller;
a wireless communication hub inside of said chamber and programmed to maintain respective independent wireless communication channels between the wireless transceiver of respective ones of said sensors and said wireless communication hub; and
a communication path between said wireless communication hub and said process controller.

US Pat. No. 10,141,164

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus comprising:a radio frequency (RF) power source connected between a reference electrode and a base stand to apply an RF voltage;
an electrostatic chuck arranged on the base stand;
a gas storage unit configured to store a gas, the gas storage unit being arranged in the base stand and including a gas introducing port;
a blocking mechanism configured to open and close the gas introducing port;
a control unit configured to control the blocking mechanism to open the gas introducing port; and
a connection unit configured to connect the gas storage unit and a space between a substrate set on the electrostatic chuck and the electrostatic chuck, wherein:
the apparatus is configured to introduce the gas into the gas storage unit from an outside gas source through the gas introducing port, and
the control unit is configured to open the gas introducing port when no RF voltage is applied between the reference electrode and the base stand by the RF power source.

US Pat. No. 10,141,163

CONTROLLING ION ENERGY WITHIN A PLASMA CHAMBER

Lam Research Corporation,...

1. A method comprising:generating a first sinusoidal radio frequency (RF) signal for providing to an upper electrode of a plasma chamber;
generating a second sinusoidal RF signal;
filtering the second sinusoidal RF signal to generate a nonsinusoidal RF signal having no off cycles;
amplifying the nonsinusoidal RF signal to generate an amplified nonsinusoidal RF signal;
filtering the amplified nonsinusoidal RF signal to generate a filtered nonsinusoidal RF signal having a series of pulses between consecutive off cycles; and
providing the filtered nonsinusoidal RF signal to a lower electrode of the plasma chamber.

US Pat. No. 10,141,161

ANGLE CONTROL FOR RADICALS AND REACTIVE NEUTRAL ION BEAMS

Varian Semiconductor Equi...

1. A workpiece processing apparatus, comprising:a plasma generator;
a plasma chamber; and
one extraction plate having a first aperture and a second aperture;
wherein charged ions are extracted through the first aperture at a first selected extraction angle, and reactive neutrals are passed through the second aperture at a second selected extraction angle, where the second aperture is different than the first aperture and comprises a suppressor to minimize charged ions passing through the second aperture by repelling or neutralizing the charged ions.

US Pat. No. 10,141,158

WAFER AND DUT INSPECTION APPARATUS AND METHOD USING THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A wafer and a device under test (DUT) inspection apparatus, comprising:a vacuum chamber;
a stage disposed in the vacuum chamber and near a first end of the vacuum chamber, wherein the stage is configured to hold a wafer or DUT;
an electron gun disposed in the vacuum chamber and near a second end of the vacuum chamber opposite to the first end for providing an E-beam;
a lens system disposed between the stage and the electron gun, wherein the lens system is a total reflective achromatic lens system comprising:
a first lens having a first aperture; and
a second lens having a second aperture aligned with the first aperture, the second lens is disposed between the electron gun and the first lens;
an optical mirror disposed between the lens system and the electron gun, wherein the optical mirror has a slit aligned with the second aperture, thereby allowing the E-beam to pass through the slit, the first aperture and the second aperture;
a beam shaping aperture disposed between the electron gun and the optical mirror;
a grating horizontally aligned with the optical mirror and configured to reflect towards the detector cathodoluminescence reflected from the optical mirror; and
a detector aligned with the grating, wherein the detector is configured to detect the cathodoluminescence for forming an image.

US Pat. No. 10,141,155

ELECTRON BEAM EMITTERS WITH RUTHENIUM COATING

KLA-Tencor Corporation, ...

1. An apparatus comprising:a silicon emitter, wherein the silicon emitter has a diameter of 100 nm or less; and
a protective cap layer disposed on an exterior surface of the silicon emitter, wherein the protective cap layer includes ruthenium.

US Pat. No. 10,141,153

MAGNETRON HAVING ENHANCED COOLING CHARACTERISTICS

Applied Materials, Inc., ...

1. A cooling assembly, comprising:a plurality of cooling fins, each cooling fin having a central opening; and
one or more flow directing structures formed between neighboring cooling fins, wherein the one or more flow directing structures form a flow channel between the neighboring cooling fins, wherein each flow directing structure intersects two or more cooling fins, wherein the one or more flow directing structures comprises channel walls that are contiguous from a front edge of the cooling fin to an air restriction facing a rear edge of the cooling fin, and wherein the channel walls define the flow channel that expands in a cone-shape from the air restriction adjacent the rear edge to the front edge.

US Pat. No. 10,141,152

DRIFT CHAMBER CONNECTION METHODS AND APPARATUS

1. A method for attaching a signal wire to a drift chamber, the method comprisingfeeding a signal wire through an end of a drift chamber;
feeding the signal wire through the dielectric tube;
extending the dielectric tube outwardly from the drift chamber end;
at a location on the outside of the drift chamber end, setting the extending dielectric tube and signal wire together to thereby fit the signal wire to the drift chamber end and gas seal the dielectric tube end;
feeding the signal wire through a second end of the drift chamber;
feeding the signal wire through the second dielectric tube;
extending the extending the second dielectric tube outwardly from the drift chamber second end; and
at a second location on the outside of the drift chamber second end, setting the extending dielectric second tube and signal wire together to thereby fit the signal wire to the drift chamber second end and gas seal the dielectric second tube.

US Pat. No. 10,141,151

FUSE WITH SEPARATING ELEMENT

Robert Bosch GmbH, Stutt...

1. A fuse (1) comprising:a U-shaped fusible element (2) with
a first portion (3),
a second portion (4) generally parallel to the first portion (3), and
a connecting portion (5) which connects the first portion (3) to the second portion (4),
such that the first portion (3), the second portion (4), and the connecting portion (5) define a plane,
a separating element (6) which is configured to prevent an arc between the first portion (3) and the second portion (4),
a first field-generating device (7a) for generating a first magnetic field in the region of the connecting portion (5), and
a second field-generating device (7b) for generating a second magnetic field in the region of the connecting portion (5),
wherein the first and second field-generating devices (7a, 7b) are permanent magnets,
wherein the first portion (3) of the fusible element (2) extends on a first side of the separating element (6),
wherein the second portion (4) of the fusible element (2) extends on a second side of the separating element (6), which is situated opposite the first side,
wherein the connecting portion (5) of the fusible element (2) extends on a third side of the separating element (6),
wherein the first and second field-generating devices (7a, 7b) are positioned on opposite sides of the fusible element (2) and on opposite sides of the plane, and
wherein the first and second magnetic fields are directed in such a manner that an arc, caused by a current, between the first portion (3) and the second portion (4) is directed toward the separating element (6).

US Pat. No. 10,141,148

AFFIXED OBJECT, FUSIBLE LINK, AND AFFIXING STRUCTURE FOR FUSIBLE LINK

Yazaki Corporation, Toky...

1. An affixed object affixed to an affixing object including an installation surface portion, an intersection surface portion extending in a direction intersecting the installation surface portion, and a locking portion provided in the intersection surface portion, the affixed object comprising:an affixed-object body to be installed in the installation surface portion; and
a locking member, attached to the affixed-object body, including:
a locked portion to be locked to the locking portion;
a first arm portion extending from the affixed-object body along the installation surface portion;
a connection portion which is elastically deformed and has one end connected to an end portion of the first arm portion; and
a second arm portion having an end portion connected to the other end of the connection portion, extending along the intersection surface portion, and provided with the locked portion,
wherein the locking member is provided on a wall portion of the affixed-object body such that the affixed-object body is sandwiched between the locking member and the affixing object when the affixed object is affixed to the affixing object,
wherein the connection portion is bent such that the one end of the connection portion extends away from the installation surface portion as the connection portion extends away from the first arm portion, and the other end of the connection portion extends away from the intersection surface portion as the connection portion extends away from the second arm portion, and
wherein a gap is formed between the connection portion and the affixing object.

US Pat. No. 10,141,146

FORCE-DISTANCE CONTROLLED MECHANICAL SWITCH

1. A switch comprising:a first elastic element;
a second elastic element;
an actuator-element mechanically coupled to a first side of the first elastic element and mechanically coupled to a first side of the second elastic element;
a first switching conductor mechanically coupled to a second side of the first elastic element;
a second switching conductor mechanically coupled to a second side of the second elastic element; and
a first strip conductor, a second strip conductor and a third strip conductor; and
wherein the first switching conductor is configured to move between a first conductor position and a second conductor position,
wherein the actuator-element is configured to move between a first position and a second position separated by a pre-defined actuator-element lift, thereby moving the first side of the first elastic element, and to move the first side of the second elastic element while moving between the first position and the second position,
wherein the first elastic element is configured to convert a movement of the first side of the first elastic element by the pre-defined actuator-element lift into a movement of the second side of the first elastic element with a pre-defined elastic force,
wherein the second elastic element is configured to convert the movement of the first side of the second elastic element by the pre-defined actuator-element lift into the movement of the second side of the second elastic element with the pre-defined elastic force,
wherein the first switching conductor and the second switching conductor are configured whereby, in the first conductor position, the first strip conductor is in contact with the first switching conductor, the second strip conductor is in contact with the first switching conductor and the second switching conductor is not in contact with the first strip conductor, the second strip conductor and the third strip conductor.

US Pat. No. 10,141,145

RELAY APPARATUS HAVING PLURALITY OF RELAYS AND RELAY SYSTEM INCORPORATING THE RELAY APPARATUS

NIPPON SOKEN, INC., Nish...

1. A relay apparatus, comprising:a first relay, the first relay comprising:
a first electromagnetic coil;
a first movable magnetic member;
a first electromagnetic coil; and
a first contact switch, the first contact switch being set to a predetermined one of a conducting condition and a non-conducting condition by a magnetic flux produced by the first electromagnetic coil acting on the first movable magnetic member;
a second relay, the second relay comprising:
a second electromagnetic coil;
a second movable magnetic member; and
a second contact switch, the second contact switch being set to a predetermined one of the conducting condition and non-conducting condition by a magnetic flux produced by the second electromagnetic coil acting on the second movable magnetic member;
a yoke, the yoke being configured to partially surround each of the first electromagnetic coil and the second electromagnetic coil;
a first magnetic circuit extending around the first electromagnetic coil and through a first core and the yoke, the relay apparatus being operable for producing a flow of a first magnetic flux via the first magnetic circuit by passing a current through the first electromagnetic coil;
a second magnetic circuit extending around the second electromagnetic coil and through a second core and the yoke, the relay apparatus being operable for producing a flow of a second magnetic flux via the second magnetic circuit by passing a current through the second electromagnetic coil; and
a third magnetic circuit extending successively through the first core, the yoke, and the second core, the relay apparatus being operable for producing a flow of a third magnetic flux via a third magnetic circuit by passing respective currents concurrently through the first electromagnetic coil and the second electromagnetic coil,
wherein the yoke comprises a magnetic flux restriction portion formed to restrict the flow of magnetic flux via the third magnetic circuit.

US Pat. No. 10,141,144

SELF-POWERED SWITCHES AND RELATED METHODS

Eaton Intelligent Power L...

1. A self-powered switch, comprising:an externally accessible user input member;
a switch housing attached to the user input member;
a permanent magnet held in the switch housing;
a magnet housing held in the switch housing, wherein the magnet housing is attached to the user input member and is pivotably attached to the switch housing via at least one spindle, and wherein the magnet housing resides under a medial portion of the user input member; and
a magnet assembly comprising a coil and a shaft extending a distance beyond the coil held in the switch housing,
wherein at least one of the magnet assembly and permanent magnet moves in response to movement of the user input member to thereby induce a voltage to power a transmitter associated with the switch.

US Pat. No. 10,141,143

WEAR-BALANCED ELECTROMAGNETIC MOTOR CONTROL SWITCHING

Rockwell Automation Techn...

1. A method comprising:in a first switching operation of an electrical power switching system comprising three separately controllable single pole, single current-carrying path switching devices configured to provide three-phase power to a load, and control circuitry coupled to the switching devices to control closing and opening of the current-carrying paths, commanding at least one of the switching devices to open or close in advance of at least one other of the switching devices based upon a current zero-crossing or a predicted current zero-crossing of input three-phase power; and
in subsequent switching operations alternating which of the three switching devices is closed or opened in advance of another of the switching devices.

US Pat. No. 10,141,141

MAGNETICALLY ACTUATED SWITCH

S. J. Electro Systems, In...

1. A magnetically activated switch, comprising:an arm member having a first magnet, the first magnet including a first magnet portion and a second magnet portion spaced apart to form a channel therebetween;
an actuating member having a second magnet, the actuating member being configured and arranged to move relative to the arm member thereby moving the second magnet relative to the first magnet, the second magnet moving through the channel, the second magnet having a repulsion force to the first magnet, the second magnet having a north pole on a first side and a south pole on a second side, the first magnet portion having a north pole on a side adjacent the first side of the second magnet and the second magnet portion having a south pole on a side adjacent the second side of the second magnet when the second magnet is moving through the channel; and
a switch having a contact, wherein movement of the second magnet in a first direction past the first magnet positions the contact in an open position and movement of the second magnet in a second direction past the first magnet positions the contact in a closed position.

US Pat. No. 10,141,140

AIR CIRCUIT BREAKER

LSIS CO., LTD., Ayang-si...

1. An air circuit breaker comprising:an insulating cage provided with a plurality of contact plates;
movable contactors each inserted between the contact plates; and
fixed contactors brought into contact with or separated from the movable contactors in response to a movement of the movable contactors,
wherein each of the contact plates is provided with a recess,
wherein the recess is inclined toward an inside of the contact plates from rear sides of the contact plates to front sides of the contact plates,
wherein in a connected state, the movable contactors are pushed toward the insulating cage to be inserted between the contact plates and thus brought into contact with the contact plates, and
wherein a middle part of the movable contactors does not contact the contact plates by the recess.

US Pat. No. 10,141,138

SWITCH ASSEMBLY

FORD GLOBAL TECHNOLOGIES,...

1. A switch assembly, comprising:a switch including a button and an arm extending from the button along a height direction, the arm including first and second contact portions spaced along a longitudinal direction; and
a slider unit extending along a width direction, including a polymeric nose, positioned between the arm and a spring along the width direction to contact the first and second contact portions, respectively, at first and second engagement positions.

US Pat. No. 10,141,137

LATCH-FREE ACTUATORS

ABB Schweiz AG, Baden (C...

1. A mechanism, said mechanism comprising:a movable arm;
first biasing means operable to apply a force to move said movable arm in a first direction;
a yieldable support having a rigid configuration defining a generally straight axis and a flexible configuration defining a non-straight axis;
said yieldable support operable in said rigid configuration to support a compression force along said straight axis due to and countering said first biasing means so that said movable arm is prevented from movement in said first direction; and
said yieldable support operable, by applying a tripping force, to said yieldable support to transition said rigid configuration to said flexible configuration to withdraw support of the compression force and allow said movable arm to be moved by said first biasing means in said first direction;
wherein said yieldable support comprises a flat elongated member having a curved cross-section.

US Pat. No. 10,141,136

LIGHT SWITCH ACTUATOR

1. A mechanism for operating an electric switch comprising:a toggle switch, a wall plate, a toggle attachment, a plurality of eyebolts, and a plurality of cords;
wherein the plurality of eyebolts attach to the wall plate;
wherein the toggle attachment attaches the plurality of cords to a toggle of the toggle switch;
wherein the mechanism for operating the electric switch is a kit;
wherein the toggle switch is further defined with a toggle;
wherein the toggle switch is further defined with one or more interior screw threads;
wherein the wall plate is placed over the toggle switch;
wherein the wall plate is further defined with a first switch screw hole and a second switch screw hole;
wherein the toggle actuates the toggle switch;
wherein the first switch screw hole and second switch screw hole allow the wall plate to be attached to the toggle switch;
wherein the first switch screw hole is a hole that is formed through the wall plate;
wherein the second switch screw hole is a hole that is formed through the wall plate;
wherein the toggle attachment is formed from an elastomeric material;
wherein the elastomeric material is deformed as the toggle attachment is attached to the toggle;
wherein any eyebolt selected from the plurality of eyebolts is sized such that the selected eyebolt can be inserted through a screw hole selected from the group consisting of the first switch screw hole of the wall plate and the second switch screw hole of the wall plate;
wherein any eyebolt selected from the plurality of eyebolts is sized such that the selected eyebolt can be screwed directly into an interior screw thread selected from the one or more interior screw threads;
wherein each of the plurality of cords is a cord;
wherein an end of each of the plurality of cords attaches to the toggle attachment;
wherein the plurality of cords are arranged such that pulling on a cord selected form the plurality of cords will actuate the toggle switch;
wherein the toggle attachment comprises an elastic ring;
wherein the elastic ring is a ring shaped structure;
wherein the elastic ring further comprises a ring aperture;
wherein the elastic ring is formed from an elastomeric material;
wherein the ring aperture is placed over the toggle of the toggle switch;
wherein the ring aperture is sized such that the ring aperture must be deformed in order to fit over the toggle of the toggle switch;
wherein as the elastic ring returns to its relaxed shape the ring aperture applies a force to the toggle;
wherein the plurality of eyebolts attach the wall plate to the toggle switch;
wherein each of the plurality of eyebolts is an eyebolt;
wherein each of the plurality of eyebolts is further formed with an exterior screw thread;
wherein the plurality of eyebolts comprises a first eyebolt and a second eyebolt;
wherein the first eyebolt attaches the wall plate to the toggle switch;
wherein the second eyebolt attaches the wall plate to the toggle switch;
wherein the first eyebolt is sized such that the first eyebolt inserts through the first switch screw hole;
wherein the first eyebolt is sized such that the first eyebolt screws into a first interior screw thread selected from the one or more interior screw threads;
wherein the second eyebolt is sized such that the second eyebolt inserts through the second switch screw hole;
wherein the second eyebolt is sized such that the second eyebolt screws into a second interior screw thread selected from the one or more interior screw threads.

US Pat. No. 10,141,133

ELECTRONIC DEVICE INCLUDING KEY

Samsung Electronics Co., ...

1. An electronic device including a key, comprising:a housing covering at least a portion of a front of an electronic device and having a lower portion that includes a through-hole formed therein;
a structure provided on a back side of the electronic device, wherein the structure comprises a lower part corresponding to the lower portion of the housing;
a key having a front surface at least partially exposed through the through-hole and a rear surface facing opposite the front surface, wherein the key is configured to be pressed by a user in a direction toward the structure;
a key switch located between the rear surface of the key and the structure, wherein the key switch is configured to enable the key to be pressed;
a dummy detachably provided between the housing and the structure, wherein the dummy, when attached, supports the key and the key switch such that the key and the key switch are capable of being pressed in the through-hole toward the direction of the structure;
a flange protruded from an outer periphery of the key; and
at least one or more adhesive members are provided between the lower surface of the dummy and the structure,
wherein the dummy, when attached, be stacked on the one or more adhesive members, and
wherein the dummy is provided on an upper surface of at least part of the flange.

US Pat. No. 10,141,132

DUAL-ACTUATOR SWITCH

SOLTEAM ELECTRONICS (DONG...

1. A dual-actuator switch, comprising:a base, having an accommodating space;
a first electrical connection member, being disposed in the accommodating space and having a first electrical terminal and a second electrical terminal;
a second electrical connection member, being disposed in the accommodating space for facing the first electrical connection member, and having a third electrical terminal and a fourth electrical terminal for respectively connecting the first electrical terminal and the second electrical terminal;
a first isolation sleeve cylinder, being disposed in the accommodating space and provided with a first protrusion member on the outer wall thereof;
a second isolation sleeve cylinder, being disposed in the accommodating space and provided with a second protrusion member on the outer wall thereof;
a first return spring, being disposed in the first isolation sleeve cylinder;
a first post-shaped actuator, being disposed in the first isolation sleeve cylinder and connecting with the first return spring;
a second return spring, being disposed in the second isolation sleeve cylinder;
a second post-shaped actuator, being disposed in the second isolation sleeve cylinder and connecting with the second return spring; and
a cover, being assembled with the base for sheltering the accommodating space, and having two openings;
wherein a first pressing portion of the first post-shaped actuator and a second pressing portion of the second post-shaped actuator are extended out of the cover via the two openings.

US Pat. No. 10,141,129

INTERLOCK APPARATUS OF RING MAIN UNIT

LSIS CO., LTD., Anyang-s...

1. An interlock apparatus of a ring main unit including two or more switches where a plurality of insertion holes into which a handle can be inserted are respectively provided for controlling a closed or cutoff state, the interlock apparatus comprising:a plate disposed in front of each of the plurality of insertion holes, wherein when one of the plurality of insertion holes is opened, the plate moves so that another insertion hole is closed, a plurality of fitting grooves formed in an upper end of the plate;
an indicator provided in each of the two or more switches, wherein the indicator rotates by controlling a closed or cutoff state of each of the two or more switches; and
a movement prevention member provided in each of the two or more switches to prevent a movement of the plate, wherein when one of the switches is in a closed state, the movement prevention member is inserted into one of the plurality of fitting grooves according to a rotation of the indicator, thereby maintaining an open state of the one insertion hole and a closed state of the other insertion hole.

US Pat. No. 10,141,128

METHOD AND APPARATUS FOR AUTHENTICATING AND DETECTING CIRCUIT BREAKER INTEGRITY

Eaton Corporation, Cleve...

1. A circuit breaker apparatus comprising:a housing;
a circuit disposed in the housing and configured to connect a power line to a load via one or more conductors and provide circuit protection for the one or more conductors and the load;
a display attached to an outside surface of the housing;
a controller;
a power control device electrically coupled to the display and the controller, and configured to provide power to the controller when the apparatus is being tampered with; and
a first RFID tag attached to the apparatus, the first RFID tag containing authentication data therein;
wherein the controller is configured to, when powered, cause the power control device to cause the display to change from a first state to a second state, wherein the first state indicates that the apparatus is authenticated and the second state indicates that the apparatus has been tampered with; and
wherein the controller is further configured to initialize the display to the first state by:
retrieving the authentication data from the first RFID tag,
retrieving a key stored external to the apparatus,
using the key to determine whether the authentication data retrieved from the first RFID tag is valid, and
upon determining that the authentication data retrieved from the first RFID tag is valid, causing the power control device to initialize the display to the first state.

US Pat. No. 10,141,125

CONTACT FOR BUS PLUG SWITCHES

1. A single-pole electrical switch for a bus plug, comprising:a stationary contact having a first contact surface;
a moveable contact having a second contact surface, the moveable contact mounted to a contact head pivotally-mounted to a rotating contact arm about a pivot axis, the moveable contact rotatably moveable between an open position and a closed position, the closed position bringing the first and second contact surfaces into mutual contact and completing thereby an electrical circuit, wherein in the closed position the pivot axis is entirely in a plane bisecting the second contact surface at a right angle;
a switching means to move the contacts between the open position and the closed position;
whereby, when the switching means moves the movable contact into the closed position, the contact surfaces are aligned by articulation of the pivotally-mounted second contact, and pitting of the contact surfaces by electric current flowing there through is prevented by intimate engagement.

US Pat. No. 10,141,124

ELECTRONIC COMPONENT FABRICATION METHOD USING REMOVABLE SPACERS

Yen Technologies, LLC, W...

1. An apparatus comprising:a plurality of electrodes in a stack, wherein spacing between adjacent electrodes in the stack is determined by one or more removable spacers that are removed prior to bonding adjacent electrodes together to fix the spacing.

US Pat. No. 10,141,121

SUPER ELECTRICAL BATTERY

1. An electric energy storage device comprising:a first conductor layer in a multilayer structure both surfaces of which comprising a first ionic or dipole material layer adjacent to an entire conductor surface thereof and being insulated electrically;
a second conductor layer in the multilayer structure, both surfaces of which comprising a second ionic or dipole material layer adjacent to an entire conductor surface thereof and being insulated electrically, wherein a bilayer hetero-structure is comprised of the first and second conductor layers and the ionic material layer sandwiched therebetween,
wherein the multilayer structure is comprised of the millions of conductor layers of nanometer thickness, both conductor surfaces of which being coated with the ionic or dipole materials across the enter surface thereof and being insulated electrically,
wherein the first and second conductor layers form the bilayers configured to store an electrical energy in the bilayer in a form of binding energy,
wherein the multilayer is consisted of the millions of the bilayers,
wherein the ionic or dipole material layers comprise an ionic or dipole material selected from the group consisting of MgSO4, LiPF6, LiCl04, LiN(CF3S02)2, LiBF4, LiCF3S03, LiSbF6, Li4Ti5012, ionic polymers, ionic mineral materials, and dipole materials, wherein the ionic or dipole material is MgSO4,
wherein a thickness of the conductor layers and the interval between the conductor layers are a nanometer scale to form a quantum dipole system of excitons and ions, so that an interaction between excitonic dipoles and ionic dipoles occur in the bilayer hetero-structure;
a positive electrode attached to the first conductor layer of the multilayer structure; and
a negative electrode attached to the last conductor layer of the multilayer structure,
wherein every conductor layer in the multilayer structure is disconnected, insulated and isolated from an electric current, and each conductor layer is not a current collector, but an excitonic dipole collector,
wherein neither electronic nor ionic current is allowed in the multilayer structure except for the electrodes which are attached to a copper (conductor) sheet, because the current in the multilayer structure destroys the excitonic dipoles and the ionic dipoles,
wherein the first conductor layer is stacked on top of the second conductor layer with a nanometer-scale interval and the ionic or dipole material layer is sandwiched therebetween so as to form the bilayer structure,
wherein the electrical energy is stored in the bilayer by applying a DC voltage in a direction perpendicular to a layer plane sheet to the positive and negative electrodes,
wherein the stored an electrical energy is discharged and output to the electrodes by using an external AC field in a predetermined frequency range as a guiding wave with trigger power,
wherein the conductor layer is adopted because low excitation energy of valence electrons is required for jumping to a conduction band, and the nanometer thickness of the conductor layer is adopted because a reciprocal of a length of a layer period in the vertical direction shall be large for a polaron formation at an interface between the conductor layer and the ionic layer,
wherein the length of the layer period in the multilayer structure is in a range of the nanometer scale to have a quantum dipole interaction in the bilayers,
wherein the length of the layer period in the multilayer structure is in the range of nanometer scale for an electrical energy storage device, so that a spatial period of the conductor layers in the vertical direction is directly related to the polaron formation in the bilayers, and the thickness of conductor layers as well,
wherein a linear chain of excitonic dipoles and ionic dipoles is introduced and formed in the vertical direction to the conductor layers, and an optical vibration is governed to be tuned by the acoustical vibration and the frequencies of the vibrations as well,
wherein the layer thickness and interval between the conductor layers are in the range of the nanometer scale for formation of the quantum dipole system and exciton,
wherein the layer thickness and interval in the multilayer structure are in the range of the nanometer scale in order to have a polaron interaction effective, and the polaron formation at the interface between the conductor layer and the ionic layer is important in a storing an electrical energy in the bilayers, because an excitonic and ionic dipole structure has been transformed into an excitonic bipolaron which leads to the formation of a stable anti-ferroelectric structure in the bilayers,
wherein when an external field is applied, a polarization of ions and an excitation of the valence electrons to conduction band create a collective dipole in a multilayer system through a propagation of a dipole field (pseudo spin wave) from the electrodes to the empty states,
wherein an interaction energy between an excitonic dipole and an ionic dipole depends upon the directions and positions of the excitonic dipoles and ionic dipoles in the bilayer, which is a quasi-one dimensional interaction in the vertical direction to the conductor layers,
wherein in the nanometer scale, a charge polarization in a quantum hetero-structure is a quantum dipole,
wherein the states of electronic and ionic dipoles are described in the eigenstates of two-level system, which represents a transition,
wherein the interaction terms of excitonic dipoles and ionic dipoles describe a propagation of pseudo spin waves across the layers in the vertical direction to the layer plane sheet,
wherein the pseudo spin waves propagate crossing the conductor layers by an applied power, and as the pseudo spin waves propagate in the vertical direction, the excitonic dipoles and ionic dipoles spread all over the multilayer structure as the applied power continues to be provided by the external field,
wherein a mechanism for a charging process is induced by the polaron interaction, and by the polaron interaction and Coulomb force, the excitonic dipoles and ionic dipoles keep transforming into the anti-ferroelectric nanostructures in charge,
wherein the polaron interaction is so strong that the excitons in the conductor layer have been broken into the electrons and the holes to form the positive polarons and the negative polarons in the bilayers,
wherein the positive polarons on one conductor layer and the negative polarons on the other conductor are combined together to form excitonic bipolarons in the bilayers, and
wherein a mechanism for a storing energy in the multilayer structure is a transformation process from the quantum dipole system creating into an anti-ferroelectric nanostructure created by the applied power in the bilayers.

US Pat. No. 10,141,120

POWER STORAGE SYSTEM AND MANUFACTURING METHOD THEREOF AND SECONDARY BATTERY AND CAPACITOR

Semiconductor Energy Labo...

1. A power storage system comprising:a negative electrode comprising:
a current collector;
a negative electrode active material layer comprising a crystalline silicon film over and in contact with an upper surface of the current collector; and
a conductive oxide over and in contact with an upper surface of the crystalline silicon film,
wherein the conductive oxide comprises
one selected from the group consisting of nickel, copper, indium, tin, and silver.

US Pat. No. 10,141,119

DYE-SENSITIZED SOLAR CELLS INCLUDING CARBON NANOTUBE YARNS

Florida State University ...

1. A dye-sensitized solar cell, comprising:a working electrode comprising seven twisted carbon nanotube yarns;
a hybrid sensitizer which comprises:
a nanoporous titanium oxide layer coated on the seven twisted carbon nanotube yarns,
a microporous titanium oxide layer coated onto the nanoporous titanium oxide layer, and
dye particles and quantum dots disposed in the pores of the microporous titanium oxide layer, wherein the dye particles comprise N719 dye, and the quantum dots comprise CdS and CdSe;
a conducting electrode comprising one carbon nanotube yarn disposed about the hybrid sensitizer or three twisted carbon nanotube yarns disposed about the hybrid sensitizer; and
a solid state electrolyte disposed about the hybrid sensitizer.

US Pat. No. 10,141,118

CARRIER SYSTEM AND PHOTOELECTRIC CONVERSION DEVICE

ADEKA CORPORATION, Tokyo...

1. A carrier system comprising a carrier, a dye (A) and a co-adsorbent (B), wherein said dye (A) and co-adsorbent (B) are bonded or adsorbed to said carrier, and said co-adsorbent (B) is represented by general formula (1) below:
wherein, ring A represents a 5- or 6-membered heterocycle and may further be fused with another cyclic group;
a hydrogen atom in the ring A may be replaced by a halogen atom, a cyano group, a nitro group, an —OR2 group, an —SR2 group, or a hydrocarbon group that has a substituent or that is not substituted;
Z represents a divalent aliphatic hydrocarbon group that is interrupted zero to three times by —O—, —S—, —CO—, —COO—, —OCO—, —CONR3—, —NR3CO—, or —Z1—;
Z1 represents a divalent aromatic group;
R1 represents a group selected from a carboxylic acid group, a sulfonic acid group, a phosphoric acid group, and a phosphonic acid group;
R2 and R3 each independently represent a hydrogen atom or a hydrocarbon group that has a substituent or that is not substituted;
Anm? represents an m-valent anion;
m represents an integer of 1 or 2; and
p represents a coefficient for keeping the electrical charge neutral.

US Pat. No. 10,141,117

PROCESS OF FORMING A PHOTOACTIVE LAYER OF A PEROVSKITE PHOTOACTIVE DEVICE

COMMONWEALTH SCIENTIFIC A...

1. A process of forming a thin film photoactive layer of a perovskite photoactive device comprising:applying at least one coating to a substrate, the coating comprising at least one perovskite precursor solution and a crystallisation retardant for perovskite crystallisation comprising at least one polymer additive; and
crystallizing a perovskite photoactive layer on the substrate, the perovskite photoactive layer comprising a continuous and substantially uniform thin film perovskite layer,
wherein the polymer additive comprises from 0.01 to 5 wt % of reaction constituent; and
wherein the at least one perovskite precursor solution comprises at least one reaction constituent for forming at least one perovskite compound having the formula AMX3 dissolved in a coating solvent selected from at least one polar aprotic solvent, the polymer additive being soluble in said coating solvent, and in which A comprises an ammonium group or other nitrogen containing organic cation, M is selected from Pb, Sn, Ge, Ca, Sr, Cd, Cu, Ni, Mn, Co, Zn, Fe, Mg, Ba, Si, Ti, Bi, or In, and X is selected from at least one of F, Cl, Br or I,
and wherein the polymer additive retards the crystallisation rate of the perovskite precursor solution during perovskite crystallisation.

US Pat. No. 10,141,115

THIN FILM CAPACITOR INCLUDING ALTERNATIVELY DISPOSED DIELECTRIC LAYERS HAVING DIFFERENT THICKNESSES

SAMSUNG ELECTRO-MECHANICS...

1. A thin film capacitor comprising:a body having first and second electrode layers and first and second dielectric layers alternately stacked on a substrate, each of the number of the first dielectric layers, the number of the second dielectric layers, the number of the first electrode layers, and the number of the second electrode layers being two or greater; and
first and second vias electrically connected to the first and second electrode layers, respectively,
wherein a thickness of the first dielectric layer is 1.2 to 3 times that of the second dielectric layer.

US Pat. No. 10,141,114

MULTI-LAYER CERAMIC CAPACITOR AND METHOD OF PRODUCING THE SAME

Taiyo Yuden Co., Ltd., T...

1. A multi-layer ceramic capacitor, comprising:a body including
a first end surface and a second end surface that face each other,
a side surface that extends between the first end surface and the second end surface,
a first recess that extends along a first ridge of the first end surface and the side surface,
a second recess that extends along a second ridge of the second end surface and the side surface,
a first internal electrode that is drawn to the first end surface and the first recess, and
a second internal electrode that faces the first internal electrode and is drawn to the second end surface and the second recess;
a first external electrode that covers the body from the first end surface; and
a second external electrode that covers the body from the second end surface,
wherein a depth of the first recess from the first end surface is 30% or less of an interval between the first end surface and the second internal electrode, and a depth of the second recess from the second end surface is 30% or less of an interval between the second end surface and the first internal electrode.

US Pat. No. 10,141,113

CERAMIC ELECTRONIC COMPONENT

TDK Corporation, Tokyo (...

1. A ceramic electronic component comprising an interior part and an exterior part, whereinthe interior part includes an interior part dielectric layer and an internal electrode layer,
the exterior part includes an exterior part dielectric layer, the exterior part is positioned outside the interior part along a laminating direction thereof,
the interior part dielectric layer and the exterior part dielectric layer respectively contain barium titanate as a main component, and
????0.20 and ?/??0.88 are satisfied, where
? mol part is an amount of a rare earth element contained in the interior part dielectric layer, provided that an amount of barium titanate contained in the interior part dielectric layer is 100 mol parts in terms of BaTiO3 and
? mol part is an amount of a rare earth element contained in the exterior part dielectric layer, provided that an amount of barium titanate contained in the exterior part dielectric layer is 100 mol parts in terms of BaTiO3.

US Pat. No. 10,141,109

POWER STORAGE MODULE

AutoNetworks Technologies...

1. A power storage module comprising:a plurality of power storage elements that each have cathode and anode electrode portions;
a connection member that connects the cathodes and anodes of the power storage elements to each other and is fixed to the power storage elements by a fixing means; and
an insulating protector in which the connection member is housed,
wherein the insulating protector includes an opposing portion that opposes one surface of the connection member, and a partition wall that surrounds the connection member, the partition wall including a withdrawal restriction portion that protrudes inward from the partition wall and extends in a cantilevered manner so that he withdrawal restriction portion is capable of bending deformation and restricts withdrawal of the connection member from another surface side of the connection member, and the opposing portion and the withdrawal restriction portion have a first clearance that is the sum of a clearance between the one surface of the connection member and the opposing portion and a separate clearance between the other surface of the connection member and the withdrawal restriction portion in a state where the connection member is fixed to the power storage elements by the fixing means, and
the insulating protector further includes a restriction portion that restricts movement relative to the power storage elements by an amount greater than or equal to a second clearance that is smaller than the first clearance.

US Pat. No. 10,141,108

APPARATUS AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT

NITTOKU ENGINEERING CO., ...

1. An apparatus for manufacturing an electronic component, the apparatus comprising:a grip unit configured to grip an electronic member having a plurality of projections arranged thereon;
a connected coil assembly forming unit configured to form a connected coil assembly in which a plurality of single coils are connected to one another; and
a coil mounting unit configured to sequentially mount the plurality of single coils of the connected coil assembly on the plurality of projections.

US Pat. No. 10,141,107

MINIATURE PLANAR TRANSFORMER

Analog Devices, Inc., No...

1. An inductive device, comprising:a substrate;
a pair of half-shell magnetically-conductive housings each having a cavity and being joined together to define a first, enclosed cavity between them, and disposed fully within a second cavity in the substrate; and
primary and secondary windings provided spatially within the first cavity to provide magnetic coupling between them, the windings electrically insulated from each other by an insulator disposed between the windings that extends into the cavity of each of the half-shell magnetically-conductive housings, wherein terminals of the primary and secondary windings traverse to an exterior of the inductive device.

US Pat. No. 10,141,105

WIRELESS POWER TRANSMISSION SYSTEM FOR FREE-POSITION WIRELESS CHARGING OF MULTIPLE DEVICES

KOREA ELECTROTECHNOLOGY R...

1. A coil assembly, comprising:a coil part through which a current flows in a direction of an input current applied from a first end of the coil assembly, the coil part being disposed between the first end and a second end of the coil assembly,
wherein the coil part comprises:
a first coil part, two or more coils are connected in parallel and concentrically wound one or more times towards a center thereof so that the current flows in a direction of the input current; and
wherein the coil assembly transfers a wireless power via magnetic coupling with respective target coils, relative center positions of which are horizontally different from each other.

US Pat. No. 10,141,104

CONTACTLESS CONNECTOR

1. A contactless connector, comprising:an inductive coupling element having a coil winding;
a first contact lead and a second contact lead connected to the coil winding and carrying electric currents in opposing directions;
a base plate formed of a ferritic material and having a first lead receiving passageway receiving a contact lead of the first contact lead or the second contact lead, a second lead receiving passageway provided opposite the first lead receiving passageway receiving a contact lead of the other of the first contact lead or the second contact lead, an air gap extending continuously between the first and second lead receiving passageways and along a peripheral surface of the base plate and arranged in a magnetic path of a magnetic field induced by electric current flowing through the contact lead of the first contact lead or the second contact lead, and a component receiving passageway, a portion of the air gap along the peripheral surface of the base plate is filled with a non-magnetic material;
an inner ferrite element formed as a single part with the base plate, the component receiving passageway extending through the base plate and the inner ferrite element; and
an outer ferrite element partially surrounding the inductive coupling element, magnetically coupled to the base plate, and open to the inductive coupling element at a mating end of the outer ferrite element opposite the base plate.

US Pat. No. 10,141,101

TRANSFORMER AND SWITCHED-MODE POWER SUPPLY APPARATUS

Tamura Corporation, Toky...

1. A transformer, comprising:a core having a linear center leg portion in a center portion thereof;
a primary winding that is provided around the linear center leg portion of the core and is configured to be electrically connected to an external power source, wherein the primary winding creates a varying flux in the core in response to an input voltage applied from the external power source;
at least two secondary windings provided around the linear center leg portion of the core and having a winding axis which is the same as a winding axis of the primary winding, wherein each of the at least two secondary windings is configured to induce a voltage in response to the created varying flux in the core in order to provide the induced voltage to a load; and
at least two auxiliary windings provided around the linear center leg portion of the core and having a winding axis which is the same as the winding axis of the primary winding, the auxiliary windings respectively neighboring the secondary windings, wherein each of the at least two auxiliary windings is configured to induce a voltage in response to the created varying flux in the core, the auxiliary windings being connected with each other in a parallel electric connection,
wherein the auxiliary windings are electrically connected with a control circuit for controlling a switching element which is electrically connected with the primary winding and the auxiliary windings provide the control circuit with the induced voltage for driving the switching element, and
wherein the secondary windings are disposed at both sides of the primary winding in a winding axis direction of the primary winding and are disposed closer to the primary winding than the auxiliary windings, in the winding axis direction of the primary winding.

US Pat. No. 10,141,099

ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a magnetic body; and
an internal coil structure embedded in the magnetic body, wherein
the internal coil structure includes a first coil pattern part and a second coil pattern part formed on the first coil pattern part, and
an entire outermost coil turn of the first coil pattern part is thicker than an inner coil turn thereof, wherein the second coil pattern part has a non-uniform thickness such that a thickness from an uppermost surface of the outermost coil turn of the first coil pattern part to an uppermost surface of an outermost coil turn of the second coil pattern part is smaller than a thickness from an uppermost surface of the inner coil turn of the first coil pattern part to an uppermost surface of an inner coil turn of the second coil pattern part.

US Pat. No. 10,141,098

COIL COMPONENT

Murata Manufacturing Co.,...

1. A coil component comprising:a core having a winding core portion and first and second flange portions disposed on opposite ends of the winding core portion in a length direction, each of the first and second flange portions having an end surface to which a respective one of the opposite ends of the winding core portion is connected;
a plurality of wires wound around the winding core portion; and
a plurality of electrode portions disposed on bottom surfaces of the first and second flange portions and connected to the plurality of wires, wherein
the plurality of wires includes two wires crossing each other at the first flange portion,
the first flange portion has a groove adjacent to a position of crossing of the two wires,
the lower one of the two wires passes through the groove and the upper one of the two wires does not pass through the groove so that the two wires are separated from each other,
the first flange portion has a protrusion adjacent to the position of crossing of the two wires, and the upper one of the two wires passes through the protrusion so that the two wires are separated from each other, and
the protrusion and the groove being disposed on an end edge of the bottom surface of the first flange portion and directly adjacent to each other, the end edge being adjacent to the end surface of the first flange portion, and the protrusion protruding from the end surface of the first flange portion.

US Pat. No. 10,141,093

REACTOR

AUTONETWORKS TECHNOLOGIES...

1. A reactor comprising:a coil made of a wound coil wire;
a magnetic core on which the coil is arranged, and that forms a closed magnetic path, wherein the magnetic core has an inner core section that is arranged on an inside of the coil; and
a heat dissipating sheet that is interposed at least partially between an inner circumferential surface of the coil and an outer circumferential surface of the inner core section that is opposite to the inner circumferential surface of the coil, wherein:
the heat dissipating sheet is in contact with the coil and the inner core section and the heat dissipating sheet is only at a lower surface of the inner core section, and
the inner core section includes a middle body section forming the magnetic path, and a middle resin molded section that covers at least a part of an outer circumferential surface of the middle body section.

US Pat. No. 10,141,092

POCKET HOLSTER

1. A system for carrying a device, comprising:at least one first ferromagnetic area disposed on at least one surface of the device;
at least one second ferromagnetic area configured to interact with the at least one first ferromagnetic area, the at least one second ferromagnetic area including at least:
a first raised area;
a second recessed area; and
a third raised area, wherein the first and third raised areas are substantially co-planar; and
at least one magnet configured to be removably received by the at least one second ferromagnetic area, the at least one magnet configured to fit within the second recessed area.

US Pat. No. 10,141,086

CABLE FOR HIGH SPEED DATA COMMUNICATIONS

Lenovo Enterprise Solutio...

1. A method of manufacturing a cable for high speed data communications, the method comprising:providing a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the first inner conductor substantially parallel to the second inner conductor and to a longitudinal axis; and
wrapping a conductive shield around the first and second inner conductors, including overlapping the conductive shield along and only about the longitudinal axis, wherein the overlap is aligned with a low current plane, the low current plane substantially parallel to the first and second inner conductors, substantially equidistant from the first and second inner conductors, and substantially orthogonal to a plane including the first and second inner conductors, wherein for the length of the shield, within every plane that is perpendicular to the longitudinal axis of the overlap, the longitudinal axis of the first inner conductor, and the longitudinal axis of the second inner conductor: the center of the overlap is equidistance to the center of first inner conductor and the center of the second inner conductor, thereby tuning a stopband with the overlap to filter frequencies at a desired center frequency,
wherein:
the first and second inner conductors are substantially the same length;
providing the first and second inner conductors further comprises aligning corresponding ends of the first and second inner conductors; and
wrapping a conductive shield further comprises wrapping a plurality of conductive shields around the first and second inner conductors, including overlapping each of the conductive shields along and about the longitudinal axis, wherein the overlap of the conductive shields is aligned with the low current plane and wherein the conductive shields are wrapped along the first and second inner conductors iteratively beginning at one end of the first and second inner conductors and ending at the other end of the first and second inner conductors, andwherein the overlap produces a stopband filter that filters frequencies in a stopband, the stopband including frequencies greater than frequencies of signals to be transmitted along the first and second inner conductors and including frequencies greater than frequencies in the range of 5-10 gigahertz.

US Pat. No. 10,141,031

STORAGE SYSTEM AIRFLOW IMPEDANCE REGULATOR

LENOVO ENTERPRISE SOLUTIO...

1. A system, comprising:a storage bay having a peripheral sidewall defining an interior dimensioned to receive a data storage device therein,
at least one flap coupled to the peripheral sidewall, the at least one flap being positionable between a retracted position and a deployed position, the at least one flap substantially blocking airflow through the interior of the peripheral sidewall when the at least one flap is in the deployed position, wherein the at least one flap does not significantly block airflow through the interior of the peripheral sidewall when the at least one flap is in the retracted position, wherein the at least one flap resides in the interior of the storage bay when the at least one flap is in the retracted position;
a retention mechanism configured to retain the at least one flap in the retracted position, the retention mechanism being electronically controllable to cause the at least one flap to move toward the deployed position; and
an electronic connector coupled to the retention mechanism and configured to pass control signals to the retention mechanism.

US Pat. No. 10,141,027

METHOD, STORAGE MEDIUM, AND ELECTRONIC DEVICE FOR PROVIDING PLURALITY OF IMAGES

Samsung Electronics Co., ...

1. A method of providing an image by an electronic device, the method comprising:acquiring a first image using a first camera module or a communication module;
acquiring second image using a second camera module or the communication module;
acquiring sound data;
generating event information related to at least one of the first image, the second image and the sound data; and
generating a multitrack file including the first image, second image, the sound data, and the event information.

US Pat. No. 10,141,021

DISTINGUISHING HEVC PICTURES FOR TRICK MODE OPERATIONS

CISCO TECHNOLOGY, INC., ...

1. An apparatus comprising:a memory; and
a processor configured to execute instructions stored on the memory, the instructions comprising:
providing a video program in a transport stream, the transport stream including an elementary stream corresponding to a High Efficiency Video Coding (HEVC) bitstream; and
providing a respective tier number to respective ones of a plurality of pictures in the elementary stream, the respective tier number being provided in a transport stream packet that corresponds to a start of the respective ones of the plurality of pictures,
wherein the respective tier number comprises a lowest tier number when the respective ones of the plurality of pictures comprise an Intra Random Access Point (“IRAP”) picture of the HEVC bitstream,
wherein the respective tier number comprises the lowest tier number plus 1 when the respective ones of the plurality of pictures do not comprise an IRAP picture of the HEVC bitstream and have a temporal identifier comprising 0,
wherein reference pictures are extracted from the elementary stream based on the respective tier number to provide a requested trick mode, and
wherein a predetermined tier number is assigned to a highest tier number that is assigned to the reference pictures that are intended to be extracted for trick mode.

US Pat. No. 10,141,020

DISPLAY DEVICE AND DRIVE METHOD FOR SAME

SHARP KABUSHIKI KAISHA, ...

1. A current drive-type display device, comprising:a plurality of pixels arranged two-dimensionally, each including a display element and a drive element provided in series with the display element to control an amount of a current flowing through the display element;
a current measurement circuit configured to measure a current which passes through the drive element and is output to an outside of the pixel, without passing through the display element;
a correction calculation unit configured to correct a video signal based on a current measurement result by the current measurement circuit; and
a drive circuit configured to write a voltage in accordance with a corrected video signal to the pixel, wherein the correction calculation unit includes:
a light emission current efficiency calculation unit configured to obtain a light emission current efficiency of the display element for each pixel based on the current measurement result;
a first correction unit configured to correct the video signal for each pixel in view of characteristics of each pixel, based on the current measurement result and the light emission current efficiency; and
a second correction unit configured to obtain a correction term for each pixel in view of a difference in the light emission current efficiency compared to neighboring pixels, based on a two-dimensional distribution of the light emission current efficiency, and
the correction calculation unit is configured to obtain the corrected video signal based on the video signal corrected by the first correction unit and the correction term obtained by the second correction unit; wherein
the correction calculation unit comprising:
a light emission current efficiency storage unit configured to store for each pixel a light emission current efficiency obtained by the light emission current efficiency calculation unit.

US Pat. No. 10,141,018

METHOD AND SYSTEM FOR OPTICAL DATA STORAGE

Shanghai Naguang Informat...

1. A method of recording optically readable data, the method employing a provided recording medium which comprises an optically active material able to induce a change in properties of the medium in the presence of optical radiation having a first characteristic, and wherein the change in properties can be inhibited by optical radiation having a second characteristic, the method comprising: irradiating a region of the recording medium with a first beam of optical radiation having the first characteristic, the beam having a sufficient intensity within a central portion of the irradiated region and being of sufficient duration to cause an optically induced change in properties of the recording medium; and simultaneously irradiating the region of the recording medium with a second beam of optical radiation having the second characteristic, the second beam having a local intensity minimum within the central portion of the irradiated region, and a local intensity maximum in at least one portion of the irradiated region adjacent to the central portion which is sufficient to inhibit the optically induced change in properties of the recording medium.

US Pat. No. 10,141,013

SHINGLED MAGNETIC RECORDING DEVICE CAPABLE OF SETTING TRACK-PITCH AT TARGET TRACK AND TWO ADJACENT TRACKS

Kabushiki Kaisha Toshiba,...

1. A magnetic disk device comprising:a disk;
a head which writes data to the disk; and
a controller which sets a first track pitch between a first track of the disk and a second track away from the first track in a first direction of a radial direction of the disk based on fringing when the second track is written, sets a second track pitch between the first track and a third track away from the first track in a second direction opposite to the first direction based on fringing when the third track is written, calculates a difference between the first track pitch and the second track pitch, sets, when the difference is less than or equal to a reference value, an area to which the first track is written in a first recording area for wiring a track to a position away from an adjacent track, and sets, when the difference is greater than the reference value, the area to which the first track is written in a second recording area for writing a track such that the track partially overlaps an adjacent track.

US Pat. No. 10,141,011

CONVERSATION QUALITY ANALYSIS

Avaya Inc., Basking Ridg...

1. A method of analyzing a conversation between a plurality of participants, comprising:in a processing system coupled to a storage system that stores the conversation:
determining a first speaker from the plurality of participants;
determining a second speaker from the plurality of participants;
determining a first plurality of turns comprising portions of the conversation when the first speaker is speaking;
determining a second plurality of turns comprising portions of the conversation when the second speaker is speaking; and
determining a characterization for quality of the conversation based on gaps between turns of the first plurality of turns and turns of the second plurality of turns and further based on a plurality of hesitations within turns of the first plurality of turns and the second plurality of turns, wherein each hesitation comprises one or more gaps within speech of a turn that is below a threshold amount of time that indicates when one turn ends and a second turn begins.

US Pat. No. 10,141,009

SYSTEM AND METHOD FOR CLUSTER-BASED AUDIO EVENT DETECTION

Pindrop Security, Inc., ...

1. A computer-implemented method for audio event detection, comprising:forming clusters of audio frames of an audio signal using K-means and at least one Gaussian mixture model (GMM), wherein each cluster includes audio frames having similar features, and wherein a number k equal to a total number of the clusters of audio frames is equal to 1 plus a ceiling function applied to a quotient obtained by dividing a duration of a recording of the audio signal by an average duration of the clusters of audio frames; and
determining, for at least one of the clusters of audio frames, whether the cluster includes a type of sound data using a supervised classifier.

US Pat. No. 10,141,008

REAL-TIME VOICE MASKING IN A COMPUTER NETWORK

Interviewing.io, Inc., S...

1. A computer system, comprising one or more hardware computer processors programmed, via executable code instructions, to:receive an audio signal representing at least a portion of speech;
split the audio signal into a plurality of overlapping segments;
generate a frequency domain representation of a current signal segment in the plurality of overlapping segments, wherein the frequency domain representation comprises components corresponding to a plurality of frequency bins;
generate, from the frequency domain representation of the current signal segment, a polar representation comprising a magnitude component and a phase component for each of the frequency bins;
generate a refined frequency domain representation of the current signal segment based on a comparison, for each of the frequency bins, between a first phase component from the current signal segment and a second phase component from a prior signal segment;
calculate an initial cepstrum from the refined frequency domain representation;
calculate a spectral envelope from the initial cepstrum using iterative smoothing with a resolution lower than a resolution of the frequency domain representation, wherein the iterative smoothing terminates after a predetermined number of iterations or a predetermined degree of convergence is reached;
calculate an excitation spectrum from the refined frequency domain representation and the spectral envelope;
rescale the spectral envelope based on a formant adjustment parameter to obtain a modified spectral envelope, wherein the spectral envelope is distinct from the current signal segment, the frequency domain representation, and the initial cepstrum;
calculate a modified frequency domain representation by combining the modified spectral envelope and the excitation spectrum;
synthesize a modified signal segment from the modified frequency domain representation; and
transmit the modified signal segment over a computer network.

US Pat. No. 10,141,007

SOUND/VIBRATION SPECTRUM ANALYZING DEVICE AND METHODS OF ACQUIRING AND ANALYZING FREQUENCY INFORMATION

SAMSUNG ELECTRONICS CO., ...

22. A method of analyzing a sound and vibration spectrum using a plurality of resonators having different center frequencies, the method comprising:acquiring a first frequency signal of a first resonance mode of at least some of the plurality of resonators;
acquiring a second frequency signal of a second resonance mode of the at least some of the plurality of resonators; and
analyzing each of the first frequency signal of the first resonance mode and the second frequency signal of the second resonance mode.

US Pat. No. 10,141,006

ARTIFICIAL INTELLIGENCE SYSTEM FOR IMPROVING ACCESSIBILITY OF DIGITIZED SPEECH

AMAZON TECHNOLOGIES, INC....

1. An artificial intelligence system comprising:one or more memories storing computer-executable instructions; and
one or more hardware processors, to execute the computer-executable instructions to:
access webpage data including visual data for rendering visible elements of a webpage and audio data for rendering audible elements that include speech representative of at least a subset of the visible elements of the webpage;
generate text data based on the audio data using a speech-to-text module, the text data including a transcription of the audible elements;
determine, based on the text data, one or more of:
a repeated string in the text data;
a semantic error in the text data;
a total quantity of text, in the text data, that exceeds a threshold total quantity;
a quantity of text, in the text data, that corresponds to a particular visible feature of the webpage, that is less than a threshold minimum value;
a quantity of text, in the text data, that corresponds to the particular visible feature, that is greater than a threshold maximum value; or
a separation between at least a portion of the text data and the particular visible feature that exceeds a threshold separation;
access first user data indicative of first user interactions with a visible element of the webpage;
determine an audible element that corresponds to the visible element;
access second user data indicative of second user interactions with the audible element;
determine one or more differences between the first user data and the second user data, the one or more differences indicating that the first user interactions with the visible element exceed the second user interactions with the audible element; and
based on the text data and the one or more differences, modify the audio data by one or more of:
removing at least a portion of the audible element;
moving the audible element from a first location in the webpage to a second location subsequent to the first location; or
modifying a portion of the audio data that corresponds to the one or more of the repeated text string, the semantic error, the total quantity of text that exceeds the threshold quantity, the quantity of text that is less than the threshold minimum value, the quantity of text that is greater than the threshold maximum value, or the separation.

US Pat. No. 10,141,005

NOISE DETECTION AND REMOVAL SYSTEMS, AND RELATED METHODS

Apple Inc., Cupertino, C...

1. A method for removing an unwanted target signal from an observed signal, the method comprising:assessing each of a plurality of regions of an observed signal to determine whether the respective region includes a component of an unwanted target signal from a probabilistic correlation between a prior event and a presence of the unwanted target signal following the prior event, wherein each region spans a selected number of samples of the observed signal, and the selected number of samples in each region is substantially less than a total number of samples of the observed signal, wherein the unwanted target signal comprises one or more of a stationary signal, a non-stationary signal, and a colored signal;
in response to determining one of the regions contains the component of the unwanted target signal, searching the observed signal within the respective region and over a selected number of samples adjacent the respective region for one or more other components of the unwanted target signal;
identifying a removal region of the observed signal corresponding to each component of the unwanted target signal;
supplanting each component of the observed signal corresponding to each respective removal region with an estimate of a corresponding portion of a desired signal based on the observed signal in a region adjacent the respective removal region to form a corrected signal.

US Pat. No. 10,141,001

SYSTEMS, METHODS, APPARATUS, AND COMPUTER-READABLE MEDIA FOR ADAPTIVE FORMANT SHARPENING IN LINEAR PREDICTION CODING

QUALCOMM Incorporated, S...

1. An apparatus comprising:an audio coder input configured to receive an audio signal;
a first calculator configured to determine a long-term noise estimate of the audio signal;
a second calculator configured to determine a formant-sharpening factor based on the determined long-term noise estimate;
a filter configured to filter a codebook vector based on the determined formant-sharpening factor to generate a filtered codebook vector, wherein the codebook vector is based on information from the audio signal; and
an audio coder configured to:
generate a formant-sharpened low-band excitation signal based on the filtered codebook vector; and
generate a synthesized audio signal based on the formant-sharpened low-band excitation signal.

US Pat. No. 10,140,997

DECODER AND METHOD FOR DECODING AN AUDIO SIGNAL, ENCODER AND METHOD FOR ENCODING AN AUDIO SIGNAL

Fraunhofer-Gesellschaft z...

1. A decoder for decoding an audio signal, the decoder comprising:a first target spectrum generator for generating a first target spectrum for a first time frame of a subband signal of the audio signal using first correction data;
a first phase corrector for correcting, with a first phase correction algorithm, a phase of the subband signal in the first time frame of the audio signal wherein the correction is performed by reducing, for the first time frame, a difference between a measure of the subband signal in the first time frame of the audio signal and the first target spectrum;
an audio subband signal calculator for calculating the audio subband signal for the first time frame using a corrected phase determined by the first phase corrector for the first time frame;
a second target spectrum generator, wherein the second target spectrum generator is configured for generating a second target spectrum for the second time frame of the subband of the audio signal using second correction data;
a second phase corrector for correcting, with a second phase correction algorithm, a phase of the subband signal in the second time frame of the audio signal, wherein the correction is performed by reducing, for the second time frame, a difference between a measure of the subband signal in the second time frame of the audio signal and the second target spectrum,
wherein the second phase correction algorithm is different from the first phase correction algorithm, and
wherein the audio subband signal calculator is configured for calculating the audio subband signal for the second time frame using a corrected phase determined by the second phase corrector for the second time frame.

US Pat. No. 10,140,996

SIGNALING LAYERS FOR SCALABLE CODING OF HIGHER ORDER AMBISONIC AUDIO DATA

QUALCOMM Incorporated, S...

1. A device configured to decode a bitstream representative of a higher order ambisonic audio signal, the device comprising:a memory configured to store the bitstream; and
one or more processors configured to:
obtain, from the bitstream, an indication of a number of layers specified in the bitstream;
obtain, from the bitstream, an indication of a number of channels specified in the bitstream; and
obtain the layers of the bitstream based on the indication of the number of layers specified in the bitstream and the indication of the number of channels specified in the bitstream.

US Pat. No. 10,140,995

DECODING DEVICE, DECODING METHOD, ENCODING DEVICE, ENCODING METHOD, AND PROGRAM

Sony Corporation, Tokyo ...

1. A decoding device comprising:a decoding unit that decodes audio data included in an encoded bit stream;
a read unit that reads information indicating whether extended information is present in the encoded bit stream from the encoded bit stream and reads the extended information on the basis of the read information; and
a processing unit that processes the decoded audio data on the basis of the extended information,
wherein the extended information includes first information for specifying a downmix coefficient, and further includes second information,
the processing unit downmixes the decoded audio data of a plurality of channels on the basis of the downmix coefficient to provide downmixed audio data, and
the processing unit further downmixes the downmixed audio data on the basis of the second information.

US Pat. No. 10,140,993

APPARATUS AND METHOD FOR GENERATING AN ERROR CONCEALMENT SIGNAL USING INDIVIDUAL REPLACEMENT LPC REPRESENTATIONS FOR INDIVIDUAL CODEBOOK INFORMATION

Fraunhofer-Gesellschaft z...

1. An apparatus for generating an error concealment audio signal, comprising:an LPC (linear prediction coding) representation generator for generating a first replacement LPC representation and a different second replacement LPC representation;
an LPC synthesizer for filtering a first codebook information using the first replacement LPC representation to acquire a first replacement audio signal and for filtering a different second codebook information using the second replacement LPC representation to acquire a second replacement audio signal; and
a replacement signal combiner for combining the first replacement audio signal and the second replacement audio signal by summing-up the first replacement audio signal and the second replacement audio signal to acquire the error concealment audio signal,
wherein at least one of the LPC representation generator, the LPC synthesizer, and the replacement signal combiner is implemented, at least in part, by one or more hardware elements of the apparatus.

US Pat. No. 10,140,992

SYSTEM AND METHOD FOR VOICE AUTHENTICATION OVER A COMPUTER NETWORK

NUANCE COMMUNICATIONS, IN...

1. A method comprising:receiving, on a mobile device, a speech sample from a user as part of a request for a restricted-access resource separate from the mobile device; and
when the user has previously established identity with the mobile device:
transmitting the speech sample along with the request to an authentication server which compares the speech sample to a previously established speech profile associated with the user; and
providing access to the restricted-access resource if the speech sample from the user matches the previously established speech profile with a minimum certainty threshold.

US Pat. No. 10,140,989

METHOD AND SYSTEM FOR SPEECH RECOGNITION PROCESSING

Alibaba Group Holding Lim...

1. A speech recognition system, comprising:an instant messaging server (IMS) configured to:
assign a unique identifier to speech information received from a sending end to serve as a speech ID;
send the speech information to a receiving end; and
in response to a determination that a speech recognition request issued from a user of the receiving end corresponding to the speech information is received:
extract the speech ID corresponding to the speech information from the speech recognition request;
look up the speech information; and
deliver a speech recognition command in the speech recognition request and the looked-up speech information to one of a speech recognition module, a speech recognition server, or a speech recognition server cluster;
the one of the speech recognition module, the speech recognition server, or the speech recognition server cluster configured to:
perform speech recognition based on the speech information and the speech recognition command; and
convert the speech information to obtain text information corresponding to the speech information, wherein the IMS obtains the text information from the one of the speech recognition module, the speech recognition server, or the speech recognition server cluster; and
a sending module configured to send the obtained text information back as a speech recognition result to the receiving end, wherein the speech recognition module is set up in the one of the IMS, the speech recognition server, or the speech recognition server cluster, wherein the IMS is further configured to:
store the obtained text information in a cache in correspondence with the speech ID; and
in response to a determination that another speech recognition request for the same speech information is received:
extract a speech ID from the other speech recognition request; and
locate the text information corresponding to the speech ID from the other speech recognition request.

US Pat. No. 10,140,988

SPEECH RECOGNITION

Microsoft Technology Lice...

1. A computer system comprising:an input configured to receive voice input from a user, the voice input having speech intervals separated by non-speech intervals;
a system configured to identify individual words in the voice input during the speech intervals of the voice input, and store the identified individual words in memory;
a speech overload detection module configured to detect a speech overload condition at a time during a speech interval of the voice input, the speech overload condition being based on one or more of a rate at which words are identified during the speech interval, or a state of an artificial intelligence (AI) tree being driven by the voice input; and
a notification module configured to output, in response to the speech overload detection module detecting the speech overload condition, a notification of the speech overload condition.

US Pat. No. 10,140,987

AERIAL DRONE COMPANION DEVICE AND A METHOD OF OPERATING AN AERIAL DRONE COMPANION DEVICE

INTERNATIONAL BUSINESS MA...

1. A method of operating an aerial drone companion device, comprising:detecting a first voice command spoken by a first user by at least one microphone disposed on the aerial drone companion device;
autonomously orientating the aerial drone companion device such that an image capture device disposed on the aerial drone companion device faces the first user in response to detecting the first voice command;
detecting a second voice command spoken by the first user by the at least one microphone while the image capture device faces the first user and while the first user looks at the image capture device;
transmitting the second voice command from the aerial drone companion device to a computer located remotely from the aerial drone companion device;
receiving a task signal indicating a task to be performed, wherein the task signal is generated by the computer based on the second voice command, and the task signal is transmitted by the computer and received by the aerial drone companion device; and
autonomously executing the task by the aerial drone companion device.

US Pat. No. 10,140,984

METHOD AND APPARATUS FOR PROCESSING VOICE DATA

Baidu Online Network Tech...

1. A method for processing voice data, comprising:receiving voice data sent by a user terminal;
extracting a voiceprint characteristic vector in the voice data;
matching the voiceprint characteristic vector with a registered voiceprint vector prestored by the user, and generating a matching degree between the voiceprint characteristic vector and the registered voiceprint vector;
determining whether the matching degree is greater than or equal to a preset update threshold; and
updating the registered voiceprint vector by using the voiceprint characteristic vector and the voice data in response to determining that the matching degree is greater than or equal to the preset update threshold
the updating the registered voiceprint vector by using the voiceprint characteristic vector and the voice data comprising:
acquiring an amount of registered voice data inputted by the user and each of voiceprint characteristic vectors prestored by the user; and
updating the registered voiceprint vector according to the each of voiceprint characteristic vectors prestored by the user, an amount of voice data prestored by the user, an amount of the registered voice data and the registered voiceprint vector,
the updating the registered voiceprint vector according to the each of voiceprint characteristic vectors prestored by the user, the amount of voice data prestored by the user, the amount of the registered voice data and the registered voiceprint vector comprising:
carrying out a data standardization operation on the each of voiceprint characteristic vectors prestored by the user, and carrying out a summing operation on the vector subject to the data standardization operation to obtain the sum of the voiceprint characteristic vectors prestored by the user;
multiplying the amount of the registered voice data by the registered voiceprint vector to obtain a product of the registered voiceprint vector; and
calculating a vector sum of the sum of the voiceprint characteristic vectors and the product of the registered voiceprint vector, calculating an amount sum of the amount of the voice data prestored by the user and the amount of the registered voice data, and dividing the amount sum by the vector sum to obtain the updated registered voiceprint vector.

US Pat. No. 10,140,983

BUILDING OF N-GRAM LANGUAGE MODEL FOR AUTOMATIC SPEECH RECOGNITION (ASR)

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method for building an n-gram language model for an automatic speech recognition, comprising:reading training text data and additional text data for the n-gram language model from storage, wherein the additional text data comprises a plurality of sentences having at least one target keyword;
building the n-gram language model by a smoothing algorithm having discount parameters for n-gram counts, wherein each discount parameter for each target keyword is tuned using development data which are different from the additional text data so that a predetermined balance between precision and recall is achieved;
decreasing erroneous detection of one or more target keywords by tuning all of the discount parameters to be larger, or increasing n-gram counts of each of a plurality of words erroneously detected as one of the one or more target keywords by tuning each of the discount parameters to be smaller; and
performing spoken term detection based on the n-gram language model built using the development data.

US Pat. No. 10,140,974

METHOD AND APPARATUS FOR SPEECH RECOGNITION

Samsung Electronics Co., ...

1. A speech recognition method, comprising:generating, by a processor, a word sequence based on a phoneme sequence generated from a speech signal;
generating, by the processor, a syllable sequence based on the phoneme sequence, in response to a word element among words included in the word sequence having a lower recognition rate than a threshold value; and
determining, by the processor, a text corresponding to a recognition result of the speech signal based on the word sequence and the syllable sequence,
wherein the syllable sequence corresponds to the word element,
wherein the generating of the syllable sequence comprises generating the syllable sequence by decoding a portion corresponding to the word element, among phonemes included in the phoneme sequence, and
wherein the word sequence is generated by decoding the phoneme sequence and corresponds to at least the text corresponding to the recognition result of the speech signal.

US Pat. No. 10,140,972

TEXT TO SPEECH PROCESSING SYSTEM AND METHOD, AND AN ACOUSTIC MODEL TRAINING SYSTEM AND METHOD

Kabushiki Kaisha Toshiba,...

3. A text to speech method, the method comprising:receiving input text;
dividing said inputted text into a sequence of acoustic units;
converting said sequence of acoustic units to a sequence of speech vectors using an acoustic model, wherein said acoustic model comprises a set of speaker parameters and a set of speaker clusters relating to speaker voice and a set of expression parameters and a set of expression clusters relating to expression, and wherein the sets of speaker and expression parameters and the sets of speaker and expression clusters do not overlap; and
outputting said sequence of speech vectors as audio,
the method further comprising determining at least some of said parameters relating to expression by:
extracting expressive features from said input text to form an expressive linguistic feature vector constructed in a first space; and
mapping said expressive linguistic feature vector to an expressive synthesis feature vector which is constructed in a second space,
wherein said text to speech method includes training said acoustic model using a method comprising:
receiving speech data, said speech data further comprising speech data from one or more speakers speaking with neutral speech,
said speech data comprising data corresponding to different values of a first speech factor, wherein the first speech factor is speaker and speech data corresponding to different values of a second speech factor, wherein the second speech factor is expression,
and wherein said speech data is unlabeled, such that for a given item of speech data, the value of said first speech factor is unknown;
clustering said speech data according to the value of said first speech factor into a first set of clusters and clustering said speech data according to the value of said second speech factor into a second set of clusters; and
estimating a first set and a second set of parameters to enable the acoustic model to accommodate speech for the different values of the first speech factor and the second speech factor respectively,
wherein said clustering and the parameter estimation are jointly performed according to a common maximum likelihood criterion which is common to both parameter estimation and said clustering.

US Pat. No. 10,140,970

ENGINE SOUND PRODUCTION SYSTEMS AND METHODS

GM GLOBAL TECHNOLOGY OPER...

1. An audio system of a vehicle, comprising:a detection module configured to detect an occurrence of a sound when a pressure measured by an exhaust pressure sensor in an exhaust system is greater than a predetermined pressure;
a sound control module configured to, in response to the detection of the sound, increase a magnitude of a predetermined sound to be output within a passenger cabin of the vehicle; and
an audio driver module configured to apply power to a speaker of the passenger cabin of the vehicle based on the predetermined sound.

US Pat. No. 10,140,968

ACOUSTIC ABSORPTION AND METHODS OF MANUFACTURE

Ashmere Holdings Pty Ltd,...

1. A method of providing a micro-perforated panel absorber comprising:providing a primary cellular core having a number of primary cells;
providing secondary cells in a number of recesses, the secondary cells being of reduced depth in comparison to the primary cells; the primary cells providing for absorption of relatively low frequencies; and the secondary cells of reduced depth providing for absorption of relatively high frequencies; and
crushing one or more portions of the primary cellular core to provide the number of recesses, wherein the crushing of the primary cellular core and providing the secondary cells is performed using a secondary reduced depth cellular core having a higher compression strength than the primary cellular core that is crushed.

US Pat. No. 10,140,966

LOCATION-AWARE MUSICAL INSTRUMENT

1. A method comprising:receiving, from each of a plurality of moveable nodes, the position of the moveable node within a coordinate space, wherein the moveable nodes comprise objects that can be physically moved by a person;
generating a graph of the moveable nodes based on the received positions;
generating an audio-visual composition based on a sweep of the graph over time; and
outputting the audio-visual composition.

US Pat. No. 10,140,964

GUITAR TREMOLO BRIDGE

1. A tremolo bridge for mounting to a guitar body, comprising:a block;
a base plate coupled to the block, wherein the base plate includes a pivot point for the base plate to move about an arc;
a body plate adapted to affix to the guitar body;
a locking mechanism coupled between the base plate and body plate; and
a tremolo arm coupled to the base plate for moving the base plate within the arc, wherein the tremolo arm is further coupled to the locking mechanism which is capable of locking and maintaining the base plate at all positions within the arc.

US Pat. No. 10,140,962

DISPLAY UNIT, DISPLAY PANEL AND DRIVING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display unit, comprising: a full color display subunit capable of displaying full color, and at least one black and white display subunit capable of displaying black and white;wherein the full color display subunit and the at least one black and white display subunit are configured such that;
in a case where a display panel to which the display unit belongs is to display a frame of an image, including both a color graph and a black and white graph, and the display unit is not located at a boundary between the color graph and the black and white graph, the full color display subunit and all the black and white display subunit(s) in the display unit display one pixel together; and
in a case where a display panel to which the display unit belongs is to display a frame of an image, including both a color graph and a black and white graph, and the display unit is located at the boundary between the color graph and the black and white graph, the full color display subunit in the display unit displays one full-color pixel, and concurrently each black and white display subunit in the display unit forms one black and white pixel and performs display independently from the full-color pixel.

US Pat. No. 10,140,961

SYSTEMS AND METHODS FOR CONTROLLING A DISPLAY SCREEN OF A PORTABLE COMPUTING DEVICE

VONAGE BUSINESS INC., At...

1. A method of controlling the orientation of images on a display screen of a portable computing device that is configured to display images in different orientations on the display screen when the portable computing device is positioned in corresponding different orientations, comprising:determining a duration of a switching time period that elapses between a first point in time at which the portable computing device changes from a first orientation to a second orientation, and a second point in time at which the portable computing device changes from the second orientation back to the first orientation, wherein the portable computing device is determined to have changed from the first orientation to the second orientation when an angle between the vertical direction and a central longitudinal axis of the portable computing device exceeds a reference angle and wherein the portable computing device is determined to have changed from the second orientation back to the first orientation when an angle between the vertical direction and the central longitudinal axis of the portable computing device becomes less than the reference angle; and
setting the reference angle to a first value when the determined duration of the switching time period is greater than or equal to a threshold duration and setting the value of the reference angle to a second value that is different from the first value when the determined duration of the switching time period is less than the threshold duration, wherein a subsequent determination of when the portable computing device changes between the first and second orientations will be based on the set reference angle.

US Pat. No. 10,140,956

DISPLAY CONTROL APPARATUS

DENSO CORPORATION, Kariy...

1. A display control apparatus performing a predetermined comparison operation on display images to automatically assign the display images to a plurality of areas configured as display regions on a screen of a display mounted to a vehicle, the display control apparatus comprising:a processor, the processor is configured to
store, by an area relationship information storage, area relationship information for each of the areas, wherein the area relationship information for each area has information on another area that is closely related to the each area;
store, by a display image relationship information storage, image relationship information for each of the display images, wherein the image relationship information for each display image has information on another display image that is closely related to the each display image;
determine, by an image determination portion, that, of two display images related to each other, one of the two display images belongs to a first image group and the other belongs to a second image group different from the first image group; and
assign, by a display image assignment portion, the display image determined as belonging to the first image group to an area by performing the predetermined comparison operation,
and then superimpose, by the display image assignment portion, the display image determined as belonging to the second image group on the display image determined as belonging to the first image group by assigning the display image determined as belonging to the second image group to an area that is superimposed on the area to which the display image determined as belonging to the first image group is assigned, based on the area to which the display image determined as belonging to the first image group is assigned, and based on the information stored in the area relationship information storage, wherein:
the image relationship information is link information that links the closely-related display images and that is defined independently of the areas;
the area relationship information is link information that links the closely-related areas and that is defined independently of the display images;
the areas linked by the area relationship information for a first area is the first area and a second area superimposed on the first area;
the areas not linked by the area relationship information for the first area include the first area and a third area separated from the first area; and
the image relationship information further stores ruling-set numbers for determining that, of two display images closely related to each other in the image relationship information, a first display image belongs to the first image group and the second display image belongs to the second image group different from the first image group; and
when the image determination portion determines based on the image relationship information and the ruling-set numbers that the first and second display images are closely related to each other and belong to the first and second image groups respectively, the display image assignment portion is further configured to
assign the first display image to the first area by performing the predetermined comparison operation,
and then superimpose the second display image on the first display image by assigning the second display image not to the third area separated from the first area but to the second area superimposed on the first area based on the area relationship information and based on the first area to which the first display image is assigned.

US Pat. No. 10,140,953

AMBIENT-LIGHT-CORRECTED DISPLAY MANAGEMENT FOR HIGH DYNAMIC RANGE IMAGES

Dolby Laboratories Licens...

1. A method for adaptive display management with a computer, the method comprising:receiving one or more viewing environment parameters;
receiving an effective luminance range for a target display;
receiving an input image comprising pixel values;
generating a tone-mapped image by mapping with the computer intensity pixel values of the input image pixel values to intensity pixel values in the tone-mapped image, wherein generating the tone-mapped image is based on an original perceptually quantized (PQ) luminance mapping function and the effective luminance range of the display;
generating a corrected PQ (PQ?) luminance mapping function based on the one or more viewing environment parameters;
generating a PQ-to-PQ? mapping wherein a first codeword in the original PQ luminance mapping function is mapped to a second codeword in the corrected (PQ?) luminance mapping function according to the effective luminance range of the target display;
generating an adjusted tone-mapped image by mapping intensity values in the tone-mapped image to intensity values in the adjusted tone-mapped image, wherein generating the adjusted tone-mapped image is based on the PQ-to-PQ? mapping.

US Pat. No. 10,140,952

CONTROL OF SPECTRAL RANGE INTENSITY IN MEDIA DEVICES

AMAZON TECHNOLOGIES, INC....

1. A device, comprising:a display; and
at least one controller to:
cause presentation of content on the display in a first output mode using a first pattern profile for light intensity across a spectral range;
send one or more of usage data, derived from detected interaction by a user with the content presented on the display, or account data, to at least one remote device;
receive, from the at least one remote device, a second pattern profile for light intensity across the spectral range of a second output mode, and a spectral transition sequence describing a transition of light intensity of a first portion of the spectral range of the first pattern profile in the first output mode to a second pattern profile of light intensity of the first portion of the spectral range in the second output mode; and
responsive to receiving the second pattern profile for light intensity and the spectral transition sequence, cause the display to transition from the first pattern profile to the second pattern profile according to the spectral transition sequence, wherein:
the first pattern profile of the first output mode is associated with a first amount of light emitted across the first portion of the spectral range and a second amount of light emitted across a second portion of the spectral range, and
the second pattern profile of the second output mode is associated with a third amount of light emitted across the first portion of the spectral range and the second amount of light emitted across the second portion of the spectral range, the third amount differing from the first amount.

US Pat. No. 10,140,951

USER INTERFACE DISPLAY COMPOSITION WITH DEVICE SENSOR/STATE BASED GRAPHICAL EFFECTS

Futurewei Technologies, I...

1. A method comprising:receiving sensor data from a light sensor;
obtaining image data from a graphical effects shader based on the sensor data;
blending the image data with a plurality of application surfaces to create a blended image;
blending the blended image with a color image to create a color-tinted blended image in response to a change in ambient light sensed by the light sensor; and
transmitting the color-tinted blended image to a display.

US Pat. No. 10,140,950

DISPLAY DEVICE DRIVING METHOD AND VIDEO DISPLAY APPARATUS

JOLED INC., Tokyo (JP)

1. A display device driving method for driving a display device, the display device driving method comprising:receiving a training signal, for inquiring whether the display device is ready to accept a video signal representing a moving image, that is transmitted from an external signal source;
after receiving the training signal, transmitting a lock signal, indicating that the display device is ready to accept the video signal, to the external signal source at a timing based on an internal synchronization signal of the display device;
after transmitting the lock signal, receiving the video signal that is transmitted from the external signal source and is synchronous with an external synchronization signal; and
displaying a video by using the video signal received from the external signal source,
wherein in the receiving of the video signal, the external synchronization signal is further received, and
the timing is a timing at which the external synchronization signal is received within an effective window period of the internal synchronization signal in the receiving of the video signal, the effective window period being a period in which a received signal is enabled.

US Pat. No. 10,140,949

DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a printed circuit board including:
a base circuit board;
a transmission control unit which outputs input image data,
a wireless data generating unit which converts the input image data to a data transmission signal,
a wireless transmission pad unit which wirelessly transmits the data transmission signal as wireless data and is disposed on a bottom surface of the base circuit board; and
a circuit device disposed on a top surface of the based circuit board;
and
a display panel including:
a panel substrate;
a wireless reception pad unit which is coupled to the wireless transmission pad unit, and wirelessly receives the wireless data to output a data reception signal,
a wireless data restoring unit which converts the data reception signal to restored image data; and,
a data driver disposed on a top surface of the panel substrate and converts the restored image data to a data voltage,
wherein the data driver is inserted into an opening defined at the printed circuit board.

US Pat. No. 10,140,948

METHOD FOR ADJUSTING DRIVING VOLTAGE, RELATED ADJUSTING DEVICE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for adjusting a gate driving voltage for a gate driving circuit, output terminals of the gate driving circuit being connected with gate lines, input terminals of the gate driving circuit being connected with a propel link gate (PLG) wiring, comprising:determining an equivalent resistance between an electrical connection point and an input terminal of the PLG wiring along the PLG wiring, wherein:
the electrical connection point connects an input terminal of the gate driving circuit with the input terminal of the PLG wiring, and
the equivalent resistance of the electrical connection point corresponds to a distance from the electrical connection point to the input terminal of the PLG wiring;
obtaining a voltage-drop value at the electrical connection point based on the equivalent resistance; and
compensating the gate driving voltage on the input terminal of the gate driving circuit based on the voltage-drop value.

US Pat. No. 10,140,947

FLEXIBLE DISPLAY SCREEN, DISPLAY DEVICE, AND DISPLAY METHOD APPLIED TO FLEXIBLE DISPLAY SCREEN

BOE Technology Group Co.,...

1. A flexible display screen (100) having an extending mode and a retracting mode, wherein in the extending mode, the entire flexible display screen is used for displaying, and in the retracting mode, at least a portion (105) of the flexible display screen is curled and an uncurled portion of the flexible display screen is used for displaying, wherein the flexible display screen adopts a GOA driving circuit to perform a partitioned display driving,wherein the flexible display screen (100) comprises a main display portion (110) and an addition display portion (115), the additional display portion having a free end capable of being curled, and wherein the additional display portion includes a first additional display portion (115a) and a second additional display portion (115b), the second additional display portion being curled and retracted in the retracting mode, and
wherein in the extending mode, a first switching transistor is controlled to be turned on and a second switching transistor is controlled to be turned off, a display driving control signal is inputted to the entire flexible display screen, and in the retracting mode, the first switching transistor is turned off and the second switching transistor is turned on, inputting of the display driving control signal to the second additional display portion of the flexible display screen is stopped.

US Pat. No. 10,140,945

LUMINANCE SUPPRESSION POWER CONSERVATION

Samsung Electronics Co., ...

1. A method for reducing power consumed by an electronics device that includes a display device, the method comprising:increasing a size of a graphics item to create a larger graphics item;
in response to increasing the size of the graphics item, altering, if a portion of the graphics item includes a color that increases a brightness, video information for at least a portion of the larger graphics item to produce an altered larger graphics item with a reduced luminance; and
displaying the larger graphics item based on the altered video information without altering video information of other graphics items displayed on the display device,
wherein the display device consumes less power when displaying the larger graphics item based on the altered video information than would be consumed for the larger graphics item without the video information alteration.

US Pat. No. 10,140,944

DISPLAY DEVICE COMPENSATING CLOCK SIGNAL WITH TEMPERATURE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a display panel comprising a gate line and a date line;
a gate driver comprising a plurality of stages, at least one of the stages receiving a clock signal and providing a gate signal to the gate line, the clock signal comprising a first clock signal having a first pulse amplitude;
a data driver configured to provide a data signal to the data line; and
a pulse compensator configured to output a second clock signal having a second pulse amplitude higher than the first pulse amplitude to the stage when a peripheral temperature is lower than a reference temperature,
wherein the pulse compensator outputs a third clock signal having a third pulse amplitude lower than the first pulse amplitude when the peripheral temperature is higher than the reference temperature,
wherein the pulse compensator comprises:
a first voltage generator configured to output a gate-on voltage having an increased voltage level when the peripheral temperature is lower than the reference temperature;
a second voltage generator configured to output a gate-off voltage having a reduced voltage level when the peripheral temperature is lower than the reference temperature; and
a switching circuit switching between the gate-on voltage and the gate-off voltage to output the second clock signal or the third clock signal to the stage.

US Pat. No. 10,140,942

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a first gate driver circuit;
a second gate driver circuit; and
a pixel portion between the first gate driver circuit and the second gate driver circuit,
wherein the first gate driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor,
wherein the second gate driver circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one end of a gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the one end of the gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the other end of the gate signal line,
wherein one of a source and a drain of the eighth transistor is electrically connected to the other end of the gate signal line,
wherein one of a source and a drain of the ninth transistor is electrically connected to a gate of the seventh transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the eighth transistor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to a gate of the tenth transistor,
wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the eighth transistor,
wherein a gate of the eleventh transistor is electrically connected to the gate of the seventh transistor,
wherein one of a source and a drain of the twelfth transistor is electrically connected to the gate of the seventh transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the eleventh transistor,
wherein a clock signal is input to the other of the source and the drain of the first transistor,
wherein a start signal is input to a gate of the third transistor,
wherein a first potential is input to the other of the source and the drain of the fourth transistor during a frame period,
wherein a second potential is input to the other of the source and the drain of the fourth transistor during another frame period, and
wherein the second potential is higher than the first potential.

US Pat. No. 10,140,940

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device having a display area wherein pixels are arranged in a matrix pattern, each of the pixels comprising:a display element;
a capacitive element series circuit connected in parallel with the display element, and comprising at least a first capacitive element and a second capacitive element; and
a boost circuit making an electric potential of the capacitive element series circuit increase to obtain a boosted electric potential, and applying the boosted electric potential to the display element,
the boost circuit having a plurality of switches, each controlled in respect of opening and closing by a gate signal during one pulse period of an input source signal, at least one of the switches opening in a first half of the pulse period and closing in a second half of the pulse period, whereas the rest of the switches closing in the first half of the pulse period and opening in the second half of the pulse period.

US Pat. No. 10,140,939

DATA CONVERSION METHOD AND DISPLAY DEVICE USING THE SAME

Sitronix Technology Corp....

1. A data conversion method for converting display data of a display device, the data conversion method comprising:detecting an ambient temperature of the display device;
receiving a specific display data to be displayed by the display device, a previous display data in N row before the specific display data, and a next display data in N row after the specific display data;
converting the specific display data into a display output data according to the previous display data, the next display data and the ambient temperature; and
outputting the display output data to perform displaying;
wherein the step of converting the specific display data into the display output data according to the previous display data, the next display data and the ambient temperature comprises:
obtaining a lookup table corresponding to the ambient temperature; and
obtaining the display output data from the lookup table according to a first data change amount between the previous display data and the specific display data and a second data change amount between the specific display data and the next display data;
wherein the display output data is same as the specific display data or the display output data is nearer to the next display data in comparison with the specific display data when the first data change amount is smaller than a data change threshold corresponding to the ambient temperature and the second data change amount is greater than the data change threshold.

US Pat. No. 10,140,938

GIP TYPE LIQUID CRYSTAL DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A Gate-In-Panel (GIP) type of liquid crystal display device, comprising a display unit, a clock generator and a gate driving unit, wherein the gate driving unit is connected with the display unit and the clock generator respectively;the display unit comprises a plurality of pixel units for image display and a plurality of rows of gate lines, every two rows of the gate lines constitute a gate line group and have a row of pixel units disposed therebetween, an odd numbered row of the gate line is connected with pixel units in an adjacent row and odd numbered columns, and an even numbered row of the gate line is connected with pixel units in an adjacent row and even columns;
the gate driving unit comprises a first driver and a second driver, the first driver is used to provide driving signals to odd numbered rows of the gate lines and the second driver is used to provide driving signals to even numbered rows of the gate lines;
the clock generator is used to provide K scan clock signals to the first driver and K scan clock signals to the second driver respectively according to a scan sequence to make the first/second driver provide driving signals to odd/even numbered rows of the gate lines;
scan sequences of odd numbered frames and even numbered frames are different, the scan sequence comprises a first scan sequence and a second scan sequence corresponding to the odd/even numbered frames or the even/odd numbered frames; in the first scan sequence, the phase of the scan clock signals to scan the (2N)th row of the gate line lags behind that of the scan clock signals to scan the (2N?1)th row of the gate line by ½K of a cycle; in the second scan sequence, the phase of the scan clock signals to scan the (2N?1)th row of the gate line lags behind that of the scan clock signals to scan the (2N)th row of the gate line by ½K of a cycle, where N is a natural number, K=2m, and m is a natural number.

US Pat. No. 10,140,937

DISPLAY PANEL, LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREFOR

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising a plurality of pixels arranged in a matrix, data lines electrically connected with columns of pixels respectively, and gate lines electrically connected with rows of pixels respectively, wherein:each row of pixels comprises a plurality of primary color pixels and a plurality of white pixels arranged alternately, and each column of pixels comprises a plurality of primary color pixels and a plurality of white pixels arranged alternately;
a color of each primary color pixel is one of a first color, a second color and a third color which are different from a white color;
in each row of pixels, all the primary color pixels are electrically connected with one same gate line, all the white pixels are electrically connected with one same gate line, and the primary color pixels and the white pixels are electrically connected with different gate lines; and
the primary color pixels and the white pixels are arranged such that:
colors of the primary color pixels in each odd-numbered row of pixels are the third color, colors of the primary color pixels in each even-numbered row of pixels are arranged with the first color and the second color alternating with each other, and in any two adjacent even-numbered rows of pixels, colors of two primary color pixels located in one same column are different from each other; or
colors of the primary color pixels in each even-numbered row of pixels are the third color, colors of the primary color pixels in each odd-numbered row of pixels are arranged with the first color and the second color alternating with each other, and in any two adjacent odd-numbered rows of pixels, colors of two primary color pixels located in one same column are different from each other.

US Pat. No. 10,140,936

DRIVING METHOD FOR IMAGE DISPLAY APPARATUS

JAPAN DISPLAY INC., Toky...

1. A driving method for an image display apparatus which includes(A) an image display panel including a plurality of pixels arrayed in a two-dimensional matrix and each comprised of a first subpixel for displaying a first primary color, a second subpixel for displaying a second primary color, a third subpixel for displaying a third primary color and a fourth subpixel for displaying a fourth color; and
(B) a signal processing section, the signal processing section being capable of, for each pixel, (a) calculating a first subpixel output signal based at least on a first subpixel input signal and an expansion coefficient (?0) and outputting the calculated first subpixel output signal to the first subpixel, (b) calculating a second subpixel output signal based at least on a second subpixel input signal and the expansion coefficient (?0) and outputting the calculated second subpixel output signal to the second subpixel, (c) calculating a third subpixel output signal based at least on a third subpixel input signal and the expansion coefficient (?0) and outputting the calculated third subpixel output signal to the third subpixel, and (d) calculating a fourth subpixel output signal based on the first subpixel input signal, second subpixel input signal and third subpixel input signal and outputting the calculated fourth subpixel output signal to the fourth subpixel,
the driving method comprising:
a step, carried out by the signal processing section, of setting the expansion coefficient (?0) to a value equal to or lower than a predetermined value when a ratio to all pixels of those pixels with regard to which a hue (H) and a saturation (S) in an HSV (Hue, Saturation and Value) color space where a color defined by (R, G, B) is displayed by each pixel respectively satisfy
40?H?65 and
0.5?S?1.0exceeds a predetermined value (??0),(a) the hue (H) being given, when R exhibits a maximum value, by
H=60(G?B)/(Max?Min),
when G exhibits a maximum value, by
H=60(B?R)/(Max?Min)+120,
and, when B exhibits a maximum value by
H=60(R?G)/(Max?Min)+240, and
(b) the saturation (S) being given by
S=(Max?Min)/Max,
where Max is a maximum value among the three subpixel input signal values of the first subpixel input signal value, second subpixel input signal value and third subpixel input signal value to an individual pixel, and Min is a minimum value among the three subpixel input signal values of the first subpixel input signal value, second subpixel input signal value and third subpixel input signal value to the individual pixel.

US Pat. No. 10,140,933

DISPLAY APPARATUS AND METHOD FOR DRIVING DISPLAY APPARATUS

Japan Display Inc., Toky...

1. A display apparatus comprising:a plurality of light sources aligned in at least one direction;
a display device that has a display area provided with a plurality of pixels, the display device being irradiated with light from the light sources to output an image; and
a controller that controls an operation of the light sources in accordance with a display output content of the display device,
wherein the display area includes a plurality of partial areas, the partial areas corresponding to the light sources on a one-to-one basis,
wherein each of the partial areas includes a first area and a second area, the first area being irradiated with light from a first light source that corresponds thereto, and the second area being irradiated with light from the first light source that corresponds to the first area and a second light source adjacent to the first light source,
wherein the controller controls an operation of the first light source based on whether the first area requires the light from the first light source and whether the second area obtains light required for display output by receiving the light from the second light source,
wherein the controller controls an operation of the second light source based on a result of comparison between luminance of light required for the second area and a predetermined threshold, and
wherein, when Expression (1)
L2_lq?T1  (1)
is satisfied, the controller turns on the second light source such that the second light source provides luminance calculated by Expression (2)
BL1=L1_cq×(L2_lq/T1)  (2)
where L2_lq is the luminance of light required for the second area, L1_cq is luminance of light required for the first area corresponding to the second light source, T1 is a first threshold obtained by multiplying L1_cq by a first coefficient of 0 to 1, and BL1 is luminance of the first area obtained by turning on the second light source.

US Pat. No. 10,140,930

SIGNAL GENERATING UNIT, SHIFT REGISTER, DISPLAY DEVICE AND SIGNAL GENERATING METHOD

BOE Technology Group Co.,...

1. A signal generating unit, comprising:a first output transistor disposed between an output node and a first power node, the first power node configured for receiving a high-level power supply signal, a gate electrode of the first output transistor coupled to a first node;
a second output transistor disposed between the output node and a second power node, the second power node configured for receiving a low-level power supply signal, a gate electrode of the second output transistor coupled to a second node;
a first-node potential control module, coupled to the first node and configured to output a start signal to the first node;
a second-node potential control module coupled to the second node, the second-node potential control module including a switching-off control unit configured to switch off the second output transistor when the first output transistor is switched on; and
a first capacitor structure connected with the gate electrode of the first output transistor, and configured to be charged when the first-node potential control module outputs a single-pulse-width level signal for controlling the first output transistor to be switched on, and to maintain the gate electrode of the first output transistor in an on state during a subsequent time period having one pulse width, wherein:
the switching-off control unit includes a second potential control transistor, a gate electrode of the second potential control transistor is coupled to the first node, a first electrode of the second potential control transistor is directly connected with the first power node to receive the high-level power supply signal, and a second electrode of the second potential control transistor is coupled to the second node to be connected with the gate electrode of the second output transistor.

US Pat. No. 10,140,929

CURRENT SENSOR AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. An organic light emitting display device comprising:a display panel comprising:
pixels;
power supply lines configured to transfer power to the pixels;
data lines configured to transfer data voltages to the pixels; and
scan lines configured to transfer scan signals to the pixels;
a display panel driver configured to drive the display panel by generating and providing the data voltages to the data lines, and by generating and providing the scan signals to the scan lines;
a power supply configured to generate and supply the power to the power supply lines; and
a current sensor configured to measure a current level of the power, the current sensor comprising:
a first resistor between a first node and a second node;
a first voltage limiting device between the first node and the second node;
a second resistor between the second node and a third node; and
a selector configured to output one of either a first value corresponding to a voltage across the first resistor or a second value corresponding to a voltage across the second resistor,
wherein a resistance level of the first resistor is greater than a resistance level of the second resistor, and
wherein a current flowing from the third node to the first node is configured to be measured based on the voltage across the first resistor or the voltage across the second resistor.

US Pat. No. 10,140,927

GRAY SCALE GENERATOR AND DRIVING CIRCUIT USING THE SAME

MY-SEMI INC., Hsinchu Co...

1. A driving circuit, used for driving a light emitting unit, comprising:a gray scale generation circuit, including:
a shift register unit, receiving a luminance-related data, wherein the shift register unit is a k-bit shift register unit and k is a positive integer greater than 1; and
a data storage unit, having a plurality of parallel input ends and a serial output end, the data storage unit receiving a plurality of bits of the luminance-related data via its parallel input ends from the shift register unit and serially outputting the bits to generate a serial signal, and the data storage unit generating a gray-scale control signal according to the serial signal, wherein the data storage unit determines time points for outputting different bits of the serial signal according to a serial-out control signal; and
a driving unit, coupled to the gray scale generation circuit, adjusting a light-emitting time of the light emitting unit according to the gray-scale control signal received from the gray scale generation circuit.

US Pat. No. 10,140,926

DISPLAY DEVICE AND ELECTRONIC DEVICE HAVING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a pixel unit including a plurality of pixels; and
a driving unit formed on a non-display area adjacent to the pixel unit, the driving unit configured to drive the pixels, wherein the driving unit includes:
an emission driver coupled to a first clock line and a second clock line and configured to receive therefrom a first clock signal and a second clock signal, respectively, and to generate an emission control signal provided to the pixels based on the first clock signal and the second clock signal; and
a scan driver coupled to the emission driver through a first coupling line and a second coupling line, the scan driver configured to receive the first clock signal and the second clock signal from the emission driver and to generate a scan signal provided to the pixels based on the first clock signal and the second clock signal.

US Pat. No. 10,140,925

PIXEL CIRCUITS FOR AMOLED DISPLAYS

Ignis Innovation Inc., W...

1. A display system comprising:a reference voltage source;
a supply voltage source; and
a plurality of pixels arranged in an array, each pixel comprising a pixel circuit including:
a light-emitting device,
a drive transistor for driving current through the light emitting device according to a driving voltage across the drive transistor during an emission cycle, said drive transistor having a gate, a source, a drain and a threshold voltage,
a storage capacitor coupled to said drive transistor for storing said driving voltage, and
a reference voltage transistor coupled to the reference voltage source for coupling the drive transistor to the reference voltage source during a first operation cycle for charging a node common to said storage capacitor and said light-emitting device to the reference voltage, said reference voltage having a magnitude that turns off said light-emitting device, the reference voltage transistor for isolating the drive transistor from the reference voltage source during a second operation cycle subsequent to the first operation cycle for allowing said drive transistor to transfer to said node, a voltage that is a function of the threshold voltage and mobility of said drive transistor.

US Pat. No. 10,140,923

PIXEL DRIVING SYSTEM OF AMOLED HAVING INITIALIZATION SIGNAL OF ALTERNATING HIGH AND LOW LEVELS AND METHOD FOR DRIVING PIXEL OF AMOLED HAVING INITIALIZATION SIGNAL OF ALTERNATING HIGH AND LOW LEVELS

SHENZHEN CHINA STAR OPTOE...

1. A pixel driving system of an organic light emitting display (AMOLED), comprising: a pixel driving circuit and an initialization voltage supply module electrically connected to the pixel driving circuit;the pixel driving circuit comprising: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a capacitor, and an organic light emitting diode;
a gate of the first thin film transistor receives a first scanning signal, a source receives a data signal, a drain is electrically connected to the first node;
a gate of the second thin film transistor is electrically connected to the first node, a drain receives a power supply voltage, a source is electrically connected to a second node;
a gate of the third thin film transistor receives a second scanning signal, a source is electrically connected to the first node, a drain is electrically connected to the third node;
a gate of the fourth thin film transistor receives the second scanning signal, a source is electrically connected to the third node, a drain is electrically connected to the second node;
one end of the capacitor is electrically connected to the first node and the other end is electrically connected to the second node;
an anode of the organic light emitting diode is electrically connected to the second node and the cathode is grounded; and
the initialization voltage supply module is electrically connected to the third node, and provides an initialization signal having a high and low alternating level to the third node in time order, the high level of the initialization signal is equal to the level of the first node when the organic light emitting diode emits light or the level of the second node when the organic light emitting diode emits light or greater than the level of the first node when the organic light emitting diode emits light;
wherein the initialization voltage supply module comprises: a multiplexer, an initialization high voltage generation module, and an initialization low voltage generation module; and
input terminals of the multiplexer are respectively electrically connected to the initialization high voltage generation module and the initialization low voltage generation module; an output terminal is electrically connected to the third node, control terminals receive the first strobe signal and a second gating signal; and
further comprising: a control signal generation module, a first scanning signal output processing module electrically connected to the control signal generation module, and a data signal output processing module electrically connected to the control signal generation module;
the control signal generation module outputs the enable signal of the first scanning signal and the driving signal of the data signal, respectively to the first scanning signal output processing module and the data signal output processing module to control the first scanning signal output processing module and the data signal output processing module output the first scanning signal and the data signal, respectively;
the first strobe signal is the enable signal of the first scanning signal, the second strobe signal is the driving signal of the data signal;
when the enable signal of the first scanning signal is at high level, the first scanning signal is at low level, when the enable signal of the first scanning signal is at low level, the first scanning signal is at high level; and
when the driving signal of the data signal is at low level, the data signal is at low level, and when the driving signal of the data signal is at high level, the data signal is at high level; when the enable signal of the first scanning signal and the driving signal of the data signal are both at high level, the initialization signal is at high level, and the initialization signal is all at low level in the rest of the time.

US Pat. No. 10,140,921

EM SIGNAL CONTROL CIRCUIT, EM SIGNAL CONTROL METHOD AND ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

10. An organic light emitting display device comprising:a panel including a plurality of pixels;
a plurality of shift registers configured to provide scan signals to the respective pixels; and
an emission (EM) signal control circuit coupled to the plurality of shift registers and configured to provide EM signals to the respective pixels,
wherein the EM signal control circuit includes:
a first transistor, wherein a drain electrode of the first transistor is coupled to a first emission power source, a gate electrode of the first transistor is coupled to a QB node, and the first transistor is configured to output a voltage of the first emission power source to an output node coupled to a source electrode thereof in response to a set signal;
a second transistor, wherein a source electrode of the second transistor is coupled to a second emission power source, a gate electrode of the second transistor is coupled to a Q node, and the second transistor is configured to output a voltage of the second emission power source to the output node coupled to a drain electrode thereof in response to a reset signal;
a third transistor, wherein a source electrode of the third transistor is coupled to a second gate power source, a drain electrode of the third transistor is coupled to the QB node, and the third transistor is configured to transfer a voltage of the second gate power source to the QB node in response to the set signal;
a fourth transistor, wherein a drain electrode of the fourth transistor is coupled to a first gate power source, a source electrode of the fourth transistor coupled to the QB node, a gate electrode of the fourth transistor is coupled to the Q node, and the fourth transistor is configured to transfer a voltage of the first gate power source to the QB node in response to the reset signal;
a first capacitor coupled between the QB node and the drain electrode of the first transistor;
a fifth transistor, wherein a source electrode of the fifth transistor is coupled to the second gate power source, a drain electrode of the fifth transistor is coupled to the Q node, and the fifth transistor is configured to transfer the voltage of the second gate power source to the Q node in response to the reset signal; and
a sixth transistor, wherein a source electrode of the sixth transistor is coupled between the drain electrode of the fifth transistor and the Q node, a drain electrode of the sixth transistor is coupled to the first gate power source, and a gate electrode of the sixth transistor is coupled between the QB node and the drain electrode of the third transistor.

US Pat. No. 10,140,920

PIXEL DRIVING CIRCUIT, DISPLAY DEVICE AND PIXEL DRIVING METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A method of driving a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a storage capacitor, a light-emitting device, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor and a fifth switch transistor, whereina control electrode of the first switch transistor is connected with a second scanning line, a first electrode of the first switch transistor is connected with a first power supply terminal, and a second electrode of the first switch transistor is connected with a first terminal of the storage capacitor;
a control electrode of the second switch transistor is connected with a third scanning line, a first electrode of the second switch transistor is connected with the first power supply terminal, and a second electrode of the second switch transistor is connected with a first electrode of the driving transistor and a first electrode of the third switch transistor;
a control electrode of the third switch transistor is connected with a first scanning line, the first electrode of the third switch transistor is connected with the first electrode of the driving transistor, and a second electrode of the third switch transistor is connected with a control electrode of the driving transistor and a second terminal of the storage capacitor;
a control electrode of the fourth switch transistor is connected with the first scanning line, a first electrode of the fourth switch transistor is connected with a data line, and a second electrode of the fourth switch transistor is connected with the first terminal of the storage capacitor;
a control electrode of the fifth switch transistor is connected with a fourth scanning line, a first electrode of the fifth switch transistor is connected with a second electrode of the driving transistor, and a second electrode of the fifth switch transistor is connected with a first terminal of the light-emitting device;
the second terminal of the storage capacitor is connected with the control electrode of the driving transistor, and a second terminal of the light-emitting device is connected with a second power supply terminal; and
the first power supply terminal is used to provide a working voltage, and the second power supply terminal is used to provide a reference voltage,
the method comprising:
performing a data write phase in which the first switch transistor and the fifth switch transistor are turned off, the second switch transistor, the third switch transistor and the fourth switch transistor are turned on, a data voltage on the data line is written to the first terminal of the storage capacitor through the fourth switch transistor, and the working voltage provided by the first power supply terminal is written to the second terminal of the storage capacitor through the second switch transistor and the third switch transistor,
performing a compensation write phase in which the first switch transistor and the second switch transistor are turned off, the third switch transistor, the fourth switch transistor and the fifth switch transistor are turned on, and the driving transistor discharges to write a compensation voltage including a threshold voltage of the driving transistor to the second terminal of the storage capacitor; and
performing a display phase in which the third switch transistor and the fourth switch transistor are turned off, the first switch transistor, the second switch transistor and the fifth switch transistor are turned on, the working voltage provided by the first power supply terminal is written to the first terminal of the storage capacitor through the first switch transistor, a control voltage is output from the second terminal of the storage capacitor to the driving transistor, and the driving transistor generates a driving current under control of the control voltage to drive the light-emitting device to emit light.

US Pat. No. 10,140,919

PIXEL CIRCUIT AND DRIVING METHOD THEREOF

TIANMA JAPAN, LTD., Kawa...

5. A pixel circuit, comprising:a light emitting element;
a driving transistor which supplies an electric current to the light emitting element according to a voltage applied to a gate terminal of the driving transistor;
a capacitor part which holds an emitting voltage containing a threshold voltage of the driving transistor and a data voltage; and
a switch part which holds the emitting voltage in the capacitor part, and applies the emitting voltage which is held by the capacitor part to the gate terminal of the driving transistor, wherein
the switch part applies a prescribed voltage to the gate terminal of the driving transistor, and the driving transistor supplies an electric current corresponding to the prescribed voltage which is applied by the switch part, before making the capacitor part hold the emitting voltage,
the switch part further comprises a current detour transistor which makes the electric current supplied from the driving transistor detour without flowing through the light entitling element before making the capacitor part hold the emitting voltage, and
the electric current supplied from the driving transistor corresponds to the prescribed voltage,
the driving transistor comprises the gate terminal, a source terminal, and a drain terminal, and supplies an electric current according to a voltage applied between the gate terminal and the source terminal to the light emitting element that is connected in series to the drain terminal and the source terminal,
the switch part comprises:
a data voltage transistor which inputs the data voltage from a data supply line, a reference voltage transistor which inputs a reference voltage from a reference voltage line,
a gate voltage transistor which applies the voltage held to the capacitor part between the gate terminal and the source terminal, and
a power switching transistor which function as a switch of an electric current flown to the drain terminal and the source terminal from a power supply voltage line,
the switch part applies the constant voltage between the gate terminal and the source terminal by turning on the data voltage transistor, the reference voltage transistor, the gate voltage transistor, and the power switching transistor,
the switch part makes the capacitor part hold the voltage containing the threshold voltage and the data voltage by turning on the data voltage transistor and the reference voltage transistor and turning off the gate voltage transistor and the power switching transistor, and
the switch part applies the voltage held to the capacitor part between the gate terminal and the source terminal by turning off the data voltage transistor and the reference voltage transistor and turning on the gate voltage transistor and the power switching transistor, wherein
a second terminal of the capacitor part is connected to the source terminal of the driving transistor;
the reference voltage transistor connects the reference voltage line and a first terminal of the capacitor part;
the data voltage transistor connects the data supply line and the gate terminal of the driving transistor;
the gate voltage transistor connects the gate terminal of the driving transistor and the first terminal of the capacitor part;
the power switching transistor connects the power supply line and the source terminal of the driving transistor;
the drain terminal of the driving transistor is connected to a first terminal of the light emitting element;
the current detour transistor connects the first terminal of the light emitting element and a fourth power supply line; and
a second terminal of the light emitting element is connected to a second power supply line.

US Pat. No. 10,140,917

POWER SUPPLY CIRCUIT, DRIVING METHOD FOR THE SAME AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A power supply circuit, comprising:a first control sub-circuit connected to a first voltage level terminal, a first scan signal terminal, and a first node, and configured to control the first voltage level terminal to be connected to the first node under control of a voltage at the first scan signal terminal;
a second control sub-circuit connected to a second voltage level terminal, a second scan signal terminal, and a second node, and configured to control the second voltage level terminal to be connected to the second node under control of a voltage at the second scan signal terminal;
a voltage converting sub-circuit connected to the first node and the second node, and configured to adjust a voltage at the first node and a voltage at the second node under control of the first control sub-circuit and the second control sub-circuit;
a first output sub-circuit connected to a third scan signal terminal, a first output terminal, and the first node, and configured to output the voltage at the first node to the first output terminal under control of a voltage at the third scan signal terminal; and
a second output sub-circuit connected to a fourth scan signal terminal, a second output terminal and the second node, and configured to output the voltage at the second node to the second output terminal, under control of voltage at the fourth scan signal terminal.

US Pat. No. 10,140,916

CHARGE PUMP AND OPERATING METHOD THEREOF

DAZZO TECHNOLOGY CORPORAT...

1. A charge pump, coupled to a loading capacitor, receiving an input voltage and providing an output voltage to the loading capacitor, the charge pump comprising:three capacitors comprising a first capacitor, a second capacitor and a third capacitor; and
ten switches comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch and a tenth switch;
wherein the first switch and the second switch are coupled in series between the input voltage and a ground terminal; one terminal of the first capacitor is coupled between the first switch and the second switch and another terminal of the first capacitor is coupled to the third switch; the third switch is coupled between the first capacitor and the fifth switch; one terminal of the second capacitor is coupled to a first node between the first capacitor and the third switch and another terminal of the second capacitor is coupled to a second node between the third switch and the fifth switch; the fourth switch is coupled between the second node and the loading capacitor; the loading capacitor is coupled between the fourth switch and the ground terminal; the fifth switch is coupled between the third switch and the third capacitor; one terminal of the sixth switch is coupled to the first node and another terminal of the sixth switch is coupled to a third node between the fifth switch and the third capacitor; the seventh switch is coupled between the third node and the ground terminal; the third capacitor is coupled between the fifth switch and the tenth switch; one terminal of the eighth switch is coupled to the ground terminal and another terminal of the eighth switch is coupled to a fourth node between the third capacitor and the tenth switch; the ninth switch is coupled between the fourth node and the first node; one terminal of the tenth switch is coupled to the fourth node and the another terminal of the tenth switch is coupled to a fifth node between the fourth switch and the loading capacitor.

US Pat. No. 10,140,915

DISPLAY DEVICE, DISPLAY SYSTEM AND DISPLAY METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A display device, comprising a driver circuit, a display panel, and an interference unit arranged at a display side of the display panel, the interference unit comprising a front light source, whereinthe driver circuit is configured to drive the display panel to display an image, and a time period for each frame of the image comprises a display period and an interference period;
during the display period, the front light source is turned off to be in a transparent state so as to enable light beams from the display panel to pass through the interference unit; and
during the interference period, the front light source is turned on to emit light and to be in an interference state so as to interfere with the light beams from the display panel.

US Pat. No. 10,140,912

SHARED MULTIPOINT REVERSE LINK FOR BIDIRECTIONAL COMMUNICATION IN DISPLAYS

Samsung Display Co., Ltd....

1. A display interface, comprising:a timing controller;
a first plurality of driver integrated circuits;
a first shared data lane connected to the timing controller and to each of the first plurality of driver integrated circuits; and
a shared synchronization lane connected to the timing controller and to each of the first plurality of driver integrated circuits,
each of the first plurality of driver integrated circuits having:
a data input configured to receive reverse data from a display panel; and
a buffer configured to store reverse data,
the timing controller being configured to periodically send, on the shared synchronization lane, a synchronization pulse, having a triggering edge, to all of the driver integrated circuits of the first plurality of driver integrated circuits,
each of the first plurality of driver integrated circuits being configured to periodically send, on the first shared data lane, reverse data to the timing controller in a respective time slot of a plurality of non-overlapping time slots, after each triggering edge.

US Pat. No. 10,140,910

SHIFT REGISTER, A GATE LINE DRIVING CIRCUIT, AN ARRAY SUBSTRATE AND A DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A shift register, comprising:an inputting circuit, having a first terminal connected to a signal inputting terminal and a second terminal connected to a pulling up node, wherein the inputting circuit is configured to control a potential of the pulling up node, under the control of the signal inputting terminal;
a pulling down driving circuit, having a first terminal connected to a direct current (DC) signal terminal, a second terminal connected to a pulling down node, a third terminal connected to the pulling up node, and a fourth terminal connected to a low level signal terminal, wherein the pulling down driving circuit is configured to control the pulling down node being at a low level when the pulling up node is at a high level and to control the pulling up node being at the low level when the pulling down node is at the high level;
a resetting circuit, having a first terminal connected to a resetting signal terminal, a second terminal connected to the pulling up node, a third terminal connected to the low level signal terminal, and a fourth terminal connected to a signal outputting terminal, wherein the resetting circuit is configured to pull down the potentials of the pulling up node and the signal outputting terminal, under the control of the resetting signal terminal;
a first outputting circuit, having a first terminal connected to the pulling down node, a second terminal connected to the low level signal terminal, and a third terminal connected to the signal outputting terminal, wherein the first outputting circuit is configured to pull down the potential of the signal outputting terminal, under the control of the pulling down node;
a controlling circuit, having a first terminal connected to the DC signal terminal, a second terminal connected to a ground, a third terminal connected to the low level signal terminal, a fourth terminal connected to the pulling up node, and a fifth terminal connected to a first terminal of a second outputting circuit, wherein the controlling circuit is configured to connect the second outputting circuit with the pulling up node when the pulling up node is at the high level, and to pull the potential of the first terminal of the second outputting circuit down to a potential as twice as the potential of the low level signal terminal when the pulling up node is at the low level, under the control of the DC signal terminal and the pulling up node; and
the second outputting circuit, having a second terminal connected to the pulling up node, a third terminal connected to a clock signal terminal and a fourth terminal connected to the signal outputting terminal, wherein the second outputting circuit is configured to output a signal of a clock signal terminal via the signal outputting terminal, under the control of the pulling up node.

US Pat. No. 10,140,909

DISPLAY DEVICE

1. A display device comprising:a plurality of pixels arranged in a two dimensional matrix in an image display region, wherein, each of the pixels includes a plurality of sub-pixels, and each of the sub-pixels includes a self-luminous layer;
a low-density region arranged in the image display region and including low-density pixels each including a first number of the sub-pixels;
a high-density region arranged in the image display region and including high-density pixels each including a second number of the sub-pixels, wherein the second number is greater than the first number;
a lighting drive circuit arranged in the image display region and configured to light up the self-luminous layer,
wherein the sub-pixels are configured to receive signals to drive the sub-pixels through wiring, the wiring being provided below the self-luminous layer with respect to an image display surface of the image display region; and
a drive control circuit configured to provide at least one of scanning signals or power supply signals to respectively control driving of the lighting drive circuit of said each of the pixels, the drive control circuit being arranged within the image display region in the low-density region and outside the high-density region.

US Pat. No. 10,140,908

LED DRIVING CIRCUIT AND METHOD

MY-SEMI INC., Hsinchu Co...

1. A LED driving circuit used to generate a driving current to drive the LED during a grayscale period according to a grayscale signal, comprising:a high bit driving circuit coupled to a high bit signal of the grayscale signal determining a first current continuously driven during the grayscale period according to a value of the high bit signal of the grayscale signal, wherein the first current is invariant during the grayscale period;
a low bit driving circuit coupled to a low bit signal of the grayscale signal determining a second current driven in at least two time intervals during the grayscale period according to a value of the low bit signal of the grayscale signal; and
a driving output terminal coupled to the high bit driving circuit and the low bit driving circuit outputting the driving current added by the first current and the second current;
wherein a ratio of the first current to a constant current is m/(2k), m is the value of the high bit signal, and k is a bit number of the high bit signal.

US Pat. No. 10,140,907

DISPLAY PANEL, DISPLAY DEVICE AND METHOD FOR PIXEL ARRANGEMENT

BOE TECHNOLOGY GROUP CO.,...

1. A display panel comprising a plurality of sub-pixels arranged in an array, wherein the sub-pixels arranged in a first direction are arranged in one of following modes:a first mode of sub-pixel arrangement, in which a first sub-pixel or a third sub-pixel is inserted between every two second sub-pixels; and
a second mode of sub-pixel arrangement, in which the first sub-pixel and the third sub-pixel are inserted between every two second sub-pixels,
wherein the second sub-pixel is a green sub-pixel, the first sub-pixel is one of a red sub-pixel and a blue sub-pixel, and the third sub-pixel is the other of the red sub-pixel and the blue sub-pixel,
wherein compensation is performed on image data for the first sub-pixel using a first compensation parameter and mapping is performed on a compensation result of the image data for the first sub-pixel using a first mapping parameter to obtain output image data for the first sub-pixel,
wherein compensation is performed on image data for the third sub-pixel using a third parameter and mapping is performed on a compensation result of the image data for the third sub-pixel using a third mapping parameter to obtain output image data for the third sub-pixel,
wherein mapping is performed on image data for the second sub-pixel using a second mapping parameter, and a mapping result of the image data for the second sub-pixel, the compensation result of the image data for the first sub-pixel and the compensation result of the image data for the third sub-pixel are superimposed onto each other to obtain output image data for the second sub-pixel.

US Pat. No. 10,140,904

ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL AND DRIVING METHOD THEREOF AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An organic light emitting diode (OLED) display panel, comprising a plurality of pixel units, each pixel unit including six colors of sub-pixels: a red sub-pixel, a green sub-pixel, a blue sub-pixel, a cyan sub-pixel, a fuchsine sub-pixel and a yellow sub-pixel,wherein, in the six colors of sub-pixels, three colors of sub-pixels and the other three colors of sub-pixels are arranged in an overlapping manner in a light exiting direction perpendicular to the display panel, and
wherein the three colors of sub-pixels include two of the red sub-pixel, the green sub-pixel and the blue sub-pixel, and one of the cyan sub-pixel, the fuchsine sub-pixel and the yellow sub-pixel, and
the other three colors of sub-pixels include the other one of the red sub-pixel, the green sub-pixel and the blue sub-pixel, and the other two of the cyan sub-pixel, the fuchsine sub-pixel and the yellow sub-pixel.

US Pat. No. 10,140,902

DISPLAY METHOD AND DISPLAY PANEL

BOE Technology Group Co.,...

1. A display method applied to a display panel, wherein the display panel comprises a plurality of rows of sub-pixels, the sub-pixels in each row are arranged in cyclical orders of sub-pixels of three colors, and the cyclical orders of the sub-pixels in the respective rows being the same; the adjacent sub-pixels in a column direction having different colors and being staggered from each other by ½ of a sub-pixel in a row direction, wherein the display method comprises the following steps:S1, generating an original image composed of a matrix of virtual pixels;
S2, enabling the virtual pixels to correspond to sampling locations, wherein each sampling location corresponds to a virtual pixel; wherein each sampling location is located between every two adjacent rows of the sub-pixels, and corresponds to a location between two sub-pixels in one row and a central location of a sub-pixel in the other row; and
S3, calculating a display component of each sub-pixel in accordance with original components of corresponding colors of the virtual pixels corresponding to the sub-pixel,
wherein the virtual pixels are in one-to-one correspondence with the sampling locations, the sampling locations constitute a matrix, the number of rows of the matrix is less than the number of rows of the sub-pixels of the display panel by one and the number of columns of the matrix is less than twice of the number of the sub-pixels in one row by two; anda dimension of a sub-pixel in each of the first row and the last row in the column direction is ½ of that of a standard sub-pixel in the column direction.

US Pat. No. 10,140,900

DATA DRIVER, DISPLAY DEVICE INCLUDING THE DATA DRIVER AND METHOD OF DRIVING THE DISPLAY DEVICE WITH DIFFERENT GAMMA DATA

SAMSUNG DISPLAY CO., LTD....

1. A data driver comprising:a gamma unit receiving at least one reference voltage, and generating a first gamma reference voltage corresponding to a first sub-pixel of a pixel and a second gamma reference voltage corresponding to a second sub-pixel of the pixel using the received at least one reference voltage, and generates separate gamma curves for each of the first sub-pixel and second sub-pixel;
a digital-to-analog converter receiving the first and second gamma reference voltages from the gamma unit, and generating a first gamma data value corresponding to the first sub-pixel using the first gamma reference voltage and a second gamma data value corresponding to the second sub-pixel using the second gamma reference voltage; and
an output buffer outputting a first frame including the first gamma data value and a second frame including the second gamma data value, respectively,
wherein the output buffer outputs the first and second frames in a repeated manner for every predetermined number of frames,
wherein the output buffer outputs the first and second frames using a single amplifier, and wherein an output frame rate of the single amplifier is proportional to a number of gamma curves set.

US Pat. No. 10,140,899

IMAGE SHIFT CONTROLLER FOR CHANGING A STARTING POSITION OF AN IMAGE AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. An image shift controller comprising:a starting position generator configured to generate image position information using sample data of first image data, and comprising:
a first flip flop configured to receive a partial bit of the sample data; and
a plurality of second flip flops configured to receive output signals of a respective preceding one of the first and second flip flops; and
a shift determiner configured to determine a movement direction and a movement amount of an image using the image position information.

US Pat. No. 10,140,898

MULTI-VIEW DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A multi-view display device, comprising:a display panel; and
an optical grating;
wherein the display panel comprises an array of a plurality of sub-pixels, and the sub-pixels in different columns, which are adjacent to each other in a row direction, are of different colors and staggered in a column direction;
wherein the array comprises a plurality of pixel units, and each of the pixel units comprises at least one sub-pixel in each of three adjacent columns of the sub-pixels;
wherein in each pixel unit, a middle column comprises more sub-pixels than each of two side columns, amounts of the sub-pixels in the two side columns are identical, and the middle column comprises one more sub-pixel than each of the two side columns; and
wherein the optical grating comprises a light-transmitting region corresponding to a central region of the middle column in each pixel unit,
wherein in each pixel unit, the middle column comprises two sub-pixels, and the central region of the middle column comprises a part of each of the two sub-pixels in the middle column which is near to a center of the middle column, an area of the central region is smaller than an area of one sub-pixel; and a size of the light-transmitting region of the optical grating is adapted to a total size of the sub-pixels in the central region of the middle column in each pixel unit.

US Pat. No. 10,140,896

AIRFRAME DISPLAY SYSTEMS AND METHODS

Skyline Displays, LLC, E...

1. A display system, comprising:a plurality of airtight, inflatable airbeams defining an airframe, each airbeam comprising a sleeve of dimensionally stable material configured to define a predetermined inflated sleeve dimension, the predetermined inflated sleeve dimension of the plurality of airbeams defining a depth of the airframe;
a stretch fabric cover defining an enclosure having a front surface area and a back surface area, the airframe received within the stretch fabric cover;
whereby, when inflated, the stretch fabric cover is drawn taut over the airframe such that the front surface area of the stretch fabric cover is substantially smooth and spaced from the back surface area by the depth of the airframe.

US Pat. No. 10,140,893

ENCIRCLED WRISTBAND DEVICE AND METHOD FOR REMOVAL

1. A wristband comprising:an elongated base band layer of flexible material having sufficient length to encircle a human wrist, said base band layer having a top side and bottom side, said base band layer further comprising a removable portion of flexible material, said removable portion having a top side and a bottom side;
a permanent fastener affixed to said base band layer to allow for encirclement of said base band layer around said human wrist;
a plurality of perforations separating said removable portion of said base band layer from said base band layer to allow for removal of said removable portion from said base band layer; and
a plurality of removable tab layers layered upon and affixed to said base band layer, said plurality of removable tab layers being disposed on top of said removable portion of flexible material of said base band layer, wherein said removable tab layers are stacked one on top of another, and wherein each of said removable tab layers comprise:
a removable portion,
a permanently affixed portion at opposing ends of each of said removable tab layers providing attachment to a permanently affixed portion of any preceding tab layer and providing attachment to said base band layer, and
a plurality of perforations separating said removable portion of said removable tab layer from said base band layer and separating said removable portion of said removable tab layer from said permanently affixed portion.

US Pat. No. 10,140,892

MULTI-PART LABEL SYSTEMS

1. A method of assembling a multi-layer label, the method comprising the steps of:providing a label dispensing apparatus, said label dispensing apparatus comprising a dispensing mechanism and a receptacle;
providing a carrier material to said label dispensing apparatus, said carrier material comprising a first label thereon and a second label thereon in a position on said carrier material adjacent to said first label, wherein said first label and said second label are removably adhered to said carrier material in a non-overlapping arrangement, said first label comprising a top side and an opposing underside, said underside facing said carrier material, said second label comprising a top surface and an opposing undersurface, said undersurface facing said carrier material;
with said label dispensing apparatus, dispensing said first label from said carrier material onto said receptacle, whereby said underside of said first label is against said receptacle and said top side of said first label is exposed;
while said first label is on said receptacle, with said label dispensing apparatus, dispensing said second label from said carrier material, wherein said second label alights on said first label such that said second label is layered over and aligned with said first label with said undersurface of said second label in contact with said top side of said first label.

US Pat. No. 10,140,891

ACTIVATABLE ADHESIVE, LABELS, AND RELATED METHODS

Avery Dennison Corporatio...

1. A label assembly comprising a facestock layer and a heat activatable adhesive layer, and a functional coating layer disposed between the adhesive layer and the facestock layer, wherein the heat activatable adhesive layer comprises:20 to 35 wt % of a base polymer including at least one lower alkyl acrylate selected from the group consisting of methyl acrylate, ethyl acrylate, butyl acrylate and 2-ethylhexyl acrylate, styrene, methyl methacrylate, methacrylic acid, acrylic acid,
at least one multifunctional monomer, and
at least one chain transfer agent,
wherein the concentrations of the above components of the base polymer are:
12 to 48 wt % of the at least one lower alkyl acrylate,
23 to 78 wt % of styrene,
3 to 30 wt % of methyl methacrylate,
1 to 2 wt % of methacrylate acid,
1 to 3 wt % of acrylic acid,
0.5 to 2.5 wt % of the at least one multifunctional monomer, and
1.0 to 4.0 wt % of the at least one chain transfer agent,
50 to 75 wt % of a plasticizer, and
5 to 20 wt % of a tackifier.

US Pat. No. 10,140,890

GIFT CARD PRESENTER FOR GREETING CARDS

HALLMARK CARDS, INCORPORA...

1. A method of using a gift card presenter with a greeting card, the method comprising:providing the greeting card;
providing the gift card presenter, the gift card presenter comprising:
a body comprising a cover panel, a holding panel, and a joining panel which, when folded together, provide a pocket for receiving a corner of the greeting card,
wherein the cover panel and the joining panel are coupled to the holding panel along separate edges of the holding panel that are adjoining,
wherein the body includes a plurality of slots for receiving corners of a gift card,
wherein the plurality of slots are formed in one of the cover panel and the holding panel, and
wherein the joining panel has been folded and secured to the cover panel to form the pocket;
coupling the gift card presenter to the greeting card by placing the corner of the greeting card within the pocket; and
upon coupling the gift card presenter to the greeting card, folding a portion of the greeting card to at least partially cover the gift card presenter.

US Pat. No. 10,140,888

TRAINING AND TESTING SYSTEM FOR ADVANCED IMAGE PROCESSING

TeraRecon, Inc., Foster ...

1. A method for providing a networked system of computer training stations, the method comprising:providing an image processing server that includes an image processing training system, the image processing training system having at least one medical image associated with a medical image processing training course (MIPTC), including:
capturing the at least one medical image by a medical imaging device so that the at least one medical image includes a view of an internal organ or structure of a body captured by the medical imaging device in image slices that are combined to form the at least one medical image, and
storing the at least one medical image by a storage associated with the image processing server;
providing a first computer training station, the first computer training station implemented by a first client device and a first display, including:
displaying by the first client device, in a first display area of the first display, the at least one medical image stored by the storage associated with the image processing server,
providing, by the first client device within a second display area of the first display, a first workflow template of a plurality of workflow templates stored in the image processing server:
wherein the first workflow template is provided based on a role or an access privilege of a first user,
wherein the first workflow template comprises a representation of a predefined set of workflow stages associated with a type of medical diagnosis or processing, and
wherein each workflow stage defines one or more image processing operations and includes one or more user selectable image processing tools to allow users to measure a diameter, an area, a distance, or a volume of a body part within the medical image displayed in the first display area,
providing, by the first client device, an instruction associated with a currently displayed workflow stage of the first workflow template, the instruction requesting the first user to perform a quantitative determination on at least a portion of the body part within the medical image displayed in the first display area and to perform the one or more image processing operations on the medical image using the one or more user selectable image processing tools provided by the currently displayed workflow stage on the first client device,
transmitting, from the first client device to the image processing server, a user action input performed by the first user using the one or more of the image processing tools in response to performing the requested quantitative determination and the one or more image processing operations, wherein the user action invokes the image processing server to perform the quantitative determination based on a determined type of user action performed by the first user,
receiving, by the first client device from the image processing server, a quantitative value as a result of the image processing server performing the quantitative determination, and
comparing, by the first client device, the quantitative value to a predefined model answer associated with the medical image to determine a score evaluating the quantitative determination performed by the first user, and
displaying, by the first client device, the score on the first display; and,
providing a second computer training station, the second computer training station implemented by a second client device and a second display, including:
providing, by the second client device and within a second display area of the first display, a second workflow template of the plurality of workflow templates stored in the image processing server, wherein the second workflow template is provided based on a role or an access privilege of a second user.

US Pat. No. 10,140,886

AUTOMATED ASSESSMENT AND GRADING OF COMPUTERIZED ALGORITHMS

DATA SCIENCE EVANGELISTS,...

1. A method for grading a user solution to a computing assignment, comprising:receiving a program code submitted by a user, wherein the received program code is the user solution to the computing assignment;
activating a plurality of code execution engines, wherein each code execution engine of the plurality of code execution engines is a secured isolated execution environment;
executing the program code in the plurality of code execution engines concurrently to produce an answer;
determining a grade for the answer based on an expected answer and an approximate grading function, wherein the approximate grading function is determined based on a type of the computing assignment; and
returning the grade to the user.

US Pat. No. 10,140,884

METHOD AND APPARATUS FOR WRITING FORM TRAINING

1. An apparatus for writing position alignment that is wearable on a writing hand of a user, comprising:a wearable structure comprising:
a glove comprising a palm side, a back side and an edge side, the glove further including at least a forefinger portion, a middle finger portion, a thumb portion, and an outer lateral back portion that is configured to be worn on at least a forefinger, middle finger, a thumb and an outer lateral back portion of the writing hand of the user, respectively;
a first attachment device comprising a first mechanical fastener affixed in position on and connecting the palm side of the forefinger portion and the middle finger portion of the glove to each other, such that a writing implement can be located on the first attachment device opposite the palm side between the forefinger and the middle finger of the writing hand of the user;
a second attachment device comprising a second mechanical fastener corresponding to the first mechanical fastener affixed in position on the palm side of the thumb portion of the glove, the second mechanical fastener of the second attachment device being configured to releasably engage directly with and contact the first mechanical fastener of the first attachment device, so that releasably engaging directly with and contacting the first attachment device and the second attachment device together connects the thumb portion, forefinger portion and middle finger portion of the glove together in a desired grip position, for writing with the writing implement, such that the dimensions of the writing implement felt by the user are substantially maintained and the writing implement is not fully surrounded by the wearable apparatus; and
a protrusion releasably fastened by a mechanical fastener at a variable position on the outer lateral back portion of the glove not along the edge such that when the glove is on the writing hand of the user, the protrusion is positioned between a pinky finger and a wrist of the writing hand of the user at a position for urging the writing hand of the user to a desired position for writing wherein the edge of the writing hand of the user comprising an entire outer lateral portion and heel of a palm between the pinky finger and the wrist are permitted to directly support the writing hand of the user on a writing surface via the urging provided by the protrusion such that the edge of the glove is not resting on the protrusion.

US Pat. No. 10,140,879

INTERACTIVE BEHAVIORAL TREATMENT DELIVERY SYSTEM AND METHOD OF USE

1. An interactive birthing patient computerized behavioral treatment delivery system comprising: receiving means for inputting data concerning one or more among a birthing patient preference, a birthing patient symptom, an external condition, or an available resource, evaluation means for automatically determining without interacting with a medical practitioner one or more available birthing patient behavioral treatment options according to a set of rules specifying birthing patient behavioral instructional content, the set of rules including: (i) rules specifying birthing patient behavioral instructional content according to desires and preferences of a birthing patient for behavioral treatment education, (ii) rules specifying birthing patient behavioral instructional content according to when a particular need, desire, condition, or symptom appears, (iii) rules specifying birthing patient behavioral instructional content according to one or more of physical attributes, state history, and decisions of the birthing patient and external and birthing patient variables, conditions, and circumstances, (iv) rules specifying birthing patient behavioral instructional content that shows the birthing patient what is occurring in her body and how far she has progressed and thereby tends to motivate her to continue with her labor by showing the extent of her progress, and (v) rules providing for selection of birthing patient behavioral instructional content by the birthing patient and thereby tending to provide her with confidence and a feeling of control, presenting means for displaying said one or more available birthing patient behavioral treatment options, monitoring means for detecting the occurrence of a birthing patient behavioral treatment option selection event, programming means for accessing birthing patient behavioral instructional content associated with said treatment option selection, and feedback means for displaying said birthing patient behavioral instructional content in an instructional view,wherein the birthing patient behavioral instructional content includes a plurality of videos, and wherein the input data comprises a biometric data collection device.