US Pat. No. 10,991,896

ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

UNIVERSAL DISPLAY CORPORA...

1. A first device comprising a first organic light emitting device, the first organic light emitting device comprising:an anode;
a cathode; and
an organic layer, disposed between the anode and the cathode, comprising a compound having a formula of Ir(L1)x(L2)y,
wherein x is 1 or 2;
wherein y is 1 or 2;
wherein x+y is 3;
wherein the first ligand L1 has the formula:

wherein the second ligand L2 has a formula selected from the group consisting of

wherein R1, R2, R3, and R4 are independently selected from group consisting of alkyl and cycloalkyl;
wherein each of R1, R2, R3, and R4 has at least two C;
wherein Ra and Rb can represent mono, di, tri, or tetra substitution, or no substitution;
wherein each of Ra, Rb, and R5 is selected from group consisting of hydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof;
wherein two adjacent substituents of Ra and Rb are optionally joined to form a fused ring or form a multidentate ligand; and
wherein R1 and R2 or R3 and R4 can be joined to form into a ring.

US Pat. No. 10,991,895

ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES

UNIVERSAL DISPLAY CORPORA...

1. A compound having a partial structure of
wherein Ra1, Ra2, Ra3, Ra4, and R are independently selected from the group consisting of hydrogen, deuterium, halide, alkyl, haloalkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, thioalkoxy, aryloxy, thioaryloxy, amino, silyl, halosilyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, NCO, NCS, OCN, SCN, OCmF2m+1 or SCmF2m+1, and combinations thereof;
wherein Rb1, Rb2, Rb3, and Rb4 are independently selected from the group consisting of hydrogen, deuterium, alkyl, haloalkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, and combinations thereof;
wherein two or more of Ra1, Ra2, Ra3, Ra4, Rb1, Rb2, Rb3, Rb4, and R can join to form fused rings;
wherein at least one of Ra1, Ra2, Ra3, and Ra4 is CN; and
wherein M is a metal having an atomic mass of at least 40.

US Pat. No. 10,991,894

COMPOUND OF ORGANIC SEMICONDUCTOR AND ORGANIC SEMICONDUCTOR DEVICE USING THE SAME

FOUNDATION OF SOONGSIL UN...

1. An organic semiconductor compound, comprising:a precursor structure; and
an organic semiconductor,
wherein the organic semiconductor penetrates the precursor structure to form a three-dimensional network structure,
wherein the precursor structure is formed by gelating an organometallic precursor by hydrolysis and condensation reaction,
wherein the organometallic precursor is represented by Formula 1 below:

wherein M1 and M2 each independently comprise at least one of Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Si, Cu, Zn, Pd, Ag, Au, Hg, Pt, Ta, Mo, Zr, Ta, Mg, Sn, Ge, Y, Nb, Tc, Ru, Rh, Lu, Hf, W, Re, Os, Ir, Lr, Rf, Db, Sg, Bh, Hs, Mt, Ds, Rg, and Uub,
Y is one of a substituted or unsubstituted C1 to C30 alkyl group, a C3 to C30 cycloalkyl group, a C3 to C30 heterocyclic group, a C2 to C30 alkenyl group, a C3 to C30 cycloalkenyl group, a C2 to C30 alkynyl group, a C1 to C30 alkoxy group, a C1 to C30 alkylthio group, a C3 to C30 arylether group, a C3 to C30 arylthioether group, a C3 to C30 aryl group, a C3 to C30 heteroaryl group, a halogen atom, a cyano group, a formyl group, a C1 to C30 alkylcarbonyl group, a C3 to C30 arylcarbonyl group, a carboxyl group, a C1 to C30 alkoxycarbonyl group, a C3 to C30 aryloxycarbonyl group, a C1 to C30 alkylcarbonyloxy group, a C1 to C30 arylcarbonyloxy group, a carbamoyl group, an amino group, and a silyl group, and
X1 and X2 are each independently one selected from the group consisting of a hydrogen atom, a substituted or unsubstituted C1 to C30 alkyl group, a C3 to C30 cycloalkyl group, a C3 to C30 heterocyclic group, a C2 to C30 alkenyl group, a C3 to C30 cycloalkenyl group, a C2 to C30 alkynyl group, a C1 to C30 alkoxy group, a C1 to C30 alkylthio group, a C3 to C30 arylether group, a C3 to C30 arylthioether group, a C3 to C30 aryl group, a C3 to C30 heteroaryl group, a halogen atom, a cyano group, a formyl group, a C1 to C30 alkylcarbonyl group, a C3 to C30 arylcarbonyl group, a carboxyl group, a C1 to C30 alkoxycarbonyl group, a C3 to C30 aryloxycarbonyl group, a C1 to C30 alkylcarbonyloxy group, a C1 to C30 arylcarbonyloxy group, a carbamoyl group, an amino group, and a hydroxyl group, wherein the substituted alkyl group comprises an alkyl group substituted with a halogen element.

US Pat. No. 10,991,893

ORGANIC SEMICONDUCTING COMPOUNDS

RAYNERGY TEK INCORPORATIO...

1. A compound of formula Iwherein individual radicals, independently of each other and on each occurrence identically or differently, have the following meaningsAr2,3 arylene or heteroarylene that has from 5 to 20 ring atoms, is mono- or polycyclic, optionally contains fused rings, and is unsubstituted or substituted by one or more identical or different groups L,
Ar4,5 arylene or heteroarylene that has from 5 to 20 ring atoms, is mono- or polycyclic, optionally contains fused rings, and is unsubstituted or substituted by one or more identical or different groups L, or CY1?CY2 or —C?C—,
Y1, Y2 H, F, Cl or CN,
W1,2 S, O or Se,
U1 CR1R2, SiR1R2, GeR1R2, or C?O,
U2 CR3R4, SiR3R4, GeR3R4, or C?O,
R1-4 H, F, Cl or straight-chain, branched or cyclic alkyl with 1 to 30, C atoms, in which one or more CH2 groups are optionally replaced by —O—, —S—, —C(?O)—, —C(?S)—, —C(?O)—O—, —O—C(?O)—, —NR0—, —SiR0R00—, —CF2—, —CR0?CR00—, —CY1?CY2— or —C?C— in such a manner that O and/or S atoms are not linked directly to one another, and in which one or more H atoms are optionally replaced by F, Cl, Br, I or CN, and in which one or more CH2 or CH3 groups are optionally replaced by a cationic or anionic group, or aryl, heteroaryl, arylalkyl, heteroarylalkyl, aryloxy or heteroaryloxy, wherein each of the aforementioned cyclic groups has 5 to 20 ring atoms, is mono- or polycyclic, does optionally contain fused rings, and is unsubstituted or substituted by one or more identical or different groups L, and the pair of R1 and R2 and/or the pair of R3 and R4 together with the C, Si or Ge atom to which they are attached, may also form a spiro group with 5 to 20 ring atoms which is mono- or polycyclic, does optionally contain fused rings, and is unsubstituted or substituted by one or more identical or different groups L
RT1, RT2 are selected from the group consisting of H, F, Cl, Br, —NO2, —ON, —CF3, R*, —CF2—R*, —O—R*, —S—R*, —SO2—R*, —SO3—R*, —C(?O)—H, —C(?O)—R*, —C(?S)—R*, —C(?O)—CF2—R*, —C(?O)—OR*, —C(?S)—OR*, —O—C(?O)—R*, —O—C(?S)—R*, —C(?O)—SR*, —S—C(?O)—R*, —C(?O)NR*R**, —NR*—C(?O)—R*, —NHR*, —NR*R**, —CR*?CR*R**, —C?C—R*, —C?C—SiR*R**R***, —SiR*R**R***, —CH?CH(CN), —CH?C(CN)2, —C(CN)?C(CN)2, —CH?C(CN)(Ra), CH?C(CN)—C(?O)—OR*, —CH?C(CO—OR*)2, —CH?C(CO—NR*R**)2, and the group consisting of the following formulae

Ra, Rb aryl or heteroaryl, each having from 4 to 30 ring atoms, optionally containing fused rings and being unsubstituted or substituted with one or more groups L, or one of the meanings given for L,
R*, R**, R*** alkyl with 1 to 20 C atoms which is straight-chain, branched or cyclic, and is unsubstituted, or substituted with one or more F or C1 atoms or CN groups, or perfluorinated, and in which one or more C atoms are optionally replaced by —O—, —S—, —C(?O)—, —C(?S)—, —SiR0R00—, —NR0R00—, —CHR0?CR00— or —C?C— such that O— and/or S-atoms are not directly linked to each other,
L F, Cl, —NO2, —CN, —NC, —NCO, —NCS, —OCN, —SCN, R0, OR0, SR0, —C(?O)X0, —C(?O)R0, —C(?O)—OR0, —O—C(?O)—R0, —NH2, —NHR0, —NR0R00, —C(?O)NHR0, —C(?O)NR0R00, —SO3R0, —SO2R0, —OH, —NO2, —CF3, —SF5, or optionally substituted silyl, or carbyl or hydrocarbyl with 1 to 30,
L? H or one of the meanings of L,
Y1, Y2 H, F, Cl or CN,
r 0, 1, 2, 3 or 4,
s 0, 1, 2, 3, 4 or 5,
t 0, 1, 2 or 3,
u 0, 1 or 2,
R0, R00 H or straight-chain or branched alkyl with 1 to 20 C atoms that is optionally fluorinated,
X0 halogen,
a, b 0, 1, 2 or 3,
m 1, 2 or 3.

US Pat. No. 10,991,892

MATERIALS FOR ORGANIC ELECTROLUMINESCENT DEVICES

Merck Patent GmbH, Darms...

1. An organic electroluminescent device which comprises a compound of the formula (2a)
where the following applies to the symbols and indices used:
Ar is on each occurrence, identically or differently, a phenylene group, which is optionally substituted by one or more radicals R; wherein the phenylene is identically or differently selected from the formulae (3), (4) or (5),

 where the dashed bond in each case indicates the linking of these groups and each of these groups is optionally substituted by one or more radicals R and wherein at least one of the phenylene groups is a group of formula (4) or formula (5),
Ar1 is an aromatic ring system having 6 to 24 aromatic ring atoms which contains no condensed aryl groups having more than 10 aromatic ring atoms and which is optionally substituted by one or more radicals R1, or is a dibenzofuran or dibenzothiophene group, each of which is optionally substituted by one or more radicals R1;
Ar2 is on each occurrence, identically or differently, an aryl group, where the aryl group has 6 to 10 aromatic ring atoms and is optionally substituted by one or more non-aromatic radicals R1, or is a dibenzofuran or dibenzothiophene group, each of which is optionally substituted by one or more radicals R1;
R is on each occurrence, identically or differently, H, D, F, CN, an aryl group, a biaryl group, a triaryl group or quateraryl group, where each individual aryl group in the above-mentioned groups has 6 to 10 aromatic ring atoms and is optionally substituted by one or more radicals R1, or a carbazole group which is linked via a carbon atom and which may also be substituted by one or more radicals R1;
R1 is on each occurrence, identically or differently, H, D, F, CN, a straight-chain alkyl or alkoxy group having 1 to 20 C atoms or a branched or cyclic alkyl or alkoxy group having 3 to 20 C atoms, where one or more non-adjacent CH2 groups is optionally replaced by R2C?CR2, C?C or O and where one or more H atoms is optionally replaced by D or F, or an aryl group having 6 to 10 C atoms, which is optionally substituted by one or more radicals R2, or is a dibenzofuran or dibenzothiophene group, each of which is optionally substituted by one or more radicals R2, or a carbazole group which is linked via a carbon atom and which may also be substituted by one or more radicals R2, or an aralkyl group having 6 to 10 aromatic ring atoms, which is optionally substituted by one or more radicals R2; two adjacent substituents R1 here, together with the atoms to which they are bonded, may also form a mono- or polycyclic, aliphatic ring system with one another;
R2 is on each occurrence, identically or differently, H, D or an aliphatic hydrocarbon radical having 1 to 20 C atoms or an aryl group having 6 to 10 ring atoms;
n is 2, 3 or 4,
wherein the compound of the formula (2a) is employed as matrix material for phosphorescent emitters in an emitting layer.

US Pat. No. 10,991,891

CONDENSED CYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

13. An organic light-emitting device comprising:a first electrode;
a second electrode facing the first electrode; and
an organic layer between the first electrode and the second electrode,
wherein the organic layer comprises an emission layer and at least one of the condensed cyclic compound of claim 1.

US Pat. No. 10,991,890

COMPOUND CONTAINING A 5-MEMBERED HETEROCYCLE AND ORGANIC LIGHT-EMITTING DIODE USING SAME, AND TERMINAL FOR SAME

DUK SAN NEOLUX CO., LTD.,...

1. A compound represented by the following formula:
wherein, R1 through R10 each are independently selected from the group consisting of a hydrogen atom, a halogen atom, a cyano group, an alkoxy group, a thiol group, a substituted or unsubstituted alkyl group having 1 to 50 carbon atoms, a substituted or unsubstituted alkoxy group having 1 to 50 carbon atoms, a substituted or unsubstituted alkenyl group having 2 to 50 carbon atoms, a substituted or unsubstituted arylene group having 6 to 60 carbon atoms, a substituted or unsubstituted aryl group having 6 to 60 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 60 carbon atoms, a substituted or unsubstituted C1-C50 alkyl group having at least one of sulfur (S), nitrogen (N), oxygen (O), phosphorous (P) and silicon (Si), a substituted or unsubstituted C5-C60 heteroaryl group having at least one heteroatom selected from the group consisting of sulfur (S), nitrogen (N), oxygen (O), phosphorous (P) and silicon (Si), and a substituted or unsubstituted C5-C60 heteroaryloxy group having at least one of sulfur, nitrogen, oxygen, phosphorous and silicon, wherein any of R1 through R10 optionally forms a substituted or unsubstituted, saturated or unsaturated ring together with an adjacent group;
X is at least one selected from sulfur, oxygen or silicon,
n is an integer of 1 to 3,
where n is 1, Y is selected from the group consisting of a hydrogen atom, a halogen atom, a cyano group, an alkoxy group, a thiol group, a substituted or unsubstituted alkyl group having 1 to 50 carbon atoms, a substituted or unsubstituted alkenyl group having 2 to 50 carbon atoms, a substituted or unsubstituted aryl group having 6 to 60 carbon atoms, a substituted or unsubstituted aryloxy group having 6 to 60 carbon atoms, and a substituted or unsubstituted C5-C60 heteroaryl group having at least one heteroatom selected from the group consisting of sulfur, nitrogen, oxygen, phosphorous and silicon, and where n is 2 or 3, Y is a substituted or unsubstituted aryl or arylene group having 6 to 60 carbon atoms, with the proviso that where Y is a substituted aryl or arylene group having 6 to 60 carbon atoms, Y is not substituted with a pyrenyl group or a substituted pyrenyl group, and
wherein a compound represented by the formula wherein R1 to R10 are each hydrogen, X is S, Y is a substituted or unsubstituted C5-C60 heteroaryl group containing nitrogen and n is 1, is excluded, and
wherein a compound represented by the formula wherein R3 and/or R7 are a substituted or unsubstituted C5-C60 heteroaryl group containing at least one of sulfur, nitrogen, oxygen, phosphorous and silicon, is excluded.

US Pat. No. 10,991,889

ORGANIC ELECTROLUMINESCENT COMPOUND AND ORGANIC ELECTROLUMINESCENT DEVICE COMPRISING THE SAME

Rohm and Haas Electronic ...

1. An organic electroluminescent compound represented by the following formula 7:
wherein,
R1 to R3 each independently represent hydrogen, deuterium, halogen, cyano, a substituted or unsubstituted (C1-C30)alkyl, a substituted or unsubstituted (C6-C30)aryl, or a substituted or unsubstituted (5- to 30-membered)heteroaryl, provided that at least two of R1 to R3 each independently represent a substituted or unsubstituted (C1-C30)alkyl, a substituted or unsubstituted (C6-C30)aryl, or a substituted or unsubstituted (5- to 30-membered)heteroaryl;
B1 and B2 each independently represent hydrogen, deuterium, halogen, cyano, a substituted or unsubstituted (C1-C30)alkyl, a substituted or unsubstituted (C6-C30)aryl, a substituted or unsubstituted (5- to 30-membered)heteroaryl, a substituted or unsubstituted (C3-C30)cycloalkyl, a substituted or unsubstituted (C1-C30)alkoxy, a substituted or unsubstituted tri(C1-C30)alkylsilyl, a substituted or unsubstituted di(C1-C30)alkyl(C6-C30)arylsilyl, a substituted or unsubstituted (C1-C30)alkyldi(C6-C30)arylsilyl, a substituted or unsubstituted tri(C6-C30)arylsilyl, a substituted or unsubstituted mono- or di-(C1-C30)alkylamino, a substituted or unsubstituted mono- or di-(C6-C30)arylamino, or a substituted or unsubstituted (C1-C30)alkyl(C6-C30)arylamino;
Ar1 and Ar2 each independently represent halogen, a substituted or unsubstituted (C1-C30)alkyl, a substituted or unsubstituted (C6-C30)aryl, or a substituted or unsubstituted (5- to 30-membered)heteroaryl; or may be linked to an adjacent substituent to form a substituted or unsubstituted (3- to 30-membered) mono- or polycyclic, alicyclic or aromatic ring, or a combination thereof; and
R11 to R14 each independently represent hydrogen, deuterium, halogen, cyano, a substituted or unsubstituted (C1-C30)alkyl, a substituted or unsubstituted (C6-C30)aryl, a substituted or unsubstituted (5- to 30-membered)heteroaryl, a substituted or unsubstituted (C3-C30)cycloalkyl, a substituted or unsubstituted (C1-C30)alkoxy, a substituted or unsubstituted tri(C1-C30)alkylsilyl, a substituted or unsubstituted di(C1-C30)alkyl(C6-C30)arylsilyl, a substituted or unsubstituted (C1-C30)alkyldi(C6-C30)arylsilyl, a substituted or unsubstituted tri(C6-C30)arylsilyl, a substituted or unsubstituted mono- or di-(C1-C30)alkylamino, a substituted or unsubstituted mono- or di-(C6-C30)arylamino, or a substituted or unsubstituted (C1-C30)alkyl(C6-C30)arylamino; or may be linked to an adjacent substituent to form a substituted or unsubstituted (3- to 30-membered) mono- or polycyclic, alicyclic or aromatic ring, or a combination thereof.

US Pat. No. 10,991,888

COMPOUND FOR ORGANIC ELECTRONIC ELEMENT, ORGANIC ELECTRONIC ELEMENT USING THE SAME, AND AN ELECTRONIC DEVICE

DUK SAN NEOLUX CO., LTD.,...

1. An organic electronic element comprising:a first electrode, a second electrode, and an organic layer formed between the first electrode and the second electrode, wherein the organic material layer includes an emitting auxiliary layer formed between the first electrode and the emitting layer, and a hole transport layer formed between the first electrode and the emitting auxiliary layer, wherein the hole transport layer contains a compound represented by the following Formula (1), and the emitting auxiliary layer contains a compound represented by the following Formula (2),

in Formulas (1) and (2), Ar1, Ar2, Ar4, Ar5 and Ar6 are each independently selected from the group consisting of a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group including at least one heteroatom of O, N, S, Si or P; a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50alkyl group; a C2-C20 aklenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxyl group; a C6-C30 aryloxy group; and -L?-N(Ra)(Rb) (where, L? may be selected from the group consisting of a single bond; a C6-C60 arylene group; a fluorenylene group; a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring; and a C2-C60 heterocyclic, and the Ra and Rb may be independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring; and a C2-C60 heterocyclic group containing at least one heteroatom of O, N, S, Si, or P), and
Ar3 is at least one of the Formula (1-a) or Formula (1-b) below,

wherein q, r and s are each an integer of 0 to 4, t is an integer of 0 to 3, and R1, R2, R3, R4 are the same or different, and are each independently selected from the group consisting of deuterium; halogen; a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group including at least one heteroatom of O, N, S, Si or P; a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxyl group; a C6-C30 aryloxy group; and -L?-N(Ra)(Rb) (wherein, L?, Ra and Rb are the same as indicated above), wherein in case q, r and s are each an integer of 2 or more, R1, R2 and R3 are each in plural and are the same or different, and a plurality of R1 or a plurality of R2 or a plurality of R3 or a plurality of R4 may combine to each other to form a ring, and
L4 is selected from the group consisting of a C6-C60 arylene group, and a fluorenylene group; a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring; and a C2-C60 heterocyclic group including at least one heteroatom of O, N, S, Si or P, and
L5 is selected from the group consisting of a single bond; a C6-C60 arylene group; a fluorenylene group; a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring; and a C2-C60 heterocyclic group including at least one heteroatom of O, N, S, Si or P, and
Ar7 is independently selected from the group consisting of a C6-C60 aryl group; a fluorenyl group; a C2-C60 heterocyclic group including at least one heteroatom of O, N, S, Si or P; a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C1-C50 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C1-C30 alkoxyl group; a C6-C30 aryloxy group; and -L?-N(Ra)(Rb) (wherein, L?, Ra and Rb are as defined above), and
L1, L2 and L3 are selected from the group consisting of a single bond; a C6-C60 arylene group; a fluorenylene group; a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring; a C2-C60 heterocyclic group including at least one heteroatom of O, N, S, Si or P,
wherein the aryl group, fluorenyl group, heterocyclic group, fused ring group, alkyl group, alkenyl group, alkynyl group, alkoxyl group, aryloxy group, arylene group and fluorenylene group may be substituted with one or more substituents selected from the group consisting of deuterium; halogen; a silane group; a siloxane group; boron group; a germanium group; a cyano group; a nitro group; -L?-N(Ra)(Rb); a C1-C20 alkylthio group; a C1-C20 alkoxyl group; a C1-C20 alkyl group; a C2-C20 alkenyl group; a C2-C20 alkynyl group; a C6-C60 aryl group; a C6-C60 aryl group substituted with deuterium; a fluorenyl group; a C2-C20 heterocyclic group; a C3-C20 cycloalkyl group; a C7-C20 arylalkyl group; and a C8-C20 arylalkenyl group, wherein the substituents may combine each other to form a saturated or unsaturated ring selected from the group consisting of a C3-C60 aliphatic ring, a C6-C60 aromatic ring, a C2-C60 heterocyclic ring, and a fused ring formed by the combination thereof.

US Pat. No. 10,991,887

AMINE COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE COMPRISING SAME

LG Chem, Ltd.

1. A compound of the following Chemical Formula 2:
in Chemical Formula 2,
Ar1 to Ar4 are the same as or different from each other, and are each independently a substituted or unsubstituted aryl group or a substituted or unsubstituted heterocyclic group, or Ar1 and Ar2 are linked to each other by E1, or Ar3 and Ar4 are linked to each other by E2,
E1 and E2 are the same as or different from each other, and are each independently a direct bond, CRR?, NR, O, or S,
L1 and L2 are the same as or different from each other, and are each independently a direct bond, or a substituted or unsubstituted arylene or a substituted or unsubstituted heteroarylene, n and m are the same as or different from each other, and are each an integer of 0 to 3, and
R? are the same as or different from each other, and are each independently hydrogen; deuterium; a halogen group; a nitrile group; a substituted or unsubstituted alkyl group; a substituted or unsubstituted cycloalkyl group; a substituted or unsubstituted alkoxy group; a substituted or unsubstituted aryloxy group; a substituted or unsubstituted aralkyl group; a substituted or unsubstituted aralkenyl group; a substituted or unsubstituted alkylaryl group; a substituted or unsubstituted aryl group; or a substituted or unsubstituted heterocyclic group, and p and q are the same as or different from each other, and are each an integer of 0 to 7,
wherein at least one of Ar1 to Ar4 is an unsubstituted phenyl, or at least one of Ar1 and Ar2, or Ar3 and Ar4 are bonded to each other through CRR?, NR, S, or O, and R and R? are each independently a substituted or unsubstituted alkyl group.

US Pat. No. 10,991,886

AMINE-BASED COMPOUND AND ORGANIC LIGHT EMITTING DEVICE COMPRISING SAME

LG Chem, Ltd.

1. A compound represented by any one of the following Chemical Formulae 4 to 6:
in Chemical Formulae 4 to 6,
L1 and L2 are a direct bond,
R1 to R5 are hydrogen,
the
moiety is represented by any one selected from the following structures:
wherein B1 is deuterium; a halogen group; a nitrile group; an alkyl group having 1 to 6 carbon atoms; or a silyl group substituted with an alkyl group having 1 to 6 carbon atoms,
B2 and B3 are the same as or different from each other and are each independently an alkyl group having 1 to 6 carbon atoms,
a and b are an integer of 4,
c is an integer of 3,
d is an integer of 7,
e is an integer of 8,
f is an integer of 1, 2 or 5, and
p and q are an integer of 1.

US Pat. No. 10,991,885

COMPOUND FOR ORGANIC ELECTRONIC ELEMENT, ORGANIC ELECTRONIC ELEMENT USING THE SAME AND ELECTRONIC DEVICE THEREOF

DUK SAN NEOLUX CO., LTD.,...

1. A compound of Formula (1):
wherein R1 to R10 are independently selected from the group consisting of hydrogen, deuterium, halogen, a C6 to C60 aryl group, a fluorenyl group, a fused ring group of a C3 to C60 aliphatic ring and a C6 to C60 aromatic ring, a C2 to C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, -L-N(R?)(R?), a C1 to C50 alkyl group, a C2 to C20 alkenyl group, a C1 to C30 alkoxy group, and a C6 to C30 aryloxy group; and any two adjacent groups of R1 to R10 are optionally linked together to form a fused ring,
with the proviso that: (a) where R5 and R6 do not form a ring with each other, at least one of R1 to R4 is not hydrogen and at least one of R7 to R10 is not hydrogen; (b) where R5 and R6 form a ring with each other, either i) at least one of R1 to R4 is not hydrogen and at least one of R7 to R10 is not hydrogen, or ii) L-Ar1 is a C7-C60 heterocyclic group containing pyridopyrimidine moiety in the compound; and (c) none of R2, R8 and R9 is a polyheterocyclic group containing N or O,
X and Y are independently S, O, or SiR31R32, wherein R31 and R32 are independently hydrogen, a C6 to C60 aryl group, a C2 to C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, or a C1 to C50 alkyl group, and m and n are each 0 or 1 with the proviso that m+n is an integer equal to or greater than 1;
L is selected from the group consisting of a single bond; a C6 to C60 arylene group; a fluorenyl group; a C2 to C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; and a bivalent aliphatic hydrocarbon group, wherein, the arylene group, the fluorenyl group, the heterocyclic group, and the aliphatic hydrocarbon group are optionally substituted by one or more substituents selected from the group consisting of a nitro group, a cyano group, a halogen group, a C1 to C20 alkyl group, a C6 to C20 aryl group, a C2 to C20 heterocyclic group, a C1 to C20 alkoxy group, and an amino group;
Ar1 is a C2 to C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C6 to C60 aryl group, a fluorenyl group, or —N(R?)(R?); and
R? and R? are independently a C2 to C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C6 to C60 aryl group, or a fluorenyl group, wherein R? and R? do not form a fused ring with each other or with any adjacent group or ring;
where R1 to R10, Ar1, R?, and R? are an aryl group, R1 to R10, Ar1, R?, and R? are optionally substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a boron group, a germanium group, a cyano group, a nitro group, a C1 to C20 alkylthio group, a C1 to C20 alkoxy group, a C1 to C20 alkyl group, a C2 to C20 alkenyl group, a C2 to C20 alkynyl group, a C6 to C20 aryl group, a C6 to C20 aryl group substituted by deuterium, a C2 to C20 heterocyclic group, a C3 to C20 cycloalkyl group, a C7 to C20 arylalkyl group, and a C8 to C20 arylalkenyl group;
where R1 to R4 and R7 to R10 are heterocyclic group, R1 to R4 and R7 to R10 are optionally substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a cyano group, a nitro group, a C1 to C20 alkoxy group, a C1 to C20 alkyl group, a C2 to C20 alkenyl group, a C2 to C20 heterocyclic group, a C3 to C20 cycloalkyl group, a C7 to C20 arylalkyl group, and a C8 to C20 arylalkenyl group;
where R5, R6, Ar1, R?, and R? are an heterocyclic group, R5, R6, Ar1, R?, and R? are optionally substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a cyano group, a nitro group, a C1 to C20 alkoxy group, a C1 to C20 alkyl group, a C2 to C20 alkenyl group, a C6 to C20 aryl group, a C6 to C20 aryl group substituted by deuterium, a C2 to C20 heterocyclic group, a C3 to C20 cycloalkyl group, a C7 to C20 arylalkyl group, and a C8 to C20 arylalkenyl group;
where R1 to R10, Ar1, R?, and R? are a fluorenyl group, R1 to R10, Ar1, R?, and R? are optionally substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a cyano group, a C1 to C20 alkyl group, a C2 to C20 alkenyl group, a C6 to C20 aryl group, a C6 to C20 aryl group substituted by deuterium, a C2 to C20 heterocyclic group, and a C3 to C20 cycloalkyl group;
where R1 to R10 are a fused ring group, R1 to R10 are optionally substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a boron group, a germanium group, a cyano group, a nitro group, a C1 to C20 alkylthio group, a C1 to C20 alkoxy group, a C1 to C20 alkyl group, a C2 to C20 alkenyl group, a C2 to C20 alkynyl group, a C6 to C20 aryl group, a C6 to C20 aryl group substituted by deuterium, a C2 to C20 heterocyclic group, a C3 to C20 cycloalkyl group, a C7 to C20 arylalkyl group, and a C8 to C20 arylalkenyl group;
where R1 to R10 are an alkyl group, R1 to R10 are optionally substituted by one or more substituents selected from the group consisting of halogen, a silane group, a boron group, a cyano group, a C1 to C20 alkoxy group, a C1 to C20 alkyl group, a C2 to C20 alkenyl group, a C6 to C20 aryl group, a C6 to C20 aryl group substituted by deuterium, a C2 to C20 heterocyclic group, a C7 to C20 arylalkyl group, and a C8 to C20 arylalkenyl group;
where R1 to R10 are an alkenyl group, R1 to R10 are optionally substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a cyano group, a C1 to C20 alkoxy group, a C1 to C20 alkyl group, a C2 to C20 alkenyl group, a C6 to C20 aryl group, a C6 to C20 aryl group substituted by deuterium, a C2 to C20 heterocyclic group, a C3 to C20 cycloalkyl group, a C7 to C20 arylalkyl group, and a C8 to C20 arylalkenyl group;
where R1 to R10 are an alkoxy group, R1 to R10 are optionally substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a C1 to C20 alkyl group, a C6 to C20 aryl group, a C6 to C20 aryl group substituted by deuterium, a C2 to C20 heterocyclic group, and a C3 to C20 cycloalkyl group; and
where R1 to R10 are an aryloxy group, R1 to R10 are optionally substituted by one or more substituents selected from the group consisting of deuterium, a silane group, a cyano group, a C1 to C20 alkyl group, a C6 to C20 aryl group, a C6 to C20 aryl group substituted by deuterium, a C2 to C20 heterocyclic group, and a C3 to C20 cycloalkyl group.

US Pat. No. 10,991,884

MASK PLATE, OLED DISPLAY SUBSTRATE, DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

CHENGDU BOE OPTOELECTRONI...

1. A mask plate for manufacturing an organic electroluminescent light-emitting diode OLED display substrate, comprising:a mask plate body provided with a plurality of openings arranged in a matrix;
a first blocking wall arranged on a surface of the mask plate body facing the OLED display substrate, wherein the first blocking wall is proximate to the plurality of openings, and at least a portion of the first blocking wall is between two adjacent rows or adjacent columns of openings,
wherein an orthographic projection of the first blocking wall onto the mask plate body partially overlaps the mask plate body.

US Pat. No. 10,991,883

DEPOSITION MASK, METHOD OF MANUFACTURING DEPOSITION MASK DEVICE, AND METHOD OF MANUFACTURING DEPOSITION MASK

Dai Nippon Printing Co., ...

1. A deposition mask extending in a first direction, the deposition mask comprising:a central axis line extending in the first direction and arranged at a central position in a second direction orthogonal to the first direction;
a point P1 and a point Q1 provided on one side of the central axis line and spaced apart from each other along the first direction;
a point P2 and a point Q2 provided on the other side of the central axis line and spaced apart from each other along the first direction,
wherein the point P1 and the point P2 are arranged to be symmetric with each other with respect to the central axis line during deposition, and
the point Q1 and the point Q2 are arranged to be symmetric with each other with respect to the central axis line during deposition, and
when a dimension from the point P1 to the point Q1 is X1, a dimension from the point P2 to the point Q2 is X2, and a design value is ?x, the deposition mask satisfies the following,

wherein
the deposition mask comprises:
a first ear portion and a second ear portion that form a pair of end portions in the first direction;
through-holes provided between the first ear portion and the second ear portion; and
a first edge and a second side edge that form a pair of side edges in a second direction perpendicular to the first direction,
wherein
the point P1 and the point P2 are formed on a side closest to the first ear portion and are positioned at center points of corresponding through-holes,
the point Q1 and the points Q2 are formed on a side closest to the second ear portion and are positioned at center points of corresponding through-holes,
the through-holes corresponding to the point P1 and the point Q1 are formed on a side closest to the first side edge, and
the through-holes corresponding to the point P2 and point Q2 are formed on a side closest to the second side edge.

US Pat. No. 10,991,882

METHODS OF FORMING RESISTIVE MEMORY ELEMENTS

Micron Technology, Inc., ...

1. A method of forming a resistive memory element, comprising:forming a switchable resistivity material over an electrode, the switchable resistivity material comprising one or more of a metal oxide and a chalcogenide;
forming a buffer material over the switchable resistivity material, the buffer material comprising:
a crystalline material comprising longitudinally extending, columnar grains of one or more of TiNx, TaNx, WNx, TiNxCy, TaNxCy, WNxCy, TiNxBy, TaNxBy, WNxBy, TiNxSiy, TaNxSiy, and WNxSiy; and
an electrolyte material comprising elemental Te within interstitial spaces between the longitudinally extending, columnar grains of the crystalline material;
forming a material over the buffer material, the material comprising a chalcogen and one or more of Cu, Ag, and Al; and
forming another electrode over the material.

US Pat. No. 10,991,881

METHOD FOR CONTROLLING THE FORMING VOLTAGE IN RESISTIVE RANDOM ACCESS MEMORY DEVICES

Tokyo Electron Limited, ...

1. A method of forming a resistive random access memory (ReRAM) device, the method comprising:depositing a dielectric film containing intrinsic defects on a substrate;
forming a plasma-excited treatment gas containing H2 gas;
exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film;
following the exposing the dielectric film to the plasma-excited treatment gas, depositing an additional dielectric film on the dielectric film; and
exposing the additional dielectric film to additional plasma-excited treatment gas containing H2 gas to create additional defects in the additional dielectric film.

US Pat. No. 10,991,880

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A variable resistance at emory device, comprising:a substrate;
a first conductive line disposed on the substrate and extending primarily in a first direction;
a second conductive line disposed on the substrate and extending primarily in a second direction, the second direction intersecting the first direction;
a phase change pattern disposed between the first conductive line and the second conductive line;
a bottom electrode disposed between the phase change pattern and the first conductive line; and
a spacer disposed on the bottom electrode,
wherein the bottom electrode comprises a first sidewall segment that connects the first conductive line and the phase change pattern to each other,
wherein the spacer comprises a second sidewall segment that contacts the phase change pattern and the bottom electrode,
wherein the phase change pattern has a curved bottom surface;having a width in the first direction that decreases toward the substrate,
wherein the first sidewall segment has a first lateral surface and a second lateral surface that face each other,
wherein the lowermost portion of the phase change pattern is disposed between the first lateral surface and the second lateral surface,
wherein the first sidewall segment further comprises a first curved top surface contacting the bottom surface of phase change pattern,
wherein the second side wall segment comprises a second curved top surface contacting the bottom surface of phase change pattern, and
wherein a contact area of the first top surface of first sidewall segment is smaller than a contact area of the second top surface of the second sidewall segment.

US Pat. No. 10,991,879

MULTI-LEVEL PHASE CHANGE MEMORY CELLS AND METHOD OF MAKING THE SAME

WESTERN DIGITAL TECHNOLOG...

1. A memory device comprising at least one phase change memory cell, wherein the at least one phase change memory cell comprises:a first electrode located over a substrate;
a second electrode located over the first electrode;
a pillar structure located between the first and second electrodes and extending along a vertical direction perpendicular to the substrate, the pillar structure comprising a first phase change memory (PCM) material portion, a second PCM material portion and an intermediate electrode located between the first PCM material portion and the second PCM material portion; and
a resistive liner comprising a first segment electrically connected in parallel to the first PCM material portion between the first electrode and the intermediate electrode, and a second segment electrically connected in parallel to the second PCM material portion between the intermediate electrode and the second electrode;
wherein:
the first PCM material portion has a different electrical resistance than the second PCM material portion; and
the first segment of the resistive liner has a different electrical resistance than the second segment of the resistive liner;
the electrical resistance along the vertical direction of a crystalline state of the second PCM material portion is x times the electrical resistance along the vertical direction of a crystalline state of the first PCM material portion, and x is greater than 1;
the electrical resistance along the vertical direction of the first segment of the resistive liner is y times the electrical resistance along the vertical direction of the crystalline state of the first PCM material portion;
y is greater than x, such that electrical resistance along the vertical direction of the first segment of the resistive liner is greater than the electrical resistance of the crystalline state of the second PCM material portion; and
the electrical resistance along the vertical direction of the second segment of the resistive liner is greater than the electrical resistance along the vertical direction of the first segment of the resistive liner.

US Pat. No. 10,991,878

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A manufacturing method of a semiconductor device, comprising:forming a first inter-metal dielectric (IMD) layer on a substrate;
forming a cap layer on the first IMD layer;
forming a connection structure on the substrate, wherein the connection structure penetrates the cap layer and the first IMD layer;
forming a magnetic tunnel junction (MTJ) stack on the connection structure and the cap layer;
performing a patterning process to the MTJ stack for forming a MTJ structure on the connection structure, wherein the cap layer is completely removed by the patterning process; and
forming a second IMD layer on the first IMD layer, wherein the second IMD layer surrounds the MTJ structure, and the second IMD layer directly contacts the first IMD layer.

US Pat. No. 10,991,877

MULTI-STATE MEMORY AND METHOD FOR MANUFACTURING THE SAME

Institute of Microelectro...

1. A method for manufacturing a multi-state memory, comprising:providing a substrate;
forming a spin-orbit coupling layer on the substrate;
forming a magnetoresistive tunnel junction on the spin-orbit coupling layer, wherein the magnetoresistive tunnel junction comprises a first magnetic layer, a tunneling layer and a second magnetic layer that are sequentially stacked from bottom to top, and the first magnetic layer and the second magnetic have perpendicular anisotropy;
injecting dopant ions from a side of the magnetoresistive tunnel junction; and
performing thermal annealing;
wherein injecting the dopant ions from a side of the magnetoresistive tunnel junction comprises:
injecting the dopant ions to the magnetoresistive tunnel junction that is exposed, wherein there is an angle between a direction of the injecting and a direction perpendicular to the substrate, a projection of the direction of the injecting on the substrate is non-parallel to a direction of a current in the spin-orbit coupling layer.

US Pat. No. 10,991,876

METHODS TO IMPROVE MAGNETIC TUNNEL JUNCTION MEMORY CELLS BY TREATING NATIVE OXIDE

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor structure, the method comprising:forming a bottom electrode layer, wherein a dielectric layer overlies the bottom electrode layer;
performing a treatment to reduce the dielectric layer on the bottom electrode layer;
after performing the treatment, forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;
forming a top electrode layer over the MTJ layer;
patterning the top electrode layer, the MTJ layer, and the bottom electrode layer to form a magnetic random access memory (MRAM) cell;
after patterning, forming a dielectric spacer over the MRAM cell; and
etching the dielectric spacer, the etching exposing a side portion of the top electrode layer.

US Pat. No. 10,991,875

MAGNETORESISTIVE RANDOM ACCESS MEMORY

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate having a magnetic tunneling junction (MTJ) region and a logic region;
an inter-metal dielectric (IMD) layer on the substrate;
a MTJ in the IMD layer on the MTJ region;
a first metal interconnection in the IMD layer on the logic region; and
protrusions adjacent to two sides of the first metal interconnection, wherein a top surface of the protrusions is lower than a bottom surface of the MTJ.

US Pat. No. 10,991,874

MAGNETO-IONIC DEVICE WITH A SOLID STATE PROTON PUMP AND METHODS FOR USING THE SAME

Massachusetts Institute o...

1. A magneto-ionic device, comprising:a first electrode;
a second electrode;
a magnetic layer disposed between the first electrode and the second electrode; and
a proton conductor disposed between the magnetic layer and the second electrode,
wherein a first gate voltage applied to the first electrode and the second electrode transports protons from the second electrode through the proton conductor toward the magnetic layer where a first portion of the protons are reduced to hydrogen, the hydrogen and a second portion of the protons causing the magnetic layer to switch from a first magnetic state to a second magnetic state.

US Pat. No. 10,991,873

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a first inter-metal dielectric (IMD) layer on a substrate;
a first metal interconnection in the first IMD layer;
a magnetic tunneling junction (MTJ) on the first metal interconnection, wherein the MTJ comprises:
a bottom electrode;
a fixed layer; and
a top electrode, comprising:
a bottom portion on the MTJ, wherein a sidewall of the bottom portion is aligned with a sidewall of the MTJ; and
a top portion on the bottom portion, wherein a width of a top surface of the bottom portion is less than a width of a top surface of the top portion and the top surface of the bottom portion contacts a bottom surface of the top portion directly;
a second IMD layer on the first IMD layer and around the MTJ; and
a liner on the second IMD layer and around the top portion of the top electrode, wherein a top surface of the top portion is even with a top surface of the liner.

US Pat. No. 10,991,872

BULK ACOUSTIC WAVE RESONATOR

Samsung Electronics Co., ...

1. A bulk acoustic wave resonator (BAWR), comprising:an air cavity;
a bulk acoustic wave resonant unit comprising a first electrode disposed on the air cavity, a second electrode disposed on the first electrode, and a piezoelectric layer disposed between the first electrode and the second electrode;
a first reflective layer disposed between the air cavity and the first electrode;
a second reflective layer disposed between the first reflective layer and the air cavity;
a third reflective layer disposed on the second electrode such that the second electrode is disposed between the third reflective layer and the piezoelectric layer; and
a fourth reflective layer disposed on the third reflective layer such that the third reflective layer is disposed between the fourth reflective layer and the second electrode,
wherein an acoustic impedance of the second reflective layer is different from an acoustic impedance of the first reflective layer,
wherein an acoustic impedance of the fourth reflective layer is different from an acoustic impedance of the third reflective layer,
wherein the first reflective layer comprises at least one material to compensate for a temperature coefficient of frequency (TCF) of the bulk acoustic wave resonant unit, and
wherein the first electrode is formed in direct contact with a first surface of the first reflective layer.

US Pat. No. 10,991,871

PIEZOELECTRIC ELEMENT, PIEZOELECTRIC ACTUATOR, ULTRASONIC PROBE, ULTRASONIC DEVICE, ELECTRONIC APPARATUS, LIQUID JET HEAD, AND LIQUID JET DEVICE

Seiko Epson Corporation

1. A piezoelectric element comprising:a piezoelectric element main body having a first electrode layer, a piezoelectric layer disposed on the first electrode layer, and a second electrode layer disposed on the piezoelectric layer; and
a metal layer disposed on the second electrode layer via an insulating layer such that an entirety of the metal layer is spaced apart from the second electrode,
wherein the piezoelectric layer has an extending part extending from the piezoelectric element main body beyond an outer peripheral edge of the second electrode layer in a plan view,
the metal layer extends outward from the outer peripheral edge of the second electrode such that metal layer overlaps the extending part of the piezoelectric layer in the plan view.

US Pat. No. 10,991,870

METHOD OF PRODUCTION OF THERMOELECTRIC MICRO-COOLERS (VARIANTS)

RMT LIMITED, Nizhniy Nov...

1. A method of production of a thermoelectric micro-cooler, comprisingforming on a first ceramic wafer a first conductive layer containing conductive traces,
soldering legs of thermoelectric material to the conductive traces of the first conductive layer,
forming on a temporary wafer a second conductive layer containing conductive traces,
soldering the conductive traces of the second conductive layer to legs of thermoelectric material,
applying a protective coating onto the legs of thermoelectric material and soldered joints,
removing the temporary wafer,
applying an elastic heat-conductive adhesive layer onto a second ceramic wafer,
adhering the second ceramic wafer to the conductive traces of the second conductive layer.

US Pat. No. 10,991,869

THERMOELECTRIC DEVICE HAVING A PLURALITY OF SEALING MATERIALS

GENTHERM INCORPORATED, N...

1. A thermoelectric device comprising:a thermally conductive first plate comprising at least one hole extending through the first plate; and
at least one thermoelectric sub-assembly comprising:
a thermally conductive second plate displaced from the at least one hole in a direction parallel to the first plate such that the second plate does not extend over the at least one hole along the direction parallel to the first plate;
a plurality of thermoelectric elements in a region between the first plate and the second plate, the plurality of thermoelectric elements in thermal communication with the first plate and the second plate via a plurality of shunts positioned on the first and second plates;
a first material along a first portion of a perimeter of the region, the first material in mechanical communication with the first plate and the second plate, the first material having a first stiffness; and
a second material along a second portion of the perimeter of the region, the second material in mechanical communication with the first plate and the second plate, the second material having a second stiffness less than the first stiffness.

US Pat. No. 10,991,868

THERMOELECTRIC CONVERSION ELEMENT

FUJIFILM Corporation, To...

1. A thermoelectric conversion element comprising:a p-type thermoelectric conversion layer; and
an n-type thermoelectric conversion layer electrically connected to the p-type thermoelectric conversion layer,
wherein the p-type thermoelectric conversion layer contains a nanocarbon material and at least one kind of component selected from the group consisting of an onium salt and an inorganic salt,
the n-type thermoelectric conversion layer contains a nanocarbon material and an onium salt, and
a difference between an ionization potential of the p-type thermoelectric conversion layer and an ionization potential of the n-type thermoelectric conversion layer is equal to or smaller than 0.15 eV,
the onium salt contained in the n-type thermoelectric conversion layer being an onium salt represented by Formula (2),

where in Formula (2),
Z21 represents a nitrogen atom, a phosphorus atom, a sulfur atom, or an oxygen atom,
in a case where Z21 is a nitrogen atom or a phosphorus atom, r is 1, and in a case where Z21 is a sulfur atom or an oxygen atom, r is 0,
X21? represents an anion whose conjugate acid has a pKa of ?10 to ?3,
R51 to R54 each independently represents a hydrogen atom or an organic group selected from the group consisting of a hydrocarbon group which may contain a heteroatom, a heterocyclic group, and a group obtained by combining two or more of these groups, and
in a case where the pKa of the conjugate acid of the anion represented by X21? is ?10 to ?3.7, at least three groups among R51 to R54 are organic groups each having 8 or more carbon atoms.

US Pat. No. 10,991,867

HIGH-PERFORMANCE TERBIUM-BASED THERMOELECTRIC MATERIALS

University of Utah Resear...

1. A thermoelectric material, comprising a material having formula (I)TbxM1y-xM2zOw  (I)
where M1 is one of Ca, Mg, Sr, Ba and Ra, M2 is at least one of Co, Fe, Ni, and Mn, x ranges from 0.01 to 5; y is 1, 2, 3, or 5; z is 1, 2, 3, or 4; and w is 1, 2, 3, 4, 5, 7, 8, 9, or 14;
wherein the material includes Tb having an oxidation state of Tb3+, Tb4+, and Tb9+; and
wherein the material is air stable within 5% mass for one year and is non-toxic.

US Pat. No. 10,991,866

LIGHT EMITTING MODULE

Toshiba Hokuto Electronic...

1. A light emitting module comprising:a first insulation film with a light transmissivity;
a second insulation film with a light transmissivity disposed to face the first insulating film;
a first double sided light emitting element disposed between the first insulating film and the second insulating film, and having a pair of electrodes on one surface of the first double sided light emitting element;
a second double sided light emitting element disposed between the first insulating film and the second insulating film, and having a pair of electrodes on one surface of the second double sided light emitting element, said second double sided light emitting element disposed adjacent to said first double sided light emitting element;
at least a first conducting area and a second conducting area formed on said first insulating film,
said first conducting area connecting a first electrode of said first double sided light emitting element and a first electrode of said second double sided light emitting element as a common pattern, the common pattern having one common end,
said second conducting area having a first individual conducting pattern connected to a second electrode of said first double sided light emitting element, and having a second individual conducting pattern connected to a second electrode of said second double sided light emitting element, the first individual conducting pattern and the second individual conducting pattern each having an individual end.

US Pat. No. 10,991,865

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate; a plurality of pixels disposed on the substrate;
an electrode part including a first electrode in each pixel of the plurality of pixels on the substrate and a second electrode spaced apart from the first electrode on a same plane;
a plurality of light emitting devices spaced apart from each other between the first electrode and the second electrode;
a power line part including a first power line between the substrate and the first electrode, the first power line to receive a first driving power source, and a second power line between the substrate and the second electrode, the second power line to receive a second driving power source; and
a shielding electrode line between the power line part and the first electrode, the shielding electrode line to receive the first driving power source.

US Pat. No. 10,991,864

LED PACKAGE AND LED DISPLAY DEVICE

ROHM CO., LTD., Kyoto (J...

1. An LED package, comprising:a substrate having a front surface and a back surface that are spaced apart from each other in a thickness direction, wherein
the substrate has a first side surface and a first recess, the first side surface facing in a first direction perpendicular to the thickness direction and being connected to the front surface and the back surface, the first recess being recessed from the first side surface and extending from the front surface to the back surface;
a first wiring and a second wiring arranged on the substrate;
an LED chip mounted on the front surface and electrically connected to the first wiring and the second wiring, wherein
the first wiring includes a first connecting portion and a first terminal portion, the first connecting portion being arranged on the front surface and electrically connected to the LED chip, the first terminal portion being connected to the first connecting portion, and
the first terminal portion is in contact with the front surface and the first recess; and
a sealing resin covering the LED chip, wherein
the substrate comprises a plurality of glass cloths laminated in the thickness direction and an impregnated resin impregnated in the plurality of glass cloths,
the impregnated resin comprises acrylic resin, and
the sealing resin comprises silicone.

US Pat. No. 10,991,861

LOW OPTICAL LOSS FLIP CHIP SOLID STATE LIGHTING DEVICE

Cree, Inc., Durham, NC (...

1. A light emitting device comprising a flip chip light emitting diode, the flip chip light emitting diode comprising:a plurality of semiconductor layers including a first semiconductor layer comprising doping of a first type and a second semiconductor layer comprising doping of a second type, wherein a light emitting active region is arranged between the first semiconductor layer and the second semiconductor layer;
a multi-layer reflector arranged proximate to the plurality of semiconductor layers, the multi-layer reflector comprising a metal reflector layer and a dielectric reflector layer, wherein the dielectric reflector layer is arranged between the metal reflector layer and the plurality of semiconductor layers;
a passivation layer arranged between the metal reflector layer and (i) a first electrical contact and (ii) a second electrical contact, wherein the first electrical contact is arranged in conductive electrical communication with the first semiconductor layer, and the second electrical contact is arranged in conductive electrical communication with the second semiconductor layer; and
an adhesion layer between the metal reflector layer and the dielectric reflector layer;
wherein the plurality of semiconductor layers forms a mesa; a peripheral portion of each of the first semiconductor layer, the light emitting active region, and the second semiconductor layer forms a sidewall of at least one recess laterally bounding the mesa; the mesa has a major surface bounded by the sidewall; the multi-layer reflector is arranged over at least 90% of the major surface of the mesa and is arranged between the mesa and the passivation layer; and the at least one recess comprises a peripheral portion of the dielectric reflector layer that bounds respective peripheral portions of the second semiconductor layer, the light emitting active region, and a segment of the first semiconductor layer.

US Pat. No. 10,991,860

LIGHT GUIDE WITH PATTERNED INK

Lumileds LLC, San Jose, ...

1. A light-emitting system, comprising:a light guide configured to guide light received from a light source;
a first light extraction element positioned on a first surface of the light guide and configured to extract a portion of the guided light from the light guide, the first light extraction element having a first reflectance and a first transmittance; and
a second light extraction element positioned on the first surface of the light guide and configured to extract a portion of the guided light from the light guide, the second light extraction element having a second reflectance different from the first reflectance, the second light extraction element having a second transmittance different from the first transmittance.

US Pat. No. 10,991,858

LIGHT-EMITTING DIODE WITH LIGHT EXTRACTING STRUCTURE

FACEBOOK TECHNOLOGIES, LL...

1. A light-emitting diode (LED) comprising:a semiconductor junction for emitting light upon application of electric current, the semiconductor junction comprising positive (p) and negative (n) regions; and
a structured metamaterial layer coupled to the semiconductor junction and supported by one of the p- or n-regions, the structured metamaterial layer comprising an optical surface for outputting at least a portion of the light emitted by the semiconductor junction, the structured metamaterial layer comprising at least one of: an array of tilted features having parallel sidewalls extending from the optical surface at an acute angle thereto; or an array of tilted voids having parallel sidewalls extending into the optical surface at an acute angle thereto, and configured to increase the portion of the light outputted by the optical surface.

US Pat. No. 10,991,856

LED WITH STRUCTURED LAYERS AND NANOPHOSPHORS

Lumileds LLC, San Jose, ...

1. A device comprising:a light emitting diode (LED); and
a meta-molecule wavelength converting layer positioned within an emitted light path from the LED, the meta-molecule wavelength converting layer including a plurality of meta-molecules, the meta-molecules comprising one or more nanoparticles and one or more converter nanoparticles such that:
the one or more nanoparticles is a plurality of core-shell metal or dielectric nanoparticles each comprising a different material in a core than in a shell and the one or more converter nanoparticles is a converter nanoparticle, and the core-shell metal or dielectric nanoparticles surround the converter nanoparticle such that the core-shell metal or dielectric nanoparticles are resonance tuned with the converter nanoparticle; or
the one or more nanoparticles is a core-shell metal or dielectric nanoparticle comprising a different material in the core than in the shell and the one or more converter nanoparticles is a plurality of converter nanoparticles, and the core-shell metal or dielectric nanoparticle is surrounded by the converter nanoparticles such that the core-shell metal or dielectric nanoparticle is resonance tuned with the converter nanoparticles; and
the one or more nanoparticles are resonance tuned with the one or more converter nanoparticles such that they affect interaction of the one or more converter nanoparticles with one or both of light emitted by the LED and light emitted by the one or more converter nanoparticles.

US Pat. No. 10,991,855

WHITE LIGHT EMITTING DEVICE

Lextar Electronics Corpor...

1. A white light emitting device for emitting a white light close to a natural light, comprising:a blue LED chip configured to emit a light having a dominant emission wavelength of about 440-465 nm;
a phosphor layer configured to be excited by the light having the dominant emission wavelength of the blue LED chip, the phosphor layer comprising:
a blue-green phosphor having a peak emission wavelength of about 480-519 nm;
a green phosphor having a peak emission wavelength of about 520-560 nm; and
a red phosphor having a peak emission wavelength of about 620-670 nm,
wherein the blue-green phosphor and the green phosphor both have a garnet structure represented by A3B5O12:Ce, A is selected from the group consisting of Y, Lu, and a combination of thereof, and B is selected from the group consisting of Al, Ga and a combination of thereof,
a substrate having an upper surface, wherein the blue LED chip is disposed on the upper surface of the substrate;
a transparent cover layer disposed on the phosphor layer, wherein the cover layer has a top surface, a bottom surface, and a side surface between the top and bottom surfaces; and
a reflective wall disposed on the upper surface of the substrate, wherein the reflective wall reflects the light emitted from the blue LED chip and light emitted by the phosphor layer;
wherein the reflective wall has an inner surface with an inclined portion which is inclined to the upper surface of the substrate, and a straight portion which is substantially vertical to the upper surface of the substrate;
wherein the inclined portion of the inner surface of the reflective wall surrounds and directly contacts the phosphor layer, and surrounds the blue LED chip while being spaced apart from the blue LED chip; and
wherein the straight portion of the inner surface of the reflective wall surrounds and directly contacts the side surface of the cover layer,
wherein the white light emitting device has a Color Fidelity Index (Rf) that is greater than 93, a Color Gamut Index (Rg) that ranges from 99 to 130, a color rendering index (CRI) that is greater than 95 at correlated color temperature (CCT) of 2700-6500K, and R1-R15 that is respectively greater than 90.

US Pat. No. 10,991,854

LIGHT-EMITTING ELEMENT WITH CRACK PREVENTING CUSHION

EPISTAR CORPORATION, Hsi...

1. A light-emitting element comprises:a semiconductor light-emitting stack comprising a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed therebetween;
a first conductive layer disposed on the second semiconductor layer and electrically connecting the second semiconductor layer;
a second conductive layer disposed on the second semiconductor layer and electrically connecting the first semiconductor layer; and
a cushion part disposed on and directly contacts the first conductive layer,
wherein the cushion part is surrounded by and electrically isolated from the second conductive layer, and the cushion part electrically connects to the first conductive layer.

US Pat. No. 10,991,853

CARRIER FOR AN OPTOELECTRONIC COMPONENT, METHOD OF PRODUCING A CARRIER FOR AN OPTOELECTRONIC COMPONENT, WAFER AND SOLDERING METHOD

OSRAM OLED GmbH, Regensb...

1. A carrier for an optoelectronic component comprising:a main body,
wherein the main body comprises a first electrically conductive heating layer arrangement,
a first solder layer for soldering an optoelectronic component to the main body is arranged on a first side of the main body,
the first electrically conductive heating layer arrangement is electrically insulated from the first solder layer and thermally connected to the first solder layer,
the first heating layer arrangement has an exposed portion on which molten solder of the first solder layer can flow to reduce an electrical resistance of the first heating layer arrangement,
the first heating layer arrangement has a first electrical contacting portion, a second electrical contacting portion and a heating portion extending between the first solder layer and the first side, and the heating portion of the first heating layer arrangement is electrically contacted by the two electrical contacting portions of the first heating layer arrangement, and
the heating portion of the first heating layer arrangement has a two-dimensional coil structure.

US Pat. No. 10,991,852

TRANSPARENT LIGHT-EMITTING DISPLAY FILM, METHOD OF MANUFACTURING THE SAME, AND TRANSPARENT LIGHT-EMITTING SIGNAGE USING THE SAME

JMICRO INC., Daejeon (KR...

1. A transparent light-emitting display film, comprising:A transparent substrate in a form of flexible film, the transparent substrate forming an electrode pattern groove on a first side of the transparent substrate;
a transparent electrode on the first side of the transparent substrate, the transparent electrode formed in the electrode pattern groove and including a first transparent electrode and a second transparent electrode on the first side;
a through hole formed to penetrate through the transparent substrate in a direction perpendicular to the first side of the transparent substrate;
a light-emitting device including a first device electrode and a second device electrode on a first side thereof, the light-emitting device mounted in the through hole in a manner that the first side of the light-emitting device on which the first device electrode and the second device electrode are provided and the first side of the transparent substrate are substantially level;
a first connection member configured to electrically connect the first transparent electrode and the first device electrode of the light-emitting device; and
a second connection member configured to electrically connect the second transparent electrode and the second device electrode of the light-emitting device.

US Pat. No. 10,991,851

LIGHT EMITTING DIODE FOR SURFACE MOUNT TECHNOLOGY, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING LIGHT EMITTING DIODE MODULE

SEOUL VIOSYS CO., LTD., ...

1. A light emitting diode (LED), comprising:a substrate;
a first semiconductor layer disposed on the substrate;
an active layer disposed on a portion of the first semiconductor layer;
a second semiconductor layer disposed on the active layer;
a side of the active layer and the second semiconductor layer have inclined profile with respect to a surface of the first semiconductor layer;
a reflection pattern disposed on a portion of the second semiconductor layer;
a first pad and a second pad spaced apart from each other; and
a first insulating layer comprising a first portion having a first thickness and a second portion having a second thickness different from the first thickness,
wherein:
an end portion of the first insulation layer contacting the first semiconductor layer is under a top surface of the a second semiconductor layer,
the first portion is disposed on the reflection pattern; and
the second portion is disposed on the second semiconductor layer.

US Pat. No. 10,991,850

GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD OF MANUFACTURING SAME

DOWA Electronics Material...

1. A group III nitride semiconductor light-emitting element comprising, in the following order:an n-type group III nitride semiconductor layer;
a group III nitride semiconductor laminated body obtained by alternately laminating a barrier layer and a well layer narrower in bandgap than the barrier layer in the stated order so that the number of barrier layers and the number of well layers are both N, where N is an integer;
an AlN guide layer; and
a p-type group III nitride semiconductor layer,
wherein the AlN guide layer has a thickness of 0.7 nm or more and 1.7 nm or less, and
wherein an Nth well layer in the group III nitride semiconductor laminated body and the AlN guide layer are in contact with each other,
wherein the p-type group III nitride semiconductor layer includes a first p-type group III nitride semiconductor layer and a second p-type group III nitride semiconductor layer in the stated order,
the first p-type group III nitride semiconductor layer is narrower in bandgap than the AlN guide layer, and wider in bandgap than the barrier layer,
the second p-type group III nitride semiconductor layer is narrower in bandgap than the first p-type group III nitride semiconductor layer, and
wherein the first p-type group III nitride semiconductor layer and the second p-type group III nitride semiconductor layer are in contact with each other, and the second p-type group III nitride semiconductor layer is composed only of a p-type contact layer.

US Pat. No. 10,991,849

LIGHT-EMITTING THYRISTOR, LIGHT-EMITTING ELEMENT CHIP, OPTICAL PRINT HEAD, AND IMAGE FORMING APPARATUS

OKI DATA CORPORATION, To...

1. A light-emitting thyristor comprising:a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type arranged adjacent to the first semiconductor layer;
a third semiconductor layer of the first conductivity type arranged adjacent to the second semiconductor layer; and
a fourth semiconductor layer of the second conductivity type arranged adjacent to the third semiconductor layer, wherein
the first semiconductor layer includes an active layer adjacent to the second semiconductor layer,
the second semiconductor layer includes a first layer adjacent to the active layer and a second layer arranged between the first layer and the third semiconductor layer,
the first layer has a band gap wider than a band gap of the active layer and a band gap of the second layer, and
the band gap of the second layer is equal to or wider than the band gap of the active layer.

US Pat. No. 10,991,848

DISPLAY PANEL AND DISPLAY DEVICE

WUHAN TIANMA MICRO-ELECTR...

1. A display panel, comprising:a display area, wherein the display area comprises pixels arranged in an array, and the pixels comprise at least three sub-pixels of different colors;
the display area comprises a general display area, a transition display area and a photosensitive device setting area, the general display area surrounds at least a part of the transition display area, and the transition display area surrounds the photosensitive device setting area;
in the transition display area, the at least three sub-pixels comprise display sub-pixels and virtual sub-pixels, the sub-pixels comprise pixel circuits and light-emitting units, the light-emitting units are electrically connected to the pixel circuits in the display sub-pixels, and the light-emitting units are insulated from the pixel circuits in the virtual sub-pixels; and in the photosensitive device setting area, the at least three sub-pixels only comprise display sub-pixels; and
a setting density of the display sub-pixels in the transition display area is higher than a setting density of the display sub-pixels in the photosensitive device setting area, and lower than a setting density of the display sub-pixels in the general display area.

US Pat. No. 10,991,847

SEMICONDUCTING DEVICES CONTAINING QUANTUM WELLS

Alliance for Sustainable ...

1. A device comprising, in order:an emitter layer;
a quantum well; and
a base layer, wherein:
the emitter layer has a first bandgap,
the base layer has a second bandgap, and
the first bandgap is different than the second bandgap by an absolute difference between about 25 meV and about 100 meV.

US Pat. No. 10,991,846

METHOD OF MANUFACTURING MICRO LIGHT-EMITTING ELEMENT ARRAY, TRANSFER CARRIER, AND MICRO LIGHT-EMITTING ELEMENT ARRAY

PLAYNITRIDE INC., Zhubei...

16. A micro light-emitting element array, comprising:a transfer carrier comprising a transfer substrate and at least one metal bonding pad, and the at least one metal bonding pad being disposed on the transfer substrate; and
a plurality of micro light-emitting elements, a surface of each of the plurality of micro light-emitting elements having at least one electrode, a connecting surface of the at least one electrode and a lateral surface of the at least one electrode being adjacent to each other, and the at least one metal bonding pad is connected to the connecting surface and a part of the lateral surface so as to fix the plurality of micro light-emitting elements on the transfer carrier;
wherein the at least one metal bonding pad is connected to the connecting surface of the at least one electrode through a diffusion force, the connection between the at least one metal bonding pad and the connecting surface of the at least one electrode is achieved by peritectic reaction or in a non-wetting state, and the connection is reversible, and a ratio of an area of the lateral surface covered by the at least one metal bonding pad to a surface area of the lateral surface is greater than or equal to 0.05 and is smaller than or equal to 0.3.

US Pat. No. 10,991,845

METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND OPTOELECTRONIC SEMICONDUCTOR COMPONENT

OSRAM OLED GMBH, Regensb...

14. A method for producing an optoelectronic semiconductor component, the method comprising:providing at least two source substrates, wherein a first source substrate is equipped with a first type of radiation-emitting semiconductor chips and a second source substrate is equipped with a second type of radiation-emitting semiconductor chips;
providing a target substrate having a mounting plane for mounting the first and second types of semiconductor chips;
transferring at least part of the first type of semiconductor chips with a wafer-to-wafer process from the first source substrate onto the target substrate so that the first type of semiconductor chips maintain their relative position with respect to one another;
forming a first casting layer so that the first casting layer is located in the same plane with the first type of semiconductor chips, wherein the first casting layer has the same thicknesses as the first type of semiconductor chips with a tolerance of at most 5 ?m and of at most 25% of a mean height of the first type of semiconductor chips;
after forming the first casting layer, transferring at least part of the second type of semiconductor chips with a wafer-to-wafer process from the second source substrate onto the target substrate so that the second type of semiconductor chips maintain their relative position with respect to one another; and
forming a second casting layer so that the second casting layer is located in the same plane with the second type of semiconductor chips, wherein the second casting layer has the same thicknesses as the second type of semiconductor chips with a tolerance of at most 5 ?m and of at most 25% of a mean height of the second type of semiconductor chips;
wherein the first casting layer terminates flush with the first type of semiconductor chips on a side of the first type of semiconductor chips facing away from the mounting plane, and wherein the second casting layer terminates flush with the second type of semiconductor chips on a side of the second type of semiconductor chips facing away from the mounting plane.

US Pat. No. 10,991,844

APPARATUS FOR ALIGNING A SOLAR CELL ELEMENT, SYSTEM FOR USE IN THE MANUFACTURE OF A SOLAR CELL ARRANGEMENT, AND METHOD FOR ALIGNING A SOLAR CELL ELEMENT

APPLIED MATERIALS ITALIA ...

1. Apparatus for aligning a solar cell element, comprising:a gripper configured for moving the solar cell element from a first position on a transport device to a second position on a support device;
a detection device configured to detect a first orientation of the solar cell element on the transport device and configured to detect a second orientation of the solar cell element held by the gripper; and
a controller configured to change an orientation of the solar cell element held by the gripper based on at least one of the first orientation and the second orientation to align the solar cell element.

US Pat. No. 10,991,843

SOLAR CELL AND METHOD FOR PREPARING SAME

1. A method for preparing a solar cell, comprising:forming a first electrode on a substrate; forming a light absorbing layer on the first electrode;
forming a second electrode on the light absorbing layer,
forming an impurity material layer including an impurity element on the light absorbing layer adjacent to the first electrode or the second electrode in any one side or both sides thereof; and
after forming the impurity material layer, forming a doping layer by diffusing the impurity element into a portion of the light absorbing layer through a heat treatment,
wherein the light absorbing layer is composed of a Cu compound or a Cd compound,
wherein a p-n junction or an internal electric field layer is formed in the Cu compound or the Cd compound by the doping layer,
wherein the Cu compound or Cd compound has a binary composition,
wherein the impurity material layer is composed of a metal oxide containing any one or more of Ti and Si.

US Pat. No. 10,991,842

PHOTOELECTRIC CONVERSION ELEMENT

SUMITOMO CHEMICAL COMPANY...

1. A photodetector comprising:an anode;
a cathode; and
an active layer provided between the anode and the cathode, wherein the active layer contains a p-type semiconductor material that is a polymer compound having a polystyrene-equivalent weight average molecular weight of 40,000 or more and 200,000 or less, and an n-type semiconductor material, and
on an image obtained by binarizing an image of the active layer observed by a transmission electron microscope, a junction length between a phase of the p-type semiconductor material and a phase of the n-type semiconductor material is 130 ?m or more and less than 200 ?m per square micrometer of area of the binarized image.

US Pat. No. 10,991,841

PEROVSKITE SOLAR CELL AND TANDEM SOLAR CELL

Industrial Technology Res...

1. A perovskite solar cell comprising:a perovskite light-absorbing layer having a first surface and a second surface;
a first electrode disposed on the first surface of the perovskite light-absorbing layer, wherein the first electrode is a transparent single-layered electrode, and the first electrode is consisted of niobium-doped molybdenum oxide (MoO3); and
a second electrode disposed on the second surface of the perovskite light-absorbing layer.

US Pat. No. 10,991,840

MULTI-JUNCTION SOLAR CELL

AZUR SPACE Solar Power Gm...

1. A stacked multi-junction solar cell comprising:a first subcell having a first layer including germanium, the first subcell forming a substrate for the stacked multi-junction solar cell;
a second subcell having a larger band gap than the first subcell;
a third subcell having a larger band gap than the second subcell, the first, second and third subcells having an emitter and a base;
a fourth subcell having a fourth layer;
a metamorphic buffer formed between the first subcell and the second subcell, the metamorphic buffer having a sequence of at least three layers, and a lattice constant increasing from layer to layer in a sequence in a direction of the second subcell, the metamorphic buffer layer being directly adjacent to the first subcell,
wherein the second subcell comprises a second layer formed of a compound that includes at least the elements GaInAsP, a thickness of the second layer being greater than 100 nm, the second layer being formed as part of the emitter or as part of the base or as part of a space-charge zone situated between the emitter and the base, and a lattice constant of the second layer is less than 5.84 ?,
wherein the third subcell includes a third layer having a compound formed of at least the elements GaInP, a thickness of the third layer being greater than 100 nm, the third layer being formed as part of the emitter or as part of the base or as part of the space-charge zone situated between the emitter and the base, a lattice constant of the third layer of the third subcell differing from the lattice constant of the second layer of the second subcell by less than 0.2%,
wherein, in the second subcell, a phosphorus content of the second layer is greater than 1 atomic % and less than 45 atomic % and an indium content of the second layer of the second subcell is less than 50 atomic %, and
wherein a fifth subcell is disposed between the second subcell and the third subcell, and the fifth subcell includes a fifth layer having a compound formed of at least the compound GaInAs, and the thickness of the fifth layer is greater than 100 nm, and the fifth layer is formed as part of the emitter or as part of the base or as part of the space charge zone situated between the emitter and the base,
wherein the second subcell, the third subcell, the fourth subcell, and the fifth subcell are lattice matched.

US Pat. No. 10,991,839

SOLAR CELL METAL-LESS REFLECTOR / BACK ELECTRODE STRUCTURE

1. A photovoltaic or light detecting device comprising:a periodic array of dome or dome-like protrusions at a light impingement surface;
an electrode following the contour of said periodic array of dome or dome-like protrusions;
a back electrode also defining a metal-less reflector, said metal-less reflector and back electrode serving as the back light reflector and counter electrode to said periodic array of dome or dome-like protrusions, where said metal-less reflector-and back electrode is planar and continuous under said periodic array of dome or dome-like protrusions, contains no metal layers, and is electrically conducting and devoid of any metal film having an optical function;
an active region intermediate between said electrode and said metal-less reflector and back electrode;
a planar substrate supporting said metal-less reflector and back electrode; and
a metal layer forming a back contact on said planar substrate, said metal layer having no required or significant optical function as a reflector and serves only as a structural support, an electrical conduit, or a combination thereof.

US Pat. No. 10,991,838

PHOTOVOLTAIC MODULE, SOLAR CELL, AND MANUFACTURING METHOD THEREFOR

JINKO GREEN ENERGY (SHANG...

1. A solar cell, comprising:a semiconductor layer; and
a passivation film stack provided on a back surface of the semiconductor layer,
wherein the passivation film stack comprises:
a first passivation layer provided on the back surface of the semiconductor layer and including a silicon-rich layer with a silicon atom concentration ranging from 5×1021/cm3 to 2.5×1022/cm3;
a second passivation layer provided on a surface of the first passivation layer and including an oxygen-rich and nitrogen-rich layer; and
a third passivation layer provided on a surface of the second passivation layer and including at least one silicon nitride film with a gradient-varied refractive index,
wherein a first refractive index of the first passivation layer is greater than a second refractive index of the second passivation layer and smaller than a third refractive index of the third passivation layer.

US Pat. No. 10,991,837

CONFIGURATIONS FOR SOLAR CELLS, SOLAR PANELS, AND SOLAR PANEL SYSTEMS

1. A solar panel comprising:a recessed solar cell pit comprising a first solar cell forming a first pit side of the recessed solar cell pit, a second solar cell forming a second pit side of the recessed solar cell pit, and a third solar cell forming a third pit side of the recessed solar cell pit, wherein the first solar cell, the second solar cell, and the third solar cell comprise a triangular configuration, and each of the first solar cell, the second solar cell, and the third solar cell configured to convert solar energy to electricity;
the first solar cell comprising a first edge and a second edge that converge to form a corner of the first pit side;
the second solar cell comprising a first edge and a second edge that converge to form a corner of the second pit side;
the third solar cell comprising a first edge and a second edge that converge to form a corner of the third pit side;
the first solar cell, the second solar cell, and the third solar cell defining a triangular opening of the recessed solar cell pit;
wherein the corner of the first pit side, the corner of the second pit side, and the corner of the third pit side are joined together such that the first edge of the first solar cell is adjacent to the second edge of the second solar cell, the first edge of the second solar cell is adjacent to the second edge of the third solar cell, the first edge of the third solar cell is adjacent to the second edge of the first solar cell;
wherein light received by the recessed solar cell pit through the triangular opening of the recessed solar cell pit that impinges on the first solar cell is partially captured by the first solar cell to be converted to electricity and partially reflected by the first solar cell toward the second solar cell;
wherein light reflected by the first solar cell toward the second solar cell is partially captured by the second solar cell to be converted to electricity and partially reflected by the second solar cell toward the third solar cell; and
wherein light reflected by the second solar cell toward the third solar cell is at least partially captured by the third solar cell to be converted to electricity.

US Pat. No. 10,991,836

ARCHITECTURES ENABLING BACK CONTACT BOTTOM ELECTRODES FOR SEMICONDUCTOR DEVICES

University of Houston Sys...

1. A semiconductor device comprising:a polycrystalline or amorphous substrate;
an electrically conductive Ion Beam-Assisted Deposition (IBAD) template layer positioned above the substrate; and
at least one electrically conductive hetero-epitaxial buffer layer positioned above the IBAD template layer, wherein the at least one buffer layer has a resistivity of less than 100 ??cm, and wherein the at least one buffer layer comprises a fluorite structure that has a (004) out-of-plane orientation;
wherein the substrate comprises metal and functions as a back contact bottom electrode, or the semiconductor device further comprises a back contact bottom electrode positioned below the substrate.

US Pat. No. 10,991,835

HYDROGEN DIFFUSION BARRIER FOR HYBRID SEMICONDUCTOR GROWTH

ARRAY PHOTONICS, INC., T...

1. A semiconductor device comprising:a dilute nitride active layer, wherein the dilute nitride active layer comprises:
a dilute nitride material selected from GaNAs, GaInNAs, GaInNAsSb, GaInNAsBi, GaInNAsSbBi, GaNAsSb, GaNAsBi, and GaNAsSbBi;
a background doping concentration less than 5×1016 cm?3; and
a hydrogen-induced defect density less than the background doping density;
a hydrogen diffusion barrier region overlying the dilute nitride active layer, wherein the hydrogen diffusion barrier region comprises a doped semiconductor layer, a dilute nitride semiconductor layer, a strained semiconductor layer, or a combination of any of the foregoing; and
one or more semiconductor layers overlying the hydrogen diffusion barrier region.

US Pat. No. 10,991,834

PHOTOVOLTAIC MODULE, SOLAR CELL, AND METHOD FOR PRODUCING SOLAR CELL

JINKO GREEN ENERGY (SHANG...

1. A solar cell, comprising:a semiconductor layer; and
a plurality of passivation layers provided on a back surface of the semiconductor layer,
wherein the plurality of passivation layers include:
a first silicon oxynitride film layer having a first refractive index;
a second silicon oxynitride film layer having a second refractive index and provided on a surface of the first silicon oxynitride film layer; and
at least one silicon nitride film layer having a third refractive index and provided on a surface of the second silicon oxynitride film layer,
wherein a sum of thicknesses of the first silicon oxynitride film layer and the second silicon oxynitride film layer is greater than 70 nm, a thickness of the at least one silicon nitride film layer is greater than 60 nm, a sum of thicknesses of the plurality of passivation layers is greater than 130 nm and smaller than 300 nm, and the first refractive index is greater than the second refractive index and smaller than the third refractive index,
wherein a thickness of the first silicon oxynitride film layer ranges from 30 nm to 40 nm, and the first refractive index ranges from 1.64 to 1.67, and
wherein a thickness of the second silicon oxynitride film layer ranges from 40 nm to 60 nm, and the second refractive index ranges from 1.54 to 1.58.

US Pat. No. 10,991,833

LAMINAR AIRFOIL AND THE ASSEMBLY AND MOUNTING OF SOLAR CELL ARRAYS ON SUCH AIRFOILS

SolAero Technologies Corp...

1. A vehicle comprising(a) a streamlined body having a top surface,
(b) a double sided adhesive film positioned on and mounted to the top surface of the streamlined body, and
(c) a solar cell assembly bonded to the top surface by the double sided adhesive film, wherein the solar cell assembly comprises
(i) a first silicone film;
(ii) an array of interconnected solar cells having a front light receiving side and a back side, with the back side disposed directly over the first silicone film; and
(iii) a second silicone film comprising a first portion tapering in thickness and comprising a second portion of the second silicone film over the front side of the solar cells so as to encapsulate the solar cells and provide a smooth surface wherein the tapering of the second silicone film is no more than a gradation of two degrees.

US Pat. No. 10,991,832

POWER DIODE

Infineon Technologies Aus...

1. A power diode, comprising a semiconductor body coupled to an anode metallization and to a cathode metallization, wherein the semiconductor body has a drift region of a first conductivity type and an anode region of a second conductivity type, the anode region comprising:a contact zone arranged in contact with the anode metallization;
a field stop zone arranged below the contact zone; and
a body zone arranged below the field stop zone and above the drift region;
wherein an electrically activated dopant concentration of the anode region has a profile, along a vertical direction, according to which:
a first maximum is present within the contact zone;
a second maximum is present within the field stop zone;
the dopant concentration continuously decreases from the first maximum to a local minimum, and continuously increases from the local minimum to the second maximum; and
the second maximum is within a range of 70% to 130% of the first maximum, wherein, according to the profile, the dopant concentration continuously decreases from the second maximum to an inflexion point at which a rate of change of the dopant concentration with respect to the vertical direction has a local maximum, and wherein during a blocking state of the power diode, the electrical field stops below the inflexion point.

US Pat. No. 10,991,831

LAYER, MULTILEVEL ELEMENT, METHOD FOR FABRICATING MULTILEVEL ELEMENT, AND METHOD FOR DRIVING MULTILEVEL ELEMENT

IUCF-HYU (INDUSTRY-UNIVER...

1. A multilevel element comprising:a gate electrode;
a first active layer formed over one side of the gate electrode;
a second active layer formed over one side of the first active layer;
source and drain electrodes; and
a barrier layer configured to separate the first active layer from the second active layer,
wherein the number of active layers, in which a channel is formed, including the first and second active layers, is controlled according to a magnitude of a gate voltage which is applied to the gate electrode,
wherein at least one of the first and second active layer exhibits a first number of electron states in a low-level electron energy range in a conduction band, and exhibits a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, and
wherein localized states exist between the low-level electron energy range and the high-level electron energy level.

US Pat. No. 10,991,830

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. An electronic appliance comprising:a silicon substrate;
an insulating layer over the silicon substrate;
a wiring embedded in the insulating layer; and
a conductive layer over the insulating layer and the wiring;
wherein a flat surface of the conductive layer is in contact with a top surface of the insulating layer and a top surface of the wiring,
wherein a first portion of the silicon substrate is included in a photoelectric conversion element,
wherein a second portion of the silicon substrate is included in a first transistor,
wherein a second transistor is positioned over the first transistor,
wherein the first transistor, the second transistor, and the photoelectric conversion element are positioned at different heights,
wherein a trench of the silicon substrate is adjacent to the photoelectric conversion element,
wherein a first insulator is provided along a side surface of the trench,
wherein a second insulator is provided in the trench with the first insulator therebetween,
wherein the trench does not penetrate the silicon substrate,
wherein a light-receiving surface of the photoelectric conversion element is provided on a first side of the silicon substrate, the first side being opposite to a second side where the first transistor is formed.

US Pat. No. 10,991,829

SEMICONDUCTOR DEVICE COMPRISING OXIDE SEMICONDUCTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:an oxide semiconductor layer including a first region and a pair of second regions;
a source electrode layer and a drain electrode layer over the pair of second regions;
a gate insulating film over the first region, the pair of second regions, the source electrode layer, and the drain electrode layer; and
a gate electrode layer over the gate insulating film and overlapping with the first region,
wherein the oxide semiconductor layer contains at least four kinds of elements of indium, gallium, zinc, and oxygen,
wherein a composition ratio of indium is larger than a composition ratio of zinc,
wherein the composition ratio of zinc is larger than a composition ratio of gallium,
wherein each of the composition ratios is represented by atomic percentage,
wherein the pair of second regions includes a dopant and the first region does not include the dopant, and
wherein the dopant is one of phosphorus, arsenic, antimony, boron, aluminum, nitrogen, argon, helium, neon, fluorine, chlorine, and titanium.

US Pat. No. 10,991,828

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure for avoiding current leakage, comprising:a gate structure disposed on a substrate;
a source and a drain disposed in the substrate on two sides of the gate structure;
a dielectric layer disposed on the substrate and the gate structure;
two contact openings disposed in the dielectric layer to respectively expose the source and the drain;
two contact trenches disposed in the source and drain and under the two contact openings, respectively;
two contact spacers respectively covering sidewalls of the contact trenches for avoiding current leakage induced by the gate structure, wherein a material of the contact spacers comprises silicon oxide or silicon nitride;
two silicide layers disposed under the bottom surface of the contact trenches; and
two contact plugs filled in the contact trenches and the contact openings,
wherein the gate structure comprises:
a gate dielectric layer on the substrate;
a gate layer on the gate dielectric layer; and
a gate mask layer on the gate layer.

US Pat. No. 10,991,827

STRUCTURE OF OXIDE THIN FILM TRANSISTOR

TCL CHINA STAR OPTOELECTR...

1. A structure of an oxide thin film transistor, comprising: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer,wherein the oxide semiconducting layer has a body exhibiting a predetermined original material property of semiconduction and a skin layer, which is a unitary part of the oxide semiconducting layer and defines a surface of the oxide semiconducting layer, the skin layer having a modified material property of semiconduction that is different from the predetermined original material property of semiconduction and extends inward from a top face of the oxide semiconducting layer;
two vias are formed in the etching stopper layer and the oxide semiconducting layer comprises two recesses formed in the surface of the oxide semiconducting layer and extending from the top face of the oxide semiconducting layer to run completely through the skin layer and penetrate into the body of the oxide semiconducting layer, wherein the two recesses respectively correspond to the two vias, and the two recesses are extended through the skin layer into an interior of the body so as to expose a part of the body that exhibits the predetermined original material property of semiconduction; and
the two recesses are respectively connected with and in communication with the two vias, the source being filled in a first one of the vias and a first one of the recesses that is connected with the first via to connect to and physically contact the part of the body of the oxide semiconducting layer that exhibits the predetermined original material property of semiconduction, the drain being filled in a second one of the vias and a second one of the recesses connected with the second via to connect to and physically contact the part of the body of the oxide semiconducting layer that exhibits the predetermined original material property of semiconduction, wherein the source and the drain are both connected to the part of the body of the oxide semiconducting layer that exhibits the predetermined original material property of semiconduction, and the source and the drain are connected to each other by a portion of the body of the oxide semiconducting layer that exhibits the predetermined original material property of semiconduction.

US Pat. No. 10,991,825

SEMICONDUCTOR DEVICE INCLUDING NON-ACTIVE FINS AND SEPARATION REGIONS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a substrate having a plurality of fins protruding therefrom, the plurality of fins comprising a plurality of active fins and at least one non-active fin disposed between ones of the plurality of active fins;
at least one gate electrode crossing at least a portion of the active fins;
a plurality of source/drain regions disposed on the active fins adjacent the at least one gate electrode and separated from one another by the at least one non-active fin; and
a gate separating pattern interposed between first and second gate electrodes of the at least one gate electrode,
wherein a lowermost surface of the gate separating pattern directly contacts a source/drain region of the plurality of source/drain regions.

US Pat. No. 10,991,824

SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a first gate structure on a substrate;
a first epitaxial layer on one side of the first gate structure; and
a second epitaxial layer on another side of the first gate structure, wherein the first epitaxial layer and the second epitaxial layer comprise different sizes and different depths, a top surface of the first epitaxial layer and a top surface of the second epitaxial layer comprise different widths, the first epitaxial layer and the second epitaxial layer contact the substrate directly, and the first epitaxial layer comprises a circular shape and the second epitaxial layer comprises an elliptical shape, a diameter of the elliptical shape of the second epitaxial layer is less than a diameter of the circular shape of the first epitaxial layer;
a fin-shaped structure on the substrate;
a shallow trench isolation (STI) around the fin-shaped structure;
a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion;
a second gate structure adjacent to the first epitaxial layer and on the STI;
a third gate structure adjacent to the second epitaxial layer and on the SDB structure;
a first spacer on one sidewall of the first gate structure and between the first gate structure and the second gate structure;
a second spacer on another sidewall of the first gate structure and between the first gate structure and the third gate structure;
a third spacer on one sidewall of the second gate structure and between the first gate structure and the second gate structure; and
a fourth spacer on one sidewall of the third gate structure and between the first gate structure and the third gate structure, wherein the top surface of the first epitaxial layer extending from a sidewall of the first spacer to a sidewall of the third spacer and the top surface of the second epitaxial layer extending from a sidewall of the second spacer to a sidewall of the fourth spacer comprise different widths.

US Pat. No. 10,991,822

SILICON CARBIDE SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE LAYER FORMED ABOVE A BOTTOM SURFACE OF A WELL REGION SO AS NOT TO BE IN OHMIC CONNECTION WITH THE WELL REGION AND POWER CONVERTER INCLUDING THE SAME

MITSUBISHI ELECTRIC CORPO...

18. A silicon carbide semiconductor device comprising:a semiconductor substrate of a first conductivity type made of silicon carbide;
a drift layer of the first conductivity type formed on the semiconductor substrate;
multiple first well regions of a second conductivity type provided in a surface layer of the drift layer in a cross-sectional view;
a first separation region of the first conductivity type, which is a region separating each of the first well regions from each other in the cross-sectional view;
a source region of the first conductivity type formed in a surface layer area of each of the first well regions;
a first Schottky electrode provided on the first separation region and forming a Schottky junction with the first separation region;
an ohmic electrode provided on each of the first well regions and in ohmic connection with each of the first well regions;
a gate insulating film formed on each of the first well regions;
a second well region of the second conductivity type provided in the surface layer of the drift layer to be continuous with at least one of the first well regions;
a gate electrode formed on the gate insulating film on each of the first well regions and on an insulating film provided on the second well region;
a gate pad formed above the second well region and connected with the gate electrode;
a conductive layer formed above the bottom surface of the second well region so as not to be in ohmic connection with the second well region, the conductive layer having an area half or more of the area of the second well region below the gate pad and being lower in sheet resistance than the second well region; and
a source electrode connected with the first Schottky electrode, the ohmic electrode, and the conductive layer, wherein
the second well region is in ohmic connection with the source electrode through a first well region contact hole on at least one of the first well regions.

US Pat. No. 10,991,821

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

10. A method of manufacturing a semiconductor device, the method comprising:forming a first semiconductor layer of a first conductivity type on a front surface of a semiconductor substrate of the first conductivity type, the first semiconductor layer having an impurity concentration that is lower than that of the semiconductor substrate;
selectively forming a second semiconductor layer of a second conductivity type in a surface layer of the first semiconductor layer on a first side of the first semiconductor layer, opposite a second side of the first semiconductor layer facing toward the semiconductor substrate;
selectively forming a first semiconductor region of the first conductivity type in a surface layer of the second semiconductor layer on a first side of the second semiconductor layer, opposite a second side of the second semiconductor layer facing toward the semiconductor substrate;
selectively forming a second semiconductor region of the second conductivity type in the surface layer of the second semiconductor layer on the first side of the second semiconductor layer, the second semiconductor region having an impurity concentration that is higher than that of the second semiconductor layer;
introducing a lifetime killer to form a lifetime killer region which is provided at an interface of the second semiconductor layer and the first semiconductor layer;
forming, via a gate insulating film, a gate electrode at least at a part of a surface of the second semiconductor layer sandwiched between the first semiconductor region and the first semiconductor layer;
forming a first electrode on surfaces of the first semiconductor region and the second semiconductor layer;
forming a second electrode on a rear surface of the semiconductor substrate; and
forming a gate electrode pad electrically connected with the gate electrode,
wherein
the lifetime killer region is provided at least partially in a portion of the second semiconductor layer disposed below the gate electrode pad and is excluded from the second semiconductor layer disposed below the first semiconductor region.

US Pat. No. 10,991,820

MANUFACTURING METHOD FOR FORMING INSULATING STRUCTURE OF HIGH ELECTRON MOBILITY TRANSISTOR

UNITED MICROELECTRONICS C...

1. A method of forming an insulating structure of a high electron mobility transistor (HEMT), comprising:forming a gallium nitride layer;
forming an aluminum gallium nitride layer on the gallium nitride layer;
performing an ion doping step to dope a plurality of ions in the gallium nitride layer and the aluminum gallium nitride layer,
forming an insulating doped region in the gallium nitride layer and the aluminum gallium nitride layer;
forming two grooves on both sides of the insulating doped region; and
filling an insulating layer in the two grooves and forming two sidewall insulating structures respectively positioned at two sides of the insulating doped region.

US Pat. No. 10,991,819

HIGH ELECTRON MOBILITY TRANSISTORS

Taiwan Semiconductor Manu...

1. A transistor device, comprising:a layer of GaN disposed over a substrate;
a mobility-enhancing layer of AlzGa(1-z)N disposed over the layer of GaN and having a first molar fraction z that is in a first range of between 0.25 and 0.4;
a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x that in a second range of between 0.1 and 0.15;
a source comprising a source contact and an underlying source region, wherein the source region extends through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N, and wherein the source region has a bottom that is over a bottom of the mobility-enhancing layer of AlzGa(1-z)N;
a drain comprising a drain contact and an underlying drain region, wherein the drain region extends through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N, and wherein the drain region has a bottom that is over the bottom of the mobility-enhancing layer of AlzGa(1-z)N;
a first isolation structure arranged over the resistance-reducing layer of AlxGa(1-x)N, wherein the source region and the drain region each have a top surface that is above a bottom surface of the first isolation structure;
a second isolation structure arranged over the first isolation structure;
a gate structure laterally between the source contact and the drain contact, wherein the gate structure has a sidewall defined by a differentiable function between a top and a bottom of the sidewall, and wherein the sidewall extends between a top of the second isolation structure and a bottom of the first isolation structure; and
wherein the drain contact has a first sidewall and a second sidewall laterally offset from the first sidewall, and wherein the first sidewall is disposed along a sidewall of the second isolation structure and the second sidewall is disposed along a sidewall of the first isolation structure.

US Pat. No. 10,991,818

NITRIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR

ROHM CO., LTD., Kyoto (J...

1. A nitride semiconductor device, comprising:an electron transit layer that is formed of a nitride semiconductor;
an electron supply layer that is formed on the electron transit layer, and that is formed of a nitride semiconductor whose composition is different from the electron transit layer;
an insulating film that is formed along a top surface of the electron supply layer;
a gate electrode that is formed to penetrate the insulating film so as to extend toward the electron transit layer such that a bottom end of the gate electrode is located below a top surface of the insulating film, and is opposite to the electron transit layer;
a gate insulating film interposed between the bottom end of the gate electrode and the electron transit layer and extending onto the top surface of the insulating film to cover the top surface of the insulating film; and
a source wiring film and a drain wiring film that are provided above the electron supply layer at an interval when viewed in plan, wherein the source wiring film and the drain wiring film are formed in comb tooth shapes, respectively, that mesh with each other.

US Pat. No. 10,991,816

NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

FUJITSU LIMITED, Kawasak...

20. A manufacturing method for a nitride semiconductor device, comprising:forming a back-barrier layer containing InAlGaN on a first nitride semiconductor layer; and
forming a second nitride semiconductor layer on the back-barrier layer,
wherein, in the back-barrier layer, in a thickness direction, a sum of an In composition and an Al composition continuously increases toward an interface with the second nitride semiconductor layer from a minimum value to the maximum value, and the sum of the In composition and the Al composition is reduced at the interface from the maximum value to the minimum value,
wherein the minimum value is 0%,
wherein a maximum value is 50% to 80%.

US Pat. No. 10,991,815

SEMICONDUCTOR DEVICE

SANKEN ELECTRIC CO., LTD....

1. A semiconductor device, comprising:a semiconductor base;
a trench insulating film which is provided on an inner wall surface and a bottom of a trench formed from an upper surface of the semiconductor base in a thickness direction of the semiconductor base and includes a positively charged region, the trench insulating film having a structure comprising an outer charged region, an uncharged region, and an inner charged region, in which the outer charge region is disposed at least on portions of the inner wall surface and on the bottom of the trench, the uncharged region is disposed on the outer charged region, and an inner charged region is disposed on the uncharged region; and
a gate electrode provided on the trench insulating film within the trench, wherein
a positive charge density of the charged region at least in a side part of the outer charged region of the trench insulating film which is provided on the inner wall surface of the trench is higher than that of the inner charged region of the trench insulating film which is opposite to the outer charge region, the outer charged region being in contact with the semiconductor base.

US Pat. No. 10,991,814

THREE-DIMENSIONAL TUNNELING FIELD-EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME

Industry-University Coope...

1. A method of fabricating a three-dimensional tunneling field-effect transistor, the method comprising:growing a buffer layer, an embedded source layer, an etch stop layer, an active source layer, a channel layer, and a drain layer on a substrate;
depositing a metal layer on the drain layer, and then forming a pattern in a mesa structure shape;
forming a vertical gate at one end of each of the etch stop layer, the active source layer, the channel layer, and the drain layer;
forming a first air bridge by etching portions of the embedded source layer and the etch stop layer, not the buffer layer;
forming a second air bridge by etching portions of the drain layer and the channel layer, not the active source layer, the second air bridge is spaced apart from the first air bridge; and
forming a third air bridge by etching a portion of the embedded source layer under the vertical gate, not the buffer layer, the third air bridge is spaced apart from the first and second air bridge.

US Pat. No. 10,991,813

FABRICATION METHOD OF SEMICONDUCTOR DEVICE HAVING SIGE SHELL CHANNEL AND SEMICONDUCTOR DEVICE FABRICATED BY THE SAME

GACHON UNIVERSITY OF INDU...

1. A method for fabricating a semiconductor device having a silicon germanium shell channel comprising:a first step of forming an active layer by alternately stacking a silicon germanium layer and a silicon layer on a semiconductor substrate one or more times;
a second step of sequentially forming a first insulating layer, a second insulating layer, a third insulating layer, a lower insulating layer etching silicon layer, and a fourth insulating layer for dummy patterns on the active layer;
a third step of forming one or more dummy patterns by etching the fourth insulating layer;
a fourth step of forming a sidewall insulating layer on each sidewall of the dummy patterns;
a fifth of forming a plurality of channel fine patterns by removing both ends of the sidewall insulating layer exposed by removing the dummy patterns;
a sixth of forming a source and drain patterns at both ends of the plurality of channel fine patterns, at least one of the channel fine patterns connecting the source and drain patterns;
a seventh step of etching the lower insulating layer etching silicon layer using the source and drain patterns and the channel fine patterns as an etching hard mask;
an eighth step of forming a first insulating layer pattern, a second insulating layer pattern, and a third insulating layer pattern by etching the third insulating layer, the second insulating layer, and the first insulating layer sequentially to expose the active layer using a silicon mask pattern of the lower insulating layer etching silicon layer exposed after removing the source and drain patterns and the channel fine patterns;
a ninth step of forming an active layer pattern by etching the active layer and a part of the semiconductor substrate sequentially using an insulating mask pattern of the third insulating layer exposed after removing the silicon mask pattern;
a tenth step of covering the etched semiconductor substrate, the active layer pattern, the first insulating layer pattern, the second insulating layer pattern, and the third insulating layer pattern with a fifth insulating layer and exposing the second insulating layer pattern through a planarization process;
an eleventh step of forming a separation insulating layer on the etched semiconductor substrate by etching the fifth insulating layer using the second insulating pattern and the first insulating pattern as a mask;
a twelfth step of forming a dummy gate on the separation insulating layer to surround the first insulating layer pattern and the active layer pattern;
a thirteenth step of covering a channel fin including the dummy gate, the first insulating layer pattern, and the active layer pattern with the sixth insulating layer on the separation insulating layer, and exposing the dummy gate through a planarization process;
a fourteenth step of exposing the channel fin to a space in which the dummy gate is removed;
a fifteenth step of selectively etching silicon germanium layers in the exposed channel fin to float silicon layers;
a sixteenth step of forming a silicon buffer layer around each of the floating silicon layers;
a seventeenth step of forming a silicon germanium shell on the silicon buffer layer; and
an eighteenth step of sequentially forming a gate insulating film and a gate surrounding the silicon germanium shell.

US Pat. No. 10,991,812

TRANSISTOR DEVICE WITH A RECTIFIER ELEMENT BETWEEN A FIELD ELECTRODE AND A SOURCE ELECTRODE

Infineon Technologies Aus...

1. A transistor device, comprising:in a semiconductor body, a drift region, a body region adjoining the drift region, and a source region separated from the drift region by the body region;
a gate electrode dielectrically insulated from the body region by a gate dielectric;
a source electrode electrically connected to the source region;
at least one field electrode dielectrically insulated from the semiconductor body by a field electrode dielectric;
a rectifier element coupled between the source electrode and the field electrode; and
a resistor coupled between the source electrode and the field electrode and in parallel with the rectifier element,
wherein the field electrode and the field electrode dielectric are arranged in a first trench that extends from a first surface of the semiconductor body into the semiconductor body,
wherein the rectifier element is integrated in the first trench in a rectifier region that is adjacent at least one of the source region and the body region,
wherein the resistor is integrated in the rectifier region,
wherein the field electrode comprises a semiconductor material of a first doping type,
wherein the resistor comprises a semiconductor region of the first doping type and more lightly doped than the semiconductor material of the field electrode,
wherein the semiconductor region of the first doping type is coupled between the source electrode and the field electrode.

US Pat. No. 10,991,811

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH NANOWIRES

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device structure, comprising:a substrate having a plurality of nanowires over an input-output region;
a protective layer surrounding the nanowires, wherein the protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof;
a high-k dielectric layer surrounding the protective layer;
a gate electrode surrounding the high-k dielectric layer;
a source/drain portion adjacent to the gate electrode;
an interlayer dielectric layer over the source/drain portion;
an etch stop layer between the source/drain portion and the interlayer dielectric layer; and
a protective element over the interlayer dielectric layer, wherein a sidewall of the interlayer dielectric layer and a sidewall of the protective element are covered by the etch stop layer.

US Pat. No. 10,991,810

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:forming a gate structure on a substrate;
forming a polymer block on a corner between the gate structure and the substrate, wherein the polymer block comprises fluorine, bromide, or silicon;
performing an oxidation process to form a first seal layer on sidewalls of the gate structure; and
forming a source/drain region adjacent to two sides of the gate structure.

US Pat. No. 10,991,807

SEMICONDUCTOR DEVICE HAVING GATE INSULATING LAYER

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate comprising an upper surface;
a gate trench on the upper surface of the substrate, the gate trench including an upper region and a lower region,
the upper region of the gate trench including a first inner surface,
the lower region of the gate trench including a second inner surface and a lower surface;
an upper gate insulating layer on the first inner surface;
a lower gate insulating layer on the second inner surface and the lower surface, the lower gate insulating layer connected to the upper gate insulating layer;
a first gate barrier layer on a first inner side of the lower gate insulating layer;
a gate electrode on a second inner side of the first gate barrier layer, the gate electrode filling the lower region of the gate trench; and
a gate buried portion on the gate electrode,
wherein a diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.

US Pat. No. 10,991,806

TWO-TRANSISTOR MEMORY DEVICE AND METHOD FOR FABRICATING MEMORY DEVICE

UNITED MICROELECTRONICS C...

1. A structure of memory device, comprising:a first gate structure, disposed on a substrate, wherein the first gate structure is for storing charges;
a second gate structure, disposed on the substrate;
an insulating layer in contact between a first sidewall of the first gate structure and a second sidewall of the second gate structure; and
an isolation structure integrated with the insulating layer between the first gate structure and the second gate structure and at a top portion of the first gate structure and the second gate structure, wherein the isolation structure provides an isolation distance between the first gate structure and the second gate structure larger than a thickness of the insulating layer.

US Pat. No. 10,991,805

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:forming an etching plasma from a first precursor material;
separating neutral radicals of the etching plasma, wherein the separating the neutral radicals of the etching plasma comprises activating a filter that prevents positive ions and negative ions of the etching plasma from passing through the filter; and
exposing surfaces of a protective layer over a gate dielectric to the neutral radicals of the etching plasma and a second precursor material to etch portions of the surfaces of the protective layer, the second precursor material not being a plasma.

US Pat. No. 10,991,804

TRANSISTOR LEVEL INTERCONNECTION METHODOLOGIES UTILIZING 3D INTERCONNECTS

Xcelsis Corporation, San...

1. A microelectronic unit, comprising:an epitaxial silicon layer having a front silicon surface and a back silicon surface opposite the front silicon surface, the epitaxial silicon layer having a source and a drain each extending between the front and back silicon surfaces, the source and the drain being doped portions of the epitaxial silicon layer;
a buried oxide layer having a top oxide surface and a bottom oxide surface opposite the top oxide surface, such that the top oxide surface faces the back silicon surface; and
an ohmic contact extending through the buried oxide layer between the top and bottom oxide surfaces, the ohmic contact being physically coupled to a lower surface of one of the source or the drain.

US Pat. No. 10,991,803

HEMT-COMPATIBLE LATERAL RECTIFIER STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a layer of semiconductor material disposed over an upper surface of a substrate;
an electron supply layer disposed over the layer of semiconductor material between an anode terminal and a cathode terminal;
a layer of III-N (III-nitride) semiconductor material disposed over the electron supply layer;
a passivation layer contacting an upper surface of the electron supply layer and further contacting an upper surface and a sidewall of the layer of III-N semiconductor material, wherein the passivation layer has a first outermost sidewall separated from the upper surface of the substrate by a first vertical distance and an opposing second outermost sidewall that is separated from the upper surface of the substrate by a second vertical distance that is smaller than the first vertical distance; and
a gate structure separated from the layer of III-N semiconductor material by the passivation layer, wherein the passivation layer continuously extends from directly below the gate structure to past opposing outermost sidewalls of the gate structure.

US Pat. No. 10,991,802

QUANTUM DOT DEVICES WITH GATE INTERFACE MATERIALS

Intel Corporation, Santa...

1. A quantum dot device, comprising:a first quantum well stack region, wherein the first quantum well stack region includes an active quantum well layer;
a first set of gates on the first quantum well stack region, wherein an individual gate in the first set of gates includes a gate interface material, a gate electrode, and a high-k gate dielectric, and the gate interface material is between the high-k gate dielectric and the first quantum well stack region;
a second quantum well stack region, wherein the second quantum well stack region includes a read quantum well layer; and
a second set of gates, parallel to the first set of gates, on the second quantum well stack region.

US Pat. No. 10,991,801

SEMICONDUCTOR DEVICE WITH IMPROVED CURRENT FLOW DISTRIBUTION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate;
a transistor section provided in the semiconductor substrate; and
a diode section provided in the semiconductor substrate, the diode section being adjacent to the transistor section; wherein
the diode section comprises:
a second conductivity-type anode region at least partially exposed on an upper surface of the semiconductor substrate;
a first conductivity-type drift region provided below the anode region;
a first conductivity-type cathode region provided below the drift region;
a plurality of dummy trench portions that penetrate at least the anode region and are arrayed along a predetermined array direction;
a contact portion provided at least above the anode region and along an extending direction of the plurality of dummy trench portions, the extending direction being different from the array direction;
a second conductivity-type lower-surface side semiconductor region provided below the drift region and provided directly below an outer end portion of the contact portion in the extending direction, an end portion of the lower-surface side semiconductor region in the extending direction being adjacent to the cathode region; and
a lifetime killer region provided at least in the diode section.

US Pat. No. 10,991,800

METHOD FOR FINFET LDD DOPING

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
an isolation structure over the substrate;
a fin over the substrate and the isolation structure;
a gate structure engaging a first portion of the fin;
first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin;
source/drain (S/D) features adjacent to the first sidewall spacers, wherein the S/D features are grown over a third portion of the fin that is different from the first and the second portions of the fin; and
second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features, wherein the second sidewall spacers include a dielectric material, and the second sidewall spacers and the second portion of the fin include a same dopant, wherein the first portion of the fin has a first height above the isolation structure, the second sidewall spacers have a second height above the isolation structure, and the second height is less than half of the first height.

US Pat. No. 10,991,799

SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES

Sony Corporation, Tokyo ...

1. An integrated circuit structure, comprising:a substrate;
a horizontal nanowire channel structure above the substrate, the horizontal nanowire channel structure having a bottommost surface, wherein the horizontal nanowire channel structure has a first end opposite a second end;
a gate electrode surrounding the horizontal nanowire channel structure, wherein a portion of the gate electrode has an uppermost surface above the horizontal nanowire channel structure, and wherein a second portion of a gate electrode is beneath the bottommost surface of the horizontal nanowire channel structure;
sidewall spacers adjacent to the gate electrode, wherein a portion of the sidewall spacers is laterally adjacent to the first portion of the gate electrode above the horizontal nanowire channel structure, wherein the sidewall spacers have a bottommost surface below the bottommost surface of the horizontal nanowire channel structure, and wherein first and second ends of the horizontal nanowire channel structure do not extend beyond the sidewall spacers;
a semiconductor material beneath a portion of the horizontal nanowire channel structure beneath the sidewall spacers, the semiconductor material comprising a material different than the horizontal nanowire channel structure, wherein the portion of the horizontal nanowire channel structure beneath the sidewall spacers is directly on the semiconductor material; and
source/drain structures on either side of the horizontal nanowire channel structure, wherein a portion of the source/drain structures is laterally adjacent to and in contact with the portion of the sidewall spacers laterally adjacent to the portion of the gate electrode above the horizontal nanowire channel structure, and the source/drain structures are in contact with respective ones of the first and second ends of the horizontal nanowire channel structure.

US Pat. No. 10,991,796

SOURCE/DRAIN CONTACT DEPTH CONTROL

GLOBALFOUNDRIES U.S. Inc....

1. A method of fabricating a device, comprising:providing a semiconductor structure disposed over a semiconductor substrate, the semiconductor structure comprising (i) a semiconductor fin comprising alternating channel and source/drain regions, (ii) a shallow trench isolation layer disposed over the semiconductor substrate laterally adjacent to a lower portion of the fin and within a fin cut opening between cut ends of the fin, (iii) an oxide layer disposed directly over and extending into the shallow trench isolation layer within the fin cut opening; and
forming a liner completely filling a space defined by the oxide layer within the fin cut opening, wherein the oxide layer extends above the shallow trench isolation layer and a side surface of the oxide layer above the shallow trench isolation layer abuts a side wall spacer, the space forming a hollow extending from above the shallow trench isolation layer and into the shallow trench isolation layer, the liner completely filling the hollow, the liner further defining sidewalls and a bottom of a first trench over the shallow trench isolation layer, the first trench having a bottom surface above a top surface of the shallow trench isolation layer and defined by a top surface of the oxide layer.

US Pat. No. 10,991,795

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a substrate;
inter-device isolation structures over the substrate; and
a crown active region between the inter-device isolation structures, wherein the crown active region comprises:
a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin;
an intra-device isolation structure between the first semiconductor fin and the second semiconductor fin;
a source/drain structure comprising a first portion on the first semiconductor fin and comprising a second portion on the second semiconductor fin, wherein an air gap is between the intra-device isolation structure and the source/drain structure; and
a dielectric layer on the intra-device isolation structure, the dielectric layer physically contacting and extending continuously along an upper surface of the intra-device isolation structure from the first portion of the source/drain structure to the second portion of the source/drain structure, wherein upper surfaces of the inter-device isolation structures distal from the substrate and proximate to the crown active region are free of the dielectric layer.

US Pat. No. 10,991,793

DOUBLE-SIDED CAPACITOR AND METHOD FOR FABRICATING THE SAME

SHENZHEN WEITONGBO TECHNO...

1. A double-sided capacitor, comprising:an intermediate insulating layer disposed between a first semiconductor layer and a second semiconductor layer;
the first semiconductor layer provided with a first trench and a second trench, wherein the first trench and the second trench are downward from an upper surface of the first semiconductor layer, a depth of the first trench is less than a thickness of the first semiconductor layer, and the second trench penetrates through the first semiconductor layer and the intermediate insulating layer;
the second semiconductor layer provided with a third trench and a fourth trench, wherein the third trench and the fourth trench are upward from a lower surface of the second semiconductor layer, a depth of the third trench is less than a thickness of the second semiconductor layer, the fourth trench penetrates through the second semiconductor layer and the intermediate insulating layer, and any two of the first trench, the second trench, the third trench, and the fourth trench are not communicated;
a first electrode layer disposed above the first semiconductor layer, in the first trench, and in the second trench;
a first insulating layer disposed between the first electrode layer and the first semiconductor layer to isolate the first electrode layer in the first trench from the first semiconductor layer, and broken at a bottom of the second trench to electrically connect the first electrode layer to the second semiconductor layer;
a second electrode layer disposed below the second semiconductor layer, in the third trench, and in the fourth trench; and
a second insulating layer disposed between the second electrode layer and the second semiconductor layer to isolate the second electrode layer in the third trench from the second semiconductor layer, and broken at a bottom of the fourth trench to electrically connect the second electrode layer to the first semiconductor layer.

US Pat. No. 10,991,792

ORGANIC LIGHT EMITTING DIODE DISPLAY

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate;
a semiconductor layer on the substrate, the semiconductor layer including a plurality of channels and a plurality of electrodes;
a scan line including a switching gate electrode overlapping a switching channel of the plurality of channels;
a storage line including a storage electrode;
a data line crossing the scan line and for transmitting a data voltage;
a driving voltage line crossing the scan line and for transmitting a driving voltage;
a switching transistor including the switching channel, the switching gate electrode, a switching electrode of the plurality of electrodes, and an electrode of the plurality of electrode, wherein the electrode includes a first end disposed at a side of the switching channel, and the switching electrode is electrically connected to the data lines;
a driving transistor including a driving channel of the plurality of channels, a driving gate electrode overlapping the driving channel, the electrode, and a driving electrode, wherein the electrode includes a second end disposed at a side of the driving channel; and
a storage capacitor including the driving gate electrode and the storage electrode overlapping each other, wherein
the electrode comprises a first portion extending substantially parallel to the data line, an entirety of the first portion being separated from the data line in a plan view, and
at least a portion of the first portion overlaps the storage electrode in the plan view.

US Pat. No. 10,991,791

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a substrate including a pixel area with at least a first rounded corner portion and a non-pixel area arranged sequentially along an outer circumference of the pixel area;
a plurality of pixels in the pixel area, at least one of the pixels comprising:
a transistor on the substrate, the transistor having a semiconductor layer, a gate electrode, and source and drain electrodes;
a first electrode on a first layer on the transistor;
a light emission layer on the first electrode; and
a second electrode on the light emission layer;
an internal circuit in the non-pixel area and having a first end portion adjacent to the first rounded corner portion of the pixel area;
a plurality of routing wires in the non-pixel area below the pixel area, the routing wires extending to the pixel area from the non-pixel area; and
a power source wire in the non-pixel area, provided between the internal circuit and an edge of the display device,
wherein, the power source wire branches into at least a first sub power source line and a second sub power source line in an area adjacent to the first end portion of the internal circuit, and
wherein the first end portion is between the first and second sub power source lines.

US Pat. No. 10,991,790

SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a substrate having a first surface, a second surface opposite to the first surface, and an inner side surface defining a plurality of through holes;
a first wiring and a second wiring both on the first surface; and
a first conductor and a second conductor both in one of the plurality of through holes,
wherein the first conductor is connected to the first wiring,
the second conductor is connected to the second wiring, and
the first and second conductors are insulated from each other.

US Pat. No. 10,991,789

FOLDABLE DISPLAY DEVICE HAVING PLURALITY OF SIGNAL LINES CONNECTED TO NON-FOLDABLE DISPLAY REGIONS

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising:a plurality of non-foldable display regions;
at least one foldable display regions each arranged between two adjacent non-foldable display regions;
a first electrode and a second electrode, a subpixel of the display substrate being configured to emit light under the effect of an electric field generated between the first electrode and the second electrode; and
a first signal line connected to the first electrode and a second signal line connected to the second electrode,
wherein the first signal line comprises a plurality of secondary signal lines independent of each other, and the plurality of secondary signal line corresponds to one of the plurality of non-foldable display regions and is configured to control whether to supply power to the corresponding non-foldable display region,
wherein the first electrode is connected to a first signal source via the first signal line, and the second electrode is connected to a second signal source via the second signal line, and
wherein each secondary signal line is located at the corresponding non-foldable display region, the secondary signal lines comprise at least one first secondary signal lines, and each first secondary signal line is configured to be switched between a first state and a second state, the first secondary signal line is electrically disconnected from the first signal source for providing an electric signal to the first signal line and electrically connected to the second signal line in the first state, and the first secondary signal line is electrically connected to the first signal source and electrically disconnected from the second signal line in the second state.

US Pat. No. 10,991,788

ORGANIC LIGHT EMITTING DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting display apparatus, comprising:active patterns arranged corresponding to a plurality of pixels, and connected to each other along a first direction;
a first initialization power supply line to which a first initialization voltage is applied;
a second initialization power supply line to which a second initialization voltage different from the first initialization voltage is applied;
an organic light emitting diode; and
a first transistor which apply the second initialization voltage to a first electrode of the organic light emitting diode,
wherein the first transistor comprises a first_first transistor and a first second transistor,
a first electrode of the first_first transistor is electrically connected to a first electrode of the first second transistor, and
a second electrode of the first_first transistor is electrically connected to a second electrode of the first second transistor.

US Pat. No. 10,991,787

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a display panel having a display area and a pad area, the pad area being spaced apart from the display area, wherein an image is displayed on a first surface of the display panel;
a window disposed on the first surface of the display panel;
a protective film disposed on a second surface of the display panel which is opposite to the first surface of the display panel; and
a middle layer interposed between the protective film and the second surface of the display panel,
wherein
the middle layer has a light-blocking area and a light-transmitting area,
the light-blocking area overlaps the display area,
the light-transmitting area configured to selectively transmit visible ray overlaps the pad area, and
the display panel overlaps the light-blocking area and the light-transmitting area.

US Pat. No. 10,991,786

SIGNAL CONTROL UNIT FOR AN ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

DB HITEK CO., LTD., Seou...

1. A signal control unit for an organic light emitting diode (OLED) display device comprising:a substrate structure including a plurality of active elements corresponding to each of a plurality of pixels;
first metal electrodes disposed on the substrate structure and at least one of the first metal electrodes configured to be electrically connected to a portion of each one of the plurality of active elements;
second metal electrodes disposed over the first metal electrodes such that each of the second metal electrodes is configured to be electrically connected to a corresponding one of the first metal electrodes;
via contacts extending vertically to electrically connect the first metal electrodes to the corresponding ones of the second metal electrodes; and
an interlayer insulating layer structure interposed between the first electrodes and the second electrodes and having the via contacts therein, the interlayer insulating layer structure defining a stacked structure in which a first interlayer insulating layer, a light blocking layer and a second interlayer insulating layer are stacked sequentially,
wherein the second metal electrodes are disposed on the second interlayer insulating layer, and the signal control unit further comprises a third interlayer insulating layer disposed between the second metal electrodes and arranged on the second interlayer insulating layer.

US Pat. No. 10,991,785

DOUBLE-SIDED DISPLAY PANEL, FABRICATING METHOD OF SAME, AND DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A method of fabricating a double-sided display panel, comprising:providing a base substrate and forming a thin film transistor on the base substrate;
forming a first anode on the thin film transistor;
forming a first organic layer and a first cathode on the first organic layer by vacuum evaporation or solution film formation on the first anode and the thin film transistor;
forming an interlayer insulating layer by chemical vapor deposition on the first cathode;
forming a second cathode and a second organic layer on the second cathode by vacuum evaporation on the interlayer insulating layer, and forming the second anode by vacuum sputtering, wherein the second cathode is strip-shaped, the second anode is strip-shaped, and a projection of the second anode on the second cathode is perpendicular to the second cathode.

US Pat. No. 10,991,784

TRANSISTOR DISPLAY PANEL INCLUDING LOWER ELECTRODE DISPOSED UNDER SEMICONDUCTOR AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A transistor display panel comprising:a substrate;
a lower electrode disposed on the substrate;
a buffer layer covering the lower electrode;
a transistor disposed on the substrate; and
a pixel electrode connected to the transistor,
wherein the transistor includes:
a semiconductor on the substrate,
a first insulating layer disposed on the semiconductor,
a gate electrode on the first insulating layer overlapping the semiconductor,
a connecting member disposed on the first insulating layer and connected to the semiconductor, the connecting member including a source connecting member and a drain connecting member,
a second insulating layer covering the gate electrode, the source connecting member and the drain connecting member, and
a source electrode and a drain electrode disposed on the second insulating layer,
wherein the lower electrode is disposed under the semiconductor and connected to the source connecting member,
wherein the semiconductor includes a channel, and a source region and a drain region disposed at respective sides of the channel,
wherein the source region and the drain region are respectively connected to the source connecting member and the drain connecting member,
wherein the source electrode is connected to the source connecting member, and
wherein the source connecting member is connected to the lower electrode through an opening of the buffer layer and the first insulating layer.

US Pat. No. 10,991,783

SCAN DRIVER AND DISPLAY DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A scan driver, comprising:a substrate;
a first transistor on the substrate, the first transistor comprising a first active pattern and a first gate electrode, the first active pattern comprising a first region, a second region, and a first channel region between the first region and the second region;
a second transistor on the first transistor, the second transistor comprising a second active pattern and a second gate electrode, the second active pattern comprising a third region, a fourth region, and a second channel region between the third region and the fourth region;
a first electrode and a second electrode on the second transistor, the first electrode and the second electrode electrically connected to the first region and the second region, respectively; and
a third electrode and a fourth electrode on the second transistor, the third electrode and the fourth electrode electrically connected to the third region and the fourth region, respectively,
wherein the first electrode is electrically connected to the third electrode.

US Pat. No. 10,991,782

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device comprising:a substrate having an active area and a non-active area;
a thin film transistor arranged on the active area of the substrate;
at least two planarization layers arranged on the thin film transistor;
signal links arranged on the non-active area of the substrate;
a first outer cover layer overlapping upper and side surfaces of the signal links in the non-active area;
conductive pads connected to the signal links;
a light emitting element connected to the thin film transistor; and
at least one dam arranged between the conductive pads and the light emitting element in the non-active area,
wherein the at least two planarization layers comprise:
a first planarization layer arranged on a protective film covering the thin film transistor in the active area, and
a second planarization layer arranged on the first planarization layer in the active area,
wherein the first outer cover layer is formed of a same material as the first planarization layer arranged on the protective film in the non-active area, and
the first outer cover layer is arranged between the at least one dam arranged on the protective film and the conductive pads in the non-active area.

US Pat. No. 10,991,781

DISPLAY DEVICE CONFIGURED TO SWITCH BETWEEN SINGLE-SIDED AND DOUBLE-SIDED DISPLAY

SHARP KABUSHIKI KAISHA, ...

1. A display device comprising:a plurality of pixels each including:
a light emitting element including at least a light emitting layer between a lower electrode and an upper electrode, and
a drive element electrically connected to the light emitting element; and
a first light modulating unit layer including a first light modulating layer configured to electrically switch between a light transmissive state and a light reflective state, wherein
the first light modulating unit layer, a drive element layer including a plurality of the drive elements, and a plurality of the light emitting elements are layered in the stated order,
a top-emitting single-sided display emitting light emitted from the light emitting layer from an upper electrode side and a double-sided display extracting light emitted from the light emitting layer from each of the upper electrode side and a lower electrode side are electrically switched between,
a second light modulating unit layer is further provided on the plurality of light emitting elements, the second light modulating unit layer including a second light modulating layer configured to electrically switch between a light transmissive state and a light reflective state independently of the first light modulating unit layer,
a bottom-emitting single-sided display extracting light emitted from the light emitting layer from the lower electrode side, the top-emitting single-sided display, and the double-sided display are electrically switched between,
the second light modulating unit layer and the upper electrode are layered to be adjacent to each other with an inorganic insulating film between the second light modulating unit layer and the upper electrode,
a distance between the second light modulating layer and the lower electrode is an optical path length, a peak wavelength of light in color radiated from each of the plurality of pixels resonating in the optical path length,
a sealing film is provided that covers the plurality of light emitting elements,
the sealing film includes a first inorganic sealing layer, an organic sealing layer, and a second inorganic sealing layer layered in the stated order from a light emitting element side, and
the inorganic insulating film provided between the second light modulating unit layer and the upper electrode includes the first inorganic sealing layer.

US Pat. No. 10,991,780

ARRAY SUBSTRATE AND DISPLAY DEVICE

XIAMEN TIANMA MICRO-ELECT...

14. A display device, comprising:a display panel comprising:
an array substrate, comprising:
a display area, and a non-display area surrounding the display area, wherein:
the display area comprises at least one first non-right-angled edge; and
a plurality of multi-access selectors are arranged in the non-display area proximate to the first non-right-angled edge, wherein at least one of the multi-access selectors is segmented into a plurality of electrically connected sub-units, and the sub-units are arranged in an extension direction of the first non-right-angled edge.

US Pat. No. 10,991,777

PIXEL HAVING AN ORGANIC LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE PIXEL

Ignis Innovation Inc., W...

1. A pixel comprising:an organic light emitting diode (OLED) device having a bottom electrode, one or more OLED layers and a transparent top electrode for emitting light;
a thin-film transistor (TFT) based backplane for electrically driving the OLED device, the TFT based backplane being vertically integrated with the OLED layers and located below said bottom electrode to form a top-emitting OLED, the TFT based backplane comprising source and drain nodes;
a planarization dielectric layer provided between the TFT based backplane and the OLED bottom electrode so as to planarize the vertical profile on the TFT based backplane, said planarization dielectric layer being in direct contact with both said TFT based backplane and said OLED bottom electrode;
a via in said planarization dielectric layer to provide a communication path between said TFT based backplane and said OLED device; and
a dielectric layer deposited on top of said bottom electrode and covering said via and all the edges of said bottom electrode while leaving the rest of said bottom electrode uncovered.

US Pat. No. 10,991,776

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display apparatus comprising:a substrate having a light emitting area and a non-light emitting area adjacent to the light emitting area;
a pixel defining layer on the non-light emitting area of the substrate;
a spacer on the pixel defining layer;
an auxiliary electrode on the spacer; and
an organic light emitting diode on the substrate and having at least a portion in the light emitting area,
wherein the organic light emitting diode comprises: a pixel electrode; an intermediate layer on the pixel electrode and comprising an organic light emitting layer; and an opposite electrode on the intermediate layer and electrically connected to the auxiliary electrode.

US Pat. No. 10,991,775

DISPLAY SUBSTRATE, FABRICATION METHOD THEREOF, AND DISPLAY PANEL

BOE Technology Group Co.,...

1. A display substrate, comprising:a base substrate;
a pixel defining layer, on the base substrate and configured to define a plurality of sub-pixel regions, each of the plurality of sub-pixel regions comprising a first electrode layer and a second electrode layer; and
an auxiliary electrode layer, on at least a portion of the pixel defining layer, the auxiliary electrode layer having a hydrophobic surface, and the hydrophobic surface being configured to be in contact with and electrically connected with the second electrode layer,
wherein the pixel defining layer comprises a plurality of first defining strips arranged in parallel and a plurality of second defining strips arranged in parallel, a plurality of sub-pixel regions of a same color are provided between two adjacent first defining strips of the plurality of first defining strips, a plurality of sub-pixel regions of different colors are provided between two adjacent second defining strips of the plurality of second defining strips, and a height of each of the plurality of first defining strips with respect to the base substrate is greater than a height of each of the plurality of second defining strips with respect to the base substrate,
wherein the auxiliary electrode layer comprises an auxiliary electrode strip on each of the plurality of second defining strips, and the auxiliary electrode strip covers an entire top surface of each of the plurality of second defining strips.

US Pat. No. 10,991,774

DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a display panel comprising a through-hole;
a window glass on the display panel; and
a filling member in the through-hole and opposing the window glass,
wherein the through-hole overlaps a camera module that includes at least one lens,
the filling member opposes the camera module,
a refractive index difference between an end portion of the filling member and a lens of the at least one lens is about 0.7 or less, and
a refractive index difference between another end portion of the filling member and the window glass is about 0.5 or less, and
wherein the display panel comprises:
a substrate; and
a pixel circuit unit on the substrate and comprising a first hole;
the substrate comprises: a first layer comprising a depression corresponding to the first hole; and a second layer between the first layer and the pixel circuit unit and comprising a second hole defined between the depression and the first hole, and
the depression has a width larger than a width of the second hole.

US Pat. No. 10,991,773

DISPLAY PANEL WITH LIGHT-EMITTING FUNCTIONAL UNITS, DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY PANEL

Xiamen Tianma Micro-Elect...

1. A display panel, having a first display region and a second display region, wherein the display panel comprises:a base;
an array portion located on the base; and
a light-emitting functional portion located on a side of the array portion facing away from the base, the light-emitting functional portion comprising an Active Matrix Organic Light Emitting Diode (AMOLED) light-emitting unit and a Passive Matrix Organic Light Emitting Diode (PMOLED) light-emitting unit,
wherein the AMOLED light-emitting unit is located in the first display region, the PMOLED light-emitting unit is located in the second display region, and the second display region is surrounded or partially surrounded by the first display region,
wherein the AMOLED light-emitting unit comprises a first anode and a first cathode, the PMOLED light-emitting unit comprises a second anode and a second cathode, and the second anode of the PMOLED light-emitting unit has an area smaller than an area of the first anode of the AMOLED light-emitting unit;
wherein the display panel further comprises a transparent carrier substrate located on a side of the light-emitting functional portion facing away from the base, and the PMOLED light-emitting unit has at least one film layer carried by the transparent carrier substrate, and
wherein an auxiliary conductive layer is provided on a side of the transparent carrier substrate facing the base, and the auxiliary conductive layer contacts the first cathode of the AMOLED light-emitting unit and is isolated from the second cathode or the second anode of the PMOLED light-emitting unit.

US Pat. No. 10,991,772

TOUCH DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A touch display panel, comprising:a thin-film transistor substrate comprising a thin-film transistor;
a pixel defining layer disposed on the thin-film transistor substrate and comprising a first opening;
a light emitting structure disposed in the first opening;
a thin film encapsulation layer covering the light emitting structure and the pixel defining layer;
a first metal pattern disposed on the thin film encapsulation layer;
a first insulation pattern disposed on the first metal pattern and having a plane area the same as or smaller than that of the first metal pattern;
a second metal pattern disposed on the first insulation pattern; and
a second insulation layer disposed on the second metal pattern and the thin film encapsulation layer, and contacting the first metal pattern, the first insulation pattern, and the second metal pattern.

US Pat. No. 10,991,771

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a window comprising a light shielding pattern and a base layer, the base layer comprising a light shielding region in which the light shielding pattern is disposed and a transmission region adjacent to the light shielding region;
a display panel disposed under the window; and
an input detection sensor disposed between the window and the display panel, the input detection sensor having a wiring region corresponding to the light shielding region and a sensing region corresponding to the transmission region,
wherein the input detection sensor comprises:
a first electrode group comprising first to ith electrodes (where “i” is a natural number equal to or greater than 2) arranged in a first direction away from a pad region defined on one side of the light shielding region and extending in a second direction intersecting the first direction;
a second electrode group comprising first to jth electrodes (where “j” is a natural is number equal to or greater than 2) intersecting with the electrodes of the first electrode group;
a first signal line group comprising first to ith signal lines electrically connected to the first to ith electrodes of the first electrode group; and
a second signal line group comprising first to jth signal lines electrically connected to the first to jth electrodes of the second electrode group,
wherein each of the first to nth signal lines (where “n” is a natural number less than i) of the first signal line group comprises:
a first part extending from the pad region in the first direction;
a second part connected to a corresponding electrode of the first electrode group; and
a third part disposed between the pad region and the sensing region, having a shape bent multiple times, and connecting the first part to the second part,
wherein the third part of the first signal line of the first signal line group has a greater length and higher resistance than the third part of the nth signal line of the first signal line group, and
wherein at least a portion of the first to nth signal lines of the first signal line group overlap the light shielding pattern in a planar view.

US Pat. No. 10,991,770

DISPLAY DEVICE WITH DISPLAY PORTION, LIGHT SENSING PORTION, AND CONNECTION BENDING PORTION

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate comprising a display portion, a light sensing portion, and a connection portion located between the display portion and the light sensing portion;
pixel transistors disposed at the display portion;
light sensor transistors disposed at the light sensing portion;
a driving integrated circuit disposed at the connection portion and applying a driving signal to each of the pixel transistors and the light sensor transistors; and
an organic light emitting element disposed at the display portion,
wherein the connection portion is bent, and by bending of the connection portion, the light sensing portion overlaps the display portion and at least one of the light sensor transistors is disposed overlapping the display portion
the light sensor transistors comprise a light sensor driving transistor and a light sensor switching transistor,
the organic light emitting element comprises a pixel electrode, and
at least one of the light sensor driving transistors disposed overlapping the display portion does not overlap the pixel electrode.

US Pat. No. 10,991,769

DISPLAY APPARATUS HAVING A COLOR FILTER LAYER

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a base layer comprising an emission area and a non-emission area adjacent to the emission area;
a circuit element layer disposed on the base, layer;
a display element layer disposed on the circuit element layer, the display element layer including an organic light emitting diode;
an encapsulation layer disposed on the display element layer and configured to encapsulate the organic light emitting diode; and
a color filter layer disposed in the encapsulation layer and in direct contact with a bottommost layer of the encapsulation layer,
wherein the color filter layer includes a color shielding layer having a plurality of layers disposed in the non emission area and a color filter disposed in the emission area.

US Pat. No. 10,991,768

PIXEL ARRANGEMENT, MANUFACTURING METHOD THEREOF, DISPLAY PANEL, DISPLAY DEVICE, AND MASK

BOE TECHNOLOGY GROUP CO.,...

1. A pixel arrangement comprising:a plurality of first groups of sub-pixels arranged in a first direction, each of the plurality of first groups comprising first ones of a plurality of first sub-pixels and first ones of a plurality of third sub-pixels arranged alternately; and
a plurality of second groups of sub-pixels arranged in the first direction, each of the plurality of second groups comprising second ones of the plurality of third sub-pixels and first ones of a plurality of second sub-pixels arranged alternately,
wherein the plurality of first groups and the plurality of second groups are alternately arranged in a second direction intersecting the first direction,
wherein the plurality of first groups and the plurality of second groups are arranged to form a plurality of third groups of sub-pixels arranged in the second direction and a plurality of fourth groups of sub-pixels arranged in the second direction,
wherein the plurality of third groups and the plurality of fourth groups are alternately arranged in the first direction,
wherein each of the plurality of third groups comprises second ones of the plurality of first sub-pixels and third ones of the plurality of third sub-pixels arranged alternately,
wherein each of the plurality of fourth groups comprises fourth ones of the plurality of third sub-pixels and second ones of the plurality of second sub-pixels arranged alternately, and
wherein the first ones and the second ones of the third sub-pixels in the plurality of first and second groups comprise at least one configuration selected from a group consisting of:
(i) each of the third sub-pixels in each first group of the plurality of first groups having a first minimum distance from one of two first sub-pixels, directly adjacent thereto, of the first sub-pixels in the first group and a second minimum distance from another of the two first sub-pixels, directly adjacent thereto, of the first sub-pixels in the first group, the first minimum distance being not equal to the second minimum distance; and
(ii) each of the third sub-pixels in each second group of the plurality of second groups having a third minimum distance from one of two second sub-pixels, directly adjacent thereto, of the second sub-pixels in the second group and a fourth minimum distance from another of the two second sub-pixels, directly adjacent thereto, of the second sub-pixels in the second group, the third minimum distance being not equal to the fourth minimum distance.

US Pat. No. 10,991,767

DISPLAY PANEL AND DISPLAY APPARATUS

SHANGHAI TIANMA AM-OLED C...

1. A display panel having a first display region and a second display region, the display panel comprisinga sub-pixel array comprising a plurality of sub-pixels arranged in an array; and
gate signal lines extending in a first direction and data lines extending in a second direction, the first direction intersecting with the second direction,
wherein the plurality of sub-pixels is distributed in the first display region and the second display region,
wherein a non-light-emitting region in the second display region has a greater light transmittance than a non-light-emitting region in the first display region,
wherein a distribution density of sub-pixels of the plurality of sub-pixels in the second display region is smaller than a distribution density of sub-pixels of the plurality of sub-pixels in the first display region,
wherein among sub-pixels emitting a same color of the plurality of sub-pixels in the first display region and the second display region, a light-emitting area of a sub-pixel in the second display region is larger than a light-emitting area of a sub-pixel in the first display region, and
wherein among the sub-pixels emitting the same color of the plurality of sub-pixels in the first display region and the second display region, a width in the first direction of a sub-pixel in the second display region is R1 times a width in the first direction of a sub-pixel in the first display region, and a width in the second direction of a sub-pixel in the second display region is R2 times a width in the second direction of a sub-pixel in the first display region; and a ratio of a center-to-center distance between two adjacent sub-pixels in the first direction in the second display region to a center-to-center distance between two adjacent sub-pixels in the first direction in the first display region is R3, and a ratio of a center-to-center distance between two adjacent sub-pixels in the second direction in the second display region to a center-to-center distance between two adjacent sub-pixels in the second direction in the first display region is R4, where 0.8?(R1×R2)/(R3×R4)?1.2.

US Pat. No. 10,991,766

ELECTRONIC DEVICE

InnoLux Corporation, Mia...

1. An electronic device, comprising:a first electronic unit emitting a blue light having a first spectrum, and the first spectrum having a first intensity, wherein the first intensity is a maximum intensity of the first spectrum; and
a second electronic unit emitting a light having a second spectrum different from the first spectrum, and the second spectrum having a second intensity in a range from 300 nm to 460 nm, wherein the second intensity is a maximum intensity in the range from 300 nm to 460 nm of the second spectrum;
wherein a ratio of the second intensity to the first intensity is in a range from 0.06% to 10.0%.

US Pat. No. 10,991,764

PHOTODETECTOR ARRAY

SIGNTLE INC., Tokyo (JP)...

1. A photodetector array having a stacked film,the stacked film comprising
a plurality of first electrodes formed on a substrate and extending in parallel in a first direction,
a plurality of second electrodes extending in parallel in a second direction crossing the first electrodes,
a first organic thin film diode and a second organic thin film diode disposed between each of the first electrodes and each of the second electrodes, and
an intermediate connection electrode layer serving as a common anode or a common cathode, the intermediate connection electrode layer connecting the first organic thin film diode and the second organic thin film diode by backward-diode connection,
wherein at least either the first electrodes or the second electrodes are transparent with light passing therethrough,
the first organic thin film diode is a photoresponsive organic diode,
the second organic thin film diode is an organic rectifier diode, and
the intermediate connection electrode layer operates so that, with respect to the first organic thin film diode and the second organic thin film diode connected thereto, positive holes are transferred as the common anode and electrons are transferred as the common cathode.

US Pat. No. 10,991,763

VERTICAL ARRAY OF RESISTIVE SWITCHING DEVICES HAVING RESTRICTED FILAMENT REGIONS AND TUNABLE TOP ELECTRODE VOLUME

INTERNATIONAL BUSINESS MA...

1. A vertical resistive device comprising:a horizontal plate comprising a conductive electrode region and a filament region;
an opening extending through the filament region and defined by sidewalls of the filament region, wherein the filament region is positioned outside of the opening; and
a pillar positioned within the opening and communicatively coupled to the filament region,
wherein the pillar comprises a reactive electrode and a metal fill material.

US Pat. No. 10,991,762

MEMORY UNIT

Sony Semiconductor Soluti...

1. A memory unit comprising:a memory cell array; and
a driving circuit that accesses the memory cell array,
the memory cell array including
pluralities of first wiring lines that extend in a first direction, and are disposed to be aligned in a second direction orthogonal to the first direction and in a third direction orthogonal to the first direction and the second direction,
a plurality of second wiring lines that extends in the first direction, and is disposed to be aligned in the second direction,
pluralities of third wiring lines that extend in the third direction, and are disposed to be aligned in the first direction and in the second direction, and are also disposed to go through a gap between two first wiring lines adjacent to each other in the second direction when viewed from the third direction,
a plurality of resistance-varying memory cells, one memory cell being provided at each of respective points at which the third wiring lines and the first wiring lines are opposed to each other,
a plurality of transistors each having a gate coupled to the corresponding second wiring line, one transistor being provided for each of the third wiring lines, and
a plurality of fourth wiring lines that extends in the second direction, and is disposed to be aligned in the first direction, one fourth wiring line being provided for multiple third wiring lines disposed to be aligned in the second direction, and each of the fourth wiring lines being coupled to the corresponding multiple third wiring lines through the transistors,
wherein when, of the plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, the memory cell array allows for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring lines shared by the first memory cells.

US Pat. No. 10,991,761

THREE-DIMENSIONAL CROSS-POINT MEMORY DEVICE CONTAINING INTER-LEVEL CONNECTION STRUCTURES AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A memory device, comprising:a vertical stack including first electrically conductive lines, a two-dimensional array of first pillar structures, second electrically conductive lines, a two-dimensional array of second pillar structures, third electrically conductive lines, a two-dimensional array of third pillar structures, fourth electrically conductive lines, a two-dimensional array of fourth pillar structures, and fifth electrically conductive lines, wherein each of the first pillar structures, the second pillar structures, the third pillar structures, and the fourth pillar structures comprises a respective memory element; and
interconnection structures providing electrically conductive paths between the fifth electrically conductive lines and the first electrically conductive lines, wherein each of the interconnection structures comprises a vertical stack of a first conductive via structure contacting a respective one of the first electrically conductive lines, a conductive pad structure contacting a top surface of the first conductive via structure, and a second conductive via structure contacting the conductive pad structure and a respective one of the fifth electrically conductive lines,
wherein:
the first electrically conductive lines, the third electrically conductive lines, and the fifth electrically conductive lines laterally extend along the first horizontal direction;
the second electrically conductive lines and the fourth electrically conductive lines laterally extend along a second horizontal direction;
the first electrically conductive lines have a first pitch along the second horizontal direction that is perpendicular to the first horizontal direction;
the conductive pad structures have a second pitch along the second horizontal direction;
the second pitch is the first pitch times an integer N that is greater than 1; and
each of the conductive pad structures has a pad width along the second horizontal direction, wherein the pad width is greater than the first pitch.

US Pat. No. 10,991,760

MEMORY DEVICE HAVING PUC STRUCTURE

SK hynix Inc., Gyeonggi-...

1. A memory device comprising:first and second peripheral regions in which peripheral circuits related to data input/output are disposed;
a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed; and
a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed,
wherein the dummy cell region includes: a plurality of dummy word lines extended in a first direction and arranged in a second direction; and a plurality of dummy bit lines extended in the second direction and arranged in the first direction, wherein the plurality of dummy cells are coupled between the dummy word lines and the dummy bit lines, and
wherein the plurality of dummy word lines include:
odd-numbered dummy word lines coupled to a first power supply voltage terminal; and
even-numbered dummy word lines coupled to a second power supply voltage terminal, wherein the capacitors are formed between the odd-numbered dummy word lines and the even-numbered dummy word lines.

US Pat. No. 10,991,759

METHODS OF FORMING VERTICAL FIELD-EFFECT TRANSISTOR WITH SELFALIGNED CONTACTS FOR MEMORY DEVICES WITH PLANAR PERIPHERY/ARRAY AND INTERMEDIATE STRUCTURES FORMED THEREBY

Micron Technology, Inc., ...

15. A memory device, comprising:a peripheral circuit transistor formed on a substrate in a first region;
an array transistor formed on the substrate in a second region, the array transistor having a self-aligned contact that extends to a first width within a volume that is self-aligned with a pillar of the array transistor;
a confined phase change memory cell comprising a phase change material that extends to a second width less than the first width confined within the volume and in direct contact with the self-aligned contact of the array transistor, the volume comprising the first width, a length, and a height that extends from a bottom surface of the array transistor to an upper surface of the phase change material; and
a dielectric portion over at least the first region, the dielectric portion including an upper surface that is coplanar with the upper surface of the phase change material.

US Pat. No. 10,991,758

SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a bottom electrode via (BEVA) in a dielectric layer, comprising:
a lining layer over a bottom and a sidewall of a trench of the BEVA; and
a copper layer over the lining layer, filling the trench of the BEVA;
a recap layer on the BEVA; and
a bottom electrode on the recap layer;
a magnetic tunneling junction (MTJ) layer over the recap layer and vertically aligning with the BEVA;
wherein the copper layer and the lining layer jointly have a dimpled structure with a top surface lower than a top surface of the dielectric layer, and the recap layer overlaps a top surface of the lining layer, an entire top surface of the copper layer, and a portion of the dielectric layer adjacent to the lining layer.

US Pat. No. 10,991,757

MAGNETORESISTIVE RANDOM ACCESS MEMORY

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate having a magnetic tunneling junction (MTJ) region and a logic region;
a magnetic tunneling junction (MTJ) on the MTJ region, wherein a top view of the MTJ comprises a circle; and
a first metal interconnection on the MTJ, wherein a top view of the first metal interconnection comprises a flat oval overlapping the circle and an edge of the circle contacts an edge of the flat oval directly.

US Pat. No. 10,991,756

BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES

Taiwan Semiconductor Manu...

1. A memory cell comprising:a data-storage element having a variable resistance; and
a bipolar selector electrically coupled in series with the data-storage element, wherein the bipolar selector comprises a first unipolar selector and a second unipolar selector, wherein the first and second unipolar selectors are electrically coupled in parallel with opposite orientations, and wherein the bipolar selector has different threshold voltages respectively at opposite polarities;
wherein the data-storage element comprises a magnetic tunnel junction (MTJ), wherein the MTJ comprises a reference ferromagnetic element and a free ferromagnetic element, wherein the free ferromagnetic element is electrically separated from the bipolar selector by the reference ferromagnetic element, wherein the reference ferromagnetic element is electrically separated from an anode of the first unipolar selector by a cathode of the first unipolar selector, and wherein a threshold voltage of the first unipolar selector is less than a threshold voltage of the second unipolar selector.

US Pat. No. 10,991,755

SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS

D-WAVE SYSTEMS INC., Bur...

1. A quantum computer comprising an integrated circuit, the integrated circuit comprising:a substrate;
a quantum device comprising a loop of superconducting material interrupted by a Josephson junction, the Josephson junction comprising a Josephson junction trilayer overlying the substrate;
a superconducting wiring layer overlying the Josephson junction trilayer, the superconducting wiring layer which comprises material that is superconductive at or below a critical temperature;
a passivating layer overlying the superconducting wiring layer; and
a cap overlying the Josephson junction trilayer.

US Pat. No. 10,991,754

DISPLAY DEVICE WITH STACKING DESIGN OF SENSING ELEMENT

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a display panel, comprising:
a first substrate;
a first transistor disposed on the first substrate;
a sensing element disposed on the first substrate and electrically connected to the first transistor, wherein the sensing element comprises:
a first-type semiconductor layer;
an insulation layer disposed on the first-type semiconductor layer; and
a second-type semiconductor layer disposed on the insulation layer;
a first conductive layer disposed between the first substrate and the sensing element, the first conductive layer contacting with and electrically connected to the first-type semiconductor layer; and
a second conductive layer disposed on the sensing element, the second conductive layer contacting with and electrically connected to the second-type semiconductor layer;
wherein the first conductive layer, the second conductive layer and the insulation layer are stacked to form a storage capacitor, and the storage capacitor shares the insulation layer with the sensing element.

US Pat. No. 10,991,753

IMAGING DEVICE AND ELECTRONIC DEVICE

Sony Semiconductor Soluti...

1. An imaging device, comprising:a photoelectric conversion part configured to convert received light into a charge;
a holding part configured to hold a charge transferred from the photoelectric conversion part; and
a light shielding part configured to shield light between the photoelectric conversion part and the holding part,
wherein the photoelectric conversion part, the holding part, and the light shielding part are formed in a semiconductor substrate having a predetermined thickness,
wherein the light shielding part of a transfer region that transfers the charge from the photoelectric conversion part to the holding part is formed as a non-penetrating light shielding part that does not penetrate the semiconductor substrate,
wherein the light shielding part other than the transfer region is formed as a penetrating light shielding part that penetrates the semiconductor substrate, and
wherein the holding part is disposed at a position shifted by a half pitch with respect to the photoelectric; conversion part such that a transfer control gate that controls the transfer of the charge from the photoelectric conversion part to the holding part is formed between the photoelectric conversion part and another photoelectric conversion part adjacent to the photoelectric conversion part in a vertical direction.

US Pat. No. 10,991,751

PRINT SENSOR WITH GALLIUM NITRIDE LED

1. A papillary print sensor, comprising:a light emitting device and a matrix photodetector interlaced together in a same semiconducting substrate and/or above a surface of the same semiconducting substrate,
the light emitting device being oriented in and/or above the surface of the same semiconducting substrate such that the light emitting device is configured to emit light radiation towards a contact surface of the papillary print sensor along an axis orthogonal to the contact surface,
the matrix photodetector being sensitive to at least part of an emission spectrum of the light emitting device, and being oriented in and/or above the surface of the same semiconducting substrate such that the matrix photodetector is configured to detect light radiation backscattered through the contact surface,
wherein the light emitting device is composed of at least one gallium nitride light emitting diode (LED),
wherein the matrix photodetector extends on a capture surface of the papillary print sensor, and
wherein the light emitting device occupies a surface area on the semiconducting substrate equal to at least ten times less than a surface area occupied by the matrix photodetector.

US Pat. No. 10,991,750

ACTIVE MATRIX SUBSTRATE AND IMAGING PANEL WITH SAME

SHARP KABUSHIKI KAISHA, ...

1. An active matrix substrate comprising:a substrate;
a photoelectric conversion element provided on the substrate;
a first planarizing film that covers the photoelectric conversion element and has a first opening at a position at which the first opening overlaps with the photoelectric conversion element in plan view;
a first inorganic insulating film that has a second opening inside the first opening and covers a surface of the first planarizing film; and
a bias wire provided on the first inorganic insulating film and connected to the photoelectric conversion element via the second opening.

US Pat. No. 10,991,749

STRUCTURE, COMPOSITION FOR FORMING NEAR-INFRARED TRANSMITTING FILTER LAYER, AND OPTICAL SENSOR

FUJIFILM Corporation, To...

1. A structure comprising:a support;
a partition wall provided on the support; and
a near-infrared transmitting filter layer provided in a region partitioned by the partition wall, that shields visible light and transmits at least a portion of near-infrared light,
wherein the refractive index of the partition wall is smaller than the refractive index of the near-infrared transmitting filter layer structure at at least a portion of the wavelengths of the near-infrared light transmitted by the near-infrared transmitting filter layer, and
wherein the partition wall includes at least one selected from silica particles, a siloxane resin, a fluorine resin, or silicon dioxide.

US Pat. No. 10,991,748

3D IMAGE SENSOR

Samsung Electronics Co., ...

1. A three-dimensional (3D) image sensor comprising:a first substrate including an upper pixel, the upper pixel including a photoelectric element and first and second photogates connected to the photoelectric element;
a second substrate including a lower pixel, which corresponds to the upper pixel, and spaced apart from the first substrate in a vertical direction, the lower pixel including a first transfer transistor transmitting a first signal provided by the first photogate, a first source follower generating a first output signal in accordance with the first signal, a second transfer transistor transmitting a second signal provided by the second photogate, and a second source follower generating a second output signal in accordance with the second signal; and
first and second bonding conductors disposed between the first and second substrates and electrically connecting the upper and lower pixels.

US Pat. No. 10,991,747

IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

1. An image sensor structure, comprising:a substrate having a front side and a backside;
a light-sensing region formed in the substrate;
a front side isolation structure surrounding the light sensing region and having an opening region in a top view;
a backside isolation structure formed at the backside of the substrate and encompassing the light-sensing region and vertically overlapping the opening region;
a first gate structure formed over the front side of the substrate and overlapping the opening region and the front side isolation structure; and
a storage node in the substrate adjacent to the first gate structure,
wherein the storage node extends into the opening region.

US Pat. No. 10,991,746

HIGH PERFORMANCE IMAGE SENSOR

Taiwan Semiconductor Manu...

1. An integrated chip, comprising:an image sensing element disposed within a pixel region of a substrate;
a plurality of conductive interconnect layers disposed within a dielectric structure arranged along a first side of the substrate;
wherein a second side of the substrate comprises a plurality of interior surfaces arranged directly over the image sensing element, the plurality of interior surfaces respectively comprising a substantially flat surface that extends along a plane; and
an isolation region disposed between the pixel region and an adjacent pixel region, the isolation region defined by an upper surface of the substrate that extends in an unbroken loop surrounding the pixel region and arranged along a horizontal plane that is vertically separated from tops of the plurality of interior surfaces by one or more non-zero distances.

US Pat. No. 10,991,745

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A semiconductor device, comprising:a device substrate including a device region and a peripheral region, wherein a wiring layer and a first semiconductor layer including a compound semiconductor material are stacked in the device region, and wherein the peripheral region is disposed outside the device region;
a second semiconductor layer that is stacked on the device substrate, wherein the second semiconductor layer includes a photodiode; and
a readout circuit substrate that faces the first semiconductor layer, wherein the wiring layer is between the readout circuit and the first semiconductor layer, and wherein the readout circuit is electrically coupled to the first semiconductor layer through the wiring layer, and
wherein the peripheral region of the device substrate includes a junction surface with the readout circuit substrate.

US Pat. No. 10,991,744

IMAGE SENSORS COMPRISING ARRAYS OF PHOTOSENSITIVE ELEMENTS SEPARATED BY A NON-PHOTOSENSITIVE INTERVENING REGION

Alentic Microscience Inc....

1. A method comprisingsituating a sample on a sample surface of a large-area high-aspect-ratio integral image sensor, the sensor comprising two arrays of photosensitive elements arranged to receive light passing through the sample and onto the sample surface, the two arrays being separated by a non-photosensitive intervening region of the sensor,
the sample including portions situated on the two arrays and a portion situated on the non-photosensitive intervening region of the sample surface,
storing data about light received at the two arrays after passing through the sample, without regard to light received at the non-photosensitive intervening region,
processing the stored data to derive information about one or more constituents of the sample, and
treating the derived information as representative of the one or more constituents of the portions of the sample situated on the two arrays and the portion of the sample situated on the non-photosensitive intervening region of the sample surface.

US Pat. No. 10,991,742

IMAGE SENSORS

Samsung Electronics Co., ...

1. An image sensor, comprising:a semiconductor substrate having a first surface and a second surface;
a pixel element isolation film extending through an interior of the semiconductor substrate between the first and second surfaces of the semiconductor substrate and defining a plurality of active pixels in the semiconductor substrate; and
a dummy element isolation film extending through the interior of the semiconductor substrate between the first and second surfaces of the semiconductor substrate and extending along at least one side of the active pixels in a plan view and defining a plurality of dummy pixels in the semiconductor substrate,
wherein the pixel element isolation film has a first end that is substantially coplanar with the first surface, the first end of the pixel element isolation film having a first width in a first direction parallel to the first surface, and the dummy element isolation film has a first end that is substantially coplanar with the first surface, the first end of the dummy element isolation film having a second width that is greater than the first width of the pixel element isolation film.

US Pat. No. 10,991,741

PHOTOELECTRIC CONVERSION APPARATUS AND EQUIPMENT

Canon Kabushiki Kaisha, ...

1. A photoelectric conversion apparatus comprising:a semiconductor layer including a plurality of photoelectric conversion portions and a main face forming respective light receiving faces of the plurality of photoelectric conversion portions,
wherein the plurality of photoelectric conversion portions includes a first photoelectric conversion portion, a second photoelectric conversion portion and a third photoelectric conversion portion,
wherein the semiconductor layer has a first trench positioned between the first photoelectric conversion portion and the second photoelectric conversion portion, a second trench positioned between the second photoelectric conversion portion and the third photoelectric conversion portion,
wherein the first trench and the second trench each continuously extend on the main face,
wherein a silicon compound film that is any one of a silicon oxide film, a silicon nitride film, and a silicon carbide film and a metal compound film lying between the silicon compound film and the semiconductor layer are provided above the main face,
wherein the silicon compound film and the metal compound film extend into the first trench,
wherein the metal compound film extends into the second trench, and
wherein the following conditions are satisfied:
Hd Wa?2×Hd>Wb,
where a distance from a bottom of the second trench to the silicon compound film is expressed as Hb, a distance from the main face to the silicon compound film is expressed as Hd, a width of the first trench is expressed as Wa, and a width of the second trench is expressed as Wb.

US Pat. No. 10,991,740

NARROW BAND FILTER WITH HIGH TRANSMISSION

Taiwan Semiconductor Manu...

1. A method for forming an image sensor, the method comprising:forming a photodetector in a substrate;
depositing an isolation layer overlying the substrate and the photodetector;
depositing a first multilayer film on the isolation layer, wherein the first multilayer film comprises a plurality of first layers and a plurality of second layers, and wherein the first layers are alternatingly stacked with the second layers and share a first refractive index that is different than a second refractive index shared by the second layers;
depositing a defect layer on the first multilayer film; and
performing an etch into the defect layer and the first multilayer film to form a plurality of columnar cavities, wherein the columnar cavities overlie the photodetector and extend completely through the defect layer and the first multilayer film to expose the isolation layer, and wherein the columnar cavities are in a periodic pattern;
wherein the isolation layer is a different type of material than each of the first layers and each of the second layers.

US Pat. No. 10,991,739

NARROW BAND FILTER WITH HIGH TRANSMISSION

Taiwan Semiconductor Manu...

1. An image sensor comprising:an optical filter comprising:
a first distributed Bragg reflector (DBR) alternating between a first refractive material type and a second refractive material type from a bottom surface of the first DBR to a top surface of the first DBR;
a second DBR over the first DBR;
an interlayer between the first and second DBRs; and
a plurality of columnar structures extending through the interlayer,
wherein the columnar structures are in a first periodic pattern and have a refractive index different than a refractive index of the interlayer; and
an isolation layer under the first DBR, wherein the isolation layer is a different type of material than the first and second refractive material types;
wherein the columnar structures further extend through the first DBR to direct contact with the isolation layer.

US Pat. No. 10,991,737

SOLID-STATE IMAGING DEVICE AND IMAGE SENSOR FOR SUPPRESSING OR PREVENTING LEAKING OF LIGHT INTO ADJOINING PIXELS

Mitsubishi Electric Corpo...

1. A solid-state imaging device, comprising:a red photoelectric conversion element to receive and convert red light to electric signals;
a green photoelectric conversion element to receive and convert green light to electric signals;
a blue photoelectric conversion element to receive and convert blue light to electric signals;
an infrared photoelectric conversion element to receive and convert infrared light to electric signals, wherein the red, green, blue, and infrared photoelectric conversion elements are disposed on a semiconductor substrate;
an infrared cut filter layered on the red photoelectric conversion element, the green photoelectric conversion element with a uniform film thickness, and the blue photoelectric conversion element, the infrared cut filter cutting infrared light;
a red filter layered on the infrared cut filter that is above the red photoelectric conversion element, the red filter transmitting light of red wavelengths;
a green filter layered on the infrared cut filter that is above the green photoelectric conversion element, the green filter transmitting light of green wavelengths;
a blue filter layered on the infrared cut filter that is above the blue photoelectric conversion element, the blue filter transmitting light of blue wavelengths;
a visible-light shielding filter layered on the infrared photoelectric conversion element, the visible-light shielding filter transmitting infrared light and shielding red light, green light, and blue light;
an ultraviolet cut filter layered between (i) the red photoelectric conversion element; the green photoelectric conversion element, and the blue photoelectric conversion element and (ii) the infrared cut filter and between (iii) the infrared photoelectric conversion element and (iv) the visible-light shielding filter with a uniform film thickness, the ultraviolet cut filter transmitting infrared light and visible light and cutting ultraviolet light; and
a passivation film formed on a surface of the semiconductor substrate,
wherein the passivation film is eliminated in an area above the red, green, blue, and infrared photoelectric conversion elements, thereby exposing the red filter, the green filter, the blue filter, and the visible-light shielding filter.

US Pat. No. 10,991,736

METHOD OF PRODUCING SOLID-STATE IMAGING DEVICE HAVING COLOR FILTERS, SOLID-STATE IMAGING DEVICE HAVING COLOR FILTERS, METHOD OF PRODUCING COLOR FILTER DEVICE COMPRISING COLOR FILTERS, AND COLOR FILTER DEVICE COMPRISING COLOR FILTERS

TOPPAN PRINTING CO., LTD....

1. A method of producing a solid-state imaging device, comprising:applying, on a semiconductor substrate, a first color filter material comprising a first pigment and a resin material;
curing the first color filter material such that a first color filter film is formed on the semiconductor substrate;
forming a photosensitive resin mask material layer on the first color filter film;
forming a plurality of openings by photolithography in the photosensitive resin mask material layer such that portions of the first color filter film are exposed by the openings;
dry-etching the portions of the first color filter film by using a dry etching gas and the photosensitive resin mask material layer as an etching mask such that a first color filter having a plurality of openings is formed on the semiconductor substrate;
removing the etching mask from the first color filter formed on the semiconductor substrate;
forming, in a group of the plurality of openings, a second color filter comprising a second pigment that is different from the first pigment;
forming, in another group of the plurality of openings, a third color filter comprising a third pigment that is different from the first and second pigments; and
forming a plurality of microlenses on the first, second and third color filters such that the plurality of microlenses collects incident light to a plurality of photoelectric conversion elements that are two-dimensionally arrayed in the semiconductor substrate,
wherein the dry-etching comprises controlling a reaction of the first color filter material with the dry etching gas such that the reaction produces a reaction product of the first color filter material reacted with the dry etching gas and that the reaction product forms a barrier layer formed on side walls of the first color filter in the plurality of openings in the first color filter and having a pattern surrounding the first color filter.

US Pat. No. 10,991,735

OPTICAL DETECTION PIXEL UNIT, OPTICAL DETECTION CIRCUIT, OPTICAL DETECTION METHOD AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An optical detection method for an optical detection pixel unit, the optical detection pixel unit consisting of a photosensitive element and a detection transistor, whereinthe photosensitive element has a first electrode connected with a photovoltage terminal, and a second electrode connected with a gate of the detection transistor; and
the detection transistor has a first electrode connected with a detection voltage line, and a second electrode connected with a reading line;
wherein the photosensitive element is a photodiode; and an anode of the photodiode is the first electrode of the photosensitive element, and a cathode of the photodiode is the second electrode of the photosensitive element,
the method comprising a reset stage, an integration stage and a reading stage sequentially in each detection cycle, wherein:
in the reset stage, resetting a potential of the gate of the detection transistor;
in the integration stage, providing a first detection voltage for the detection voltage line to turn off the detection transistor, and providing a first photovoltage for the photovoltage terminal so as to enable the photosensitive element to convert an optical signal received by the photosensitive element into a corresponding current signal; and
in the reading stage, providing a second detection voltage for the detection voltage line to control the detection transistor to operate in a saturation status.

US Pat. No. 10,991,734

IMAGING DEVICE AND ELECTRONIC DEVICE

Sony Semiconductor Soluti...

1. An imaging device comprising:a photoelectric conversion part configured to convert received light into a charge;
a holding part configured to hold a charge transferred from the photoelectric conversion part;
a charge capturing region configured to capture a charge on a light incident side of a region where the holding part is formed; and
a discharge drain configured to discharge a charge from the charge capturing region,
wherein the photoelectric conversion part and the holding part are formed in a semiconductor substrate having a predetermined thickness,
wherein the holding part is formed with a thickness that is half or less of the predetermined thickness, and
wherein an overflow path from the charge capturing region to the discharge drain is formed in a region of a light shielding part, and
wherein the light shielding part does not penetrate the semiconductor substrate.

US Pat. No. 10,991,733

IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME

UNITED MICROELECTRONICS C...

1. An image sensor comprising:a substrate;
a photodiode formed in the substrate and in a pixel region;
a plurality of storage devices formed in the substrate and adjacent to the photodiode;
a plurality of deep trench isolation walls penetrating whole through the substrate to isolate the photodiode and the storage devices;
a circuit layer disposed on a first surface of the substrate and connected to the photodiode and the storage devices;
a shielding structure disposed on a second surface of the substrate to shield the storage devices;
a material layer disposed above the second surface of the substrate; and
a lens disposed on the material layer and configured to receive incident light and transmit the incident light to the photodiode.

US Pat. No. 10,991,732

DEVICE INCLUDING ELEMENT HAVING RECTIFICATION CHARACTERISTICS AND THIN FILM TRANSISTOR

TIANMA JAPAN, LTD., Kana...

1. A device comprising:a first element having rectification characteristics that allow electric current to flow from an upper electrode to a lower electrode;
an n-channel thin film transistor including a semiconductor film, a gate electrode, a first signal electrode, and a second signal electrode; and
a control electrode facing the gate electrode with the semiconductor film interposed therebetween,
wherein the second signal electrode is connected with the lower electrode,
wherein the control electrode is connected with the lower electrode,
wherein at least a part of a first channel end on the first signal electrode side of the semiconductor film is located within a region of the control electrode, when viewed planarly,
wherein a second channel end on the second signal electrode side of the semiconductor film is distant from the control electrode, when viewed planarly, and
wherein the first channel end and the second channel end of the semiconductor film are disposed between distal ends of the gate electrode, when viewed planarly.

US Pat. No. 10,991,731

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductive film;
a first insulating film in contact with a top surface and a side surface of the first conductive film;
a first oxide semiconductor film in contact with a top surface of the first insulating film, the first oxide semiconductor film containing indium, gallium and zinc;
a second insulating film in contact with a top surface and a side surface of the first oxide semiconductor film;
a third conductive film in contact with a top surface of the second insulating film;
a first region in which the third conductive film is in contact with the top surface of the first oxide semiconductor film in a first opening provided in the second insulating film; and
a second region in which the third conductive film is in contact with the top surface of the first conductive film in a second opening provided in the first insulating film and the second insulating film,
wherein the first region overlaps with the first conductive film, and
wherein a side surface of the second opening is stepwise in a cross sectional view.

US Pat. No. 10,991,730

ACTIVE MATRIX SUBSTRATE

SHARP KABUSHIKI KAISHA, ...

1. An active matrix substrate comprising: a display region that includes a plurality of pixels; and a peripheral region that is disposed around the display region,the peripheral region including a connecting portion formation region in which a plurality of line connecting portions are arranged, wherein,
each of the plurality of line connecting portions includes
a lower connecting portion supported on a substrate,
an organic insulating layer disposed on the lower connecting portion so as to be in contact with the lower connecting portion, the organic insulating layer having at least one aperture through which a part of the lower connecting portion is exposed, and
an upper connecting portion disposed on the organic insulating layer and in the at least one aperture, the upper connecting portion being directly in contact with the part of the lower connecting portion within the at least one aperture;
the organic insulating layer extends into an adjoining region that adjoins the connecting portion formation region;
in the adjoining region, the organic insulating layer has a plurality of dummy apertures that are disposed so as not to overlap the lower connecting portions when viewed from a normal direction of the substrate, each of the plurality of dummy apertures exposing a part of an underlying layer that is located on the substrate side of the lower connecting portion; and
the upper connecting portions are not provided in the plurality of dummy apertures.

US Pat. No. 10,991,729

ACTIVE MATRIX SUBSTRATE, OPTICAL SHUTTER SUBSTRATE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE

SHARP KABUSHIKI KAISHA, ...

1. An active matrix substrate comprising:a substrate;
a first metal film;
an interlayer insulating film formed in an upper layer on the first metal film; and
a second metal film formed in an upper layer on the interlayer insulating film, the first metal film and the second metal film being electrically connected to each other via a contact hole formed in the interlayer insulating film,
wherein an oxide semiconductor film converted into a conductor is provided in a layer between the substrate and the first metal film,
within the contact hole, the oxide semiconductor film converted into a conductor is in contact with the second metal film,
outside of the contact hole, the oxide semiconductor film converted into a conductor is in contact with the first metal film,
the first metal film does not overlap with the contact hole,
an end portion of the first metal film includes an end face facing a side wall of the contact hole, and
a distance from the end face to the side wall of the contact hole is less than a thickness of the interlayer insulating film.

US Pat. No. 10,991,728

DISPLAY PANEL

Au Optronics Corporation,...

1. A display panel, comprising:a first substrate;
a second substrate, provided opposite to the first substrate;
a sealant, located between the first substrate and the second substrate;
a signal line, located on the first substrate, and comprising a first signal line to an nth signal line substantially extending along a first direction, n being a positive integer and n being greater than or equal to 2; and
a turning line, connected to the signal line, the turning line comprising a first turning line to an mth turning line substantially extending along a second direction, m being a positive integer and m being greater than or equal to 2, a common boundary between the turning line and the signal line being substantially parallel with a third direction, and the signal line overlapping the turning line and the sealant in a direction perpendicular to the first substrate, wherein a first auxiliary region is defined by the first direction, a fourth direction perpendicular to the first direction, and the third direction, one side of the first auxiliary region overlaps the common boundary, two vertices of the first auxiliary region overlap the first signal line and the other vertex of the first auxiliary region overlaps the nth signal line, the signal line comprises a first auxiliary electrode provided between the first and nth signal lines and the common boundary in the first auxiliary region, the first auxiliary electrode is connected to at least one of the first signal line to the nth signal line, a vertical projection area of the signal line in the first auxiliary region is A1, an area of the first auxiliary region is B1, and 60%?A1/B1?100%.

US Pat. No. 10,991,727

LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. A light emitting display device, comprising:a substrate;
an uneven portion over the substrate, the uneven portion including a plurality of concave portions separated from each other and having protruding portions between the plurality of concave portions, each protruding portion including:
a vertex portion between three neighboring concave portions; and
a connection portion connecting two neighboring vertex portions that are between two neighboring concave portions, the connection portion having a height less than that of the vertex portions; and
a light emitting element over the uneven portion.

US Pat. No. 10,991,725

ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING SAME

SHARP KABUSHIKI KAISHA, ...

1. An active matrix substrate having a display region that includes a plurality of pixels and a non-display region that is provided around the display region, the active matrix substrate comprising:a substrate;
a plurality of first thin-film transistors (TFTs) supported on the substrate and provided in the non-display region;
a peripheral circuit including the plurality of first TFTs;
a plurality of second TFTs supported on the substrate and provided in the display region or the non-display region; and
an inorganic insulating layer that covers the plurality of first TFTs and the plurality of second TFTs, wherein:
each of the plurality of first TFTs and the plurality of second TFTs includes:
a gate electrode;
a gate insulating layer that covers the gate electrode;
an oxide semiconductor layer arranged so as to oppose the gate electrode with the gate insulating layer interposed therebetween, the oxide semiconductor layer including a channel region, a source contact region and a drain contact region, wherein the source contact region and the drain contact region are located on opposite sides of the channel region; and
a source electrode that is in contact with the source contact region of the oxide semiconductor layer and a drain electrode that is in contact with the drain contact region of the oxide semiconductor layer;
the oxide semiconductor layer of the plurality of first TFTs and the plurality of second TFTs is formed from the same oxide semiconductor film;
a carrier concentration in the channel regions of the plurality of first TFTs is higher than a carrier concentration in the channel regions of the plurality of second TFTs; and
the carrier concentration in the channel regions of the plurality of first TFTs is 10 times or more and 1000 times or less the carrier concentration in the channel regions of the plurality of second TFTs.

US Pat. No. 10,991,724

CMOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for fabricating a CMOS transistor, comprising steps of:forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate; and
injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process, wherein a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer,
forming a planarization layer on the first source electrode, the second source electrode, the first drain electrode and the second drain electrode before injecting the dopant ions;
wherein the step of injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process comprises:
forming a photoresist layer on the planarization layer, the photoresist layer comprising a first photoresist region and a second photoresist region, the first photoresist region corresponding to the first active layer, and the second photoresist region corresponding to the second active layer;
performing the doping process on the first active layer through the first photoresist region to inject the first dopant ions into the first active layer;
performing the doping process on the second active layer through the second photoresist region to inject the second dopant ions into the second active layer; and
removing the photoresist layer.

US Pat. No. 10,991,722

ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GAN DEVICES

International Business Ma...

1. A semiconductor structure comprising:a single integrated circuit die formed on top a semiconductor-on-insulator substrate, the integrated circuit die comprising:
a first field effect transistor (FET); and
a second field effect transistor comprising a Group III nitride material connected in cascode to the first transistor, the second FET transistor having a first dielectric sidewall liner structure extending along a sidewall surface of said second field effect transistor and a second dielectric sidewall liner structure extending along an opposite sidewall surface of said second field effect transistor, said first and second sidewall liner structures insulating said second field effect transistor from said cascode connected first FET, the first transistor having a gate terminal receiving an input signal, the first transistor having a drain terminal driving a source terminal of the cascode connected second transistor, the second transistor having a drain terminal providing an output signal; and
an integrated conductive structure formed at an interconnect layer above said semiconductor-on-insulator substrate for connecting said drain terminal of said first transistor to the source terminal of said integrated cascode connected second transistor;
said conductive structure of a length configured to reduce a parasitic resistance and inductance between said first FET and cascode connected second FET, wherein said semiconductor-on-insulator substrate includes, from bottom to top, a (111) silicon layer, a buried insulator layer and a (100) silicon layer, the second FET transistor comprising: at least one Group III nitride material layer embedded within a trench that extends through the (100) silicon layer and the buried insulator layer and into an upper portion of the (111) silicon layer.

US Pat. No. 10,991,721

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LINER FREE MOLYBDENUM WORD LINES AND METHODS OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the electrically conductive layers comprise molybdenum portions;
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and
a backside blocking dielectric layer comprising a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms, wherein the backside blocking dielectric layer is located between the electrically conductive layers and the memory stack structures and directly contacts the molybdenum portions and the backside blocking dielectric layer has a gradient in material composition such that an atomic concentration of the at least one of lanthanum or zirconium atoms decreases with a distance from the memory film.

US Pat. No. 10,991,719

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A method for manufacturing a semiconductor memory device comprising:forming a first stacked unit above a substrate, the first stacked unit including a pluralit of first insulating layers and first layers alternately stacked above the substrate;
forming a second insulating layer above the first stacked unit;
forming a second stacked unit above the second insulating layer, the second stacked unit including a plurality of the first insulating layers and the first layers alternately stacked above the second insulating layer; and
forming first memory cells in the first stacked unit and second memory cells in the second stacked unit, the first memory cells including first control gates stacked in the first stacked unit and a first semiconductor portion provided in a first hole, the first semiconductor portion extending inside the first stacked unit and functioning as channels of the first memory cells, the second memory cells including second control gates stacked in the second stacked unit and a second semiconductor portion provided in a second hole coupled to the first hole, the second semiconductor portion extending inside the second stacked unit and functioning as channels of the second memory cells;
the forming of the first memory cells and the second memory cells including:
forming the first hole extending through the first stacked unit in a stacking direction of the first stacked unit and the second stacked unit,
forming the second hole extending through the second stacked unit and the second insulating layer in the stacking direction, and
etching the second insulating layer exposed to the second hole in a direction orthogonal to the stacking direction, wherein
the forming of the second insulating layer is performed by using a material whose etching rate with respect to a certain etching is higher than that of the first insulating layers.

US Pat. No. 10,991,718

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A VERTICAL SEMICONDUCTOR CHANNEL CONTAINING A CONNECTION STRAP AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings vertically extending through the alternating stack; and
memory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises:
a memory film contacting a sidewall of a respective memory opening and including an opening at a bottom portion thereof;
a vertical semiconductor channel contacting an inner sidewall of the memory film and overlying the opening in the memory film;
a dielectric core contacting an inner sidewall of the vertical semiconductor channel; and
a connection strap comprising a semiconductor material, extending through the opening in the memory film, and contacting a bottom surface of the vertical semiconductor channel and a top surface of a semiconductor material that underlies the respective memory opening,
wherein:
the connection strap comprises a single crystalline strap semiconductor material;
the vertical semiconductor channel comprises a polycrystalline semiconductor material; and
the dielectric core also contacts the single crystalline strap semiconductor material of the connection strap.

US Pat. No. 10,991,717

VERTICAL MEMORY DEVICES

Samsung Electronics Co., ...

1. A vertical memory device, comprising:a circuit pattern formed on a substrate including a first region and a second region;
gate electrodes disposed on the circuit pattern in the first region, the gate electrodes stacked in a first direction vertical to an upper surface of the substrate, the gate electrodes extending in a second direction parallel to the upper surface of the substrate, and arranged in a third direction perpendicular to the second direction and parallel to the upper surface of the substrate;
a channel through the gate electrodes in the first direction;
a merged pattern structure formed on the second region, wherein
the merged pattern structure extends in the second direction, ends of extensions of gate electrodes of each level are merged, edges of the second direction of the merged pattern structure have a step shape, and the merged pattern structure includes insulation materials and pad patterns electrically connected to the extensions of gate electrodes of each level; and
cell contact plugs extending through the merged pattern structure in the first direction, each of the cell contact plugs electrically connected to the circuit pattern and one of the pad patterns.

US Pat. No. 10,991,716

SEMICONDUCTOR DEVICE HAVING A VERTICAL CHANNEL LAYER WITH AN IMPURITY REGION SURROUNDING A DIELECTRIC CORE

SK hynix Inc., Icheon-si...

1. A semiconductor device, comprising:a core insulating layer extending in a first direction;
an etch stop layer disposed on an upper surface of the core insulating layer;
a channel layer surrounding a sidewall of the core insulating layer and a sidewall of the etch stop layer and extending in the first direction;
conductive patterns each surrounding the channel layer and stacked to be spaced apart from each other in the first direction;
an impurity region formed in an upper end of the channel layer; and
a diffusion prevention layer extending between the impurity region and the etch stop layer wherein the diffusion prevention layer forms an interface between the impurity region and the etch stop layer.

US Pat. No. 10,991,715

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a stack body on a substrate, the stack body having a step structure body including a plurality of steps, each step formed with a plurality of sets of stacked layers, each set including a wire line layer and an interlayer insulating layer stacked with each other; and
memory cells arranged three-dimensionally in the stack body, wherein
each of the plurality of steps of the step structure body includes an upper wire line layer and a lower wire line layer and a lead wire line that is formed lower than the lower wire line layer; the upper wire line layer, the lower wire line layer; and the lead wire line being insulated from each other by the interlayer insulating layers,
the step structure body includes:
a plurality of terrace portions configured with the interlayer insulating layers, the plurality of terrace portions positioned at different heights;
a plurality of step portions connecting the respective terrace portions in a height direction; and
insulating layers covering the plurality of step portions, wherein the plurality of steps includes a first step and a second step that is lower than the first step, the lead wire line leads out a lowermost layer of the wire line layers of the first step, which is formed lower than the lower wire line layer of the first step, onto the terrace portion of the second step, and
the lead wire line is thicker than the interlayer insulating layers and thicker than the wire line layers in the step structure body.

US Pat. No. 10,991,714

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A three-dimensional semiconductor memory device comprising:first and second gate stacked structures, disposed on a base substrate, and stacked in a vertical direction perpendicular to a surface of the base substrate, the first and second gate stacked structures including first and second gate electrodes, respectively, spaced apart from each other and stacked in the vertical direction;
a through region passing through the first and second gate stacked structures and surrounded by the first and second gate stacked structures;
vertical channel structures passing through the first and second gate stacked structures; and
first and second gate contact plugs connected to the first and second gate electrodes, respectively,
wherein the first gate stacked structure includes a first step region having a first stepped shape such that steps of the first gate electrodes lower in a first direction toward the through region and a second step region having a second stepped shape such that steps of the first gate electrodes lower in a second direction toward the through region,
wherein the first direction and the second direction are parallel to the surface of the base substrate and are different each other,
wherein the second gate stacked structure includes a third step region having a third stepped shape such that steps of the second gate electrodes lower in the first direction toward the through region and a fourth step region having a fourth stepped shape such that steps of the second gate electrodes lower in the second direction toward the through region,
wherein the first gate contact plugs are connected to first contact pads of the first gate electrodes of any one region of the first and second step regions, and
wherein the second gate contact plugs are connected to second contact pads of the second gate electrodes of any one region of the third and fourth step regions.

US Pat. No. 10,991,711

STACKED-NANOSHEET SEMICONDUCTOR STRUCTURES

International Business Ma...

1. A semiconductor structure that includes an erasable programmable read-only memory (EPROM) bit cell, the EPROM bit cell comprising:a stacked pair of field-effect transistors including a first field-effect transistor (FET) and a second FET, the first FET having a first gate terminal connected to a word-line and a first source/drain terminal connected to a select-line;
wherein: the first and second FET are horizontal nano-sheet FETs (HNS-FETs).

US Pat. No. 10,991,710

NON-VOLATILE MEMORY DEVICE WITH VERTICAL STATE TRANSISTOR AND VERTICAL SELECTION TRANSISTOR

STMICROELECTRONICS (ROUSS...

1. A non-volatile memory device comprising:a vertical state transistor disposed in a semiconductor substrate, the vertical state transistor being configured to trap charges in a dielectric interface between a semiconductor well and a control gate;
a vertical selection transistor disposed in the semiconductor substrate, the vertical selection transistor being disposed under the state transistor, the vertical selection transistor being configured to select the state transistor; and
a trench disposed in the semiconductor well, the trench comprising an upper portion and a lower portion, the upper portion comprising the control gate of the vertical state transistor and the lower portion comprising a selection gate of the vertical selection transistor, wherein the dielectric interface is disposed on sidewalls of the upper portion of the trench, each of the vertical state transistor and the vertical selection transistor having an associated current conduction path oriented in a substantially vertical direction along the trench.

US Pat. No. 10,991,708

SEMICONDUCTOR DEVICE FOR PREVENTING AN INCREASE IN RESISTANCE DIFFERENCE OF AN ELECTRODE LAYER

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a stacked body including a first electrode layer and a second electrode layer provided to be electrically insulated from the first electrode layer in a stacking direction;
at least two first insulating layers provided in the stacked body to range from an upper end of the stacked body to a lower end of the stacked body, and extending in a first direction intersecting the stacking direction;
a first staircase portion provided in a first end region of the stacked body between the at least two first insulating layers;
a second staircase portion provided in a second end region of the stacked body located on a side opposite to the first end region between the at least two first insulating layers; and
a second insulating layer extending in the first direction, provided in the stacked body between the at least two first insulating layers, and dividing the second electrode layer in the first direction,
a length in the first direction of the second insulating layer being longer than a length in the first direction of the second electrode layer and shorter than a length in the first direction of the second electrode layer.

US Pat. No. 10,991,707

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

United Semiconductor Japa...

1. A semiconductor device, comprising:a gate insulation film provided above a semiconductor substrate;
a gate electrode provided above the gate insulation film;
a first sidewall insulation film provided on each of sidewalls of the gate electrode and above the semiconductor substrate, wherein the first sidewall insulation film includes a silicon oxide film and a silicon nitride film on the silicon oxide film;
a second sidewall insulation film provided on sidewalls of the silicon nitride film;
a source region and a drain region provided in the semiconductor substrate on both sides of the gate electrode, respectively, the source region and the drain region containing first conductive impurities, wherein in a plan view, an edge of the source region directed to the gate electrode coincides with a first outer edge of the silicon nitride film formed on one side of the gate electrode, an edge of the drain region directed to the gate electrode coincides with a second outer edge of the silicon nitride film formed on another side of the gate electrode, and the second sidewall insulation film overlaps a part of the source region and a part of the drain region;
a first semiconductor region provided in the semiconductor substrate below a first portion of the sidewall insulation film, a location of the first portion being on a source region side with respect to the gate electrode, the first semiconductor region having a concentration of the first conductive impurities lower than that of the source region and that of the drain region;
a second semiconductor region provided in the semiconductor substrate below a second portion of the sidewall insulation film, a location of the second portion being on a drain region side with respect to the gate electrode, the second semiconductor region having a concentration of the first conductive impurities lower than those of the drain region and the first semiconductor region;
a channel region provided in the semiconductor substrate between the first semiconductor region and the second semiconductor region; and
a third semiconductor region provided in the semiconductor substrate under the channel region and including second conductive impurities, which are higher in concentration than the channel region and are different from the first conductive impurities,
wherein information is stored by accumulating charges in the sidewall insulation film, and
the first semiconductor region and the second semiconductor region contact the third semiconductor region with bottom surfaces in a depth direction.

US Pat. No. 10,991,706

THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings vertically extending through the alternating stack; and
memory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises:
a memory film contacting a sidewall of a respective memory opening and including an opening at a bottom portion thereof;
an epitaxial pedestal structure comprising a single crystalline semiconductor material and including a cylindrical portion located underneath a bottom surface of the memory film and a protrusion portion having a tubular configuration and extending through the opening in the memory film;
a vertical semiconductor channel contacting an inner sidewall of the memory film and overlying and contacting the protrusion portion of the epitaxial pedestal structure; and
a dielectric core having a cylindrical shape and contacting an inner sidewall of the vertical semiconductor channel and contacting the single crystalline semiconductor material of the epitaxial pedestal structure at an inner sidewall of the protrusion portion of the epitaxial pedestal structure.

US Pat. No. 10,991,705

THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings vertically extending through the alternating stack; and
memory opening fill structures located within a respective one of the memory openings, wherein each of the memory opening fill structures comprises:
a memory film contacting a sidewall of a respective memory opening and including an annular opening at a bottom portion thereof;
a vertical semiconductor channel including a polycrystalline cylindrical portion contacting an inner sidewall of a vertically-extending portion of the memory film, a polycrystalline neck portion extending through the annular opening in the annular bottom portion of the memory film, and a polycrystalline base portion contacting an annular bottom surface of the annular bottom portion of the memory film; and
an epitaxial pedestal structure including a single crystalline semiconductor material and contacting the polycrystalline base portion and contacting a sidewall of a bottommost insulating layer of the insulating layers,
wherein an outer periphery of a topmost surface of the epitaxial pedestal structure is coincident with a bottom periphery of the polycrystalline base portion of the vertical semiconductor channel.

US Pat. No. 10,991,704

MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE

GLOBALFOUNDRIES Singapore...

1. A memory device comprising:a substrate comprising a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region;
a first gate structure at least partially arranged over the channel region, wherein the first gate structure comprises a top surface and wherein the top surface is substantially flat and wherein the first gate structure comprises entirely of electrically conductive material;
a protecting element at least partially arranged over the top surface of the first gate structure;
a tunnel oxide layer arranged over the first gate structure and the protecting element, wherein the tunnel oxide layer comprises a portion arranged horizontally beside the protecting element and further arranged to overlap vertically with the substantially flat top surface of the first gate structure; and
a second gate structure at least partially arranged over the protecting element and at least partially arranged adjacent to the first gate structure.

US Pat. No. 10,991,701

MULTI-COMPONENT CONDUCTIVE STRUCTURES FOR SEMICONDUCTOR DEVICES

Micron Technology, Inc., ...

1. A method of forming a semiconductor device, comprising:forming conductive materials within a recess within a substrate structure, the recess having an aspect ratio of at least 6:1 and a lateral dimension of 20 nm or less, comprising,
forming a first conductive material within the recess of the substrate structure by a cyclic vapor deposition process performed through use of a precursor gas comprising carbon, the deposited first conductive material comprising at least 60% ruthenium, the first conductive material filling the majority of the recess; and
forming a second conductive material on the first conductive material through a different deposition process than the cyclic deposition process, the deposited second conductive material comprising 40% or less of ruthenium.

US Pat. No. 10,991,700

METHODS OF FORMING SEMICONDUCTOR DEVICES USING ASPECT RATIO DEPENDENT ETCHING EFFECTS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS

Micron Technology, Inc., ...

13. An electronic system, comprising:an input device;
an output device;
a processor device operably coupled to the input device and the output device; and
a memory device operably coupled to the processor device and comprising at least one elongate semiconductive pillar comprising:
a digit line contact region; and
storage node contact regions laterally flanking the digit line contact region, each of the storage node contact regions individually exhibiting a larger lateral cross-sectional area than the digit line contact region.

US Pat. No. 10,991,699

SEMICONDUCTOR MEMORY DEVICES

Samsung Electronics Co., ...

1. A method of forming a semiconductor memory device, the method comprising:forming a device isolation layer in a substrate to define active regions;
forming a trench to cross the active regions, the trench comprising first trench portions exposing the device isolation layer and second trench portions exposing the active regions; and
sequentially forming a gate insulating layer and a gate electrode layer in the trench,
wherein each of the second trench portions comprises an upper trench and a lower trench that is wider than the upper trench,
wherein the sequentially forming comprises forming the gate insulating layer in the upper trench to define gate regions in the lower trench, and
wherein the sequentially forming further comprises forming the gate electrode layer in the gate regions through the first trench portions.

US Pat. No. 10,991,698

METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE WITH FLOATING BODY TRANSISTOR USING SILICON CONTROLLED RECTIFIER PRINCIPLE

Zeno Semiconductor, Inc.,...

1. A semiconductor memory cell comprising:a first silicon controlled rectifier device having a first region, a first floating body region, a first buried layer region, and a first substrate region;
a second silicon controlled rectifier device having a second region, a second floating body region, a second buried layer region, and a second substrate region;
a transistor comprising said first region, said first floating body region, said second region, and a gate;
wherein said first floating body region is common to said second floating body region;
wherein said first buried layer region is common to said second buried layer region;
wherein said first substrate region is common to said second substrate region;
wherein said transistor is usable to access said semiconductor memory cell;
wherein a state of said semiconductor memory cell is maintained through a positive voltage applied to said first and second substrate regions; and
wherein said state of said semiconductor memory cell is maintained and memory operations can be performed in an uninterrupted manner.

US Pat. No. 10,991,697

NAND STRING UTILIZING FLOATING BODY MEMORY CELL

Zeno Semiconductor, Inc.,...

1. A NAND string configuration comprising:a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;
a select gate drain device connecting one end of said string of semiconductor memory cells to a bit line, wherein said select gate drain device is not a semiconductor memory cell; and
a select gate source device connecting an opposite end of said string of semiconductor memory cells to a common source line, wherein said select gate source device is not a semiconductor memory cell;
wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;
wherein said third region is commonly connected to at least two of said semiconductor memory cells;
wherein each of said at least one of said plurality of semiconductor memory cells has only one gate; and
wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals.

US Pat. No. 10,991,696

VERTICALLY STACKED DEVICES WITH SELF-ALIGNED REGIONS FORMED BY DIRECT SELF ASSEMBLY (DSA) PROCESSING

Intel Corporation, Santa...

1. An integrated circuit structure comprising:a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and
a gate stack comprising gate regions for the stack of transistors,
wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.