US Pat. No. 10,461,940

SECURE FIRMWARE TRANSACTION SIGNING PLATFORM APPARATUSES, METHODS AND SYSTEMS

FMR LLC, Boston, MA (US)...

1. A transaction signing apparatus, comprising:a memory;
a component collection in the memory, including:
a secure firmware transaction signing component implemented by a first hardware security module (HSM) wherein the first HSM is a Peripheral Component Interconnect Express (PCIe) appliance installed in a transaction signing server;
a processor disposed in communication with the memory, and configured to issue a plurality of processing instructions from the component collection stored in the memory,
wherein the processor issues instructions from the secure firmware transaction signing component, stored in the memory, to:
receive, via at least one processor, a transaction signing request message for a transaction;
obtain, via at least one processor, an encrypted master private key associated with the transaction from a second HSM, wherein the second HSM is a Universal Serial Bus (USB) appliance communicatively coupled to the first HSM via USB;
retrieve, via at least one processor, from a first HSM's tamper-proof storage, a private key decryption key associated with the first HSM;
decrypt, via at least one processor, by the first HSM, the encrypted master private key using the retrieved private key decryption key;
determine, via at least one processor, a transaction hash and a keychain path associated with the transaction signing request message, wherein generation of the keychain path includes a hierarchical tree of private-public key pairs from the decrypted master private key, wherein the private-public key pairs are configured to cryptographically interoperate with the master private key, and wherein cryptographically interoperate includes encrypting and decrypting;
determine, via at least one processor, by the first HSM, a signing private key from the generated hierarchical tree of private-public key pairs for the determined keychain path using the decrypted master private key;
sign, via at least one processor, by the first HSM, the determined transaction hash using the generated signing private key to generate a signature; and
return, via at least one processor, the generated signature;
wherein the first and second HSMs, the memory and the processor are electronically connected.

US Pat. No. 10,461,935

VERIFICATION PROCESS OF AUTHENTICATION OR BIOMETRIC IDENTIFICATION

1. A method for processing biometric data, the method being executed by a proving entity (P) and a verification entity (V), each entity being a processing unit comprising processing and communication means with the other entity, the method comprising the following steps:communicating, by the proving entity (P), to the verification entity (V) the result of a calculation of distance between a biometric candidate datum (a) and at least one biometric reference datum (b), each comprising a number n of indexed components (ai, bi), and said data, said calculation of distance comprising that of a polynomial of the components of the biometric data,
generating, by the proving entity (P), from each datum a function of a number d of variables fa(i1, . . . , id), fb(i1, . . . , id) where d=log2n, defined for each variable on the set {0,1}, by reformulation of the index i of each component (ai, bi) in binary format,
generating, by the proving entity (P), from each function a polynomial of d variables ã(x1, . . . xd), b(xi, . . . xd) defined on ?d where ? is a finite field, such that each polynomial ã, b coincides with the corresponding function fa,fb on the set {0,1}d, and
generating, by the proving entity (P) from the polynomials ã, b a polynomial p(x1, . . . , xd) of d variables of the same expression as that of the distance between the data,
engaging, by the proving entity (P) and the verification entity (V), in a Sumcheck protocol applied to the polynomial p to verify the result of the calculation of the distance between the data, and
verifying of the result of calculation of distance between the biometric candidate datum and the at least one biometric reference datum.

US Pat. No. 10,461,933

METHODS FOR SECURE CREDENTIAL PROVISIONING

Visa International Servic...

1. A computer-implemented method, comprising:determining, by a user device, a one-time user public key;
sending, by the user device to a provisioning server computer, a provisioning request message including the one-time user public key;
receiving, by the user device, an encrypted provisioning response message from the provisioning server computer, the encrypted provisioning response message comprising encrypted credential data;
determining, by the user device, a response shared secret using a static server public key;
determining, by the user device, a response session key from the response shared secret, the response session key usable for decrypting the encrypted provisioning response message;
decrypting, by the user device, the encrypted provisioning response message using the response session key to determine the encrypted credential data;
determining, by the user device, a storage protection key from the response shared secret, the storage protection key being different from the response session key and usable for decrypting the encrypted credential data;
encrypting, by the user device, the storage protection key with a key encryption key to generate an encrypted storage protection key;
storing, by the user device, the encrypted storage protection key;
storing, by the user device, the encrypted credential data;
retrieving, by the user device, the encrypted credential data;
retrieving, by the user device, the encrypted storage protection key;
decrypting, by the user device, the encrypted storage protection key using the key encryption key to obtain the storage protection key; and
decrypting, by the user device, the encrypted credential data using the storage protection key to obtain credential data.

US Pat. No. 10,461,932

METHOD AND SYSTEM FOR DIGITAL SIGNATURE-BASED ADJUSTABLE ONE-TIME PASSWORDS

Oath Inc., New York, NY ...

1. A method, implemented on a machine having at least one processor, storage, and a communication platform connected to a network for identity verification, the method comprising:determining, at a first device, a first length of a signature, wherein the signature has been used previously by a first user to initially sign-in a second device;
determining, at the first device, a second length of the signature that is different from the first length, wherein the second length of the signature is determined based on a report including information of unauthorized accesses of the second device and a parameter associated with the second device;
generating a signing key based on the second length of the signature;
generating a new signature having the second length of the signature based on the signing key;
providing the new signature to a second user so that the second user can input a portion of the new signature into the second device for a subsequent sign in;
generating a verification key based on the new signature; and
transmitting the verification key to a third device to enable the third device to verify the second user based on the verification key and the portion of the new signature input by the second user into the second device.

US Pat. No. 10,461,929

UPDATING LOGIN CREDENTIALS OF AN ISCSI CLIENT IN A STORAGE AREA NETWORK

Hewlett Packard Enterpris...

1. A method comprising:sending, by an Internet Storage Name Service (iSNS) server, a target notification to an Internet Small Computer System interface (iSCSI) target device in a storage area network, the target notification including an instruction for the iSCSI target device to update a target-side record of login credentials for an iSCSI client;
receiving, by the iSNS server, a first target response message to the target notification from the iSCSI target device;
in response to the first target response message, providing, by the iSNS server, updated login credentials for the iSCSI client to the iSCSI target device;
receiving, by the iSNS server, a second target response message from the iSCSI target device indicating that the target-side record of the login credentials for the iSCSI client has been updated;
in response to the second target response message, sending, by the iSNS server, a client notification to the iSCSI client, the client notification including an instruction for the iSCSI client to update a client-side record of its login credentials;
receiving, by the iSNS server, a first client response message to the client notification from the iSCSI client;
in response to the first client response message, providing, by the iSNS server, the updated login credentials to the iSCSI client;
receiving, by the iSNS server, a second client response message from the iSCSI client indicating that the client-side record of its login credentials have been updated, wherein the updated credentials are useable by the iSCSI client to login to the iSCSI target device.

US Pat. No. 10,461,928

EMAIL VERIFICATION

1. Method for verifying an identity of an email-address utilized by a client device, the method being performed by a server and comprising:receiving a request for verifying the identity of the email-address;
in response to receiving the request for verifying the identity of the email-address, generating a first asymmetric key pair, KP1-S, comprising a private key, PrivK1-S, and a public key, PubK1-S;
calculating a first verification token, VN-1, based on the private key, PrivK1-S, of KP1-S and a known public key, PubK-C, of an asymmetric key pair, KP-C, of the client device;
transmitting a verification email message to the email-address to be verified comprising the public key, PubK1-S, of KP1-S, wherein the server signs the verification email message using a private key, PrivK2-S, of a second asymmetric key pair, KP2-S, of the server;
receiving a response to the verification email message including a second verification token, VN-2, calculated by the client device based on the private key, PrivK-C, of KP-C and the public key, PubK1-S, transmitted in the verification email message, wherein the server verifies the response using the known public key PubK-C;
verifying the identity of the email-address by verifying that VN-2 is identical to VN-1.

US Pat. No. 10,461,927

SECURE CHANNEL ESTABLISHMENT BETWEEN PAYMENT DEVICE AND TERMINAL DEVICE

Mastercard International ...

1. A method of establishing a secure channel for communication between a payment device and a terminal device using an elliptic curve Diffie-Hellman protocol, wherein G is an elliptic curve generator point and the payment device has a unique private key dc with a public key Qc=dc G certified by a party trusted by the terminal device, the method comprising:the payment device generating a blinding factor r and sending a blinded public key R=r·Qc to the terminal device;
the terminal device generating an ephemeral private key dt and a corresponding ephemeral public key Qt=dt G and sending Qt to the payment device;
wherein the payment device generates Kc=KDF(r dc·Qt) and the terminal device generates Kt=KDF(dt·R), where KDF is a key derivation function used in both generation operations, to establish a secure channel between the payment device and the terminal device;
wherein G is a point in the elliptic curve group E, wherein E is a group of prime order but E* is the quadratic twist of E and is a group of order m=z·m? where m? is prime and z is an integer;
wherein r·dc is chosen such that z is a factor of r·dc.

US Pat. No. 10,461,926

CRYPTOGRAPHIC EVIDENCE OF PERSISTED CAPABILITIES

HEWLETT PACKARD ENTERPRIS...

1. A system comprising:a processing resource connected to a globally shared memory and additional processing resources via a fabric; and
a non-transitory machine readable medium storing instructions that, when executed, cause the processing resource to:
in response to a request from one or more processes executing on the processing resource and invoking a persisted capability stored in the globally shared memory, determine whether to trust the persisted capability by verification of cryptographic evidence accompanying the persisted capability, wherein the persisted capability stored in the globally shared memory is a second persisted capability;
store a local capability into the globally shared memory as a first persisted capability;
extend a trust domain of the local capability to the first persisted capability via cryptographic evidence of authenticity and integrity of the first persisted capability; and
load the persisted capability upon the determination to trust the persisted capability based on successful verification,
wherein the persisted capability is a token of authority employed by the system to provide the one or more requesting processes assess to system resources.

US Pat. No. 10,461,925

HARDWARE MASKED SUBSTITUTION BOX FOR THE DATA ENCRYPTION STANDARD

Cryptography Research, In...

1. An integrated circuit comprising:a counter to generate a plurality of counter values;
an input mask component to generate a plurality of unmasked input values, wherein an unmasked input value of the plurality of unmasked input values is based on a combination of a respective counter value of the plurality of counter values and an input mask value;
a substitution function component to receive the plurality of unmasked input values and to generate a plurality of output values, wherein an output value of the plurality of output values is based on a respective unmasked input value of the plurality of unmasked input values and a substitution function;
an output mask component to generate a plurality of masked output values, wherein a masked output value of the plurality of masked output values is based on a combination of a respective output value of the plurality of output values and an output mask value; and
a plurality of memory elements to store the plurality of masked output values.

US Pat. No. 10,461,918

DATA TRANSMISSION SYSTEM

MEGACHIPS TECHNOLOGY AMER...

1. A data transmission system, comprising:a transmitter;
a receiver; and
retimer circuitry provided between the transmitter and the receiver, the retimer circuitry having local timing reference circuitry and clock data recovery circuitry,whereinthe retimer circuitry is configured to
start performing a link training sequence of a data transmission based on a local reference clock generated from the local timing reference circuitry, and
after starting the performing of the link training sequence, perform a normal operation sequence of the data transmission based on a clock generated by the clock data recovery circuitry and by transitioning from the local reference clock, and
the retimer circuitry is further configured to
generate an incoming link training sequence marker based on a serial bit stream received from the transmitter,
generate a self link training sequence marker during the link training sequence, and
adjust a time difference in the incoming link training sequence marker and the self link training sequence marker before transmitting the serial bit stream to the receiver.

US Pat. No. 10,461,915

METHOD AND APPARATUS FOR HANDLING TDD FRAME FOR SHORT TTI IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for communicating with a user equipment (UE) in a wireless communication system, the method performed by an eNodeB (eNB) and comprising:configuring a time division duplex (TDD) frame including a set of short downlink (DL) TTIs and a set of short uplink (UL) TTIs; and
communicating with the UE based on the TDD frame,
wherein a length of a short DL TTI and a length of a short UL TTI are less than 1 ms,
wherein the TDD frame is configured for a complementary carrier, which is located between a first regular carrier and a second regular carrier in a frequency domain,
wherein the complementary carrier, the first regular carrier and the second regular carrier are divided from a legacy carrier, and
wherein the TDD frame includes at least one short DL TTI overlapping with a UL resource allocated for the first regular carrier and the second regular carrier in a time domain.

US Pat. No. 10,461,912

DYNAMICAL SEARCH SPACE ALTERATIONS

Telefonaktiebolaget LM Er...

1. A method performed by a wireless device for updating an allocated search space to monitor for downlink control information, wherein the method comprises:receiving, from a base station, a downlink control information message;
obtaining, from the downlink control information message, information specifying an alteration of the allocated search space to monitor for downlink control information, DCI wherein the information specifying an alteration of the allocated search space specifies a complementary search space;
determining an updated search space based on the allocated search space and the information specifying an alteration of the allocated search space; and
using the updated search space to monitor for additional downlink control information;
wherein the information specifying a complementary search space also comprises instructions ordering the wireless device to reduce the allocated search space by removing the specified complementary search space from the allocated search space in order to obtain a reduced search space to monitor for downlink control information.

US Pat. No. 10,461,911

CHANNEL QUALITY INDICATOR FEEDBACK METHOD, USER EQUIPMENT, AND NETWORK DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A channel quality indicator (CQI) feedback method, wherein the method is applied to a co-cell communications system, a cell in the co-cell communications system comprises at least two single sectors and at least one joint sector, each of the at least two single sectors for providing a single-sector communications service for user equipment in the cell, and each of the at least one joint sector for providing a joint-sector communications service for the user equipment, the method comprising:receiving, by the user equipment, a secondary pilot receive signal of each single sector and that is obtained after a secondary pilot transmit signal of each single sector transmitted by a network device is transmitted by using a radio channel;
estimating, by the user equipment, a CQI of each single sector according to the secondary pilot receive signal of each single sector, a pre-known secondary pilot transmit signal of each single sector, and a first precoding matrix;
estimating, by the user equipment, a CQI of each joint sector according to the secondary pilot receive signal of each single sector, a pre-known secondary pilot transmit signal of each single sector, and a second precoding matrix; and
feeding back, by the user equipment, each CQI to the network device.

US Pat. No. 10,461,905

CHANNEL SELECTION IN WIRELESS COMMUNICATIONS

KYYNEL OY, Kempele (FI)

1. A method comprising:receiving, by a first network node from a second network node through a radio path, a first message comprising a pilot sequence;
processing the received first message and determining, by the first network node as a result of processing the pilot sequence, whether the first message has travelled the radio path as a surface wave along a ground surface or as a reflection from an ionosphere;
if it is determined that the first message has travelled the radio path as the surface wave, selecting by the first network node a first set of communication parameters for communication with the second network node;
if it is determined that the first message has travelled the radio path as the reflection from the ionosphere, selecting by the first network node a second set of communication parameters for communication with the second network node, wherein the second set of communication parameters is at least partly different from the first set of communication parameters; and
causing transmission of a second message from the first network node to the second network node by using the selected first or second set of communication parameters, wherein the second set of communication parameters specifies a communication frequency preferred exclusively by the second network node, and wherein the first set of communication parameters specifies a communication frequency preferred by both the first network node and the second network node.

US Pat. No. 10,461,904

METHOD, APPARATUS, AND DEVICE FOR DETERMINING MODULATION AND CODING ORDER

Huawei Technologies Co., ...

1. A method for determining a modulation and coding order, the method comprising:determining, by a network device, a quantity K of terminal devices that reuse a first time-frequency resource in a first time period to receive downlink data from the network device, wherein K?2;
determining, by the network device, a signal to interference plus noise ratio (SINR) of a channel, wherein the channel is a channel based on the first time-frequency resource, and the channel is used to transmit the downlink data between the network device and a first terminal device in the first time period;
determining, by the network device, a quantity of first acknowledgement messages and a quantity of first negative acknowledgement messages, wherein the first acknowledgement messages are acknowledgement messages sent by the first terminal device to the network device in a HARQ process for the downlink data, and the first negative acknowledgement messages are negative acknowledgement messages sent by the first terminal device to the network device in the HARQ process;
determining, by the network device, a channel quality indicator (CQI), wherein the CQI is determined according to the SINR of the channel, the quantity K of the terminal devices, the quantity of the first acknowledgement messages, and the quantity of the first negative acknowledgement messages; and
determining, by the network device, a Modulation and Coding scheme (MCS) of the first terminal device according to the CQI.

US Pat. No. 10,461,902

TERMINAL DEVICE, BASE STATION DEVICE, AND COMMUNICATION METHOD

SONY CORPORATION, Tokyo ...

1. A terminal device that communicates with a base station device, the terminal device comprising:a layer processing circuit configured to set a short transmission time interval (STTI) channel setting through signaling of a layer from the base station device; and
a receiver configured to
receive a first physical downlink shared channel (PDSCH) in a case in which the STTI channel setting is not set, and
receive a second PDSCH and a demodulation reference signal corresponding to the second PDSCH in a case in which the STTI channel setting is set, wherein
the first PDSCH is mapped to one or more resource blocks,
the second PDSCH is mapped to a sub resource block defined in accordance with a smaller number of symbols than a number of symbols corresponding to a resource block of the one or more resource blocks, and
in a case in which the demodulation reference signal is not mapped to the sub resource block, the demodulation reference signal is mapped in a resource block including the sub resource block.

US Pat. No. 10,461,901

METHOD AND DEVICE FOR TRANSMITTING DATA FOR PLURALITY OF STATIONS THROUGH PLURALITY OF BANDS IN WIRELESS LAN SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for transmitting a signal in a wireless LAN, comprising:allocating, by an access point (AR) including in a first basic service set (BSS), a first frequency band and a second frequency band,
wherein a non-contiguous band exits between the first and second frequency band,
wherein the non-contiguous band is overlapped with a hearable interfering source that canbe received from a second BSS, andwherein the second BSS is an overlapping basic service set (QBSS) for the first BSS: and
transmitting, by the AR, a first signal to a first station through the first frequency band and a second signal to a second station through the second frequency band,
wherein a first leftover tone is inserted in a resource unit (RU) closest to the non contiguous band in the first frequency band,
wherein a second leftover tone is inserted in a RU closest to the non-contiguous band inthe second frequency band,wherein the first and second leftover tones have 8 tones respectively,
wherein a first frequency resource through which the first signal is transmitted in the first frequency band has 234 tones, and
wherein a second frequency resource through which the second signal is transmitted in the second frequency band has 234 tones.

US Pat. No. 10,461,900

HIERARCHICAL ARRANGEMENT AND MULTIPLEXING OF MOBILE NETWORK RESOURCE SLICES FOR LOGICAL NETWORKS

Nokia Solutions and Netwo...

10. A method comprising:providing a hierarchical arrangement of a plurality of resource slices of a mobile network;
allocating, to each of a plurality of logical networks, a resource slice within the mobile network for each of a plurality of layers, wherein each logical network provides network services for one of a plurality of service categories, the allocating including:
allocating, for each of the logical networks, at least one dedicated resource slice to the logical network; and
allocating, for each of the logical networks, at least one shared resource slice to the logical network, the shared resource slice being shared among a plurality of the logical networks, and wherein the plurality of resource slices include a plurality of resource slices of a first layer and a plurality of resource slices of a second layer, wherein the first layer is lower than the second layer;
interfacing, by a multiplexer, between at least a set of resource slices of the second layer and a first resource slice of the first layer, wherein the interfacing includes:
aggregating or multiplexing data from the set of resource slices of the second layer into the first resource slice of the first layer; and
controlling, by a multiplexing policy function, the interfacing by the multiplexer to aggregate data of the set of resource slices of the second layer into the first slice of the first layer.

US Pat. No. 10,461,899

METHOD AND APPARATUS FOR SELECTING ANTENNAS IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method of processing signals by a base station, the method comprising:configuring an operating mode of the base station to be a multi-user multiple input multiple output (MU-MIMO) operating mode;
receiving signals using multiple antennas by using the MU-MIMO operating mode;
measuring channel information from each of the received signals;
identifying a user equipment (UE) among multiple UEs based on a modulation and coding scheme (MCS) and a number of allocated resource blocks (RBs);
determining antennas based on channel information corresponding to signals received from the identified UE; and
combining and processing signals received using the determined antennas.

US Pat. No. 10,461,898

PARALLEL DATA TRANSMISSION

Bank of America Corporati...

1. A system, comprising:a first subsystem located in a first location, a second subsystem located in a second location, and a third subsystem located in a third location, wherein the first, second, and third locations correspond to different geographical locations and wherein:
the first subsystem comprises a first analytics engine and a first delivery engine, the first analytics engine configured to:
receive a request to deliver data to the third subsystem, the data comprising a plurality of packets;
determine whether to deliver the data via transmission in series or transmission in parallel, based on a time of day and the third location of the third subsystem, wherein transmission in series comprises sending the plurality of packets along a single transmission path and transmission in parallel comprises sending subsets of the plurality of packets along different transmission paths; and
responsive to a determination to deliver the data via transmission in parallel, inform the first delivery engine of the request and the determination to deliver the data via transmission in parallel;
the first delivery engine configured to:
determine a first subset of the plurality of packets and a second subset of the plurality of packets to transmit in parallel, wherein the second subset of the plurality of packets is different from the first subset of the plurality of packets;
send the first subset of the plurality of packets to the second subsystem; and
send, through a first combination of nodes, a first data stream to the third subsystem, the first data stream comprising the second subset of the plurality of packets and first information identifying the first data stream as part of a parallel transmission;
the second subsystem comprises a second analytics engine and a second delivery engine, the second analytics engine configured to:
receive the first subset of the plurality of packets from the first subsystem; and
inform the second delivery engine to deliver the first subset of the plurality of packets to the third subsystem;
the second delivery engine configured to:
send, through a second combination of nodes that differ from the first combination of nodes, a second data stream to the third subsystem, the second data stream comprising the first subset of the plurality of packets and second information identifying the second data stream as part of the parallel transmission;
the third subsystem comprising a data stream processor, the data stream processor configured to:
receive the first and second data streams;
determine, based on the first and second information, that the first and second data streams are part of the parallel transmission;
responsive to determining that the first and second data streams are part of the parallel transmission, determine that the first and second data streams, in combination, comprise each of the plurality of packets;
responsive to determining that the first and second data streams, in combination, comprise each of the plurality of packets, build a data set based on the first and second data streams, wherein the data set comprises the plurality of packets; and
send the data set to a downstream component of the third subsystem.

US Pat. No. 10,461,895

TRANSMISSION OF UPLINK CONTROL INFORMATION IN UNLICENSED SPECTRUM

Nokia Technologies Oy, E...

1. An apparatus, comprising:at least one processor; and
at least one memory including computer program code,
wherein the at least one memory and computer program code are configured, with the at least one processor, to cause the apparatus at least to
transmit uplink control information in at least one of multiple transmission opportunities scheduled by a network node,
wherein the transmitting comprises transmitting, depending on a success of a listen-before-talk procedure, a hybrid automatic repeat request acknowledgement/non-acknowledgement on control channel resources allocated by the network node, and
wherein said multiple transmission opportunities are scheduled for each hybrid automatic repeat request acknowledgement/non-acknowledgement on the control channel.

US Pat. No. 10,461,894

TRANSMISSION CONTROL METHOD FOR HARQ IN MOBILE COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method by a terminal, the method comprising:receiving downlink control information on a physical downlink control channel (PDCCH) for a cell-radio network temporary identifier (C-RNTI) of the terminal;
receiving a transport block (TB) based on the downlink control information;
determining, based on a reset of a medium access control (MAC) entity being requested, whether the TB is received after the reset of the MAC; and
determining, in case that the TB is received after the reset of the MAC entity, a new data indicator (NDI) of the downlink control information to have been toggled regardless of a value of the NDI.

US Pat. No. 10,461,893

DATA AND CONTROL MULTIPLEXING IN PUSCH IN WIRELESS NETWORKS

TEXAS INSTRUMENTS INCORPO...

15. A user equipment (UE) comprising;circuitry for receiving data and control multiplexed bits g0, g1, g2, . . . , gH??1;
circuitry for receiving rank indicator bits q0RI, q1RI, q2RI, . . . , qQ?RI?1RI;
circuitry for receiving ACK/NACK bits q0ACK, q1ACK, q2ACK, . . . , qQ?ACK?1ACK;
circuitry for performing interleaving by constructing a matrix of Cmax=NsymbPUSCH columns wherein rank indicator bits are written onto the columns numbered {1, 4, 7, 10} for a normal cyclic prefix (CP) configuration and columns numbered {0, 3, 5, 8} for an extended CP configuration and ACK/NACK bits are written onto the columns numbered {2, 3, 8, 9} for a normal cyclic prefix (CP) configuration and columns numbered {1, 2, 6, 7} for an extended CP configuration;
circuitry for forming an output of the interleaver by reading off the matrix column by column;
circuitry for modulating the bit sequence and inserting reference signals; and
circuitry for transmitting the modulated bits and reference signals using one or more slots and one or more layers.

US Pat. No. 10,461,891

STAGGERED PILOT PLACEMENT

QUALCOMM Incorporated, S...

1. An apparatus for wireless communication, comprising:a processing system configured to:
receive a plurality of combined signals, each combined signal being on a tone of a plurality of tones, each combined signal comprising a first symbol of a first plurality of symbols from a first user equipment (UE) and a second symbol of a second plurality of symbols from a second UE, the first plurality of symbols including at least one first pilot symbol and at least one first data symbol, the second plurality of symbols including at least one second pilot symbol and at least one second data symbol, each of the at least one first pilot symbol being on a tone that carries one of the at least one second data symbol;
determine a first pilot signal on a first tone of the plurality of tones, the first tone carrying a respective one of the at least one first pilot symbol and a respective one of the at least one second data symbol, the first pilot signal being determined based on a channel element associated with the first tone and the respective one of the at least one first pilot symbol on the first tone; and
generate an interference-reduced signal for the first tone by canceling the determined first pilot signal from the first tone of the plurality of tones;
de-interleave the plurality of combined signals to determine a first set of pilot signals from the first UE, first and second code blocks from the first UE, a second set of pilot signals from the second UE, and third and fourth code blocks from the second UE; and
perform successive decoding of code blocks after de-interleaving the plurality of combined signals by:
decoding the third code block by canceling the first set of pilot signals from the third code block;
decoding the first code block by canceling the third code block from the first code block;
decoding the fourth code block by canceling the first code block from the fourth code block; and
decoding the second code block by canceling the fourth code block from the second code block.

US Pat. No. 10,461,884

SERVER SELECTED VARIABLE BITRATE STREAMING

COMCAST CABLE COMMUNICATI...

1. A method comprising:receiving a request for a portion of a content item at a first bitrate, wherein the request comprises a first identifier associated with the portion of the content item at the first bitrate;
determining, based on at least one network heuristic and independently from the first bitrate, a second bitrate from a plurality of bitrates associated with the portion of the content item;
determining, based on the first identifier and the second bitrate, a second identifier associated with the portion of the content item at the second bitrate;
sending, to a user device, the portion of the content item at the second bitrate, wherein the portion of the content item at the second bitrate is associated with the first identifier; and
sending, to the user device via a server push, a subsequent portion of the content item at the second bitrate.

US Pat. No. 10,461,877

DEVICE AND METHOD OF CONFIGURABLE SYNCHRONIZATION SIGNAL AND CHANNEL DESIGN

Intel IP Corporation, Sa...

1. An apparatus of user equipment (UE) comprising:a transceiver arranged to communicate with an evolved NodeB (eNB); and
processing circuitry arranged to:
configure the transceiver to receive a primary synchronization signal (xPSS) transmission and one of a secondary synchronization signal (xSSS) and a synchronization channel (xS-SCH) transmission after the xPSS transmission, comprising one of:
a plurality (Nrep) of xPSS symbols each comprising an xPSS subcarrier spacing an integer times a PSS subcarrier spacing and an xPSS duration the integer divided by a PSS duration, and
an Interleaved Frequency Division Multiple Access (IFDMA) structure comprising sets of xPSS symbols separated by non-xPSS symbols;
obtain a physical layer cell identification and achieve synchronization with the eNB using the xPSS transmission;
configure the transceiver to communicate with the eNB after synchronization is achieved with the eNB; and
configure the transceiver to receive information regarding the xPSS transmission from a primary cell (Pcell) via UE-specific dedicated Radio Resource Control (RRC) signaling, the information including at least one of an indication of whether the xPSS transmission is one of a beamformed and a repeated xPSS transmission, an indication of whether Power Spectral Density (PSD) boosting is being used for the xPSS transmission, an indication of whether a cyclic prefix (CP) is used for the xPSS transmission and a type of the CP, and a periodicity, an aggregation level (K) and a repetition level of the xPSS transmission.

US Pat. No. 10,461,876

TECHNIQUES FOR TRANSMITTING OR USING A PULL-IN SIGNAL TO LOCATE A SYNCHRONIZATION CHANNEL

QUALCOMM Incorporated, S...

1. A method for wireless communications at a wireless device, comprising:searching for a synchronization channel on a first raster point of a frequency raster identified for synchronization channel transmissions, the frequency raster comprising a plurality of raster points in a radio frequency spectrum;
identifying a pull-in signal on the first raster point;
determining, from the pull-in signal, a second raster point of the frequency raster on which the synchronization channel is transmitted; and
receiving the synchronization channel on the second raster point.

US Pat. No. 10,461,875

NETWORK NODE AND A METHOD THEREIN, AND A RADIO BASE STATION AND A METHOD THEREIN FOR PROTECTING CONTROL CHANNELS OF A NEIGHBOURING RADIO BASE STATION

TELEFONAKTIEBOLAGET LM ER...

1. A method performed by a first Radio Base Station (RBS) for protecting control channels of a neighbouring second RBS, the first RBS and the second RBS being operable in an Orthogonal Frequency Division Multiplexing (OFDM) based radio communication network, the method comprising:determining at least one subframe out of a predetermined number of subframes in which control channels of the first RBS are to be transmitted with reduced transmission power in relation to a nominal transmission power; and
informing the second RBS of the determined at least one subframe;
wherein determining the at least one subframe is performed independently of in which subframe(s) data channels of the first RBS are to be transmitted with reduced transmission power; and
wherein, for each subframe of the determined at least one subframe, the control-channel transmissions of the first RBS are performed in a control region that spans up to the first three OFDM symbols of the subframe, and wherein the method further includes indicating to the second RBS that the first RBS will, for each of the determined at least one subframe, transmit the first three OFDM symbols with the reduced transmission power, irrespective of whether the control region in each such subframe spans the three first OFDM symbols.

US Pat. No. 10,461,871

MANAGEMENT APPARATUS AND INFORMATION PROCESSING SYSTEM

FUJITSU LIMITED, Kawasak...

1. A management apparatus, comprising:a memory; and
a processor coupled to the memory and the processor configured to:
broadcast an activation request to a plurality of information processing devices having a reception period during which the activation request is received, the reception period occurring in a predetermined cycle;
receive a confirmation response from first information processing devices among the plurality of information processing devices, the first information processing devices receiving the activation request;
issue an activation instruction to a predetermined number of second information processing devices among the first information processing devices, the activation instruction instructing to activate the second information processing devices;
issue, to the first information processing devices other than the second information processing devices, an activation prohibition instruction to prohibit activation;
calculate a cycle of the reception period to make an average number of information processing devices which transmit the confirmation response corresponding to the activation request be a predetermined expectation value, basis of a number of third information processing devices among the plurality of information processing devices, the third information processing devices not being activated; and
set the calculated cycle, as the predetermined cycle, in at least one of the plurality of information processing devices.

US Pat. No. 10,461,870

PARALLEL IDENTIFICATION OF MEDIA SOURCE

iHeartMedia Management Se...

1. A method for use in a computing device implementing an identification server, the method comprising:obtain, at the identification server, first representations of broadcast content broadcast by a plurality of different media stations;
storing each of the first representations of broadcast content in separate buffers as buffered representations, wherein particular separate buffers are associated with particular media stations of the plurality of different media stations;
receiving, at the identification server, a second representation of media content captured by an end user device;
performing comparisons in parallel between the second representation of media content and each of a plurality of the buffered representations; and
identifying, at the identification server, a media station associated with the second representation of media content based, at least in part, on a result of the comparisons.

US Pat. No. 10,461,862

SUBSEA FIBER OPTICAL TERMINATION MODULE

SIEMENS AKTIENGESELLSCHAF...

1. A subsea fiber optical termination for terminating at least one fiber optical cable, the subsea fiber optical termination being configured for deployment in a subsea environment, the subsea fiber optical termination, comprising:at least one fiber optical termination to terminate a fiber optical cable, the fiber optical cable including a plurality of optical fibers, wherein the at least one fiber optical termination includes a high-pressure section and a low-pressure section therein, wherein when deployed in the subsea environment, a pressure in the high-pressure section is relatively higher than a pressure in the low-pressure section;
at least one optical connector;
at least one connecting tube, the at least one connecting tube containing one or more of the plurality of optical fibers, wherein the at least one connecting tube is configured to connect one or more of the plurality of optical fibers from the high-pressure section to the at least one optical connector; and
a support structure including
at least one recess to accommodate the at least one optical connector, and at least one support element configured to connect the at least one fiber optical termination to the support structure, wherein
the at least one fiber optical termination includes
a separating portion, to separate the low-pressure section from the high-pressure section,
at least one opening, configured to connect the low-pressure section to the high-pressure section, and
at least one fiber optical penetrator, each of the at least one fiber optical penetrator being configured to supply at least one optical fiber from the low-pressure section through a corresponding opening in the separating portion to the high-pressure section, and each of the at least one fiber optical penetrator being configured to provide at least one seal between the low-pressure section and the high-pressure section of the at least one fiber optical termination.

US Pat. No. 10,461,859

METHOD OF OUTPUTTING COLOR CODE FOR DATA COMMUNICATION TO DISPLAY SCREEN AND METHOD OF TRANSMITTING DATA USING COLOR CODE

1. A processor-implemented method of outputting, for data communication, color codes to a display screen, the method comprising:determining respective locations of a plurality of sections, each section divided in the display screen, wherein the respective locations of the plurality of sections each has a different binary code;
generating the color codes, using a color code table for the data communication, by mapping a predetermined respective color to each of the plurality of sections corresponding to source data to be communicated; and
outputting the predetermined respective color to the display screen.

US Pat. No. 10,461,858

VEHICLE COMMUNICATIONS USING VISIBLE LIGHT COMMUNICATIONS

1. An apparatus comprising:a pixel array having a plurality of photosensitive detectors, a first subset of the plurality of photosensitive detectors configured to capture an image of a light source, a second subset of the plurality of photosensitive detectors configured to capture data from an encoded pulsed light signal of the light source; and
processing circuitry configured to process data captured by pixels of the pixel array to provide image information and to detect data on an encoded pulsed light signal, processing circuitry configured to process data by:
sampling the light source at a first ratio corresponding to a sampling rate of the image to a sampling rate of the encoded pulsed light signal; and
detecting a data source in the light source, and based thereon, sampling the light source at a second ratio, the sampling rate of the encoded pulsed light signal in accordance with the second ratio being greater than the sampling rate of the encoded pulsed light signal in accordance with the first ratio.

US Pat. No. 10,461,857

CLOCK RECOVERY FOR A CODED LIGHT RECEIVER

SIGNIFY HOLDING B.V., Ei...

1. A signal processing module for receiving a coded light signal from light captured by a rolling-shutter camera, wherein the coded light signal comprises a periodically repeating message repeating with a message period; and wherein the signal processing module is configured to receive the coded light signal by performing operations of:receiving a respective portion of the message in each of a plurality of frames captured by the rolling-shutter camera, with different ones of said portions being received in different ones of the frames;
based on each respective one of a discrete group of trial values of the message period, using the respective trial value to reconstruct a respective first version of the message from the portions received in a first subset of said frames, and to reconstruct a respective second version of the message from the portions received in a second subset of said frames, wherein one or more of the frames in the second subset are not members of the first subset;
for each of the trial values, generating a respective value of a measure of similarity between the respective reconstructed first and second versions of the message; and
determining an estimate of the message period based on the values of said measure of similarity, and determining an output version of the message based on said estimate.

US Pat. No. 10,461,855

METHOD OF COMMUNICATION LINK ACQUISITION USING SEARCH PATTERN

X Development LLC, Mount...

1. A method comprising:detecting, by one or more processors, a misalignment between a first optical system of a first communication device and a second optical system of a second communication device;
rotating, by the one or more processors, the second optical system according to a series of positions ordered in increasing distance from a starting position;
capturing, by the one or more processors, a set of frames for each of the series of positions at the second communication device;
determining, by the one or more processors, whether a beacon beam transmitted from the first communication device is detected in one or more of the captured frames at the second communication device;
digitally cropping, by the one or more processors, a frame of the one or more of the captured frames after the beacon beam is detected, the digitally cropped frame including a pixel region where the beacon beam is detected in the frame; and
forming, by the one or more processors, a communication link between the first communication device and the second communication device when the beacon beam is detected.

US Pat. No. 10,461,853

OPTICAL MEMORY GATES

Hewlett Packard Enterpris...

1. A method, comprising:receiving at least one optical signal via a waveguide of an optical memory gate;
comparing a wavelength of the at least one optical signal to a resonant wavelength associated with a resonator;
reading out a value that is stored in the resonator via the at least one optical signal when the wavelength of the at least one optical signal matches the resonant wavelength;
transmitting the at least one optical signal with the value that is read out;
receiving an optical pump signal associated with a power level;
routing the optical pump signal into a feedback loop via a second resonator that applies a phase shift to the optical pump signal; and
monitoring a total power level of the optical memory gate.

US Pat. No. 10,461,851

PREDICTING OPTICAL TRANSCEIVER FAILURE

Facebook, Inc., Menlo Pa...

1. A method, comprising:calibrating a monitoring sensitivity of a power monitor that monitors a power output of an optical network transceiver device;
monitoring an amount of current provided to a laser diode of the optical network transceiver device;
detecting that the amount of current has reached a threshold limit;
monitoring the power output of the optical network transceiver device using the power monitor, including by determining a range based on a difference between a beginning-of-life transceiver power output level and an end-of-life transceiver power output level, determining a threshold magnitude that is a relative portion of the determined range, and detecting whether the power output drops by a magnitude that is greater than the threshold magnitude associated with the determined range; and
based at least in part on the detection that the amount of current has reached the threshold limit and the monitored power output of the optical network transceiver device, providing an indication associated with a likelihood of failure of the optical network transceiver device.

US Pat. No. 10,461,841

SATELLITE COMMUNICATION NETWORK TERMINAL INSTALLATION METHOD AND SYSTEM

HUGHES NETWORK SYSTEMS, L...

1. A method for installing a terrestrial antenna for a satellite communication network, the method comprising:providing a remote unit to an installation location for the terrestrial antenna, the remote unit being configured to communicate with a satellite of the satellite communication network and including a memory in which is stored antenna information pertaining to positioning of the terrestrial antenna with respect to a virtual beam generated by the satellite, the antenna information being accessible by entering a code that is associated with the virtual beam generated by the satellite;
accessing the antenna information from the memory at the installation location using the code; and
positioning the terrestrial antenna in relation to a virtual beam generated by the satellite based on the antenna information accessed from the memory at the installation location.

US Pat. No. 10,461,840

SUDAC, USER EQUIPMENT, BASE STATION AND SUDAC SYSTEM

Fraunhofer-Gesellschaft z...

1. A Shared User Equipment-Side Distributed Antenna Component (SUDAC) comprising:a first wireless communication interface, configured for using ultra-high frequency in order to establish at least one backend communication link with a base station; and
a second wireless communication interface, configured for using extremely-high frequency in order to establish at least one frontend communication link with a user equipment; and
a processor,
wherein the processor is configured for at least partially forwarding a first user information signal received via the frontend communication link as a first communication signal to be transmitted via the backend communication link while frequency converting the extremely-high frequency to the ultra-high frequency; or
wherein the processor is configured for at least partially forwarding a second communication signal received via the backend communication link as a second user information signal to be transmitted via the frontend communication link while frequency converting the ultra-high frequency to the extremely-high frequency;
wherein the processor is configured for extracting control information from the first user information signal and for controlling forward parameters of the first or the second wireless communication interface based on the control information,
wherein the control information is a transmit power, a modulation scheme or is related to a frequency, a code, a space and/or a time slot to be utilized by the SUDAC;
wherein the forward parameters relates at least to one of a time, a frequency, a space or a code resource of the backend communication link or the frontend communication link; and
wherein the processor is configured for frequency converting the first user information signal received at extremely-high frequency to the first communication signal at the ultra-high frequency and for frequency converting the second communication signal at the ultra-high frequency to the second user information signal at the extremely-high frequency; or
wherein the SUDAC comprises an analog to digital converter configured for digitizing the user information signal received at extremely-high frequency, and a digital to analog converter configured for analogizing a digitalized communication signal to acquire the communication signal at the ultra-high frequency wherein the processor is configured for generating the digitalized communication signal based on the digitalized user information signal.

US Pat. No. 10,461,834

METHOD AND DEVICE FOR SELECTING AND ALLOCATING TRANSMISSION BEAM INDEX HAVING PRIORITY

Samsung Electronics Co., ...

1. A method of a base station in a wireless communication system, the method comprising:transmitting reference signals using a plurality of beams and information on priorities of the plurality of beams;
receiving, from a terminal, index information on at least one beam selected from the plurality of beams; and
scheduling a beam selected from the at least one beam to the terminal,
wherein the at least one beam is selected from beams having a reference signal received power greater than a predetermined threshold based on the priorities of the plurality of beams, and
wherein the priorities of the plurality of beams are determined based on types of data transmitted through the plurality of beams.

US Pat. No. 10,461,832

CHANNEL STATUS INFORMATION FEEDBACK AND CONTROL METHOD AND DEVICE

1. A method for feeding back channel state information, the method comprising:receiving, by a user equipment, a trigger signaling transmitted by a base station, wherein the trigger signaling is configured to indicate the user equipment to report Channel State Information (CSI) obtained in a specified measurement window; and
reporting, by the user equipment, the CSI measured by the user equipment in the measurement window to the base station;
wherein reporting, by the user equipment, the CSI measured in the measurement window to the base station comprises:
reporting, by the user equipment, CSI measured by the user equipment in a first measurement window to the base station after M sub-frames elapse since the trigger signaling is received, wherein the first measurement window is a measurement window before the trigger signaling is received and closest to a sub-frame in which the trigger signaling is received, and M is an integer more than or equal to 0; or
reporting, by the user equipment, CSI measured by the user equipment in a second measurement window to the base station after M sub-frames elapse following the end of the second measurement window, wherein the second measurement window is a specified measurement window after the trigger signaling is received and closest to a sub-frame in which the trigger signaling is received, and M is an integer more than or equal to 0; or
reporting, by the user equipment, CSI measured by the user equipment in a second measurement window to the base station after M sub-frames elapse since the trigger signaling is received, wherein the second measurement window is a specified measurement window after the trigger signaling is received and closest to a sub-frame in which the trigger signaling is received, and M is an integer more than or equal to 0.

US Pat. No. 10,461,828

MILLIMETER WAVE DISTRIBUTED NETWORK ANTENNA SECTOR SWITCH

Intel IP Corporation, Sa...

1. A device of an initiator for performing time division duplex (TDD) sector switch, the device comprising memory and processing circuitry, the processing circuitry coupled to the memory, and the processing circuitry configured to:determine one or more antenna sector configurations based on time division duplex (TDD) beamforming, wherein the one or more antenna sector configurations are associated with first antenna sectors used to communicate with a first station device (STA);
initiate a TDD sector switch with the first STA to switch from the one or more first antenna sectors to one or more second antenna sectors;
cause to send, to the first STA, an action frame comprising TDD sector setting parameters associated with the TDD sector switch;
identify a response frame received from the first STA, wherein the response frame comprises the TDD sector setting parameters; and
perform the TDD sector switch by switching from the one or more first antenna sectors to the one or more second antenna sectors.

US Pat. No. 10,461,827

METHOD AND SYSTEM FOR MULTIPLE-HOP RELAYED DIRECTIONAL WIRELESS COMMUNICATION

SONY CORPORATION, Tokyo ...

1. An apparatus for wireless communication between stations (STAs) using directional transmission/reception, comprising:(a) a wireless communication station (STA) configured for mm-wave communication, in which said STA, and nearby STA instances of the apparatus are configured for performing sector sweep and feedback signaling to exchange antenna sector information;
(b) a transmitter of said wireless communication station (STA) configured for generating directional radio transmissions to other wireless radio communication devices which are in range;
(c) a receiver of said wireless communication station (STA) configured for receiving radio transmissions from other wireless radio communication devices;
(d) a computer processor coupled to said transmitter and said receiver for controlling communications between itself and other wireless radio communication devices;
(e) a non-transitory computer-readable memory storing instructions executable by the computer processor;
(f) wherein said instructions, when executed by the computer processor, perform steps comprising:
(i) exchanging quantized channel gain, or path loss, information of each antenna sector with one or more neighboring stations;
(ii) recording received quantized channel gain information from communication with neighboring stations;
(iii) generating route discovery messages to neighboring stations when establishing a multiple hop routing path from an originating station to a destination station;
(iv) processing received route discovery messages by (A) determining transmit antenna sector for the communication with a neighboring station that generated the route discovery message; (B) determining link metrics with the neighboring station that generated the route discovery message, (C) propagating the route discovery message to a neighbor station if the station is not the destination station; and
(v) determining link metrics, based on channel time utilization information, when establishing the multiple hop routing path.

US Pat. No. 10,461,826

ASSISTING A USER EQUIPMENT (UE) IN REFERENCE SIGNAL MEASUREMENTS BASED ON MEASUREMENT REPORT

QUALCOMM Incorporated, S...

1. A method for wireless communication by a base station (BS), comprising:transmitting, to a user equipment (UE), a request for information regarding one or more beams received by the UE in a synchronization region of a subframe;
receiving, from the UE, a measurement report including the information;
transmitting, to the UE, information for measuring one or more reference signals; and
transmitting, to the UE, additional information regarding direction information associated with the one or more reference signals to be used by the UE to measure the one or more reference signals, wherein the direction information is based, at least in part, on the measurement report.

US Pat. No. 10,461,823

APERTURE CONSTRAINT FOR NEW RADIO UPLINK MULTIPLE-INPUT MULTIPLE-OUTPUT

NOKIA TECHNOLOGIES OY, E...

1. A method comprising:receiving or calculating aperture constraint parameters, wherein the aperture constraint parameters are indicated by a network node in a downlink measurement indication; and
applying the aperture constraint parameters to limit uplink precoder candidates for transmission.

US Pat. No. 10,461,822

COMMUNICATION METHOD, NETWORK DEVICE, AND TERMINAL DEVICE

HUAWEI TECHNOLOGIES CO., ...

11. A communication method, comprising:determining, by a terminal device, and according to a value of a resource bundling granularity, at least one resource block bundling group in a scheduling resource corresponding to the terminal device, wherein the value of the resource bundling granularity is one of a first-type value and a second-type value, and wherein a resource block bundling group determining method corresponding to the first-type value is different from a resource block bundling group determining method corresponding to the second-type value; and
receiving, by the terminal device by using the at least one resource block bundling group, data transmitted by a network device.

US Pat. No. 10,461,820

WIRELESS COMMUNICATION USING WIRELESS ACTIVE ANTENNAS

RF DSP INC., Irvine, CA ...

1. Wireless Smart Antenna apparatus comprising a Base Station Side Radio Unit (BSSRU) and one or more User Equipment Side Radio Units (UESRUs),wherein if the BSSRU is distributed in a coverage area of a Base Station (BS), the BSSRU communicates with the BS using a first frequency band F1 and simultaneously communicates with a plural of UESRUs selected from said one or more UESRUs using a second frequency band F2, OR wherein if the BSSRU is integrated into a BS, the BSSRU communicates with the BS baseband through circuits and communicates with a plural of UESRUs selected from said one or more UESRUs in the second frequency band F2 using Multi-User Multiple Input Multiple Output (MU-MIMO) spatial multiplexing,
wherein a UESRU selected from said one or more UESRUs communicates with one or more distributed OR integrated BSSRUs using the second frequency band F2 and simultaneously communicates with one or more User Equipment (UEs) using the first frequency band F1, and
wherein a UESRU selected from said one or more UESRUs with a plural of radio transmitting and receiving paths and antennas, or a plural of UESRUs selected from said one or more UESRUs collectively, simultaneously communicate in the F1 frequency band with a plural of UEs distributed over the coverage area of the UESRU or the plural of UESRUs using MU-MIMO spatial multiplexing.

US Pat. No. 10,461,815

MULTI-INPUT AND MULTI-OUTPUT SATELLITE SERVICE TERMINAL

1. A Multi-Input and Multi-Output (MIMO) satellite service terminal including:an antenna adapted to receive and transmit a satellite signal in a frequency range of a plurality of different satellite communication systems;
an interface circuit connected to the antenna;
a receive signal processing module of an integrated circuit connected to the interface circuit to RF (radio frequency) sample the received satellite signal to obtain a radio frequency digital signal from the received satellite signal, and the receive signal processing module of the integrated circuit demodulates, dispreads, and decodes the radio frequency digital signal to obtain a broadcast message or a destination address in all the satellite signals as a receive message of the terminal;
a scheduling software module of the integrated circuit that acquires a set of connectable systems of all the MIMO satellite service terminals from the broadcast message, determines, a set of connectable systems of the terminal based on the detected satellite communication link status and selects the satellite communication system with the best link status as the satellite communication system selected by the terminal, wherein the set of connectable systems is the set of the satellite communication systems whose link status satisfy transmission and receive requirements;
a wireless communication connection that wirelessly transmits the receive message to the general-purpose data processing terminal; and
a transmission signal processing module of the integrated circuit periodically generates a satellite signal adapted to be transmitted by the satellite communication system selected by the terminal with terminal status information as message content and a gateway platform address as the destination address and transmits the generated satellite signal to the interface circuit, wherein the terminal status information includes the set of connectable systems.

US Pat. No. 10,461,810

LAUNCH TOPOLOGY FOR FIELD CONFINED NEAR FIELD COMMUNICATION SYSTEM

TEXAS INSTRUMENTS INCORPO...

1. A system comprising a module, the module comprising:a substrate;
a radio frequency (RF) transmitter mounted on the substrate;
a near field communication (NFC) coupler, on the substrate, coupled to the RF transmitter, wherein the NFC coupler has a front side and a back side, and wherein the NFC coupler comprises an antenna, comprising:
an outer conductive region; and
a non-conducting slot surrounded by the outer conductive region;
a housing that surrounds the substrate, the housing having a port region;
a field confiner, between the front side of the NFC coupler and the port region of the housing, arranged to propagate a first portion of near-field electromagnetic energy through the port region, the near-field electromagnetic energy being emanated from the NFC coupler; and
a reflective surface, facing the back side of the NFC coupler, arranged to reflect a second portion of the near-field electromagnetic energy towards the port region.

US Pat. No. 10,461,804

ELIMINATION OF CROSSTALK EFFECTS IN NON-VOLATILE STORAGE

WESTERN DIGITAL TECHNOLOG...

1. An arrangement, comprising:a flash interface module connected to the application specific integrated circuit, the flash interface module having a flash interface;
a flash memory interface configured to accept and transmit data;
a flash memory configured to receive and transmit data from the flash memory interface;
at least two lines configured to transmit data from the flash interface module to the flash memory interface; and
at least one spare line configured to transmit data from the flash interface module to the flash memory interface, the at least one spare line; and
an application specific integrated circuit configured to replace one of the at least two lines configured to transmit data from the flash interface to the flash memory interface.

US Pat. No. 10,461,800

COMMUNICATION CONTROL METHOD AND RELATED APPARATUS

Huawei Technologies Co., ...

1. A base station comprising:an antenna;
a processor coupled to the antenna; and
a non-transitory computer readable storage medium storing a program for execution by the processor, the program including instructions to:
transmit, by the base station to N user terminals using the antenna, a configuration message, wherein the configuration message carries a secondary configuration indication, the secondary configuration indication indicating a secondary transmission configuration configured by the base station for the N user terminals, and wherein the secondary transmission configuration of the N user terminals is different from a primary transmission configuration of M user terminals in a cell, the N user terminals being a subset of the M user terminals, and N and M being positive integers;
obtain interference parameters about interference that the N user terminals receive from neighboring user terminals in a full-duplex subframe, wherein the full-duplex subframe is a subframe in which the primary transmission configuration corresponds to uplink transmission and the secondary transmission configuration corresponds to downlink transmission in the same subframes of the same band;
activate the secondary transmission configuration for K user terminals of the N user terminals using an activation message, wherein interference parameters about interference that the K user terminals receive from neighboring user terminals meet a specified activation condition, the K user terminals being a subset of the N user terminals, and K being a positive integer; and
use directional downlink transmission in the full-duplex subframe, wherein a beam corresponding to the directional downlink transmission covers at least one user terminal of the K user terminals,
wherein the primary transmission configuration is a primary carrier, and the secondary transmission configuration is a secondary carrier, and
wherein an uplink band of the primary carrier is the same as a downlink band of the secondary carrier, and a downlink band of the primary carrier is the same as an uplink band of the secondary carrier, or a band of the primary carrier is the same as a band of the secondary carrier, and a time division duplex (TDD) uplink-downlink configuration of the primary carrier is different from a TDD uplink-downlink configuration of the secondary carrier.

US Pat. No. 10,461,795

MOBILE COMPUTING/COMMUNICATING ATTACHMENT DEVICE

1. An attachment system for holding at least one mobile computing device comprising:a. a first attachment device attached to a first mobile computing device, comprising:
i. a removable, flexible plate attached to a portion of one side the of first mobile computing device;
ii. a first elongated rail mounted on the plate, and
iii. at least two first elongated structures defining a first elongated opening between them;
b. a second attachment device attached to a second mobile computing device, comprising:
i. a second elongated rail; and
ii. at least two second elongated structures defining a second elongated opening between them such that the second elongated rail is sized and shaped to receive and hold the at least two first elongated structures and the at least two second elongated structures are sized and shaped to receive and hold the first elongated rail in order to interact with and attach the second mobile computing device to the first attachment device, wherein the first and second elongated structures have a first and second end and the first and second elongated structures narrow in width at their first end to create a widened beveled opening.

US Pat. No. 10,461,790

METHOD FOR COMPENSATION OF PHASE NOISE EFFECT ON DATA TRANSMISSION IN RADIO CHANNEL

1. A method for estimation and compensation of phase noise effect on data transmission comprising:a. Reception of a sequence of multiple signal samples;
b. Estimation of phase noise in the sequence of multiple signal samples;
c. Compensation of the phase noise in the sequence of multiple signal samples using a phase noise estimate,
wherein the phase noise estimation comprises the successive steps of:
b1. Selection of a sequence of several signal samples from a variety of signal samples;
b2. Direct estimation of phase noise realization from the sequence of several signal samples;
b3. Generation of a sequence of estimates of the phase noise realization;
b4. Estimation and extraction of one or several phase noise low-frequency spectral components by a linear combination of the phase noise realization estimates with weighted coefficients;
b5. Estimation of the phase noise in a sequence of multiple signal samples in a time domain using an inverse Fourier transform of the estimated low-frequency phase noise components.

US Pat. No. 10,461,787

SPUR MITIGATION FOR PULSE OUTPUT DRIVERS IN RADIO FREQUENCY (RF) DEVICES

Silicon Laboratories Inc....

1. An integrated circuit, comprising:a first clock generator having a digital clock as an output;
a second clock generator having a local oscillator (LO) clock as an output;
radio frequency (RF) circuitry coupled to operate using the LO clock;
a circuit coupled to receive the digital clock and the LO clock as inputs and having a retimed clock as an output, the retimed clock representing the digital clock retimed with the LO clock;
digital circuitry coupled to have internal timing based upon the digital clock; and
one or more drivers coupled to be timed by the retimed clock, each driver being coupled to provide a pulse output signal to an output pad.

US Pat. No. 10,461,783

RADIO FREQUENCY COMMUNICATION DEVICES HAVING BACKSCATTER AND NON-BACKSCATTER COMMUNICATION MODES AND HARDWARE RE-USE

University of Washington,...

1. A radio frequency communication device, comprising:a backscatter transmitter circuit;
a non-backscatter transceiver circuit;
an antenna; and
a transistor in a transmit path of the non-backscatter transceiver circuit and electrically coupled to the antenna, the transistor configured to, in a backscatter modulator mode, vary an impedance presented to the antenna via the transmit path of the non-backscatter transceiver circuit;
wherein each of the backscatter transmitter circuit and the non-backscatter transmitter circuit are in electrical communication with the antenna.

US Pat. No. 10,461,782

METHOD AND APPARATUS FOR DYNAMIC TUNING

BLACKBERRY LIMITED, Onta...

1. A communication device, comprising:a matching network including a tunable reactive element;
a processing system including a processor, the processing system being coupled with the matching network; and
a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations, comprising:
during Frequency Division Duplex (FDD) communication, selecting first, second, and third tuning states from first, second and third groups of tuning states, respectively, wherein the first, second and third groups of tuning states are stored in the memory and are predetermined tuning states based on increasing performance in transmit, receive and duplex operation, respectively;
determining a weighted tuning state based on a weighting factor, and the first, second and third tuning states, wherein the first, second and third tuning states comprise sets of digital to analog converter values, and wherein the weighting factor is based on an interpolation that utilizes digital to analog converter values of at least two of the first, second and third tuning states;
adjusting the matching network utilizing the weighted tuning state resulting in a tuning;
responsive to the tuning, determining a first performance metric according to a first measurement associated with the FDD communication;
selecting first, second, and third reference metrics from first, second and third groups of reference metrics stored in the memory, wherein the first, second and third groups of reference metrics are predetermined expected metrics based on the increasing performance in the transmit, receive and duplex operation, respectively;
determining a weighted reference metric based on the weighting factor, and the first, second and third reference metrics;
comparing the first performance metric to the weighted reference metric resulting in a first comparison; and
responsive to a first determination that the first performance metric satisfies a first threshold according to the first comparison, continuing the tuning utilizing the weighted tuning state.

US Pat. No. 10,461,777

ERROR LOCATOR POLYNOMIAL DECODER AND METHOD

WESTERN DIGITAL TECHNOLOG...

1. A decoding apparatus comprising:a syndrome generator circuit configured to receive data and generate at least two different sets of syndromes;
an error locator polynomial generator circuit configured to receive the at least two different sets of syndromes and generate a mutual error locator polynomial; and
a convergence detector circuit coupled to the error locator polynomial generator circuit, the convergence detector circuit including:
at least two computation circuits configured to generate at least two convergence signals based on the mutual error locator polynomial from the error locator polynomial generator circuit and on the at least two different sets of syndromes, wherein each of the different sets of syndromes corresponds to a different one of the convergence signals.

US Pat. No. 10,461,776

DEVICE AND METHOD OF CONTROLLING AN ITERATIVE DECODER

Realtek Semiconductor Cor...

8. A controlling method, for controlling operations of an iterative decoder, comprising:receiving at least one coded signal;
performing an iterative decoding on the at least one coded signal, to generate a plurality of decoded signals, wherein the plurality of decoded signals comprise a first decoded signal from a first iteration, a second decoded signal from a second iteration and a third decoded signal from a third iteration;
determining whether the plurality of decoded signals diverge, to generate a first determination result;
generating a control signal according to at least the first determination result, wherein the control signal indicates the iterative decoder whether to stop performing the iterative decoding on the at least one coded signal;
performing an error detection on the plurality of decoded signals, to generate a second determination result; and
generating the control signal according to the first determination result and the second determination result.

US Pat. No. 10,461,774

TECHNOLOGIES FOR ASSIGNING WORKLOADS BASED ON RESOURCE UTILIZATION PHASES

Intel Corporation, Santa...

1. An orchestrator server to assign workloads among a set of managed nodes based on resource utilization phases, the orchestrator server comprising:one or more processors;
one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, cause the orchestrator server to:
assign a set of workloads to the managed nodes;
receive telemetry data from the managed nodes, wherein the telemetry data is indicative of resource utilization by each of the managed nodes as the workloads are performed and wherein each managed node includes a set of sleds that define pools of different types of disaggregated resources;
identify, as a function of the telemetry data, historical resource utilization phases of the workloads, wherein each historical resource utilization phase is indicative of a utilization of a particular type of managed node component that satisfies a predefined threshold amount over a time period;
determine, as a function of the historical resource utilization phases and as the workloads are performed, predicted resource utilization phases for the workloads, wherein each predicted resource utilization phase is indicative of a predicted utilization of a particular type of managed node component that satisfies the predefined threshold amount over a second time period; and
apply, as a function of the predicted resources utilization phases, an adjustment to the assignments of the workloads among the managed nodes to delay an execution of a first workload to temporally align a first predicted resource utilization phase of the first workload with a second predicted resource utilization phase of a second workload on the same managed node to cause the first predicted resource utilization phase and the second predicted resource utilization phase to occur concurrently and wherein the first predicted resource utilization phase and the second resource utilization phase are predicted to utilize complementary amounts of the same resource.

US Pat. No. 10,461,772

CODE CONVERSION

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method comprising:obtaining, by one or more processors, a first code point from a source data string in a first character encoding, wherein the source data string is to be converted to a target data string in a second character encoding;
looking up, by one or more processors, a target code point corresponding to the first code point in a map table, the target code point being in the second character encoding;
determining, by one or more processors, whether the first code point is a first combining character in response to receiving a lookup failure generated from the looking up operation;
identifying, by one or more processors, a combination unit comprising the first combining character and at least one base character next to the first combining character in the source data string in response to determining that the first code point is the first combining character; and
converting, by one or more processors, the combination unit to a substitute character in the target data string.

US Pat. No. 10,461,771

SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER WITH MULTIPLE COUNTERS

TEXAS INSTRUMENTS INCORPO...

1. A sigma-delta analog-to-digital converter (ADC), comprising:a first set of switches coupled to a first node and a second node, the first set of switches configured to receive a first voltage signal;
a second set of switches coupled to the first node and the second node, the second set of switches configured to receive a second voltage signal;
an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal;
a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and
a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator,
wherein the processor is configured to increment a first counter value of the first counter based on the second output signal and a second counter value of the second counter based on the second output signal,
wherein the processor is configured to compute a value based on the first and second counter values;
wherein the controller unit is configured to change the first output signal based on the second output signal;
wherein if the second output signal is 1, the controller unit is configured to subtract the first output signal by the second voltage signal, wherein if the second output signal is 0, the controller unit is configured to add the first output signal with first voltage signal.

US Pat. No. 10,461,768

DIGITAL-TO-ANALOG CONVERTER (DAC) DESIGN WITH REDUCED SETTLING TIME

QUALCOMM Incorporated, S...

1. A digital-to-analog converter (DAC), comprising:a plurality of transistors selectively coupled to an output of the DAC; and
a biasing circuit coupled to gates of the plurality of transistors, wherein the biasing circuit comprises:
a first transistor having a gate coupled to a drain of the first transistor;
a first buffer having an input coupled to the gate of the first transistor;
a second transistor having a gate coupled to an output of the first buffer;
a first resistive-capacitive (RC) circuit having a first resistive element and a first capacitive element, the first RC circuit being coupled between the gate of the first transistor and the gate of the second transistor; and
a first switch coupled between the first resistive element and the first capacitive element.

US Pat. No. 10,461,766

SEMICONDUCTOR DEVICE, SIGNAL PROCESSING SYSTEM, AND SIGNAL PROCESSING METHOD

Renesas Electronics Corpo...

1. A semiconductor device comprising:a reference voltage generation circuit that generates a reference voltage;
an analog signal processing circuit that outputs a first processing signal according to the reference voltage;
a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal;
an input section that receives a regulation signal for the outputted test signal; and
a regulator circuit that regulates an output of the analog signal processing circuit in response to the regulation signal,
wherein the test signal output section outputs, as the test signal, one of the second processing signal and the reference voltage.

US Pat. No. 10,461,765

SUCCESSIVE APPROXIMATION TYPE AD CONVERTER AND SENSOR DEVICE

Hitachi, Ltd., Tokyo (JP...

1. A successive approximation type AD converter comprising:a first capacitance DA converter that samples a first input analog signal and outputs a voltage corresponding to a sampled value;
a second capacitance DA converter that samples a second input analog signal and outputs a voltage corresponding to a sampled value;
a comparator that compares an output of the first capacitance DA converter and an output of the second capacitance DA converter;
a successive approximation logic unit that supplies a control signal to the first capacitance DA converter and the second capacitance DA converter on the basis of a comparison result of the comparator; and
an in-phase voltage detection and supply circuit that, in a sampling period, supplies an in-phase voltage obtained by impedance voltage division of the first input analog signal and the second input analog signal to the first capacitance DA converter and the second capacitance DA converter,
wherein the first capacitance DA converter samples the first input analog signal with reference to the in-phase voltage in the sampling period, the second capacitance DA converter samples the second input analog signal with reference to the in-phase voltage,
after the sampling period ends, the comparator compares the output of the first capacitance DA converter and the output of the second capacitance DA converter, output voltages of the first capacitance DA converter and the second capacitance DA converter are changed by the control signal of the successive approximation logic unit on the basis of a comparison result, comparison processing is repeated, and thereby, a digital signal of a successive approximation result is output.

US Pat. No. 10,461,764

SYSTEM AND METHOD FOR INTERLEAVED DIGITAL-TO-ANALOG CONVERTER (DAC) CALIBRATION

IQ-Analog Corporation, S...

1. A system for calibrating an interleaved digital-to-analog converter (DAC), the system comprising:an interleaved DAC comprising 2N selectively enabled sub-DACs, where N is an integer greater than or equal to 1, each sub-DAC having an input to accept a digital data signal, a clock input to accept a first clock signal at a first frequency with unique phase, and an output to supply an analog signal converted from the data signal;
a data generator having 2N outputs to respectively supply 2N data signals to the 2N sub-DACs corresponding to a fundamental analog signal, and an input to accept signal generation commands;
a clock generator having an output to supply 2N unique phases of the first clock signal;
a clock calibration module having an input to accept the 2N phases of the first clock signal, an input to accept calibration signals, and 2N outputs to selectively supply unique phases of the first clock signal to the enabled sub-DACs in response to the calibration signals;
a summing device having 2N inputs to accept analog signals from enabled sub-DACs, and an output to supply a summed analog signal comprising the fundamental analog signal with spurious signals offset from a multiple of the first frequency of the first clock signal, where the spurious signals are responsive to duty cycle mismatch and first clock signal phases errors between enabled sub-DACs;
an analog-to-digital converter (ADC) having a signal input to accept the summed analog signal, a clock input to accept a second clock signal, and an output to supply a digital conversion signal converted from the summed analog signal; and,
a control module having an input to accept the conversion signal, an output to supply the signal generation commands, and an output to supply the calibration signals to the clock calibration module.

US Pat. No. 10,461,763

DOUBLE DATA RATE TIME INTERPOLATING QUANTIZER WITH REDUCED KICKBACK NOISE

Huawei Technologies Co., ...

1. An apparatus comprising:a first double data rate comparator circuit configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the first double data rate comparator circuit;
a second double data rate comparator circuit configured to determine a relative voltage of a second differential input signal during each of the rising edge and the falling edge in the single clock cycle of the comparator clock input to the second double data rate comparator circuit;
a third double data rate comparator circuit configured to determine a relative voltage of a third differential input signal during each of a rising edge and a falling edge in the single clock cycle of an inverted comparator clock input to the third double data rate comparator circuit; and
a first floating voltage reference circuit configured to shift a voltage of a differential comparator input signal by a first fixed amount, and produce the first differential input signal;
a second floating voltage reference circuit configured to shift the differential comparator input signal by a second fixed amount and produce the second differential input signal; and
a clock inverter circuit connected to the comparator clock signal and configured to produce the inverted comparator clock signal;
wherein the third differential input signal is cross connected to the first differential input signal and the second differential input signal.

US Pat. No. 10,461,762

SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER CHOPPING

QUALCOMM Incorporated, S...

1. An analog-to-digital converter (ADC) comprising:a comparator comprising a first input and a second input;
a switch connected between the first and second inputs of the comparator;
a first capacitive array having a first terminal coupled to the first input of the comparator;
a second capacitive array having a first terminal coupled to the second input of the comparator; and
a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.

US Pat. No. 10,461,761

PIPELINED SAR WITH TDC CONVERTER

Taiwan Semiconductor Manu...

1. An analog-to-digital converter (ADC), comprising:a successive approximation register configured to receive an input signal and to generate a first digital signal and a residue voltage;
a voltage-to-time conversion element configured to convert the residue voltage to a time domain representation, the voltage-to-time conversion element comprising:
an amplifier comprising an input coupled to an output of the successive approximation register;
a zero crossing detector directly coupled to an output of the amplifier; and
a time-to-digital converter coupled to an output of the zero crossing detector and configured to generate a second digital signal.

US Pat. No. 10,461,759

DLL CIRCUIT HAVING VARIABLE CLOCK DIVIDER

Micron Technology, Inc., ...

1. An apparatus, comprising:a variable clock divider configured to generate a divided clock signal based on feedback of a delay amount;
a delay circuit configured to input the divided clock signal, delay and output the divided clock signal based on the delay amount, and provide the feedback of the delay amount to the variable clock divider; and
a phase detector configured to:
compare phases of the divided clock signal and the delayed divided clock signal, and
control the delay circuit to match phases of the divided clock signal and the delayed divided clock signal.

US Pat. No. 10,461,757

REFERENCE-LESS FREQUENCY DETECTOR WITH HIGH JITTER TOLERANCE

Futurewei Technologies, I...

1. An apparatus comprising:a not-and (NAND) gate comprising a first NAND gate input port, a second NAND gate input port, and a NAND gate output port;
a charge pump comprising a charge pump activation port and a charge pump output current port, the charge pump activation port is coupled to the NAND gate output port, and the charge pump output current port is configured to couple to a frequency detection loop filter;
an inverter module coupled to the NAND gate and the charge pump so that the inverter module is positioned between the NAND gate and the charge pump; and
a buffer module coupled to the NAND gate and the charge pump so that the buffer module is positioned between the NAND gate and the charge pump,
the buffer module is configured to buffer or delay a signal by a period of time.

US Pat. No. 10,461,756

PLL CIRCUIT

MITSUBISHI ELECTRIC CORPO...

1. A PLL circuit comprising:a voltage-controlled oscillator to transmit a frequency signal corresponding to a voltage of a supplied signal;
a variable frequency divider to perform frequency dividing on an output signal of the voltage-controlled oscillator at a supplied frequency dividing ratio;
a phase frequency comparator to compare an output signal of the variable frequency divider with a reference signal;
a charge pump to output a signal corresponding to a result of the comparison performed by the phase frequency comparator;
a loop filter to supply a signal obtained by smoothing the output signal of the charge pump to the voltage-controlled oscillator;
a ?? modulator to generate the frequency dividing ratio for the variable frequency divider depending on a supplied signal;
a first frequency accumulator to operate using the output signal of the variable frequency divider as a clock, and generate an output value corresponding to the clock as an input value for the ?? modulator;
a second frequency accumulator to operate using the reference signal as a clock, and generate an output value corresponding to the clock;
a comparison operating circuit to compare the output values of the first frequency accumulator and the second frequency accumulator, and calculate a parameter so that a result of the comparison falls within a set value; and
a digital-analog converting circuit to output a signal to be added to an output of the loop filter depending on the parameter output from the comparison operating circuit.

US Pat. No. 10,461,755

DIGITALLY ASSISTED FEEDBACK LOOP FOR DUTY-CYCLE CORRECTION IN AN INJECTION-LOCKED PLL

Oracle International Corp...

1. A duty-cycle correction circuit for an injection-locked phase-locked loop (PLL), comprising a digital calibration circuit, which performs a duty-cycle correction operation by:obtaining a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle;
multiplying the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values;
accumulating the duty-cycle distortion values to produce a duty-cycle-error amplitude;
multiplying the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal; and
using the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

US Pat. No. 10,461,754

SWITCH BETWEEN INPUT REFERENCE CLOCKS OF DIFFERENT FREQUENCIES IN A PHASE LOCKED LOOP (PLL) WITHOUT PHASE IMPACT

TEXAS INSTRUMENTS INCORPO...

1. A phase-locked loop (PLL), comprising:a selection circuit including a plurality of inputs, each input to receive a separate reference clock;
a programmable reference clock divider to divide down the reference clock selected by the selection circuit to generate a divided down reference clock;
an analog phase-locked loop (APLL) to generate an output clock;
a feedback clock divider coupled to an output of the APLL, the feedback clock divider to divide down the output clock to generate a feedback clock;
a time-to-digital converter (TDC) coupled to an output of the reference clock divider and an output of the feedback clock divider, the TDC to generate a digital output value based on a phase difference between the divided down reference clock and the feedback clock;
an invalid clock detection circuit to detect whether each of the reference clocks provided to the selection circuit is valid or invalid, wherein, for a reference clock detected by the invalid clock detection circuit to be invalid, the invalid clock detection circuit is to assert an error signal; and
a circuit including a finite state machine, the circuit to cause, responsive to assertion of the error signal for a current reference clock, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.

US Pat. No. 10,461,753

PULSE-BASED SYNCHRONIZATION TRAINING FOR SYNCHRONOUS DIGITAL AND MIXED-SIGNAL SYSTEMS

SEAKR ENGINEERING, INC., ...

1. A method of synchronizing clock signals in a system implemented in a space-based or high-altitude asset, the system comprising a central device having a central device clock and a destination device having a destination device clock, the method comprising:(a) obtaining a first delay amount;
(b) providing, by the central device, a pulse signal to the destination device, wherein the pulse signal is advanced or retarded by the delay amount;
(c) detecting, at the destination device, the pulse signal;
(d) in response to detecting the pulse signal, obtaining, at the destination device, a sample of the destination device clock and storing the sample in a register;
(e) providing the sample of the destination device clock to the central device;
(f) determining, by the central device, whether enough samples are stored in the register to enable calculation of a phase offset between the central device clock and the destination device clock, wherein the phase offset may be calculated when an edge of the destination device clock is detected based on the samples;
(g) in accordance with a determination that a phase offset cannot be calculated, adjusting the first delay amount and repeating steps (a)-(f); and
(h) in accordance with a determination that the phase offset can be calculated, then calculating, by the central device, the phase offset based on a position, in the register, of the sample representing the edge of the destination device clock.

US Pat. No. 10,461,751

FE-FET-BASED XNOR CELL USABLE IN NEUROMORPHIC COMPUTING

Samsung Electronics Co., ...

1. A computing cell for performing a XNOR operation of an input signal with a weight comprising:at least one pair of FE-FETs coupled with a plurality of input lines and storing the weight, the at least one pair of FE-FETs including a first FE-FET and a second FE-FET, the first FE-FET receiving the input signal and storing a first weight, the second FE-FET receiving the input signal complement and storing a second weight, the first FE-FET and the second FE-FET being coupled to form a dynamic storage node;
a plurality of selection transistors coupled with the at least one pair of FE-FETs; and
a reset transistor having a reset transistor source, a reset transistor gate and a reset transistor drain, the reset transistor source being connected to the dynamic storage node, the reset transistor gate being coupled with a reset line.

US Pat. No. 10,461,750

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device comprising:an input/output (IO) signal receiver circuit; and
a latch circuit connected to the IO signal receiver circuit,
wherein the latch circuit includes
a first inverter configured to output a first signal based on an input signal received from the IO signal receiver circuit,
a plurality of N1 inverters connected in series with the first inverter,
a second inverter configured to output a first clock signal based on a first strobe signal,
a plurality of N2 inverters connected in series with the second inverter,
a third inverter configured to output a second clock signal based on a second strobe signal which is an inversion signal of the first strobe signal,
a plurality of N3 inverters connected in series with the third inverter,
a first clock generation circuit which is connected to an output terminal of the second inverter and is configured to generate a third clock signal from the first clock signal, wherein logical level transitions in the third clock signal are delayed with respect to the first clock signal and are completed in a shorter amount of time than the first clock signal,
a second clock generation circuit which is connected to an output terminal of the third inverter and is configured to generate a fourth clock signal from the second clock signal, wherein logical level transitions in the fourth clock signal are delayed with respect to the second clock signal and are completed in a shorter amount of time than the first clock signal,
a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and
a data latch circuit configured to latch an output signal of the fourth inverter in accordance with the third and fourth clock signals, and
wherein (N1+1) is an odd integer equal to 3 or more and both N2 and N3 are equal to (N1+1).

US Pat. No. 10,461,747

LOW POWER CLOCK GATING CIRCUIT

Apple Inc., Cupertino, C...

1. A circuit comprising:an input circuit configured to receive an enable signal;
clock enable circuitry configured to receive a clock signal;
a latch configured to capture and store an enabled state of the enable signal, wherein the enabled state corresponds to the enable signal being in an active state, wherein the latch comprises a feed forward circuit having a feed forward node and a feedback circuit having a feedback node, wherein the feedback circuit is coupled to provide a feedback signal to the feed forward circuit, wherein the feed forward circuit is configured to capture a current state of the enable signal when the clock signal is inactive, and wherein the feedback circuit is configured to cause the feed forward circuit to retain the enabled state of the enable signal when the clock signal transitions from a logic high state to a logic low state, wherein respective states of a signal on the feed forward node and the feedback signal are independent of a state of the clock signal when the latch is in the enabled state, and wherein the state of the feedback signal is dependent on the state of the signal of the feed forward node;
an output circuit configured to provide an output signal corresponding to a state of the clock signal when the latch is storing the enabled state;
wherein the circuit is configured such that dynamic power consumption does not change responsive to a change in the state of the clock signal when the latch is not storing the enabled state.

US Pat. No. 10,461,746

PROXIMITY SWITCH ASSEMBLY AND METHOD THEREFOR

Ford Global Technologies,...

1. A proximity switch assembly comprising:a proximity switch comprising a proximity sensor providing an activation field; and
control circuitry monitoring a signal responsive to the activation field and determining an activation of the switch based on detecting a first peak value above a threshold when the signal is not stable, followed by a drop and a subsequent rise to a second peak value followed by a sharp drop, wherein the control circuitry further delays recalibration of the switch assembly by a predetermined time period when the signal is detected dropping fast.

US Pat. No. 10,461,745

SENSOR ELECTRODE FOR CAPACITIVE SENSOR DEVICE IN A KEYBOARD HAVING A WIDTH DECREASING TOWARDS ITS CENTER

MICROCHIP TECHNOLOGY GERM...

1. A sensor electrode (SE) for a capacitive sensor device, comprising a plurality of sensor segments separated by insulating spaces and distributed along a line, wherein each sensor segment has a width extending along the line, wherein the width of a sensor segment arranged at a longitudinal center area of the line is smaller than the width of a sensor segment arranged at a beginning or an end of the line defining the sensor electrode, wherein the width of each sensor element is chosen such that the capacity between the sensor electrode and an object (F) with constant distance between the sensor electrode and the object (F) substantially is equal in size for each position of the object (F) relative to the sensor electrode along a longitudinal axis of the sensor electrode and wherein the plurality of sensor segments are electrically short-circuited to one another.

US Pat. No. 10,461,744

PROXIMITY SENSOR CONNECTION MECHANISM

Google LLC, Mountain Vie...

1. An electronic device, comprising:a display assembly comprising an electronic display configured to generate an optical image viewable from in front of the electronic device;
a proximity sensor coupled to at least a portion of the display assembly, the proximity sensor comprising a sensing element configured to be responsive to presence of an object in front of the electronic device, the sensing element supported by a support structure having an upper surface facing a frontal direction of the electronic device, wherein the support structure comprises a body carrying a housing of the proximity sensor within which the sensing element is disposed; and
a conductor that electrically connects the sensing element of the proximity sensor and the portion of the display assembly, the conductor comprising a conductive path extending along the support structure to the upper surface of the support structure.

US Pat. No. 10,461,743

INTERACTIVE DISPLAY SYSTEM AND METHOD FOR USE WITH LOW EMISSIVITY GLASS USING INFRARED ILLUMINATION

imageSurge, Inc., Cambri...

1. A method for operating an interface device on a retail storefront with low emissivity glass, the method comprising:providing the interface device mounted to a first surface of the low emissivity glass with all components of the interface device inside the retail storefront and opposite a second surface of the low emissivity glass outside of retail storefront, the interface device comprising a plurality of infrared(IR) mountable switches each comprising:
at least one infrared (IR) emitter configured to emit IR radiation through the low emissivity glass; and
at least one IR sensor configured to detect a reflection of the IR radiation through the low emissivity glass;
generating, using emitted IR radiation transmitted directly through the low emissivity glass by the at least one IR emitter, at least one trigger area with a reflective zone on the second surface of the low emissivity glass opposite the first surface and at a location substantially opposite the at least one IR emitter of the interface device;
wherein the at least one IR sensor is calibrated to detect reflection of IR radiation reflected back through the low emissivity glass by an IR-reflective object when the at least one IR emitter emits the IR radiation through the low emissivity glass;
detecting, by the at least one IR sensor, a no touch value of IR radiation when no object is in front of the reflective zone, the no touch value comprising a measured value of IR radiation caused by ambient light;
detecting, by the at least one IR sensor, a touch value when the IR radiation emitted from the at least one IR emitter impacts the IR-reflective object located at the reflective zone and reflects back through the low emissivity glass in the reflective zone to the at least one IR sensor, the touch value of IR radiation being greater than the no touch value of IR radiation;
wherein the at least one IR sensor both emits and detects IR radiation in a combined configuration working in conjunction with the at least one IR emitter;
wherein the at least one emitter, the at Ieast one IR sensor and printed circuit board (PCB) components are placed within a multi-layered system further comprising at least one decoupling capacitor placed between the least one IR sensor and the at least one IR emitter as a physical radiation barrier between the at least one IR sensor and at least one IR emitter; and
providing the touch value as a signal input to an interactive display device.

US Pat. No. 10,461,742

CHIP, SELECTABLE MODE BUFFER CIRCUIT AND MODE SELECTING METHOD THEREOF

Novatek Microelectronics ...

1. A selectable mode buffer circuit, comprising:a plurality of pads;
a binary mode selecting circuit, having a plurality of switches, coupled to the pads, the binary mode selecting circuit selecting only one of a charge pumping operation and an interfacing operation for operating according to on or off status of at least one of the switches changed by a mode selecting signal; and
a control circuit, receiving the mode selecting signal, and generating a plurality of input signals for controlling the switches according to the mode selecting signal,
wherein, when the binary mode selecting circuit selecting the charge pumping operation for operating, the binary mode selecting circuit pumps up a power voltage to generate an output voltage,
when the binary mode selecting circuit selecting the interfacing operation for operating, the binary mode selecting circuit buffers an input signal to generate an output signal.

US Pat. No. 10,461,738

COMPARATOR ARCHITECTURE AND RELATED METHODS

QUALCOMM Incorporated, S...

1. A system including:a first stage configured to receive an input voltage and a reference voltage, the first stage including an input transistor pair, wherein:
the input voltage is coupled to the input transistor pair;
the input transistor pair is coupled to ground; and
the input transistor pair includes at a common drain a high-gain node having a high-gain node voltage; and
a second stage coupled to the high-gain node and configured to generate an output voltage based on a difference between the input voltage and the reference voltage, the second stage comprising a resistor and an inverter transistor pair, wherein:
gates of the inverter transistor pair are coupled to the high-gain node of the first stage; and
the resistor couples the high-gain node of the first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of the first stage.

US Pat. No. 10,461,733

PARALLELING POWER SWITCHES USING A DIFFERENTIAL MODE CHOKE IN THE GATE DRIVE LOOP

Power Integrations, Inc.,...

1. A power module, comprising:a first power switch having a first gate;
a second power switch paralleled with the first power switch and having a second gate;
a third power switch paralleled with the first and the second power switches and having a third gate;
a terminal coupled to receive a gate drive signal from a gate driver;
a first conduction path to couple the gate drive signal to the first gate;
a second conduction path to couple the gate drive signal to the second gate;
a third conduction path to couple the gate drive signal to the third gate;
a distribution choke to distribute the gate drive signal to the first and second power switches, the distribution choke having a first winding disposed in the first conduction path and a second winding disposed in the second conduction path, the distribution choke coupled in a differential mode;
a second distribution choke to distribute the gate drive signal, the second distribution choke comprising a third winding disposed in the first conduction path and a fourth winding disposed in the third conduction path; and
a third distribution choke to distribute the gate drive signal, the third distribution choke comprising a fifth winding disposed in the second conduction path.

US Pat. No. 10,461,732

SYSTEM AND METHOD OF DRIVING A POWER SWITCH IN COMBINATION WITH REGULATED DI/DT AND/OR DV/DT

Infineon Technologies Aus...

1. A gate drive circuit for controlling a gate-controlled component, the gate drive circuit comprising:a dynamic controller configured to receive an input reference signal and to control a gate voltage of the gate-controlled component via an output terminal of the gate drive circuit;
at least one component feedback circuit for the dynamic controller, the at least one component feedback circuit configured to provide feedback from at least one of a time derivative of a load path voltage or a time derivative of a load path current of the gate-controlled component to the dynamic controller; and
a gate drive feedback circuit for the dynamic controller, the gate drive feedback circuit configured to provide feedback from a time derivative of a voltage at the output terminal of the gate drive circuit.

US Pat. No. 10,461,731

POWER SUPPLY DEVICE

ULVAC, INC., Chigasaki (...

1. A power supply device comprising:a DC power source configured to output a DC voltage;
a high frequency amplifying circuit configured to generate a high frequency current by repeatedly turning on and turning off a semiconductor switch connected to the DC power source;
a high frequency output circuit configured to supply the high frequency current to a load;
a main reactance circuit having a predetermined reactance value, the main reactance circuit having a first end connected to the high frequency amplifying circuit and a second end connected to the high frequency output circuit;
a protection circuit connected in parallel to the main reactance circuit between the high frequency amplifying circuit and the high frequency output circuit, the protection circuit including:
a DC voltage source configured to supply a predetermined reference voltage;
a switch circuit configured to turn on when a turning on voltage larger than the predetermined reference voltage is applied, the switch circuit including:
a reference capacitance element to be charged by the reference voltage; and
a diode element to be reverse-biased by a charged voltage of the reference capacitance element; and
a sub-reactance circuit having a predetermined reactance value, wherein:
an absolute value of an impedance of a parallel connection circuit of the protection circuit and the main reactance circuit, when the switch circuit is turned on, is set to be larger than an absolute value of an impedance of the parallel connection circuit of the protection circuit and the main reactance circuit when the switch circuit is turned off,
once the switch circuit is turned on, an absolute value of an impedance on a load side of the high frequency amplifying circuit becomes larger than an absolute value of an impedance when the protection circuit is turned off, so that the high frequency current is limited, and
the turning on voltage is applied to the switch circuit, the diode element is forward-biased to turn on, and the switch circuit is then turned on.

US Pat. No. 10,461,730

ADAPTIVE MULTI-LEVEL GATE DRIVER

Infineon Technologies Aus...

1. A gate driver circuit for driving a power switch comprising:a gate driver having a first input for receiving an input signal and an output coupled to the power switch, the gate driver configured for providing a primary gate current and an auxiliary gate current; and
a differential voltage sensor having a first input for receiving the input signal, a second input coupled to a power supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to a second input of the gate driver,
wherein the gate driver comprises a primary driver configured for providing the primary gate current and an auxiliary driver configured for providing the auxiliary gate current, and
wherein the primary driver is coupled to the first input of the gate driver and the auxiliary driver is coupled to the second input of the gate driver.

US Pat. No. 10,461,727

SYSTEM AND METHOD FOR GENERATING PLURALITY OF SHORT RF PULSES

H6 SYSTEMS INC., Nashua,...

1. A system for generating a plurality of short RF pulses for use in determining susceptibility of an electronic target to interference from microwaves, the system comprising:a first circuit comprising a first power supply and a plurality of first networks for generating a first output signal in a form of a high voltage pedestal pulse which is supplied to a common node;
a second circuit comprising a second power supply and a plurality of second networks for generating a second output signal in a form of a high voltage short pulse which is supplied to the common node;
the high voltage pedestal pulse passing through a blocking inductor and being combined with the high voltage short pulse such that the high voltage short pulse being stacked on top of the high voltage pedestal pulse to form a stacked combined high voltage pulse; and
a low frequency magnetron being coupled to the common node for receiving the stacked combined high voltage pulse and generating a short RF pulse which has a duration of time which is less than 130 nanoseconds and useful in determining the susceptibility of an electronic target to interference from microwaves.

US Pat. No. 10,461,726

COMPENSATED COMPARATOR

1. A compensated comparator, comprising:first and second inputs configured to receive, respectively, first (Vin1) and second (Vin2) input potentials to be compared;
a differential stage provided with first and second transistors of a same type, connected by sources thereof in a node (S) and respectively comprising a first gate and a second gate;
a decision stage connected to drains of the first and second transistors and delivering a comparison signal on an output of the comparator;
first and second capacitors intercalated, respectively, between the first gate and the first input and between the second gate and the second input;
first and second decision switches disposed between the decision stage and the drains of the first and second transistors of the differential stage; and
pre-charge, sharing, and decision devices commanded by a control circuit, configured to implement successive pre-charge, sharing, and decision phases,
the pre-charge device being configured to impose a charge on the first and second capacitors such that a pre-charge voltage is present at terminals of the capacitors at an end of the pre-charge phase,
the sharing device being configured to short circuit a gate and a drain of each of the first and second transistors, the short circuit causing a charge transfer from the first and second capacitors to the node (S), the charge transfer being interrupted from a moment that gate-source voltages of the first and second transistors become lower than respective threshold voltages of the first and second transistors, and
the decision device being configured to switch on the decision switches and to make a comparison between the first (Vin1) and second (Vin2) input potentials applied on the first and second inputs.

US Pat. No. 10,461,725

VOLTAGE COMPARATOR, VOLTAGE COMPARISON METHOD OF THE SAME, AND RESET METHOD OF THE SAME

ELECTRONICS AND TELECOMMU...

1. A voltage comparator comparing a voltage of a first input signal and a voltage of a second input signal, comprising:a first switch pair transmitting, respectively, the first input signal and the second input signal to a gate of a first transistor and a gate of a second transistor in response to a clock signal;
a second switch pair connecting a drain and a source of the first transistor and connecting a drain and a source of the second transistor in response to at least one of the clock signal and a reset signal; and
a first reset switch connecting the gate of the first transistor and the gate of the second transistor in response to the reset signal.

US Pat. No. 10,461,722

FREQUENCY SPREADING CIRCUIT

DENSO CORPORATION, Kariy...

1. A frequency spreading circuit comprising:a ring oscillator configured with a multiple number of logic inverting circuits in a ring shape for generating multi-phase clock signals;
a period measuring unit configured to measure a period of a reference clock, which is inputted, by the multi-phase clock signals of the ring oscillator and output a measured period as a period data value;
a frequency spreading calculation unit configured to calculate a frequency spreading command value in accordance with a frequency spreading rate, a frequency spreading period and the period data value of the period measuring unit, which are inputted; and
a pulse generation unit configured to generate a clock pulse corresponding to the frequency spreading command value in accordance with a data value determined by addition of the frequency spreading command value to the period data value.

US Pat. No. 10,461,716

LOW-PASS FILTER

TDK CORPORATION, Tokyo (...

3. A low-pass filter comprising:a first input/output port;
a second input/output port;
a first LC parallel resonator and a second LC parallel resonator connected in series and provided between the first input/output port and the second input/output port;
a first path;
a second path;
a third path;
a multilayer stack for integrating the first and second input/output ports, the first and second LC parallel resonators and the first to third paths, the multilayer stack including a plurality of dielectric lavers stacked to be aligned in a first direction, the multilayer stack having a first end face and a second end face located at opposite ends in the first direction; and
a ground terminal provided on the first end face of the multilayer stack and connected to the third path, wherein
the first LC parallel resonator has a plurality of ends including a first end, the first end being closest to the first input/output port in circuit configuration as compared to all other ones of the plurality of ends of the first LC parallel resonator,
the second LC parallel resonator has a plurality of ends including a second end, the second end being closest to the second input/output port in circuit configuration as compared to all other ones of the plurality of ends of the second LC parallel resonator,
the first path includes a first LC series resonator and connects the first end to a ground,
the second path includes a second LC series resonator and connects the second end to the ground,
the third path include, a third-path capacitor and connects a connection point between the first and second LC parallel resonators to the ground,
the third path has an inductance lower than an inductance of each of the first path and the second path, and
a physical connection corresponding to the connection point between the first and second LC parallel resonators, the third-path capacitor, and the ground terminal are arranged to intersect or contact one imaginary straight line extending in the first direction.

US Pat. No. 10,461,715

MITIGATING POWER NOISE USING A CURRENT SUPPLY

INTERNATIONAL BUSINESS MA...

11. A system for mitigating power noise using a current supply, the system comprising:an integrated circuit operably coupled to a first circuit over a first path;
a controller configured to determine a variation of a current level in the integrated circuit; and
a second circuit operably coupled to the integrated circuit over a second path, wherein the second circuit is configured to provide additional power to the integrated circuit based at least in part on the determined variation of the current level.

US Pat. No. 10,461,714

CLASS D AMPLIFIER CIRCUIT

Cirrus Logic, Inc., Aust...

1. A Class-D amplifier circuit for amplifying a digital input signal comprising a controller configured to control the Class-D amplifier circuit to selectively transition between an open-loop operational mode and a closed-loop operational mode based on indication of amplitude of said digital input signal, wherein the controller is configured to control the Class-D amplifier circuit in the open-loop operational mode if the indication of the amplitude of the digital input signal is below a first amplitude threshold and to control the Class-D amplifier circuit in the closed-loop operational mode if the indication of the amplitude of the digital input signal is above said first amplitude threshold.

US Pat. No. 10,461,713

RADIO-FREQUENCY AMPLIFIER DEVICE

Nordic Semiconductor ASA,...

1. A radio-frequency (RF) amplifier device, comprising:a signal input for receiving an RF electrical signal;
a variable-gain amplifier for amplifying the received RF electrical signal;
a signal output for outputting the amplified RF electrical signal;
a serial input for receiving serialised data encoding a custom gain level;
a memory for storing data representative of the custom gain level;
a binary input for switching a gain of the amplifier between a first level and the custom gain level;
configuration logic configured to receive serialised data encoding the custom gain level at the serial input, and to store data representative of the custom gain level in the memory; and
gain-control logic configured to read the data representative of the custom gain level from the memory, and to set the gain of the amplifier to the first level or to the custom gain level in dependence on a state of the binary input.

US Pat. No. 10,461,711

METHOD AND APPARATUS FOR OUTPUTTING AUDIO SIGNAL, METHOD FOR CONTROLLING VOLUME

Gaonda Corporation, Goya...

1. A method for outputting an audio signal, the method comprising:measuring, by a processor, a first hearing threshold of a user in a frequency band among a plurality of predefined frequency bands;
setting, by the processor, an output level of a modulated signal in the frequency band to a level less than or equal to a level of the first hearing threshold;
setting, by the processor, an output level of an audio signal in the frequency band to a level greater than the level of the first hearing threshold, wherein the output level of the audio signal is determined using a weight value and the level of the first hearing threshold, such that an increase of the level of the first hearing threshold causes a decrease of a rate of increase of the output level of the audio signal in the frequency band;
outputting, by the processor, the modulated signal and the audio signal simultaneously via an audio output unit, wherein the modulated signal is outputted at a level that is equal to the level of the first hearing threshold;
outputting, by the processor, an interface via a display unit, the interface including:
i) a frequency selection module for selecting one of the plurality of predefined frequency bands on a display unit,
ii) a visual information output module for outputting a visual signal which changes in synchronization with a modulation pattern of the modulated signal for each respective frequency band of the plurality of predefined frequency bands, the visual signal being output in a different visual pattern for each frequency band according to the modulation pattern, and
iii) a volume adjustment module for dynamically adjusting the first hearing threshold according to an improvement in hearing of the user by adjusting an intensity of a modulated signal of the selected frequency band such that the modulated signal of the selected frequency band is not audible,
wherein the visual information output module is outputted at a position in a central area of the volume adjustment module, the visual signal outputted by the visual information output module for each frequency band changes according to the same modulation pattern as that of the corresponding modulation signal, and the visual signal is outputted at a fixed position when the volume adjustment module is adjusted;
receiving, by the processor, response information of the user via the interface responding to the visual signals for the respective frequency bands when the user perceives one or more of the modulated signals for the respective frequency bands as a result of the improvement in hearing of the user;
adjusting, by the processor, an output level of the one or more perceived modulated signals based on the response information of the user until the modulated signal is no longer heard by the user;
measuring, by the processor, a second hearing threshold of the user in the frequency band that is lower than the first hearing threshold based on response information received from the user; and
adjusting, by the processor, the respective output levels of the modulated signal and the audio signal based on the second hearing threshold,
wherein the adjusting of the respective output levels of the modulated signal and the audio signal includes lowering the output level of the modulated signal to a level less than or equal to a level of the second hearing threshold and lowering the output level of the audio signal to a level greater than the level of the second hearing threshold.

US Pat. No. 10,461,710

MEDIA PLAYBACK SYSTEM WITH MAXIMUM VOLUME SETTING

Sonos, Inc., Santa Barba...

1. A controller device of a media playback system, the controller device comprising:a network interface configured to communicatively couple the controller device to at least one playback device of the media playback system;
an input interface;
at least one processor;
a non-transitory computer-readable medium having instructions stored thereon, wherein the instructions, when executed by the at least one processor, cause the controller device to:
receive, via the input interface, a request to change a volume level of the at least one playback device to a requested volume level;
send, via the network interface to the at least one playback device, an instruction indicative of the requested change to the volume level, wherein sending the instruction causes the at least one playback device to adjust a volume level of the at least one playback device to a first adapted volume level that is lower than the requested volume level; and
after the volume level of the at least one playback device has been adjusted to the first adapted volume level, output an indication of an adjustment to the volume level of the at least one playback device, wherein the indication of the adjustment is representative of the requested volume level.

US Pat. No. 10,461,709

AMPLIFIER WITH AUXILIARY PATH FOR MAXIMIZING POWER SUPPLY REJECTION RATIO

Cirrus Logic, Inc., Aust...

1. An amplifier, comprising:a main signal path having a plurality of stages compensated by feedback elements, the plurality of stages comprising an output stage configured to receive electrical energy from a power supply; and
an auxiliary path independent of the main signal path and comprising an output stage compensation circuit configured to:
generate a compensation current proportional to noise present in the power supply; and
apply the compensation current to cancel a power supply-induced current present in at least one of the feedback elements.

US Pat. No. 10,461,708

SIGNAL AMPLIFIER, SIGNAL RECEIVING CIRCUIT INCLUDING THE SAME, AND DEVICE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A signal amplifier, comprising:a first amplifier to amplify a first input signal to form a first amplified output signal, the first input signal having a common mode voltage in a first voltage range and the first amplified output signal having a common mode voltage in a second voltage range different from the first voltage range;
a second amplifier to amplify a second input signal to form a second amplified output signal, the second input signal, different from the first input signal, having a common mode voltage in the second voltage range and the second amplified output signal having a common mode voltage in the second voltage range, wherein the first amplifier is off when the second amplifier is on and the second amplifier is off when the first amplifier is on; and
an output to output the first amplified output signal or the second amplified output signal as an amplified output signal.

US Pat. No. 10,461,707

AMPLIFIER CLASS AB OUTPUT STAGE

TEXAS INSTRUMENTS INCORPO...

1. An amplifier, comprising:an input stage;
a folded cascode stage coupled to the input stage; and
a class AB output stage coupled to the folded cascode stage, the class AB output stage comprising:
a high-side output transistor;
a low-side output transistor; and
a high-side feedback circuit coupled to the high-side output transistor, the high-side feedback circuit comprising:
a high-side sense transistor comprising a control terminal, wherein the control terminal of the high-side sense transistor is coupled to a control terminal of the high-side output transistor; and
a high-side feedback transistor coupled to an output of the high-side sense transistor and to the folded cascode stage;
wherein a first output of the folded cascode stage is coupled to the control terminal of the high-side sense transistor and the control terminal of the high-side output transistor;
wherein the high-side feedback transistor is configured to operate as a degeneration resistor.

US Pat. No. 10,461,704

SWITCHLESS MULTI INPUT STACKED TRANSISTOR AMPLIFIER TREE STRUCTURE

pSemi Corporation, San D...

1. A multi-input cascode amplifier configuration comprising:an input stage comprising a plurality of input transistors configured to receive a plurality of input RF signals; and
a plurality of cascode stages comprising an output stage,
wherein the input transistors of the input stage and cascode transistors of the plurality of cascode stages are connected according to a tree structure so that at least one cascode transistor of a first cascode stage of the plurality of cascode stages is coupled to at least two cascode transistors of a second cascode stage of the plurality of cascode stages, and
wherein the output stage comprises one or more cascode transistors, each cascode transistor of the one or more cascode transistors coupled via a drain of said cascode transistor to a supply voltage.

US Pat. No. 10,461,701

SYSTEM AND METHOD FOR REDUCING OUTPUT HARMONICS

SILICON LABORATORIES INC....

1. A power amplifier system, comprising:an amplification stage including a first amplifier having an input for receiving an input signal, a control input for receiving a first control signal, and an output, and a second amplifier having an input coupled to said output of said first amplifier, a control input for receiving a second control signal, and an output;
a low-pass filter having a first input coupled to said output of said first amplifier, a second input coupled to said output of said second amplifier, and an output; and
a controller having a first input coupled to said output of said low-pass filter, a first output coupled to said control input of said first amplifier, and a second output coupled to said control input of said second amplifier, wherein said controller varies said first control signal to reduce a difference between said output of said low-pass filter and a first target voltage level, and varies said second control signal to reduce a difference between said output of said low-pass filter and a second target voltage level.

US Pat. No. 10,461,700

TEMPERATURE COMPENSATED OSCILLATOR

SKYWORKS SOLUTIONS, INC.,...

1. A relaxation oscillator comprising:a proportional to absolute temperature (PTAT) biasing unit configured to output a bias signal, the PTAT biasing unit being formed in an integrated circuit;
an additional biasing unit configured to receive the bias signal from the PTAT biasing unit and generate an output signal based on the bias signal;
a voltage-controlled RC relaxation oscillator core including first and second cross-coupled MOSFETs each having a gate, a source, and a drain, and a capacitor coupled between the source of the first MOSFET and the source of the second MOSFET, the gate of the first MOSFET being coupled to the drain of the second MOSFET and the gate of the second MOSFET being coupled to the drain of the first MOSFET, the oscillator core configured to generate an oscillating signal upon receiving the output signal from the additional biasing unit, the oscillating signal having a smooth profile and a fundamental frequency of less than five megahertz (MHz); and
an enable unit coupled to the oscillator core and configured to operate the oscillator core in one of an active mode in which the oscillating signal is generated and a sleep mode in which the oscillating signal is not generated, the enable unit being formed in the integrated circuit with the PTAT biasing unit, the additional biasing unit, and the oscillator core.

US Pat. No. 10,461,695

PLANAR DIFFERENTIAL INDUCTOR WITH FIXED DIFFERENTIAL AND COMMON MODE INDUCTANCE

QUALCOMM Incorporated, S...

1. A planar differential inductor, comprising:a ground plane;
a plurality of routing lines;
a bypass capacitor array coupled between the ground plane and the plurality of routing lines;
an exterior inductor structure coupled between the plurality of routing lines and a power supply; and
an interior inductor located within the ground plane and coupled between the plurality of routing lines and differential ports, the plurality of routing lines at least partially surrounding the interior inductor.

US Pat. No. 10,461,694

CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, VEHICLE, AND MANUFACTURING METHOD FOR CIRCUIT DEVICE

SEIKO EPSON CORPORATION, ...

1. A circuit device comprising:an A/D conversion circuit configured to perform A/D conversion on a temperature detection voltage from a temperature sensor so as to output temperature detection data; and
a digital signal processing circuit configured to perform a temperature compensation process based on the temperature detection data,
wherein the A/D conversion circuit
operates in a first mode so as to obtain the temperature detection data by performing an A/D conversion process according to a first A/D conversion method, and
switches to a second mode so as to obtain the temperature detection data by performing an A/D conversion process according to a second A/D conversion method which is different from the first A/D conversion method in a case where a predetermined condition is established,
wherein, in a case where the minimum resolution of data in A/D conversion is indicated by LSB, the first A/D conversion method is a process of obtaining the temperature detection data such that a change in the temperature detection data at a second output timing following a first output timing with respect to the temperature detection data at the first output timing is equal to or less than k×LSB (where k is a positive integer satisfying k

US Pat. No. 10,461,693

CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT

Seiko Epson Corporation, ...

1. A circuit device comprising:an A/D conversion unit that performs A/D conversion of a temperature detection voltage from a temperature sensor unit and outputs temperature detection data;
a processing unit that performs a temperature compensation process of an oscillation frequency based on the temperature detection data and outputs frequency control data of the oscillation frequency;
an oscillation signal generating circuit that generates, using the frequency control data from the processing unit and a resonator, an oscillation signal at the oscillation frequency set by the frequency control data, wherein
the oscillation signal generating circuit includes
a D/A conversion unit that performs D/A conversion of the frequency control data from the processing unit, and
an oscillation circuit that generates the oscillation signal using an output voltage of the D/A conversion unit and the resonator, and
wherein, in a plan view of a substrate comprising the A/D conversion unit, the D/A conversion unit, the processing unit, and the oscillation circuit:
the D/A conversion unit is disposed on a first side of the A/D conversion unit,
the processing unit is disposed on a second side of the A/D conversion unit and the D/A conversion unit, the second side being perpendicular to the first side, and
the oscillation circuit is disposed on a third side or the first side of the D/A conversion unit, the third side being opposite to the second side;
a first reference voltage generating circuit that is electrically coupled to a first power supply terminal and supplies a first reference voltage to the processing unit;
a second reference voltage generating circuit that is electrically coupled to the first power supply terminal and generates a second reference voltage; and
a reference current generating circuit that generates a reference current based on the second reference voltage,
wherein the oscillation circuit causes the resonator to oscillate with a drive current based on the reference current.

US Pat. No. 10,461,692

DUAL-MODE OSCILLATOR AND MULTI-PHASE OSCILLATOR

HUAWEI TECHNOLOGIES CO., ...

1. A dual-mode oscillator, comprising:two transformer-coupled oscillators, wherein each of the two transformer-coupled oscillators comprises:
a differential metal oxide semiconductor (MOS) transistor pair, wherein the differential MOS transistor pair comprises:
a first MOS transistor comprising a first source terminal, a first gate terminal, and a first drain terminal, wherein the first source terminal is electrically coupled to a constant-voltage node; and
a second MOS transistor comprising a second source terminal, a second gate terminal, and a second drain terminal, wherein the second source terminal is electrically coupled to the constant-voltage node;
a step-up transformer coupled to the first MOS transistor and the second MOS transistor, wherein the step-up transformer comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end and the first output end are dotted terminals;
a primary capacitor coupled to the first MOS transistor and the second MOS transistor, wherein the primary capacitor comprises a first primary capacitor end and a second primary capacitor end, wherein the first drain terminal is coupled to the first primary capacitor end and the first input end, wherein the second drain terminal is coupled to the second primary capacitor end and to the second input end; and
a secondary capacitor comprising a first secondary capacitor end and a second secondary capacitor end, wherein the first gate terminal is directly coupled to each of the first secondary capacitor end and the second output end, wherein the second gate terminal is directly coupled to each of the second secondary capacitor end and the first output end; and
a mode switching circuit electrically coupled to each of the two transformer-coupled oscillators, wherein the mode switching circuit is located between the two transformer-coupled oscillators and is separately coupled to a drain terminal of each of the two transformer-coupled oscillators, and wherein the mode switching circuit is configured to change an oscillation frequency range output by the dual-mode oscillator using switching.

US Pat. No. 10,461,691

SOLAR TESTING DEVICE

PASAN SA, Neuchatel (CH)...

1. A solar testing device for testing a solar cell or a solar module comprising:a test area for at least one solar cell or solar module to be tested,
a light emitting area, arranged opposite to the test area, comprising:
an array of LED-modules arranged with a pitch (P) to each other, and
sidewall mirrors, extending in a direction from the light emitting area to the test area, the reflecting surface of said sidewall mirrors being inclined at an obtuse angle relative to a planar surface of the light emitting area,
wherein a ratio between the distance (H) between the light emitting area and the test area and the pitch (P) of the LED-modules lies in a range of 1.5 to 3.5.

US Pat. No. 10,461,690

DEFECT INSPECTION METHOD AND SYSTEM FOR SOLAR CELL

Industrial Technology Res...

1. A defect inspection method for a solar cell, applicable to a defect inspection system having a measuring device, a processing device, and an output device, wherein the processing device is connected to the measuring device and the output device, and wherein the method comprises:measuring a plurality of output voltages and a plurality of output currents of the solar cell by the measuring device;
generating a stepwise current-voltage curve (stepwise IV curve) and a fitted current-voltage curve (fitted IV curve) by the processing device according to the output voltages and the output currents, wherein the stepwise IV curve comprises a plurality of steps, wherein the fitted IV curve corresponds to an ideal current-voltage curve when the solar cell has no defect;
determining whether a first error of the fitted IV curve is less than a first error tolerance by the processing device;
when the first error is not less than the first error tolerance, determining whether there exists at least one surge in each of the steps of the stepwise IV curve by the processing device so as to accordingly determine whether the solar cell has a defect; and
outputting a determined result of the processing device by the output device.

US Pat. No. 10,461,682

HEIGHT ADJUSTABLE SOLAR PANEL MOUNTING ASSEMBLY

Unirac Inc., Albuquerque...

1. A solar panel mounting assembly, comprising:a mounting bracket including an upper bracket and a lower bracket, the lower bracket including a first slot and a second slot;
a stanchion including a first vertical arm opposite a second vertical arm, the first vertical arm and the second vertical arm each including teeth protruding from respective inside surfaces thereof, respective outside surfaces thereof being smooth and planar, and the teeth of the first vertical arm facing the teeth of the second vertical arm to define an open central region between the first vertical arm and the second vertical arm; and
a helical drive element disposed inside of the open central region between the first vertical arm and the second vertical arm,
wherein:
the upper and lower brackets are coupled to the helical drive element wherein the mounting bracket is vertically adjustable by rotating the freestanding helical drive element,
the first vertical arm is received by the first slot such that the first vertical arm passes through the first slot when the mounting bracket is vertically adjusted, and
the second vertical arm is received by the second slot such that the second vertical arm passes through the second slot when the mounting bracket is vertically adjusted.

US Pat. No. 10,461,673

SINGLE PHASE MOTOR DRIVE CIRCUIT AND A METHOD OF DRIVING A SINGLE PHASE MOTOR

Melexis Bulgaria Ltd., S...

1. A single phase motor drive circuit for driving a single phase motor, the single phase motor drive circuit comprising:a timer unit adapted for receiving a sensor signal indicative of an angular position of a rotor of the single phase motor, and for providing at least one timing signal in phase with the sensor signal;
a waveform generator for generating at least one waveform for energizing the single phase motor, the waveform generator being adapted for receiving the at least one timing signal and for receiving at least one configurable setting, and being adapted for generating the at least one waveform based on the at least one timing signal and based on the at least one configurable setting, the at least one configurable setting consisting of one or more ON-time settings corresponding to time when the waveform is to be non-zero or OFF-time settings corresponding to time when the waveform is to be zero (Noff, Noff_begin, Noff_end); a phase period comprising at most two ON-time settings;
a configuration unit adapted for receiving a first input signal indicative of a desired speed (Vrel) of the single phase motor and for receiving at least one of a second input signal indicative of a supply voltage (Vbat) and a third input signal indicative of a temperature of the single phase motor drive circuit (Temp), the configuration unit being adapted for providing the at least one configurable setting as a function of the first input signal (Vrel) and at least one of the second input signal (Vbat) and the third input signal (temp) to the waveform generator to dynamically configure the waveform generator as a function of the desired speed (Vrel) and at least one of the supply voltage (Vbat) and the temperature of the single phase motor drive circuit;
wherein the motor drive circuit is adapted for applying the waveform to the single phase motor as a baseband signal.

US Pat. No. 10,461,672

ROTOR POSITION SENSING SYSTEM FOR THREE PHASE MOTORS AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. A method for sensing rotor position of a motor, the method comprising:applying, using a controller configured to be coupled with a motor, a plurality of current vectors to the motor, the plurality of current vectors comprising a plurality of dummy current vectors and a plurality of measured current vectors, wherein at least one of the plurality of measured current vectors is applied quadrature to a dummy current vector from the plurality of dummy current vectors preceding each measured current vector;
measuring, with a measurement circuit, a plurality of values corresponding with one of the plurality of measured current vectors; and
calculating, based on the plurality of values and using one or more position algorithms, a position of a rotor of the motor.

US Pat. No. 10,461,670

GENERATOR AND METHOD FOR CONVERTING VIBRATIONAL ENERGY INTO ELECTRICAL ENERGY

PERPETUUM LTD., (GB)

1. An electromechanical generator for converting mechanical vibrational energy into electrical energy, the electromechanical generator comprising: a mass resiliently connected to a body by a biasing device and adapted to oscillate about an equilibrium point relative to the body, wherein the electromechanical generator is configured to convert oscillations of the mass about the equilibrium point relative to the body into electrical energy, and a spring washer disposed between the mass and the body, wherein the mass is adapted to oscillate about the equilibrium point relative to the body with an oscillation amplitude, and the spring washer is configured to be deformed between the mass and the body only when the oscillation amplitude exceeds a predetermined non-zero threshold amplitude.

US Pat. No. 10,461,668

SYSTEMS FOR PROTECTING AND MONITORING POWER ELECTRONIC DEVICES

1. A system for protecting a power electronic device, the system comprising:a power electronic device comprising:
a piezoelectric substrate;
a metal substrate coupled to the piezoelectric substrate;
a semiconductor device; and
a bonding layer positioned between the metal substrate and the semiconductor device such that the metal substrate is bonded to the semiconductor device; and
a controller comprising:
a power supply;
one or more processors; and
one or more memory modules storing computer readable and executable instructions which, when executed by the one or more processors, cause the controller to:
receive a temperature of the power electronic device; and
provide a voltage determined based on the temperature of the power electronic device across the piezoelectric substrate.

US Pat. No. 10,461,665

SWITCH DEVICE FOR AN ELECTRIC MOTOR, CONTROL DEVICE AND STEERING SYSTEM

Robert Bosch GmbH, Stutt...

1. A switch device for an electric motor, comprising:at least one half-bridge having two semiconductor switches configured to energize at least one phase of the electric motor on demand; and
a driver device assigned to the two semiconductor switches and configured to actuate the two semiconductor switches in accordance with an activation signal, the driver device including:
an oscillator configured to generate an operating clock frequency,
an apparatus configured to receive a synchronization signal, and
an adjustment device configured to adjust the operating clock frequency in accordance with the synchronization signal.

US Pat. No. 10,461,663

METHOD FOR DISCHARGING AN ELECTRIC ENERGY STORAGE UNIT

Siemens Aktiengesellschaf...

1. A method for discharging an electrical energy storage device, which is connected to an electronic circuit, by way of a first electrical conductor and a second electrical conductor, the method comprising:providing a thyristor for discharging the energy storage device;
when a fault occurs in the electronic circuit, a discharge current of the energy storage device begins to flow from the energy storage device via the first electrical conductor to the electronic circuit and via the second electrical conductor back to the energy storage device;
generating with the discharge current a temporally varying magnetic field around the first electrical conductor and around the second electrical conductor and causing the magnetic field to pass through a semiconductor material of the thyristor;
inducing a current in the semiconductor material of the thyristor with the temporally varying magnetic field; and
switching the thyristor on by the current induced therein.

US Pat. No. 10,461,660

CONTROL DEVICE OF POWER CONVERSION DEVICE

TOSHIBA MITSUBISHI-ELECTR...

1. A control device of a power conversion device converting alternating current power into direct current power and supplying the direct current power to a direct current circuit, the alternating current power being supplied from an alternating current power supply, the power conversion device being separately-excited and including a first switching circuit, a second switching circuit, and a third switching circuit, the first switching circuit including a first converter arm and a second converter arm connected in series at a first alternating current connection point, the second switching circuit including a third converter arm and a fourth converter arm connected in series at a second alternating connection point, the third switching circuit including a fifth converter arm and a sixth converter arm connected in series at a third alternating current connection point, the first alternating current connection point capable to be connected to a first phase of the alternating current power, the second alternating current connection point capable to be connected to a second phase of the alternating current power, the third alternating current connection point capable to be connected to a third phase of the alternating current power, one end of the first switching circuit, one end of the second switching circuit, and one end of the third switching circuit capable to be connected to a high-voltage side of the direct current circuit, another end of the first switching circuit, another end of the second switching circuit, and another end of the third switching circuit capable to connected to a low-voltage side of the direct current circuit, the control device comprising:a first control circuit controlling a gate pulse of each of the first converter arm and the second converter arm included in the first switching circuit;
a second control circuit controlling a gate pulse of each of the third converter arm and the fourth converter arm included in the second switching circuit; and
a third control circuit controlling a gate pulse of each of the fifth converter arm and sixth converter arm included in the third switching circuit,
the first control circuit including a first power interruption compensation circuit supplying electrical power to the first control circuit for a prescribed amount of time during a power interruption of the first control circuit,
the second control circuit including a second power interruption compensation circuit supplying electrical power to the second control circuit for a prescribed amount of time during a power interruption of the second control circuit, and
the third control circuit including a third power interruption compensation circuit supplying electrical power to the third control circuit for a prescribed amount of time during a power interruption of the third control circuit.

US Pat. No. 10,461,659

SEMICONDUCTOR DEVICE AND POWER CONVERTING DEVICE

SHINDENGEN ELECTRIC MANUF...

1. A semiconductor device configured to convert an inputted voltage and output a converted voltage, comprising:a module substrate;
a first input wiring line disposed on a top surface of the module substrate and including a first portion that extends along a first side of the module substrate and a second portion that extends along a second side, which is adjacent to the first side, the second portion having one end that is connected to one end of the first portion;
a first input terminal disposed on another end of the second portion and electrically connected to the first input wiring line;
a first transistor disposed on the first portion so as to be on a side of the one end of the first portion;
a second transistor disposed on the first portion so as to be on a side of another end of the first portion;
a first power wiring line disposed in a first substrate region that is closer to a central region of the top surface of the module substrate than the first input wiring line, the first power wiring line being adjacent to the one end of the first portion and the second portion of the first input wiring line;
a second power wiring line disposed in a second substrate region that is closer to the central region on the top surface of the module substrate than the first input wiring line, the second power wiring line being adjacent to the first substrate region on a side of a third side that is opposite to the second side;
a third transistor disposed on the first power wiring line;
a fourth transistor disposed on the second power wiring line;
a first output terminal disposed on the first power wiring line and electrically connected to the first power wiring line;
a second output terminal disposed on the second power wiring line and electrically connected to the second power wiring line;
a second input wiring line disposed on the top surface of the module substrate so as to be close to a fourth side that is opposite to the first side and adjacent to the second side of the module substrate;
a second input terminal disposed on the second input wiring line and electrically connected to the second input wiring line;
a module sealing member configured to seal the top surface of the module substrate;
a first control wiring line disposed on the top surface of the module substrate, and having one end that is connected to a control electrode of the first transistor;
a second control wiring line disposed on the top surface of the module substrate, and having one end that is connected to a control electrode of the second transistor;
a first control terminal disposed on another end of the first control wiring line so as to be closer to the second side than the first transistor, and electrically connected to the first control wiring line; and
a second control terminal disposed on another end of the second control wiring line so as to be closer to the third side than the second transistor, and electrically connected to the second control wiring line.

US Pat. No. 10,461,654

POWER SUPPLY LIGHT LOAD EFFICIENCY CONTROL CIRCUIT

Dell Products, LP, Round...

1. A power supply unit operating a light load efficiency control system comprising:a power regulator circuit for receiving an alternating current (AC) input voltage from within a range of accommodated AC input voltages including:
a power factor correction (PFC) circuit and an LLC resonator circuit having a bulk capacitance voltage level and operable to receive the input AC voltage in the power supply unit;
a transformer to step down the input AC voltage; and
a rectifier circuit for generating a DC output voltage;
a processor logic core for the power regulator circuit to control a plural stage bulk capacitor voltage level having at least a high step bulk capacitor voltage level for operation when a normal load is applied to the power supply unit and a low step bulk capacitor voltage level for operation under light load conditions;
a light load control circuit for receiving a control input voltage representative of the AC input voltage received by the power regulator circuit, comparing via a comparator circuit the control input voltage to a reference voltage generated to represent a threshold level of AC input voltage, and activating a light load control feedback signal if the control input voltage exceeds the reference voltage level; and
the processor logic core transitioning the plural stage bulk capacitor voltage level from a low step bulk capacitor voltage level to a high step bulk capacitor voltage level to avoid ringing in the DC output voltage upon receiving the light load control feedback signal from the light load control circuit.

US Pat. No. 10,461,641

REFERENCE VOLTAGE CONTROL IN A POWER SUPPLY

Infineon Technologies Aus...

1. A power supply comprising:a power converter to produce an output voltage to power a load;
a reference voltage generator to generate a floor reference voltage, a magnitude of the floor reference voltage varying as a function of the output voltage;
a controller to produce control output to control the power converter as a function of the floor reference voltage and the output voltage; and
wherein the controller is operable to receive an output voltage feedback signal derived from the output voltage, the controller including a comparator to compare the output voltage feedback signal to the floor reference voltage to produce the control output.

US Pat. No. 10,461,636

VOLTAGE MULTIPLIER CIRCUIT WITH A COMMON BULK AND CONFIGURED FOR POSITIVE AND NEGATIVE VOLTAGE GENERATION

STMicroelectronics Intern...

1. A circuit, comprising:a voltage multiplier circuit including:
a first node configured to receive a first voltage when said voltage multiplier circuit is configured for operation in a positive voltage boosting mode and configured to output a negative voltage when said circuit is configured for operation in a negative voltage boosting mode;
a second node configured to output a positive voltage in excess of said first voltage when said voltage multiplier circuit is configured for operation in the positive voltage boosting mode and configured to receive a second voltage in excess of said negative voltage when said circuit is configured for operation in a negative voltage boosting mode; and
a plurality of transistors of a same conductivity type and sharing a common bulk that is not tied to a source of any transistor in said plurality of transistors; and
a bias generator circuit coupled to receive a first voltage from the first node and second voltage from the second node, said bias generator circuit configured to apply a lower one of the first and second voltages to the common bulk.

US Pat. No. 10,461,634

CHARGE PUMP CIRCUIT FOR PROVIDING VOLTAGES TO MULTIPLE SWITCH CIRCUITS

FAIRCHILD SEMICONDUCTOR C...

1. An electrical circuit comprising:a charge pump circuit that generates a charge pump voltage;
a bias circuit that receives the charge pump voltage at a first node, generates a reference current, and generates a plurality of switch currents from the reference current, the plurality of switch currents including a first switch current and a second switch current;
a first switch circuit receiving the first switch current, the first switch current flowing into the first switch circuit, and the first switch circuit including a first transistor, the first transistor having a gate and a source that receive a first gate-source voltage that is generated from the first switch current in the plurality of switch currents;
a first impedance element and a first capacitor, the first switch current flowing through the first impedance element to generate the first gate-source voltage, the first impedance element and the first capacitor being coupled to each other in parallel; and
a second switch circuit receiving the second switch current, the second switch current flowing into the second switch circuit, and the second switch circuit including a second transistor, the second transistor having a gate and a source that receive a second gate-source voltage that is generated from the second switch current in the plurality of switch currents.

US Pat. No. 10,461,629

SYSTEM AND APPARATUS TO PROVIDE CURRENT COMPENSATION

Texas Instruments Incorpo...

1. An apparatus comprising:a first current path including a first transistor that includes a first gate, a first drain and a first source, and a second transistor that includes a second gate, a second drain and a second source, the first drain coupled to the second drain;
a second current path including a third transistor that includes a third gate, a third drain, and a third source, and a fourth transistor that includes a fourth gate a fourth drain and a fourth source, the third source coupled to the first source and the third gate, the third drain coupled to the fourth drain, the fourth source coupled to the fourth gate and the second source; and
a current mirror including a fifth transistor that includes a fifth gate, a fifth drain, and a fifth source, and a sixth transistor that includes a sixth gate, a sixth drain, and a sixth source, the fifth drain coupled to the third drain, the sixth gate and the fifth gate, the sixth drain coupled to the second drain, the fifth source coupled to the sixth source and the fourth source, wherein a first ratio exists between the first transistor and the third transistor, a second ratio exists between the second transistor and the fourth transistor, and a third ratio exists between the fifth transistor and the sixth transistor, the third ratio greater than or equal to the second ratio, the second ratio greater than or equal to the first ratio.

US Pat. No. 10,461,628

CONTROL CIRCUIT FOR OUTPUTTING PULSE WIDTH MODULATION CONTROL SIGNAL WITH ZERO-CROSSING DETECTION

DELTA ELECTRONICS, INC., ...

1. A control circuit for outputting a pulse width modulation (PWM) control signal, comprising:a signal detection unit, coupled to an AC-side inductor of an AC/DC converter, which is configured to detect a voltage of the AC-side inductor and output an inductor voltage detection signal, wherein the inductor voltage detection signal is an AC signal;
a zero-crossing detection (ZCD) signal acquisition unit, coupled to the signal detection unit, which is configured to receive the inductor voltage detection signal, and generate a zero-crossing detection signal of the voltage of the AC-side inductor;
a signal selection unit, coupled to the ZCD signal acquisition unit, which is configured to receive the zero-crossing detection signal, and generate an inductor voltage frequency indication signal according to the zero-crossing detection signal;
a frequency limiting unit, coupled to the signal selection unit, which is configured to receive the inductor voltage frequency indication signal and a pulse signal of a preset threshold frequency, and generate a ZCD trigger signal of which the frequency is not greater than the preset threshold frequency; and
a PWM control signal generation unit, coupled to the frequency limiting unit, which is configured to receive the ZCD trigger signal and generate a PWM control signal for the AC/DC converter according to the ZCD trigger signal.

US Pat. No. 10,461,627

FRACTIONAL VALLEY SWITCHING CONTROLLER

Silanna Asia Pte Ltd, Si...

1. A power converter controller comprising:a fractional valley controller configured to determine a target number of valleys of a resonant waveform at a drain node of a main switch, the target number of valleys corresponding to a desired off-time of the main switch, the fractional valley controller modulating an off-time of the main switch between a plurality of modulated off-times;
wherein:
the target number of valleys corresponds to a non-integer number of valleys of the resonant waveform at the drain node of the main switch;
each of the modulated off-times of the main switch corresponds to an integer number of valleys; and
the plurality of modulated off-times of the main switch has an average value that corresponds to the desired off-time.

US Pat. No. 10,461,623

VOLTAGE CONVERTER CIRCUIT, ELECTRONIC DEVICE INCLUDING THE SAME AND VOLTAGE CONVERSION METHOD

Samsung Electronics Co., ...

1. A voltage converter circuit, comprising:a plurality of switched capacitors; and
a buck converter comprising an inductor and a capacitor, the buck converter configured to be alternately supplied with a first voltage and a second voltage output from each of two switched capacitors selected from the plurality of switched capacitors, to convert the supplied first voltage or second voltage into an output voltage via an LC filter and to provide the output voltage; and
a feedback controller configured to select the two switched capacitors for outputting the voltage supplied to the buck converter from among the plurality of switched capacitors,
wherein output terminals of each of the plurality of switched capacitors are selectively electrically connected to an input terminal of the buck converter.

US Pat. No. 10,461,620

X-Y STAGE WITH ROTATION

Kim Rubin, Menlo Park, C...

1. An X-Y stage comprising:a base comprising:
a base surface;
a plurality of base magnets arranged in a checkerboard pattern, proximal to the base surface, of alternating north and south magnetic poles;
a puck comprising:
a puck surface;
at least four controllable first electromagnetic nodes;
wherein each of the controllable first electromagnetic nodes is adapted to receive an each node drive signal and generate responsively an each magnetic field;
wherein the puck and base are adapted such that the puck surface moves proximal to and parallel to the base surface responsive to the node drive signals, due to magnetic attraction or repulsion between the base magnets and the controllable first electromagnetic nodes.

US Pat. No. 10,461,619

MOTOR, AND ELECTRIC POWER STEERING APPARATUS AND VEHICLE IN WHICH SAID MOTOR IS MOUNTED

NSK LTD., Shinagawa-ku, ...

1. A synchronous type motor,wherein said synchronous type motor has a skew effect in a rotor gap surface of a mechanical angle one-cycle, by that a rotor magnetic pole comprises plural magnetic salient pole portions by means of magnetic material, N-pole magnets and S-pole magnets are alternately arranged on a rotor surface between said magnetic salient pole portions, and magnetic pole pitches of an electrical angle one-cycle, which comprise said magnetic salient pole portions and said N-pole magnets and said S-pole magnets, are unevenly arranged,
wherein a torque generation mechanism due to a magnet torque and a reluctance torque is formed by said magnetic salient pole portions and said N-pole magnets and said S-pole magnets,
wherein said rotor magnetic pole comprises four magnetic pole pitches P1 to P4, mechanical angles of said magnetic pole pitches P1 and P4 are A°, and mechanical angles of said magnetic pole pitches P2 and P3 are B° (?A°),
wherein a d-axis is an axis that a magnetic flux formed by said N-pole magnets and said S-pole magnets penetrates a rotor to a diameter direction, and a q-axis is an axis that a magnetic flux formed by a stator coil of a stator penetrates said rotor to a diameter direction,
wherein Iq is a q-axis component of an armature current, Id is a d-axis component of said armature current, ? is a lead angle of a rotational magnetic field for said d-axis, and ? shows a phase for said d-axis of an input current,
wherein ? is a rotor lead angle for a phase of said rotational magnetic field, and ? is determined based on said uneven magnetic pole pitches and is used for calculating said armature currents Iq and Id,
wherein Ld is an inductance of said d-axis and Lq is an inductance of said q-axis,
wherein Ia is an amplitude which is a half of a difference between a maximum value and a minimum value of said input current being alternating current,
wherein Tr1, Tr2, Tr3 and Tr4 which are respectively reluctance torques in said magnetic pole pitches P1, P2, P3 and P4, are defined as follows:
Tr1=(Lq?Ld)×Ia2×sin(???)×cos(???)
Tr2=(Lq?Ld)×Ia2×sin(?+?)×cos(?+?)
Tr3=(Lq?Ld)×Ia2×sin(?+?)×cos(?+?) and
Tr4=(Lq?Ld)×Ia2×sin(???)×cos(???),
wherein said magnetic pole pitches are unevenly arranged in order to reduce said reluctance torque which is a sum of Tr1, Tr2, Tr3 and Tr4 while phases of armature rotational magnetic fields corresponding to said magnetic pole pitches P1, P2, P3 and P4 are equivalent, by leading or delaying a phase of magnet magnetic field of said rotor side based on said rotor lead angle ?, thereby to reduce a torque ripple or a cogging torque.

US Pat. No. 10,461,616

ROTOR, METHOD FOR PRODUCING A ROTOR, ASYNCHRONOUS MACHINE, AND VEHICLE

Bayerische Motoren Werke ...

1. A rotor for an asynchronous machine, comprising:a laminated core; and
a short-circuit cage which is at least partially integrated into the laminated core, wherein
the short-circuit cage comprises
rods made with or from a first electrically conductive material,
short-circuit rings made with or from a second electrically conductive material,
wherein at least one of the short-circuit rings is constructed with a support ring,
wherein a respective support ring is constructed as a structure which is cast onto or into the respective short-circuit ring in at least one of a positively locking and materially joining fashion,
wherein the respective support ring is constructed with, on a surface, a contour for supporting the at least one of the positive locking and the material joining with the respective short-circuit ring, and
wherein the contour has a plurality of projections disposed on an inner surface of the contour inside of a peripheral edge of the contour and projecting radially toward a center of the contour.

US Pat. No. 10,461,615

ROTOR FOR A SLIP RING MOTOR AND SLIP RING MOTOR

LINDE AKTIENGESELLSCHAFT,...

1. A rotor for a slip ring motor, comprisinga hollow shaft having an open end,
a plurality of electric cables, and
a cable guide arranged in the open end guiding the electric cables from inside the hollow shaft towards connection points of the electric cables outside the hollow shaft,
wherein the cable guide comprises
a ring member and a funnel member connected to said ring member, the ring member including recesses and the funnel member including an inside surface, and
a fixing member releasably fixing the electric cables to the ring member, wherein the fixing member is bolted to the ring member.

US Pat. No. 10,461,614

ROTOR AND ELECTRICAL MACHINE

FEAAM GmbH, Neubiberg (D...

1. An electrical machine comprising:a stator; and
a rotor comprising:
a main rotor, which can be rotated about a longitudinal axis and which is free of permanent magnets, the main rotor being configured as a claw pole rotor; and
an auxiliary rotor, comprising two axial flux rotors,
wherein each the axial flux rotors
is rotatable about the longitudinal axis,
is arranged in an axial direction adjacent to the main rotor, and
has an annular iron core with permanent magnets arranged on end surfaces thereof, the permanent magnets facing each other, teeth of the annular iron core being assembled directly on the lateral surfaces of the claw pole rotor and being adjusted there flush with rotor teeth along an external circumference of the main rotor, and
wherein the main rotor
comprises a single excitation coil which is wound in a circumferential direction, and
has substantially the same axial extension as the stator of the machine.

US Pat. No. 10,461,612

PLANAR POSITIONING APPARATUS AND POSITIONING TABLE

1. Planar positioning apparatus, comprisinga stator which comprises a coil arrangement of flat coils,
a rotor which is arranged opposite the stator in the operating position of the positioning apparatus and has a planar magnet arrangement comprising a plurality of rows of magnets, wherein the plane which is spanned by the planar magnet arrangement is arranged parallel to the plane of the coil arrangement,
a position detecting device for detecting the position of the rotor relative to the stator, and
an evaluation and control device for evaluating position signals of the position detecting device and for controlling a current supply to the coil arrangement for controlling the position of the rotor with respect to the stator,
wherein the coil arrangement comprises in each case n×3 (n?1) elongate flat coils which are interleaved with one another, in a first and second orientation of the coil arrangement, which over the majority of their extent, are designed as conductors tracks of a first plane of a multiple-plane printed circuit board, and the conductor tracks of the three associated flat coils enclose crossover regions which run in a second plane of the multiple-plane printed circuit board, while all of the connection ends of the three associated flat coils each are concentrated in a small connection region of the multiple-plane printed circuit board.

US Pat. No. 10,461,611

ELECTROMECHANICAL MOTOR UNIT

JTEKT CORPORATION, Osaka...

1. An electromechanical motor unit comprising:a motor including a motor housing made of metal; and
a motor control device disposed outside the motor housing so as to face the motor in an axial direction of the motor, the motor control device including a driving unit including a driving circuit configured to execute drive control of the motor and a cover member made of metal and configured to accommodate the driving unit, wherein
the driving unit comprises:
a substrate having a first main surface facing the motor housing, and a second main surface that is on an opposite side of the substrate from the first main surface;
a semiconductor chip joined to the second main surface of the substrate, the semiconductor chip including a switching device constituting a part of the driving circuit, and the semiconductor chip having a first end portion facing the second main surface of the substrate in the axial direction and a second end portion that is on an opposite side of the semiconductor chip from the first end portion; and
a smoothing capacitor joined to the second main surface of the substrate, the smoothing capacitor constituting a part of the driving circuit, the smoothing capacitor configured to smooth a voltage to be applied to the semiconductor chip, the smoothing capacitor having a third end portion facing the second main surface of the substrate in the axial direction and a fourth end portion that is on an opposite side of the smoothing capacitor from the third end portion, and the fourth end portion being at a position further away, in the axial direction, from the second main surface of the substrate than the second end portion of the semiconductor chip is, and
the cover member comprises:
a facing wall disposed so as to face the second main surface of the substrate in the axial direction and so as to face the smoothing capacitor in a direction perpendicular to the axial direction, and the facing wall being thermally connected to the semiconductor chip, at a position between the third end portion and the fourth end portion of the smoothing capacitor in the axial direction; and
a connection portion disposed outward of a peripheral edge of the substrate as viewed in the axial direction, the connection portion extending from a peripheral edge of the facing wall toward the motor housing, and the connection portion thermally connecting the facing wall and the motor housing to each other.

US Pat. No. 10,461,610

ELECTRICALLY-CONDUCTIVE CONNECTION DEVICE FOR USE IN A COMPACT MINIATURIZED MOTOR ASSEMBLY

1. A motor assembly comprising:a motor having an end component;
a printed circuit board configured to operate the motor;
at least one electrically-conductive connection device for securing the printed circuit board to the end component of the motor, the connection device comprising:
a first side and a second side, wherein the first side and the second side connect to one another along an outer edge, wherein the first side and the second side are positioned perpendicular to one another;
the first side further including a threaded aperture, wherein the threaded aperture is designed for receiving a fastener there through for connecting the printed circuit board to the motor; and,
wherein the connection device provides multiple points of electrical and mechanical contacts between the motor and the printed circuit board.

US Pat. No. 10,461,606

LINEAR ELECTRIC ACTUATOR FOR STEERING SYSTEMS

OGNIBENE POWER S.P.A., R...

1. A linear electrical actuator (10) for steering systems comprising:a casing (20),
an electric motor (50), housed in the casing (20), which is provided with a stator (55) and a hollow rotor (60) internally concentric to the stator (55),
a holder nut (80) internally fixed to the rotor (60), and
a stem (85) having a thread (90) coupled to the holder nut (80), the stem (85) comprising a first portion (105) provided with a surface treatment, which projects outside the casing (20), and a second portion (120) without said surface treatment, which is contained inside the casing (20) and in which said thread (90) is obtained.

US Pat. No. 10,461,604

OIL DISTRIBUTION ELEMENT

THYSSENKRUPP PRESTA TECCE...

1. A hollow rotor shaft for a rotor of an electric machine, the hollow rotor shaft comprising:a cylinder barrel enclosing a shaft cavity and closed off on a first side by a face flange and closed off on a second side by a face flange, wherein a shaft journal is disposed or formed on each of the face flanges;
an inlet disposed in one of the face flanges that permits a cooling fluid to pass into the shaft cavity and to an inner surface of the cylinder barrel; and
a distribution element disposed in the shaft cavity, wherein the distribution element is configured to
receive the cooling fluid that enters by way of the inlet,
conduct the cooling fluid in a direction of the inner surface of the cylinder barrel by way of a drainage surface, and
provide the cooling fluid to the inner surface by way of a mouth region of the drainage surface,
wherein the drainage surface of the distribution element comprises a conical funnel having a smooth inner surface that is straight or arched, with the conical funnel opening into the shaft cavity at an opening angle.

US Pat. No. 10,461,600

CRANKSHAFT STARTER GENERATOR AND HOUSING FOR A CRANKSHAFT STARTER GENERATOR

1. A crankshaft starter generator comprising a stator divided circumferentially into at least two stator parts, the crankshaft starter generator is designed to be connected between an engine and a transmission, and the stator is designed to be divisible so that in a connected state, in which the stator is connected to the engine and the transmission, one of the at least two stator parts is removable while others of the at least two stator parts remain connected to the engine and the transmission.

US Pat. No. 10,461,598

DIRECT CURRENT MACHINE AND METHOD FOR MANUFACTURING A DIRECT CURRENT MACHINE

Alber GmbH, (DE)

1. A direct current machine, the machine comprising: a stator and a rotor, wherein one of these two has a plurality of magnets which are alternatively magnetized north and south, and the respective other part has a plurality of coils which are formed by teeth around which insulated wire is wound, wherein between these coils there are formed respective slots and the coils are combined in coil groups: a current controlled inverter for driving the machine; wherein each coil group has a front terminal and a rear terminal and the coil groups are connected such that a defined wiring concept is formed; wherein the front terminals and end terminals are connected via an interconnection element which is specifically designed for a defined wiring concept; and wherein the interconnection element is provided in the form of a circuit board assembly.

US Pat. No. 10,461,595

ROTOR ASSEMBLY AND COOLING ARRANGEMENT FOR AN ELECTRIC MACHINE

GE Aviation Systems LLC, ...

1. A rotor assembly for an electric machine comprising:a rotor core having a rotatable shaft having hollow interior defining a coolant conduit and at least one post defining a winding pole;
a winding wound around the pole, and having axial segments that extend axially along the pole and end turn segments that extend axially beyond ends of the post;
a coolant manifold supported by the shaft and sealed from the winding but fluidly coupled to the coolant conduit wherein coolant can move between the coolant manifold and the coolant conduit, the coolant manifold having a thermally conductive face radially underlying at least a portion of the end turn segment and in thermal contact with the portion of an end turn segment, wherein heat from the end turn segment is transferred by conduction through the thermally conductive face of the coolant manifold to coolant in the coolant manifold; and
at least one coolant tube in fluid communication with the coolant manifold and extending axially along the post, wherein the coolant tube comprises a first thermally conductive face radially underlying, in thermal contact with, and at least partially supporting, an axial segment of a first winding and a second thermally conductive face radially underlying, in thermal contact with, and at least partially supporting, an axial segment of a second winding.

US Pat. No. 10,461,594

REDUCTION OF STARTING CURRENT IN LINE START PERMANENT MAGNET BRUSHLESS MOTORS

HAMILTON SUNDSTRAND CORPO...

1. A rotor of a line start permanent magnet synchronous motor, the rotor comprising:two or more bars of cage windings;
an additional inductance coupled to the cage windings and configured on a first end of the two or more bars; and
an end ring configured on a second end of the two or more bars,
wherein the additional inductance provides a reactance to reduce a starting current during an asynchronous starting of the line start permanent magnet synchronous motor.

US Pat. No. 10,461,591

ROTARY ELECTRIC MACHINE WITH ARMATURE COIL END TOP PORTIONS DISPLACED IN A RADIAL DIRECTION

MITSUBISHI ELECTRIC CORPO...

1. A rotary electric machine comprising an armature that is formed by mounting an armature core to an annular armature winding, wherein:said armature winding includes winding bodies each being formed by winding a jointless, continuous conductor wire that is coated with insulation for m turns into a helical shape such that end portions of rectilinear portions are linked by coil ends, where m is a natural number that is greater than or equal to two, said winding bodies located in pairs of slots of said armature core that are separated by a predetermined number of slots and being arranged in a circumferential direction at a pitch of one slot; and
each winding body including rectilinear portions on a first side at one end in the circumferential direction and rectilinear portions at a second side at an end opposite to the one end in the circumferential direction,
rectilinear portions positioned on the first side in the circumferential direction of a first winding body and rectilinear portions positioned on the second side in the circumferential direction of a second winding body are housed so as to line up radially in each of said slots of said armature core such that greater than or equal to one and less than or equal to (m?1) rectilinear portions of said first winding body arranged between rectilinear portions of said second winding body.

US Pat. No. 10,461,590

SINGLE PHASE PERMANENT MAGNET MOTOR

Johnson Electric Internat...

1. A single phase permanent magnet motor comprising:a stator comprising a stator core and windings wound around the stator core, the stator core comprising a ring portion, a plurality of tooth bodies extending radially from the ring portion, and a pole shoe extending from a distal end to two circumferential sides of each tooth body, a slot formed between each two adjacent pole shoes;
wherein each pole shoe defines a positioning slot, a center of each positioning slot is offset from a center of symmetry of one adjacent tooth body so that a torque fluctuation of an output torque of the single phase permanent magnet motor during operation is less than 50%;
wherein a rotor is rotatable relative to the stator, and the rotor has a plurality of permanent magnetic poles cooperatively with the pole shoes for forming a symmetrical uneven air gap, a width of the slot is greater than zero and less than or equal to two times of a minimum thickness of the symmetrical uneven air gap; and
wherein the rotor comprises an outer circumferential surface of a rotor core defining a plurality of axially extending grooves, the plurality of permanent magnetic poles are arranged on the outer circumferential surface of the rotor core, each groove being located at a junction between two adjacent permanent magnetic poles to reduce magnetic leakage, the plurality of axially extending grooves being arranged to face the positioning slot.

US Pat. No. 10,461,588

SLOT COIL AND STATOR FOR ELECTRIC ROTARY MACHINE

HONDA MOTOR CO., LTD., T...

1. A slot coil that is inserted into a slot provided in a stator core, whereinthe slot coil is covered with an insulating material,
the insulating material has an ear portion on an outer circumferential surface thereof, and
the slot coil is fixed to the stator core by the ear portion welded to one end surface of the stator core.

US Pat. No. 10,461,586

METHODS AND APPARATUS FOR CROSS CONNECTION DETECTION AND MITIGATION IN WIRELESS POWER TRANSFER NETWORKS

INTEL CORPORATION, Santa...

1. A method comprising:receiving first data from a first power transmitting unit (PTU);
receiving second data from a second PTU, wherein the first PTU and the second PTU are capable of providing wireless power to power receiving units;
generating, by executing an instruction with a processor of a gateway, a connected device association corresponding to the first PTU, the second PTU, and a power receiving unit (PRU) based on the first data and the second data;
responsive to obtaining communication data from the second PTU, determining that the communication data is intended for the first PTU based on the connected device association, the PRU transmitting the communication data to the second PTU and the PRU receiving power from the first PTU; and
transmitting the communication data to the first PTU.

US Pat. No. 10,461,585

POWER-RECEIVING DEVICE, WIRELESS POWER-FEEDING SYSTEM INCLUDING POWER-RECEIVING DEVICE, AND WIRELESS COMMUNICATION SYSTEM INCLUDING POWER-RECEIVING DEVICE

Semiconductor Energy Labo...

1. A power-receiving device comprising:a first coil on a first region of a substrate, the first coil being configured to generate a first high-frequency voltage;
a second coil on a second region of the substrate, the second coil being configured to generate a second high-frequency voltage;
a wireless power-feeding unit electrically connected to the second coil, the wireless power-feeding unit including a battery; and
a wireless communication unit electrically connected to the second coil, the wireless communication unit comprising:
a reception circuit configured to receive a signal that has been received by at least one of the first coil and the second coil; and
a reception controller configured to control the signal received by the reception circuit,
wherein the wireless power-feeding unit and the wireless communication unit are provided over the substrate and integrated,
wherein the substrate is a flexible substrate, and
wherein the battery is overlapped with at least one of the first coil and the second coil.

US Pat. No. 10,461,584

POWER RECEIVER AND POWER TRANSMITTING SYSTEM

FUJITSU LIMITED, Kawasak...

1. A power receiver comprising:a secondary-side resonant coil including a resonant coil part and configured to receive electric power from a primary-side resonant coil through magnetic field resonance generated between the primary-side resonant coil and the secondary-side resonant coil;
a first capacitor inserted in series in the resonant coil part of the secondary-side resonant coil;
a series circuit, coupled in parallel with the first capacitor, of a first switch and a second switch;
a first rectifier coupled in parallel with the first switch, the first rectifier having a first rectification direction;
a second rectifier coupled in parallel with the second switch, the second rectifier having a second rectification direction opposite to the first rectification direction;
a second capacitor inserted in series with the series circuit;
a detector configured to detect a voltage waveform or a current waveform of the electric power supplied to the secondary-side resonant coil; and
a controller configured to adjust a phase difference between the voltage waveform or the current waveform detected by the detector and a driving signal that includes a first signal for switching on/off the first switch and includes a second signal for switching on/off the second switch to adjust an amount of the electric power received by the secondary-side resonant coil.

US Pat. No. 10,461,581

CHARGING CASE FOR ELECTRONIC DEVICES

Nook Digital, LLC, New Y...

1. An electronic system, comprising:a mobile electronic device comprising
a touch screen display;
a processor;
a battery;
a first conductive contact connected to the battery; and
a single port for receiving both power to charge the battery and data for processing by the processor; and
a charging case to which the mobile electronic device is attachable, the charging case comprising
a second conductive contact, the first conductive contact to be in direct contact with the second conductive contact when the device is attached to the charging case,
an inductive coil configured to electromagnetically couple to a primary inductive charging coil, and
charging circuitry configured to provide power from the inductive coil to the battery through the first and second conductive contacts, thereby leaving the single port available for use during charging of the battery.

US Pat. No. 10,461,580

NOISE MITIGATION IN WIRELESS POWER SYSTEMS

APPLE INC., Cupertino, C...

1. A wireless power system comprising:a transmitter comprising:
a substrate;
a distribution of transmitter coils on the substrate, each transmitter coil formed with at least one crossover per turn; and
a receiver magnetically coupled to at least one transmitter coil and comprising a receiver coil formed with at least one crossover per turn; wherein a first transmitter coil of the distribution of transmitter coils comprises:
a first portion;
a second portion; and
an in-line filter capacitor coupled between the first portion and the second portion, wherein at least one crossover is formed by the in-line filter capacitor.

US Pat. No. 10,461,579

METHOD AND SYSTEM FOR MONITORING THE OPERATING STATUS OF AN ENERGY DELIVERY NETWORK

Siemens Aktiengesellschaf...

1. A method for monitoring an operating status of an energy delivery network, which comprises the steps of:acquiring measured values indicating the operating status of the energy delivery network from sensors disposed at measurement locations assigned to primary components of the energy delivery network;
transmitting the measured values or values derived from the measured values first to an application server, disposed outside a sphere of influence of an operator of the energy delivery network;
determining with the sensors state values indicating their own operating status and transmitting the state values to the application server;
analyzing and/or processing the measured values or the values derived therefrom via the application server, thereby forming system status values indicating the operating status of the energy delivery network at a measurement location of a respective sensor;
checking via the application server the measured values received with regard to their position in an admissible operating range of a respective primary component to which the respective sensor is assigned;
forming system status values according to a result of the checking step via the application server and transmitting the system status values from the application server to a monitoring device of the operator of the energy delivery network; and
generating, via the monitoring device of the operator of the energy delivery network, a visualization that indicates the operating status of the energy delivery network at the measurement location of the respective sensor, based on at least one of the measured values, the values derived therefrom or the system status values received from the application server;
wherein the application server analyzes and/or processes the state values, thereby forming sensor status values which indicate an operating status of each of the sensors, the sensor status values are transmitted from the application server to the monitoring device of the operator of the energy delivery network; and
wherein the monitoring device uses the sensor status values received from the application server to generate and display the visualization indicating the operating status of the respective sensor.

US Pat. No. 10,461,575

MULTISTATE PWM COMMAND FOR 3 LEVELS INVERTERS

SCHNEIDER ELECTRIC IT COR...

1. An Uninterruptible Power Supply (UPS) system comprising:an input configured to be coupled to an AC source and to receive input AC power from the AC source;
an output configured to provide output AC power to a load, the output AC power having a positive average output voltage level during a positive half-period of a line cycle and a negative average output voltage level during a negative half-period of the line cycle;
a converter coupled to the input and configured to convert the input AC power into DC power;
a plurality of DC busses coupled to the converter and configured to receive the DC power from the converter;
an inverter coupled to the plurality of DC busses, the inverter having a common point configured to receive the DC power from the plurality of DC busses and a filter coupled between the common point and the output, and the inverter configured to convert the DC power from the plurality of DC busses into the output AC power and provide the output AC power to the output; and
a controller configured to operate the inverter, during the positive half-period of the line cycle, by alternating between a first mode of operation to provide a positive voltage to the common point, a second mode of operation to provide a neutral voltage to the common point, and a third mode of operation to provide a negative voltage to the common point to generate the positive average output voltage level of the output AC power provided to the output.

US Pat. No. 10,461,574

TRANSFER SWITCH WITH MONITOR ON LOAD SIDE

Kohler Co., Kohler, WI (...

1. A system comprising:a first input port for receiving alternating current from a first power source;
a second input port for receiving alternating current from a second power source; and
a switch configured to switch an output port between the first input port and the first power source and the second input port and the second power source, the switch comprising a measurement circuit electrically connected to the output port and a home electrical panel, wherein the measurement circuit is configured to generate a load measurement signal for the output port, wherein the load measurement signal includes at least one sample corresponding to a total home consumption value for a status message.

US Pat. No. 10,461,573

EMERGENCY POWER SUPPLY UNIT AND METHOD FOR OPERATING AN EMERGENCY LIGHTING MEANS

1. An emergency power supply unit (A) for operating an emergency light (6), comprising at least one LED, the emergency power supply unit (A) comprising:an energy storage unit (2) configured to provide a battery supply voltage (VBat) in case of a mains voltage supply loss, wherein the emergency power supply unit (a) detects a battery supply voltage value;
and
a controlling unit (5) configured to control the operation of the emergency power supply unit (A) based on the actually monitored battery supply voltage (VBat) value;
wherein in a first operating mode of the emergency power supply unit (A), an emergency light (6) is switched-on;
wherein in a second operating mode of the emergency power supply unit (A), the controlling unit (5) is operative and the emergency light (6) is switched-off; and
wherein in a third operating mode, the battery supply voltage (VBat) is galvanically isolated from the controlling unit (5) by a switching means (11).

US Pat. No. 10,461,571

CHARGING CIRCUIT AND MODULE USING THE SAME

MURATA MANUFACTURING CO.,...

1. A charging circuit comprising:an electric storage element having a rated charging voltage:
a power generation element having a rated power generation voltage which is greater than the rated charging voltage, the power generation element being coupled to the electric storage unit so as to charge the electric storage element; and
the electric storage element having a positive electrode active material layer containing a lithium-transition metal oxide and a negative electrode active material layer containing lithium-titanium oxide having a spinel-type crystal structure.

US Pat. No. 10,461,570

SYSTEMS AND METHODS TO PROVIDE ENHANCED DIODE BYPASS PATHS

TIGO ENERGY, INC., Los G...

1. A bypass switch circuit, comprising:a bypass transistor having a parasitic diode, the bypass transistor to be connected in parallel with an output of a group of solar cells;
a first diode;
a first capacitor connected in series with the first diode, wherein a path formed by the first diode and the first capacitor is connected in parallel with the bypass transistor;
a single cell converter connected to the first capacitor to receive an input, the single cell converter to generate an output;
a second diode connected to receive the output of the single cell converter;
a second capacitor connected in series with the second diode; and
a controller connected to the second capacitor and configured to activate the bypass transistor in response to the parasitic diode being conductive.

US Pat. No. 10,461,569

POWER PATH INFORMATION GENERATION DEVICE, METHOD FOR GENERATING POWER PATH INFORMATION, AND COMPUTER PROGRAM

SONY CORPORATION, Tokyo ...

1. A system comprising:circuitry configured to
acquire information indicating a variation in voltage corresponding to each of a plurality of nodes connected to a direct-current (DC) line; and
identify a topology of the plurality of nodes connected to the DC line based on the acquired information indicating the variation in voltage corresponding to each of the plurality of nodes,
wherein each of the plurality of nodes comprises a bidirectional DC-to-DC converter configured to be coupled to the DC line, and each of the plurality of nodes comprises a battery capable of supplying power via the DC line.

US Pat. No. 10,461,568

CHARGING SYSTEM, CHARGING METHOD, AND POWER ADAPTER

Guangdong Oppo Mobile Tel...

1. A charging system, comprising:a battery;
a first rectification unit, configured to rectify, in a charging process, an input alternating current (AC) and output a voltage of a first pulsating waveform;
a switch unit and a transformer, configured to receive the voltage of the first pulsating waveform outputted by the first rectification unit, and couple the voltage of the first pulsating waveform to a secondary side circuit, the secondary side circuit, configured to generate an output voltage for charging the battery;
a second rectification unit, configured to rectify a voltage of a second pulsating waveform and output a voltage of a third pulsating waveform;
a first charging interface coupled with the second rectification unit, configured to apply the voltage of the third pulsating waveform to a battery of a terminal via a second charging interface of the terminal when the first charging interface is coupled with the second charging interface, wherein the second charging interface is coupled with the battery;
a sampling unit, configured to sample at least one of an output voltage or an output current of the second rectification unit to obtain at least one of a voltage sampling value or a current sampling value; and
a control unit coupled with the sampling unit and the switch unit, respectively, the control unit configured to output a control signal to the switch unit to adjust a duty ratio of the control signal based on at least one of the voltage sampling value or the current sampling value, enabling the voltage of the third pulsating waveform to meet charging requirements of the terminal.

US Pat. No. 10,461,567

FEED SYSTEM, FEED UNIT, AND ELECTRONIC UNIT

Sony Corporation, Tokyo ...

1. A power transmitter, comprising:a power transmitting unit configured to detect a power receiving unit to be charged before the power transmitting unit performs pre-charging of the power receiving unit and to receive a charging request from the power receiving unit after the power transmitting unit performs the pre-charging of the power receiving unit,
wherein the power transmitting unit is configured to transmit power to the power receiving unit during main charging based upon result information of a first authentication between the power transmitting unit and the power receiving unit.

US Pat. No. 10,461,566

SYSTEM, APPARATUS, AND METHOD FOR CAPACITIVE WIRELESS CHARGING

1. A capacitive wireless charging system, comprising:a charging circuit having adjustable operating characteristics, and including two coupling capacitors formed by two transmitter electrode plates of a source device at least partially overlapping two receiver electrode plates of a user device; and
a positioning device configured to move at least one of the transmitter electrode plates in order to adjust coupling characteristics of the coupling capacitors to reach a pre-determined threshold wherein the at least one transmitter electrode plate is configured to rotate around an axis that is geometrically off center of the at least one transmitter electrode plate and the coupling characteristics indicate a total coupling capacitance of the coupling capacitors.

US Pat. No. 10,461,564

COIL STRUCTURE FOR INDUCTIVE AND RESONANT WIRELESS CHARGING TRANSMITTER AND INTEGRAL CONTROL METHOD FOR THE SAME

KOREA AUTOMOTIVE TECHNOLO...

1. A wireless power transmitter, comprising:a first coil disposed to transmit wireless power;
a second coil disposed outside of the first coil to transmit wireless power; and
a controller configured to:
determine whether to operate the wireless power transmitter in a magnetic induction mode or a magnetic resonance mode;
in the magnetic induction mode, control the first coil to transmit wireless power in the magnetic induction mode and control the second coil not to transmit wireless power; and
in the magnetic resonance mode, control both the first coil and the second coil to transmit wireless power in the magnetic resonance mode.

US Pat. No. 10,461,561

BATTERY CHARGING APPARATUS AND BATTERY CHARGING PROTECTION CONTROL METHOD

GUANGDONG OPPO MOBILE TEL...

1. A battery charging apparatus, comprising a power adapter and a charging control circuit, wherein, the charging control circuit is built in an electronic device and coupled to a controller and a battery in the electronic device, the power adapter is coupled to a communication interface of the electronic device via a communication interface thereof, the battery is charged by the power adapter via the communication interface of the electronic device, and the charging control circuit performs data communication with the power adapter via the communication interface of the electronic device;if a conventional charging or a quick charging is performed on the battery, the power adapter first determines whether an output voltage is greater than a voltage threshold and whether an output current is greater than a current threshold, if the output voltage is greater than the voltage threshold and/or the output current is greater than the current threshold, the power adapter sends a first charging stop command to the charging control circuit and automatically switches off direct current output, the charging control circuit drives the controller to switch off the communication interface of the electronic device according to the first charging stop command; if the output voltage is not greater than the voltage threshold, and the output current is not greater than the current threshold, the power adapter feeds back output voltage information and output current information to the charging control circuit, if the charging control circuit determines that the output voltage of the power adapter is greater than the voltage threshold and/or the output current of the power adapter is greater than the current threshold according to the output voltage information and the output current information, the charging control circuit feeds back a second charging stop command to the power adapter and drives the controller to switch off the communication interface of the electronic device, and the power adapter switches off the direct current output according to the second charging stop command; and if the charging control circuit determines that the output voltage of the power adapter is not greater than the voltage threshold and the output current of the power adapter is not greater than the current threshold according to the output voltage information and the output current information, the power adapter continues to determine the output voltage and the output current,
wherein, the power adapter comprises an EMI filter circuit, a high-voltage rectifier and filter circuit, an isolation transformer, an output filter circuit, and a voltage tracking and control circuit;
the EMI filter circuit is configured to perform an electromagnetic interference filter on mains supply, the high-voltage rectifier and filter circuit is configured to perform a rectifying and filtering process for outputting a high-voltage direct current, the isolation transformer is configured to perform an electrical isolation on the high-voltage direct current, the output filter circuit is configured to perform a filtering process on an output voltage of the isolation transformer so as to charge the battery, the voltage tracking and control circuit is configured to regulate the output voltage of the isolation transformer according to an output voltage of the output filter circuit;
the power adapter further comprises a power circuit, a main control circuit, a potential regulation circuit, a current detection circuit, a voltage detection circuit and an output switch circuit:
an input terminal of the power circuit is coupled to a secondary terminal of the isolation transformer; a power terminal of the main control circuit, a power terminal of the potential regulation circuit, and a power terminal of the current detection circuit are jointly coupled to an output terminal of the power circuit, a high-potential terminal of the main control circuit and a high-potential terminal of the potential regulation circuit are both coupled to a positive output terminal of the output filter circuit, a potential regulation terminal of the potential regulation circuit is coupled to the voltage tracking and control circuit; a direct current input terminal of the current detection circuit is coupled to a positive output terminal of the output filter circuit; a current detection feedback terminal of the current detection circuit is coupled to a current detection terminal of the main control circuit; a clock output terminal and a data output terminal of the main control circuit are coupled to a clock input terminal and a data input terminal of the potential regulation circuit; a first detection terminal and a second detection terminal of the voltage detection circuit are coupled to a direct current output terminal of the current detection circuit and a negative output terminal of the output filter circuit respectively, a first output terminal and a second output terminal of the voltage detection circuit are coupled to a first voltage detection terminal and a second voltage detection terminal of the main control circuit respectively; an input terminal of the output switch circuit is coupled to the direct current output terminal of the current detection circuit; an output terminal of the output switch circuit is coupled to a third detection terminal of the voltage detection circuit; a ground terminal of the output switch circuit is coupled to a negative output terminal of the output filter circuit; a controlled terminal and a power terminal of the output switch circuit are coupled to a switch control terminal of the main control circuit and the secondary terminal of the isolation transformer respectively; each of a negative output terminal of the output filter circuit, the output terminal of the output switch circuit, and a first communication terminal and a second communication terminal of the main control circuit is coupled to the communication interface of the power adapter;
the power circuit comprises: a first capacitor, a voltage stabilizing chip, a second capacitor, a first inductor, a second inductor, a first diode, a second diode, a third capacitor, a first resistor and a second resistor;
a junction of a first terminal of the first capacitor and an input power pin and an enable pin of the voltage stabilizing chip is configured as the input terminal of the power circuit, a second terminal of the first capacitor and a ground pin of the voltage stabilizing chip are jointly grounded; a switch pin of the voltage stabilizing chip and a first terminal of the second capacitor are jointly coupled to a first terminal of the first inductor; an internal switch pin of the voltage stabilizing chip and a second terminal of the second capacitor are jointly coupled to a cathode of the first diode; a voltage feedback pin of the voltage stabilizing chip is coupled to a first terminal of the first resistor and a first terminal of the second resistor, a second terminal of the first inductor and a cathode of the second diode are jointly coupled to a first terminal of the second inductor, a junction of a second terminal of the second inductor, an anode of the first diode, a second terminal of the first resistor and a first terminal of the third capacitor is configured as the output terminal of the power circuit; an anode of the second diode, a second terminal of the second resistor and a second terminal of the third capacitor are jointly grounded.

US Pat. No. 10,461,560

INFORMATION HANDLING SYSTEM EXTERNAL ADAPTER AND BATTERY SOURCE

Dell Products L.P., Roun...

1. A method for powering a portable information handling system, the method comprising:removeably coupling a power-in port of a first battery module to a charging port of power source with a first cable;
removeably coupling a power-out port of the first battery module to a power-in port of a second battery module with a second cable;
providing power from the power source to the first battery module through the power-in port;
determining at the first battery module that the second battery module has capacity to accept a charge;
charging the second battery module with power provided at the power-out port of the first battery module to the power-in port of the second battery module; and
charging the first battery module when the second battery module a predetermined capacity to accept a charge.

US Pat. No. 10,461,557

RECHARGEABLE TOOL BATTERY, MAINS-OPERABLE HAND-HELD POWER TOOL, AND TOOL SYSTEM

Hilti Aktiengesellschaft,...

1. A rechargeable tool battery comprising:a rechargeable tool battery housing, a secondary cell battery being situated inside the battery housing and having a nominal cell voltage; and
a rechargeable battery DC-DC converter integrated into the rechargeable tool battery housing and electrically connected to the secondary cell battery, and designed for raising the nominal cell voltage to a supply voltage tappable at a rechargeable tool battery terminal of the rechargeable tool battery.

US Pat. No. 10,461,555

BATTERY CHARGING FOR MOBILE DEVICES

Dialog Semiconductor (UK)...

1. A charging system for providing power over a bus between a source and a sink;said bus comprising a power transmission channel and a configuration channel;
said system comprising:
a capacitive power converter;
a controller for controlling operation of the capacitive power converter;
a configuration channel detector arranged to detect the status of the configuration channel and provide said status as an input for the controller, so that the system can determine that the source has been detached from the bus when no configuration channel data is present.

US Pat. No. 10,461,552

MOBILE DEVICE CHARGER

BIBICORD, INC., Lutz, FL...

1. A mobile device charger, comprising:an enclosure comprising:
a cylindrical shape defined by a first circular surface having a perimeter and connected to a second circular surface having a perimeter by a curved connecting surface having a first end at the perimeter of the first circular surface and a second end at the perimeter of the second circular surface, the perimeters of the first and second circular surface beveled at the connections to the curved connecting surface, and
an electrical plug;
an AC/DC converter circuit, comprising:
a rectifier,
a flyback controller,
a transformer,
a wake-up monitor and synchronous rectifier, and
an active charge indicator; and
a retractable cable with a charging connector extending out from the enclosure, which cable is able to be extended from the enclosure while in use and retracted into the enclosure for storage,
wherein the wake-up monitor and synchronous rectifier is configured to send a series of pulses through the transformer to signal the flyback controller to shut down when there is no mobile device connected to the mobile device charger.

US Pat. No. 10,461,550

FAST CHARGING METHOD, POWER ADAPTER AND MOBILE TERMINAL

Guangdong Oppo Mobile Tel...

9. A mobile terminal, the mobile terminal being coupled with a power adapter via a USB interface, a power line of the USB interface being configured for charging the mobile terminal, a data line of the USB interface being configured for a bidirectional communication between the mobile terminal and the power adapter, the power adapter transmitting a clock signal to the mobile terminal via a first data line of the USB interface in a process of coupling the power adapter with the mobile terminal, the clock signal being configured for indicating a communication sequence between the power adapter and the mobile terminal, the communication sequence containing instruction transmission time slots of the power adapter and instruction reception time slots of the power adapter, and the instruction transmission time slots and the instruction reception time slots being alternatively generated, the mobile terminal supporting a normal charging mode and a fast charging mode, a charging current of the fast charging mode being higher than a charging current of the normal charging mode, the mobile terminal comprising:a charging circuit; and
a communication control circuit configured to determine to activate the fast charging mode, receive a second instruction from the power adapter, wherein the second instruction is configured for querying whether or not a current output voltage of the power adapter is proper to be a charging voltage of the fast charging mode;
the communication control circuit being further configured to transmit a reply instruction corresponding to the second instruction to the power adapter, wherein the reply instruction corresponding to the second instruction is configured for indicating that the current output voltage of the power adapter is proper, high, or low, whereby the power adapter adjusts the current output voltage of the power adapter to be the charging voltage of the fast charging mode according to the reply instruction corresponding to the second instruction;
the communication control circuit being further configured to receive a third instruction from the power adapter, wherein the third instruction is configured for querying a maximum charging current currently supported by the mobile terminal;
the communication control circuit being further configured to transmit a reply instruction corresponding to the third instruction to the power adapter, wherein the reply instruction corresponding to the third instruction is configured for indicating the maximum charging current currently supported by the mobile terminal, whereby the power adapter determines the charging current of the fast charging mode according to the reply instruction corresponding to the third instruction;
the communication control circuit being further configured to receive a fourth instruction from the power adapter after the power adapter adjusts an output current of the power adapter to be the charging current of the fast charging mode and enters a constant current phase, wherein the fourth instruction is configured for querying a current voltage of a battery of the mobile terminal;
the communication control circuit being further configured to transmit a reply instruction corresponding to the fourth instruction to the power adapter, wherein the reply instruction corresponding to the fourth instruction is configured for indicating the current voltage of the battery of the mobile terminal, whereby the power adapter adjusts the output current of the power adapter according to the current voltage of the battery to charge the mobile terminal in a multi-stage constant current mode via the charging circuit, wherein
each instruction transmitted to the mobile terminal by the power adapter comprises an 8-bit data, and each reply instruction received from the mobile terminal by the power adapter comprises a 10-bit data.

US Pat. No. 10,461,547

PORTABLE DRONE BATTERY CHARGING SYSTEM

1. A portable charging system for charging a multi-cell drone battery, comprising:a) a system battery configured to power the portable charging system during a portable operation to charge the multi-cell drone battery;
b) a recharging circuit for providing, in a system battery recharge operation, the system battery with sufficient charge for powering the portable operation to charge the multi-cell drone battery, the recharging circuit comprising:
a power input for receiving power during the system battery recharge operation of the system battery; and
a protector coupled between the power input and the system battery, the protector configured to protect the system battery during the system battery recharge operation;
c) a charging module coupled to the system battery and configured to receive power from the system battery to charge the multi-cell drone battery in a drone battery charge operation as part of the portable operation, the charging module comprising:
a drone battery charge control circuit configured to provide charging control of the multi-cell drone battery during the drone battery charge operation; and
a drone battery charging status monitor coupled to the drone battery charge control circuit, the drone battery charging status monitor being configured to control operation of the drone battery charge control circuit based on a multi-cell drone battery status; and
d) a drone battery connector configured to connect the multi-cell drone battery to the charging module;
wherein the charging module further comprises a power switch coupled to the drone battery charge control circuit, the power switch configured to initiate the drone battery charge operation, and wherein the charging module further comprises a timer configured to disable the drone battery charge control circuit after the drone battery charge operation has been initiated by the power switch when the multi-cell drone battery has not been detected to be connected to the drone battery connector within a certain amount of time.

US Pat. No. 10,461,545

BATTERY SYSTEM

Hitachi Chemical Company,...

1. A battery system that connects a first battery and a second battery in parallel through a switch, the battery system comprising:an estimator which estimates a charging current of the first battery at least from an internal resistance of the first battery; and
an estimator which estimates a charging current of the second battery at least from an internal resistance of the second battery,
wherein the switch is switched between the first battery and the second battery based on the charging current of the first battery and the charging current of the second battery such that a sum of a stored charge in the first battery and a stored charge in the second battery increases,
wherein the procedure switches the switch once during a regenerative charging,
wherein, in a case that a regeneration time is T, a charging time of the second battery is ?, and a first charging time is T??, where T is greater than ?, the second battery first is charged, and the switch is switched to the first battery at the timing ? at which a charge amount of the first battery and a charge amount of the second battery are maximum, and
wherein ? is a time t from a start of charge and the switch is switched so as to select the first battery after the time t has elapsed from the start of charge.

US Pat. No. 10,461,544

METHOD FOR DIAGNOSING ERROR OF CELL BALANCING

HYUNDAI MOTOR COMPANY, S...

1. A method for diagnosing an error in a cell balancing circuit configured to constantly maintain a plurality of cell voltages of a battery, comprising:a first step of calculating a cell balancing residual time (trd_1) based on a cell balancing required time (trq_1) and a cell balancing performing time (tpf_1) in a previous driving;
a second step of confirming a cell balancing required time (trq_2) in a current driving after the first step;
a third step of calculating a time deviation (tdev) based on the cell balancing required time (trq_2) of the second step and the cell balancing residual time (trd_1) of the first step;
a fourth step of deciding whether or not an error has occurred in the cell balancing circuit based on a ratio between the time deviation (tdev) and the cell balancing performing time (tpf_1); and
a fifth step of operating the cell balancing circuit in a case in which the error does not occur in the fourth step,
wherein in the fourth step, it is decided that the error has occurred in the cell balancing circuit when the ratio between the time deviation (tdev) and the cell balancing performing time (tpf_1) satisfies any one of following ranges:

US Pat. No. 10,461,540

SCALABLE FLEXIBILITY CONTROL OF DISTRIBUTED LOADS IN A POWER GRID

GENERAL ELECTRIC TECHNOLO...

1. A system, comprising:a load controller of distributed load controllers, the load controller coupled to manage a power-consuming load that consumes power supplied via a consumer supply device of a power grid, wherein the load controller manages the load to satisfy the load's quality of service constraint or constraints,
wherein the load controller is communicatively coupled to an aggregator that aggregates data sent by the load controller and received from one or more other distributed load controllers of the distributed load controllers, the data comprising initial data that comprises a power range,
wherein the load controller is configured to receive an initial ratio value from the aggregator,
wherein the initial ratio value is based on the power range and other power range data from the one or more other distributed load controllers of the distributed load controllers,
wherein the load controller is further configured to use the initial ratio value to set a local power level to an initial level, and use load-specific information of the power-consuming load to determine condensed information comprising one or more scalar values that represent the load-specific information in a more compact form than the load-specific information, and to communicate the condensed information to the aggregator, wherein the local power level is local to the load controller,
wherein the load controller is further configured to perform iterations based on communication with the aggregator to modify the local power level to approach a specified aggregated load power consumption level until the aggregator determines that the iterations have satisfied a defined condition, and
wherein the iterations are performed to:
receive a step size value and a global value from the aggregator, wherein the step size value and the global value are based on the condensed information and other condensed information from the one or more other distributed load controllers of the distributed load controllers,
determine a step direction,
control the power-consuming load with an adjustment based on the step size value and the step direction to approach the specified aggregated load power consumption level,
re-determine updated condensed information that updates the condensed information and comprises one or more updated scalar values that represent the load-specific information after the adjustment, and
communicate the updated condensed information to the aggregator.

US Pat. No. 10,461,535

POWER MANAGEMENT SYSTEM, POWER MANAGEMENT METHOD, AND COMPUTER PROGRAM

PANASONIC INTELLECTUAL PR...

1. A power management system, comprising:a first administrator configured to manage a residual capacity of a power storage apparatus;
a second administrator configured to manage interruption information that includes an interruption period during which a power grid is in a service interruption state;
a first estimator configured to estimate, as first power information, an amount of power that is consumed by an electric load during the interruption period;
a second estimator configured to estimate, at a start point of the interruption period or before start of the interruption period, an estimation residual capacity based on the first power information,
the estimation residual capacity being the residual capacity of the power storage apparatus at an end point of the interruption period; and
a determiner configured to determine that a condition for participating in a power trade market is met, when the estimation residual capacity exceeds a reference value, and to set an amount of power by which the estimation residual capacity exceeds the reference value, as an upper limit of a power selling amount in the power trade market.

US Pat. No. 10,461,529

TRIGGER CIRCUITRY FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION

Qorvo US, Inc., Greensbo...

1. An electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) comprising:ESD clamping circuitry coupled between a supply rail and a ground rail and configured to discharge an ESD event in an IC in response to an activation signal;
trigger circuitry configured to divide a voltage spike between the supply rail and the ground rail to provide a trigger voltage; and
latch circuitry coupled to the ESD clamping circuitry and the trigger circuitry and configured to:
detect that the trigger voltage exceeds an ESD threshold voltage; and
provide the activation signal to the ESD clamping circuitry to discharge the ESD event in response to detecting the trigger voltage exceeding the ESD threshold voltage;
wherein the trigger circuitry is decoupled from the latch circuitry when the latch circuitry provides the activation signal to the ESD clamping circuitry to discharge the ESD event in the IC.

US Pat. No. 10,461,528

ELECTRICAL BYPASS APPARATUS

General Electric Technolo...

1. An electrical bypass apparatus comprising:first and second terminals for connection across an electrical component;
an electrically-triggered bypass switch being switchable to form a short circuit across the first and second terminals; and
a first control circuit connected between the first and second terminals, the first control circuit including mutually coupled first and second windings, the first winding being isolated from the second winding, the first control circuit being configured to:
inhibit a current flowing between the first and second terminals from flowing through the first winding when a normal operating voltage is present across the first and second terminals; and
permit a current to flow between the first and second terminals and through the first winding when an overvoltage is present across the first and second terminals and thereby induce a current pulse in the second winding,
wherein the second winding is electrically coupled to the electrically-triggered bypass switch such that the current pulse induced in the second winding acts as a switching control signal to close the electrically-triggered bypass switch and thereby form the short circuit across the first and second terminals; and
wherein the first control circuit includes a rectifier connected across the first and second terminals, the rectifier being configured to rectify a voltage present across the first and second terminals and thereby cause a current to flow between the first and second terminals and through the first winding.

US Pat. No. 10,461,526

EXPLOSION PROTECTION CIRCUIT WITH IMPEDANCE MATCHING

1. Field device for monitoring at least one physical or chemical process variable, comprising:at least one transformer;
at least one sensor unit;
an electronics unit for signal registration, evaluation and/or feeding; and
an explosion protection circuit, wherein:
said at least one sensor unit is operated with alternating electrical current and/or communication between said electronics unit and said at least one sensor unit occurs with alternating electrical current and/or alternating voltage;
said explosion protection circuit with intrinsic safety, which includes a safety barrier, which has at least one unit for electrical current and voltage limiting, said explosion protection circuit is arranged fixedly between said at least one sensor unit and said electronics unit, and,
there is provided within said explosion protection circuit a unit for impedance matching, which unit for impedance matching includes said at least one transformer;
wherein said at least one sensor unit has at least one piezoelement,
and wherein said unit for voltage limiting includes at least one coil,
wherein said piezoelement with said unit for voltage limiting are shockproof against a mechanical impact with an energy of 7 Joule according to DIN EN60079-11.

US Pat. No. 10,461,520

CONTROLLABLE TEST-PULSE WIDTH AND POSITION FOR SELF-TEST GROUND FAULT CIRCUIT INTERRUPTER

Hubbell Incorporated, Sh...

1. An electrical wiring device comprising:a fault detection circuit configured to detect real, simulated and test fault conditions; and
a test fault circuit configured to generate one or more test pulses that cause said test fault condition, wherein said one or more test pulses are generated to occur approximately five milliseconds after a leading edge of a positive half-cycle of AC power.

US Pat. No. 10,461,518

GROUNDING SYSTEM

Cambria County Associatio...

1. A transmission assembly structured to support current wire extending between an installation source assembly and an installation receiving assembly, said transmission assembly comprising:a support assembly, said a support assembly including a number of conductive piles and a number of cable hangers;
each said conductive pile structured to support a multi-function line assembly at an elevation above the ground;
each said cable hanger structured to be coupled to a multi-function line and structured to support a current wire;
a grounding system, said grounding system including a multi-function line assembly and a number of conductive mounting assemblies;
each of said conductive mounting assemblies structured to be coupled to said multi-function line and to a conductive pile;
said multi-function line assembly including a multi-function line; and
said multi-function line is coupled to, and in electrical communication with, said number of conductive mounting assemblies and each of said cable hangers.