US Pat. No. 10,171,302

NETWORK CONFIGURATION HEALTH CHECK IN VIRTUALIZED COMPUTING ENVIRONMENT

NICIRA, INC., Palo Alto,...

1. A method for a host to perform network configuration health check in a virtualized computing environment, wherein the host includes multiple network interface controllers (NICs), the method comprising:selecting, from the multiple NICs, a source NIC and one or more destination NICs;
based on a first network configuration of the host, generating one or more unicast probe packets that are addressed from the source NIC to the respective one or more destination NICs;
sending the one or more unicast probe packets to the respective one or more destination NICs from the source NIC via a physical switch connected to the host;
determining whether there is a match between the first network configuration of the host and a second network configuration of the physical switch based on whether the respective one or more destination NICs received the one or more unicast probe packets from the physical switch; and
generating a result of the network configuration health check based on the determining whether there is a match between the first network configuration of the host and the second network configuration of the physical switch.

US Pat. No. 10,171,291

TENANT-SPECIFIC LOG FOR EVENTS RELATED TO A CLOUD-BASED SERVICE

International Business Ma...

1. A method to establish and utilize a tenant-specific log for events related to a cloud-based service, the method comprising:creating, by one or more processors, a metamodel for a cloud-based service running on a cloud, wherein the cloud-based service is provided to a specific tenant of the cloud, and wherein the metamodel describes types of resources, on the cloud, that are providing the cloud-based service for the specific tenant and that the specific tenant desires to monitor;
appending, by one or more processors, the metamodel to the cloud-based service;
in response to the cloud-based service being executed for the specific tenant of the cloud, applying, by one or more processors, the metamodel to identify a set of resources, on the cloud, that are providing the cloud-based service for the specific tenant;
issuing, by one or more processors, instructions to establish a tenant-specific log for events related to the cloud-based service, wherein the tenant-specific log tracks events that occur on each actual resource from the set of resources, on the cloud, that are providing the cloud-based service to the specific tenant, and wherein the tenant-specific log identifies a specific unit of hardware being used to provide the cloud-based service to the specific tenant; and
in response to the tenant-specific log recording access to the specific unit of hardware by a predefined party, transferring, by one or more processors, all operations related to the cloud-based service from the specific unit of hardware to another unit of hardware, wherein the predefined party is an authorized user of the specific unit of hardware, and wherein said another unit of hardware is a local device that is available only to the specific tenant.

US Pat. No. 10,171,290

SYSTEMS AND METHODS FOR REAL-TIME CORRECTION OF CORE APPLICATIONS

Sprint Communications Com...

1. A method for correcting connectivity failures of core applications on a user equipment (UE), the method comprising:detecting, via execution of a client on a processor of the UE, a plurality of request-reply message sequences between a core application of a plurality of core applications and a corresponding server;
learning, by execution of the client, a set of reply messages within the plurality of request-reply message sequences that are coming from the corresponding server and not producing a connection error with the corresponding server;
based on the set of reply messages, creating, by execution of a ghost client on the processor of the UE, a series of ghost replies that each mimics a reply that is one of the set of learned reply messages coming from the corresponding server;
retaining, by execution of the client within a memory of the UE, the series of ghost replies;
subsequent to retaining the series of ghost replies, detecting, by the client, that the core application has exceeded a threshold number of request messages that are unanswered by the corresponding server due to a lack of reply by the corresponding server; and
based on the detecting, feeding, by execution of the client, a ghost reply from the retained series to the core application.

US Pat. No. 10,171,288

DIAGNOSING FAULTS IN STATELESS DISTRIBUTED COMPUTING PLATFORMS

International Business Ma...

1. A computer-implemented method, comprising:processing a plurality of communication messages exchanged between two or more distributed components within a stateless distributed system, wherein the plurality of communication messages comprises (i) one or more representational state transfer messages and (ii) one or more remote procedure call messages;
determining a message context for each of the plurality of communication messages based on one or more message identifiers extracted from each of the plurality of communication messages;
grouping the plurality of communication messages into multiple clusters pertaining to message invocation, wherein said grouping is based on the determined message context for each of the plurality of communication messages;
generating a control flow graph by creating one or more connections across the multiple clusters; and
detecting a causal chain of events associated with a detected fault in the stateless distributed system by navigating the control flow graph;
wherein the steps are carried out by at least one computing device.

US Pat. No. 10,171,269

EQUALIZER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. An equalizer circuit comprising:an equalizer controller configured to provide an enable signal, a delay control signal, and a voltage control signal based on a control signal; and
at least one equalizer configured to provide an equalizer signal based on the enable signal, the delay control signal and the voltage control signal, the at least one equalizer configured to provide the equalizer signal to a corresponding connection node, the corresponding connection node being connected to a corresponding logic circuit,
wherein the at least one equalizer includes,
a delay control circuit configured to delay a transfer signal from the corresponding logic circuit to provide a delayed transfer signal, the delay control circuit configured to delay the transfer signal based on the delay control signal, and
a voltage control circuit configured to provide the equalizer signal based on the delayed transfer signal and the voltage control signal,
wherein the voltage control circuit includes,
a voltage control inverter configured to provide the equalizer signal based on the delayed transfer signal.

US Pat. No. 10,171,260

MANAGING ROUTER ADVERTISEMENT MESSAGES TO SUPPORT ROAMING OF WIRELESS MOBILE CLIENT DEVICES

Cisco Technology, Inc., ...

1. A method comprising:at a controller configured to control one or more wireless access point devices that serve wireless mobile client devices that are part of a first virtual local area network, storing information identifying any other controllers that control other wireless access point devices to which at least one wireless mobile client device that is part of the first virtual local area network has roamed;
storing a list of one or more wireless mobile client devices from which router solicitation messages have been received;
at the controller, receiving a router advertisement message sent by a network router device;
determining whether the router advertisement message is a multicast message and if so determining for which virtual local area network the router advertisement message is intended;
determining whether the router advertisement responds to a router solicitation message received from a particular wireless mobile client device on the stored list;
generating a unicast router advertisement message by changing a header field of the router advertisement message to replace a multicast destination address in the router advertisement message with a media access control address for a wireless mobile client device that is part of the first virtual local area network for which the router advertisement message was intended;
sending the unicast router advertisement message to one or more wireless access point devices for wireless transmission to the particular wireless mobile client device when it is determined that the router advertisement message is intended for the first virtual local area network, wherein the unicast router advertisement message is sent without waiting for a next permitted router advertisement message according to a stored router advertisement frequency parameter; and
forwarding a copy of the multicast router advertisement message to the other controllers that control wireless access point devices to which at least one wireless mobile client device that is part of the first virtual local area network has roamed.

US Pat. No. 10,171,241

STEP-UP AUTHENTICATION FOR SINGLE SIGN-ON

VMWare, Inc., Palo Alto,...

1. A method for providing step-up authentication in a system providing single-sign on to a plurality of applications on a computing device, comprising:receiving a request to authenticate a user of the computing device for a first application using a primary token associated with a single-sign on capability;
determining that the primary token is insufficient to authenticate the user for the first application;
requesting a token agent executing on the computing device to perform a step-up authentication of the user;
updating the primary token to reflect the step-up authentication of the user after receiving an indication of a successful step-up authentication of the user from the token agent;
providing the updated primary token to the computing device;
receiving, from the computing device, a resubmission of the request to authenticate the user for the first application, the resubmitted request including the updated primary token reflecting the step-up authentication; and
transmitting a secondary token to the token agent executing on the computing device based on granting access to the first application, wherein the secondary token authenticates the user for the first application, and wherein granting access to the first application is based on receiving the resubmitted requesting including the updated primary token.

US Pat. No. 10,171,237

HIGH-SPEED AUTOCOMPENSATION SCHEME OF QUANTUM KEY DISTRIBUTION

1. A communication system for transmitting a cryptographic key across a channel, comprising:a transmission node (“Alice”) including a beam splitter, an electro-optical attenuator, an amplitude modulator, an electro-optical phase modulator, a storage line, a Faraday mirror, and a synchronization detector, wherein the storage line directly connects the Faraday mirror and the electro-optical phase modulator;
a receiver node (“Bob”) including a laser, avalanche photodiodes, a beam splitter, a circulator, a delay line, an electro-optical phase modulator, a polarizing beam splitter, and a Mach-Zehnder interferometer connected between the beam splitter and the polarizing beam splitter; and
a quantum channel connecting the transmission and receiver nodes,
wherein the storage line is placed between the electro-optical phase modulator of the transmission node and the Faraday mirror.

US Pat. No. 10,171,235

USER-INITIATED MIGRATION OF ENCRYPTION KEYS

NXP B.V., Eindhoven (NL)...

1. A method, comprising:storing a master key in a non-volatile memory;
using a communication circuit of a computing server,
authenticating a first network communication device in a data network using a first key, wherein the first key is derived from the master key and a first set of key derivation data stored on the first network communication device, and
receiving a data migration request from a second network communication device in the data network, the data migration request specifying the first set of key derivation data and specifying a second set of key derivation data stored at the second network communication device;
in response to receiving the data migration request, using a processing circuit of the computing server to
determine a temporary key used by the second network communication device based on the first and second sets of key derivation data and the master key, and
generate a second key based on the master key and the second set of key derivation data; and
using the communication circuit,
providing the second key to the second network communication device via a secure communication channel established using the temporary key, and
authenticating the second network communication device using the second key.

US Pat. No. 10,171,232

FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)

Intel Corporation, Santa...

1. A system comprising:a processor comprising:
a plurality of cores;
a level 1 (L1) instruction cache to store a plurality of instructions, the plurality of instructions to include a plurality of Advanced Encryption Standard (AES) instructions of an instruction set of the processor that includes a Single Instruction Multiple Data (SIMD) instruction set, wherein the plurality of AES instructions include more than four but less than ten AES instructions including a first AES instruction for a final round of an AES encryption operation, a second AES instruction for a round of the AES encryption operation, a third AES instruction for a round of an AES decryption operation, and a fourth AES instruction for a final round of the AES decryption operation, and wherein the plurality of AES instructions each comprise a different opcode;
an L1 data cache;
instruction fetch logic to fetch instructions from the L1 instruction cache;
decode logic to decode instructions including the first AES instruction;
a microcode memory to store microcode;
a first 128-bit source register to store a round key to be used for the final round of the AES encryption operation;
a second 128-bit source register to store input data to be encrypted by the final round of the AES encryption operation;
a plurality of ports each associated with one or more corresponding execution resources to support parallel execution of integer and floating point operations;
an execution unit including AES execution logic to execute the first AES instruction to perform the final round of the AES encryption operation using microcode determined from the decode of the first AES instruction and obtained from the microcode memory, the final round of the AES encryption operation to use the round key from the first 128-bit source register to encrypt the input data from the second 128-bit source register, and to store a final encrypted result of the final round of the AES encryption operation in a 128-bit destination register,
wherein the final round of the AES encryption operation is to include:
a substitution operation to be performed on the input data, the substitution operation to use a substitution box (S-box) lookup to result in a first array of substituted data;
a Shift Rows transform to shift row data in the first array by a specified amount to generate a shift rows result; and
an Add Round Key transform in which an exclusive OR function is to use data from the round key and the shift rows result; and
a retirement unit
a memory controller to couple the processor to a dynamic random access memory (DRAM); and
an input/output (I/O) controller to couple the processor to one or more devices, the one or more devices to include one or more storage devices, wherein at least one of the one or more storage devices is to be coupled to the processor over at least one Serial Attached Small Computer System Interface (SAS).

US Pat. No. 10,171,223

METHOD AND APPARATUS FOR DYNAMICALLY ASSIGNING MASTER/SLAVE ROLES WITHIN A DISTRIBUTED ANTENNA DIVERSITY RECEIVER APPARATUS

NXP B.V., Eindhoven (NL)...

15. A method of dynamically assigning master/slave roles within a distributed antenna diversity receiver apparatus; the method comprising:receiving intra-packet channel reliability parameters for a master wireless receiver and for at least one slave wireless receiver, wherein the at least one slave wireless receiver is independent of the master wireless receiver and coupled to the master wireless receiver via a bi-directional communication link,
determining whether to assign a new master receiver for the distributed antenna diversity receiver apparatus based on the received intra-packet reliability parameters, and
if it is determined to assign a new master receiver, dynamically re-assigning the master receiver within the distributed antenna diversity receiver apparatus.

US Pat. No. 10,171,219

METHOD AND APPARATUS FOR ENCODING AND PROCESSING ACKNOWLEDGEMENT INFORMATION

HUAWEI TECHNOLOGIES CO., ...

1. A method for encoding acknowledgement information, comprising:receiving at least one component carrier, wherein each component carrier in the at least one component carrier comprises at least one downlink subframe;
generating acknowledgement information bits corresponding to the each component carrier according to the each component carrier;
ordering the acknowledgement information bits corresponding to the each component carrier according to a maximum value DAI_max of a downlink assignment index (DAI) field in downlink control information (DCI) which is received on the each component carrier and used for controlling physical downlink shared channel (PDSCH) transmission or indicating downlink semi-persistent scheduling (SPS) release and the number N_sps of physical downlink shared channels (PDSCHs) scheduled by the SPS in the at least one downlink subframe;
alternately assigning the ordered acknowledgement information bits corresponding to the each component carrier to two groups, and obtaining two groups of acknowledgement information bits; and
encoding the two divided groups of acknowledgement information bits to obtain two groups of codeword bits, respectively, and generating a total codeword bits to be transmitted, from the two groups of codeword bits obtained by the encoding;
wherein the ordering the acknowledgement information bits corresponding to the each component carrier according to the DAI_max and the N_sps comprises:
placing acknowledgement information bits into last N_sps×a bit positions, with the acknowledgement information bits corresponding to N_sps PDSCHs scheduled by semi-persistent scheduling;
placing acknowledgement information bits into first DAI_max×a bit positions, with the acknowledgement information bits corresponding to downlink subframes corresponding to DCI of DAI=1 to DAI=DAI_max; and
setting the remaining (D×a?(DAI_max+N_sps)×a) acknowledgement information bits to ‘0’;
wherein the a is a bit number of acknowledgement information bits corresponding to each of the downlink subframes and the D is a number of downlink subframes for which the acknowledgement information bits need to be generated.

US Pat. No. 10,171,212

METHOD AND DEVICE FOR PERFORMING CHANNEL ESTIMATION

LG Electronics Inc., Seo...

1. A method for performing channel state reporting on a downlink channel transmitted through M two-dimensionally arranged antenna ports, the method implemented by a user equipment (UE) and comprising:receiving a channel state information-reference signal (CSI-RS) configuration for N virtual antenna ports formed by applying beamforming to each vertical antenna group of the M two-dimensionally arranged physical antenna ports matrix;
calculating channel state information (CSI) about the downlink channel using the received CSI-RS configuration; and
reporting the CSI to a serving cell associated with the UE,
wherein the reported CSI comprises information about rotational transformation of a first codeword in a codebook for a combination of Q unit vectors orthogonal to each other in an N-dimensional space,
wherein the reported CSI further comprises an indicator indicating whether the rotational transformation to be applied overlaps with a previous rotational transformation, and
wherein N and Q are integers satisfying 2?Q?N, and M is an integer satisfying 2?M.

US Pat. No. 10,171,210

METHOD AND DEVICE FOR SPECTRUM COMB SIGNALING NOTIFICATION AND FOR SOUNDING REFERENCE SIGNAL TRANSMISSION

1. A spectrum comb signaling notification method, comprising:a network side configuring and notifying a receiving side of a two-layer spectrum comb signaling, including a first spectrum comb signaling and a second spectrum comb signaling, and the two-layer spectrum comb signaling indicating subcarrier positions of transmitting sounding reference signals to the receiving side;
wherein the method further comprises: performing joint encoding on a repetition factor and a spectrum comb value to generating the second spectrum comb signaling;
wherein the first spectrum comb signaling is used to instruct a first user at the receiving side to determine the subcarrier positions of transmitting the sounding reference signals, and the second spectrum comb signaling is used to instruct a second user at the receiving side to determine the subcarrier positions of transmitting the sounding reference signals;
wherein the second spectrum comb signaling is a 3-bit high layer signaling, and an attribute of the 3-bit high layer signaling is UE-specific;
wherein the second spectrum comb signaling instructs the second user to occupy subcarrier positions whose subcarrier indexes are a multiple of 2, a multiple of 2 plus 1, a multiple of 4, a multiple of 4 plus 1, a multiple of 4 plus 2, or a multiple of 4 plus 3 within a sounding signal bandwidth.

US Pat. No. 10,171,208

DYNAMIC ERROR CORRECTION PROCEDURES

Verizon Patent and Licens...

1. A base station, comprising:a non-transitory computer-readable medium storing a set of processor-executable instructions; and
one or more processors configured to execute the set of processor-executable instructions, wherein executing the set of processor-executable instructions causes the one or more processors to:
monitor network conditions corresponding to a Radio Access Network (RAN), of a wireless telecommunications network, to which the base station corresponds, wherein the monitored network conditions include at least one of:
a quantity of user equipment (UEs) connected to the base station, or
a quantity of connections between the UEs and the base station;
transmit information to a particular UE connected to the base station;
receive a notification, from the particular UE, that the particular UE failed to receive the information,
wherein the notification from the particular UE includes a request to retransmit the information that the particular UE failed to receive,
wherein the request from the particular UE corresponds to at least one of:
a Hybrid Automatic Repeat Request (HARQ) procedure,
a Forward Error Correction (FEC) procedure, or
a channel coding procedure;
determine an appropriate error correction policy, from a plurality of error correction policies, based on whether the network conditions exceed a threshold representing a level of network activity associated with the RAN;
when the network conditions exceed the threshold, implement a first error correction policy that includes instructions to retransmit information, corresponding to failed transmissions, in accordance with:
a service requirement associated with each failed transmission, and
an availability of network resources to retransmit information corresponding to the failed transmissions;
when the network conditions does not exceed the threshold, implement a second error correction policy that includes instructions to enhance the efficiency with which the information, corresponding to the failed transmissions, is retransmitted by allocating additional network resources to the retransmission of the information corresponding to the failed transmissions, wherein the second error correction policy is selected without regard to the service requirement associated with the failed transmissions; and
retransmit the information, corresponding to the notification, in accordance with the first error correction policy or the second error correction policy.

US Pat. No. 10,171,207

METHODS AND APPARATUS FOR CONTROL BIT DETECTION

Cavium, LLC, Santa Clara...

1. A method of detecting control bit information from a user equipment (UE) via a communication network which includes at least one radio tower, switching network, and a control bit detector (CBD), wherein the CBD includes a threshold generator, a control bit log-likelihood ratio (LLR) input interface, a processor, and an output register, the method comprising:receiving, at the control bit LLR input interface, an LLR sequence (l) that includes P control bits;
calculating, at the processor, a sum of LLR squares parameter (L) associated with the LLR sequence;
generating a (Vp) value for each of 2P combinations of the control bits, wherein each Vp value is computed based on a new sequence and the LLR sequence;
determining, by the processor, a smallest value of Vp; and
outputting, by the CBD, a determination that a control bit combination was received if the smallest value of Vp is less than a threshold value (THD) multiplied by the parameter L.

US Pat. No. 10,171,199

TUNABLE LASER IN AN OPTICAL ACCESS NETWORK

Google LLC, Mountain Vie...

16. A method comprising:receiving, at data processing hardware, a request to transmit a data packet from an optical network unit (ONU) to an optical line terminal (OLT) of an optical access network having a multiplexer optically coupled between the ONU and the OLT, the multiplexer having a wavelength pass-band, the ONU comprising a tunable laser configured to continuously transmit an optical signal that alternates between a burst-on state and a burst-off state;
triggering, by the data processing hardware, the burst-on state of the tunable laser by transmitting a burst-on current to the tunable laser, the burst-on current biasing the tunable laser to transmit the optical signal at a transmit wavelength within the wavelength pass-band of the multiplexer, the multiplexer configured to allow passage therethrough of the optical signal at the transmit wavelength;
instructing, by the data processing hardware, the tunable laser to transmit the data packet in the optical signal; and
after transmission of the data packet, enabling, by the data processing hardware, the burst-off state of the tunable laser by transmitting a burst-off current to the tunable laser, the burst-off current biasing the tunable laser to transmit the optical signal at a non-transmit wavelength outside of the wavelength pass-band of the multiplexer, the multiplexer configured to block passage therethrough of the optical signal at the non-transmit wavelength.

US Pat. No. 10,171,196

TERMINAL DEVICE, BASE STATION APPARATUS, AND INTEGRATED CIRCUIT

SHARP KABUSHIKI KAISHA, ...

1. A terminal device that communicates with a base station device, comprising:higher layer processing circuitry configured to receive configuration information;
reception circuitry configured to monitor downlink control information (DCI) via a physical downlink control channel (PDCCH); and
signal detection circuitry configured to detect a modulation and coding scheme (MCS) for the terminal device based on the monitored DCI,
wherein, the configuration information includes whether a prescribed reception scheme for a multi-user transmission is applied or not,
in a case where the prescribed reception scheme is applied, the signal detection circuitry detects a modulation scheme of an interference from the DCI,
in a case where the prescribed reception scheme is not applied, the signal detection circuitry detects the MCS for the terminal device from the DCI, and
the DCI is defined in a same DCI format regardless of whether the prescribed reception scheme is applied or not.

US Pat. No. 10,171,186

METHOD AND DEVICE FOR DETECTING NOTCH BAND

MSTAR SEMICONDUCTOR, INC....

1. A method for detecting a notch band in a bandwidth of a frequency spectrum of a received signal, applied to a multicarrier system operating in a wideband, the method comprising:receiving the received signal, and generating a plurality of frequency-domain signals according to the received signal;
performing a magnitude operation on the plurality of frequency-domain signals to obtain a plurality of magnitude values; and
determining whether there is a notch band in the bandwidth of the frequency spectrum of the received signal according to a plurality of ratios of a first magnitude set among the plurality of magnitude values to a second magnitude set among the plurality of magnitude values;
wherein, a first magnitude value in the first magnitude set corresponds to a second magnitude value in the second magnitude set, and a frequency where the first magnitude value is located is spaced from a second frequency where the second magnitude value is located by a fixed interval,
wherein the step of determining whether there is a notch band in the bandwidth of the frequency spectrum of the received signal according to the plurality of ratios of the first magnitude set among the plurality of magnitude values to the second magnitude set among the plurality of magnitude values comprises;
obtaining the plurality of ratios of the first magnitude set among the plurality of magnitude values to the second magnitude set among the plurality of magnitude values; and
determining whether there is a notch band in the bandwidth of the frequency spectrum of the received signal according to the plurality of ratios; and
wherein the step of obtaining the plurality of ratios comprises:
obtaining each of the plurality of ratios as a ratio of a third magnitude value in the first magnitude set to a fourth magnitude value in the second magnitude set corresponding to the third magnitude value.

US Pat. No. 10,171,176

PHASE DEMODULATION METHOD AND CIRCUIT

Elenion Technologies, LLC...

18. An electrical circuit for demodulating a received PSK modulated carrier signal, the electrical circuit comprising:a first signal splitter configured to split the received PSK modulated carrier signal into two analog PSK-modulated signals, each comprising a PSK-modulated carrier wave with a carrier wave frequency f that may vary in time;
a multiplying circuit disposed to receive a first of the two analog PSK-modulated signals and configured to convert it into a frequency-multiplied carrier signal absent of PSK modulation;
a first frequency dividing flip-flop circuit configured to convert the frequency multiplied carrier signal into a first reference carrier wave signal with the carrier wave frequency f,
a first electrical signal mixer configured to mix the first reference carrier wave signal with the second of the two analog PSK-modulated signals to extract a first de-modulated signal therefrom; and,
an electrical transmission line connecting the first signal splitter with the first electrical signal mixer;wherein the received PSK modulated carrier signal comprises a BPSK modulated signal, wherein the multiplying circuit comprises a signal squaring circuit configured to output a frequency-doubled carrier wave signal, and wherein the electrical circuit further comprises:a second frequency dividing circuit connected in parallel with the first frequency dividing circuit so as to obtain a second reference carrier wave signal that is phase-shifted relative to the first reference carrier wave,
a second electrical signal mixer configured to mix the second reference carrier wave signal with a portion of the second of the two analog PSK-modulated signals, and
an electrical signal combiner disposed to combine outputs from the first and second electrical signal mixers to produce an output de-modulated signal.

US Pat. No. 10,171,175

METHOD AND APPARATUS FOR DESPREADING IN OPTICAL DOMAIN

Huawei Technologies Co., ...

1. An apparatus for despreading in an optical domain, comprising:an optical splitter configured to:
split a received optical signal into a first optical signal and a second optical signal;
output the first optical signal to an optical coupler; and
output the second optical signal to an optical modulator,
wherein the optical modulator is coupled to the optical splitter and is configured to:
perform field modulation on the second optical signal to obtain a third optical signal; and
output the third optical signal to the optical coupler, wherein a phase difference between the third optical signal and the first optical signal is a first difference,
wherein the optical coupler is coupled to the optical splitter and the optical modulator and is configured to:
perform phase deflection processing on the first optical signal and the third optical signal to obtain a fourth optical signal and a fifth optical signal respectively; and
output the fourth optical signal and the fifth optical signal to a balanced receiver,
wherein the balanced receiver is coupled to the optical coupler and is configured to:
superimpose electrical signals obtained by converting the fourth optical signal and the fifth optical signal to generate a first electrical signal; and
output the first electrical signal to an accumulator, and
wherein the accumulator is coupled to the balanced receiver and is configured to accumulate the first electrical signal in each code word period.

US Pat. No. 10,171,170

MULTI-CHANNEL PARALLEL OPTICAL TRANSCEIVER MODULE

Global Technology Inc., ...

1. A multi-channel parallel optical transceiver module, comprising:a shell body and a circuit board located in the shell body;
an optical emitter base soldered to a first end of the circuit board;
a notch located on the optical emitter base for engaging the first end of the circuit board with the first end of the optical emitter base being soldered to two opposite sides of the circuit board;
a plurality of optical emitters disposed in parallel on the optical emitter base, wherein at least two of the optical emitter of the plurality of optical emitters are separated from each other by a block;
a plurality of lasers, each laser of the plurality of lasers disposed at a first side of an associated optical emitter of the plurality of optical emitters;
a plurality of lenses, each lens of the plurality of lenses being associated with a laser of the plurality of lasers and disposed at the first side of an associated optical emitter of the plurality of optical emitters;
a plurality of optical monitors, each optical monitor of the plurality of optical monitors disposed on a second end of the circuit board adjacent to an associated laser of the plurality of lasers, wherein each optical monitor is connected to an associated laser by a bonding wire, each optical monitor of the plurality of optical monitors and laser of the plurality of lasers being connected to a laser controller and a driving chip disposed on the circuit board;
an optical fiber array and a processing chip for received optical signals adhered onto the circuit board;
a first metal shielding mask disposed on the circuit board for covering and sealing the optical fiber array and the processing chip for the received optical signals; and
a second metal shielding mask disposed on the circuit board, for covering and sealing the first metal shielding mask, the optical monitor, the laser controller, and the driving chip.

US Pat. No. 10,171,159

DONOR SELECTION FOR RELAY ACCESS NODES USING REFERENCE SIGNAL BOOSTING

Sprint Spectrum L.P., Ov...

1. A method for donor selection in a relay access node, the method comprising:identifying a plurality of candidate donor access nodes;
obtaining one or more characteristics associated with each of the plurality of candidate donor access nodes;
determining a primary donor access node based on a comparison of the one or more characteristics between each of the plurality of candidate donor access nodes;
receiving a reference signal transmitted by the primary donor access node at a transmission power higher than a transmission power of downlink information transmitted by the primary donor access node;
evaluating one or more quality characteristics of the primary donor access node; and
based on the one or more quality characteristics meeting a predetermined threshold, requesting a connection to the primary donor access node.

US Pat. No. 10,171,158

ANALOG SURFACE WAVE REPEATER PAIR AND METHODS FOR USE THEREWITH

1. An analog surface wave repeater pair comprising:a first launcher configured to transmit and receive first guided electromagnetic waves that propagate on an outer surface of a first segment of a transmission medium without requiring an electrical return path;
a second launcher configured to transmit and receive second guided electromagnetic waves that propagate on an outer surface of a second segment of transmission medium without requiring an electrical return path;
a first transceiver including:
a first low noise amplifier configured to receive a first microwave signal from the first launcher, wherein the first microwave signal is generated by the first launcher in response to receiving the first guided electromagnetic waves from the first segment of the transmission medium;
a first notch filter configured to attenuate signals in a fourth generation (4G) wireless frequency band from the first microwave signal;
a first amplifier configured to amplify a second microwave signal; and
a first directional coupler configured to couple the first microwave signal from the first launcher and the second microwave signal to the first launcher to facilitate transmission of the first guided electromagnetic waves on the first segment of the transmission medium; and
a second transceiver including:
a second low noise amplifier configured to receive the second microwave signal from the second launcher, wherein the second microwave signal is generated by the second launcher in response to receiving the second guided electromagnetic waves from the second segment of the transmission medium;
a second notch filter configured to attenuate signals in the 4G wireless frequency band from the second microwave signal;
a second amplifier configured to amplify the first microwave signal; and
a second directional coupler configured to couple the second microwave signal from the second launcher and the first microwave signal to the second launcher to facilitate transmission of the second guided electromagnetic waves on the second segment of the transmission medium.

US Pat. No. 10,171,153

METHOD AND APPARATUS FOR TRANSMITTING CHANNEL STATE INFORMATION IN WIRELESS COMMUNICATION SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for transmitting channel state information (CSI) by a user equipment in a wireless communication system, the method comprising:subsampling a first codebook associated with a first PMI (precoding matrix indicator) and a second codebook associated with a second PMI according to a reporting submode for 4 antenna ports,
wherein the subsampling, for selecting Discrete Fourier Transform (DFT) vectors, comprises selecting a second codebook index for the second PMI based on a first codebook index for the first PMI,
wherein the DFT vectors selected are odd-numbered vectors of vectors of a beam group constructing the first codebook if the first codebook index corresponds to an even number, and
wherein the DFT vectors selected are even-numbered vectors of the vectors of the beam group if the first codebook index corresponds to an odd number; and
transmitting the channel state information based on the subsampled first codebook and the second codebook.

US Pat. No. 10,171,142

DATA TRANSMISSION METHOD, APPARATUS, AND DEVICE

Huawei Technologies Co., ...

1. A data transmission method, wherein the method comprises:determining, by a transmit end device, a signature matrix S according to a quantity L of layers of a data stream and a quantity R of receive antennas used by a receive end device, wherein the signature matrix S comprises L first element sequences arranged in a first dimensional direction, the L first element sequences are in one-to-one correspondence with the L layers of the data stream, each first element sequence of the L first element sequences comprises R first elements arranged in a second dimensional direction, the R first elements are in one-to-one correspondence with the R receive antennas, the R first elements comprise at least one zero element and at least one non-zero element, R?2, the L first element sequences are different from each other, the L layers of the data stream correspond to a same time-frequency resource, and L?2;
determining, by the transmit end device, a precoding matrix P according to a channel matrix H and the signature matrix S, and performing precoding processing on the L-layer data stream according to the precoding matrix P, wherein the channel matrix H corresponds to channels between the transmit end device and the receive end device, the precoding matrix P comprises L second element sequences arranged in the first dimensional direction, the L second element sequences are in one-to-one correspondence with the L first element sequences, and the L second element sequences are in one-to-one correspondence with the L layers of the data stream; and
sending, by the transmit end device to the receive end device, the L-layer data stream on which the precoding processing has been performed and information used to indicate the signature matrix S.

US Pat. No. 10,171,140

MU-MIMO GROUP SELECTION

Hewlett Packard Enterpris...

1. A communications device, comprising:communications circuitry to wirelessly communicate with a number of client devices using multiple possible bandwidth settings; and
control circuitry to determine signal-to-interference-plus-noise ratios (SINRs) for the client devices based on compressed client-side channel state information received from the client devices, and to select a set of multi-user-multiple-input-multiple-output (MU-MIMO) groups and bandwidth settings respectively assigned thereto, by:
estimating, based on the SINRs, bandwidth-specific throughputs for potential MU-MIMO groups at a specified bandwidth setting from among the multiple-possible bandwidth settings, and
selecting the set of MU-MIMO groups together with their respectively assigned bandwidth settings based on the bandwidth-specific throughputs.

US Pat. No. 10,171,137

METHOD AND DEVICE FOR TRANSMITTING DATA BY USING SPATIAL MODULATION SCHEME IN WIRELESS ACCESS SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for transmitting data signals from a transmitter by using a spatial modulation (SM) scheme in a wireless access system, the method performed an enhanced Node-B (eNB) and comprising:selecting two or more transmitting antennas for transmitting the data signals by using two or more ranks;
deriving data bit streams by applying the SM scheme,
wherein the data bit streams correspond to the two or more ranks;
configuring the data signals by using the SM scheme on the basis of the data bit streams;
transmitting, to a user equipment (UE), an enhanced physical downlink control channel (E-PDCCH) and demodulation reference signals (DM-RSs) through one of the two or more transmitting antennas, the E-PDCCH including rank information indicating a number of rank used for transmitting the data signals; and
transmitting, to the UE, the configured data signals through the selected two or more transmitting antennas and DM-RSs matched with each of the selected two or more transmission antennas,
wherein each of the two or more transmission antennas uses different predetermined DM-RSs from each other,
wherein combinations of the rank information and the DM-RSs identify each of the two or more transmission antennas,
wherein, if the E-PDCCH is transmitted through a first transmission antenna of the two or more transmission antennas, this represents a positive acknowledgment (ACK) for uplink data transmitted from the UE, and
wherein, if the E-PDCCH is transmitted through a second transmission antenna of the two or more transmission antennas, this represents a negative acknowledgement (NACK) for the uplink data transmitted from the UE.

US Pat. No. 10,171,136

REDUCING INTERNAL SIGNALING BURDEN IN THE DISTRIBUTED ANTENNA SYSTEM

LG ELECTRONICS INC., Seo...

1. A method for a user equipment (UE) to receive signals from a network, the method comprising:receiving a first information unit from the network by a first distributed unit (DU) among multiple DUs distributed within the UE;
reporting, by the first DU, reception information of the first information unit to a central unit (CU) of the UE before decoding the received first information unit, wherein the CU controls the multiple DUs;
receiving, at the first DU from the CU, a direction indicating whether the first DU is to decode the received first information unit or not, and indicating whether the first DU is to transfer the received first information unit to the CU or another DU within the UE,
wherein the CU sends the direction based on the reception information of the first received information unit; and
decoding and transferring, by the first DU, the received first information unit to the CU and the another DU within the UE when the direction indicates a specific value,
wherein the CU sends the direction with an indication that the first DU is to transfer the first information unit.

US Pat. No. 10,171,131

ELECTRONIC TUNING SYSTEM

William Redman-White, Al...

1. A circuit configured to control a resonant frequency of a tuned circuit so as to correspond with an applied excitation frequency over a continuous range of excitation frequencies, the tuned circuit comprising: an inductor; at least two capacitors; and at least one switch connected in combination with one of the at least two capacitors, wherein an apparent resonant frequency can be varied by controlling the duty cycle of an opening and closing of the at least one switch; and a source providing an excitation signal to the tuned circuit, the circuit configured to control the resonant frequency comprising:a voltage sensor configured to sense a voltage across two terminals of the at least one switch when the at least one switch is in an open state;
tuning control circuitry configured to derive a tuning control input signal from the sensed voltage; and
switch timing circuitry configured to control the timing of the opening and closing of the at least one switch in a manner based on the derived tuning control input signal, wherein the opening and closing instants of the said at least one switch are synchronous with the applied excitation signal and wherein the opening and closing instants of the said at least one switch are substantially equally spaced in time around a peak of a voltage at the connection between the inductor and the capacitors when the circuit is at resonance.

US Pat. No. 10,171,130

RECEIVER CIRCUIT

Power Integrations, Inc.,...

1. An analog receiver frontend, comprising:a first amplification circuit coupled to receive an input signal, wherein the first amplification stage is coupled to amplify a difference between the input signal and a threshold to generate the first signal;
a second amplification circuit coupled to receive the first signal from the first amplification circuit, wherein the second amplification circuit is coupled to amplify the first signal to generate a second signal;
an output circuit coupled to receive the second signal from the second amplification circuit, wherein the output circuit is coupled to output a recovered signal wherein the recovered signal is a pulse waveform of high and low sections; and
an input hysteresis circuit coupled to the output circuit to receive the recovered signal and generate a hysteresis signal, wherein one or both of the input signal and the threshold are level shifted by the hysteresis signal in response to the recovered signal.

US Pat. No. 10,171,126

APPARATUS FOR UPLINK MULTI-ANTENNA COMMUNICATION BASED ON A HYBRID COUPLER AND A TUNABLE PHASE SHIFTER

Intel IP Corporation, Sa...

1. Front end module (FEM) circuitry, comprising:a hybrid coupler to generate a first antenna transmit signal and a second antenna transmit signal based on hybrid coupler input signals; and
one or more tunable phase shifters to generate the hybrid coupler input signals based at least partly on an FEM input signal,
wherein the first antenna transmit signal is based on a first signal summation that comprises summation of a first hybrid coupler input signal and a second hybrid coupler input signal phase-shifted, by the hybrid coupler, according to a predetermined hybrid coupler phase shift, and
wherein the second antenna transmit signal is based on a second signal summation that comprises summation of the second hybrid coupler input signal and the first hybrid coupler input signal phase-shifted, by the hybrid coupler, according to the predetermined hybrid coupler phase shift.

US Pat. No. 10,171,123

TRIPLE-GATE PHEMT FOR MULTI-MODE MULTI-BAND SWITCH APPLICATIONS

SKYWORKS SOLUTIONS, INC.,...

1. A switch element comprising:a source including a plurality of source fingers and a drain including a plurality of drain fingers interleaved with the source fingers;
an active mesa region defined between at least one of the plurality of source fingers and an adjacent at least one of the plurality of drain fingers; and
a plurality of gates disposed between the at least one of the plurality of source fingers and the adjacent at least one of the plurality of drain fingers, at least one of the plurality of gates including a finger extending into the active mesa region from outside of the active mesa region and terminating within the active mesa region, the plurality of gates including a first gate, a second gate, and a third gate, a non-zero voltage difference across the source and the drain being evenly divided between the first gate, the second gate, and the third gate.

US Pat. No. 10,171,114

RADIO FREQUENCY SWITCH APPARATUS HAVING IMPROVED NOISE SUPPRESSION CHARACTERISTICS

Samsung Electro-Mechanics...

1. A radio frequency switch apparatus, comprising:a first switching circuit connected between an antenna terminal and a first signal terminal, comprising a first series switching circuit and a first shunt switching circuit configured to switch a first signal band on and off;
a second switching circuit connected between the antenna terminal and a second signal terminal, configured to switch a second signal band, different from the first signal band, on and off; and
an inductor circuit comprising a first inductor device connected between the first shunt switching circuit and a ground,
wherein the first inductor device suppresses noise, except for the first signal band and the second signal band, by being resonant with a capacitance present upon the first shunt switching circuit being turned off.

US Pat. No. 10,171,103

HARDWARE DATA COMPRESSION ARCHITECTURE INCLUDING SHIFT REGISTER AND METHOD THEREOF

Mellanox Technologies, Lt...

1. A hardware compression architecture, comprising:a shift register including a plurality of sequentially coupled stages and a window stage coupled at an output end of the shift register, the shift register configured to receive an uncompressed data stream at an input end and output the uncompressed data from the window stage;
a plurality of comparators each coupled to receive a data value held in a corresponding stage of the shift register and a data value held in the window stage, each of the comparators being configured to output a comparison result indicating whether the received stage value and the window stage data value match;
logic, coupled to the comparators to receive the comparison results, to selectively compute one or more indexes based on the comparisons; and
an encoder coupled to receive the one or more indexes and output, based on the one or more indexes, a position of a matching data value and a length of a matching sequence of data values.

US Pat. No. 10,171,100

CIRCUIT AND METHOD FOR GENERATING REFERENCE SIGNALS FOR HYBRID ANALOG-TO-DIGITAL CONVERTORS

STMICROELECTRONICS INTERN...

1. A circuit configured to generate a plurality of reference signals for an analog-to-digital convertor (ADC) comprising a first stage and a second stage, the circuit comprising:a first reference source comprising a first output terminal and a second output terminal coupled to respective terminals of the first stage of the ADC, the first reference source being configured to generate a first reference voltage between the first output terminal and the second output terminal of the first reference source, the first reference voltage being configured to be provided as a first reference signal to the first stage of the ADC, the first reference voltage comprising a first transient signal generated by the first stage of the ADC;
a filter coupled to the first output terminal and the second output terminal of the first reference source and configured to filter the first transient signal from the first reference signal to produce a filtered first reference signal; and
a second reference source having input terminals coupled to the filter, wherein the filter comprises at least one first capacitive element coupled between the input terminals of the second reference source, the second reference source comprising a first output terminal and a second output terminal coupled to respective terminals of the second stage of the ADC, the second reference source configured to generate a second reference signal between the first output terminal and the second output terminal of the second reference source based on the filtered first reference signal, the second reference signal being configured to be provided as a second reference signal to the second stage of the ADC.

US Pat. No. 10,171,093

SLEW RATE LOCKED LOOP

2. A slew rate locked loop circuit for controlling and maintaining a constant slew rate at an output of a buffer, wherein said buffer receives (i) a first input signal and (ii) at least one of a control voltage, said slew rate locked loop circuit comprising:a slew rate determining unit that comprises:
a first reference voltage generator that generates (i) an upper threshold voltage (Vh) and (ii) a lower threshold voltage (Vl);
a first comparator that compares said upper threshold voltage (Vh) with said output of said buffer to obtain a first output digital signal;
a second comparator, that compares said lower threshold voltage (Vl) with said output of said buffer to obtain a second output digital signal; and
a phase detector that determines a phase difference between said first output digital signal and said second output digital signal, wherein said phase difference is directly proportional to said slew rate at said output of said buffer;
a loop filter that produces a DC voltage from an output of said phase detector;
a second reference voltage generator that generates a reference voltage; and
an amplifier that (a) receives said DC voltage from said loop filter and said reference voltage generated by said second reference voltage generator, and (b) amplifies the difference between (i) said DC voltage from said loop filter and (ii) said reference voltage to obtain a control voltage, wherein said control voltage is fed back to said buffer, wherein said slew rate at said output of said buffer is determined using said control voltage.

US Pat. No. 10,171,089

PVT-FREE CALIBRATION FUNCTION USING A DOUBLER CIRCUIT FOR TDC RESOLUTION IN ADPLL APPLICATIONS

Taiwan Semiconductor Manu...

1. A circuit, comprising:a time-to-digital converter (TDC) configured to generate a phase variation signal indicative of a phase difference between a first signal and a reference signal; and
a doubler electrically coupled to the TDC, wherein the doubler is configured to receive a first voltage signal and generate a second voltage signal, wherein the second voltage signal is provided to a voltage input of the TDC, and wherein the TDC generates one or more control signals configured to adjust the second voltage signal, wherein the doubler comprises:
a first ring oscillator;
a first flip-flop electrically coupled to the first ring oscillator; and
a first clock generator electrically coupled to an output of the first flip-flop.

US Pat. No. 10,171,086

SUPERCONDUCTING THREE-TERMINAL DEVICE AND LOGIC GATES

Massachusetts Institute o...

1. A three-terminal device comprising:a main channel connecting a first terminal and a second terminal;
a gate channel connecting a control terminal to the main channel; and
a low-resistance constriction formed in the gate channel between the control terminal and the main channel, wherein the constriction is configured to increase a gate current density proximal to the main channel and the constriction is located within approximately 200 nm of an edge of the main channel.

US Pat. No. 10,171,082

DRIVING CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A driving circuit which drives a subsequent stage circuit depending on a set signal and a reset signal that are inputted, comprising:a set side level shift circuit which operates depending on the set signal, and generates a set potential,
a reset side level shift circuit which operates depending on the reset signal, and generates a reset potential, and
a control circuit which generates a control signal depending on the set potential and the reset potential, and drives the subsequent stage circuit, wherein
each of the set side level shift circuit and the reset side level shift circuit has
an input transistor which is provided between a high potential and a reference potential, operates depending on the set signal or the reset signal, and outputs a drain potential as the set potential or the reset potential, and
a serial transistor unit which includes a first MOS transistor and a second MOS transistor which are connected in series between a drain terminal of the input transistor and the high potential,
the first MOS transistors in the set side level shift circuit and the reset side level shift circuit complementarily operate to each other corresponding to a logical value of the control signal which the control circuit outputs,
the set side level shift circuit further has a set side buffer which compares a level of the set potential with a threshold value of the set side buffer depending on the high potential, and controls the second MOS transistor of the reset side level shift circuit based on a result of the comparison of the level of the set potential with the threshold value of the set side buffer,
the reset side level shift circuit further has a reset side buffer which compares a level of the reset potential with a threshold value of the reset side buffer depending on the high potential, and controls the second MOS transistor of the set side level shift circuit based on a result of the comparison of the level of the reset potential with the threshold value of the reset side buffer.

US Pat. No. 10,171,079

METHODS AND APPARATUSES FOR DYNAMIC STEP SIZE FOR IMPEDANCE CALIBRATION OF A SEMICONDUCTOR DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a resistor; and
a chip comprising a driver impedance calibration circuit configured to determine an impedance of a driver based on an impedance of the resistor, wherein, during a calibration operation, the driver impedance calibration circuit is configured to adjust an impedance code that controls an impedance of the driver and to provide a next impedance code based on a comparison of a driver output voltage with a reference voltage, wherein an adjustment step size of the impedance code is determined based on a value of the impedance code, wherein the driver impedance calibration circuit comprises an adder/subtractor circuit configured to adjust the impedance code based on a comparison of a driver output voltage with a reference voltage and wherein the adder/subtractor circuit is configured to adjust the impedance code by a value equal to a value of a subset of most significant bits of the impedance code.

US Pat. No. 10,171,073

REGULATING TRANSITION SLOPE USING DIFFERENTIAL OUTPUT

SEMICONDUCTOR COMPONENTS ...

1. A circuit for producing a differential output signal pair, the circuit comprising:a first driver for a first output signal in the differential output signal pair;
a second driver for a second output signal in the differential output signal pair;
one or more monitor modules coupled to the first and second drivers to measure slope times of the first and second drivers during each transition;
a comparator coupled to the one or more monitor modules to compare the slope times of the first and second drivers;
one or more regulators coupled to the comparator and at least one of the first and second drivers to regulate at least one slope time of the first or second driver, based on output of the comparator, to provide the first and second output signals in the differential output signal pair with a constant average.

US Pat. No. 10,171,070

SIGNAL TRANSMISSION CIRCUIT AND POWER CONVERSION DEVICE

Mitsubishi Electric Corpo...

1. A signal transmission circuit comprising:a first circuit to output first and second transmission signals on the basis of an external input signal;
first and second transformers to receive said first and second transmission signals on a primary side and obtain first and second transformer output signals on a secondary side; and
a second circuit to generate an external output signal on the basis of said first and second transformer output signals,
wherein said external input signal has first and second logic levels, changes from the second logic level to the first logic level at a first transition time, and changes from the first logic level to the second logic level at a second transition time,
said first circuit outputs said first and second transmission signals such that said first transmission signal changes between the first and second logic levels in a first period when said external input signal is at the first logic level, is fixed to the second logic level when said external input signal is at the second logic level, and is set at the first logic level for a predetermined period at said first transition time of said external input signal, and
such that said second transmission signal changes between the first and second logic levels in a second period when said external input signal is at the second logic level, is fixed to the second logic level when said external input signal is at the first logic level, and is set at the first logic level for a predetermined period at said second transition time of said external input signal, and
said second circuit includes
first and second control protectors to invalidate said first and second transformer output signals for first and second mask periods on the basis of the first or second logic level of said external output signal,
a first signal shaping circuit to receive said first transformer output signal via said first control protector and generate a first logic setting signal indicating an active level for a first logic setting period exceeding a period for which said first transformer output signal indicates an active level,
a second signal shaping circuit to receive said second transformer output signal via said second control protector and generate a second logic setting signal indicating an active level for a second logic setting period exceeding a period for which said second transformer output signal indicates an active level,
a logic setting signal control circuit to receive said first and second logic setting signals and invalidate indication of an active level by said first and second logic setting signals when both said first and second logic setting signals indicate an active level, and
an output signal generation circuit to receive said first and second logic setting signals via said logic setting signal control circuit and generate said external output signal that is set at one logic level of first and second logic levels when said first logic setting signal indicates an active level, and set at the other logic level when said second logic setting signal indicates an active level.

US Pat. No. 10,171,068

INPUT INTERFACE CIRCUIT

MSTAR SEMICONDUCTOR, INC....

1. An input interface circuit, comprising:a power line, supplying a default operating voltage;
a ground line, supplying a ground voltage;
an input pad, receiving a pad voltage;
a clamping circuit, coupled between the input pad and a first node, the clamping circuit causing a voltage at the first node to be maintained at the default operating voltage when the pad voltage is higher than the default operating voltage;
a first inverter, having an input end and an output end, the input end coupled to the first node and the output end coupled to a second node;
a high-voltage buffering circuit, having a first input end, a second input end and an output end, the first input end coupled to the input pad, the second input end coupled to the second node, and the output end coupled to a third node, wherein a voltage at the third node is adjusted along with the pad voltage and a voltage at the second node, and the voltage at the third node has a same voltage change trend as the pad voltage;
a second inverter, having an input end and an output end, the input end coupled to the third node and the output end coupled to a fourth node;
a voltage recovery circuit, connected between the power line and the ground line, having an input end and an output end, the input end coupled to the fourth node and the output end coupled to the third node, the third node is selectively coupled to one of the power line and the ground line according to a voltage at the fourth node; and
a third inverter, having an input end thereof coupled to the fourth node and an output end thereof providing a converted voltage.

US Pat. No. 10,171,059

COMPOSITE COMPONENT AND FRONT-END MODULE

MURATA MANUFACTURING CO.,...

1. A composite component adapted for being disposed on a mounting substrate, the composite component comprising:a transmitting filter;
a first substrate adapted for being disposed adjacent to the mounting substrate and electrically connected to the mounting substrate;
a second substrate disposed opposite to the first substrate;
a spacer member interposed between the first substrate and the second substrate to support the first substrate and the second substrate, the spacer member being configured to electrically connect the first substrate to the second substrate,
wherein the second substrate is adapted for being electrically connected to the mounting substrate through a second spacer member; and
the transmitting filter is disposed in an internal space and on a principal surface of the first substrate, the internal space being surrounded by the first substrate and the second substrate.

US Pat. No. 10,171,056

APPARATUS AND METHOD FOR IMPROVING NONLINEARITY OF POWER AMPLIFIER IN WIRELESS COMMUNICATION SYSTEM

Samsung Electronics Co., ...

1. A method for operating an apparatus comprising a transceiver and a power amplifier, in a wireless communication system, the method comprising:attenuating a power of a signal based on a gain compensation value corresponding to the power of the signal, if the power of the signal inputted to the transceiver coupled with the power amplifier is smaller than a reference value; and
transmitting the signal with the attenuated power to the power amplifier.

US Pat. No. 10,171,044

POWER AMPLIFICATION CIRCUIT

MURATA MANUFACTURING CO.,...

1. A power amplification circuit comprising:a first amplifier that is input with a first signal and outputs a second signal obtained by amplifying the first signal;
a bias circuit that supplies a bias current or a bias voltage to the first amplifier; and
a control voltage generating circuit that generates a control voltage in accordance with a signal level of the first signal,
wherein the bias circuit includes:
a first transistor, the bias current or bias voltage being output from an emitter or source of the first transistor,
a second transistor that is provided between the emitter or the source of the first transistor and ground; and
a third transistor, wherein the control voltage is supplied to a base or gate of the third transistor and an emitter or source of the third transistor supplies a first current or a first voltage to a base or gate of the second transistor,
wherein the control voltage generating circuit includes:
a second amplifier that is input with the first signal and outputs a third signal obtained by amplifying the first signal, and
a voltage outputting circuit that outputs the control voltage in accordance with the third signal, and
wherein the voltage outputting circuit includes:
a current-voltage converting circuit that outputs a second voltage in accordance with a current of the third signal, and
a voltage-level converting circuit that converts the second voltage into the control voltage such that the value of the first current or the first voltage is larger when the signal level of the first signal is the first level than when the signal level of the first signal is the second level.

US Pat. No. 10,171,043

AMPLIFICATION DEVICE INCORPORATING LIMITING

Telefonaktiebolaget LM Er...

1. An amplification device, comprising:an amplifier circuit comprising a signal input for an input signal to be amplified and a first signal output for a first output signal; and
a limiter, wherein the limiter comprises:
a differential amplifier comprising:
a first differential amplifier input for a threshold control signal;
a second differential amplifier input for a feedback signal; and
a differential amplifier output for a threshold signal indicative of a difference between the threshold control signal and the feedback signal;
a first diode having a first anode coupled to the first signal output and a first cathode coupled to the differential amplifier output; and
a feedback stage coupled between the differential amplifier output and the second differential amplifier input, wherein the feedback stage is configured to generate the feedback signal dependent on the threshold signal.

US Pat. No. 10,171,041

PREDISTORTION DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A device, comprising:an input terminal configured to receive an input signal;
a predistortion filter, connected between the input terminal and a non-linear power amplifier (PA), the predistortion filter having second filter weights;
a first delay element coupled to the input terminal, and configured to delay the input signal by a time delay D to provide a delayed input signal;
an adaptive filter having first filter weights, and configured to filter the delayed input signal; and
an adjuster configured to, according to an adaptive algorithm and the delayed input signal, adjust the first filter weights of the adaptive filter and the second filter weights of the predistortion filter so that the first filter weights are the same as the second filter weights,
wherein both the adaptive filter and the adjuster are coupled to the first delay element to receive the delayed input signal.

US Pat. No. 10,171,037

MULTI-MODE POWER MANAGEMENT SYSTEM SUPPORTING FIFTH-GENERATION NEW RADIO

Qorvo US, Inc., Greensbo...

1. A multi-mode power management system comprising:a power amplifier circuit configured to amplify a fifth-generation new radio (5G-NR) signal to an output power level for transmission in a 5G-NR band, the power amplifier circuit comprising:
a carrier amplifier configured to amplify the 5G-NR signal to a first power level in response to receiving a first bias voltage at a first bias voltage input; and
a peaking amplifier configured to amplify the 5G-NR signal to a second power level in response to receiving a second bias voltage at a second bias voltage input;
wherein a sum of the first power level and the second power level equals the output power level;
first tracker circuitry configured to generate a first voltage at a first voltage output;
second tracker circuitry configured to generate a second voltage at a second voltage output; and
control circuitry configured to:
couple the first voltage output to the first bias voltage input and the second bias voltage input in a 5G-NR low power mode; and
couple the first voltage output and the second voltage output to the first bias voltage input and the second bias voltage input, respectively, in a 5G-NR high power mode.

US Pat. No. 10,171,036

POWER AMPLIFICATION CIRCUIT

MURATA MANUFACTURING CO.,...

1. A power amplification circuit comprising:an amplifier that amplifies an input signal and outputs an amplified signal;
a first bias circuit that supplies a first bias current or voltage to the amplifier;
a second bias circuit that supplies a second bias current or voltage to the amplifier;
a first control circuit that outputs a first current that controls a level of the first bias current or voltage; and
a second control circuit that outputs a second current that controls a level of the second bias current or voltage;
wherein a current supplying capacity of the first bias circuit is different from a current supplying capacity of the second bias circuit,
wherein the first bias circuit comprises a first transistor that outputs the first bias current or voltage in accordance with the first current,
wherein the second bias circuit comprises a second transistor that outputs the second bias current or voltage in accordance with the second current, and comprises a fourth transistor, wherein a collector of the fourth transistor is connected to a base or gate of the second transistor, a base of the fourth transistor is connected to an emitter or source of the second transistor, an emitter of the fourth transistor is connected to ground, and the second current is supplied to the collector of the fourth transistor, and
wherein a size of the first transistor is different from a size of the second transistor.

US Pat. No. 10,171,034

PHASE-ROTATED HARMONIC-REJECTION MIXER APPARATUS

MEDIATEK INC., Hsin-Chu ...

8. A harmonic-rejection mixer apparatus comprising:a mixing circuit, configured to receive a first input signal, a second input signal, and a local oscillator (LO) signal, and further configured to mix the first input signal and the LO signal to generate a first output signal and mix the second input signal and the LO signal to generate a second output signal, wherein the first input signal and the second input signal have a same peak amplitude but different phases; and
a combining circuit, configured to combine the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

US Pat. No. 10,171,026

STRUCTURAL ATTACHMENT SEALING SYSTEM

Solsera, Inc., Phoenix, ...

1. A method of securing structural attachments comprising the steps of:a. placing a mount on a structure, the mount comprising:
i. a base that conforms to the shape of the surface of the structure, the base comprising an internal cavity further comprising at least one concave section wherein the at least one concave section forms an external cavity, the external cavity further comprising a base;
ii. a port hole coupled to the internal cavity that is accessible from an outer surface of the mount;
iii. a vent coupled to the internal cavity that is accessible from the outer surface of the mount;
iv. a bolt for securing the mount to the structure, the bolt further comprising a head, and a shaft extending from the head;
v. an opening through the external cavity of the at least one concave section, the opening configured to receive the bolt; and
vi. a generally U-shaped guide comprising a pair of vertical members, the vertical members extending from the at least one concave section forming an aperture that is configured to secure a solar panel mounting rail guide to the mount wherein each vertical member further comprising a front side and a rear side;
b. inserting the shaft of the bolt through the opening and through the volume of the internal cavity so that the head resides on the base of the external cavity thereby securing the mount to the structure; and
c. injecting a liquid into the port hole of the mount until the liquid fills the volume of the internal cavity.

US Pat. No. 10,171,003

CONTROLLING A SWITCHING RESONANT CONVERTER

STMICROELECTRONICS S.R.L....

1. A system, comprising:a converter including a transformer having a primary winding in a primary side of the transformer and a secondary winding in a secondary side of the transformer, the converter including a resonant tank in the primary side; and
a controller including:
a capacitance configured to be charged simultaneously using a first current and a second current that is different than the first current or discharged simultaneously using the first current and the second current;
sourcing and sinking transistors configured to source or sink the first current for charging or discharging the capacitance;
an operational transconductance amplifier configured to determine a level of the second current based on a level of current flowing through the resonant tank, and source or sink the second current for charging or discharging the capacitance; and
logic configured to output a switching signal for operating the converter based on a voltage across the capacitance.

US Pat. No. 10,170,990

METHODS AND APPARATUS FOR A SINGLE INDUCTOR MULTIPLE OUTPUT (SIMO) DC-DC CONVERTER CIRCUIT

University of Virginia Pa...

1. A method, comprising:receiving information related to one or more of a processing power demand and an available energy level of an integrated circuit (IC) that includes a single-inductor multiple-output (SIMO) direct current-direct current (DC-DC) converter circuit and a panoptic dynamic voltage scaling (PDVS) circuit operatively coupled to the SIMO DC-DC converter circuit,
the SIMO DC-DC converter circuit having a plurality of output nodes, each output node from the plurality of output nodes being uniquely associated with a supply voltage rail from a plurality of supply voltage rails, and
the PDVS circuit having a plurality of operational blocks; and
operating the PDVS circuit such that each operational block from the plurality of operational blocks draws power from one supply voltage rail from the plurality of supply voltage rails.

US Pat. No. 10,170,979

POINT OF LOAD REGULATOR SYNCHRONIZATION AND PHASE OFFSET

International Business Ma...

1. An electronic system including at least three point of load (POL) regulators that supply a regulated voltage to a component within the electronic system, the electronic system comprising:a master POL regulator that operates under a reference phase and communicates a first SYNC OUT signal that is offset from the reference phase by a first phase offset to a first controlled POL regulator and communicates a second SYNC OUT signal that is offset from the reference phase by a second phase offset to a second controlled POL regulator.

US Pat. No. 10,170,978

SIGNAL TRANSMISSION CIRCUIT

DENSO CORPORATION, Kariy...

1. A signal transmission circuit comprising a transmission apparatus and a reception apparatus which are insulated from each other and between which a signal indicative of predetermined information is transmitted via an insulation element,wherein the transmission apparatus includes a first transmission unit transmitting a first signal indicative of first information based on the number of pulses consecutively outputted with a predetermined period and each having a first waveform with a duty cycle of less than 100% with respect to the period and a second transmission unit transmitting a second signal indicative of second information based on a pulse having a longer wavelength than the first waveform,
wherein the first transmission unit transmitting the first signal to the reception apparatus and the second transmission unit transmitting the second signal to the reception apparatus, via the insulation element common to the first transmission unit and the second transmission unit, and
wherein the second transmission unit transmits the second signal in synchrony with the pulse having the first waveform, and transmits the second signal indicative of the second information using a pulse having a wavelength which is longer than the first waveform and which is shorter than a period during which the pulse having the first waveform is consecutively outputted.

US Pat. No. 10,170,955

PULL TIGHT MOTOR HOUSING

1. A motor comprises:a motor assembly that includes a stator, a rotor, and wiring connected to the stator;
an end-cap coupled to the motor assembly to produce first sub-assembly, wherein the end-cap includes an electrical fitting for feeding the wiring externally of the motor;
a flexible insulating sleeve fitted over at a least a portion the first sub-assembly to produce a second sub-assembly; and
a flexible enclosure including a formed housing section and a connecting section, wherein the formed housing section loosely fits over the second sub-assembly prior to tightening of the connecting section and, when the connecting section is tightened, the formed housing section tightly fits over the second sub-assembly compressing the flexible insulating sleeve to produce an insulating seal.

US Pat. No. 10,170,954

DIRECT CURRENT MOTOR

Hitachi Automotive System...

1. A direct-current motor including an armature including a plurality of armature slots and an armature coil wound to stride over two of the armature slots away from each other with a certain number of the armature slots interposed therebetween, the direct-current motor comprising:at least four armature coils each wound on a lowermost layer of a coil end portion without overlapping with the armature coil wound through the different armature slots,
wherein, on a higher layer than the four armature coils wound on the lowermost layer, at least four armature coils wound in an equal pattern to that of the four armature coils are provided
wherein the four armature coils wound on the lowermost layer have coil sides thereof adjacent to each other housed in the respective equal armature slots, and the four armature coils wound on the higher layer than the lowermost layer have coil sides thereof adjacent to each other housed in the respective equal armature slots,
wherein the armature coils constitute a plurality of coil groups each including coils which get an equal number to the number of pole pairs P, each of the coil groups being wound by one continuous winding conductor, and a coil group including (P?1) coils,
wherein a part between two coils wound by one continuous winding conductor is retained in a conductor retaining portion of a commutator segment in a state in which the two coils are continuous, and
wherein each end portion of each of the coil groups is cut in a state of being retained in a conductor retaining portion of a different commutator segment from the commutator segment.

US Pat. No. 10,170,909

CONVERTER AND PHOTOVOLTAIC GENERATION SYSTEMS WITH CONVERTER

TAIYO YUDEN CO., LTD., T...

1. A converter for use in a distributed power system for stepping up or down a voltage of a power source connected thereto, the converter being a local converter directly attached to the power source, the converter comprising:a step up/down circuit that directly receives said voltage, steps up or steps down said voltage from the power source, and then outputs said stepped up/down voltage;
a control circuit directly connected to the step up/down circuit to direct said voltage from the power source and transmits a control signal for stepping up or stepping down said voltage to said step up/down circuit; and
a frontend circuit that communicates with another converter attached to another power source in the distributed power system when said another power source with said another converter is connected to the distributed power system,
wherein said control circuit generates an identification signal that identifies said converter and transmits said identification signal through the frontend circuit, and said control circuit is configured to receive an identification signal from said another converter through the frontend circuit without going through a central control system when said another power source with said another converter is connected to the distributed power system so as to detect the presence of said another converter without using the central control system.

US Pat. No. 10,170,908

PORTABLE DEVICE CONTROL AND MANAGEMENT

INTERNATIONAL BUSINESS MA...

1. An apparatus for managing and distributing battery power charge, comprising:multiple electronic devices each having at least one electronic device battery in need of charging;
a computing device having a computing device battery;
a signal receiving component within said computing device comprises multiple ports such that:
the signal receiving component receives at least input battery signal data from the multiple electronic devices, and
the signal receiving component transfers an allocated amount of battery power to each of the multiple electronic devices,
the input battery signal data including battery power level data of each electronic device battery in need of charging;
a monitoring component within said computing device continuously monitoring and receiving the input battery signal data from the signal receiving component;
a controller within said computing device receiving and analyzing the input battery signal data to determine, based on the battery power level data, the allocated amount of battery power charge required for charging each said electronic device battery to a desired battery charge level; and
a charge distribution unit within the computing device receiving each allocated amount of battery power charge, the computing device via the charge distribution unit transferring each allocated amount of battery power charge from the computing device battery to each electronic device battery of the multiple electronic devices to continuously maintain and ensure battery power is available on each electronic device at a time when needed.

US Pat. No. 10,170,898

SIGNAL LEAKAGE PROOF HOUSING FOR SIGNAL DISTRIBUTORS

Signal Cable System Co., ...

1. A signal leakage proof housing for signal distributors, comprising:a metal case, comprising:
a plurality of signal connection terminals;
a circumferential side wall, comprising:
a top surface, comprising:
a plurality of fixing protrusions arranged at intervals on and around the top surface;
at least one rib on and around the top surface; and
a metal cover plate comprising:
a bottom surface, comprising;
a plurality of fixing holes on and around the bottom surface; wherein,
when the metal case and the metal cover plate are assembled together, the plurality of fixing protrusions each respectively pass through the corresponding fixing holes and fix with each other; wherein,
each one of the at least one rib is in direct contact with the bottom surface of the metal cover plate.

US Pat. No. 10,170,894

MULTIPOINT IGNITION DEVICE AND MULTIPOINT IGNITION ENGINE

Miyama, Inc., Nagano-shi...

1. A multipoint ignition device for igniting an air-fuel mixture in a combustion chamber of an engine, comprising:an insulating member formed in an annular shape such that an inner periphery thereof faces the combustion chamber; and
a plurality of electrodes held on the insulating member so as to form a plurality of ignition gaps in a circumferential direction inside the combustion chamber,
wherein the insulating member includes a plurality of divided insulating members formed in divided form, and
the divided insulating member close to an intake valve of the engine has a higher thermal conductivity than the divided insulating member close to an exhaust valve of the engine.

US Pat. No. 10,170,886

RGB LASER SOURCE FOR LUMINAIRE PROJECTOR SYSTEM

IPG PHOTONICS CORPORATION...

1. A Red Green Blue (RGB) laser light source for luminaire projector system, comprising at least a first channel configured with:a randomly polarized (RP) broadband (BB) single mode (SM) Green laser including
a master oscillator power fiber amplifier (MOPFA) pump which is operative to output a pulsed RP BB SM pump beam at a fundamental wavelength in a 1 ?m wavelength range, and
a second harmonic generator (SHG) which is configured with a lithium triborate (LBO) nonlinear crystal receiving the SM BB pulsed pump beam and outputting a train of pulses of BB Green light in a 5xx nm wavelength range, a broad spectral linewidth ??1 of at least 4 nm;
an RP BB SM Red laser configured with respective quasi continuous wave (QCW) fiber laser pump which is operative to output a RP SM BB pulsed pump beam at a central wavelength, and a frequency converter with an LBO nonlinear crystal receiving the RP SM BB pulsed pump beam so as to output a train of pulses of red light in a 6xx nm wavelength range with a broad spectral line ??2 of at least 4 nm; and
a blue-light laser outputting RP Blue light at a central wavelength in a 4xx nm wavelength range with a broad spectral linewidth ??3 of at least 4 nm.

US Pat. No. 10,170,866

SHIELDED ELECTRIC CONNECTOR

1. A shielded electrical connector, comprising:a first connector having a first end and having a second end;
a center conductor extending axially through said first connector from a first side of said center conductor at or adjacent said first end of said first connector to a second side of said center conductor in an engagement with one end of a cable running axially through said first connector and exiting at said second end thereof;
said first connector slidably positionable to an inserted position where said first end of said first connector is located within a axial cavity of a second connector, to thereby operatively connect said center conductor with an electric charged contact communicating into said axial cavity of said second connector;
an annular ring having an exterior surface and having a passage running therethrough from a first end to a second end thereof;
said engagement of said second side of said center conductor to said cable and a portion of said cable adjacent said engagement to said center conductor, being positioned within said passage which is surrounded by said annular ring;
a first portion of dielectric insulating material positioned in-between said annular ring and said engagement of said second side of said center conductor to said cable and said portion of said cable adjacent said engagement to said center conductor;
a second portion of dielectric insulating material surrounding said exterior surface of said annular ring;
an annular projecting ring extending from said first end of said annular ring, a surface of said annular projecting ring extending from said second portion of said dielectric insulating material; and
said annular projecting ring positionable to a contact with a grounded mating connecter located in said axial cavity by positioning said first connector to said inserted position, whereby said annular ring forms a shield preventing RF or EMF from exiting said axial cavity.

US Pat. No. 10,170,862

ELECTRICAL DEVICE HAVING A GROUND BUS TERMINATED TO A CABLE DRAIN WIRE

TE CONNECTIVITY CORPORATI...

1. An electrical device comprising:a circuit board having upper signal contacts and at least one upper ground contact along an upper surface of the circuit board;
a communication cable including a differential pair of signal conductors, a shield layer that surrounds the signal conductors, a drain wire electrically coupled with the shield layer, and a cable jacket that surrounds the shield layer and the drain wire; wherein each of the signal conductors has a wire-terminating end that is engaged to a corresponding upper signal contact of the circuit board, the wire-terminating ends projecting beyond a jacket edge of the cable jacket; and
an upper ground-terminating component electrically coupled to the at least one upper ground contact, the upper ground-terminating component having a main panel with a connective terminal electrically coupled to the drain wire, the connective terminal including an opening and a pair of opposed angled tabs, wherein each of the opposed angled tabs includes a base end and a free end, the free end of each of the opposed angled tabs extending into the opening and away from the main panel.

US Pat. No. 10,170,854

HOLDING FRAME FOR PLUG CONNECTOR MODULES HAVING A LEAF-SPRING-TYPE FASTENING MEANS

1. A holding frame into which plug connector modules can be inserted, wherein the holding frame comprises:two halves which can be connected to one another in a jointed manner, a first half and a second half; and
at least one locking element formed from a flat component which covers both halves at least in some regions, the locking element having at least one latching hook at an end thereof, and
wherein one half of the holding frame has at least one cut-out in which the latching hook of the locking element can engage, whereby the holding frame can be secured in an open position.

US Pat. No. 10,170,844

METHOD FOR DISH REFLECTOR ILLUMINATION VIA SUB-REFLECTOR ASSEMBLY WITH DIELECTRIC RADIATOR PORTION

CommScope Technologies LL...

1. An apparatus comprising:a unitary dielectric block having a waveguide transition portion located at a first end of the unitary dielectric block, a sub-reflector support portion located at a second end of the unitary dielectric block that is opposite from the first end, and a radiator portion between the waveguide transition portion and the sub-reflector support portion;
a waveguide coupled to a dish reflector of a reflector antenna and aligned with a longitudinal axis of the unitary dielectric block;
wherein the waveguide transition portion is dimensioned to couple to a distal end of the waveguide,
wherein the waveguide transition portion has a first portion with a first diameter and a second portion located nearer to the radiator portion than the first portion and having a second diameter greater than the first diameter, and
wherein the waveguide transition portion comprises a shoulder perpendicular to the longitudinal axis and having a third diameter that is greater than the first and second diameters.

US Pat. No. 10,170,819

RFID ANTENNA STRUCTURE

AAC ACOUSTIC TECHNOLOGIES...

1. A RFID antenna structure, including:a metal back cover;
a circuit board located below the metal back cover, the circuit board including a base plate and a ground plate overlaid on the base plate;
a RFID chip mounted on the base plate;
match circuits connected electrically with the RFID chip and located on the base plate;
an antenna coil connected electrically with the match circuits and located between the circuit board and the metal back cover; wherein
the metal back cover includes a top cover and a middle cover separated from the top cover by a slit, the antenna coil is located at least partly inside an area of the top cover, and the antenna coil is connected inductively with the top cover and/or the middle cover.

US Pat. No. 10,170,776

FUEL CELL MODULE

HONDA MOTOR CO., LTD., T...

1. A fuel cell module comprising:a fuel cell stack including a plurality of fuel cells stacked in a vertical direction configured to generate electrical energy by electrochemical reactions of a fuel gas and an oxygen-containing gas;
a combustor provided at a lower end of the fuel cell stack, and configured to produce a combustion gas so as to heat the fuel cell stack;
a channel member connected to the combustor, extending upward along the stacking direction of the fuel cell stack, and facing a side surface of the fuel cell stack, the side surface being perpendicular to the stacking direction;
wherein the channel member includes a combustion gas channel configured to allow the combustion gas produced in the combustor to flow upward along the stacking direction of the fuel cell stack; and
a combustion gas ejection hole that is connected to the combustion gas channel, opens toward a direction perpendicular to the stacking direction of the fuel cell stack, and is configured to release, toward the side surface of the fuel cell stack, part of the combustion gas that touches the side surface of the fuel cell stack.

US Pat. No. 10,170,768

GRID ASSEMBLY FOR A PLATE-SHAPED BATTERY ELECTRODE OF AN ELECTROCHEMICAL ACCUMULATOR BATTERY

1. A grid arrangement (101, 102) for a plate-shaped battery electrode (104, 105) of an electrochemical accumulator (100), having a frame (117, 118, 119, 120) and a grid (113) arranged thereon, wherein the frame (117, 118, 119, 120) comprises at least one upper frame element (120) having a connecting lug (103) of the battery electrode (104, 105) disposed on its side facing away from the grid (113), and wherein the grid (113) is at least formed by horizontal bars (21 to 25), which are bars extending substantially horizontally, and vertical bars (9 to 20), which are bars extending substantially vertically, wherein at least some of the vertical bars (9 to 20) are arranged at different angles to one another in the shape of a fan, characterized by at least features a), c) and d) or all of the following features a), b), c), and d):a) a straight line (G), which runs through the center of gravity of the grid arrangement (101, 102) and is a parallel to the central axis (M) of the vertical bar (14) having the shortest distance to the center of gravity (S) of the grid arrangement (101, 102), passes the connecting lug (103) at a distance (D) of less than 15%, in particular less than 10%, of the connecting lug width (B), or intersects the connecting lug (103),
b) a straight line (G) which runs through the center of gravity of the grid arrangement (101, 102) and is a parallel to the central axis (M) of the vertical bar (14) having the shortest distance to the center of, gravity (S) of the grid arrangement (101, 102), intersecting the upper frame element (120) at a point (1) which is less than 15%, particularly less than 10%, of the length (L) of the upper frame element (120) away from a vertical central axis (A) of the connecting lug (103),
c) the sum of all the angles of those vertical bars (9 to 20) which intersect both the upper as well as a lower frame element (120, 117) of the grid arrangement (101, 102), or at least would intersect in mathematical extension, is greater than 7°, wherein the angles are defined in terms of an axis (A) extending exactly vertically,
d) the sum of the angles of the outermost left and outermost right vertical bar (10, 20) intersecting both the upper as well as the lower frame element (120, 117) of the grid arrangement (101, 102), or at least would intersect in mathematical extension, is greater than 7°, wherein the angles are defined in terms of an axis (A) extending exactly vertically.

US Pat. No. 10,170,741

EXPANDABLE BATTERY MODULE

EMATRIX ENERGY SYSTEMS, I...

20. A battery module comprising:a first battery brick and a second battery brick;
wherein both the first battery brick and the second battery brick comprise:
at least one battery cell;
a connecting layer configured to connect layers of battery cells, comprising:
at least one spacer, and
at least one busbar having a top side and a bottom side, wherein a first spacer is located above said top side and a second spacer is located below said bottom side;
a mechanical mating member having a plurality of flow passages;
a top cover having a primary flow channel fluidly connected to a plurality of secondary flow channels, and a bottom cover having primary flow channel fluidly connected to a plurality of secondary flow channels, wherein said top cover and bottom cover are configured to be mechanically interlocked to the battery module;
an electrical mating member having a plurality of flow passages; and
an external enclosure, wherein the external enclosure of the first battery brick is configured to interface with the external enclosure of the second battery brick;
wherein the flow passages of the mechanical mating member, the flow passages of the electrical mating member, and the flow passages of the top cover and bottom cover are fluidly connected; and
wherein the secondary channels of the top cover and bottom cover are configured to provide equal pressure though the plurality of flow passages of the battery module.

US Pat. No. 10,170,725

LAMINATED STRUCTURE, DISPLAY DEVICE AND DISPLAY UNIT EMPLOYING SAME

Sony Corporation, Tokyo ...

1. A manufacturing method of an organic light emitting device, comprising:providing a substrate;
forming an anode including, stacked in this order:
a first anode layer comprising a metal compound or a conductive oxide,
a second anode layer that is a reflective layer, and
a third anode layer comprising a metal compound or a conductive oxide;
forming an insulating film so as to cover the anode;
patterning the insulating film so as to partially expose the anode;
forming an organic layer over the exposed portion of the anode and the insulating film, the organic layer comprising a light-emitting layer; and
forming a cathode on the organic layer,
wherein the organic light emitting device is configured to generate light in the light-emitting layer, and the light is extracted through the cathode,
wherein a thickness of the third anode layer is between about 3-15 nm, and
wherein the patterning the laminated structure includes making a side surface of the second anode layer a convex shape when viewed as a cross-section in the laminated direction of the anode.

US Pat. No. 10,170,688

MAGNETIC FIELD SENSOR BASED ON TOPOLOGICAL INSULATOR AND INSULATING COUPLER MATERIALS

INTERNATIONAL BUSINESS MA...

1. A method of forming a sensor, the method comprising:forming a first electrode region;
forming a second electrode region;
forming a detector region;
electrically coupling the detector region to the first electrode and the second electrode;
forming the detector region to include a first layer comprising a topological insulator;
the topological insulator having an insulating region in a body of the topological insulator;
the topological insulator further having a conducing path along a surface of the topological insulator, wherein a steady state condition of the topological insulator comprises the insulation region acting as an insulator and the conducting path along the surface of the topological insulator acting as a current conductor; and
forming the detector region to further include a second layer comprising a first insulating magnetic coupler;
wherein the detector region comprises a third layer comprising a second insulating magnetic coupler;
wherein a magnetic field applied to the detector region is sufficient to change the steady state condition of the topological insulator by developing energy gaps in the conducting path along the surface of the topological insulator that are sufficient to change a resistance of the conducting path.

US Pat. No. 10,170,681

LASER ANNEALING OF QUBITS WITH STRUCTURED ILLUMINATION

International Business Ma...

1. A method for forming a qubit, the method comprising:forming a Josephson junction between two capacitive plates; and
annealing the Josephson junction with a thermal source, wherein the thermal source is a laser that generates a Gaussian beam, wherein an axicon lens is exposed to the Gaussian beam, and wherein annealing the Josephson junction alters a resistance of the Josephson junction.

US Pat. No. 10,170,680

QUBITS BY SELECTIVE LASER-MODULATED DEPOSITION

INTERNATIONAL BUSINESS MA...

17. A qubit device, comprising:a Josephson junction; and
a shunt capacitor coupled to the Josephson junction, the shunt capacitor including a shape modified, post-production, to adjust a qubit characteristic for the qubit device.

US Pat. No. 10,170,672

OPTICAL ELEMENT AND OPTOELECTRONIC COMPONENT

OSRAM Opto Semiconductors...

1. An optical element comprising a first surface and a second surface opposite the first surface,wherein the first surface is subdivided into two or more segments,
each segment adjoins a midpoint of the first surface,
each segment has a tooth structure forming a total internal reflection lens and having projections extending along tooth extension directions, and
the tooth extension directions have bends at boundaries between the segments,
wherein the projections contained in the tooth structures of two adjacent segments continue continuously at the boundary between the segments,
the optical element comprises a frame enclosing the first surface, and
the frame defines a cavity, the bottom of the cavity formed by a base section of the optical element.

US Pat. No. 10,170,669

LIGHT EMITTING DEVICE AND METHOD OF PRODUCING THE SAME

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a resin package comprising:
a plurality of leads that includes:
a first lead having an upper surface, and
a second lead having an upper surface, and
a resin body that includes:
a first resin portion having at least one inner lateral wall surface,
a second resin portion,
a third resin portion disposed between the first lead and the second lead and having an upper surface, and
a resin connection portion,
the plurality of leads and the at least one inner lateral wall surface of the first resin portion defining a recess,
the upper surface of the first lead, the upper surface of the second lead and the upper surface of the third resin portion located at a bottom of the recess,
at the bottom of the recess, the second resin portion being in contact with a portion of the upper surface of the third resin portion and surrounding an element mounting region, and
the resin connection portion connecting the first resin portion and the second resin portion at the bottom of the recess;
at least one light emitting element disposed on the element mounting region at the bottom of the recess of the resin package; and
a light-reflective member disposed between the inner lateral wall surface and the second resin portion in the recess.

US Pat. No. 10,170,660

DIGITAL ALLOY GERMANIUM HETEROJUNCTION SOLAR CELL

International Business Ma...

1. A photovoltaic device, comprising:a digital alloy buffer layer including a plurality of alternating layers of semiconductor material, wherein the digital alloy buffer layer includes a mass variance adjusted by isotropic enrichment in the digital alloy buffer layer to increase thermal conductivity of the digital alloy buffer layer;
an absorption layer epitaxially grown directly on the digital alloy buffer layer;
an intrinsic layer formed on the absorption layer;
a doped layer formed on the intrinsic layer; and
a metal contact formed on the doped layer.

US Pat. No. 10,170,659

MONOLITHICALLY INTEGRATED THIN-FILM ELECTRONIC CONVERSION UNIT FOR LATERAL MULTIJUNCTION THIN-FILM SOLAR CELLS

International Business Ma...

1. An integrated thin-film lateral multi junction solar device, comprising:a substrate;
a plurality of stacks extending vertically from the substrate, each stack comprising layers, wherein each stack is electrically isolated against another stack, each stack comprising:
an energy storage device above the substrate;
a solar cell above the energy storage device,
a transparent medium above the solar cell, and
a micro-optic layer of spectrally dispersive and concentrating optical devices above the transparent medium, wherein the micro-optic layer is a combination of refractive and/or diffractive optical elements;
a first power converter connected between the energy storage device and a power bus; and
a second power converter connected between the solar cell and the power bus,
wherein different solar cells of different stacks have different absorption characteristics, and
wherein the different absorption characteristics of the different solar cells are based on different energy band-gaps of semiconductors building the solar cell.

US Pat. No. 10,170,655

ENERGY HARVESTING DEVICE WITH PREFABRICATED THIN FILM ENERGY ABSORPTION SHEETS AND ROLL-TO-SHEET AND ROLL-TO-ROLL FABRICATION THEREOF

International Business Ma...

1. A roll-to-sheet method for fabricating energy harvesting devices comprising:unrolling a plurality of prefabricated thin film energy absorption sheets from a plurality of corresponding rolls of the prefabricated thin film energy absorption sheets into which the prefabricated thin film energy absorption sheets have been wound;
laminating the prefabricated thin film energy absorption sheets together after unrolling, resulting in more than one of the prefabricated thin film energy absorption sheets being laminated together;
after lamination, drilling a plurality of vias through the prefabricated thin film energy absorption sheets that have been laminated together;
filling the vias with a conductive material; and
dividing the thin film sheets into the energy harvesting devices after drilling and filling the vias,
wherein the prefabricated thin film energy absorption sheets absorb electromagnetic energy.

US Pat. No. 10,170,648

SEMICONDUCTOR NANOCRYSTAL, AND METHOD OF PREPARING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A nanocrystal comprising:a core consisting of a Group III element, P, and a Group II element; and
a shell overcoating the core and comprising ZnSeS multi-layers consisting of Zn, Se, and S, wherein a single monolayer directly disposed on a surface of the core in the shell comprises a compound of the formula ZnSexS(1-x),
wherein an average ratio of x:(1?x) in the single monolayer ranges from about 5:1 to about 20:1,
wherein the shell further comprises at least two additional single monolayers each comprising a compound of the formula ZnSeyS(1-y), wherein 0 wherein the at least two additional single monolayers have a Se:S concentration ratio gradient between the at least two additional single monolayers,
wherein the Se:S concentration ratio gradient comprises an increasing concentration of Se and a decreasing concentration of S in a direction from the core to a predetermined single monolayer; and a decreasing concentration of Se and an increasing concentration of S in a direction from the predetermined single monolayer to an outermost single monolayer, wherein the predetermined single monolayer is located between the single monolayer directly disposed on the surface of the core and the outermost single monolayer, and
wherein the nanocrystal has a luminous efficiency “QY” of greater than 70 percent.

US Pat. No. 10,170,636

GATE-TO-BULK SUBSTRATE ISOLATION IN GATE-ALL-AROUND DEVICES

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a fin including a first semiconductor material on a substrate, wherein the first semiconductor material includes silicon germanium having a first concentration of germanium in the silicon germanium;
a nanowire over the fin, the nanowire including a second semiconductor material, wherein the second semiconductor material includes silicon germanium having a second concentration of germanium in the silicon germanium; and
wherein the first concentration is at least 10% less than the second concentration;
a first layer of oxide material on exposed portions of the nanowire and a second layer of oxide material on the fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness; and
a gate stack over a channel region of the nanowire, the gate stack including a gate dielectric layer on the nanowire and directly on the second layer of oxide material, a workfunction metal on the gate dielectric layer, and a gate conductor on the workfunction metal.

US Pat. No. 10,170,622

SEMICONDUCTOR DEVICE INCLUDING MOS TRANSISTOR HAVING SILICIDED SOURCE/DRAIN REGION AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit structure comprising:a semiconductor substrate;
a gate structure over the semiconductor substrate;
a spacer on a sidewall of the gate structure;
a silicon germanium region including a first silicon germanium region and a second silicon germanium region;
the first silicon germanium region being located in the substrate, and the first silicon germanium region having a first germanium percentage,
the second silicon germanium region lying over the first silicon germanium region, and the second silicon germanium region having a second germanium percentage higher than the first germanium percentage; and
a metal silicide region over the second silicon germanium region,
wherein the spacer has a side surface and bottom surface extending from a lower end of the side surface, the bottom surface of the spacer facing the substrate,
the silicon germanium region has an inclined surface,
one part of the inclined surface of the silicon germanium region intersects the side surface of the spacer at a level above the lower end of the side surface, and
another part of the inclined surface of the silicon germanium region intersects the bottom surface of the spacer at a second location spaced from the lower end of the side surface of the spacer in a direction towards the gate structure, such that the silicon germanium region contacts the spacer along both the side surface and the bottom surface of the spacer.

US Pat. No. 10,170,598

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:forming an oxynitride semiconductor layer over an oxide insulating layer formed over an insulating surface;
forming a gate insulating layer over the oxynitride semiconductor layer; and
forming a gate electrode over the gate insulating layer,
wherein the oxynitride semiconductor layer includes a channel region, a source region, and a drain region,
wherein an amount of oxygen released by the oxide insulating layer in thermal desorption spectroscopy is greater than or equal to 1.0×1020 atoms/cm3, and
wherein the oxynitride semiconductor layer is an n-type semiconductor layer.

US Pat. No. 10,170,596

FABRICATION OF AN ISOLATED DUMMY FIN BETWEEN ACTIVE VERTICAL FINS WITH TIGHT FIN PITCH

International Business Ma...

1. An arrangement of active and inactive fins on a substrate, comprising:a substrate;
a pair of vertical fins on the substrate;
an inactive vertical fin on the substrate between the pair of vertical fins, wherein the inactive vertical fin includes a lower portion made of a semiconductor material and an upper portion made of an insulating material;
a protective liner on a lower portion of each of the pair of vertical fins and the lower portion of the inactive vertical fin; and
a filler layer on the protective liner and the substrate, wherein a top surface of the filler layer is above the protective liner and the lower portion of the inactive vertical fin made of the semiconductor material.

US Pat. No. 10,170,587

HETEROGENEOUS SOURCE DRAIN REGION AND EXTENSION REGION

International Business Ma...

1. A semiconductor device fabrication process comprising:forming a sacrificial portion upon a substrate;
forming a sacrificial gate stack upon the sacrificial portion;
forming a sacrificial gate spacer upon the sacrificial portion against the sacrificial gate;
forming a source drain region of a first doped material upon the substrate against the gate spacer;
removing the sacrificial gate stack forming a replacement gate trench;
forming an extension trench between the sacrificial gate spacer and the substrate by removing the sacrificial portion accessible via the replacement gate trench;
forming an extension region of a second doped material that has a higher mobility relative to the first doped material within the extension trench against the sacrificial gate spacer and against the substrate;
removing the sacrificial gate spacer; and
forming a replacement gate spacer upon the extension region.

US Pat. No. 10,170,586

UNIPOLAR SPACER FORMATION FOR FINFETS

International Business Ma...

1. A method for forming a spacer for a semiconductor device, comprising:depositing a dummy spacer layer over surfaces of gate structures and fins, the gate structures being transversely orientated relative to the fins;
planarizing a dielectric fill formed over the gate structures and the fins to remove a portion of the dummy spacer layer formed on tops of the gate structures and expose the dummy spacer layer at tops of sidewalls of the gate structures;
forming channels by removing the dummy spacer layer along the sidewalls of the gate structures, the fins being protected by the dielectric fill;
forming a spacer by filling the channels with a spacer material; and
removing the dielectric fill and the dummy spacer layer to expose the tins.

US Pat. No. 10,170,584

NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS

International Business Ma...

1. A method of forming a nanosheet device, comprising:forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer;
forming a stack cover layer on at least a portion of the channel stack, wherein the stack cover layer is formed on at least a portion of exposed sides of the at least one nanosheet channel layer and the at least one sacrificial release layer;
forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate;
removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib; and
forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

US Pat. No. 10,170,576

STABLE WORK FUNCTION FOR NARROW-PITCH DEVICES

International Business Ma...

1. A method for forming a gate structure for a field effect transistor, comprising:forming a gate dielectric layer over and between a plurality of fins;
depositing a single diffusion prevention layer on the gate dielectric layer over and between the plurality of fins; and
depositing an oxygen affinity layer on the diffusion prevention layer by pinching off portions of the oxygen affinity layer within the diffusion prevention layer to merge the portions without intervening layers between the portions.

US Pat. No. 10,170,571

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a composite gate structure formed over a semiconductor substrate, wherein the composite gate structure comprises:
a gate dielectric layer;
a metal layer disposed on the gate dielectric layer; and
a semiconductor layer disposed on the gate dielectric layer, wherein the metal layer and the semiconductor layer are stacked on the gate dielectric layer side by side.

US Pat. No. 10,170,570

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction, and stacked one over the other with an insulating layer disposed between each adjacent electrode;
the plurality of electrodes including a first side, and a second side, each extending in the second direction and spaced from each other in the first direction;
a plurality of protrusion portions extending from the first side of at least two of the electrodes, the protrusion portions spaced from one another in the second direction;
an extraction portion extending from the second side of the electrode on the at least two electrodes having protrusion portions extending from the first side thereof; and
first and second contact plugs extending in a third direction, orthogonal to the first and second directions, one of each contacting the extraction portions connected to one of the two electrodes having protrusion portions extending from the first side thereof,
wherein the extraction portion extending from the uppermost of the two electrodes having protrusion portions extending from the first side thereof is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the two electrodes having protrusion portions extending from the first side thereof.

US Pat. No. 10,170,569

THIN FILM TRANSISTOR FABRICATION UTLIZING AN INTERFACE LAYER ON A METAL ELECTRODE LAYER

APPLIED MATERIALS, INC., ...

1. A thin film transistor structure, comprising:a metal electrode layer disposed on a barrier layer formed above a gate insulating material;
an interface layer disposed on and in direct contact with the metal electrode layer, wherein the interface layer is an oxygen free dielectric material sized to be formed on and to have the same width as the metal electrode layer; and
an inorganic insulating material layer disposed on and in direct contact with the interface layer, wherein the inorganic insulating material layer is an oxygen containing dielectric layer.

US Pat. No. 10,170,558

LOCALIZED AND SELF-ALIGNED PUNCH THROUGH STOPPER DOPING FOR FINFET

International Business Ma...

1. A method for doping punch through stoppers (PTSs), comprising:recessing a dielectric layer to form gaps between a top portion of the dielectric layer and a spacer formed on sidewalls of fins to expose the fins in the gaps; and
doping the fins through the gaps to form PTSs in the fins, wherein a doped region extends from a bottom surface of the PTSs into a substrate, wherein each fin is formed of a material compound that is different from the substrate.

US Pat. No. 10,170,556

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device manufacturing method, comprising:preparing a semiconductor substrate of a first conductivity type;
forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate;
forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate;
forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction;
covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film;
after the covering the side wall of each of the first ditches, forming gate electrodes inside the first ditches and the second ditches;
forming a first semiconductor region of a second conductivity type different from the first conductivity type over a side wall of each of the first ditches; and
forming a source region of the first conductivity type in an upper surface portion of the semiconductor layer,
wherein, in the first ditches adjacently arranged in the first direction, distances between an upper surface of the grate electrodes and a bottom surface of the second insulating film are different.

US Pat. No. 10,170,551

SIDEWALL IMAGE TRANSFER NANOSHEET

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a nanosheet stack on a substrate, the nanosheet stack comprising:
a sacrificial nanosheet layer on the substrate; and
a nanosheet layer on the sacrificial nanosheet layer;
an etch stop layer on the nanosheet stack;
a mandrel on the etch stop layer;
sidewalls adjacent to sidewalls of the mandrel; and
a fill layer on exposed portions of the etch stop layer.

US Pat. No. 10,170,550

STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming an alternating stack of disposable material portions and semiconductor material portions on a substrate;
forming a disposable gate structure straddling, and contacting sidewalls of, said alternating stack;
removing said disposable material portions selective to said semiconductor material portions and said disposable gate structure;
forming a first gate structure between each vertically neighboring pair among said semiconductor material portions, said first gate structure including a first gate dielectric and a first gate electrode;
forming a planarization dielectric layer around said disposable gate structure;
forming a gate cavity by removing said disposable gate structure selective to said planarization dielectric layer; and
forming a second gate structure within said gate cavity, said second gate structure including a second gate dielectric and a second gate electrode, wherein said forming the first gate structure comprises forming, after removing said disposable material portions, a first gate dielectric layer on surfaces of said semiconductor material portions, forming a first gate conductor layer on said first gate dielectric layer, anisotropically etching said first gate conductor layer and said first gate dielectric layer employing a combination of said disposable gate structure and said semiconductor material portions as an etch mask, and isotropically etching remaining portions of said first gate conductor layer and said first gate dielectric layer between said vertically neighboring pair among said semiconductor material portions.

US Pat. No. 10,170,549

STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET

Samsung Electronics Co., ...

1. A method for fabricating a nanosheet stack structure having one or more sub-stacks, the method comprising:growing an epitaxial crystalline initial stack of the one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are each kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing such that the non-sacrificial layers B and C remain metastable and without relaxation during processing, and wherein the sacrificial layer A is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A;
proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that hold the nanosheets in place after selective etch of the sacrificial layers; and
selectively removing sacrificial layers A from all non-sacrificial layers B and C, while the remaining layers B and C in the stack are held in place by the pillar structures, so that after removal of the sacrificial layers A, each of the sub-stacks contains the non-sacrificial layers B and C, the sacrificial layer A differing from the non-sacrificial layers B and C such that removal of the sacrificial layer A leaves the non-sacrificial layer B and the non-sacrificial layer C in all of the plurality of sub-stacks and such that no sub-stack includes the non-sacrificial layer B in the absence of the non-sacrificial layer C and no sub-stack includes the non-sacrificial layer C in the absence of the non-sacrificial layer B, the sacrificial layer A being at least three times as thick as the non-sacrificial layer B and as the non-sacrificial layer C.

US Pat. No. 10,170,548

INTEGRATED CAPACITORS WITH NANOSHEET TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:depositing alternating nanosheet layers and sacrificial layers onto a substrate;
simultaneously forming fins in a capacitor region and fins in a device region, wherein the fins in the capacitor region have a greater width than the fins in the device region;
selectively etching the sacrificial layers to form an undercut in the capacitor region and complete removal in the device region;
doping the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region;
depositing a high k dielectric layer onto the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region, and on the nanosheet layers in the device region; and
forming top and bottom electrodes in the capacitor region.

US Pat. No. 10,170,547

NANODEVICE

JAPAN SCIENCE AND TECHNOL...

1. A nanodevice comprising:nanogap electrodes comprising a first electrode and a second electrode so as to have a nanosized gap in between;
a nanoparticle disposed between the nanogap electrodes;
one or more gate electrodes, each of the one or more gate electrodes connected to a wire so as to apply an input voltage;
a floating gate electrode;
a control gate electrode to control a state of electric charge of the floating gate electrode;
a first insulating layer on which the nanogap electrodes and the floating gate electrode are disposed; and
a second insulating layer disposed on the first insulating layer, the nanogap electrodes, the floating gate electrode, and the nanoparticle,
wherein the control gate electrode is disposed on the first insulating layer, and
the control gate electrode is disposed on an opposite side to the nanoparticle with the floating gate electrode interposed therebetween, or
wherein the control gate electrode is disposed on the second insulating layer and above the floating gate electrode, and
wherein the one or more gate electrodes do not include the floating gate electrode and the control gate electrode.

US Pat. No. 10,170,543

VERTICAL FIN FIELD EFFECT TRANSISTOR WITH AIR GAP SPACERS

International Business Ma...

1. A method of forming a fin field effect transistor device with air gaps, comprising:forming a vertical fin on a substrate;
forming an inner protective cap on the vertical fin;
forming an outer protective cap on the inner protective cap;
forming a source/drain layer in contact with the vertical fin;
forming a sacrificial bottom spacer on each side of the vertical fin, and on the source/drain layer; and
forming a spacer cap layer on the sacrificial bottom spacer.

US Pat. No. 10,170,540

CAPACITORS

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming separate wiring lines on a substrate, with spacing between adjacent separate wiring lines;
forming air gaps within the spacing by depositing capping material on the separate wiring lines and the spacing between the adjacent separate wiring lines;
forming a dielectric material over the capping material;
forming a trench in the dielectric material and over plural ones of the adjacent separate wiring lines, wherein the forming the trench opens the air gaps by removing a surface of the capping material; and
depositing conductive material within the opened air gaps through the trench.

US Pat. No. 10,170,518

SELF-ASSEMBLED PATTERN PROCESS FOR FABRICATING MAGNETIC JUNCTIONS USABLE IN SPIN TRANSFER TORQUE APPLICATIONS

Samsung Electronics Co., ...

1. A method for providing a plurality of magnetic junctions on a substrate and usable in a magnetic device, the method comprising:providing a patterned seed layer, the patterned seed layer including a plurality of magnetic seed islands interspersed with an insulating matrix;
providing at least a portion of a magnetoresistive stack after the step of providing the patterned seed layer, the magnetoresistive stack including at least one magnetic segregating layer, the at least one magnetic segregating layer including at least one magnetic material and at least one insulator;
annealing the at least the portion of the magnetoresistive stack such that the at least one magnetic segregating layer segregates such that a plurality of portions of at least one magnetic material align with the plurality of magnetic seed islands and such that a plurality of portions of the at least one insulator align with the insulating matrix.

US Pat. No. 10,170,506

LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME

Shenzhen China Star Optoe...

1. A method for producing a low temperature poly-silicon (LTPS) array substrate, comprising:forming a gate of a thin-film transistor (TFT) on a substrate;
forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one in which an upper surface of the insulating layer is a plane;
exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer;
forming a source and a drain of the TFT on the polycrystalline silicon layer;
forming a pixel electrode on the insulating layer and a part of the drain;
forming a plain passivation layer on a source-drain electrode layer, which is fabricated from the source and the drain, and forming contact vias in the plain passivation layer for exposing surfaces of the gate and the drain, and the contact vias being disposed outside the polycrystalline silicon layer; and
forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is electrically connected to the gate via the contact via;
wherein before the insulating layer is formed on the substrate, a pre-operation is carried out to form a buffer layer on a portion of the substrate that is not covered by the gate such that an upper surface of the buffer layer and an upper surface of the gate collectively form a plane, and the pre-operation comprises the following steps:
forming the buffer layer and a negative photoresist layer on the substrate in sequence;
exposing one side of the substrate on the opposite side of the gate for removing a portion of the negative photoresist layer disposed right above the gate; and
removing the buffer layer disposed right above the gate such that a portion of the buffer layer is preserved on the portion of the substrate that is not covered by the gate; and
wherein the step of “exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer” comprises the following sub-steps:
exposing one side of the substrate on the opposite side of the gate for only preserving the first positive photoresist layer disposed on a first section disposed right above the gate;
injecting P-type impurity ions into the semiconductor layer outside the first section;
exposing one side of the substrate on the opposite side of the gate for forming the first positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; and
removing the first positive photoresist layer disposed on the second section.

US Pat. No. 10,170,481

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor memory device comprising:a substrate, wherein the substrate comprises a memory cell region and a periphery region;
a plurality of bit lines, disposed on the substrate, within the memory cell region;
a gate, disposed on the substrate, within the periphery region;
a spacer layer covering the bit lines and a sidewall of the gate; and
a first spacer disposed on the sidewall and an opposite sidewall of the gate and covering the spacer layer.

US Pat. No. 10,170,478

SPACER FOR DUAL EPI CMOS DEVICES

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor comprising:forming a first semiconductor device comprising two or more first gate stacks formed on a first substrate, and forming a second semiconductor device comprising two or more second gate stacks formed on the first substrate, the first semiconductor device including a first fin region having first source-drain areas and the second semiconductor device including a second fin region having second source-drain areas, the first source-drain area and the second source drain area each comprising a horizontal surface on an upper surface of the respective source-drain area:
depositing a wet-etch resistant spacer material on the first and second semiconductor devices;
removing a portion of the wet-etch resistant spacer material from the first fin region and the second fin region with anisotropic spacer reactive ion etch such that remaining portions of the wet-etch resistant spacer material form first wet-etch resistant spacers having a first thickness on the first semiconductor device and second wet-etch resistant spacers having a second thickness equal to the first thickness on the second semiconductor device;
depositing a first nitride liner on the first and second semiconductor devices;
depositing a dielectric layer on the first nitride liner;
planarizing the dielectric layer;
selectively removing the dielectric layer from between the first wet-etch resistant spacer material in the first fin region and the second wet-etch resistant spacer in the second fin region;
depositing a second nitride liner on the first and second semiconductor devices and selectively removing the second nitride liner from the first semiconductor device;
growing a first epitaxial layer on the first source-drain area by an epitaxial growth process such that the first epitaxial layer extends the length of the first source-drain area and covers the horizontal surface of the first source-drain area except areas covered by the first gate stack and the first wet-etch resistant spacer material;
depositing a third nitride liner on the first and second semiconductor devices and selectively removing the third nitride liner from the second semiconductor device; and
growing a second epitaxial layer on the second source-drain area by a second epitaxial growth process.

US Pat. No. 10,170,474

TWO DIMENSION MATERIAL FIN SIDEWALL

International Business Ma...

1. A semiconductor structure fabrication method comprising:forming neighboring fins associated with a semiconductor substrate, the neighboring fins separated by a fin well;
forming a fin cap upon each neighboring fin;
forming a well-plug within a bottom portion of the fin well such that sidewall portions of the neighboring fins are exposed to an upper portion of the fin well; and
forming a 2D material upon the sidewall portions of the neighboring fins.

US Pat. No. 10,170,342

FLOW CONTROLLED LINER HAVING SPATIALLY DISTRIBUTED GAS PASSAGES

Applied Materials, Inc., ...

1. A liner assembly, comprising:a lower liner having an outer surface, an inner surface defining a processing volume, an upper surface connecting the outer surface to the inner surface, and a plurality of gas passages connecting the outer surface to the processing volume, each of the plurality of gas passages comprising a first portion connected to a second portion, each first portion opening to the outer surface of the lower liner and each second portion having an upper end open to the upper surface and a lower end connected to the first portion; and
an upper liner disposed adjacent to the lower liner, the upper liner including a plurality of flow guides aligned with the plurality of gas passages.

US Pat. No. 10,170,309

DUMMY PATTERN ADDITION TO IMPROVE CD UNIFORMITY

GLOBALFOUNDRIES INC., Gr...

1. A method of forming a semiconductor device, comprising:forming a first masking layer over a semiconductor substrate, the first masking layer comprising first features; and
forming a second masking layer over the semiconductor substrate, the second masking layer comprising second features, wherein
a first portion of the first features are formed laterally adjacent to the second features, a second portion of the first features entirely overlie the second features, a first portion of the second features are formed laterally adjacent to the first features, and a second portion of the second features entirely overlie the first features, wherein the first features have a constant width and the second features have a constant width different from the width of the first features, and wherein the semiconductor device comprises an SRAM.

US Pat. No. 10,170,290

SYSTEMS AND METHODS FOR GROUPING MS/MS TRANSITIONS

THERMO FINNIGAN LLC, San...

1. A method for analyzing a sample, comprising:identifying a plurality of precursors for analysis;
grouping the precursors into two or more groups, such that the precursors within a group conform to at least the following criteria:
a) masses of ions of the precursors in the group are within a first mass range;
b) masses of product ions of the precursors in the group are within a second mass range;
c) the number of precursors within the group is below a maximum allowable number of precursors; and
d) each precursor within the group has at least one unique product ion that differs from the product ions of all the other precursors within the group;
generating ions from the sample;
isolating precursor ions of a group;
fragmenting the ions of the group;
determining the mass-to-charge ratio of the fragment ions;
repeating the isolating, fragmenting, and determining steps for additional groups;
identifying or quantifying the presence of one or more precursors within the sample based on the presence of fragmented ions having a mass-to-charge ratio corresponding to the unique product ion for the precursor.

US Pat. No. 10,170,289

PHOTOTUBE AND METHOD OF MAKING IT

Shenzhen Genorivision Tec...

1. A phototube suitable for detecting a photon, the phototube comprising:an electron ejector configured for emitting electrons in response to an incident photon;
a detector configured for collecting the electrons and providing an output signal representative of the incident photon;
an electrode configured for applying a voltage to drive the electrons to the detector;
one or more sidewalls forming an envelope of a hole between the electrode and the detector, wherein the electron ejector is inside the hole and bonded to the electrode, wherein the hole is in a substrate; and
a metal wall at the one or more sidewalls, wherein the metal wall is configured for applying a voltage to drive the electrons away from the sidewalls.

US Pat. No. 10,170,279

MULTIPLE COIL INDUCTIVELY COUPLED PLASMA SOURCE WITH OFFSET FREQUENCIES AND DOUBLE-WALLED SHIELDING

Applied Materials, Inc., ...

1. A plasma reactor comprisinga window assembly;
first and second coil antennas adjacent said window assembly;
a first current distributor coupled to said first coil antenna and a second current distributor coupled to said second coil antenna;
first and second RF feed terminals;
first and second RF power sources coupled to said first and second RF feed terminals respectively;
a conductive feed plate lying in a plane above said first and second coil antennas and coupled to said second RF feed terminal, and a plurality of axial rods coupled between a peripheral annular zone of said conductive feed plate and said second current distributor;
a conductive ground plate in a plane between said conductive feed plate and said first current distributor; and
a first radial conductive feed rod lying in a plane above said conductive ground plate and having an inner end coupled to said first current distributor and an outer end coupled to said first RF feed terminal.

US Pat. No. 10,170,238

HAND TOOL DEVICE HAVING AT LEAST ONE CHARGING COIL

ROBERT BOSCH GMBH, Stutt...

1. A hand tool device, comprising:at least one charging coil for inductive charging which includes at least one coil core which is at least partially made of a ceramic material and which is provided for transmitting energy, and at least one wound electrical conductor;
wherein the coil core is configured as a composite component, has at least two magnetic field bundling elements including an upper part bundling element and a lower part bundling element which are made of a ceramic material, and are at least partially formed by a film which glues the upper part bundling element and the lower part bundling element, wherein the upper part bundling element has a diameter that is three times a diameter of the lower part bundling element,
wherein the film is attached to an upper side of the at least one magnetic field bundling element, and the at least one wound electrical conductor is arranged on a lower side of the at least one magnetic field bundling element, wherein the upper side is facing away from the at least one magnetic field bundling element in a first direction and the lower side is facing away from the at least one magnetic field bundling element in a second direction, wherein the first direction is opposite to the second direction,
wherein the entire at least one magnetic field bundling element is surrounded by the film,
wherein the coil core has a toroid shape,
wherein the magnetic field bundling element has a toroid shape,
wherein the magnetic field bundling element surrounds the wound electrical conductor only on an upper side and an inner side,
wherein the coil core is at least partially made of a soft elastic material,
wherein the coil core is made of at least one sintered powder or pellets.

US Pat. No. 10,170,199

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

International Business Ma...

1. A system comprising:a multiple input signature register (MISR), wherein the MISR is logically coupled to digital outputs of a content addressable memory (CAM) (CAM match outputs), is logically coupled to digital inputs of a random access memory (RAM) (RAM inputs), and is logically coupled to digital outputs of an array built-in self-test (ABIST) controller circuit (ABIST outputs);
wherein the MISR comprises a plurality of L1 latch circuits logically coupled to a plurality of L2 latch circuits, a plurality of multiplexer (MUX) circuits logically coupled to the plurality of L1 latch circuits, a plurality of exclusive or (XOR) circuits (inner XOR circuits) logically coupled to the plurality of MUX circuits and to the plurality of L2 latch circuits, and at least two XOR circuits (outer XOR circuits), wherein each of the outer XOR circuits is logically coupled to one of the inner XOR circuits, to at least one of the MUX circuits, and to at least one of the L2 latch circuits,
wherein each of the L1 latch circuits comprises a first data input, a first scan input, and a first output, and
wherein each of the L2 latch circuits comprises a second data input, a second scan input, and a second output;
wherein the MISR is logically configured to receive the CAM match outputs on the first data inputs of the L1 latch circuits;
wherein the MISR is logically configured to address the RAM via the first outputs of the L1 latch circuits and the RAM inputs;
wherein the MISR is logically configured to receive the ABIST outputs via the MUX circuits and the inner XOR circuits on the first scan inputs of the L1 latch circuits;
wherein the MISR is logically configured to output compression data (L2 scan out data) via the second outputs of the L2 latch circuits; and
wherein the MISR is logically configured to provide feedback data via the outer XOR circuits;
wherein the CAM is logically coupled to a compare mask circuit, and
wherein the compare mask circuit is logically configured to direct the CAM to output one bit of the CAM match outputs at a time;
wherein the MISR is further logically configured, in response to receiving a digital control input signal, to address the RAM via the first outputs of the L1 latch circuits and the RAM inputs and via CAM match wordlines on the first outputs of the L1 latch circuits, wherein the CAM match wordlines correspond to the CAM match outputs;
wherein the MISR is further logically configured, in response to receiving a first type of digital signal from one of the ABIST outputs, to test even numbered CAM match outputs (even CAM match data) among the CAM match outputs against a first set of the ABIST outputs; and
wherein the MISR is further logically configured, in response to receiving a second type of digital signal from one of the ABIST outputs, to test odd numbered CAM match outputs (odd CAM match data) among the CAM match outputs against a second set of the ABIST outputs.

US Pat. No. 10,170,198

DATA STORAGE AND METHOD OF OPERATING THE SAME

Samsung Electronics Co., ...

1. A data storage comprising:at least one nonvolatile memory device; and
a controller operatively connected to the at least one nonvolatile memory device,
wherein the controller is configured to receive binary data from a host through a side-band interface,
wherein the controller includes a buffer configured to store the binary data,
wherein the controller is configured to execute the binary data according to a request from the host to execute a test operation,
wherein the data storage is an on-board SSD in which the at least one nonvolatile memory device and the controller are mounted on a board,
wherein the binary data is divided according to a property of the test operation to provide divided binary data and is received from the host, and
wherein a size of the divided binary data is equal to or smaller than a size of the buffer.

US Pat. No. 10,170,186

HIGH-DENSITY EEPROM ARRAYS UTILIZING STACKED FIELD EFFECT TRANSISTORS

International Business Ma...

1. A semiconductor device, comprising:a substrate;
a first transistor located on top of the substrate and connected to a first terminal;
a second transistor located on top of the first transistor and connected in parallel to the first transistor and connected to a second terminal, where the first and second transistors share a common floating gate and a common output terminal; and
an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.

US Pat. No. 10,170,181

VARIABLE RESISTANCE MEMORY DEVICE INCLUDING BIDIRECTIONAL SWITCH, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF

Samsung Electronics Co., ...

1. A memory device, comprising:a plurality of word lines and a plurality of bit lines;
a cell array connected to the plurality of word lines and the plurality of bit lines, the cell array including a plurality of memory cells each including a variable resistance element and a bidirectional selection element, the cell array having a first area including at least some of the memory cells and further having a second area including at least some others of the memory cells;
a selection circuit which is configured to select a selected word line of the plurality of word lines and a selected bit line of the plurality of bit lines; and
control logic configured to control the selection circuit such that in a stand-by state, the word lines and the bit lines connected to the memory cells of the first area of the cell array are maintained at a discharge state so as to have a discharge voltage, and the word lines and the bit lines connected to the memory cells of the second area of the cell array are maintained at a precharge state so as to have a precharge voltage which is greater than the discharge voltage.

US Pat. No. 10,170,178

SECURE OFF-CHIP MRAM

International Business Ma...

1. A method of operating a nonvolatile memory chip, comprising the steps of:overwriting data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on; and
providing a user with an option to change a security setting from a volatile mode whereby the data is overwritten automatically upon the nonvolatile memory chip being powered on to a nonvolatile mode whereby the overwriting step is bypassed.

US Pat. No. 10,170,171

3D SPINRAM

Integrated Magnetoelectro...

1. A three-dimensional memory, comprising:a first level including first circuitry configured to generate drive signals for each of a plurality of memory cells in the memory, the first circuitry also being configured to generate address signals corresponding to each of the memory cells, the address signals addressing the memory cells as a two-dimensional array; and
a plurality of memory array levels fabricated in a stack on the first level, each memory array level including a corresponding memory cell array including a subset of the memory cells, each memory cell comprising a multilayer structure exhibiting magnetoresistance, each memory array level also including second circuitry configured to translate corresponding address signals from the first circuitry to a physical structure of the corresponding memory cell array, and to route corresponding drive signals to corresponding memory cells, the second circuitry being implemented using solid-state components, each solid state component comprising a network of multilayer structures exhibiting magnetoresistance.

US Pat. No. 10,170,169

APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS

Micron Technology, Inc., ...

1. A method, comprising:accessing a first sub-block of memory cells and a second sub-block of memory cells at the same time, wherein the first and second sub-blocks of memory cells are part of a first block of memory cells of multiple blocks of memory cells of a memory array,
wherein the first and second sub-blocks within the block are enabled to be accessed simultaneously, and wherein the memory cells in a second block of memory cells are not enabled to be accessed when memory cells of the first block are being accessed; and
wherein the first sub-block of the block of memory cells and the second sub-block of the block of memory cells are not in the same row or the same column of the block of memory cells.

US Pat. No. 10,170,166

DATA TRANSMISSION APPARATUS FOR MEMORY AND DATA TRANSMISSION METHOD THEREOF

Winbond Electronics Corp....

1. A data transmission apparatus for a memory, comprising:a prior stage shift register circuit, coupled to a sense amplifying device of the memory, receiving sensed data from the sense amplifying device and outputting a plurality of the readout data in series by bitwise shifting out the sensed data according to a shift clock signal; and
a plurality of rear stage shift register circuits, coupled to the prior stage shift register circuit and respectively coupled to a plurality of pads, respectively receiving the readout data and respectively bitwise providing the readout data to the pads according to a clock signal,
wherein, a frequency of the shift clock signal is less than a frequency of the clock signal.

US Pat. No. 10,170,164

SENSE AMPLIFIER LATCH CIRCUIT AND SENSE AMPLIFIER MULTIPLEXED LATCH CIRCUIT

GLOBALFOUNDRIES INC., Gr...

1. A sense amplifier latch circuit comprising:a latch circuit driven by a first and second sense amplifier output;
a first latch driver having a first PMOS transistor coupled to a latch node and to a pair of serially coupled NMOS transistors, wherein the first sense amplifier output is gate coupled to the first PMOS transistor and the first NMOS transistor of the first latch driver;
a second latch driver having a second PMOS transistor coupled to a latch node and to a pair of serially coupled NMOS transistors, wherein the second sense amplifier output is gate coupled to the second PMOS transistor and the second NMOS transistor of the second latch driver;
a first and second supply PMOS transistor, wherein an output of the first supply PMOS transistor is coupled to the latch node of the first latch driver and to a gate of both the second supply PMOS transistor and first NMOS transistor of the second latch driver, and wherein an output of the second supply PMOS transistor is coupled to the latch node of the second latch driver and to a gate of both the first supply PMOS transistor and second NMOS transistor of the first latch driver.

US Pat. No. 10,170,161

SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR

RENESAS ELECTRONICS CORPO...

1. A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method comprising:writing first data into a plurality of memory cells;
while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data;
and reading the data written into the memory cells.

US Pat. No. 10,170,147

MOVING CARTRIDGES WITHIN A SHUTTLE COMPLEX

International Business Ma...

1. A method to move an access-cartridge including a storage medium within a shuttle complex having a plurality of library strings connected by a plurality of shuttle connections, the method comprising:identifying a library string comprising an access-cartridge (LSAC);
determining whether there is a local drive amongst a plurality of local drives within the LSAC that has a second cartridge mounted therein which comprises only inactive data chunks;
removing the second cartridge from the local drive within the LSAC and mounting the access-cartridge to the local drive within the LSAC, if an elapsed time since the local drive within the LSAC most recently accessed the second cartridge exceeds a predetermined time period threshold; and
if the elapsed time since the local drive within the LSAC most recently accessed the second cartridge does not exceed the predetermined time period threshold:
identifying a remote drive within a remote library string (LSR) connected to the LSAC by at least one shuttle connection;
moving the access-cartridge from the LSAC to the LSR with the at least one shuttle connection; and
mounting the access-cartridge to the remote drive within the LSR.

US Pat. No. 10,170,128

METHOD AND APPARATUS FOR PROCESSING TEMPORAL ENVELOPE OF AUDIO SIGNAL, AND ENCODER

HUAWEI TECHNOLOGIES CO., ...

8. An apparatus for processing an audio signal, comprising:a memory comprising instructions; and
a processor in communication with the memory, wherein the processor executes the instructions to:
obtain a high-band signal of a current frame of an audio signal;
divide the high-band signal of the current frame signal into M subframes, wherein M is an integer that is greater than 2;
perform windowing on a first subframe of the M subframes and a last subframe of the M subframes by using a first asymmetric window function,
perform windowing on a subframe except the first subframe and the last subframe of the M subframes to obtain a temporal envelope of the M subframes; and
encode the high-band signal of the current frame of the audio signal according to the temporal envelope of the M subframes.

US Pat. No. 10,170,127

METHOD AND APPARATUS FOR SENDING MULTIMEDIA DATA

SAMSUNG ELECTRONICS CO., ...

1. A first device, which provides an audio signal to a second device, the first device comprising:a memory that stores at least one previous audio frame;
a controller that:
determines a packet size based on a bandwidth supported by a channel mode,
determines using lossless codec, when the packet size is larger than a data threshold,
determines a frame size based on the packet size, when the packet size is smaller than or equal to the data threshold,
divides an audio signal input to the first device into a plurality of audio frames based on the frame size, compares a current audio frame among the plurality of audio frames with the at least one previous audio frame prestored in the memory of the first device, and selects one of the prestored previous audio frames based on similarity of the prestored previous audio frame and the current audio frame; and
a communicator that transmits an identification value of the selected previous audio frame to the second device instead of compressed data for the current audio frame.

US Pat. No. 10,170,114

SYSTEMS AND METHODS FOR ADAPTIVE PROPER NAME ENTITY RECOGNITION AND UNDERSTANDING

Promptu Systems Corporati...

1. A computer-implemented method for recognizing and understanding spoken commands that include one or more proper name entities, comprising:receiving an utterance from a user as input;
performing primary automatic speech recognition (ASR) processing upon said utterance with a primary automatic speech recognizer to output one or more datasets, each said dataset comprising at least a sequence of nominal transcribed words, said sequence comprising a nominal primary transcription;
performing understanding processing upon each said dataset with a natural language understanding (NLU) processor to generate and augment the dataset with a nominal meaning for the nominal primary transcription and to determine the putative presence and type of one or more spoken proper name entities within said utterance, and wherein with each said spoken proper name entity is associated a contiguous sequence of nominal transcribed words within said dataset comprising a target span;
performing for each said dataset one or more instances of secondary automatic speech recognition (ASR) processing upon an entirety of said utterance, in each instance said secondary automatic speech recognizer specialized to process each given putative type of proper name entity and associated target span to generate one or more transcriptions and associated meanings for each said target span;
revising each said dataset by substituting, for each of the one or more instances of secondary automatic speech recognition processing, each of the one or more transcriptions and associated meanings obtained for each target span, to create from the totality of aforesaid revised datasets a set of one or more complete transcriptions and associated meanings; and
outputting a set of one or more complete transcriptions and associated meanings for the entire utterance.

US Pat. No. 10,170,110

SYSTEM AND METHOD FOR RANKING OF HYBRID SPEECH RECOGNITION RESULTS WITH NEURAL NETWORKS

Robert Bosch GmbH, Stutt...

1. A method for speech recognition in an automated system comprising:generating, with a controller, a plurality of feature vectors, each feature vector corresponding to one candidate speech recognition result in a plurality of candidate speech recognition results, the generating of a first feature vector in the plurality of feature vectors for a first candidate speech recognition result in the plurality of candidate speech recognition results further comprising:
identifying, with the controller, at least one trigger pair including two predetermined trigger words within the first candidate speech recognition result with reference to a plurality of predetermined trigger pairs stored in a memory;
identifying, with the controller, a plurality of unique words in the first candidate speech recognition result including a frequency that each unique word in the plurality of words occurs and at least one position of each unique word in the first candidate speech recognition result;
generating, with the controller a plurality of bag-of-words with decay parameters, each bag-of-words with decay parameter bowi being defined as bowi=?p?P?(wi)?p corresponding to one unique word wi in the plurality of unique words based on the frequency and the at least one position of the one unique word wi in a set of positions P?(wi) where the one unique word wi occurs and a predetermined numeric decay factor ?; and
generating, with the controller, the first feature vector including an element for the at least one trigger pair and an element for each bag-of-words with decay parameter in the plurality of bag-of-words with decay parameters;
providing, with the controller, the plurality of feature vectors as inputs to a neural network stored in the memory;
generating, with the controller a plurality of ranking scores corresponding to the plurality of feature vectors for the plurality of candidate speech recognition results based on an output layer of the neural network; and
operating, with the controller, the automated system using the candidate speech recognition result in the plurality of candidate speech recognition results corresponding to a highest ranking score in the plurality of ranking scores as input.

US Pat. No. 10,170,102

AUTOMATIC ACCURACY ESTIMATION FOR AUDIO TRANSCRIPTIONS

International Business Ma...

9. A system for assigning a confidence level to at least one axiom extracted from text data, comprising:a memory medium comprising instructions;
a bus coupled to the memory medium; and
an audio transcription tool coupled to the bus that when executing the instructions causes the system to:
determine a number of accurate words in the text data based on a spell check function;
divide the number of accurate words from the text data by a total number of words in the text data;
automatically extract from a knowledge base stored in a computer infrastructure, the at least one axiom, wherein the axiom comprises a computer-parsable definition of a relationship of data to at least one of the words in the text data;
assign a confidence level to the at least one axiom based on an output of a Gaussian function applied to the result of the dividing;
receive a query from a user device, wherein the query includes at least one word;
match the at least one word with the at least one axiom using the knowledge base; and
provide the at least one axiom from the knowledge base to the user device based on the matching and the assigned confidence level.

US Pat. No. 10,170,099

ELECTRONIC DEVICE AND METHOD FOR REPRESENTING WEB CONTENT FOR THE ELECTRONIC DEVICE

Samsung Electronics Co., ...

1. An electronic device comprising:a speaker;
a display;
a sensor;
communication circuitry; and
a controller configured to:
display, on the display, a first web page comprising a first area and a second area, the first area including a plurality of objects linked to a plurality of web pages, respectively,
determine, via the sensor, a state of the electronic device,
output, via the speaker, at least one voice corresponding to at least one text included in at least one of the first area and the second area, when it is determined that a user does not stare at the first web page according to the state of the electronic device, and
determine whether to convert the at least one text included in the at least one of the first area and the second area of the first web page to voice data based on a capability of a wearable external device received from the wearable external device, and
transmit, via the communication circuitry, a first information to output information included in the first area to the wearable external device, based on the capability of the wearable external device when it is determined that the user does not stare at the first web page according to the state of the electronic device.

US Pat. No. 10,170,098

SOUND EFFECT GENERATION DEVICE FOR VEHICLES

MAZDA MOTOR CORPORATION, ...

1. A vehicle sound effect generation apparatus for generating a sound effect of an engine based on a vibration sound database including a fundamental wave sound having a fundamental frequency component and a plurality of adjustment wave sounds having a frequency component other than the fundamental frequency component, the vehicle sound effect generation apparatus comprising:a running state detecting unit that detects a running state of a vehicle;
a lateral input amount setting unit that sets, based on the running state detected by the running state detecting unit, a lateral input amount in which a physical amount relating to at least one of a movement of the vehicle in a width direction and a movement of the vehicle in a turning direction is a parameter;
an adjustment wave sound selector that selects one or more half-order adjustment wave sounds having a half-order frequency component, based on the lateral input amount; and
a sound effect generation unit that synthesizes the fundamental wave sound with the one or more half-order adjustment wave sounds selected.

US Pat. No. 10,170,079

DISPLAY APPARATUS AND DISPLAY PANEL DRIVING METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A method of driving a display panel comprising a plurality of pixels including red (R), green (G), blue (B), and white (W) sub-pixels, the method comprising:receiving image data;
converting RGB data included in the received image data into RGBW data; and
driving the display panel based on the converted RGBW data,
wherein the converting comprises converting the RGB data into YCbCr data and obtaining a W value of the RGBW data based on a Y value of the converted YCbCr data, and
wherein the W value is the Y value of the converted YCbCr data or a value obtained by applying the Y value to a predetermined contrast enhancement algorithm.

US Pat. No. 10,170,069

SHIFT REGISTER, DRIVING METHOD THEREOF AND GATE DRIVING DEVICE HAVING STABLE OUTPUT

BOE TECHNOLOGY GROUP CO.,...

1. A shift register, comprising:an input circuit, coupled to a signal input terminal, a first voltage signal terminal and a first node, and configured to supply a first voltage signal from the first voltage signal terminal to the first node according to an input signal from the signal input terminal;
a first reset circuit, coupled to a reset signal terminal, a second voltage signal terminal and the first node, and configured to supply a first reset signal from the second voltage signal terminal to the first node according to a second reset signal from the reset signal terminal, so as to reset a voltage of the first node;
an output circuit, coupled to a clock signal terminal, a signal output terminal and the first node, and configured to supply a clock signal from the clock signal terminal to the signal output terminal as an output signal, according to the voltage of the first node;
a second reset circuit, coupled to a third voltage signal terminal, the first node, a second node and the signal output terminal, and configured to supply a third voltage signal from the third voltage signal terminal to the first node and the signal output terminal according to a voltage of the second node, so as to reset the voltage of the first node and the output signal; and
a first pull-down control circuit, coupled to the first node, the second node, the third voltage signal terminal, a first auxiliary voltage signal terminal and a second auxiliary voltage signal terminal, and configured to control the voltage of the second node according to the voltage of the first node;
wherein a phase of a first auxiliary voltage signal from the first auxiliary voltage signal terminal is opposite to that of a second auxiliary voltage signal from the second auxiliary voltage signal terminal, each with a duty ratio of 50%, and
wherein the first pull-down control circuit comprises:
a sixth transistor having a control electrode coupled to the first node, a first electrode coupled to the third voltage signal terminal, and a second electrode coupled to the second node;
a seventh transistor having a control electrode and a first electrode both coupled to the second auxiliary voltage signal terminal, and a second electrode coupled to the second node; and
an eighth transistor having a control electrode and a first electrode both coupled to the first auxiliary voltage signal terminal, and a second electrode coupled to the second node, and
wherein a width-to-length ratio of the seventh transistor is identical with a width-to-length ratio of the eighth transistor; and
a width-to-length ratio of the sixth transistor is an integral multiple of the width-to-length ratios of the seventh transistor and the eighth transistor.

US Pat. No. 10,170,068

GATE DRIVING CIRCUIT, ARRAY SUBSTRATE, DISPLAY PANEL AND DRIVING METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A driving method for a gate driving circuit, the gate driving circuit comprising:at least a Gate driver on Array (GOA) unit at stage n, GOAn, and a GOA unit at stage n+m, GOAn+m, an output terminal of GOAn being connected to an input terminal of GOAn+m, and an output terminal of GOAn+m being connected to a reset terminal of GOAn, where n and m are natural numbers;
a signal line providing an electrical leakage compensation signal VLHB; and
an electrical leakage compensation sub circuit having two input terminals connected to output terminals of GOAn and GOAn+m, respectively, a control terminal connected to the signal line, and an output terminal connected to a Pull-Up (PU) node of GOAn+m, the electrical leakage compensation sub circuit being configured to compensate for a voltage at the PU node of GOAn+m in response to the electrical leakage compensation signal VLHB,wherein the driving method comprises:a display scanning phase in which the electrical leakage compensation signal is at a first level;
a compensation phase in which the electrical leakage compensation signal is at a second level, such that the electrical leakage compensation sub circuit compensates for the voltage at the PU node of the GOA unit, GOAn+m; and
a resetting phase in which the electrical leakage compensation sub circuit is reset in response to the electrical leakage compensation signal being switched from the second level to the first level,wherein the electrical leakage compensation sub circuit comprises a first N-type TFT, a second N-type TFT, a third N-type TFT and a fourth N-type TFT, the first level is low level and the second level is a high level, and wherein:in the display scanning phase, when the output terminal of the GOA unit at stage n, GOAn, is at a low level, the first N-type TFT, the second N-type TFT, the third N-type TFT and the fourth N-type TFT are all off; when the output terminal of the GOA unit at stage n, GOAn, becomes high, the first N-type TFT and the second N-type TFT are on and the third N-type TFT and the fourth N-type TFT are off,
in the compensation phase, the first N-type TFT is off, the second N-type TFT remains on and the third N-type TFT is on, such that a voltage at PUn+1 is pulled up, and
in the resetting phase, when the output terminal of the GOA unit GOAn+m is at the high level, the first N-type TFT, the second N-type TFT and the third N-type TFT are off and the fourth N-type TFT is on; in response to the output terminal of the GOA unit GOAn+m being switched from the high level to the low level, the first N-type TFT, the second N-type TFT, the third N-type TFT and the fourth N-type TFT are all off.

US Pat. No. 10,170,066

DRIVING METHOD AND DRIVING MODULE FOR GATE SCANNING LINE AND TFT-LCD DISPLAY PANEL

Shenzhen China Star Optoe...

1. A driving method for a plurality of gate scanning lines, wherein, the driving method comprises:driving the gate scanning lines line by line through a CKV waveform of a variable frequency of a gate driver;
from a first line of the gate scanning lines to a middle line of the gate scanning lines, an opening time is gradually increased for each of the gate scanning lines;
from the middle line of the gate scanning lines to a N-th line of the gate scanning lines, the opening time is gradually decreased for each of the gate scanning lines,
wherein the middle line of the gate scanning lines comprises a N/2-th line of the gate scanning lines and a N/2+1-th line of the gate scanning lines, the opening time of the N/2-th line of the gate scanning lines is the same as the opening time of the N/2+1-th line of the gate scanning lines, and N is an even integer.

US Pat. No. 10,170,064

CIRCUIT FOR PROCESSING GATE VOLTAGE SIGNAL SUPPLIED FOR LIQUID CRYSTAL DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A circuit for processing a gate voltage signal supplied for a liquid crystal display device, comprising: an input-output circuit and a control circuit;wherein the input-output circuit is configured for receiving the gate voltage signal, the control circuit is configured for receiving a control signal and being subjected to the control of the control signal to make the input-output circuit to output a first output signal in a first time segment, a second output signal in a second time segment, a third output signal in a third time segment and a fourth output signal in a fourth time segment during each period based on the gate voltage signal;
wherein the control signal comprises a first control signal and a second control signal, a period of the first control signal and a period of the second control signal are the same as a period of the gate voltage signal, the first control signal has a first voltage level and the second control signal has a second voltage level in the second time segment, the first control signal has the second voltage level and the second control signal has the first voltage level in the third time segment, the first control signal and the second control signal in the other time segments both have the first voltage level or both have the second voltage level.

US Pat. No. 10,170,058

DISPLAY DEVICE WITH TEMPERATURE-BASED CONTROL AND METHOD FOR DRIVING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A display device comprising:a light emitter comprising a plurality of light emitting elements connected in parallel to each other;
a plurality of switching elements, respectively connected to the plurality of light emitting elements;
a plurality of temperature sensors, respectively configured to detect a temperature of the plurality of switching elements; and
a driving circuit configured to:
control a turn-on level of each of the plurality of switching elements based on the detected temperature, and
adjust a driving current of each of the plurality of light emitting elements based on the turn-on level of a respective switching element connected thereto;
wherein the driving circuit comprises:
a gain adjuster configured to adjust a reference current value based on the detected temperature; and
a compensator configured to adjust the turn-on level of the respective switching element based on a difference between the adjusted reference current value and a feedback current value of the respective switching element.

US Pat. No. 10,170,057

METHOD AND APPARATUS FOR CONTROLLING LIQUID CRYSTAL DISPLAY BRIGHTNESS, AND LIQUID CRYSTAL DISPLAY DEVICE

Hisense Electric Co., Ltd...

1. A method of controlling liquid crystal display brightness, the method comprising:determining, by a liquid crystal display device, grayscale values of pixels in a zone image data block under a predetermined rule according to a received image signal, and pre-obtaining a zone backlight value corresponding to the zone image data block according to the grayscale values;
determining, by the liquid crystal display device, a backlight gain coefficient according to a backlight value gain variable and an ambient luminance revision variable, and multiplying, by the liquid crystal display device, the zone backlight value with the backlight gain coefficient to obtain a backlight value, to which a gain is applied, of a backlight zone corresponding to the zone image data block, wherein the backlight value gain variable is determined by the grayscale values, and the ambient luminance revision variable is determined by ambient luminance; and
outputting, by the liquid crystal display device, the backlight value, to which a gain is applied, of the backlight zone to a driver circuit of a backlight source in the backlight zone to control brightness of the backlight source in the backlight zone as a result of the driver circuit driving the backlight source.

US Pat. No. 10,170,056

METHOD OF CONTROLLING MIRROR DISPLAY AND ELECTRONIC DEVICE FOR THE SAME

Samsung Electronics Co., ...

1. A method of controlling a mirror display, comprising:applying lighting power generated from one of external power and battery power to a power input terminal of a lighting unit of the mirror display, according to whether the external power is input to the mirror display, wherein the lighting unit includes the power input terminal and an enable terminal, the power input terminal is configured to receive the lighting power, and the enable terminal is configured to receive a signal for enabling or disabling the lighting unit;
applying the external power to a power key to operate a controller while the external power is input to the mirror display and applying the battery power to the power key while the external power is not input to the mirror display, wherein the power key outputs the one of the external power and the battery power while the power key is closed;
connecting one of the controller of the mirror display and the power key to the enable terminal of the lighting unit, such that lighting unit is enabled or disabled according to the signal from one of the controller or the battery power from the power key, according to whether the external power is input to the mirror display;
detecting a battery residual capacity of a battery providing the battery power; and
stopping an operation of a display of the mirror display in response to the external power not being input to the mirror display and the battery residual capacity being less than a predetermined value,
wherein connecting the one of the controller and the power key to the enable terminal of the lighting unit further comprises:
connecting the controller to the enable terminal of the lighting unit in response to the battery residual capacity being equal to or greater than the predetermined value; and
connecting the power key to the enable terminal of the lighting unit in response to the battery residual capacity being less than the predetermined value.

US Pat. No. 10,170,050

PIXEL CIRCUIT, DRIVING METHOD, ORGANIC ELECTROLUMINESCENT DISPLAY PANEL, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel circuit, comprising a driving controller, a light emitter, a light emitting controller, an initialization controller, and a compensation controller,wherein the driving controller comprises a first input terminal which is connected with an output terminal of the initialization controller; a second input terminal which is connected with an output terminal of the compensation controller and a first output terminal of the light emitting controller; a third input terminal which is connected with a first input terminal of the light emitting controller and a first reference voltage line; and an output terminal which is connected with a second input terminal of the light emitting controller, and the driving controller is configured to supply a driving current to the light emitter for driving the light emitter to emit light;
wherein the initialization controller comprises a control terminal which is configured to receive an initialization control signal; an input terminal which is configured to receive an initialization signal; and an output terminal which is connected with the first input terminal of the driving controller, and in an initialization phase, the initialization controller is configured to, under the control of the initialization control signal, supply the initialization signal to the driving controller;
wherein the compensation controller comprises a first control terminal which is configured to receive a compensation control signal; a second control terminal which is configured to receive a data signal; an output terminal which is connected with the second input terminal of the driving controller and the first output terminal of the light emitting controller; and an input terminal which is connected with a second reference voltage line, and in the compensation phase, the compensation controller is configured to, under the control of the compensation control signal and the data signal, write the data signal and a preset threshold voltage into the driving controller, wherein the preset threshold voltage has a same threshold voltage as the driving controller to compensate the drift of the threshold voltage of the driving controller; and
wherein the light emitting controller comprises a first input terminal which is connected with the third input terminal of the driving controller and the first reference voltage line; a control terminal which is configured to receive a light emitting control signal; the second input terminal which is connected with an output terminal of the driving controller; the first output terminal which is connected with the second input terminal of the driving controller and the output terminal of the compensation controller; and a second output terminal which is connected with a terminal of the light emitter, and the other terminal of the light emitter is connected with a third reference voltage line, and in a light emitting phase, the light emitting controller is configured to, under the control of the light emitting control signal, supply a voltage of the first reference voltage line to input terminal of the driving controller, store the data signal and the preset threshold voltage in another input terminal of the driving controller, and apply the driving current from the driving controller to the light emitter for driving the light emitter to emit light.

US Pat. No. 10,170,046

OLED DISPLAY DEVICE AND METHOD FOR CORRECTING IMAGE STICKING OF OLED DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An OLED display device, the OLED display device comprises an OLED pixel array; wherein the OLED display device further comprises:a pixel detecting circuit for detecting aging degrees of respective OLED pixels in the OLED pixel array;
wherein respective OLED pixels are aged by displaying an aging image on the OLED pixel array, such that the aging degrees of respective OLED pixels are the same; a brightness of a pixel in the aging image corresponding to an OLED pixel in the OLED pixel array is inversely proportional to the aging degree of the OLED pixel.

US Pat. No. 10,170,043

DISPLAY DRIVING CIRCUIT, ARRAY SUBSTRATE, CIRCUIT DRIVING METHOD, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A display driving circuit, being connected to one scan line and one data line, and comprising a pixel unit, a reset module, and a current control module, whereinthe reset module is connected to a reset signal line and the data line, respectively, and configured to set a voltage on the data line to a preset initial voltage when an active level is on the reset signal line;
the current control module is connected to a reference signal line, a data voltage signal line, and the data line, respectively, and configured to form a first current flowing from the data line to the reference voltage line, a magnitude of the first current being controlled by a voltage on the data voltage signal line; and
the pixel unit is connected to the scan line, the data line, a preset-level voltage line, and an output terminal for outputting a driving current, and configured to output the driving current to the output terminal when the active level is on the scan line,
wherein the pixel unit includes a first transistor and a second transistor,
the first transistor and the second transistor have device parameters that are the same or in a predetermined proportion, gates of the first transistor and the second transistor are both connected to a first node, and first electrodes of the first transistor and the second transistor are both connected to the preset-level voltage line; and
a second electrode of the second transistor is connected to the output terminal for outputting the driving current.

US Pat. No. 10,170,039

METHOD FOR CORRECTING DISPLAY DEVICE AND CORRECTION DEVICE FOR DISPLAY DEVICE

JOLED INC., Tokyo (JP)

1. A method for correcting a display device including:a display panel having display pixels,
a first memory that stores cumulative values of pixel signals included in a video signal,
a second memory having a slower write speed than a write speed of the first memory, and
a control unit that controls display of the display panel, the method to be performed by the control unit, comprising:
performing cumulative processing for calculating the cumulative values repeatedly in every first period and storing the cumulative values in the first memory in every the first period;
performing transfer processing for transferring the cumulative values from the first memory to the second memory in every second period longer than the first period;
delaying timing of the transfer processing in one part of the display pixels from timing of the transfer processing in the other part of the display pixels according to the write speed of the second memory;
for each of the display pixels, reading a cumulative value from the first memory and correcting a corresponding pixel signal; and
delaying start timing of the cumulative processing in the one part of the display pixels according to the timing of the transfer processing.

US Pat. No. 10,170,038

ORGANIC LIGHT EMITTING DIODE DISPLAY

Samsung Display Co., Ltd....

1. An organic light emitting diode display, comprising:a substrate;
a scan line and a previous stage scan line on the substrate and configured to transmit scan signals;
a data line and a driving voltage line crossing the scan line and configured to transmit a data voltage and a driving voltage, respectively;
an initialization transistor connected to the previous stage scan line and the driving voltage line, and comprising an initialization drain electrode connected to a driving gate electrode of a driving transistor;
a compensation transistor connected to the scan line and comprising a compensation drain electrode connected to the initialization drain electrode; and
an organic light emitting diode electrically connected to the driving transistor,
wherein at least one of the initialization transistor and the compensation transistor comprises a plurality of gate electrodes,
wherein the initialization transistor comprises:
a first initialization transistor comprising a first initialization channel, a first initialization gate electrode, a first initialization source electrode, and a first initialization drain electrode; and
a second initialization transistor comprising a second initialization channel, a second initialization gate electrode, a second initialization source electrode, and a second initialization drain electrode,
a third initialization transistor comprising a third initialization channel, a third initialization gate electrode, a third initialization source electrode, and a third initialization drain electrode, and
a fourth initialization transistor comprising a fourth initialization channel, a fourth initialization gate electrode, a fourth initialization source electrode, and a fourth initialization drain electrode.

US Pat. No. 10,170,034

GRAPHENE DISPLAY, A DRIVING METHOD FOR A GRAPHENE DISPLAY AND A DRIVING APPARATUS

Shenzhen China Star Optoe...

1. A graphene display wherein the graphene display comprising a display panel and a driving apparatus electrically connected to the display panel, the display panel comprising a plurality of pixels distributed in array type and each of the pixels is consisted of three dynamic sub-pixels;wherein the driving apparatus comprising:
an obtaining module to obtaining grayscale values of three primary colors of each of the pixels to be input;
a determination module to determining adjusted grayscale values of the three dynamic sub-pixels of each of the pixels according to the obtained grayscale values of the three primary colors of each of the pixels and a preset correspondence relationship of the obtained grayscale values of the three primary colors and color blocks determined by five primary colors in color gamut;
a driving module to apply driving voltages to the three dynamic sub-pixels respectively corresponding to the adjusted grayscale values of the three dynamic sub-pixels of each of the pixels such that each of the pixels uses the three dynamic sub-pixels thereof to display the adjusted grayscale values of the five primary colors in the color gamut.

US Pat. No. 10,170,026

DETECTION CIRCUITS AND DETECTION METHODS OF LIQUID CRYSTAL PANELS

Shenzhen China Star Optoe...

1. A detection circuit of liquid crystal panels, comprising:at least one optical sensor configured to detect brightness of a liquid crystal panel, and to convert the detected brightness into a first voltage;
an operational amplifier configured to amplify the first voltage according to a predetermined ratio to generate a second voltage; and
a comparison circuit configured to compare the second voltage generated by the operational amplifier with a plurality of reference voltages to generate control signals for shutting down power of the liquid crystal panel;
wherein the comparison circuit comprises:
a first comparator that is configured to compare the second voltage with a first reference voltage;
a first switch that is turned on or off in accordance with first control signals outputted by the first comparator;
a second comparator that is configured to compare the second voltage with a second reference voltage;
a second switch that is turned on or off in accordance with second control signals outputted by the second comparator; and
wherein the second reference voltage is greater than the first reference voltage, and the power of the liquid crystal panel is turned off when the first switch is turned on by the first control signals or when the second switch is turned on by the second control signals.

US Pat. No. 10,170,015

EDUCATIONAL MEDIA PLANNING AND DELIVERY FOR IN-CLASS LESSONS WITH LIMITED DURATION

INTERNATIONAL BUSINESS MA...

1. A method comprising:defining a topic for a plurality of students and a time period for presenting the topic to the plurality of students, each of the students in the plurality of students having an associated learning style parameter, the learning style parameter including a learning style information, learning pace information or speed or mastery information;
determining by a computing device a first electronic media from a plurality of electronic media on the topic for each of the students in the plurality of students, the determination of the first electronic media being based on a consumption time of the electronic media, the time period and the associated learning style parameter of each student, the duration of the electronic media being less than the time period;
presenting the first electronic media determined for each student to each student in the plurality of students;
determining a plurality of test questions for each of the first electronic media, and transmitting the plurality of test questions to each of the plurality of students when each student completes the associated first electronic media;
tracking a progress of each student in completing the plurality of test questions during the time period; and
changing a number of test questions in the plurality of test questions when the progress of the student indicates the student will not complete the topic within the time period.

US Pat. No. 10,170,014

DOMAIN-SPECIFIC QUESTION-ANSWER PAIR GENERATION

International Business Ma...

1. A computer-implemented method, the computer-implemented method comprising:retrieving question-answer pairs from a database;
constructing question-answer pair templates, wherein the constructing is based on leveraging domain specific resources and user experiences of a plurality of users; and
eliminating erroneous question-answer pairs from the retrieved question-answer pairs based on specifications of a heuristic process of the constructed templates, wherein the heuristic process is based on a term definition text operation that analyzes question-forming strings and answer-forming strings based on a plurality of glossaries and sentence formulations of the constructed templates.

US Pat. No. 10,170,011

GUIDE DRONES FOR AIRPLANES ON THE GROUND

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method, comprising:meeting, by a drone device operatively coupled to a processor, an aircraft at a first location; and
guiding, by the drone device, the aircraft to a second location along a ground movement path selected from a plurality of ground movement paths associated with an airport, wherein the guiding comprises:
providing a direction indication to the aircraft;
monitoring a defined region around the aircraft for one or more hazards; and
in response to identifying a hazard on the aircraft from the one or more hazards related to the defined region around the aircraft;
providing a hazard indication to the aircraft, and
employ, by the drone device, a tool of the drone device to eliminate the hazard.

US Pat. No. 10,170,003

DYNAMIC PARKING SPACE DEFINITION

INTERNATIONAL BUSINESS MA...

1. A computer-implement method comprising:performing an automated measurement of at least one dimension of an arriving vehicle arriving at a parking area, the arriving vehicle to be parked in the parking area;
obtaining a skills assessment of a driver of the arriving vehicle, the skills assessment indicating skill level of the driver in performing at least one parking maneuver;
dynamically defining a parking space in an unoccupied area within the parking area for the arriving vehicle based at least on the at least one dimension of the arriving vehicle and the obtained skills assessment, the defining comprising allocating the dynamically defined parking space in the unoccupied area, the allocating comprising choosing dimensions for the dynamically defined parking space;
directing the arriving vehicle to the dynamically defined parking space, the directing comprising providing live parking guidance to facilitate maneuvering the arriving vehicle into position in the dynamically defined parking space, wherein the dynamically defined parking space is an initial parking space to which the arriving vehicle is initially directed;
observing the arriving vehicle in maneuvering into the initial parking space;
determining, based on the observing, that the initial parking space is sub-optimal;
based on determining that the initial parking space is sub-optimal, dynamically defining a different parking space in another unoccupied area within the parking area; and
re-directing the arriving vehicle to the dynamically defined different parking space.

US Pat. No. 10,169,998

SYSTEM AND METHOD FOR CONFIGURING LANE NODE TREE

Hyundai Motor Company, S...

1. A system for configuring a lane node tree, the system comprising:a host vehicle; and
a controller disposed in the host vehicle and including a memory configured to store program instructions and a processor configured to execute the stored program instructions, which when executed cause the controller to:
select a driving vehicle detection mode among a plurality of driving vehicle detection modes according to a driving application that is executed by the host vehicle, wherein the plurality of driving vehicle detection modes includes a self-lane mode for detecting a vehicle in a lane in which the host vehicle is present, an opposite lane mode for detecting a vehicle in an opposite lane of the lane in which the host vehicle is present, and a left/right lane mode for detecting a vehicle in a left lane or a right lane with respect to the lane in which the host vehicle is present;
select a lane of a road according to the selected driving vehicle detection mode;
determine whether a neighbor vehicle neighboring the host vehicle is present in the selected lane; and
request a node connection from a neighbor vehicle present in the selected lane when the neighbor vehicle is determined to be present in the selected lane, wherein
when the selected driving vehicle detection mode is the self-lane mode, the controller configures the lane node tree using connection information regarding at least one node received from the neighbor vehicle present in the lane in which the host vehicle is present,
when the selected driving vehicle detection mode is the opposite lane mode, the controller configures the lane node tree using connection information regarding at least one node received from the neighbor vehicle present in the opposite lane of the lane in which the host vehicle is present, and
when the selected driving vehicle detection mode is the left/right lane mode, the controller configures the lane node tree using connection information regarding at least one node received from the neighbor vehicle present in the left lane or the right lane with respect to the lane in which the host vehicle is present.

US Pat. No. 10,169,988

AERIAL DRONE FOR CORRECTING ERRATIC DRIVING OF A VEHICLE

International Business Ma...

1. A computer-implemented method comprising:receiving, by one or more processors and from at least one sensor associated with a vehicle, sensor readings indicating that the vehicle is being operated by a driver in an erratic manner;
computing, by one or more processors, a risk R associated with the driver operating the vehicle in the erratic manner;
determining, by one or more processors, whether the risk R is above a predefined threshold T;
in response to determining that the risk R is above the predefined threshold T, deploying, by one or more processors, an aerial drone to a current location of the vehicle; and
transmitting, by one or more processors, instructions to the aerial drone to perform an action that causes an amelioration of the erratic manner in which the vehicle is being driven.

US Pat. No. 10,169,983

METHOD OF NOISE SUPPRESSION FOR VOICE BASED INTERACTIVE DEVICES

HONEYWELL INTERNATIONAL I...

1. A method comprising:a security system protecting a secured area;
a volume control processor of the security system operating in a standby mode;
an audio device providing audio entertainment within the secured area, wherein the audio device provides the audio entertainment at a volume having a first level;
a wireless interface providing a communication channel between the security system and the audio device, wherein the audio device transmits a registration message to the security system through the wireless interface when the audio device is activated;
a second processor of the security system detecting a security threat within the secured area or detecting a voice command from a second person proximate a control panel of the security system located within the secured area;
the volume control processor entering an active state in response to the second processor detecting the security threat or the voice command;
the second processor providing a voice connection between the control panel and a remotely located central monitoring station in response to the second processor detecting the security threat, thereby facilitating a first person located at the remotely located central monitoring station conversing with the second person;
when in the active state, the volume control processor automatically transmitting a first automatic notification of activation of the voice connection to the audio device that transmitted the registration message in response to the second processor providing the voice connection;
when in the active state, the volume control processor automatically transmitting a second automatic notification to the audio device that transmitted the registration message in response to the second processor detecting the voice command;
a third processor of the audio device receiving the first automatic notification or the second automatic notification from the volume control processor through the wireless interface and automatically reducing the volume of the audio entertainment from the first level to a second level in response to receiving the first automatic notification or the second automatic notification;
the volume control processor automatically transmitting a call termination message to the audio device in response to the voice connection terminating; and
the third processor receiving the call termination message from the volume control processor through the wireless interface and automatically returning the volume of the audio entertainment to the first level in response to receiving the call termination message.

US Pat. No. 10,169,982

SYSTEMS AND METHODS FOR DELAYING OR ACTIVATING A BLOWOUT DEVICE OR A PURGE DEVICE IN A SAMPLING PIPE NETWORK OF AN ASPIRATED SMOKE DETECTION SYSTEM

HONEYWELL INTERNATIONAL I...

1. A system comprising:an aspirated smoke detector;
a sampling pipe coupled to the aspirated smoke detector;
a blowout device coupled to the sampling pipe; and
a delay device coupled to the blowout device,
wherein, responsive to the aspirated smoke detector detecting a triggering event, the aspirated smoke detector transmits a triggering event signal to the blowout device,
wherein, responsive to the blowout device receiving the triggering event signal, the blowout device transmits a delay signal to the delay device, and
wherein, responsive to the aspirated smoke detector receiving the delay signal, the delay device delays the blowout device from performing a blowout action in the sampling pipe by delaying transmission of an activation signal to the blowout device.

US Pat. No. 10,169,980

PORTABLE SECURITY BIN

USA Technologies, Inc., ...

1. A portable security bin comprising:a closed, lockable enclosure;
a receiving slot in the enclosure that receives secure material;
a contents height sensor that measures a height of the secure material in the enclosure; and
an electronic bin controller, comprising:
a short-range radio;
a long-range radio;
a processor;
non-volatile memory;
a non-volatile bin controller ID; a time-base;
wherein the electronic bin controller:
periodically monitors, at a first time interval, the height of the secure material;
periodically listens, at a second time interval, to receive, via to the short-range radio, a first radio beacon, wherein the first radio beacon comprises a first broadcast radio ID;
determines a first bin-distance, wherein the first bin-distance is a distance between the bin and a first broadcast radio, responsive to the short-range radio;
selects one of three mutually exclusive bin security states: (a) a home state, (b) a caution state, or (c) a warning state; responsive to the first bin-distance;
sends a bin-security message, via the long-range radio, responsive a change in the security state, comprising the bin security state; and
periodically transmits, at a third time interval, a bin-status message, comprising: (a) the bin controller ID, (b) the first broadcast radio ID, and (c) the height of the secure material; and
wherein the bin controller is affixed to the enclosure.

US Pat. No. 10,169,972

METHOD AND SYSTEM FOR MONITORING THE SAFETY OF FIELD WORKERS

Blackline Safety Corp., ...

1. A worker safety device comprising:a manually actuable device usable by the worker to indicate a need for assistance, wherein the manually actuable device is a retained mechanical lever configured be actuable from a normal position to a help request position only by being moved outward and away from the safety device, and the retained mechanical lever comprises a detent configured to allow a user's finger to flip the mechanical lever outward;
a gas sensor configured to detect gas in the environment of the worker;
a processor programmed to obtain information from said manually actuable device and the gas sensor to determine worker status;
a communication system controlled by the processor for communicating worker status data to a remote server, wherein the worker status data comprises information generated by the gas sensor;
wherein the safety device is configured to wirelessly communicate an emergency alert comprising the worker status data to the remote server when the mechanical lever moved from the normal position to the help request position.

US Pat. No. 10,169,968

MULTI-LAYER STACK WITH EMBEDDED TAMPER-DETECT PROTECTION

INTERNATIONAL BUSINESS MA...

1. A tamper-respondent assembly comprising:a multi-layer stack comprising multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers;
a tamper-respondent electronic circuit structure embedded within the multi-layer stack, the tamper-respondent electronic circuit structure comprising at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack, the tamper-respondent electronic circuit structure defining a secure volume within the multi-layer stack; and
wherein the tamper-respondent electronic circuit structure is embedded within the multi-layer stack, and the secure volume resides fully within the multi-layer stack.

US Pat. No. 10,169,964

METHOD OF ACTIVATING A SUPPLEMENTAL VISUAL WARNING SIGNAL BASED ON FREQUENCY EMITTED FROM A GENERATOR OF A PRIMARY AUDIBLE WARNING SIGNAL

International Business Ma...

1. A system to activate supplemental signals in response to primary signals, the system comprising:a plurality of first signal devices for generating the primary signals, each of the first signal devices being associated with one of a plurality of defined areas to generate one of the primary signals to indicate specified events associated with said one of the plurality of defined areas;
a plurality of second signal devices for generating the supplemental signals, each of the second signal devices being associated with one of the defined areas;
a multitude of wireless transceivers, each of the transceivers having a plurality of settable operating frequencies for communicating with at least one of the first signal devices and at least one of the second signal devices; and
a computer for configuring the multitude of wireless transceivers by determining a specified frequency for each of the wireless transceivers to associate each of the defined areas with one of the transceivers; wherein when one of the first signal devices associated with the one of the defined areas generates one of the primary signals to indicate one of the specified events relating to the one of the defined areas, said one of the first signal devices sends an activation signal to the one of the transceivers associated with said one of the areas, and said one of the transceivers is activated by the activation signal, and in response, the one of the transceivers activates one or more of the second signal devices associated with said one of the defined areas to generate one or more of the supplemental signals to confirm that said one of the first signal devices has generated one of the primary signals to indicate the one of the specified events related to said one of the defined areas; and
wherein the computer communicates with a global timing system to provide an automatic alert signal based on a synchronized time.

US Pat. No. 10,169,955

GAME WORLD SERVER DRIVEN TRIGGERING FOR GAMBLING HYBRID GAMING SYSTEM

Gamblit Gaming, LLC, Gle...

1. A gaming system for providing a gambling hybrid game that includes an entertainment game and a gambling game, comprising:a processing device constructed to:
execute the entertainment game, wherein the entertainment game updates a value for each entertainment game variable in a set of entertainment game variables and the set of entertainment game variables represents a state of the entertainment game, including at least one continuous variable;
display a user interface for the entertainment game;
communicate, to a game world server, a signal including a trigger of a wager based upon a comparison of a value of the continuous variable to a threshold value;
communicate, to the game world server, a signal including the value for each entertainment game variable in the set of entertainment game variables;
receive, from the game world server, a signal including a result of the wager;
display the result of the wager via the user interface for the entertainment game;
display an amount of intermediate in-game user resources that may be used to purchase or enable in-game resources based on the result of the wager via the user interface for the entertainment game;
and
receive, from the game world server, a signal including a change in the set of entertainment game variables;
a real world server constructed to:
receive, from the game world server, the signal including the trigger of the wager;
receive, from the game world server, a signal including the value for each entertainment game variable in the set of entertainment game variables;
determine the result of the wager using a random number generator and the signal including the value for each entertainment game variable in the set of entertainment game variables;
communicate, to the game world server, the signal including the result of the wager;
and
communicate, to the game world server, the result of the wager; and
the game world server, connected to the processing device via a network and connected to the real world server via a communication link, constructed to:
continuously monitor the processing device for the signal including the trigger of the wager;
receive, from the processing device, the signal including the trigger of the wager;
receive, from the processing device, the signal including the value for each entertainment game variable in the set of entertainment game variables;
determine the wager is triggered based upon the signal including the value for each entertainment game variable in the set of entertainment game variables;
communicate, to the real world server, the signal including the trigger of the wager;
communicate, to the real world server, the signal including the value for each entertainment game variable in the set of entertainment game variables;
receive, from the real world server, the signal including the result of the wager;
calculate the amount of intermediate in-game user resources that may be used to purchase or enable in-game resources based on the result of the wager;
communicate, to the processing device, the signal including the result of the wager and the amount of intermediate in-game user resources;
determine the change to the set of entertainment game variables based upon the result of the wager; and
communicate, to the processing device, the signal including the change to the set of entertainment game variables.

US Pat. No. 10,169,951

GAMING MACHINE WITH RUNS OF SYMBOLS

KONAMI GAMING, INC., Las...

1. A gaming machine, comprising:a memory device configured to store data representing a plurality of symbols and a plurality of reels for use during a game, each reel of the plurality of reels including a plurality of symbol containing elements, each symbol containing element configured to display a symbol, the plurality of reels including a first reel and a second reel, each of the first reel and the second reel including a consecutive run of symbol containing elements configured to display an identical symbol;
a display device configured to display a game screen; and
a game controller for executing a play of the game, the game controller including a microprocessor programmed to:
generate the plurality of reels for use during the play of the game by:
generating the first reel including randomly selecting a first identical symbol and inserting the first identical symbol into each symbol containing element of the consecutive run of symbol containing elements of the first reel prior to a spin of the first reel; and
generating the second reel including randomly selecting a second identical symbol and inserting the second identical symbol into each symbol containing element of the consecutive run of symbol containing elements of the second reel prior to a spin of the second reel;
display the plurality of reels on the game screen and spin the plurality of reels including the first reel having the selected first identical symbol in each symbol containing element of the consecutive run of symbol containing elements included in the first reel and the second reel having the selected second identical symbol in each symbol containing element of the consecutive run of symbol containing elements included in the second reel; and
stop the plurality of reels to display an outcome of the play of the game.

US Pat. No. 10,169,950

REMOTE CONTENT MANAGEMENT AND RESOURCE SHARING ON A GAMING MACHINE AND METHOD OF IMPLEMENTING SAME

IGT, Las Vegas, NV (US)

1. A gaming system comprising:at least one display device;
at least one processor; and
at least one memory device which stores a plurality of instructions, which when executed by the at least one processor, cause the at least one processor to:
enable a placement of a wager on a play of a game, for the wagered on play of the game:
determine a game outcome from a plurality of game outcomes,
cause the at least one display device to display, in a game window controlled by the at least one processor, the determined game outcome,
determine any award associated with the displayed game outcome, and
cause the at least one display device to display any determined award associated with the displayed game outcome, and
after a determination occurs to allocate control of a first resource of the at least one display device to a remote host executing remote host software, cause a display, in a first service window controlled by the remote host which is distinct from the at least one processor, of at least one of: an available player service and an available function, wherein said determination to allocate control of the first resource of the at least one display device to the remote host occurs based on a usage of the at least one processor.

US Pat. No. 10,169,942

DOOR LOCK SENSOR AND ALARM

Schlage Lock Company LLC,...

1. A system for generating an alarm associated with acceleration of a door, the system comprising:a door lock mechanism installed with a door panel that includes a lock and permits entry through the door based on a status of the lock;
at least one accelerometer coupled to the door lock mechanism and configured to detect motion of the door; and
a controller configured to:
determine whether an initial acceleration detected by the at least one accelerometer during a first period of time of the door being in motion is less than an acceleration threshold of the door, wherein the acceleration threshold is an acceleration that when exceeded by the door is indicative of a forced entry; and
maintain the alarm associated with the door lock mechanism in a deactivated state when the initial acceleration of the door detected by the at least one accelerometer is less than the acceleration threshold.

US Pat. No. 10,169,939

IDENTITY RECOGNITION

International Business Ma...

1. A computer-implemented method comprising:receiving, by a user device of a first user, identification data comprising a universally unique identifier (UUID) that is associated with a security database of a second user and a first security token associated with the second user;
verifying, by the user device, the received identification data by utilizing the UUID to access the security database that purportedly issued the UUID and verifying that the first security token matches a second security token generated by the security database;
responsive to verifying the received identification data, disarming a security system associated with the user device for a specified time period;
detecting the presence or absence of the second user;
confirming whether the second user has completed a task associated with the first security token; and
responsive to detecting the absence of the second user and confirming whether the second user has completed the task, automatically re-arming the security system associated with the user device after the specified time period expires.

US Pat. No. 10,169,930

VEHICLE LIFT CONFIGURED FOR INTEGRATION WITH VEHICLE DIAGNOSTIC COMPUTING DEVICES

Gray Manufacturing Compan...

1. A vehicle lift comprising:a main housing;
a lift actuator;
a carriage assembly configured to engage a wheel of a vehicle, wherein said lift actuator is configured to vertically shift said carriage assembly relative to said main housing; and
a lift control module configured to control said lift actuator to vertically shift said carriage assembly, wherein said lift control module comprises a graphic display for displaying information related to operation of said vehicle lift;
wherein said vehicle lift is configured to connect with an on-board diagnostic (OBD) system of a vehicle,
wherein said lift control module is configured to obtain vehicle diagnostic information generated by the OBD system of the vehicle and to display, via said graphic display, the vehicle diagnostic information.

US Pat. No. 10,169,927

METHODS AND SYSTEMS FOR MONITORING VEHICLE SYSTEMS USING MOBILE DEVICES

HONEYWELL INTERNATIONAL I...

1. A method of presenting information pertaining to a plurality of mechanical components of a rotorcraft including at least one of a rotor assembly and a drive assembly, the method comprising:initiating, by a client device, an ad hoc wireless connection with a monitoring system onboard the rotorcraft via a wireless network associated with the rotorcraft, wherein the monitoring system onboard the rotorcraft analyzes measurement data obtained during operation of the rotorcraft corresponding to operational characteristics of one or more of the plurality of mechanical components of the rotorcraft and generates a status summary file including status summary data indicative of a health of each respective mechanical component of the plurality of mechanical components based at least in part on the measurement data, the measurement data corresponding to operational characteristics of the one or more mechanical components of the at least one of the rotor assembly and the drive assembly during flight;
requesting, by the client device via the ad hoc wireless connection, the status summary file from the monitoring system;
receiving, by the client device, the status summary file from the monitoring system via the ad hoc wireless connection, the monitoring system providing the status summary file in response to the client device requesting the status summary file;
processing, by the client device, the status summary data of the status summary file to present graphical representations of the health of each respective mechanical component of the at least one of the rotor assembly and the drive assembly of the rotorcraft on the client device; and
providing, on the client device, an indication the rotorcraft is cleared for further operation when the status summary data indicates the plurality of mechanical components are healthy.

US Pat. No. 10,169,926

DRIVER ASSISTANCE SYSTEM FOR VEHICLE

MAGNA ELECTRONICS INC., ...

1. A method for providing backup assistance for a driver of a vehicle, said method comprising:providing a rear backup camera at a vehicle so as to have a field of view at least rearward of the vehicle;
providing a processor at the vehicle;
storing a plurality of sets of overlays in memory, wherein each set of the stored plurality of sets of overlays is associated with a respective vehicle wheelbase configuration of a plurality of different vehicle wheelbase configurations;
providing a wheelbase configuration input to the processor that is representative of the vehicle wheelbase configuration of the vehicle;
selecting, via the processor, and responsive at least in part to the wheelbase configuration input, a particular set of stored overlays from the stored plurality of sets of overlays, wherein the selected set of stored overlays comprises a plurality of individual predicted vehicle trajectory overlays that correspond to respective steering angle ranges for the vehicle wheelbase configuration of the vehicle; and
selecting, via the processor, and responsive at least in part to a steering angle of the vehicle during a reversing maneuver of the vehicle, an individual predicted vehicle trajectory overlay of the selected set of stored overlays for displaying at a display of the vehicle for viewing by a driver of the vehicle during the reversing maneuver of the vehicle.

US Pat. No. 10,169,898

METHOD FOR GENERATING SCREENSHOT IMAGE ON TELEVISION TERMINAL AND ASSOCIATED TELEVISION

HISENSE ELECTRIC CO., LTD...

1. A method for generating a screenshot image on a television (TV) terminal, comprising:upon receiving a screenshot request, acquiring a first layer range of at least one On Screen Display (OSD) sub-layer corresponding to an application displayed on an OSD layer, wherein a second layer range is at outer side of the first layer range; and
in response to the at least one OSD sub-layer in the first layer range comprises an opaque layer, generating the screenshot image by taking a snap shot of the opaque layer and other layers at the outer side of the opaque layer within the first layer range, wherein an OSD sub-layer in the first layer range is an Activity layer for displaying the application, and an OSD sub-layer in the second layer range is a layer for displaying system notification information, and wherein the OSD sub-layers in the second layer range for displaying system notification information is not taken a snap shot for generating the screenshot image.

US Pat. No. 10,169,896

REBUILDING IMAGES BASED ON HISTORICAL IMAGE DATA

International Business Ma...

1. A method comprising:receiving, over a network and from a mobile device, a marked-up digital photograph of a scene including a partially-obscured target object including an obscured portion and an unobscured portion, the marked-up digital photograph being received along with associated aspect metadata and geolocation metadata, wherein the marked-up digital photograph and associated aspect metadata and geolocation metadata are generated by the mobile device by:
capturing, by a digital camera of the mobile device, a digital photograph;
obtaining, using a global positioning system (GPS) device of the mobile device, the geolocation metadata, wherein the geolocation metadata indicates a geographic location where the digital photograph was captured;
obtaining, using a gyroscope of the mobile device, photograph angle metadata, wherein the photograph angle metadata indicates an angle at which the digital camera was positioned when the digital photograph was captured;
obtaining, using a range finder of the mobile device, object distance metadata, wherein the object distance metadata indicates a distance from the digital camera to the partially-obscured target object when the digital photograph was captured;
obtaining, by the mobile device, exposure metadata, wherein the exposure metadata indicates aperture of the digital camera, shutter speed of the digital camera, and a measure of an amount of ambient light present when the digital photograph was captured;
associating, by the mobile device and responsive to the capture of the digital photograph, the aspect metadata and the geolocation metadata with the digital photograph, wherein the aspect metadata includes the photograph angle metadata, the object distance metadata, and the exposure metadata; and
receiving, via selection tools on a graphical user interface (GUI) of the mobile device, a first user selection indicating a flawed portion of the scene in the digital photograph, the flawed portion including the partially-obscured target object and a second user selection indicating, within the flawed portion, the unobscured portion of the partially-obscured target object, wherein mobile device marks up the digital photograph based on the first user selection and the second user selection;
querying, based on the geolocation metadata, a repository of a set of images, to identify a reduced subset of the set images, wherein each image in the reduced subset has corresponding geolocation metadata, such that an amount of time and computing resources required to analyze images is reduced;
generating, based on the mark-up of the digital photograph in accordance with the second user selection, a digital fingerprint of the unobscured portion in the digital photograph;
comparing the digital fingerprint of the unobscured portion to digital fingerprints generated based on images in the reduced set; and
determining, based on the comparison, whether there are any suitable replacement images of the obscured portion of the partially-obscured target object in the reduced set,
wherein responsive to determining that there is no suitable replacement images of the obscured portion, the method further comprises:
modifying the digital photograph by repairing the obscured portion without utilizing any of the images in the reduced set in the repair; and
transmitting the modified digital photograph to the mobile device, and
wherein responsive to determining that there is at least one suitable replacement image of the obscured portion, the method further comprises:
modifying the digital photograph by replacing the obscured portion in the digital photograph with a replacement portion taken from the at least one suitable replacement image and using morphing algorithms to blend, based on the photograph angle metadata, the object distance metadata, and the exposure metadata, the replacement portion with a remainder of the digital image; and
transmitting the modified digital photograph to the mobile device.

US Pat. No. 10,169,887

ACCELERATED BLITS OF MULTISAMPLED TEXTURES ON GPUS

Apple Inc., Cupertino, C...

1. A non-transitory program storage device comprising instructions stored thereon to cause one or more processors to:determine that a number of samples in a first row of multisampled pixels in a source memory exceeds a maximum row stride of a destination memory, wherein the source memory comprises a two-dimensional memory buffer having a first number of rows of multisampled pixels and a second number of columns of multisampled pixels, wherein the multisampled pixels in the source memory are sampled using a first sample count, and wherein the destination memory comprises a one-dimensional memory buffer of pixel sample information; and
in response to determining that the number of samples in the first row of multisampled pixels in the source memory exceeds the maximum row stride of the destination memory:
create a texture view of the destination memory, wherein the texture view comprises a two-dimensional representation of the destination memory, the texture view having a third number of rows of pixel sample information and a fourth number of columns of pixel sample information, and wherein a row stride of the texture view equals the maximum row stride;
determine that a first portion of the samples in the first row of multisampled pixels in the source memory corresponds to a first row of the texture view of the destination memory;
determine that a second portion of the samples in the first row of multisampled pixels in the source memory corresponds to a second row of the texture view of the destination memory;
write the first portion of the samples in the first row of multisampled pixels in the source memory to a location corresponding to the first row of the texture view of the destination memory; and
write the second portion of the samples in the first row of multisampled pixels in the source memory to a location corresponding to the second row of the texture view of the destination memory, wherein a row number of the first row of multisampled pixels in the source memory is different than a row number of the second row of the texture view of the destination memory.

US Pat. No. 10,169,878

SYSTEM AND METHOD FOR SEGMENTATION OF THREE-DIMENSIONAL MICROSCOPE IMAGES

Molecular Devices, LLC, ...

1. A computer implemented system to segment an image, comprising:an image capture device; and
one or more processors connected to memory and configured to:
receive the image captured by the image capture device;
identify one or more pixels that are associated with an object;
select at least one marker pixel from the one or more pixels that are associated with the object, the marker pixel representing an approximate center of the object; and
segment the object from the background of the captured based at least in part on a distance metric between a particular pixel of the one or more pixels and the marker pixel.

US Pat. No. 10,169,858

SYSTEM AND METHOD FOR AUTOMATED COSMETIC INSPECTION OF ELECTRONIC DEVICES

1. An image capture unit device configured to capture images of an electronic device, the image capture unit device comprising:a camera configured to capture still or video images of the electronic device
a processor for controlling the camera and processing of images;
a control arm configured to grip the electronic device to be imaged and rotate the electronic device in at least one direction to allow multiple surfaces of the electronic device to be imaged;
a control arm logic for directing the control arm to move the electronic device to be imaged from multiple views and angles; and
a memory for storing captured images and storing camera control logic, wherein the camera control logic comprises instructions that in operation cause the processor to:
receive instructions to capture images of specified dimensions associated with the electronic device;
direct the camera to capture images according to the specified dimensions;
determine if a portion of the electronic device is obstructed in the captured images;
if obstruction is determined to be present, coordinate placement of the electronic device and re-grasp the electronic device to capture additional, unobstructed images;
identify components of the electronic device utilizing the captured images;
compare component images of the identified components of the electronic device with baseline images associated with each of the identified components; and
display information regarding the comparison of the images of the electronic device to a user, wherein the information comprises an indication of a defective component of the identified components of the electronic device and a recommendation to repair the defective component based on a comparison of the component images with the baseline images.

US Pat. No. 10,169,844

LENS DISTORTION CORRECTION USING A NEUROSYNAPTIC CIRCUIT

International Business Ma...

1. A neurosynaptic circuit comprising:a plurality of neurosynaptic core circuits that:
perform image distortion correction by converting a source image to a destination image by:
taking as input a sequence of image frames of a video with one or more channels per frame, and converting dimensions and pixel distortion coefficients of each frame as one or more corresponding neuronal firing events;
mapping each distorted pixel to zero or more undistorted pixels by processing each neuronal firing event corresponding to each pixel of each image frame; and
processing corresponding pixel intensity values of each distorted pixel to output undistorted pixels for each image frame as neuronal firing events for a spike representation of the destination image.

US Pat. No. 10,169,839

METHOD AND APPARATUS FOR EXECUTING GRAPHICS PIPELINE

SAMSUNG ELECTRONICS CO., ...

1. A method comprising:executing a graphics pipeline by a graphics processor coupled to a memory, the executing comprising:
while executing the graphics pipeline on a current frame, receiving properties of an object included in a following frame;
determining whether a time benefit is obtainable if a pre-process of the object in the following frame is performed, the time benefit being obtainable when:
N×f×(Tc/Tr)>1,
where N represents a number of passes in a rendering process when executing the graphics pipeline, f represents usage frequency of the object that is to be pre-processed, Tc represents a time taken for a controller to transform a property of the object, and Tr represents a time taken for a renderer to transform a property of the object;
performing the pre-process, when it is determined that the time benefit is obtainable, otherwise skipping the pre-process; and
executing, when the pre-process is to be performed, the graphics pipeline for the following frame by using the transformed property of the object.

US Pat. No. 10,169,834

CONSERVATION DEVICE, SYSTEM AND METHOD

1. An energy monitoring and conservation system for a building, comprising:a support network for encouraging energy saving habits, comprising;
a processor that is connected with a communication network;
a plurality of smart circuit monitors that are connected with power lines wherein each measures power usage through the respective power line, and each is communicatively connected to the processor by way of the communication network;
a plurality of first smart sockets connected with the power lines in the building via wall outlets that are permanently connected with the building, the plurality of first smart sockets in communication with the processor by way of the communication network, the plurality of first smart sockets associated with a first user group;
a plurality of second smart sockets connected with the power lines in the building via wall outlets that are permanently connected with the building, the plurality of second smart sockets in communication with the processor by way of the communication network, the plurality of second smart sockets associated with a second user group;
a first display associated with the first user group, the first display being connected with the processor by way of the network; and a second display associated with the second user group, the second display being connected with the processor by way of the network; wherein each smart socket has a male portion that plugs into the respective wall outlet, and has plural female portions that accept male portions of power consumption devices, and the smart socket measures power consumption of the power consumption devices in congregate or individually; wherein the plurality of first smart sockets transmits information relating to power consumption of the power consumption devices plugged into the plurality of first smart sockets to the processor by way of the network;
wherein the first display is a computer monitor that is connected with a computer, the computer connecting with the processor by way of the network;
wherein the second display is a computer monitor that is connected with a computer, the computer connecting with the processor by way of the network;
wherein the first user group comprises at least two users forming a first team of users, wherein a first user who is selected because they are identified as using a first amount of energy and a second user who is selected because they are identified as using a second amount of energy that is lower than the first amount of energy, and the second group comprises at least two users forming a second team of users, wherein a third user who is selected because they are identified as using a third amount of energy and a fourth user who is selected because they are identified as using a fourth amount of energy that is lower than the third amount of energy;
the first display showing data relating to consumption of the first user compared to consumption of the second user within the first user group, and the first user group's consumption with respect to the second user group's consumption, to effect change in the first user group's behavior and reduce the first user group's consumption by fostering competition and accountability;
the second display showing data relating to consumption of the third user compared to consumption of the fourth user within the second user group, and the second user group's consumption with respect to the first user group's consumption to effect change in the second user group's behavior and reduce the second user group's consumption by fostering competition and accountability;
and
a reward scheme coupled with a deterrent scheme within the support network, wherein the reward scheme provides a reward to individual users and teams using reduced amounts of energy, and the deterrent scheme removes a reward and allows removal of users from teams when if they are not using reduced amounts of energy.

US Pat. No. 10,169,832

METHOD AND INSTRUMENTATION FOR SUSTAINABLE ENERGY LOAD FLOW MANAGEMENT SYSTEM PERFORMING AS RESILIENT ADAPTIVE MICROGRID SYSTEM

Instant Access Networks, ...

1. A system and method of managing microgrids using Observer, Resource Estimator, Simulator, Scheduler, and Controller routines each considered as a separate virtual device created in the computer software as separate functions, comprising the steps of:using a processor of a computing device to check collected processed data to determine the status of the micro-grid;
using the processor to determine if an electric battery bank is full, and if so then to command channelling excess energy to be stored in non-electrical form;
using the processor to determine if a secondary energy storage system is full, and if so then to command diverting power into dummy loads;
if the battery bank is not full, then using the processor to determine the likely available energy given weather data collected and weather forecasted in an observer routine, the step using a resource estimator routine to determine an amount of likely available energy required for an adequate level of electric storage, and then to:
i) run a load scheduler which limits use of deferrable loads by sending signals from a controlling computer to turn off deferrable loads according to priorities until a simulation indicates an adequate level of electric storage;
ii) then, if the level of electric storage is not indicated to be adequate, command on the use of the secondary energy storage system; then,
iii) provide alarms and alerts to the system management system showing the use of the energy storage system; then,
iv) check the rate of the energy storage system and continue to use the auxiliary energy system until the rate changes in order to meet the adequate level of electric storage;
v) compare an amount of energy reserve in the secondary storage system and the observer routine to determine projected power coming into the system, and using the resource estimator routine to determine the amount of time the auxiliary storage system will provide the needed amount of energy and provide alerts and alarms to the system management system;
using the processor to determine if the auxiliary energy storage system continues to discharge, and if so then, determine priorities of critical loads and begin to reduce the critical loads, maintaining the power management and alert system as the most critical load; then
continue to send alarms and alerts to the management system;
using the processor to determine if the auxiliary management system continues to discharge at an unacceptable rate, and if so then begin the final safe and orderly shut down of the system while maintaining a minimum of power and system management of the system;
wherein each of the above steps utilizes at least one particular machine, said at least one particular machine comprising a computer and related industrial controls necessary to adjust power sources, storage systems and power using applications.