US Pat. No. 10,141,480

LIGHT EMITTING DIODE CHIP HAVING DISTRIBUTED BRAGG REFLECTOR AND METHOD OF FABRICATING THE SAME

Seoul Viosys Co., Ltd., ...

1. A method of fabricating a light emitting diode chip, the method comprising:forming a light emitting structure on a first surface of a substrate, the light emitting structure comprising:
a first conductive-type semiconductor layer;
a second conductive-type semiconductor layer; and
an active layer disposed between the first conductive-type semiconductor layer and the second conductive-type semiconductor layer;
removing a portion of the substrate by grinding a second surface of the substrate;
after the grinding, reducing the surface roughness of the second surface of the substrate by lapping the substrate; and
forming a distributed Bragg reflector on the second surface of the substrate,
wherein the distributed Bragg reflector comprises a first material layer comprising TiO2, a second material layer comprising SiO2, a third material layer comprising TiO2, and a fourth material layer comprising SiO2, and
wherein the first material layer has an optical thickness that is different from an optical thickness of the third material layer.

US Pat. No. 10,141,468

METHOD AND APPARATUS FOR A THERMOPHOTOVOLTAIC CELL

Atrius Energy, Inc., Hun...

1. A thermophotovoltaic cell, comprising:a PN junction comprising a p-type semiconductor layer, wherein said p-type semiconductor layer further comprises chromium oxide;
a passivation layer; and
a pair of opposing conductive current collectors;
wherein said PN junction and said passivation layer are positioned between said pair of opposing conductive current collectors.

US Pat. No. 10,141,439

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first GaN based semiconductor layer of a first conductive type;
a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, the second GaN based semiconductor layer having an impurity concentration of the first conductive type lower than that of the first GaN based semiconductor layer;
a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer;
a fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, the fourth GaN based semiconductor layer having the impurity concentration of the first conductive type higher than that of the second GaN based semiconductor layer;
a gate insulating film provided on the second GaN based semiconductor layer, the third GaN based semiconductor layer, and the fourth GaN based semiconductor layer;
a gate electrode provided on the gate insulating film;
a first electrode provided on the fourth GaN based semiconductor layer;
a second electrode provided at a side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer;
a third electrode provided on the second GaN based semiconductor layer; and
a plurality of fifth GaN based semiconductor layers of the second conductive type provided above a part of the second GaN based semiconductor layer, the plurality of fifth GaN based semiconductor layers surrounding the first electrode and the third electrode, the plurality of fifth GaN based semiconductor layers being provided to be separated from each other, the plurality of fifth GaN based semiconductor layers having substantially the same impurity concentration of the second conductive type as the third GaN based semiconductor layer;
wherein the first electrode is provided in a groove having a bottom-face and side-faces, the third GaN based semiconductor layer is exposed to the bottom-face, the fourth GaN based semiconductor layer is exposed to the side-faces, and the first electrode is in contact with the third GaN based semiconductor layer.

US Pat. No. 10,141,434

COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

Huawei Technologies Co., ...

1. A complementary tunneling field effect transistor, comprising:a first drain region and a first source region disposed on a substrate, wherein the first drain region and the first source region comprise a first dopant;
a first channel disposed on the first drain region and a second channel disposed on the first source region;
a second source region disposed on the first channel and a second drain region disposed on the second channel, wherein the second source region and the second drain region comprise a second dopant;
a first epitaxial layer disposed on the first drain region and the second source region, and a second epitaxial layer disposed on the second drain region and the first source region, wherein the first epitaxial layer covers a side wall of the first channel and the second source region, and the second epitaxial layer covers a side wall of the second channel and the second drain region;
a first gate stack layer disposed on the first epitaxial layer, and a second gate stack layer disposed on the second epitaxial layer;
a first isolator disposed on the second source region and the first drain region, and a second isolator disposed on the first source region and the second drain region, wherein the first isolator is in contact with the first epitaxial layer and the first gate stack layer, and the second isolator is in contact with the second epitaxial layer and the second gate stack layer; and
wherein the first drain region, the first channel, the second source region, the first epitaxial layer, and the first gate stack layer form a first tunneling field effect transistor, and the second drain region, the second channel, the first source region, the second epitaxial layer, and the second gate stack layer form a second tunneling field effect transistor.

US Pat. No. 10,141,431

EPITAXY SOURCE/DRAIN REGIONS OF FINFETS AND METHOD FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming isolation regions extending into a semiconductor substrate, wherein the forming the isolation regions comprises:
in a common etching process, etching the semiconductor substrate to form two first trenches and a second trench between the two first trenches;
forming a hard mask layer comprising first bottom portions extending to bottoms of the two first trenches, and a second bottom portion extending to a bottom of the second trench;
performing an etching step, wherein both the two first bottom portions and the second bottom portion are exposed to an etchant used in the etching step, and the first bottom portions and portions of the semiconductor substrate directly underlying the first bottom portions are etched to extend the two first trenches down, and the second bottom portion protects a portion of the semiconductor substrate directly underlying the second bottom portion; and
filling the two first trenches and the second trench with a dielectric material to form isolation regions;
recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins;
recessing the semiconductor fins to form recesses;
epitaxially growing a first semiconductor material from the recesses;
etching the first semiconductor material; and
epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.

US Pat. No. 10,141,404

POWER SEMICONDUCTOR DEVICE HAVING FULLY DEPLETED CHANNEL REGION

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current;
a first cell and a second cell, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
a first mesa included in the first cell, the first mesa including a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region;
a second mesa included in the second cell, the second mesa including a second port region having a second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
each of the first mesa and the second mesa being spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and having a total extension of less than 100 nm in the direction, wherein the insulation structure houses:
a control electrode structure for controlling the load current within the first mesa and the second mesa, the control electrode structure being electrically insulated from the first load terminal structure; and
a guidance electrode electrically insulated from the control electrode structure and arranged in between the first mesa and the second mesa,
wherein the control electrode structure is configured to induce an inversion channel within the first channel region and an accumulation channel within the second channel region.

US Pat. No. 10,141,398

HIGH VOLTAGE MOS STRUCTURE AND ITS MANUFACTURING METHOD

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a high-voltage (HV) NMOS structure, comprising:
a source region and a drain region separated from each other;
a channel region disposed between the source region and the drain region, the channel region having a channel direction from the source region toward the drain region;
a gate dielectric disposed on the channel region and on portions of the source region and the drain region; and
a gate electrode disposed on the gate dielectric, the gate electrode comprising:
a first portion of n-type doping; and
two second portions of p-type doping disposed at two sides of the first portion, the two second portions having an extending direction perpendicular to the channel direction;
wherein the HV NMOS structure further comprises:
a substrate;
a first n-type doped region and a second n-type doped region disposed in the substrate and separated from each other;
an isolation structure disposed in the substrate, the isolation structure having a first through opening and a second through opening in the first n-type doped region and the second n-type doped region, respectively;
a first n-type heavily doped region and a second n-type heavily doped region disposed in the first through opening and the second through opening, respectively;
wherein the first n-type doped region and the first n-type heavily doped region are disposed in the source region, and the second n-type doped region and the second n-type heavily doped region are disposed in the drain region.

US Pat. No. 10,141,391

MICROSTRUCTURE MODULATION FOR 3D BONDED SEMICONDUCTOR CONTAINING AN EMBEDDED RESISTOR STRUCTURE

International Business Ma...

11. A method of forming a three-dimensional (3D) bonded semiconductor structure, the method comprising:providing a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and a first metallic pad structure having a columnar grain microstructure embedded in the first bonding oxide layer, and a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and a second metallic pad structure having a columnar grain microstructure embedded in the second bonding oxide layer;
forming a metal resistor structure on a recessed surface of the first metallic pad structure or the second metallic pad structure; and
bonding the first semiconductor structure to the second semiconductor structure, wherein the bonding provides a bonding interface between the first and second bonding oxide layers and another bonding interface between the metal resistor structure and the first metallic pad structure or the second metallic pad structure.

US Pat. No. 10,141,388

DISPLAY DEVICE WITH TRANSISTOR SAMPLING FOR IMPROVED PERFORMANCE

SONY CORPORATION, Tokyo ...

1. An apparatus comprising:a plurality of pixels arranged in a matrix form, each of the pixels including a capacitor, a first transistor, a second transistor, and a light emitting element;
a plurality of first lines that extend along a first direction and connected to the pixels;
a plurality of second line that extend along a second direction and connected to the pixels, the second direction being perpendicular to the first direction;
wherein,
(a) each of the first lines includes a first lower wiring portion, a second lower wiring portion, and an upper wiring portion, and
(b) in each of the first lines:
(i) the upper wiring portion is connected to the first lower wiring portion via a first plurality of contact holes formed in an insulating film, and connected to the second lower wiring portion via a second plurality of contact holes formed in the insulating film,
(ii) the upper wiring portion is on the insulating film,
(iii) the insulating film is on the lower wiring portion,
(iv) the power supply line crosses the first lower wiring portion, and
(v) the second lower wiring portion crosses a corresponding one of the second lines.

US Pat. No. 10,141,384

ORGANIC ELECTROLUMINESCENT PANEL AND LUMINESCENT UNIT

Joled Inc., Tokyo (JP)

1. An organic electroluminescent panel comprising:a plurality of pixels each including a plurality of subpixels, the subpixels each including an organic electroluminescent element, the organic electroluminescent element including a first electrode, a second electrode, and an organic material layer that is provided between the first electrode and the second electrode; and
a plurality of banks that define each of the subpixels in each of the pixels,
the organic electroluminescent element in each of the subpixels being provided in a gap between adjacent two of the plurality of banks, and
the following relational expression being satisfied:
y?0.0001714x2+0.0151429x+0.2914286
where y denotes a height, from a bottom surface of the gap, of a pinning position at which a surface of the organic material layer and one of the banks are in contact with each other, and x denotes a width of the bottom surface of the gap.

US Pat. No. 10,141,375

DISPLAY DEVICE HAVING A SOLAR CELL LAYER

LG Display Co., Ltd., Se...

1. A display device comprising:a first light-emitting area provided on a lower substrate;
a second light-emitting area provided on the lower substrate;
a third light-emitting area provided on the lower substrate;
a solar cell layer provided on an upper substrate facing the lower substrate, the solar cell layer producing power by absorbing light, the solar cell layer including first, second and third organic solar cell layers which are disposed in areas corresponding to the respective first, second and third light-emitting areas,
wherein the solar cell layer includes:
a first electrode provided on the upper substrate;
a hole transporting layer provided between the first electrode and each of the first, second and third organic solar cell lavers,
an electron transporting layer provided the first, second and third organic solar cell layers, and
a second electrode provided on the electron transporting layer and disposed in areas corresponding to the respective first, second and third organic solar cell layers.

US Pat. No. 10,141,371

WIDE BAND GAP DEVICE INTEGRATED CIRCUIT DEVICE

Qromis, Inc., Santa Clar...

1. A device comprising:a plurality of groups of gallium nitride (GaN) epitaxial layers, a combined thickness of the plurality of groups of GaN epitaxial layers greater than ten microns;
mesas etched within at least some groups of the plurality of groups of GaN epitaxial layers;
internal interconnects formed within the mesas;
electrodes formed on at least one of the internal interconnects or the GaN epitaxial layers, the electrodes configuring each group of GaN epitaxial layers of the plurality of groups of GaN epitaxial layers into a GaN device of a plurality of GaN devices; and
external interconnects formed over at least some of the electrodes for connecting the plurality of GaN devices into an integrated circuit.

US Pat. No. 10,141,359

IMAGE SENSOR

HIMAX TECHNOLOGIES LIMITE...

1. An image sensor, comprising:an infrared receiving portion configured to receive infrared, and
a visible light receiving portion configured to receive a visible light, wherein the visible light receiving portion comprises an infrared cutoff filter grid and a color filter;
wherein the infrared cutoff filter grid has a grid structure;
wherein the infrared cutoff filter grid is configured to block the transmission of the infrared laterally passing the color filter;
wherein when viewed in cross section, the infrared cutoff filter grid comprises a base portion having an upper surface, and a plurality of pillar portions extending upwardly from the upper surface of the base portion, each adjacent pair of the pillar portions forming a space therebetween to thereby form a plurality of spaces;
wherein the color filter comprises a red color filter unit, a blue color filter unit, and a green color filter unit, and each of the red color filter unit, the blue color filter unit, and the green color filter unit is filled in one of the spaces;
wherein the visible light receiving portion further comprises a visible light photodiode and an infrared cutoff filter disposed on the visible light photodiode;
wherein the infrared cutoff filter and infrared cutoff filter grid are formed in one-piece.

US Pat. No. 10,141,356

IMAGE SENSOR PIXELS HAVING DUAL GATE CHARGE TRANSFERRING TRANSISTORS

SEMICONDUCTOR COMPONENTS ...

1. An image sensor pixel, comprising:a photodiode that generates charge in response to image light;
a floating diffusion node; and
a charge transferring transistor having a first gate and a second gate, wherein the first gate and the second gate are controlled by respective first and second control lines, wherein the charge transferring transistor is configured to transfer the generated charge from the photodiode to the floating diffusion node, wherein the second control line is configured to modulate a bias applied to the second gate between at least three different voltages, wherein the at least three different voltages include a reset voltage, a transfer voltage, and an intermediate voltage, and wherein the intermediate voltage is dynamically adjusted while the generated charge is transferred from the photodiode to the floating diffusion node to change a conversion gain of the image sensor pixel.

US Pat. No. 10,141,353

PASSIVE COMPONENTS IMPLEMENTED ON A PLURALITY OF STACKED INSULATORS

QUALCOMM Incorporated, S...

1. An integrated circuit apparatus, comprising:a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface;
a first conductor disposed on the first insulator;
a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface;
a second conductor disposed on the second insulator; and
a dielectric layer disposed between the first conductor of the first insulator and the second conductor of the second insulator;
wherein:
a capacitor is formed by the first conductor disposed on the first insulator, the dielectric layer, and the second conductor disposed on the second insulator; and
an inductor is formed on the first insulator and the second insulator.

US Pat. No. 10,141,349

THIN-FILM TRANSISTOR ARRAY, FABRICATION METHOD THEREFOR, IMAGE DISPLAY DEVICE AND DISPLAY METHOD

TOPPAN PRINTING CO., LTD....

1. A thin-film transistor array, comprising:a plurality of thin-film transistors each having a configuration in which a gate electrode, a gate wiring connected to the gate electrode, capacitor electrode, and a capacitor wiring connected to the capacitor electrode are provided on an insulating substrate, with a source electrode and a drain electrode having a gap therebetween and including a semiconductor pattern being formed, in a region overlapping with the gate electrode via a gate insulator film, the semiconductor pattern being covered with a protective layer, two thin-film transistors of the plurality of thin-film transistors being independently formed for each pixel, two source electrodes in each pixel being separately connected to two respective source wirings, two drain electrodes each being directly connected to an electrode of the pixel via respective drain-connecting electrodes,
wherein the thin-film transistor array includes source-connecting electrodes each connecting between the source electrodes of the two thin-film transistors formed for each pixel,
wherein the protective layer is in a stripe pattern and formed along the gate wirings such that the protective layer covers the semiconductor patterns and the source wirings,
wherein the protective layer does not cover a portion of the source-connecting electrodes, and
wherein the thin-film transistor array includes an insulating film that covers the source wirings and the portion of the source-connecting electrodes not covered by the protective layer.

US Pat. No. 10,141,343

OXIDE SEMICONDUCTOR, THIN FILM TRANSISTOR, AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductive layer;
a second conductive layer;
a first insulating layer over the first conductive layer and the second conductive layer;
an oxide semiconductor layer over the first insulating layer;
a third conductive layer electrically connected to the oxide semiconductor layer;
a fourth conductive layer electrically connected to the oxide semiconductor layer; and
a fifth conductive layer over the first insulating layer,
wherein the first conductive layer includes a region functioning as a gate electrode of a transistor,
wherein the second conductive layer includes a region functioning as a first electrode of a capacitor,
wherein the oxide semiconductor layer includes a region functioning as a channel formation region of the transistor,
wherein the third conductive layer includes a region functioning as one of a source electrode and a drain electrode of the transistor,
wherein the fourth conductive layer includes a region functioning as the other one of the source electrode and the drain electrode of the transistor,
wherein the fourth conductive layer is electrically connected to the second conductive layer,
wherein the fifth conductive layer includes a region functioning as a second electrode of the capacitor,
wherein the oxide semiconductor layer includes In, Ga, and Zn, and
wherein a concentration of Zn is lower than a concentration of In or a concentration of Ga.

US Pat. No. 10,141,341

THIN-FILM-TRANSISTOR (TFT) ARRAY PANEL WITH STRESS ELIMINATION LAYER AND METHOD OF MANUFACTURING THE SAME

Shenzhen China Star Optoe...

1. A method for manufacturing a TFT array panel, the TFT array panel comprising:a flexible baseplate;
a buffer layer, disposed on the flexible baseplate, on which a stress-elimination portion for eliminating a stress of the flexible baseplate is disposed;
a display-element layer, disposed on the buffer layer;
wherein the method comprises steps:
A. disposing the buffer layer on the flexible baseplate;
B. disposing the stress-elimination portion on the buffer layer, wherein the stress-elimination portion is used to eliminate a stress of the flexible baseplate;
C. disposing the display-element layer on the buffer layer;
wherein the step B comprises:
b1. Performing a photo-mask process and/or an etching process on the buffer layer, to form the stress-elimination portion;
the stress-elimination portion is disposed on a plane of the buffer layer, and the plane is positioned closer to the display-element layer than a position of one other plane of the buffer layer;
wherein the stress-elimination portion comprises at least one recess and at least one protrusion portion, wherein the at least one recess and the at least one protrusion portion are lined up as a one dimensional array or a two dimensional array.

US Pat. No. 10,141,339

EMBEDDED SECURITY CIRCUIT FORMED BY DIRECTED SELF-ASSEMBLY

International Business Ma...

1. A method, comprising:defining at least two regions of a circuit structure on a substrate, wherein the at least two regions comprise a security region and a non-security region;
forming a guiding pattern on the substrate, wherein the guiding pattern comprises a plurality of raised features formed within the security and non-security regions, wherein the raised features of the guiding pattern formed within the non-security region are separated by a first distinct width, and wherein the raised features of the guiding pattern formed within the security region are separated by a second distinct width;
depositing a self-assembling material comprising at least one of a block copolymer and a block copolymer/homopolymer combination, within spaces between the raised features of the guiding pattern, wherein the self-assembling material comprises block materials that are configured to assemble into a block pattern with a natural pitch;
annealing the self-assembling material to initiate a self-assembly process directed by the plurality of raised features of the guiding pattern, and form block patterns of the block materials within the spaces between the raised features of the guiding pattern; and
selectively removing one of the block materials of the assembled block patterns to define a pattern of fin structures by the remaining block material in the spaces between the raised features of the guiding pattern;
wherein the pattern of fin structures comprises a pattern of unbroken fin structures within the non-security region, and a pattern of broken fin structures within the security region;
wherein the broken fin structures comprise discontinuous regions that are formed due to a dissimilarity between the second distinct width and the natural pitch of the block materials of the self-assembling material.

US Pat. No. 10,141,338

STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

International Business Ma...

1. A FinFET device comprising:a strain relaxation buffer (SRB) substrate;
a set of cut silicon fins on the SRB substrate, each fin in the set of cut silicon fins having a pair of long vertical faces and a pair of short vertical faces, where pairs of the cut silicon fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other;
a set of cut silicon germanium fins on the SRB substrate, each fin in the set of silicon germanium fins having a pair of long vertical faces and a pair of short vertical faces, where pairs of the cut silicon germanium fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other;
a set of tensile dielectric structures, wherein respective ones of the tensile dielectric structures bridge between the short vertical faces of respective pairs of the cut silicon fins to maintain tensile strain at the fin ends of the pair of cut silicon fins; and
a set of compressive dielectric structures, wherein respective ones of the compressive dielectric structure bridge between the short vertical faces of respective pairs of the cut silicon germanium fins to maintain compressive strain at the fin ends of the pair of cut silicon germanium fins.

US Pat. No. 10,141,337

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor comprising a silicon semiconductor layer including a first channel formation region;
an insulating layer comprising a first nitride insulating layer and a second nitride insulating layer over the first transistor;
a second transistor comprising an oxide semiconductor layer including a second channel formation region over the insulating layer; and
a third nitride insulating layer over the second transistor,
wherein the second nitride insulating layer is between the first nitride insulating layer and the oxide semiconductor layer,
wherein a density of the second nitride insulating layer is higher than or equal to 2.75 g/cm3, and
wherein a density of the third nitride insulating layer is higher than or equal to 2.75 g/cm3.

US Pat. No. 10,141,336

POWER GATE SWITCHING SYSTEM

SAMSUNG ELECTRONICS CO., ...

1. A power gate switching system, comprising:a first row including a first virtual power line, a first power gate cell and a second power gate cell, wherein the first power gate cell includes a first gate electrode disposed between first and second diffusion regions, and at least one tab, wherein the second power gate cell includes a second gate electrode disposed between third and fourth diffusion regions and does not include a tab; and
a second row including a second virtual power line, a third power gate cell and a fourth power gate cell, wherein the third power gate cell includes a third gate electrode disposed between fifth and sixth diffusion regions, and at least one tab, and the fourth power gate cell includes a fourth gate electrode disposed between seventh and eighth diffusion regions and does not include a tab, and
wherein the fourth power gate cell is connected to the second power gate cell.

US Pat. No. 10,141,335

SEMICONDUCTOR CIP INCLUDING REGION HAVING RECTANGULAR-SHAPED GATE STRUCTURES AND FIRST METAL STRUCTURES

Tela Innovations, Inc., ...

1. A semiconductor chip, comprising:gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a gate horizontal grid, the gate horizontal grid including at least seven gate gridlines, each gate structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, each gate gridline having at least one gate structure layout shape positioned thereon, wherein adjacently positioned ones of the gate structures are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each of the gate structures having a width of less than or equal to about 45 nanometers, wherein each pair of the gate structures that are positioned in and end-to-end manner are separated from each other by a line end-to-line end gap of less than or equal to about 193 nanometers;
a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, the first-metal structure layout shapes positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each of the first-metal structures having at least one adjacent first-metal structure positioned next to each of its sides at a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the first-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers;
at least six contact structures formed within the region of the semiconductor chip, the at least six contact structures formed in part utilizing corresponding at least six contact structure layout shapes as an input to a lithography process, the at least six contact structures formed in physical and electrical contact with corresponding ones of at least six of the gate structures, each of the at least six contact structure layout shapes having a substantially rectangular shape and a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structure layout shapes positioned and sized to form its corresponding contact structure to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,
wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region, wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit.

US Pat. No. 10,141,334

SEMICONDUCTOR CHIP INCLUDING REGION HAVING RECTANGULAR-SHAPED GATE STRUCTURES AND FIRST-METAL STRUCTURES

Tela Innovations, Inc., ...

1. A semiconductor chip, comprising:gate structures formed within a region of the semiconductor chip, the gate structures positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein adjacent gate gridlines are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each gate structure in the region having a substantially rectangular shape with a width of less than or equal to about 45 nanometers and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate structure positioned thereon, wherein each pair of gate structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers, wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region;
a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure in the region having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each first-metal structure in the region having at least one adjacent first-metal structure positioned next to each of its sides in accordance with a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of first-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers; and
at least six contact structures formed within the region of the semiconductor chip, wherein at least six gate structures within the region have a respective top surface in physical and electrical contact with a corresponding one of the at least six contact structures, each of the at least six contact structures having a substantially rectangular shape with a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structures positioned and sized to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,
wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit, wherein the logic circuit includes electrical connections that collectively include first-metal structures positioned on at least five of the at least eight first-metal gridlines.

US Pat. No. 10,141,331

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SUPPORT PILLARS UNDERNEATH A RETRO-STEPPED DIELECTRIC MATERIAL AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stack comprises a memory array region and a terrace region;
memory stack structures extending through the memory array region of the alternating stack, wherein each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel contacting an inner sidewall of the respective memory film; and
support pillar structures extending through the terrace region of the alternating stack,
wherein the support pillar structures have different heights from each other;
wherein each of the support pillar structures has a respective topmost surface that is coplanar with a top surface of a respective one of the insulating layers in the alternating stack; and
wherein each of the support pillar structures comprises a dummy vertical semiconductor channel that is identical to the vertical semiconductor channels in material composition.

US Pat. No. 10,141,330

METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES, SEMICONDUCTOR DEVICES, AND ELECTRONIC SYSTEMS

Micron Technology, Inc., ...

1. A method of forming a semiconductor device structure, comprising:forming a stack structure comprising stacked tiers, each of the stacked tiers comprising a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure;
forming a patterned hard mask structure over the stack structure;
forming dielectric structures within openings in the patterned hard mask structure;
forming a photoresist structure over the dielectric structures and the patterned hard mask structure;
subjecting the photoresist structure, the dielectric structures, and the stack structure to a series of material removal processes to selectively remove portions of the photoresist structure, portions of the dielectric structures not covered by remaining portions of the photoresist structure, and portions of the stack structure not covered by one or more of the patterned hard mask structure and the remaining portions of the photoresist structure to form apertures extending to different depths within the stack structure;
forming dielectric structures over side surfaces of the stack structure within the apertures, upper surfaces of the dielectric structures substantially coplanar with an upper surface of the patterned hard mask structure; and
forming conductive contact structures longitudinally extending to bottoms of the apertures.

US Pat. No. 10,141,329

METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A method for manufacturing a semiconductor memory device, comprising:forming, in a stacked body including a plurality of first layers and a plurality of second layers each of which is provided between the first layers, a plurality of first holes and a plurality of second holes in which a channel film is to be formed inside the first holes, the first holes and the second holes extending through the stacked body in a stacking direction of the stacked body and being arrayed in a first direction intersecting the stacking direction and in a direction oblique to the first direction;
etching a portion between the second holes next to each other in the stacked body to connect the second holes next to each other in the first direction and the second holes next to each other in the direction oblique to the first direction via the etched portion and form a trench in the stacked body.

US Pat. No. 10,141,328

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three-dimensional (3D) memory device, comprising:a substrate;
a ridge-shaped stack, including a plurality of conductive strips stacked on the substrate along a first direction;
a memory layer, stacked on a vertical sidewall of the ridge-shaped stack along a second direction that forms a non-straight angle with the first direction, and having a first narrow sidewall with a first long side extending along the first direction and a first narrow side extending along the second direction;
a channel layer, stacked on the memory layer along the second direction, the channel layer having a portion recessed in a third direction by an etch back process to form a second narrow sidewall having a second long side extending along the first direction and a second narrow side extending along the second direction, wherein the first narrow sidewall is separated from the second narrow sidewall along the third direction, and the third direction forms a non-straight angle with both the first direction and the second direction; and
a capping layer stacked on the second narrow sidewall along the third direction.

US Pat. No. 10,141,327

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a first insulating layer disposed on a semiconductor substrate;
a first semiconductor layer disposed on the semiconductor substrate;
a plurality of memory cells arranged three-dimensionally above the first insulating layer and disposed above the first semiconductor layer;
a plurality of conductive layers stacked in a first direction that intersects a surface of the semiconductor substrate;
a second insulating layer covering a side surface of a lowermost layer of the plurality of conductive layers;
an oxide layer disposed on a side surface of the first semiconductor layer and contacting the second insulating layer; and
a high permittivity layer provided between the first insulating layer and the second insulating layer, a permittivity of the high permittivity layer being higher than that of the first insulating layer and the high permittivity layer directly contacting the side surface of the first semiconductor layer.

US Pat. No. 10,141,326

SEMICONDUCTOR MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:a peripheral circuit element provided over a lower substrate;
an upper substrate provided over an interlayer dielectric layer which partially covers the peripheral circuit element;
a memory cell array including a channel structure which extends in a first direction perpendicular to a top surface of the upper substrate and a plurality of gate lines which are stacked over the upper substrate to surround the channel structure; and
a plurality of transistors electrically coupling the gate lines to the peripheral circuit element,
the transistors comprising:
a gate electrode provided over the interlayer dielectric layer and disposed to overlap with the memory cell array in the first direction;
a plurality of vertical channels passing through the gate electrode in the first direction and electrically coupled to the gate lines, respectively; and
gate dielectric layers disposed between the vertical channels and the gate electrode.

US Pat. No. 10,141,325

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device comprising steps of:(a) providing a semiconductor substrate;
(b) forming a first resistor element comprised of polycrystalline silicon in a first region of a main surface of the semiconductor substrate;
(c) ion-implanting a first impurity, which is at least one selected from a group consisting of: a group 14 element, nitrogen, and a group 18 element, into the first resistor element; and
(d) after the step (c), forming an insulating film including a charge storage portion in a second region of the main surface of the semiconductor substrate; which is different from the first region;
(e) ion-implanting a second impurity into a third region of the main surface of the semiconductor substrate, which is different from the first and second regions; and
(f) after the step (e), performing a first heat treatment on the semiconductor substrate so as to activate the second impurity,
wherein, during the step (d), or after the step (d) and before the step (e), a second heat treatment is performed on the semiconductor substrate so as to improve a quality of the insulating film, and
wherein the second heat treatment has a longer duration than the first heat treatment.

US Pat. No. 10,141,324

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a semiconductor substrate having a main surface;
a first nonvolatile memory cell and a second nonvolatile memory cell formed on the main surface of the semiconductor substrate;
the first nonvolatile memory cell including a first memory transistor for storing data having a first memory gate electrode and a first select transistor for selecting the first memory transistor having a first select gate electrode; and
the second nonvolatile memory cell including a second memory transistor for storing data having a second memory gate electrode and a second select transistor for selecting the second memory transistor having a second select gate electrode;
wherein the first select gate electrode and the second select gate electrode extend in a first direction so as to be disposed next to each other in a second direction substantially perpendicular to the first direction in a plan view,
wherein the first memory gate electrode extends in the first direction so as to be disposed along a sidewall of the first select gate electrode,
wherein the second memory gate electrode extends in the first direction so as to be disposed along a sidewall of the second select gate electrode,
wherein the first memory gate electrode and the second memory gate electrode are disposed between the first select gate electrode and the second select gate electrode,
wherein the first memory gate electrode has a first contact portion extending in the second direction to provide an electrical contact to a first interconnect,
wherein the second memory gate electrode has a second contact portion extending in the second direction to provide an electrical contact to a second interconnect,
wherein the first contact portion is spaced apart from the second contact portion in the first direction in the plan view, and
wherein a first portion of the first contact portion and a second portion of the second contact portion are overlapped with each other in the second direction in the plan view.

US Pat. No. 10,141,323

NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

16. A non-volatile memory array, comprising:a first pair of memory cell wherein the first pair of memory cell further comprises:
a first MOSFET having a first gate region; and
a second MOSFET having a second gate region; and
a second pair of memory cell adjacent to the first pair of memory cell, wherein the second pair of memory cell includes a third MOSFET having a third gate region and a fourth MOSFET;
wherein the second MOSFET of the first pair of memory cell and third MOSFET of the second pair of memory cell are connected to a same bit line; and
wherein the first gate region and the second gate region of the first pair of memory cell extend over and connect to a first active region providing a first word line and the third gate region of the second pair of memory cell extends over and connects to a second active region providing a second word line different than the first word line.

US Pat. No. 10,141,321

METHOD OF FORMING FLASH MEMORY WITH SEPARATE WORDLINE AND ERASE GATES

Silicon Storage Technolog...

1. A method of forming a non-volatile memory cell comprising:forming, in a substrate of a first conductivity type, spaced apart first and second regions of a second conductivity type, defining a channel region there between;
forming a floating gate disposed over and insulated from a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region;
forming a tunnel oxide layer around the sharp edge;
forming an erase gate over and insulated from the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer; and
forming a word line gate disposed over and insulated from a second portion of the channel region which is adjacent to the second region, wherein the forming of the word line gate is entirely performed after the forming of the tunnel oxide layer and the forming of the erase gate.

US Pat. No. 10,141,320

MULTIPLE-BIT ELECTRICAL FUSES

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a nanosheet stack on a semiconductor substrate, the nanosheet stack comprising alternating layers of a first material and a second material on a substrate;
removing portions of the stack to form tapered stack sidewalls, wherein said sidewalls have a taper angle in relation to a horizontal surface of the substrate, the taper angle extending inward from the semiconductor substrate toward an upper surface of the nanosheet stack; and
converting the second material to a resistive material, wherein the layers comprising the resistive material form one or more electrical fuses,
wherein the taper angle sets a different breakdown voltage for each electrical fuse among the one or more electrical fuses.

US Pat. No. 10,141,319

LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY

UNITED MICROELECTRONICS C...

1. A layout pattern of a static random access memory, comprising:a first inverter and a second inverter cross-coupled for data storage, each inverter including a pull-up device (PL) and a pull-down device (PD);
each inverter comprising a step-shaped structure disposed on a substrate, the step-shaped structure comprising a first part and a second part arranged along a first direction, and a bridge part connected to the first part and the second part, the bridge part is arranged along a second direction, wherein the first direction is perpendicular to the second direction, in addition, the first part is disposed at one side of the bridge part, and the second part is disposed at the opposite side of the bridge part along the first direction, and wherein the first part crosses over a first diffusion region, and the second part crosses over a second diffusion region to form the pull-down device (PD), wherein the first part crosses over a third diffusion region to form the pull-up device (PL);
each inverter has an inverter output, the inverter output connecting a first pass gate structure and a second pass gate structure disposed on the substrate, the first pass gate structure and the first part of the step-shaped structure being arranged along a same direction and comprising a same symmetry axis, the second pass gate structure and the second part of the step-shaped structure being arranged along a same direction and comprising a same symmetry axis, wherein the first pass gate structure crosses over the second diffusion region to form a first pass gate device (PG1), and the second pass gate structure crosses over the first diffusion region to form a second pass gate device (PG2), wherein a drain of the PG1 is connected to a drain of the PG2, and the bridge part of each step-shaped structure of each inverter is disposed between the first pass gate structure and the second pass gate structure; and
each inverter output comprising an extending contact structure at least crossing over one of the first diffusion region, the second diffusion region and the third diffusion region.

US Pat. No. 10,141,318

STRUCTURE AND METHOD FOR FINFET SRAM

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:four SRAM cells in four quadrants of a region of the semiconductor device,
wherein the four SRAM cells include FinFET transistors comprising gate features engaging fin active lines,
wherein each of the four SRAM cells includes at least one gate feature overlapping with three or more fin active lines,
wherein the fin active lines of the four SRAM cells have reflection symmetry with respect to an imaginary line dividing the four quadrants along a first direction,
wherein each of the four SRAM cells includes at least one fin active line over a first P-well adjacent one side of an N-well, and at least one fin active line over a second P-well adjacent another side of the N-well, and
wherein two of the four SRAM cells share all the fin active lines over the first and second P-wells.

US Pat. No. 10,141,317

METAL LAYERS FOR A THREE-PORT BIT CELL

QUALCOMM Incorporated, S...

1. A method comprising:patterning a first metal layer at a bit cell;
patterning a second metal layer between the first metal layer and a third metal layer, the second metal layer including two read word lines coupled to the bit cell; and
patterning the third metal layer, the third metal layer including a write word line coupled to the bit cell.

US Pat. No. 10,141,315

SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:an array of memory cells formed in a semiconductor, the array comprising:
a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising:
a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;
a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, and the buried region is discontinuous along one direction;
wherein said floating body region stores a charge level indicative of a state of the memory cell selected from at least first and second states;
wherein said buried region is configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said buried region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and
first control circuitry configured to provide electrical signals to said buried region.

US Pat. No. 10,141,314

MEMORIES AND METHODS TO PROVIDE CONFIGURATION INFORMATION TO CONTROLLERS

Micron Technology, Inc., ...

1. A memory system, comprising:a memory controller; and
a memory module coupled to the memory controller, wherein the memory module comprises:
a memory package of a first type, wherein the memory package of the first type includes a first memory die and a second memory die coupled to the first memory die wherein the first memory die and second memory die are separate dies, the memory package of the first type configured to receive an external signal for the second memory die and further configured to couple the external signal to the second memory die through the first memory die; and
a signal presence detect unit including a memory module and configured to receive a configuration signal and to provide configuration data associated with a memory package of a second type to the memory controller in response to the configuration signal, wherein the configuration data includes control signal timings for accessing one or more memory dies in the memory package of the second type, wherein the control signal timings provided from the signal presence detection unit to the memory controller include timing relationships between clock enable, chip select, and on-die termination signals, wherein the memory package of the second type is configured to provide the external signal directly to a respective second memory die, the memory controller being configured to interface with the memory package of the first type utilizing the control signal timings of the second type, based, at least in part, on the configuration data of the second type and further configured to provide the external signal for the second memory die to the memory package of the first type.

US Pat. No. 10,141,313

FINFET WITH UNIFORM SHALLOW TRENCH ISOLATION RECESS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:forming a dense region comprising at least two fins on a substrate, the dense region being arranged adjacent to an isolated region without fins;
depositing an oxide on the at least two fins of the dense region and on the isolated region of the substrate;
removing a portion of the oxide, removing more oxide in the isolated region, such that polishing results in forming a non-uniform oxide surface; and
performing an etch process to further recess the oxide in the dense region and the isolated region, such that a thickness of the oxide in the dense region and the isolated region is substantially uniform.

US Pat. No. 10,141,312

SEMICONDUCTOR DEVICES INCLUDING INSULATING MATERIALS IN FINS

Samsung Electronics Co., ...

1. A semiconductor device comprising:a first substrate region and a second substrate region;
a first fin protruding from the first substrate region and comprising a first recess;
a first isolation layer in the first recess;
a first source/drain region on the first fin adjacent the first recess;
a second fin protruding from the second substrate region and comprising a second recess;
a second isolation layer in the second recess; and
a second source/drain region on the second fin adjacent the second recess,
wherein a bottom surface of the first recess is lower than a bottom surface of the second recess,
wherein an upper surface of the first isolation layer is coplanar with, or protrudes beyond, an upper surface of the first fin, and
wherein an upper surface of the second isolation layer is coplanar with, or protrudes beyond, an upper surface of the second fin.

US Pat. No. 10,141,310

SHORT CHANNEL EFFECT SUPPRESSION

TAIWAN SEMICONDUCTOR MANU...

18. A semiconductor device comprising:a p-type region comprising:
a first set of fin structures, the fin structures of the first set varying in size, the fin structures of the first set each comprising:
a bottommost portion;
a channel portion disposed above the bottommost portion and having an n-type dopant at a first concentration; and
an epitaxially grown anti-punch-through feature extending from the bottommost portion to the channel portion and having an n-type dopant throughout at a second concentration greater than the first concentration, wherein the anti-punch-through feature of a first fin structure of the first set extends to a different depth than the anti-punch-through feature of a second fin structure of the first set;
a plurality of p-type transistors formed on the fin structures of the first set, the p-type transistors having varying dimensions; and
a number of isolation features positioned such that a top surface of the isolation features is below a first portion of each of the anti-punch-through features and above a second portion of each of the anti-punch-through features.

US Pat. No. 10,141,309

TIGHT PITCH INVERTER USING VERTICAL TRANSISTORS

International Business Ma...

1. A fabrication method for forming an inverter structure, comprising:obtaining a monolithic structure including a p-type region and an n-type region, the p-type region being electrically isolated from the n-type region;
forming a dummy gate on the monolithic structure;
epitaxially forming first and second semiconductor fins on the monolithic structure and within the dummy gate, the first semiconductor fin being formed on the p-type region and the second semiconductor fin being formed on the n-type region;
forming a first drain region on the first semiconductor fin and above the dummy gate, the first drain region having p-type conductivity;
forming a second drain region on the second semiconductor fin and above the dummy gate, the second drain region having n-type conductivity, and
replacing the dummy gate with a gate dielectric layer and an electrically conductive gate electrode on the gate dielectric layer such that the gate dielectric layer adjoins the first and second semiconductor fins and the gate electrode adjoins the gate dielectric layer, and further such that:
the p-type region, the first semiconductor fin, the first drain region, and the gate electrode form a vertical, p-type field-effect transistor,
the n-type region, the second semiconductor fin, the second drain region, and the gate electrode form a vertical, n-type field-effect transistor, and
the gate electrode is shared by the p-type field-effect transistor and the n-type field-effect transistor.

US Pat. No. 10,141,307

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:an isolation insulating layer disposed over a substrate;
a first fin structure and a second fin structure, both disposed over the substrate, the first and second fin structures extending in a first direction in plan view, upper portions of the first and second fin structures being exposed from the isolation insulating layer;
a first gate structure disposed over parts of the first and second fin structures, the first gate structure extending in a second direction crossing the first direction;
first fin sidewall spacers covering a lower portion of the exposed first fin structure, and second fin sidewall spacers covering a lower portion of the exposed second fin structure; and
a source/drain structure formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation insulating layer, and wrapping side surfaces and a top surface of each of the exposed first and second fin structures, wherein:
a void is formed between the source/drain structure and the isolation insulating layer,
one of the first fin sidewall spacers and one of the second fin sidewall spacers are disposed in the void, and
an entirety of side surface of the one of the first fin sidewall spacers and an entirety of side surface of the one of the second fin sidewall spacers are exposed in the void.

US Pat. No. 10,141,306

SYSTEMS, METHODS, AND APPARATUS FOR IMPROVED FINFETS

QUALCOMM Incorporated, S...

1. A finFET comprising:a plurality of fins separated from each other to form a plurality of gaps between adjacent fins of the plurality of fins;
an oxide material located in the plurality of gaps, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material; and
wherein the first density is greater than the second density.

US Pat. No. 10,141,305

SEMICONDUCTOR DEVICES EMPLOYING FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE CHANNEL STRUCTURES WITHOUT SHALLOW TRENCH ISOLATION (STI) VOID-INDUCED ELECTRICAL SHORTS

QUALCOMM Incorporated, S...

1. A semiconductor device, comprising:a substrate;
a plurality of channel structures disposed over the substrate, the plurality of channel structures of a first field effect transistor (FET);
one or more shallow trench isolation (STI) trenches, each STI trench formed between a corresponding pair of channel structures of the plurality of channel structures and comprising:
a bottom region filled with a lower quality oxide; and
a top region formed above the bottom region and filled with a higher quality oxide;
a gate of the first FET disposed over the plurality of channel structures and the top region of each STI trench of the one or more STI trenches;
a source of the first FET disposed on a first side the plurality of channel structures and the one or more STI trenches; and
a drain of the first FET disposed on a second side of the plurality of channel structures and the one or more STI trenches opposite of the first side,
wherein the top region of each STI trench of the one or more STI trenches is filled with the higher quality oxide such that a void is not formed in the top region, and
wherein the top region of each STI trench of the one or more STI trenches electrically isolates the gate from the source and the drain.

US Pat. No. 10,141,301

CROSS-DOMAIN ESD PROTECTION

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:a triggering arrangement coupled to a first reference voltage node, the triggering arrangement having an output node for a triggering indication; and
interface circuitry coupled to a second reference voltage node different from the first reference voltage node, wherein the interface circuitry comprises a transistor having a body electrode biased to the output node of the triggering arrangement;
a second transistor coupled between the transistor and a third reference voltage node, wherein:
a gate electrode of the second transistor is biased to a triggering node of the triggering arrangement; and
the triggering indication at the output node is a logical inverse of a signal at the triggering node.

US Pat. No. 10,141,299

SEMICONDUCTOR DEVICE WITH PROTECTIVE ELEMENT PORTION

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first semiconductor region of a second conductivity type selectively provided in a surface layer of a first principal surface of a semiconductor substrate of a first conductivity type;
an element structure of a semiconductor element provided in the first semiconductor region;
a second semiconductor region of the first conductivity type selectively provided in the first semiconductor region, the second semiconductor region constituting the element structure of the semiconductor element;
a third semiconductor region of the second conductivity type selectively provided to penetrate the first semiconductor region in a depth direction and to surround the element structure of the semiconductor element at a depth equal to or deeper than a depth of the first semiconductor region, the third semiconductor region having an impurity concentration that is higher than that of the first semiconductor region;
a fourth semiconductor region of the second conductivity type selectively provided in the surface layer of the first principal surface of the semiconductor substrate to be spaced apart from the first semiconductor region;
a fifth semiconductor region of the first conductivity type selectively provided in the fourth semiconductor region;
a sixth semiconductor region of the second conductivity type selectively provided to penetrate the fourth semiconductor region in the depth direction and to be at a depth equal to or deeper than a depth of the fourth semiconductor region, the sixth semiconductor region having an impurity concentration that is higher than that of the fourth semiconductor region;
a first electrode that is electrically connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; and
a second electrode that is connected to a second principal surface of the semiconductor substrate.

US Pat. No. 10,141,297

INTEGRATED DEVICE COMPRISING DEVICE LEVEL CELLS WITH VARIABLE SIZES FOR HEAT DISSIPATION AROUND HOTSPOTS

QUALCOMM Incorporated, S...

1. An integrated device comprising:a substrate;
a device level layer over the substrate, the device level layer including:
a plurality of first device level cells, each first device level cell including a first configuration, wherein the plurality of first device level cells includes standard device level cells that represent at least about 90 percent of all device level cells of the integrated device; and
a plurality of second device level cells, at least one second device level cell including a second configuration that is different than the first configuration, wherein the plurality of second device level cells is located over at least one region of the integrated device that includes at least one hotspot; and
an interconnect portion over the device level layer.

US Pat. No. 10,141,296

DUMMY FIN CELL PLACEMENT IN AN INTEGRATED CIRCUIT LAYOUT

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit, comprising:a semiconductor device formed over a substrate;
a first plurality of dummy fin structures over a first portion of the substrate, wherein each of the first plurality of dummy fin structures has a first gate structure having a first gate width, and the first plurality of dummy fin structures being based on a first standard dummy fin cell; and
a second plurality of dummy fin structures over a second portion of the substrate, wherein each of the second plurality of dummy fin structures has a second gate structure having a second gate width different from the first gate width, and the second plurality of dummy fin structures being based on a second standard dummy fin cell,
wherein the second portion surrounds the semiconductor device and the first portion surrounds the second portion.

US Pat. No. 10,141,293

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...

1. A semiconductor package, comprising:a package base substrate having first to fourth edges;
a plurality of bonding pads disposed on upper surface of the package base substrate, wherein first to fourth portions of the bonding pads are disposed adjacent to the first to fourth edges of the package base substrate, respectively;
a plurality of connection pads disposed on lower surface of the package base substrate;
four identical semiconductor chips disposed on upper surface of the package base substrate, each of the semiconductor chips including a plurality of first chip pads adjacent to a first edge of the semiconductor chip, and each of the first to fourth semiconductor chips being rotated by ninety degrees relative to adjacent semiconductor chips and thereby, first edges of the first to fourth semiconductor chips facing the first to fourth edges of the package base substrate respectively; and
bonding wires electrically connecting the first chip pads of the first to fourth semiconductor chips to the first to fourth portions of bonding pads respectively,
wherein each of semiconductor chips further includes a second chip pad, and the second chip pads of the first semiconductor chip and the third semiconductor chip are electrically connected by a first matching wire, and the second chip pads of the second semiconductor chip and the fourth semiconductor chip are electrically connected by a second matching wire.

US Pat. No. 10,141,291

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, including:attaching a carrier wafer having a first wafer width to a front side of a die wafer having a second wafer width, the first wafer width being substantially identical to the second wafer width, the die wafer having a thickness of about 700 ?m when attaching to the carrier wafer;
thinning a back side of the die wafer, the back side of the die wafer being opposite to the front side of the die wafer;
singulating the carrier wafer and the die wafer concurrently when die wafer having the second wafer width, whereby singulated dies attached to singulated carrier dies are formed; and
bonding the singulated dies attached to singulated carrier dies to a bottom wafer, wherein a back side of each of the singulated dies is facing a front side of the bottom wafer.

US Pat. No. 10,141,288

SURFACE MOUNT DEVICE/INTEGRATED PASSIVE DEVICE ON PACKAGE OR DEVICE STRUCTURE AND METHODS OF FORMING

Taiwan Semiconductor Manu...

1. A package structure comprising:an integrated circuit die embedded in an encapsulant;
a redistribution structure on the encapsulant and electrically coupled to the integrated circuit die, the redistribution structure comprising:
a metallization layer distal from the encapsulant and the integrated circuit die, wherein the metallization layer is an uppermost metallization layer of the redistribution structure, and
a dielectric layer on the metallization layer, wherein the dielectric layer is an uppermost dielectric layer of the redistribution structure;
a first under metallization structure on the dielectric layer, the first under metallization structure comprising:
a first under-terminal metallization including a first extending portion and a second extending portion, wherein the first extending portion extends through a first opening of the dielectric layer to a first pattern of the metallization layer, wherein the second extending portion extends through a second opening of the dielectric layer to a second pattern of the metallization layer, wherein the first under-terminal metallization further includes a first upper portion on an upper surface of the dielectric layer distal the encapsulant, the first upper portion extending continuously from the first extending portion to the second extending portion; and
a second under-terminal metallization including a third extending portion and a fourth extending portion, wherein the third extending portion extends through a third opening of the dielectric layer to a third pattern of the metallization layer, wherein the fourth extending portion extends through a fourth opening of the dielectric layer to a fourth pattern of the metallization layer, wherein the second under-terminal metallization further includes a second upper portion on the upper surface of the dielectric layer distal the encapsulant, the second upper portion extending continuously from the third extending portion to the fourth extending portion, wherein the first opening, the second opening, the third opening, and the fourth opening are physically separated from each other; and
a Surface Mount Device and/or Integrated Passive Device (SMD/IPD) attached to the first under metallization structure, wherein the SMD/IPD has a first connector formed of a first conductive material, wherein the first connector physically contacts the first extending portion and the second extending portion of the first under-terminal metallization, wherein the first conductive material extends continuously from the first extending portion to the second extending portion.

US Pat. No. 10,141,281

SUBSTRATE AND PACKAGE STRUCTURE

Taiwan Semiconductor Manu...

1. A package structure, comprising:a chip comprising a plurality of pillar bumps;
a substrate, having a core area aligned with a center of the chip and a non-core area, and comprising a plurality of pads having at least one pad in the core area and at least one pad in the non-core area, the at least one pad in the core area having a first pad size and the at least one pad in the non-core area having a second pad size, the first pad size being greater than the second pad size;
wherein the at least one pad in the core area is bonded to a first pillar bump of the plurality of pillar bumps, the first pillar bump having a first bump size;
wherein the at least one pad in the non-core area is bonded to a second pillar bump of the plurality of pillar bumps, the second pillar bump having the first bump size;
wherein a ratio of the first pad size to the first bump size is greater than a ratio of the second pad size to the first bump size; and
wherein a width of the at least one pad in the core area is greater than a width of the at least one pad in the non-core area, and a height of the at least one pad in the core area is the same as a height of the at least one pad in the non-core area.

US Pat. No. 10,141,280

MECHANISMS FOR FORMING PACKAGE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A package structure, comprising:a semiconductor die; and
a substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween, wherein:
the first bonding structure and the second bonding structure are next to each other,
the second bonding structure is wider than the first bonding structure,
the first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump,
the first UBM structure is between the first solder bump and the semiconductor die,
the first solder bump has a first end and a second end opposite to the first end,
the second end is in direct contact with the first UBM structure,
the second end is wider than the first end,
the second bonding structure has a second UBM structure and a second solder bump,
the second solder bump has a third end and a fourth end opposite to the third end,
the fourth end is in direct contact with the second UBM structure,
the third end of the second solder bump is as wide as the first end of the first solder bump,
the second UBM structure has a continuous linear portion extending across an entirety of the fourth end of the second solder bump,
the second UBM structure has a sidewall portion surrounding the continuous linear portion and extending along a side surface of the second solder bump,
the third end of the second solder bump and the first end of the first solder bump are substantially positioned at a plane that is parallel to a main surface of the substrate,
the second UBM structure is between the second solder bump and the semiconductor die, and
the second UBM structure has a maximum width larger than that of the first UBM structure, and the second solder bump has a maximum width larger than that of the first solder bump.

US Pat. No. 10,141,279

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A semiconductor device, comprising:a semiconductor substrate;
a conductor provided on a main surface of the semiconductor substrate;
an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor; and
an external connection terminal connected to the portion of the conductor exposed from the opening, wherein
in a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.

US Pat. No. 10,141,278

CHIP MOUNTING STRUCTURE

International Business Ma...

1. A method for changing a shape of a substrate to reduce stress exerted on an interlayer insulating layer of a chip, the method comprising:providing the substrate;
mounting the chip on the substrate such that a center of the chip corresponds to a center of the substrate and such that sides of the chip are parallel to sides of the substrate;
measuring a distance B between a side of the chip and a nearest side of the substrate; and
cutting off square portions of the substrate from each corner of the substrate such that a distance between a corner of the chip and a nearest corner of the substrate is less than the distance B,
wherein each square portion has sides of a length c, and wherein

US Pat. No. 10,141,277

MONOLITHIC DECOUPLING CAPACITOR BETWEEN SOLDER BUMPS

International Business Ma...

1. An integrated circuit, comprising:pads formed on a back end of the line surface;
decoupling capacitor stacks monolithically formed about the pads, each decoupling capacitor stack including dielectric layers, and a first conductive layer and a second conductive layer disposed between the dielectric layers, the first and second conductive layers including respective materials having different etch selectivities;
and solder balls formed on respective ones of the pads and connecting to respective ones of the first and second conductive layers to reduce noise and voltage spikes between the solder balls.

US Pat. No. 10,141,275

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A method of manufacturing a semiconductor structure, comprising:providing a substrate;
disposing a pad over the substrate;
disposing a first passivation over the substrate to partially cover the pad;
disposing a conductive material over the first passivation and the pad to form a conductive line electrically connected to the pad;
disposing a second passivation over the first passivation to partially cover the conductive line; and
forming a plurality of first protrusions over the conductive line exposed from the second passivation;
wherein the method further comprising:
disposing a patterned mask including a plurality of openings over the first passivation;
removing portions of the first passivation exposed from the patterned mask to form a plurality of recesses over the first passivation;
removing the patterned mask; and
disposing the conductive material within the plurality of recesses to form a plurality of second protrusions protruded from the conductive line towards the substrate.

US Pat. No. 10,141,274

SEMICONDUCTOR CHIP WITH ANTI-REVERSE ENGINEERING FUNCTION

International Business Ma...

1. An anti-reverse engineering semiconductor structure, comprising:a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, said first wiring level closest to said semiconductor substrate and said last wiring level furthest from said semiconductor substrate, said stack of wiring levels including an intermediate wiring level between said first wiring level and said last wiring level, said semiconductor substrate and said first wiring level comprising active devices, wherein each wiring level of said stack of wiring levels comprises a dielectric layer containing electrically conductive wire;
active devices contained in said semiconductor substrate and said first wiring level, each wiring level of said stack of wiring levels comprising a dielectric layer containing electrically conductive wire;
a liner on sidewalls and a bottom of a trench extending from said intermediate wiring level, through said first wiring level into said semiconductor substrate, such that said trench comprises an open space;
a cap sealing a top of said open space of said trench, wherein each of said liner and said cap is configured to be damaged during a reverse engineering process such that said trench is exposed to said at least one wiring level of said stack of wiring levels; and
a chemical agent filling said open space of said trench, wherein said liner and said cap are chemically inert to said chemical agent, wherein portions of said at least one wiring level of said stack of wiring levels are not chemically inert to said chemical agent or a reaction product of said chemical agent, and wherein upon said liner or said cap being damaged during said reverse engineering process, said chemical agent is configured to damage wires, dielectric layers, dielectric materials, and said active devices of said at least one wiring level of said stack of wiring levels.

US Pat. No. 10,141,265

BENT-BRIDGE SEMICONDUCTIVE APPARATUS

Intel IP Corporation, Sa...

1. A bent-bridge semiconductive apparatus comprising:a first semiconductive device;
a silicon bridge that is integrally part of the first semiconductive device, wherein the silicon bridge is deflected out of planarity with respect to the first semiconductive device, and
electrical connection selected from the group consisting of an electrical bump and a redistribution layer coupled to the first semiconductive device at metallization on an active surface thereof.

US Pat. No. 10,141,263

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method for fabricating semiconductor device, comprising:providing a substrate;
forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer;
performing a first etching process to remove part of the ILD layer for forming a recess;
performing a second etching process to remove part of the first spacer for expanding the recess after performing the first etching process; and
forming a contact plug in the recess.

US Pat. No. 10,141,262

ELECTRICALLY CONDUCTIVE LAMINATE STRUCTURES

Micron Technology, Inc., ...

1. An electrical interconnect, comprising:an electrically conductive laminate structure; the laminate structure comprising multiple regions nested within one another; one of said nested regions being a graphene region and others of the nested regions being non-graphene regions; the graphene region being sandwiched between a pair of non-graphene regions; the laminate structure comprising an uppermost surface that contains segments of the graphene region and of the non-graphene regions; at least one of the non-graphene regions being electrically conductive;
an electrically insulative material over the upper surface of the laminate structure, and having an opening extending therethrough to a portion of the laminate structure; said portion differing from other portions of the laminate structure by having space between the pair of non-graphene regions instead of having graphene between the non-graphene regions; and
electrically conductive material within the opening and within the space.

US Pat. No. 10,141,261

DEVICE COMPRISING NANOSTRUCTURES AND METHOD OF MANUFACTURING THEREOF

1. A device (300, 410-412) having individually addressable sets of nanostructures (207) comprising:a first substrate (200), wherein the first substrate comprises a first face (202) and a second face (203), wherein an insulating layer (201) comprising an insulating material arranged on said first face (202) of said first substrate (200);
a plurality of electrically conductive portions (208) within said insulating layer (201), said portions being spaced apart from each other;
a set of nanostructures (207) arranged on said first face (202) of the first substrate, such that the nanostructures are spatially separated and grown on top of the said first face (202), wherein said sets of nanostructures (207) are arranged on each of said electrically conductive portions (208) such that each electrically conductive portion is in electrical connection with a respective one of said sets of nanostructures;
a connecting structure (210) in a second substrate (209) underlying said second face (203) of said insulating layer (201), wherein the said connecting structure (210) is comprised of materials different than the composition materials of the conductive portions (208), the insulating material and the said second substrate (209), said connecting structure being connectable to an external device and configured to provide a first electrical connection to each of said electrically conductive portions (208), and thereby enabling individual addressing of each set of nano structures (207).

US Pat. No. 10,141,260

INTERCONNECTION STRUCTURE AND METHOD FOR FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming an interconnection structure, comprising:forming a dielectric structure over a non-insulator structure;
forming a hole in the dielectric structure to expose the non-insulator structure;
forming a first diffusion barrier layer into the hole in the dielectric structure using a first deposition process;
forming a second diffusion barrier layer over the first diffusion barrier layer using a second deposition process that is different from the first deposition process;
removing a first portion of the second diffusion barrier layer from a bottom of the hole; and
forming a metal over the first diffusion barrier layer.

US Pat. No. 10,141,259

SEMICONDUCTOR DEVICES HAVING ELECTRICALLY AND OPTICALLY CONDUCTIVE VIAS, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a first semiconductor die having a first optical component for receiving and/or transmitting optical signals;
a second semiconductor die adjacent to the first semiconductor die and having a second optical component for receiving and/or transmitting optical signals; and
a via extending at least between the first optical component and the second optical component, the via having a transparent and electrically conductive material disposed therein, wherein the transparent and electrically conductive material (a) optically couples the first and second optical components and (b) electrically couples the first and second semiconductor dies.

US Pat. No. 10,141,258

SEMICONDUCTOR DEVICES HAVING STAGGERED AIR GAPS

Samsung Electronics Co., ...

9. A semiconductor device comprising:a substrate including a first region and a second region spaced apart from each other in a first direction;
lower conductive patterns disposed on the substrate and including first lower conductive patterns on the first region and second lower conductive patterns on the second region;
a first interlayer dielectric layer disposed between the first lower conductive patterns
a lower air gap provided in a space between the second lower conductive patterns;
a middle conductive pattern disposed on the lower conductive pattern in the second region;
upper conductive patterns including first upper conductive patterns disposed on the first lower conductive patterns and second upper conductive patterns disposed on the second lower conductive patterns; and
an upper air gap provided in a space between the second upper conductive patterns,
wherein the first interlayer dielectric layer completely fills a space between the first lower conductive patterns.

US Pat. No. 10,141,257

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A semiconductor integrated circuit device, comprising:(a) a first interconnect made of a first metal film and formed over a main surface of a semiconductor substrate;
(b) a first barrier insulating film formed on the first interconnect such that the first barrier insulating film contacts a top surface of the first interconnect;
(c) a first interlayer insulating film formed over the first barrier insulating film;
(d) a first via hole formed in the first interlayer insulating film and the first barrier insulating film such that the first via hole connects with the first interconnect;
(e) a first interconnect trench formed in the first interlayer insulating film over the first via hole and connected with the first via hole;
(f) a second interconnect formed by filling a second metal film in the first interconnect trench and the first via hole;
(g) a third interconnect made of a third metal film and formed over the second interconnect and the first interlayer insulating film;
(h) a second barrier insulating film formed on the third interconnect such that the second barrier insulating film contacts a top surface of the third interconnect;
(i) a second interlayer insulating film formed over the second barrier insulating film;
(j) a second via hole formed in the second interlayer insulating film and the second barrier insulating film such that the second via hole connects with the third interconnect;
(k) a second interconnect trench formed in the second interlayer insulating film over the second via hole and connected with the second via hole; and
(l) a fourth interconnect formed by filling a fourth metal film in the second interconnect trench and the second via hole,
wherein the second interlayer insulating film has an etching stopper film,
wherein the etching stopper film is arranged nearer to a bottom surface of the fourth interconnect than to a top surface of the third interconnect and a top surface of the fourth interconnect,
wherein the first interlayer insulating film does not have an etching stopper film,
wherein the second interlayer insulating film is thicker than the first interlayer insulating film,
wherein a depth of the second interconnect trench is greater than a depth of the first interconnect trench,
wherein a depth of the second via hole is greater than a depth of the first via hole,
wherein a dielectric constant of the first interlayer insulating film is lower than a dielectric constant of the second interlayer insulating film,
wherein the first barrier insulating film includes silicon, carbon and nitrogen,
wherein the second barrier insulating film includes silicon, carbon and nitrogen, and
wherein the etching stopper film includes silicon and nitrogen.

US Pat. No. 10,141,256

SEMICONDUCTOR DEVICE AND LAYOUT DESIGN THEREOF

Taiwan Semiconductor Manu...

1. A device, comprising:a substrate having formed therein an active region, the active region including an edge extending in a first direction;
a plurality of gates;
a first conductive segment over the active region,
wherein a first distance is present between a first gate of the gates and the first conductive segment, a second distance is present between a second gate of the gates and the first conductive segment, and the first distance is greater than the second distance, and further wherein the second gate of the gates has a major axis in the first direction that extends over the edge of the active region in the first direction; and
a via contacting the first conductive segment wherein the first conductive segment is between the via and the substrate; and further wherein
a third distance between the first gate of the gates and the via is different than the first distance and a fourth distance between the second gate of the gates and the via is different than the second distance.

US Pat. No. 10,141,255

CIRCUIT BOARDS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package substrate, comprising:an upper conductive pattern disposed on a top surface of the semiconductor package substrate, the upper conductive pattern including bonding pads and upper electric patterns; and
a lower conductive pattern disposed on a bottom surface of the semiconductor package substrate, the lower conductive pattern including ball lands and a lower electric pattern,
wherein the bonding pads are disposed in an upper window region of the top surface and at least one of the bonding pads is electrically connected to at least one of the upper electric patterns, and the lower electric pattern is disposed in a lower window region and is electrically connected to at least one of the bonding pads and at least one of the ball lands,
wherein the lower window region is defined by outer boundaries of the lower electric pattern along at least two perpendicular directions, and the upper window region is defined as an overlapped region with the lower window region, and
wherein the upper electric patterns and the lower electric pattern include the same metallic material, and a ratio of the area occupied by the lower electric pattern in the lower window region to the area occupied by the upper conductive pattern in the upper window region is less than or equal to 1.5.

US Pat. No. 10,141,254

DIRECT BONDED COPPER POWER MODULE WITH ELEVATED COMMON SOURCE INDUCTANCE

FORD GLOBAL TECHNOLOGIES,...

1. A half-bridge power module comprising:a first direct bonded copper substrate (DBC) with a first insulation layer, a first etched circuit layer on an inner surface, and a first heat transfer layer on an outer surface, wherein the first etched circuit layer includes a high-side plate with a high-side terminal pad;
a second direct bonded copper substrate (DBC) with a second insulation layer, a second etched circuit layer on an inner surface, and a second heat transfer layer on an outer surface, wherein the second etched circuit layer includes an output plate with a output terminal pad;
a high-side transistor die having a collector side soldered to the high-side plate; and
a low-side transistor die having a collector side soldered to the output plate;
wherein the high-side plate defines a first indented notch disposed between the high-side transistor die and the high-side terminal pad to concentrate a magnetic flux at the first indented notch induced by a current in the high-side plate; and
wherein one of the first or second etched circuit layers further includes a high-side gate trace connected to the high-side transistor die and overlapping the first indented notch.

US Pat. No. 10,141,250

CHIP AND ELECTRONIC DEVICE

HUAWEI TECHNOLOGIES CO., ...

1. A chip comprising:a substrate;
a die wrapped together with the substrate by a package;
a plurality of conductive bumps disposed on the die;
an attachment point matrix arranged on a first surface of the substrate, the attachment point matrix comprising multiple attachment points;
a solder joint matrix arranged on a second surface of the substrate, the solder joint matrix comprising a plurality of solder joints comprising a first solder joint group and a second solder joint group; and
multiple substrate cables corresponding to the multiple attachment points, each of the multiple substrate cables extending through an entire thickness of the substrate and extending through a portion of a length of the substrate, each of the multiple substrate cables comprising a first end and a second end, each of the multiple substrate cables comprising at least one bend between the first end and the second end, each of the plurality of conductive bumps being electrically coupled to a corresponding one of the multiple attachment points, the first end of each of the multiple substrate cables being electrically coupled to a corresponding one of the multiple attachment points, the second end of each of the multiple substrate cables being electrically coupled to a corresponding one of the plurality of solder joints, the first solder joint group being arranged along a first parallel line, the second solder joint group being arranged along a second parallel line that is parallel to the first parallel line, a first subset of the multiple substrate cables electrically coupled to the first solder joint group being a first length value, a second subset of the multiple substrate cables electrically coupled to the second solder joint group being a second length value, and a difference between the first length value and the second length value equaling a predetermined value that is not equal to zero.

US Pat. No. 10,141,248

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device comprising:a first semiconductor chip having a first front surface on which a first electrode pad is formed;
a first chip mounting part on which the first semiconductor chip is mounted;
a first lead arranged in a region around the first semiconductor chip;
a first conductive member which is electrically connected to the first electrode pad of the first semiconductor chip via a first conductive adhesive, and is electrically connected to the first lead;
a first support part arranged over the first chip mounting part and supporting the first conductive member; and
a sealing member that seals the first semiconductor chip, the first conductive member and a portion of the first lead,
wherein the first conductive member includes a main body part and a first extension part which is continuous to the main body part and extends from the main body part in plan view,
wherein a first portion of the first extension part is disposed in the sealing member so as to overlap a first portion of the first support part in the sealing member in plan view,
wherein an end portion of the first support part is exposed from the sealing member,
wherein the sealing member has a first side extending along a first direction,
wherein a second portion of the first lead projects from the first side of the sealing member in plan view,
wherein the end portion of the first support part is exposed from the first side of the sealing member,
wherein the sealing member has a second side extending along a second direction intersecting with the first direction, and
wherein the first support part includes a bent part arranged between the end portion of the first support part and the first portion of the first support part, such that the bent part is bent closer to the main body part of the first conductive member than to the second side of the sealing member in plan view.

US Pat. No. 10,141,242

THERMALLY ENHANCED SEMICONDUCTOR PACKAGE HAVING FIELD EFFECT TRANSISTORS WITH BACK-GATE FEATURE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a first buried oxide (BOX) layer;
a non-silicon thermal conductive component, wherein the first BOX layer resides over the non-silicon thermal conductive component;
a first epitaxial layer over the first BOX layer;
a second BOX layer over the first epitaxial layer;
a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain;
a gate dielectric aligned over the channel; and
a front-gate structure over the gate dielectric, wherein
a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel; and
a field effect transistor (FET) is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

US Pat. No. 10,141,241

MULTI-CHIP SELF ADJUSTING COOLING SOLUTION

Intel Corporation, Santa...

1. An apparatus comprising:a primary device and at least one secondary device coupled in a planar array to a substrate;
a first passive heat exchanger comprising a heatsink base and a fin structure disposed on the primary device and the heatsink base and the fin structure of the first passive heat exchanger both comprise an opening over an area corresponding to the at least one secondary device, wherein the heatsink base of the first passive heat exchanger has a bottommost surface;
at least one second passive heat exchanger comprising a heatsink base and a fin structure both disposed in the opening and on the at least one secondary device;
at least one first spring operable to apply a force to the first passive heat exchanger in a direction of the primary device, the at least one first spring between the substrate and the heatsink base of the first passive heat exchanger; and
at least one second spring operable to apply a force to the at least one second passive heat exchanger in a direction of the at least one secondary device, the at least one second spring between the heatsink base of the first passive heat exchanger and the heatsink base of the at least one second passive heat exchanger, wherein the at least one second spring extends below the bottommost surface of the heatsink base of the first passive heat exchanger.

US Pat. No. 10,141,239

THERMAL DISSIPATION THROUGH SEAL RINGS IN 3DIC STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a plurality of dies bonded to each other;
an interposer bonded to one of the plurality of dies;
a seal-ring comprising thermal path extending through each of the plurality of dies;
a metal line on the interposer, the metal line extending away from the plurality of dies in a direction parallel with a major surface of the interposer;
an interposer seal ring extending at least partially through the interposer; and
a through via extending at least partially through the interposer, the through via in thermal connection with the metal line through the interposer seal ring.

US Pat. No. 10,141,238

SEMICONDUCTOR POWER DEVICE INCLUDING ADJACENT THERMAL SUBSTRATE FOR THERMAL IMPEDANCE REDUCTION

Integra Technologies, Inc...

16. A gallium-nitride (GaN) on silicon carbide (SiC) high electron mobility transistor (HEMT), comprising:a base plate;
an input lead disposed on and electrically isolated from the base plate;
an output lead disposed on and electrically isolated from the base plate;
a semiconductor power die disposed on the base plate, wherein the semiconductor power die includes a set of one or more gate electrodes configured to receive an input signal by way of the input lead, a set of one or more source electrodes electrically coupled to the base plate, and a set of one or more drain electrodes configured to produce an output signal at the output lead;
a first thermal substrate disposed on the base plate, and thermally and electrically coupled to the set of one or more gate electrodes to reduce a temperature of an active region of the semiconductor power die;
a second thermal substrate disposed on the base plate, and thermally and electrically coupled to the set of one or more drain electrodes to reduce the temperature of the active region of the semiconductor power die;
a first set of one or more electrical conductors by way the set of one or more gate electrodes receive the input signal from the input lead;
a second set of one or more electrical conductors electrically connecting the set of one or more gate electrodes to a metallization layer on the first thermal substrate;
a third set of one or more electrical conductors electrically connecting the set of one or more source electrodes to the base plate;
a fourth set of one or more electrical conductors by way the set of one or more drain electrodes produce the output signal at the output lead; and
a fifth set of one or more electrical conductors electrically connecting the set of one or more drain electrodes to a second metallization layer of the second thermal substrate.

US Pat. No. 10,141,234

FLIPPED VERTICAL FIELD-EFFECT-TRANSISTOR

International Business Ma...

1. A circuit comprising:a top supply rail and a top ground rail disposed within a top level of the circuit;
a bottom supply rail and a bottom ground rail disposed within a bottom level of the circuit;
at least one input line disposed within a middle level of the circuit;
an output line disposed within the top level of the circuit;
a plurality of p-type vertical FETs coupled to the at least one input line and having at least one p-type vertical FET coupled to the output line, where the plurality of p-type vertical FETs comprises an odd number of plurality of p-type vertical FETs, and wherein at least one p-type vertical FET in the plurality of p-type vertical FETs is coupled to the bottom supply rail; and
at least one n-type vertical FET coupled to one of the bottom ground rail and the top ground rail.

US Pat. No. 10,141,231

FINFET DEVICE WITH WRAPPED-AROUND EPITAXIAL STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor device, the method comprising:forming two fins extending from a substrate, each fin having two source/drain (S/D) regions and a channel region;
forming a gate stack engaging each fin at the respective channel region;
depositing one or more dielectric layers over top and sidewall surfaces of the gate stack and over top and sidewall surfaces of the S/D regions of the fins;
performing an etching process to the one or more dielectric layers, wherein the etching process simultaneously produces a polymer layer over the top surface of the gate stack, resulting in the top and sidewall surfaces of the S/D regions of the fins being exposed and a majority of the sidewall surfaces of the gate stack still being covered by the one or more dielectric layers; and
growing one or more epitaxial layers over the top and sidewall surfaces of the S/D regions of the fins.

US Pat. No. 10,141,230

METHOD AND STRUCTURE TO ENABLE DUAL CHANNEL FIN CRITICAL DIMENSION CONTROL

International Business Ma...

1. A semiconductor device, comprising:a substrate having a {100} crystallographic surface orientation;
a first plurality of fins comprising a first semiconductor material; and
a second plurality of fins comprising a second semiconductor material different from the first semiconductor material, wherein:
the first and second plurality of fins extend vertically with respect to the substrate;
the second plurality of fins each comprise a conformal semiconductor layer on lateral sides thereof; and
the first plurality of fins has the same or substantially the same lateral critical dimension as the second plurality of fins combined with the conformal semiconductor layer on the lateral sides thereof.

US Pat. No. 10,141,228

FINFET DEVICE HAVING SINGLE DIFFUSION BREAK STRUCTURE

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a fin-shaped structure on a substrate;
a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion;
a gate structure on the first portion; and
a contact etch stop layer (CESL) adjacent to the gate structure and extending to cover and directly contacting a top surface of the SDB structure.

US Pat. No. 10,141,227

METHOD AND SYSTEM FOR ACHIEVING SEMICONDUCTOR-BASED CIRCUITS OR SYSTEMS HAVING MULTIPLE COMPONENTS WITH ONE OR MORE MATCHED OR SIMILAR CHARACTERISTICS OR FEATURES

NXP USA, INC., Austin, T...

1. A method of achieving at least one part of a semiconductor system having matched or similar components, the method comprising:directing a pick and place head mechanism, by way of a processing device associated with an assembly machine, to move to a first position at a first column of a first row of a singulated semiconductor wafer having a plurality of rows including the first row and a plurality of columns including a first set of columns each including a plurality of first dice of a first type and a second set of columns each including a plurality of second dice of a second type, the first set of columns including the first column;
directing the pick and place head mechanism to implement a first one of the first dice from the first position at a first location on one or more substrates, wherein the first one of the first dice includes a first component;
determining whether the first one of the first dice was implemented at the first location as directed;
subsequent to determining that the first one of the first dice was implemented at the first location as directed, determining that a first one of the second dice is present at a second position at a second column that is also within the first row and that satisfies a proximity criterion indicative of a maximum distance on the wafer that can separate matched or similar dice, the second set of columns including the second column; and
upon determining that the first one of the second dice is present at the second position at the second column that satisfies the proximity criterion, directing the pick and place head mechanism to implement the first one of the second dice from the second position at the second location, wherein the first one of the second dice includes a second component that is matched or similar to the first component due to the first and second type being matched or similar;
wherein, upon the first one of the first dice and the first one of the second dice being implemented on the one or more substrates, the one or more substrates constitutes or constitute the at least one part of the semiconductor system having the matched or similar components, the matched or similar components including the first and second components.

US Pat. No. 10,141,226

SELF-ALIGNED CONTACTS

Intel Corporation, Santa...

1. A nonplanar transistor comprising:a body;
a pair of spacers on the body;
a gate dielectric layer on a surface of the body between the pair of spacers and along sidewalls of the pair of spacers;
a gate electrode on the gate dielectric layer and between the pair of spacers, wherein the gate electrode is separated from the pair of spacers by portions of the gate dielectric layer along the sidewalls of the pair of spacers;
an insulating cap layer on the gate electrode between the pair of spacers and directly on the portions of the gate dielectric layer along the sidewalls of the pair of spacers; and
a pair of diffusion regions adjacent to the pair of spacers.

US Pat. No. 10,141,225

METAL GATES OF TRANSISTORS HAVING REDUCED RESISTIVITY

Taiwan Semiconductor Manu...

1. A method comprising:forming a transistor comprising:
forming a gate dielectric on a semiconductor region;
forming a gate electrode over the gate dielectric; and
forming a source/drain region extending into the semiconductor region;
forming a source/drain contact plug over and electrically coupling to the source/drain region; and
forming a gate contact plug over and in contact with the gate electrode, wherein at least one of the forming the gate electrode, the forming the source/drain contact plug, or the forming the gate contact plug comprises:
removing a hard mask between opposite portions of gate spacers;
forming a metal nitride barrier layer;
depositing a metal-containing layer over and in contact with the metal nitride barrier layer, wherein the metal-containing layer comprises at least one of a cobalt layer or a metal silicide layer, and wherein the metal nitride barrier layer and the metal-containing layer extend into an opening left by the removed hard mask; and
performing a planarization to remove excess portions of the metal nitride barrier layer and the metal-containing layer.

US Pat. No. 10,141,223

METHOD OF IMPROVING MICRO-LOADING EFFECT WHEN RECESS ETCHING TUNGSTEN LAYER

UNITED MICROELECTRONICS C...

1. A method for improving micro-loading effect when recess etching a tungsten layer, comprising:providing a semiconductor substrate having a main surface, wherein a plurality of trenches is formed in the semiconductor substrate;
blanket depositing a tungsten layer on the semiconductor substrate, wherein the plurality of trenches is filled with the tungsten layer;
subjecting the tungsten layer to a planarization process to form a planarization layer on the tungsten layer;
performing a first etching process to completely remove the planarization layer and partially remove the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1; and
performing a second etching process to etch remainder of the tungsten layer until a top surface of the tungsten layer is lower than the main surface of the semiconductor substrate.

US Pat. No. 10,141,222

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS THROUGH INTERCONNECT STRUCTURES AND ENCAPSULANT OF WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a carrier;
providing a semiconductor die;
disposing a first interconnect structure over an active surface of the semiconductor die;
disposing the semiconductor die over the carrier with the active surface of the semiconductor die oriented toward the carrier;
forming a second interconnect structure over a second surface of the semiconductor die opposite the active surface;
forming a first insulating layer over the second interconnect structure;
forming a protective layer on the first insulating layer;
forming a via in order through the protective layer, second interconnect structure, first interconnect structure, and partially into the carrier;
removing the protective layer after forming the via;
removing the carrier after forming the via;
forming a first conductive layer in the via and extending over the semiconductor die directly on a major surface of the first insulating layer; and
forming an opening in the first insulating layer, wherein the first conductive layer extends into the opening to contact the second interconnect structure.

US Pat. No. 10,141,217

DICING-TAPE INTEGRATED FILM FOR BACKSIDE OF SEMICONDUCTOR AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

NITTO DENKO CORPORATION, ...

1. A dicing-tape integrated film for a backside of a semiconductor havinga dicing tape having a substrate and pressure-sensitive adhesive layer formed on the substrate and
a film for the backside of a flip-chip semiconductor formed on the pressure-sensitive adhesive layer of the dicing tape, wherein the pressure-sensitive adhesive layer comprises a silicone pressure-sensitive adhesive layer at the interface with the film for the backside of a flip-chip semiconductor, and wherein
the difference (?2??1) of the surface free energy ?2 and the surface free energy ?1 is 10 mJ/m2 or more, in which ?1 represents the surface free energy that is calculated from contact angles of water and iodomethane measured using a contact angle gauge according to a geometric mean method on the pressure-sensitive adhesive layer, and ?2 represents the surface free energy that is calculated from contact angles of water and iodomethane measured using a contact angle gauge according to a geometric mean method on the film for the backside of a flip-chip semiconductor after the pressure-sensitive adhesive layer and the film for the backside of a flip-chip semiconductor are peeled from each other at the interface.

US Pat. No. 10,141,215

COMPLIANT NEEDLE FOR DIRECT TRANSFER OF SEMICONDUCTOR DEVICES

1. An apparatus configured to transfer an electrically-actuatable element directly from a first side of a wafer tape to a product substrate having a circuit trace thereon, the apparatus comprising:a needle disposed adjacent a second side of the wafer tape opposite the first side of the wafer tape;
a needle actuator to move the needle to a position at which the needle presses on the second side of the wafer tape to press the electrically-actuatable element into contact with the circuit trace disposed adjacent the first side of the wafer tape; and
a dampener arranged with an end of the needle and an end of the needle actuator, the dampener dampening a force applied to the electrically-actuatable element when the needle presses the electrically-actuatable element into contact with the circuit trace.

US Pat. No. 10,141,212

AUTOMATED MATERIAL HANDLING SYSTEM FOR SEMICONDUCTOR MANUFACTURING BASED ON A COMBINATION OF VERTICAL CAROUSELS AND OVERHEAD HOISTS

Murata Machinery Ltd., K...

7. A system comprising:an overhead rail in a semiconductor fabrication plant;
an overhead hoist transport (OHT) vehicle coupled to the overhead rail, wherein the OHT vehicle comprises:
a body;
a gripper configured to hold a material unit;
a hoist coupled to the movable stage and to the gripper;
a moveable stage coupled to the hoist and the body, wherein the OHT transport vehicle is configured to move the moveable stage along a horizontal axis to positions exterior to the body on either side of the body of OHT transport vehicle;
wherein the movable stage is configured to move along the horizontal axis from a first position within to the body to a second position that is exterior to the body of the OHT vehicle and adjacent to a side of the OHT vehicle; and
wherein the hoist is configured to move the gripper along a vertical axis to a position that is directly below the moveable stage;
wherein the hoist is configured to move the gripper along a vertical axis to a position that is directly below the moveable stage when the moveable stage is in the first position;
wherein the hoist is configured to move the gripper along a vertical axis to a position that is directly below the moveable stage when the moveable stage is in the second position that is adjacent to a side of the OHT vehicle;
wherein the OHT vehicle is configured to move the material unit from a starting position to an ending position, wherein the starting position comprises a horizontal starting position and a vertical starting position, and the ending position comprises a horizontal ending position and a vertical ending position;
wherein the hoist is configured to move the gripper vertically to a work station; and
wherein the movable stage and the hoist are configured to work in concert to move the gripper to a fixed shelf.

US Pat. No. 10,141,211

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE TRANSFER METHOD

EBARA CORPORATION, Tokyo...

1. A substrate processing apparatus, comprising:a substrate holder configured to hold a substrate;
a fixing unit configured to mount and remove the substrate on and from the substrate holder,
a substrate dryer configured to dry the substrate;
a robot configured to transfer the substrate at least between the fixing unit and the substrate dryer;
a processing bath configured to process the substrate while the substrate holder is holding the substrate such that the substrate is in a vertical orientation; and
a substrate transfer device including a grasping section configured to grasp the substrate holder, and a transferring section configured to transfer the substrate holder grasped by the grasping section,
wherein the substrate transfer device is configured to transfer the substrate holder at least between the fixing unit and the processing bath,
the grasping section is configured to rotate the substrate holder between the vertical orientation and a horizontal orientation, which is angularly offset from the vertical orientation while the substrate holder is holding the substrate, and
the transferring section is configured to transfer the substrate holder and the substrate while the substrate holder is holding the substrate from the processing bath to the fixing unit, with the substrate in the horizontal orientation, along a path that is above the processing bath.

US Pat. No. 10,141,209

PROCESSING GAS GENERATING APPARATUS, PROCESSING GAS GENERATING METHOD, SUBSTRATE PROCESSING METHOD, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. An apparatus for generating a processing gas by bubbling a raw material liquid with a carrier gas, the apparatus comprising:a raw material liquid tank configured to store the raw material liquid;
a raw material liquid supplying path provided between a raw material liquid bottle that stores the raw material liquid and the raw material liquid tank and configured to supply the raw material liquid into the raw material liquid tank from the raw material liquid bottle,
a cover provided at a top portion of the raw material liquid tank and configured to block an opening formed on a top surface of the raw material liquid tank;
a carrier gas source connected to the raw material liquid tank through a carrier gas supply path and configured to supply the carrier gas to the raw material liquid in the raw material liquid tank;
a taking-out path provided inside the cover and configured to take out the processing gas generated by the bubbling from a vapor-phase portion above a liquid-phase portion which is a region where the raw material liquid is stored in the raw material liquid tank, an end of the taking-out path being connected to the vapor-phase portion and the other end of the taking-out path being connected to a processing gas supply path to supply the processing gas to a substrate provided outside of the apparatus for generating the processing gas through the processing gas supply path;
a first temperature controller having a square column shape to cover a side wall and a bottom wall of the raw material liquid tank and configured to perform a temperature adjustment of the liquid-phase portion through at least one of the side wall and the bottom wall of the raw material liquid tank; and
a second temperature controller having a plate shape to cover an upper surface of the cover and configured to perform a temperature adjustment of the vapor-phase portion through the upper surface of the cover such that a temperature of the vapor-phase portion is higher than a temperature of the liquid-phase portion,
wherein the raw material liquid supplying path includes a raw material liquid temperature controller provided from an outside of a sidewall surface of the first temperature controller to an inside of the raw material liquid tank and configured to adjust a temperature of the raw material liquid such that the temperature of the raw material liquid supplied to the raw material liquid tank approaches the temperature of the liquid-phase portion.

US Pat. No. 10,141,208

VACUUM PROCESSING APPARATUS

Canon Anelva Corporation,...

1. A vacuum processing apparatus comprising:a vacuum vessel in which vacuum processing can be performed;
a substrate holder capable of holding a substrate;
a tilting unit capable of making said substrate holder pivot about a pivotal axis and tilting the substrate held by said substrate holder with respect to a process source provided in said vacuum vessel;
a cooling device provided in said substrate holder and configured to act together with a compression device provided outside said vacuum vessel to cool the substrate held by said substrate holder; and
a rotary joint provided in said tilting unit and including a supply path configured to supply a coolant gas from said compression device to said cooling device and an exhaust path configured to exhaust the coolant from said cooling device to said compression device,
wherein said rotary joint comprises:
a fixed portion fixed to said vacuum vessel;
a pivotal portion provided so as to pivot with respect to said fixed portion and fixed to said substrate holder; and
a gas guide path provided in one of said fixed portion and said pivotal portion and configured to communicate a space region formed between the supply path and the exhaust path and guide the coolant gas that has leaked from one of the supply path and the exhaust path in the space region, where said fixed portion faces said pivotal portion and the supply path and the exhaust path are separated, to an outside of said rotary joint.

US Pat. No. 10,141,205

APPARATUS AND METHOD FOR CLEANING SEMICONDUCTOR WAFER

ACM Research (Shanghai) I...

1. An apparatus for cleaning semiconductor wafer comprising:a brush module having a brush head for providing mechanical force on a surface of a wafer;
a swing arm of which an end mounts the brush module, wherein the brush module is vertically disposed and includes a brush base, a bearing, a flexible component, at least one damper, a mounting section, a brush shell and a coil spring, the brush head is mounted on the brush base, an end of the bearing connects with the brush base and the other end of the bearing penetrates into the brush shell and connects to a side of the flexible component, the other side of the flexible component connects with the damper which is mounted on the brush shell, the coil spring is received in the brush shell, an end of the coil sing is fixed on the side of the flexible component and the other end of the coil spring is fixed on the mounting section which is the top plate of the brush shell and opposite to the flexible component, the brush shell is fixed at the end of the swing arm, an elastic deformation of the coil spring generates a press force that the brush head acts on the surface of the wafer, and the elastic deformation of the coil spring is determined by a height of a process position of the brush module;
a rotating actuator connected with the other end of the swing arm, the rotating actuator driving the swing arm to swing across the whole surface of the wafer, which brings the brush head moving across the whole surface of the wafer; and
an elevating actuator connected with the other end of the swing arm, the elevating actuator driving the swing arm to rise or descend, which brings the brush module rising or descending.

US Pat. No. 10,141,203

ELECTRICAL INTERCONNECT STRUCTURE FOR AN EMBEDDED ELECTRONICS PACKAGE

General Electric Company,...

1. An electronics package comprising:an upper insulating layer;
at least one electrical component positioned within an opening in the upper insulating layer;
a patterned contact layer comprising at least one electrical connection formed on a first surface of the upper insulating layer;
a lower insulating layer coupled to the upper insulating layer and the at least one electrical component;
an upper interconnect layer formed on a second surface of the upper insulating layer and electrically coupled to the patterned contact layer; and
a lower interconnect layer formed on the lower insulating layer and electrically coupled to the upper interconnect layer and the at least one electrical component.

US Pat. No. 10,141,202

SEMICONDUCTOR DEVICE COMPRISING MOLD FOR TOP SIDE AND SIDEWALL PROTECTION

QUALCOMM Incorporated, S...

12. An apparatus comprising:a substrate;
a plurality of metal layers and dielectric layers coupled to the substrate;
a pad coupled to one of the plurality of metal layers;
a passivation layer on a surface of the plurality of metal layers and dielectric layers and coupled to the pad;
a first metal redistribution layer above the passivation layer and coupled to the pad;
a first insulation layer between the passivation layer and the first metal redistribution layer;
a second insulation layer at least partially above the first metal redistribution layer, wherein the second insulation layer further comprises a side formed by a trough;
an under bump metallization (UBM) layer above the second insulation layer, coupled to the first metal redistribution layer via a cavity in the second insulation layer; and
a means for protecting the apparatus from cracking during a cutting process, the means for protecting covering a first surface of the apparatus, at least a side portion of the apparatus including the side of the second insulation layer, and a portion of the UBM layer,
wherein at least a portion of the second insulation layer is between the first metal redistribution layer and the means for protecting,
wherein the side of the second insulation layer is spaced apart from a plane including both an exterior sidewall of the means for protecting and an exterior sidewall of the plurality of metal layers and dielectric layers by a portion of the means for protecting.

US Pat. No. 10,141,201

INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming a workpiece, wherein forming the workpiece comprises:
attaching a first surface of an integrated circuit die to a carrier;
encapsulating the integrated circuit die in a first encapsulant, a second surface of the integrated circuit die being level with a surface of the first encapsulant, the second surface of the integrated circuit die being opposite the first surface of the integrated circuit die;
forming one or more redistribution layers over the integrated circuit die and the first encapsulant, the one or more redistribution layers physically contacting the second surface of the integrated circuit die and the surface of the first encapsulant; and
after forming the one or more redistribution layers, removing the carrier from the integrated circuit die and the first encapsulant;
after forming the workpiece, attaching the workpiece to a heat dissipation feature, the heat dissipation feature being directly attached to the first surface of the integrated circuit die using a thermal adhesive, wherein a width of the heat dissipation feature is greater than a width of the workpiece;
mounting the workpiece on a first side of a package substrate, the package substrate comprising a through hole, wherein the heat dissipation feature is not directly attached to the package substrate;
forming a second encapsulant on the first side of the package substrate, wherein the second encapsulant surrounds the workpiece;
planarizing a top surface of the second encapsulant to be level with a top surface of the heat dissipation feature; and
mounting a die stack to the workpiece, the die stack comprising one or more integrated circuit dies, wherein the die stack is at least partially disposed in the through hole of the package substrate.

US Pat. No. 10,141,200

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A method of manufacturing a semiconductor device, the method comprising:forming a plurality of conductive structures on a substrate, each of the conductive structures including a first conductive pattern and a hard mask sequentially stacked;
forming a plurality of preliminary spacer structures on sidewalls of the conductive structures, respectively, the preliminary spacer structures including first spacers, sacrificial spacers and second spacers sequentially stacked;
forming a plurality of pad structures on the substrate between the preliminary spacer structures, respectively, the plurality of pad structures defining openings exposing upper portions of the sacrificial spacers;
forming a capping layer on surfaces of the pad structures;
forming a first mask pattern on the pad structures, the first mask pattern covering the surfaces of the pad structures and exposing the upper portions of the sacrificial spacers; and
removing the sacrificial spacers to form first spacer structures having respective air spacers, the first spacer structures including the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.

US Pat. No. 10,141,199

SELECTING A SUBSTRATE TO BE SOLDERED TO A CARRIER

Infineon Technologies AG,...

1. A method for soldering an insulating substrate onto a substrate mounting portion of a carrier by a predefined solder, wherein the insulating substrate comprises a dielectric insulation carrier, a top side, and a bottom side opposite to the top side, the method comprising:selecting the insulating substrate based on a criterion which indicates that the insulating substrate having the solidus temperature of the solder, has a positive unevenness;
soldering the insulating substrate on the bottom side to the substrate mounting portion, such that, after the soldering, the solidified solder extends continuously from the bottom side of the insulating substrate as far as the substrate mounting portion; and
populating the top side of the insulating substrate with at least one semiconductor chip,
wherein the criterion indicates that when the insulating substrate is heated proceeding from an initial temperature which is lower than the solidus temperature of the solder up to a predefined maximum temperature which is higher than the liquidus temperature of the solder, and then cooled to the solidus temperature of the solder, such that the insulating substrate has a positive unevenness when the solidus temperature of the solder is reached again.

US Pat. No. 10,141,198

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

1. An electronic package, comprising:a middle patterned conductive layer having a first surface, a second surface opposite to the first surface and a plurality of middle conductive pads;
a first redistribution circuitry disposed on the first surface of the middle patterned conductive layer and comprising a first patterned conductive layer, wherein the first patterned conductive layer has a plurality of first conductive elements, each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section, and each of the first conductive via connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad; and
a second redistribution circuitry disposed on the second surface of the middle patterned conductive layer and comprising a second patterned conductive layer, wherein the second patterned conductive layer has a plurality of second conductive elements, each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section, and each of the second conductive via connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad.

US Pat. No. 10,141,196

POWER SEMICONDUCTOR DEVICE WITH THICK TOP-METAL-DESIGN AND METHOD FOR MANUFACTURING SUCH POWER SEMICONDUCTOR DEVICE

ABB Schweiz AG, Baden (C...

1. A method for manufacturing a power semiconductor device, the method comprising the following steps:providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side;
forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane (B; B?) parallel to the first main side;
forming an isolation layer on the first main side to cover the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane (A) parallel to the first main side;
after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and
thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel,
wherein the second plane (A) is at most 1 ?m further away from the wafer than the first plane (B; B?), wherein
the step of forming the metallization layer comprises:
a first step of forming a lower portion of the metallization layer on the first main side in the active cell area before the step of forming the isolation layer; and
a second step of forming an upper portion of the metallization layer on the lower portion of the metallization layer in the active cell area after the step of forming the isolation layer.

US Pat. No. 10,141,194

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

UNITED MICROELETRONICS CO...

1. A manufacturing method of a semiconductor structure, comprising:forming a first polysilicon layer on a substrate;
performing a planarization process to the first polysilicon layer;
performing a first etching back process to the first polysilicon layer after the planarization process, wherein the first polysilicon layer has a first thickness after the planarization process and before the first etching process;
performing a second etching back process to the first polysilicon layer after the first etching back process, wherein the thickness of the first polysilicon layer is reduced by the second etching back process, wherein the first polysilicon layer has a second thickness after the first etching back process and before the second etching back process, the first polysilicon layer has a third thickness after the second etching back process, and the difference between the first thickness and the second thickness is smaller than the difference between the second thickness and the third thickness; and
performing a first wet clean process to the first polysilicon layer after the first etching back process and before the second etching back process.

US Pat. No. 10,141,193

FABRICATING METHOD OF A SEMICONDUCTOR DEVICE WITH A HIGH-K DIELECTRIC LAYER HAVING A U-SHAPE PROFILE

UNITED MICROELECTRONICS C...

1. A fabricating method of a semiconductor device, comprising:forming an inter layer dielectric layer on a substrate;
forming a trench in the inter layer dielectric layer;
forming a high-k dielectric layer having a U-shape profile in the trench;
transforming two ends of the U-shape profile to a metal layer, wherein the transforming step is a reduction;
after transforming the two ends of the U-shape profile to the metal layer, forming a work function metal layer on the high-k dielectric layer and the metal layer; and
removing a portion of the metal layer to expose an upper portion of sidewalls of the trench.

US Pat. No. 10,141,192

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A manufacturing method of a semiconductor device including a nitride semiconductor layer, the manufacturing method comprising:implanting impurities into the nitride semiconductor layer;
performing a first annealing on the nitride semiconductor layer while an implantation surface on the nitride semiconductor layer remains exposed, the first annealing being at a first temperature within an atmosphere of a nitrogen atom containing gas;
forming a protective film on the nitride semiconductor layer after the first annealing; and
after the protective film is formed, performing a second annealing on the nitride semiconductor layer at a second temperature that is higher than the first temperature.

US Pat. No. 10,141,190

MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A method of manufacturing a semiconductor device comprising:forming a multilayer structure by stacking first insulating films and second insulating films or metal films;
forming a hole through the multilayer structure in a stacking direction;
forming a block insulating film, a charge storage film, and a tunnel insulating film on an inner surface of the hole;
forming the semiconductor layer containing the impurity on the tunnel insulating film on the inner surface of the hole;
forming an oxide film on the semiconductor layer containing an impurity;
performing a heat treatment on the semiconductor layer to diffuse part of the impurity into the oxide film with hydrogen plasma treatment on the oxide film or ultraviolet irradiation on the oxide film; and
removing the oxide film after the heat treatment.

US Pat. No. 10,141,187

MASK PATTERN FORMING METHOD, FINE PATTERN FORMING METHOD, AND FILM DEPOSITION APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A mask pattern forming method comprising steps of:loading a substrate which has a thin film and a pattern on the thin film, into a process chamber, the pattern having a line and a space therein;
slimming the pattern using a first oxygen-containing gas plasma in the process chamber for a predetermined period of time such that the line is slimmed to have a predetermined width; and
forming an oxide film on the slimmed pattern and the thin film in the process chamber by performing a cycle of adsorbing an aminosilane based precursor on the thin film and the slimmed pattern and oxidizing the aminosilane based precursor on the thin film and the slimmed pattern using a second oxygen-containing gas plasma a predetermined number of times such that the deposited oxide film has a predetermined thickness,
wherein the steps of slimming the pattern and forming the oxide film are performed in the same process chamber, and
wherein temperatures at which the pattern is slimmed and at which the oxide film is formed on the pattern are 100 degrees C. or less.

US Pat. No. 10,141,185

OXIDE SEMICONDUCTOR, COATING LIQUID, METHOD OF FORMING OXIDE SEMICONDUCTOR FILM, SEMICONDUCTOR ELEMENT, DISPLAY ELEMENT, IMAGE DISPLAY DEVICE AND IMAGE DISPLAY SYSTEM

RICOH COMPANY, LTD., Tok...

1. An oxide semiconductor comprising an oxide having a layered structure expressed by an expression
wherein an atom A is a positive monovalent element, an atom Z is a positive divalent element, an atom B is a positive trivalent element, L is a positive integer, and mi and ni are independent integers greater than or equal to zero, that satisfy

US Pat. No. 10,141,183

METHODS OF SPIN-ON DEPOSITION OF METAL OXIDES

Tokyo Electron Limited, ...

1. A method for depositing material on a substrate, the method comprising:receiving a substrate having a relief pattern that defines openings that uncover an underlying layer, the relief pattern providing sidewall surfaces that define the openings, the underlying layer providing floor surfaces that define the openings, the sidewall surfaces having a first surface energy value, the floor surfaces having a second surface energy value;
identifying a fill material comprising a metal hard mask material to fill the defined openings by being deposited on the substrate via spin-on deposition;
executing a surface energy modification treatment, the surface energy modification treatment modifying at least one of the first surface energy value and the second surface energy value such that a contact angle value of an interface between the fill material in liquid form and the sidewall surfaces or the floor surfaces is less than 60 degrees; and
depositing the fill material on the substrate via spin-on deposition after executing the surface energy modification treatment such that the fill material fills the defined openings being in contact with the sidewall surfaces and the floor surfaces.

US Pat. No. 10,141,180

SILICON WAFER AND METHOD FOR MANUFACTURING THE SAME

GLOBALWAFERS JAPAN CO., L...

1. A method of manufacturing a silicon wafer comprising:subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by a Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds and then cooled at a cooling rate of 3 to 5° C./second, wherein the rapid thermal process is performed in an oxygen-containing atmosphere comprising oxygen gas having a partial pressure of 20 to 100%;
calculating a surface layer of the wafer having a thickness of not less X [?m] according to the following equations (1) to (3):
X [?m]=a [?m]+b [?m]  (1);
a [?m]=(0.0031×(said maximum temperature) [° C.]?3.1)×6.4×(cooling rate)?0.4 [° C./second]  (2); and
b [?m]=a/(solid solubility limit of oxygen) [atoms/cm3]/(oxygen concentration in substrate) [atoms/cm3]  (3); and
removing the surface layer having the thickness of not less than X,
to obtain a silicon wafer comprising a laser scattering tomography defect (LSTD) density of less than 1×10?1/cm2 and a slip dislocation length of 5 mm or less.

US Pat. No. 10,141,177

MASS SPECTROMETER USING GASTIGHT RADIO FREQUENCY ION GUIDE

1. A mass spectrometer, comprising:(a) a vacuum recipient containing ion handling elements, the vacuum recipient having a plurality of walls which define a gastight volume and comprise at least one of an entrance and exit, wherein different portions of an ion path pass at least one of the entrance and exit and run through the gastight volume; and
(b) a gastight radio frequency ion guide having an ion passage along an axis and being mounted gastight to at least one of the entrance and exit as to extend the gastight volume and continue the ion path in its ion passage outside the vacuum recipient,
wherein the gastight radio frequency ion guide is located outside the vacuum recipient in an environment of ambient pressure in order to lower pumping requirements for the mass spectrometer.

US Pat. No. 10,141,174

METHOD FOR EXAMINING A GAS BY MASS SPECTROMETRY AND MASS SPECTROMETER

Carl Zeiss SMT GmbH, Obe...

1. A method, comprising:producing ions by ionizing a gas;
storing at least some of the ions in an FT ion trap; and
detecting at least some of the ions in the FT ion trap,
wherein at least one of the following holds:
i) producing the ions comprises exposing the ions to an IFT excitation based on a mass-to-charge ratio of the ions;
ii) storing the ions in the FT ion trap comprises exposing the ions to an IFT excitation based on a mass-to-charge ratio of the ions; and
iii) before detecting the ions in the FT ion trap, exposing the ions to an IFT excitation based on a mass-to-charge ratio of the ions, and
wherein:
a degree of excitation and/or a phase angle of the IFT excitation are varied between a first excitation frequency and a second excitation frequency; and
both the first excitation frequency and the second excitation frequency deviate from a predetermined excitation frequency by no more than 10%.

US Pat. No. 10,141,173

SYSTEMS FOR SEPARATING IONS AND NEUTRALS AND METHODS OF OPERATING THE SAME

Rapiscan Systems, Inc., ...

1. A mass spectrometer system comprising:a sample injection device defining a sample injection aperture;
an ion trap defining an ion outlet aperture, said ion trap coupled to said sample injection device;
a detector positioned downstream of said ion outlet aperture, wherein the detector is positioned in a detector enclosure defining a detector chamber;
an ion source coupled to said ion trap, said ion source configured to ionize a sample injected into said ion trap and generate a plurality of ionized molecules within said ion trap, said ion trap configured to maintain said plurality of ionized molecules therein while a plurality of neutral molecules migrate out of said ion trap, and into the detector chamber, until a predetermined pressure is attained in said ion trap;
a first vacuum pump coupled to the ion trap wherein the first vacuum pump is configured to decrease a pressure in the ion trap; and
a second vacuum pump coupled to the detector chamber wherein the second vacuum pump is configured to decrease a pressure in the detector chamber such that a pressure in the detector chamber induced by the neutral molecules therein decays at a predetermined rate.

US Pat. No. 10,141,170

DEVICE FOR MASS SPECTROMETRY

TOFWERK AG, Thun (CH)

1. A device for mass spectrometry comprising:a) an ionization source;
b) a mass analyzer fluidly coupled to the ionization source;
c) an electronic data acquisition system for processing signals provided by the mass analyzer;whereas the electronic data acquisition system comprisesd) at least one analog-to-digital converter producing digitized data from the signals obtained from the mass analyzer;
e) a fast processing unit receiving the digitized data from said analog-to-digital converter;whereinf) the fast processing unit is programmed to continuously, in real time inspect the digitized data for events of interest measured by the mass spectrometer, wherein said inspection is based on a filter definition, the filter definition comprising at least one region of interest including a selection of values of m/Q and further comprising at least one filter criterion to be applied to the at least one region of interest, wherein the selection of values of m/Q is a subsection of all values of m/Q of an entire mass spectrum; and
g) the electronic data acquisition system is programmed to forward the digitized data representing mass spectra relating to events of interest for further analysis and to reject the digitized data representing mass spectra not relating to events of interest.

US Pat. No. 10,141,168

METHOD FOR CHARACTERISING A SAMPLE BY MASS SPECTROMETRY IMAGING

IMABIOTECH, Loos (FR)

1. A process for identifying by mass spectrometry imaging (MSI) a molecule of interest in a sample of interest, the process comprising:analyzing a spatial arrangement of a plurality of ions in the sample of interest from MSI data of said ions in said sample to determine morphometric features and/or texture features associated with said ions in said sample, the morphometric features defining geometrical patterns formed by a presence of said ions and mathematical dimensions of the geometrical patterns, the texture features defining an arrangement of the geometrical patterns in said sample;
comparing the morphometric and/or texture features associated with the plurality of ions in said sample of interest with morphometric and/or texture data associated with a plurality of ions in a reference sample;
identifying at least one characteristic ion of the sample; and
identifying the molecule corresponding to said identified ion.

US Pat. No. 10,141,164

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus comprising:a radio frequency (RF) power source connected between a reference electrode and a base stand to apply an RF voltage;
an electrostatic chuck arranged on the base stand;
a gas storage unit configured to store a gas, the gas storage unit being arranged in the base stand and including a gas introducing port;
a blocking mechanism configured to open and close the gas introducing port;
a control unit configured to control the blocking mechanism to open the gas introducing port; and
a connection unit configured to connect the gas storage unit and a space between a substrate set on the electrostatic chuck and the electrostatic chuck, wherein:
the apparatus is configured to introduce the gas into the gas storage unit from an outside gas source through the gas introducing port, and
the control unit is configured to open the gas introducing port when no RF voltage is applied between the reference electrode and the base stand by the RF power source.

US Pat. No. 10,141,163

CONTROLLING ION ENERGY WITHIN A PLASMA CHAMBER

Lam Research Corporation,...

1. A method comprising:generating a first sinusoidal radio frequency (RF) signal for providing to an upper electrode of a plasma chamber;
generating a second sinusoidal RF signal;
filtering the second sinusoidal RF signal to generate a nonsinusoidal RF signal having no off cycles;
amplifying the nonsinusoidal RF signal to generate an amplified nonsinusoidal RF signal;
filtering the amplified nonsinusoidal RF signal to generate a filtered nonsinusoidal RF signal having a series of pulses between consecutive off cycles; and
providing the filtered nonsinusoidal RF signal to a lower electrode of the plasma chamber.

US Pat. No. 10,141,161

ANGLE CONTROL FOR RADICALS AND REACTIVE NEUTRAL ION BEAMS

Varian Semiconductor Equi...

1. A workpiece processing apparatus, comprising:a plasma generator;
a plasma chamber; and
one extraction plate having a first aperture and a second aperture;
wherein charged ions are extracted through the first aperture at a first selected extraction angle, and reactive neutrals are passed through the second aperture at a second selected extraction angle, where the second aperture is different than the first aperture and comprises a suppressor to minimize charged ions passing through the second aperture by repelling or neutralizing the charged ions.

US Pat. No. 10,141,158

WAFER AND DUT INSPECTION APPARATUS AND METHOD USING THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A wafer and a device under test (DUT) inspection apparatus, comprising:a vacuum chamber;
a stage disposed in the vacuum chamber and near a first end of the vacuum chamber, wherein the stage is configured to hold a wafer or DUT;
an electron gun disposed in the vacuum chamber and near a second end of the vacuum chamber opposite to the first end for providing an E-beam;
a lens system disposed between the stage and the electron gun, wherein the lens system is a total reflective achromatic lens system comprising:
a first lens having a first aperture; and
a second lens having a second aperture aligned with the first aperture, the second lens is disposed between the electron gun and the first lens;
an optical mirror disposed between the lens system and the electron gun, wherein the optical mirror has a slit aligned with the second aperture, thereby allowing the E-beam to pass through the slit, the first aperture and the second aperture;
a beam shaping aperture disposed between the electron gun and the optical mirror;
a grating horizontally aligned with the optical mirror and configured to reflect towards the detector cathodoluminescence reflected from the optical mirror; and
a detector aligned with the grating, wherein the detector is configured to detect the cathodoluminescence for forming an image.

US Pat. No. 10,141,156

MEASUREMENT OF OVERLAY AND EDGE PLACEMENT ERRORS WITH AN ELECTRON BEAM COLUMN ARRAY

KLA-Tencor Corporation, ...

1. A metrology system comprising:a plurality of electron beam measurement columns, each spatially separated from an adjacent electron beam measurement column of the plurality of electron beam measurement columns by a fixed distance along a first direction, each electron beam measurement column including:
an electron beam source configured to generate a beam of primary electrons;
a beam deflector configured to adjust a location of incidence of the beam of primary electrons onto a specimen under measurement; and
a detector configured to detect secondary electrons from the specimen in response to the incident beam of primary electrons and generate an output signal based on the detected secondary electrons;
a specimen positioning subsystem configured to scan a specimen in a second direction aligned with a row of die disposed on the specimen, wherein the first direction is oriented at an oblique angle with respect to the second direction such that each of the plurality of electron beam columns performs a one dimensional measurement of the same row of features of a different row of die; and
a computing system configured to:
receive the output signals generated by each of the electron beam measurement columns; and
estimate an overlay value, an edge placement error value, or both, based on the output signals.

US Pat. No. 10,141,155

ELECTRON BEAM EMITTERS WITH RUTHENIUM COATING

KLA-Tencor Corporation, ...

1. An apparatus comprising:a silicon emitter, wherein the silicon emitter has a diameter of 100 nm or less; and
a protective cap layer disposed on an exterior surface of the silicon emitter, wherein the protective cap layer includes ruthenium.

US Pat. No. 10,141,154

ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a first substrate;
a first electrode on the first substrate;
a passivation layer on a side of the first electrode distal to the first substrate, the array substrate comprising a plurality of first vias in the passivation layer, each of which corresponds to a different part of the first electrode;
an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias; and
a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias;
wherein the at least one electron emission source comprises a first portion having a first end and a second portion having a second end;
the first end is in contact with the first electrode, the first portion is within a corresponding one of the plurality of dielectric blocks;
the second portion and the second end are outside the corresponding one of the plurality of dielectric blocks; and
the dielectric layer is made of a material consisting essentially of a resin.

US Pat. No. 10,141,152

DRIFT CHAMBER CONNECTION METHODS AND APPARATUS

1. A method for attaching a signal wire to a drift chamber, the method comprisingfeeding a signal wire through an end of a drift chamber;
feeding the signal wire through the dielectric tube;
extending the dielectric tube outwardly from the drift chamber end;
at a location on the outside of the drift chamber end, setting the extending dielectric tube and signal wire together to thereby fit the signal wire to the drift chamber end and gas seal the dielectric tube end;
feeding the signal wire through a second end of the drift chamber;
feeding the signal wire through the second dielectric tube;
extending the extending the second dielectric tube outwardly from the drift chamber second end; and
at a second location on the outside of the drift chamber second end, setting the extending dielectric second tube and signal wire together to thereby fit the signal wire to the drift chamber second end and gas seal the dielectric second tube.

US Pat. No. 10,141,151

FUSE WITH SEPARATING ELEMENT

Robert Bosch GmbH, Stutt...

1. A fuse (1) comprising:a U-shaped fusible element (2) with
a first portion (3),
a second portion (4) generally parallel to the first portion (3), and
a connecting portion (5) which connects the first portion (3) to the second portion (4),
such that the first portion (3), the second portion (4), and the connecting portion (5) define a plane,
a separating element (6) which is configured to prevent an arc between the first portion (3) and the second portion (4),
a first field-generating device (7a) for generating a first magnetic field in the region of the connecting portion (5), and
a second field-generating device (7b) for generating a second magnetic field in the region of the connecting portion (5),
wherein the first and second field-generating devices (7a, 7b) are permanent magnets,
wherein the first portion (3) of the fusible element (2) extends on a first side of the separating element (6),
wherein the second portion (4) of the fusible element (2) extends on a second side of the separating element (6), which is situated opposite the first side,
wherein the connecting portion (5) of the fusible element (2) extends on a third side of the separating element (6),
wherein the first and second field-generating devices (7a, 7b) are positioned on opposite sides of the fusible element (2) and on opposite sides of the plane, and
wherein the first and second magnetic fields are directed in such a manner that an arc, caused by a current, between the first portion (3) and the second portion (4) is directed toward the separating element (6).

US Pat. No. 10,141,146

FORCE-DISTANCE CONTROLLED MECHANICAL SWITCH

1. A switch comprising:a first elastic element;
a second elastic element;
an actuator-element mechanically coupled to a first side of the first elastic element and mechanically coupled to a first side of the second elastic element;
a first switching conductor mechanically coupled to a second side of the first elastic element;
a second switching conductor mechanically coupled to a second side of the second elastic element; and
a first strip conductor, a second strip conductor and a third strip conductor; and
wherein the first switching conductor is configured to move between a first conductor position and a second conductor position,
wherein the actuator-element is configured to move between a first position and a second position separated by a pre-defined actuator-element lift, thereby moving the first side of the first elastic element, and to move the first side of the second elastic element while moving between the first position and the second position,
wherein the first elastic element is configured to convert a movement of the first side of the first elastic element by the pre-defined actuator-element lift into a movement of the second side of the first elastic element with a pre-defined elastic force,
wherein the second elastic element is configured to convert the movement of the first side of the second elastic element by the pre-defined actuator-element lift into the movement of the second side of the second elastic element with the pre-defined elastic force,
wherein the first switching conductor and the second switching conductor are configured whereby, in the first conductor position, the first strip conductor is in contact with the first switching conductor, the second strip conductor is in contact with the first switching conductor and the second switching conductor is not in contact with the first strip conductor, the second strip conductor and the third strip conductor.

US Pat. No. 10,141,143

WEAR-BALANCED ELECTROMAGNETIC MOTOR CONTROL SWITCHING

Rockwell Automation Techn...

1. A method comprising:in a first switching operation of an electrical power switching system comprising three separately controllable single pole, single current-carrying path switching devices configured to provide three-phase power to a load, and control circuitry coupled to the switching devices to control closing and opening of the current-carrying paths, commanding at least one of the switching devices to open or close in advance of at least one other of the switching devices based upon a current zero-crossing or a predicted current zero-crossing of input three-phase power; and
in subsequent switching operations alternating which of the three switching devices is closed or opened in advance of another of the switching devices.

US Pat. No. 10,141,141

MAGNETICALLY ACTUATED SWITCH

S. J. Electro Systems, In...

1. A magnetically activated switch, comprising:an arm member having a first magnet, the first magnet including a first magnet portion and a second magnet portion spaced apart to form a channel therebetween;
an actuating member having a second magnet, the actuating member being configured and arranged to move relative to the arm member thereby moving the second magnet relative to the first magnet, the second magnet moving through the channel, the second magnet having a repulsion force to the first magnet, the second magnet having a north pole on a first side and a south pole on a second side, the first magnet portion having a north pole on a side adjacent the first side of the second magnet and the second magnet portion having a south pole on a side adjacent the second side of the second magnet when the second magnet is moving through the channel; and
a switch having a contact, wherein movement of the second magnet in a first direction past the first magnet positions the contact in an open position and movement of the second magnet in a second direction past the first magnet positions the contact in a closed position.

US Pat. No. 10,141,140

AIR CIRCUIT BREAKER

LSIS CO., LTD., Ayang-si...

1. An air circuit breaker comprising:an insulating cage provided with a plurality of contact plates;
movable contactors each inserted between the contact plates; and
fixed contactors brought into contact with or separated from the movable contactors in response to a movement of the movable contactors,
wherein each of the contact plates is provided with a recess,
wherein the recess is inclined toward an inside of the contact plates from rear sides of the contact plates to front sides of the contact plates,
wherein in a connected state, the movable contactors are pushed toward the insulating cage to be inserted between the contact plates and thus brought into contact with the contact plates, and
wherein a middle part of the movable contactors does not contact the contact plates by the recess.

US Pat. No. 10,141,139

MULTIPLE POSITION ELECTRICAL SWITCH

1. An electrical switch comprising:a casing made of insulating material;
a fixed upper contact and a fixed lower contact, wherein the fixed upper contact and the fixed lower contact are vertically opposed;
a mobile contact blade, wherein the mobile contact blade is elastically deformable between two switching states such that a contact part of the mobile contact blade is in electrical contact with the fixed lower contact or with the fixed upper contact, respectively;
a fixed support bearing the mobile contact blade, wherein the fixed support comprises two parallel vertical support plates spaced transversely apart from one another, further wherein each vertical support plate comprises a vertical front support branch and a vertical rear support branch spaced apart longitudinally from one another, and further wherein each of the vertical front support branch and the vertical rear support branch comprises a transversely oriented horizontal notch, in the bottom of which is housed a transverse free edge of a respective front and rear section of the mobile contact blade; and
an actuator, wherein the actuator collaborates with a part of the mobile contact blade to bring about a change in switching state.

US Pat. No. 10,141,138

SWITCH ASSEMBLY

FORD GLOBAL TECHNOLOGIES,...

1. A switch assembly, comprising:a switch including a button and an arm extending from the button along a height direction, the arm including first and second contact portions spaced along a longitudinal direction; and
a slider unit extending along a width direction, including a polymeric nose, positioned between the arm and a spring along the width direction to contact the first and second contact portions, respectively, at first and second engagement positions.

US Pat. No. 10,141,137

LATCH-FREE ACTUATORS

ABB Schweiz AG, Baden (C...

1. A mechanism, said mechanism comprising:a movable arm;
first biasing means operable to apply a force to move said movable arm in a first direction;
a yieldable support having a rigid configuration defining a generally straight axis and a flexible configuration defining a non-straight axis;
said yieldable support operable in said rigid configuration to support a compression force along said straight axis due to and countering said first biasing means so that said movable arm is prevented from movement in said first direction; and
said yieldable support operable, by applying a tripping force, to said yieldable support to transition said rigid configuration to said flexible configuration to withdraw support of the compression force and allow said movable arm to be moved by said first biasing means in said first direction;
wherein said yieldable support comprises a flat elongated member having a curved cross-section.

US Pat. No. 10,141,136

LIGHT SWITCH ACTUATOR

1. A mechanism for operating an electric switch comprising:a toggle switch, a wall plate, a toggle attachment, a plurality of eyebolts, and a plurality of cords;
wherein the plurality of eyebolts attach to the wall plate;
wherein the toggle attachment attaches the plurality of cords to a toggle of the toggle switch;
wherein the mechanism for operating the electric switch is a kit;
wherein the toggle switch is further defined with a toggle;
wherein the toggle switch is further defined with one or more interior screw threads;
wherein the wall plate is placed over the toggle switch;
wherein the wall plate is further defined with a first switch screw hole and a second switch screw hole;
wherein the toggle actuates the toggle switch;
wherein the first switch screw hole and second switch screw hole allow the wall plate to be attached to the toggle switch;
wherein the first switch screw hole is a hole that is formed through the wall plate;
wherein the second switch screw hole is a hole that is formed through the wall plate;
wherein the toggle attachment is formed from an elastomeric material;
wherein the elastomeric material is deformed as the toggle attachment is attached to the toggle;
wherein any eyebolt selected from the plurality of eyebolts is sized such that the selected eyebolt can be inserted through a screw hole selected from the group consisting of the first switch screw hole of the wall plate and the second switch screw hole of the wall plate;
wherein any eyebolt selected from the plurality of eyebolts is sized such that the selected eyebolt can be screwed directly into an interior screw thread selected from the one or more interior screw threads;
wherein each of the plurality of cords is a cord;
wherein an end of each of the plurality of cords attaches to the toggle attachment;
wherein the plurality of cords are arranged such that pulling on a cord selected form the plurality of cords will actuate the toggle switch;
wherein the toggle attachment comprises an elastic ring;
wherein the elastic ring is a ring shaped structure;
wherein the elastic ring further comprises a ring aperture;
wherein the elastic ring is formed from an elastomeric material;
wherein the ring aperture is placed over the toggle of the toggle switch;
wherein the ring aperture is sized such that the ring aperture must be deformed in order to fit over the toggle of the toggle switch;
wherein as the elastic ring returns to its relaxed shape the ring aperture applies a force to the toggle;
wherein the plurality of eyebolts attach the wall plate to the toggle switch;
wherein each of the plurality of eyebolts is an eyebolt;
wherein each of the plurality of eyebolts is further formed with an exterior screw thread;
wherein the plurality of eyebolts comprises a first eyebolt and a second eyebolt;
wherein the first eyebolt attaches the wall plate to the toggle switch;
wherein the second eyebolt attaches the wall plate to the toggle switch;
wherein the first eyebolt is sized such that the first eyebolt inserts through the first switch screw hole;
wherein the first eyebolt is sized such that the first eyebolt screws into a first interior screw thread selected from the one or more interior screw threads;
wherein the second eyebolt is sized such that the second eyebolt inserts through the second switch screw hole;
wherein the second eyebolt is sized such that the second eyebolt screws into a second interior screw thread selected from the one or more interior screw threads.

US Pat. No. 10,141,132

DUAL-ACTUATOR SWITCH

SOLTEAM ELECTRONICS (DONG...

1. A dual-actuator switch, comprising:a base, having an accommodating space;
a first electrical connection member, being disposed in the accommodating space and having a first electrical terminal and a second electrical terminal;
a second electrical connection member, being disposed in the accommodating space for facing the first electrical connection member, and having a third electrical terminal and a fourth electrical terminal for respectively connecting the first electrical terminal and the second electrical terminal;
a first isolation sleeve cylinder, being disposed in the accommodating space and provided with a first protrusion member on the outer wall thereof;
a second isolation sleeve cylinder, being disposed in the accommodating space and provided with a second protrusion member on the outer wall thereof;
a first return spring, being disposed in the first isolation sleeve cylinder;
a first post-shaped actuator, being disposed in the first isolation sleeve cylinder and connecting with the first return spring;
a second return spring, being disposed in the second isolation sleeve cylinder;
a second post-shaped actuator, being disposed in the second isolation sleeve cylinder and connecting with the second return spring; and
a cover, being assembled with the base for sheltering the accommodating space, and having two openings;
wherein a first pressing portion of the first post-shaped actuator and a second pressing portion of the second post-shaped actuator are extended out of the cover via the two openings.

US Pat. No. 10,141,129

INTERLOCK APPARATUS OF RING MAIN UNIT

LSIS CO., LTD., Anyang-s...

1. An interlock apparatus of a ring main unit including two or more switches where a plurality of insertion holes into which a handle can be inserted are respectively provided for controlling a closed or cutoff state, the interlock apparatus comprising:a plate disposed in front of each of the plurality of insertion holes, wherein when one of the plurality of insertion holes is opened, the plate moves so that another insertion hole is closed, a plurality of fitting grooves formed in an upper end of the plate;
an indicator provided in each of the two or more switches, wherein the indicator rotates by controlling a closed or cutoff state of each of the two or more switches; and
a movement prevention member provided in each of the two or more switches to prevent a movement of the plate, wherein when one of the switches is in a closed state, the movement prevention member is inserted into one of the plurality of fitting grooves according to a rotation of the indicator, thereby maintaining an open state of the one insertion hole and a closed state of the other insertion hole.

US Pat. No. 10,141,128

METHOD AND APPARATUS FOR AUTHENTICATING AND DETECTING CIRCUIT BREAKER INTEGRITY

Eaton Corporation, Cleve...

1. A circuit breaker apparatus comprising:a housing;
a circuit disposed in the housing and configured to connect a power line to a load via one or more conductors and provide circuit protection for the one or more conductors and the load;
a display attached to an outside surface of the housing;
a controller;
a power control device electrically coupled to the display and the controller, and configured to provide power to the controller when the apparatus is being tampered with; and
a first RFID tag attached to the apparatus, the first RFID tag containing authentication data therein;
wherein the controller is configured to, when powered, cause the power control device to cause the display to change from a first state to a second state, wherein the first state indicates that the apparatus is authenticated and the second state indicates that the apparatus has been tampered with; and
wherein the controller is further configured to initialize the display to the first state by:
retrieving the authentication data from the first RFID tag,
retrieving a key stored external to the apparatus,
using the key to determine whether the authentication data retrieved from the first RFID tag is valid, and
upon determining that the authentication data retrieved from the first RFID tag is valid, causing the power control device to initialize the display to the first state.

US Pat. No. 10,141,126

VIBRATION-LIMITING DEVICE FOR AN APPARATUS COMPRISING A SWITCHGEAR AND A SWITCHING DEVICE, SUCH AS A CIRCUIT BREAKER, AND APPARATUS COMPRISING SAID VIBRATION-LIMITING DEVICE

ABB Schweiz AG, Baden (C...

1. An apparatus comprising a switchgear having at least one couple of stationary conducting terminals and a switching device having at least one couple of corresponding movable conducting terminals, wherein the switching device is movable with respect to the switchgear along a connection/disconnection direction (CD) between a connection position, wherein the switching device is electrically and mechanically connected to the switchgear by engagement of the movable conducting terminals with the corresponding stationary contacting terminals through contact assemblies coupled either to the movable conducting terminals or to the stationary conducting terminals, and a disconnection position, wherein the switching device and the switchgear are electrically and mechanically disconnected, at least one vibration-limiting device integrally coupled to either one movable conducting terminal of said at least one couple of movable conducting terminals or to one corresponding stationary conducting terminal of said at least one couple of stationary conducting terminals and conformed such that:when the switching device is approaching the connection position moving along said connection/disconnection direction (CD), the vibration-limiting device does not interfere with the other of the one movable conducting terminal or the one corresponding stationary conducting terminal;
when the switching device is in the connection position, in case of vibrations of the one movable conducting terminal transversal to said connection/disconnection direction (CD), the vibration-limiting device interferes with the other of the one movable conducting terminal or the one corresponding stationary conducting terminal so to limit a vibrations amplitude;
wherein the vibration-limiting device is made of an electrically non-conductive material.

US Pat. No. 10,141,125

CONTACT FOR BUS PLUG SWITCHES

1. A single-pole electrical switch for a bus plug, comprising:a stationary contact having a first contact surface;
a moveable contact having a second contact surface, the moveable contact mounted to a contact head pivotally-mounted to a rotating contact arm about a pivot axis, the moveable contact rotatably moveable between an open position and a closed position, the closed position bringing the first and second contact surfaces into mutual contact and completing thereby an electrical circuit, wherein in the closed position the pivot axis is entirely in a plane bisecting the second contact surface at a right angle;
a switching means to move the contacts between the open position and the closed position;
whereby, when the switching means moves the movable contact into the closed position, the contact surfaces are aligned by articulation of the pivotally-mounted second contact, and pitting of the contact surfaces by electric current flowing there through is prevented by intimate engagement.

US Pat. No. 10,141,121

SUPER ELECTRICAL BATTERY

1. An electric energy storage device comprising:a first conductor layer in a multilayer structure both surfaces of which comprising a first ionic or dipole material layer adjacent to an entire conductor surface thereof and being insulated electrically;
a second conductor layer in the multilayer structure, both surfaces of which comprising a second ionic or dipole material layer adjacent to an entire conductor surface thereof and being insulated electrically, wherein a bilayer hetero-structure is comprised of the first and second conductor layers and the ionic material layer sandwiched therebetween,
wherein the multilayer structure is comprised of the millions of conductor layers of nanometer thickness, both conductor surfaces of which being coated with the ionic or dipole materials across the enter surface thereof and being insulated electrically,
wherein the first and second conductor layers form the bilayers configured to store an electrical energy in the bilayer in a form of binding energy,
wherein the multilayer is consisted of the millions of the bilayers,
wherein the ionic or dipole material layers comprise an ionic or dipole material selected from the group consisting of MgSO4, LiPF6, LiCl04, LiN(CF3S02)2, LiBF4, LiCF3S03, LiSbF6, Li4Ti5012, ionic polymers, ionic mineral materials, and dipole materials, wherein the ionic or dipole material is MgSO4,
wherein a thickness of the conductor layers and the interval between the conductor layers are a nanometer scale to form a quantum dipole system of excitons and ions, so that an interaction between excitonic dipoles and ionic dipoles occur in the bilayer hetero-structure;
a positive electrode attached to the first conductor layer of the multilayer structure; and
a negative electrode attached to the last conductor layer of the multilayer structure,
wherein every conductor layer in the multilayer structure is disconnected, insulated and isolated from an electric current, and each conductor layer is not a current collector, but an excitonic dipole collector,
wherein neither electronic nor ionic current is allowed in the multilayer structure except for the electrodes which are attached to a copper (conductor) sheet, because the current in the multilayer structure destroys the excitonic dipoles and the ionic dipoles,
wherein the first conductor layer is stacked on top of the second conductor layer with a nanometer-scale interval and the ionic or dipole material layer is sandwiched therebetween so as to form the bilayer structure,
wherein the electrical energy is stored in the bilayer by applying a DC voltage in a direction perpendicular to a layer plane sheet to the positive and negative electrodes,
wherein the stored an electrical energy is discharged and output to the electrodes by using an external AC field in a predetermined frequency range as a guiding wave with trigger power,
wherein the conductor layer is adopted because low excitation energy of valence electrons is required for jumping to a conduction band, and the nanometer thickness of the conductor layer is adopted because a reciprocal of a length of a layer period in the vertical direction shall be large for a polaron formation at an interface between the conductor layer and the ionic layer,
wherein the length of the layer period in the multilayer structure is in a range of the nanometer scale to have a quantum dipole interaction in the bilayers,
wherein the length of the layer period in the multilayer structure is in the range of nanometer scale for an electrical energy storage device, so that a spatial period of the conductor layers in the vertical direction is directly related to the polaron formation in the bilayers, and the thickness of conductor layers as well,
wherein a linear chain of excitonic dipoles and ionic dipoles is introduced and formed in the vertical direction to the conductor layers, and an optical vibration is governed to be tuned by the acoustical vibration and the frequencies of the vibrations as well,
wherein the layer thickness and interval between the conductor layers are in the range of the nanometer scale for formation of the quantum dipole system and exciton,
wherein the layer thickness and interval in the multilayer structure are in the range of the nanometer scale in order to have a polaron interaction effective, and the polaron formation at the interface between the conductor layer and the ionic layer is important in a storing an electrical energy in the bilayers, because an excitonic and ionic dipole structure has been transformed into an excitonic bipolaron which leads to the formation of a stable anti-ferroelectric structure in the bilayers,
wherein when an external field is applied, a polarization of ions and an excitation of the valence electrons to conduction band create a collective dipole in a multilayer system through a propagation of a dipole field (pseudo spin wave) from the electrodes to the empty states,
wherein an interaction energy between an excitonic dipole and an ionic dipole depends upon the directions and positions of the excitonic dipoles and ionic dipoles in the bilayer, which is a quasi-one dimensional interaction in the vertical direction to the conductor layers,
wherein in the nanometer scale, a charge polarization in a quantum hetero-structure is a quantum dipole,
wherein the states of electronic and ionic dipoles are described in the eigenstates of two-level system, which represents a transition,
wherein the interaction terms of excitonic dipoles and ionic dipoles describe a propagation of pseudo spin waves across the layers in the vertical direction to the layer plane sheet,
wherein the pseudo spin waves propagate crossing the conductor layers by an applied power, and as the pseudo spin waves propagate in the vertical direction, the excitonic dipoles and ionic dipoles spread all over the multilayer structure as the applied power continues to be provided by the external field,
wherein a mechanism for a charging process is induced by the polaron interaction, and by the polaron interaction and Coulomb force, the excitonic dipoles and ionic dipoles keep transforming into the anti-ferroelectric nanostructures in charge,
wherein the polaron interaction is so strong that the excitons in the conductor layer have been broken into the electrons and the holes to form the positive polarons and the negative polarons in the bilayers,
wherein the positive polarons on one conductor layer and the negative polarons on the other conductor are combined together to form excitonic bipolarons in the bilayers, and
wherein a mechanism for a storing energy in the multilayer structure is a transformation process from the quantum dipole system creating into an anti-ferroelectric nanostructure created by the applied power in the bilayers.

US Pat. No. 10,141,120

POWER STORAGE SYSTEM AND MANUFACTURING METHOD THEREOF AND SECONDARY BATTERY AND CAPACITOR

Semiconductor Energy Labo...

1. A power storage system comprising:a negative electrode comprising:
a current collector;
a negative electrode active material layer comprising a crystalline silicon film over and in contact with an upper surface of the current collector; and
a conductive oxide over and in contact with an upper surface of the crystalline silicon film,
wherein the conductive oxide comprises
one selected from the group consisting of nickel, copper, indium, tin, and silver.

US Pat. No. 10,141,113

CERAMIC ELECTRONIC COMPONENT

TDK Corporation, Tokyo (...

1. A ceramic electronic component comprising an interior part and an exterior part, whereinthe interior part includes an interior part dielectric layer and an internal electrode layer,
the exterior part includes an exterior part dielectric layer, the exterior part is positioned outside the interior part along a laminating direction thereof,
the interior part dielectric layer and the exterior part dielectric layer respectively contain barium titanate as a main component, and
????0.20 and ?/??0.88 are satisfied, where
? mol part is an amount of a rare earth element contained in the interior part dielectric layer, provided that an amount of barium titanate contained in the interior part dielectric layer is 100 mol parts in terms of BaTiO3 and
? mol part is an amount of a rare earth element contained in the exterior part dielectric layer, provided that an amount of barium titanate contained in the exterior part dielectric layer is 100 mol parts in terms of BaTiO3.

US Pat. No. 10,141,111

METHOD OF MANUFACTURING STACKED CERAMIC CAPACITOR INCLUDING IDENTIFYING DIRECTION OF STACKING IN STACKED CERAMIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A method of manufacturing a stacked ceramic capacitor, comprising steps of:fabricating a stacked ceramic capacitor including a plurality of internal electrodes stacked in one direction; and
identifying the one direction of stacking of the plurality of internal electrodes in the stacked ceramic capacitor by the steps of:
measuring a variation in magnetic flux density at least at a time of passage of the stacked ceramic capacitor by causing the stacked ceramic capacitor to pass between a magnetism generation apparatus and a magnetic flux density measurement instrument while a density of magnetic flux generated from the magnetism generation apparatus is measured with the magnetic flux density measurement instrument; and
wherein said identifying the one direction of stacking of the plurality of internal electrodes in the stacked ceramic capacitor is based on a result of measurement of the magnetic flux density obtained from the step of measuring a variation in magnetic flux density.

US Pat. No. 10,141,105

WIRELESS POWER TRANSMISSION SYSTEM FOR FREE-POSITION WIRELESS CHARGING OF MULTIPLE DEVICES

KOREA ELECTROTECHNOLOGY R...

1. A coil assembly, comprising:a coil part through which a current flows in a direction of an input current applied from a first end of the coil assembly, the coil part being disposed between the first end and a second end of the coil assembly,
wherein the coil part comprises:
a first coil part, two or more coils are connected in parallel and concentrically wound one or more times towards a center thereof so that the current flows in a direction of the input current; and
wherein the coil assembly transfers a wireless power via magnetic coupling with respective target coils, relative center positions of which are horizontally different from each other.

US Pat. No. 10,141,103

POWER SUPPLY CIRCUIT

Murata Manufacturing Co.,...

1. A power supply circuit comprising:a DC-DC converter, including a switching element that switches a DC input voltage inputted from a DC power source, that supplies a DC output voltage according to an on-off duty ratio of the switching element to a load; and
a choke coil, including a pair of coils wound in mutually opposite directions, in which the paired coils are connected between the DC power source and the DC-DC converter,
wherein in the choke coil, a self-resonating frequency in a common mode, in which a current flows in the paired coils in the same direction, is higher than a self-resonating frequency in a normal mode, in which the current flows in the paired coils in mutually opposite directions; and
in the choke coil, a normal mode impedance at the highest frequency in a predetermined low-frequency band is higher than a common mode impedance at the lowest frequency in a high-frequency band that is higher than the low-frequency band.

US Pat. No. 10,141,099

ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a magnetic body; and
an internal coil structure embedded in the magnetic body, wherein
the internal coil structure includes a first coil pattern part and a second coil pattern part formed on the first coil pattern part, and
an entire outermost coil turn of the first coil pattern part is thicker than an inner coil turn thereof, wherein the second coil pattern part has a non-uniform thickness such that a thickness from an uppermost surface of the outermost coil turn of the first coil pattern part to an uppermost surface of an outermost coil turn of the second coil pattern part is smaller than a thickness from an uppermost surface of the inner coil turn of the first coil pattern part to an uppermost surface of an inner coil turn of the second coil pattern part.

US Pat. No. 10,141,097

ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a magnetic body;
a coil pattern embedded in the magnetic body and including internal coil parts having a spiral shape and lead parts connected to ends of the internal coil parts and externally exposed from the magnetic body; and
external electrodes disposed on outer surfaces of the magnetic body and connected to the lead parts,
wherein a thickness of each of the lead parts is thinner than a thickness of each of the internal coil parts,
the lead parts do not overlap the internal coil parts when viewed in a thickness direction of the magnetic body,
the lead parts extend to be exposed only at opposite end surfaces of the magnetic body,
0.6?b/a<1 is satisfied, in which a is the thickness of the internal coil part and b is the thickness of the lead part,
a thickness of each of cover regions covering an upper portion and a lower portion of the coil pattern in the magnetic body is 150 ?m or less, and
the external electrodes are formed of a conductive paste.

US Pat. No. 10,141,095

INDUCTOR COOLING SYSTEMS AND METHODS

Ford Global Technologies,...

1. A vehicle inductor cooling system, comprising:an inductor assembly;
a flange extending continuously around a mid-portion of the inductor assembly and including a first recess;
an inductor cover having a sealing surface forming a seal with the flange;
a cavity defined by the inductor cover and the inductor assembly; and
a first opening defined in the inductor cover in fluid communication with the first recess to provide coolant to the cavity.

US Pat. No. 10,141,093

REACTOR

AUTONETWORKS TECHNOLOGIES...

1. A reactor comprising:a coil made of a wound coil wire;
a magnetic core on which the coil is arranged, and that forms a closed magnetic path, wherein the magnetic core has an inner core section that is arranged on an inside of the coil; and
a heat dissipating sheet that is interposed at least partially between an inner circumferential surface of the coil and an outer circumferential surface of the inner core section that is opposite to the inner circumferential surface of the coil, wherein:
the heat dissipating sheet is in contact with the coil and the inner core section and the heat dissipating sheet is only at a lower surface of the inner core section, and
the inner core section includes a middle body section forming the magnetic path, and a middle resin molded section that covers at least a part of an outer circumferential surface of the middle body section.

US Pat. No. 10,141,021

DISTINGUISHING HEVC PICTURES FOR TRICK MODE OPERATIONS

CISCO TECHNOLOGY, INC., ...

1. An apparatus comprising:a memory; and
a processor configured to execute instructions stored on the memory, the instructions comprising:
providing a video program in a transport stream, the transport stream including an elementary stream corresponding to a High Efficiency Video Coding (HEVC) bitstream; and
providing a respective tier number to respective ones of a plurality of pictures in the elementary stream, the respective tier number being provided in a transport stream packet that corresponds to a start of the respective ones of the plurality of pictures,
wherein the respective tier number comprises a lowest tier number when the respective ones of the plurality of pictures comprise an Intra Random Access Point (“IRAP”) picture of the HEVC bitstream,
wherein the respective tier number comprises the lowest tier number plus 1 when the respective ones of the plurality of pictures do not comprise an IRAP picture of the HEVC bitstream and have a temporal identifier comprising 0,
wherein reference pictures are extracted from the elementary stream based on the respective tier number to provide a requested trick mode, and
wherein a predetermined tier number is assigned to a highest tier number that is assigned to the reference pictures that are intended to be extracted for trick mode.

US Pat. No. 10,141,018

METHOD AND SYSTEM FOR OPTICAL DATA STORAGE

Shanghai Naguang Informat...

1. A method of recording optically readable data, the method employing a provided recording medium which comprises an optically active material able to induce a change in properties of the medium in the presence of optical radiation having a first characteristic, and wherein the change in properties can be inhibited by optical radiation having a second characteristic, the method comprising: irradiating a region of the recording medium with a first beam of optical radiation having the first characteristic, the beam having a sufficient intensity within a central portion of the irradiated region and being of sufficient duration to cause an optically induced change in properties of the recording medium; and simultaneously irradiating the region of the recording medium with a second beam of optical radiation having the second characteristic, the second beam having a local intensity minimum within the central portion of the irradiated region, and a local intensity maximum in at least one portion of the irradiated region adjacent to the central portion which is sufficient to inhibit the optically induced change in properties of the recording medium.

US Pat. No. 10,141,016

BALANCED DELAY AND RESOLUTION FOR TIMING BASED SERVO SYSTEMS

INTERNATIONAL BUSINESS MA...

1. A tape drive-implemented method, comprising:determining a number of lateral position estimates to use for calculating a lateral position value;
receiving lateral position estimates from a single servo channel;
calculating the lateral position value by using the number of lateral position estimates; and
using the lateral position value to control a tape head actuator.

US Pat. No. 10,141,014

WRITE HEAD WITH REDUCED TRAILING SHIELD—SIDE SHIELD SPACING

SEAGATE TECHNOLOGY LLC, ...

1. An apparatus comprising:a bearing surface;
a write pole having a front surface that forms a portion of the bearing surface, the front surface having a leading edge and a trailing edge, the write pole further comprising side edges connecting the leading edge to the trailing edge at the bearing surface;
side shields proximate to the side edges of the write pole;
a trailing shield over the write pole and the side shields;
a trailing shield-write pole gap between the trailing edge of the write pole and the trailing shield; and
a trailing shield-side shield gap between the trailing shield and the side shields, the trailing shield-side shield gap being substantially less that the trailing shield-write pole gap,
the trailing shield-side shield gap comprises a single layer comprising a first material,
the trailer shield-write pole gap comprises multiple layers with at least one of the multiple layers comprising the first material, the multiple layers comprising:
a first thin metal layer;
an insulation layer; and
a second thin metal layer.

US Pat. No. 10,141,011

CONVERSATION QUALITY ANALYSIS

Avaya Inc., Basking Ridg...

1. A method of analyzing a conversation between a plurality of participants, comprising:in a processing system coupled to a storage system that stores the conversation:
determining a first speaker from the plurality of participants;
determining a second speaker from the plurality of participants;
determining a first plurality of turns comprising portions of the conversation when the first speaker is speaking;
determining a second plurality of turns comprising portions of the conversation when the second speaker is speaking; and
determining a characterization for quality of the conversation based on gaps between turns of the first plurality of turns and turns of the second plurality of turns and further based on a plurality of hesitations within turns of the first plurality of turns and the second plurality of turns, wherein each hesitation comprises one or more gaps within speech of a turn that is below a threshold amount of time that indicates when one turn ends and a second turn begins.

US Pat. No. 10,141,009

SYSTEM AND METHOD FOR CLUSTER-BASED AUDIO EVENT DETECTION

Pindrop Security, Inc., ...

1. A computer-implemented method for audio event detection, comprising:forming clusters of audio frames of an audio signal using K-means and at least one Gaussian mixture model (GMM), wherein each cluster includes audio frames having similar features, and wherein a number k equal to a total number of the clusters of audio frames is equal to 1 plus a ceiling function applied to a quotient obtained by dividing a duration of a recording of the audio signal by an average duration of the clusters of audio frames; and
determining, for at least one of the clusters of audio frames, whether the cluster includes a type of sound data using a supervised classifier.

US Pat. No. 10,141,008

REAL-TIME VOICE MASKING IN A COMPUTER NETWORK

Interviewing.io, Inc., S...

1. A computer system, comprising one or more hardware computer processors programmed, via executable code instructions, to:receive an audio signal representing at least a portion of speech;
split the audio signal into a plurality of overlapping segments;
generate a frequency domain representation of a current signal segment in the plurality of overlapping segments, wherein the frequency domain representation comprises components corresponding to a plurality of frequency bins;
generate, from the frequency domain representation of the current signal segment, a polar representation comprising a magnitude component and a phase component for each of the frequency bins;
generate a refined frequency domain representation of the current signal segment based on a comparison, for each of the frequency bins, between a first phase component from the current signal segment and a second phase component from a prior signal segment;
calculate an initial cepstrum from the refined frequency domain representation;
calculate a spectral envelope from the initial cepstrum using iterative smoothing with a resolution lower than a resolution of the frequency domain representation, wherein the iterative smoothing terminates after a predetermined number of iterations or a predetermined degree of convergence is reached;
calculate an excitation spectrum from the refined frequency domain representation and the spectral envelope;
rescale the spectral envelope based on a formant adjustment parameter to obtain a modified spectral envelope, wherein the spectral envelope is distinct from the current signal segment, the frequency domain representation, and the initial cepstrum;
calculate a modified frequency domain representation by combining the modified spectral envelope and the excitation spectrum;
synthesize a modified signal segment from the modified frequency domain representation; and
transmit the modified signal segment over a computer network.

US Pat. No. 10,141,007

SOUND/VIBRATION SPECTRUM ANALYZING DEVICE AND METHODS OF ACQUIRING AND ANALYZING FREQUENCY INFORMATION

SAMSUNG ELECTRONICS CO., ...

22. A method of analyzing a sound and vibration spectrum using a plurality of resonators having different center frequencies, the method comprising:acquiring a first frequency signal of a first resonance mode of at least some of the plurality of resonators;
acquiring a second frequency signal of a second resonance mode of the at least some of the plurality of resonators; and
analyzing each of the first frequency signal of the first resonance mode and the second frequency signal of the second resonance mode.

US Pat. No. 10,141,006

ARTIFICIAL INTELLIGENCE SYSTEM FOR IMPROVING ACCESSIBILITY OF DIGITIZED SPEECH

AMAZON TECHNOLOGIES, INC....

1. An artificial intelligence system comprising:one or more memories storing computer-executable instructions; and
one or more hardware processors, to execute the computer-executable instructions to:
access webpage data including visual data for rendering visible elements of a webpage and audio data for rendering audible elements that include speech representative of at least a subset of the visible elements of the webpage;
generate text data based on the audio data using a speech-to-text module, the text data including a transcription of the audible elements;
determine, based on the text data, one or more of:
a repeated string in the text data;
a semantic error in the text data;
a total quantity of text, in the text data, that exceeds a threshold total quantity;
a quantity of text, in the text data, that corresponds to a particular visible feature of the webpage, that is less than a threshold minimum value;
a quantity of text, in the text data, that corresponds to the particular visible feature, that is greater than a threshold maximum value; or
a separation between at least a portion of the text data and the particular visible feature that exceeds a threshold separation;
access first user data indicative of first user interactions with a visible element of the webpage;
determine an audible element that corresponds to the visible element;
access second user data indicative of second user interactions with the audible element;
determine one or more differences between the first user data and the second user data, the one or more differences indicating that the first user interactions with the visible element exceed the second user interactions with the audible element; and
based on the text data and the one or more differences, modify the audio data by one or more of:
removing at least a portion of the audible element;
moving the audible element from a first location in the webpage to a second location subsequent to the first location; or
modifying a portion of the audio data that corresponds to the one or more of the repeated text string, the semantic error, the total quantity of text that exceeds the threshold quantity, the quantity of text that is less than the threshold minimum value, the quantity of text that is greater than the threshold maximum value, or the separation.

US Pat. No. 10,141,005

NOISE DETECTION AND REMOVAL SYSTEMS, AND RELATED METHODS

Apple Inc., Cupertino, C...

1. A method for removing an unwanted target signal from an observed signal, the method comprising:assessing each of a plurality of regions of an observed signal to determine whether the respective region includes a component of an unwanted target signal from a probabilistic correlation between a prior event and a presence of the unwanted target signal following the prior event, wherein each region spans a selected number of samples of the observed signal, and the selected number of samples in each region is substantially less than a total number of samples of the observed signal, wherein the unwanted target signal comprises one or more of a stationary signal, a non-stationary signal, and a colored signal;
in response to determining one of the regions contains the component of the unwanted target signal, searching the observed signal within the respective region and over a selected number of samples adjacent the respective region for one or more other components of the unwanted target signal;
identifying a removal region of the observed signal corresponding to each component of the unwanted target signal;
supplanting each component of the observed signal corresponding to each respective removal region with an estimate of a corresponding portion of a desired signal based on the observed signal in a region adjacent the respective removal region to form a corrected signal.

US Pat. No. 10,141,001

SYSTEMS, METHODS, APPARATUS, AND COMPUTER-READABLE MEDIA FOR ADAPTIVE FORMANT SHARPENING IN LINEAR PREDICTION CODING

QUALCOMM Incorporated, S...

1. An apparatus comprising:an audio coder input configured to receive an audio signal;
a first calculator configured to determine a long-term noise estimate of the audio signal;
a second calculator configured to determine a formant-sharpening factor based on the determined long-term noise estimate;
a filter configured to filter a codebook vector based on the determined formant-sharpening factor to generate a filtered codebook vector, wherein the codebook vector is based on information from the audio signal; and
an audio coder configured to:
generate a formant-sharpened low-band excitation signal based on the filtered codebook vector; and
generate a synthesized audio signal based on the formant-sharpened low-band excitation signal.

US Pat. No. 10,140,997

DECODER AND METHOD FOR DECODING AN AUDIO SIGNAL, ENCODER AND METHOD FOR ENCODING AN AUDIO SIGNAL

Fraunhofer-Gesellschaft z...

1. A decoder for decoding an audio signal, the decoder comprising:a first target spectrum generator for generating a first target spectrum for a first time frame of a subband signal of the audio signal using first correction data;
a first phase corrector for correcting, with a first phase correction algorithm, a phase of the subband signal in the first time frame of the audio signal wherein the correction is performed by reducing, for the first time frame, a difference between a measure of the subband signal in the first time frame of the audio signal and the first target spectrum;
an audio subband signal calculator for calculating the audio subband signal for the first time frame using a corrected phase determined by the first phase corrector for the first time frame;
a second target spectrum generator, wherein the second target spectrum generator is configured for generating a second target spectrum for the second time frame of the subband of the audio signal using second correction data;
a second phase corrector for correcting, with a second phase correction algorithm, a phase of the subband signal in the second time frame of the audio signal, wherein the correction is performed by reducing, for the second time frame, a difference between a measure of the subband signal in the second time frame of the audio signal and the second target spectrum,
wherein the second phase correction algorithm is different from the first phase correction algorithm, and
wherein the audio subband signal calculator is configured for calculating the audio subband signal for the second time frame using a corrected phase determined by the second phase corrector for the second time frame.

US Pat. No. 10,140,996

SIGNALING LAYERS FOR SCALABLE CODING OF HIGHER ORDER AMBISONIC AUDIO DATA

QUALCOMM Incorporated, S...

1. A device configured to decode a bitstream representative of a higher order ambisonic audio signal, the device comprising:a memory configured to store the bitstream; and
one or more processors configured to:
obtain, from the bitstream, an indication of a number of layers specified in the bitstream;
obtain, from the bitstream, an indication of a number of channels specified in the bitstream; and
obtain the layers of the bitstream based on the indication of the number of layers specified in the bitstream and the indication of the number of channels specified in the bitstream.

US Pat. No. 10,140,995

DECODING DEVICE, DECODING METHOD, ENCODING DEVICE, ENCODING METHOD, AND PROGRAM

Sony Corporation, Tokyo ...

1. A decoding device comprising:a decoding unit that decodes audio data included in an encoded bit stream;
a read unit that reads information indicating whether extended information is present in the encoded bit stream from the encoded bit stream and reads the extended information on the basis of the read information; and
a processing unit that processes the decoded audio data on the basis of the extended information,
wherein the extended information includes first information for specifying a downmix coefficient, and further includes second information,
the processing unit downmixes the decoded audio data of a plurality of channels on the basis of the downmix coefficient to provide downmixed audio data, and
the processing unit further downmixes the downmixed audio data on the basis of the second information.

US Pat. No. 10,140,993

APPARATUS AND METHOD FOR GENERATING AN ERROR CONCEALMENT SIGNAL USING INDIVIDUAL REPLACEMENT LPC REPRESENTATIONS FOR INDIVIDUAL CODEBOOK INFORMATION

Fraunhofer-Gesellschaft z...

1. An apparatus for generating an error concealment audio signal, comprising:an LPC (linear prediction coding) representation generator for generating a first replacement LPC representation and a different second replacement LPC representation;
an LPC synthesizer for filtering a first codebook information using the first replacement LPC representation to acquire a first replacement audio signal and for filtering a different second codebook information using the second replacement LPC representation to acquire a second replacement audio signal; and
a replacement signal combiner for combining the first replacement audio signal and the second replacement audio signal by summing-up the first replacement audio signal and the second replacement audio signal to acquire the error concealment audio signal,
wherein at least one of the LPC representation generator, the LPC synthesizer, and the replacement signal combiner is implemented, at least in part, by one or more hardware elements of the apparatus.

US Pat. No. 10,140,992

SYSTEM AND METHOD FOR VOICE AUTHENTICATION OVER A COMPUTER NETWORK

NUANCE COMMUNICATIONS, IN...

1. A method comprising:receiving, on a mobile device, a speech sample from a user as part of a request for a restricted-access resource separate from the mobile device; and
when the user has previously established identity with the mobile device:
transmitting the speech sample along with the request to an authentication server which compares the speech sample to a previously established speech profile associated with the user; and
providing access to the restricted-access resource if the speech sample from the user matches the previously established speech profile with a minimum certainty threshold.

US Pat. No. 10,140,990

DISPLAY APPARATUS CAPABLE OF RELEASING A VOICE INPUT MODE BY SENSING A SPEECH FINISH AND VOICE CONTROL METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A display apparatus that performs a search based on a voice of a user in a voice input mode and exits the voice input mode according to a result of the search, the display apparatus comprising:a display;
a voice receiver configured to receive a voice signal in the voice input mode;
a communicator configured to communicate with a server; and
a processor configured to:
based on the voice signal being received by the voice receiver within a standby time period, convert the voice signal into text by using a voice recognition program, transmit the text to the server through the communicator, receive one or more search results relating to the voice signal from the server through the communicator, the one or more search results being obtained by the server based on the text,
based on a single search result being received from the server through the communicator, control the display to display the single search result relating to the voice signal and exit the voice input mode, and
based on a plurality of search results being received from the server through the communicator, control the display to display a list including the search results relating to the voice signal, reset the standby time period, maintain the voice input mode for the reset standby time period and await input of a subsequent voice signal for the reset standby time period in the voice input mode,
wherein the processor is further configured to:
based on receiving the subsequent voice signal to select one of the search results included in the list within the reset standby time period, receive an additional search result relating to the selected search result from the server through the communicator, and
based on a single additional search result being received from the server through the communicator within the reset standby time period, control the display to display the single additional search result and exit the voice input mode without awaiting lapse of the reset standby time period.

US Pat. No. 10,140,989

METHOD AND SYSTEM FOR SPEECH RECOGNITION PROCESSING

Alibaba Group Holding Lim...

1. A speech recognition system, comprising:an instant messaging server (IMS) configured to:
assign a unique identifier to speech information received from a sending end to serve as a speech ID;
send the speech information to a receiving end; and
in response to a determination that a speech recognition request issued from a user of the receiving end corresponding to the speech information is received:
extract the speech ID corresponding to the speech information from the speech recognition request;
look up the speech information; and
deliver a speech recognition command in the speech recognition request and the looked-up speech information to one of a speech recognition module, a speech recognition server, or a speech recognition server cluster;
the one of the speech recognition module, the speech recognition server, or the speech recognition server cluster configured to:
perform speech recognition based on the speech information and the speech recognition command; and
convert the speech information to obtain text information corresponding to the speech information, wherein the IMS obtains the text information from the one of the speech recognition module, the speech recognition server, or the speech recognition server cluster; and
a sending module configured to send the obtained text information back as a speech recognition result to the receiving end, wherein the speech recognition module is set up in the one of the IMS, the speech recognition server, or the speech recognition server cluster, wherein the IMS is further configured to:
store the obtained text information in a cache in correspondence with the speech ID; and
in response to a determination that another speech recognition request for the same speech information is received:
extract a speech ID from the other speech recognition request; and
locate the text information corresponding to the speech ID from the other speech recognition request.

US Pat. No. 10,140,988

SPEECH RECOGNITION

Microsoft Technology Lice...

1. A computer system comprising:an input configured to receive voice input from a user, the voice input having speech intervals separated by non-speech intervals;
a system configured to identify individual words in the voice input during the speech intervals of the voice input, and store the identified individual words in memory;
a speech overload detection module configured to detect a speech overload condition at a time during a speech interval of the voice input, the speech overload condition being based on one or more of a rate at which words are identified during the speech interval, or a state of an artificial intelligence (AI) tree being driven by the voice input; and
a notification module configured to output, in response to the speech overload detection module detecting the speech overload condition, a notification of the speech overload condition.

US Pat. No. 10,140,987

AERIAL DRONE COMPANION DEVICE AND A METHOD OF OPERATING AN AERIAL DRONE COMPANION DEVICE

INTERNATIONAL BUSINESS MA...

1. A method of operating an aerial drone companion device, comprising:detecting a first voice command spoken by a first user by at least one microphone disposed on the aerial drone companion device;
autonomously orientating the aerial drone companion device such that an image capture device disposed on the aerial drone companion device faces the first user in response to detecting the first voice command;
detecting a second voice command spoken by the first user by the at least one microphone while the image capture device faces the first user and while the first user looks at the image capture device;
transmitting the second voice command from the aerial drone companion device to a computer located remotely from the aerial drone companion device;
receiving a task signal indicating a task to be performed, wherein the task signal is generated by the computer based on the second voice command, and the task signal is transmitted by the computer and received by the aerial drone companion device; and
autonomously executing the task by the aerial drone companion device.

US Pat. No. 10,140,984

METHOD AND APPARATUS FOR PROCESSING VOICE DATA

Baidu Online Network Tech...

1. A method for processing voice data, comprising:receiving voice data sent by a user terminal;
extracting a voiceprint characteristic vector in the voice data;
matching the voiceprint characteristic vector with a registered voiceprint vector prestored by the user, and generating a matching degree between the voiceprint characteristic vector and the registered voiceprint vector;
determining whether the matching degree is greater than or equal to a preset update threshold; and
updating the registered voiceprint vector by using the voiceprint characteristic vector and the voice data in response to determining that the matching degree is greater than or equal to the preset update threshold
the updating the registered voiceprint vector by using the voiceprint characteristic vector and the voice data comprising:
acquiring an amount of registered voice data inputted by the user and each of voiceprint characteristic vectors prestored by the user; and
updating the registered voiceprint vector according to the each of voiceprint characteristic vectors prestored by the user, an amount of voice data prestored by the user, an amount of the registered voice data and the registered voiceprint vector,
the updating the registered voiceprint vector according to the each of voiceprint characteristic vectors prestored by the user, the amount of voice data prestored by the user, the amount of the registered voice data and the registered voiceprint vector comprising:
carrying out a data standardization operation on the each of voiceprint characteristic vectors prestored by the user, and carrying out a summing operation on the vector subject to the data standardization operation to obtain the sum of the voiceprint characteristic vectors prestored by the user;
multiplying the amount of the registered voice data by the registered voiceprint vector to obtain a product of the registered voiceprint vector; and
calculating a vector sum of the sum of the voiceprint characteristic vectors and the product of the registered voiceprint vector, calculating an amount sum of the amount of the voice data prestored by the user and the amount of the registered voice data, and dividing the amount sum by the vector sum to obtain the updated registered voiceprint vector.

US Pat. No. 10,140,983

BUILDING OF N-GRAM LANGUAGE MODEL FOR AUTOMATIC SPEECH RECOGNITION (ASR)

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method for building an n-gram language model for an automatic speech recognition, comprising:reading training text data and additional text data for the n-gram language model from storage, wherein the additional text data comprises a plurality of sentences having at least one target keyword;
building the n-gram language model by a smoothing algorithm having discount parameters for n-gram counts, wherein each discount parameter for each target keyword is tuned using development data which are different from the additional text data so that a predetermined balance between precision and recall is achieved;
decreasing erroneous detection of one or more target keywords by tuning all of the discount parameters to be larger, or increasing n-gram counts of each of a plurality of words erroneously detected as one of the one or more target keywords by tuning each of the discount parameters to be smaller; and
performing spoken term detection based on the n-gram language model built using the development data.

US Pat. No. 10,140,976

DISCRIMINATIVE TRAINING OF AUTOMATIC SPEECH RECOGNITION MODELS WITH NATURAL LANGUAGE PROCESSING DICTIONARY FOR SPOKEN LANGUAGE PROCESSING

INTERNATIONAL BUSINESS MA...

1. A method for language processing, comprising:training one or more automatic speech recognition models using an automatic speech recognition dictionary and speech recognition training data;
determining a set of N automatic speech recognition hypotheses that characterize a spoken input, based on the one or more automatic speech recognition models, using a processor;
selecting a hypothesis from the set of N automatic speech recognition hypotheses using a discriminative language model and a first natural language processing dictionary that excludes words having little discriminatory value according to an error rate of only words other than words having little likely effect on the natural language outcome in each hypothesis; and
performing natural language processing on the selected hypothesis using a second natural language processing dictionary that is different from the automatic speech recognition dictionary and the first natural language processing dictionary.

US Pat. No. 10,140,974

METHOD AND APPARATUS FOR SPEECH RECOGNITION

Samsung Electronics Co., ...

1. A speech recognition method, comprising:generating, by a processor, a word sequence based on a phoneme sequence generated from a speech signal;
generating, by the processor, a syllable sequence based on the phoneme sequence, in response to a word element among words included in the word sequence having a lower recognition rate than a threshold value; and
determining, by the processor, a text corresponding to a recognition result of the speech signal based on the word sequence and the syllable sequence,
wherein the syllable sequence corresponds to the word element,
wherein the generating of the syllable sequence comprises generating the syllable sequence by decoding a portion corresponding to the word element, among phonemes included in the phoneme sequence, and
wherein the word sequence is generated by decoding the phoneme sequence and corresponds to at least the text corresponding to the recognition result of the speech signal.

US Pat. No. 10,140,973

TEXT-TO-SPEECH PROCESSING USING PREVIOUSLY SPEECH PROCESSED DATA

Amazon Technologies, Inc....

18. A system, comprising:at least one processor; and
at least one memory including instructions that, when executed by the at least one processor, cause the system to:
receive input audio data corresponding to at least one utterance associated with user profile data;
perform automatic speech recognition processing on the input audio data to create first text data;
associate the first text data with the user profile data and at least a portion of the input audio data;
receive second text data representing at least a first word;
determine the second text data is associated with the user profile data;
determine the first word does not correspond to the first text data;
perform natural language understanding processing on the second text data;
determine a second word having a similar meaning as the first word;
determine the second word corresponds to the first text data;
send, to a first device, first data representing the second word;
receive, from the first device, an indication representing the second word is to be used;
generate output audio data using the second word; and
send the output audio data to a second device.

US Pat. No. 10,140,972

TEXT TO SPEECH PROCESSING SYSTEM AND METHOD, AND AN ACOUSTIC MODEL TRAINING SYSTEM AND METHOD

Kabushiki Kaisha Toshiba,...

3. A text to speech method, the method comprising:receiving input text;
dividing said inputted text into a sequence of acoustic units;
converting said sequence of acoustic units to a sequence of speech vectors using an acoustic model, wherein said acoustic model comprises a set of speaker parameters and a set of speaker clusters relating to speaker voice and a set of expression parameters and a set of expression clusters relating to expression, and wherein the sets of speaker and expression parameters and the sets of speaker and expression clusters do not overlap; and
outputting said sequence of speech vectors as audio,
the method further comprising determining at least some of said parameters relating to expression by:
extracting expressive features from said input text to form an expressive linguistic feature vector constructed in a first space; and
mapping said expressive linguistic feature vector to an expressive synthesis feature vector which is constructed in a second space,
wherein said text to speech method includes training said acoustic model using a method comprising:
receiving speech data, said speech data further comprising speech data from one or more speakers speaking with neutral speech,
said speech data comprising data corresponding to different values of a first speech factor, wherein the first speech factor is speaker and speech data corresponding to different values of a second speech factor, wherein the second speech factor is expression,
and wherein said speech data is unlabeled, such that for a given item of speech data, the value of said first speech factor is unknown;
clustering said speech data according to the value of said first speech factor into a first set of clusters and clustering said speech data according to the value of said second speech factor into a second set of clusters; and
estimating a first set and a second set of parameters to enable the acoustic model to accommodate speech for the different values of the first speech factor and the second speech factor respectively,
wherein said clustering and the parameter estimation are jointly performed according to a common maximum likelihood criterion which is common to both parameter estimation and said clustering.

US Pat. No. 10,140,970

ENGINE SOUND PRODUCTION SYSTEMS AND METHODS

GM GLOBAL TECHNOLOGY OPER...

1. An audio system of a vehicle, comprising:a detection module configured to detect an occurrence of a sound when a pressure measured by an exhaust pressure sensor in an exhaust system is greater than a predetermined pressure;
a sound control module configured to, in response to the detection of the sound, increase a magnitude of a predetermined sound to be output within a passenger cabin of the vehicle; and
an audio driver module configured to apply power to a speaker of the passenger cabin of the vehicle based on the predetermined sound.

US Pat. No. 10,140,968

ACOUSTIC ABSORPTION AND METHODS OF MANUFACTURE

Ashmere Holdings Pty Ltd,...

1. A method of providing a micro-perforated panel absorber comprising:providing a primary cellular core having a number of primary cells;
providing secondary cells in a number of recesses, the secondary cells being of reduced depth in comparison to the primary cells; the primary cells providing for absorption of relatively low frequencies; and the secondary cells of reduced depth providing for absorption of relatively high frequencies; and
crushing one or more portions of the primary cellular core to provide the number of recesses, wherein the crushing of the primary cellular core and providing the secondary cells is performed using a secondary reduced depth cellular core having a higher compression strength than the primary cellular core that is crushed.

US Pat. No. 10,140,966

LOCATION-AWARE MUSICAL INSTRUMENT

1. A method comprising:receiving, from each of a plurality of moveable nodes, the position of the moveable node within a coordinate space, wherein the moveable nodes comprise objects that can be physically moved by a person;
generating a graph of the moveable nodes based on the received positions;
generating an audio-visual composition based on a sweep of the graph over time; and
outputting the audio-visual composition.