US Pat. No. 10,770,172

APPARATUS AND METHOD FOR HEALTH MANAGEMENT

SAMSUNG ELECTRONICS CO., ...

1. An apparatus for health management comprising:an information collector configured to collect body composition information and characteristic information of a user; and
a processor configured to determine a degree of muscle loss of the user and a risk in a future health condition of the user based on the body composition information and the characteristic information of the user and provide a personalized health management program to the user based on the determined degree of muscle loss and the risk in the future health condition,
wherein the risk in the future health condition comprises a risk of developing, if no further action is taken by the user, one of pre-sarcopenia, sarcopenia, severe sarcopenia, and sarcopenic obesity by analyzing the body composition information and the characteristic information,
wherein the apparatus further comprises a display configured to:
display, on a first section of a display area, a graph indicating a history of changes in the degree of muscle loss over time of the user, the history of changes including a current muscle mass of the user,
in response to receiving a user selection of a portion of the graph, display, on the graph, an identification mark indicating the selected portion of the graph, the selected portion indicating information of a change in the degree of muscle loss at a specific time point, and display, on a second section of the display area, detailed information comprising one or more items of information associated with the change in the degree of muscle loss at the specific time point, and
in response to receiving a user operation of horizontally moving a position of the identification mark on the graph, display on the second section of the display area, concurrently with the graph in the first section of the display area, detailed information comprising one or more items of information associated with a change in the degree of muscle loss at another time point corresponding to the position to which the identification mark is moved, and
wherein the one or more items of information comprise at least one of the body composition information, the characteristic information, the degree of muscle loss, the risk in the future health condition, the personalized health management program, and an evaluation of the personalized health management program.

US Pat. No. 10,770,170

SIGNAL ENCODING AND DECODING IN MULTIPLEXED BIOCHEMICAL ASSAYS

California Institute of T...

1. A method of unambiguously detecting any unique combination of presence or absence of at least five polynucleotide analytes in a plurality of droplets, the method comprising:(a) providing a sample comprising, or potentially comprising, at least one of said at least five polynucleotide analytes;
(b) forming a mixture of said sample and at least five hybridization probes, wherein each of said at least five hybridization probes further comprises at least one fluorophore and at most four fluorophores;
(c) partitioning said mixture into said plurality of droplets;
(d) exciting said at least one fluorophore to generate one or more signals if one or more of said at least five polynucleotide analytes is present in said plurality of droplets, wherein said one or more signals comprise at least one signal generated by excitement of said at least one fluorophore;
(e) measuring said one or more signals to generate a cumulative intensity measurement, wherein said cumulative intensity measurement corresponds to the presence of a unique combination of presence or absence of said at least five polynucleotide analytes in said sample; and
(f) determining whether each of said least five polynucleotide analytes is present, in any unique combination of presence or absence, based on said cumulative intensity measurement,
wherein the method does not require any step of immobilization of said at least five polynucleotide analytes or mass spectrometry.

US Pat. No. 10,770,168

MEMORY SUB-SYSTEM WITH BACKGROUND SCAN AND HISTOGRAM STATISTICS

Micron Technology, Inc., ...

1. A system, comprising:a memory component comprising a plurality of memory regions configured to store a plurality of codewords; and
a processing device operably connected to the memory component, wherein the processing device is configured to
generate a bit error count (BEC) of a first codeword of the plurality of codewords saved to a first memory region in the plurality of memory regions; and
store statistical information corresponding to the BEC of the first codeword in a BEC histogram corresponding to the plurality of codewords, wherein storing the statistical information comprises incrementing a counter value of a bin of the BEC histogram corresponding to the BEC of the first codeword.

US Pat. No. 10,770,167

MEMORY STORAGE APPARATUS AND FORMING METHOD OF RESISTIVE MEMORY DEVICE THEREOF

Winbond Electronics Corp....

1. A memory storage apparatus, comprising:a memory cell array, comprising:
a main memory cell block, comprising a plurality of resistive memory devices arranged in an array; and
a redundant memory cell block, comprising a plurality of redundant resistive memory devices arranged in an array; and
a memory control circuit, coupled to the memory cell array, applying a test forming voltage to at least one redundant resistive memory device, reading a corresponding test current, and determining a forming voltage applied to the main memory cell block according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.

US Pat. No. 10,770,166

MEMORY DEVICE AND OPERATING METHOD TO DETERMINE A DEFECTIVE MEMORY BLOCK

SK hynix Inc., Icheon-si...

1. A memory device, comprising:one or more memory blocks;
one or more peripheral circuits configured to perform an erase operation and a threshold voltage distribution scan operation on a selected memory block; and
a control logic configured to control the one or more peripheral circuits, and determine the selected memory block to be a normal memory block or a defective memory block based on a result of the threshold voltage distribution scan operation,
wherein the control logic is configured to control the one or more peripheral circuits to perform the threshold voltage distribution scan operation after the erase operation on the selected memory block is completed, and
wherein the one or more peripheral circuits are configured to scan threshold voltage distributions of select transistors included in the selected memory block during the threshold voltage distribution scan operation, and detect whether scanned threshold voltage distributions fall within a normal range, or a left tail area or a right tail area falling out of the normal range.

US Pat. No. 10,770,165

NO-VERIFY PROGRAMMING FOLLOWED BY SHORT CIRCUIT TEST IN MEMORY DEVICE

SanDisk Technologies LLC,...

1. An apparatus, comprising:a set of word lines;
a plurality of memory cells, the memory cells are connected to the word lines;
a control circuit connected to the memory cells; and
a volatile storage connected to the control circuit, the volatile storage configured to store successive units of write data, one unit at a time, including a unit of write data for a first group of memory cells of the plurality of memory cells, the first group of memory cells is connected to one or more word lines of the set of word lines; and
the control circuit is configured to program the first group of memory cells using the unit of write data without performing a verify test, subsequently test the one or more word lines for a short circuit, and decide whether to replace the unit of write data for the first group of memory cells with a unit of write data for a next group of memory cells based on a result of the test.

US Pat. No. 10,770,164

SOFT POST PACKAGE REPAIR FUNCTION VALIDATION

INTERNATIONAL BUSINESS MA...

1. A method comprising:performing a validation of a soft post package repair (sPPR) function of a memory device, the validation comprising:
writing a first pattern to a first target row of a bank group of the memory device;
executing the sPPR function on the first target row to change a mapping of the first target row to a spare row of the memory device and divert a subsequent memory access request targeting the first target row to the spare row;
reading the first target row to confirm that data read from a memory row mapped to the first target row is a mismatch to the first pattern;
writing a second pattern to the first target row;
executing the sPPR function on a second target row of the bank group to change a mapping of the second target row to the spare row and restore the mapping of the first target row;
reading the first target row to confirm the first pattern and restoration of the mapping of the first target row from the spare row; and
reading the second target row to confirm the second pattern and remapping of the second target row to the spare row; and
reporting a result of the validation.

US Pat. No. 10,770,161

SENSE AMPLIFIER

MEDIATEK INC., Hsin-Chu ...

1. A sense amplifier, for reading a via Read-Only Memory (Via-ROM), comprising:a read circuit connected to the via-ROM;
an adaptive keeper circuit connected to the read circuit;
a leakage monitor circuit connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened;
wherein the current mirror is formed by a part of the leakage monitor circuit and a part of the adaptive keeper circuit; and
another part of the leakage monitor circuit and the read circuit are substantially the same.

US Pat. No. 10,770,160

PROGRAMMABLE RESISTIVE MEMORY FORMED BY BIT SLICES FROM A STANDARD CELL LIBRARY

Attopsemi Technology Co.,...

1. A Programmable Resistive Device (PRD) memory integrated in an integrated circuit, the PRD memory comprising:a plurality of PRD cells; and
at least one of the plurality of PRD cells including at least:
a PRD element,
a program selector,
the PRD element is coupled to a first supply voltage line and to the program selector, which is further coupled to a second supply voltage and/or one enable signal, and
the PRD cell has at least one latch built-in as a sense amplifier,
wherein the PRD cell is built from one or more basic cells in a standard cell library and follows standard cell design and layout guidelines associated with the standard cell library,
wherein the PRD cell has an interface unit coupled to the other PRD cells,
wherein the PRD memory is built with replica of the PRD cell with at least one peripheral cell and
wherein the PRD element can be configured to be programmable by applying voltages to the first supply voltage line, the second supply voltage line and/or the enable signal to change resistance of the PRD element into a different logic state.

US Pat. No. 10,770,159

ANTIFUSE DEVICE AND METHOD OF OPERATING THE SAME

UNITED MICROELECTRONICS C...

1. An antifuse device, comprising:a substrate having a plurality of active regions;
a plurality of word lines formed in the substrate and extending along a first direction, each of the active regions being cut by two adjacent word lines and divided into a first doped region and two second doped regions;
a plurality of bit lines formed on the substrate and extending along a second direction, the first doped region of each of the active regions being connected to one of the bit lines through a bit line contact structure disposed on the first doped region;
a plurality of source lines formed on the substrate and extending along the second direction, the second doped regions of the active regions being respectively connected to one of the source lines through a source line contact structure disposed on each of the second doped regions; and
a plurality of capacitors arranged along the second direction and respectively sandwiched between the source line contact structure and one of the source lines.

US Pat. No. 10,770,158

DETECTING A FAULTY MEMORY BLOCK

Western Digital Technolog...

1. A storage system, configured to detect a faulty block in a memory array during operation of the storage system, comprising:the memory array; and
a controller coupled to the memory array, wherein the controller is configured to:
perform a read operation on a memory block of the memory array, the read operation generating a failed bit count;
determine the failed bit count is above a value associated with an overall failed bit count;
determine the failed bit count is above a threshold value, the threshold value based on an initial failed bit count; and
in response to the failed bit count being above the threshold value;
perform a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, and the confirmation process resulting is in erase pass or erase fail; and
mark the memory block for garbage collection in response to determining the confirmation process results in erase fail.

US Pat. No. 10,770,157

METHOD OF REDUCING INJECTION TYPE OF PROGRAM DISTURB DURING PROGRAM PRE-CHARGE IN MEMORY DEVICE

SanDisk Technologies LLC,...

1. An apparatus, comprising:a set of memory cells arranged in NAND strings in a block, each NAND string comprising a channel extending from a source end to a drain end of the NAND string;
a respective bit line connected to the drain end of each NAND string;
a plurality of word lines connected to the set of memory cells and comprising a selected word line, drain-side word lines of the selected word line and source-side word lines of the selected word line, the source-side word lines are programmed, the drain side word lines are unprogrammed; and
a control circuit connected to the bit line and the word lines, the control circuit is configured to, in a program loop of a program operation:
perform a pre-charge phase in which a positive voltage is applied to the bit lines while a voltage applied to the selected word line and a voltage applied to the drain-side word lines allow the positive voltage to charge a region of the channel adjacent to the selected word line and the drain-side word lines, where the voltage applied to the selected word line is adjusted based on a risk factor for an injection type of program disturb on the selected word line; and
after the pre-charge phase, apply a program voltage to the selected word line.

US Pat. No. 10,770,156

MEMORY DEVICES AND METHODS FOR READ DISTURB MITIGATION INVOLVING WORD LINE SCANS TO DETECT LOCALIZED READ DISTURB EFFECTS AND TO DETERMINE ERROR COUNT IN TRACKED SUB SETS OF MEMORY ADDRESSES

Micron Technology, Inc., ...

1. A memory device, comprising:a main memory comprising a plurality of memory addresses, each memory address corresponding to a single one of a plurality of word lines and being included in a tracked subset of the plurality of memory addresses, each tracked subset including memory addresses corresponding to more than one of the plurality of word lines; and
a controller operably connected to the main memory and configured to:
track, for each tracked subset, a number of read operations,
scan, in response to the number of read operations for a first tracked subset exceeding a threshold value as scaled by a first threshold scaling factor corresponding to the first tracked subset, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset, and
update the first threshold scaling factor by an amount corresponding to the determined error count.

US Pat. No. 10,770,155

DETERMINING A READ APPARENT VOLTAGE INFECTOR PAGE AND INFECTED PAGE

International Business Ma...

1. A method for determining a read apparent voltage infector and infected page comprising:initially programming each page of each block within a plane such that each transistor within the plane stores a same binary value;
reading one or more pages within each block within the plane to force, for each transistor within the plane, an apparent threshold voltage to equal an actual threshold voltage;
setting an acting infector page within an acting infector block within the plane;
setting a possible infected page within a possible infected block that is different from the acting infector block within the plane;
reading the acting infector page a predetermined plurality of instances;
subsequently reading the possible infected page;
determining a raw bit error rate (RBER) of the read of the possible infected page versus the same binary value initially programmed to the possible infected page; and
setting the acting infector page as an actual infector page and setting the possible infected page as an actual infected page if the determined RBER is above a predetermined RBER threshold.

US Pat. No. 10,770,154

SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS HAVING THE SAME

Samsung Electronics Co., ...

1. A semiconductor memory device comprising:a power-up signal generator configured to generate a power-up signal in response to a memory voltage reaching a target voltage level;
an initializer configured to generate an initialization signal in response to the power-up signal and a reset signal and to generate an initial refresh command in response to completion of an initialization operation;
a memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the memory cell array configured to perform an initial refresh operation on the plurality of memory cells in response to the initial refresh command; and
a command/address generator configured to receive a clock enable signal and a chip selection signal in response to a clock signal and generate a power-down exit command,
wherein the initializer is configured to generate the initial refresh command when the initialization operation is completed at a third time point before a first time point at which the power-down exit command is generated and after a second time point at which the clock signal is applied.

US Pat. No. 10,770,151

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A method for operating a semiconductor memory device including a plurality of memory blocks, the method comprising:receiving a read command for a memory block among the plurality of memory blocks;
referring to a block read count value corresponding to the memory block;
determining whether the block read count value has reached a threshold value; and
performing a read operation on the memory block based on a result of the determining operation,
wherein the performing of the read operation on the memory block when it is determined that the block read count value reaches the threshold value, includes:
performing a threshold voltage increase operation on a select program state of the memory block; and
performing the read operation on the memory block.

US Pat. No. 10,770,150

NON-VOLATILE MEMORY DEVICE AND INITIALIZATION INFORMATION READING METHOD THEREOF

Samsung Electronics Co., ...

1. A non-volatile memory device comprising:a memory cell array configured to store initialization information for the non-volatile memory device in memory cells connected to a plurality of word lines;
a voltage generator configured to receive a source voltage, generate a first read voltage from the source voltage, and generate a second read voltage from the source voltage, wherein the magnitude of the second read voltage exceeds the magnitude of the first read voltage and is less than or equal to the magnitude of the source voltage; and
a control circuit configured to control application of the first read voltage to a selected word line and to control application of the second read voltage to unselected word lines in an initialization information read operation of reading the initialization information, wherein:
the voltage generator generates the second read voltage in response to a voltage control signal provided by the control circuit in the initialization information read operation,
the voltage generator generates a third read voltage from the source voltage in a read operation of reading the non-initialization information, wherein the third read voltage has a magnitude exceeding that of the source voltage, and
the control circuit applies the first read voltage to another selected word line, among the word lines, and applies the third read voltage to other unselected word lines, among the word lines, to thereby read the non-initialization information from other memory cells of the memory cell array.

US Pat. No. 10,770,149

NON-VOLATILE MEMORY DEVICE

Samsung Electronics Co., ...

1. An output driver circuit, comprising:a first pull-up driver having a plurality of P-type transistors;
a second pull-up driver having a plurality of N-type transistors;
a first pull-down driver including a plurality of N-type transistors; and
a second pull-down driver including a plurality of P-type transistors,
wherein:
a first power supply voltage is applied to the first pull-up driver,
a second power supply voltage is applied to the second pull-up driver,
outputs of the first pull-up driver and the second pull-up driver are coupled together for generating a current at a common output node,
the first pull-down driver and the second pull-down driver are each coupled to the common output node, and
the first pull-up driver, the second pull-up driver, the first pull-down driver, and the second pull-down driver are selectively operated based on a frequency of a clock signal input to the data output circuit.

US Pat. No. 10,770,148

NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME

Samsung Electronics Co., ...

1. An operation method executed by a nonvolatile memory device, the method comprising:applying a programming voltage to a selected word line and programming a selected memory cell that is connected to the selected word line;
reading an adjacent memory cell that is connected to an adjacent word line of the selected word line; and
verifying the selected memory cell by adjusting charge sharing between the selected memory cell and a sensing node, which is connected to the selected memory cell through a bit line, based on a result of reading the adjacent memory cell.

US Pat. No. 10,770,147

MEMORY SYSTEM INCLUDING A MEMORY DEVICE THAT CAN DETERMINE OPTIMUM READ VOLTAGE APPLIED TO A WORD LINE

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:a nonvolatile memory including a word line and a plurality of memory cells connected to the word line; and
a controller configured to:
perform a first threshold voltage tracking operation, during which the controller determines an optimum read voltage for the plurality of memory cells connected to the word line based on data read from the plurality of memory cells using multiple read voltages;
calculate an exhaustion degree of the plurality of memory cells connected to the word line based on the number of times of erasing of a block including the plurality of memory cells connected to the word line; and
when the calculated exhaustion degree is less than a predetermined threshold, perform a second threshold voltage tracking operation to cause the nonvolatile memory to determine an optimum read voltage, wherein, during the second threshold voltage tracking operation, the controller transmits to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line, wherein
the nonvolatile memory is configured to, in response to the command, search an optimum read voltage for the plurality of memory cells connected to the word line using multiple read voltages, and to transmit a response including a search result.

US Pat. No. 10,770,146

METHOD AND APPARATUS FOR PUF GENERATOR CHARACTERIZATION

Taiwan Semiconductor Manu...

1. A method for testing a physical unclonable function (PUF) generator, the method comprising:verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array;
determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states;
if the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, wherein the first map comprises at least one stable bit cells and at least one unstable bit cell, wherein the first set of operation conditions comprises a first operating temperature and a first operating voltage applied to the PUF cell array;
generating a second map under a second set of operation conditions using the PUF generator and the masking circuit, wherein the second map comprises at least one stable bit cells and at least one unstable bit cell, wherein the second set of operation conditions comprises a second operating temperature and a second operating voltage applied to the PUF cell array;
determining a second number of second bit cells, wherein the second bit cells are stable in the first map and unstable in the second map using a Built-in Self Test (BIST) engine;
if the second number of second bit cells is determined to be zero, determining a third number of third bit cells using the BIST engine, wherein the third bit cells are stable in the first map and stable in the second map; and
if the third number of third bit cells are greater than a second preconfigured number, the PUF generator is determined as a qualified PUF generator that meets a predefined quality criterion.

US Pat. No. 10,770,145

TWO-PART PROGRAMMING METHODS

Micron Technology, Inc., ...

1. A method of operating a memory, comprising:increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses to control gates of the plurality of memory cells, wherein the first plurality of programming pulses each have a respective voltage level within a first range of voltage levels;
after applying the first plurality of programming pulses to the control gates of the plurality of memory cells, increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses to the control gates of the plurality of memory cells, wherein the second plurality of programming pulses each have a respective voltage level within a second range of voltage levels;
inhibiting the second subset of memory cells from programming for each programming pulse of the first plurality of programming pulses, and enabling the first subset of memory cells for programming for at least one programming pulse of the first plurality of programming pulses; and
inhibiting the first subset of memory cells from programming for each programming pulse of the second plurality of programming pulses, and enabling the second subset of memory cells for programming for at least one programming pulse of the second plurality of programming pulses;
wherein a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

US Pat. No. 10,770,144

NON-VOLATILE MEMORY AND PROGRAM METHOD THEREOF

MACRONIX INTERNATIONAL CO...

1. A program method of a non-volatile memory, comprising:setting one of a plurality of word lines to be a program word line, setting the word lines except the program word line to be a plurality of unselected word lines;
raising a voltage on the program word line from a reference voltage to a first program voltage during a first sub-time period of a program time period;
raising the voltage on the program word line from the first program voltage to a second program voltage during a second sub-time period of the program time period, wherein the second program voltage is greater than the first program voltage; and
raising voltages on at least part of the unselected word lines from the reference voltage to a pass voltage during the second sub-time period,
wherein the first sub-time period is before the second sub-time period.

US Pat. No. 10,770,143

MEMORY SYSTEMS AND MEMORY PROGRAMMING METHODS

Micron Technology, Inc., ...

1. A memory system comprising:a plurality of memory cells individually configured to have a plurality of different memory states;
a plurality of bitlines coupled with the memory cells;
access circuitry coupled with the bitlines and configured to apply a program signal having a first voltage to one of the bitlines which is configured to apply the program signal to one of the memory cells to change the one memory cell from a first of the memory states to a second of the memory states; and
wherein the access circuitry is configured to provide a second voltage to the bitlines which are immediately adjacent to the one bitline during the application of the program signal to the one memory cell, wherein the second voltage is different than the first voltage.

US Pat. No. 10,770,142

MEMORY DEVICE

NATIONAL TSING HUA UNIVER...

1. A memory device, comprising:a memory array, comprising a plurality of resistive memory cells, wherein each of the resistive memory cells comprises:
a data line; and
a bit line coupled to the data line through a column multiplexing decoder;
a control circuit connected to the memory array; and
an auto-switching structure connected to the control circuit and comprising:
a counter receiving a write complete signal from one of the resistive memory cells in one part of the memory array and independently incrementing a counting number for accessing another one of the resistive memory cells in the one part of the memory array in response to the write complete signal without waiting for another counter responsible for further another one of the resistive memory cells in another part of the memory array to receive another write complete signal, wherein the another one of the resistive memory cells is on a column subsequent to the one of the resistive memory cells; and
a local pre-decoder pre-decoding the counting number as an address and transmitting the address to the column multiplexing decoder.

US Pat. No. 10,770,141

SEMICONDUCTOR MEMORY DEVICES INCLUDING A MEMORY ARRAY AND RELATED METHOD INCORPORATING DIFFERENT BIASING SCHEMES

Ovonyx Memory Technology,...

1. A method of operating a semiconductor memory device, the method comprising:accessing at least a quarter of a page of memory cells located between different row address lines and column address lines within a single clock cycle responsive to selectively applying voltages to the row address lines and the column address lines according to a bias scheme, wherein accessing includes applying different voltages to a first row address line and a second row address line of the row address lines to access the at least the quarter of the page within the single clock cycle, the first row address line adjacent at least one accessed memory cell of the at least a quarter of the page, and the second row address line adjacent at least one other accessed memory cell of the at least a quarter of the page.

US Pat. No. 10,770,140

MEMRISTIVE ARRAY WITH PARALLEL RESET CONTROL DEVICES

Hewlett Packard Enterpris...

1. A memristive array comprising:a number of memristive devices, wherein a memristive device is switchable between states and is to store information; and
a parallel reset control device coupled to the number of memristive devices in parallel to regulate a resetting operation for the number of memristive devices by regulating current flow through target memristive devices, wherein the regulating of the resetting operation comprises drawing current away from a target memristive device as the target memristive device approaches a target state of the states between which the memristive device is switchable,
wherein the parallel reset control device comprises multiple sets of fixed value resistors each being coupled in parallel to a respective set of memristive devices and wherein the parallel reset control device comprises a plurality of parallel reset controllers, each parallel reset controller comprising a set of fixed value resistors of the multiple sets of fixed value resistors, each parallel reset controller being coupled in parallel to a set of the number of memristive devices in a row of the memristive array.

US Pat. No. 10,770,139

VARIABLE RESISTANCE MEMORY DEVICE AND OPERATING METHOD THEREOF

KOREA RESEARCH INSTITUTE ...

1. A method for operating a variable resistance memory device, the method comprising:programming multi-bit data in a multi-bit variable resistance memory cell of the variable resistance memory device, the programming being performed in a set operation and a reset operation, wherein the multi-bit variable resistance memory cell is programmed from a first resistance state to a second resistance state in the set operation and the multi-bit variable resistance memory cell is programmed from a third resistance state to a fourth resistance state in the reset operation, wherein a resistance of the first resistance state is higher than a resistance of the second resistance state while a resistance of the third resistance state is lower than a resistance of the fourth resistance state,
wherein the programming includes:
generating sequentially increased program voltage pulses, based on the multi-bit data; and
applying the program voltage pulses to the multi-bit variable resistance memory cell,
wherein a current-voltage curve of the multi-bit variable resistance memory cell in the set operation includes a first region that does not exhibit a distinguishable hysteresis characteristic and a second region that exhibits both a hysteresis characteristic and a self-compliance characteristic, the current-voltage curve in the set operation in the second region being more gradual than the current-voltage curve in the set operation in the first region such that an increasement of a current per an increment of the applied program voltage pulses in the second region is greater than an increasement of a current per an increment of the applied program voltage pulses in the first region,
wherein the program voltage pulses are applied to the multi-bit variable resistance memory cell in the second region of the current-voltage curve of the multi-bit variable resistance memory cell,
wherein the variable resistance memory cell includes a variable resistance element and a first resistor coupled to the variable resistance element,
wherein the self-compliance characteristic is generated by the variable resistance element and the first resistor.

US Pat. No. 10,770,138

METHOD OF OPERATING RESISTIVE MEMORY DEVICE REDUCING READ DISTURBANCE

Samsung Electronics Co., ...

1. A resistive memory device, comprising:a memory cell array including a plurality of resistive memory cells connected to a plurality of word lines in a first direction and a plurality of bit lines in a second direction substantially perpendicular to the first direction, the plurality of word lines including a first word line and a second word line relatively closer to a selection circuit than the first word line, and the plurality of bit lines including a first bit line and a second bit line relatively closer to the selection circuit than the first bit line;
the selection circuit having selection transistors, the selection transistors being turned on in response to a selection signal, the selection signal being applied to gates of the selection transistor;
a write/read circuit configured to perform a write operation or a read operation with respect to a memory cell selected from among the plurality of resistive memory cells, the write/read circuit being connected to a plurality of data lines; and
a control circuit configured to variably control a voltage level of the selection signal,
wherein, when the selection transistors are connected between the plurality of data lines and the plurality of word lines, a first voltage level of the selection signal when the selected memory cell is connected to the first word line is set to be higher than a second voltage level of the selection signal when the selected memory cell is connected the second word line.

US Pat. No. 10,770,137

RESISTIVE MEMORY DEVICE INCLUDING COMPENSATION CIRCUIT

Samsung Electronics Co., ...

1. A memory device, comprising:a memory cell array comprising a plurality of memory cells;
a plurality of bit lines, wherein each of the plurality of bit lines is connected to at least one of the plurality of memory cells, and among the plurality of bit lines, a predetermined voltage is applied to selected bit lines that are connected to selected memory cells;
a compensation circuit comprising a sampling circuit that generates a sampling value by sensing a leakage current that is applied to non-selected memory cells from among the plurality of memory cells, and a holding circuit that compensates for voltages applied to the selected bit lines, based on the sampling value; and
a control logic circuit that outputs a sampling-enable signal that controls enabling of the sampling circuit and a holding-enable signal that controls enabling of the holding circuit.

US Pat. No. 10,770,136

WRITE ASSIST CIRCUIT OF MEMORY DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A device, comprising:a first write assist unit configured to provide a first operational voltage and a second operational voltage to a memory cell; and
a second write assist unit configured to provide a third operational voltage and a fourth operational voltage to the memory cell;
wherein during a write operation, the first write assist unit is further configured to adjust the first operational voltage or the second operational voltage while the third operational voltage and the fourth operational voltage are at a same voltage level, and
the second write assist unit is further configured to adjust the third operational voltage or the fourth operational voltage while the first operational voltage and the second operational voltage are at a same voltage level.

US Pat. No. 10,770,134

SRAM BASED AUTHENTICATION CIRCUIT

Taiwan Semiconductor Manu...

1. A memory device, comprising:a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state;
a physically unclonable function (PUF) generator, comprising:
a first sense amplifier, coupled to the plurality of memory cells, wherein while at least some of the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, located in first and second columns of the memory cell array, respectively, and based on the comparison, provide a first output signal for generating a first PUF signature; and
a pre-charge/pre-discharge (PC/PD) circuit that is coupled to the plurality of memory cells, wherein the PC/PD circuit is configured to pre-charge bit lines of the first and second columns to either a positive supply voltage or to ground based on a data state of the plurality of memory cells before the first and second memory cells are accessed.

US Pat. No. 10,770,132

SRAM WITH BURST MODE ADDRESS COMPARATOR

Qualcomm Incorporated, S...

1. A memory, comprising:a plurality of latches configured to store a previous row address for the memory;
a first plurality of logic gates configured to assert a bit comparison word responsive to a current row address for the memory equaling the previous row address;
a first transistor having a terminal coupled to a burst mode node for a burst mode signal; and
a second plurality of logic gates configured to switch on the first transistor to ground the burst mode node responsive to the assertion of the bit comparison word.

US Pat. No. 10,770,131

SRAM CELL FOR INTERLEAVED WORDLINE SCHEME

Taiwan Semiconductor Manu...

1. A static random access memory (SRAM) cell laid out on a semiconductor substrate according to an SRAM cell layout, the SRAM cell layout comprising:upper and lower cell edges and left and right cell edges corresponding to an outer perimeter of the SRAM cell on the semiconductor substrate;
a first power rail extending in parallel with and lying along the left cell edge or the right cell edge, wherein the first power rail is configured to couple the SRAM cell to a first voltage;
a second power rail extending in parallel with the first power rail and along a midline of the SRAM cell between the left and right cell edges, wherein second power rail is configured to couple the SRAM cell to a second voltage, the second voltage differing from the first voltage;
a gate electrode disposed at a first height over the semiconductor substrate, the gate electrode extending in parallel with the upper and lower cell edges over the SRAM cell and perpendicular to the first and second power rails; and
a first local interconnect line disposed at the first height and extending in parallel with the gate electrode, wherein a first wide or elongated contact extends laterally and continuously from over an upper surface of the gate electrode to over an upper surface of the first local interconnect line to couple the first local interconnect line to the gate electrode.

US Pat. No. 10,770,128

NON VOLATILE MASS STORAGE DEVICE WITH IMPROVED REFRESH ALGORITHM

Intel Corporation, Santa...

1. An apparatus, comprising:a controller to implement a non-volatile memory refresh algorithm, the controller comprising logic circuitry to recognize a set of blocks of the non-volatile memory for refreshing and then refresh only a subset of data stored within the set of blocks, where, invalid data is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

US Pat. No. 10,770,127

APPARATUSES AND METHODS FOR MANAGING ROW ACCESS COUNTS

Micron Technology, Inc., ...

1. An apparatus comprising:memory cells configured to store data;
counter memory cells;
a wordline coupled to each of the memory cells and each of the counter memory cells, wherein the counter memory cells are configured to store a number of accesses to the wordline; and
a refresh address control circuit configured to determine if the wordline is an aggressor wordline based on the number of accesses.

US Pat. No. 10,770,126

PARALLEL ACCESS TECHNIQUES WITHIN MEMORY SECTIONS THROUGH SECTION INDEPENDENCE

Micron Technology, Inc., ...

1. An apparatus, comprising:a bank of memory cells that includes a first memory cell and a second memory cell, the second memory cell independent of the first memory cell;
a controller coupled with the bank of memory cells, the controller operable to cause the apparatus to:
activate the first memory cell;
initiate a precharge operation for the first memory cell after the first memory cell is activated;
identify the second memory cell for activation; and
activate the second memory cell during the precharge operation for the first memory cell, wherein the activation of the second memory cell being during the precharge operation is based at least in part on the second memory cell being independent of the first memory cell.

US Pat. No. 10,770,125

FIXED VOLTAGE SENSING IN A MEMORY DEVICE

Micron Technology, Inc., ...

1. An apparatus comprising:a ferroelectric random access memory (FeRAM) circuit comprising:
a ferroelectric memory cell having a first node coupled to a data line through a first access transistor and a second node coupled to a plate node of the FeRAM circuit; and
a reference capacitance having a first node coupled to a reference line through a second access transistor and a second node coupled to the plate node of the FeRAM circuit; and
first and second precharge transistors coupled in series between the data line and the reference line of the FeRAM circuit, the first precharge transistor having a first node coupled to the data line and a second node coupled to the plate node of the FeRAM circuit, and the second precharge transistor having a first node coupled to the reference line and a second node coupled to the plate node of the FeRAM circuit,
wherein the plate node of the FeRAM: circuit is configured to hold the second nodes of the first and second precharge transistors and the first nodes of the ferroelectric memory cell and the reference capacitor at the same potential throughout sense and write operations of the ferroelectric memory cell.

US Pat. No. 10,770,124

MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACES

Rambus Inc., San Jose, C...

1. A first memory device, comprising:a first set of pins symmetrically arranged on both sides of a first line of symmetry, wherein the first set of pins is suitably arranged for use in a clamshell configuration;
a first command-and-address (CA) interface to receive command and address information, the first CA interface including a first subset of the first set of pins located on a first side of the first line of symmetry; and
a set of data interfaces including a respective second subset of the first set of pins, wherein a variable number of data interfaces of the set of data interfaces are active in accordance with a plurality of selectable operation modes.

US Pat. No. 10,770,123

STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE

Samsung Electronics Co., ...

1. A storage device comprising:a nonvolatile memory device including memory blocks; and
a controller connected with the nonvolatile memory device through data input and output lines and a data strobe line,
wherein the nonvolatile memory device and the controller are configured to perform a first training to align a data strobe signal of the data strobe line and data bits of the data input and output lines,
wherein the data strobe signal includes a first data strobe signal output to the data strobe line from the controller and a second data strobe signal output to the data input and output line from the nonvolatile memory device,
wherein the data bits includes a first data bits output to the data strobe line from the controller and a second data bits output to the data input and output line from the nonvolatile memory device,
wherein the first training comprises,
inputting, by the controller, data through the first data bits through the data input and output lines to the nonvolatile memory device in sync with the first data strobe signal,
reading, by the controller, the second data bits corresponding to the first data bits through the data input and output lines from the nonvolatile memory device in sync with the second data strobe signal, and
adjusting, by the controller, the first data strobe signal based on a result of the reading,
wherein the nonvolatile memory device is further configured to receive a read enable signal from the controller and output the second data strobe signal during the first training, the second data strobe signal being delayed from the read enable signal, and
wherein the read enable signal toggles with a certain period during a first time interval and stop toggling with the certain period during a second time interval.

US Pat. No. 10,770,122

MEMORY INPUT HOLD TIME ADJUSTMENT

TAIWAN SEMICONDUCTOR MANU...

1. A device for providing gated data signals, the device comprising:a delay path configured to receive an input signal and output a data signal indicative of the input signal and delayed from the input signal by a time interval;
a gating signal generator configured to supply a gating signal;
a gating circuit having a data input operatively connected to the delay path, a data output, and a gating input operatively connected to the gating signal generator, the gating circuit being configured to receive the data signal from the delay path at the data input, receive the gating signal at the gating input, and output at the data output an output signal indicative of the received data signal when the gating signal is present at the gating input; and
a delay controller configured to receive a variable delay control signal and set the delay time interval according to the delay control signal, wherein the delay path comprises a delay element powered by a power supply and having a delay time that is dependent at least in part on the power applied to the delay element, and wherein delay controller is configured to vary the power applied to the delay element.

US Pat. No. 10,770,121

MEMORY DEVICE AND MEMORY WRITING METHOD

JIANGSU ADVANCED MEMORY T...

1. A memory device comprising:a memory array, comprising a plurality of memory units respectively arranged in a plurality of bit lines;
a plurality of write drivers configured to generate a plurality of write bit signals respectively input to the bit lines; and
a controller configured to provide a voltage mode control signal and a current mode control signal, wherein the controller is electrically coupled to the write drivers;
wherein, each of the write drivers respectively generates, according to the voltage mode control signal and the current mode control signal, one of the write bit signals corresponding to each of the write drivers;
in response to each of the memory units being in a set state, the controller outputs the voltage mode control signal and the current mode control signal to the write drivers and in response to each of the memory units being in a reset state, the controller outputs the voltage mode control signal to the write drivers.

US Pat. No. 10,770,120

MEMORY SYSTEM AND OPERATING METHOD OF THE SAME

SK hynix Inc., Gyeonggi-...

1. A memory system comprising:a sudden power off (SPO) frequency value calculator suitable for determining a SPO frequency value;
a checkpointing mode controller suitable for setting the memory system to one among a high frequency checkpointing mode and a low frequency checkpointing mode according to the SPO frequency value; and
a processor suitable for performing a checkpointing operation according to the set frequency checkpointing mode.

US Pat. No. 10,770,119

MEMORY CIRCUIT

MACRONIX INTERNATIONAL CO...

1. A memory circuit, having a memory cell array, and comprising:a data receiving stage circuit, configured to receive a serial input signal and a chip enable signal;
a data writing circuit, coupled to the data receiving stage circuit, and configured to generate at least one of a command signal and a data signal according to the serial input signal;
a power supply circuit, configured to generate an operating voltage for the memory cell array to perform a data access operation;
a data output stage circuit, coupled to the memory cell array, and configured to output a readout data; and
a controller, coupled to the data writing circuit and the power supply circuit, and configured to:
perform a switching operation of an operating state of the memory circuit according to a changing state of the chip enable signal; and
determine a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit and the data output stage circuit according to the operating state of the memory circuit.

US Pat. No. 10,770,117

SEMICONDUCTOR STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device, comprising:a source line, a first selection gate line, a plurality of word lines, a first dummy word line, and a second selection gate line stacked one above the other in a first direction;
a first pillar including a first semiconductor layer, the first pillar extending in the first direction through the first selection gate line, the word lines, and the first dummy word line, the first semiconductor layer being electrically connected to the source line;
a plurality of memory cells at intersections of the first pillar and the word lines;
a conductive layer at an end of the first pillar, extending into the first dummy word line, and being an N-type diffusion layer;
a second pillar including a second semiconductor layer, the second pillar extending in the first direction through the second selection gate line, the second semiconductor layer in contact with the conductive layer;
a bit line above the second selection gate line in the first direction and electrically connected to the second semiconductor layer; and
a control circuit configured to apply during an erasing operation of the memory cells:
a first voltage to the source line, the first selection gate line, the second selection gate line, and the bit line,
a second voltage lower than the first voltage to the word lines, and
a third voltage that is between the first voltage and the second voltage to the first dummy word line.

US Pat. No. 10,770,116

MEMORY DEVICE WITH A SIGNALING MECHANISM

Micron Technology, Boise...

1. A memory device, comprising:active circuitry configured to process a segment set that corresponds to a source data, wherein:
the source data comprises information corresponding to a device operation, the source data having a block length representing a number of bits therein, and
the segment set includes at least a first segment and a second segment, the first segment and the second segment each including number of bits less than the block length; and
a set of die pads coupled to the active circuitry and configured to communicate the segment set for operating a second device, wherein the set includes a number of die pads less than the block length.

US Pat. No. 10,770,115

RECORDING MEDIUM, PLAYBACK METHOD, AND PLAYBACK DEVICE

PANASONIC INTELLECTUAL PR...

1. A playback method of reading out and playing streams from a recording medium, in which are recordeda stream file including a first luminance video expressed by luminance of a first dynamic range, and a second luminance video expressed by luminance of a second dynamic range that is broader than the first dynamic range, and
a playlist file for controlling playback of the stream file,
first and second combination information, representing combinations of elementary streams that each can be played at the same time in a same playback section, being described in the playlist file,
elementary streams that can be played at the same time with the first luminance video in this playback section being all listed in the first combination information, and
elementary streams that can be played at the same time with the second luminance video in this playback section being all listed in the second combination information,
wherein all of the elementary streams that can be played at the same time with the first luminance video listed in the first combination information and all of the elementary streams that can be played at the same time with the second luminance video listed in the second combination information are included in the stream files including the first luminance video and the second luminance video,
the playback method comprising:
in a case of playing the first luminance video, reading out any one of the elementary streams listed in the first combination information of the playlist file, and playing at the same time with the first luminance video; and
in a case of playing the second luminance video, reading out any one of the elementary streams listed in the second combination information of the playlist file, and playing at the same time with the second luminance video.

US Pat. No. 10,770,113

METHODS AND SYSTEM FOR CUSTOMIZING IMMERSIVE MEDIA CONTENT

Zeality Inc., Pleasanton...

1. A method for customizing dynamic immersive media content, comprising:at a first computing system having one or more processors, memory, a microphone, and an image sensor:
displaying an immersive media customization user interface;
playing an immersive video in a first region of the user interface, wherein the first region displays a portion of the immersive video according to a user selected visibility window;
while playing the immersive video:
receiving first input from a first user to initiate a recording of the immersive video as displayed in the first region;
in response to initiating the recording, capturing video of the first user by the microphone and the image sensor;
detecting user adjustment of the visibility window and recording information that identifies placement of the visibility window within the immersive video; and
receiving second input from the first user to complete the recording;
using the captured video of the first user and the information that identifies placement of the visibility window to form a customized video comprising (i) what was displayed in the visibility window while playing the immersive video and (ii) a video overlay in a peripheral portion of the customized video showing the captured video of the user;
transmitting the customized video to a second computing system;
displaying the customized video on the second computing system;
receiving input from a second user, at the second computer system, to move away from the visibility window; and
in response to receiving the input from the second user, displaying a frame-shaped portion of video from the immersive video outside of the visibility window in an obfuscated manner, wherein the frame-shaped portion of video is configured to guide the second user to the visibility window.

US Pat. No. 10,770,112

AGGREGATION OF RELATED MEDIA CONTENT

Google LLC, Mountain Vie...

1. A media system, comprising:a memory; and
a processor that executes computer-executable instructions stored in the memory that cause the processor to:
receive first metadata associated with a first video item captured by a first user device and second metadata associated with a second video item captured by a second user device;
determine, based at least on the first metadata and the second metadata, that the first video item and the second video item are associated with each other;
determine a timeline such that a first time in the first video item is synchronized with a second time in the second video item;
aggregate the first video item and the second video item into a composite video item that includes at least a first segment from the first video item and a second segment from the second video item, wherein the first segment and the second segment are arranged in the composite video in synchronization with the determined timeline;
cause the composite video item to be presented on a third user device in which the first video item and the second video item are simultaneously played back based on the synchronization, wherein the composite video item is a mosaic in which the first video item and the second video item are concurrently displayed; and
modify presentation of the composite video item at a third time on the third user device by modifying a visual characteristic with which the first video item is presented within the mosaic based on a user preference indicated by a user of the first user device.

US Pat. No. 10,770,111

DISK DRIVE WITH EFFICIENT HANDLING OF OFF-TRACK EVENTS DURING SEQUENTIAL WRITE

KABUSHIKI KAISHA TOSHIBA,...

1. A method of writing data to a recording surface of a magnetic disk, the method comprising:moving a head to a first track on the recording surface to start a write operation on data including first data and second data that are sequential;
controlling the head to write the first data to a first sector of the first track;
controlling the head to write the second data to a first group of one or more sectors of the first track in a same revolution of the magnetic disk as when the first data was written, wherein the first group of one or more sectors is adjacent to the first sector; and
upon detecting that an off-track event occurred while writing the second data to the first group of one or more sectors, controlling the head to write the second data to a second group of one or more sectors of the first track that is adjacent to the first group of one or more sectors in the same revolution of the magnetic disk as when the first data was written and the second data was written to the first group of one or more sectors.

US Pat. No. 10,770,110

DISK DRIVE WITH EFFICIENT HANDLING OF OFF-TRACK EVENTS DURING SEQUENTIAL WRITE

KABUSHIKI KAISHA TOSHIBA,...

1. A method of accessing a recording surface of a magnetic disk in a disk drive, the method comprising:moving a head to a first track to start a disk access operation;
controlling the head to perform the disk access operation on one or more sectors of the first track beginning at a first sector of the first track;
if there are any sectors in a second track to be written as part of the disk access operation after the head has performed the disk access operation on all sectors of the first track to be written as part of the disk access operation, determining whether or not an off-track event occurred while the head was performing the disk access operation on any of the sectors of the first track; and
upon determining that the off-track event occurred while the head was performing the disk access operation on any of the sectors of the first track to be written as part of the disk access operation, moving the head to the second track and controlling the head to write sequentially to one or more sectors of the second track beginning at a first sector of the second track.

US Pat. No. 10,770,108

DISC STORAGE APPARATUS AND DISC ARCHIVE APPARATUS

SONY SEMICONDUCTOR SOLUTI...

7. A disc archive apparatus, comprising:a disc storage apparatus capable to store N rows of stacked M discs, wherein each of N and M indicates a positive integer equal to or greater than two;
a first storage rack and a second storage rack, wherein
each of the first storage rack and the second storage rack includes including a plurality of storage sections,
each storage section of the plurality of storage sections includes a front opening and a rear opening, and
each storage section of the plurality of storage sections is configured to allow the disc storage apparatus to be mounted or taken out through the front opening and the rear opening;
a conveying robot configured to:
select the disc storage apparatus specified; and
convey the disc storage apparatus through the front opening of each of the first storage rack and the second storage rack;
a disc drive including a plurality of drives configured to record on or reproduce from disc-shaped recording media in the disc storage apparatus conveyed by the conveying robot; and
a disc conveying picker configured to set the discs from the disc storage apparatus into each drive of the plurality of drives of the disc drive, wherein
the disc storage apparatus is capable to store the N rows of the stacked M disc-shaped recording media in a case having an opening on an upper surface of the case,
each of the N and M indicates the positive integer equal to or greater than two, and
based on the disc storage apparatus taken out from the rear opening of one of the plurality of storage sections of the second storage rack, a tray cover is configured to slide from the rear opening and cover the rear opening, wherein the disc storage apparatus is taken out with the rear opening covered by the tray cover.

US Pat. No. 10,770,107

ADAPTIVE TENSION POSITION CHANGING FOR MAGNETIC TAPE RECORDING DEVICE

International Business Ma...

1. A method for handling seek commands for a tape drive, the method comprising:receiving a seek command for moving tape in the tape drive to a target position;
determining, based on a current position of the tape, the target position, a high water mark for the tape, a first speed of moving the tape at a first tension, and a second speed of moving the tape at a second tension, whether to move the tape according to a first procedure or a second procedure, the first procedure including directly moving the tape from the current position to the target position with the tape at the first tension, the second procedure including moving the tape from the current position to the HWM with the tape at the first tension and moving the tape from the HWM to the target position with the tape at the second tension; and
moving the tape according to the determined first or second procedure.

US Pat. No. 10,770,106

SYSTEM AND METHOD USING ON-RAMP HEATING TO DETECT LASER MODE HOPPING IN HEAT ASSISTED RECORDING

Seagate Technology LLC, ...

1. A method, comprising:moving a heat-assisted recording head onto a ramp such that the recording head is thermally isolated from a moving disk;
activating a heating device on the recording head to cause the recording head to obtain a high temperature that is not obtainable when proximate to the moving disk;
moving the recording head over the moving disk such that the recording head reaches an operating temperature that is below the high temperature;
determining one or more temperatures between the high temperature and the operational temperature at which a laser of the recording head experiences mode-hopping, and
using the one or more temperatures by a controller to mitigate mode hops during an operation of the recording head.

US Pat. No. 10,770,105

MAGNETIC TAPE HAVING CHARACTERIZED MAGNETIC LAYER AND MAGNETIC TAPE DEVICE

FUJIFILM Corporation, To...

1. A magnetic tape comprising:a non-magnetic support;
a non-magnetic layer including non-magnetic powder and a binding agent on the non-magnetic support; and
a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic layer,
wherein a total thickness of the non-magnetic layer and the magnetic layer is equal to or smaller than 0.60 ?m,
the magnetic layer has a servo pattern,
the ferromagnetic powder is ferromagnetic hexagonal ferrite powder,
an intensity ratio Int(110)/Int(114) of a peak intensity Int(110) of a diffraction peak of a (110) plane with respect to a peak intensity Int(114) of a diffraction peak of a (114) plane of a hexagonal ferrite crystal structure obtained by an X-ray diffraction analysis of the magnetic layer by using an In-Plane method is 0.5 to 4.0, and
a vertical direction squareness ratio of the magnetic tape is 0.65 to 1.00.

US Pat. No. 10,770,104

ALTERNATIVE DESIGNS FOR MAGNETIC RECORDING ASSISTED BY A SINGLE SPIN HALL EFFECT (SHE) LAYER IN THE WRITE GAP

Headway Technologies, Inc...

1. A Spin Hall Effect (SHE) assisted magnetic recording (SHAMR) device, comprising:(a) a main pole (MP) configured to generate a magnetic (write) field in a MP tip with a front side at an air bearing surface (ABS), and having a local magnetization that is proximate to a MP trailing side and substantially in a direction of a write gap (WG) flux field that is between the MP tip and a trailing shield, and across an adjoining WG;
(b) the trailing shield (TS) with a front side at the ABS, and a local magnetization proximate to a bottom surface that faces the MP, and that is substantially in a direction of the WG flux field; and
(c) a Spin Hall Effect (SHE) layer formed in the WG and having a bottom surface that contacts the MP trailing side and a top surface adjoining the TS bottom surface, and comprised of a Spin Hall Angle (SHA) material, wherein the SHE layer is configured to generate a first transverse spin transfer torque that tilts the local MP magnetization to a direction that is more orthogonal to the ABS thereby enhancing the write field when a first current (I1) is applied between the MP trailing side and the SHE layer, and is configured to generate a second transverse spin transfer torque that tilts the local TS magnetization to a direction that is more orthogonal to the ABS to increase a TS return field when a second current (I2) is applied between the TS and the SHE layer.

US Pat. No. 10,770,103

PERPENDICULAR MAGNETIC RECORDING (PMR) WRITER WITH NARROW HIGH MOMENT TRAILING SHIELD

Headway Technologies, Inc...

1. A perpendicular magnetic recording (PMR) writer, comprising:(a) a main pole with a leading side and a trailing side at an air bearing surface (ABS), and two sides that connect the leading side and trailing side and are formed equidistant from a center plane that is orthogonal to the ABS;
(b) a side shield on each side of the center plane that is separated from one of the MP sides by a side gap, and wherein an inner section of a top surface of each side shield is at a first plane that includes the MP trailing side and a side gap top surface at the ABS;
(c) a trailing shield structure, comprising;
(1) a high moment trailing shield (HMTS) having a saturation (Bs) value from 19 kiloGauss (kG) to 24 kG and a first cross-track width (w), and wherein the HMTS has a bottom surface separated from the MP trailing side by a first portion of a write gap (WG) having a first thickness (t1) and width w;
(2) a first trailing shield (TS) layer having a width w1 where w1 is substantially greater than w, and wherein the first TS layer is formed on a top surface of the HMTS and on a top surface of a second portion of WG where a side of the second WG portion adjoins a side of the first WG portion on each side of the center plane, the second WG portion has a thickness t2 where t2>t1; and
(3) a second TS layer formed on a top surface of the first TS layer, and that contacts an outer section of each side shield top surface at a cross-track distance from ½ w1 from the center plane to a far side of the trailing shield structure, and
(d) the second WG portion that is formed on a top surface of each inner SS section, and has an outer side that is coplanar with a first TS layer side at the cross-track distance of ½ w1 from the center plane.

US Pat. No. 10,770,102

HYBRID SERVO PATTERN CONFIGURATIONS FOR MAGNETIC TAPE

International Business Ma...

1. A tape drive-implemented method, comprising:using information read by one or more servo readers from one or more servo bands on a magnetic tape to position a magnetic tape head relative to the magnetic tape,
wherein an array of data transducers is positioned along the magnetic tape head, the array extending perpendicular to a direction of travel of the magnetic tape,
wherein a group of servo readers is positioned at each end of the array of data transducers,
wherein a distance between each of the immediately adjacent servo readers in each of the groups of servo readers is less than or equal to one third of a prespecified width of each of the servo bands,
wherein the distance between each of the servo readers in each of the groups and the prespecified width are both measured in a direction perpendicular to the direction of travel of the magnetic tape.

US Pat. No. 10,770,101

SYSTEMS AND METHODS FOR WRITING SERVO PATTERNS

International Business Ma...

1. A system, comprising:a magnetic tape having a servo track having physical characteristics of being written by a tape drive that monitors a lateral position of the magnetic tape passing over a servo writing head of the tape drive during a servo track writing operation and writes servo marks to the magnetic tape, a spacing between the servo marks being physically characteristic of variations in a timing of the writing of each servo mark made based on the monitored lateral position of the magnetic tape; and
the tape drive configured to:
monitor, by the tape drive, the lateral position of the magnetic tape passing over the servo writing head during the servo track writing operation, and
write, by the tape drive, servo marks to the magnetic tape, the timing of the writing of each mark being based on the monitored lateral position of the magnetic tape.

US Pat. No. 10,770,100

BALANCED CURRENT MIRRORS FOR BIASING A MAGNETIC RESISTOR IN A HARD DISK DRIVE

Marvell Asia Pte, Ltd., ...

1. A bias circuit comprising:a closed loop gain stage arranged to determine a difference between a first current in a first branch circuit and a second current in a second branch circuit, wherein the first branch circuit and the second branch circuit are coupled to respective terminals of a magnetic resistor (MR); and
a first set of current mirrors and a second set of current mirrors which are balanced, the first set of current mirrors arranged to provide a source current to one of the terminals of the MR and the second set of current mirrors arranged to provide a sink current to another of the terminals of the MR to reduce the difference between the first current and the second current and provide a constant voltage bias to the MR based on a voltage of a voltage source.

US Pat. No. 10,770,099

STRESS-FREE TAPE HEAD MODULE

International Business Ma...

1. A method, comprising:attaching a die to a beam, wherein the die comprises an array of transducers in a transducer region of the die, a first region extending from the transducer region to a first end of the die and a second region extending from the transducer region to a second end of the die,
wherein the transducer region of the die is attached to the beam,
wherein the first region and the second region are not attached to the beam.

US Pat. No. 10,770,098

HEAT-ASSISTED MAGNETIC RECORDING HEAD WITH NEAR-FIELD TRANSDUCER HAVING FIRST AND SECOND SURFACE-PLASMONIC PLATES

Seagate Technology LLC, ...

1. A write head comprising:a waveguide core;
a magnetic pole;
a first surface-plasmonic plate proximate the magnetic pole and recessed from a media-facing surface of the write head, a bottom surface of the first surface-plasmonic plate facing away from the magnetic pole and towards the waveguide core, the first surface-plasmonic plate formed of a first material having lower-loss in plasmonic coupling than a second material, the second material being more mechanically robust than the first material; and
a second surface-plasmonic plate formed of the second material and located on the bottom surface of the first surface-plasmonic plate, a lower edge of the second surface-plasmonic plate extending closer to the media-facing surface than the first surface-plasmonic plate, the second surface-plasmonic plate comprising a peg that extends from the lower edge to the media-facing surface, an upper edge of the second surface-plasmonic plate slanted in a downtrack direction.

US Pat. No. 10,770,097

ELEMENT HEATER WITH BACK PLANE REFLECTORS

SEAGATE TECHNOLOGY LLC, ...

1. A system comprising:a first heater including,
a first electrode,
a first heating element attached to the first electrode,
a first heat sink between the first electrode and the first heating element;
a first mirror between the first heat sink and the first heating element, and
a first aperture reflector surrounding the first mirror and the first heating element;
a second heater including,
a second electrode,
a second heating element attached to the second electrode,
a second heat sink between the second electrode and the second heating element;
a second mirror between the second heat sink and the second heating element, and
a second aperture reflector surrounding the second mirror and the second heating element; and
a carrier configured to move a workpiece in a gap between the first heater and the second heater, wherein
the first aperture reflector is positioned to direct heat from the first heating element onto a first side of the workpiece, and
the second aperture reflector is positioned to direct heat from the second heating element onto a second side of the workpiece.

US Pat. No. 10,770,096

DUAL WRITER WITH BRIDGED CONNECTION

SEAGATE TECHNOLOGY LLC, ...

1. A recording head comprising:a bearing surface;
a first writer;
a first shield structure for the first writer, the first shield structure having a first trailing edge shield with a first top surface;
a second writer;
a second shield structure for the second writer, the second shield structure having a second trailing edge shield with a second top surface that is physically separate from the first top surface; and
a magnetic bridge connecting the first shield structure to the second shield structure at the bearing surface.

US Pat. No. 10,770,095

RECORDING DENSITY SETTING METHOD BASED ON LINEAR RECORDING DENSIT AND TRACK PITCH LIMITING

Kabushiki Kaisha Toshiba,...

1. A recording density setting method, comprising:performing first process of recording and reading data on and from a disk medium of a magnetic disk device, acquiring first information for setting the read data to satisfy a certain quality criterion, the first information representing a first shape of a first plurality of unit regions, each of the a first plurality of unit regions being a recording region of a unit capacity; and
performing second process of acquiring second information representing a second shape of the first plurality of unit regions, and setting a recording density on the basis of the second information, the second shape being formed by adding margin regions having the same area to the first plurality of unit regions of the first shape.

US Pat. No. 10,770,094

ROUTING AUDIO STREAMS BASED ON SEMANTICALLY GENERATED RESULT SETS

Intel IP Corporation, Sa...

1. An apparatus for routing audio streams, comprising:an audio receiver to receive audio from a microphone;
a classifier to semantically generate a result set comprising a confidence score generated for each of a plurality of different spoken language understanding (SLU) engines based on the audio, wherein the classifier is trained directly on domain data associated with the plurality of different SLU engines associated with different devices;
a scheduler to select an SLU engine of the plurality of different SLU engines based on a highest confidence score in the result set; and
a router to stream the audio to the selected SLU engine.

US Pat. No. 10,770,093

SECURELY EXECUTING VOICE ACTIONS USING CONTEXTUAL SIGNALS TO PERFORM AUTHENTICATION

Google LLC, Mountain Vie...

1. A method performed by a data processing apparatus, the method comprising:receiving, from a first computing device, audio data representing a voice command spoken by a speaker;
obtaining, based on the audio data representing the voice command, a speaker identification result indicating that the voice command was spoken by the speaker;
determining, based on the speaker identification result indicating that the voice command was spoken by the speaker, a device identifier that corresponds to a second computing device of the speaker;
selecting a voice action based at least on a transcription of the audio data;
selecting a service provider corresponding to the selected voice action from among a plurality of different service providers that are configured to perform authentication using different types of contextual data;
identifying, based on the selection of the service provider, one or more input data types, separate from speaker identification results based on voice input, that the selected service provider uses to perform authentication for the selected voice action;
obtaining, using the device identifier that corresponds to the second computing device, contextual data from the second computing device that the selected service provider can use to authenticate the speaker without requiring the speaker to provide explicit authentic information, the contextual data comprising a status of the second computing device;
obtaining, from the contextual data and without requiring the speaker to provide explicit authentication information, one or more values that correspond to the identified one or more input data types; and
providing, to the selected service provider:
a request to perform the selected voice action;
the speaker identification result; and
the one or more values that correspond to the identified one or more input data types.

US Pat. No. 10,770,092

VISEME DATA GENERATION

Amazon Technologies, Inc....

1. A system comprising:one or more processors; and
computer-readable media storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
generating, in an uncompressed format, audio data corresponding to a song, the audio data representing frequencies and amplitudes of the song;
analyzing the audio data to determine a number of beats per minute associated with the audio data;
determining, using a Viterbi algorithm and the beats per minute, a portion of the audio data representing human sound;
determining viseme data to associate with the audio data, the viseme data determined from an amplitude of the amplitudes;
generating lip-sync data including the viseme data and the audio data; and
sending the lip-sync data to a first device, the lip-sync data causing the first device to output the audio data and causing a second device to present the viseme data while the audio data is output.

US Pat. No. 10,770,091

BLIND SOURCE SEPARATION USING SIMILARITY MEASURE

GOOGLE LLC, Mountain Vie...

1. A method comprising:receiving time instants of electronic audio signals generated by a set of microphones at a location;
determining a distortion measure between frequency components of at least some of the received electronic audio signals;
determining similarity measures for the frequency components using the determined distortion measure, the similarity measures measuring a similarity of the electronic audio signals at different time instants for respective frequency bins; and
performing blind source separation of the electronic audio signals, the blind source separation including processing the electronic audio signals based on the determined similarity measure, including aggregating the similarity measures over a frequency band corresponding to the frequency bins.

US Pat. No. 10,770,090

METHOD AND DEVICE OF AUDIO SOURCE SEPARATION

Realtek Semiconductor Cor...

1. A method of audio source separation, configured to separate audio sources from a plurality of received signals, the method comprising:applying a demixing matrix on the plurality of received signals to generate a plurality of separated results;
performing a recognition operation on the plurality of separated results to generate a plurality of recognition scores, wherein the plurality of recognition scores are related to matching degrees between the plurality of separated results and a target signal;
generating a constraint according to the plurality of recognition scores, wherein the constraint is a spatial constraint or a mask constraint; and
adjusting the demixing matrix according to the constraint;
wherein the adjusted demixing matrix is applied to the plurality of received signals to generate a plurality of updated separated results from the plurality of received signals;
wherein the method of audio source separation is utilized for speech recognition.

US Pat. No. 10,770,089

SOUND DAMPENING AND PASS THROUGH FILTERING

Caterpillar Inc., Peoria...

1. A sound monitoring system for collecting and processing an environmental noise level surrounding a work machine, the sound monitoring system comprising:an acoustic sensor including a plurality of microphones arranged into an acoustic signal detection array configured to detect and capture the environmental noise level and the acoustic sensor generates an acoustic sensor output signal based on the environmental noise level detected;
a controller communicably coupled to the acoustic sensor, the controller programmed to receive and perform a signal processing on the acoustic sensor output signal to identify a first portion of the acoustic sensor output signal and a second portion of the acoustic sensor output signal, wherein the controller is programmed to generate a controller output signal based on the first portion and the second portion of the acoustic sensor output signal;
a speaker located on the work machine and communicably coupled to the controller, wherein the controller transmits the controller output signal to the speaker and the speaker emits the controller output signal; and
a plurality of acoustic sensors and each acoustic sensor of the plurality of acoustic sensors generates a unique acoustic sensor output signal, wherein the controller receives the unique acoustic sensor output signal from each acoustic sensor of the plurality of acoustic sensors, and wherein the signal processing identifies the first portion of the unique acoustic sensor output signal and the second portion of the unique acoustic sensor output signal from each of the unique acoustic sensor output signals.

US Pat. No. 10,770,088

ADAPTIVE AUDIO DECODER SYSTEM, METHOD AND ARTICLE

IMMERSION NETWORKS, INC.,...

1. An apparatus, comprising:a decoder configured to generate decoded signals based on quantized signals and generating a prediction signal, the decoder including:
a feedback loop including:
an inverse quantizer configured to receive a quantized signal from a variable rate adaptive quantizer; and
a predictor circuit; and
a low-pass filter having a stop band with a bandwidth selected as a function of a sampling rate, wherein the stop band bandwidth is at least 31% of half of the sampling rate
an adder configured to receive an output of the decoder and a modified low-pass filter output;
wherein the low-pass filter and the predictor circuit are coupled and the predictor circuit is configured to provide a predetermined prediction gain for the input signal as a function of the stop band bandwidth of the low-pass filter.

US Pat. No. 10,770,087

SELECTING CODEBOOKS FOR CODING VECTORS DECOMPOSED FROM HIGHER-ORDER AMBISONIC AUDIO SIGNALS

Qualcomm Incorporated, S...

1. A device comprising:a memory configured to store a plurality of codebooks to use when performing vector dequantization with respect to a vector quantized spatial component of a soundfield, the vector quantized spatial component defined in a spherical harmonic domain, and obtained through application of a decomposition to a plurality of higher order ambisonic coefficients representative of the soundfield; and
one or more processors coupled to the memory, and configured to:
select one of the plurality of codebooks;
perform vector dequantization with respect to the vector quantized spatial component using the selected one of the plurality of codebooks to obtain a vector dequantized spatial component of the soundfield; and
render, based on the vector dequantized spatial component, speaker feeds.

US Pat. No. 10,770,086

ZERO-LATENCY PULSE DENSITY MODULATION INTERFACE WITH FORMAT DETECTION

Cirrus Logic, Inc., Aust...

1. A method comprising:receiving a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit;
detecting an invalid state associated with the stream; and
responsive to detecting the invalid state, determining boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.

US Pat. No. 10,770,085

ENCODING METHOD, DECODING METHOD, ENCODING APPARATUS, AND DECODING APPARATUS

HUAWEI TECHNOLOGIES CO., ...

1. An encoding method for encoding a speech signal, comprising:obtaining a low band signal of the speech signal and a high band signal of the speech signal;
encoding the low band signal to obtain a low frequency encoding parameter;
encoding the high band signal to obtain a linear predictive coding (LPC) parameter;
obtaining an excitation signal according to the low frequency encoding parameter;
obtaining a synthesized high band signal according to the excitation signal and the LPC parameter; and
performing filtering processing on the synthesized high band signal, using a pole-zero filter, wherein a coefficient of the pole-zero filter is set based on the LPC parameter.

US Pat. No. 10,770,083

AUDIO PROCESSOR AND METHOD FOR PROCESSING AN AUDIO SIGNAL USING VERTICAL PHASE CORRECTION

Fraunhofer-Gesellschaft z...

3. A method for decoding an encoded audio signal, the method comprising:decoding the encoded audio signal in a first time frame to obtain a set of subbands of a baseband in the first time frame and for decoding the encoded audio signal in a second time frame to obtain a set of subbands of the baseband in the second time frame;
patching the set of subbands of the baseband in the first time frame, wherein the set of subbands in the first time frame forms a patch, to further subbands in the first time frame, adjacent to the baseband, to achieve decoded audio signal comprising frequencies higher than the frequencies in the baseband for the first time frame;
patching the set of subbands of the baseband in the second time frame, wherein the set of subbands in the second time frame forms a patch, to further subbands in the second time frame, adjacent to the baseband, to achieve a decoded audio signal comprising frequencies higher than the frequencies in the baseband for the second time frame;
determining a target phase measure for an audio signal in the first time frame comprising the set of subbands or the further subbands in the first time frame;
calculating a phase error using the phase of the audio signal in the first time frame and a target phase measure; and
correcting phases of the set of subbands of the patch or of the further subbands according to the target phase measure in the first time frame; and
determining a further target phase measure for an audio signal in the second time frame comprising the set of subbands or the further subbands in the second time frame; calculating a further phase error using a further phase of the audio signal in the second time frame and the target phase measure; and correcting phases of the set of subbands of the patch or of the further subbands according to the target phase measure in the second time frame, wherein a phase derivative over frequency is received, and wherein a transient in the audio signal in the second time frame is corrected using the received phase derivative over frequency.

US Pat. No. 10,770,082

AUDIO DECODER AND METHOD FOR TRANSFORMING A DIGITAL AUDIO SIGNAL FROM A FIRST TO A SECOND FREQUENCY DOMAIN

Dolby International AB, ...

1. A method in an audio decoder for transforming a digital audio signal from a first frequency domain to a second frequency domain, comprising:receiving subsequent frames of a digital audio signal being represented in a first frequency domain, the digital audio signal having a Nyquist frequency which is half of an original sampling rate of the digital audio signal,
for each frame of the digital audio signal:identifying an upper limit of a frequency range of said frame of the digital audio signal by analyzing spectral contents of said frame of the digital audio signal, wherein the upper limit is determined as the highest frequency having a non-zero spectral content within said frame,if the upper limit of the frequency range is below the Nyquist frequency by more than a threshold amount, lowering the Nyquist frequency of said frame of the digital audio signal from its original value to a reduced value by removing spectral bands of said frame of the digital audio signal above the identified upper limit of the frequency range,transforming said frame of the digital audio signal from the first frequency domain to a second frequency domain via an intermediate time domain, wherein said frame of the digital audio signal has a sampling rate in the intermediate time domain which is reduced in relation to the original sampling rate by a sub-sampling factor defined by a ratio between the original value of the Nyquist frequency and the reduced value of the Nyquist frequency, andappending spectral bands to said frame of the digital audio signal in the second frequency domain above the reduced value of the Nyquist frequency so as to restore the Nyquist frequency to its original value.

US Pat. No. 10,770,081

STEREO AUDIO SIGNAL ENCODER

Nokia Technologies Oy, E...

1. A method comprising:receiving at least two audio channel signals;
determining, for a first frame, at least two parameters representing a difference between the at least two channel audio signals;
scalar quantising the at least two parameters to generate at least two index values;
adaptively encoding an initial scalar quantized parameter of the at least two parameters;
determining whether the initial scalar quantized parameter has a value different from a predetermined value;
adaptively encoding any unencoded scalar quantized parameters where the initial scalar quantized parameter has a value different from the predetermined value;
determining whether the at least two scalar quantized parameters have values equal to the predetermined value where the initial scalar quantized parameter has a value equal to the predetermined value;
adaptively encoding any unencoded scalar quantized parameters and generating an indicator that an output is one of fixed or variable rate coding where the initial scalar quantized parameter has a value equal to the predetermined value and at least one of the at least two scalar quantized parameters have values different from the predetermined value;
generating an indicator that the output is the other of the one of fixed or variable rate coding where the initial scalar quantized parameter has a value equal to the predetermined value and the at least two scalar quantized parameters have values equal to the predetermined value;
generating a single channel representation of the at least two audio channel signals dependent on the at least two parameters; and
encoding the single channel representation.

US Pat. No. 10,770,080

AUDIO DECODER, AUDIO ENCODER, METHOD FOR PROVIDING AT LEAST FOUR AUDIO CHANNEL SIGNALS ON THE BASIS OF AN ENCODED REPRESENTATION, METHOD FOR PROVIDING AN ENCODED REPRESENTATION ON THE BASIS OF AT LEAST FOUR AUDIO CHANNEL SIGNALS AND COMPUTER PROGRAM USING

Fraunhofer-Gesellschaft z...

1. An audio decoder for providing at least four bandwidth-extended channel signals on the basis of an encoded representation, comprising:a multi-channel decoder configured to provide a first downmix signal and a second downmix signal on the basis of a jointly encoded representation of the first downmix signal and the second downmix signal using a multi-channel decoding;
wherein the audio decoder is configured to provide at least a first audio channel signal and a second audio channel signal on the basis of the first downmix signal using a multi-channel decoding;
wherein the audio decoder is configured to provide at least a third audio channel signal and a fourth audio channel signal on the basis of the second downmix signal using a multi-channel decoding;
a first multi-channel bandwidth extension configured to perform a multi-channel bandwidth extension on the basis of the first audio channel signal and the third audio channel signal, to acquire a first bandwidth-extended channel signal and a third bandwidth-extended channel signal; and
a second multi-channel bandwidth extension configured to perform a multi-channel bandwidth extension on the basis of the second audio channel signal and the fourth audio channel signal, to acquire a second bandwidth extended channel signal and a fourth bandwidth extended channel signal.

US Pat. No. 10,770,079

APPARATUS AND METHOD FOR PROCESSING AN INPUT AUDIO SIGNAL USING CASCADED FILTERBANKS

Franhofer-Gesellschaft zu...

1. Apparatus for processing a time discrete input audio signal, comprising:a synthesis filterbank that receives, as an input, a plurality of time discrete first subband signals representing the time discrete input audio signal and having been generated by an analysis filterbank, and that synthesizes an audio intermediate signal from the input audio signal, wherein a number of channels of the synthesis filterbank is smaller than a number of channels of the analysis filterbank; and
a further analysis filterbank that receives, as an input, the audio intermediate signal and that generates a plurality of time discrete second subband signals from the audio intermediate signal, wherein the further analysis filterbank comprises a number of channels being different from the number of channels of the synthesis filterbank, and wherein a sampling rate of a time discrete subband signal of the plurality of time discrete second subband signals is different from a sampling rate of a time discrete first subband signal of the plurality of time discrete first subband signals,
wherein the further analysis filterbank or the synthesis filterbank comprises a prototype window function calculator for calculating a prototype window function by subsampling or interpolating using a stored window function for a filterbank comprising a different size using information on a number of channels for the further analysis filterbank or the synthesis filterbank,
wherein a coefficient of the prototype window function is calculated using a weighted addition of different coefficients of the stored window function, wherein weighting factors of the weighted addition and indices of the different coefficients of the stored window function are derived from integer and fractional parts of a value derived from the different size, an index of the coefficient of the prototype window function, and the information on the number of channels for the further analysis filterbank or the synthesis filterbank, and
wherein at least one of the synthesis filterbank and the further analysis filterbank comprises a hardware implementation.

US Pat. No. 10,770,078

ADAPTIVE GAIN-SHAPE RATE SHARING

Telefonaktiebolaget LM Er...

1. A method in an encoder for allocating bits to a gain adjustment quantizer and a shape quantizer to be used for encoding a gain shape vector comprising a gain adjustment factor and a shape vector, the method comprising:determining a current bitrate and a signal bandwidth;
identifying a bit allocation for the gain adjustment quantizer and the shape quantizer for the determined current bitrate and the signal bandwidth by using information mapping bit allocations to the gain adjustment quantizer and the shape quantizer based on bitrate and signal bandwidth; and
applying the identified bit allocation when encoding the gain shape vector.

US Pat. No. 10,770,077

ELECTRONIC DEVICE AND METHOD

Toshiba Client Solutions ...

1. An electronic device comprising:a microphone configured to collect a voice;
a memory in which at least the collected voice and speaker feature data are stored;
a display configured to display at least a recording view and a reproduction view as a display screen; and
a hardware processor configured to execute a voice recorder application, the hardware processor configured to:
record the voice collected by the microphone as audio data on the memory according to a recording operation in the recording view;
classify a plurality of voice sections of the recorded audio data into a plurality of clusters corresponding to a plurality of speakers, for displaying the reproduction view;
extract a speaker feature amount included in one or more voice sections classified into the same cluster, and register in the memory the speaker feature amount as the speaker feature data;
delete the speaker feature data whose importance is low if the number of the speaker feature data of the memory exceeds a predetermined number; and
compare the extracted speaker feature amount with the speaker feature data which have been registered, and identify a speaker name included in the speaker feature data which includes the extracted speaker feature amount as a speaker of the voice sections.

US Pat. No. 10,770,075

METHOD AND APPARATUS FOR ACTIVATING APPLICATION BY SPEECH INPUT

QUALCOMM Incorporated, S...

1. A method for processing input sound, the method comprising: receiving, at an electronic device, an input sound stream including an activation keyword for activating a target application and a speech command portion that follows the activation keyword;detecting, at the electronic device, the activation keyword from the input sound stream;
based on the detecting of an activation keyword, processing the speech command portion to determine whether to activate the target application;
generating sensor data indicative of an environment where the device is located using one or more context sensors in the electronic device; and
selectively activating the target application based on the processing of the speech command and the sensor data.

US Pat. No. 10,770,074

COOPERATIVE DELEGATION FOR DIGITAL ASSISTANTS

United Services Automobil...

10. A system, comprising:at least one processor; and
a memory communicatively coupled to the at least one processor, the memory storing instructions which, when executed by the at least one processor, cause the at least one processor to perform operations comprising:
receiving a first request communicated to a first digital assistant (DA) executing on a computing device, the request comprising one or more terms;
determining, based on the one or more first terms, if the first DA is capable of handling the first request;
initiating, responsive to determining that the first DA is capable of handling the first request, a communication session between a user and the first DA to handle the first request;
receiving, during the communication session between the user and the first DA, a second request comprising one or more second terms;
accessing a DA directory that includes, for each of a plurality of available DAs on the computing device, a respective list of associated keywords;
determining that at least one term of the one or more second terms corresponds to at least one keyword that is associated, in the DA directory, with multiple candidate DAs;
receiving selection data indicating that the user has selected a second DA from the multiple candidate DAs;
determining, responsive to determining that the first DA is incapable of handling the second request, that the second DA is configured to handle the second request, wherein the second DA executes on the computing device that executes the first DA; and
initiating, responsive to determining the second DA, a communication session between the user and the second DA to handle the second request.

US Pat. No. 10,770,073

REDUCING THE NEED FOR MANUAL START/END-POINTING AND TRIGGER PHRASES

Apple Inc., Cupertino, C...

1. A non-transitory computer-readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by one or more processors of an electronic device, cause the device to:receive, from a user, a spoken user input comprising a user request;
determine whether to respond to the spoken user input based on contextual information associated with the spoken user input, wherein the contextual information comprises a direction of a user's gaze when the spoken user input was received, wherein the determining comprises:
calculating a likelihood score that a virtual assistant should provide a response to the spoken user input based on the contextual information associated with the spoken user input, wherein the response at least partially satisfies the user request;
increasing the likelihood score in response to the direction of the user's gaze being pointed at the electronic device when the spoken user input was received; and
decreasing the likelihood score in response to the direction of the user's gaze being pointed away from the electronic device when the spoken user input was received;
in response to a determination to respond to the spoken user input:
generate the response to the spoken user input; and
output the response.

US Pat. No. 10,770,071

ELECTRONIC DEVICE WITH VOICE PROCESS CONTROL AND CORRESPONDING METHODS

Motorola Mobility LLC, C...

1. A method, comprising:receiving, with one or more audio input devices of an electronic device, a first audio input, the first audio input comprising a process initiation command;
initiating, with one or more processors, a process at the electronic device in response to the process initiation command;
determining, with one or more sensors of the electronic device, one or more contextual factors within an environment of the electronic device;
receiving, with the one or more audio input devices, a second audio input, the second audio input comprising a process control command;
establishing, with the one or more processors, a timer duration window having a duration that is a function of the one or more contextual factors; and
determining, with the one or more processors, whether one or more substantially matching audio characteristics are present in both the first audio input and the second audio input; and
where the one or more substantially matching audio characteristics are absent from one of the first audio input or the second audio input, ignoring, with the one or more processors, the process control command;
the process control command comprising a process cessation command, further comprising ceasing, with the one or more processors, the process at the electronic device in response to the process cessation command where the one or more substantially matching audio characteristics are present in both the first audio input and the second audio input.

US Pat. No. 10,770,070

VOICE RECOGNITION APPARATUS, VEHICLE INCLUDING THE SAME, AND CONTROL METHOD THEREOF

Hyundai Motor Company, S...

1. A voice recognition apparatus comprising a first controller configured to:acquire a voice signal of a user and acquire a phonebook list including at least one phonebook data piece in which a name and a phone number match from a user terminal;
recognize the voice signal based on a voice recognition parameter; and
determine whether to change a value of the voice recognition parameter based on the phonebook list and change the value of the voice recognition parameter based on the determination result,
wherein the first controller extracts at least one information of a number of total phonebook data pieces, a number of phonebook data pieces in which names are one word, or a number of phonebook data pieces in which names have similar pronunciations from the phonebook list, and determines whether to change the value of the voice recognition parameter based on the extracted at least one information.

US Pat. No. 10,770,069

SPEECH PROCESSING AND CONTEXT-BASED LANGUAGE PROMPTING

International Business Ma...

1. A computer-implemented method of processing speech, the method comprising:receiving speech of a user from an audio sensor;
determining an interruption in the speech of the user and analyzing the speech of the user to determine a context of the speech at a time of the interruption;
analyzing one or more language data sources to generate a suggestion corresponding to the interruption and based on the determined context of the speech, wherein generating the suggestion comprises determining one or more words to automatically prompt the user to complete the speech after the interruption, and wherein the one or more language data sources include one or more from a group of: a document written by the user, a speech history of the user, a social media history of the user, prior suggestions to the user, and brain data of the user; and
presenting the suggestion to the user.

US Pat. No. 10,770,068

DIALOG AGENT, REPLY SENTENCE GENERATION METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

CASIO COMPUTER CO., LTD.,...

1. A dialog device comprising:a processor; and
a speaker or a display;
the processor being configured to
acquire an utterance of a user relative to content provided in real time,
set a retrieving time period that is a time period of retrieval in response to a timing of the utterance of the user,
continuously execute a retrieval operation to retrieve posted data from a microblog server during a period when the set retrieving time period elapses since the utterance of the user, the posted data relating to the content and being an utterance of another user who posts, during the period when the set retrieving time period elapses since the utterance of the user, an utterance related to the utterance of the user from a terminal other than the dialog device to the microblog server;
generate, based on the posted data retrieved by the retrieval operation, a reply sentence that is a response to the acquired utterance of the user; and
output the generated reply sentence to the user through the speaker or display, wherein the processor
until a count of posted data related to the utterance of the user having given by other users since the utterance of the user is less than a threshold, measures a count of posting related to the utterance of the user given by each of the other users,
updates a cumulative posting count of each of the other users by cumulating, each time the user makes an utterance, the count of posting of each of the other users having measured since start of the content, and
selects, from among the other users, a user for which the posted data is to be retrieved from the microblog server, based on the updated cumulative posting count of each of the other users.

US Pat. No. 10,770,067

DYNAMIC VOICE SEARCH TRANSITIONING

Amazon Technologies, Inc....

1. A method comprising:receiving, by a computer system physically coupled to a television, a pre-listen indication from a remote control wirelessly connected to the computer system, wherein the pre-listen indication is associated with a button press gesture at the remote control;
causing the computer system to enter a pre-listen state;
receiving a first voice data initiation signal from the remote control, wherein the first voice data initiation signal is associated with a button press and hold gesture at the remote control;
monitoring for first voice data at the computer system;
receiving first voice data at the computer system from the remote control;
sending the first voice data to a remote server for voice processing;
initiating a voice search user interface theme for presentation at the television, wherein the voice search user interface theme is a default user interface theme comprising a list of one or more options;
causing visual feedback associated with the first voice data to be presented at the television, wherein the visual feedback is overlaid on a voice search user interface;
receiving, from the remote server, an indication to initiate a virtual assistant user interface theme that comprises a set of one or more cards;
causing the virtual assistant user interface theme that is presented at the television to be replaced with the voice search user interface theme;
receiving, from the remote server, first search result data comprising one or more content search results; and
sending the first search result data to the television for display with the virtual assistant user interface theme, wherein the first search result data is displayed in a card-based format and is different than the list of one or more options.

US Pat. No. 10,770,066

SLOT FILLING IN SPOKEN LANGUAGE UNDERSTANDING WITH JOINT POINTER AND ATTENTION

Robert Bosch GmbH, Stutt...

1. A method for operation of a spoken language understanding (SLU) system comprising:receiving, with a processor in the SLU system, an input sequence including a plurality of words in a text phrase;
generating, with the processor, an encoded output corresponding to the plurality of words and a plurality of attention weights corresponding to the plurality of words using a recurrent neural network (RNN) encoder with an attention mechanism that receives the plurality of words as inputs to the RNN encoder;
generating, with the processor, a first probability distribution corresponding to a plurality of words in an extended slot vocabulary database being a slot word at a time step using an RNN decoder that receives the encoded output from the RNN encoder as input;
generating, with the processor, a second probability distribution corresponding to the plurality of words in the input sequence being a slot word at the time step using a pointer network that receives the plurality of attention weights as input;
generating, with the processor, a combined probability distribution based on the first probability distribution and the second probability distribution;
identifying, with the processor, a slot word corresponding to one word in the extended slot vocabulary database having a highest probability value in the combined probability distribution for the time step; and
performing, with the processor, a command using the slot word as a parameter to the command.

US Pat. No. 10,770,065

SPEECH RECOGNITION METHOD AND APPARATUS

Samsung Electronics Co., ...

1. A speech recognition method, performed by a speech recognition apparatus, the speech recognition method comprising:determining a speech recognition model, based on user information, the determining of the speech recognition model comprising determining a predictive language model included in the speech recognition model based on language models included in a range, the range being determined based on an utterance predicted to be uttered by a user of the speech recognition apparatus;
downloading the speech recognition model;
performing speech recognition, based on the speech recognition model; and
outputting a result of performing the speech recognition.

US Pat. No. 10,770,064

SYSTEM AND METHOD FOR SPEECH RECOGNITION USING DEEP RECURRENT NEURAL NETWORKS

Google LLC, Mountain Vie...

1. A system for traininga deep recurrent neural network (“deep RNN”) to perform speech recognition, the deep RNN being an RNN comprising an input layer, an output layer, and multiple recurrent hidden layers organized in a stack on top of each other;
wherein the multiple recurrent hidden layers comprise:
a lowest hidden layer configured to receive input vectors from the input layer, and
a highest hidden layer configured to generate output vectors received as inputs by the output layer, wherein at least one of the multiple recurrent hidden layers is implemented by a Long Short-term Memory (“LSTM”) RNN, wherein the system comprises one or more computers storing instructions that when executed by the one or more computers cause one or more computers to perform operations comprising:
receiving training data comprising a plurality of sequences of audio observations and, for each sequence of audio observations, a corresponding sequence of text symbols that represents the sequence of audio observations; and
training the deep RNN to map the sequences of audio observations to the corresponding sequences of text symbols.

US Pat. No. 10,770,063

REAL-TIME SPEAKER-DEPENDENT NEURAL VOCODER

Adobe Inc., San Jose, CA...

1. A method for generating speech samples, the method comprising:receiving an input tensor;
splitting said received input tensor into a first portion and a second portion;
performing a 1×1 convolution respectively on said first portion and said second portion to generate a respective first intermediate result and a second intermediate result;
summing said first intermediate result and said second intermediate result to generate a third intermediate result;
applying a post-processing function on said third intermediate result to generate a fourth intermediate result;
computing an output tensor by summing said received input tensor with said fourth intermediate result;
recursing by setting said input tensor to said output tensor until said output tensor is of size one in a pre-determined dimension; and,
performing a prediction of a speech sample using said output tensor of size one in a pre-determined dimension.

US Pat. No. 10,770,062

ADJUSTING A RANKING OF INFORMATION CONTENT OF A SOFTWARE APPLICATION BASED ON FEEDBACK FROM A USER

INTUIT INC., Mountain Vi...

1. A method, comprising:receiving, from a first user, a first audio stream associated with a content item;
extracting a first set of paralinguistic features from the first audio stream;
determining an attribute of the first user based on the first set of paralinguistic features;
annotating the content item with the attribute of the first user as metadata;
receiving a second audio stream from a second user requesting the content item;
extracting a second set of paralinguistic features from the second audio stream;
determining an attribute of the second user based on the second set of paralinguistic features;
determining the attribute of the second user matches the metadata indicating the attribute of the first user; and
providing the content item to the second user.

US Pat. No. 10,770,061

FALSE TRIGGER CORRECTION FOR A VOICE-ACTIVATED INTELLIGENT DEVICE

Harman International Indu...

1. A method for confirming a trigger for a voice-activated intelligent device, the method carried out on a device having a processing unit, including a non-transitory computer-readable storage medium, capable of executing instructions of a software program, the method comprising the steps of:listening for a trigger in an audio input;
upon hearing the trigger, performing a wake confirmation by detecting a fingerprint in the audio input, performing a wake confirmation further comprises;
monitoring, in a cloud-based environment, occurrences of a user canceling a command at the voice-activated intelligent device that was the result of a false trigger;
generating a fingerprint to associate the trigger in the audio input with a false trigger for each occurrence of a user canceling a command that was the result of the false trigger;
performing a statistical analysis on the generated fingerprints;
upon identification of a statistically viable quantity of generated fingerprints, generating a final fingerprint that defines the trigger as a false trigger;
synchronizing the final fingerprint to the voice-activated intelligent device to detect and identify the trigger as false in subsequent audio inputs that contain the trigger; and
upon confirmation that the audio input contains a trigger and a final fingerprint, instructing the voice-activated intelligent device to ignore the audio input.

US Pat. No. 10,770,060

ADAPTIVELY LEARNING VOCABULARY FOR COMPLETING SPEECH RECOGNITION COMMANDS

Lenovo (Singapore) Pte. L...

1. A method, comprising:receiving, via an audio receiver of an information handling device, user voice input from a user;
accessing, using a processor, a user profile associated with the user;
identifying, using a processor, a first word from the user voice input, wherein the first word demands performance of an original action or a user-specific action, wherein the original action performs a different command than the user-specific action;
accessing, using the processor, a word association data store associated with the user profile;
determining, in the word association data store, whether feedback input adjusting the original action to the user-specific action for the first word was previously received, wherein the feedback input does not adjust an identification of the first word; and
performing, responsive to determining that the feedback input was previously received, the user-specific action.

US Pat. No. 10,770,059

CONVERSATIONAL SPEECH AGENT

Gridspace Inc., Menlo Pa...

1. A method of operating a speech synthesizing conversation agent comprising:operating an audio interface to receive a caller audio signal during a call session;
generating an audio transcript comprising a sentiment score from the caller audio signal through operation of a sentiment analysis engine configured by a sentiment model;
communicating the audio transcript to a user interface switch configured to receive inputs from a user model;
communicating a response control from the user interface switch to a speech synthesizer engine trained with historical conversation data from the user model;
operating the speech synthesizer engine to:
generate a response signal for the caller audio signal and the audio transcript through operation of a response logic engine configured by the historical conversation data; and
generate a synthesized audio response comprising an ambient signal and a synthesized user model response from the response signal through operation of a speech synthesis model configured by the historical conversation data; communicating the synthesized audio response, responsive to the caller audio signal, through the audio interface during the call session;
receiving a user model input through the user interface switch from the user model, in response to the receiving the caller audio signal through the audio interface;
communicating a user model audio response, responsive to the caller audio signal, to the audio interface, the user model audio response comprising response audio and background noise;
storing the audio transcript, the caller audio signal, and the user model audio response as the historical conversation data in a controlled memory data structure; and
operating the speech synthesis model to generate the ambient signal from the background noise of user model responses in the historical conversation data.

US Pat. No. 10,770,058

ACOUSTIC LENS FOR MICROMACHINED ULTRASOUND TRANSDUCERS

FUJIFILM SONOSITE, INC., ...

1. An ultrasonic transducer stack comprising:a first matching layer having a first top surface and a first bottom surface, wherein the first matching layer comprises a compliant material, and wherein the first matching layer has a first thickness and a first acoustic impedance;
a lens layer having a second bottom surface comprising a polymethylpentene or a thermoset cross-linked styrene copolymer material that is textured overlying the first top surface, and a second top surface, wherein the lens layer has a second thickness and a second acoustic impedance; and
a transducer layer having a third top surface underlying the first bottom surface and the second bottom surface, wherein the transducer layer includes a micromachined ultrasound transducer configured to generate ultrasound at a center frequency, and wherein the third top surface comprises an upper membrane of the transducer.

US Pat. No. 10,770,057

SYSTEMS AND METHODS FOR NOISE CANCELATION IN A LISTENING AREA

DISH NETWORK, L.L.C., En...

1. A method for noise cancelation, comprising:receiving, by at least one computer processor, a plurality of audio data samples each representing a different baseline profile of ambient white noise associated with a media content listening area within a building;
after receiving the plurality of audio data samples each representing a different baseline profile of ambient white noise, outputting, by the at least one computer processor, programming including media content for presentation to a listener of the media content in the media content listening area within the building;
outputting, by the at least one computer processor, while outputting the programming, an audio signal based on a selected audio data sample of the plurality of received audio data samples to cancel ambient white noise for the listener of the media content in the media content listening area within the building; and
selecting, by the at least one computer processor, the selected audio data sample of the plurality of received audio data samples to cancel ambient white noise for the listener of the media content in the media content listening area within the building, wherein the selecting the selected audio data sample of the plurality of received audio data samples to cancel ambient white noise for the listener of the media content in the media content listening area within the building includes:
receiving, from a microphone, a sample of audio present in the media content listening area within the building;
for each audio data sample of the plurality of audio data samples, comparing the received sample of audio to the baseline profile of the ambient white noise associated with the media content listening area within the building represented by the audio data sample to determine common characteristics between the received sample of audio and the baseline profile of the ambient white noise associated with the media content listening area within the building represented by the audio data sample; and
selecting the selected audio data sample of the plurality of received audio data samples to cancel ambient white noise for the listener of the media content in the media content listening area within the building based on the comparison and determined common characteristics.

US Pat. No. 10,770,056

SELECTIVE NOISE CANCELLATION FOR A VEHICLE

Harman Becker Automotive ...

1. A system for performing selective active noise cancellation (ANC) for a vehicle, the system comprising:a plurality of reference sensors for being positioned external to a vehicle cabin and being configured to generate reference signals indicative of at least one of road noise and engine noise that is external to the vehicle cabin;
at least one first loudspeaker for being positioned in a first zone of the vehicle and being configured to generate a first cancellation field to cancel the at least one of road noise and engine noise in the first zone;
at least one second loudspeaker for being positioned in a second zone of the vehicle and being configured to generate a second cancellation field to cancel the at least one of road noise and engine noise in the second zone;
a plurality of error microphones for being positioned in the first zone and the second zone of the vehicle and being configured to generate a plurality of error signals; and
at least one ANC controller configured to:
determine an amount of noise present in the first zone and the second zone;
selectively drive only the at least one first loudspeaker in the first zone to generate the first cancellation field in response to the amount of noise present in the first zone being greater than the amount of noise present in the second zone of the vehicle; and
selectively drive only the at least one second loudspeaker in the second zone to generate the second cancellation field based in response to the amount of noise present in the second zone being greater than the amount of noise present in the first zone,
wherein the at least one ANC controller includes a first adaptive filter that is trained to reach a first predetermined noise level while driving only the at least one first loudspeaker and while the at least one second loudspeaker is disabled.

US Pat. No. 10,770,055

THERMAL/ACOUSTICAL LINER

1. A multi-layer, light weight and highly breathable/air permeable thermal/acoustical liner, said multi-layer liner comprising:a nonwoven, fire resistant (FR), air permeable, hydrophobic and oleophobic thermal and acoustical insulation core layer having an upper surface and a lower surface, said insulation core layer inherently fire resistant with no chemical treatment providing sound transmission loss of; at least 10 dB in the 250 to 1,000 Hz range, and 20 dB in the 1,000 to 10,000 Hz ranges and an insulation R value of 1.8 or greater;
a first highly breathable, hydrophobic and oleophobic layer disposed proximate and adjacent said upper surface of said insulation core layer, said first highly breathable layer constructed from an ePTFE membrane, said first highly breathable, hydrophobic and oleophobic layer is hydrophobic to a level of at least 10 m water column;
a second highly breathable, hydrophobic and oleophobic layer disposed proximate and adjacent said lower surface of said insulation core layer, said second highly breathable, hydrophobic and oleophobic layer hydrophobic to a level of at least 10 m water column;
a facing layer disposed proximate and adjacent a surface of said first highly breathable layer that is opposite a surface that is proximate and adjacent said insulation core layer, wherein said facing is constructed from a material that is highly breathable and fire-resistant, said facing layer comprised of a hybrid of fire-resistant combination of rayon, nylon and aramid/para-aramid configured to provide inherent fire resistance with no chemical treatment; and
a backing layer disposed proximate and adjacent a surface of said second highly breathable layer that is opposite a surface that is proximate and adjacent said insulation core layer, wherein said backing is a highly breathable, fire-resistant material, said backing layer comprised of a hybrid of fire-resistant combination of rayon, nylon and aramid/para-aramid configured to provide inherent fire resistance with no chemical treatment, and wherein said insulation core, said first highly breathable layer, said second highly breathable layer, said facing and said backing layers of said multi-layer liner are laminated to one another, and wherein said laminated multi-layer liner exhibits air permeability of 0.10 CFM or greater and MVTR of 3500 g/m2/24 hr once laminated together.

US Pat. No. 10,770,054

HEAT MOLDED, TRANSPARENT BAFFLE FOR INSTRUMENTAL SOUND DEFLECTION

1. A sound baffle comprising:a polycarbonate circular disc formed as a truncated cone having:
a cap of the cone with a hole bored through the center thereof;
a base of the cone; and
a body raising from an edge of the base to an edge of the cap and wherein the body has an arcuate curve such that an outer segment of the body defined adjacent the base of the cone is configured with a longer radius of curvature then a radius of curvature defined by an inner segment of the body that is defined adjacent the cap of the cone.

US Pat. No. 10,770,053

NOISE REDUCING LIGHTING DEVICES

ABL IP HOLDING LLC, Cony...

1. A lighting device, comprising:a housing;
a light source mounted within the housing and configured to emit light sufficient for general illumination of an area; and
a panel supported by the housing at a location to receive light from the light source at one or more light input surfaces of the panel and output the received light via a light output surface of the panel facing the area, the light propagating within material of the panel from the one or more light input surfaces to the light output surface,
wherein the light output surface of the panel comprises an acoustic noise reduction structure.

US Pat. No. 10,770,052

ANALOG RECALL SYNTHESIZER HAVING PATCH AND KNOB RECALL

Lafayette College, Easto...

1. A sound generating analog synthesizer that is comprised of at least one potentiometer, at least one switch, and at least one patch jack; and comprising a control system that can be operated in three modes, a manual mode, an automatic mode, and a guided mode; wherein the manual mode allows said at least one potentiometer, said at least one switch position, and said at least one patch cable connection to be set by hand; wherein the automatic mode automatically sets patch connections as on or off and sets potentiometer positions and switch states with electromechanical or electrical devices to reach such positions; and wherein the guided mode provides at least one visual information on how to change the potentiometer positions, switch states, and/or patch jack connections such that a previously obtained sound can be reproduced.

US Pat. No. 10,770,051

APPARATUS AND METHOD FOR HARMONIC-PERCUSSIVE-RESIDUAL SOUND SEPARATION USING A STRUCTURE TENSOR ON SPECTROGRAMS

1. An apparatus for analysing a magnitude spectrogram of an audio signal, comprising:a frequency change determiner being configured to determine a change of a frequency for each time-frequency bin of a plurality of time-frequency bins of the magnitude spectrogram of the audio signal depending on the magnitude spectrogram of the audio signal, and
a classifier being configured to assign each time-frequency bin of the plurality of time-frequency bins to a signal component group of two or more signal component groups depending on the change of the frequency determined for said time-frequency bin.

US Pat. No. 10,770,050

AUDIO DATA PROCESSING METHOD AND APPARATUS

TENCENT TECHNOLOGY (SHENZ...

1. A method comprising:obtaining audio data;
obtaining an overall spectrum of the audio data;
separating the overall spectrum into a first singing voice spectrum and a first accompaniment spectrum;
adjusting the overall spectrum according to the first singing voice spectrum and the first accompaniment spectrum, to obtain a second singing voice spectrum and a second accompaniment spectrum;
calculating an accompaniment binary mask of the audio data according to the audio data; and
processing the second singing voice spectrum and the second accompaniment spectrum using the accompaniment binary mask, to obtain accompaniment data and singing voice data.

US Pat. No. 10,770,049

KEYBOARD APPARATUS

YAMAHA CORPORATION, Hama...

1. A keyboard apparatus, comprising:a key disposed so as to be pivotable with respect to a frame;
a hammer assembly disposed so as to be pivotable in response to pivotal movement of the key;
a first member;
a second member disposed so as to be slid and moved on the first member when the hammer assembly pivots in response to pivotal movement of the key; and
a third member connected to the first member and configured to guide the second member such that the second member is not located at a distance greater than or equal to a predetermined distance from the first member, the third member having a shape in which a second contact area that is an area of contact between the second member and the third member is less than a first contact area that is an area of contact between the first member and the second member.

US Pat. No. 10,770,048

ANALOG SYNTHESIZER PATCH MORPHING AND SIMULTANEOUS PARAMETER CONTROL THOUGH INPUT DEVICES

Lafayette College, Easto...

1. A sound generating analog synthesizer comprising a controller electronically connected to rotate at least one knob, actuate at least one switch, and make at least one patch connection; said knob comprising a drive system, a shaft position sensor, and a potentiometer; wherein said controller rotates at least one knob by generating instructions to said drive system; said at least one switch comprising an electronic connection to said controller to turn on or off said switch upon receiving instructions from said controller defining a switch position; and at least one patch connection, comprising at least one patch switch, wherein said at least one patch switch controls a connection between at least one input of said patch and at least one output of said patch; and a control system to interpolate the potentiometer, the switch position and the at least one patch connection between at least two predetermined settings.

US Pat. No. 10,770,047

ELECTRIC MUSICAL INSTRUMENT HAVING REAR MOUNTED SPEAKER

Bose Corporation, Framin...

1. An electric musical instrument comprising:a body having a front side and a rear side;
a plurality of strings extending across at least a portion of the front side of the body;
at least one electric pickup to detect vibrations of the strings and generate a pickup signal;
at least one speaker mounted at the rear side of the body, the speaker comprising an acoustic driver and an acoustic deflector, and the acoustic deflector is configured to receive acoustic energy propagating from the acoustic driver and deflect at least a portion of the acoustic energy; and
an amplifier to amplify the pickup signal to generate an amplified pickup signal, and drive the at least one speaker based on the amplified pickup signal.

US Pat. No. 10,770,046

INTERACTIVE PERCUSSIVE DEVICE FOR ACOUSTIC APPLICATIONS

ODDBALL STUDIOS LTD, Lon...

1. A percussive interactive device, comprising:an external polyhedric or spherical case of deformable material; and
an internal case within the external case and housing an electronic apparatus,
wherein the electronic apparatus is configured to detect a set of external forces from at least a rebound effect applied to the electronic apparatus as a result of the external case impacting and deflecting off of a surface external to the external case, to collect electronic data related to the rebound effect, to convert the collected electronic data into converted electronic data related to the rebound effect for subsequent audio application, and to transmit the converted electronic data to remote interactive device, the converted electronic data being configured to be processed by the remote interactive device for emitting related sounds.

US Pat. No. 10,770,045

REAL-TIME AUDIO SIGNAL TOPOLOGY VISUALIZATION

Avid Technology, Inc., B...

1. A user interface for visualizing audio signal routing for an audio composition, the user interface comprising:within a graphical user interface of a digital audio workstation application displaying a node graph representing an audio signal routing of the audio composition, wherein:
the node graph includes a first node representing a first independent submix;
the first independent submix is mapped to a first channel of a mixer that enables the user to adjust the first independent submix; and
the node graph is updated in real-time when the audio signal routing of the audio composition is changed.

US Pat. No. 10,770,044

LYRICS ANALYZER

SPOTIFY AB, Stockholm (S...

1. A method, comprising:receiving a plurality of tracks at an information storage and retrieval platform via an electronic communication from a datastore of tracks, a plurality of the tracks including lyrics;
extracting n topics summarizing the lyrics of the plurality of tracks, each topic consisting of a plurality of words, where n is an integer;
generating, for each of the plurality of tracks, an n-dimensional vector using a generative statistical model based on the association of the lyrics of the track with the n topics, thereby generating a plurality of n-dimensional lyrics vectors;
receiving a set of training tracks from among the plurality of tracks, each training track having an indicator of explicitness;
training a classifier for determining whether a track is explicit, based on the lyrics vectors of each of the training tracks;
generating a first explicitness indicator for each of the plurality of tracks by applying the classifier to the lyrics vectors of each of the plurality of tracks;
training a second, different, classifier based on the lyrics vectors of at least one of the training tracks;
generating a second explicitness indicator for at least one of the plurality of tracks by applying each second classifier to the lyrics vectors of at least one of the plurality of tracks; and
generating a final explicitness indicator based on the combination of the first explicitness indicator and the second explicitness indicator.

US Pat. No. 10,770,043

TUBULAR THUNDER STICKS

1. A wireless drumstick comprising:a tubular hollow body portion, having a tip section having a plurality of LED lights mounted inside the tip section, at least a portion of the tip section being translucent to allow the LED light to illuminate the tip of the drumstick;
the tubular hollow body portion further including a wireless mic, and
a battery is electronically connected to the LED lights and wireless mic.

US Pat. No. 10,770,042

ROD HOLDER FOR MUSICAL INSTRUMENT

1. A rod holder for musical instrument, comprising:two clamp sets, each clamp set comprising a fixed clamping block, a movable clamping block, a locking member driving the movable clamping block to move toward the fixed clamping block, and a cylindrical portion connected to the fixed clamping block, one surface of the fixed clamping block and one surface of the movable clamping block which correspond to each other respectively recessed inwardly and facing to each other to form a clamping groove, and one side of the cylindrical portion opposite to the clamping groove disposed with a circular disk; and
a connecting ring, comprising two arcuate members, a first end of one of the two arcuate members pivotally connected to a first end of another arcuate member by a hinge, and a second end of one of the two arcuate members fixedly connected to a second end of another arcuate member by a pressing member, the two arcuate members assembled to form an inner ring surface and two approximately circular grooves located at the inner ring surface, wherein the two circular disks of the two clamp sets are respectively disposed in the two approximately circular grooves in a rotatable manner, and the pressing member presses the two second ends of the two arcuate members to force the two second ends to be relatively closer to each other and reduce the two approximately circular grooves, the two circular disks are respectively clamped and fixed by the two approximately circular grooves.

US Pat. No. 10,770,041

KICK PAD

Pearl Musical Instrument ...

1. A kick pad comprising:a piezoelectric element that converts a vibration generated by beating with a beater into an electric signal and outputs the electric signal;
an impact-absorbing member arranged between the piezoelectric element and a surface to be beaten by the beater; and
a sheet-like striking surface cover that includes a front surface including the surface to be beaten, and that wraps the impact-absorbing member, together with the piezoelectric element.

US Pat. No. 10,770,039

DROP TUNER

Meister Works, Inc., Fuj...

1. A drop tuner, comprising:a lock screw projected from a main saddle which is rotatably supported by the drop tuner; and
a base body supported by the lock screw so as to be capable of being inserted between the lock screw and a fine tuning screw and separated from the fine tuning screw, wherein
a rotation angle of the main saddle varies when the base body is switched between an inserted state and a separated state, and
a fin member projected toward a radial direction of the lock screw is provided on the base body near an end portion farther from the main saddle.

US Pat. No. 10,770,038

TWO PIECE SOUND-HOLE COVER

1. A sound-hole cover comprising:a frame member, the frame member having a rim and a front surface that is recessed from the rim, the frame member having a plurality of spring-loaded orifices, a back surface of the frame member having a plurality of spring member holders opening radially outwardly from a center point of the frame member;
an insert member having a planar front surface and a plurality of pegs, each peg corresponding to one of the spring-loaded orifices such that when the pegs are inserted into the spring-loaded orifices, the insert member remains on the frame member within the rim; and
a plurality of foam spring members, each foam spring member held by a corresponding spring member holder of the frame member, the foam spring members for removably holding the sound-hole cover within a sound-hole of a musical instrument.

US Pat. No. 10,770,037

MOBILE TERMINAL DEVICE

KYOCERA Document Solution...

1. A mobile terminal device comprising:a housing;
a display section housed in the housing;
a touch panel disposed on a screen of the display section;
a sensor that detects an inclination of the housing; and
a control unit that comprises a processor and, upon execution of a control program by the processor, functions as:
a display control section that allows the display section to display, at a plurality of predetermined placement locations on the screen, a plurality of objects selectable by a user's touch gesture;
an operating region decision section that, during holding of the housing with a user's one hand, determines an operating region on the screen of the display section reachable with an operating finger of the one hand from a trace of points of touch on the screen of the display section with the operating finger;
an operating region storage section that stores region data indicating the operating region determined by the operating region decision section;
a specific inclination determination section that, after storage of the region data in the operating region storage section, determines whether or not the inclination of the housing detected by the sensor is a specific inclination toward the operating finger of the one hand; and
a display change section that, upon determination of the specific inclination by the specific inclination determination section, sets a plurality of changed placement locations within the operating region, moves the plurality of objects to the set plurality of changed placement locations, respectively, and displays the plurality of objects at the plurality of changed placement locations, respectively,
wherein the control unit further functions as a determination section that determines whether or not at least one of the plurality of predetermined placement locations is contained within the operating region determined by the operating region decision section,
wherein when the determination section determines that none of the plurality of predetermined placement locations for the plurality of objects is contained within the operating region and the detected inclination of the housing is determined to be the specific inclination by the specific inclination determination section, the display change section moves the plurality of objects to the plurality of changed placement locations, respectively, within the operating region indicated by the region data stored in the operating region storage section, and displays the plurality of objects at the plurality of changed placement locations, respectively,
wherein when the determination section determines that the at least one predetermined placement location is contained within the operating region and the detected inclination of the housing is determined to be the specific inclination by the specific inclination determination section, the display change section replaces the object located at the at least one predetermined placement location with the object located out of the operating region and displays the plurality of objects in reflection of the replacement of the objects,
wherein when the determination section determines that one or some of the plurality of objects are placed within the operating region and the detected inclination of the housing is determined to be the specific inclination by the specific inclination determination section, the display change section replaces the one or some objects within the operating region with, among the remaining objects out of the operating region, one or some objects within a predetermined area located upstream in a direction of the specific inclination and displays the plurality of objects in reflection of the replacement of the objects,
wherein the control unit further functions as:
a use frequency storage section that stores respective frequencies of use of the plurality of objects; and
a first specifying section that, using the respective frequencies of use of the plurality of objects stored in the use frequency storage section, specifies, among the one or some objects within the operating region, an object having the lowest frequency of use and specifies, among the objects out of the operating region and within the predetermined area located upstream in the direction of the specific inclination, an object having the highest frequency of use, and
wherein when the determination section determines that one or some of the plurality of objects are placed within the operating region and the detected inclination of the housing is determined to be the specific inclination by the specific inclination determination section, the display change section replaces the object having the lowest frequency of use with the object having the highest frequency of use and displays the plurality of objects in reflection of the replacement of the objects.

US Pat. No. 10,770,036

PRESENTATION OF CONTENT ON LEFT AND RIGHT EYE PORTIONS OF HEADSET

Lenovo (Singapore) Pte. L...

1. A device, comprising:at least one processor;
at least one display, the at least one display comprising a left eye portion and a right eye portion, the at least one display being accessible to the at least one processor; and
storage accessible to the at least one processor and comprising instructions executable by the at least one processor to:
present, using the device, first content on one of the left eye portion and the right eye portion so that the first content is viewable respectively using one of a user's left eye and the user's right eye but not the other of the user's left eye and the user's right eye;
receive first user input to switch presentation of the first content from one of the left eye portion and the right eye portion to the other of the left eye portion and the right eye portion; and
based on receipt of the first user input, use the device to present the first content on the other of the left eye portion and the right eye portion so that the first content is viewable respectively using one of a user's left eye and the user's right eye but not the other of the user's left eye and the user's right eye.

US Pat. No. 10,770,035

SMARTPHONE-BASED RADAR SYSTEM FOR FACILITATING AWARENESS OF USER PRESENCE AND ORIENTATION

Google LLC, Mountain Vie...

1. A smartphone, comprising:a display;
a radar system, implemented at least partially in hardware, configured to:
provide a radar field;
sense reflections from an object in the radar field;
analyze the reflections from the object in the radar field; and
provide, based on the analysis of the reflections, radar data;
one or more computer processors; and
one or more computer-readable media having instructions stored thereon that, responsive to execution by the one or more computer processors, perform operations comprising:
determining, based on a first subset of the radar data, an orientation of the smartphone with reference to the object;
responsive to determining the orientation of the smartphone, entering a do-not-disturb (DND) mode when the smartphone is determined to be in a first orientation with reference to the object;
determining, based on a second subset of the radar data, a change in the orientation of the smartphone with reference to the object, the change in the orientation comprising a rotation of the smartphone within a plane that is substantially parallel to a viewing surface of the display, the rotation effective to cause the smartphone to be in a second orientation with reference to the object; and
responsive to the change in orientation, exiting the DND mode.

US Pat. No. 10,770,034

GENERATION SYSTEM, GENERATION METHOD, AND STORAGE MEDIUM

SAKAI DISPLAY PRODUCTS CO...

1. A generation system, comprising:a display control section configured to cause a mark image including a mark to be displayed on a display screen of a display panel, the mark having a prescribed shape and indicating a position of a boundary of a target region in an image;
an imaging section configured to capture a plurality of partial images each of which includes the mark and in each of which a part of the display screen is imaged with the mark image displayed on the display screen, and to generate captured image data of the plurality of partial images;
a specification section configured to specify, in each of the plurality of partial images, the target region within the partial image based on the mark included in the partial image;
an extraction section configured to extract, in each of the plurality of partial images, a target part corresponding to the target region from the captured image data of the partial image; and
a screen image data generation section configured to generate screen image data corresponding to captured image data of the whole display screen by synthesizing the target parts extracted by the extraction section.

US Pat. No. 10,770,033

APPARATUS AND METHOD FOR VISUALLY PROVIDING INFORMATION REGARDING CONTENTS INDICATING TIME INTERVAL

Samsung Electronics Co., ...

1. An electronic device comprising:a display;
at least one processor electrically connected to the display; and
a memory electrically connected to the at least one processor and including instructions,
wherein the instructions, when executed by the at least one processor, cause the at least one processor to:
display contents indicating a time interval on a first region of a screen displayed by the display,
display, in the contents, a text representing information regarding the contents,
receive a user input for scrolling the first region,
determine whether a part of the text is located on a second region included in the first region,
fix the text on the second region during a scroll operation according to the user input when the part of the text is located on the second region,
compare a size of a first area in which the text occupies within the contents and a size of a second area remaining within contents on the screen, and
allow the text and the contents on the screen to disappear together according to the user input when the size of the first area is larger than the size of the second area.

US Pat. No. 10,770,031

DISPLAY CORRECTION METHOD AND DISPLAY CORRECTION SYSTEM

BOE TECHNOLOGY GROUP CO.,...

1. A display correction method for correcting display performance of a display by a display correction system, the display correction system comprising an automatic adjustment apparatus and a light detection apparatus, the method comprising:acquiring, by the light detection apparatus, an optical signal emitted by the display, determining a first brightness value according to the optical signal, and transmitting the first brightness value to the automatic adjustment apparatus;
in response to determining that the first brightness value is different from a first standard brightness value preset for the display, adjusting, by the automatic adjustment apparatus, the brightness value of the display to the first standard brightness value;
triggering, by the automatic adjustment apparatus, a brightness sensor in the display to detect brightness of the display, and
in response to determining that a second brightness value detected by the brightness sensor is different from a second standard brightness value preset for the brightness sensor, correcting the second standard brightness value of the brightness sensor to the second brightness value.

US Pat. No. 10,770,030

PROJECTION DISPLAY DEVICE, PROJECTION CONTROL METHOD, AND PROJECTION CONTROL PROGRAM

FUJIFILM Corporation, To...

1. A projection display device having a projection display unit that performs, in accordance with input image data, spatial modulation on light emitted by a light source, and projects image light obtained through the spatial modulation onto a projection surface of a vehicle to display an image that is based on the image data,the projection surface being formed of a member having a reflectance that is higher for light in a plurality of wavelength ranges than for light in a wavelength range outside the plurality of wavelength ranges,
the projection display device comprising:
a rotation angle control mechanism comprising an actuator that controls a rotation angle of the image light on the projection surface; and
a processor, being configured to function as
an image light control unit that controls, in accordance with the rotation angle, amount of intensity of the light in the plurality of wavelength ranges included in the image light,
wherein the image light control unit controls the amount of intensity of the light in the plurality of wavelength ranges included in the image light in accordance with control information for the amount of intensity, the control information being stored in a storage medium and corresponding to the rotation angle controlled by the rotation angle control mechanism,
wherein the image light control unit controls the amount of intensity by obtaining parameters related with relation between the rotation angle and the amount of intensity.

US Pat. No. 10,770,029

DISPLAY DEVICE AND METHOD OF CONTROLLING DISPLAY DEVICE

SEIKO EPSON CORPORATION, ...

1. A display device comprising:a solid-state light source driven by a PWM signal;
a light modulation device that modulates light emitted by the solid-state light source in response to an image signal; and
a signal output unit that:
determines a duty ratio and a current value of the PWM signal;
outputs a PWM signal having a predetermined current value to the solid-state light source if the duty ratio is less than a predetermined threshold value; and
outputs a PWM signal having a current value more than the predetermined current value and increasing as the duty ratio is increases, to the solid-state light source if the duty ratio is equal to or more than the predetermined threshold value.

US Pat. No. 10,770,028

DISPLAY BRIGHTNESS ADJUSTMENT BASED ON AMBIENT LIGHT LEVEL

Lenovo (Singapore) Pte. L...

1. A method, comprising:detecting, at an information handling device, a change in light level to a new light level;
communicating, to a plurality of other devices that are separate from the information handling device, the detected change in light level;
receiving, in response to the communicating and from the plurality of other devices, light level data identified by each of the plurality of other devices;
identifying, from the received light level data, a majority light level, wherein the identifying comprises:
disregarding the light level data received from each of the plurality of other devices previously determined as being inconsistent providers of accurate light level data; and
identifying, from the light level data remaining after the disregarding, the majority light level;
determining, using a processor, that the change in light level corresponds to a change in an ambient light level via comparing the new light level to the majority light level and thereafter identifying that the new light level is substantially equivalent to the majority light level; and
adjusting, responsive to the determining, a brightness level of a display operatively coupled to the information handling device.

US Pat. No. 10,770,027

IMAGE COLOR CAST COMPENSATION METHOD AND DEVICE, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An image color cast compensation method, comprising:inputting a three-dimensional (3D) reference image, driving a display panel to display the 3D reference image, and determining pixels with color cast in the 3D reference image as target pixels;
with respect to each of the target pixels, determining a color cast value for a to-be-displayed image corresponding to the target pixel in accordance with the 3D reference image;
determining an inverted color corresponding to the color cast value in accordance with the 3D reference image, and taking the inverted color as a complementary color for the target pixel; and
compensating a to-be-outputted 3D image signal in accordance with the complementary color.

US Pat. No. 10,770,025

METHOD FOR TRANSMITTING AND RECEIVING DATA IN DISPLAY DEVICE AND DISPLAY PANEL DRIVE DEVICE

SILICON WORKS CO., LTD., ...

1. A data drive device in a display device, the data drive device comprising:a data reception circuit configured to train a communication clock according to a received clock pattern, to receive first link data in accordance with the communication clock, to train a data link according to the first link data, to receive image data in a plurality of image reception periods within one frame period, to sort the image data in accordance with the data link, to receive second link data in a link reception period disposed between the plurality of image reception periods, and to retrain the data link according to the second link data; and
a data voltage drive circuit configured to generate a data voltage by converting the image data and to supply the data voltage to each sub-pixel.

US Pat. No. 10,770,024

DISPLAY DEVICE HAVING A VOLTAGE GENERATOR

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a driving controller configured to sense a pattern of first image signals, and output a compensation selection signal corresponding to the sensed pattern; and
a voltage generator configured to generate a driving power voltage in response to a feedback signal having a slew rate based on the compensation selection signal, the voltage generator comprising:
a power converter configured to generate the driving power voltage in response to a power control signal;
a comparator configured to compare the driving power voltage with a reference voltage to generate a feedback signal and apply the feedback signal to a first node;
a compensation circuit comprising a plurality of compensation units, wherein the compensation circuit selects one of the compensation units in response to the compensation selection signal, and connects the selected compensation unit to the first node; and
a power control circuit configured to generate the power control signal in response to the feedback signal.

US Pat. No. 10,770,023

DYNAMIC OVERDRIVE FOR LIQUID CRYSTAL DISPLAYS

Synaptics Incorporated, ...

1. A method, comprising:determining a current pixel value for a first pixel element of a pixel array;
determining a target pixel value for the first pixel element;
determining a target voltage which causes the first pixel element to settle at the target pixel value;
selecting the target voltage or an overdrive voltage to be applied to the first pixel element to cause the first pixel element to transition from the current pixel value to the target pixel value by a first instance of time, wherein the selection is based at least in part on a position of the first pixel element in the pixel array;
applying the selected voltage to the first pixel element before the first instance of time; and
activating one or more light sources to illuminate the pixel array at the first instance of time.

US Pat. No. 10,770,022

SOURCE DRIVER AND A DISPLAY DRIVER INTEGRATED CIRCUIT

SAMSUNG ELECTRONICS CO., ...

1. A source driver, comprising:a first source line connected to a first terminal;
a second source line connected to a second terminal;
a charge sharing switch which controls a connection between the first source line and the second source line;
a first cross charge sharing switch which controls a connection between a first capacitor and the first source line, and a connection between a second capacitor and the second source line, wherein a first cross charge sharing line is connected to a first end of the first cross charge sharing switch, a second end of the first cross charge sharing switch is connected to the first source line, and the first capacitor is connected to the first cross charge sharing line though a third terminal; and
a second cross charge sharing switch which controls a connection between the first capacitor and the second source line, and a connection between the second capacitor and the first source line.

US Pat. No. 10,770,021

DISPLAY DEVICE AND DRIVING METHOD OF THE SAME

LG Display Co., Ltd., Se...

1. A display device comprising:a display panel including a first display area and a second display area;
a data correcting unit which receives n-bit input image data and generates (n-a)-bit corrected image data;
a timing control unit which receives the (n-a)-bit corrected image data and generates (n-a)-bit output image data; and
a data driver which receives the (n-a)-bit output image data and outputs a first data voltage to a first pixel disposed in the first display area and outputs a second data voltage to a second pixel which is disposed in the second display area at a position that corresponds to a position of the first pixel in the first display area,
wherein a gray scale of the first pixel and a gray scale of the second pixel are the same or are different by one gray scale, n is a natural number and a is a natural number which is smaller than n,
wherein the data correcting unit includes:
a data processing unit which divides the n-bit input image data and extracts upper (n-a)-bit first corrected data and lower a-bit second corrected data;
a frame determining unit which generates a frame signal representing an order of 2 a frames;
a position determining unit which generates a position signal determining a position where the (n-a)-bit corrected image data is output; and
a data output unit which converts the first corrected data based on the second corrected data, the frame signal, and the position signal, and outputs the corrected image data to the timing control unit, and
wherein the data output unit performs both eye gray scale mixing through the first display area and the second display area using the position signal and performs a temporal gray scale mixing within the 2 a frames using the frame signal.

US Pat. No. 10,770,020

DISPLAY PANEL

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a display area including a gate line;
a gate driver connected to an end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
wherein a stage of the plurality of stages comprises:
a clock input terminal to which a clock signal is input;
a first low voltage terminal to which a first low voltage is input;
a second low voltage terminal to which a second low voltage is input, the second low voltage being different from the first low voltage;
a first input terminal to which at least one transmission signal from a previous stage is input;
a gate voltage output terminal which outputs a gate signal including a gate-off voltage and a gate-on voltage;
a first transistor including a control terminal connected to a first node, an input terminal connected to the clock input terminal, and an output terminal connected to the gate voltage output terminal;
a third transistor including a control terminal connected to a second node, an input terminal connected to the gate voltage output terminal, and an output terminal connected to the first low voltage terminal;
a fifth transistor including a control terminal connected to the first input terminal, an input terminal connected to the second low voltage terminal, and an output terminal connected the second node; and
a tenth transistor including a control terminal, an input terminal, and an output terminal, wherein the input terminal of the tenth transistor is connected to the second low voltage terminal, and the output terminal of the tenth transistor is connected to the first node,
wherein a voltage level of the gate-off voltage includes the first low voltage.

US Pat. No. 10,770,019

METHOD AND DEVICE FOR DRIVING DISPLAY PANEL WITH TWO PULSE SIGNALS FOR PRECHARGING PIXEL DRIVE CELLS

CHONGQING HKC OPTOELECTRO...

1. A method for driving a display panel, the display panel comprising: pixel display cells in array distribution, and pixel drive cells, configured to respectively drive the pixel display cells; wherein a liquid crystal polarity of liquid crystal molecules in an x-th row is the same as a liquid crystal polarity of liquid crystal molecules in an x+4m-th row, wherein x is an integer greater than or equal to 1, and m is an integer greater than or equal to 1; and wherein the method comprises: outputting an initial scanning signal, wherein the initial scanning signal comprises two pulse signals; pre-charging an x-th row of pixel drive cells when the x-th row of pixel drive cells receive a first pulse signal; and charging the x-th row of pixel drive cells when the x-th row of pixel drive cells receive a second pulse signal, writing data into the x-th row of pixel drive cells, and meanwhile, pre-charging an x+4m-th row of pixel drive cells, and whereinthe first pulse signal and the second pulse signal are separated by 4n clock cycles, and n is an integer greater than or equal to 1.

US Pat. No. 10,770,018

SCANNING SIGNAL LINE DRIVE CIRCUIT, DISPLAY DEVICE INCLUDING THE SAME, AND SCANNING SIGNAL LINE DRIVING METHOD

SHARP KABUSHIKI KAISHA, ...

1. A scanning signal line drive circuit that selectively drives a plurality of scanning signal lines provided on a display unit of a display device, the scanning signal line drive circuit comprising:a first scanning signal line drive unit disposed on one end side of the plurality of scanning signal lines;
a second scanning signal line drive unit disposed on the other end side of the plurality of scanning signal lines;
a first power supply line configured to supply a fixed voltage to be applied to a scanning signal line to be brought into a selected state; and
a second power supply line configured to supply a fixed voltage to be applied to the scanning signal line to be brought into a non-selected state,
wherein
the first scanning signal line drive unit includes
a first activation switching element that is provided for each of odd-numbered scanning signal lines in the plurality of scanning signal lines, is in an on-state while the scanning signal line is to be in a selected state, and is in an off-state while the scanning signal line is to be in a non-selected state,
a first inactivation switching element that is provided for each of the odd-numbered scanning signal lines in the plurality of scanning signal lines, is in the off-state while the scanning signal line is to be in the selected state, and is in the on-state while the scanning signal line is to be in the non-selected state, and
a first inactivation auxiliary switching element that is provided for each of even-numbered scanning signal lines in the plurality of scanning signal lines, is in the off-state while the scanning signal line is to be in the selected state, and is in the on-state while the scanning signal line is to be in the non-selected state,
the second scanning signal line drive unit includes
a second activation switching element that is provided for each of the even-numbered scanning signal lines in the plurality of scanning signal lines, is in the on-state while the scanning signal line is to be in the selected state, and is in the off-state while the scanning signal line is to be in the non-selected state,
a second inactivation switching element that is provided for each of the even-numbered scanning signal lines in the plurality of scanning signal lines, is in the off-state while the scanning signal line is to be in the selected state, and is in the on-state while the scanning signal line is to be in the non-selected state, and
a second inactivation auxiliary switching element that is provided for each of odd-numbered scanning signal lines in the plurality of scanning signal lines, is in the off-state while the scanning signal line is to be in the selected state, and is in the on-state while the scanning signal line is to be in the non-selected state,
each of the odd-numbered scanning signal lines in the plurality of scanning signal lines is connected to the first power supply line via the first activation switching element, is connected to the second power supply line via the first inactivation switching element, and is connected to the second power supply line via the second inactivation auxiliary switching element, and
each of the even-numbered scanning signal lines in the plurality of scanning signal lines is connected to the first power supply line via the second activation switching element, is connected to the second power supply line via the second inactivation switching element, and is connected to the second power supply line via the first inactivation auxiliary switching element.

US Pat. No. 10,770,017

DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a panel, comprising:
a gate driver for driving a pixel array, wherein the gate driver comprises a multi-stage shift register; an N-th stage shift register of the multi-stage shift register comprises:
a control module having a first terminal and a second terminal, wherein the first terminal is for receiving a first signal from an (N?M)-th stage shift register; the second terminal is electrically connected to a node; the control module transmits the first signal to the node; a value of (N?M) is larger than or equivalent to 1; both N and M are positive integers;
a leakage compensation module having a third terminal and a fourth terminal, wherein the third terminal is electrically connected to a compensation voltage; the fourth terminal is electrically connected to the node; and
an output module having a fifth terminal and a sixth terminal, wherein the fifth terminal is electrically connected to the node for receiving the first signal; the sixth terminal outputs a second signal of the N-th stage shift register for driving at least some parts of the pixel array;
wherein the compensation voltage charges the node during a touch sensing period between an enable period of the first signal and an enable period of the second signal.

US Pat. No. 10,770,016

SWITCHING CIRCUIT, CONTROL CIRCUIT, DISPLAY DEVICE, GATE DRIVING CIRCUIT AND METHOD

BOE TECHNOLOGY GROUP CO.,...

1. A switching circuit, comprising a gate scanning signal receiving terminal, a second output terminal, a third output terminal, an inverter sub-circuit, an output control sub-circuit, and an output sub-circuit;wherein the gate scanning signal receiving terminal of the switching circuit is configured to receive a gate scanning signal, and the switching circuit is configured to output the gate scanning signal to the second output terminal and the third output terminal simultaneously under control of the gate scanning signal;
the inverter sub-circuit is configured to control a level of a first node in the switching circuit under control of the gate scanning signal;
the output control sub-circuit is configured to transmit a common voltage input by a common voltage terminal to the third output terminal under control of the level of the first node; and
the output sub-circuit is configured to output the gate scanning signal to both the second output terminal and the third output terminal simultaneously under control of the gate scanning signal.

US Pat. No. 10,770,015

DISPLAY APPARATUS HAVING A SMALL BEZEL

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising a display area, in which an image is displayed, and a peripheral area, which is a non-display area, the peripheral area surrounding the display area, the display apparatus comprising:a plurality of pixels disposed in the display area;
a data integrated circuit (IC) disposed in a first side portion of the peripheral area, wherein the peripheral area is disposed adjacent to the display area;
a gate IC disposed in a second side portion of the peripheral area, wherein the display area is disposed between the first and second side portions of the peripheral area;
a data fan-out part disposed in the first side portion of the peripheral area, wherein the data fan-out part extends from the data IC to the display area, wherein the data fan-out part includes a plurality of wires that are spaced apart from each other in a fanned out manner, and
a gate connecting part disposed in the second side portion of the peripheral area and electrically connecting the gate IC to an amorphous silicon gate (ASG) driving circuit disposed in a third side portion of the peripheral area, wherein the third side portion of the peripheral area is disposed adjacent to the display area in a first direction, and
wherein the display apparatus further comprises:
a gate line disposed in the display area, wherein the gate line is electrically connected to a first pixel of the plurality of pixels, and the gate line extends in the first direction; and
a data line disposed in the display area, wherein the data line is electrically connected to the first pixel, and the data line extends in a second direction that crosses the first direction,
wherein the data line is electrically connected to the data IC through one of the plurality of wires included in the data fan-out part,
wherein the gate line is electrically connected to the gate IC through the gate connecting part, and
wherein the data fan-out part is disposed between the data IC and the gate IC in the second direction.

US Pat. No. 10,770,014

DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a display panel having a display region and a peripheral region, the display panel comprising:
a substrate;
a scan driving circuit disposed on the substrate, the scan driving circuit comprising a plurality of scan driving blocks and a plurality of first conductive lines, the plurality of first conductive lines respectively coupled to and disposed between adjacent ones of the plurality of scan driving blocks, the plurality of scan driving blocks disposed corresponding to the peripheral region, and the plurality of first conductive lines disposed corresponding to the display region and the peripheral region; and
a plurality of scan lines, wherein the plurality of scan lines is disposed on the substrate, the plurality of scan driving blocks is respectively coupled to a portion of the plurality of scan lines, and one of the plurality of first conductive lines overlaps with one of the plurality of scan lines.

US Pat. No. 10,770,012

DISPLAY PANEL AND DISPLAY DEVICE

HKC Corporation Limited, ...

1. A display panel, wherein the display panel comprises a plurality of display units which extend along a first direction and are arranged along a second direction;the display unit comprises a first subpixel column, a second subpixel column, a first data line, and a second data line, all of which are arranged along the second direction, and
the first subpixel column comprises first subpixels arranged along the first direction, and one first subpixel is electrically connected only with the first data line or the second data line;
the second subpixel column comprises second subpixels arranged along the first direction, and one second subpixel is only electrically connected with the first data line or the second data line;
the first data line is electrically connected with the first subpixel and the second subpixel of a first driving polarity in the first subpixel column and the second subpixel column; and,
the second data line is electrically connected with the first subpixel and the second subpixel of a second driving polarity in the first subpixel column and the second subpixel column.

US Pat. No. 10,770,011

BUFFER CIRCUIT, PANEL MODULE, AND DISPLAY DRIVING METHOD

NOVATEK MICROELECTRONICS ...

1. A gamma circuit, comprising:a first polarity gamma buffer having a first power receiving terminal for receiving a first supply voltage, and having a second power receiving terminal for receiving a second supply voltage which is different from a ground voltage, to output a first reference voltage to a plurality of first resistance strings;
a supply voltage output circuit for providing the second supply voltage; and
a second polarity gamma buffer having a third power receiving terminal for receiving the second supply voltage and having a fourth power receiving terminal for receiving a third supply voltage lower than the second supply voltage, to output a second reference voltage to a plurality of second resistance strings,
wherein the supply voltage output circuit comprises a medium voltage gamma buffer having an output terminal and a capacitor coupled to the output terminal of the medium voltage gamma buffer, the medium voltage gamma buffer comprises a first power supply for receiving the first supply voltage, a second power supply for receiving the third supply voltage and an output supply that outputs the second supply voltage, and each of the second power receiving terminal and the third power receiving terminal is coupled to the output terminal of the medium voltage gamma buffer, and
wherein the output terminal of the medium gamma buffer is connected to an inverting input terminal of the medium voltage gamma buffer.

US Pat. No. 10,770,010

INFORMATION TERMINAL

Semiconductor Energy Labo...

1. An information terminal comprising:a touch sensor; and
a display panel capable of display information input via the touch sensor, the display panel comprising:
a first display element;
a second display element; and
a strain sensor; and
wherein the information terminal is configured so that light emitted by the second display element is sighted by a user of the information terminal when the strain sensor does not sense strain whereas light reflected by the first display element is sighted by the user of the information terminal when the strain sensor senses strain.

US Pat. No. 10,770,009

DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A display device for displaying a color image by separating a frame consisting of a plurality of fields into the individual fields and displaying an image in a different color for each field, the device comprising:a display panel including a plurality of pixel circuits capable of display in a transparent display mode, the pixel circuits being arranged in a matrix;
a driver circuit configured to drive the pixel circuits;
an image timing control portion configured to control a time to output a plurality of pieces of color image data included in input image data in an RGB format to the driver circuit, each piece of the color image data representing an image in a different color;
a signal source configured to convert externally provided input image data to YUV image data in YUV422 format and, when transparency information by which the display panel is caused to be transparent, is inputted as well, generate transparency YUV image data by adding the transparency information to information about color-difference components in the YUV image data; and
a signal processing portion configured to, when the transparency information is added, extract the transparency information from the transparency YUV image data and convert the YUV image data remaining after the extraction of the transparency information to RGB image data in the RGB format, or when the transparency information is not added, convert the YUV image data to image data in the RGB format and output both the transparency information and the RGB image data, or only the RGB image data, to the image timing control portion on a field by field basis, wherein,
the image timing control portion, when provided with the transparency information and the RGB image data, causes the display panel to be transparent so as to transmit background light, on the basis of the transparency information, or when provided with only the RGB image data, displays an image.

US Pat. No. 10,770,008

DISPLAY DEVICE WITH DIMMING PANEL

Japan Display Inc., Toky...

1. A display device comprising:a display panel comprising a plurality of pixels;
a light guide plate provided on a back surface side of the display panel;
a light source configured to emit light from a lateral side of the light guide plate;
a dimming panel provided on a display panel side of the light guide plate; and
a controller configured to control operations of at least the display panel and the dimming panel,
wherein the dimming panel comprises a plurality of dimming areas arranged in an emission direction of the light from the light source,
wherein the dimming areas are capable of individually changing transmittance of the light according to intensities of light required to display an image using the display panel,
wherein, when adjacent two of the dimming areas differ in light transmittance from each other, the controller increases output gradation values of target pixels, the target pixels being located in a predetermined area extending from a boundary between the two dimming areas in one of the two dimming areas that has lower light transmittance,
wherein the dimming areas are capable of changing the light transmittance to minimum transmittance, to maximum transmittance, or to any of one or more degrees of intermediate transmittance, the intermediate transmittance being transmittance between the minimum transmittance and the maximum transmittance, and
wherein, when the light transmittance in one of the two adjacent dimming areas having lower light transmittance is the minimum transmittance, the controller causes the output gradation values of the target pixels to be higher than those in a case where the lower light transmittance is not the minimum transmittance.

US Pat. No. 10,770,006

DISPLAY DEVICE HAVING POWER WIRES OVERLAPPING A DRIVING INTEGRATED CIRCUIT

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a plurality of pixels;
a driving integrated circuit (IC) configured to generate a data voltage for driving the pixels;
a display substrate including a display region in which the pixels are disposed and a driving IC region in which the driving IC is disposed; and
a first power wire passing below the driving IC, wherein the first power wire is separated from the driving IC by a difference in height between the first power wire and an IC body support, the first power wire transmits a first power-supply voltage for driving the pixels, and an insulating layer is disposed between the driving IC and the first power wire so that the first power wire is not electrically connected to the driving IC.

US Pat. No. 10,770,005

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device, comprising:a substrate including a display area which has an irregularly shaped side and a non-display area which includes a notch area defined by a shape of the irregularly shaped side of the display area and is disposed to enclose the display area;
a plurality of gate lines divided to be disposed in a left display area and a right display area due to the irregularly shaped side of the display area;
a plurality of data lines in the display area; and
a plurality of sensing lines disposed in the notch area and connected to the plurality of gate lines to transmit a scan output signal output from the plurality of gate lines;
a load detecting unit detecting a scan load difference of the display area due to the shape of the irregularly shaped side based on the scan output signal transmitted from the plurality of sensing lines; and
a data driver correcting an offset of a data signal based on the scan load difference detected by the load detecting unit and outputting the offset to the plurality of data lines,
wherein when a quantified scan load amount difference outputted from a load difference quantifying unit is larger than a predetermined value, the data driver corrects the offset of the data signal so as to apply a data voltage which is higher than the data voltage set based on a data control signal applied from a timing controller, and when the quantified scan load amount difference outputted from the load difference quantifying unit is smaller than the predetermined value, the data driver corrects the offset of the data signal so as to apply a data voltage which is lower than the data voltage set based on the data control signal applied from the timing controller.

US Pat. No. 10,770,004

PIXEL CIRCUIT

Samsung Display Co., Ltd....

1. A pixel circuit, comprising:an organic light-emitting diode;
a first transistor coupled between a second node and a third node, wherein a gate electrode of the first transistor is coupled to a first node;
a second transistor coupled between a data line and the second node, wherein a gate electrode of the second transistor is coupled to a first scan line;
a fourth transistor coupled between the first node and an initialization power source, wherein a gate electrode of the fourth transistor is coupled to a second scan line;
a fifth transistor coupled between a first power source and the second node, wherein a gate electrode of the fifth transistor is coupled to a first emission line; and
a sixth transistor and an eighth transistor coupled in series between the third node and the organic light-emitting diode, wherein a gate electrode of the sixth transistor is coupled to the first emission line, and a gate electrode of the eighth transistor is coupled to a second emission line,
wherein a phase of a first emission signal applied to the first emission line is delayed relative to a phase of a second emission signal applied to the second emission line.

US Pat. No. 10,770,003

TRANSFER CIRCUIT, SHIFT REGISTER, GATE DRIVER, DISPLAY PANEL, AND FLEXIBLE SUBSTRATE

JOLED INC., Tokyo (JP)

1. A transfer circuit that includes an input circuit, a reset circuit, an output circuit, and an output stabilizer circuit, and obtains an input signal at an input terminal, holds the input signal, and outputs the input signal from an output terminal as an output signal in synchronization with a clock signal, the transfer circuit comprising:a first capacitor that holds the input signal;
a first inverter circuit that has an input terminal connected to the input terminal of the transfer circuit, and outputs an inverted signal from an output terminal, the inverted signal having an inverted polarity of the input signal; and
a fourth transistor having a control signal end connected to the output terminal of the first inverter circuit, the fourth transistor switching continuity and discontinuity of a signal path between a first end of the first capacitor that holds the input signal and a first power supply,
wherein the first inverter circuit is included in the reset circuit.

US Pat. No. 10,770,002

SHIFT REGISTER CIRCUIT, DRIVING METHOD THEREOF, GATE DRIVER AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A shift register circuit comprising:an input terminal configured to receive an input pulse;
a reset terminal configured to receive a reset pulse;
a first scan voltage terminal configured to be applied with a first scan voltage;
a second scan voltage terminal configured to receive a second scan voltage;
a first reference voltage terminal configured to receive a first reference voltage;
a second reference voltage terminal configured to receive a second reference voltage;
a clock terminal configured to receive a clock signal;
an output terminal configured to output an output signal;
an input circuit configured to supply the first scan voltage to a first node in response to the input pulse received at the input terminal being active, and to supply the second scan voltage to the first node in response to the reset pulse received at the reset terminal being active;
a first control circuit configured to bring the first reference voltage terminal into conduction with a second node in response to the first reference voltage applied at the first reference voltage terminal being active, to bring the second reference voltage terminal into conduction with the second node in response to the first node being at an active potential, to supply the second reference voltage applied at the second reference voltage terminal to the first node, and bring the second reference voltage terminal into conduction with the output terminal in response to the second node being at the active potential;
a second control circuit configured to bring the second reference voltage terminal into conduction with a third node in response to the second reference voltage applied at the second reference voltage terminal being active, to bring the first reference voltage terminal into conduction with the third node in response to the first node being at the active potential, and to supply the first reference voltage applied at the first reference voltage terminal to the first node and bring the first reference voltage terminal into conduction with the output terminal in response to the third node being at the active potential; and
an output circuit configured to bring the clock terminal into conduction with the output terminal in response to the first node being at the active potential.

US Pat. No. 10,770,001

FLICKER QUANTIFICATION SYSTEM AND METHOD OF DRIVING THE SAME

Samsung Display Co., Ltd....

1. A flicker quantification system comprising:a display device configured to be driven according to a unit of a reference period comprising a first frame for writing data and at least one second frame for holding the data;
a luminance measurer configured to generate luminance data by measuring a luminance of a display surface of the display device during the reference period;
a voltage measurer configured to measure a voltage of a photo sensor corresponding to light emitted from the display surface, and to generate first voltage data representing an accumulation amount of the voltage during the first frame and second voltage data representing an accumulation amount of the voltage during the at least one second frame; and
a processor configured to calculate a flicker index value representing a ratio of a measured luminance difference to a just noticeable difference, based on the luminance data, the first voltage data, and the second voltage data,
wherein the measured luminance difference represents the difference between a luminance during the first frame and a luminance during the at least one second frame.

US Pat. No. 10,770,000

PIXEL CIRCUIT, DRIVING METHOD, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display panel, comprising a plurality of pixel circuits,wherein each of the plurality of pixel circuits comprises at least two pixel sub-circuits; and
a data line, a first scan line, a second scan line, a third scan line and a light-emitting control line corresponding to the pixel circuit,
each of the pixel sub-circuits comprises: a light-emitting control sub-circuit, a node reset sub-circuit, a drive control sub-circuit, a write sub-circuit and a light emitting device, and
in each of the pixel sub-circuits:
the light-emitting control sub-circuit is connected with a first voltage signal end, a light-emitting control end and a first node respectively: the light-emitting control sub-circuit is configured to provide a signal provided by the first voltage signal end to the first node under a control of the light-emitting control end;
the node reset sub-circuit is connected with a first scanning signal end, the first node and a second node respectively: the node reset sub-circuit is configured to form a conductive path between the first node and the second node under a control of the first scanning signal end;
the write sub-circuit is connected with a second scanning signal end, a data signal end and the second node respectively: the write sub-circuit is configured to write a data signal provided by the data signal end and a threshold voltage to the second node under a control of the second scanning signal end;
the drive control sub-circuit is connected with the first node, the second node and the light emitting device respectively; the drive control sub-circuit is configured to drive the light emitting device to emit light under a control of the second node; and
the light emitting device is connected between the drive control sub-circuit and the second voltage signal end,
the plurality of the pixel circuits is arranged in a matrix;
each column of the pixel circuits shares a single data line, and each row of the pixel circuits shares a single first scan line, a single second scan line, a single third scam line and a single light-emitting control line,
the plurality of pixel circuits comprises N rows of pixel circuits, N is an integer greater than 3, and
the first scan line of an (n+1)th row of the pixel circuits is reused as the second scan line of an nth row of the pixel circuits, the first scan line of an (n+2)th row of the pixel circuits is reused as the third scan line of an nth row of the pixel circuits, n is an integer greater than or equal to 1, and n is less than or equal to N?2.

US Pat. No. 10,769,999

DISPLAY DEVICE AND DRIVING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:a first initialization voltage source to provide a first initialization voltage;
a second initialization voltage source to provide a second initialization voltage less than the first initialization voltage;
a first pixel circuit including a first organic light emitting diode and a first driving transistor; and
a second pixel circuit including a second organic light emitting diode that includes an organic material having a band gap different from a band gap of an organic material in the first organic light emitting diode, wherein
the first pixel circuit is coupled to the first initialization voltage source and the second initialization voltage source,
the first initialization voltage is applied to a gate terminal of the first driving transistor,
the second initialization voltage is applied to an anode of the first organic light emitting diode, and
the second pixel circuit is coupled to a single initialization voltage source.

US Pat. No. 10,769,998

PIXEL CIRCUIT AND DRIVING METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

4. An array substrate comprising:a plurality of pixel circuits, the plurality of pixel circuits arranged in a matrix;
wherein each of the pixel circuits comprises a drive transistor, a data write circuit, a light emission control circuit, a compensation circuit, a reset circuit, and a light emitting device,
wherein a first control electrode of the drive transistor is coupled to a first node, wherein a second control electrode of the drive transistor is coupled to a second node, wherein a first electrode of the drive transistor is coupled to a first voltage signal terminal, wherein a second electrode of the drive transistor is coupled to a third node, and wherein the drive transistor is configured to provide a drive current;
wherein the data write circuit is configured to provide a reference signal or a data signal from a data line to the first node according to a first drive signal from a first drive signal terminal;
wherein the light emission control circuit is configured to control, according to a pixel drive signal from a pixel drive signal terminal, to provide the drive current to the light emitting device;
wherein the compensation circuit is configured to control a voltage of the second node to be equal to a voltage of the third node according to a second drive signal from a second drive signal terminal;
wherein the reset circuit is configured to provide a third voltage signal from a third voltage signal terminal to the second node according to a reset signal from a reset signal terminal; and
wherein the light emitting device is coupled between the light emission control circuit and a second voltage signal terminal and is configured to emit light according to the drive current
wherein the array substrate further comprises a plurality of cascade-coupled gate driving transistors, wherein a gate drive signal provided by the (n?1)th stage gate driving transistor serves as a second drive signal of the nth row of pixel circuits, and wherein a gate drive signal provided by the nth stage gate driving transistor serves as a first drive signal of the nth row of pixel circuits.

US Pat. No. 10,769,997

ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE

Samsung Display Co., Ltd....

1. An organic EL display device including a display region comprising:a substrate;
a plurality of pixels in the display region including a cathode;
a first power source bus line electrically connected with the plurality of pixels, the first power source bus line comprising a first portion disposed along a first side of the display region, a second portion disposed along a second side of the display region, and a third portion disposed along a third side of the display region which is connecting the first side and the second side;
a cathode contact electrically connecting the cathode, the cathode contact comprising a first portion extended along a fourth side of the display region which is facing the third side of the display region with the display region therebetween; and
a scanning line drive circuit disposed along the third side of the display region, and transmitting scanning signals to the plurality of pixels,
wherein the first power source bus line and the cathode contact are supplied with different voltage levels from each other, and the third portion of the first power source bus line is disposed between the display region and the scanning line drive circuit, and
wherein the first portion, the second portion, and the third portion of the first power source bus line are positioned outside the display region.

US Pat. No. 10,769,996

ELECTRO-OPTICAL DEVICE, ELECTRONIC APPARATUS, AND METHOD OF DRIVING ELECTRO-OPTICAL DEVICE

SEIKO EPSON CORPORATION, ...

1. An electro-optical device comprising:a plurality of groups pixel circuits;
a first data transfer line;
a plurality of data transfer lines comprising: a second data transfer line that is coupled to at least one of the plurality of groups of pixel circuits; and a third data transfer line that is coupled to at least one of the remaining of the plurality of groups of pixel circuits;
a first capacitor that includes a first electrode which is coupled to the first data transfer line and a second electrode which is coupled to the second data transfer line; and
a second capacitor that includes a third electrode which is coupled to the first data transfer line and a fourth electrode which is coupled to the third data transfer line,
wherein each pixel circuit includes:
a drive transistor that has a gate electrode, a first current terminal, and a second current terminal;
a compensation transistor that electrically couples between the first current terminal of the drive transistor and the gate electrode of the drive transistor;
a data transfer line driver circuit that switches potentials of the first data transfer line and the first electrode, in such a manner that potential change amounts of the first data transfer line and the first electrode becomes a value according to a gradation level; and
a light emitting element that emits light in brightness according to a magnitude of a current which is supplied based on a potential that is shifted in accordance with the potential change amounts from a potential according to the electrical characteristics of the drive transistor,
wherein the second data transfer line and the third data transfer line are shorter than the first data transfer line.

US Pat. No. 10,769,995

DISPLAY DEVICE AND PANEL COMPENSATION METHOD THEREOF

Silicon Works Co., Ltd., ...

1. A panel compensation method of a display device, comprising the steps of:(a) using at least one line pixel as a current source that generates a pixel current with a same value by correcting a characteristic deviation of the at least one line pixel of a display panel; and
(b) correcting a deviation between current sensing paths of a source driver by using the pixel current with the same value provided from the at least one line pixel, and correcting a characteristic deviation between pixels by using the corrected current sensing paths.

US Pat. No. 10,769,994

DISPLAY APPARATUS HAVING A NOTCH

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus, comprising:a substrate comprising:
a first pixel area;
a second pixel area having a surface area smaller than that of the first pixel area and connected to the first pixel area; and
a third pixel area spaced apart from the second pixel area and having a surface area smaller than that of the first pixel area and connected to the first pixel area, wherein a notch is formed between the second pixel area and the third pixel area, and wherein the substrate further comprises a notch peripheral area adjacent to the first, second and third pixel areas;
a plurality of pixels disposed on the substrate, and provided in each of the first, second and third pixel areas;
a first scan line disposed on the substrate, and comprising a first portion disposed in the second pixel area, a second portion disposed in the third pixel area, and a third portion which connects the first portion to the second portion and is disposed in the notch peripheral area;
a first connecting line disposed on the substrate in a first peripheral area, and configured to electrically connect the first scan line to a first scan driver;
a second scan line disposed on the substrate in the first pixel areas;
a second connecting line disposed on the substrate in a second peripheral area, and configured to electrically connect the second scan line to a second scan driver;
wherein a surface area of the first scan line in the second pixel area, the third pixel area, and the notch peripheral area is from about 90% to about 110% of a surface area of the second scan line in the first pixel area.

US Pat. No. 10,769,993

ORGANIC ELECTROLUMINESCENCE DISPLAY APPARATUS

Canon Kabushiki Kaisha, ...

1. A display apparatus that includes a pixel including a first sub-pixel and a second sub-pixel disposed adjacently to each other,wherein the first sub-pixel emits a first color and the second sub-pixel emits a second color different from the first color,
wherein each of the first sub-pixel and the second sub-pixel includes a first electrode, a second electrode, and a functional layer disposed between the first electrode and the second electrode,
wherein the first electrode of the first sub-pixel includes a first pixel electrode and a second pixel electrode disposed adjacently to each other,
wherein when a voltage is applied to the first pixel electrode and the second pixel electrode, the first pixel electrode and the second pixel electrode emit the first color, and
wherein the second pixel electrode of the first sub-pixel is disposed in each of regions between the first pixel electrode and the second sub-pixel.

US Pat. No. 10,769,992

DISPLAY PANEL, DRIVING METHOD, AND DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...

1. A display panel, comprising:a plurality of data signal lines;
a plurality of scan signal lines disposed to intersect the plurality of data signal lines to define a plurality of sub-pixels in an array;
wherein the plurality of sub-pixels each comprises a pixel driving circuit, wherein the pixel driving circuit includes a driving transistor and an organic light emitting diode, wherein the organic light emitting diode has a threshold voltage for turning on; and
an external compensation circuit comprising a power supply unit, a sampling unit and a data signal generation unit, wherein the external compensation circuit connects to the plurality of data signal lines, and transmits a compensated data signal via the plurality of data signal lines to the pixel driving circuit of each of the plurality of sub-pixels in a number of periods to compensate for the threshold voltage in a threshold compensation phase;
wherein the power supply unit provides a current signal to the driving transistor and/or the organic light emitting diode of each of the plurality of sub-pixels;
wherein the sampling unit samples a voltage signal of the driving transistor and/or the organic light emitting diode of each of the plurality of sub-pixels based on a current signal provided by the power supply unit, and compares the voltage signal with a pre-stored characteristic curve of the driving transistor and/or a characteristic curve of the organic light emitting diode of each of the plurality of sub-pixels to determine a degraded voltage of the driving transistor and/or the organic light emitting diode; and
wherein the data signal generation unit generates the compensated data signal based on the degraded voltage of the driving transistor and/or the organic light emitting diode of each of the plurality of sub-pixels determined by the sampling unit, and provides the compensated data signal to the pixel driving circuits of each of the plurality of sub-pixels;
wherein the display panel further comprising a first switch unit, a second switch unit, and a third switch unit;
wherein the first switch unit comprises a plurality of first switches, each first switch-is turned on or turned off between the power supply unit and an associated data signal line of the plurality of data signal lines;
wherein the second switch unit comprises a plurality of second switches, each second switch is turned on or turned off between the sampling unit and an associated data signal line of the plurality of data signal lines; and
wherein the third switch unit comprises a plurality of third switches, each third switch is turned on or turned off between the data signal generation unit and an associated data signal line of the plurality of data signal lines;
wherein in a first period of the threshold compensation phase, the first switch unit is turned on and sends out a first signal under control of a control terminal of the first switch unit, the second switch unit and the third switch unit are turned off, the power supply unit of the external compensation circuit transmits a fixed current signal to the associated data signal line connected thereto in response to the first signal from the control terminal of the first switch unit, and the associated data signal line transmits the current signal to a first node and a second node of the pixel driving circuit, terminal voltages at the first node and the second node change accordingly, after the power supply unit detects that a voltage of the first node is unchanged relative to a reference potential, the first switch unit is turned off;
wherein in a second period of the threshold compensation phase, the second switch unit is turned on and sends out a second signal under control of a control terminal of the second switch unit, the first switch unit and the third switch unit are turned off, sampling unit of the external compensation circuit connected to the data signal line samples a voltage signal from the data signal line, and the voltage signal is a saturated voltage of the first node relative to the reference potential in the previous period; and
wherein a timing in a third period of the threshold compensation phase is the same as the first period of the threshold compensation phase, and a timing in a fourth period of the threshold compensation phase is the same as the second period of the threshold compensation phase,
wherein the third switch unit is turned on and sends out a third signal under control of a control terminal of the third switch unit, the first switch unit and the second switch unit are turned off, wherein a date signal generated by the data signal generation unit is transmitted to the associated data signal line, in response to the third signal from the control terminal of the third switch unit.

US Pat. No. 10,769,991

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a display region comprising:
a first pixel region; and
a second pixel region and a third pixel region disposed at one side of the first pixel region to be spaced apart from each other;
a dummy region comprising a first dummy region disposed between the second pixel region and the third pixel region;
first pixels, second pixels, and third pixels respectively arranged in the first pixel region, the second pixel region, and the third pixel region, the first pixels, the second pixels, and the third pixels are disposed in a matrix of vertical lines and horizontal lines;
a data converter configured to:
receive first image data comprising effective data corresponding to the display region and dummy data corresponding to the dummy region; and
generate second image data by converting the first image data; and
a data driver configured to:
generate a data signal corresponding to the second image data; and
supply the data signal to the first pixels, the second pixels, and the third pixels,
wherein the data converter is configured to convert a gray scale value of dummy data corresponding to at least one region of the first dummy region in the first image data into a predetermined first gray scale value, the first gray scale value being between a lowest gray scale value and a highest gray scale value.

US Pat. No. 10,769,990

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate having a display region and a non-display region; and
a plurality of pixels in the display region of the substrate, each of the pixels comprising first and second sub-pixels, each of the first and second sub-pixels having a light emitting region for emitting light,
wherein the first sub-pixel comprises a first light emitting element in the light emitting region, the first light emitting element being configured to emit visible light,
wherein the second sub-pixel comprises:
a second light emitting element in the light emitting region, the second light emitting element being configured to emit infrared light; and
a light receiving element configured to receive the infrared light emitted from the second light emitting element to detect a user's touch, and
wherein the second light emitting element and the light receiving element in the second sub-pixel are electrically insulated from and optically coupled to each other to form a photo-coupler.

US Pat. No. 10,769,989

METHOD AND DEVICE FOR DETECTING THRESHOLD VOLTAGE OF DRIVING TRANSISTOR BY ADJUSTING AT LEAST ONE OF DATA SIGNAL AND REFERENCE SIGNAL LOADED ON TARGET DRIVING TRANSISTOR SUCH THAT A FIRST-ELECTRODE TARGET VOLTAGE OF THE TARGET DRIVING TRANSISTOR IS WITHIN

BOE TECHNOLOGY GROUP CO.,...

1. A detecting method for detecting threshold voltages of driving transistors, comprising:loading data signals and reference signals on respective driving transistors in a detection group;
when the respective driving transistors in the detection group are in a turn-off state, detecting first-electrode voltages of the respective driving transistors in the detection group;
determining an amount of driving transistors, first-electrode voltages of which are not within a preset voltage range, in the detection group, and determining a target adjustment set in the detection group in a case where the amount of the driving transistors, the first-electrode voltages of which are not within the preset voltage range, is greater than a threshold; and
for each target driving transistor in the target adjustment set:
during a detecting process of threshold voltages, adjusting a data signal loaded on the target driving transistor;
when the target driving transistor is in the turn-off state, detecting a first-electrode target voltage of the target driving transistor; and
determining a threshold voltage of the target driving transistor according to the first-electrode target voltage of the target driving transistor.

US Pat. No. 10,769,988

DISPLAY DEVICE CONFIGURED TO MEASURE LIGHT AND ADJUST DISPLAY BRIGHTNESS AND A METHOD OF DRIVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a screen comprising a plurality of pixels displaying an image; and
a projector comprising a light source emitting a first light and a light converter configured to change an intensity of the first light so that the projector emits a conversion light including information of the image displayed by each of the plurality of pixels,
wherein each of the plurality of pixels of the screen comprises:
a light receiving element configured to receive the conversion light from the projector and to generate a current proportional to an intensity of the conversion light within the light receiving element of the screen; and
a light emitting element configured to display the image on the screen based on the generated current,
wherein the light receiving element is electrically connected to the light emitting element and the current generated by the light receiving element is transmitted to the light emitting element by this electrical connection, and
wherein each of the plurality of pixels does not receive data voltages corresponding to the information of the image.

US Pat. No. 10,769,987

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device, comprising:first pixels in a first pixel region and connected to first scan lines;
second pixels in a second pixel region having a width less than the first pixel region, the second pixels connected to second scan lines;
a first scan driver to supply first scan signals to the first scan lines in a first scan period;
a second scan driver to supply second scan signals to the second scan lines in a second scan period;
a first signal line, connected to the first scan driver and the second scan driver, to supply a first driving signal to the first scan driver and the second scan driver;
a data driver to supply data signals to the first pixels and the second pixels through data lines; and
a signal delay circuit to delay the first driving signal in the second scan period and not to delay the first driving signal in the first scan period.

US Pat. No. 10,769,986

OLED DISPLAY DEVICE AND DRIVING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. An OLED display device, comprisingan OLED display module,
a driving module, and
a system module;
wherein the OLED display module is connected to the driving module, the driving module is connected to the system module, and the driving module comprises a display driving module and a human eye recognition module; the system module generates display data based on an image to be displayed, the display driving module drives the OLED display module to display according to the display data generated by the system module, the human eye recognition module senses a human eye's focus area and gives feedback information of the human eye's focus area to the system module; when the human eye recognition module senses the human eye's focus area, information of the human eye's focus area is fed back to the system module, the system module determines a focus area and a non-focus area according to information of the human eye's focus area, and the display driving module turns off all or part of predetermined sub-pixels in the non-focus area when the display driving module drives the OLED display module to display;
wherein a service life of the predetermined sub-pixels in the non-focus area is lower than a service life of non-predetermined sub-pixels in the non-focus area, and the predetermined sub-pixels are red sub-pixels.

US Pat. No. 10,769,985

LIGHT-EMITTING DEVICE DISPLAY

MIKRO MESA TECHNOLOGY CO....

1. A light-emitting device display, comprising:a pixel comprising:
a first light-emitting device having a first forward voltage;
a second light-emitting device having a second forward voltage,
wherein the second forward voltage is higher than the first forward voltage;
a first type scan line electrically connected to and in direct contact with a first end of the first light-emitting device, wherein the first type scan line is configured to receive a first scan voltage and provide the first scan voltage to the first light-emitting device, and the first scan voltage is switched between a first scan-on voltage and a first scan-off voltage;
a second type scan line electrically connected to and in direct contact with a first end of the second light-emitting device, wherein the second type scan line is configured to receive a second scan voltage and provide the second scan voltage to the second light-emitting device, the second scan voltage is switched between a second scan-on voltage and a second scan-off voltage, and an absolute value of a difference between the second scan-on voltage and the second scan-off voltage is greater than an absolute value of a difference between the first scan-on voltage and the first scan-off voltage; and
two data lines electrically connected to and in contact with a second end of the first light-emitting device and a second end of the second light-emitting device, respectively, wherein one of the data lines is configured to receive a first data voltage and provide the first data voltage to the first light-emitting device, another of the data lines is configured to receive a second data voltage and provide the second data voltage to the second light-emitting device, the first data voltage is higher than or equal to the first scan voltage and the second scan voltage, and the second data voltage is higher than or equal to the first scan voltage and the second scan voltage.

US Pat. No. 10,769,984

DISPLAY DEVICE AND DRIVING METHOD THEREOF

BEIJING BOE DISPLAY TECHN...

1. A display device, comprising:a display panel comprising a plurality of micro-LED pixel units arranged in an array; and
a light-controlling component on a light exiting side of the plurality of micro-LED pixel units of the display panel, the light-controlling component comprising a plurality of light-controlling regions, ones of the light-controlling regions comprising at least four sub-regions individually controllable to switch between a transmissive state and a non-transmissive state,
wherein the light-controlling component comprises:
a first substrate;
a second substrate opposite to the first substrate;
an electrically controllable optical medium layer between the first substrate and the second substrate;
a first electrode layer on a side of the first substrate facing the second substrate; and
a second electrode layer on a side of the second substrate facing the first substrate,
wherein at least one of the first electrode layer or the second electrode layer comprises a plurality of electrodes within each sub-region of the at least four sub-regions, wherein the electrodes within each sub-region are individually controllable,
wherein respective orthographic projections of the ones of the light-controlling regions on the display panel cover respective ones of the micro-LED pixel units and surrounding regions of the respective ones of the micro-LED pixel units, and the light-controlling regions do not overlap each other,
wherein the electrically controllable optical medium layer comprises ferroelectric liquid crystal material.

US Pat. No. 10,769,983

BACKLIGHT MODULE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

XIAMEN TIANMA MICRO-ELECT...

1. A backlight module, comprising:a substrate;
a plurality of LED chips arranged on a side of the substrate and electrically connected to the substrate; and
a first film disposed on a side of each of the plurality of LED chips facing away from the substrate, wherein each of the first films are formed in one piece,
wherein an orthographic projection of the at least one LED chip on a plane of the substrate is located within an orthographic projection of the first film on the plane of the substrate,
the first film has a plurality of channels penetrating through the first film,
each of the plurality of channels comprises a first side close to the at least one LED chip and a second side facing away from the at least one LED chip,
each of the plurality of channels is filled with a channel filling portion having a first end surface located on the first side and a second end surface located on the second side, the first film has a refractive index nl, and the channel filling portion has a refractive index n2, where n2>n1, wherein total reflection occurs when light emitted from the LED chips is transmitted in the channels, and
the first film has a first region and a second region surrounding the first region, an orthographic projection of the first region on the plane of the substrate at least partially overlaps with an orthographic projection of the at least one LED chip of on the plane of the substrate; in the first region, an area of the first end surface of the channel filling portion is smaller than an area of the second end surface of the channel filling portion in a same channel; and in the second region, an area of the first end surface of the channel filling portion is larger than an area of the second end surface of the channel filling portion in a same channel.

US Pat. No. 10,769,982

ALTERNATE-LOGIC HEAD-TO-HEAD GATE DRIVER ON ARRAY

Apple Inc., Cupertino, C...

1. An electronic device comprising:a display comprising:
a pixel array comprising a plurality of pixel groups; and
gate on array circuitry comprising:
a first driver configured to receive a first clock signal and a first gate-enable signal, and provide a first driving output to a first pixel group of the plurality of pixel groups;
a second driver configured to receive a second clock signal and the first gate-enable signal, and provide a second driving output to a second pixel group of the plurality of pixel groups;
a bootstrapping capacitor coupled to the first driver and the second driver, wherein the bootstrapping capacitor is configured to facilitate operations of the first driver and the second driver; and
a first shift register configured to generate the first gate-enable signal.

US Pat. No. 10,769,981

ELECTRO-OPTICAL MODULE, POWER SUPPLY SUBSTRATE, WIRING SUBSTRATE, AND ELECTRONIC APPARATUS

138 EAST LCD ADVANCEMENTS...

1. An electro-optical display panel device comprising:a liquid crystal display panel, comprising a main side which emits light, the main side comprising an upper substrate, the liquid crystal display panel further comprising a rear side opposing the main side, the rear side comprising a base substrate which protrudes beyond the upper substrate at one side of a plurality of sides forming a periphery of the liquid crystal display panel,
a flexible wiring substrate connected to the base substrate where the base substrate protrudes, the flexible wiring substrate extending outward from the base substrate at a point of connection between the flexible wiring substrate and the base substrate,
a driver integrated circuit formed on the flexible wiring substrate, a bend of approximately 180 degrees being formed in the flexible wiring substrate back towards the liquid crystal display panel such that the driver integrated circuit and a portion of the flexible wiring substrate on which the driver integrated circuit is formed extend over the rear side of the liquid crystal display panel and overlap the rear side of the liquid crystal display panel, the driver integrated circuit and the portion of the flexible wiring substrate being approximately parallel to the rear side of the liquid crystal display panel,
there being a metal frame between the liquid crystal display panel and the portion of the flexible wiring substrate on which the driver integrated circuit is formed,
further comprising a power supply substrate electrically connected to the flexible wiring substrate, the power supply substrate also being approximately parallel to the rear side of the liquid crystal display panel and not overlapping with the driver integrated circuit, the metal frame also being between the liquid crystal display panel and the power supply substrate, the power supply substrate comprising a plurality of conductive layers, each pair of conductive layers separated by an insulating layer in at least some regions, the driver integrated circuit generating a driving signal supplied through a first wiring in the flexible wiring substrate to the liquid crystal display panel, and the power supply substrate generating a power supply voltage to the driver integrated circuit through a second wiring in the flexible wiring substrate.

US Pat. No. 10,769,980

TILED DISPLAY AND OPTICAL COMPENSATION METHOD THEREOF

LG Display Co., Ltd., Se...

1. A tiled display, comprising:two or more display panels; and
a color coordinate compensation circuit configured to:
convert color coordinates of pure color data to be displayed in the two or more display panels into target color coordinates having a color gamut smaller than a color gamut defined in color coordinates of each of the two or more display panels, and
convert the pure color data into a combination of two or more different color data,
wherein the color coordinate compensation circuit is configured to convert the pure color data into a combination of two or more pure color data or a combination of one or more pure color data and a white data,
wherein the color coordinate compensation circuit is configured to convert a first pure color data into any one of a combination of a first pure color and a second pure color; a combination of the first pure color and a third pure color; a combination of the first pure color and a white: a combination of the first pure color, the second pure color, and the third pure color; a combination of the first pure color, the second pure color, and the white; and a combination of the first pure color, the third pure color, and the white, and
wherein when luminance of the first pure color is 100%, a luminance ratio of the first pure color in the color combinations exceeds 50%.

US Pat. No. 10,769,979

PIXEL ARRANGEMENT STRUCTURE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A pixel arrangement structure, comprising a plurality of circular pixels, whereinthe plurality of circular pixels comprise a center pixel and a plurality of peripheral pixels located around the center pixel, and some of the plurality of peripheral pixels distributed on a same circumference with the center pixel as a center constitute a first pixel group, so as to form a plurality of first pixel groups on different circumferences respectively,
radiuses of circumferences of the plurality of first pixel groups respectively located on different circumferences gradually increase in a direction away from the center pixel, and
a shape of the pixel arrangement structure is at least a part of a circle,
the pixel arrangement structure further comprising at least two second pixel groups each of which is composed of some of the plurality of peripheral pixels, wherein peripheral pixels in each of the second pixel groups are respectively located on different circumferences in a direction close to or away from the center pixel; and in each of the second pixel groups, a center of each of the peripheral pixels is on a straight line as a center of the center pixel, and an angle between any two adjacent second pixel groups ranges from 58° to 62°,
wherein among the plurality of circular pixels, at least the center pixel comprises at least three sub-pixels, and any two of the at least three sub-pixels have equal areas, and wherein the at least three sub-pixels constitute a pixel unit for emitting white light.

US Pat. No. 10,769,978

DETECTION SIGNAL SELECTING CIRCUIT, THIN FILM TRANSISTOR SUBSTRATE, AND DISPLAY PANEL

Wuhan China Star Optoelec...

1. A detection signal selecting circuit, used in a scan driving circuit of a display panel, the scan driving circuit comprising multi-stages driving units, each stage of the driving units outputting a scan driving signal, wherein the detection signal selecting circuit comprises:a first switch unit and a second switch unit, the first switch unit comprising a first control terminal, a first input terminal, and a first output terminal, the second switch unit comprising a second control terminal, a second input terminal, and a second output terminal, the first output terminal connecting to the second output terminal, the first input terminal connecting to an output terminal of a first-stage of the driving units, and the second input terminal connecting to an output terminal of a last-stage of the driving units;
wherein a first control signal inputted from the first control terminal controls the first switch unit to be turned on or off, and a second control signal inputted from the second control terminal controls the second switch unit to be turned on or off, to selectively output an output signal of the first output terminal or an output signal of the second output terminal based on an output sequence of the scan driving signal;
wherein the first switch unit comprises a first thin-film transistor, the first thin-film transistor comprises a first gate, a first source, and a first drain, the first gate connects to the first control terminal, the first source or the first drain connects to the first input terminal, and another one of the first source and the first drain connects to the first output terminal; and
wherein the second switch unit comprises a second thin-film transistor, the second thin-film transistor comprises a second gate, a second source, and a second drain, the second gate connects to the second control terminal, the second source or the second drain connects to the second input terminal, and another one of the second source and the second drain connects to the second output terminal.

US Pat. No. 10,769,977

SHIFT REGISTER AND DRIVING METHOD OF THE SAME, EMISSION DRIVING CIRCUIT, AND DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...

1. An emission driving circuit, comprising a shift register, wherein the shift register comprises:a first node control module electrically connected to an input signal terminal, a first clock signal terminal, a second clock signal terminal and a high level signal terminal, and configured to provide an input signal or a high level signal to a first node based on a first clock signal and a second clock signal, so as to control a level at the first node;
a second node control module electrically connected to the first node, the first clock signal terminal, the second clock signal terminal, a first low level signal terminal and the high level signal terminal, and configured to control a level at a second node based on the level at the first node, the first clock signal, the second clock signal, a first low level signal and the high level signal;
an output control module electrically connected to the first node, the second node, the high level signal terminal and a second low level signal terminal, and configured to control an output terminal to output a high level or a low level based on the level at the first node, the level at the second node, the high level signal and a second low level signal; and
a carry control module electrically connected to the second node, the high level signal terminal, the output terminal and the second low level signal terminal, and configured to control a carry terminal to output a high level or a low level based on the level at the second node, a level at the output terminal, the high level signal and the second low level signal,
wherein the output control module comprises a ninth transistor, a tenth transistor; the carry control module comprises an eleventh transistor and a twelfth transistor,
wherein the ninth transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the output terminal,
the tenth transistor has a control terminal electrically connected to the first node, a first terminal electrically connected to the second low level signal terminal and a second terminal electrically connected to the output terminal,
wherein the eleventh transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the carry terminal, and
the twelfth transistor has a control terminal electrically connected to the output terminal, a first terminal electrically connected to the second low level signal terminal and a second terminal electrically connected to the carry terminal,
wherein in a first phase when the input signal provided by the input signal terminal is at a high level, the first clock signal provided by the first clock signal terminal is at a low level, and the second clock signal provided by the second clock signal terminal is at a high level, the first node control module provides a high level at the first node, the second node control module maintains the second node at a high level in a previous phase, the output control module maintains the output terminal at a low level outputted in a previous phase based on the high level at the first node and the high level at the second node, and the carry control module controls the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal,
in a second phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a high level, and the second clock signal provided by the second clock signal terminal is at a low level, the first node control module provides a high level at the first node, the second node control module provides a low level at the second node, the output control module controls the output terminal to output a high level based on the high level at the first node and the low level at the second node, and the carry control module controls the carry terminal to output a high level based on the low level at the second node and the high level at the output terminal,
in a third phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a low level, the second clock signal provided by the second clock signal terminal is at a high level, the first node control module provides a low level at the first node, the second node control module provides a high level at the second node, the output control module controls the output terminal to output a low level based on the low level at the first node and the high level at the second node, and the carry control module controls the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal, and
in a fourth phase when the input signal provided by the input signal terminal is at a low level, the first clock signal provided by the first clock signal terminal is at a high level, the second clock signal provided by the second clock signal terminal is at a low level, the first node control module provides a low level at the first node, the second node control module provides a high level at the second node, the output control module controls the output terminal to output a low level based on the low level at the first node and the high level at the second node, and the carry control module controls the carry terminal to output a low level based on the high level at the second node and the low level at the output terminal.