US Pat. No. 10,510,877

SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a source/drain region over the substrate;
a composite layer over the substrate, wherein the composite layer comprises:
a first sublayer comprising a first material;
a second sublayer comprising a second material stacked on the first sublayer, wherein a bandgap of the second material is larger than a bandgap of the first material; and
a third sublayer comprising the first material, wherein the second sublayer is between the first sublayer and the third sublayer; and
a plug through the composite layer, and electrically connected to the source/drain region, wherein the plug includes a first portion laterally adjoining the first sublayer, a second portion laterally adjoining the second sublayer, and a third portion laterally adjoining the third sublayer, a first width of the first portion and a third width of the third portion is smaller than a second width of the second portion, and the second portion of the plug has a substantially curved sidewall profile.

US Pat. No. 10,510,875

SOURCE AND DRAIN STRUCTURE WITH REDUCED CONTACT RESISTANCE AND ENHANCED MOBILITY

TAIWAN SEMICONDUCTOR MANU...

14. A method, comprising:forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions;
forming a first gate stack on the first fin active region and a second gate stack on the second fin active region;
depositing a dielectric layer on the first and second gate stacks;
performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch;
performing a first epitaxial growth to form a first source/drain feature on the first source/drain region;
performing a second recessing process to a second source/drain region of the second fin active region by a second dry etch;
performing a fin sidewall pull back (FSWPB) process to remove portions of the dielectric layer on the second fin active region; and
performing a second epitaxial growth to form a second source/drain feature on the second source/drain region, wherein the first dry etch recesses the first fin active region to a first depth; the second dry etch recesses the second fin active region to a second depth; and the second depth is less than the first depth.

US Pat. No. 10,510,870

TECHNIQUES FOR FORMING DEVICE HAVING ETCH-RESISTANT ISOLATION OXIDE

VARIAN SEMICONDUCTOR EQUI...

1. A method for forming a semiconductor device, comprising:providing a transistor structure, the transistor structure comprising a set of semiconductor fins and a set of gate structures, disposed on the set of semiconductor fins, wherein an isolation layer is disposed between the set of semiconductor fins and between the set of gate structures;
implanting ions into an exposed area of the isolation layer, wherein an altered portion of the isolation layer is formed in the exposed area, wherein an altered region of the set of semiconductor fins is formed in an exposed portion of the set of semiconductor fins; and
performing an epitaxial growth process on the set of semiconductor fins, the performing the epitaxial growth process further comprising performing a wet etch that etches the altered portion of the isolation layer at a first etch rate, and etches an unaltered portion of the isolation layer, not exposed to the ions, at a second etch rate, greater than the first etch rate.

US Pat. No. 10,510,864

SEMICONDUCTOR DEVICE MANUFACTURING METHOD WITH REDUCED GATE ELECTRODE HEIGHT LOSS AND RELATED DEVICES

Semiconductor Manufacturi...

1. A semiconductor device manufacturing method, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises:
a substrate;
at least one source region on the substrate;
an interlayer dielectric layer covering a portion of the source region, wherein the interlayer dielectric layer has a cavity on the source region; and
a pseudo gate insulation layer at a bottom of the cavity covering a portion of the source region,
wherein providing the semiconductor structure comprises:
providing an initial structure, wherein the initial structure comprises:
the substrate;
the at least one source region on the substrate;
a pseudo gate structure on the source region, wherein the pseudo gate structure comprises the pseudo gate insulation layer on the source region and a pseudo gate electrode on the pseudo gate insulation layer; and
the interlayer dielectric layer around the pseudo gate structure, wherein an upper surface of the interlayer dielectric layer is on a same horizontal level as an upper surface of the pseudo gate electrode; and
forming a barrier layer in the cavity, wherein an upper surface of the barrier layer is lower than a top position of the cavity;
forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion on the semiconductor structure;
removing the barrier layer;
removing the pseudo gate insulation layer to expose a portion of the source region; and
forming a gate structure on the exposed portion of the source region.

US Pat. No. 10,510,861

GASEOUS SPACER AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming a gate stack over a substrate;
depositing a first gate spacer on sidewalls of the gate stack;
epitaxially growing source/drain regions on opposite sides of the gate stack;
depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer, the gaseous spacer being disposed laterally between the source/drain regions and the gate stack; and
after depositing the second gate spacer, planarizing the first gate spacer and the gate stack such that top surfaces of the first gate spacer and the gate stack are level with one another.

US Pat. No. 10,510,854

SEMICONDUCTOR DEVICE HAVING GATE BODY AND INHIBITOR FILM BETWEEN CONDUCTIVE PRELAYER OVER GATE BODY AND CONDUCTIVE LAYER OVER INHIBITOR FILM

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a gate body over a substrate;
a conductive prelayer over the gate body;
an inhibitor film over the conductive prelayer; and
a conductive layer over the inhibitor film, wherein:
the inhibitor film is between a sidewall of the conductive prelayer and a sidewall of the conductive layer,
the conductive layer has a top portion width and a bottom portion width, and
the top portion width is greater than the bottom portion width.

US Pat. No. 10,510,853

FINFET WITH TWO FINS ON STI

Taiwan Semiconductor Manu...

1. A method of forming a fin field effect transistor (FinFET) device, the method comprising:forming a first fin, the first fin having a top surface, a first sidewall, and a second sidewall, the first sidewall facing a first isolation region and the second sidewall facing a second isolation region;
forming a mask on the top surface of the first fin;
recessing the first isolation region and the second isolation region to expose the first sidewall and the second sidewall;
epitaxially growing a second fin on the first sidewall and a third fin on the second sidewall, wherein
a first sidewall of the second fin contacts the first sidewall of the first fin,
a second sidewall of the second fin faces away from the first fin, the first sidewall of the second fin and the second sidewall of the second fin being on opposing sides of the second fin,
a first sidewall of the third fin contacts the second sidewall of the first fin, and
a second sidewall of the third fin faces away from the first fin, the first sidewall of the third fin and the second sidewall of the third fin being on opposing sides of the second fin;
recessing the first fin to expose the first sidewall of the second fin and the first sidewall of the third fin; and
forming a gate structure along the first sidewall of the second fin and the first sidewall of the third fin.

US Pat. No. 10,510,852

LOW-K FEATURE FORMATION PROCESSES AND STRUCTURES FORMED THEREBY

Taiwan Semiconductor Manu...

1. A method comprising:forming a low-k layer using an Atomic Layer Deposition (ALD) process, the ALD process comprising:
for a cycle, flowing a silicon-carbon source precursor having a chemical structure comprising at least one carbon atom bonded between two silicon atoms and wherein each chemical bond of the two silicon atoms that are not bonded to the at least one carbon atom is bonded to a halogen element, wherein the silicon-carbon source precursor further includes C(SiCl2)2; and
repeating the cycle a number of times.

US Pat. No. 10,510,849

METHOD FOR AUTO-ALIGNED MANUFACTURING OF A VDMOS TRANSISTOR, AND AUTO-ALIGNED VDMOS TRANSISTOR

STMICROELECTRONICS S.R.L....

1. A MOS transistor, comprising:a semiconductor body bounded by a first and a second side, the semiconductor body having a first type of conductivity and an axis of symmetry transverse to the first and second side;
a body region having a second type of conductivity, the body region extends into the semiconductor body from the first side;
a source region having the first type of conductivity, the source region extends into the body region from the first side;
a drain electrode on the second side of the semiconductor body;
a gate electrode that extends into the semiconductor body from the first side, the gate electrode laterally faces the source region and the body region in a symmetrical manner with respect to the axis of symmetry;
one or more structural regions disposed laterally to the gate electrode and are symmetrical with respect to the axis of symmetry, the one or more structural regions having a surface, the surface of the one or more structural regions being spaced farther apart from the second side of the semiconductor body than the first side of the semiconductor body is spaced apart from the second side of the semiconductor body so as to define a step between said surface of the one or more structural regions and the first side of the semiconductor body;
one or more spacers that surround a portion of the first side of the semiconductor body, said one or more spacers being symmetrical with respect to the axis of symmetry and adjacent to the one or more structural regions;
a source electrode in electrical contact with the source region at said portion of the first side surrounded by said one or more spacers, said source electrode being adjacent to the one or more spacers.

US Pat. No. 10,510,842

SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS

GREENTHREAD, LLC, Dallas...

1. A semiconductor device, comprising:a substrate of a first doping type at a first doping level having first and second surfaces;
a first active region disposed adjacent the first surface of the substrate with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed;
a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed;
transistors formed in at least one of the first active region or second active region; and
at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the first surface to the second surface of the substrate.

US Pat. No. 10,510,839

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:receiving a semiconductor substrate;
forming a dielectric layer over the semiconductor substrate;
forming a first semiconductive layer over the dielectric layer;
forming a plurality of dopants in a first portion of the first semiconductive layer over the dielectric layer;
removing a second portion of the first semiconductive layer to form a patterned first semiconductive layer over the dielectric layer, wherein a first sidewall profile of the first portion after the removing the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion; and
using the patterned first semiconductive layer as a mask to pattern the dielectric layer to form a hole in the dielectric layer, wherein a sidewall profile of the hole in the dielectric layer is controlled by the first sidewall profile of the first portion of the patterned first semiconductive layer.

US Pat. No. 10,510,835

SEMICONDUCTOR DEVICE WITH LOW RANDOM TELEGRAPH SIGNAL NOISE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a source/drain diffusion area, defined between a first isolation structure and a second isolation structure, including:
a source region;
a drain region; and
a device channel between the source region and the drain region; and
a first doped region disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region, the first doped region separated from at least one of the source region and the drain region, the first doped region being formed on a first portion of the first junction; and
a second doped region disposed along the first junction, the second doped region being formed on a second portion of the first junction separated from the first portion of the first junction such that the first doped region and the second doped region are spaced apart from each other,
wherein the first doped region has a dopant concentration higher than that of the device channel.

US Pat. No. 10,510,833

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

TOYODA GOSEI CO., LTD., ...

1. A method for manufacturing a semiconductor device, the method comprising:forming a first groove in a stacked body comprising a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity, the first groove including a bottom portion located in the second semiconductor layer;
depositing a p-type impurity on a side portion and the bottom portion of the first groove;
ion-implanting a p-type impurity into the first semiconductor layer through the first groove;
growing a gallium nitride (GaN)-based semiconductor layer containing a p-type impurity on the first groove after the depositing the p-type impurity and forming a second groove using the first groove as an alignment mark.

US Pat. No. 10,510,825

METAL-INSULATOR-METAL CAPACITOR WITH IMPROVED TIME-DEPENDENT DIELECTRIC BREAKDOWN

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a substrate with circuit components;
a back-end-of-line (BEOL) dielectric layer having a plurality of interlevel dielectric (ILD) levels, wherein an ILD level includes a metal ILD level with metal lines and an ILD via contact ILD level with via contacts for interconnection with the circuit components; and
a capacitor level disposed between lower and upper metal levels of lower and upper ILD levels of the BEOL dielectric layer, wherein the capacitor level includes a capacitor, the capacitor comprises a bottom capacitor electrode, a capacitor dielectric disposed on the bottom capacitor electrode, and a top capacitor electrode disposed above the capacitor dielectric, and the top capacitor electrode comprises a sidewall profile with rounded corners at an interface of the top capacitor electrode and the capacitor dielectric.

US Pat. No. 10,510,823

IMPEDANCE CIRCUIT WITH POLY-RESISTOR

MediaTek Inc., Hsin-Chu ...

1. An amplifier, comprising:a first operational amplifier;
a poly-resistor, having a first terminal, a second terminal, a first control terminal and a second control terminal, wherein the poly-resistor is coupled to an output of the first operational amplifier and wherein the poly-resistor comprises a plurality of sub-poly-resistors coupled in series;
a controller, providing a first control voltage to the first control terminal and a second control voltage to the second control terminal; and
a second operational amplifier that receives an inner voltage from a terminal connected between respective sub-poly resistors of the plurality of sub-poly-resistors,
wherein a resistance between the first terminal and the second terminal of the poly-resistor is set by the first control voltage and the second control voltage;
wherein the second control voltage is different from the first control voltage.

US Pat. No. 10,510,818

ORGANIC LIGHT EMITTING DISPLAY DEVICE

SHENZHEN CHINA STAR OPTOE...

1. An organic light emitting display device, comprising:an array substrate, comprising a pixel electrode and a metal connection electrode and an auxiliary electrode located around the pixel electrode, wherein the metal connection electrode is electrically connected to the auxiliary electrode through a recessed hole formed in the array substrate; the recessed hole is located above the auxiliary electrode and forms a first cavity and a second cavity communicating with each other, and the first cavity extends from an edge line of the second cavity away from the pixel electrode in a direction away from the pixel electrode;
a pixel definition layer disposed on the array substrate; wherein the pixel definition layer is respectively provided with corresponding grooves above the recessed hole and the pixel electrode of the array substrate;
an organic light emitting diode (OLED) semiconductor layer disposed on the array substrate and the pixel definition layer; wherein the OLED semiconductor layer further covers the pixel electrode and the metal connection electrode and extends into the first cavity of the recessed hole to achieve electrical connection with the auxiliary electrode; and
a cathode disposed on the OLED semiconductor layer; wherein the cathode further extends into the first cavity of the recessed hole to achieve electrical connection with the auxiliary electrode and is in a discontinuous connection state with the recessed hole as a breakpoint.

US Pat. No. 10,510,817

METHOD FOR MANUFACTURING OLED DISPLAY DEVICE, OLED DISPLAY DEVICE AND OLED DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an OLED display device, comprising:forming a pixel-defining layer on a substrate to define a plurality of pixel regions, forming an organic film layer in each pixel region, determining at least one area to be compensated in the pixel region according to a surface shape of the organic film layer;
aligning an evaporation source, an opening of a mask and the pixel region, making each opening of the mask respectively correspond to the position of each area to be compensated;
forming an electron function layer in the area to be compensated by evaporation of the evaporation source, wherein the electron function layer is configured to compensate a surface shape of the organic film layer in the pixel region.

US Pat. No. 10,510,815

ACTIVE MATRIX ORGANIC LIGHT EMITTING DIODE BACK PLATE FOR DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an AMOLED back plate, comprising:forming source and drain electrodes on a substrate having a light shielding layer and a buffer layer covering the light shielding layer formed thereon, by a patterning process, wherein the source and drain electrodes are on the buffer layer;
depositing an active layer film and a gate insulating layer film sequentially, and forming an active layer, a gate insulating layer and a second via hole by a patterning process, wherein the active layer covers at least a part of a s urface of the source and drain electrodes, the surface being at a side of the source and drain electrodes which is farther away from the substrate, and the gate insulating layer is on the active layer; and
forming a gate electrode and a transparent anode sequentially, wherein the transparent anode is arranged in a light emitting area and connected with one of the source and drain electrodes through the second via hole; and the gate electrode is on the gate insulating layer;
wherein the gate electrode is covered by a transparent conducting film, and the gate electrode is in direct contact with the transparent conducting film.

US Pat. No. 10,510,809

OLED DISPLAY

WUHAN CHINA STAR OPTOELEC...

1. An OLED display, comprising a substrate, a thin film transistor layer formed on the substrate, a blue light OLED formed on the thin film transistor layer, a cover plate located on the blue light OLED and laminated with the substrate and a color conversion layer formed at an inner side of the cover plate;the blue light OLED comprising an anode, a hole injection layer, a hole transporting layer, a blue light emitting layer, an electron transport layer, an electron injection layer and a cathode which are stacked up from bottom to top in order;
the color conversion layer comprising a plurality of red conversion units and green conversion units which are separately located;
blue light emitted by the blue light emitting layer being respectively converted into red light by the red conversion units to emit, converted into green light by the green conversion units to emit and emitted through the cover plate, directly to realize color display;
wherein both materials of the red conversion units and the green conversion units are organic metal halide perovskite materials;
wherein a material of the red conversion units is CH3NH3Pb(I0.9Br0.1)3, and a material of the green conversion units is CH3NH3PbBr3.

US Pat. No. 10,510,799

ABSORPTION ENHANCEMENT STRUCTURE FOR IMAGE SENSOR

Taiwan Semiconductor Manu...

15. An integrated chip, comprising:a substrate comprising a plurality of sidewalls defining a first protrusion and a second protrusion disposed along a first side of the substrate;
an image sensing element arranged within the substrate; and
wherein the first protrusion comprises a first sidewall having a first flat segment and the second protrusion comprises a second sidewall having a second flat segment, the first flat segment is coupled to the second flat segment by a horizontally extending surface of the substrate that is between the first protrusion and the second protrusion.

US Pat. No. 10,510,798

METHOD OF FORMING DEEP TRENCH ISOLATION IN RADIATION SENSING SUBSTRATE AND IMAGE SENSOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming deep trench isolation in a radiation sensing substrate, comprising:forming a trench in the radiation sensing substrate, the trench extending from a back surface of the radiation sensing substrate into the radiation sensing substrate; and
forming a corrosion resistive layer in the trench, wherein the corrosion resistive layer comprises titanium carbon nitride.

US Pat. No. 10,510,792

3DIC SEAL RING STRUCTURE AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate;
a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip comprising a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate;
a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, the first conductive feature having a first width in the plurality of first dielectric layers;
a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip, the first seal ring structure having the first width in the plurality of first dielectric layers, the first seal ring structure being electrically isolated from the first conductive feature, wherein a bottom surface of the first seal ring is disposed in the second semiconductor chip, and wherein a distance between a top surface of the first seal ring and the second semiconductor chip is less than a distance between a top surface of the first substrate and the second semiconductor chip; and
a second seal ring structure extending through the plurality of first dielectric layers, wherein the second seal ring structure is spaced apart from and electrically isolated from the first seal ring structure.

US Pat. No. 10,510,790

HIGH-K DIELECTRIC LINERS IN SHALLOW TRENCH ISOLATIONS

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, the method comprising:forming an opening extending from a top surface of a semiconductor substrate into the semiconductor substrate, the opening being entirely within a p-well of the semiconductor substrate;
depositing a metal oxide layer on sidewalls and a bottom of the opening, the metal oxide layer directly contacting the p-well;
after depositing the metal oxide layer, annealing the metal oxide layer;
after annealing the metal oxide layer, depositing a dielectric material over the metal oxide layer in the opening;
performing a planarization to remove excess portions of the dielectric material; and
forming a photo image sensor completely within the p-well of the semiconductor substrate, wherein the photo image sensor is configured to receive light, and convert the light to an electrical signal, wherein a sidewall of the metal oxide layer extends continuously from a top surface of the semiconductor substrate to a top surface of the dielectric material above the top surface of the semiconductor substrate.

US Pat. No. 10,510,786

APPARATUS AND METHOD FOR IMPROVED PRECISION OF PHASE DIFFERENCE DETECTION

Sony Corporation, Tokyo ...

1. A solid-state imaging device, comprising:a pixel array unit comprising a plurality of imaging pixels for generation of a captured image and a plurality of phase difference detection pixels for phase difference detection,
wherein each of a first imaging pixel of the plurality of imaging pixels and a first phase difference detection pixel of the plurality of phase difference detection pixels comprise an on-chip lens, a first photoelectric conversion unit, and a charge accumulation unit; and
a driving control unit configured to drive the plurality of imaging pixels and the plurality of phase difference detection pixels,
wherein the charge accumulation unit of the first imaging pixel is shielded from light,
wherein at least one of a part of the first photoelectric conversion unit or a part of the charge accumulation unit of the first phase difference detection pixel is unshielded from the light,
wherein the first phase difference detection pixel shares a constituent element with another pixel of the pixel array unit,
wherein the constituent element includes at least one of a floating diffusion region, a reset transistor, an amplifier transistor, or a selection transistor,
wherein the charge accumulation unit is configured to retain charge from the first photoelectric conversion unit,
wherein the first phase difference detection pixel includes a transfer electrode,
wherein the transfer electrode is configured to transfer charge from the first photoelectric conversion unit to the charge accumulation unit,
wherein the transfer electrode is above the charge accumulation unit, and
wherein the transfer electrode comprise a transparent conductive film.

US Pat. No. 10,510,783

TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A TFT array substrate having a bottom gate structure, comprising:a bearing substrate,
a gate line and a data line arranged across each other on the bearing substrate,
a pixel region defined by the gate line and the data line, and
a thin film transistor, a pixel electrode and an active layer disposed in the pixel region, a gate of the thin film transistor being connected to the gate line, a source thereof being connected to the data line and a drain thereof being connected to the pixel electrode, wherein
an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in said insulating layer,
the drain of the thin film transistor is in said drain trench and is connected to the source through the active layer, and
wherein common electrode wires are further provided on the TFT array substrate, the insulating layer also forms a common electrode insulating layer above the common electrode wires, and common electrode via holes are formed in said common electrode insulating layer, which are filled with a drain material.

US Pat. No. 10,510,778

ARRAY SUBSTRATE, DISPLAY DEVICE AND WEARABLE DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising a plurality of pixel units, wherein each of the pixel units comprises a pixel electrode and a thin film transistor connected to the pixel electrode, the plurality of pixel units forms a display region, and the thin film transistor of each of the pixel units at an edge of the display region is closer to the edge of the display region than the pixel electrode thereof;the array substrate comprises a first arrangement region, a second arrangement region, a third arrangement region and a fourth arrangement region which together form the edge of the display region, wherein
the first arrangement region corresponds to an upper left peripheral portion of the display region, the thin film transistor of each pixel unit in the first arrangement region is on the upper left of the pixel electrode thereof;
the second arrangement region corresponds to an upper right peripheral portion of the display region, the thin film transistor of each pixel unit in the second arrangement region is on the upper right of the pixel electrode thereof;
the third arrangement region corresponds to a lower left peripheral portion of the display region, the thin film transistor of each pixel unit in the third arrangement region is on the lower left of the pixel electrode thereof; and
the fourth arrangement region corresponds to a lower right peripheral portion of the display region, the thin film transistor of each pixel unit in the fourth arrangement region is on the lower right of the pixel electrode thereof;
wherein the array substrate further comprises a plurality of edge pixel units at the upper left peripheral portion, the upper right peripheral portion, the lower left peripheral portion and the lower right peripheral portion of the display region, and a thin film transistor of each edge pixel unit at the upper left peripheral portion, the upper right peripheral portion, the lower left peripheral portion and the lower right peripheral portion of the display region is farther away from a center of the display region than the pixel electrode thereof.

US Pat. No. 10,510,774

INTEGRATED CIRCUIT POWER DISTRIBUTION NETWORK

IMEC vzw, Leuven (BE)

1. An integrated circuit device comprising:a semiconductor substrate;
a plurality of standard cells, each standard cell comprising:
a plurality of integrated transistors and interconnecting structures for locally interconnecting the transistors so as to provide a predetermined function of the standard cell, wherein each of the integrated transistors comprises at least one gate structure and wherein each gate structure is oriented in a first direction parallel to the substrate; and
at least one internal power pin for supplying a reference voltage to contacts of the integrated transistors in accordance with the predetermined function of the standard cell,
wherein a spatial dimension of each standard cell measured in a second direction orthogonal to the first direction and parallel to the substrate defines a standard cell width;
a stack of layers comprising a plurality of metal layers in which conductive metal lines are formed to route signals between the standard cells, the metal lines in each metal layer having a preferred orientation, wherein each metal layer has a preferred orientation that is orthogonal to the preferred orientation of the metal lines in an adjacent metal layer of the plurality of metal layers,
wherein a first vertical metal layer of the plurality of metal layers is the lowest metal layer in the stack that has the first direction as preferred orientation and that provides routing resources for signal routing between the standard cells, and wherein a second horizontal metal layer of the plurality of metal layers is the nearest metal layer above the first vertical metal layer in the stack,
wherein the semiconductor substrate forms a bottom level of the stack; and
a power distribution network for delivering the reference voltage to the at least one internal power pin, wherein for any conductive path in the power distribution network that electrically connects a further metal layer above the second horizontal metal layer to the at least one internal power pin, any portion of the conductive path that is contained within the second horizontal metal layer covers less than the width of the standard cell in the second direction, such that the power distribution network does not include any conductive path within the second horizontal metal layer spanning across more than any two adjacent standard cells in the second direction.

US Pat. No. 10,510,769

THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME

Micron Technology, Inc., ...

1. A method comprising:forming conductive regions over a substrate;
forming conductive materials and dielectric materials over the conductive regions, the conductive materials being electrically isolated from each other by the dielectric materials;
forming holes through the conductive materials and dielectric materials to create initial cavities in each of the conductive materials;
enlarging a size of each of the initial cavities to form enlarged cavities;
forming memory elements in the enlarged cavities, each of the memory elements formed in a respective enlarged cavity of the enlarged cavities; and
forming conductive paths through the memory elements, each of the conductive paths formed to electrically couple to a respective conductive region of the conductive regions.

US Pat. No. 10,510,766

FLASH MEMORY STRUCTURE WITH REDUCED DIMENSION OF GATE STRUCTURE AND METHODS OF FORMING THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, the method comprising:forming a first gate electrode layer on a substrate;
forming a first charge trapping dielectric on the first gate electrode layer;
forming a patterned hardmask layer over the first charge trapping dielectric;
etching the first charge trapping dielectric exposed by the patterned hardmask layer to form a patterned first charge trapping dielectric, wherein etching the first charge trapping dielectric forms a recess extending partially through the first gate electrode layer;
forming a dielectric layer on the substrate covering the patterned first charge trapping dielectric and sidewalls of the recess in the first gate electrode layer, wherein a portion of the first gate electrode layer at a bottom of the recess is exposed; and
forming a select gate structure by etching through the portion of the first gate electrode layer at the bottom of the recess using the dielectric layer as sidewall protection for an upper sidewall portion of the first gate electrode layer.

US Pat. No. 10,510,764

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:a stacked body including a plurality of conductive layers and a plurality of insulating layers, the conductive layers and the insulating layers being stacked alternately along a first direction, the conductive layers including a first conductive layer and a second conductive layer disposed above the first conductive layer;
a first insulating body extending in a second direction and being provided inside the stacked body along the first direction and dividing the first conductive layer and the second conductive layer, the second direction crossing the first direction;
a second insulating body extending in the second direction and being provided inside the stacked body along the first direction and dividing the first conductive layer and the second conductive layer, the second insulating body being at a position different from the first insulating body in a third direction, the third direction crossing the first direction and the second direction;
a third insulating body provided inside the stacked body along the first direction and dividing the first conductive layer and the second conductive layer, the third insulating body being between the first insulating body and the second insulating body;
a fourth insulating body provided inside the stacked body along the first direction, dividing the second conductive layer, and not dividing the first conductive layer, the fourth insulating body being between the first insulating body and the second insulating body, the fourth insulating body including a plurality of portions extending in the second direction, the plurality of portions contacting the third insulating body and being separated from each other in the second direction with the third insulating body interposed;
a first columnar portion provided inside the stacked body along the first direction and penetrating the first conductive layer and the second conductive layer, the first columnar portion being between the first insulating body and the fourth insulating body and including a semiconductor layer; and
a second columnar portion provided inside the stacked body along the first direction and penetrating the first conductive layer and the second conductive layer, the second columnar portion being between the second insulating body and the fourth insulating body and including a semiconductor layer.

US Pat. No. 10,510,762

SOURCE AND DRAIN FORMATION TECHNIQUE FOR FIN-LIKE FIELD EFFECT TRANSISTOR

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a first fin and a second fin over a substrate, wherein the first fin and the second fin have a fin spacing less than about 25 nm, and further wherein the first fin and the second fin each includes a channel region disposed between a source region and a drain region;
forming a gate structure over the channel regions of the first fin and the second fin; and
performing only one cycle of a cyclic deposition etch process to form a merged epitaxial source feature that spans the source regions of the first fin and the second fin and a merged epitaxial drain feature that spans the drain regions of the first fin and the second fin, wherein the one cycle of the cyclic deposition etch process includes:
a deposition process that forms a semiconductor material over the first fin and the second fin, wherein the deposition process is performed until the semiconductor material in the fin spacing between the first fin and the second fin extends above an initial height of the first fin and the second fin, and
an etching process to planarize the semiconductor material to achieve a substantially flat top surface and substantially flat sidewall surfaces for each of the merged epitaxial source feature and the merged epitaxial drain feature, wherein the etching process is separate from the deposition process.

US Pat. No. 10,510,754

COMPLIMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) WITH LOW CONTACT RESISTIVITY AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

1. An integrated circuit device comprising:an n-type metal-oxide-semiconductor (NMOS) device comprising:
a first source/drain region;
a first metal contact over the first source/drain region;
a first titanium-containing layer having a portion between the first metal contact and the first source/drain region; and
a p-type metal-oxide-semiconductor (PMOS) device comprising:
a second source/drain region;
a second metal contact over the second source/drain region; and
a second titanium-containing layer between the second metal contact and the second source/drain region, wherein the second titanium-containing layer comprises titanium silicon germanium (Ti(Si)Ge) or titanium digermanium (TiGe2).

US Pat. No. 10,510,750

HIGH VOLTAGE INTEGRATION FOR HKMG TECHNOLOGY

Taiwan Semiconductor Manu...

1. An integrated circuit (IC), comprising:a first transistor gate stack disposed in a low voltage region defined on a substrate, wherein the first transistor gate stack comprises a first gate electrode and a first gate dielectric separating the first gate electrode from the substrate; and
a third transistor gate stack disposed in a high voltage region defined on the substrate, wherein the third transistor gate stack comprises a third gate electrode and a third gate dielectric separating the third gate electrode from the substrate, wherein the third gate dielectric comprises an oxide component and a first interlayer dielectric layer.

US Pat. No. 10,510,749

RESISTOR WITHIN SINGLE DIFFUSION BREAK, AND RELATED METHOD

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit (IC), comprising:a plurality of semiconductor fins on a substrate, at least one semiconductor fin being part of at least one finFET;
a single diffusion break (SDB) in a selected one of the plurality of semiconductor fins; and
a resistor positioned within the SDB.

US Pat. No. 10,510,746

SEMICONDUCTOR DEVICE INCLUDING ELECTROSTATIC DISCHARGE PROTECTION PATTERNS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a front-end-of-line region, at least a portion of which is disposed on a substrate, the front-end-of-line region including an electrostatic discharge protection circuit and an integrated circuit electrically connected to the electrostatic discharge protection circuit;
a back-end-of-line region on the front-end-of-line region; and
an electrostatic discharge protection pattern on a scribe region of the substrate,
wherein the electrostatic discharge protection pattern comprises:
a lower pattern extending horizontally and having a side cross-sectional surface defined by a height and a width of the lower pattern, the side cross-sectional surface exposed through a side surface of the back-end-of-line region;
a via electrically connected to the lower pattern and extending perpendicularly to the substrate; and
an upper pattern electrically connected to the via.

US Pat. No. 10,510,745

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising a display region and a peripheral region surrounding the display region, wherein gate lines and data lines crossing the gate lines are arranged at the display region and a static charge shielding unit is arranged at the peripheral region, wherein the array substrate further comprises a static charge releasing line connected to the static charge shielding unit, and the static charge shielding unit is configured to release static charges at the peripheral region through the static charge releasing line,wherein the static charge shielding unit comprises:
a first electrostatic protection line,
a first electrostatic protection unit, and
at least one shielding line,
wherein the first electrostatic protection line and the at least one shielding line are parallel to the gate lines,
a length of the first electrostatic protection line along the gate lines is greater than a length of the display region along the gate lines,
a length of the at least one shielding line along the gate lines is greater than a length of the display region along the gate lines,
the first electrostatic protection line is connected to the static charge releasing line through the first electrostatic protection unit, and
the at least one shielding line is directly connected to the static charge releasing line,
wherein the array substrate further comprises a second electrostatic protection line, a second electrostatic protection unit and a third electrostatic protection unit arranged at the peripheral region, and wherein the second electrostatic protection line is arranged parallel to the gate lines, each data line is connected to the second electrostatic protection line through the second electrostatic protection unit, and the second electrostatic protection line is connected to the static charge releasing line through the third electrostatic protection unit.

US Pat. No. 10,510,744

VERTICAL NANOWIRE TRANSISTOR FOR INPUT/OUTPUT STRUCTURE

Taiwan Semiconductor Manu...

1. A method comprising:receiving an input signal to an input terminal; and
attenuating an electrostatic discharge (ESD) voltage in the input signal by a drift region of a transistor that has a resistance in series between a first source region and a first drain region of the transistor, wherein the resistance is generated by a first nanowire channel between the first source region and the first drain region, and the first nanowire channel has a lengthwise direction perpendicular to a major top surface of a device die that comprises the transistor therein.

US Pat. No. 10,510,740

STRAPPING STRUCTURE OF MEMORY CIRCUIT

Taiwan Semiconductor Manu...

1. A memory array comprising:a first memory cell comprising a first pass transistor;
a second memory cell adjacent the first memory cell comprising a second pass transistor;
a first word line strapping line in a first metallization layer and electrically connecting a gate of the first pass transistor to a first word line and a gate of the second pass transistor to the first word line, the first word line being disposed in a second metallization layer over the first metallization layer, wherein the first word line strapping line extends into the first memory cell and the second memory cell, and wherein the first word line strapping line extends over a second word line different than the first word line.

US Pat. No. 10,510,737

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...

1. A semiconductor package comprising:a substrate;
a semiconductor memory chip on the substrate;
a second semiconductor chip on the substrate and spaced laterally apart from the semiconductor memory chip;
a mold layer on the substrate and covering sides of the semiconductor memory chip and the second semiconductor chip; and
an image sensor unit on the semiconductor memory chip, the second semiconductor chip and the mold layer, the image sensor unit comprising:
a third semiconductor chip having integrated circuitry constituting a logic circuit electrically connected to the semiconductor memory chip, and
a fourth semiconductor chip stacked on the third semiconductor chip and comprising photodiodes that convert light into electric charges,
wherein the fourth semiconductor chip is electrically connected to the third semiconductor chip and the integrated circuit of the third semiconductor chip is configured to convert the electric charges generated by the photodiodes of the fourth semiconductor chip into an electrical signal, and
wherein the semiconductor package further comprises a connection pad on an upper surface of the image sensor unit, and a bonding wire electrically connecting the connection pad to a terminal of the substrate.

US Pat. No. 10,510,736

LIGHT EMITTING STRUCTURE

Apple Inc., Curpentino, ...

1. A display comprising:a display substrate;
a plurality of bottom conductive layers on the display substrate;
an electrode on the display substrate;
a passivation layer spanning across the display substrate and directly over the plurality of bottom conductive layers and the electrode;
a corresponding plurality of LED devices bonded to the plurality of bottom conductive layers, and embedded within the passivation layer;
wherein the passivation layer laterally surrounds each LED device;
an opening in the passivation layer over the electrode; and
a transparent top conductive layer directly over the passivation layer and in contact with at least one of the LED devices and spanning within the opening to contact the electrode.

US Pat. No. 10,510,735

PACKAGES AND METHODS OF FORMING PACKAGES

Taiwan Semiconductor Manu...

1. A structure comprising:a first die embedded in an encapsulant, a first pad being on an active side of the first die, a first die connector being on the first pad, the first pad having a first width and the first die connector having a second width, the first and second widths being measured in a first direction, the first direction being parallel to the active side of the first die;
a second die embedded in the encapsulant, a second pad being on an active side of the second die, a second die connector contacting the second pad, the second pad having a third width and the second die connector having a fourth width, the third and fourth widths being measured in the first direction, the fourth width being less than the third width; and
a redistribution structure over the encapsulant, the first die, and the second die, the first die being electrically coupled to the second die through the first die connector, the redistribution structure, and the second die connector.

US Pat. No. 10,510,733

INTEGRATED DEVICE COMPRISING EMBEDDED PACKAGE ON PACKAGE (POP) DEVICE

QUALCOMM Incorporated, S...

1. A device comprising:a printed circuit board (PCB);
a package on package (PoP) device coupled to the printed circuit board (PCB), wherein the package on package (PoP) device includes:
a first package having a first electronic package component;
a second package coupled to the first package; and
a gap controller configured to provide a spacing between the first electronic package component and the second package, the gap controller includes a spacer and an adhesive layer;
a first encapsulation layer formed between the first package and the second package, wherein the first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer; and
a second encapsulation layer configured to at least partially encapsulates the package on package (PoP) device.

US Pat. No. 10,510,731

PACKAGE-ON-PACKAGE (POP) STRUCTURE INCLUDING STUD BULBS

Taiwan Semiconductor Manu...

1. A device comprising:a first pad on a first surface of a first package;
a second pad on a second surface of a second package;
a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;
a solder connector in contact with the elongated portion and electrically coupled to the second pad; and
an inter-metallic compound (IMC) between the elongated portion and the solder connector.

US Pat. No. 10,510,730

STACKED SEMICONDUCTOR STRUCTURE AND METHOD

Taiwan Semiconductor Manu...

1. A device comprising:a first chip comprising:
a first connection pad embedded in a first dielectric layer; and
a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad; and
a second chip comprising:
a second connection pad on a non-bonding side of the second chip, wherein a top surface of the second connection pad is lower than a backside of a substrate of the second chip; and
a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

US Pat. No. 10,510,729

3DIC INTERCONNECT APPARATUS AND METHOD

Taiwan Semiconductor Manu...

1. An apparatus comprising:a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first metal lines formed in the plurality of first dielectric layers over the first substrate, a first surface of the plurality of first dielectric layers facing the first substrate;
a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second metal lines formed in the second dielectric layers over the second substrate;
a conductive element extending from a second surface of the first semiconductor chip to one of the plurality of second metal lines in the second semiconductor chip, the conductive element having a first portion extending through the first substrate, a second portion extending through the plurality of first dielectric layers, and a third portion extending into the plurality of second dielectric layers; and
a plurality of dielectric liners interposed between the conductive element and the first substrate, the plurality of dielectric liners not extending between the conductive element and the plurality of first dielectric layers, the conductive element contacting a portion of the first surface of the plurality of first dielectric layers, wherein the plurality of dielectric liners comprises a first liner and a second liner, wherein the second liner is interposed between the first liner and the first substrate, wherein the first liner is a spacer-shaped structure.

US Pat. No. 10,510,728

MAGNETIC COUPLING PACKAGE STRUCTURE FOR MAGNETICALLY COUPLED ISOLATOR WITH DUO LEADFRAMES AND METHOD FOR MANUFACTURING THE SAME

LITE-ON SINGAPORE PTE. LT...

1. A method for manufacturing a magnetic coupling package structure with duo leadframes for a magnetically coupled isolator, comprising:a leadframe providing step including providing a first leadframe and a second leadframe, wherein the first leadframe includes a first chip-mounting portion, at least a first coil portion, a plurality of first pins and a plurality of floated pins, and the second leadframe includes a second chip-mounting portion, at least a second coil portion, a plurality of second pins and a plurality of second floated pins;
a chip connecting step including respectively disposing at least a first chip and at least a second chip on the first chip-mounting portion and the second chip-mounting portion and establishing electrical connections between the first chip and the first pins and between the second chip and the second pins; and
a coil aligning step including disposing the first leadframe at a position above or under the second leadframe and respectively applying a first magnetic field and a second magnetic field to the first leadframe and the second leadframe for aligning the first coil portion and the second coil portion;
wherein the first chip and the first coil portion together form a first closed circuit through a first connecting wire, and the at least one second chip and the at least one second coil portion together form a second closed circuit through a second connecting wire.

US Pat. No. 10,510,727

SEMICONDUCTOR DEVICE WITH DISCRETE BLOCKS

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:forming a first redistribution layer on a first side of an encapsulant, wherein the encapsulant is planar with both a first semiconductor device and an integrated passive device within a first connection block; and
forming a second redistribution layer on a second side of the encapsulant opposite the first side of the encapsulant, the forming the second redistribution layer electrically connecting the second redistribution layer to the first redistribution layer through a first through substrate via.

US Pat. No. 10,510,725

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device, the device comprising:a base member having a first surface and a second surface, the second surface being on a side opposite to the first surface, the base member including at least one interconnect extending in a first direction along the first surface;
two or more stacked bodies arranged in the first direction on the first surface, each of the two or more stacked bodies including a plurality of semiconductor chips stacked in a second direction perpendicular to the first surface;
two or more logic chips electrically connected respectively to the stacked bodies; and
a resin member over the first surface of the base member, the resin member sealing the two or more stacked bodies and the two or more logic chips on the base member, the resin member physically contacting the first surface of the base member,
each of the plurality of semiconductor chips including a first semiconductor layer and a second semiconductor layer,
the first semiconductor layer and the second semiconductor layer each having an element surface and a back surface, an active element being provided on the element surface, the back surface being on a side opposite to the element surface, and the first semiconductor layer and the second semiconductor layer being bonded such that the element surface of the second semiconductor layer faces the element surface of the first semiconductor layer.

US Pat. No. 10,510,723

BUFFER LAYER(S) ON A STACKED STRUCTURE HAVING A VIA

Taiwan Semiconductor Manu...

1. A structure comprising:a first substrate comprising a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate;
a second substrate comprising a second semiconductor substrate and a second interconnect structure on a first side of the second semiconductor substrate, the first substrate being bonded to the second substrate at a bonding interface, the first interconnect structure and the second interconnect structure being disposed between the first semiconductor substrate and the second semiconductor substrate;
a via extending at least through the second semiconductor substrate into the second interconnect structure;
a first stress buffer layer on a second side of the second semiconductor substrate, the second side of the second semiconductor substrate being opposite from the first side of the second semiconductor substrate;
a post-passivation interconnect (PPI) structure on the first stress buffer layer and electrically coupled to the via;
a second stress buffer layer on the PPI structure and the first stress buffer layer, wherein a first portion of the second stress buffer layer and a second portion of the second stress buffer layer extend through a first region of the PPI structure to contact the first stress buffer layer, wherein the first portion and the second portion of the second stress buffer layer are separated and surrounded by the first region of the PPI structure, wherein the first region of the PPI structure is a continuous layer of electrically conductive material, wherein the second stress buffer layer contacts a sidewall and a top surface of the first region of the PPI structure;
an under-bump structure on the first region of the PPI structure, the second stress buffer layer having a continuous material composition from the first stress buffer layer to the under-bump structure; and
a bump contact on the under-bump structure.

US Pat. No. 10,510,720

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Siliconware Precision Ind...

1. An electronic package, comprising:a first substrate;
a first electronic component having a first surface and a second surface opposite to the first surface, the first electronic component being disposed on the first substrate through a plurality of conductive bumps formed on the first surface in a flip-chip manner, wherein the first electronic component is a semiconductor component;
a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the second surface of the first electronic component through a bonding layer, wherein the first conductive elements are different in structure from the second conductive elements, and the bonding layer is in direct contact with the first electronic component and the second substrate; and
a first encapsulant formed between the first substrate and the second substrate and encapsulating the first electronic component, the bonding layer, the first conductive elements and the second conductive elements, wherein the bonding layer is a stress-absorbing layer configured to absorb stresses of an upward pushing force generated by the first encapsulant for the second surface of the first electronic component.

US Pat. No. 10,510,705

SEMICONDUCTOR PACKAGE STRUCTURE HAVING A SECOND ENCAPSULANT EXTENDING IN A CAVITY DEFINED BY A FIRST ENCAPSULANT

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package structure, comprising:a first semiconductor die;
a second semiconductor die disposed on the first semiconductor die;
a plurality of conductive elements each comprising a first portion and a second portion, and disposed around the first semiconductor die and the second semiconductor die;
a first encapsulant surrounding the first semiconductor die and the respective first portions of the conductive elements; and
a second encapsulant covering a portion of a top portion of the first semiconductor die and surrounding the respective second portions of the conductive elements, wherein the second encapsulant directly contacts the first encapsulant, the first encapsulant defines a cavity to expose at least the portion of the top portion of the first semiconductor die, and the second encapsulant covers the first encapsulant and extends into the cavity.

US Pat. No. 10,510,704

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:a first die;
an encapsulant aside the first die, encapsulating sidewalls of the first die;
a first redistribution layer (RDL) structure on the first die and the encapsulant; and
a conductive terminal, electrically connected to first die through the RDL structure,
wherein the first RDL structure comprises a first polymer layer and a first RDL, the first polymer layer comprises a non-shrinkage material and a top surface of the first polymer layer is substantially flat,
wherein a portion of the first polymer layer is extending into the encapsulant and is surrounded by the encapsulant.

US Pat. No. 10,510,699

BOND STRUCTURES AND THE METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

16. A device comprising:a semiconductor substrate;
integrated circuit devices at a surface of the semiconductor substrate;
a metal pad over and electrically coupling to the integrated circuit devices, wherein the metal pad is configured to prohibit currents flowing through;
an etch stop layer over the metal pad;
a first bond pad overlapping the metal pad, wherein the first bond pad is electrically floating, and entireties of spaces between the first bond pad and the metal pad are free from conductive features therein;
a second bond pad configured to allow currents flowing through, wherein both the first bond pad and the second bond pad comprise bottom surfaces contacting the etch stop layer; and
a package component bonding to the first bond pad and the second bond pad.

US Pat. No. 10,510,695

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:a die on an adhesive layer;
an encapsulant, laterally encapsulating the die and laterally encapsulating the adhesive layer;
a redistribution layer (RDL) structure electrically connected to the die, wherein the RDL structure and the adhesive layer are disposed at opposite sides of the die, and the RDL structure comprises:
a first dielectric layer on the encapsulant and the die;
a first RDL embedded in the first dielectric layer and comprising a first via and a first trace connected to each other, wherein a top surface of the first RDL is coplanar with a top surface of the first dielectric layer;
a second dielectric layer on the first dielectric layer and the first RDL; and
a second RDL embedded in the second dielectric layer and comprising a second via and a second trace connected to each other, wherein a top surface of the second RDL is coplanar with a top surface of the second dielectric layer,
wherein the second via is stacked directly on the first via.

US Pat. No. 10,510,692

SEMICONDUCTOR DEVICE INCLUDING DUMMY CONDUCTIVE CELLS

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a plurality of metal layers comprising a plurality of empty areas and grouped into a plurality pairs of neighboring metal layers;
a plurality of first dummy conductive cells each formed in each of the empty areas in each of the plurality pairs of neighboring metal layers that is overlapped by another empty area or a line in the same pair of neighboring metal layers; and
a plurality groups of second dummy conductive cells, wherein each group of the second dummy conductive cells is formed in each of the empty areas in each of the plurality pairs of neighboring metal layers that is overlapped by a signal line in the same pair of neighboring metal layer.

US Pat. No. 10,510,690

WAFER LEVEL PACKAGE (WLP) AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:attaching a semiconductor device structure to a substrate, the semiconductor device structure comprising a chip structure, a conductive pad over the chip structure, a passivation layer over the conductive pad and the chip structure, a first protection layer over the passivation layer, and a post-passivation interconnect (PPI) pad extending through the first protection layer and the passivation layer, the PPI pad being electrically connected to the conductive pad;
forming an insulating layer surrounding the chip structure, the passivation layer, and the first protection layer;
forming a second protection layer over the insulating layer, the first protection layer, and the PPI pad;
etching the second protection layer to form first openings exposing top surfaces of the PPI pad;
forming a PPI structure in the first openings, the PPI structure being electrically connected to the PPI pad; and
forming a first moisture-resistant layer over the second protection layer and the PPI structure, the first moisture-resistant layer comprising a different material than the first protection layer and the second protection layer.

US Pat. No. 10,510,682

SEMICONDUCTOR DEVICE WITH SHIELD FOR ELECTROMAGNETIC INTERFERENCE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first die in a molding layer;
a first redistribution structure on a first side of the molding layer and electrically coupled to the first die;
a second redistribution structure on a second side of the molding layer opposing the first side;
a first conductive structure in the molding layer and laterally spaced apart from the first die, wherein the first conductive structure comprises:
a first dielectric region around the first die; and
a first conductive coating on opposing sidewalls of the first dielectric region, the first conductive coating physically contacting the molding layer; and
a via in the molding layer and electrically coupled to the first redistribution structure and the second redistribution structure, wherein the via comprises:
a second dielectric region; and
a second conductive coating on sidewalls of the second dielectric region, wherein the second conductive coating extends further from a center axis of the via than the second dielectric region, the center axis of the via being perpendicular to the first side of the molding layer.

US Pat. No. 10,510,676

SYSTEM AND METHOD FOR ALIGNED STITCHING

Taiwan Semiconductor Manu...

1. A method, comprising:depositing a first dielectric layer over a substrate;
depositing a first photoresist over the first dielectric layer;
exposing the first photoresist to a first light-exposure through a first lithographic mask;
after exposing the first photoresist to the first light-exposure, exposing the first photoresist to a second light-exposure through a second lithographic mask, wherein:
a first overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure;
the first overlap region is interposed between a first active signal region and a second active signal region;
the first active signal region and the second active signal region are disposed in a same die;
the first light-exposure is used to image the first active signal region; and
the second light-exposure is used to image the second active signal region; and
after the exposing the first photoresist to the second light-exposure, developing the first photoresist and patterning the first dielectric layer to form a first mask overlay alignment feature, the first mask overlay alignment feature disposed in the first overlap region.

US Pat. No. 10,510,672

SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a semiconductor package comprising:attaching a plurality of first conductive bumps to respective first conductive pads provided on an upper surface of a first substrate;
providing an interposer with a plurality of second conductive bumps attached to respective second conductive pads on a bottom surface of the interposer;
flip chip mounting a first semiconductor chip to the first substrate including electrically connecting the first semiconductor chip to third conductive pads provided on the upper surface of the first substrate;
forming an insulative mold layer on the upper surface of the first substrate to cover and surround the first conductive bumps, the insulative mold layer extending along sidewalls of the first semiconductor chip and having an upper surface at least as high as an upper surface of the first semiconductor chip;
etching the mold layer to provide a recess in the mold layer, to define upwardly extending protrusions formed of the etched mold layer and to expose the first conductive bumps;
placing the interposer on the first substrate so that each of the plurality of second conductive bumps on the bottom surface of the interposer are in contact with a corresponding one of the plurality of first conductive bumps to provide a plurality of contacting pairs of first conductive bumps and second conductive bumps, and so that the bottom surface of the interposer is in contact with upper surfaces of the protrusions;
performing a reflow process to merge each of the contacting pairs of the first conductive bumps and the second conductive bumps to form a plurality of conductive connection members, each conductive connection member extending between a corresponding first conductive pad on the upper surface of the first substrate and a corresponding second conductive pad on the bottom surface of the interposer;
flowing an under-fill resin in a space between the interposer and the first substrate to surround and encapsulate the conductive connection members; and
cutting the first substrate to form the semiconductor package, the semiconductor package including the first semiconductor chip and at least portions of the protrusions in contact with the interposer.

US Pat. No. 10,510,669

MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME

Intel Corporation, Santa...

1. A multi-chip package comprising:a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side, the third side constituting a portion of an outside perimeter of the substrate;
a first die attached to the first side of the substrate and a second die attached to the first side of the substrate;
a bridge within an opening of the substrate, the bridge attached to the first die and to the second die, wherein the bridge creates a connection between the first die and the second die; and
one or more wire bonds coupling the bridge die to the substrate.

US Pat. No. 10,510,665

LOW-K DIELECTRIC PORE SEALANT AND METAL-DIFFUSION BARRIER FORMED BY DOPING AND METHOD FOR FORMING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a low-k Inter Layer Dielectric (ILD) material comprising a trench structure or a via structure, the trench structure comprising at least one sidewall and a bottom and the via structure comprising at least one sidewall, the low-k ILD material comprising a low-k dielectric matrix having a first region with a first density and a second region with a second density, the first region of the low-k dielectric matrix having the first density being located in one or more regions of the low-k ILD material proximate to the at least one sidewall and the bottom of the trench structure or proximate to the at least one sidewall of the via structure, the second region of the low-k dielectric matrix having the second density being located distal to the one or more regions of the low-k ILD material proximate to the at least one sidewall and the bottom of the trench structure or proximate to the at least one sidewall of the via structure, the first density being greater than the second density, and the low-k dielectric matrix having the second density comprising a dielectric constant that is between 2.5 and 3.7; and
a conductive material disposed in the at least one trench structure or in the at least one via structure,
wherein the first region of the low-k dielectric matrix is interposed between the conductive material and the second region of the low-k dielectric matrix, and
wherein pores in the low-k dielectric matrix comprising the first density are at least partially sealed in comparison to pores in the low-k dielectric matrix comprising the second density.

US Pat. No. 10,510,660

SEMICONDUCTOR PACKAGE DEVICES INTEGRATED WITH INDUCTOR

TAIWAN SEMICONDUCTOR MANU...

1. An inductor structure, comprising:a first carrier having a first surface;
a first conductive pattern on the first surface of the first carrier;
a second carrier at one edge of the first carrier, the second carrier having a second surface substantially perpendicular to the first surface of the first carrier; and
a second conductive pattern on the second surface of the second carrier,
wherein the second conductive pattern is electrically connected with the first conductive pattern.

US Pat. No. 10,510,659

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

Invensas Corporation, Sa...

1. A microelectronic package, comprising:first conductive elements, including a first trace, obtained from a same conductive layer located on a lower side of the microelectronic package;
wire bond wires connected to and extending away from upper surfaces of the first conductive elements;
a first microelectronic component coupled with a first attachment layer to the first trace;
a first conductive via in the first attachment layer and interconnecting the first trace and a first contact structure of the first microelectronic component;
a second microelectronic component coupled to the first microelectronic component with a second attachment layer;
second conductive elements, including a second trace, respectively connected to upper surfaces of the wire bond wires; and
a second conductive via in a dielectric layer and interconnecting the second trace and a second contact structure of the second microelectronic component.

US Pat. No. 10,510,643

SEMICONDUCTOR PACKAGE WITH LEAD FRAME AND RECESSED SOLDER TERMINALS

TEXAS INSTRUMENTS INCORPO...

17. A semiconductor device comprising:a lead frame including a die attach pad, the die attach pad including a first surface and an opposite second surface;
a semiconductor chip attached to the die attach pad and electrically connected to a plurality of leads, each of the plurality of leads including a first lead surface, a second lead surface opposite to the first lead surface, a third lead surface and a fourth lead surface opposite to the third lead surface, wherein a plane along the third lead surface is below a plane along the first lead surface, and a plane along the fourth lead surface is below a plane along the second lead surface, the semiconductor chip including a third surface and an opposite fourth surface, the opposite fourth surface of the semiconductor chip attached to the first surface of the die attach pad;
a packaging compound covering portions of the semiconductor chip, the die attach pad and the plurality of leads forming a package, the opposite second surface of the die attach pad exposed from the package on a package surface, the opposite second surface being coplanar with the package surface; and
a plurality of recess holes having a conductive adhesive, each of the plurality of recess holes extending from a first surface of each of the plurality of leads to the package surface;
wherein a first distance between a plane along the package surface and a plane along the opposite fourth surface of the semiconductor chip is less than a second distance between the plane along the package surface and the plane along the third lead surface of each of the plurality of leads.

US Pat. No. 10,510,641

SEMICONDUCTOR DEVICE HAVING BACKSIDE INTERCONNECT STRUCTURE ON THROUGH SUBSTRATE VIA AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a semiconductor substrate having a frontside and a backside, the frontside having a transistor formed thereon and the backside being opposite the frontside;
a through-substrate via extending from the frontside to the backside of the semiconductor substrate and comprising a convex portion protruding from the backside of the semiconductor substrate;
an isolation film comprising a first portion formed on a sidewall of the convex portion of the through-substrate via and a second portion formed on the backside of the semiconductor substrate, wherein the top of the convex portion of the through-substrate via is higher than a top surface of the second portion of the isolation film;
a conductive layer comprising a first portion formed on a top of the convex portion of the through-substrate via and a second portion formed on the second portion of the isolation film; and
a passivation layer partially covering a topmost surface of the conductive layer, the passivation layer including an opening therein that at least partially exposes the first portion of the conductive layer.

US Pat. No. 10,510,639

VEHICLE CONTROL DEVICE

AISIN AW CO., LTD., Anjo...

1. A vehicle control device comprising:a housing mounted on a vehicle and made of metal;
a substrate housed in the housing and having a mounting surface that faces an inner surface of the housing;
an electronic component mounted on the mounting surface; and
a heat radiation material disposed between the electronic component and the inner surface of the housing, wherein
the electronic component has a contact portion that contacts the heat radiation material and a non-contact portion that does not contact the heat radiation material, the contact portion and the non-contact portion being portions of the electronic component on a side facing the inner surface of the housing:
the electronic component has a first circuit portion and a second circuit portion;
the first circuit portion radiates a larger amount of noise than an amount of noise radiated from the second circuit portion, and is superposed on the non-contact portion as seen in a direction that is perpendicular to the mounting surface; and
a distance between the non-contact portion and the inner surface of the housing in a direction that is perpendicular to the mounting surface is longer than a distance between the contact portion and the inner surface of the housing in the perpendicular direction.

US Pat. No. 10,510,637

DEVICES AND METHODS FOR HEAT DISSIPATION OF SEMICONDUCTOR INTEGRATED CIRCUITS

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:an electronic component having a top surface, a bottom surface, and two end portions;
a plurality of contacts disposed on the top surface, wherein the plurality of contacts includes
two end contacts disposed at the two end portions respectively, and
at least one intermediate contact disposed between the two end contacts; and
a plurality of metal nodes disposed on the plurality of contacts, wherein the plurality of metal nodes includes
two end metal nodes disposed on the two end contacts respectively, and
at least one intermediate metal node disposed on the at least one intermediate contact, wherein the at least one intermediate metal node further comprises a plurality of metal layers and at least one vertical interconnect access (via) that thermally couples adjacent metal layers in the plurality of metal layers.

US Pat. No. 10,510,635

INTEGRATED CIRCUIT PACKAGES AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A chip comprising:a substrate;
a metal pad over the substrate;
a polymer layer over the metal pad, wherein the polymer layer extends to an edge of the chip, and an edge of the polymer layer forms a part of the edge of the chip;
an electrical connector over the polymer layer; and
a molding compound, wherein a lower portion of the electrical connector is in the molding compound, and wherein the molding compound comprises a top surface comprising:
a first horizontal portion substantially perpendicular to the edge of the chip; and
a slant sidewall portion, wherein the first horizontal portion is connected to a first end of the slant sidewall portion, and the first horizontal portion is spaced apart from the edge of the chip by the slant sidewall portion, and wherein the slant sidewall portion is neither perpendicular to nor parallel to the edge of the chip.

US Pat. No. 10,510,633

PACKAGE AND PRINTED CIRCUIT BOARD ATTACHMENT

Taiwan Semiconductor Manu...

1. A method comprising:disposing solder on first pads on a side of a package, the package including one or more dies; and
attaching pins on second pads on the side of the package, wherein the first pads and the second pads together form a matrix on the side of the package, the second pads being in outer rows, outer columns, or a combination thereof of the matrix.

US Pat. No. 10,510,628

CONTACT PADS FOR ELECTRICAL MODULE ASSEMBLY WITH MULTIDIMENSIONAL TRANSDUCER ARRAYS

Siemens Medical Solutions...

1. A multidimensional transducer array system, the system comprising:a first printed circuit board having a first surface with ends of traces, the ends of the traces electrically connecting to metallic contact pads separated by kerfs in the first surface;
a multidimensional transducer array having first elements in electrical contact with the metallic contact pads, wherein the kerfs in the first surface are patterned to match kerfs separating the first elements of the multidimensional array; and
an integrated circuit connected with the first printed circuit board such that signals on the contact pads are provided at the integrated circuit by the traces, the integrated circuit connected on a second surface of the first printed circuit board different than the first surface.

US Pat. No. 10,510,621

METHODS FOR THRESHOLD VOLTAGE TUNING AND STRUCTURES FORMED THEREBY

Taiwan Semiconductor Manu...

1. A method for semiconductor processing, the method comprising:depositing a gate dielectric layer over a first active area in a first device region of a substrate and a second active area in a second device region of the substrate;
depositing a first blocking layer over the gate dielectric layer in the second device region;
depositing a first dipole layer over the gate dielectric layer in the first device region, wherein the first dipole layer is further deposited over the first blocking layer in the second device region, wherein the first blocking layer is not disposed between the first dipole layer and the gate dielectric layer in the first device region; and
diffusing a dipole dopant species from the first dipole layer into the gate dielectric layer in the first device region and diffusing the dipole dopant species from the first dipole layer into the gate dielectric layer in the second device region, wherein after diffusing the dipole dopant species from the first dipole layer in the first device region and the second device region, a concentration of the dipole dopant species in the gate dielectric layer in the first device region is greater than a concentration of the dipole dopant species in the gate dielectric layer in the second device region.

US Pat. No. 10,510,620

WORK FUNCTION METAL PATTERNING FOR N-P SPACE BETWEEN ACTIVE NANOSTRUCTURES

GLOBALFOUNDRIES, INC., G...

1. A field effect transistor (FET) structure, comprising:a first type field effect transistor having: a first active nanostructure on a substrate, a gate having a high dielectric constant (high-K) layer and a first work function metal (WFM) surrounding the first active nanostructure, and a source/drain (S/D) region at each of opposing ends of the first active nanostructure;
a second type field effect transistor having: a second active nanostructure on the substrate adjacent to the first active nanostructure and separated by a space, the second FET further including a gate having the first WFM and a second work function metal (WFM) surrounding the second active nanostructure, and a source/drain (S/D) region at each of opposing ends of the second active nanostructure, the second WFM being different than the first WFM; and
an isolation pillar positioned between the first and second active nanostructures in the space,
wherein one of the first and second WFMs extends along a sidewall of the isolation pillar but not over a part of the isolation pillar.

US Pat. No. 10,510,613

CONTACT STRUCTURES

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:an active gate structure composed of conductive material located between sidewall material;
a source/drain region on sides of the active gate structure;
an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and
a first contact structure in electrical contact with the conductive material of the active gate structure, the first contact structure being located between the sidewall material and between the upper sidewall material;
contact material in electrical contact with the source/drain region, the contact material being separated from active gate structure by at least the sidewall material;
a second contact structure in electrical and direct physical contact with the contact material of the source/drain region,
wherein:
the sidewall material is a low-k dielectric material and the upper sidewall material has an etch selectivity different than the low-k dielectric material;
the upper sidewall material separates the first contact structure for the active gate structure from the second contact structure of the source/drain region of the active gate structure; and
a lower portion of the second contact structure of the source/drain region is located between the sidewall material and an upper portion of the second contact structure of the source/drain region is located between and in direct physical contact with the upper sidewall material.

US Pat. No. 10,510,608

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A method for manufacturing a semiconductor structure, the method comprising:forming an insulating layer covering a first fin and a second fin;
forming a mask layer over the insulating layer and covering the first fin and the second fin;
patterning the mask layer to form a gap between the first fin and the second fin;
forming an insulating structure in the gap, wherein the insulating structure is formed over a first portion of the insulating layer;
after forming the insulating structure, removing the mask layer, wherein removing the mask layer includes removing a first portion of the mask layer and a second portion of the insulating layer;
after removing the mask layer, forming a first dummy gate and a second dummy gate at the opposite sides of the insulating structure, wherein the first dummy gate and the second dummy gate are, respectively, at least partially present on the first fin and the second fin;
removing the first dummy gate and the second dummy gate; and
forming first and second gates at opposite sides of the insulating structure, wherein the first and second gates are respectively at least partially present on the first and second fins.

US Pat. No. 10,510,605

SEMICONDUCTOR DIE SINGULATION AND STRUCTURES FORMED THEREBY

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor die, wherein the semiconductor die comprises:
a semiconductor substrate;
a plurality of dielectric layers on the semiconductor substrate, a first dielectric layer of the plurality of dielectric layers forming an interface with the semiconductor substrate;
a first sidewall provided by the semiconductor substrate;
a second sidewall below the first sidewall and disposed on a same side of the semiconductor die as the first sidewall, wherein the first sidewall is spaced laterally apart from the second sidewall, and wherein a material of the second sidewall is a material of a recast region, and wherein the recast region comprises a material of the plurality of dielectric layers; and
an underfill extending along the second sidewall of the semiconductor die and below the semiconductor die.

US Pat. No. 10,510,601

METHOD FOR REDUCING METAL PLUG CORROSION AND DEVICE

Taiwan Semiconductor Manu...

1. A method comprising:forming a transistor comprising:
forming a gate dielectric on a semiconductor region;
forming a gate electrode over the gate dielectric; and
forming a source/drain region extending into the semiconductor region;
forming a source/drain contact plug over and electrically coupled to the source/drain region;
forming a gate contact plug over and electrically coupled to the gate electrode, wherein forming at least one of the source/drain contact plug or the gate contact plug comprises a CMP operation; and
during the forming of the source/drain contact plug or gate contact plug, exposing at least one of the source/drain contact plug or the gate contact plug to a metal ion source solution, wherein a constituent metal of a metal ion in the metal ion source solution and a constituent metal of the at least one of the source/drain contact plug or gate contact plug are the same, and
minimizing a metal recess of the least one of the source/drain contact plug or the gate contact plug to a depth of less than two nm measured from a top surface of a dielectric layer adjacent to a respective contact plug surface while maintaining a CMP removal rate of the CMP operation greater than 30 nm/minute during formation of the respective contact plug.

US Pat. No. 10,510,595

INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, the method comprising:attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil;
forming a conductive pillar on a first side of the metal foil distal to the carrier;
attaching a semiconductor die to the first side of the metal foil;
after attaching the semiconductor die, performing an etching process, wherein the etching process reduces a width of the conductive pillar, wherein the etching process removes a portion of the metal foil disposed laterally between the conductive pillar and the semiconductor die, and wherein a remaining portion of the metal foil disposed between the semiconductor die and the carrier has a width that is smaller than a width of the semiconductor die;
after performing the etching process, forming a molding material around the semiconductor die and the conductive pillar; and
forming a redistribution structure over the molding material.

US Pat. No. 10,510,590

LOW RESISTIVITY FILMS CONTAINING MOLYBDENUM

Lam Research Corporation,...

1. A method comprising:depositing a tungsten (W)-containing layer on a substrate by reacting a W-containing precursor with a reducing agent, wherein the reducing agent is a silicon (Si)-containing compound or a boron (B)-containing compound; and
depositing a molybdenum (Mo)-containing layer on the W-containing layer, wherein the Mo-containing layer is deposited by exposing the W-containing layer to a reducing agent and a Mo-containing precursor and wherein the substrate is exposed to the reducing agent at first substrate temperature and is exposed to the Mo-containing precursor at a second substrate temperature, wherein the first substrate temperature is less than the second substrate temperature.

US Pat. No. 10,510,585

MULTI-PATTERNING TO FORM VIAS WITH STRAIGHT PROFILES

Taiwan Semiconductor Manu...

17. A method comprising:forming a first hard mask layer;
forming a carbon-containing layer over the first hard mask layer;
forming a second hard mask layer over the carbon-containing layer;
performing a first patterning to form a first opening in the second hard mask layer and the carbon-containing layer;
performing a second patterning to forming a second opening in the second hard mask layer and the carbon-containing layer;
using the second hard mask layer and the carbon-containing layer as a first etching mask to simultaneously extend the first opening and the second opening into the first hard mask layer; and
extending the first opening and the second opening in the first hard mask layer into a photo resist.

US Pat. No. 10,510,570

SYSTEMS, APPARATUS, AND METHODS FOR PURGING A SUBSTRATE CARRIER AT A FACTORY INTERFACE

Applied Materials, Inc., ...

1. A kit for purging a substrate carrier at a load port of a factory interface (FI) or equipment front end module (EFEM), the kit comprising:a frame configured to sit proximate to a load port door without interfering with operation of the FI or an EFEM robot;
one or more inter-substrate nozzle arrays supported by the frame and configured to spray gas into a substrate carrier, wherein the one or more inter-substrate nozzle arrays have an adjustable aiming angle; and
one or more curtain nozzle arrays supported by the frame and configured to spray gas across an opening of the substrate carrier.

US Pat. No. 10,510,569

PATTERN FORMING APPARATUS AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A pattern forming apparatus comprising:a processing unit that applies processing to a substrate having a mark provided on a front surface of the substrate;
a transfer unit that transfers the substrate into the processing unit;
a placing table on which the substrate transferred into the processing unit is placed;
a first imaging element that is provided at a position included in the placing table and overlapping with an edge of the substrate, and captures an image of the substrate from a back side of the substrate to detect a position of the edge of the substrate;
a second imaging element that captures an image of the mark of the substrate on the placing table from a front side of the substrate to detect a position of the mark; and
a control unit that calculates, before performing alignment of the position of the substrate with the position of the mark detected by the second imaging element, a positional displacement amount of the substrate from the position of the edge of the substrate detected by the first imaging element, and controls the placing table based on the positional displacement amount of the substrate to correct the position of the substrate.

US Pat. No. 10,510,568

CORROSION INHIBITOR INJECTION APPARATUS

RKD Engineering Corporati...

1. An inhibitor solution injector system for an IC decapsulation apparatus, comprising:a first source reservoir containing inhibitor solution;
a second source reservoir containing etchant solution;
an injection coupling having an etchant input passage intersecting at an angle approximately 135 degrees with an etchant output passage, and an inhibitor input passage joining the etchant passages at the intersection of the etchant input passage and the etchant output passage;
an etchant pump coupled to the second source reservoir, pumping etchant to the etchant input passage and through the etchant output passage;
an inhibitor injection apparatus comprising a motor-driven syringe coupled to the first source reservoir and to the inhibitor input passage; and
control circuitry controlling the motor-driven syringe of the fluid injection apparatus;
wherein the etchant pump urges etchant from the second source reservoir through the etchant input and output passages, and the motor-driven syringe of the inhibitor injection apparatus draws inhibitor from the first source reservoir, and the control circuitry controls the motor-driven syringe to inject the inhibitor into the etchant passages at the point of intersection of the etchant input passage and the etchant output passage, the acute change in direction in the etchant passages causing turbulence enhancing efficiency of mixing the etchant and the inhibitor.

US Pat. No. 10,510,567

INTEGRATED SUBSTRATE TEMPERATURE MEASUREMENT ON HIGH TEMPERATURE CERAMIC HEATER

APPLIED MATERIALS, INC., ...

8. A processing chamber, comprising:a chamber body defining a processing volume; and
a substrate support assembly disposed in the processing volume, the substrate support assembly comprising:
a support shaft;
a substrate support disposed on the support shaft;
a substrate temperature monitoring system for measuring a temperature of a substrate to be disposed on the substrate support, comprising:
an optical fiber tube;
a light guide coupled to the optical fiber tube, wherein the light guide comprises a sapphire tube having a length of at least 400 mm and an inner diameter of at least about 40 mm, and at least a portion of the light guide is disposed in an opening extending through the support shaft and into the substrate support; and
a cooling assembly disposed about a junction of the optical fiber tube and the light guide, wherein the cooling assembly maintains the optical fiber tube at a temperature of less than about 100° C. during substrate processing.

US Pat. No. 10,510,562

STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a die having:
contact pads thereon; and
a routing structure over the contact pads, the routing structure comprising:
a passivation layer over the contact pads;
a buffer layer over the contact pads and the passivation layer;
first conductive pillars over a first set of the contact pads, the first conductive pillars having first portions and second portions, the first portions extending through the passivation layer and the buffer layer, the first portions contacting the first set of the contact pads, the second portions extending over the buffer layer;
conductive lines over the buffer layer, the conductive lines connecting pairs of the first conductive pillars; and
a protective layer over the buffer layer and the passivation layer, a portion of the protective layer being between one of the first conductive pillars and the one of the conductive lines, the portion of the protective layer contacting the passivation layer; and
an external connector structure over the routing structure, the routing structure electrically coupling the contact pads to the external connector structure.

US Pat. No. 10,510,558

ELECTRONIC DEVICE, THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

BOE Technology Group Co.,...

1. A manufacturing method of an electronic device, comprising:forming a metallic structure on a base substrate;
forming an oxygen-free insulating layer on the metallic structure and the base substrate; and
forming an insulating protective layer on the oxygen-free insulating layer,
wherein the oxygen-free insulating layer is made from silane; and the manufacturing method of the electronic device further comprises:
forming a semiconductor layer on a side of the metallic structure away from the oxygen-free insulating layer; and
changing a part of the semiconductor layer making contact with the oxygen-free insulating layer into a conductor by hydrogen released from the silane in the process of forming the oxygen-free insulating layer.

US Pat. No. 10,510,552

HARD MASK REMOVAL METHOD

Taiwan Semiconductor Manf...

1. A method of removing a hard mask, the method comprising:patterning gate stacks on a substrate, wherein the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer, wherein the gate stacks are patterned in an isolated region and a dense region, and wherein gate stacks of the isolated region have lower thicknesses than gate stacks of the dense region;
depositing a dielectric layer directly on exposed portions of the substrate between the gate stacks and on the gate stacks, wherein after the dielectric layer is deposited the dielectric layer has a first thickness in the isolated region and a second thickness in the dense region, the first thickness is greater than the second thickness, the first thickness is between a first surface of the dielectric layer that is closest to the substrate in the isolated region and a second surface of the dielectric layer that is farthest from the substrate in the isolated region, the second thickness is between a third surface of the dielectric layer that is closest to the substrate in the dense region and a fourth surface of the dielectric layer that is farthest from the substrate in the dense region, and the first surface of the dielectric layer is level with the third surface of the dielectric layer;
planarizing a first portion of the dielectric layer by a first chemical mechanical polishing (CMP) process, wherein after the first CMP process a difference in the first thickness and the second thickness has been reduced; and
removing the hard mask and a second portion of the dielectric layer by a second CMP process, wherein a thickness difference between the gate stacks in the isolated region and the gate stacks in the dense region is less than 30 ? after the removing of the hard mask and the second portion.

US Pat. No. 10,510,544

NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a non-volatile memory semiconductor device, comprising:forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate,
forming a conductive layer over the plurality of memory cells;
forming a first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise over the plurality of memory cells;
performing a planarization operation on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer;
after the planarization operation, forming a hard mask layer on the plurality of memory cells; and
after forming the hard mask layer on the plurality of memory cells, completely removing portions of a lower region of the conductive layer between the memory cells.

US Pat. No. 10,510,542

GATE ELECTRODES WITH NOTCHES AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:forming a gate electrode layer over a semiconductor substrate;
forming a hard mask over the gate electrode layer;
patterning the hard mask to form an opening in the hard mask;
performing a first etching step using the patterned hard mask as a first etching mask to form a notch in a first portion of the gate electrode layer;
forming a patterned photo resist, wherein the patterned photo resist extends into a first portion of the notch, and a second portion of the notch is exposed through the patterned photo resist; and
performing a second etching step using the patterned photo resist as a second etching mask, wherein the gate electrode layer is further etched in the second etching step to form a gate electrode, wherein the gate electrode is a part of a Metal-Oxide-Semiconductor (MOS) device, and an additional portion of the notch remains with the gate electrode after the second etching step.

US Pat. No. 10,510,539

FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH CONTROLLED END-TO-END CRITICAL DIMENSION AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor device structure, comprising:providing a substrate;
forming a first fin structure and a second fin structure extending from the substrate by etching a portion of the substrate;
forming a polysilicon layer and a masking layer over the first fin structure and the second fin structure;
patterning the masking layer to form a first opening in the masking layer, wherein the first opening has a first dimension;
lining the first opening to form a second opening, wherein the second opening has a second dimension and the second dimension is smaller than the first dimension; and
patterning the polysilicon layer through the second opening to form an end-to-end gap between the first fin structure and the second fin structure.

US Pat. No. 10,510,536

METHOD OF DEPOSITING A CO-DOPED POLYSILICON FILM ON A SURFACE OF A SUBSTRATE WITHIN A REACTION CHAMBER

ASM IP Holding B.V., Alm...

1. A method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber, the method comprising:heating the substrate to a deposition temperature of less than 550° C.;
simultaneously contacting the substrate with a silicon precursor, a n-type dopant precursor, and a p-type dopant precursor; and
depositing the co-doped polysilicon film on the surface of the substrate,
wherein the deposited co-doped polysilicon film has a p-type dopant concentration greater than 1×1018/cm3 and an n-type dopant concentration greater than 1×1018/cm3.

US Pat. No. 10,510,535

OPTOELECTRONIC DEVICE COMPRISING THREE-DIMENSIONAL SEMICONDUCTOR ELEMENTS, AND METHOD FOR MANUFACTURING SAID DEVICE

Aledia, Grenoble (FR)

1. A method of manufacturing an optoelectronic device comprising wire-shaped, conical, or frustoconical semiconductor elements mainly comprising a III-V compound, each semiconductor element extending along an axis and comprising a portion having its lateral surfaces covered with a shell comprising at least one active area, wherein the portions are formed by continuous growth in a reactor and wherein the temperature in the reactor varies, along the continuous growth of the portions, uninterruptedly from a first temperature value which promotes the growth of first crystallographic planes perpendicular to said axis to a second temperature value, lower than the first temperature value, which promotes the growth of second crystallographic planes parallel to said axis.

US Pat. No. 10,510,529

FORMATION OF SIOCN THIN FILMS

ASM IP Holding B.V., Alm...

1. A plasma enhanced atomic layer deposition (PEALD) method of forming a thin film comprising silicon, oxygen and carbon on a substrate that comprises a material that would be oxidized by exposure to oxygen plasma, wherein the PEALD method comprises at least one deposition cycle comprising:contacting a surface of the substrate with a vapor phase silicon precursor to thereby adsorb a silicon species on the surface of the substrate; and
contacting the adsorbed silicon species with at least one reactive species generated by plasma formed from a gas that does not comprise oxygen,
wherein the silicon precursor comprises a silicon atom, an alkoxide group bonded to the silicon atom and a ligand comprising an amino group bonded to the silicon atom through a carbon, and
wherein the substrate is not contacted with a reactive species generated by a plasma from oxygen in the at least one deposition cycle.

US Pat. No. 10,510,524

ION TRAP MASS SPECTROMETRY DEVICE AND MASS SPECTROMETRY METHOD USING SAID DEVICE

SHIMADZU CORPORATION, Ky...

1. A mass spectrometric method using an ion trap mass spectrometer in which an ion of sample origin is captured within an inner space of an ion trap formed by a plurality of electrodes, the ion is dissociated by a predetermined ion dissociation technique, and thereby generated product ions are ejected from the ion trap and detected, the mass spectrometric method comprising:a) an ion selection step in which ions other than a target ion having a specific mass-to-charge ratio are ejected from the ion trap, among ions captured within the ion trap;
b) an ion dissociation-ejection step in which an ion-dissociating operation and an ion-ejecting operation are repeatedly performed multiple times, where the ion-dissociating operation includes dissociating, by the predetermined dissociation technique, the target ion maintained within the ion trap by the ion selection step, and the ion-ejecting operation includes ejecting ions having smaller mass-to-charge ratios than the mass-to-charge ratio of the target ion among the ions captured within the ion trap after the ion-dissociating operation while performing a mass scan in a direction in which the mass-to-charge ratio increases from a low mass-to-charge-ratio side, or in an opposite direction; and
c) a mass spectrum creation step in which a mass spectrum is created based on a result of detection of the ions ejected from the ion trap during the ion-ejecting operation performed multiple times in the ion dissociation-ejection step.

US Pat. No. 10,510,522

MASS SPECTROMETRY USING PLASMA ION SOURCE

Agilent Technologies, Inc...

1. A method of correcting spectral interference due to a divalent ion of an interfering element on a measurement ion of an analysis element in a sample measured by a mass spectrometer using a plasma ion source, where at least one type of interfering element having three different isotopes is present in the sample, the three different isotopes being a first isotope having an odd mass number, a second isotope having an odd mass number, and a third isotope, the method comprising:using, from the at least one type of interfering element, a measurement value of ionic strength of a divalent ion of the first isotope in the sample and a measurement value of ionic strength of a divalent ion of the second isotope in the sample to calculate an interference amount of spectral interference due to a divalent ion of the third isotope on the measurement ion of the analysis element; and
subtracting the interference amount calculated for the at least one type of interfering element from a measurement value of ionic strength at a mass-to-charge ratio of the measurement ion of the analysis element in the sample measured by the mass spectrometer to seek a corrected value of ionic strength at the mass-to-charge ratio of the measurement ion of the analysis element.

US Pat. No. 10,510,516

MOVING FOCUS RING FOR PLASMA ETCHER

Taiwan Semiconductor Manu...

1. A method comprising:placing a wafer within a plasma chamber;
etching a first layer of the wafer to form a recess in the first layer using a first plasma process, wherein the first layer is a single layer, and the recess exposes first sidewalls of the first layer; and
moving a focus ring within the plasma chamber from a first vertical position relative to the wafer to a second vertical position relative to the wafer during the first plasma process, wherein the first vertical position and the second vertical position are different plasma etch positions, the first vertical position corresponds to a first etch rate for the first plasma process, and the second vertical position corresponds to a second etch rate for the first plasma process different from the first etch rate, wherein moving the focus ring comprises moving part of a focus ring holder that supports the focus ring, wherein moving the focus ring during the first plasma process produces a non-liner sidewall profile for the first sidewalls of the first layer, wherein the first sidewalls of the first layer comprises a first portion and a second portion underlying the first portion, wherein a first distance between first opposing sidewalls of the first portion decreases continuously along a first direction from a top of the recess toward a bottom of the recess, and a second distance between second opposing sidewalls of the second portion increases continuously along the first direction.

US Pat. No. 10,510,515

PROCESSING TOOL WITH ELECTRICALLY SWITCHED ELECTRODE ASSEMBLY

Applied Materials, Inc., ...

1. A plasma reactor comprising:a chamber body having an interior space that provides a plasma chamber;
a gas distributor to deliver a processing gas to the plasma chamber;
a pump coupled to the plasma chamber to evacuate the chamber;
a workpiece support to hold a workpiece;
an intra-chamber electrode assembly comprising a plurality of filaments extending laterally through the plasma chamber between a ceiling of the plasma chamber and the workpiece support, each filament including a conductor surrounded by a cylindrical insulating shell, wherein the plurality of filaments includes a first multiplicity of filaments and a second multiplicity of filaments arranged in an alternating pattern with the first multiplicity of filaments,
a first bus coupled to the first multiplicity of filaments and a second bus coupled to the second multiplicity of filaments;
an RF power source to apply an RF signal the intra-chamber electrode assembly; and
at least one RF switch configured to controllably electrically couple and decouple the first bus from one of i) ground, ii) the RF power source, or iii) the second bus.

US Pat. No. 10,510,514

GAS SUPPLY MECHANISM AND SEMICONDUCTOR MANUFACTURING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A gas supply mechanism for supplying a gas to a semiconductor manufacturing apparatus, comprising:a pipe connecting a gas source and the semiconductor manufacturing apparatus; and
a valve provided on the pipe, wherein
the valve includes
a plate rotatable about an axis, the axis extending in a plate thickness direction, and
a housing provided along the plate without contacting the plate to accommodate the plate, the housing providing a gas supply path along with the pipe,
a through hole is formed in the plate, the through hole penetrating the plate at a position on a circle which extends around the axis and intersects the gas supply path, and
the through hole is configured to move, by changing a rotation angle of the plate, between a first position, which overlaps with the gas supply path when viewed from a direction along the axis, and a second position, which does not overlap with the gas supply path when viewed from a direction along the axis.

US Pat. No. 10,510,512

METHODS AND SYSTEMS FOR CONTROLLING PLASMA PERFORMANCE

Tokyo Electron Limited, ...

1. A method of controlling plasma performance in a system for treating a substrate, the method comprising:supplying power at a first set of power parameters to a plasma chamber;
forming plasma within the plasma chamber using the first set of power parameters;
measuring power coupling to the plasma at the first set of power parameters;
supplying power at a second set of power parameters to the plasma chamber;
measuring power coupling to the plasma at the second set of power parameters to the plasma; and
adjusting the first set of power parameters based, at least in part, on the measuring of the power coupling at the second set of power parameters, wherein measuring the power coupling to the plasma includes at least measuring a resonant power and an intensity of power provided to the plasma chamber.

US Pat. No. 10,510,508

CHARGED PARTICLE BEAM APPARATUS

HITACHI HIGH-TECH SCIENCE...

1. A charged particle beam apparatus comprising:a sample stage on which a sample is placed;
a sample chamber receiving the sample stage therein;
a charged particle beam column irradiating the sample with a charged particle beam;
a displacement member including an open/close portion displaceable between an insertion position, which is between a beam emitting end portion of the charged particle beam column and the sample stage so as to block an opening of the beam emitting end portion, and a withdrawal position which is away from the insertion position, and a contact portion provided at a contact position capable of contacting the sample before the beam emitting end portion during operation of the sample stage and configured so as not to interfere with the charged particle beam from the charged particle beam column with which the sample is irradiated;
driving means for displacing the displacement member; and
detecting means for detecting whether the sample is in contact with the contact portion.

US Pat. No. 10,510,505

FUSE UNIT AND METHOD OF MANUFACTURING FUSE UNIT

PACIFIC ENGINEERING CORPO...

3. A fuse unit which comprises a bus bar comprising a battery terminal, a fuse connection terminal, and an external connection terminal, wherein the bus bar and a resin covering body are integrated, the fuse connection terminal comprising an input side tuning fork terminal connected to the battery terminal and an output side tuning fork terminal connected to the external connection terminal, the input side tuning fork terminal and the output side tuning fork terminal once connected via a joining portion such that they face each other, the resin covering body comprising a cutting window which is provided between a base end portion of the input side tuning fork terminal and a base end portion of the output side tuning fork terminal and such that the cutting window only exposes the joining portion to the outside, and the joining portion having been cut and removed so as to separate the input side tuning fork terminal and the output side tuning fork terminal.

US Pat. No. 10,510,494

SUPERCAPACITORS WITH ORIENTED CARBON NANOTUBES AND METHOD OF PRODUCING THEM

DEUTSCHES ZENTRUM FUR LUF...

1. A method of manufacturing an electrochemical storage device, the method comprisingapplying a conductive contact layer to a non-conductive substrate,
segmentally removing the conductive contact layer from the non-conductive substrate, thus forming an electrode basis from one partial area of the contact layer and a counter electrode basis from another partial area of the contact layer, the electrode basis and the counter electrode basis extending in a common contact plane,
forming an electrode surface-enlarging structure on the electrode basis, the electrode basis and the electrode surface-enlarging structure forming an electrode,
forming a counter electrode surface-enlarging structure on the counter electrode basis, the counter electrode basis and the counter electrode surface-enlarging structure forming a counter electrode, and
arranging an electrolyte between the electrode and the counter electrode.

US Pat. No. 10,510,490

MULTILAYER CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component, comprising:a ceramic body including a dielectric layer and first and second internal electrodes stacked to be alternately exposed from one end surface and another end surface in a length direction with the dielectric layer disposed therebetween; and
first and second external electrodes disposed on the one end surface and the another end surface of the ceramic body and connected to the first and second internal electrodes, respectively,
wherein the ceramic body includes an area of overlap in a thickness direction of the first and second internal electrodes, and margin regions disposed on one side and another side in a width direction of the area of overlap, respectively,
the margin regions in the width direction include a phosphoric acid-based second phase, and
the phosphoric acid-based second phase has an acicular shape or a rhomboid shape.

US Pat. No. 10,510,487

MULTI-LAYER CERAMIC ELECTRONIC COMPONENT AND METHOD OF PRODUCING THE SAME

TAIYO YUDEN CO., LTD., T...

1. A multi-layer ceramic electronic component, comprising:a multi-layer chip including
ceramic layers laminated in a first direction,
internal electrodes disposed between the ceramic layers,
a plurality of pores respectively formed at end portions of the internal electrodes in a second direction orthogonal to the first direction, and
a side surface that is orthogonal to the second direction and that includes a first area and a second area; and
a side margin that covers the side surface of the multi-layer chip,
wherein the plurality of pores include a first pore corresponding to the first area of the side surface and a second pore corresponding to the second area of the side surface,
wherein the second pore has a larger dimension than the first pore,
wherein each pore of the plurality of pores includes an open space between the side margin and the end portion of the respective internal electrode at which it is formed, and
wherein the first area and the second area each form a predetermined pattern.

US Pat. No. 10,510,449

EXPERT OPINION CROWDSOURCING

MERGE HEALTHCARE SOLUTION...

1. A computer-implemented method comprising:under direction of one or more hardware processors configured with specific software instructions,
receiving a medical image series including one or more medical images;
providing a user interface to a user, the user interface configured to allow the user to set preferences for selection of one or more reviewers of the medical image series, the preferences including:
first preferences identifying a first medical specialty and a first minimum quantity of reviewers having the first medical specialty;
second preferences identifying a second medical specialty and a second minimum quantity of reviewers having the second medical specialty; and
third preferences indicating a criteria regarding one or more of:
whether reviewers offer availability to be contacted directly by the user;
whether reviewers offer availability to review the medical image series as part of at least one of: a legal investigation, an insurance investigation, a consultation with a doctor, or a request of a patient;
a minimum and/or maximum quantity of reviewers to be selected to review the medical image series;
a minimum and/or maximum quantity of reviewers permitted to provide review information; and/or
a minimum average user feedback required for reviewers to be selected for review of the medical image series;
receiving, via the internet, the preferences provided by the user;
automatically analyzing the medical image series, at least in part based on natural language processing, to determine one or more characteristics of the medical image series;
accessing a reviewer database storing a plurality of reviewer records associated with a corresponding plurality of reviewers, each of the reviewer records indicating one or more characteristics of the corresponding reviewer;
comparing the preferences set by the user and the one or more characteristics of the medical image series to respective reviewer records in the reviewer database;
selecting, based on said comparison of the first preferences and the one or more characteristics of the medical image series to respective reviewer records, a first subset of reviewers including at least the first quantity of reviewers each having the first medical specialty;
selecting, based on said comparison of the second preferences and the one or more characteristics of the medical image series to respective reviewer records, a second subset of reviewers including at least the second quantity of reviewers each having the second medical specialty;
selecting, based on said comparison of the third preferences and the one or more characteristics of the medical image series to respective reviewer records, a third subset of reviewers including one or more reviewers having characteristics matching the third preferences;
automatically analyzing the medical image series to identify personally identifiable information in the medical image series;
automatically anonymizing the medical image series by removing or obscuring the personally identifiable information from the medical image series;
providing a notice, via a computerized user interface, to the selected first, second, and third subsets of reviewers indicating availability of the medical image series for review, the medical image series having been anonymized, wherein an identity of the user is also anonymized such that the first, second, and third subsets of reviewers cannot determine the identity of the user from the notice indicating availability of the medical image series or from the medical image series;
receiving separate medical reports from each reviewer of the first, second, and third subsets of reviewers;
anonymizing identities of each reviewer of the first, second, and third subsets of reviewers such that receivers of the medical reports cannot determine the identities of the reviewers of the first, second, and third subsets of reviewers from the medical reports;
providing, via a computerized user interface, the medical reports to a plurality of rating entities, the medical reports having been anonymized;
receiving, via a computerized user interface, from each of the rating entities, a separate rating for each of the medical reports, the ratings indicating accuracy of respective medical reports;
for each reviewer of the first, second, and third subsets:
compiling ratings of the reviewer from the plurality of rating entities; and
determining an overall rating of the reviewer;
generating a composite report comprising information on each of the medical reports from the first, second, and third subsets of reviewers, wherein the composite report indicates one of the medical reports associated with a highest overall rating and include one of:
the medical reports from each of the first, second, and third subsets of reviewers, the medical reports having been anonymized; or
summaries of at least some of the medical reports from the first, second, or third subsets of reviewers, the medical reports having been anonymized;
providing the composite report to the user;
receiving a request from the user to contact a first reviewer associated with a first medical report, the first medical report having been anonymized;
automatically determining an identity of the first reviewer;
requesting authorization from the first reviewer to provide the identity of the first reviewer to the user; and
in response to receiving authorization from the first reviewer to provide the identity of the first reviewer to the user, providing the identity of the first reviewer to the user.

US Pat. No. 10,510,424

SEMICONDUCTOR MEMORY DEVICE FOR IMPROVING DIFFERENCES BETWEEN CURRENT CHARACTERISTICS OF MEMORY CELLS

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:a voltage supply unit configured to provide operating voltages to a plurality of pages;
a page buffer coupled to a bit line and configured to control and sense currents flowing through the bit line in response to a page buffer sensing signal; and
a control logic configured to control the voltage supply unit and the page buffer to successively program the plurality of pages, and adjust a potential level of the page buffer sensing signal used for a program verify operation when a page selected to be programmed is changed according to a program sequence of the plurality of pages,
wherein different potential levels of the page buffer sensing signal are respectively used for program operations of different pages among the plurality of pages, and
wherein the potential levels of the page buffer sensing signal are increased as the selected page is changed in the program sequence.

US Pat. No. 10,510,419

MONITORING AND CHARGING INHIBIT BIT-LINE

Micron Technology, Inc., ...

1. A memory device, comprising:a group of memory cells including a first memory cell coupled to a first bit line (BL) and a second memory cell coupled to a second BL; and
a BL charging circuit configured to provide an inhibit signal to the second BL in response to a control signal to program the first memory cell, wherein, to provide the inhibit signal, the BL charging circuit is configured to apply a supply voltage (VCC) to the second BL for an initial wait time and, after the initial wait time, to apply a higher voltage than the supply voltage (VCC) until the inhibit signal reaches a value of the supply voltage (VCC).

US Pat. No. 10,510,417

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a first memory unit including a first memory string, the first memory string including first and second memory cells and a first select transistor;
a second memory unit including a second memory string, the second memory string including third and fourth memory cells and a second select transistor;
a third memory unit including a third memory string, the third memory string including fifth and sixth memory cells and a third select transistor;
a first word line coupled to gates of the first, third, and fifth memory cells;
a second word line coupled to gates of the second, fourth, and sixth memory cells;
first to third select gate lines coupled to gates of the first to third select transistors, respectively; and
a row decoder coupled to the first and second word lines and the first to third select gate lines,
wherein, in a write operation, the first memory cell, the third memory cell, the fifth memory cell, the sixth memory cell, the fourth memory cell, and the second memory cell are written in this order.

US Pat. No. 10,510,413

MULTI-PASS PROGRAMMING WITH MODIFIED PASS VOLTAGES TO TIGHTEN THRESHOLD VOLTAGE DISTRIBUTIONS

SanDisk Technologies LLC,...

1. An apparatus, comprising:a set of memory cells arranged in a NAND string and connected to a plurality of word lines, the NAND string extends vertically in a stack comprising alternating conductive and dielectric layers; and
a control circuit, the control circuit is configured to program a selected memory cell of the set of memory cells in a pre-final program pass, subsequently program a source side memory cell adjacent to the selected memory cell in a final program pass, and subsequently program the selected memory cell in a final program pass;
in the pre-final program pass of the selected memory cell, the control circuit is configured to apply a first pass voltage to the source side memory cell while applying a program voltage to the selected memory cell;
in the final program pass of the selected memory cell, the control circuit is configured to apply a second pass voltage to the source side memory cell while applying a program voltage to the selected memory cell; and
the second pass voltage is lower than the first pass voltage when the selected memory cell is in a bottom portion of the stack.

US Pat. No. 10,510,412

DATA TABLES IN CONTENT ADDRESSABLE MEMORY

Hewlett Packard Enterpris...

1. A processor coupled to a lookup engine and a content addressable memory (CAM) storing a plurality of data tables, wherein the processor is to send to the lookup engine a command to search a selected data table from the plurality of data table for a search word, wherein the command is to cause the search engine to:receive search parameters that comprise a search key, a column mask, and a row mask;
determine a set of rows and a set of columns associated with the selected data table based on the row mask and column mask, wherein a respective bit in the row mask indicates whether a corresponding entry in the selected data table is excluded from a search;
cause the CAM to perform the search in the set of rows for an entry comprising the search word in the set of columns; and
obtaining from the CAM an entry address of the entry comprising the search word in the set of columns.

US Pat. No. 10,510,404

WRITE ASSIST CIRCUIT OF MEMORY DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A device, comprising:a memory cell comprising a first inverter and a second inverter cross-coupled with the first inverter, wherein the first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage,
wherein during a write operation of the memory cell, the first operational voltage and the second operational voltage are configured at different voltage levels, and the third operational voltage and the fourth operational voltage are configured at the same voltage level.

US Pat. No. 10,510,398

SYSTEMS AND METHODS FOR IMPROVING WRITE PREAMBLES IN DDR MEMORY DEVICES

Micron Technology, Inc., ...

1. A memory device, comprising:data write circuitry configured to:
capture a first write command received via an external input/output (I/O) interface;
generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command; and
write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device, wherein the data write circuitry comprises a write command-to-write command counter system comprising at least one counter and counter circuitry to generate a partial write preamble signal (PartialWPre) based on a clock (CLK) waveform and the first write command, and wherein the data write circuitry is configured to use the PartialWPre to generate the first InternalWrStart internally and in the DQS domain.

US Pat. No. 10,510,397

INTEGRATED CIRCUIT DEVICES CONFIGURED TO CONTROL DISCHARGE OF A CONTROL GATE VOLTAGE

Micron Technology, Inc., ...

1. An integrated circuit device, comprising:a first node;
a second node;
a transistor connected between the first node and the second node;
a current path between a control gate of the transistor and the second node; and
a controller, wherein the controller is configured to:
concurrently discharge a voltage level of the first node and a voltage level of the second node;
monitor a representation of a voltage difference between the voltage level of the first node and a voltage level of the control gate of the transistor while discharging the voltage level of the first node and discharging the voltage level of the second node;
activate the current path if the voltage difference is deemed to be greater than a first value; and
deactivate the current path if the voltage difference is deemed to be less than a second value.

US Pat. No. 10,510,395

PROTOCOL FOR REFRESH BETWEEN A MEMORY CONTROLLER AND A MEMORY

Rambus Inc., Sunnyvale, ...

1. A memory controller integrated circuit (IC) to control a dynamic random access memory (DRAM) device, the memory controller IC comprising:interface circuitry to command the DRAM device to perform a refresh operation on a selected bank of the DRAM device;
wherein the memory controller IC is to observe a first time interval from completion of the refresh operation on the selected bank before sending a command directed to the selected bank via the interface circuitry; and
wherein the interface circuitry is to issue a command directed to a bank of the DRAM device other than the selected bank using a second time interval from completion of the refresh operation on the selected bank, the second time interval being shorter than the first time interval.

US Pat. No. 10,510,393

RESISTIVE MEMORY DEVICE INCLUDING REFERENCE CELL AND OPERATING METHOD THEREOF

Samsung Electronics Co., ...

1. A resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device comprising:a cell array including the memory cell and a reference cell;
a reference resistance circuit electrically connected to the reference cell;
an offset current source circuit configured to generate an offset current based on a control signal, the offset current being combined with a read current provided to the reference resistance circuit to increase or decrease a magnitude of the read current; and
a control circuit configured to generate the control signal to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.

US Pat. No. 10,510,390

MAGNETIC EXCHANGE COUPLED MTJ FREE LAYER HAVING LOW SWITCHING CURRENT AND HIGH DATA RETENTION

INTERNATIONAL BUSINESS MA...

1. A magnetic tunnel junction (MTJ) storage element comprising:a reference layer having a fixed magnetization direction;
a tunnel barrier layer; and
a free layer on an opposite side of the tunnel barrier layer from the reference layer;
where the free layer comprises a first region, a second region, and a third region;
where the first region comprises a first material configured to include a first predetermined magnetic moment and a first non-fixed magnetization direction;
where the second region comprises a second material configured to include a second predetermined magnetic moment and a second non-fixed magnetization direction;
where the first predetermined magnetic moment is configured to be lower than the second predetermined magnetic moment;
where the third region comprises a third material configured to magnetically couple the first region and the second region;
where the first region, the second region, and the third region are configured such that a direction of the first non-fixed magnetization direction changing also initiates the change in the direction of the second non-fixed magnetization direction.

US Pat. No. 10,510,374

SELF-HEALING IN A STORAGE SYSTEM

SEAGATE TECHNOLOGY LLC, ...

1. A method comprising:detecting a defect in a storage system causing a loss in physical storage capacity of the storage system, the storage system including a storage media storing data according to a first recording scheme; and
responsive to detecting the defect, converting at least a portion of the storage media to store data according to a second recording scheme, the second recording scheme storing data at a substantially higher storage density than a storage density of the first recording scheme.

US Pat. No. 10,510,373

MULTIPLE-ACTUATOR DRIVE WITH SEPARATE, RADIALLY-DEFINED, ZONES HAVING REDUCED SKEW AND/OR DIFFERENT TRACK PROPERTIES

Seagate Technology LLC, ...

1. A method comprising:reading first tracks via a first head that is moved via a first voice coil motor over a first, radially-defined, zone of a disk surface, the first voice coil motor and first head rotating about a first pivot;
reading second tracks via a second head that is moved via a second voice coil motor over a second zone of the disk surface that is separate from the first zone, the second voice coil motor and second head rotating about a second pivot independently from the first voice coil motor and first head, the second pivot being different from the first pivot, the first and second heads being optimized to read data within first and second skew angle ranges associated with the first and second zones, the first and second skew angle ranges each being less than a total skew angle range of the disk surface; and
reading from both the entire first and second zones via at least one of the first and second heads.

US Pat. No. 10,510,369

MAGNETIC TAPE HAVING CHARACTERIZED MAGNETIC PARTICLES AND MAGNETIC TAPE DEVICE

FUJIFILM Corporation, To...

1. A magnetic tape comprising:a non-magnetic support;
a non-magnetic layer including non-magnetic powder and a binder on the non-magnetic support; and
a magnetic layer including ferromagnetic powder and a binder on the non-magnetic layer,
wherein the total thickness of the non-magnetic layer and the magnetic layer is equal to or smaller than 0.60 ?m,
the magnetic layer includes a timing-based servo pattern,
the ferromagnetic powder is ferromagnetic hexagonal ferrite powder,
the magnetic layer includes an abrasive,
the tilt cos ? of the ferromagnetic hexagonal ferrite powder with respect to the surface of the magnetic layer acquired by cross section observation performed by using a scanning transmission electron microscope is 0.85 to 1.00, and
the percentage of hexagonal ferrite particles having a length in the long axis direction of equal to or greater than 10 nm and having an aspect ratio in a range of 1.5 to 6.0 in all of the hexagonal ferrite particles is equal to or greater than 50% but equal to or smaller than 95%, based on the particle number.

US Pat. No. 10,510,368

MAGNETIC TAPE INCLUDING CHARACTERIZED MAGNETIC LAYER AND MAGNETIC TAPE DEVICE

FUJIFILM Corporation, To...

1. A magnetic tape comprising:a non-magnetic support; and
a magnetic layer including ferromagnetic powder and a binder on the non-magnetic support,
wherein a total thickness of the magnetic tape is equal to or smaller than 5.30 ?m,
the magnetic layer includes a timing-based servo pattern,
a center line average surface roughness Ra measured regarding a surface of the magnetic layer is equal to or smaller than 1.8 nm,
the magnetic layer includes fatty acid ester,
a full width at half maximum of spacing distribution measured by optical interferometry regarding the surface of the magnetic layer before performing vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 7.0 nm,
a full width at half maximum of spacing distribution measured by optical interferometry regarding the surface of the magnetic layer after performing the vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 7.0 nm, and
a difference Safter?Sbefore between a spacing Safter measured by optical interferometry regarding the surface of the magnetic layer after performing the vacuum heating with respect to the magnetic tape and a spacing Sbefore measured by optical interferometry regarding the surface of the magnetic layer before performing the vacuum heating with respect to the magnetic tape is greater than 0 nm and equal to or smaller than 8.0 nm.

US Pat. No. 10,510,366

MAGNETIC TAPE DEVICE AND HEAD TRACKING SERVO METHOD

FUJIFILM Corporation, To...

1. A magnetic tape device comprising:a magnetic tape; and
a servo head,
wherein the servo head is a magnetic head including a tunnel magnetoresistance effect type element as a servo pattern reading element,
the magnetic tape includes a non-magnetic support, and a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic support,
the magnetic layer includes a servo pattern, and
a coefficient of friction measured regarding a base portion of a surface of the magnetic layer is equal to or smaller than 0.30.

US Pat. No. 10,510,358

RESOLUTION ENHANCEMENT OF SPEECH SIGNALS FOR SPEECH SYNTHESIS

Amazon Technologies, Inc....

1. A method for automated speech synthesis, said method comprising:receiving a control input representing a word sequence for synthesis, the control input including a time series of control values representing a phonetic label as a function of time;
generating a first synthesized waveform by processing the control values using a first artificial neural network, the first synthesized waveform including a first degradation associated with a limited number of quantization levels used in determining the first synthesized waveform;
generating a second synthesized waveform by processing the first synthesized waveform using a second artificial neural network, the second artificial neural network being configured such that the second synthesized waveform includes a second degradation, the second degradation being lesser than the first degradation in one or more of a degree of quantization, a perceptual quality, a noise level, a signal-to-noise ratio, a distortion level, and a bandwidth; and
providing the second synthesized waveform for presentation of the word sequence as an acoustic signal to a user.

US Pat. No. 10,510,354

SPEECH AUDIO ENCODING DEVICE, SPEECH AUDIO DECODING DEVICE, SPEECH AUDIO ENCODING METHOD, AND SPEECH AUDIO DECODING METHOD

PANASONIC INTELLECTUAL PR...

1. A speech/audio coding apparatus, comprising:a receiver that receives a time-domain speech input signal;
a processor that
transforms a time-domain speech input signal into a frequency-domain spectrum;
divides a frequency region of the spectrum in an extended band into a plurality of bands;
sets a limited band for each divided band in the current frame, when a difference between a first frequency with a first maximum amplitude in a spectrum of the divided band in a preceding frame and a second frequency with a second maximum amplitude in a spectrum of the divided band in a current frame is below a threshold, a width of the limited band in the current frame being narrower than the divided band and the limited band including the first frequency; and
encodes the spectrum in the limited band within each divided band in the current frame, and does not encode a spectrum outside the limited band within each divided band in the current frame,
wherein the width of the limited band is predetermined and is set to 31.

US Pat. No. 10,510,340

DYNAMIC WAKEWORD DETECTION

Amazon Technologies, Inc....

1. A computer-implemented method comprising:receiving, from a device and in response to the device detecting a wakeword in audio using a first wakeword detection threshold value, input audio data corresponding to an utterance;
performing automatic speech recognition (ASR) on the input audio data to generate input text data;
performing natural language understanding (NLU) on the input text data to generate NLU results data including intent data;
determining output data using the NLU results data;
based on the intent data, determine the device is to use a second wakeword detection threshold value for a duration of time, the second wakeword detection threshold value being different from the first wakeword detection threshold value;
causing the device to present content corresponding to the output data; and
sending, to the device, a command to use the second wakeword detection threshold value during the duration of time.

US Pat. No. 10,510,337

METHOD AND DEVICE FOR VOICE RECOGNITION TRAINING

Google LLC, Mountain Vie...

1. A method comprising:executing, by a processor of a mobile device, a first mode of the mobile device, the first mode configured to:
display on a screen in communication with the processor a first graphical user interface including a prompt instructing a user associated with the mobile device to speak a designated phrase for training a voice recognition system of the mobile device, the voice recognition system configured to recognize a voice of the user;
receive a first voice training sample corresponding to the user speaking the designated phrase; and
determine whether a noise level for the received first voice training sample exceeds a predetermined threshold; and
in response to determining that the noise level for the received first voice training sample exceeds the predetermined threshold, executing, by the processor, a second mode of the mobile device, the second mode configured to display on the screen of the mobile device a second graphical user interface comprising:
a notification that recommends an environment conducive to voice training; and
a graphical element,
wherein the second mode is further configured to enable the graphical element of the second graphical user interface for selection by the user when a background noise level does not exceed the predetermined threshold, the enabled graphical element, when selected by the user, causes the processor to transition from executing in the second mode back to executing in the first mode.

US Pat. No. 10,510,301

SCAN DRIVER AND DISPLAY APPARATUS HAVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A scan driver, comprising:a plurality of circuit stages sequentially outputting a plurality of gate signals and a plurality of compensation control signals, a single n-th circuit stage of the plurality of circuit stages comprising:
a first signal generator includes:
a first T1 transistor to apply an (n?1)-th gate signal to a first control node based on a first clock signal,
a second T1 transistor to output an n-th gate signal synchronized with a second clock signal different from the first clock signal based on a voltage of the first control node,
a third T1 transistor to apply a first gate voltage to a second control node based on the first clock signal, and
a fourth T1 transistor to output a second gate voltage as the n-th gate signal based on a voltage of the second control node (n is a natural number); and
a second signal generator including:
a first T2 transistor to apply an (n?1)-th compensation control signal to a third control node based on a third clock signal different from the first and second clock signals,
a second T2 transistor to output the first gate voltage as an n-th compensation control signal based on a voltage of the third control node,
a third T2 transistor to apply the first gate voltage to a fourth control node based on the second clock signal, and
a fourth T2 transistor to output the second gate voltage as the n-th compensation control signal based on a voltage of the fourth control node, wherein
an activated state of the (n?1)-th compensation control signal, an activated state of the n-th compensation control signal, and an activated state of the third clock signal overlap each other.

US Pat. No. 10,510,286

MOUNTING SUBSTRATE AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A mounting substrate comprising:a wiring substrate;
a plurality of pixels arranged in a matrix in a pixel region of the wiring substrate; and
a plurality of drivers that are disposed between pixels of the plurality of pixels in the pixel region and select the plurality of pixels in units of two or more pixels,
wherein each of the pixels includes an optical element and a pixel circuit, wherein the optical element emits or receives light, and the pixel circuit controls light emission or light reception of the optical element,
wherein each of the plurality of drivers is assigned to two or more pixel rows, and
wherein the optical elements, the pixel circuits and the drivers are mounted directly on a same surface of a layer of the mounting substrate.

US Pat. No. 10,510,277

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND REPAIRING METHOD THEREOF

Samsung Display Co., Ltd....

1. An organic light emitting display device comprising pixels positioned in regions defined by scan lines and light emission control lines extending in a first direction and data lines extending in a second direction different from the first direction, the pixels being configured to control an amount of current flowing from a first power source to a second power source by way of organic light emitting diodes (OLEDs) in response to data signals, the organic light emitting display device comprising: a scan driver configured to sequentially supply scan signals to the scan lines and light emission control signals to the light emission control lines during an inspection period; a data driver configured to supply inspection data signals to the data lines in synchronization with the scan signals during the inspection period; a first power source supply configured to supply a first voltage as the first power source during the inspection period and to supply a second voltage as the first power source during another period, the second voltage being higher than the first voltage; and one or more pads connected to at least one of the data lines, and configured to enable detection of an improperly functioning light emission control transistor due to a short between a specific one of the light emission control lines and the first power source when the first voltage is supplied as the first power source during the inspection period, wherein a pixel connected to an i-th (i is a natural number) light emission control line, an i-th scan line, and a j-th (is a natural number) data line among the pixels comprises: an organic light emitting diode; a first transistor configured to control the amount of current flowing from the first power source to the second power source by way of the organic light emitting diode according to a voltage of a gate electrode of the first transistor; a second transistor connected between a second electrode of the first transistor and the gate electrode of the first transistor, the second transistor having a gate electrode connected to the i-th scan line, a third transistor connected between an initialization power source having a voltage that is lower than that of the data signals and the gate electrode of the first transistor, and configured to apply a voltage of the initialization power source to the gate electrode of the first transistor while the light emission control signal of a hi h level is applied to the pixel, the third transistor having a gate electrode connected to an (i?1)-th scan line; a fourth transistor connected between the j-th data line and a first electrode of the first transistor, the fourth transistor having a gate electrode connected to the i-th scan line; and a light emission control transistor on a path of the current flowing from the first power source to the second power source by way of the organic light emitting diode, the light emission control transistor having a gate electrode connected to the i-th light emission control line.

US Pat. No. 10,510,276

APPARATUS AND METHOD FOR CONTROLLING A DISPLAY OF A VEHICLE

HYUNDAI MOTOR COMPANY, S...

1. An apparatus for controlling a display of a vehicle, the apparatus comprising:a camera configured to obtain a face image of a driver;
a sensor configured to sense a location of a seat on which the driver is seated; and
a controller,
wherein the controller is configured to
determine a location of an eye of the driver based on the face image and the location of the seat, and
correct a projection location of a virtual image projected onto a display device, based on the location of the eye.

US Pat. No. 10,510,270

LABEL WITH ADHESIVE AND SILICONE-FREE RELEASE COATING

Iconex LLC, Duluth, GA (...

1. A method, comprising:formulating a water-based release coating with a starch, a silicone release agent, a cross-linker, a catalyst, and a fluorochemical component, wherein formulating further includes formulating the water-based release coating with the fluorochemical component comprising approximately 21.45% of a total dry weight for the water-based release coating and with the fluorochemical component comprising approximately 38.87% of a total wet weight for the water-based release coating;
formulating a microsphere adhesive;
applying the water-based release coating on a first surface of a substrate; and
applying the microsphere adhesive on a second surface of the substrate with a coat weight of approximately 9 g/m2 as an adhesive patch.

US Pat. No. 10,510,263

DYNAMICALLY CONFIGURABLE AUDIENCE RESPONSE SYSTEM

Boxlight Corporation, La...

1. A handset configuration station for use in an audience response system, the audience response system comprising a wireless aggregation point, a first handset and a second handset, the first handset configured to communicatively couple to the wireless aggregation point to receive a first user input from a first user and to communicate the first user input to the wireless aggregation point, the second handset configured to communicatively couple to the wireless aggregation point to receive a second user input from a second user and to communicate the second user input to the wireless aggregation point, the handset configuration station comprising:a first configuration interface, wherein the first handset is configured to communicatively couple to the first configuration interface to define an operating parameter of the first handset via the first configuration interface; and
a second configuration interface, wherein the second handset is configured to communicatively couple to the second configuration interface to define an operating parameter of the second handset via the second configuration interface;
wherein the first handset and the second handset each reconfigure themselves with updated operating parameters based on each wirelessly receiving redefined operating parameters from the wireless aggregation point, the operating parameters for the first handset comprising a first handset identification (ID), a first frequency associated with a first communication channel, and a first key that establishes a communication link with the wireless aggregation point, wherein the first key is a first synchronization key or a first access key, and the operating parameters for the second handset comprising a second handset ID, a second frequency associated with a second communication channel, and a second key that establishes a communication link with the wireless aggregation point, wherein the second key is a second synchronization key or a second access key.

US Pat. No. 10,510,260

AIR TRAFFIC CONTROL OF UNMANNED AERIAL VEHICLES FOR DELIVERY APPLICATIONS

ETAK Systems, LLC, Hunte...

1. An Unmanned Aerial Vehicle (UAV) air traffic control method utilizing wireless networks and concurrently supporting package delivery management, the UAV air traffic control method comprising the steps of:communicating with a plurality of UAVs via a plurality of cell towers associated with the wireless networks, wherein each of the plurality of UAVs comprises hardware and antennas adapted to enable the respective UAV to communicate with the plurality of cell towers;
constraining a flight of each of the plurality of UAVs based on cell communication coverage of the plurality of cell towers, wherein the step of constraining the flight further comprises the steps of:
monitoring a strength of cell signals between the respective UAV and the plurality of cell towers during the flight of the respective UAV; and
adjusting the flight of the respective UAV whenever the cell signals are lost or the strength of the cell signals is degraded;
maintaining data associated with the flight of each of the plurality of UAVs based on the step of communicating with the plurality of UAVs via the plurality of cell towers;
processing the maintained data to perform a plurality of functions associated with air traffic control of the plurality of UAVs; and
processing the maintained data to perform a plurality of functions associated with the package delivery management for each of the plurality of UAVs.

US Pat. No. 10,510,256

VEHICLE COLLISION AVOIDANCE SYSTEM AND METHOD

1. A system for providing input to a control system of an operating vehicle, said system comprising a forward-facing signal sensor, said forward facing signal sensor operable to detect transmitted data signals reflecting a presence, relative distance and relative location of a first forward obstruction in or near a travel lane in front of said operating vehicle;an on-board vehicle status sensor configured to generate a status signal, wherein said status signal comprises a speed of said operating vehicle;
a processor configured to receive data from said forward-facing signal sensor and said status sensor and said processor adapted to process said transmitted data and a status operating information signal to determine a separate distance, a speed, and an acceleration or a deceleration of said forward obstruction with respect to said operating vehicle;
said forward-facing signal sensor further adapted to receive a relay signal from said forward obstruction, said relay signal originating from a source remote from said forward obstruction and relating to a second forward obstruction; and
a rear-signal transmitter, said rear-signal transmitter adapted to transmit information to a following vehicle, said information comprising said status signal and information from said forward-facing signal sensor indicating said presence and relative distance of said first forward obstruction and second forward obstruction; and
a vehicle control signal, wherein said vehicle control signal is generated in response to a collision avoidance algorithm run by said processor that uses data from a forward-facing signal detector, said status operating information and said relay signal in an event that said algorithm determines that a collision is imminent.

US Pat. No. 10,510,255

METHOD FOR REDUCING COLLISION DAMAGE

Robert Bosch GmbH, Stutt...

1. A method for performing an evasive maneuver of a motor vehicle in the event of an imminent collision with at least one collision object, the method comprising:a) detecting that a collision with the at least one collision object is imminent;
b) analyzing the at least one collision object and detecting whether a particularly sensitive upper region of the motor vehicle would be at least partially affected by the collision, the analyzing including ascertaining a height of a center of mass of the at least one collision object; and
c) outputting a signal for initiating an evasive maneuver when a collision of the motor vehicle with the at least one collision object is imminent by which the particularly sensitive upper region of the motor vehicle would be at least partially affected;
wherein the evasive maneuver of step c) is initiated when the ascertained height of the center of mass of the at least one collision object is higher than a predetermined minimum height.

US Pat. No. 10,510,253

METHOD AND APPARATUS FOR INDICATING VEHICLE MOVING STATE

Baidu Online Network Tech...

1. A method for indicating a vehicle moving state, comprising:receiving a vehicle driving instruction;
detecting a driving environment outside a vehicle;
determining a driving strategy for executing the vehicle driving instruction in the driving environment;
determining a driving track instructed by the driving strategy; and
projecting the driving track on a road by using a light projecting device mounted at a headlight, a rear position light, or a front/rear door handle of the vehicle when the driving environment satisfies a preset condition, wherein the satisfying the preset condition comprises: the vehicle being located in a residential area;
wherein the determining the driving strategy for executing the vehicle driving instruction in the driving environment comprises:
determining a target position to be reached by executing the vehicle driving instruction; and
determining a vehicle driving distance and a vehicle turning angle required for avoiding an obstacle outside the vehicle during driving from a current position of the vehicle to the target position, based on the current position, a position of the obstacle, and the target position.

US Pat. No. 10,510,249

SAFETY DRIVING ASSISTANT SYSTEM, VEHICLE, AND PROGRAM

SUMITOMO ELECTRIC INDUSTR...

1. A safety driving assistant system, comprising:an acquisition unit configured to acquire pieces of probe information from probe vehicles, each piece of probe information including information of a position of the corresponding probe vehicle and information of a time at which the probe vehicle has passed through the position;
a detection unit configured to detect a sudden-deceleration-prone spot where sudden deceleration of the probe vehicles frequently occurs, based on the pieces of probe information acquired by the acquisition unit; and
a provision unit configured to provide information of the sudden-deceleration-prone spot detected by the detection unit, to a target vehicle that receives safety driving assistance, wherein
each piece of probe information further includes information of a lane on which the corresponding probe vehicle travels, and
the detection unit detects the sudden-deceleration-prone spot for each lane, based on the pieces of probe information.

US Pat. No. 10,510,248

AUXILIARY IDENTIFICATION DEVICE FOR INDICATOR OBJECT AND AUXILIARY IDENTIFICATION AND DISPLAY METHOD THEREFOR

Wistron Corporation, New...

1. An auxiliary identification device for real-time acquiring road condition relating to a traveling vehicle, comprising:a camera module configured to obtain a video in a first direction of the traveling vehicle;
a controller coupled to the camera module and configured to receive the video obtained by the camera module and capture and identify a plurality of indicator objects in the video, wherein each of the indicator objects comprises indication information, and the controller sorts the indicator objects to determine a priority display order of the indicator objects and further generates a display image signal according to the priority display order; and
a display coupled to the controller and the display is configured to sequentially display the indicator objects according to the display image signal.

US Pat. No. 10,510,241

COMMUNICATION APPARATUS AND DATA PROCESSING METHOD

SONY CORPORATION, Tokyo ...

1. A communication apparatus for receiving and outputting emergency information, the communication apparatus comprising:circuitry configured to:
generate an emergency information viewing result report that contains a record of emergency information viewing result information; and
send the generated emergency information viewing result report, wherein
the emergency information viewing result report contains a record of:
an identifier of the emergency information output on the communication apparatus, and
time information representing a time in which at least one of a display and a speaker of the communication apparatus output the emergency information.

US Pat. No. 10,510,239

SYSTEMS AND METHODS FOR MANAGING ALERT NOTIFICATIONS FROM A SECURED AREA

Honeywell International I...

1. A system comprising:a transceiver device that receives first data from a first surveillance device that monitors a first secured area;
a processor that uses the first data to identify a first scenario associated with the first secured area and a first alert notification having a first notification priority of the first scenario; wherein:
when the processor recognizes a presence of a weapon carried by a person in the first secured area using the first data in the first scenario, and also recognizes the person as being authorized to carry the weapon, the processor sets the first notification priority below a preconfigured level;
when the processor recognizes a presence of a weapon carried by a person in the first secured area using the first data in the first scenario, but does not recognizes the person as being authorized to carry the weapon, the processor sets the first notification priority at or above the preconfigured level;
when the first notification priority is below the preconfigured level, the processor does not transmit, via the transceiver device, the first alert notification with the first notification priority to a cloud server indicative of the first scenario; and
when the first notification priority is at or above the preconfigured level, the processor transmits, via the transceiver device, the first alert notification with the first notification priority to a cloud server indicative of the first scenario.

US Pat. No. 10,510,237

SAFETY SERVICE SYSTEM AND METHOD THEREOF

THINKWARE CORPORATION, S...

1. A user terminal for providing a safety service, comprising:a location calculator that acquires a current location of the user terminal;
a communication unit that communicates with a security system;
a memory having computer readable instructions stored thereon; and
at least one processor configured to execute the computer readable instructions to determine whether an emergency situation is detected or a request of the safety service from a guardian terminal for the user terminal is received, wherein the emergency situation being detected requires no operation performed by a user of the user terminal to the user terminal and, in response to the emergency situation being detected or the request of the safety service being received, transmit the current location to at least one of the guardian terminal and the security system;
wherein the user terminal is registered on the security system which is associated with a user of the guardian terminal,
wherein the user terminal further comprises a camera unit that captures a peripheral image of the user terminal at predetermined time intervals, and
wherein the at least one processor is further configured to execute the computer readable instructions to, in response to the emergency situation being detected or the request of the safety service being received, transmit the captured peripheral image to the at least one of the guardian terminal and the security system.

US Pat. No. 10,510,235

TIME-REVERSAL INDOOR DETECTION SYSTEM AND METHOD

WISTRON NEWEB CORPORATION...

1. A time-reversal indoor detection system, comprising:an anchor node device, including:
a first wireless communication circuit supporting a first communication protocol; and
a second wireless communication circuit supporting a second communication protocol;
an access point (AP) device, comprising:
a processor;
a memory connected to the processor, configured to store a preset channel state information (CSI), wherein the preset CSI includes a first CSI and a normal CSI; and
a third wireless communication circuit supporting the first communication protocol and connected to the processor, communicating with the first wireless communication circuit through the first communication protocol within an indoor space; and
a first electronic device, including a fourth wireless communication circuit supporting the second communication protocol, and communicating with the second communication circuit through the second communication protocol,
wherein the first wireless communication circuit is configured to send a probe signal,
wherein the third wireless communication circuit is configured to receive the probe signal,
wherein the processor is configured to obtain a current CSI from the probe signal, and to compare the current CSI to the preset CSI, and
wherein when the first CSI is matched to the current CSI, the second wireless communication circuit is configured to activate at least one function of the first electronic device through the second communication protocol,
wherein the processor is configured to calculate a first time-reversal resonating strength (TRRS) value between the current CSI and the first CSI, and a second TRRS value between the current CSI and the normal CSI, and
wherein the first CSI is determined to be matched to the current CSI if the first TRRS value is larger than the second TRRS value and a threshold.

US Pat. No. 10,510,233

REDUCING AND ELIMINATING THE EFFECTS OF BRIGHT LIGHTS IN A FIELD-OF-VIEW OF A CAMERA

JEMEZ TECHNOLOGY LLC, Lo...

1. A system, comprising:at least one processor; and
a memory storing instructions that, when executed by the at least one processor, perform a method, comprising:
receiving a reference image;
receiving a new image;
determining an average value of pixels in the new image;
determining an average value of differences of the pixels in the new image;
determining whether a value of a pixel of the new image is greater than a sum of the average value of the pixels in the new image and the average value of the difference of the pixels in the new image; and
when it is determined that the value of the pixel of the new is greater than the sum, changing the value of the pixel to the sum of the average value of the pixels in the new image and the average value of the difference of the pixels in the new image.

US Pat. No. 10,510,228

SECURITY SYSTEM WITH KILL SWITCH FUNCTIONALITY

InVue Security Products I...

1. A merchandise display security system for protecting a handheld electronic article of merchandise from theft in a retail store, the merchandise display security system comprising:a handheld electronic article of merchandise on display in a retail store, the handheld electronic article of merchandise comprising a software program for generating a kill switch on the handheld electronic article of merchandise in response to a security event;
wherein the handheld electronic article of merchandise is configured to wirelessly transmit a unique identifier associated with the handheld electronic article of merchandise in response to the security event.

US Pat. No. 10,510,225

BENDABLE ELECTRONIC DEVICE APPARATUS AND METHODS

IMMERSION CORPORATION, S...

1. A bendable electronic device comprising:a flexible display coupled to a flexible haptic actuator, wherein the flexible haptic actuator includes:
a core, the core being formed with a flexible material, the core defining a volume;
an electromagnetic coil coiled around the core;
a casing surrounding the electromagnetic coil and at least a part of the core, the casing including a plurality of flexible trough sections and a plurality of stiff ridge sections; and
a haptic mass in the volume, the haptic mass at least partially formed with a ferromagnetic material, the haptic mass movable in the volume in response to the electromagnetic coil generating a magnetic field.

US Pat. No. 10,510,222

COLOR-CHANGING LIGHTING DYNAMIC CONTROL

Inception Innovations, LL...

1. A method of communicating emergencies using color-changing light sources, by emitting color-coded lighting messages, the method comprising:emitting from the at least one color-changing light source a first message segment consisting of three segment elements of lights-on of a first selected color alternated with three message elements of lights-off, wherein the color of the first selected color indicates an emergency type; and then
emitting from the at least one color-changing light source a second message segment consisting of three segment elements of lights-on of a white color alternated with three message elements of lights-off; and then
emitting from the at least one color-changing light source a third message segment identical to the first message segment; and then
repeatedly and sequentially emitting the first, second and third message segments; and then
changing at least one of the message segments, indicating verification of the emergency type.

US Pat. No. 10,510,220

INTELLIGENT ALARM SOUND CONTROL

INTERNATIONAL BUSINESS MA...

1. A method for implementing intelligent alarm sound control by a processor, comprising:isolating a targeted entity for a generated sound to be delivered, while simultaneously providing noise cancellation to prevent an alternative entity from being disturbed by the generated sound; wherein the generated sound is activated and isolated within a cone of silence for a selected period of time, and the alternative entity located outside the cone of silence is shielded from the generated sound by initiating the noise cancellation for a duration beginning prior to the selected period of time until the target entity performs a certain action.

US Pat. No. 10,510,207

LINKED COMMUNICATIONS FOR GAMING SYSTEMS USING ACOUSTIC SIGNATURES

Bally Gaming, Inc., Las ...

1. A gaming system comprising:a gaming machine configured to conduct a casino wagering game, the gaming machine including an acoustic input component; and
logic circuitry configured to:
receive, via the acoustic input component, an acoustic capture signal from a mobile device, the capture signal representative of a player account identifier corresponding to a player account, the capture signal having distinctive capture characteristics;
determine the player account identifier represented by the capture signal and associate a gaming session of the casino wagering game on the gaming machine with the corresponding player account;
in response to receiving, in a prescribed manner via the acoustic input component, an acoustic maintain-session signal from the mobile device, the maintain-session signal having distinctive maintain-session characteristics, maintain the association between the gaming session on the gaming machine and the corresponding player account for a period of time; and
in response to failing to receive the maintain-session signal in the prescribed manner, terminate the association between the gaming session on the gaming machine and the corresponding player account.

US Pat. No. 10,510,201

ELECTROMECHANICAL LOCK SECURITY SYSTEM

Xerox Corporation, Norwa...

1. An electromechanical locking system comprising:one or more moveable locking elements;
one or more actuators configured to move each of the one or more moveable locking elements between a plurality of positions that comprise a locked position and an unlocked position;
a receptacle configured to receive a key;
a sensor;
a processor; and
a computer-readable storage medium containing programming instructions that are configured to cause the processor to:
when the key is inserted into the receptacle, cause the sensor to scan the key and detect one or more features of the key,
identify a first code that corresponds to the detected features of the key,
apply one or more functions to the first code to yield a second code, wherein the second code comprises one or more characters, wherein each character corresponds to one of the plurality of positions, and
cause the one or more actuators to move the one or more movable locking elements to the one or more positions that correspond to the one or more characters of the second code.

US Pat. No. 10,510,196

REMOTE KEY FOB FOR MOTOR VEHICLES

1. A remote key fob for a vehicle, comprisinga communications and control device that includes at least one transmit/receive device,
a microcontroller,
a housing, arranged on the outer shell of which is a control surface that is coupled to the communications and control device for detecting operations of the control surface,
a printed circuit board accommodated in the housing and placed beneath the control surface and on which the microcontroller is placed,
wherein the control surface is mechanically coupled to a metal detection section such that a pressure actuation of the control surface from the outside results in a deformation or change of position of the metal detection section,
wherein the printed circuit board located beneath the control surface and the metal detection section includes a detection coil, wherein the detection coil is coupled to the communications and control device for forming an inductive proximity switch,
wherein the communications and control device determines a measure for the inductivity or quality of the detection coil and detects an actuation of the control surface as a function of the measure for the inductivity or quality of the detection coil.

US Pat. No. 10,510,195

SYSTEM AND METHOD FOR MONITORING STRESS CYCLES

Tesla, Inc., Palo Alto, ...

1. A system for monitoring stress cycles, the system comprising:a memory storing a base value and an inflection value of a stress cycle; and
one or more processors coupled to the memory and configured to receive a series of stress values of the stress cycle from a stress sensor, wherein the one or more processors are configured to perform operations comprising:
performing a first comparison between a first stress value and a previous stress value in the series of stress values;
detecting an inflection in the series of stress values of the stress cycle based on the first comparison;
updating the inflection value to be the previous stress value in response to the detecting the inflection;
performing a second comparison between a second stress value in the series of stress values and the base value;
determining that the stress cycle is complete based on the second comparison; and
recording the stress cycle in response to the determining that the stress cycle is complete.

US Pat. No. 10,510,194

CLOUD-BASED CONNECTIVITY ENERGY BUDGET MANAGER

Ford Global Technologies,...

1. A system comprising:a storage, onboard a vehicle, configured to maintain diagnostic data, cadence trigger criteria defining a periodic transmission of the diagnostic data, and priority trigger criteria defining out-of-cadence transmission of the diagnostic data; and
a processor, onboard the vehicle, programmed to
periodically send diagnostic data accumulated since a previous cadence transmission to a remote server per the cadence trigger criteria,
send out-of-cadence diagnostic data meeting the priority trigger criteria to the remote server, and
delete the out-of-cadence diagnostic data from the storage responsive to the send of the out-of-cadence diagnostic data to avoid resending the out-of-cadence diagnostic data in a next cadence transmission.

US Pat. No. 10,510,190

MIXED REALITY INTERACTIONS

MICROSOFT TECHNOLOGY LICE...

1. A mixed reality interaction system comprising:a head-mounted display device including a display system, and a camera; and
a processor configured to:
identify a physical object in a mixed reality environment based on an image captured by the camera;
determine an interaction context for the identified physical object based on one or more aspects of the mixed reality environment;
programmatically select an interaction mode from a plurality of interaction modes for the identified physical object based on the interaction context and a stored profile for the physical object, wherein the plurality of interaction modes are respectively associated with a plurality of different virtual actions;
interpret a user input directed at the physical object to correspond to a virtual action that is selected from the plurality of different virtual actions based on the selected interaction mode;
execute the virtual action to modify an appearance of a virtual object associated with the physical object; and
display the virtual object via the head-mounted display device with the modified appearance.

US Pat. No. 10,510,187

METHOD AND SYSTEM FOR VIRTUAL SENSOR DATA GENERATION WITH DEPTH GROUND TRUTH ANNOTATION

FORD GLOBAL TECHNOLOGIES,...

13. A sensor data generation system, comprising:one or more processors; and
memory operably connected to the one or more processors, the memory storing a plurality of components executable by the one or more processors, the plurality of components comprising:
a virtual environment programmed to include a plurality of virtual objects;
a sensor model programmed to model a sensor in the virtual environment;
a positioning module programmed to set a location and an orientation of the sensor in the virtual environment, wherein at least one of the virtual objects is a mobile virtual object, and wherein the sensor is on the mobile virtual object; and
a simulation module programmed to utilize the virtual environment, the sensor model and the positioning module to produce simulation-generated data characterizing the virtual environment as perceived by the sensor as the mobile virtual object and the virtual sensor move around in the virtual environment to model an output of the sensor in a real-world scenario sensing a real-world environment similar to or matching the virtual environment,
wherein the one or more processors execute the plurality of components to develop, test or train a computer vision detection algorithm by modeling the real-word environment with the virtual environment such that the simulation-generated data represents information collected by one or more real-word sensors in the real-word environment.

US Pat. No. 10,510,185

VARIABLE RATE SHADING

ADVANCED MICRO DEVICES, I...

1. A method for processing three-dimensional graphics with decoupled rasterization and pixel shading resolutions, to render an image to a render target, the method comprising:rasterizing, via a rasterizer, a triangle to produce fine rasterization data and a set of one or more quads;
accumulating at least one of the set of one or more quads output by the rasterizer into a tile buffer having a tile buffer size;
downsampling quads in the tile buffer to generate coarse quads, the downsampling based on a shading rate defined for the at least one of the set of one or more quads, wherein the shading rate indicates a first number of quads to generate from a second number of quads that fit into the tile buffer size;
shading the coarse quads to generate shaded coarse quads; and
modulating the shaded coarse quads with the fine rasterization data.

US Pat. No. 10,510,184

METHOD AND DEVICE FOR DETERMINING ILLUMINATION OF 3D VIRTUAL SCENE

SAMSUNG ELECTRONICS CO., ...

1. An electronic device for rendering a three-dimensional (3D) virtual scene, the electronic device comprising:a storage unit; and
at least one processor configured to:
divide the 3D virtual scene by using a plurality of grids,
obtain location information about a plurality of first points at which a plurality of rays originating from a light source located within the 3D virtual scene are incident on one or more objects located within the 3D virtual scene and location information about a plurality of first grids including the plurality of first points,
obtain location information about a plurality of second points at which the plurality of rays reflected from the plurality of first points are incident on the one or more objects and location information about a plurality of second grids including the plurality of second points,
identify illumination of each of the plurality of grids based on the location information about the plurality of first grids and the location information about the plurality of second grids, and
render the 3D virtual scene based on the identified illumination of each of the plurality of grids.

US Pat. No. 10,510,180

LEARNING TO RECONSTRUCT 3D SHAPES BY RENDERING MANY 3D VIEWS

Google LLC, Mountain Vie...

1. A computer-implemented method comprising:obtaining, from an object recognition engine, data specifying first image features derived from an image of an object;
providing the first image features to a three-dimensional estimator neural network;
obtaining, from the three-dimensional estimator neural network, data specifying (i) an estimated three-dimensional shape based on the first image features;
providing the data specifying the estimated three-dimensional shape to a three-dimensional rendering engine;
obtaining, from the three-dimensional rendering engine, data specifying a plurality of three-dimensional views of the object that are each generated based on the data specifying the estimated three-dimensional shape;
providing the data specifying each of the plurality of three-dimensional views to the object recognition engine;
obtaining, from the object recognition engine and for each of the plurality of three-dimensional views specified by the data, data specifying second image features derived from the data specifying the three-dimensional view;
computing, based at least on the data specifying the first image features and the data specifying the second image features, a first loss based on a first loss function; and
training the three-dimensional estimator neural network based at least on the computed first loss.

US Pat. No. 10,510,178

METHODS AND SYSTEMS FOR VOLUMETRIC RECONSTRUCTION BASED ON A CONFIDENCE FIELD

Verizon Patent and Licens...

1. A method comprising:accessing, by a volumetric reconstruction system, captured color and depth data for a surface of an object in a real-world capture space, the captured color and depth data captured by a plurality of capture devices positioned with respect to the real-world capture space so as to have different vantage points of the surface of the object; and
generating, by the volumetric reconstruction system based on the captured color and depth data, reconstructed color and depth data for a volumetric reconstruction of the surface of the object, the generating including
allocating, within a voxel data store, a respective set of voxel nodes corresponding to each surface point in a plurality of surface points on the surface of the object in the real-world capture space,
for each voxel node in each of the respective sets of voxel nodes within the voxel data store:
determining an intermediate confidence field value based on captured color and depth data captured for the voxel node by a first capture device in the plurality of capture devices,
updating the intermediate confidence field value based on captured color and depth data captured for the voxel node by each capture device in the plurality of capture devices other than the first capture device, and
storing, within the voxel node and subsequent to the updating of the intermediate confidence field value, the intermediate confidence field value as a confidence field value associated with the voxel node, and
determining, using a raytracing technique and based on the stored confidence field values within the voxel data store, the reconstructed color and depth data.

US Pat. No. 10,510,174

CREATING A MIXED-REALITY VIDEO BASED UPON TRACKED SKELETAL FEATURES

Microsoft Technology Lice...

1. A computing system comprising:a processor; and
memory storing instructions that, when executed by the processor, cause the processor to perform acts comprising:
estimating positions of skeletal features of a human body captured in frames of video generated by a camera, wherein the positions of the skeletal features of the human body in the captured frames are estimated based solely upon the captured frames of the video generated by the camera, and further wherein estimating the positions of the skeletal features comprises:
for a frame in the captured frames, generating an estimate of a position of a first skeletal feature of the human body;
determining that the estimate of the position of the first skeletal feature is incorrect based upon the estimate of the position of the first skeletal feature relative to an estimate of a position of a second skeletal feature in the frame; and
updating the estimate of the position of the first skeletal feature in the frame responsive to determining that the estimate of the position of the first skeletal feature is incorrect;
generating mixed reality video frames based upon the estimated positions of the skeletal features of the human body, wherein the mixed reality video frames include the captured frames combined with an animation; and
storing the mixed reality video frames in a computer-readable storage device.

US Pat. No. 10,510,168

METHOD FOR EDITING CHARACTER IMAGE IN CHARACTER IMAGE EDITING APPARATUS AND RECORDING MEDIUM HAVING PROGRAM RECORDED THEREON FOR EXECUTING THE METHOD

Jungha Ryu, Seongnam-si ...

1. A method for creating at least one dot image by using a dot image creating apparatus, comprising:(a) acquiring, by the apparatus, information on a character, wherein the information on the character includes a geometry of the character and an empty space within a subject region surrounding the geometry of the character, and wherein the empty space is an area within the subject region not occupied by the geometry of the character;
(b) assigning, by the apparatus, first metadata to portions within the subject region corresponding to the character, wherein the first metadata has a first color;
(c) assigning, by the apparatus, second metadata to portions of the subject region corresponding to the empty space not occupied by the character, wherein the second metadata has a second color;
(d) reassigning, by the apparatus, the first metadata to have the second color and the second metadata to have the first color;
(e) adjusting, by the apparatus, a ratio of an area of the first metadata to an area of the second metadata while maintaining the information on the geometry of the character by increasing the area of the first metadata within the subject region and by decreasing the area of the second metadata within the subject region, wherein the adjusted second metadata corresponds to the dot image; and
(f) outputting, by the apparatus, the dot image only without outputting the character, wherein the dot image per se represents the information on the geometry of the character.

US Pat. No. 10,510,163

IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD

Kabushiki Kaisha Toshiba,...

1. An image processing apparatus comprising:a rectification circuit configured to parallelize a first image and a second image based on parameter information for performing at least one of rotation and parallel movement on one or both of the first image and the second image;
a matching circuit configured to calculate and output y disparity by performing stereo matching processing on the first image and the second image outputted from the rectification circuit, the stereo matching processing being performed by calculating a degree of matching of each pixel in the first image while moving a window of a predetermined size in an X direction in the second image, and when the movement in the X direction is finished, changing from a line to a next line and moving the window in the X direction;
a displacement amount information creating circuit configured to create, by using the y disparity, displacement amount information of the images in a direction orthogonal to a search line for the first and second images subjected to the stereo matching processing; and
a rectification error determining circuit configured to determine whether or not there is an error of rectification which parallelizes the first and second images in the rectification circuit, based on the displacement amount information.

US Pat. No. 10,510,162

COMPUTER-IMPLEMENTED METHOD OF CALIBRATING A CAMERA

DASSAULT SYSTEMES, Veliz...

1. A computer-implemented method of calibrating a camera, comprising the steps of:a. acquiring a video stream from said camera, and displaying it on a screen;
b. displaying on the screen, superimposed to the video stream, a representation of a given target area from among a predetermined set of target areas;
c. detecting a calibration pattern in the video stream and periodically checking whether it fits within the given target area;
d. when the calibration pattern is found to fit within the given target area, extracting an image thereof from the video stream and storing it;
said steps a. to d. being iterated a plurality of times using respective target areas from the predetermined set of target areas, different from each other, each target area corresponding to an outline of the calibration pattern as seen by the camera when a physical support carrying the calibration pattern takes a respective position within a field of view of the camera; and then
e. estimating intrinsic calibration parameters of the camera by processing the stored images.

US Pat. No. 10,510,160

MULTISCALE WEIGHTED MATCHING AND SENSOR FUSION FOR DYNAMIC VISION SENSOR TRACKING

SAMSUNG ELECTRONICS CO., ...

1. A Dynamic Vision Sensor (DVS) pose-estimation system, comprising:a DVS to detect DVS events and to shape frames based on accumulated DVS events;
a transformation estimator to estimate a transformation of a camera of the DVS based on an estimated depth and to match confidence-level values within a camera-projection model such that at least one of a plurality of DVS events detected during a first frame corresponds to a DVS event detected during a second frame, the second frame being subsequent to the first frame, the transformation estimator estimating the transformation based on
in which i is an index, u is a detected DVS event, Cui is a scalar confidence-level value for a DVS event ui, I is a frame, k is a frame index, ? is a camera-projection model for the DVS, ??1 is an inverse of the camera-projection model for the DVS, ui is a vector corresponding to a detected event ui within the camera-projection model ?, dui is a three-dimensional depth of the DVS event ui in world coordinates, and Tk,k-1 is one of a plurality of possible vector transformations based on world coordinates between frame Ik-1 and frame Ik;an inertial measurement unit (IMU) to detect inertial movements of the DVS with respect to world coordinates between the first and second frames; and
a camera-pose estimator to combine information from a change in a pose of the DVS camera between the first frame and the second frame based on the estimated transformation and the detected inertial movements of the DVS.

US Pat. No. 10,510,158

COLLABORATIVE AIRBORNE OBJECT TRACKING SYSTEMS AND METHODS

Amazon Technologies, Inc....

1. A computer-implemented method to track airborne objects, comprising:receiving, from a first aerial vehicle of a plurality of aerial vehicles:
first location information associated with the first aerial vehicle;
first pose information associated with the first aerial vehicle;
first optical axis information associated with a first imaging device of the first aerial vehicle; and
first imaging data from the first imaging device of the first aerial vehicle;
identifying a first object within the first imaging data;
determining a first pixel location of the first object within the first imaging data;
determining a first optical ray associated with the first pixel location of the first object;
receiving, from a second aerial vehicle of the plurality of aerial vehicles:
second location information associated with the second aerial vehicle;
second pose information associated with the second aerial vehicle;
second optical axis information associated with a second imaging device of the second aerial vehicle; and
second imaging data from the second imaging device of the second aerial vehicle;
identifying a second object within the second imaging data;
determining a second pixel location of the second object within the second imaging data;
determining a second optical ray associated with the second pixel location of the second object;
determining that the first optical ray and the second optical ray intersect with a threshold degree of confidence, such that the first object and the second object are a same object;
determining at least one of a location or a range of the same object relative to at least one of the first aerial vehicle or the second aerial vehicle; and
instructing the at least one of the first aerial vehicle or the second aerial vehicle to navigate to avoid the same object based at least in part on the determined at least one of the location or the range of the same object relative to the at least one of the first aerial vehicle or the second aerial vehicle.

US Pat. No. 10,510,151

METHOD AND SYSTEM FOR OBTAINING PAIR-WISE EPIPOLAR CONSTRAINTS AND SOLVING FOR PANORAMA POSE ON A MOBILE DEVICE

Google LLC, Mountain Vie...

1. A computer implemented method for determining the location and orientation of panoramic images:receiving, by one or more computing devices, alignment data between a pair of panoramic images including a first panoramic image and second panoramic image, and original location data for the pair of panoramic images, wherein the original location data includes geographic location data including latitude and longitude coordinates corresponding to where the first panoramic image and the second panoramic image were captured;
calculating, by the one or more computing devices, a heading from the first panoramic image to the second panoramic image based on the original location data;
determining, by the one or more computing devices, relative orientations between the pair of panoramic images based on the alignment data and the heading;
optimizing, by the one or more computing devices, the original location data and the alignment data based on the relative orientations between the pair of panoramic images and the original location data, wherein optimizing includes calculating optimized relative orientations and optimized location data by minimizing costs for a location objective function and an orientation objective function;
replacing, by the one or more computing devices, the original location data and relative orientations with the optimized relative orientations and optimized location data.

US Pat. No. 10,510,147

IMAGE PROCESSING DEVICE

OLYMPUS CORPORATION, Tok...

1. An image processing device comprising:a plurality of label data generation units of the device which generate label data in which a predetermined label is assigned to each of a plurality of pixels in each of a plurality of divided images into which an input image is divided as a plurality of regions;
a plurality of label integration information generation units of the device which correspond to the respective label data generation units and generate label integration information representing association of labels included in the label data in order to integrate label data generated by a corresponding label data generation unit and label data generated by another label data generation unit;
a plurality of label integration units of the device which generate integrated label data in which respective pieces of label data corresponding to neighboring divided images are integrated on the basis of the label integration information; and
a label integration processing controller which distributes the label data to the respective label integration units such that computational loads to integrate the label data are equalized,
wherein the label integration information generation units generate the label integration information for all the label data before the label integration units perform computations for integrating the respective pieces of label data; and
wherein each of the label data generation units generates label data in which overlap pixels which are pixels overlapping with a peripheral portion of another one of the divided images which are positioned in a peripheral portion of the corresponding divided image are assigned with a first label having a value uniquely determined depending on the positions of the overlap pixels or a second label which is determined to be an exclusive value for pixels located at positions other than the peripheral portion included in the divided image and is different from the first label,
the label integration information is information in which the value of the first label is stored as an initial value in a first storage region corresponding to each of the overlap pixels included in each of the divided images, and the value of the second label assigned to any one pixel located at a position other than the peripheral portion included in each of the divided images is stored in a second storage region other than the first storage region,
each of the label integration information generation units updates, when the corresponding label data generation unit assigns the second label to any one of the overlap pixels, the value of the first label stored in the first storage region corresponding to the overlap pixel assigned with the second label to the value of the assigned second label in the label integration information, and
each of the label integration units changes the value of the first label assigned to pixels assigned with the first label having the same value as a value which has been uniquely determined for the overlap pixel corresponding to the first storage region whose value is updated from the initial value to the updated value stored in the first storage region.

US Pat. No. 10,510,145

MEDICAL IMAGE COMPARISON METHOD AND SYSTEM THEREOF

INDUSTRIAL TECHNOLOGY RES...

1. A medical image comparison method, comprising the steps of:obtaining a plurality of images of a body at different time points, while allowing the plural images to include a first image captured at a first time point and a second image captured at a second time point;
obtaining a first feature point group by detecting feature points in the first image, while obtaining a second feature point group by detecting feature points in the second image;
enabling an overlapping image information to be generated by aligning the second image with the first image according to the first feature point group and the second feature point group, while allowing the overlapping image information to include a first matching image corresponding to the first image and a second matching image corresponding to the second image; and
sequentially extracting corresponding window areas from the first matching image and the second matching image in the overlapping image information respectively by the use of a sliding window mask, while calculating an image difference ratio for each of the window areas according to the ratio between the number of matching points and the number of unmatched points in the corresponding window areas of the first and the second matching images.

US Pat. No. 10,510,138

DEVICE AND METHOD FOR IMAGE ENLARGEMENT AND DISPLAY PANEL DRIVER USING THE SAME

Synaptics Japan GK, Toky...

1. A display driver, comprising:a scaler circuit configured to enlarge an input image with an enlargement by:
generating an intermediate pixel image composed of intermediate pixels, wherein each of the intermediate pixels corresponds to a different 2×2 pixel array of the input image, wherein the intermediate pixels are determined by calculating an average pixel value of at least two pixels of a corresponding pixel array of the input image, and wherein the at least two pixels of the corresponding pixel array do not include a pixel having a highest pixel value of the pixel array and a pixel having a lowest pixel value of the pixel array;
generating an interpolated image comprising interpolation pixels, wherein each of the interpolation pixels corresponds to at least one of a combination of two adjacent pixels of the input image in a horizontal direction, and a combination of two adjacent pixels of the input image in a vertical direction; and
incorporating the input image, the intermediate pixel image, and the interpolated image into an enlarged image; and
a driver section configured to drive a display panel at least partially based on the enlarged image.

US Pat. No. 10,510,132

VEHICLE FLEET MANAGEMENT METHOD AND SYSTEM WITH LOAD BALANCING

CREATIVE MOBILE TECHNOLOG...

1. A method of managing a plurality of vehicles in a fleet of vehicles operatively controlled by a fleet management system, the method comprising:maintaining a plurality of wireless communication connections between the plurality of vehicles in the fleet and a central control center, each wireless communication connection operative between one or more of the plurality of vehicles and the central control center, via a cluster of gateways and a cluster of application switches, each wireless communication connection being maintained, at least in part, by messages initiated by each connected vehicle of the plurality of vehicles, wherein the central control center, the cluster of gateways, and the cluster of application switches handle a plurality of simultaneous wireless communication connections with the plurality of vehicles;
receiving a plurality of vehicle location messages at the central control center;
the plurality of vehicle location messages including information indicating the geographic location of a corresponding one of the plurality of vehicles in the fleet, in real-time or near real-time;
wherein the plurality of vehicle location messages are sent to the central control center frequently enough to maintain the wireless communication connections, wherein the central control center monitors the plurality of vehicle location messages and establishes a new communication session if a vehicle location message is not received within a predetermined time period, to ensure consistent receipt of the plurality of vehicle location messages;
load balancing using the messaging gateways of the cluster of messaging gateways to provide maximum communication uptime for the plurality of vehicles, while only one messaging gateway of the cluster of messaging gateways is visible to any single vehicle of the plurality of vehicles, at a given time;
wherein, based on current load conditions, one or more of the cluster of application switches determines which messaging gateway of the cluster of gateways is to maintain the wireless communication connections between a specific vehicle of the plurality of vehicles and the central control center, such that additional messaging gateways are included when the load conditions increase;
collecting and storing the plurality of vehicle location messages and additional messages at the central control center;
receiving, by the central control center, a polling communications from the plurality of vehicles; and
sending, by the central control center, updates to the plurality of vehicles based on the received polling communications.

US Pat. No. 10,510,125

EXPENSE COMPLIANCE CHECKING BASED ON TRAJECTORY DETECTION

International Business Ma...

1. A computer-implemented method, comprising:determining a trajectory information type of a receipt submitted by an employee;
retrieving, based on the trajectory information type, trajectory information associated with the receipt submitted by the employee;
retrieving trajectory information corresponding to a device associated with the employee based on at least
obtaining, from the device, one or more location-time sequences of the device, and
deducing the trajectory information from at least one of the one or more location-time sequences; and
determining the receipt is a valid receipt in response to the trajectory information associated with the receipt submitted by the employee matching the trajectory information associated with the device associated with the employee, wherein the receipt is reimbursable based on determining the receipt is a valid receipt.

US Pat. No. 10,510,124

SYSTEMS AND METHODS FOR VEHICLE ACCIDENT DETECTION BASED ON INTELLIGENT MICRO DEVICES

United Services Automobil...

1. A system comprising:a marker-reading device configured to determine a plurality of machine-readable markers on a vehicle; and
a computing device in communication with the marker-reading device, wherein the computing device is configured to:
receive, from the marker-reading device, an indication of the plurality of machine-readable markers on the vehicle; and
determine, based on the plurality of machine-readable markers on the vehicle and historical data associated with the vehicle, damage to the vehicle.

US Pat. No. 10,510,115

COMPUTERIZED EXCHANGE CONTROLLED NETWORK SYSTEM AND RELATED METHOD

DEARBORN FINANCIAL, INC.,...

1. A system forming a computerized, Exchange-controlled network (“ECN”) operated by an organization forming an Exchange, the system comprising:at least one host server disposed at a first location and being in communication with at least two front-end virtual servers disposed at second and third locations, respectively, the at least two front-end virtual servers assigned to Exchange-authorized communities of interest (“COI”) each made up of at least one member and authenticated to cryptographically validate, process, transmit and receive pre-approved digital information passed along the ECN without the use of intermediaries in a chain of communications; and
a plurality of dongles comprised of hardware and software, each said dongle configured to operate in conjunction with a respective server, enabling the dongles to control access to the ECN and what digital data is made available to its respective said server at any given time, where said digital data is stored and who manages various storage needs and server networks, regardless if the various storage needs are at a front-end or at a host end of the ECN; and enables buy and sell orders of digital ETD contracts to be cryptographically authenticated, posted and ultimately matched, executed and confirmed as trades to be cleared, settled and reported contemporaneously over the ECN in compliance with policies and rules established by the Exchange, and without the use of intermediaries in the chain of communications.

US Pat. No. 10,510,110

HOME ELECTRICAL APPLIANCE AND NETWORK SYSTEM

1. A network system comprising:a home appliance connected to a communication line, the home appliance including a control portion configured to control an operating state of the home appliance, an information setting portion configured to set information corresponding to a current state of the home appliance, and a transmitting portion configured to externally transmit a result of information set by the information setting portion through the communication line;
a storing unit connected to the home appliance through the communication line and configured to store multiple entries of data for displaying advice pertaining to the home appliance; and
a communication terminal connected to the storing unit through the communication line and provided with a display portion, the communication terminal being configured to display: a select screen provided with multiple keys, each of the multiple keys provided with a message label indicating a different, improper operation state of the home appliance respectively and configured to be selected and electrically operated by a user determining a corresponding improper operation state of the home appliance, a specific advice to improve the operation state of the home appliance indicated by the message label provided on the key operated by the user, the specific advice being based on data obtained from the multiple entries of data stored in the storing unit corresponding to the result of information transmitted by the home appliance, and a general advice displayed on a same screen and at a same time as the specific advice, the general advice including information not reflective of the result of information transmitted by the home appliance.

US Pat. No. 10,510,109

CONTROLLING ROUTING OF OUTPUT INFORMATION TO OUTPUT DEVICES

Amazon Technologies, Inc....

1. A system for presenting output information, comprising:a plurality of output devices located within a materials handling facility;
an output host configured to provide output information for presentation by at least one of the plurality of output devices, wherein the output information includes an image to be presented by an output device of the plurality of output devices, the image including location information indicating at least one of:
a physical location within the materials handling facility at which at least a portion of the output information is to be presented;
a logical location within the materials handling facility at which at least a portion of the output information is to be presented; or
a device identifier identifying the output device of the plurality of output devices that is to present at least a portion of the output information;
an output router communicatively coupled with the output host and each of the plurality of output devices, wherein the output router is configured to at least:
receive the output information from the output host;
process at least a portion of the image included in the output information to obtain the location information;
determine, based at least in part on the location information, the output device from the plurality of output devices to which to send the output information; and
send the output information to the output device; and
the output device configured to at least:
receive the output information; and
present at least a portion of the image.

US Pat. No. 10,510,105

TRAVELER RECOMMENDATIONS

Oath Inc., New York, NY ...

1. A method, comprising:identifying a set of location points indicative of one or more locations at which a device of a user has been located;
generating location point pairings from the set of location points;
evaluating the location point pairings to identify a target location point pairing indicative of air flight travel from a target departure location point to a target arrival location point, wherein the evaluating the location point pairings comprises:
calculating, based upon timestamp data associated with a location point pairing, an average speed for traveling from a departure location point of the location point pairing to an arrival location point of the location point pairing; and
responsive to the average speed not exceeding an air flight speed threshold, filtering the location point pairing;
determining that the user of the device is an air flight traveler to a destination location corresponding to the target arrival location point; and
responsive to determining that the user of the device is the air flight traveler to the destination location:
generating a recommendation of content for the destination location; and
providing the recommendation to the device of the user,
wherein at least one of the set of location points or the location point pairings is stored in a computational cluster configured to store data in a distributed computing environment, wherein computational processing of at least one of the set of location points or the location point pairings utilizing the computational cluster is associated with a reduction in computational processing time.

US Pat. No. 10,510,095

SEARCHING BASED ON A LOCAL DENSITY OF ENTITIES

Samsung Electronics Co., ...

1. A method for providing content to a user device in an electronic device, comprising:in response to receiving a search criteria and location data from the user device, identifying, by a processor of the electronic device, a user location based on the location data;
generating, by the processor, an entity density grid for a geographical area, wherein the entity density grid has one or more nodes, wherein the entity density grid includes a plurality of cells formed by latitude lines and longitudinal lines;
identifying, by the processor, a first entity density value for each of the one or more nodes included in the entity density grid, wherein the one or more nodes are intersections of the entity density grid, wherein the first entity density value for each of the one or more nodes is a total number of entities included in four cells surrounding a corresponding node from among the plurality of cells;
identifying, by the processor, a second entity density value for each of the one or more nodes by increasing the first entity density value for each of the one or more nodes based on locations of the entities with respect to each of the one or more nodes;
identifying, by the processor, a geographical density of entities corresponding to the user location as a second entity density value of a closest node to the user location;
selecting, by the processor, one or more access mechanisms based on the search criteria and the geographical density, each access mechanism, when executed by the user device, causes the user device to access a resource identified by the access mechanism; and
transmitting, by the processor via a communication circuitry of the electronic device, search results including the one or more selected access mechanisms to the user device.

US Pat. No. 10,510,091

SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING DIGITAL COUPONS TO USERS

INMAR CLEARING, INC., Wi...

1. A method of providing a digital coupon to a user for redemption at a point-of-sale (POS) terminal, the method comprising:using a processor and a memory coupled thereto to
store historical purchased product data including corresponding historical purchased product identification codes,
receive a plurality of coupon identifiers from a plurality of retailers, the plurality of coupon identifiers being associated with products being offered at a discount by the plurality of retailers, each coupon identifier corresponding to a code to be read at the POS terminal, to identify to the POS terminal, coupon information comprising a manufacturer and an amount of the discount,
associate the plurality of coupon identifiers with a respective first plurality of product identification codes,
compare the first plurality of product identification codes associated with products being offered at a discount by a given retailer from among the plurality thereof and stored in the memory with a second plurality of product identification codes associated with products being offered at a discount by a manufacturer and stored in the memory,
display, on a display coupled to the processor, at least one matched product corresponding to matching first and second product identification codes,
display, on the display, a digital coupon corresponding to each matching product, the digital coupon having a value equal to a sum of the discount by the given retailer and the discount by the manufacturer,
receive user identification information associated with the user,
determine whether the user has activated auto-clipping of digital coupons based upon the user identification information,
when the user has activated auto-clipping of digital coupons, determine whether the user has previously purchased each of the matching products based upon comparing the first and second identification codes to the historical product identification codes for the user based upon the user identification information, and for each of the matching products the user has previously purchased, place a corresponding digital promotion in a digital wallet associated with the user and for redemption at the POS terminal at a retailer location associated with the given retailer, and
when the user has not activated auto-clipping of digital coupons, permit user-selection via at least one input device coupled to the processor, of the corresponding digital coupon for placement in the digital wallet associated with the user and for redemption at the POS terminal at the retailer location associated with the given retailer,
obtain at least one purchased product identification code associated with a purchased product during a purchase transaction associated with the user from the POS terminal at the retailer location, and
determine whether digital coupons in the digital wallet are applicable by comparing the at least one purchased product identification code with one of the first and second product identification codes associated with each matching product and based upon the user identification information.