US Pat. No. 10,340,289

CASCODE RADIO FREQUENCY (RF) POWER AMPLIFIER ON SINGLE DIFFUSION

QUALCOMM Incorporated, S...

1. An amplifier, comprising:a cascode structure comprising a first transistor having first characteristics coupled to a second transistor having second characteristics different than the first characteristics, the first transistor located with the second transistor on a single diffusion, the single diffusion having no intervening insulating layer separating the first transistor from the second transistor, the single diffusion comprising at least a P-type well region, a floating P body region having a P+ island, and a no well region having a native state of a silicon-on-insulator (SOI) layer on which the amplifier is located.

US Pat. No. 10,340,288

METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVING UNIDIRECTIONAL LAYOUT USING SELF-ALIGNED DOUBLE PATTERNING

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a first set of metal features extending in a first lateral direction in a first metal layer of a memory cell;
forming a second set of metal features extending in a second lateral direction perpendicular to the first lateral direction in a second metal layer of said memory cell;
forming a third set of metal features extending in the second lateral direction in a second metal layer of a functional cell for providing routing compatibility between said memory cell and said functional cell; and
placing said memory cell adjacent to said functional cell for forming an integrated circuit device.

US Pat. No. 10,340,287

APPARATUSES AND METHODS FOR FORMING MULTIPLE DECKS OF MEMORY CELLS

Micron Technology, Inc., ...

1. An apparatus comprising:a first deck including alternating levels of first conductor materials and levels of first dielectric materials;
first memory cells located in the first deck, each of the first memory cells located in a respective level of the levels of first conductor materials;
a second deck including alternating levels of second conductor materials and levels of second dielectric materials;
second memory cells located in the second deck, each of the second memory cells located in a respective level of the levels of second conductor materials;
a level of third conductor material located between the first and second decks;
a level of fourth conductor material located between the first and second decks; and
a level of a dielectric material located between the level of third conductor material and the level of fourth conductor material.

US Pat. No. 10,340,286

METHODS OF FORMING NAND MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method of forming a NAND memory array, comprising:forming a vertical stack of alternating first and second levels; the first levels comprising first material, and the second levels comprising second material;
recessing the first levels relative to the second levels; the second levels having projecting terminal ends extending beyond the recessed first levels; cavities extending into the first levels between the projecting terminal ends;
forming charge-storage material around the terminal ends of the second levels; the charge-storage material extending into the cavities to line the cavities;
forming charge-tunneling material extending vertically along the charge-storage material; the charge-tunneling material filling the lined cavities;
forming channel material extending vertically along the charge-tunneling material;
removing the first material to leave first voids;
etching into the charge-storage material with etchant provided in the first voids;
forming insulative third material within the first voids after etching into the charge-storage material;
removing the second material to form second voids; and
forming conductive levels within the second voids; the conductive levels being wordline levels of the NAND memory array and having terminal ends corresponding to control gate regions; the control gate regions being adjacent the charge-storage material.

US Pat. No. 10,340,285

NON-VOLATILE MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device comprising:a plurality of memory cells stacked in a first direction and electrically connected in series;
at least one of the memory cells including:
a first electrode;
a first semiconductor layer extending in the first direction through the first electrode;
a memory film provided between the first electrode and the first semiconductor layer; and
a first insulating core layer provided inside the first semiconductor layer; and
a select transistor provided above the memory cells in the first direction and electrically connected to the memory cells in series, the select transistor including:
a second electrode;
a second semiconductor layer extending in the first direction through the second electrode, the second semiconductor layer being coupled to the first semiconductor layer of the at least one of the memory cells;
a gate insulating film provided between the second electrode and the second semiconductor layer; and
a second insulating core layer provided inside the second semiconductor layer;
a thickness of the second semiconductor layer in a second direction orthogonal to the first direction being thinner than a thickness of the first semiconductor layer in the second direction.

US Pat. No. 10,340,284

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Samsung Electronics Co., ...

8. A semiconductor device comprising:a stack structure including a plurality of conductive layer patterns and a plurality of interlayer insulating layer patterns that are alternately and vertically stacked on one another;
an air gap disposed vertically in the stack structure;
a passivation layer covering an upper surface of the air gap;
a channel layer surrounding a side surface of the air gap;
a dielectric layer surrounding a side surface of the channel layer and in contact with the stack structure; and
a pad disposed on the passivation layer and in contact with an uppermost interlayer insulating layer pattern of the plurality of interlayer insulating layer patterns.

US Pat. No. 10,340,283

PROCESS FOR FABRICATING 3D MEMORY

MACRONIX International Co...

1. A process for fabricating a 3D memory, comprising:forming a plurality of linear stacks, each of which comprises a plurality of gate lines and a plurality of insulating layers that are stacked alternately;
forming a charge trapping layer covering tops and sidewalls of the linear stacks;
forming an amorphous semiconductor layer on the charge trapping layer;
forming a cap layer on the amorphous semiconductor layer; and
annealing the amorphous semiconductor layer to form a crystalline channel layer while the charge trapping layer covers the tops and the sidewalls of the linear stacks, wherein agglomeration of a material of the amorphous semiconductor layer is suppressed by the cap layer.

US Pat. No. 10,340,281

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three-dimensional (3D) semiconductor device, comprising:a substrate having an array area and a staircase area adjacent to the array area, wherein the staircase area comprises N steps, N is an integer one or greater;
a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers above the substrate, the stack comprising sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps of the staircase area to form respective contact regions, wherein two of the respective contact regions are positioned higher than one of the respective contact regions disposed between said two of the respective contact regions, and an uppermost active layer of each of the sub-stacks in the respective contact regions comprises a silicide layer, wherein the uppermost active layer of each of the sub-stacks in the respective contact regions is continuously extended from one of the active layers in the array area respectively; and
multilayered connectors, formed in the respective contact regions and extending downwardly to electrically connect the silicide layer of the uppermost active layer in each of the sub-stacks.

US Pat. No. 10,340,280

METHOD AND SYSTEM FOR OBJECT RECONSTRUCTION

APPLE INC., Cupertino, C...

1. A system for object reconstruction, comprising:an illuminating unit, configured to generate a pattern of spots;
a diffractive optical element (DOE) in an optical path of illuminating light propagating from the illuminating unit toward an object, thereby projecting the pattern of spots onto an object;
an imaging unit configured to detect a light response of an illuminated region and generating image data indicative of the object within the projected pattern; and
a processor, configured to reconstruct a three-dimensional (3D) map of the object by processing the image data.

US Pat. No. 10,340,279

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Sony Semiconductor Soluti...

1. A method of manufacturing a semiconductor device comprising:selecting a first through electrode from a plurality of through electrodes, the through electrodes penetrating a plurality of conductive layers and a plurality of insulating layers that are alternately stacked, wherein
antifuses are each provided between corresponding ones of the through electrodes and corresponding ones of the conductive layers;
applying a first voltage and a second voltage, the first voltage being applied to one or more of the through electrodes excluding the first electrode, and the second voltage being applied to the first through electrode; and
causing the first through electrode to be electrically floated after the second voltage is applied to the first through electrode.

US Pat. No. 10,340,278

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor memory device, comprising:a semiconductor substrate, wherein a memory cell region and a peripheral region are defined on the semiconductor substrate;
a patterned conductive structure disposed on the semiconductor substrate, wherein the patterned conductive structure is disposed on the memory cell region and the peripheral region, and the patterned conductive structure comprises:
a first silicon conductive layer;
a second silicon conductive layer disposed on the first silicon conductive layer;
an interface layer disposed between the first silicon conductive layer and the second silicon conductive layer, wherein the interface layer comprises oxygen;
a barrier layer disposed on the second silicon conductive layer; and
a metal conductive layer disposed on the barrier layer, wherein the patterned conductive structure disposed on the memory cell region comprises a bit line structure; and
a bit line contact structure disposed on the memory cell region, wherein the bit line contact structure is disposed between the barrier layer and the semiconductor substrate.

US Pat. No. 10,340,277

SEMICONDUCTOR DEVICES INCLUDING SUPPORT PATTERNS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a plurality of pillar structures on a semiconductor substrate, the semiconductor substrate including a cell region and a dummy region; and
a support pattern in contact with at least a part of each of the plurality of pillar structures, the support pattern connecting the plurality of pillar structures with one another,
wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including a plurality of first support holes and at least one second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other, and
wherein the plurality of the first support holes are on a central portion of the cell region, and the at least one second support hole is only at an edge portion of the cell region among the central and edge portions of the cell region.

US Pat. No. 10,340,276

METHOD OF MAINTAINING THE STATE OF SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. An integrated circuit comprising:an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising:
said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a transistor comprising a source region, a floating body region, a drain region, and a gate;
a first bipolar device having a first floating base region, a first emitter, and a first collector; and
a second bipolar device having a second floating base region, a second emitter, and a second collector;
wherein said first floating base region and said second floating base region are common to said floating body region;
wherein said first collector is common to said second collector;
wherein application of back bias to said first and second collectors results in at least two stable floating base region charge levels;
wherein said transistor is usable to access said memory cell;
a first control circuit configured to apply said back bias to said first and second collectors; and
a second control circuit configured to access a selected memory cell selected from said semiconductor memory cells and perform a read or write operation on said selected memory cell.

US Pat. No. 10,340,274

LDMOS FINFET DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:a semiconductor substrate;
first and second fins on the semiconductor substrate and separated by a trench, the first fin comprising a first portion including a first conductivity type and a second portion including a second conductivity type different from the first conductivity type, the first and second portions adjacent to each other, the second portion connected to the second fin through the semiconductor substrate;
a gate structure on the first and second portions, the gate structure comprising:
a gate insulator layer on the first and second portions;
a gate on a portion of the gate insulator layer on the first portion; and
a dummy gate on the second portion and comprising an insulating layer or an undoped semiconductor layer, the dummy gate being adjacent to the gate.

US Pat. No. 10,340,273

DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES

Intel Corporation, Santa...

1. A structure comprising:a first fin comprising silicon and including a first region over a second region;
a gate stack adjacent to a sidewall surface of the first region, wherein the gate stack includes a gate dielectric and a gate electrode;
a first source and a first drain coupled to the first region;
a first dielectric layer adjacent to a sidewall surface of the second region, wherein the first dielectric layer comprises an impurity that is also present within the second region and associated with a conductivity type;
a second fin comprising silicon and including a third region over a fourth region;
a second gate stack is adjacent to a sidewall surface of the third region;
a second source and a second drain coupled to the third region;
a second dielectric layer adjacent to a sidewall surface of the fourth region; and
an isolation material between the first gate stack and a substrate surface that intersects the sidewall surface of the second region, wherein the isolation material is further between the first dielectric layer and the second dielectric layer, and wherein the isolation material comprises a plurality of dielectric layers including a layer comprising silicon and nitrogen that is adjacent to the first dielectric layer and is adjacent to the second dielectric layer.

US Pat. No. 10,340,272

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A manufacturing method of a semiconductor device, comprising:providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region adjacent to the first region;
forming a barrier layer on the semiconductor substrate, wherein the barrier layer is formed in the first region and the second region;
performing a first etching process for thinning the barrier layer in the first region, wherein after the first etching process, the barrier layer comprises:
a first part at least partially disposed in the first region and having a first thickness; and
a second part disposed in the second region and having a second thickness, wherein the first thickness is less than the second thickness;
forming a first work function layer on the barrier layer in the first region and the second region after the first etching process; and
performing a second etching process to remove the first work function layer in the first region.

US Pat. No. 10,340,271

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor structure, comprising:providing a semiconductor substrate having a first region, a second region, and an isolation region between the first region and the second region;
forming a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region;
forming an isolation structure, covering portions of side surfaces of the first fins and the second fins and with a top surface below the top surfaces of the first fins and the second fins, over the semiconductor substrate; and
forming an isolation layer over the isolation structure in the isolation region and with a top surface coplanar or above the top surfaces of the first fins and the second fins, wherein forming the isolation layer comprises:
forming a sacrificial layer over the isolation structure, the first fins and the second fins and exposing a portion of the isolation structure in the isolation region;
forming an initial isolation layer on exposed portion of the isolation structure and on the sacrificial layer;
removing a portion of the initial isolation layer on the sacrificial layer; and
removing the sacrificial layer.

US Pat. No. 10,340,270

INTEGRATED CIRCUIT HAVING FINFETS WITH DIFFERENT FIN PROFILES

Taiwan Semiconductor Manu...

1. A method of forming an integrated circuit, comprising:forming a first top fin, a second top fin, and a third top fin extending from a substrate;
forming a first mask over the first top fin;
forming a second mask over the second top fin and the third top fin;
removing a portion of the substrate to form a first base fin and a second base fin, the first top fin extending from the first base fin, the second top fin and the third top fin extending from the second base fin; and
after removing the portion of the substrate to form the first base fin and the second base fin, reducing a width of the first base fin.

US Pat. No. 10,340,269

CONTACT RESISTANCE REDUCTION TECHNIQUE

Taiwan Semiconductor Manu...

1. A device comprising:a fin extending from a substrate;
a gate structure on a top surface and sidewalls of the fin;
a strained material stack on the fin adjacent the gate structure, the strained material stack comprising:
a first boron-doped (B-doped) silicon-germanium (SiGeB) layer on the fin;
a second SiGeB layer on the first SiGeB layer, the second SiGeB layer having a higher concentration of Ge than the first SiGeB layer;
a B-doped germanium-tin (GeSnB) layer on the second SiGeB layer; and
a third SiGeB layer on the GeSnB layer;
a metal-silicide layer on the third SiGeB layer; and
a metal contact on the metal-silicide layer.

US Pat. No. 10,340,268

FINFET STRUCTURE AND FABRICATING METHOD OF GATE STRUCTURE

UNITED MICROELECTRONICS C...

1. A FinFET structure, comprisinga fin structure;
a first gate structure disposed on the fin structure, wherein the first gate structure comprises:
a first gate electrode;
a first silicon oxide layer contacting the fin structure and disposed directly under the first gate electrode, wherein the first silicon oxide layer is an integral monolithic structure;
a silicon nitride layer contacting the silicon oxide layer;
a first gate dielectric layer disposed between the first gate electrode and the silicon nitride layer; and
a dielectric layer disposed at two sides of the first gate electrode;
a second gate structure disposed on the fin structure, wherein the second gate structure comprises:
a second gate electrode;
a second silicon oxide layer; and
a second gate dielectric layer between the second gate electrode and the second silicon oxide layer, wherein the second gate dielectric layer does not cover the silicon nitride layer and the first silicon oxide layer;
first source/drain doped regions disposed in the fin structure at two sides of the first gate electrode; and
second source/drain doped regions disposed in the fin structure at two sides of the second gate electrode, wherein the first silicon oxide layer extends to contact the first source/drain doped regions and the second source/drain doped regions, and a portion of the first silicon oxide layer contacts the first source/drain doped regions, the dielectric layer contacts the portion of the first silicon oxide layer.

US Pat. No. 10,340,267

SEMICONDUCTOR DEVICES INCLUDING CONTROL LOGIC LEVELS, AND RELATED MEMORY DEVICES, CONTROL LOGIC ASSEMBLIES, ELECTRONIC SYSTEMS, AND METHODS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a stack structure comprising decks each comprising:
a memory element level comprising memory elements; and
a control logic level in electrical communication with the memory element level and comprising control logic devices, at least one of the control logic devices of the control logic level of one or more of the decks comprising at least one device exhibiting transistors laterally displaced from one another.

US Pat. No. 10,340,266

ESD PROTECTION CIRCUIT AND METHOD OF MAKING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:a substrate including a device region with an electrostatic discharge (ESD) protection circuit;
a gate over the device region;
a source region in the device region having a n-type (N+) implant and a p-type (P+) implant laterally separated on a first side of the gate;
a drain region in the device region on a second side of the gate, opposite the first;
another N+ implant, wherein an edge of each N+ implant is aligned with an opposite edge of the source region and the P+ implant is laterally separated therebetween; and
a low-voltage p-well (LVPW) formed in the device region prior to a formation of each of the N+ and P+ implants and wherein the N+ and P+ implants and a portion of the another N+ implant are in the LVPW.

US Pat. No. 10,340,265

COMPACT PROTECTION DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGE

STMicroelectronics SA, M...

1. An integrated circuit, comprising:a power supply terminal configured to receive a power supply voltage,
a reference terminal configured to receive a reference voltage,
a first signal terminal configured to receive or transmit a signal,
a first protection device coupled between said first signal terminal and the power supply terminal, the first protection device including a first MOS transistor having a first electrode coupled to said first signal terminal and a second electrode coupled to the power supply terminal,
a second protection device coupled between said first signal terminal and the reference terminal, the second protection device comprising a second MOS transistor having a first electrode coupled to said first signal terminal and a second electrode coupled to the reference terminal,
wherein gates of the first and second MOS transistors are directly connected to the reference terminal, and substrates of the first and second MOS transistors are directly connected to a first terminal of a common resistor and the reference terminal is directly connected to a second terminal of the common resistor.

US Pat. No. 10,340,264

SEMICONDUCTOR DEVICE COMPRISING A CLAMPING STRUCTURE

Infineon Technologies Aus...

1. A semiconductor device, comprising:a semiconductor body comprising a clamping structure including a first pn junction diode and a second pn junction diode serially connected back to back between a first contact and a second contact; and
a power transistor including first and second load terminals and a control terminal,
wherein the clamping structure is electrically connected between the control terminal and the second load terminal,
wherein the second load terminal is a drain contact of an insulated gate field effect transistor, a collector contact of an insulated gate bipolar transistor, or a collector contact of a bipolar junction transistor,
wherein the control terminal is a corresponding contact of a gate of the insulated gate field effect transistor, a gate of the insulated gate bipolar transistor, or a base of the bipolar junction transistor,
wherein a breakdown voltage of the first pn junction diode is greater than 100 V,
wherein a breakdown voltage of the second pn junction diode is greater than 10 V.

US Pat. No. 10,340,263

INTEGRATED CIRCUIT FOR REDUCING OHMIC DROP IN POWER RAILS

SAMSUNG ELECTRONICS CO., ...

1. An integrated circuit comprising:a plurality of power rail pairs, wherein each of the plurality of power rail pairs includes one of a plurality of high power rails configured to provide a first power supply voltage and one of a plurality of low power rails configured to provide a second power supply voltage that is lower than the first power supply voltage; and
a circuit chain including a plurality of unit circuits that are cascade-connected such that an output of a previous unit circuit is provided as an input of a next unit circuit, wherein the plurality of unit circuits are connected distributively to the plurality of power rail pairs,
wherein the plurality of high power rails and the plurality of low power rails extend in a row direction and are arranged alternatively one by one in a column direction to form boundaries of a plurality of circuit rows that are arranged in the column direction.

US Pat. No. 10,340,261

SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CHIPS CONNECTED BY HYBRID BONDING METHOD

Micron Technology, Inc., ...

1. An apparatus comprising:a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays; and
a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits,
wherein the first and second semiconductor chips are stacked with each other so that each of the plurality of first bonding electrodes is electrically connected to an associated one of the plurality of second bonding electrodes,
wherein each of the memory cell arrays includes a plurality of first signal lines extending in a first direction, a plurality of second signal lines extending in a second direction different from the first direction, and a plurality of memory cells each disposed on an associated one of intersections of the plurality of first and plurality of second signal lines,
wherein the plurality of memory cell arrays include first and second memory cell arrays adjacent in the second direction to each other,
wherein the plurality of first bonding electrodes include:
a first group located at one end of the first memory cell array in the first direction and electrically connected to predetermined ones of the plurality of first signal lines in the first memory cell array;
a second group located at another end of the first memory cell array in the first direction and electrically connected to remaining ones of the plurality of first signal lines in the first memory cell array; and
a third group located at one end of the second memory cell array in the first direction and electrically connected to predetermined ones of the plurality of first signal lines in the second memory cell array, a position of the third group in the first direction being located between positions of the first and second groups in the first direction.

US Pat. No. 10,340,260

MAGNETIC SMALL FOOTPRINT INDUCTOR ARRAY MODULE FOR ON-PACKAGE VOLTAGE REGULATOR

Intel Corporation, Santa...

1. An electronic assembly including:a first IC including contact pads and a voltage regulator circuit; and
an inductor module including:
a module substrate including a magnetic dielectric material;
a first surface at the top of the inductor module and a second surface at the bottom of the inductor module;
a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil oriented to extend in the direction from the first surface to the second surface and including a first end and a second end and a core, wherein the coil core includes the magnetic dielectric material; and
a plurality of conductive contact pads electrically coupled to the first and second coil ends, wherein contact pads electrically coupled to the first coil ends are arranged on the first surface, and the contact pads electrically coupled to the second coil ends are arranged on the second surface;
wherein the first IC is arranged on a surface of the inductor module and wherein at least a portion of the contact pads of the inductor module are electrically coupled to the contact pads of the voltage regulator circuit.

US Pat. No. 10,340,259

METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE

MediaTek Inc., Hsin-Chu ...

1. A method for fabricating a semiconductor package, comprising:providing a carrier;
adhering semiconductor dice to a top surface of the carrier by an adhesive that is in direct physical contact with the top surface of the carrier, wherein each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface, and wherein a plurality of input/output (I/O) pads are distributed on the active surface of each of the semiconductor dice;
printing interconnect features, the printing comprising:
printing a first conductive pad on the carrier;
printing a second conductive pad on the active surface of at least one of the semiconductor dice; and
printing a conductive wire connecting the first and second conductive pads, wherein the interconnect features comprise the first conductive pad, the second conductive pad and the conductive wire;
encapsulating the top surface of the carrier, the semiconductor dice and the interconnect features with an encapsulant; and
removing the carrier.

US Pat. No. 10,340,258

INTERCONNECT STRUCTURES, PACKAGED SEMICONDUCTOR DEVICES, AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. An interconnect structure, comprising:a polymer material; and
a conductive line comprising:
a post passivation interconnect (PPI) pad disposed above an uppermost surface of the polymer material; and
a PPI line disposed below the uppermost surface of the polymer material, wherein:
the PPI line is coupled to the PPI pad through a transition structure;
the transition structure is interposed between and different than the PPI line and the PPI pad;
the transition structure extends over the polymer material;
the transition structure has an uppermost surface disposed above an uppermost surface of the PPI line;
in a top-down view, the transition structure has a shape that tapers from a first width of the uppermost surface of the transition structure to a second width of the lowermost surface of the transition structure; and
the first width is greater than the second width.

US Pat. No. 10,340,257

DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION METHOD THEREOF

LG ELECTRONICS INC., Seo...

1. A display device, comprising:a plurality of semiconductor light emitting device packages;
a wiring substrate coupled to the plurality of semiconductor light emitting device packages; and
a plurality of wiring electrodes disposed on the wiring substrate,
wherein each of the plurality of semiconductor light emitting device packages comprises:
a plurality of semiconductor light emitting devices;
a support substrate coupled to the plurality of semiconductor light emitting devices; and
a conversion layer disposed to cover the plurality of semiconductor light emitting devices and configured to convert a color of light emitted from at least some of the plurality of semiconductor light emitting devices to a different color such that a red sub-pixel, a green sub-pixel, and a blue sub-pixel are formed, and
wherein:
at least a first semiconductor light emitting device that corresponds to the red sub-pixel or a second semiconductor light emitting device that corresponds to the green sub-pixel, among the plurality of semiconductor light emitting devices, has a light emitting area that has a different size compared to a size of a light emitting area of a third semiconductor light emitting device that corresponds to the blue sub-pixel among the plurality of semiconductor light emitting devices;
the support substrate is formed of a silicon material, and a plurality of through silicon vias are formed on the support substrate;
at least one through silicon via of the plurality of through silicon vias is electrically connected to first conductive electrodes of the plurality of semiconductor light emitting devices; and
other through silicon vias of the plurality of through silicon vias, except for the at least one through silicon via, are electrically connected to second conductive electrodes of the plurality of semiconductor light emitting devices.

US Pat. No. 10,340,256

DISPLAY DEVICES

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate having a surface comprising a display area and a non-display area adjacent to the display area;
a plurality of light-emitting diodes disposed on the display area of the substrate, wherein the light-emitting diode comprises a contact electrode;
an anisotropic conductive layer disposed between the substrate and the plurality of light-emitting diodes, wherein the anisotropic conductive layer has a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the anisotropic conductive layer is in a shape of a curve;
a covering layer contacting at least a portion of one of the plurality of light-emitting diodes, wherein the covering layer has a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the covering layer is in a shape of a curve; and
a connection structure disposed on the non-display area and/or the display area of the substrate, wherein the connection structure comprises an electrode having a cross-sectional sidewall profile, and at least a part of the cross-sectional sidewall profile of the electrode is in a shape of a curve.

US Pat. No. 10,340,255

SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor apparatus comprising:a package substrate; and
a semiconductor chip,
wherein the package substrate comprises a substrate pad coupled with a package ball,
wherein the semiconductor chip comprises:
a main pad coupled with the substrate pad;
a first buffer coupled with the main pad; and
an auxiliary pad coupled with the first buffer.

US Pat. No. 10,340,253

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A package structure, comprising:a first die and a second die side by side;
a first encapsulant, encapsulating sidewalls of the first die and sidewalls of the second die;
a bridge, electrically connecting the first die and the second die through two conductive bumps;
an underfill layer, filling the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsulant;
a second encapsulant over the first die and the second die, encapsulating sidewalls of the underfill layer and sidewalls of the bridge;
a dielectric layer, sandwiched between the first die and the second encapsulant, and between the second die and the second encapsulant; and
a redistribution layer (RDL) structure over the bridge, electrically connected to the first die and the second die though a plurality of through integrated fan-out vias (TIVs),
wherein bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.

US Pat. No. 10,340,252

HIGH VOLTAGE DEVICE WITH MULTI-ELECTRODE CONTROL

Texas Instruments Incorpo...

1. A high-voltage device, comprising:a low-voltage transistor (LVT) having a first drain node, a first control gate, and a first source node;
a high electron mobility transistor (HEMT) having a second drain node, a second source node, a second control gate, and a field electrode free of being electrically coupled to the second control gate and the second source node within the HEMT;
a first conductor external to the HEMT and the LVT, and coupling the field electrode of the HEMT to the first source node of the LVT; and
a second conductor external to the HEMT and the LVT, and coupling the second control gate of the HEMT to the first source node of the LVT.

US Pat. No. 10,340,251

METHOD FOR MAKING AN ELECTRONIC COMPONENT PACKAGE

NXP USA, Inc., Austin, T...

17. A method of making an electronic component package, the method comprising:applying a sacrificial material to a first glass carrier;
applying a second glass carrier to a top side of the sacrificial material;
curing the sacrificial material with UV radiation through the second glass carrier while the second glass carrier is applied to the top side;
after the curing, removing the second glass carrier from the sacrificial material, wherein the top side has a top surface defined by the second glass carrier, and wherein after the removing of the second glass carrier, an unfeatured area of the top surface has a roughness (Ra) of 1 nm or less;
after the removing, forming a redistribution structure over the top side of the sacrificial material, the redistribution structure including at least one redistribution layer;
attaching a plurality of electronic components to the redistribution structure;
after the attaching, encapsulating the plurality of electronic components to form an encapsulated panel that includes the redistribution structure;
removing the first glass carrier and the sacrificial material from the encapsulated panel after the encapsulating;
singulating the encapsulated panel into a plurality of electronic component packages, each electronic component package of the plurality of electronic component packages including at least one electronic component of the plurality of electronic components.

US Pat. No. 10,340,250

STACK TYPE SENSOR PACKAGE STRUCTURE

KINGPAK TECHNOLOGY INC., ...

1. A stack type sensor package structure, comprising:a substrate having an upper surface and a lower surface opposite to the upper surface, wherein the substrate includes a plurality of solder pads arranged on the upper surface;
at least one semiconductor chip mounted on the substrate;
a frame fixed on the upper surface of the substrate and surrounded by the solder pads, wherein the at least one semiconductor chip is in a space defined by the frame and the substrate and does not contact the frame, and the frame has a bearing plane above the at least one semiconductor chip;
a sensor chip having a top surface and a bottom surface opposite to the top surface, the sensor chip including a plurality of connecting pads arranged on the top surface thereof, wherein a size of the sensor chip is larger than that of the at least one semiconductor chip, and the bottom surface of the sensor chip is fixed on the bearing plane;
a plurality of wires each having a first end and a second end opposite to the first end, wherein the first ends of the wires are respectively connected to the solder pads, and the second ends of the wires are respectively connected to the connecting pads;
a transparent layer having a first surface and a second surface opposite to the first surface, wherein the second surface has a central region and a ring-shaped supported region encircling the central region;
a support having a ring-shaped structure and disposed on at least one of the top surface of the sensor chip and the bearing surface of the frame, wherein a top end of the support abuts against the supported region of the transparent layer; and
a package compound disposed on the upper surface of the substrate and covering a lateral side of the frame, at least part of a lateral side of the transparent layer, and a lateral side of the support, wherein at least part of each of the wires is embedded in the package compound,
wherein the substrate is recessed from the upper surface thereof to form an accommodating slot, and the at least one semiconductor chip is arranged in the accommodating slot,
wherein multiple semiconductor chips are included in the stack type sensor package structure, and the semiconductor chips are electrically connected to the substrate by wire bonding,
wherein the upper surface of the substrate has a wire bonding region arranged between the frame and the accommodating slot, and at least one of the semiconductor chips is electrically connected to the wire bonding region of the substrate by wire bonding.

US Pat. No. 10,340,249

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:forming a first opening in a first photosensitive adhesive layer, the first photosensitive adhesive layer being adjacent a first side of a first integrated circuit device;
plating a first reflowable layer in the first opening;
forming a second opening in a second photosensitive adhesive layer, the second photosensitive adhesive layer being adjacent a first side of a second integrated circuit device;
plating a second reflowable layer in the second opening;
pressing the first and second photosensitive adhesive layers together, thereby physically connecting the first and second integrated circuit devices; and
reflowing the first and second reflowable layers, thereby forming a conductive connector electrically connecting the first and second integrated circuit devices.

US Pat. No. 10,340,248

BONDING SYSTEMS

TOKYO ELECTRON LIMITED, ...

1. A bonding system comprising:a substrate transfer device configured to transfer a first substrate and a second substrate in an atmospheric pressure atmosphere;
a surface modifying apparatus configured to modify surfaces of the first substrate and the second substrate in a depressurized atmosphere;
a load lock chamber configured to perform delivery of the first substrate and the second substrate between the load lock chamber and the substrate transfer device and between the load lock chamber and the surface modifying apparatus, and configured to switch an internal atmosphere of the load lock chamber between the atmospheric pressure atmosphere and the depressurized atmosphere;
a surface hydrophilizing apparatus configured to hydrophilize the modified surfaces of the first substrate and the second substrate; and
a bonding apparatus configured to bond the hydrophilized surfaces of the first substrate and the second substrate by an intermolecular force,
wherein the substrate transfer device transfers the first substrate and the second substrate to and from the load lock chamber, to and from the surface hydrophilizing apparatus, and to and from the bonding apparatus, and
wherein the load lock chamber sets the internal atmosphere to be the atmospheric pressure atmosphere when the first substrate and the second substrate are delivered between the load lock chamber and the substrate transfer device, and sets the internal atmosphere to be the depressurized atmosphere when the first substrate and the second substrate are delivered between the load lock chamber and the surface modifying apparatus.

US Pat. No. 10,340,246

WIRE BALL BONDING IN SEMICONDUCTOR DEVICES

TEXAS INSTRUMENTS INCORPO...

1. A method of interconnecting components of a semiconductor device using wire bonding, the method comprising:providing a coated-aluminum wire, the coated-aluminum wire having a coating that comprises palladium;
forming a free air ball from a first end of the coated-aluminum wire, wherein during the formation of the free air ball, the coating is removed from at least a portion of the free air ball;
bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the free air ball and the aluminum surface layer of the bond pad form a substantially homogenous, aluminum-to-aluminum ball bond; and
bonding a second, opposing end of the coated-aluminum wire to a lead on a lead frame, the lead having a palladium surface layer, wherein the second end of the coated-aluminum wire and the lead form a substantially homogenous, palladium-to-palladium bond.

US Pat. No. 10,340,245

FAN-OUT SEMICONDUCTOR PACKAGE MODULE

Samsung Electro-Mechanics...

1. A fan-out semiconductor package module comprising:a fan-out semiconductor package including a first interconnection member having a through-hole;
a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip and filling at least a portion of space between walls of the through-hole and side surfaces of the semiconductor chip;
a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip;
first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the encapsulant; and
a component package including a wiring substrate and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate, the wiring substrate being disposed above the second interconnection member and connected to the second interconnection member through the first connection terminals,
wherein the first interconnection member and the second interconnection member each include a redistribution layer electrically connected to the connection pads of the semiconductor chip, and
the component package is disposed on a first surface side of the second interconnection member and the active surface of the semiconductor chip is disposed on a second surface side of the second interconnection member, the second surface being opposite the first surface,
wherein an electrical pathway at least traverses the connection pad, a first redistribution pattern of the redistribution layer of the second interconnection member, a first terminal of the first connection terminals, a wiring layer of the wiring substrate, a second terminal of the first connection terminals, a second redistribution pattern of the redistribution layer of the second interconnection member, the redistribution layer of the first interconnection member, and the second connection terminal in that sequence,
wherein the second terminal of the first connection terminals is spaced apart from the first terminal of the first connection terminals, and the second redistribution pattern of the second interconnection member is spaced apart from the first redistribution pattern of the second interconnection member.

US Pat. No. 10,340,244

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor device comprising:a low-density substrate;
a high-density patch positioned inside a cavity in the low-density substrate, the high-density patch comprising a base plate and a high-density redistribution structure, wherein the high-density redistribution structure comprises one or more high-density circuit traces on the base plate;
a first semiconductor die including high-density bumps and low-density bumps; and
a second semiconductor die including high-density bumps and low-density bumps,
wherein the high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the one or more high-density circuit traces of the high-density patch, and the low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

US Pat. No. 10,340,243

CIRCUIT SUBSTRATE AND METHOD FOR MANUFACTURING CIRCUIT SUBSTRATE

FUJI XEROX CO., LTD., To...

1. A circuit substrate comprising:a base material; and
a capacitor layer including:
a first metal layer on the base material;
a dielectric layer on the first metal layer; and
a second metal layer on the dielectric layer,
wherein the first metal layer includes a first electrode region on the base material, which is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit through the capacitor layer is to be connected, and
wherein the second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is to be connected.

US Pat. No. 10,340,242

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate including a first surface and a second surface opposite to the first surface;
a package over the substrate;
a plurality of first conductors over the substrate;
a plurality of second conductors over the substrate, wherein the plurality of first conductors and the plurality of the second conductors are substantially at a same tier, and a width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors;
a plurality of first bonding pads on the substrate and configured to receive and electrically connect to the plurality of first conductors, respectively;
a plurality of second bonding pads on the substrate and configured to receive and electrically connect to the plurality of second conductors, respectively; and
a passivation layer over the substrate, wherein the passivation layer includes a plurality of first recesses exposing the plurality of first bonding pads respectively, and a plurality of second recesses exposing the plurality of second bonding pads respectively, and a width of the first recess is wider than a width of the second recess, wherein the first conductor is apart from an edge of the respective first recess, and the second conductor is in contact with an edge of the respective second recess.

US Pat. No. 10,340,241

CHIP-ON-CHIP STRUCTURE AND METHODS OF MANUFACTURE

INTERNATIONAL BUSINESS MA...

1. A method, comprising:placing a powder on a semiconductor substrate;
sintering the powder to form a plurality of pillars directly in contact with the semiconductor substrate;
repeating the placing and sintering steps until the plurality of pillars reach a predetermined height;
forming a solder cap on the plurality of pillars;
removing non-sintered powder by a cleaning process;
joining the semiconductor substrate to a board using the solder cap and a thermal reflow process;
joining a chip to the semiconductor substrate by a reflow process; andunderfilling empty spaces between the chip, the semiconductor substrate and the board, wherein:the semiconductor substrate is a wafer placed in a chuck and coated with a plurality of layers of the powder, followed by the laser sintering after each coating to form the pillars directly in contact with the wafer;
joining the chip to the wafer between the pillars;
dicing the wafer to form a plurality chips with the pillars;
bonding a chip without the pillars to a substrate of another chip of a plurality of chips between the pillars;
the chip without the pillars including plating of micro-bumps; and
wherein the board is an organic laminate and the organic laminate is bonded to the another chip by the pillars by a reflow of the solder cap at a reflow temperature of about 250° C. to about 260° C.

US Pat. No. 10,340,240

MECHANISMS FOR FORMING POST-PASSIVATION INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:an integrated circuit;
an insulating layer overlying the integrated circuit;
a post-passivation interconnect layer over the insulating layer;
a connector electrically connected to the post-passivation interconnect layer, the connector including:
a bump comprising a first material, and
a diffusion barrier region enclosing the bump and comprising the first material doped with a dopant, a material composition of the diffusion barrier region being different than a material composition of the bump; and
a molding compound layer over the post-passivation interconnect layer and around a bottom portion of the connector, wherein a topmost surface of the molding compound layer is disposed at a level between a topmost point of the bump and a bottommost point of the bump, wherein the level of the topmost surface of the molding compound layer is further disposed between a first point of the diffusion barrier region and a second point of the diffusion barrier region, the first point of the diffusion barrier region is above and contacting the topmost point of the bump, the second point of the diffusion barrier region is below and contacting the bottommost point of the bump.

US Pat. No. 10,340,239

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

Cufer Asset Ltd. L.L.C, ...

1. A method comprising:depositing, in physical contact with at least a portion of multiple chips, a temperature-conductive liquidus or gel material on a rigid body;
hardening the temperature-conductive liquidus or gel material to constrain at least a portion of each of the multiple chips such that the hardened material and the multiple chips behave as part of the rigid body;
bringing a bonding surface of each of the multiple chips into contact with a bonding surface of an element, by uniformly applying a force on the rigid body to place the multiple chips under pressure without causing damage to the multiple chips or the bonding surface of the element; and
removing all of the hardened material from contact with the multiple chips.

US Pat. No. 10,340,238

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A wiring substrate comprising:a first wiring structure including
a first insulation layer formed from a thermosetting insulative resin and including a reinforcement material,
a recess formed in a lower surface of the first insulation layer,
a first wiring layer with which the recess is filled, and
a via wiring including an upper end surface exposed from an upper surface of the first insulation layer, wherein the via wiring extends in a thickness-wise direction through the first insulation layer and is connected to the first wiring layer;
a protective insulation layer formed on the lower surface of the first insulation layer; and
a second wiring structure laminated on the upper surface of the first insulation layer, wherein the second wiring structure includes
at least one second insulation layer formed from an insulative resin of which main component is a photosensitive resin, and
two or more second wiring layers;
wherein the upper surface of the first insulation layer and the upper end surface of the via wiring are polished surfaces,
the first wiring layer includes a lower surface formed to be flush with the lower surface of the first insulation layer or recessed from the lower surface of the first insulation layer toward the second wiring structure,
the second wiring structure has a wiring density that is higher than a wiring density of the first wiring structure, and
the reinforcement material is located toward the second wiring structure from a thickness-wise center of the first insulation layer and is located at a thickness-wise center of a thickness from the lower surface of the first insulation layer to an upper surface of an uppermost one of the two or more second wiring layers.

US Pat. No. 10,340,237

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KOKUSAI ELECTRIC CORPORAT...

1. A method of manufacturing a semiconductor device, comprising:(a) loading a substrate into a process chamber, the substrate comprising a conductive film and an insulating film formed around the conductive film to expose the conductive film; and
(b) forming a protective film selectively on an upper surface of the insulating film without forming the protective film on the conductive film by supplying into the process chamber a process gas comprising a component reactive with a desorbed gas generated from the insulating film.

US Pat. No. 10,340,236

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a semiconductor substrate;
a top metal layer over the semiconductor substrate;
a first passivation layer over and in physical contact with the top metal layer;
a first redistribution layer over and in physical contact with the first passivation layer;
a first polymer layer over and in physical contact with the first redistribution layer;
an encapsulant in physical contact with the semiconductor substrate, the first passivation layer, and the first polymer layer, wherein the encapsulant contacts a first sidewall and a second sidewall of the first polymer layer, and wherein at least a portion of the first polymer layer extends above a top surface of the encapsulant; and
a first conductive via extending through the first polymer layer and in electrical connection with the first redistribution layer, the first conductive via being laterally separated from the encapsulant, wherein a top surface of the first conductive via extends above a top surface of the encapsulant.

US Pat. No. 10,340,234

SUBSTRATE HAVING EMBEDDED ELECTRONIC COMPONENT

Samsung Electro-Mechanics...

1. A substrate having an electronic component, comprising:a frame having a through hole with the electronic component disposed in the through hole;
a first wiring portion formed on a surface of the frame and the electronic component, comprising a wiring layer and a first insulating layer;
a first layer formed on the first wiring portion; and
a second wiring portion formed on the first layer, comprising an antenna layer,
wherein the first layer is formed of a first material different from a second material of the second wiring portion, and
wherein the first layer comprises a via connecting a pattern layer of the first wiring portion and the antenna layer of the second wiring portion.

US Pat. No. 10,340,233

MILLIMETER WAVE CONNECTORS TO INTEGRATED CIRCUIT INTERPOSER BOARDS

Lockheed Martin Corporati...

1. An apparatus comprising:a connector to receive a millimeter wave signal, the connector including a signal pin;
a pin landing pad conductively coupled to the signal pin, the pin landing pad including a transition portion;
a transmission line coupling the pin landing pad to an input/output (I/O) pad of an integrated circuit; and
an interposer comprising a multilayer printed circuit board (PCB) comprising metallization layers and dielectric layers and including the pin landing pad, the transmission line, and the I/O pad of the integrated circuit, wherein a metallization under the pin landing pad is removed and a dielectric material of the dielectric layers comprises prepreg.

US Pat. No. 10,340,231

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor package structure, comprising:a semiconductor die comprising an active surface, a back surface and a sidewall surface between the active surface and the back surface, wherein the active surface of the semiconductor die has a contact pad therein;
a molding layer covering the back surface and the sidewall surface of the semiconductor die; and
an inductor in the molding layer, wherein the sidewall surface of the semiconductor die faces toward the inductor, wherein a lower surface of the molding layer is coplanar with a lower surface of the inductor, and wherein an upper surface of the contact pad is coplanar with an upper surface of the inductor.

US Pat. No. 10,340,230

SEMICONDUCTOR CHIP

United Microelectronics C...

1. A semiconductor chip, comprising:at least one interlayer dielectric layer, disposed on a substrate;
a transmission pattern, disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip, wherein the transmission pattern is electrically connected to an external signal source;
a stress absorption structure, disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern, wherein the stress absorption structure is covered by the transmission pattern.

US Pat. No. 10,340,229

SEMICONDUCTOR DEVICE WITH SUPERIOR CRACK RESISTIVITY IN THE METALLIZATION SYSTEM

GLOBALFOUNDRIES Inc., Gr...

1. A semiconductor device, comprising:a metallization system including a last metallization layer, said last metallization layer comprising a first metal region and a second metal region laterally separated from and adjacent to said first metal region;
a passivation layer formed above said last metallization layer;
a first contact pad formed in said passivation layer so as to be in contact with said first metal region, wherein said first contact pad overlaps a portion of said second metal region in a height direction perpendicular to an upper surface of said first contact pad, and
a second contact pad formed in said passivation layer adjacent to said first contact pad so as to be in contact with said second metal region and overlap a portion of said first metal region in a height direction perpendicular to an upper surface of said second contact pad.

US Pat. No. 10,340,228

FABRICATION METHOD OF SEMICONDUCTOR PACKAGE

Siliconware Precision Ind...

1. A method for fabricating a semiconductor package, comprising the steps of:providing a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface;
disposing at least a semiconductor element on the first top surface of the circuit structure, wherein the semiconductor element is electrically connected to the circuit structure;
forming an encapsulant on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface;
thinning the encapsulant from the second top surface thereof; and
forming a strengthening layer on the second top surface of the encapsulant and forming an adhesive layer between the encapsulant and the strengthening layer, wherein the strengthening layer and the adhesive layer are free from being removed, and the strengthening layer is made of a semiconductor material.

US Pat. No. 10,340,227

METHOD FOR PROCESSING A DIE

Infineon Technologies AG,...

1. A die, comprising:a die body; and
at least one of a front side metallization structure on a front side of the die body and a back side metallization structure on a back side of the die body such that the die is configured to be planar at a die attach process temperature range or to have a positive radius of curvature at the die attach process temperature range, wherein the back side metallization structure is electrically conductive and comprises impurities configured to exert a compressive stress onto the die body that is greater than a compressive stress of the front side metallization structure at the die attach process temperature range.

US Pat. No. 10,340,226

INTERCONNECT CRACK ARRESTOR STRUCTURE AND METHODS

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first contact pad on a first semiconductor substrate;
a first crack stopper on the first contact pad, the first crack stopper comprising a first wire that is wire bonded to the first contact pad on the first semiconductor substrate, the first wire having a first portion directly bonded to the first contact pad, the first portion having non-parallel sidewalls comprising a ball or wedge shape at an interface with the first contact pad, the first wire having a second portion continuous with the first portion, the second portion having parallel sidewalls extending from the first portion, the second portion being narrower than the first portion;
a protective layer surrounding sides of the first wire; and
solder surrounding the first crack stopper.

US Pat. No. 10,340,225

METHODS AND MODULES RELATED TO SHIELDED LEAD FRAME PACKAGES

Skyworks Solutions, Inc.,...

1. A method for providing electro-magnetic interference shielding for a radio-frequency module, the method comprising:applying a metal-based covering over a portion of a lead-frame package, the lead-frame package having a plurality of pins with at least one pin exposed from overmold compound and in contact with the metal-based covering, the lead-frame package including an inner row and an outer row of pins on each side, and all the pins of all the outer rows of pins assigned to ground;
mounting the lead-frame package on a substrate; and
connecting the metal-based covering to a ground plane of the substrate.

US Pat. No. 10,340,224

MICROWAVE AND MILLIMETER WAVE PACKAGE

Mitsubishi Electric Corpo...

1. A microwave and millimeter wave package comprising:a conductor base plate having a semiconductor element fixed to an upper surface thereof;
a side wall provided on the conductor base plate to surround the semiconductor element, the side wall having a conductor portion electrically connected to the conductor base plate;
a dielectric cap disposed on the side wall to form an internal space together with the conductor base plate and the side wall;
a front-side metal film provided on an entire front-side of the dielectric cap;
a first back-side metal film provided on an inner surface of the dielectric cap such that a center of the first back-side metal film approximately coincides with a center of a surface of the dielectric cap which faces the conductor base plate; and
a plurality of vias provided to pass through the dielectric cap and achieve electrical connection between the front-side metal film and the first back-side metal film and electrical connection between the front-side metal film and the conductor portion of the side wall, wherein
the first back-side metal film has, in a plan view, any one of a rectangular shape, a circular shape, an oval shape, and a polygonal shape,
the first back-side metal film comprises an opening portion in the first back-side metal film, the opening portion having a shape approximately similar to the shape of the first back-side metal film and having a small area, centers of the opening portion and the first back-side metal film approximately coinciding with each other, and
a width of the first back-side metal film of the opening portion is in a range of 1/16 to 3/16 of the wavelength for the lowest-order cavity resonant frequency.

US Pat. No. 10,340,223

METHOD OF FORMING AN INTERCONNECT STRUCTURE HAVING AN AIR GAP AND STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:embedding a conductive material into a dielectric layer to form a first conductive feature and a second conductive feature, the first conductive feature having a first width;
sealing the first conductive feature with a first etch stop layer;
removing a first portion of the first etch stop layer to form an exposed portion of the first conductive feature, the exposed portion having a second width less than the first width, wherein the removing the first portion also removes a portion of the dielectric layer to form a first opening;
re-sealing the first conductive feature with a second etch stop layer after the removing the first portion of the first etch stop layer, the second etch stop layer extending into the first opening; and
depositing a dielectric material to seal a void within the first opening.

US Pat. No. 10,340,222

STAIR CONTACT STRUCTURE, MANUFACTURING METHOD OF STAIR CONTACT STRUCTURE, AND MEMORY STRUCTURE

MACRONIX INTERNATIONAL CO...

1. A stair contact structure adjacent to a memory array, comprising:a plurality of layers of stacking structures, wherein each stacking structure comprises a conductive layer and an insulating layer, and the conductive layers and the insulating layers are interlaced; and
a first etch stop layer penetrating through the stacking structures vertically and extending along a first horizontal direction, wherein the conductive layers of the stacking structures located at a first sidewall of the first etch stop layer have a plurality of contact points, and the contact points are arranged along the first horizontal direction to form a stair structure having a plurality of stages, wherein a length along the first horizontal direction of one of the conductive layers of said each stacking structure is smaller than a length along the first horizontal direction of one of the insulating layers positioned on and directly contacting said one of the conductive layers of said each stacking structure;
wherein the stair contact structure and the memory array are disposed along a second horizontal direction vertical to the first horizontal direction.

US Pat. No. 10,340,221

STACKED FINFET ANTI-FUSE

International Business Ma...

1. A method of forming a semiconductor structure, said method comprising:providing a stacked fin structure on a surface of a first insulator layer, the stacked fin structure comprising a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion;
doping the first semiconductor fin portion and the second semiconductor fin portion;
removing the insulator fin portion;
growing a first highly doped epitaxial structure about the first semiconductor fin portion and a second highly doped epitaxial structure about the second semiconductor fin portion, wherein the first highly doped epitaxial structure has lower-most apex overlying and aligned with an upper-most apex of the second highly doped epitaxial structure, the lower-most apex separated from the upper-most portion by a gap; and
forming a second insulating layer about the first highly-doped epitaxial layer and the second highly-doped epitaxial layer, wherein the second insulator layer fills the gap.

US Pat. No. 10,340,220

COMPOUND LATERAL RESISTOR STRUCTURES FOR INTEGRATED CIRCUITRY

Intel Corporation, Santa...

17. A system on a chip (SOC), comprising:processor logic circuitry;
memory circuitry coupled to the processor logic circuitry;
RF circuitry coupled to the processor logic circuitry and including radio transmission circuitry and radio receiver circuitry; and
power management circuitry including an input to receive a DC power supply and an output coupled to at least one of the processor logic circuitry, memory circuitry, and RF circuitry, wherein at least one of the processor logic circuitry, memory circuitry, RF circuitry, or power management circuitry include both:
a resistor trace over a substrate, a length of the resistor trace comprising a first resistive material in contact a sidewall of a second resistive material;
a first dielectric material over the first resistive material, but not the second resistive material; and
a pair of resistor contacts coupled to opposite ends of the resistive trace and separated by the length; and
a transistor further comprising:
a gate stack over a semiconductor body, the gate stack including a gate electrode over a gate dielectric;
a semiconductor source and drain on opposite sides of the gate stack; and
source and drain contacts on the semiconductor source and drain, and separated from the gate stack by a spacer dielectric material that is also on a sidewall of the first dielectric.

US Pat. No. 10,340,219

SEMICONDUCTOR DEVICE HAVING A METAL VIA

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate having a device isolation region defining an active region;
an active fin positioned in the active region and extended in a first direction;
a gate structure overlapping the active fin along a direction orthogonal to an upper surface of the substrate and extended in a second direction intersecting the first direction;
a source/drain region disposed on the active fin;
a contact plug connected to the source/drain region, and overlapping the active region along the direction orthogonal to the upper surface of the substrate;
a metal via positioned at a first level above the substrate, higher than an upper surface of the contact plug, and spaced apart from the active region along the direction orthogonal to the upper surface of the substrate, wherein the metal via does not overlap the contact plug along the direction orthogonal to the upper surface of the substrate;
a metal line positioned at a second level above the substrate, higher than the first level, and connected to the metal via; and
a via connection layer extended from an upper portion of the contact plug and connected to the metal via.

US Pat. No. 10,340,218

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE COMPRISING PLURALITY OF THROUGH HOLES USING METAL HARD MASK

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure comprising:forming a first portion of a dielectric layer to conceal a conductive structure;
removing some of the first portion of the dielectric layer to expose a top surface of the conductive structure, wherein a top of the first portion of the dielectric layer is at or above the top surface of the conductive structure after removing some of the first portion of the dielectric layer;
forming a second portion of the dielectric layer over the first portion of the dielectric layer and over the top surface of the conductive structure;
forming a metal hard mask over the dielectric layer;
patterning the metal hard mask to form a patterned metal hard mask;
patterning the first portion of the dielectric layer and the second portion of the dielectric layer with the patterned metal hard mask to define a first through hole extending through the first portion of the dielectric layer and the second portion of the dielectric layer; and
patterning the second portion of the dielectric layer with the patterned metal hard mask to define a second through hole extending through the second portion of the dielectric layer.

US Pat. No. 10,340,217

SEMICONDUCTOR DEVICE INCLUDING A CYLINDRICAL ELECTRODE INSERTED INTO A LOOPED PORTION OF AN ELECTRODE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor chip;
an electrode electrically connected to the semiconductor chip, the electrode including a looped portion;
a cylindrical electrode including a main portion having a screw thread formed therein and a narrow portion continuous with the main portion, the narrow portion having a smaller width than the main portion, the cylindrical electrode being electrically connected to the electrode by the narrow portion being inserted into the looped portion; and
a case for the semiconductor chip and the electrode, the case contacting the main portion and a top surface of the looped portion, while causing the screw thread and a connecting portion between the looped portion and the cylindrical electrode to be exposed.

US Pat. No. 10,340,215

CHIP ON FILM AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A chip on film comprising:a base material;
a plurality of mutually independent output pads extending in a first direction and disposed on a side of the base material;
a chip; and
a plurality of leads, in one-to-one correspondence with the output pads and extending in a second direction, wherein the leads are configured to connect corresponding output pads to the chip, the second direction is parallel to a plane where the output pads are located,
the output pads constitute at least one set of interdigitated electrode structures arranged in a direction perpendicular to the first direction,
the chip and the output pads are located on two sides of the base material, respectively, the leads comprise:
first leads disposed on the base material on a same side as the output pads, and
second leads disposed on the base material on a same side as the chip,
wherein, first ends of the first leads are connected with a part of output pads that constitute the interdigitated electrode structures, and second ends of the first leads are connected with the chip through first vias penetrating the base material,
first ends of the second leads are connected with another part of the output pads that constitute the interdigitated electrode structures through second vias penetrating the base material, and second ends of the second leads is connected with the chip.

US Pat. No. 10,340,214

CARRIER BASE MATERIAL-ADDED WIRING SUBSTRATE

SHINKO ELECTRIC INDUSTRIE...

1. A carrier base material-added wiring substrate comprising:a wiring substrate including
an insulation layer,
a wiring layer arranged on a lower surface of the insulation layer, and
a solder resist layer that covers the lower surface of the insulation layer and includes
an opening that exposes a portion of the wiring layer as an external connection terminal;
an adhesive layer including an opening that is in communication with the opening of the solder resist layer; and
a carrier base material that is adhered by the adhesive layer to the solder resist layer to form the carrier base material-added wiring substrate, wherein the carrier base material includes an opening that is in communication with the opening of the solder resist layer and the opening of the adhesive layer and exposes the external connection terminal,
wherein the opening of the carrier base material is tapered so that the diameter of the opening of the carrier base material decreases from a lower surface of the carrier base material toward an upper surface of the carrier base material, and the opening of the adhesive layer is tapered so that the diameter of the opening of the adhesive layer decreases from a lower surface of the adhesive layer toward an upper surface of the adhesive layer,
wherein each of the opening of the carrier base material and the opening of the adhesive layer has a diameter that is smaller than that of the opening of the solder resist layer, and
wherein the adhesive layer is a separation layer that is separable from the solder resist layer to remove the carrier base material and the adhesive layer from the carrier base material-added wiring substrate.

US Pat. No. 10,340,213

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor device comprising:a substrate comprising:
a first substrate side, a second substrate side opposite the first substrate side, and a plurality of perimeter substrate sides extending between the first substrate side and the second substrate side;
a central pattern exposed at the first substrate side;
a dielectric layer;
a plurality of conductive vias connected to the central pattern, extending through the dielectric layer, and exposed at the second substrate side; and
an edge pattern exposed at the perimeter substrate sides and completely extending around the substrate; and
a semiconductor die coupled to the first substrate side,
wherein:
the edge pattern comprises a plurality of conductive layers exposed at the perimeter substrate sides and positioned directly laterally from the dielectric layer in a direction parallel to the first and second substrate sides;
a first conductive layer of the plurality of conductive layers comprises a plurality of perimeter sides, and extends a first distance directly laterally from the dielectric layer; and
a second conductive layer of the plurality of conductive layers comprises a plurality of perimeter sides, each of which extends a second distance directly laterally from the dielectric layer and is coplanar with a respective one of the perimeter sides of the first conductive layer, wherein the second distance is different from the first distance.

US Pat. No. 10,340,211

SENSOR MODULE WITH BLADE INSERT

NXP B.V., San Jose, CA (...

1. A sensor module, comprising:a dual gauge lead frame, the lead frame including:
a die pad,
a plurality of lead fingers spaced around the die pad and extending generally perpendicularly thereto, wherein each of the lead fingers has a proximal end near to the die pad and a distal end farther from the die pad, and
two or more blade-type leads having proximal ends connected to the distal ends of two or more of the plurality of lead fingers, wherein the die pad and the plurality of lead fingers have a first thickness and the blade-type leads have a second thickness that is greater than the first thickness;
a first semiconductor die attached on a top surface of the die pad;
first electrical connections connecting electrodes on an active surface of the first semiconductor die to the proximal ends of respective ones of the plurality of lead fingers;
a plurality of passive devices, each passive device mounted on and connected across respective pairs of the plurality of lead fingers;
a mold compound covering the die pad, the first semiconductor die, the plurality of passive devices, the first electrical connections, and the proximal ends of the plurality of lead fingers and the two or more blade-type leads, wherein the mold compound forms a generally rectangular molded body.

US Pat. No. 10,340,210

SYSTEM IN PACKAGE DEVICE INCLUDING INDUCTOR

TEXAS INSTRUMENTS INCORPO...

1. A system in package (SIP) device, comprising:a first leadframe having a first surface and a second surface opposite the first surface;
an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps on the second surface of the first leadframe;
a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and
an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?m.

US Pat. No. 10,340,209

MIXED IMPEDANCE LEADS FOR DIE PACKAGES AND METHOD OF MAKING THE SAME

1. A die package comprising:a die having a plurality of connection pads;
a die substrate supporting a plurality of connection elements;
a first lead connected to at least one connection pad and having a first metal core with a first core diameter, and a dielectric layer surrounding the first metal core having a first dielectric thickness; and
a second lead connected to at least one connection pad and having a second metal core with a second core diameter, and a dielectric layer surrounding the second metal core having a second dielectric thickness, with the first dielectric thickness differing from the second dielectric thickness,
wherein the first lead has a first impedance and the second lead has a second impedance different from said first impedance, and
wherein at least one of the dielectric layers includes multiple layers of different dielectric compositions including a vapor barrier layer deposited over a second dielectric layer and being thinner than the second dielectric layer.

US Pat. No. 10,340,208

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor element;
a first lead having a first obverse surface on which the semiconductor element is mounted and a first reverse surface opposite to the first obverse surface;
a bonding member that bonds the semiconductor element to the first obverse surface; and
a resin package that encloses the semiconductor element and at least a portion of the first lead,
wherein the first lead is formed with a first groove recessed in the first obverse surface at a location spaced apart from the semiconductor element as viewed in a thickness direction of the semiconductor element, the first groove having a first inner surface and a second inner surface opposite to the first inner surface, the first inner surface being closer to the semiconductor element than is the second inner surface, and
an angle the first inner surface forms with respect to the thickness direction is smaller than an angle the second inner surface forms with respect to the thickness direction.

US Pat. No. 10,340,207

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor package comprising:a die pad;
a semiconductor chip provided on the die pad;
a lead frame separated from the die pad, the lead frame being electrically connected to a terminal of the semiconductor chip, the lead frame including a first part and a second part disposed between the first part and the die pad, an upper surface of the first part being located below an upper surface of the second part, the first part having a first surface perpendicular to a first direction, the first direction being from the die pad toward the lead frame, a lower end of the first surface being located above a lower surface of the second part and below an upper surface of the die pad; and
an insulating part provided on the die pad, the semiconductor chip, and the second part, the insulating part sealing the semiconductor chip.

US Pat. No. 10,340,206

DENSE REDISTRIBUTION LAYERS IN SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming a patterned first photo resist over a seed layer, wherein a first opening in the patterned first photo resist exposes the seed layer;
plating a first conductive material in the first opening on the seed layer;
removing the patterned first photo resist;
after removing the patterned first photo resist, forming a patterned second photo resist over and along sidewalls of the first conductive material, wherein a second opening in the patterned second photo resist exposes a portion of an upper surface and a sidewall of the first conductive material, wherein the second opening does not expose the seed layer in a cross-sectional view;
plating a second conductive material in the second opening on the first conductive material;
removing the patterned second photo resist;
after removing the patterned second photo resist, removing exposed portions of the seed layer; and
depositing a dielectric layer around the first conductive material and the second conductive material.

US Pat. No. 10,340,205

THROUGH SUBSTRATE VIAS WITH IMPROVED CONNECTIONS

Taiwan Semiconductor Manu...

1. A device comprising:a substrate;
an interconnect structure over the substrate, the interconnect structure comprising:
a plurality of low-k dielectric layers;
a plurality of metallization layers in the plurality of low-k dielectric layers and comprising metal pads, wherein the metal pads comprises copper; and
a dielectric layer over the plurality of metallization layers, wherein a k value of the dielectric layer is higher than k values of the plurality of low-k dielectric layers;
a through-substrate via (TSV) extending from a top surface of the dielectric layer to a bottom surface of the substrate;
a first deep conductive via extending from the top surface of the dielectric layer and terminating on a first metal pad in a first one of the plurality of metallization layers;
a second deep conductive via extending from the top surface of the dielectric layer and terminating on a second metal pad in a second one of the plurality of metallization layers different from the first one; and
a metal line over the dielectric layer and electrically coupling the TSV to the first and the second deep conductive vias.

US Pat. No. 10,340,204

SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate including an integrated circuit and an electrical contact, the electrical contact electrically connected to the integrated circuit;
an insulation layer covering the substrate, the insulation layer including,
an interlayer dielectric layer on the substrate,
an intermetal dielectric layer on the interlayer dielectric layer, and
a plurality of metal lines electrically connected to the integrated circuit; and
a through electrode penetrating the substrate, the through electrode electrically connected to the integrated circuit,
wherein the plurality of metal lines includes:
a first metal line that is provided in the interlayer dielectric layer and electrically connected to the electrical contact; and
a plurality of second metal lines that are provided in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode,
wherein the through electrode includes a top surface higher in relation to the substrate than a top surface of the electrical contact,
wherein a top surface of the first metal line are coplanar with a top surface of the interlayer dielectric layer,
wherein the electrical contact penetrates the interlayer dielectric layer from the substrate and contacts a lower surface of the first metal line, and
wherein a width of the first metal line is greater than a width of a bottom surface of the second metal lines.

US Pat. No. 10,340,203

SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA AND METHOD FOR FABRICATING AND TESTING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor structure with a through silicon via, comprising:a substrate comprising a front side and a back side, wherein the front side is opposite to the back side;
a plurality of dielectric layers comprising an inner circuit disposed on the front side of the substrate, wherein the inner circuit is disposed within the plurality of dielectric layers, each of the plurality of dielectric layers directly contacts one of the plurality of dielectric layers;
a first through silicon via penetrating the substrate;
a second through silicon via penetrating the substrate;
a first bond pad disposed on the front side, on the topmost surface of the dielectric layers and electrically connecting to the inner circuit and the first through silicon via;
a first test pad disposed on the front side, directly contacting and on the topmost surface of the plurality of dielectric layers and connecting electrically to the first bond pad, wherein the first bond pad and the first test pad are made of a continuous metal layer, the first bond pad is directly contacted to the first test pad, and the first test pad has a first surface which is exposed and is tested by a first probe;
a second bond pad disposed on the back side of the substrate and electrically connecting to the second through silicon via; and
a second test pad disposed on and directly contacting the back side of the substrate and connecting electrically to the second bond pad, wherein the second test pad has a second surface which is exposed and is tested by a second probe, the second surface is opposite to the first surface, and the second test pad is the bottommost metal layer of the semiconductor structure with a through silicon via.

US Pat. No. 10,340,201

MULTILAYER HEAT-CONDUCTIVE SHEET, AND MANUFACTURING METHOD FOR MULTILAYER HEAT-CONDUCTIVE SHEET

DEXERIALS CORPORATION, T...

1. A method of manufacturing a multilayer heat-conductive sheet of which a tack-free layer and a heat-conductive layer are in contact with each other, the method comprising the steps of:a tack-free layer formation step for forming the tack-free layer having an adhesive surface having a Bekk smoothness within a range of at least 20 seconds and at most 300 seconds by including a thermoplastic resin having a glass transition temperature of 60° C. or higher with an inorganic filler having a median diameter of at least 0.5 ?m in a manner such that a part of the inorganic filler is projected from a layer of the thermoplastic resin; and
a heat-conductive layer disposition step for bringing the heat-conductive layer including a binder resin in contact with the adhesive surface of the tack-free layer.

US Pat. No. 10,340,200

SEMICONDUCTOR DEVICE

SHINKO ELECTRIC INDUSTRIE...

1. A semiconductor device comprising:a first semiconductor chip comprising an electrode pad on one surface of the first semiconductor chip;
a multilayer chip stack that is disposed on the one surface of the first semiconductor chip to be connected to the electrode pad;
a plurality of columnar spacers disposed on the one surface of the first semiconductor chip, the plurality of columnar spacers surrounding the multilayer chip stack and disposed outside the outer periphery of the multilayer chip stack; and
an underfill resin,
wherein:
the multilayer chip stack comprises a plurality of second semiconductor chips each of which comprises a connection terminal;
the connection terminal of one of the second semiconductor chips is directly connected to the electrode pad;
another one of the second semiconductor chips is mounted on the one of the second semiconductor chips;
a gap between the first semiconductor chip and the one of the second semiconductor chips and a gap between adjacent ones of the second semiconductor chips are filled with the underfill resin; and
a height of each of the plurality of columnar spacers is greater than a height of the connection terminal of each of the plurality of second semiconductor chips.

US Pat. No. 10,340,199

PACKAGING SUBSTRATE WITH BLOCK-TYPE VIA AND SEMICONDUCTOR PACKAGES HAVING THE SAME

MediaTek Inc., Hsin-Chu ...

1. A packaging substrate, comprising:a layer of a core layer material, having a first surface and a second surface being opposite to the first surface;
a central region on the second surface;
a peripheral region encircling the central region;
a group of ground pads disposed on the second surface within the central region;
a group of first power pads disposed on the second surface within the central region;
a group of second power pads disposed on the second surface within the central region;
a plurality of signal pads disposed on the second surface within the peripheral region;
a single first block-type via embedded in the layer within the central region, wherein the group of ground pads is physically in contact with the single first block-type via;
a single second block-type via embedded in the layer within the central region, wherein the group of first power pads is physically in contact with the single second block-type via, and the single first block-type via completely surrounds the single second block-type via; and
a third block-type via embedded in the core layer within the central region, wherein the group of second power pads is electrically connected to the third block-type via,
wherein a first portion of the core layer material separates the single first block-type via and single second block-type via, a second portion of the core layer material is outside the single first block-type via, and the first and second portions of the core layer material have a same dielectric constant, and
wherein the single first block-type via has a finger separating the single second block-type via and third block-type via.

US Pat. No. 10,340,198

SEMICONDUCTOR PACKAGE WITH EMBEDDED SUPPORTER AND METHOD FOR FABRICATING THE SAME

MEDIATEK INC., Hsin-Chu ...

1. A semiconductor package, comprising:a redistribution layer (RDL) structure having a first surface and a second surface opposite to the first surface;
a semiconductor die disposed on the first surface of the RDL structure and electrically coupled to the RDL structure;
a molding compound overlying the semiconductor die and the first surface of the RDL structure;
a supporter beside the semiconductor die and in contact with the first surface of the RDL structure; and
a paste positioned on the first surface of the RDL structure, wherein the paste is in direct contact with a boundary of the semiconductor die and an inner boundary of the supporter, and the paste connects the semiconductor die and the supporter.

US Pat. No. 10,340,197

INTEGRATED CIRCUIT SUBSTRATE HAVING CONFIGURABLE CIRCUIT ELEMENTS

Infineon Technologies AG,...

1. A die, comprising:a plurality of dielectric landings, wherein each one of the plurality of dielectric landings electrically separates two conductive landings associated with the one of the plurality of dielectric landings, wherein the two conductive landings include a first terminal end of a first metal line and a second terminal end of a second metal line, and wherein a dielectric layer over the first metal line and the second metal line includes a window that exposes the first terminal end and the second terminal end; and
a conductive material distributed inside the window of one or more of the plurality of dielectric landings, wherein the conductive material establishes an electrical connection between the first terminal end and the second terminal end of the two conductive landings associated with the one or more of the plurality of dielectric landings, and wherein a surface of the conductive material over the first terminal end and the second terminal end is below a top surface of the dielectric layer over the first metal line and the second metal line.

US Pat. No. 10,340,196

METHOD AND SYSTEM FOR SELECTION OF METROLOGY TARGETS FOR USE IN FOCUS AND DOSE APPLICATIONS

KLA-Tencor Corporation, ...

1. A method of selecting metrology targets for use in a focus and dose application comprising:providing a focus and exposure matrix wafer including a plurality of fields, each field including one or more metrology targets to a metrology tool;
measuring the one or more metrology targets within each of the plurality of fields of the focus and exposure matrix wafer with one or more detectors of the metrology tool to obtain one or more measurement results;
providing the one or more measurement results to a controller including one or more processors, wherein the one or more processors are communicatively coupled to the one or more detectors;
selecting a subset of fields of the plurality of fields of the focus and exposure matrix wafer with the one or more processors, wherein the subset of fields includes a number of fields less than the entirety of the plurality of fields;
performing a regression process on the one or more measurement results of the one or more metrology targets in the selected subset of fields of the plurality of fields of the focus and exposure matrix wafer to determine one or more dimension of interest (DOI) values for the one or more metrology targets in the selected subset of fields of the plurality of fields with the one or more processors;
calculating a focus sensitivity, a library precision, and a printability for the one or more metrology targets in the selected subset of fields of the plurality of fields based on the regression process performed on the selected subset of fields of the plurality of fields of the focus and dose exposure matrix wafer with the one or more processors, wherein the library precision is determined via a parameter sensitivity and noise model for the one or more metrology targets;
identifying a set of candidate metrology targets based on the focus sensitivity, the library precision, and the printability calculated for the one or more metrology targets in the selected subset of fields of the plurality of fields of the focus and exposure matrix wafer with the one or more processors, wherein the library precision defines a quality level of a library able to be generated from the set of candidate metrology targets; and
configuring one or more semiconductor device process tools to reduce selection time of a target for at least one of controlling or monitoring focus and dose, wherein the one or more semiconductor device process tools are configured based on the set of target candidates.

US Pat. No. 10,340,194

GUARD RINGS INCLUDING SEMICONDUCTOR FINS AND REGROWN REGIONS

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor substrate;
a guard ring comprising:
a first plurality of semiconductor fins aligned to a first ring, wherein the first ring encircles a portion of the semiconductor substrate;
a plurality of gate stacks on sidewalls and top surfaces of the first plurality of semiconductor fins;
a plurality of semiconductor regions, with each comprising a portion between two of the first plurality of semiconductor fins; and
a well region overlapped by the plurality of semiconductor regions and the first plurality of semiconductor fins, wherein the plurality of semiconductor regions and the well region are of a same conductivity type; and
a second plurality of semiconductor fins aligned to a second ring, with the plurality of gate stacks further extending on sidewalls and top surfaces of the second plurality of semiconductor fins, wherein the second ring encircles the first ring.

US Pat. No. 10,340,193

FIN FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A fin field-effect transistor comprising:a substrate, wherein the substrate is divided into a first device region and a second device region;
a fin structure disposed on the substrate, wherein the fin structure includes a plurality of trenches, wherein the fin structure includes at least one first fin positioned at the first device region, at least one second fin positioned at the second device region, and a partition fin arranged between the first device region and the second device region;
an isolation structure arranged on the substrate and in the trenches, the isolation structure includes a first isolation portion positioned at the first device region and a second isolation portion positioned at the second device region, and the first isolation portion and the second isolation portion respectively have different thicknesses; and
a gate-stacked structure covering the fin structure and the isolation structure and including a plurality of gate-stacked stripes, wherein the gate-stacked stripes intersects with the first fin, the second fin, and the partition fin, each of the gate-stacked stripes includes a gate insulating layer and a gate conductive layer disposed on the gate insulating layer, one of the gate-stacked stripes includes a first stacked portion and a second stacked portion, the first stacked portion is only located at the first device region to cover the first fin and a portion of the partition fin, and the second stacked portion is only located at the second device region to cover the second fin and another portion of the partition fin,
wherein the first stacked portion and the second stacked portion are separated from each other by the partition fin to define an opening located on the partition fin, the gate insulating layer directly contacts and covers the first fin, the second fin, and the partition fin, and a portion of the gate insulating layer, which is located on a top surface of the partition fin, is exposed from the opening;
wherein the partition fin is a dummy fin, the partition fin having two opposite sidewall surfaces respectively connecting to the first isolation portion and the second isolation portion.

US Pat. No. 10,340,192

FINFET GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a gate structure comprising:
a high-k dielectric layer;
a first metal layer over the high-k dielectric layer, wherein the first metal layer is a TiAl layer or a TaAl layer; and
a metal filler over the first metal layer, wherein:
a first surface of the first metal layer faces a gate spacer adjacent the gate structure,
a second surface of the first metal layer faces the metal filler,
a concentration of Al atoms at or near the first surface of the first metal layer is higher than a concentration of Al atoms in a region of the first metal layer between the first surface and the second surface, and
a concentration of Al atoms at or near the second surface of the first metal layer is higher than the concentration of Al atoms in the region of the first metal layer between the first surface and the second surface.

US Pat. No. 10,340,191

METHOD OF FORMING A FIN STRUCTURE OF SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A fin field effect transistor (FinFET) comprising:a substrate;
a fin structure extending from the substrate, the fin structure comprising a lower portion, an upper portion, and a middle portion interposed between the lower portion and the upper portion, the middle portion having a lattice constant different than a lattice constant of the upper portion, the middle portion having dielectric portions along opposing sidewalls;
isolation regions adjacent opposing sides of the fin structure; and
a liner interposed between the isolation regions and the dielectric portions.

US Pat. No. 10,340,190

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for fabricating a semiconductor device structure, comprising:forming a first fin structure over a substrate;
forming an isolation feature over the substrate;
forming a gate structure over the first fin structure and the isolation feature;
recessing a portion of the first fin structure that is not directly below the gate structure to form a first recess extending into a portion of the isolation feature that is not directly below the gate structure;
epitaxially growing a first semiconductor layer in the first recess of the first fin structure at a first temperature in a range of about 400° C. to about 700° C. so that the first semiconductor layer has a surface with [110] plane orientation, wherein the first semiconductor layer has a first dopant concentration of P;
epitaxially growing a second semiconductor layer covering the first semiconductor layer;
forming a second fin structure adjacent to the first fin structure;
recessing the second fin structure to form a second recess adjacent to the gate structure; and
epitaxially growing a third semiconductor layer in the second recess of the second fin structure at the first temperature so that the third semiconductor layer has a surface with [110] plane orientation, wherein the first semiconductor layer is separated from the third semiconductor layer by the second semiconductor layer, and wherein the surface of the first semiconductor layer with [110] plane orientation and the surface of the third semiconductor layer with [110] plane orientation face toward each other.

US Pat. No. 10,340,189

SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a substrate having a first region and a second region;
a first plurality of Fin Field Effect Transistors (FinFETs) are present in a first region of the substrate, the first plurality of Fin Field Effect Transistors including a first set of fin structures having a first pitch, and merged epitaxial semiconductor material of a single composition on source and drain region portions of the first set of fin structures; and
a second plurality of Fin Field Effect Transistors (FinFETs) is present in the second region of the substrate, the second plurality of FinFETs include a second set of fin structures having a second pitch that is greater than the first pitch of the first set of fin structures, wherein the second plurality of FinFETs include a composite epitaxial semiconductor material on the source and drain region portions of the second set of fin structures, the composite epitaxial semiconductor material includes a first non-merged portion, and a second bridging portion extending into contact between adjacent fin structures in the second set of fin structures, the second bridging portion having a planar upper surface that extends above an upper surface of the second set of fin structures, and planar sidewalls that are perpendicular to the planar upper surface, wherein the perpendicular relationship of the planar sidewalls and the planar upper surface extends to an edge interface of the planar sidewalls and the planar upper surface.

US Pat. No. 10,340,188

METHOD OF TRANSFERRING A SEMICONDUCTOR LAYER

IMEC vzw, Leuven (BE)

1. A method of manufacturing a semiconductor device, the method comprising:providing a donor wafer formed of a first semiconductor material;
forming a sacrificial layer on the donor wafer, the sacrificial layer formed of a second semiconductor material forming a pattern of fins, wherein each one of the fins is separated from an adjacent one of the fins by one of a plurality of isolation regions;
forming an active layer on the sacrificial layer, the active layer comprising a group IV semiconductor material or a group III-V semiconductor material or a group II-VI semiconductor material;
bonding the active layer to a handling wafer;
lifting off the donor wafer from the handling wafer such that the active layer is left on the handling wafer; and
configuring the donor wafer to be reused by removing the sacrificial layer and forming a new sacrificial layer between the isolation regions.

US Pat. No. 10,340,187

STRAIN RELIEF EPITAXIAL LIFT-OFF VIA PRE-PATTERNED MESAS

The Regents of the Univer...

11. A method of fabricating a thin film device, comprising:a. depositing a sacrificial layer over a growth substrate;
b. depositing an epilayer over the sacrificial layer;
c. depositing a metal layer over the epilayer;
d. depositing a photoresist layer over the epilayer;
e. patterning one or more trenches through the photoresist layer using photolithography, wherein the one or more trenches expose an area of the underlying metal layer;
f. patterning one or more trenches through the exposed area of the metal layer, wherein the one or more trenches expose an area of the underlying epilayer;
g. patterning one or more trenches through the exposed area of the epilayer, wherein the one or more trenches expose an area of the underlying sacrificial layer or an area of the underlying growth substrate;
h. removing the photoresist layer;
i. bonding the metal layer to a metal-coated host substrate; and
j. performing epitaxial lift off of the epilayer by etching the sacrificial layer.

US Pat. No. 10,340,186

METHOD FOR REDUCING CROSS CONTAMINATION IN INTEGRATED CIRCUIT MANUFACTURING

Skyworks Solutions, Inc.,...

17. A method of utilizing a single GaAs integrated circuit manufacturing process line to produce integrated circuits with backside conductive material selected from at least two materials, said method comprising:separately marking gold-contact wafers having gold backside conductive material as gold-marked wafers and copper-contact wafers having copper backside conductive material as copper-marked wafers;
performing pre-bond testing, wafer-carrier bonding, wafer thinning, stress relief etching, and through-wafer formation on a plurality of wafer lots having the gold backside conductive and a plurality of wafer lots having the copper backside conductive material using shared equipment and tooling;
removing the plurality of wafer lots having the copper backside conductive material and performing pre-cleaning, barrier and seed layer deposition, metal plating, and heat treatment on the plurality of wafer lots having the copper backside conductive material using dedicated equipment and tooling; and
performing street formation, copper etching, flash gold coating, debonding and cleaning on the plurality of wafer lots having the gold backside conductive material and the plurality of wafer lots having the copper backside conductive material using shared equipment and tooling, said copper-marked wafers and said gold-marked wafers being separated into containers having different colors and production personnel wear different gloves when handling said copper-marked wafers and said gold-marked wafers.

US Pat. No. 10,340,185

GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME

Intel Corporation, Santa...

1. An integrated circuit structure, comprising:a first silicon body having a longest dimension along a first direction;
a second silicon body having a longest dimension along the first direction;
a first gate line over the first silicon body and over the second silicon body along a second direction, the second direction orthogonal to the first direction, wherein the first gate line has a first discontinuity between the first silicon body and the second silicon body;
a second gate line over the first silicon body and over the second silicon body along the second direction, wherein the second gate line has a second discontinuity between the first silicon body and the second silicon body, the second discontinuity laterally adjacent to the first discontinuity, and wherein each of the first gate line and the second gate line comprises a high-k gate dielectric layer, a gate electrode, and a dielectric cap layer;
a trench contact line over the first silicon body and over the second silicon body along the second direction, the trench contact between the first gate line and the second gate line, wherein the trench contact is continuous between the first silicon body and the second silicon body at a location laterally adjacent to the first discontinuity and the second discontinuity;
a first dielectric spacer laterally between the trench contact and the first gate line; and
a second dielectric spacer laterally between the trench contact and the second gate line.

US Pat. No. 10,340,184

METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE

UNISANTIS ELECTRONICS SIN...

1. A method for producing a semiconductor device, comprising:depositing a first insulating film that is an oxide film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate;
depositing a sixth insulating film that is a nitride film;
depositing a second insulating film that is an oxide film containing an impurity of the first conductivity type;
depositing a seventh insulating film that is a nitride film;
depositing a third insulating film that is an oxide film containing an impurity of the first conductivity type;
etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole;
forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth;
removing the sixth insulating film and the seventh insulating film;
forming a first gate and a second gate; and
forming a contact connecting the first gate and the second gate.

US Pat. No. 10,340,183

COBALT PLATED VIA INTEGRATION SCHEME

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a via structure composed of cobalt; and
a wiring structure above the via structure, the wiring structure lined on its sidewalls with a barrier liner and the cobalt and further composed of conductive material over the cobalt and the barrier liner, the conductive material being different material than the cobalt, wherein the barrier liner is above the cobalt such that the barrier liner separates the cobalt from the conductive material in both the wiring structure and the via structure.

US Pat. No. 10,340,182

ENHANCED VIA FILL MATERIAL AND PROCESSING FOR DUAL DAMSCENE INTEGRATION

International Business Ma...

1. A process comprising coating a porous substrate with an organic polymer, where said porous substrate is composed of a porous microcircuit substrate material with surface pores optionally opening into subsurface pores, wherein said coating said porous substrate with said polymer is performed so as to eliminate or minimize penetration of said polymer into said surface pores and said subsurface pores by applying a coating comprising said polymer to the surface of said porous substrate where said polymer has a molecular weight of greater than about 5,000 and a glass transition temperature greater than a processing temperature required for forming an imaging layer and antireflective layer in said microcircuit.

US Pat. No. 10,340,181

INTERCONNECT STRUCTURE INCLUDING AIR GAP

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming an interconnect structure, comprising:depositing a first dielectric layer over a substrate;
depositing an etching stop layer over the first dielectric layer;
etching a via opening in the etching stop layer and the first dielectric layer;
depositing a barrier layer over a bottom surface and a sidewall of the via opening and over a top surface of the etching stop layer;
forming a conductive layer in the via opening, over the barrier layer, and over the etching stop layer;
etching the conductive layer and the barrier layer to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion, wherein a bottom-most portion of the spacing is above a top-most surface of the first dielectric layer;
removing a first portion of the etching stop layer under the spacing, while remaining a second portion of the etching stop layer such that a bottom-most surface of the second portion of the etching stop layer is above a bottom-most surface of the first conductive portion, and such that a sidewall of the second portion of the etching stop layer has a different shape from a sidewall of the first conductive portion; and
forming a second dielectric layer over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the second dielectric layer.

US Pat. No. 10,340,180

MERGE MANDREL FEATURES

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and
at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension,
wherein the at least one metal line with the second dimension comprises a first metal line and a second metal line which are merged together by a metal bridge connecting the first metal line to the second metal line, and
wherein the at least one metal line with the first dimension is a single metal line wiring structure.

US Pat. No. 10,340,179

VIA FORMATION USING DIRECTED SELF-ASSEMBLY OF A BLOCK COPOLYMER

INTERNATIONAL BUSINESS MA...

1. A method of forming an interconnect element, the method comprising:forming a trench in a dielectric material, the trench having a width equal to twice a natural pitch of a block copolymer, the block copolymer comprising a first polymer and a second polymer, wherein the natural pitch is a characteristic center-to-center distance of microdomains formed during an annealing process of the block copolymer; and
filling the trench with the block copolymer.

US Pat. No. 10,340,178

VIA PATTERNING USING MULTIPLE PHOTO MULTIPLE ETCH

Taiwan Semiconductor Manu...

1. A method comprising:forming a dielectric layer;
forming a trench in the dielectric layer;
dispensing a photo resist, wherein the photo resist comprises a first portion filling the trench;
etching a first part of the first portion of the photo resist in the trench, wherein a second part of the first portion is left in the trench after the etching; and
etching the dielectric layer to form a via opening in the dielectric layer, wherein the second part of the first portion acts as a part of an etching mask, wherein the via opening is stopped on a first etch stop layer, and the method further comprises:
removing the photo resist; and
after the photo resist is removed, etching-through a second etch stop layer underlying the first etch stop layer to expose a conductive feature.

US Pat. No. 10,340,175

SUBSTRATE TRANSFER TEACHING METHOD AND SUBSTRATE PROCESSING SYSTEM

Tokyo Electron Limited, ...

11. A substrate processing system comprising:a processing apparatus configured to process a substrate;
a transfer unit configured to transfer the substrate with respect to the processing apparatus, the transfer unit having an arm configured to hold the substrate and movable in a horizontal direction or movable in a vertical direction and a horizontal direction;
pins provided in the processing apparatus and configured to support the substrate, the pins being movable in the vertical direction;
a position detection unit configured to detect a horizontal position of the substrate with respect to the arm;
a control unit configured to determine a delivery position of the arm in the vertical direction in a case of transferring the substrate between the pins and the arm,
wherein the control unit is configured to control the pins, the arm and the position detection unit to perform a first step of vertically moving the arm or the pins from a reference position in a first direction by a predetermined distance, a second step of moving the arm in a horizontal direction, a third step of vertically moving the arm or the pins in a second direction opposite to the first direction by a distance equal to or greater than the predetermined distance, a fourth step of detecting a horizontal position of the substrate held by the arm with respect to the arm, and a fifth step of comparing the horizontal position of the substrate detected in the fourth step and a preset position, wherein the preset position corresponds to a preset horizontal position of the substrate with reference to the arm,
wherein, when the horizontal position of the substrate detected in the fourth step is identical to the preset position, the reference position is shifted in the first direction by the predetermined distance to a shifted reference position and the first step to the fifth step are repeated based on the shifted reference position, and
wherein, when the horizontal position of the substrate detected in the fourth step deviates from the preset position, a vertical position of the arm or the pins after the first step and before the third step is determined as the delivery position.

US Pat. No. 10,340,174

MOUNTING TABLE AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

6. A mounting table, comprising:a base;
an electrostatic chuck arranged on the base, the electrostatic chuck having a mounting surface on which a processing target is to be mounted;
a first hole extending through the base and the electrostatic chuck;
a second hole extending through the base and the electrostatic chuck;
a lifter pin which is received in the first hole, the lifter pin being movable up and down to protrude beyond and retract below the mounting surface so as to transfer the processing target in a vertical direction;
a first sleeve and a second sleeve respectively inserted in a first hole portion and in a second hole portion in the base, the first sleeve and the second sleeve being formed of an insulating material;
a first spacer inserted in the first sleeve and in a first hole portion in the electrostatic chuck, the first spacer being formed of an insulating material; and
a second spacer inserted in the second sleeve and in a second hole portion in the electrostatic chuck,
wherein a gas supply path configured to supply a heat transfer gas is formed inside of the second spacer and a radial space in the gas supply path is narrowed by the second sleeve and the second spacer to prevent a discharge in the gas supply path,
wherein the second sleeve is in contact with the base in the second hole portion in the base and a top end of the second sleeve is in contact with a backside surface of the electrostatic chuck,
wherein the second spacer extends from a bottom end of the second sleeve up to the mounting surface of the electrostatic chuck,
wherein the first spacer has an accommodating portion and a flange portion, the accommodation portion extending from a bottom end of the first sleeve up to the mounting surface of the electrostatic chuck and the flange portion having a flange shape protruding outwardly in a radial direction of the accommodation portion, wherein an upper surface of the flange portion faces a lower surface of the base, and
wherein the first sleeve has a flange portion.

US Pat. No. 10,340,173

SYSTEM FOR HANDLING SEMICONDUCTOR DIES

Micron Technology, Inc., ...

1. A system for handling semiconductor dies, comprising:a support member positioned to carry a semiconductor wafer, the semiconductor wafer having a plurality of semiconductor dies and being releasably attached to a dicing tape carried by a dicing frame, the support member having a plurality of apertures;
a plurality of ejector pins, with individual ejector pins operably positioned in and aligned with corresponding individual apertures of the support member;
a picking device having a pick head, the pick head having vacuum ports coupled to a vacuum source, the pick head is coupled to a fluid delivery device; and
a release station configured to be positioned opposite to the fluid delivery device the fluid delivery device being positioned to direct release fluid toward a first semiconductor die carried by the support member at the release station; and
a pick station configured to be positioned opposite the picking device and configured to support a second semiconductor die of the semiconductor wafer, such that the picking device is configured to releasably attach to the second semiconductor die of the semiconductor wafer.

US Pat. No. 10,340,172

SEMICONDUCTOR WAFER SURFACE PROTECTION FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

MITSUI CHEMICALS TOHCELLO...

1. A semiconductor wafer surface protection film comprising a substrate layer A, an adhesive absorption layer B, and an adhesive surface layer C in the order presented, whereinthe adhesive absorption layer B comprises an adhesive composition comprising a thermoset resin b1,
a minimum value, G?bmin, of a storage elastic modulus, G?b, in a range of 25° C. or higher and lower than 250° C. of the adhesive absorption layer B is 0.001 MPa or higher and lower than 0.1 MPa, the storage elastic modulus at 250° C., G?b250, of the adhesive absorption layer B is 0.005 MPa or higher and 10 MPa or lower, and the temperature at which the G?bmin is exhibited is 50° C. or higher and 150° C. or lower, and
a minimum value, G?cmin, of a storage elastic modulus, G?c, in a range of 25° C. or higher and lower than 250° C. of the adhesive surface layer C is 0.03 MPa or higher and lower than 3 MPa.

US Pat. No. 10,340,171

PERMANENT SECONDARY EROSION CONTAINMENT FOR ELECTROSTATIC CHUCK BONDS

LAM RESEARCH CORPORATION,...

1. A substrate support in a substrate processing chamber, the substrate support comprising:a baseplate,
a ceramic layer arranged on the baseplate, the ceramic layer arranged to support a substrate;
a bond layer arranged between the ceramic layer and the baseplate; and
a seal arranged between the ceramic layer and the baseplate around an outer perimeter of the bond layer, wherein the seal includes
an inner layer formed adjacent to the bond layer, wherein the inner layer comprises a first material, and wherein the first material includes at least one of silicone and an epoxy, and
an outer layer formed adjacent to the inner layer such that the inner layer is between the outer layer and the bond layer, wherein the outer layer comprises a second material,
wherein the inner layer extends from an upper surface of the baseplate to a lower surface of the ceramic layer to seal the bond layer from the substrate processing chamber,
an outer surface of the inner layer is concave and the outer layer includes an O-ring, and
the outer layer does not contact the bond layer.

US Pat. No. 10,340,169

ANTIREFLECTION MEMBER AND ORIENTER APPARATUS HAVING A THIRD PLATE PART WITH A SECOND NOTCH PART AND AN ANTIREFLECTION SURFACE

TOSHIBA MEMORY CORPORATIO...

1. An antireflection member comprising:a first plate part that has a first end and a second end, the second end being arranged at a side opposite to the first end;
a second plate part that extends from a vicinity of the first end, a first notch part being arranged on the second plate part, the second plate part having an antireflection surface; and
a third plate part that extends from a vicinity of the second end to be opposed to the second plate part, a second notch part being arranged at a position corresponding to the first notch part on the third plate part, the third plate part having an antireflection surface directed to the antireflection surface of the second plate part.

US Pat. No. 10,340,168

LOAD PORT AND EFEM

SINFONIA TECHNOLOGY CO., ...

1. A load port that is provided adjacent to a wafer transport chamber for taking in and out a wafer between the wafer transport chamber and a wafer storage container, the wafer storage container having a main body and a lid part, the main body having an abutment surface surrounding a periphery of the lid part, comprising:a plate-shaped part that constitutes a part of a wall of the wafer transport chamber, and has an opening for opening the wafer transport chamber;
a door part for opening and closing the opening; the door part includes a connecting means for latch operation which opens and closes the lid part and for holding the lid part; the connecting means being configured so as in an open configuration to make the lid part openable by performing the latch operation to the lid part, and connect so as to integrate the lid part to the door part and in a closed configuration to release the connection of the door part and the lid part and attach the lid part to the main body;
a mounting table that is configured to mount the wafer storage container so as to oppose the lid part for opening and closing an internal space of the wafer storage container to the door part, and to move to and from the plate-shaped part;
an elastic ring member that is provided on the mounting table side of the plate-shaped part so as to surround a peripheral edge of the opening,
wherein the elastic ring member elastically contacts the abutment surface by moving the mounting table toward the plate-shaped part, further comprising an engaging piece that is engageable with a flange part provided in a periphery of the lid part in the wafer storage container, and a pulling unit that pulls the engaging piece into the plate-shaped part side in a state of being engaged with the flange part, said engaging piece is attached to a shaft so as to be rotatable around the shaft,
wherein a plurality of the engaging piece and the respective shaft are provided exteriorly at both right and left sides to the opening and separate from the connecting means and
a second elastic ring member provided on the door part side of the plate-shaped part so as to surround a peripheral edge of the opening, wherein when the door part closes the opening, the second elastic ring member provided on the door part side elastically contacts the door part, so as to obtain a seal between the plate-shaped part and the door part.

US Pat. No. 10,340,167

ROBOT FOR TRANSFERRING ARTICLE

DAIFUKU CO., LTD., Osaka...

1. A robot for transferring a semiconductor component pod, comprising:a body including a rail driver configured to be hung and drive the body on a moving rail that solely supports the body, the body having a pair of pillar parts connected to the rail driver and disposed along a height direction of the body, and the pillar parts face each other;
a holding unit configured to hold a top end of the semiconductor component pod from above;
a two-way sliding unit configured to be connected to the holding unit and slide the holding unit past both sides of the body; and
an elevation-driving unit configured to be installed at the pillar parts and connected to the two-way sliding unit to elevate the two-way sliding unit along the height direction,
wherein the elevation-driving unit includes an elevation rail being installed at the pillar parts to be extended along the height direction and guiding an elevating motion of the two-way sliding unit along the height direction.

US Pat. No. 10,340,166

SUBSTRATES HANDLING IN A DEPOSITION SYSTEM

1. A substrate handling system, comprising:a first planar panel with one or more openings, wherein the one or more openings has larger dimensions than one or more substrates, wherein the substrate is mounted on any of the one or more openings;
a first sets of fingers amounted on top side of the first planar panel, wherein the first sets of fingers point away from the substrate at an angle from zero to 60 degrees relative to the first planar panel, wherein the first sets of fingers are on edge of the one or more opening, wherein there is some space between the first sets of fingers and a depositing surface of the substrate, wherein the first sets of fingers make physical contact with edge of the substrate, wherein the depositing surface amounts to full surface of the substrate;
a second planar panel coupled to the first panel, wherein the second planar panel is situated over the one more substrates; and
a second sets of fingers amounted on bottom side of the second planar panel, wherein the second sets of fingers point away from the substrate at an angle from zero to 60 degrees relative to the second planar panel, wherein the first sets of fingers and the second sets of fingers form a cage that confines the one more substrates.

US Pat. No. 10,340,165

SYSTEMS AND METHODS FOR AUTOMATED MULTI-ZONE DETECTION AND MODELING

KLA-Tencor Corporation, ...

1. A semiconductor tool comprising:an illumination source configured to generate an illumination beam;
one or more illumination optical elements configured to direct a portion of the illumination beam to a sample;
a detector;
one or more collection optical elements configured to direct radiation emanating from the sample to the detector; and
a controller communicatively coupled to the detector, the controller including one or more processors configured to execute program instructions configured to cause the one or more processors to:
measure alignment at a plurality of locations across the sample to generate alignment data based on the collection of radiation emanating from the sample by the detector in response to illumination from the illumination beam;
select an analysis area for alignment zone determination including at least some of the plurality of locations across the sample;
determine one or more zone boundaries dividing the analysis area into two or more alignment zones having different alignment signatures by minimizing, within a selected tolerance providing a selected trigger condition, interzone variations of portions of the alignment data associated with difference locations within the two or more alignment zones;
model the portions of the alignment data associated with the two or more alignment zones using two or more alignment models when the specified trigger condition is met; and
provide overlay data to correct for overlay errors in at least one of the sample or one or more additional samples, wherein the overlay data is based on the two or more alignment models applied to the two or more alignment zones when the specified trigger condition is met.

US Pat. No. 10,340,164

SUBSTRATE PROCESSING APPARATUS, METHOD OF MEASURING TEMPERATURE OF SUBSTRATE PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

Hitachi Kokusai Electric,...

1. A substrate processing apparatus comprising:a process chamber where a substrate charged in a boat is processed;
a transfer device configured to transfer the substrate to the boat;
a temperature measuring device attached to the transfer device and configured to measure an inside temperature of the process chamber; and
a controller configured to control the transfer device and the temperature measuring device to: move the transfer device along with the temperature measuring device to be adjacent to the process chamber and insert the temperature measuring device into the process chamber from an outside of the process chamber before measuring the inside temperature of the process chamber; and measure the inside temperature via the temperature measuring device inserted in the process chamber from the outside of the process chamber while simultaneously moving the temperature measuring device by way of vertically moving the transfer device having the temperature measuring device attached thereto,
wherein the controller is further configured to terminate temperature measurement by a predetermined sequence for measuring the inside temperature of the process chamber without executing the predetermined sequence when the transfer device is not present at a predetermined start position.

US Pat. No. 10,340,162

REDUCED WIRE COUNT HEATER ARRAY BLOCK

Watlow Electric Manufactu...

1. A thermal system comprising:a plurality of thermal elements, each of the thermal elements defining a resistor and a current limiting device, the plurality of thermal elements comprising at least a first subset of thermal elements connected in parallel and at least a second subset of thermal elements connected in parallel, wherein the current limiting devices in a given subset of thermal elements have opposite polarity from each other; and
a plurality of power lines connected to the plurality of thermal elements, the power lines configured in pairs for providing power to the first subset and the second subset of thermal elements, wherein each of the pairs of power lines share a common power line; and
a control system connected to the plurality of power lines and to the common power line to selectively apply power to the first subset and the second subset of thermal elements.

US Pat. No. 10,340,161

DEVICE FOR PREFIXING OF SUBSTRATES

EV Group E. Thallner GmbH...

1. A device for prefixing first and second substrates, the device comprising:at least one pretreatment system for pretreating at least one substrate surface of the first and second substrates in at least one surface area;
an alignment system for aligning the first and second substrates; and
a prefixing system for making contact with and prefixing the aligned first and second substrates on the pretreated surface areas;
wherein the prefixing is done only at partial surfaces, and
wherein local application of force is used to reach equivalent pressure for spontaneous bonds in the partial surfaces and thereby to prefix the first and second substrates.

US Pat. No. 10,340,160

METHOD OF FORMING A SEMICONDUCTOR DIE CUTTING TOOL

SEMICONDUCTOR COMPONENTS ...

1. A method of forming a tool for a semiconductor wafer comprising:forming the tool to reduce a thickness of a semiconductor material formed on a semiconductor wafer;
forming the tool with a cutting tip and cutting surfaces that are configured to penetrate into the semiconductor material to form reduced thickness regions in the semiconductor material including forming some of the cutting surfaces to intersect and form a cutting volume; and
forming an accumulation region of the tool with a recess having a first volume for accepting portions of the semiconductor material displaced from within the semiconductor material by the penetration wherein the first volume is no less than the cutting volume.

US Pat. No. 10,340,159

CLEANING CHEMICAL SUPPLYING DEVICE, CLEANING CHEMICAL SUPPLYING METHOD, AND CLEANING UNIT

EBARA CORPORATION, Tokyo...

1. A device adapted to supply a cleaning chemical to a substrate cleaning device, comprising:a De-Ionized Water (“DIW”) supply source;
a DIW supply pipeline adapted to be fluidly coupled to the DIW supply source and the substrate cleaning device, the DIW supply pipeline including a DIW supply valve and a DIW pressure control regulator;
a DIW branch pipeline, the DIW branch pipeline connected to the DIW supply pipeline between the DIW supply valve and the DIW pressure control regulator;
a dilution water switching unit adapted to be fluidly coupled to the DIW branch pipeline, a first DIW pipeline and a second DIW pipeline;
a first chemical supply source;
a first chemical supply pipeline fluidly communicating with the first chemical supply source;
a first chemical control device fluidly communicating with the first chemical supply pipeline and a first chemical pipeline;
a second chemical supply source;
a second chemical supply pipeline fluidly communicating with the second chemical supply source;
a second chemical control device fluidly communicating with the second chemical supply pipeline and a second chemical pipeline;
a first mixing unit fluidly coupled to each of the first chemical pipeline, the first dilution water pipeline, and a first cleaning chemical pipeline, the first cleaning chemical pipeline fluidly communicating with the substrate cleaning device; and
a second mixing unit fluidly coupled to each of the second chemical pipeline, the second dilution water pipeline, and a second cleaning chemical pipeline, the second cleaning chemical pipeline fluidly communicating with the substrate cleaning device;
wherein the dilution water switching unit includes a DIW closed loop controller (“CLC”), a first supply valve of the first DIW pipeline and a second supply valve of the second DIW pipeline, the DIW CLC includes a DIW internal control valve, the DIW CLC measures a flow rate of DIW flowing through the DIW CLC and controls the DIW internal control valve on the basis of the measured flow rate of DIW;
wherein the first chemical control device includes at least a first CLC, the first CLC includes a first internal control valve, the first CLC measures a flow rate of first chemical flowing through the first CLC and controls the first internal control valve on the basis of the measured flow rate of the first chemical; and
wherein the second chemical control device includes at least a second CLC, the second CLC includes a second internal control valve, the second CLC measures a flow rate of second chemical flowing through the second CLC and controls the second internal control valve on the basis of the measured flow rate of the second chemical.

US Pat. No. 10,340,158

SUBSTRATE CLEANING APPARATUS

SAMSUNG ELECTRONICS CO., ...

1. A substrate cleaning apparatus, comprising:a cleaning bath comprising a cleaning space configured to accommodate a substrate having a first surface and a second surface opposite to the first surface;
a substrate support configured to support the substrate in the cleaning bath;
a connection bar;
a first nozzle bar and a second nozzle bar, each of the first nozzle bar and the second nozzle bar including a first end and a second end opposite to the first end, the first end of each of the first nozzle bar and the second nozzle bar being pivoted at the connection bar such that the second end of each of the first nozzle bar and the second nozzle bar is rotatable in a plane parallel with the first surface and the second surface of the substrate, each of the first nozzle bar and the second nozzle bar including a passage through which a cleaning solution flows;
a plurality of nozzles provided along a longitudinal direction of each of the first nozzle bar and the second nozzle bar and configured to spray the cleaning solution from the passage of each of the first nozzle bar and the second nozzle bar to the substrate; and
a first brush and a second brush, the first brush provided on a first side of the substrate and configured to clean the first surface and the second brush provided on a second side opposite to the first side of the substrate and configured to clean the second surface of the substrate.

US Pat. No. 10,340,157

MINI-ENVIRONMENT APPARATUS

TDK CORPORATION, Tokyo (...

1. A mini-environment apparatus, comprising:a wafer transportation machine configured with a transport arm configured to transport a wafer;
a wafer transportation room provided with the wafer transportation machine and passed by the wafer transported to a processing room;
a circulating passage where a gas detoured from the wafer transportation room flows;
a blower configured to form a circulating current falling in the wafer transportation room and rising in the circulating passage;
a current guide arranged in a ceiling part of the wafer transportation room and configured to laminarize the circulating current and introduce this laminarized circulating current into the wafer transportation room;
a particle removal filter arranged in either the ceiling part of the wafer transportation room or the circulating passage; and
a chemical filter arranged detachably in the circulating passage and separately from the particle removal filter, wherein
the chemical filter is arranged at a position lower than a lowest position where the wafer may pass through in the wafer transportation room,
two shutters configured to shield the circulating current in the circulating passage are arranged in the circulating passage so as to sandwich the chemical filter from up and down directions, and a filter removal window configured such that the chemical filter can be removed from the circulating passage through the filter removal window, the filter removal window arranged between the two shutters in the circulating passage, and
the two shutters are located at a position lower than a lowest position of the transport arm.

US Pat. No. 10,340,155

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING

Taiwan Semiconductor Manu...

1. A method, comprising:forming a dielectric layer;
after forming the dielectric layer, patterning the dielectric layer to create a cavity in the dielectric layer, a plurality of contacts being exposed in the cavity, wherein all contacts of the plurality of contacts are disposed on and physically connected to a single redistribution layer overlying a substrate;
after patterning the dielectric layer, bonding a component to the plurality of contacts, a perimeter of the cavity extending around a perimeter of the component
after bonding the component to the plurality of contacts, placing underfill in the cavity in a manner that causes the underfill to fill spaces under the component and around the plurality of contacts, wherein the underfill is placed in liquid form in a first area of the cavity, and the underfill flows from the first area into the spaces under the component and around the plurality of contacts, and wherein after the underfill fills the spaces under the component and around the plurality of contacts, a first section of the underfill extends a first distance away from a first sidewall of the component towards a first sidewall of the dielectric layer, a second section of the underfill extends a second distance away from a second sidewall of the component towards a second sidewall of the dielectric layer, and the first distance is greater than the second distance; and
forming a connector over the dielectric layer beside the cavity, wherein the connector extends through the dielectric layer to contact an underlying conductor that is at a same level of metallization as the plurality of contacts and attaches to the single redistribution layer.

US Pat. No. 10,340,154

BONDING JUNCTION STRUCTURE

1. A bonding joining structure in which a heat generating body and a support comprising a metal are joined to each other via a joint portion composed of a sintered body of copper powder,wherein the support contains copper or gold, the copper or gold being present in at least an outermost surface of the support, and
an interdiffusion portion in which copper or gold contained in the support and copper contained in the sintered body are diffused to each other is formed so as to straddle a bonding interface between the support and the sintered body.

US Pat. No. 10,340,153

FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package, comprising:an insulating layer and conductive patterns disposed on a first side of the insulating layer;
a frame having a through hole and disposed on a second side of the insulating layer opposing the first side;
a metal layer having a hole, and having upper and lower surfaces being in physical contact with a lower surface of the frame and the second side of the insulating layer, respectively;
a semiconductor chip having first and second surfaces opposing each other, including electrode pads disposed on the first surface and facing the second side of the insulating layer, and disposed on a portion of the insulating layer and within the through hole of the frame and the hole of the metal layer, the electrode pads being electrically connected to the conductive patterns through vias penetrating through the insulating layer; and
an encapsulant extending continuously to cover an upper surface of the frame and the second surface of the semiconductor chip, to fill at least a portion of the through hole, and to cover a side surface of the metal layer connecting the upper and lower surfaces of the metal layer,
wherein the metal layer is electrically insulated from the semiconductor chip.

US Pat. No. 10,340,152

MECHANICAL COUPLINGS DESIGNED TO RESOLVE PROCESS CONSTRAINTS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit package, comprising:a shunt resistor having at least one self-aligning member that protrudes from a first surface of the shunt resistor; and
a lead frame having at least one self-aligning feature, wherein the self-aligning feature is a cavity extending from a first surface of the lead frame facing the first surface of the shunt resistor and the at least one self-aligning member is located within the cavity that form the at least one self-aligning feature; and
an integrated circuit located on said lead frame.

US Pat. No. 10,340,151

SUBSTRATE PROCESSING APPARATUS, HEATING APPARATUS, CEILING HEAT INSULATOR, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KOKUSAI ELECTRIC CORPORAT...

1. A ceiling heat insulator, which is located above a side wall heat insulator of a heating apparatus for a substrate processing apparatus for processing a substrate, the ceiling heat insulator comprising:an upper heat insulator;
a lower heat insulator; and
at least one gas-flow path allowing a cooling gas to pass therethrough so that the ceiling heat insulator includes a portion which has a solid cross-sectional area in an outer edge side of the ceiling heat insulator that is smaller than that in a center side of the ceiling heat insulator,
wherein each of the upper heat insulator and the lower heat insulator includes a concave portion, which is located outside the substrate and has a circular arc shape, a center of the circular arc shape being located at a central portion of the ceiling heat insulator, and
wherein the upper heat insulator and the lower heat insulator overlap with each other so that the concave portion of the upper heat insulator and the concave portion of the lower heat insulator are disposed to face each other and define the at least one gas-flow path.

US Pat. No. 10,340,149

METHOD OF FORMING DENSE HOLE PATTERNS OF SEMICONDUCTOR DEVICES

NANYA TECHNOLOGY CORPORAT...

1. A method of forming dense hole patterns, the method comprising:forming a plurality of first pillars on at least one lower hard mask layer disposed on a substrate;
blanket forming a spacer layer on the lower hard mask layer by Atomic layer deposition to form a plurality of second pillars respectively covering the first pillars, wherein a plurality of first holes are formed among the second pillars, and each of the first holes is enclosed by three of the second pillars;
etching the spacer layer to expose first portions of the lower hard mask layer via the first holes and expose top surfaces of the first pillars;
removing the first pillars to form a plurality of second holes in the spacer layer to expose second portions of the lower hard mask layer;
etching the first portions and the second portions of the lower hard mask layer; and
removing remaining portions of the spacer layer.

US Pat. No. 10,340,148

POLYMER, ORGANIC LAYER COMPOSITION, AND METHOD OF FORMING PATTERNS

SAMSUNG SDI CO., LTD., Y...

1. A polymer comprising a structural unit represented by Chemical Formula 1 and a structural unit represented by Chemical Formula 2:
wherein, in Chemical Formula 1,
B is a divalent organic group,
* is a linking point, and
A is a substituted or unsubstituted divalent group from one of the following compounds,

wherein, in the above compounds, R0 and R1 are each independently hydrogen, a hydroxy group, a methoxy group, an ethoxy group, a halogen atom, a halogen-containing group, a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C6 to C30 aryl group, or a combination thereof, and
wherein, in Chemical Formula 2,
C is a group including a substituted or unsubstituted aromatic ring,
D is a divalent organic group, and
* is a linking point.

US Pat. No. 10,340,147

SEMICONDUCTOR DEVICE WITH EQUIPOTENTIAL RING CONTACT AT CURVED PORTION OF EQUIPOTENTIAL RING ELECTRODE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor body of a first conductivity type, having a first area and a second area, the first area being an active area in which transistor element including a source, a drain, and a gate is formed, the second area surrounding the first area, the semiconductor body having a quadrilateral shape in a plan view;
an insulating film formed over the semiconductor body;
an Equipotential Ring (EQR) electrode pattern formed in the insulating film to surround the active area, and having curved portions at corners of the quadrilateral shape;
a first conductive strip connected to the source and formed in the insulating film in the active area;
a first diffusion region of a second conductivity type which is opposite to the first conductivity type, formed in the semiconductor body and in the second area;
a second conductive strip connected to the first diffusion region and the EQR electrode pattern,
wherein the second conductive strip is covered with the insulating film, and is disposed in the second area of the semiconductor body,
wherein the second conductive strip comprises a first second conductive strip and a second conductive strip, and
wherein the first second conductive strip and the second second conductive strip are arranged to be in parallel or in different directions with respect to a normal direction to one of the curved portions of the EQR electrode.

US Pat. No. 10,340,146

RELIABILITY CAPS FOR HIGH-K DIELECTRIC ANNEALS

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:depositing a first layer comprised of a metal silicon nitride on a high-k dielectric material;
thermally processing the high-k dielectric material in an oxygen-containing ambient environment with the first layer arranged as a cap between the high-k dielectric material and the oxygen-containing ambient environment; and
after the high-k dielectric material is thermally processed, completely removing the first layer with a wet chemical etching process,
wherein the first layer blocks transport of oxygen from the oxygen-containing ambient environment to the high-k dielectric material.

US Pat. No. 10,340,145

INTEGRATED CIRCUIT ELEMENT AND FABRICATING METHOD THEREOF, CIRCUIT BOARD, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An integrated circuit element, comprising:a base plate, and a plurality of connection parts and a bare integrated circuit chip arranged on the base plate,
wherein the bare integrated circuit chip comprises a plurality of connection points, and the plurality of connection parts is electrically connected to the plurality of connection points according to a one-to-one correspondence;
wherein an array substrate or a color filter substrate of a liquid crystal display panel is used as the base plate, or a cover-board of an organic light emitting diode display panel is used as the base plate,
wherein the bare integrated circuit chip is arranged at a side of the array substrate facing toward the color filter substrate, or the bare integrated circuit chip is arranged at a side of the color filter substrate facing toward the array substrate, or the bare integrated circuit chip is arranged at a side of the cover-board facing toward a backboard, and
wherein the bare integrated circuit chip is of nanometer scale.

US Pat. No. 10,340,144

DOPING OF A SUBSTRATE VIA A DOPANT CONTAINING POLYMER FILM

ROHM AND HAAS ELECTRONIC ...

1. A semiconductor substrate comprising:embedded dopant domains of diameter 3 to 30 nanometers; wherein the embedded dopant domains are selected from the group consisting of boron, arsenic, antimony, aluminum, indium, and gallium, wherein the embedded dopant domains are located within 30 nanometers of the substrate surface and are periodically spaced in the substrate.

US Pat. No. 10,340,143

ANODIC ALUMINUM OXIDE AS HARD MASK FOR PLASMA ETCHING

Lam Research Corporation,...

1. A method for performing a plasma etching process, comprising:depositing a seed layer of aluminum over a top surface of a wafer;
depositing a layer of photoresist material over the seed layer of aluminum;
patterning and developing the layer of photoresist material to expose one or more portions of the seed layer of aluminum through openings in the photoresist material;
performing an electrochemical transformation process on the wafer to electrochemically transform the one or more portions of the seed layer of aluminum that are exposed through openings in the photoresist material into anodic aluminum oxide, wherein the anodic aluminum oxide includes a pattern of holes that extend through the anodic aluminum oxide to expose areas of the top surface of the wafer beneath the seed layer of aluminum;
removing the photoresist material from the wafer; and
exposing the wafer to a plasma to etch holes into the wafer at the areas of the top surface of the wafer that are exposed by the pattern of holes in the anodic aluminum oxide.

US Pat. No. 10,340,142

METHODS, APPARATUS AND SYSTEM FOR SELF-ALIGNED METAL HARD MASKS

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming a gate disposed on a semiconductor substrate and having a first side and a second side;
forming a metal hard mask disposed on the gate and having a first side and second side, wherein the first side of the metal hard mask is vertically aligned with the first side of the gate and the second side of the metal hard mask is vertically aligned with the second side of the gate;
forming a nitride region disposed on the metal hard mask and having a first side and second side, wherein at least a portion of the first side of the nitride region is vertically aligned with the first sides of the gate and the metal hard mask, at least a portion of the second side of the nitride region is vertically aligned with the second sides of the gate and the metal hard mask; and the nitride region is T-shaped;
forming a spacer disposed on the first sides of the gate and the metal hard mask and on the second sides of the gate and the metal hard mask, wherein a top of the spacer is above a top of the metal hard mask;
forming a first source/drain (S/D) region disposed in proximity to the first side of the gate; and
forming a second S/D region disposed in proximity to the second side of the gate.

US Pat. No. 10,340,141

PATTERNING METHOD FOR SEMICONDUCTOR DEVICE AND STRUCTURES RESULTING THEREFROM

Taiwan Semiconductor Manu...

1. A method comprising:defining a first mandrel and a second mandrel over a hard mask layer, a topmost surface of the first mandrel is disposed in a first plane;
depositing a spacer layer over and along sidewalls of the first mandrel and the second mandrel;
forming a sacrificial material over the spacer layer between the first mandrel and the second mandrel, wherein the sacrificial material comprises an inorganic oxide, wherein the sacrificial material comprises a divot at a top surface of the sacrificial material, wherein a portion of the sacrificial material in the first plane extends continuously from a first sidewall of the spacer layer to a second sidewall of the spacer layer, the second sidewall of the spacer layer facing the first sidewall of the spacer layer, the first sidewall of the spacer layer and the second sidewall of the spacer layer are both disposed between the first mandrel and the second mandrel;
removing a first horizontal portion and a second horizontal portion of the spacer layer to expose the first mandrel and the second mandrel, wherein remaining portions of the spacer layer provide spacers on sidewalls of the first mandrel and the second mandrel, wherein the sacrificial material masks a third horizontal portion and a fourth horizontal portion of the spacer layer while removing the first horizontal portion and the second horizontal portion of the spacer layer, and wherein the divot at least partially exposes a fifth horizontal portion of the spacer layer between the third horizontal portion and the fourth horizontal portion while removing the first horizontal portion and the second horizontal portion of the spacer layer;
removing the first mandrel and the second mandrel; and
patterning the hard mask layer using the spacers and the sacrificial material as an etch mask.

US Pat. No. 10,340,140

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus, comprising:a processing vessel configured to accommodate therein a substrate as a processing target;
a first supply unit configured to supply a first gas into the processing vessel;
a second supply unit configured to supply a second gas, having a relative humidity different from that of the first gas, into the processing vessel; and
a control unit,
wherein the control unit is configured to determine a state of a gas within the processing vessel based on a relative humidity obtained after a supply of the first gas by the first supply unit and a supply of the second gas by the second supply unit are performed,
wherein the state of the gas includes a supply ratio of the first and second gases.

US Pat. No. 10,340,139

METHODS AND MASK STRUCTURES FOR SUBSTANTIALLY DEFECT-FREE EPITAXIAL GROWTH

IMEC, Leuven (BE)

1. A mask structure comprising:a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a substrate, wherein the first trench has a first length greater than a first width of the first trench, and wherein the first trench is oriented in a first direction along the first length; and
a second level on top of the first level, wherein the second level defines a plurality of second trenches, wherein each second trench of the plurality (i) has a second width and a second length that is greater than the second width and (ii) is oriented in a second direction along the second length,
wherein the first trench extending through the first level comprises the first trench separating the first level into a first side and a second side, wherein each second trench of the plurality extends through at least a portion of the second level over the first side of the first level, the first trench, and the second side of the first level, and
wherein the second direction is different from the first direction, thereby enabling the mask structure to trap defects in multiple directions during epitaxial growth of a semiconductor material.

US Pat. No. 10,340,136

MINIMIZATION OF CARBON LOSS IN ALD SIO2 DEPOSITION ON HARDMASK FILMS

Lam Research Corporation,...

1. A method of depositing films over a substrate received within a process chamber, comprising:processing the substrate to expose a surface of the substrate and a spin-on-hardmask (SOH) patterned thereon to a first precursor using a first plasma so that the first precursor gets partially absorbed to form Silicon-Hydrogen bonds on the surface of the substrate and on surfaces of SOH, the SOH having an initial pattern; and
processing the substrate to expose the surface of the substrate and the surfaces of the SOH to a second precursor using a second plasma, the second precursor includes a mixture of carbon-dioxide gas and an inert gas, the processing causing oxygen radicals to be released and react with the Silicon-Hydrogen bonds formed on the surface of the substrate and the surfaces of the SOH, wherein the oxygen radicals reacting with the Silicon-Hydrogen bonds form an oxide film layer on the surface of the substrate and on surfaces of the SOH, wherein the oxygen radicals reacting with the Silicon-Hydrogen bonds forms the oxide film layer without substantially consuming a surface thickness of the initial pattern of the SOH.

US Pat. No. 10,340,135

METHOD OF TOPOLOGICALLY RESTRICTED PLASMA-ENHANCED CYCLIC DEPOSITION OF SILICON OR METAL NITRIDE

ASM IP Holding B.V., Alm...

1. A method of topology-enabling selective deposition wherein a film is deposited selectively on a top surface of a substrate having a recess pattern constituted by a bottom and sidewalls in semiconductor fabrication, comprising, in sequence:(i) supplying a precursor to a reaction space in which the substrate is placed between electrodes, said precursor containing multiple elements including silicon or metal, carbon, nitrogen, and hydrogen;
(ii) conducting purging of the reaction space, without step (i), only to the extent that a greater amount of precursor than an amount of precursor chemisorbed on the top surface of the substrate remains in a vicinity of the top surface of the substrate; and then
(iii) applying RF power between the electrodes while supplying a plasma-generating gas devoid of H and O, without step (i), to generate an ion-rich anisotropic plasma to which the substrate is exposed, thereby depositing a topologically restricted layer selectively and predominantly on the top surface of the substrate wherein substantially no layer, or a substantially thinner layer than the topologically restricted layer, is deposited on the sidewalls and the bottom of the recess pattern without becoming thinner toward the bottom of the recess pattern,
wherein the topologically restricted layer is constituted by SiCN, SiN, TiCN, TiN, ZrCN, ZrN, HfCN, HfN, TaCN, TaN, NbCN, NbN, AlCN, AlN, CoCN, CoN, CuCN, CuN, WCN, WN, RuCN, RuN, NiCN, NiN LaCN, LaN, or WFN.

US Pat. No. 10,340,134

SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

KOKUSAI ELECTRIC CORPORAT...

1. A method of manufacturing a semiconductor device, comprising:forming a film on a substrate by performing a cycle n times (where n is an integer equal to or greater than 1), the cycle including alternately performing:
forming a first layer containing a borazine ring skeleton by performing a set m times (where m is an integer equal to or greater than 1), the set including:
supplying a precursor to the substrate to form a precursor layer; and
supplying a borazine compound containing the borazine ring skeleton to the precursor layer; and
forming a second layer containing the borazine ring skeleton and oxygen by supplying an oxidizing agent to the first layer.

US Pat. No. 10,340,132

OPTIMIZED ELECTROMAGNETIC FIELD ON SIDE-ON FT-ICR MASS SPECTROMETERS

DH Technologies Developme...

10. A side-on injection Penning trap that includes two sets of printed circuit board electrodes with radial dimensions that are optimized to apply a quadrupole field to charged particles, comprising:a first printed circuit board on which is printed a first set of two or more concentric circular or semi-circular electrodes;
a second printed circuit board on which is printed a second set of two or more concentric circular or semi-circular electrodes that correspond in size and shape to the first set of electrodes, wherein the second printed circuit board is placed in parallel with the first printed circuit board so that the second set of electrodes faces and is coaxial with the first set of electrodes, wherein the space between the first set of electrodes and the second set of electrodes is a cylindrical gap used to trap charged particles, wherein the cylindrical gap has a length d, wherein the first set of electrodes and the second set of electrodes each includes a central disk electrode with a radius of 1.1 d, a first concentric ring or segmented ring electrode of radius 1.9 d, and a second concentric ring or segmented ring electrode of radius 2.4 d, and wherein the first set of electrodes and the second set of electrodes apply a quadrupole electric field to the cylindrical gap; and
at least one permanent magnet that is placed coaxially with the first set of electrodes and the second set of electrodes but outside of the cylindrical gap that applies a first magnetic field to the cylindrical gap that is coaxial with the cylindrical gap, wherein the effects of the first magnetic field and the quadrupole electric field combine to trap charged particles in the cylindrical gap that are injected in a direction perpendicular to the first magnetic field;
at least one solenoid coil that is placed coaxially with the cylindrical gap, but outside of the cylindrical gap;
a current source electrically connected to the at least one solenoid coil that supplies current to the at least one solenoid coil to produce a second magnetic field that is applied to the cylindrical gap that is coaxial with the cylindrical gap;
at least one magnetic sensor placed in or on the first printed circuit board within the first set of electrodes that measures a combined magnetic field that is a combination of the first magnetic field and the second magnetic field; and
feedback control circuitry electrically connected to the at least one magnetic sensor and the current source that that receives over time the combined magnetic field measured by the at least one magnetic sensor and in response adjusts the current of the current source to increase or decrease the second magnetic field in order to maintain the combined magnetic field at a constant value.

US Pat. No. 10,340,131

METHODS AND APPARATUSES RELATING TO CLEANING AND IMAGING AN ION SOURCE USING REFLECTED LIGHT

KRATOS ANALYTICAL LIMITED...

1. A method of cleaning an ion source, the method including:at a first reflective surface of a mirror, reflecting ultraviolet light that has a wavelength in a first wavelength band onto a surface of the ion source so that contaminant material is desorbed from the surface of the ion source, wherein the ultraviolet light has a wavelength in the range 10 nm to 400 nm and is produced by a laser;
at a second reflective surface of the mirror, reflecting visible light that has a plurality of wavelengths in a second wavelength band and that comes from the surface of the ion source towards an imaging apparatus for producing an image of the surface of the ion source using the visible light, wherein the visible light has a plurality of wavelengths in the range 390 nm to 700 nm and is produced by a light source, separate from the laser, for illuminating the surface of the ion source with visible light, wherein the visible light passes through the first reflective surface of the mirror before being reflected at the second reflective surface of the mirror.

US Pat. No. 10,340,129

MICROCHANNEL PLATE AND ELECTRON MULTIPLIER

HAMAMATSU PHOTONICS K.K.,...

1. A microchannel plate comprising:a substrate including a front surface, a rear surface, and a side surface;
a plurality of channels penetrating from the front surface to the rear surface of the substrate;
a first film provided on at least an inner wall surface of the channel;
a second film provided on the first film; and
electrode layers provided on the front surface and the rear surface of the substrate,
wherein the first film is made of Al2O3,
the second film is made of SiO2, and
the first film is thicker than the second film.

US Pat. No. 10,340,128

APPARATUS, METHOD AND NONTRANSITORY COMPUTER READABLE MEDIUM FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE

TOSHIBA MEMORY CORPORATIO...

1. An apparatus for manufacturing an integrated circuit device comprising:an etching treatment unit configured to etch a stacked body including an alternately arranged plurality of films having different compositions, the etching treatment unit including
a housing configured to define a treatment chamber,
a gas supply system configured to supply an etching gas to the treatment chamber,
a pump configured to exhaust gas in the treatment chamber,
a holding table configured to hold the stacked body in the treatment chamber,
a dielectric place provided above the holding table, and
a high frequency source configured to generate an electric field between the holding table and the dielectric place;
a sensor configured to detect light intensity of one wavelength of a light emission generated by etching reaction during the etching; and
a control unit configured to
detect extreme values from data relating to a temporal change in the light intensity detected by the sensor,
determine an end point of the etching based on the extreme values while the extreme values can be detected,
estimate an end point of the etching based on the extreme values detected so far when the extreme value cannot be detected from the data at all, and
cause the etching treatment unit to stop the etching when the end point is reached, the extreme values including at least one of a plurality of peak values and a plurality of bottom values, wherein
the control unit is configured to estimate the end point by deriving a cycle from a time interval of the plurality of extreme values, and to estimate time to the end point of the etching based on the time interval,
the control unit is configured to determine an etching amount after reaching a lower layer by estimating a time to the end point based on the temporal change in the light intensity during the etching, and
the time interval is derived based on an approximation formula derived from a relation between a number of the extreme values and time in the data.

US Pat. No. 10,340,127

USING MODELING TO DETERMINE WAFER BIAS ASSOCIATED WITH A PLASMA SYSTEM

Lam Research Corporation,...

1. A method for determining wafer bias, the method comprising:receiving, by a processor from a sensor, an output complex voltage and current, the sensor located within a generator and coupled to an output of the generator, the output of the generator coupled via a radio frequency (RF) cable to an input of an impedance matching circuit, the impedance matching circuit coupled via an RF transmission line to an electrostatic chuck (ESC) of a plasma chamber;
determining, by the processor, from the output complex voltage and current a projected complex voltage and current at a point on a path from an output of a computer-generated model of the impedance matching circuit to a computer-generated model of the ESC, the determining of the projected complex voltage and current performed using a computer-generated model for the path, the computer-generated model for the path including an RF transmission model of the RF transmission line; and
applying, by the processor, the projected complex voltage and current as an input to a function to map the projected complex voltage and current to a wafer bias value at the ESC model.

US Pat. No. 10,340,125

PULSED REMOTE PLASMA METHOD AND SYSTEM

ASM IP Holding B.V., Alm...

1. A method for providing excited species to a reaction chamber of a reactor, the method comprising the steps of:providing a first gas to a remote plasma unit;
using a pressure control device located between the remote plasma unit and a vacuum source and a control valve between the remote plasma unit and the reaction chamber, controlling a pressure of the remote plasma unit located upstream of the pressure control device;
forming a plasma in a remote plasma unit; and
pulsing first excited species to the reaction chamber, while maintaining steady-state conditions for the remote plasma unit, by switching a flow of the first excited species between the reaction chamber and a vacuum source using the control valve.

US Pat. No. 10,340,124

GENERALIZED CYLINDRICAL CAVITY SYSTEM FOR MICROWAVE ROTATION AND IMPEDANCE SHIFTING BY IRISES IN A POWER-SUPPLYING WAVEGUIDE

Applied Materials, Inc., ...

1. A plasma reactor comprising:a workpiece processing chamber;
a cylindrical microwave cavity overlying the workpiece processing chamber, and a plurality of microwave input ports arranged asymmetrically about a center axis of the cylindrical microwave cavity, the plurality of microwave input ports including first and second input ports, P and Q, in a sidewall of said cylindrical microwave cavity spaced apart by an oblique azimuthal offset angle ??;
a microwave source having first microwave modules that provides a first microwave source output having a microwave frequency, and a second microwave module that provides a second microwave source output having the microwave frequency and separated by a temporal phase difference ?Ø from the first microwave source output;
a pair of respective waveguides, each of said respective waveguides having a microwave input end coupled to a respective one of said microwave source outputs and a microwave output end coupled to a respective one of said first and second input ports;
a seed signal generator having a first output signal coupled to the first microwave module and a second output signal coupled to the second microwave module, the seed signal generator configured to generate first and second output signals that generate rotating microwaves of mode TEmnl or TMmnl in said cylindrical microwave cavity, wherein m, n and l are user-selected values of a TE or TM mode.

US Pat. No. 10,340,123

MULTI-FREQUENCY POWER MODULATION FOR ETCHING HIGH ASPECT RATIO FEATURES

TOKYO ELECTRON LIMITED, ...

1. A method of etching, comprising:disposing a substrate having a surface exposing a first material and a second material in a processing space of a plasma processing system;
performing a modulated plasma etching process to selectively remove the first material at a rate greater than removing the second material, the modulated plasma etching process comprising a power modulation cycle that includes:
applying a first power modulation sequence to the plasma processing system, and
applying a second power modulation sequence to the plasma processing system, the second power modulation sequence being different than the first power modulation sequence; and
repeating the power modulation cycle at a power modulation frequency for a determined modulation time period,
wherein the first power modulation sequence includes repeating a first sub-power modulation cycle at a first sub-power modulation frequency, the first sub-power modulation cycle including:
applying a radio frequency (RF) signal to the plasma processing system at a first power level, and
applying the RF signal to the plasma processing system at a second power level, wherein the first and second power levels differ in value from one another;
wherein a time period of the second power modulation sequence is greater than a time period of the first sub-power modulation cycle.

US Pat. No. 10,340,122

SYSTEMS AND METHODS FOR TAILORING ION ENERGY DISTRIBUTION FUNCTION BY ODD HARMONIC MIXING

Lam Research Corporation,...

1. A radio frequency (RF) generator comprising:an odd harmonic power supply configured to generate an nth harmonic RF signal, wherein n is an odd number;
an impedance matching circuit coupled to the odd harmonic power supply, wherein the impedance matching circuit is configured to output an nth modified harmonic RF signal upon receiving the nth harmonic RF signal;
a frequency multiplier coupled to the impedance matching circuit, wherein the frequency multiplier is configured to receive the nth modified harmonic RF signal to output an (n+2)th harmonic RF signal;
a variable adjuster coupled to the frequency multiplier, wherein the variable adjuster is configured to modify a variable of the (n+2)th harmonic RF signal to output an adjusted (n+2)th harmonic RF signal; and
an adder coupled to the variable adjuster and the impedance matching circuit, wherein the adder is configured to add the nth modified harmonic RF signal and the adjusted (n+2)th harmonic RF signal to generate an added RF signal.

US Pat. No. 10,340,121

PLASMA PROCESSING SYSTEMS INCLUDING SIDE COILS AND METHODS RELATED TO THE PLASMA PROCESSING SYSTEMS

Lam Research Corporation,...

1. A method for processing a wafer with plasma in a plasma processing system, saidplasma processing system including a chamber structure for containing said plasma, said chamber structure including a cylindrical chamber wall, said chamber structure further including a dielectric member disposed above said cylindrical chamber wall and coupled with said cylindrical chamber wall, said dielectric member including a first element and a second element connected to said first element, the method comprising:
initiating, using a set of top coils disposed above said first element of said dielectric member, said plasma inside said chamber structure, said initiating including providing a first signal of a first frequency to said set of top coils;
after said initiating, affecting, using a set of side coils surrounding said second element, distribution of said plasma, said affecting including providing a second signal of a second frequency to said set of side coils, said second frequency being different from said first frequency, said second element being perpendicular to said first element; and
moving said set of side coils along an outer surface of said second element in a direction perpendicular to a top surface of said wafer when said wafer is processed in said plasma processing system, for tuning said distribution of said plasma.

US Pat. No. 10,340,120

BLANKING APERTURE ARRAY, METHOD FOR MANUFACTURING BLANKING APERTURE ARRAY, AND MULTI-CHARGED PARTICLE BEAM WRITING APPARATUS

NuFlare Technology, Inc.,...

1. A blanking aperture array for a multi-charged particle beam writing apparatus, the blanking aperture array comprising:a substrate; and
a plurality of blankers, each of the plurality of blankers including a blanking electrode and a ground electrode that are formed on a first surface of the substrate,
wherein the plurality of blankers includes at least
a normal blanker which is capable of applying a predetermined voltage between the blanking electrode and the ground electrode and for which a through hole bored through the substrate is formed, and
a defective blanker which is not capable of applying the predetermined voltage between the blanking electrode and the ground electrode and for which the through hole bored through the substrate is filled with a beam shield,
wherein, for the defective blanker, a recess is disposed on the first surface of the substrate, and
wherein a substrate body between a bottom surface of the recess and a second surface of the substrate serves as the beam shield.

US Pat. No. 10,340,119

AUTOMATED TEM SAMPLE PREPARATION

FEI Company, Hillsboro, ...

1. A method for automated sample preparation in a charged particle beam system, comprising:loading a work piece into a vacuum chamber including one or more charged particle beam columns and a sample manipulation probe;
performing charged particle beam milling operations to form from a portion of the work piece a sample for observation on a transmission electron microscope;
after performing charged particle beam milling operations to form from the portion of the work piece the sample, forming one or more fiducials on the formed sample;
attaching the sample manipulation probe to the sample;
removing the sample from the work piece; and
using the one or more fiducials on the removed sample to determine a position and/or a rotational alignment of the sample.

US Pat. No. 10,340,118

SCANNING TRANSMISSION ELECTRON MICROSCOPE AND METHOD OF IMAGE GENERATION

JEOL Ltd., Tokyo (JP)

1. A scanning transmission electron microscope adapted to produce scanned images by scanning an electron beam over a sample, said scanning transmission electron microscope comprising:an electron source for emitting an electron beam;
a scanning deflector for scanning the emitted electron beam over the sample;
an objective lens for converging the electron beam emitted from the electron source;
an imager placed at a back focal plane of the objective lens or at a plane conjugate with the back focal plane; and
a scanned image generator for generating the scanned images on the basis of images captured by the imager,
wherein the scanned image generator operates to form electron diffraction patterns from the electron beam passing through positions on the sample by scanning of the electron beam, to capture the electron diffraction patterns by the imager so that plural images are produced, to integrate the intensity of each pixel over an integration region that is set based on the size of an image of a transmitted wave within a respective one of the produced images such that the signal intensity at each position on the sample is found for each of the produced images, and to generate the scanned images on the basis of the signal intensities at the positions on the sample, wherein said scanned image generator operates to measure the size of the image of said transmitted wave from the image captured by said imager and to set said integration region on the basis of the measured size of the image of the transmitted wave.

US Pat. No. 10,340,117

ION BEAM DEVICE AND SAMPLE OBSERVATION METHOD

Hitachi, Ltd., Tokyo (JP...

1. An ion beam device comprising:an ion source configured to generate an ion beam;
a sample chamber;
an evacuation pump configured to reduce a pressure in the sample chamber to a first degree of vacuum; and
a vacuum container configured to hold a sample that is irradiated with the ion beam,
wherein the ion beam passes from the sample chamber to the sample through a passage in the vacuum container in which the first degree of vacuum changes to a second degree of vacuum lower than the first degree of vacuum, and the passage has an aspect ratio of 200 or more.

US Pat. No. 10,340,115

CHARGED PARTICLE BEAM APPARATUS

Hitachi High-Technologies...

1. A charged particle beam device comprising:an optical element which adjusts a charged particle beam emitted from a charged particle source;
an adjustment element which adjusts an incidence condition of the charged particle beam with respect to the optical element; and
a control device which controls the adjustment element,
wherein the control device continuously tracks or calculates a temperature fluctuation of the optical element based on a condition setting and the incidence condition of the charged particle beam with respect to the optical element.

US Pat. No. 10,340,114

METHOD OF ELIMINATING THERMALLY INDUCED BEAM DRIFT IN AN ELECTRON BEAM SEPARATOR

KLA-Tencor Corporation, ...

1. An apparatus comprising:an electron beam separator;
a ceramic divider disposed on the electron beam separator;
a set of electrostatic plates in an octupole arrangement disposed on the ceramic divider;
a first separator coil pair disposed around the ceramic divider and arranged on opposite sides of the electron beam separator;
a second separator coil pair disposed around the ceramic divider and arranged on opposite sides of the electron beam separator, orthogonal to the first separator coil pair;
a heater coil disposed around the electron beam separator; and
a power source configured to provide a heater coil current to the heater coil.

US Pat. No. 10,340,113

STUDYING DYNAMIC SPECIMEN BEHAVIOR IN A CHARGED-PARTICLE MICROSCOPE

FEI Company, Hillsboro, ...

1. A method of using a Charged Particle Microscope, comprising:a specimen holder, for holding a specimen;
a source, for producing an irradiating beam of charged particles;
an illuminator, for directing said beam so as to irradiate the specimen; and
a detector, for detecting a flux of emergent radiation emanating from the specimen in response to said irradiation,the method comprising:in said illuminator, providing an aperture plate comprising an array of apertures;
using a deflecting device to scan said beam across said array, thereby alternatingly interrupting and transmitting the beam so as to produce a train of beam pulses; and
irradiating said specimen with said train of pulses, and using said detector to perform positionally resolved detection of the attendant emergent radiation.

US Pat. No. 10,340,111

FUSE

TOYODA IRON WORKS CO., LT...

1. A fuse comprising:a conductive member formed integrally with a melting portion that melts and breaks when overcurrent occurs, and with first and second bars;
two shielding portions arranged on the conductive member to hold the melting portion in between, each of the two shielding portions being comprised of a single-piece shielding member where each shielding member is situated on the conductive member between the melting portion and the first and second bars, wherein each shielding member is disk shaped and includes a holder and a slot on one side of the holder where the slot is in communication with an outer side of the holder and extends to an outer circumference of its respective shielding member and a slit on an opposite side of the holder where the slit is in communication with an opposite outer side of the holder and extends toward but not to an opposite outer side of the outer circumference of its respective shielding member; and
a case formed from an electrically-insulative material, wherein the case encloses the melting portion in cooperation with the two shielding portions.

US Pat. No. 10,340,109

ULTRAFAST ELECTROMECHANICAL DISCONNECT SWITCH HAVING CONTACT PRESSURE ADJUSTMENT AND SWITCHING CHAMBER

The Florida State Univers...

1. An electrical transfer or disconnect switch, comprising:a first non-movable electrical contact coupled to an insulating medium;
a second non-movable electrical contact coupled to said insulating medium;
a third non-movable electrical contact coupled to said insulating medium and positioned between said first non-movable electrical contact and said second non-movable electrical contact to provide conduction between said first non-movable electrical contact and said second non-movable electrical contact when electrically in series;
a first static gap disposed between said first non-movable contact and said third non-movable contact;
a second static gap disposed between said second non-movable contact and said third non-movable contact;
an actuator having a first mounting plate and a second mounting plate, said first mounting plate aligned with said first static gap but positioned at a spaced distance away from said first non-movable contact, said third non-movable contact, and said first static gap; said second mounting plate aligned with said second static gap but positioned at a spaced distance away from said second non-movable contact, said third non-movable contact, and said second static gap;
a first movable contact directly or indirectly coupled to said first mounting plate of said actuator and aligned with said first static gap, said first movable contact contacting said first and third non-movable contacts simultaneously to complete a first series between said first and third non-movable contacts, wherein when said actuator is prompted, said first mounting plate shifts away from said first and third non-movable contacts, such that a first variable gap is formed between said first movable contact and said first and third non-movable contacts, thus breaking or disconnecting said first series between said first and third non-movable contacts, said actuator also releasing contact pressure between said first movable contact and said first and third non-movable contacts;
a second movable contact directly or indirectly coupled to said second mounting plate of said actuator and aligned with said second static gap, said second movable contact contacting said second and third non-movable contacts simultaneously to complete a second series between said second and third non-movable contacts, wherein when said actuator is prompted, said second mounting plate shifts away from said second and third non-movable contacts, such that a second variable gap is formed between said second movable contact and said second and third non-movable contacts, thus breaking or disconnecting said second series between said second and third non-movable contacts, said actuator also releasing contact pressure between said second movable contact and said second and third non-movable contacts, wherein when said actuator is idle or unprompted, said first movable contact is contacting said first and third non-movable contacts and when said second movable contact is contacting said first and second non-movable contacts, an electrical circuit is closed within said electrical transfer or disconnect switch, such that a current flows along a path of travel within said electrical transfer or disconnect switch across said first non-movable contact, said first movable contact, said third non-movable contact, said second movable contact, and said second non-movable contact;
one or more precision adjustment screws coupled to said first, second, and third non-movable contacts for adjusting said first, second, and third non-movable contacts; and
a switching chamber that encloses at least said insulating medium, said first non-movable contact, said second non-movable contact, said third non-movable contact and said actuator, said switching chamber containing vacuum or pressurized gas.

US Pat. No. 10,340,108

ULTRAFAST SINGLE ACTUATOR ELECTROMECHANICAL DISCONNECT SWITCH

The Florida State Univers...

1. An electrical switch, comprising:a first electrical feedthrough disposed through an insulating medium, said first electrical feedthrough connected to a first non-movable electrical contact and said first non-movable electrical contact coupled to said insulating medium;
a second electrical feedthrough disposed through the insulating medium, said second electrical feedthrough connected to a second non-movable electrical contact and said second non-movable electrical contact coupled to said insulating medium;
a static gap disposed between said first non-movable contact and said second non-movable contact;
an actuator aligned with said static gap but positioned at a spaced distance away from said first and second non-movable contacts; said actuator being a piezoelectric actuator or a magnetostrictive actuator;
a movable contact directly or indirectly coupled to said actuator and aligned with said static gap, said movable contact contacting said first and second non-movable contacts simultaneously to complete a series between said first and second non-movable contacts, wherein when said actuator is prompted, said movable contact shifts away from said first and second non-movable contacts, such that a variable gap is formed between said movable contact and said first and second non-movable contacts, thus breaking or disconnecting said series between said first and second non-movable contacts, said actuator also releasing contact pressure between said movable contact and said first and second non-movable contacts, wherein when said actuator is idle or unprompted, said movable contact is contacting said first and second non-movable contacts, an electrical circuit is closed within said electrical switch, such that a current flows along a path of travel within said electrical switch across said first non-movable contact, said movable contact and said second non-movable contact.

US Pat. No. 10,340,106

LOAD DRIVER

DENSO CORPORATION, Kariy...

1. A load driver for driving a load configured to receive an electric power supply from a first power supply or from a second power supply, the load driver having a first relay disposed at a position between the first power supply and the load and a second relay disposed at a position between the second power supply and the load, the load driver comprising:a controller configured to control an open state and a closed state of the first relay and the second relay by an open-close control signal;
a first open-close switch configured to control driving the first relay to the open state and the closed state based on the open-close control signal from the controller;
a second open-close switch configured to control driving the second relay to the open state and the closed state based on the open-close control signal from the controller; and
a prohibition switch configured to prohibit driving the second relay to the closed state, when the controller outputs the open-close control signal to drive the first relay to the closed state to supply electric power from the first power supply to the load via the first relay.

US Pat. No. 10,340,105

POWER SUPPLY APPARATUS AND METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A power supply apparatus to supply power to an electronic apparatus, the power supply apparatus comprising:a first relay and a second relay to be turned on and off to control the supply of the power for the electronic apparatus; and
a processor to control a switching operation of the first relay and/or the second relay based on:
a connection detection signal indicating a connection state between the power supply apparatus and the electronic apparatus, and
a power on/off signal indicating one of a power on command and a power off command with respect to the electronic apparatus,
wherein, in response to the connection detection signal indicating the connection state of the power supply apparatus being connected to the electronic apparatus and the power on/off signal indicating the power off command with respect to the electronic apparatus, the processor controls one of the first relay and the second relay to turn on one of the first relay and the second relay.

US Pat. No. 10,340,104

PERMANENT SHORT-CIRCUIT DEVICE

ABB SCHWEIZ AG, Baden (C...

1. A permanent short-circuit device for high-voltage power transmission applications, comprising:an enclosure with a first fixed electrically conducting body and a second fixed electrically conducting body, each being connected to a respective conductor leaving the enclosure,
wherein the first body has a first and a second surface on opposite sides of the first body,
wherein the second body has a first and a second surface on opposite sides of the second body, and
where the first surface of the first body faces the first surface of the second body and is separated therefrom by a gap with width d and the second surface of the first body is provided with explosives connected to a detonator for deforming the first body in the direction towards the first surface of the second body such that the first surface of the first body galvanically connects to the first surface of the second body across the gap, wherein the first and second bodies are tubes, where the first body is an outer body encircling the second body.

US Pat. No. 10,340,103

SWITCHING ASSEMBLIES WITH INTEGRAL HANDLE AND ROTOR AND METHODS OF ASSEMBLY

SIEMENS INDUSTRY, INC., ...

1. An electrical switching assembly, comprising:an integral handle and rotor unit including a rotor portion integral with a handle portion;
one or more orientation features on the rotor portion; and
a line base comprising one or more openings configured to receive the one or more orientation features, wherein the one or more orientation features enable the rotor portion to be received within the line base when the rotor portion is in a predetermined orientation relative to the line base,
wherein the one or more orientation features are configured to retain the rotor portion within the line base without needing any additional retaining mechanisms in the electrical switching assembly,
wherein the rotor portion configured to receive one or more conductors, and
wherein the rotor portion configured to be received in the line base.

US Pat. No. 10,340,102

DEVICE FOR CONTROLLING MULTIPLE FUNCTIONS IN A MOTOR VEHICLE

1. A device for controlling multiple functions, comprising:a switch panel having at least three control panels extending along a longitudinal extension of the switch panel, the switch panel being pivotably mounted about an axis of rotation that is parallel with the longitudinal extension of the switch panel to pivot about the axis of rotation in response to manual actuation of the switch panel by manual actuation of one or more of the control panels;
wherein the switch panel is movable with respect to the longitudinal extension of the switch panel and is fixed with respect to a transverse extension of the switch panel perpendicular to the longitudinal extension of the switch panel;
the switch panel further including an actuating plate having the control panels, the actuating plate extends along the longitudinal extension of the switch panel;
the switch panel further including at least three reinforcing ribs each being respectively for a respective one of the control panels, the reinforcing ribs are respectively connected to the actuating plate at locations corresponding to the control panels and extend along the transverse extension of the switch panel between the actuating plate and the axis of rotation, the reinforcing ribs are pivotably mounted about the axis of rotation whereby the switch panel is pivotably mounted about the axis of rotation to pivot about the axis of rotation, the reinforcing ribs cause the switch panel to be fixed with respect to the transverse extension of the switch panel;
a plurality of force sensors distributed along the longitudinal extension of the switch panel and respectively associated with the control panels; and
wherein actuation of the switch panel by actuating one of the control panels triggers one of a plurality of different functions depending on which one of the control panels is actuated and the force sensors are configured to detect which one of the control panels is actuated.

US Pat. No. 10,340,101

KEYCAP WITH ACTIVE ELEMENTS

Intel Corporation, Santa...

8. A method, comprising:forming a keycap for a key, the keycap including a pocket, and the pocket includes:
a protective layer; and
an active element, wherein a height of protective layer and the active element is less than about six (6) millimeters in height.

US Pat. No. 10,340,100

KEYBOARD DEVICE

PRIMAX ELECTRONICS LTD, ...

1. A keyboard device, comprising:a key switch;
a base plate;
a connecting element disposed on the base plate and connected with the base plate; and
a replaceable key comprising:
a coupling plate located over the connecting element and connected with the connecting element, and comprising a first sliding part, wherein when the coupling plate is moved downwardly relative to the base plate, the key switch is triggered; and
a keycap exposed outside the keyboard device, and comprising a second sliding part, wherein the keycap is combined with the coupling plate and at least a portion of the coupling plate is covered by the keycap when the second sliding part is slid relative to the first sliding part, or the keycap is detached from the coupling plate when the second sliding part is slid relative to the first sliding part, wherein the first sliding part is a sliding groove, and the second sliding part is a protrusion block, wherein the protrusion block is inserted into the sliding groove and laterally slidable within the sliding groove.

US Pat. No. 10,340,099

MOUSE WITH REMOVABLE BUTTON SWITCH

Dexin Corporation, New T...

1. A mouse with a removable button switch, comprising:a release unit, comprising a bearer, mounted on a circuit board of the mouse;
a press-fixing and ejection means, provided with a press-fixing part and an ejection part; and
a press-fixing means, the press-fixing means and the press-fixing and ejection means being oppositely disposed on both sides of the bearer, and the press-fixing means being provided with the press-fixing part;
wherein the button switch is disposed between the press-fixing means and the press-fixing and ejection means, the button switch is fixed in the bearer by the press-fixing part of the press-fixing means and the press-fixing part of the press-fixing and ejection means, and the button switch in the bearer is ejected by the ejection part of the press-fixing and ejection means.

US Pat. No. 10,340,098

KEY STRUCTURE

PRIMAX ELECTRONICS LTD, ...

1. A key structure, comprising:a keycap, having a light hole;
a movable mechanism, disposed below the keycap, wherein the movable mechanism has an upper connection end and a lower connection end that are opposite to each other, and the upper connection end is pivotally connected to the keycap, wherein the movable mechanism is a scissor mechanism, and the scissor mechanism has a through hole;
a support plate, disposed below the keycap, wherein the lower connection end of the movable mechanism is pivotally connected to the support plate, and the support plate has a central opening;
a circuit board, disposed below the support plate, wherein the circuit board has at least one groove, and the groove is correspondingly located directly below the keycap;
at least one trigger switch element, disposed on the circuit board, wherein one end portion of the trigger switch element is electrically connected to the circuit board, and an other end portion of the trigger switch element passes through the central opening of the support plate to be abutted against the keycap; and
at least one indicator light-emitting element, electrically connected to the circuit board and embedded in the groove, wherein light emitted by the indicator light-emitting element sequentially travels upward through the central opening of the support plate, the through hole of the scissor mechanism, and the light hole of the keycap and is emitted outward.

US Pat. No. 10,340,097

INSTALLATION SWITCHING DEVICE HAVING A CONTACT CLAMP

ABB SCHWEIZ AG, Baden (C...

1. An installation switching device comprising:a housing; and
at least one contact clamp, which is arranged in the housing, configured to connect at least one electrical conductor through a conductor insertion opening that is provided in the housing, the contact clamp comprising a clamping frame that has a rectangular cross section and a clamping screw that is configured to engage in a first narrow end side of the clamping frame and a clamping end of the clamping screw being configured to cooperate with a section of a contact rail that is fixedly mounted in the housing of the installation switching device, the section being located within the clamping frame, so that a second narrow end side that lies opposite the first narrow end side and is connected thereto via two longitudinal sides that lie opposite one another is configured to press an inserted connecting conductor against a surface of the contact rail that is remote from the clamping screw,
wherein a clamp covering part is coupled to the clamping frame,
wherein the clamp covering part has a tub-shaped cross section having two short arms that lie opposite one another and a connecting piece that connects the two short arms to one another,
wherein a first short arm is coupled to the first narrow end side and a second short arm that lies opposite the first short arm is coupled to the second narrow side, and
wherein the second short arm supports a skirt that protrudes over the second narrow end side in a direction facing away from the clamping screw.

US Pat. No. 10,340,096

SYSTEM AND METHOD FOR AIR MOTOR RECHARGING OF SPRING MECHANISMS

MITSUBISHI ELECTRIC POWER...

1. A circuit breaker system, comprising:an electrical contact mechanism, the electrical contact mechanism movable between a closed and an open position;
an air motor, the air motor operable responsive to pressurized air supplied thereto for recharging the electrical contact mechanism following a closing operation;
an air storage tank that delivers pressurized air to the air motor, wherein air in the air storage tank is stored at a predetermined storage pressure;
a solenoid valve interposing the air motor and the air storage tank and energizable to an open state to enable pressurized air to flow to the air motor; and
a pressure regulator interposing the solenoid valve and the air storage tank to control an operating pressure of the air delivered to the air motor at a predetermined pressure level, wherein the operating pressure supplying sufficient energy to the air motor to recharge the electrical contact mechanism.

US Pat. No. 10,340,095

SAFETY-SWITCH DEVICE FOR USE ON A MOVABLE DEVICE

1. A safety-switch device for use on a movable device, the safety-switch device comprising:a switch;
an enclosure surrounding the switch, the enclosure including an impact surface which serves as an actuator for the switch and a bracket that is a flexible deformable body that is mountable on a surface of a housing of the movable device, the impact surface being a separate component that is replaceably assembled on the bracket;
wherein the impact surface is constructed as a rigid element and is flexibly suspended in the bracket, so as to be movable in a horizontal, vertical, and diagonal direction between a first resting position and a second actuation position that triggers a switch operation of the switch; and
wherein a trigger mechanism is placed between the impact surface and the switch and triggers the switch when the impact surface moves to its actuation position.

US Pat. No. 10,340,094

APPARATUS AND ASSOCIATED METHODS FOR ELECTRICAL STORAGE

Nokia Technologies Oy, E...

1. An apparatus comprising a first charge collector and an ionic layer, the ionic layer configured to absorb water from the surrounding environment to deliver said water to the apparatus, the apparatus comprising:graphene oxide provided on the first charge collector, the graphene oxide configured to generate protons in the presence of water;
a second conductive material spaced apart from the first charge collector, the second material having a lower work function than the first charge collector, the graphene oxide extending from the first charge collector to be in contact with the second material at an interface;
wherein the ionic layer is in contact with the graphene oxide and the second material; and wherein the ionic layer comprises a room temperature ionic fluid and a solidifying material which provides for the ionic layer to be a solid at room temperature.

US Pat. No. 10,340,093

SOLAR CELL SYSTEM AND METHOD FOR OPERATING SOLAR CELL SYSTEM

Panasonic Intellectual Pr...

1. A solar cell system, comprising:a solar cell that includes a first electrode, a second electrode that faces the first electrode, and a light absorbing layer that is located between the first electrode and the second electrode, and converts light into charges;
a power supply that applies voltage between the first electrode and the second electrode; and
a voltage controller, wherein the light absorbing layer contains a compound having a perovskite crystal structure represented by AMX3 where A represents a monovalent cation, M represents a divalent cation, and X represents a halogen anion, and
the voltage controller controls the voltage of the power supply so that during a first period of non-power generation, an electric current of 1 ?A/cm2 or more and 100 ?A/cm2 or less flows in the light absorbing layer in a direction opposite to a direction in which an electric current flows during power generation.

US Pat. No. 10,340,092

SOLID ELECTROLYTIC CAPACITOR

MURATA MANUFACTURING CO.,...

1. A solid electrolytic capacitor comprising: at least one capacitor element including an anode portion composed of a metal layer extending in a first direction and having an external surface with a plurality of recesses, a dielectric layer on the external surface of the metal layer, and a cathode portion having a solid electrolyte layer on the dielectric layer and a current collector layer on the solid electrolyte layer; a leading conductor layer electrically connected to the current collector layer; an insulating resin body covering the capacitor element and the leading conductor layer, the insulating resin body having a first end surface and a second end surface opposite to each other along a first direction; a first external electrode including at least one first plating layer on the first end surface, the at least one first plating layer being directly connected to the leading conductor layer; and a second external electrode including at least one second plating layer on the second end surface; the at least one second plating layer being directly connected to the metal layer: the insulating resin body including: (a) a first insulating resin body having the leading conductor layer on a surface thereof, and a second insulating resin body on the first insulating resin body so as to cover the leading conductor layer and the plurality of capacitor elements, the second insulating resin body having a different composition than the first insulating resin body; (b) a first main surface and a second main surface opposite to each other in a second direction orthogonal to the first direction, and a first side surface and a second side surface opposite to each other in a third direction orthogonal to the first direction and the second direction; (c) a first connecting portion connecting the first end surface and the first main surface, a second connecting portion connecting the first end surface and the second main surface, a third connecting portion connecting the second end surface and the first main surface, and a fourth connecting portion connecting the second end surface and the second main surface; the first connecting portion, the second connecting portion, the third connecting portion, and the fourth connecting portion each have a first chamfered portion; wherein: the first external electrode is formed along the first end surface and the first chamfered portions of the first connecting portion and the second connecting portion; and the second external electrode is formed along the second end surface and the first chamfered portions of the third connecting portion and the fourth connecting portion.

US Pat. No. 10,340,091

POLYANION COPOLYMERS FOR USE WITH CONDUCTING POLYMERS IN SOLID ELECTROLYTIC CAPACITORS

KEMET Electronics Corpora...

1. A capacitor comprising:an anode;
a dielectric on said anode; and
a cathode on said dielectric wherein cathode comprises:
a conductive polymer; and
a polyanion wherein said polyanion is a copolymer comprising groups A, B and C represented by the ratio of Formula A:
AxByCz   Formula A
wherein:
A is polystyrenesulfonic acid or a salt of polystyrenesulfonate;
B and C separately represent polymerized units substituted by a group selected from:
-Carboxyl group;
—C(O)OR6 group wherein R6 is selected from the group consisting of:
an alkyl of 1 to 20 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate, anhydride and
—(CHR7CH2O)b—R8 wherein:
R7 is selected from a hydrogen or an alkyl of 1 to 7 carbons;
b is an integer from 1 to the number sufficient to provide a molecular weight of up to 200,000 for the CHR7CH2O— group;
R8 is selected from the group consisting of hydrogen, an alkyl of 1 to 9 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
—C(O)—NHR9 group wherein:
R9 is a hydrogen or an alkyl of 1 to 20 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, alcohol, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
—C6H4—R10 group wherein:
R10 is selected from:
a hydrogen or an alkyl optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
a reactive group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate, anhydride and
—(O(CHR11CH2O)d—R12 wherein:
R11 is a hydrogen or an alkyl of 1 to 7 carbons;
d is an integer from 1 to the number sufficient to provide a molecular weight of up to 200,000 for the CHR11CH2O— group;
R12 is selected from the group consisting of hydrogen, an alkyl of 1 to 9 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
C6H4—O—R13 group wherein:
R13 is selected from:
a hydrogen, an alkyl optionally substituted with a reactive group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, alcohol, phosphate and anhydride;
a reactive group selected from the group consisting of epoxy, silane, phosphate alkene, alkyne, azide, acrylate, anhydride and
—(CHR14CH2O)e—R15 wherein:
R14 is a hydrogen or an alkyl of 1 to 7 carbons;
e is an integer from 1 to the number sufficient to provide a molecular weight of up to 200,000 for the —CHR14CH2O— group;
R15 is selected from the group consisting of a hydrogen and an alkyl of 1 to 9 carbons optionally substituted with a functional group selected from the group consisting of hydroxyl, carboxyl, amine, epoxy, silane, amide, phosphate, imide, thiol, alkene, alkyne, azide, acrylate and anhydride;
x, y and z, taken together are sufficient to form a polyanion with a molecular weight of at least 100 to no more than 500,000 and y/x is 0.01 to 100; z is 0 to a ratio z/x of no more than 100; and
with the proviso that when z is not zero C is not the same group as B and B is not a polymerized monomer of acrylate, methacrylate or an alkoxysilane.

US Pat. No. 10,340,090

ELECTROLYTIC CAPACITOR, AND PRODUCTION METHOD THEREFOR

PANASONIC CORPORATION, O...

1. An electrolytic capacitor comprising:an anode body;
a dielectric layer formed on the anode body;
a first conductive polymer layer covering at least a part of the dielectric layer;
a second conductive polymer layer covering at least a part of the first conductive polymer layer; and
an intermediate layer formed between the first conductive polymer layer and the second conductive polymer layer; wherein:
the intermediate layer comprises a cation agent containing a cationic group, and an anion agent containing a first anionic group and a second anionic group;
the first anionic group is a sulfonate group;
the second anionic group is at least one of species selected from a phosphate group and a phosphonate group; and
in the intermediate layer, a total of a number of the first anionic group and a number of the second anionic group is larger than a number of the cationic group.

US Pat. No. 10,340,089

METHOD FOR PRODUCING ELECTROLYTIC CAPACITOR

PANASONIC INTELLECTUAL PR...

1. A method for producing an electrolytic capacitor, the method comprising:a first step of preparing a capacitor element that includes an anode body having a dielectric layer;
a second step of impregnating the capacitor element with a first treatment solution containing at least a conductive polymer and a liquid solvent including a first solvent; and
a third step of impregnating, after the second step, the capacitor element, in which at least a part of the first solvent remains, with a second treatment solution containing a coagulant to coagulate the conductive polymer,
wherein a remaining amount of the liquid solvent in the capacitor element to be subjected to the third step is 5% by mass or more relative to a mass of the of the liquid solvent contained in the first treatment solution impregnated into the capacitor element in the second step.