US Pat. No. 10,248,662

GENERATING DESCRIPTIVE TEXT FOR IMAGES IN DOCUMENTS USING SEED DESCRIPTORS

Google LLC, Mountain Vie...

1. A method performed by data processing apparatus, the method comprising:identifying a set of one or more seed descriptors for a given image in a given document;
for each seed descriptor:
identifying a location of at least one word of the seed descriptor in the given document by comparing each word of the seed descriptor to text included in the given document;
in response to identifying the location of the at least one word of the seed descriptor in the given document, generating one or more templates for the given image and the seed descriptor, each template including:
image location information specifying a location of the given image within the given document;
document structure information specifying a structure of the given document with respect to the given image and the seed descriptor, including a location of a given string of text that includes the at least one word of the seed descriptor within the given document with respect to the location of the given image within the given document;
image feature information specifying one or more feature values for one or more image features of the given image, each feature value representing a respective visual characteristic of the given image or data regarding an image file in which the given image is stored; and
for each generated template:
identifying a set of one or more documents that each have (i) an image that has at least one image feature that matches a corresponding image feature of the given image specified by the generated template and (ii) a string of text in the document that is located at a same location with respect to the image as the location of the given string of text with respect to the given image specified by the generated template; and
for each document in the set of documents:
generating descriptive text for the image of the document using the generated template and the document; and
associating the descriptive text with the image.

US Pat. No. 10,248,658

ANALYTICS AND DEDUPLICATION FOR AIR-GAPPED LOG ANALYSIS

International Business Ma...

1. A computer program product for data storage management, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the device to perform a method comprising:capturing an image of at least one log entry, wherein the image of the at least one log entry is a still image;
encrypting the image of the at least one log entry;
converting text in the image of the at least one log entry to machine-encoded text;
encrypting the machine-encoded text of the at least one log entry;
scanning the machine-encoded text for at least one redundant copy of the at least one log entry;
removing the at least one redundant copy of the at least one log entry;
determining if the at least one log entry is significant, wherein the determining determines that the at least one log entry is significant if a number of the at least one redundant copy of the a least one log entry is greater than a threshold number of redundant copies of log entries in a designated time span;
flagging the at least one log entry if the at least one log entry is significant; and
alerting a user if the at least one log entry is flagged.

US Pat. No. 10,248,656

REMOVAL OF REFERENCE INFORMATION FOR STORAGE BLOCKS IN A DEDUPLICATION SYSTEM

INTERNATIONAL BUSINESS MA...

1. A method for managing data in a data storage having data deduplication, comprising:under control of a processor and memory having executable instructions, performing:
for a back reference data structure incorporating reference information for at least one user data segment to a storage block, removing, by the processor, a user data segment identification (ID) representative of the at least one user data segment from the back reference data structure, the storage block being associated with both a reference counter and the user data segment ID of the back reference data structure; wherein the removal of the user data segment ID is performed in response to determining that the at least one user data segment no longer references the storage block caused by failed data, thereby maintaining the back reference data structure so as to facilitate an efficient search operation for recovering or reclaiming the failed data within the data storage;
configuring the back reference data structure by partitioning the back reference data structure as form type bits specifying a type of the ID representative of the at least one user data segment, and storage bits storing the ID of a representation of the ID thereof;
defining a plurality of form types corresponding to the form type bits;
defining a first form type structure incorporating a full representation of the ID of the at least one user data segment to be stored in the back reference data structure;
storing the defined first form type structure in the back reference data structure;
defining second, intermediate form type structures implementing a hashed form of the at least one user data segment ID to be stored in the back reference data structure;
storing the defined second, intermediate form type structures in the back reference data structure;
defining a third form type structure implementing a representation of the at least one user data segment ID as a bit bucket in a hash table of the at least one user data segment to be stored in the back reference data structure; and
storing the third form type structure in the back reference data structure; wherein a total number of the at least one user data segment ID increases as a bit per ID correspondingly decreases when migrating from the first form type through the second form types to the third form type.

US Pat. No. 10,248,655

FILE STORAGE SYSTEM, CACHE APPLIANCE, AND METHOD

Avere Systems, Inc., Pit...

1. A network file system comprising one or more processors and memory storing executable instructions which, when executed by the one or more processors configure the network file system with an architecture for managing cache appliances used for storing data, wherein the cache appliances are managed using a synchronization mechanism that ensures that all references to a cached file are up-to-date, even when a file is written through multiple cache appliances concurrently, and wherein the configured network file system comprises:a plurality of backend servers in which data is stored;
a plurality of token servers that each control access to the stored data using stored tokens, wherein the tokens are used to ensure cache coherence when data is updated at a cache appliance, and wherein the stored tokens comprise:
a write data token for files stored in the backend server, and wherein the write data token ensures that no two write data tokens are granted over a single byte of any same file;
a write attribute token for files stored in the backend server, and wherein the write attribute token ensures that no two write attribute tokens are granted for the same file;
ownership tokens that allow a given cache appliance to read data from another cache appliance; and
wherein each token server is configured to revoke an already granted write data token or a write attribute token by recalling the granted write data token or write attribute token if a new write data token or a new write attribute token is requested by a cache appliance and is incompatible with the already granted write attribute token or the already granted write data token, so that cache coherence is provided;
a plurality of cache appliances, wherein each cache appliance comprises:
a cache manager module which executes a client request to access stored data, wherein the request is executed by obtaining one or more tokens from a particular token server and accessing cache attributes and cache data in accordance with the one or more obtained tokens;
a token client module which determines the particular token server that is to be accessed when obtaining the tokens in response to the client request for access to the stored data; and
an NFS client module which sends calls for stored data to any of the backend servers, wherein the ownership tokens allow the given cache appliance to read data from another cache appliance associated with any of the backend servers.

US Pat. No. 10,248,654

VIRTUAL MACHINE OBJECT VERSION CONTROL

Nutanix, Inc., San Jose,...

1. A method for implementing a virtual machine snapshot index in a virtualization environment, the method comprising:receiving an initiation signal that initiates sending of at least one quiescence request to at least one user virtual machine;
quiescing the at least one user virtual machine by at least transmitting the at least one quiescence request to the at least one user virtual machine;
confirming that the at least one user virtual machine is quiesced based on at least receipt of an acknowledgement signal from the at least one user virtual machine, the acknowledgement signal indicating that the at least one user virtual machine has quiesced;
requesting and receiving a set of virtual machine attribute values from the at least one user virtual machine while the at least one user virtual machine is quiesced;
generating a volume index data structure comprising at least some of the set of virtual machine attribute values received from the at least one user virtual machine while the at least one user virtual machine is quiesced; and
storing the volume index data structure comprising the at least some of the set of virtual machine attribute values received from the at least one user virtual machine while the at least one user virtual machine is quiesced.

US Pat. No. 10,248,652

VISUAL WRITING AID TOOL FOR A MOBILE WRITING DEVICE

Google LLC, Mountain Vie...

1. A computer-implemented method of providing a visual writing aid in a second language, comprising:obtaining, by one or more computing devices, data descriptive of a first set of information, wherein the first set of information is presented in a first language;
determining, by the one or more computing devices, a translation of the first set of information to a second language;
presenting, by the one or more computing devices, a visual representation of the translation of the first set of information in the second language via a display device;
obtaining, by the one or more computing devices, data descriptive of a second set of information, wherein the second set of information comprises a transcription of at least a portion of the translation of the first set of information in the second language, the transcription generated by a user of a mobile writing device via the mobile writing device; and
determining, by the one or more computing devices, whether the second set of information corresponds to the visual representation of the translation of the first set of information in the second language, whereby user aid in transcribing the translation is promoted.

US Pat. No. 10,248,650

IN-CONTEXT EXACT (ICE) MATCHING

SDL Inc., Wakefield, MA ...

1. A method for determining an in-context exact (ICE) match from context matching levels of a plurality of source texts stored in a translation memory to a lookup segment to be translated, the method comprising:generating a preceding usage context hash code for a preceding segment, based on a text stream for the preceding segment next to the lookup segment;
generating a post usage context hash code for a post segment, based on a text stream for the post segment next to the lookup segment;
determining any exact matches for the lookup segment in the plurality of translation memory source texts;
calculating for each exact match a context matching level based on:
a match between the preceding usage context hash code for the lookup segment and a preceding usage context hash code generated for a segment of a translation memory source text, and
a match between the post usage context hash code for the lookup segment and a post usage context hash code generated for the segment of the translation memory source text; and
determining, for each exact match, if the segment of the translation memory source text providing the exact match is an ICE match for the lookup segment based on the calculated context matching level.

US Pat. No. 10,248,647

STYLE EXTENSIBILITY APPLIED TO A GROUP OF SHAPES BY EDITING TEXT FILES

MICROSOFT TECHNOLOGY LICE...

1. A system for providing style extensibility in a diagram, the system comprising:a semantic model in the form of a text-based tree diagram of lines of text entered by a user that create and define elements in the diagram and hierarchical relationships between each of the elements of the diagram, wherein a hierarchical level for each of the elements within the diagram is based on a position of each line of text entered by the user within the semantic model, and wherein each element that is located on a different line in the semantic model is displayed as a different element within the diagram determined from the semantic model;
a style label assigned to each of the elements of the diagram based on the hierarchical level of each of the elements within the semantic model of the defined hierarchical relationships such that each element at a same hierarchical level is assigned a same style label, wherein the style label associates the elements of the diagram with style definitions independent of a layout definition, and wherein the elements of the diagram comprise: objects, connectors and content; and
a style definition for each object of the diagram generated from the semantic model determined by locating a matching style label within a file that comprises style definitions, wherein the diagram is rendered based on the layout definition and the determined style definitions.

US Pat. No. 10,248,646

TOKEN MATCHING IN LARGE DOCUMENT CORPORA

COGNIGO RESEARCH LTD., T...

1. A method comprising:in a populating stage, receiving a dictionary comprising a plurality of entities, wherein each entity has a length of between 1 and n tokens;
automatically constructing a probabilistic data representation model comprising n Bloom filter (BF) pairs, wherein each BF pair is indexed from 1 to n;
automatically populating said probabilistic data representation model with a data representation of said entities, wherein, with respect to each BF pair indexed i:
(i) a first BF in said BF pair is populated with the first i tokens of all said entities having at least i+1 tokens, and
(ii) a second BF in said BF pair in populated with all said entities having exactly i tokens;
in a matching stage, receiving a text corpus, wherein said text corpus is segmented into tokens; and
automatically matching each token in said text corpus against said populated probabilistic data representation model, wherein said matching comprises sequentially querying each said BF pair in the order of said indexing, to determine a match.

US Pat. No. 10,248,645

MEASURING PHRASE ASSOCIATION ON ONLINE SOCIAL NETWORKS

Facebook, Inc., Menlo Pa...

1. A method comprising, by a computing device:receiving, from a client system of a first user of an online social network, a search query for posts of the online social network, the search query comprising one or more query terms;
retrieving a plurality of posts of the online social network, each post containing each of the one or more query terms in a text of the post;
identifying, from an index of known phrases, one or more known phrases in the text of the one or more retrieved posts, each identified known phrase containing at least one of the one or more query terms, wherein the index of known phrases comprises a plurality of pre-identified phrases having a length less than or equal to a pre-determined maximum length;
filtering the plurality of retrieved posts to generate a filtered set of posts, wherein the filtering comprises removing each post not containing at least one of the identified known phrases;
computing a plurality of features for each of the identified known phrases, each feature measuring a degree of equivalence between the identified known phrase and the one or more query terms included in the identified known phrase;
calculating, for each post in the filtered set of posts, a score for the post based on the plurality of features of the identified known phrases included in the post;
ranking the posts based on the calculated scores; and
sending, to the client system in response to the search query, instructions for generating a search-results interface comprising references to one or more of the posts presented in ranked order.

US Pat. No. 10,248,640

INPUT-MODE-BASED TEXT DELETION

MICROSOFT TECHNOLOGY LICE...

1. A method being performed by one or more computing devices including at least one processor, the method for deleting textual input and comprising:receiving a first text portion via a block-unit input mode;
converting the first text portion into a first typewritten text segment, the first typewritten text segment having character-units that comprise at least a first recognizable block-unit, each block-unit of the at least the first recognizable block-unit having a plurality of character-units;
receiving a second typewritten text segment via a character-based input mode, the second typewritten text segment having character-units that comprise at least a second recognizable block-unit, each block-unit of the at least the second recognizable block-unit having a plurality of character-units;
detecting a location of a boundary between the first typewritten text segment that was input via the block-unit input mode and the second typewritten text segment that was input via the character-based input mode;
visually designating the boundary;
receiving a plurality of delete commands, wherein a first portion of the plurality of delete commands directs deletion of at least a portion of the first typewritten text segment, and wherein a second portion of the plurality of delete commands directs deletion of at least a portion of the second typewritten text segment; and
subsequent to the receiving the plurality of delete commands, deleting at least a portion of the first and second typewritten text segments, wherein the deleting comprises: deleting at least a portion of the first typewritten text segment on a block-unit basis, one block unit being deleted for each of the first portion of the plurality of delete commands; detecting the boundary between the first and second typewritten text segments; and based on the detecting the boundary, altering the delete command so that at least a portion of the second typewritten text segment is deleted on a character by character basis, one character unit being deleted for each of the second portion of the plurality of delete commands.

US Pat. No. 10,248,637

HIGH PERCEPTABILITY INK EFFECTS

MICROSOFT TECHNOLOGY LICE...

1. A method for improving pattern perceptibility as applied to an ink object, comprising:selecting a contrast basis image and, based on the selected contrast basis image, defining a plurality of contrast values to be applied in an enhanced ink effect definition;
selecting a color image and, based on the color image, defining color values to be applied in the enhanced ink effect definition;
defining a contrast filter for each of the defined plurality of contrast values, wherein defining the contrast filter includes isolating a selected portion of the contrast values of the contrast basis image, wherein each of the plurality of contrast filters includes an isolated selected portion of the contrast values that is different from the isolated selected portion of contrast values of the other of the plurality of contrast filters, and wherein the isolated selected portion of contrast values for each of the plurality of contrast filters is selected to include only one of: high-tone contrast values, mid-tone contrast values or low-tone contrast values; and
applying, serially, each of the contrast filters atop the color image and atop any contrast filters previously applied to produce the enhanced ink effect definition.

US Pat. No. 10,248,636

ELECTRONIC DEVICE FOR CONTROLLING DELETION OF CHARACTER INPUT ON CHARACTER INPUT SCREEN, CHARACTER INPUT CONTROL METHOD FOR CONTROLLING DELETION OF CHARACTER INPUT ON CHARACTER INPUT SCREEN, AND STORAGE MEDIUM STORING THEREIN CHARACTER INPUT CONTROL METHO

KYOCERA Document Solution...

1. A character input control method comprising:detecting a character input key being pressed, and in response to the detection of a character input key being pressed, displaying a character corresponding to the character input key at a position of a cursor displayed on a character input screen;
selecting a deletion mode; and
detecting a single press on a character delete key, and in response to detecting a single press on a character delete key, deleting at least one character displayed on the character input screen,
wherein the displaying a character corresponding to the character input key includes:
upon detecting the character input key being pressed, displaying the character corresponding to the character input key as an unconfirmed character on the character input screen, the unconfirmed character being a character input of which is to be confirmed when a confirmation key is pressed;
acquiring and unconfirmed character or a character string of unconfirmed characters displayed on the character input screen;
determining that the unconfirmed character or the character string is not a candidate for any word registered in the word table; and
in response to determining that the unconfirmed character or the character string is not a candidate for any word registered in the word table, acquiring a character input through a character input key just before the determination and storing in storage an unconfirmed character that makes word prediction impossible the acquired character as a deletion start character,
the deleting at least one character includes:
deleting the at least one character in a first deletion mode in which the deletion start character is deleted or the deletion start character and at least one unconfirmed character immediately preceding or following the deletion start character are deleted;
deleting the at least one character in a second deletion mode in which all unconfirmed characters are deleted;
deleting the at least one character in a third deletion mode in which a designated number of characters immediately preceding or following the cursor are deleted; and
deleting the at least one character in a fourth deletion mode in which only one character immediately preceding or following the cursor is deleted, and
the selecting a deletion mode includes selecting one of the first through fourth deletion modes.

US Pat. No. 10,248,634

MODEL-DRIVEN DATA ENTRY VALIDATION

Oracle International Corp...

1. A method comprising:at a computer system having a processor and a memory storing a document readable by an application:
receiving information from an application server specifying a user interface component in response to the application processing the document,
wherein the application includes or is in communication with the application server via a client side component of an application development framework (ADF),
wherein the user interface component is a re-usable component of the ADF linked to an attribute of a data model of the application server to integrate the document with a web-based application developed on the ADF; and
wherein the document is configured to act as a user interface for the web-based application by extending functionality provided by the web-based application to the application, and the user interface comprises the user interface component;
determining, by the client side component, a set of validation rules associated with the user interface component based on the information received from the application server;
receiving, at the computer system, data representing the attribute of the data model from the application server responsive to processing the document;
rendering, using the processor, the document to include the user interface component, the set of validation rules, and the data, wherein the rendering includes configuring, using the processor, the application using the set of validation rules to perform a validation of input that is made within the application via the user interface component;
receiving an input made via the user interface component; and
performing, using the processor, one or more actions by the application in response to the application validating the input made via the user interface component using the set of validation rules.

US Pat. No. 10,248,633

CONTENT BROWSER SYSTEM USING MULTIPLE LAYERS OF GRAPHICS COMMANDS

Amazon Technologies, Inc....

1. A system configured to act as an intermediary between user devices and content servers, the system comprising one or more hardware computing devices, wherein the system is programmed to at least:receive a request for a content page hosted by a content server;
obtain a base file of the content page and a resource referenced by the base file;
generate, using a server-side browser application executing on the one or more computing devices, a first set of hardware-independent graphics commands, wherein the first set of hardware-independent graphics commands instructs a client-side browser application to display a first layer comprising a representation of at least a first text portion of the content page;
generate, using the server-side browser application, a second set of hardware-independent graphics commands, wherein the second set of hardware-independent graphics commands instructs the client-side browser application to display a second layer comprising a representation of at least a second text portion of the content page;
generate, using the server-side browser application, text data regarding text to be graphically represented by at least one of the first or second sets of hardware independent graphics commands, wherein the text data enables a user device to process a user interaction with the first layer independently of the second layer; and
transmit the text data and the first and second sets of hardware-independent graphics commands to the user device over a network.

US Pat. No. 10,248,630

DYNAMIC ADJUSTMENT OF SELECT ELEMENTS OF A DOCUMENT

Microsoft Technology Lice...

1. A computer-implemented method, the method comprising:rendering, at a computing device, a document including a formatting element and text arranged within a boundary of the formatting element, wherein the boundary maintains the text within a viewing area of a display device;
receiving a command to apply a first scale factor to the text of the document;
determining at least one dimension of the boundary of the formatting element of the document based on a second scale factor that is based on an inverse of the first scale factor;
rendering the document, wherein the text is rendered based on the first scale factor, and wherein the at least one dimension of the boundary is rendered based on the second scale factor that is based on the inverse of the first scale factor, wherein a magnitude of the second scale factor is adjusted above the inverse of the first scale factor based on an increase of a magnitude of the first scale factor, and wherein the boundary is rendered to maintain the text within the viewing area of the display device; and
in response to the rendering of the document, displaying the text without requiring a user to scroll horizontally or vertically to view the rendered text.

US Pat. No. 10,248,629

METHOD FOR DETERMINING WIRING RISK AND WIRING RISK DETERMINATION SYSTEM

MITSUBISHI AIRCRAFT CORPO...

1. A method for determining a wiring risk, comprising:identifying a number of connectors to which a target harness identified from a plurality of harnesses is indirectly connected;
determining, based on the identified number of connectors, a first risk that electric wires connected to a plurality of terminal devices are bundled into a single harness;
matching location information of the target harness to an influenced area by a hazard source;
identifying whether the target harness passes through the influenced area; and
determining, based on the matched location information and identification of whether the target harness passes through the influenced area, a second risk that harnesses fail at the same time in a wiring system in which the plurality of harnesses are provided between the plurality of terminal devices and connected via connectors; and
changing at least one of the plurality of harnesses based on the determined first risk or the determined second risk in a manner that reduces the determined first risk or the determined second risk.

US Pat. No. 10,248,628

STATISTICAL APPROACH FOR TESTING MULTIPLE VERSIONS OF WEBSITES

Hybris AG, Zug (CH)

1. A computer-implemented method for selection of a version of a website from multiple versions of the website, the method being executed by one or more processors and comprising:receiving, by the one or more processors, user interaction data representative of user interactions with respective versions of a website;
for each version of the website, determining, by the one or more processors, a posterior distribution as:
f(?i(i=1, . . . ,k)|n1,n2, . . . ,nk,n)=f(n1+?1,n2+?2, . . . ,nk+?k)(?1,?2, . . . ,?k)
where n is the total number of users visiting a respective version k of the website, ? is a shape parameter, and ? is a probability of one or more users visiting the respective version k of the website, and values of ? for the users are determined as:

selecting, by the one or more processors, a version of the website based on the posterior distributions; and
hosting, by the one or more processors, the version of the website on one or more servers.

US Pat. No. 10,248,626

METHOD AND SYSTEM FOR DOCUMENT SIMILARITY ANALYSIS BASED ON COMMON DENOMINATOR SIMILARITY

EMC IP Holding Company LL...

1. A method for document similarity analysis, the method comprising:obtaining a document to be archived;
identifying a document category similar to the document to be archived, based on indexing terms and corresponding term frequencies, comprising:
identifying a document category that includes a plurality of indexing terms that are identical to indexing terms identified in the document to be archived;
obtaining a term frequency vector for the identical indexing terms in the document to be archived;
generating a normalized term frequency vector, from the term frequency vector for the document to be archived;
obtaining a term frequency vector for the identical indexing terms in the identified document category;
generating a normalized term frequency vector, from the term frequency vector for the identified document category;
calculating a common denominator similarity based on the normalized term frequency vector for the document to be archived, the normalized term frequency vector for the identified document category, and a common denominator;
making a determination that the document category is similar to the document to be archived based on the common denominator similarity; and
registering the document to be archived in the document category.

US Pat. No. 10,248,623

DATA DEDUPLICATION TECHNIQUES

EMC IP Holding Company LL...

1. A method of processing data comprising:receiving, using a processor, a plurality of data portions of a logical device;
determining, using a processor, a plurality of hash values for the plurality of data portions, each of the plurality of data portions having a corresponding one of the plurality of hash values;
determining, using a processor, whether a first of the plurality of hash values associated with a first of the plurality of data portions is equal to a hash value of an implied data value; and
if it is determined that the first hash value is equal to the hash value of the implied data value, performing, using a processor, first processing comprising:
determining whether the first data portion has a current data value equal to the implied data value; and
responsive to determining that the first data portion has a current data value equal to the implied data value, performing second processing including updating first metadata for the first data portion with an indicator to denote that the first data portion has said implied data value, wherein the implied data value is a particular data value implied by the indicator and the first data portion is not associated with any storage storing the particular data value implied by the indicator, wherein the indicator is a non-pointer field of the first metadata, wherein an operation to read the first data portion includes determining the particular data value implied by the indicator using only the indicator without accessing a stored value that is the particular data value, and wherein the method is performed as part of data deduplication processing, and wherein no data deduplication is performed for the first data portion and any other ones of the plurality of data portions equal to the implied data value.

US Pat. No. 10,248,622

VARIABLE VIRTUAL SPLIT DICTIONARY FOR SEARCH OPTIMIZATION

SAP SE, Walldorf (DE)

1. A computer implemented method to optimize data searching in an in-memory database stored as a column store, the method comprising:assigning priorities to a plurality of attribute vectors including value identifiers that represent values of corresponding columns of a table of structured data;
basing the priorities for each of the plurality of attribute vectors on a frequency of data access from each respective attribute vector of the plurality of attribute vectors;
a processor of a computer executing a reordering optimization model to reorder the plurality of attribute vectors based on corresponding sequence scores, the corresponding sequence scores computed based on one or more of the assigned priorities, a memory size consumed by each of the plurality of attribute vectors, a historical data access metric, and a query referencing percentage for each of the plurality of attribute vectors;
upon computing the corresponding sequence scores and reordering the plurality of attribute vectors, the processor of the computer executing a partitioning optimization model to logically partition each of the plurality of attribute vectors into a varying optimal number of logical partitions, the partitioning optimization model analyzing a tree bounding model having multiple paths between a root node and a leaf node to determine an optimal path from among the multiple paths;
determining an optimal number of logical partitions for a respective attribute vector of the plurality of attribute vectors based on conditions including the priority of the respective attribute vector and a memory constraint, the memory constraint dependent on the memory size consumed by the respective attribute vector and an amount of memory available to create logical partitions of the respective attribute vector;
based on the partitioning, for each of the plurality of attribute vectors generating one or more attribute vector blocks; and
rearranging value identifiers in the one or more attribute vector blocks to additionally optimize searching for data in the table of structured data.

US Pat. No. 10,248,619

RESTORING A VIRTUAL MACHINE FROM A COPY OF A DATASTORE

EMC IP Holding Company LL...

1. A method to restore a virtual machine comprising:receiving a selection of a point-in-time copy of the virtual machine to restore the selection being made from a plurality of point-in-time copies of virtual machines stored, a point-in-time copy of a datastore comprising the plurality of point-in-time copies of the virtual machines;
retrieving point-in-time copy information, from catalog information, the point-in-time copy information being associated with the point-in-time copy of the virtual machine selected to restore;
enabling the point-in-time copy of the virtual machine to receive I/Os for a host where the virtual machine will be restored;
mounting the datastore on the host;
modifying a virtual machine configuration file path to point to the point-in-time copy of the datastore;
registering the modified virtual machine configuration file path with the host;
determining a snapshot ID of a snapshot of the virtual machine; and
reverting to the snapshot of virtual machine.

US Pat. No. 10,248,616

MONOLITHICALLY INTEGRATED SYSTEM ON CHIP FOR SILICON PHOTONICS

INPHI CORPORATION, Santa...

1. A monolithically integrated system-on-chip device configured for a multi-rate and selected format of data communication, the device comprising:a single silicon substrate member;
a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol;
an input/output block provided on the substrate member and coupled of the data input/output interface, the input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block, the SerDes block being configured to convert a first data stream of N into a second data stream of M, each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate;
a signal processing block provided on the substrate member and coupled to the input/output block, the signal processing block configured to the input/output block;
a driver module provided on the substrate member and coupled to the signal processing block, the driver module coupled to the signal processing block;
a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device, the driver interface being configured to transmit output data in either an amplitude modulation format or a combination of phase/amplitude modulation format or a phase modulation format;
a receiver module comprising a TIA block provided on the substrate member and to be coupled to the silicon photonics device using predefined modulation format, and configured to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface;
a laser coupled to the silicon photonics device;
a communication block provided on the substrate member and operably coupled to the input/output block, the signal processing block, the driver block, and the receiver block;
a communication interface coupled to the communication block; and
a control block provided on the substrate member and coupled to the communication block.

US Pat. No. 10,248,613

DATA BUS ACTIVATION IN AN ELECTRONIC DEVICE

QUALCOMM Incorporated, S...

16. An electronic device, comprising:a data bus comprising a clock line and at least one data line;
a host circuit coupled to the data bus and configured to:
determine a cumulative potential representing a cumulative fractional bus activation vote on the at least one data line; and
activate the clock line in response to determining the cumulative potential on the at least one data line being greater than a configurable bus activation threshold; and
a plurality of device circuits coupled to the data bus, wherein at least one selected device circuit among the plurality of device circuits is configured to:
determine a signal strength of an incoming signal;
compare the determined signal strength against one or more predefined signal strength thresholds to determine a selected signal strength threshold among the one or more predefined signal strength thresholds, wherein the selected signal strength threshold is less than the determined signal strength; and
assert at least one fractional potential corresponding to the selected signal strength threshold on the at least one data line in response to determining the selected signal strength threshold, wherein the at least one fractional potential represents at least one fractional bus activation vote in the cumulative fractional bus activation vote.

US Pat. No. 10,248,610

ENFORCING TRANSACTION ORDER IN PEER-TO-PEER INTERACTIONS

MELLANOX TECHNOLOGIES, LT...

1. A method for computing, comprising:receiving in a network interface controller (NIC), which is configured as a first peripheral device in a computer and couples the computer to a packet data network, data transmitted over the network in a remote direct memory access (RDMA) operation;
writing the data in a first bus transaction over a peripheral component bus in the computer from the NIC to a second peripheral device in the computer;
after executing the first bus transaction, submitting a completion notification from the NIC to a central processing unit (CPU);
in response to the completion notification, submitting a command from the CPU to one of the first and second peripheral devices to execute a second bus transaction, subsequent to the first bus transaction, that will flush the data from the peripheral component bus to the second peripheral device;
executing the second bus transaction in response to the command; and
following completion of the second bus transaction, processing the written data in the second peripheral device.

US Pat. No. 10,248,608

CONTROLLER CIRCUIT AND METHOD FOR ESTIMATING TRANSMISSION DELAY

SILICON MOTION, INC., Jh...

1. A controller circuit, comprising:a first signal processing device, configured to process signals;
a second signal processing device, configured to process signals, wherein the first signal processing device and the second signal processing device are disposed on different platforms;
a data bus, coupled between the first signal processing device and the second signal processing device and comprising a plurality of data lines; and
a confirm signal line, coupled between the first signal processing device and the second signal processing device,
wherein the first signal processing device transmits at least one synchronization signal to the second signal processing device via the data bus, the second signal processing device estimates transmission delay on each data line according to the at least one synchronization signal, performs transmission delay compensation according to the transmission delay estimated on each data line and transmits a confirmation signal on the confirm signal line to notify the first signal processing device that the transmission delay compensation on the data lines is complete.

US Pat. No. 10,248,606

I/O MODULE

YOKOGAWA ELECTRIC CORPORA...

1. An input/output (I/O) module, comprising:a base plate comprising a plurality of connection terminals, the connection terminals being electrically connectable to a plurality of field devices;
a plurality of universal circuits associated with the connection terminals, the universal circuits being provided on the base plate, and each of the plurality of universal circuits being configured to receive analog signals from respective one of the plurality of field devices, to output analog signals to the respective one of the plurality of field devices, to receive discrete signals from the respective one of the plurality of field devices, and to output discrete signals to the respective one of the plurality of field devices; and
a plurality of option modules detachably provided on the base plate, each of the option modules being provided between respective one of the connection terminals and respective one of the universal circuits, the respective one of the connection terminals being associated with the respective one of the universal circuits, and each of the option modules comprising a first circuit configured to perform transmitting of signals between the respective one of the connection terminals and the respective one of the universal circuits.

US Pat. No. 10,248,605

BIDIRECTIONAL LANE ROUTING

Hewlett-Packard Developme...

1. An apparatus, comprising:a pass-through module that includes connector pins to connect with at least one active motherboard connector and to separately connect with at least one routing motherboard connector; and
a routing function on the pass-through module to redirect a set of bidirectional lanes from the connector pins connected to the at least one active motherboard connector to the connector pins connected to the at least one routing motherboard connector to enable a connection of the set of bidirectional lanes to at least one other motherboard connector via the at least one routing motherboard connector,
wherein the pass-through module connector pins include an install pin to notify a motherboard controller that the pass-through module is installed and to enable the motherboard controller to reapportion the set of bidirectional lanes to the at least one other motherboard connector.

US Pat. No. 10,248,604

MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP

Cypress Semiconductor Cor...

1. A configurable analog processing circuit, comprising:a plurality of analog circuit blocks, each configured to provide at least one analog function;
a programmable interconnect coupled to the analog circuit blocks, the programmable interconnect configurable to interconnect combinations of at least two of the plurality of analog circuit blocks to one another to perform at least another analog function; and
at least one digital block of a plurality of digital blocks that each provides at least one digital function, and wherein the programmable interconnect is further coupled to the plurality of digital blocks and configurable to interconnect combinations of the plurality of digital blocks to one another,
wherein the circuit is formed in an integrated circuit and wherein the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the integrated circuit,
wherein the plurality of switches are configured in one or more multiplexer (MUX) circuits, the MUX circuits comprising MUX inputs and MUX outputs coupled to the analog circuit blocks.

US Pat. No. 10,248,603

PCI EXPRESS NETWORK CARD

ACCTON TECHNOLOGY CORPORA...

1. A PCI Express network card, comprising:a circuit board having five ports, each of which is adapted to be electrically connected to a small form-factor pluggable transceiver;
a plate provided on the circuit board near a front edge of the circuit board, wherein the plate has a plurality of openings;
a plurality of integrated circuits provided on a surface of the circuit board, wherein the integrated circuits comprise a first processor and a second processor; the first processor and the second processor are respectively connected to different parts of the ports; the first processor is directly electrically connected to a part of the ports, while the second processor is directly electrically connected to another part of the ports; the first processor and the second processor are staggered on the surface; and
two heat sinks abutting against the first processor and the second processor, respectively, wherein an area of each of the heat sinks is greater than an area of each one of the first processor and the second processor.

US Pat. No. 10,248,602

COMPUTING DEVICES HAVING SLOTS AND COMPONENTS FOR RECEIPT OF DIFFERENT TYPES OF PERIPHERALS

Lenovo Enterprise Solutio...

1. A computing device comprising:a body with a top wall, a side wall, and an interior, wherein the interior comprises a rear wall with a first slot that extends within a first horizontal plane and into the interior and enables a connection with a plurality of peripherals of a first protocol,
wherein the rear wall comprises a plurality of openings that extend within a first vertical plane;
a motherboard comprising a second slot, a third slot, and a rear edge, wherein the second and the third slots are of a same size that extends out of the interior at a second protocol,
wherein the motherboard is housed within the interior of the body and the rear edge of the motherboard is oriented such that the second slot, and the third slot is aligned co-planarly with the first slot; and
a connector, operatively interfaced with the motherboard and positioned at the rear edge of the motherboard, that provides a direct connection to a second plurality of peripherals of the second protocol.

US Pat. No. 10,248,601

REMOTE TERMINAL UNIT (RTU) WITH UNIVERSAL INPUT/OUTPUT (UIO) AND RELATED METHOD

Honeywell International I...

1. An apparatus comprising:a remote terminal unit (RTU) comprising:
input/output (I/O) terminals configured to be coupled to at least one industrial control and automation field device;
one or more first I/O modules comprising one or more first reconfigurable I/O channels, each first reconfigurable I/O channel configured to be coupled to a pair of the I/O terminals, each first reconfigurable I/O channel configurable as an analog input, an analog input supporting digital communication, an analog output, an analog output supporting digital communication, a digital input, a digital output, and a pulse accumulator input for communication through the pair of I/O terminals;
each of the one or more first reconfigurable I/O channel comprises:
a digital logic block configured to control operating states for devices connected to the pair of I/O terminals using logic signals;
an analog common resource block configured to convert digital and analog signals between the digital logic block and the pair of I/O terminals;
a multiplexer block configured to receive a current signal from the analog common resource block and output a voltage signal to the analog common resource block; and
an output circuit block that comprises a plurality of switches and is configured to:
connect the current signal from the analog common resource block to a first I/O terminal of the pair of I/O terminals; and
connect a second I/O terminal of the pair of I/O terminals to an input of the multiplexer block;
a first expansion board coupled to the one or more first I/O modules;
a second expansion board configured to be coupled to one or more second I/O modules comprising one or more second reconfigurable I/O channels, wherein the second expansion board is connected to the first expansion board;
first and second electric paths formed through the first expansion board and the second expansion board, wherein the first and second electric paths meet at a loop after a final expansion board to indicate a lack of any additional I/O modules or additional expansion boards;
at least one processing device configured to control a configuration of each of the one or more first reconfigurable I/O channels and each of the one or more second reconfigurable I/O channels and to control the one or more second reconfigurable I/O channels through the one or more first I/O modules;
a first circuit board coupled to the I/O terminals and the first expansion board, wherein the first circuit board is further coupled to one or more serial interfaces, one or more uplink/downlink ports, and one or more transformers coupled to the first expansion board;
a second circuit board coupled to the at least one processing device, wherein the second circuit board is further coupled to one or more transceivers configured to communicate with the first circuit board; and
a third circuit board coupled to the one or more first I/O modules, wherein the third circuit board is further coupled to a power converter, the power converter configured to convert power received from the second circuit board;
wherein the first circuit board is coupled to the second and third circuit boards.

US Pat. No. 10,248,600

REMOTE CONTROL SYSTEM

INVENTEC (PUDONG) TECHNOL...

1. A remote control system for a microserver, the remote control system comprising:a plurality of computing boards is for processing data of the microserver;
a control board electrically connected to the plurality of computing boards and communicated with a remote control manager, the control board converting network signals transmitted between the plurality of computing boards and the remote control manager, the plurality of computing boards being remote-controlled by the remote control manager through the control board, and the control board comprising:
a first network physical layer protocol conversion chip electrically connected to the remote control manager, and the first network physical layer protocol conversion chip transmitting a first network signal via the remote control, the first network physical layer protocol conversion chip transforming the first network signal to an internal signal or transforming the internal signal to the first network signal;
a network signal switch module electrically connected to the first network physical layer protocol conversion chip and the plurality of computing boards, the network signal switch module receiving the internal signal from the first network physical layer protocol conversion chip, the network signal switch module transforming the internal signal to a second network signal or transforming the second network signal to the internal signal; and
a network signal processing module electrically connected to the network signal switch module, the network signal processing module generating an executive instruction according to the internal signal received by the network signal switch module, and the network signal switch module transmitting the second network signal to at least one of the plurality of computing boards according to the executive instruction,
wherein the network signal processing module comprising a basic input-output unit, a processing unit and a memory unit, the basic input-output unit stores a configuration setting of the remote control system, the processing unit is electrically connected to the basic input-output unit and the network signal switch module, and the processing unit communicates with the plurality of computing boards through the network signal switch module to detect network status of the plurality of computing boards, the processing unit produces and transmits the executive instruction to the network signal switch module according to the configuration setting of the remote control system and the internal signal so that the network signal switch module transmits the second network signal to at least one of the plurality of computing boards according to the executive instruction, the memory unit is electrically connected to the processing unit and temporary saves staged data of the processing unit.

US Pat. No. 10,248,597

USB COMMUNICATION CONTROL MODULE, SECURITY SYSTEM, AND METHOD FOR SAME

Response Technologies, Lt...

1. A USB communication control module comprising:a first USB port that comprises an input power port and is configured for electrical coupling and data communication with an associated USB device;
a first port power controller in communication with the input power port of the first USB port, the first port power controller being operable in one of a power delivery mode and a power interrupt mode, wherein when in the power delivery mode, the first port power controller facilitates delivery of power from a power source to the input power port of the first USB port, and when in the power interrupt mode, the first port power controller facilitates the interruption of power from the power source to the input power port of the first USB port;
a USB switch in data communication with the first USB port via a first communication bus and in control communication with the first port power controller via a first control bus;
a microprocessor in data communication with the USB switch via a second communication bus; wherein:
data communicated between the microprocessor and a USB device is routed over the first communication bus, through the USB switch, over the second communication bus, and through the first USB port;
the USB switch monitors the first communication bus to determine whether communication between the first USB port and the associated USB device is lost;
when communication between the first USB port and the associated USB device is lost, the USB switch facilitates temporary operation of the first port power controller in the power interrupt mode via the first control bus to restart the first USB port; and
the USB switch monitors the delivery of power from the power source to the input power port of the first USB port, and, when abnormal power conditions exist, facilitates temporary operation of the first port power controller in the power interrupt mode to restart the first USB port.

US Pat. No. 10,248,596

SYSTEMS AND METHODS FOR PROVIDING A LOWER-LATENCY PATH IN A VIRTUALIZED SOFTWARE DEFINED STORAGE ARCHITECTURE

Dell Products L.P., Roun...

1. An information handling system, comprising:an accelerator device; and
a processor subsystem having access to a memory subsystem and having access to the accelerator device, wherein the memory subsystem stores instructions executable by the processor subsystem, the instructions, when executed by the processor subsystem, causing the processor subsystem to:
receive an input/output command from an application executing on a virtual machine of a hypervisor, wherein the hypervisor is executing on the processor subsystem;
determine if the input/output command meets a predefined criteria for trapping the input/output command; and
responsive to determining that the input/output command meets a predefined criteria for trapping the input/output command, bypass a storage stack of the hypervisor by passing the input/output command to an endpoint of the accelerator device assigned for access to the hypervisor.

US Pat. No. 10,248,594

PROGRAMMING INTERRUPTION MANAGEMENT

Micron Technology, Inc., ...

1. An apparatus, comprising:a memory array; and
a controller coupled to the memory array, wherein the controller is configured to:
modify a programming operation to program a portion of the memory array to an uncorrectable state in response to detecting an interruption during the programming operation.

US Pat. No. 10,248,592

INTERRUPTED WRITE OPERATION IN A SERIAL INTERFACE MEMORY WITH A PORTION OF A MEMORY ADDRESS

MICRON TECHNOLOGY, INC., ...

1. A method comprising:identifying a first portion of a read command that includes a first portion of a memory address of a memory device, wherein the first portion of the memory address comprises a number of bits of the memory address;
identifying a memory partition of the memory device based at least in part on the number of bits;
determining that a write operation is being performed at the identified memory partition;
interrupting the write operation in response to the determination that the write operation is being performed and identifying the first portion of the read command;
identifying, after a start of the interruption and before a completion of the interruption, a second portion of the read command that includes a second portion of the memory address, wherein the second portion of the memory address comprises a remaining number of bits of the memory address, the remaining number of bits identifying one or more memory cells of the memory partition; and
reading, after the completion of the interruption, the one or more memory cells indicated by the memory address.

US Pat. No. 10,248,591

HIGH PERFORMANCE INTERCONNECT

Intel Corporation, Santa...

1. A processor device comprising:link layer logic, implemented at least in part in hardware, to generate a link layer flow control unit (flit) comprising three slots, wherein each slot is adapted to be encoded with a separate packet header, and a particular one of the slots is designated to be alternatively encoded with a link layer credit message,
wherein the link layer credit message comprises an opcode field to identify that the particular slot is encoded with a link layer credit message, a credit type field to indicate a type of credit refund included in the link layer credit message, a credit return field to indicate a number of credits to be refunded based on the link layer credit message, and at least one acknowledgement field,
wherein format of a payload of the link layer credit message is based on the type of credit refund, and the flit further comprises a field to indicate whether the link layer credit message corresponds to a deadlock free virtual networks of a system or a shared adaptive virtual network of the system.

US Pat. No. 10,248,590

SUPPORTING DIFFERENT TYPES OF MEMORY DEVICES BASED ON SERIAL PRESENSE DETECT

Hewlett-Packard Developme...

1. A computing device for supporting a plurality of different types of memory devices, comprising:a plurality of types of memory device slots on a printed circuit board (PCB) to connect a corresponding number and types of memory devices to the computing device;
a memory voltage regulator coupled to the memory device slots;
a basic input/output system (BIOS) to: determine serial presence detect (SPD) data present on a detected memory device coupled to one of the memory device slots to determine the type of the detected memory device of the number of memory device types; and
initialize the memory voltage regulator to adjust a supply voltage to a voltage required by the detected memory device based on the SPD data; and
a memory controller coupled to the memory device slots, the memory controller to control input/output signals to and from the detected memory device based on the SPD data, wherein the memory controller transmits signals common to all memory device types to the detected memory device via a first transmission line and transmits signals not common to all memory device types to the detected memory device via a second transmission line, the second transmission line being an exclusive transmission line for the type of the detected memory device.

US Pat. No. 10,248,589

INTEGRATED CIRCUIT WITH A SERIAL INTERFACE

Dialog Semiconductor (UK)...

1. An integrated circuit coupled to an external serial bus, the integrated circuit comprisinga serial interface configured to act as a bus slave with regard to the external serial bus and to detect a data address on the external serial bus;
a data cache coupled to the serial interface via an internal bus; and
a prefetch control unit configured to instruct the serial interface to prefetch a data element associated with the detected data address by causing the data element to be read from a target data storage unit associated with the data address and the data element and the data address to be written in the data cache,
wherein the prefetch control unit is configured to not instruct the serial interface to prefetch the data element in case reading data from the target data storage unit by the serial interface involves a turnaround time which is shorter than a predetermined threshold turnaround time; and
wherein the predetermined threshold turnaround time is based on a maximum response time defined by a message protocol of the external serial bus.

US Pat. No. 10,248,584

DATA TRANSFER BETWEEN HOST AND PERIPHERAL DEVICES

Microsoft Technology Lice...

1. A peripheral device comprising:a wireless communication interface arranged to communicate with a host computing device;
an output device;
a memory arranged to store an output data set for output via the output device; and
a processor arranged to:
monitor parameters of a wireless communication link between the host computing device and the peripheral via the wireless communication interface;
detect imminent disconnection of the wireless communication link based on the parameters of the wireless communication link;
trigger, in response to imminent disconnection detection, a data transfer from the host computing device to the peripheral device via the wireless communication interface;
receive, in response to the trigger, the output data set; and
display the output data set via the output device, wherein following disconnection of the wireless communication link the output data set is fixed such that the output data set does not change.

US Pat. No. 10,248,583

SIMULTANEOUS VIDEO AND BUS PROTOCOLS OVER SINGLE CABLE

TEXAS INSTRUMENTS INCORPO...

1. A system comprising:a main switch configured to:
operate in an enhanced mode in which the main switch is configured to simultaneously transfer data from a first data source and a second data source to a cable;
operate in a default mode in which the main switch is configured to transfer data from the second data source to the cable without transferring data from the first data source;
a multipurpose switch, the multipurpose switch coupled to the cable through a first set of switch connections, the multipurpose switch configured to:
operate in a handshake mode in which the multipurpose switch is configured to transport handshake data between the cable and a digital logic, wherein the handshake data is received on the first set of switch connections;
operate in a data mode in which the multipurpose switch is configured to transport bus data between the cable and the second data source, wherein the bus data is received on the first set of switch connections; and
the digital logic coupled to the multipurpose switch through a first switch control;
the digital logic coupled to the main switch through a second switch control, the digital logic programmed to:
drive the first switch control that enables a mode of operation of the multipurpose switch, the mode of operation of the multipurpose switch comprising one of the handshake mode and the data mode; and
drive the second switch control that enables a mode of operation of the main switch, the mode of operation of the main switch comprising one of the enhanced mode and the default mode.

US Pat. No. 10,248,582

PRIMARY DATA STORAGE SYSTEM WITH DEDUPLICATION

NexGen Storage, Inc., Lo...

1. A primary data storage system for use in a computer network and having de-duplication capability, the system comprising:an input/output port configured to receive a block command packet that embodies one of a read block command and a write block command and transmitting a block result packet in reply to a block command packet;
a data store system having at least a first data store and a second data store;
wherein each of the first and second data stores is capable of receiving and storing data in response to a write block command and retrieving and providing data in response to a read block command;
wherein the first data store has a first responsiveness characteristic, the second data store has a second responsiveness characteristics, and the first and the second responsiveness characteristics are different;
a statistics database configured to provide hardware and/or volume statistical data relevant to a potential deduplication of data associated with a write block command; and
a deduplication processor configured to: (a) receive a write block command and statistical data relevant to the received write block command from the statistics database, (b) determine, using the hardware and/or volume statistical data that is relevant to the potential deduplication of data associated with the write block command, if a yet to be performed deduplication operation on the data associated with the received write block command is expected to satisfy a time constraint specifically associated with the processing of the received write block command relative to the data store system, the time constraint being the difference between (i) an allowed amount of time to process the write block command that is specifically associated with the received write block command and reflects a quality of service goal and (ii) an amount of time previously expended in processing the received write block command, (c) if the yet to be performed deduplication on the data associated with the received write block command is expected to satisfy the time constraint specifically associated with the received write block command relative to the data store system, proceeding with the performance of the deduplication operation on the data associated with the received write block command, and (d) if the yet to be performed deduplication operation on the data associated with the received write block command is not expected to satisfy the time constraint specifically associated with the received write block command relative to the data store system, forgoing the performance of the deduplication operation and proceeding with the processing of the received write block command, thereby increasing the possibility that duplicate data is established on the data store system.

US Pat. No. 10,248,581

GUARDED MEMORY ACCESS IN A MULTI-THREAD SAFE SYSTEM LEVEL MODELING SIMULATION

Synopsys, Inc., Mountain...

1. A method for multi-thread system level modeling simulation (SLMS) of a target system on a host system, the target system having a plurality of processor core models that access a memory model of the target system, the method comprising:setting a memory region of the memory model of the target system into guarded mode indicating that the memory region should be locked when the memory region is accessed by one of a plurality of SLMS processes, the plurality of SLMS processes representing functional behaviors of the processor core models;
identifying an access to the memory region by an accessing SLMS process of the plurality of SLMS processes via an interconnect model of the target system, the interconnect model connecting the processor core models to the memory model; and
responsive to the access to the memory region and the memory region being in the guarded mode, acquiring a guard lock for the memory region that allows the accessing SLMS process to access the memory region via the interconnect model while the guard lock is acquired, and wherein the plurality of SLMS processes cannot access the memory region while the guard lock is acquired.

US Pat. No. 10,248,580

METHOD AND CIRCUIT FOR PROTECTING AND VERIFYING ADDRESS DATA

STMICROELECTRONICS (ROUSS...

1. A circuit for protecting memory address data, the circuit comprising:an input data bus configured to receive write data to be written to a memory device;
an input address bus configured to receive a write address associated with the write data;
an output data bus; and
an address protection circuit coupled to said input data, input address, and output data buses and configured to
generate an address protection value based on the write address,
generate modified write data, on said output data bus, the modified write data including both the write data and the address protection value, said output data bus having a width greater than a width of said input data bus, and
generate a modified write address.

US Pat. No. 10,248,579

METHOD, APPARATUS, AND INSTRUCTIONS FOR SAFELY STORING SECRETS IN SYSTEM MEMORY

Intel Corporation, Santa...

1. A processor comprising:a hardware key;
an instruction unit to receive a compare instruction, the the compare instruction having a plaintext input value and a ciphertext input value; and
an encryption unit to, in response to the compare instruction, decrypt the ciphertext input value using the hardware key to generate a plaintext output value and compare the plaintext output value to the plaintext input value.

US Pat. No. 10,248,578

METHODS AND SYSTEMS FOR PROTECTING DATA IN USB SYSTEMS

Microsoft Technology Lice...

1. A system comprising:a processor;
memory;
a USB port;
one or more unsecure client applications stored in the memory;
one or more secure client applications stored in the memory;
an unsecure software stack including at least one unsecure USB driver;
a secure software stack including at least one secure USB driver; and
a USB host controller associated with the secure software stack and the unsecure software stack;
wherein the USB host controller being configured to:
receive a transfer descriptor including instructions for routing data from a communicating USB device, coupled with the USB port, to access the memory,
determine whether the communicating USB device is a secure USB device or an unsecure USB device,
route data to and from the unsecure USB device, based on the instructions in the transfer descriptor, through the unsecure software stack for use by the one or more unsecure client applications in response to determining the communicating USB device is the unsecure USB device, and
route data to and from the secure USB device, based on the instructions in the transfer descriptor, through the secure software stack for use by the one or more secure client applications in response to determining the communicating USB device is the secure USB device.

US Pat. No. 10,248,577

USING A CHARACTERISTIC OF A PROCESS INPUT/OUTPUT (I/O) ACTIVITY AND DATA SUBJECT TO THE I/O ACTIVITY TO DETERMINE WHETHER THE PROCESS IS A SUSPICIOUS PROCESS

International Business Ma...

1. A computer program product for detecting a security breach in a system managing access to a storage, the computer program product comprising a computer readable storage medium having computer readable program code embodied therein that when executed performs operations, the operations comprising:monitoring process Input/Output (I/O) activity of a process accessing data in a storage;
determining a peak I/O rate during a time period which an I/O rate of data access was a highest I/O rate;
determining a timestamp of when the data was last accessed;
characterizing the process initiating the I/O activity as a suspicious process in response to determining a process I/O rate of the process I/O activity as compared to the peak I/O rate of the data satisfies a first condition and a process access time at which the process is accessing the data as compared to the timestamp satisfies a second condition; and
indicating a security breach in response to characterizing the process as the suspicious process.

US Pat. No. 10,248,575

SUSPENDING TRANSLATION LOOK-ASIDE BUFFER PURGE EXECUTION IN A MULTI-PROCESSOR ENVIRONMENT

International Business Ma...

1. A method for operating translation look-aside buffers, TLBs, in a multiprocessor system, the multiprocessor system comprising at least one core each supporting at least one thread, the method comprising:receiving a purge request for purging one or more entries in the TLB;
determining if a thread requires access to an entry of the entries to be purged;
when the thread does not require access to the entries to be purged:
starting execution of the purge request in the TLB;
setting a suspension time window wherein the setting of the suspension time window is performed in response to an address translation request of the thread being rejected due to the TLB purge, wherein setting further comprises providing a level signal having a predefined activation time period during which the level signal is active, wherein the suspension time window is the predefined activation time period, and wherein a rejected address translation request is recycled during a recycling time window, wherein the recycling time window is smaller than the suspension time window;
suspending the execution of the purge during the suspension time window;
executing address translation requests of the thread during the suspension time window wherein the executing of the address translation requests of the thread comprises executing the recycled address translation request;
resuming the purge execution after the suspension window is ended;
when the thread requires access to the entries to be purged:
providing a branch point having two states;
providing a second branch point having two states;
blocking the thread for preventing the thread sending address translation requests to the TLB with firmware instructions, wherein blocking the thread comprises setting the branch point to a first state, setting the second branch point to a third state, and reading the first state of the branch point, and reading the third state of the second branch point, for performing the blocking with firmware instructions;
upon ending the purge request execution,
setting the first branch point to a second state
unblocking the thread and executing the address translation requests of the thread;
wherein the at least one core supporting a second thread, and when a first thread does not require access to the TLB entries to be purged and the second thread requires access to an entry to be purged, before starting the execution of the purge request at the TLB:
blocking both the first and second threads for preventing them sending requests to the TLB; and
when the purge request has started at both the first and second threads, unblocking the first thread.

US Pat. No. 10,248,574

INPUT/OUTPUT TRANSLATION LOOKASIDE BUFFER PREFETCHING

Intel Corporation, Santa...

1. An apparatus comprising:a bridge between an input/output (I/O) side of a system and a memory side of the system, the I/O side to include an interconnect on which a zero-length transaction is to be initiated by an I/O device, the zero-length transaction to include an I/O-side memory address;
an input/output memory management unit (IOMMU) including
address translation hardware to generate a translation of the I/O-side memory address to a memory-side memory address, and
an input/output translation lookaside buffer (IOTLB) in which to store the translation; and
an IOTLB prefetch control unit including prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction and to, in response to determining that I/O device prefetching to the IOTLB is not enabled and that the I/O device is not permitted to access a system memory, generate a fault instead of emulating completion of the zero-length transaction.

US Pat. No. 10,248,573

MANAGING MEMORY USED TO BACK ADDRESS TRANSLATION STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A computer program product for facilitating memory management of a computing environment, said computer program product comprising:a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining whether a block of memory is marked as being used to back an address translation structure used by a guest program for address translation, the block of memory being a block of host memory, wherein the guest program is managed by a virtual machine manager that further manages the host memory, and wherein the determining determines whether the block of memory is actively being used for the address translation structure, the address translation structure used in translating a virtual address to another address; and
performing a memory management action based on whether the block of memory is being used to back the address translation structure, the memory management action controlling availability of the block of memory for further use, wherein memory management within the computing environment is facilitated, enhancing system performance.

US Pat. No. 10,248,572

APPARATUS AND METHOD FOR OPERATING A VIRTUALLY INDEXED PHYSICALLY TAGGED CACHE

ARM Limited, Cambridge (...

1. An apparatus, comprising:processing circuitry to perform data processing operations on data;
a cache storage to store data for access by the processing circuitry, the cache storage having a plurality of cache entries, and each cache entry arranged to store data and an associated physical address portion, the cache storage being accessed using a virtual address portion of a virtual address in order to identify a number of cache entries whose stored physical address portions are to be compared with a physical address derived from the virtual address in order to detect whether a hit condition exists; and
snoop request processing circuitry, responsive to a snoop request specifying a physical address, to determine a plurality of possible virtual address portions for the physical address, and to perform a snoop processing operation in order to determine whether the hit condition is detected for a cache entry when accessing the cache storage using the plurality of possible virtual address portions, and on detection of the hit condition to perform a coherency action in respect of the cache entry causing the hit condition.

US Pat. No. 10,248,571

SAVING POSITION OF A WEAR LEVEL ROTATION

Hewlett Packard Enterpris...

1. A system comprising:a wear level handler to start a current rotation of a wear level algorithm through a plurality of cache line addresses in a region of memory, wherein the wear level algorithm alternates between an even rotation and an odd rotation, the even rotation characterized by a first value of the metadata and the odd rotation characterized by a second value of the metadata;
a location storer to store a rotation count corresponding to a cache line address belonging to the plurality;
a data mover to move a cache line from a selected cache line address to a gap cache line address corresponding to an additional cache line address,
a metadata setter to:
set a metadata of the gap cache line address to a value corresponding to the current rotation, wherein the first cache line address becomes the current gap cache line address after the data has been copied and the metadata has been set,
set the value of the metadata to the first value if the current rotation is the even rotation,
set the value of the metadata to second value if the current rotation is the odd rotation; and
a current position determiner to determine, based on the value of at least one metadata and the rotation count, a current position of the current rotation after a power loss event.

US Pat. No. 10,248,570

METHODS, SYSTEMS AND APPARATUS FOR PREDICTING THE WAY OF A SET ASSOCIATIVE CACHE

Intel Corporation, Santa...

1. A method for fetching a cache line of a far taken branch instruction and a cache line of a target of the far taken branch instruction, the method comprising:determining a hit at a first way of an instruction cache for the far taken branch instruction;
determining a target address from an information cache based on the first way;
determining a second way from a shadow cache tag structure based on the target address; and
fetching the far taken branch instruction from the instruction cache based on the first way and the target of the far taken branch instruction from a shadow cache based on the second way.

US Pat. No. 10,248,569

PATTERN BASED PRELOAD ENGINE

Futurewei Technologies, I...

1. A method for a processing unit executing an application, the method comprising:determining, by the processing unit, that the application has reached a specific location and state;
obtaining, by the processing unit, a trigger instruction responsive to determining the application has reached the specific location and state, wherein the trigger instruction includes an index into a preload engine offset table and a base address, wherein the preload engine offset table includes a plurality of distinct offsets associated with the base address;
accessing a memory by a preload engine coupled to the processing unit to obtain the preload engine offset table based on the index and base address to determine the plurality of distinct offsets relative to the base address, the plurality of distinct offsets being specific to the application location and state; and
prefetching data by the preload engine into a cache memory, for use by the processing unit executing the application, the data prefetched into the cache memory using addresses generated using the base address and each of the plurality of distinct offsets.

US Pat. No. 10,248,568

EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR

Intel Corporation, Armon...

1. A method comprising:writing input data to a first cache line of a cache shared by a processor and an accelerator, wherein the input data is ready to be operated on by the accelerator; and
writing instructions to one or more cache lines, the one or more cache lines designated as a queue for the accelerator, wherein the instructions indicate a first operation to be performed by the accelerator and a virtual pointer to the input data in the cache.

US Pat. No. 10,248,566

SYSTEM AND METHOD FOR CACHING VIRTUAL MACHINE DATA

Western Digital Technolog...

14. A method for caching data from a plurality of virtual machines, the method comprising:identifying, using a cache management component, a first virtual machine, of the plurality of virtual machines, which is operating;
allocating a portion of a cache storage to the first virtual machine;
performing caching of data to handle an input/output (I/O) request of the first virtual machine, wherein data written to the cache storage is written to a top of the cache storage and existing data in the cache storage is pushed down the cache storage;
identifying a second virtual machine, of the plurality of virtual machines, which is not operating based at least in part on a determination that second virtual machine data I/O does not appear in a register of the cache storage;
determining whether a number of virtual machines that use the cache storage exceeds a threshold number of virtual machines; and
in response to determining that the number of virtual machines that use the cache storage exceeds the threshold number of virtual machines:
moving data cached by the second virtual machine in the cache storage to a bottom of the cache storage; and
invalidating a portion of the cache storage associated with the second virtual machine by writing over data at the bottom of the cache storage as data is added to the top of the cache storage.

US Pat. No. 10,248,565

HYBRID INPUT/OUTPUT COHERENT WRITE

QUALCOMM Incorporated, S...

1. A method of implementing a hybrid input/output (I/O) coherent write request on a computing device, comprising:receiving an I/O coherent write request;
generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request by duplicating the I/O coherent write request;
sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory; and
sending the second hybrid I/O coherent write request duplicated from the I/O coherent write request to a coherency domain without sending the I/O coherent write data of the I/O coherent write request to the coherency domain.

US Pat. No. 10,248,564

CONTENDED LOCK REQUEST ELISION SCHEME

Advanced Micro Devices, I...

1. A method comprising:storing a plurality of data blocks at a home node of a plurality of nodes;
receiving a request at the home node from a first node, the request being a request for access to a given data block of the plurality of data blocks;
maintaining a count of a number of read requests at the home node for the given data block;
in response to determining both the given data block is currently stored at a second node and the count has exceeded a threshold, the home node:
requesting a copy of the given data block from the second node;
storing the copy of the given data block at the home node responsive to receiving the given data block from the second node; and
forwarding the copy of the given data block from the home node to the first node.

US Pat. No. 10,248,563

EFFICIENT CACHE MEMORY HAVING AN EXPIRATION TIMER

International Business Ma...

1. A method, comprising:selectively invalidating data stored in at least one cache line of a cache memory of a processor in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed, the predetermined amount of time being shorter than an average round-trip time for the processor to process a plurality of blocks of data stored sequentially to a ring buffer.

US Pat. No. 10,248,562

COST-BASED GARBAGE COLLECTION SCHEDULING IN A DISTRIBUTED STORAGE ENVIRONMENT

Microsoft Technology Lice...

1. A computer system comprising:one or more processors; and
one or more computer-readable storage media having stored thereon computer-executable instructions that are executable by the one or more processors to cause the computer system to schedule garbage collection in a distributed environment that includes a plurality of partitions that point to a plurality of data blocks that store data objects, the garbage collection scheduling being based on a cost to reclaim one or more of the data blocks for further use, the computer-executable instructions including instructions that are executable to cause the computer system to perform at least the following:
determining a reclaim cost for one or more data blocks of one or more of the plurality of partitions during a garbage collection operation;
determining a byte constant multiplier that is configured to modify the reclaim cost to account for the amount of data objects that may be rewritten during the garbage collection operation;
accessing one or more of a baseline reclaim budget and a baseline rewrite budget, the baseline reclaim budget specifying an acceptable amount of data blocks that should be reclaimed by the garbage collection operation and the baseline rewrite budget specifying an upper limit on the amount of data objects that may be rewritten during the garbage collection operation;
iteratively varying one or more of the baseline reclaim budget, the baseline rewrite budget, and byte constant multiplier to determine an effect on the reclaim cost; and
generating a schedule for garbage collection, the schedule including those data blocks that at least partially minimize the reclaim cost based on the iterative varying.

US Pat. No. 10,248,561

STATELESS DETECTION OF OUT-OF-MEMORY EVENTS IN VIRTUAL MACHINES

ORACLE INTERNATIONAL CORP...

1. A method of modifying memory allocations of virtual machines executing within a computing system, comprising:executing one or more virtual machines, including a first virtual machine, on a computing system, wherein each said virtual machine is allocated an amount of heap memory from the computer system,
performing a plurality of garbage collection processes on the computing system during execution of the first virtual machine on the computer system;
determining, by the computing system, using one or more processors of the computing system, one or more execution metrics for each of the plurality of garbage collection processes performed, the execution metrics including an execution duration for each of the plurality of garbage collection process,
using a sequential-analysis technique to analyze, by the computing system, the execution metrics for each of the plurality of garbage collection processes for stateless detection of a memory usage trend for the first virtual machine, based on the execution durations for the plurality of garbage collection processes; and
in response to detecting an upward memory usage trend for the first virtual machine based on the analysis of the execution durations for the plurality of garbage collection processes, modifying, by the computing system, the amount of heap memory allocated to the first virtual machine.

US Pat. No. 10,248,560

STORAGE DEVICE THAT RESTORES DATA LOST DURING A SUBSEQUENT DATA WRITE

Toshiba Memory Corporatio...

1. A storage device connectable to a host device, the storage device comprising:a plurality of nonvolatile memories each including first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line; and
a controller configured to:
maintain parity data in a memory area of the host device for data that has been written to the first memory cells,
write data to the second memory cells, and
upon detecting a failure in the writing of data to the second memory cells, restore, using the parity data from the memory area of the host device, the data previously written to the first memory cells.

US Pat. No. 10,248,558

MEMORY LEAKAGE POWER SAVINGS

QUALCOMM Incorporated, S...

1. A system, comprising:a cache memory, wherein a processor accesses the cache memory;
a multiplexer configured to selectively couple a first supply rail or a second supply rail to the cache memory;
a controller configured to instruct the multiplexer to couple the first supply rail to the cache memory if the processor is in a first performance mode, and to instruct the multiplexer to couple the second supply rail to the cache memory if the processor is in a second performance mode; and
a trigger device configured to detect gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, to instruct the controller to switch the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail,
wherein the trigger device is configured to receive a signal indicating whether the second supply rail is being power collapsed, and to refrain from instructing the controller to switch the cache memory from the second supply rail to the first supply rail if the signal indicates that the second supply rail is being power collapsed.

US Pat. No. 10,248,553

TEST METHODOLOGY FOR DETECTION OF UNWANTED CRYPTOGRAPHIC KEY DESTRUCTION

International Business Ma...

1. A computer program product (CPP) comprising: a computer readable storage medium; andcomputer code stored on the computer readable storage medium, with the computer code including instructions and data for causing a processor(s) set to perform at least the following operations:
running, for a first time, a test program on a computer system, with the test program using instructions and data stored in a test program space of the computer system, with the running, for the first time, of the test program including:
receiving cipher key derivation data from a system space of the computer system,
deriving and storing in the test program space a set of subsidiary cipher key(s) based upon the cipher key derivation data, and
performing a set of data encrypted data communication(s) between the test program space and the system space co-operatively using the set of subsidiary cipher key(s) stored in the test program space and a set of master cipher key(s) stored in the system space,
during or subsequent to the running for the first time of the test program, performing an operation that erroneously destroys the set of master cipher key(s) stored in the system space to yield a set of corrupted master cipher key(s) in the system space,
as the running for the first time is ending, copying the set of subsidiary cipher key(s) from the test program space to a persistent storage that is not part of the test program space, and
subsequent to the performance of the operation that erroneously destroys the set of master key(s) stored in the system space, running, for a second time, the test program on the computer system, with the running, for the second time, of the test program including:
receiving, in the test program space, the set of subsidiary cipher key(s) previously derived and copied to the persistent storage during the running, for the first time, of the test program,
encountering an error when attempting to perform a set of data encrypted data communication(s) between the test program space and the system space co-operatively using the set of subsidiary cipher key(s) received in the test program space and the set of corrupted master cipher key(s) stored in the system space, and
logging log data indicative of the error.

US Pat. No. 10,248,552

GENERATING TEST SCRIPTS FOR TESTING A NETWORK-BASED APPLICATION

International Business Ma...

1. A computer system for testing an application, comprising: at least one processor, a memory coupled to the at least one processor, computer program instructions stored in the memory and executed by the at least one processor, to perform steps of:obtaining first temporary test scripts for testing at least one test case of a first version of the application, the first temporary test scripts being recorded with first mark data used for testing the first version of the application;
obtaining a first correspondence between the first mark data and test data;
substituting the test data for the first mark data in the first temporary test scripts based on the first correspondence to obtain first test scripts for testing the at least one test case of the first version of the application;
in response to the first mark data being included in a second mark data, wherein the second mark data is used for testing a second version of the application, obtaining second temporary test scripts for testing at least one test case of the second version of the application, the second temporary test scripts being recorded with the second mark data;
obtaining a stored first correspondence;
obtaining a second correspondence between increased test data and increased data in the second mark data comparing with the first mark data; and
substituting the test data and the increased test data for the second mark data in the second temporary test scripts based on both the first and second correspondences to obtain second test scripts for testing the at least one test case of the second version of the application.

US Pat. No. 10,248,549

SYSTEMS AND METHODS FOR DETECTION OF UNTESTED CODE EXECUTION

Citrix Systems, Inc., Fo...

1. A method for improving the quality of a first software product, comprising:performing operations by a computing device to run the first software product generated by compiling source code modified based on code coverage data gathered during testing of the first software product prior to release on a market, the code coverage data identifying at least one first portion of the source code which was executed at least once during the testing and identifying at least one second portion of the source code which was not executed during the testing;
automatically detecting when an execution of the second portion is triggered while the first software product is being used by an end user subsequent to being released on the market;
automatically performing a notification action in response to said detecting; and
mitigating a risk of defect in the first software product based on the notification action through an end user data-driven triggering of additional testing for untested portions of the source code subsequent to when the first software product has been released.

US Pat. No. 10,248,548

CODE COVERAGE INFORMATION

ENTIT SOFTWARE LLC, Sunn...

1. A method comprising:obtaining code coverage information related to lines of code;
generating a two-way mapping based on the code coverage information, the two-way mapping comprising a first mapping that maps a particular test in the plurality of tests to at least one line in the lines of code that is covered by the particular test and a second mapping that maps a particular line of code in the lines of code to at least one test in the plurality of tests that covers the particular line of code;
receiving, from a client computing device, an indication that a new line has been added to the lines of code in an integrated development environment (IDE) running on the client computing device;
causing the plurality of tests to be executed; and
obtaining the code coverage information related to the new line, wherein the code coverage information related to the new line comprises at least one of: a first indication that the new line passed all of the tests covering the new line, a second indication that the new line failed at least one test covering the new line, or a third indication that the new line is not covered by any of the plurality of tests.

US Pat. No. 10,248,547

COVERAGE OF CALL GRAPHS BASED ON PATHS AND SEQUENCES

SAP SE, Walldorf (DE)

1. A non-transitory machine-readable medium storing a program executable by at least one processing unit of a computing device, the program comprising sets of instructions for:collecting a set of call stack data associated with a set of test cases executed on an application;
generating a set of call graphs based on the set of call stack data, each call graph in the set of call graphs comprising a set of nodes representing a set of functions in the application executed in the corresponding test case in the set of test cases;
generating a full call graph based on the set of call graphs, the full call graph comprising a plurality of nodes representing the sets of functions executed by the application during the execution of the set of test cases on the application;
determining a set of switch nodes and a set of edge nodes in the plurality of nodes of the full call graph, wherein each switch node in the set of switch nodes calls two or more other nodes in the full call graph, wherein each edge node in the set of edge nodes does not call any nodes in the full call graph;
determining, for each call graph in the set of call graphs, a set of short paths and a set of short sequences in the call graph, wherein each short path in the set of short paths comprises a path in the call graph that starts at a switch node in the call graph and ends at a first switch node in the call graph along the path, a first edge node in the call graph along the path, or a node in the call graph at an end of the path, wherein each short sequence in the set of short sequences comprises a switch node in the call graph and a set of nodes in the call graph that the switch node calls;
receiving a notification indicating a modification to a function in the sets of functions of the application;
determining a subset of the set of test cases to test the modification to the function based on the sets of short paths and the sets of short sequences in the set of call graphs; and
executing the subset of the set of test cases on a version of the application that includes the modified function.

US Pat. No. 10,248,546

INTELLIGENT DEVICE SELECTION FOR MOBILE APPLICATION TESTING

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method comprising:determining features of a new mobile application to be tested;
comparing, by a processor, the features of the new mobile application to be tested with features of multiple known mobile applications to identify one or more known mobile applications with similar features; and
based at least in part on automated analysis of user reviews of the one or more known mobile applications operating in one or more types of mobile devices, providing, by the processor, one or more risk scores for operation of the new mobile application in the one or more types of mobile devices, wherein providing the one or more risk scores comprises generating a respective risk score for operating the new mobile application in each type of mobile device of the one or more types of mobile devices, the respective risk scores being determined based, at least in part, on automated analysis of user reviews of the one or more known mobile applications with similar features operating on that type of mobile device, and wherein the one or more risk scores are each determined based on one or more factors selected from a group consisting of: a degree of feature similarity between the new mobile application and the known mobile application with similar features, a number of defect instances reported for the known mobile application on the type of mobile device, a sentiment of user reviews of the known mobile device application on the type of mobile device, and a number of like or dislike reviews of the known mobile application on the type of mobile device.

US Pat. No. 10,248,544

SYSTEM AND METHOD FOR AUTOMATIC ROOT CAUSE DETECTION

CA, Inc., Islandia, NY (...

1. A method, comprising:obtaining, with one or more processors, a history of performance of an application, wherein:
the history of performance comprises a plurality of historical transaction records corresponding to a plurality of transactions serviced by the application responsive to respective requests received at an entry point of the application,
respective historical transaction records identify a plurality of components of the application accessed to service a respective transaction among the plurality of transactions,
respective historical transaction records include a plurality of attributes of operation of respective components among the plurality of components of the application accessed to service the respective transaction, and
the attributes include, for at least some components in at least some transactions, a respective response time of the respective component in the respective transaction;
after obtaining the history of performance, receiving, with one or more processors, an error of the application occurring in a first component of the application during an executed transaction that is servicing a request;
obtaining, with one or more processors, an executed transaction record of the executed transaction associated with the error, the executed transaction record identifying a plurality of components of the application accessed to service the executed transaction;
selecting, with one or more processors, a subset of the historical transaction records at least in part by comparing at least part of the historical transaction records to at least part of the executed transaction record and determining that at least some request parameters and that at least some application components match between the executed transaction record and the subset of historical transaction records, the subset of the historical transaction records including a plurality of historical transaction records;
determining, with one or more processors, that a value of an attribute of the executed transaction record is inconsistent with values of the attribute in the selected subset of historical transaction records, the attribute being associated with a second component of the application, wherein determining that the value of the attribute of the executed transaction record is inconsistent with values of the attribute in the selected subset of historical transaction records comprises comparing a response time of the second component during the executed transaction associated with the error to a threshold response time, the response time of the second component being a portion attributable to the second component of a response time of the request serviced by the executed transaction associated with the error; and
in response to the determination, designating, with one or more processors, in memory, the second component as a potentially associated with a root cause of the error.

US Pat. No. 10,248,543

SOFTWARE FUNCTIONAL TESTING

1. A method comprising:presenting to a user through a client device a graphical representation of an output of executing software;
capturing at least one image of physical movement made by the user interacting with the graphical representation of the output of the executing software;
applying computer vision to the at least one image to identify graphical elements in the graphical representation of the output of the executing software;
applying computer vision to the at least one image to identify user interactions with the graphical elements in the graphical representation of the output of the executing software based on the graphical elements identified in the graphical representation of the output of the executing software;
receiving user input indicating functions associated with elements of the software including the graphical elements for use in executing the software;
generating a script package based on the user interactions with the graphical elements in the graphical representation of the output of the executing software and the user input indicating the functions associated with the elements of the software for use in executing the software, the script package including script capable of being executed in functionally testing the software;
functionally testing the software on at least one virtualized testbed machine using the script package;
generating output of functionally testing the software by functionally testing the software using the script package;
performing functional testing analysis of the software by applying computer vision to a graphical representation of the output of functionally testing the software to determine at least one of a degree to which the graphical representation of the output of functionally testing the software changes compared to an expected output of functionally testing the software and a frequency at which the graphical representation of the output of functionally testing the software changes compared to a graphical representation of the expected output of functionally testing the software, said at least one of the degree to which the output of functionally testing the software changes and the frequency at which the graphical representation of the output of functionally testing the software changes used to generate functional testing analytics data included as part of functional testing results.

US Pat. No. 10,248,542

SCREENSHOT VALIDATION TESTING

International Business Ma...

1. A method comprising:receiving, by one or more computer processors, parameters of a test scenario, wherein the parameters include a first screenshot of an application interface that is a webpage, and one or more page objects within the first screenshot that are models of areas within the webpage for verification testing of one or more features of the webpage;
generating, by the one or more computer processors, a second screenshot of an updated version of the application interface that includes changes to a website environment, a structure, a design, and a format of the application interface for the application interface;
identifying, by the one or more computer processors, one or more page objects within the second screenshot that are within a defined scope of each of the one or more page objects within the first screenshot in the parameters of the test scenario, wherein the scope defines outer boundaries of a section of the webpage associated with the one or more page objects within the first screenshot;
generating a partial screenshot containing only the identified one or more page objects within the second screenshot that are within the defined scope;
comparing, by the one or more computer processors, a section of the partial screenshot that includes the identified one or more page objects of the second screenshot to a section of the first screenshot that includes one or more page objects associated with the first screenshot that correspond to the one or more page objects included in the section of the second screenshot, wherein portions of the first screenshot not included in the section of the first screenshot and portions of the second screenshot not included in the section of the second screenshot are excluded from the comparison of the section of the second screenshot to the section of the first screenshot;
determining, by the one or more computer processors, whether the section of the second screenshot matches, within a predetermined tolerance level, the section of the first screenshot and
providing, by the one or more computer processors, a report based on the determination and comparison, wherein the report includes results of the verification testing of the one or more features of the webpage and the portions that are excluded from the comparison and outside of the defined scope are excluded in the report, the results including a difference between the compared sections be and the redetermined tolerance level.

US Pat. No. 10,248,536

METHOD FOR STATIC AND DYNAMIC CONFIGURATION VERIFICATION

International Business Ma...

1. A method for improving functionality and performance of a client terminal by verifying correctness of application configuration of an application, comprising:for each of baseline source code and changed source code of an application for a client terminal, analyzing a graph representation of an execution flow of a plurality of application functionalities performed by execution of a respective said source code;
identifying by said analysis a plurality of baseline functional dependencies between source code segments of said baseline source code, wherein each of said baseline functional dependencies defines a dependency between one of said baseline source code segments and another one of said baseline source code segments;
defining a plurality of baseline dependency pairs, each defined for another one of said plurality of identified baseline functional dependences, wherein each of said plurality of baseline dependency pairs comprises two code segments of said baseline source code, wherein a second of said two code segments depends on a first of said two code segments;
identifying by said analysis a plurality of functional dependencies between source code segments of said changed source code, wherein each of said functional dependencies defines a dependency between one of said changed source code segments and another one of said changed source code segments, wherein each of said plurality of functional dependencies and said plurality of baseline functional dependencies is at least one of data dependency and control dependency;
defining a plurality of changed source code dependency pairs, each defined for another one of said plurality of identified changed source code functional dependencies, wherein each of said plurality of changed source code dependency pairs comprises two code segments of said changed source code, wherein a second of said two code segments depends on a first of said two code segments;
comparing functional dependencies of the baseline dependency pairs with the changed source code dependency pairs and identifying one or more matches when a baseline dependency pair has a corresponding changed source code dependency pair in the baseline source code;
identifying a configuration discrepancy according to the comparison when a dependency pair does not have a corresponding dependency pair match or identifying one or more dependency pairs in the changed source code which are not permitted by the application configuration;
generating at least one of a system of a system interrupt or an error message as a notification, when said configuration discrepancy is identified.

US Pat. No. 10,248,535

ON-DEMAND AUTOMATED LOCALE SEED GENERATION AND VERIFICATION

INTERNATIONAL BUSINESS MA...

1. A method for locale verification, comprising:receiving a user's locale information to fill a locale data template at a user device;
converting the user's filled locale data template to a normalized format to prevent data loss across platforms;
converting a set of expected locale responses into the normalized format based on the locale data template;
comparing the user's normalized filled locale data template to the notinalized set of expected locale responses to identify one or more mismatches between the received locale data template and the set of expected locale responses, pertaining to at least one locale-related attribute of the system under test, using a processor; and
automatically altering the at least one locale-related attribute of the system under test to correct the one or more mismatches.

US Pat. No. 10,248,533

DETECTION OF ANOMALOUS COMPUTER BEHAVIOR

State Farm Mutual Automob...

1. A computer-implemented method for determining features of a dataset that are indicative of anomalous behavior of one or more computers in a large group of computers, the computer-implemented method comprising, via one or more processors and/or transceivers:receiving log files including a plurality of entries of data regarding connections between a plurality of computers belonging to an organization and a plurality of websites outside the organization, each entry being associated with the actions of one computer;
determining a plurality of embedded features that are included in each entry;
determining a plurality of derived features that are extracted from the embedded features;
creating a plurality of features including the embedded features and the derived features;
executing a time series decomposition algorithm on a portion of the features of the data to generate a first list of features;
implementing a plurality of traffic dispersion graphs to generate a second list of features; and
implementing an autoencoder and a random forest regressor to generate a third list of features.

US Pat. No. 10,248,531

SYSTEMS AND METHODS FOR LOCALLY STREAMING APPLICATIONS IN A COMPUTING SYSTEM

United Services Automobil...

1. A system, comprising:a storage component configured to store data; a processor configured to:
store a first set of data generated during a first period of time in the storage component;
generate a first partition in the storage component after the first period of time;
store a second set of data generated during a second period of time after the first period of time into a second partition of the storage component;
receive a request to return to a state associated with the first period of time; and
swap the second partition with a third partition of the storage component in response to the request, wherein the second partition is temporarily disabled, wherein the third partition comprises a hidden portion of the storage component and wherein the hidden portion of the storage components configured to be invisible to a user of a computing system.

US Pat. No. 10,248,530

METHODS AND SYSTEMS FOR DETERMINING CAPACITY

Comcast Cable Communicati...

1. A method comprising:determining, by a computing device, a first set of capacity test results by performing a first set of capacity tests of a computing system;
determining a second set of capacity test results by performing a second set of capacity tests of the computing system, wherein the second set of capacity tests is different from the first set of capacity tests;
determining a third set of capacity test results by performing a third set of capacity tests of the computing system, wherein the third set of capacity tests is different from the first set of capacity tests and the second set of capacity tests;
calibrating one or more of the first set of capacity tests, the second set of capacity tests, or the third set of capacity tests based on the first set of capacity test results, the second set of capacity test results, or the third set of capacity test results;
performing a fourth set of capacity tests using one or more of the first set of capacity test results, the second set of capacity test results, or the third set of capacity test results associated with the calibrated one or more of the first set of capacity tests, the second set of capacity tests, or the third set of capacity tests; and
determining a computing system capacity based on a fourth set of capacity test results derived from the fourth set of capacity tests, the first set of capacity test results, the second set of capacity test results, and the third set of capacity test results.

US Pat. No. 10,248,529

COMPUTING RESIDUAL RESOURCE CONSUMPTION FOR TOP-K DATA REPORTS

International Business Ma...

1. A system for monitoring computer system operation, the system comprising a processor, memory accessible by the processor, and computer program instructions stored in the memory and executable by the processor to perform:monitoring and measuring metrics of system resource consumption of a plurality of entities in at least one computer system to generate resource consumption data;
generating a report of the system resource consumption data for the plurality of entities for each of a plurality of time periods;
identifying a number, k, of the plurality of entities as top-k consumers of computer system resources for each of the plurality of time periods;
capturing, long term resource consumption data of an entity of the plurality of entities other than the top-k entities, said long term resource consumption data of the entity being stored as residual resource consumption data;
determining, based on said residual resource consumption data for each entity of the plurality of entities other than the top-k entities, whether the resources used by the entity accumulated over the plurality of time periods is greater than the resources used by any top-k entity during any of the plurality of time periods;
identifying at least one residual entity of the plurality of entities as an entity whose accumulated resource consumption over said plurality of time periods is greater than the resources used by any of the top-k entities based on residual resource consumption data of the entity for the plurality of time periods; and
resampling the reports of the system resource consumption data corresponding to the top-k entities and to the identified at least one residual entity to generate at least one report covering a time period including the plurality of time periods, said generated at least one report reflecting a state of said at least one computing system with increased accuracy.

US Pat. No. 10,248,526

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:a flash memory, having a plurality of blocks, and the blocks comprise a current block and temporary block; and
a controller, writing a first data sector corresponding to a first logical address into the current block, determining whether the temporary block has a second data sector that also corresponds to the first logical address, wherein when the temporary block already has a second data sector corresponding to the first logical address, the controller writes a first temporary-block table into the temporary block.

US Pat. No. 10,248,525

INTELLIGENT MEDICAL IMPLANT AND MONITORING SYSTEM

Bayer Oy, Turku (FI)

1. An intelligent medical implant and monitoring system comprising:an implant with a communication device;
an inserter for inserting the implant;
a reader that operates to broadcast a signal specific to the communication device causing the communication device to respond with a unique identifier; and
an external database for storing and providing access to information keyed to the unique identifier from the communication device;
wherein the inserter comprises circuitry for communicating with the communication device and storing the unique identifier in the communication device during an insertion process.

US Pat. No. 10,248,523

SYSTEMS AND METHODS FOR PROVISIONING DISTRIBUTED DATASETS

Veritas Technologies LLC,...

1. A computer-implemented method for provisioning distributed datasets, at least a portion of the method being performed by a computing device comprising at least one processor, the method comprising:identifying a dataset, wherein a production cluster stores a primary instance of the dataset by distributing data objects within the dataset across the production cluster according to a first partitioning scheme that assigns each data object within the dataset to a corresponding node within the production cluster;
receiving a request for a testing instance of the dataset on a testing cluster, wherein the testing cluster is to distribute storage of data objects across the testing cluster according to a second partitioning scheme that maps data objects to corresponding nodes within the testing cluster;
locating, in response to the request, a copied instance of the dataset that is derived from the primary instance of the dataset and that is stored outside both the production cluster and the testing cluster;
partitioning the copied instance of the dataset according to the second partitioning scheme, thereby generating a plurality of partitions of data objects that map to corresponding nodes within the testing cluster; and
providing the testing instance of the dataset in response to the request by providing storage access for each node within the testing cluster to a corresponding partition within the plurality of partitions without copying the copied instance of the dataset to the testing cluster.

US Pat. No. 10,248,522

SYSTEM AND METHOD FOR AUTOMATIC FEEDBACK/MONITORING OF AVIONICS ROBUSTNESS/CYBERSECURITY TESTING

Rockwell Collins, Inc., ...

1. A system for automatic feedback and monitoring of avionics robustness and cybersecurity testing, comprising:at least one fuzzer configured to be coupled to an avionics system under test (SUT) and configured to:
request at least one initial state of the SUT from a monitor module coupled to the fuzzer;
generate a plurality of test cases associated with the SUT; and
transmit the plurality of test cases to the SUT;
the at least one monitor module comprising an SNMP monitor, a serial monitor, a SYSLOG monitor, and a TCP monitor, configured to be coupled to the SUT via a serial connection, a SYSLOG server, and a TCP port, and to:
request a management information base from a managed device in data communication with the SUT;
determine at least one subsequent state of the SUT by at least one of 1) sending a system message to the SUT, the system message corresponding to a system response; and 2) detecting a regular activity of the SUT;
determine at least one error of the SUT by comparing the subsequent state and the initial state, the determined error corresponding to at least one first test case of the plurality of test cases; and
generate at least one log including one or more of the determined error, the associated initial state, the associated subsequent state, and the at least one first test case.

US Pat. No. 10,248,521

RUN TIME ECC ERROR INJECTION SCHEME FOR HARDWARE VALIDATION

MICROCHIP TECHNOLOGY INCO...

1. An integrated peripheral device having a runtime self-test capabilities, comprisinga read path configured to internally forward read data;
a read fault injection logic configured to, under program control, inject at least one faulty bit into the forwarded read data; and
an error indication logic configured to, under program control, provide an error indication to a processor when a fault injection occurs;
wherein the read fault injection logic is further configured to inject the at least one faulty bit into the forwarded read data when a user has enabled the injection and when a read address matches a user-specified memory location.

US Pat. No. 10,248,518

INFORMATION PROCESSING DEVICE AND METHOD OF STORING FAILURE INFORMATION

FUJITSU LIMITED, Kawasak...

1. An information processing device, comprising:a memory; and
a processor coupled to the memory and the processor configured to
perform a diagnosis of hardware of the information processing device,
generate plural pieces of failure information that each indicate a failure detected by the diagnosis, the plural pieces of failure information being classified into groups corresponding to respective different importance levels,
store the plural pieces of failure information in consecutive storage areas of the memory, the consecutive storage areas being divided into storage sections corresponding to the respective groups in order of importance level, and
store first piece of failure information in a head of a second storage section among the storage sections in absence of free areas in first storage section among the storage sections, the first piece of failure information being included in a first group among the groups, the first group corresponding to a first importance level among the importance levels, the first storage section being secured for the first group, the second storage section being secured for a second group among the groups, the second group corresponding to a second importance level among the importance levels, the second importance level being lower than the first importance level by one level, the first storage section and the head of the second storage section being consecutive.

US Pat. No. 10,248,517

COMPUTER-IMPLEMENTED METHOD, INFORMATION PROCESSING DEVICE, AND RECORDING MEDIUM

FUJITSU LIMITED, Kawasak...

1. A computer-implemented method for detecting a fault occurrence within a system including a plurality of information processing devices, the method comprising:each time when a failure of the system occurred, acquiring first configuration information from a failed processing device of the plurality of processing devices;
generating learning data in which a setting item, a setting value that includes a setting error and a fault type are associated with each other;
storing the generated learning data;
determining whether each of fault types included in the learning data depends on a software configuration;
extracting first software configuration pattern indicating a combination of setting files in which settings related to software are described, from the first configuration information, based on a result of the determining whether each of the fault types included in the learning data depends on the software configuration;
storing the extracted first software configuration pattern;
when monitoring the system, acquiring second configuration information from a target processing device of the plurality of processing devices;
extracting second software configuration pattern indicating a combination of setting files in which settings related to software are described, from the acquired second configuration information;
determining whether to output an indication of the fault occurrence within the target processing device based on a result obtained by comparing the second software configuration pattern with the first software configuration pattern; and
notifying the indication of the fault occurrence when determined to output the indication of the fault occurrence.

US Pat. No. 10,248,515

IDENTIFYING A FAILING GROUP OF MEMORY CELLS IN A MULTI-PLANE STORAGE OPERATION

Apple Inc., Cupertino, C...

1. An apparatus, comprising:an interface, configured to communicate with a memory comprising multiple memory cells arranged in multiple planes, wherein each plane comprises one or more blocks of the memory cells; and
storage circuitry, which is configured to: apply a multi-plane storage operation to multiple blocks simultaneously across the respective planes;
apply a single-plane storage operation, in response to detecting that the multi-plane storage operation has failed, to one or more of the blocks that were accessed in the multi-plane storage operation, including a given block, and if the single-plane operation applied to the given block fails, identify the given block as a bad block; and
for subsequent write operations, retire the given block that was accessed in the multi-plane operation and was identified as a bad block, but permit storage of data in the blocks that were accessed in the multi-plane operation but were not identified as bad blocks.

US Pat. No. 10,248,512

INTELLIGENT DATA PROTECTION SYSTEM SCHEDULING OF OPEN FILES

International Business Ma...

1. A method comprising:collecting and recording, by one or more processors, historical information pertaining to one or more backup jobs for a plurality of backup clients with a common backup window, wherein the historical information includes a temporal pattern of a number of files open during previous backup jobs and information pertaining to subsequent backup jobs initiated by an administrator after the completion of the previous backup jobs;
for each of the plurality of backup clients:
estimating, by one or more processors, a number of files to be open during the common backup window based, at least in part, on the historical information,
determining, by one or more processors, a number indicating how many subsequent backup jobs were initiated by the administrator after the completion of scheduled backup jobs of the files estimated to be open during the common backup window,
inferring, by one or more processors, an impact of skipping a backup of the files estimated to be open during the common backup window, where the impact is inferred from the historical information according to one or more predetermined criteria, wherein the one or more predetermined criteria include the determined number indicating how many subsequent backup jobs were initiated by the administrator after the completion of scheduled backup jobs of the files estimated to be open during the common backup window, and
combining, by one or more processors according to a predetermined cost function, the estimated number of files to be open during the common backup window and the inferred impact of skipping the backup of the estimated number of files to be open during the common backup window; and
scheduling, by one or more processors, an order of the one or more backup jobs among the plurality of clients during the common backup window to reduce an overall impact of skipping backups of files estimated to be open during the common backup window, based on the combining according to the predetermined cost function for each of the plurality of backup clients.

US Pat. No. 10,248,511

STORAGE SYSTEM HAVING MULTIPLE LOCAL AND REMOTE VOLUMES AND MULTIPLE JOURNAL VOLUMES USING DUMMY JOURNALS FOR SEQUENCE CONTROL

Hitachi, Ltd., Tokyo (JP...

1. A storage system comprising a primary storage system equipped with a primary storage subsystem having a primary volume and a first journal volume and a secondary storage subsystem having a local volume in which replica of data stored in the primary volume is stored and a second journal volume, and a secondary storage system equipped with a remote storage subsystem having a remote volume in which replica of the data stored in the primary volume is stored and a third journal volume, whereinin a state where the primary storage subsystem stores a write data from a host to the primary volume, the primary storage subsystem determines a sequence number which is a serial number for specifying a write order of the write data, creates a journal including a replica of the write data and the determined sequence number, stores the created journal in the first journal volume, and transmits the created journal to the remote storage subsystem,
in a state where the secondary storage subsystem receives the sequence number included in the journal stored in the first journal volume from the primary storage subsystem, the secondary storage subsystem stores the write data to the local volume, creates the journal including the replica of the write data and the sequence number, and stores the journal in the second journal volume,
during normal operation, in a state where the primary storage subsystem stops creating the journal after determining the sequence number, the secondary storage subsystem creates a dummy journal including the determined sequence number and not including the write data, and stores the dummy journal in the second journal volume, and
if a predetermined time has elapsed after the secondary storage subsystem creates a journal including a serial number larger than a second sequence number, without creating a journal including the second sequence number which is a serial number subsequent to a first sequence number,
the secondary storage subsystem creates a dummy journal including the second sequence number, and stores the dummy journal in the second journal volume.

US Pat. No. 10,248,510

GUARDRAILS FOR COPY DATA STORAGE

Actifio, Inc., Waltham, ...

1. A computerized method of preventing a user from configuring a service level agreement from creating a data management schedule that creates a set of data backups that exceeds data resource limits available for storing the set of data backups, the method being executed by a processor in communication with memory storing instructions configured to cause the processor to:receive first data indicative of a schedule to perform a backup of at least one application;
determine a first amount of pool resources associated with the backup of each of the at least one application according to the received schedule, wherein determining the first amount of pool resources comprises:
calculating a number of copies of an application associated with the received schedule,
determining a change rate parameter comprising at least one of:
an application specific change rate associated with stored historical backup data corresponding to each of the at least one application,
a system-wide change rate corresponding to change rates associated with stored historical backup data associated with applications similar to each of the at least one application, and
a generic application change rate, and
multiplying the change rate parameter for each the at least one application with a size of the application, and with a number of copies of the application associated with each of the at least one application,
add the first amount of pool resources for each of the at least one application to form an aggregate amount of pool resources;
determine a first amount of data volumes associated with the backup of each of the at least one application according to the received schedule, wherein determining the first amount of data volumes comprises:
determining a second amount of data volumes associated with each copy of the at least one application; and
multiplying the second amount of data volumes with the number of copies of the application associated with the received schedule;
add the first amount of data volumes for each of the at least one application to form an aggregate amount of data volume resource; and
transmit a resource shortage warning when the aggregate amount of pool resources exceeds an available amount of pool resources or the aggregate amount of data volume resource exceeds an available amount of data volume resource, thereby preventing a user from configuring a service level agreement that exceeds data resource limits.

US Pat. No. 10,248,509

EXECUTING COMPUTER INSTRUCTION INCLUDING ASYNCHRONOUS OPERATION

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method for executing a computer instruction including an asynchronous operation, the method comprising:computing, by a processing element, parameters associated with the asynchronous operation, and transmitting, by the processing element, via a communication interface, a command for executing the asynchronous operation by an external device;
intercepting and storing, by an interface logic controller, the parameters associated with the asynchronous operation into one or more log registers;
assigning, by the processing element, a tag to the asynchronous operation, and mapping, by the interface logic controller, the tag assigned to the asynchronous operation with the log registers that store the parameters associated with the asynchronous operation;
receiving, by the processing element, a response to the asynchronous operation, the response being indicative of whether the asynchronous operation was a success or a failure; and
in response to the asynchronous operation being a success, executing a next instruction by the processing element, and
in response to the asynchronous operation being a failure:
accessing, by the processing element, the parameters associated with the asynchronous operation from the one or more log registers; and
restarting the asynchronous operation using the parameters from the one or more log registers.

US Pat. No. 10,248,507

VALIDATION OF CONDITION-SENSITIVE MESSAGES IN DISTRIBUTED ASYNCHRONOUS WORKFLOWS

Amazon Technologies, Inc....

14. A computer-implemented method, comprising:generating an original electronic file, wherein the original electronic file includes at least one attribute related to a condition with respect to the original electronic file;
initially validating, by a validation service, a current validity of the condition;
generating at least one alternative for the electronic file, wherein the at least one alternative for the original electronic file is based upon the condition;
forwarding the original electronic file and the at least one alternative for the original electronic file along a workflow to an electronic file publishing service;
based upon the at least one condition, selecting, by a gatekeeper service, one of (i) the original electronic file or (ii) one of the at least one alternative for the original electronic file;
providing the selected one of the original electronic file or the selected at least one alternative for the original electronic file to the electronic file publishing service; and
publishing the selected one of the original electronic file or the selected at least one alternative for the original electronic file to an entity.

US Pat. No. 10,248,506

STORING DATA AND ASSOCIATED METADATA IN A DISPERSED STORAGE NETWORK

INTERNATIONAL BUSINESS MA...

1. A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method comprises:generating metadata for a data object;
first disperse storage error encoding the metadata to produce a set of metadata slices, wherein the first disperse storage error encoding includes utilizing first dispersal parameters to store metadata, the first dispersal parameters including a decode threshold of 1;
partitioning the data object to produce a plurality of data segments;
first disperse storage error encoding at least a first data segment of the plurality of data segments to produce a set of data slices, wherein the first disperse storage error encoding includes utilizing the first dispersal parameters of the metadata, the first dispersal parameters including a decode threshold of 1;
second disperse storage error encoding additional data segments of the plurality of data segments to produce a plurality of sets of encoded data slices, wherein the additional data segments do not include the at least a first data segment and wherein the second disperse storage error encoding includes utilizing second dispersal parameters, the second dispersal parameters different from the first dispersal parameters and including a decode threshold greater than 1; and
facilitating storage of the set of metadata slices and the plurality of sets of encoded data slices in one or more storage units of the DSN; and
wherein subsequent accessing of the metadata slices reproduces the metadata and the first data segment of the data object, making the first data segment of the data object available for use by the one or more computing devices while continuing to retrieve the additional data segments from the DSN.

US Pat. No. 10,248,504

LIST REQUEST PROCESSING DURING A DISPERSED STORAGE NETWORK CONFIGURATION CHANGE

International Business Ma...

1. A method for processing and proxying a listing request by resources of a dispersed storage network (DSN) during a system configuration change, the method comprises:identifying a set of resources that are affiliated with a range of slice names identified by the listing request;
creating an ordered classification of the set of resources based on the system configuration change;
determining, by a resource of the set of resources, whether the resource is in a last class of the ordered classification;
when the resource is in the last class:
processing the listing request to generate a listing response regarding encoded data slices associated with slice names within a sub-range of slice names of the range of slice names, wherein the sub-range of slices names is affiliated with the resource; and
sending the listing response to another resource in a lower higher class of the ordered classification;
when the resource is not in the last class:
identifying a second resource of the set of resource for proxying of the listing request, wherein the second resource is in a next higher class of the ordered classification;
sending the listing request to the second resource;
receiving, in response to the sending, a cumulated listing response from the second resource; and
processing the listing request to generate the listing response regarding encoded data slices associated with slice names within the sub-range of slice names;
combining the listing response with the cumulated listing response to produce an updated cumulated listing response.

US Pat. No. 10,248,500

APPARATUSES AND METHODS FOR GENERATING PROBABILISTIC INFORMATION WITH CURRENT INTEGRATION SENSING

Micron Technology, Inc., ...

1. A method comprising:sensing, responsive to a trip point selector instructing a current detector, a first set of memory cells from a plurality of memory cells at a first sense threshold;
responsive to sensing the first set of memory cells of the plurality of memory cells, identifying, via a sense latch, the first set of memory cells as having a voltage stored thereon within a first range of voltages;
sensing, responsive to the trip point selector instructing the current detector, a second set of memory cells from the plurality of memory cells at a second sense threshold, wherein the first set of memory cells are undetected by the sensing of the second set of memory cells;
responsive to sensing the second set of memory cells of the plurality of memory cells, identifying, via the sense latch, the second set of memory cells as having a voltage stored thereon within a second range of voltages; and
performing, via a decoder circuit communicatively coupled to the current detector, an error correction operation on the first and second sets of memory cells based, at least in part, on the first and second ranges of voltages.

US Pat. No. 10,248,499

NON-VOLATILE STORAGE SYSTEM USING TWO PASS PROGRAMMING WITH BIT ERROR CONTROL

SANDISK TECHNOLOGIES LLC,...

1. A non-volatile storage apparatus, comprising:a set of non-volatile memory cells; and
one or more control circuits in communication with the non-volatile memory cells, the one or more control circuits are configured to receive data from a host and perform partial programming of all the data to the set of non-volatile memory cells until no more than a first number of programming errors exist and subsequently report to the host that the programming of the data has successfully completed even though the one or more control circuits are configured to continue the programming of the data, the one or more control circuits are configured to continue to perform the programming of the data to the set of non-volatile memory cells until the one or more control circuits determine that no more than a second number of programming errors exist after reporting to the host that the programming of the data has successfully completed, the second number is lower than the first number.

US Pat. No. 10,248,498

CYCLIC REDUNDANCY CHECK CALCULATION FOR MULTIPLE BLOCKS OF A MESSAGE

Futurewei Technologies, I...

1. A method for performing a cyclic redundancy check (CRC), comprising:dividing data into a plurality of blocks, each of the plurality of blocks having a fixed size equal to a degree of a generator polynomial;
for each block in which at least one bit has been modified, applying the XOR operation to the block for which the at least one bit has been modified and a corresponding original block of the data to generate an XOR value;
independently performing a CRC computation for each of the plurality of blocks; and
combining an output of the CRC computation for each of the plurality of blocks by application of an exclusive or (XOR) operation.

US Pat. No. 10,248,497

ERROR DETECTION AND CORRECTION UTILIZING LOCALLY STORED PARITY INFORMATION

Advanced Micro Devices, I...

1. A method comprising:implementing a memory external to a processor, the memory comprising multiple banks of data, each data bank comprising a plurality of data blocks stored at locations in the memory, each data block of the plurality of data blocks including an associated checksum value for error detection;
storing a plurality of parity blocks for error correction in a cache on the processor, each parity block corresponding to a set of data blocks of the plurality of data blocks;
accessing a first data block and its associated first checksum value from the set of data blocks;
detecting an error in the first data block based on the associated first checksum value;
storing, by the processor, a modified data value to the first data block in the memory;
determining, at the processor, an updated checksum value for the first data block based on the modified data value;
storing the updated checksum value to the memory;
determining, at the processor, an updated parity block for a first set of data blocks that include the first data block based on the modified data value; and
storing the updated parity block to the cache in the processor.

US Pat. No. 10,248,496

ITERATIVE FORWARD ERROR CORRECTION DECODING FOR FM IN-BAND ON-CHANNEL RADIO BROADCASTING SYSTEMS

Ibiquity Digital Corporat...

1. A radio receiver comprising:physical layer circuitry to receive a digital radio broadcast signal;
processing circuitry configured to:
receive a plurality of protocol data units of the digital radio broadcast signal, each protocol data unit having a header including a plurality of control word bits, and a plurality of audio frames or data packets, each including a cyclic redundancy check code;
wherein the processing circuit includes an audio decoder configured to:
decode the protocol data units using an iterative decoding technique that refines bit decoding information passed between an inner error correction code and an outer error correction code over at least one iteration of the decoding technique, wherein the iterative decoding technique comprises:
for a first decoding iteration, decode the inner error correction code using Viterbi decoding as an inner decoding;
pass decoding information from the inner decoding to the outer error correction code;
use decoded cyclic redundancy check codes to detect audio frames or data packets that contain errors and flag the audio frames or data packets containing errors that require further decoding iterations; and
change the inner decoding for the further decoding iterations of flagged audio frames or flagged data packets to include decoding the inner error correction code using at least one of soft output decoding or a List Viterbi decoding; and
codec circuitry configured to produce an audio signal using audio frames of the protocol data units, or a data signal using data packets of the protocol data units, decoded using the iterative decoding technique.

US Pat. No. 10,248,494

MONITORING, DIAGNOSING, AND REPAIRING A MANAGEMENT DATABASE IN A DATA STORAGE MANAGEMENT SYSTEM

Commvault Systems, Inc., ...

1. A method comprising:monitoring a database, by a storage manager, during active operation of a data storage management system,
wherein the database stores information used by the storage manager to manage the data storage management system, and
wherein the storage manager executes on a computing device comprising one or more processors and non-transitory computer-readable memory;
collecting, by the storage manager, information about the database,
wherein the collected information includes information about the structure of the database and information about the operation of the database;
diagnosing, by the storage manager, a problem associated with the database,
based on analyzing at least some of the collected information about the database; and
correcting the problem associated with the database, at least in part, by causing
at least a threshold number of temporary-database data structures to be instantiated in the database.

US Pat. No. 10,248,493

INVARIANT DETERMINATION

HEWLETT PACKARD ENTERPRIS...

1. A method comprising:determining that an operation is accessing data on a persistent memory;
retrieving a log of the operation;
determining a type of the data being accessed by the persistent memory by the operation;
identifying, from the log, a location in the persistent memory of the data accessed by the operation;
determining contents of the data accessed by the persistent memory by the operation; and
determining whether the contents of the data hold an invariant corresponding to the type of data.

US Pat. No. 10,248,492

METHOD OF EXECUTING PROGRAMS IN AN ELECTRONIC SYSTEM FOR APPLICATIONS WITH FUNCTIONAL SAFETY COMPRISING A PLURALITY OF PROCESSORS, CORRESPONDING SYSTEM AND COMPUTER PROGRAM PRODUCT

Intel Corporation, Santa...

1. A method for executing in a system an application program provided with functional safety, the system including a single-processor or multiprocessors, and an independent control module, said method comprising:performing an operation of decomposition of the program that includes a safety function and is to be executed via said system into a plurality of parallel sub-programs;
assigning execution of each parallel sub-program to a respective processing module of the system, in particular a processor of said multiprocessors or a virtual machine associated to one of said processors; and
carrying out in the system, periodically according to a cycle frequency of the program during normal operation of said system, a framework of safety function diagnostic-self-test operations associated to each of said sub-programs and to the corresponding processing modules on which they are run;
wherein carrying out said self-test operations comprises:
generating respective self-test data corresponding to the self-test operations and carrying out checking operations on said self-test data;
exchanging said self-test data continuously via a protocol of messages with the independent control module; and
carrying out at least part of said checking operations in said independent control module; and
wherein performing an operation of decomposition of the program comprises decomposition of the program into a plurality of parallel sub-programs to obtain a coverage target for each of said self-test operations that is associated to a respective sub-program or processing module in such a way that it respects a given failure-probability target.

US Pat. No. 10,248,490

SYSTEMS AND METHODS FOR PREDICTIVE RELIABILITY MINING

Tata Consultancy Services...

1. A computer implemented method for predictive reliability mining in a population of connected machines, the method comprising:identifying sets of discriminative Diagnostic Trouble Codes (DTCs) from DTCs generated preceding failure, the sets of discriminative DTCs corresponding to associated pre-defined parts of the connected machines;
generating a temporal conditional dependence model based on temporal dependence between failure of the pre-defined parts from past failure data and the identified sets of discriminative DTCs;
segregating the population of connected machines into a first set comprising connected machines in which DTCs are not generated in a given time period and a second set comprising connected machines in which at least one DTC is generated in the given time period; and
predicting future failures based on the generated temporal conditional dependence model and occurrence and non-occurrence of DTCs in the segregated population of connected machines.

US Pat. No. 10,248,489

ELECTRONIC CONTROL UNIT

DENSO CORPORATION, Kariy...

1. An electronic control unit for a vehicle comprising:a first storage unit configured to store a readiness flag indicating that an abnormality diagnosis for an abnormality diagnostic item is complete;
a second storage unit configured to store permanent diagnostic (PDTC) information in a non-volatile manner; and
a microcomputer configured to
communicate with a data scan tool, wherein the scan tool is external to a vehicle network and connects to the vehicle network to communicate with the microcomputer via a data link connector in the vehicle,
determine whether a current all clear request is received from the vehicle data scan tool, which requests clearing of all readiness flags in the first storage unit,
determine whether an additional condition that is different from the current all clear request is fulfilled in which the additional condition includes that the microcomputer receives a read-out request from the scan tool for reading out the permanent diagnostic information stored in the second storage unit, and
clear all readiness flags in the first storage unit in response to determining both that the current all clear request from the scan tool is received and the additional condition including the read-out request from the scan tool for reading out the permanent diagnostic information stored in the second storage unit is fulfilled.

US Pat. No. 10,248,488

FAULT TOLERANCE AND DETECTION BY REPLICATION OF INPUT DATA AND EVALUATING A PACKED DATA EXECUTION RESULT

Intel Corporation, Santa...

1. An apparatus comprising:circuitry to replicate input sources of a scalar arithmetic instruction, wherein an opcode of the scalar arithmetic instruction is to indicate the use of using single instruction, multiple data (SIMD) hardware;
arithmetic logic unit (ALU) circuitry to execute the scalar arithmetic instruction with replicated input sources using the SIMD hardware to produce a packed data result; and
comparison circuitry coupled to the ALU circuitry to evaluate the packed data result and output a singular data result into a destination of the scalar arithmetic instruction, wherein the singular data result is to be stored as a scalar in a least significant data element of a packed data destination register.

US Pat. No. 10,248,487

ERROR RECOVERY FOR MULTI-STAGE SIMULTANEOUSLY RUNNING TASKS

VIOLIN SYSTEMS LLC, San ...

1. A method of managing a server with a stateless connection to a user, the method comprising:providing a server computer having a communications interface with a user computer; and
a memory system,
wherein responding to a request for a service from the user computer comprises:
receiving a user request from the user computer over a communications interface;
executing a task by the server computer to respond to the user request, the task comprising a supervisory task and a number of sub-tasks, each sub-task of the number of sub-tasks having one or more subsidiary tasks; and
configuring each sub-task to report a completion status of each subsidiary task and completion of the sub-task to the supervisory task each time a subsidiary task completes;
wherein a completion status of a subsidiary task is one of success or error, and the supervisory task determines the completion status of each subsidiary task at the completion time of the subsidiary task prior to completion of the sub-task and,
the supervisory task is configured to report an error in completion of the subsidiary task of the sub-task to the user computer if the completion status of the subsidiary task is error, wherein the error terminates or aborts execution and completion of the sub-task and other sequential subsidiary tasks of the sub-task;
wait for another completion status change when a number of completed sub-tasks is less than the number of sub-tasks; and
respond to the user request over the communications interface when a number of successfully completed sub-tasks is equal to the number of sub-tasks.

US Pat. No. 10,248,484

PRIORITIZED ERROR-DETECTION AND SCHEDULING

Intel Corporation, Santa...

1. A method for performing prioritized error detection on an array of memory cells used by an integrated circuit, the method comprising:at error detection circuitry, receiving a prioritized error detection schedule that prescribes more frequent error detection for a first subset of the array of memory cells and less frequent error detection for a second subset of the array of memory cells; and
with the error detection circuitry, performing prioritized error detection on the array of memory cells based on the prioritized error detection schedule;
with the error detection circuitry, performing error detection on the first subset of the array of memory cells with a first frequency based on the prioritized error detection schedule; and
with the error detection circuitry, performing error detection on the second subset of the array of memory cells with a second frequency that is less than the first frequency based on the prioritized error detection schedule.

US Pat. No. 10,248,483

DATA RECOVERY ADVISOR

Oracle International Corp...

1. A computer-implemented method to diagnose and fix problems in a data storage system, the data storage system being implemented at least partially by one or more computers, the method comprising:checking integrity of one or more components of the data storage system;
wherein a data failure is related to corruption of data in a file, the data being read by or written by or read and written by a software program, and at least the corruption of the data is identified by said checking of integrity after an error is encountered by said software program which during normal functioning is unable to process the data due to the corruption of the data;
wherein said checking of integrity comprises checking for at least existence of said file;
identifying a type of repair based at least in part on using, with a map in a memory of a computer that maps failure types to repair types, a type of the data failure related to corruption;
wherein the type of repair identifies a group of alternative repairs each of which can fix the data failure related to corruption, such that each repair in the group is an alternative to another repair in the group, wherein at least one repair in the group uses a backup of the data;
checking feasibility of the group of alternative repairs at least by checking for existence of a backup of the data in a storage device, wherein at least said checking of feasibility is performed automatically, and a plurality of feasible repairs are selected by said checking of feasibility, from among the group of alternative repairs, and said at least one repair is excluded from the plurality of feasible repairs in response to the checking feasibility being unable to find a backup of the data;
consolidating multiple repairs in the plurality of feasible repairs, based on respective impacts of the multiple repairs, into one or more repair plans;
displaying the one or more repair plans;
receiving identification of a specific repair plan selected by user input from among the one or more repair plans displayed;
performing the specific repair plan selected by the user input, to obtain corrected data to fix the corruption in the data;
storing the corrected data in non-volatile storage media of the data storage system; and
said software program at least using the corrected data;
wherein at least said checking of feasibility, said consolidating, said performing and said storing are performed by one or more processors in the one or more computers.

US Pat. No. 10,248,482

INTERLINKING MODULES WITH DIFFERING PROTECTIONS USING STACK INDICATORS

International Business Ma...

1. A computer program product for facilitating linking of modules of a computing environment, said computer program product comprising:a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining whether one module to be executed by a processor of the computing environment supports use of a guard word to protect a stack frame of the computing environment;
determining whether another module to be linked with the one module supports use of the guard word to protect the stack frame;
based on determining that at least one of the one module and the other module fails to support use of the guard word to protect the stack frame, providing an indication that the one module and the other module are linked modules not supporting use of the guard word, wherein the other module includes a verify guard word condition instruction to be used by a the one module to check the guard word of the stack frame based on determining that the one module and the other module support use of the guard word to determine whether the guard word is an expected value;
based on the indication, processing the one module and the other module without use of the guard word to protect the stack frame; and
executing the verify guard word condition instruction by the one module, and failing to return to a return address in the stack frame based on the guard word being an unexpected value.

US Pat. No. 10,248,481

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM AND PROGRAM

KONICA MINOLTA, INC., Ch...

1. An information processing device comprising a hardware processor configured to;acquire a determination result of a state of a user, who has given a transmission job execution instruction, determined based on biological information of the user compared to a predetermined threshold value, the biological information including information related to at least one of a pulse wave, an electrocardiogram, a temperature, a heart rate, or a blood pressure; and
control an execution of the transmission job according to the user state determination result,
wherein when it is determined that the user is in an off-normal state, the user being in the off-normal state when the acquired biological information of the user is equal to or larger than the predetermined threshold value, the hardware processor executes a confirmation request process to request the user to make a confirmation related to the transmission job,
wherein
the hardware processor also executes the confirmation request process when the user is in a normal state, the user being in the normal state when the acquired biological information of the user is smaller than the predetermined threshold value, and
a confirmation of a larger number of confirmation items are requested in the confirmation request process executed in a case where it is determined that the user is in an off-normal state, compared to the number of the confirmation items requested to confirm in a confirmation request process executed in a case where it is determined that the user is in an normal state, and
wherein the hardware processor decides that transmission of transmission target data needs to be executed when the confirmation request process is executed, in a case where a confirmation completion operation indicating an intention that a confirmation related to the transmission job is completed is given by the user.

US Pat. No. 10,248,479

ARITHMETIC PROCESSING DEVICE STORING DIAGNOSTIC RESULTS IN PARALLEL WITH DIAGNOSING, INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF ARITHMETIC PROCESSING DEVICE

FUJITSU LIMITED, Kawasak...

1. An arithmetic processing device comprising:a first memory control unit configured to control an access to a first memory;
a second memory control unit configured to control an access to a second memory; and
a diagnostic control unit configured to sequentially diagnose first parts within the first memory via the first memory control unit and to sequentially store in the second memory, via the second memory control unit, diagnostic results of sequentially diagnosing the first parts, the storing being in parallel with the diagnosing the first parts via the first memory control unit when diagnosing the first parts within the first memory, and
wherein the diagnostic control unit is further configured to sequentially diagnose second parts within the second memory via the second memory control unit and sequentially store in the first memory, via the first memory control unit, diagnostic results of sequentially diagnosing the second parts, the storing being in parallel with the diagnosing the second parts via the second memory control unit when diagnosing the second parts within the second memory.

US Pat. No. 10,248,478

INFORMATION PROCESSING DEVICE AND SPECIFICATION CREATION METHOD

FUJITSU LIMITED, Kawasak...

6. A specification creation method executed by a computer, the method comprising:generating an assumed endpoint, based on class relationship information indicating a relationship between classes of an existing web application, which is API specification information assumed from the relationship;
referring to the class relationship information and extracting a verb and a noun, being basis of an actual endpoint which is API specification information based on an execution result, from an access log to be output when the web application is executed;
generating the actual endpoint by converting the extracted verb into a method name and converting the extracted noun into a path; and
identifying an endpoint included in generated assumed endpoints, as the API specification information of the web application, among generated actual endpoints.

US Pat. No. 10,248,474

APPLICATION EVENT DISTRIBUTION SYSTEM

Microsoft Technology Lice...

1. A method, comprising:receiving a plurality of events generated by one or more of a plurality of primary applications executing on a processing device of a plurality of processing devices, the plurality of primary applications written by one or more primary application developers in a first programming language comprising an application code, the plurality of events occurring in execution of, and generated by, the one or more of the plurality of primary applications, the plurality of events comprising custom events designed by the one or more primary application developers specifically for use in one or more secondary applications based on the one or more primary applications, the one or more secondary applications written by one or more secondary application developers that are different from the primary application developers, wherein the receiving of the plurality of events includes receiving in a prioritization order according to an event priority associated with each of the plurality of events by each of the plurality of processing devices;
defining a set of transformation rules, wherein the transformation rules comprise core transformation rules provided by an administrator of a multiuser service and custom transformation rules provided by the primary application developers;
transforming, by the multiuser service accessible by the one or more secondary application developers, the plurality of events into a plurality of statistics according to the set of transformation rules, the plurality of statistics representing information about the execution of the primary applications across the plurality of processing devices; and
publishing the plurality of statistics and at least a portion of the plurality of events including the custom events to the one or more of the secondary application developers, wherein published ones of the plurality of statistics and at least the portion of the plurality of events are configured for use by the secondary application developers to create the one or more secondary applications to provide information to supplement a user experience with the plurality of primary applications.

US Pat. No. 10,248,473

DISCOVERING OBJECT DEFINITION INFORMATION IN AN INTEGRATED APPLICATION ENVIRONMENT

International Business Ma...

1. A method of discovering object definition information in an integrated application environment, comprising:providing an object discovery agent (ODA) client;
providing a plurality of ODAs, wherein each ODA is associated with one application and includes:
application programming interfaces (APIs) to communicate with the associated application to discover definition information on objects maintained by the application; and
code to communicate, with the ODA client, information on objects used by the associated application;
communicating, by the ODA client, to each ODA of the ODAs, selection of at least one object used by the application associated with the ODA to which the ODA client is communicating; and
returning to the ODA client, by each ODA of the ODAs to which the ODA client is communicating, definition information for the at least one selected object; and
providing gathered object definition information to an integration server to integrate the objects in an environment including heterogeneous objects from applications associated with the ODAs, wherein the integration server uses the object definition information to transform a source application object with the integration server for which definition information is gathered to a generic object and from the generic object to a target application object.

US Pat. No. 10,248,470

HIERARCHICAL HARDWARE OBJECT MODEL LOCKING

International Business Ma...

1. A method comprising:locking a system mutex of a system target with a read-lock operation, wherein the system target comprises a node group comprising a plurality of nodes, wherein each node of the plurality of nodes comprises a descendant group, and wherein each descendant group comprises a plurality of descendants;
subsequent to locking the system mutex, locking the node group with a first write-lock operation, wherein locking the node group comprises simultaneously locking all of the plurality of nodes of the node group with the first write-lock operation; and
subsequent to locking the node group, sequentially locking the descendant group for each of the plurality of nodes with a second write-lock operation, wherein locking the descendant group of a particular node simultaneously locks all of the descendants of the respective descendant group, and wherein the first write-lock operation is different than the second write-lock operation.

US Pat. No. 10,248,469

SOFTWARE BASED COLLECTION OF PERFORMANCE METRICS FOR ALLOCATION ADJUSTMENT OF VIRTUAL RESOURCES

International Business Ma...

1. A computer program product for collecting and processing performance metrics, the computer program product comprising:one or more computer readable storage devices and program instructions stored on the one or more computer readable storage devices, the stored program instructions comprising:
program instructions to assign an identifier corresponding to a first workload associated with a first virtual machine;
program instructions to record resource consumption data of at least one processor, wherein the at least one processor contains the first virtual machine, at a performance monitoring interrupt;
program instructions to create a relational association of the first workload and the first virtual machine to the resource consumption data of the at least one processor;
program instructions to determine if the first workload is complete;
responsive to determining that the first workload is not complete, program instructions to calculate a difference in recorded resource consumption data between the performance monitoring interrupt and a previous performance monitoring interrupt;
program instructions to assign an identifier corresponding to a second workload associated with the first virtual machine;
program instructions to record resource consumption data of at least one processor, wherein the at least one processor contains the first virtual machine, at a performance monitoring interrupt;
program instructions to aggregate the recorded resource consumption data to provide one or more resource consumption estimates; and
program instructions to notify a resource manager of a workload switch between the second workload and the third workload and data regarding changes in resource consumption of the at least one processor over time.

US Pat. No. 10,248,468

USING HYPERVISOR FOR PCI DEVICE MEMORY MAPPING

International Business Ma...

1. A method to manage peripheral component interconnect (PCI) memory, the method comprising:mapping base address register (BAR) space for PCI devices with entries in a page table;
associating the page table with a physical memory address of PCI memory to generate memory mapped I/O (MMIO);
determining whether an address of the BAR space for PCI devices with entries in the page table is in MMIO;
where the address of the BAR space for PCI devices with entries in the page table is not in the MMIO, invoking a hypervisor to perform read/write operations to obtain address information for entry to the page table, wherein invoking the hypervisor comprises validating by the hypervisor that a PCI device owns the address of the BAR space; and
where the address of the BAR space for PCI devices with entries in the page table is in the MMIO, using a partition to perform read/write operations to obtain the address information for entry to the page table.

US Pat. No. 10,248,467

CODE EXECUTION REQUEST ROUTING

Amazon Technologies, Inc....

1. A system, comprising:one or more processors; and
one or more memories, the one or more memories having stored thereon instructions, which, when executed by the one or more processors, configure the one or more processors to:
maintain a plurality of virtual machine instances on one or more physical computing devices;
in response to a first request to execute a program code, cause the program code to be executed in a container created on one of the plurality of virtual machine instances, the execution of the program code modifying one or more computing resources associated with the container;
determine, based on an amount of information stored by the execution in response to the first request, that the container is not to be shut down for at least a period of time after completion of the execution in response to the first request;
in response to the determination, refrain from shutting down the container prior to receiving a second request to execute the program code; and
in response to the second request, cause the program code to be executed in the container using the one or more computing resources associated with the container.

US Pat. No. 10,248,466

MANAGING WORKLOAD DISTRIBUTION AMONG PROCESSING SYSTEMS BASED ON FIELD PROGRAMMABLE DEVICES

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method for managing workload distribution based on field programmable devices, the method comprising:determining, by a processor, a first workload performance for a first general purpose processor and a first field programmable device for a first processing system, wherein determining the first workload performance is based on a first utilization of the first general purpose processor and a first utilization of the first field programmable device in the first processing system, wherein the first utilization of the first field programmable device is calculated based at least in part on an available capacity over a total capacity, wherein the total capacity is calculated based at least in part on a currently utilized capacity plus the available capacity, wherein the available capacity of the first field programmable device for the first processing system is calculated based at least in part on an amount of additional work that the first field programmable device can process without causing an average number of queued requests to increase over a first threshold;
determining, by the processor, a second workload performance for a second general purpose processor and a second field programmable device for a second processing system;
determining whether the first processing system is likely to outperform the second processing system for execution of a workload; and
responsive to determining that the first processing system is likely to outperform the second processing system for the workload, deploying the workload to the first processing system.

US Pat. No. 10,248,465

CONVERGENT MEDIATION SYSTEM WITH DYNAMIC RESOURCE ALLOCATION

Comptel Corporation, Hel...

1. A convergent mediation system for mediating data records, the convergent mediation system comprising:a common platform comprising hardware defining a processing power for online processing and off-line processing of data corresponding to usage of at least one of a communication network or a data communications platform, the common platform comprising:
a plurality of independent processing nodes forming processing streams, each of the processing streams comprising at least two independent processing nodes in sequence, the independent processing nodes structured to continue operating if another independent node in the processing stream fails; and
a buffer between an upstream and a downstream independent processing node from the at least two independent processing nodes in sequence, wherein the system is adapted to transport a portion of the data from the downstream to the upstream processing node through the buffer and to remove the portion of the data from the buffer only after successfully processing the portion of the data in the upstream independent processing node after receipt thereof from the buffer,
wherein at least the first independent node in the processing stream is an interface node adapted to receive the data from the at least one of the communications network or the service delivery platform and send a response thereto, wherein each of the independent processing nodes of the plurality of independent processing nodes comprises a node application and a node base, wherein the node application contains logical rules according to which the processing node processes the data and the node base provides basic functionalities for the processing node; and
a system controller adapted to dynamically allocate the processing power of the common platform for the online processing and off-line processing of the data, wherein the system controller allocates more of the processing power for the online processing of the data when a current processing power allocated to the online processing of the data exceeds a current online processing load caused by the online processing of the data by a value less than a minimum reserve threshold, the minimum reserve threshold defining a reserve of the processing power to maintain a low online processing latency during peak load times, the low online processing latency representing an online processing speed that is small enough to prevent a fraud window.

US Pat. No. 10,248,463

APPARATUS AND METHOD FOR MANAGING A PLURALITY OF THREADS IN AN OPERATING SYSTEM

Honeywell International I...

1. A method for managing a plurality of threads, the method comprising:providing an environment associated with an operating system to execute one or more threads of the plurality of threads, the environment comprising a plurality of virtual priorities and a plurality of actual priorities, wherein each of the plurality of threads selects a virtual priority of the plurality of virtual priorities to be assigned, wherein the plurality of virtual priorities comprises a broader range of values than the plurality of actual priorities;
assigning, by the operating system, the plurality of virtual priorities to the plurality of threads;
associating an actual priority of the plurality of actual priorities to one of the plurality of threads based on the plurality of virtual priorities assigned to the plurality of threads; and
executing the one of the plurality of threads associated with the actual priority.

US Pat. No. 10,248,461

TERMINATION POLICIES FOR SCALING COMPUTE RESOURCES

Amazon Technologies, Inc....

1. A computer implemented method for scaling compute resources, the method comprising:receiving a plurality of user-specified termination policies, including an ordering of attributes, that is used to select one or more virtual machine instances from a group of virtual machine instances to de-provision, the group of virtual machine instances having been provisioned for a user on one or more host computing devices and the ordering of attributes determining the order in which virtual machine instances should be de-provisioned;
detecting that at least one virtual machine instance of the group of virtual machine instances should be de-provisioned based on one or more attributes associated with the at least one virtual machine instance;
selecting the at least one virtual machine instance to de-provision based at least in part on applying a user-specified termination policy of the plurality of user-specific termination policies;
applying the plurality of user-specified termination policies in a specified order until at least one virtual machine instance is selected to be de-provisioned; and
de-provisioning the selected at least one virtual machine instance.

US Pat. No. 10,248,460

STORAGE MANAGEMENT COMPUTER

Hitachi, Ltd., Tokyo (JP...

1. A management computer which communicates with a host computer and a storage device, comprising:a memory configured to store configuration information including information about a plurality of storage media each having a different performance level in the host computer and the storage device, while indicating a storage area supplied from the storage media and the host computer with their association, information about a virtual machine stored in the storage area and executed by the host computer in association with the storage area, and information about a required performance of the virtual machine; and
a CPU connected to the memory, and configured to receive an allocation request of the storage area to the virtual machine executed by the host computer, which contains information about access characteristics by the host computer and a capacity of the storage area to be allocated, select the storage medium capable of providing the storage area with the capacity from the storage media of the storage device and the host computer based on the access characteristics included in the allocation request in reference to the configuration information, generate a configuration scheme for allocating the storage area with the capacity from the selected storage media to the host computer, and output the configuration scheme,
wherein the storage media of the host computer and the storage device include at least one Flash Memory Drive,
wherein the CPU is configured to generate the configuration scheme for allocating the storage area to the virtual machine with a higher required performance preferentially to a Flash Memory Drive in reference to the configuration information, and
wherein the CPU is further configured to control allocation of the storage area to the host computer based on the configuration scheme.

US Pat. No. 10,248,459

OPERATING SYSTEM SUPPORT FOR GAME MODE

Microsoft Technology Lice...

1. A computing system for allocating one or more system resources for the exclusive use of an application, the computing system comprising:at least one processor; and
at least one storage device having stored thereon computer-executable instructions which, when executed by the at least one processor, cause the computing system to:
receive a request for an exclusive allocation of one or more system resources for a first application, the one or more system resources being useable by the first application and one or more second applications, wherein receiving the request for the exclusive allocation of the one or more system resources comprises a negotiation process that includes:
receiving an inquiry about a maximum amount of the one or more system resources that can be allocated to the exclusive use of the first application;
responding to the inquiry by providing the maximum amount of the one or more system resources that can be allocated to the exclusive use of the first application;
receiving information that specifies an amount of the one or more system resources that the first application desires for its exclusive use; and
determining if the first application is to be given the exclusive use of the one or more system resources specified in the received information;
determine an appropriate amount of the one or more system resources that are to be allocated exclusively to the first application;
partition the one or more system resources into a first portion that is allocated for the exclusive use of the first application and a second portion that is not allocated for the exclusive use of the first application, the second portion being available for the use of the one or more second applications; and
provide an indication of a disposition of the request, the indication including information detailing which specific system resources were selected for inclusion in the first portion.

US Pat. No. 10,248,458

CONTROL METHOD, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, AND CONTROL DEVICE

FUJITSU LIMITED, Kawasak...

1. A control method executed by a control device, the control method comprising:identifying a specified time period based on execution history information on previous jobs related to a plurality of systems, the specified time period being a period prior to execution start timing of a first job, update processing for a data storage area from which the first job refers to data is not executed during the specified time period;
performing control so that evaluation timing of an amount of the data that the first job refers to from the data storage area is included in the identified time period;
determining a specified system among from the plurality of systems based on the amount of the data evaluated at the evaluation timing;
causing the specified system to execute the first job;
monitoring a processing load related to a system, from among the plurality of systems, that executes the one or more jobs different from the first job; and
determining a timing, as the evaluation timing, at which the processing load is equal to or less than a predetermined reference, the determined timing being included in the identified time period.

US Pat. No. 10,248,457

PROVIDING EXCLUSIVE USE OF CACHE ASSOCIATED WITH A PROCESSING ENTITY OF A PROCESSOR COMPLEX TO A SELECTED TASK

INTERNATIONAL BUSINESS MA...

1. A method, comprising:maintaining a plurality of processing entities in a processor complex;
in response to determining that a task is a critical task, dispatching the critical task to a scheduler, wherein it is preferable to prioritize execution of critical tasks over non-critical tasks;
in response to dispatching the critical task to the scheduler, determining, by the scheduler, which processing entity of the plurality of processing entities has a least amount of processing remaining to be performed for currently scheduled tasks;
moving tasks queued on the determined processing entity to other processing entities, and completing the currently scheduled tasks on the determined processing entity;
in response to moving tasks queued on the determined processing entity to other processing entities and completing the currently scheduled tasks on the determined processing entity, dispatching the critical task on the determined processing entity, wherein the plurality of processing entities comprise a plurality of cores, and wherein the determined processing entity corresponds to a determined core that has a clean L1 cache and a clean L2 cache at a time at which the critical task is scheduled for execution in the determined core and no other tasks besides the critical task are running on the determined core at the time; and
in response to the critical task being scheduled on the determined core, the critical task secures exclusive access to the L1 cache and L2 cache of the determined core, wherein if data is not found in the L1 cache of the determined core then the data is retrieved from the L2 cache of the determined core, and wherein each core of the plurality of cores have different sets of L1 cache and L2 cache but share a L3 cache.

US Pat. No. 10,248,456

METHOD AND SYSTEM FOR PROVIDING STACK MEMORY MANAGEMENT IN REAL-TIME OPERATING SYSTEMS

Samsung Electronics Co., ...

1. A method of providing memory management in a real-time operating system (RTOS) based system, the method comprising:creating, by a task generator, a plurality of tasks with a two level stack scheme including a first-level stack and a second-level stack;
scheduling, by a task scheduler, a first task in a first state for execution by transferring task contents associated with the first task from the first-level stack to the second-level stack;
determining whether the first task is pre-empted;
allocating the second-level stack to the first task in a second state, if the first task is not pre-empted;
changing, by the task scheduler, an active task for execution;
determining whether the first task relinquishes control from the second state and is awaiting a resource;
scanning the second-level stack, if the first task relinquishes control from the second state and is awaiting the resource;
determining whether a register is present in a range of stack addresses of the second-level stack;
determining whether usage of the second-level stack is less than a size of the first-level stack, if there are no registers present in the range of the stack addresses of the second-level stack; and
transferring the task contents from the second-level stack to the first-level stack, if the usage of the second-level stack is less than the size of the first-level stack.

US Pat. No. 10,248,455

STORAGE DEVICE AND TASK EXECUTION METHOD THEREOF, AND HOST CORRESPONDING TO THE STORAGE DEVICE AND TASK EXECUTION METHOD THEREOF

Silicon Motion, Inc., Jh...

1. A storage device, comprising:a data storage media; and
a control unit, electrically coupled to the data storage media and configured for controlling an operation of the data storage media, wherein the control unit is further configured for receiving a task assignment packet from a host, the task assignment packet comprises a plurality of tasks and each of the tasks has a task identification (ID), wherein the control unit is further configured for sorting the tasks of the task assignment packet to generate an execution order for the tasks and reply the host with a task arrangement packet according to the execution order,
wherein the control unit is further configured for receiving at least one of the task IDs from the host and executing at least one of the tasks corresponding to the at least one of the task IDs, wherein the at least one of the task IDs corresponds to at least one of the tasks having a highest priority in the execution order,
wherein the task arrangement packet comprises the execution order for the tasks and the corresponding task IDs.

US Pat. No. 10,248,453

CLIENT LIVE MIGRATION FOR A VIRTUAL MACHINE

Red Hat Israel, Ltd., Ra...

1. A method comprising:connecting a first client device to a running virtual machine instance of a virtual machine;
receiving a request from a second client device to connect to the running virtual machine instance of the virtual machine while the first client device is connected to the running virtual machine instance;
connecting the second client device to the running virtual machine instance in response to the request from the second client device to access the virtual machine; and
disabling, by a processing device, one or more functions to receive input data for the running virtual machine from the first client device after the second client device has been connected to the running virtual machine instance by converting a connection between the first client device and the running virtual machine instance of the virtual machine from a primary mode to a secondary mode, wherein the primary mode corresponds to a respective client device receiving output data from the running virtual machine instance and providing the input data from the respective client device to the running virtual machine instance and the secondary mode corresponds to the respective client device receiving the output data from the running virtual machine instance without providing the input data from the respective client device to the running virtual machine instance.

US Pat. No. 10,248,452

INTERACTION FRAMEWORK FOR EXECUTING USER INSTRUCTIONS WITH ONLINE SERVICES

Microsoft Technology Lice...

1. A computer implemented framework for processing one or more user instructions on behalf of a computer user, the framework comprising:a first computing device comprising a processor and memory, hosting an instruction processing agent, wherein the instruction processing agent, in execution on the first computing device, is configured to receive a user instruction from a user agent executing on a user computing device, and maintain a list of domain agents; and
one or more domain agent computing devices, the one or more domain agent computing devices hosting a plurality of domain agents wherein each domain agent, in execution on a domain agent computing device of the one or more domain agent computing devices, corresponds to a domain and is configured to receive a domain instruction from the instruction processing agent that can be carried out within the domain, and carry out the domain instruction on behalf of the computer user;
wherein, in execution, the instruction processing agent:
receives the user instruction from the user agent;
identifies a domain suitable for carrying out the user instruction based on an identified intent of the user instruction;
maps the user instruction into at least one domain instruction according to a domain ontology of the identified domain;
selects a domain agent of the plurality of domain agents, the selected domain agent corresponding to the identified domain; and
submits the user instruction to the selected domain agent for execution; and
wherein, in execution, the selected domain agent:
maintains a plurality of proxies for interfacing with a plurality of online services, wherein each of the plurality of proxies interfaces with one each of the plurality of online services and maps the domain instruction to a respective one of the one each of the plurality of online services;
receives the domain instruction from the instruction processing agent;
identifies an online service from the plurality of online services for completing the domain instruction; and
executes the domain instruction with the online service via the respective one of the plurality of proxies for the identified online service.

US Pat. No. 10,248,451

USING HYPERVISOR TRAPPING FOR PROTECTION AGAINST INTERRUPTS IN VIRTUAL MACHINE FUNCTIONS

1. A method of a hypervisor restricting access to memory resources by a virtual machine by controlling access by the virtual machine to virtual machine functions, wherein the virtual machine executes with a default page view stored in a default page table, wherein the default page view limits access by the virtual machine to memory resources of the virtual machine, and wherein the virtual machine has access to additional memory resources by invoking virtual machine functions, the method comprising:activating a trap to the hypervisor in response to receiving an instruction that loads an interrupt data structure on the virtual machine, wherein the hypervisor maintains an alternate page table which stores an alternate page view associated with a virtual machine function, wherein the virtual machine function has access to memory resources restricted from the default page view via the alternate page view;
reading the interrupt data structure, by the hypervisor, to determine that the interrupt data structure points to the alternate page view and that the alternate page view includes a reference to a memory location outside of a memory location of the virtual machine function; and
responsive to determining that the alternate page view includes a reference to the memory location outside of the memory location of the virtual machine function, disabling the virtual machine function.

US Pat. No. 10,248,448

UNIFIED STORAGE/VDI PROVISIONING METHODOLOGY

VMware, Inc., Palo Alto,...

1. A method for providing a virtual desktop infrastructure (VDI), the method comprising:receiving an indication of a desktop pool type;
provisioning a plurality of virtual machines (VMs) to a host computing device, each of the plurality of VMs configured to execute a virtual desktop of the desktop pool type;
provisioning virtual shared storage for the plurality of VMs by using a storage manager on the host computing device, wherein provisioning the virtual shared storage includes tuning configuration settings of the virtual shared storage based on pool-related parameters associated with the desktop pool type;
detecting that a storage performance benchmark result indicating storage performance of the VMs utilizing the virtual shared storage does not meet a target threshold that is defined for the desktop pool type; and
executing an optimization loop to optimize the virtual shared storage by periodically modifying the configuration settings of the virtual shared storage and/or modifying an allocation of processor cores and/or random access memory (RAM) allocated to the storage manager.

US Pat. No. 10,248,447

PROVIDING LINK AGGREGATION AND HIGH AVAILABILITY THROUGH NETWORK VIRTUALIZATION LAYER

Red Hat, Inc., Raleigh, ...

1. A method comprising:receiving, by a processing device of a host computer system executing a hypervisor, a network packet from a virtual port associated with a virtual machine managed by the hypervisor;
generating a metadata item associated with the network packet, the metadata item comprising an identifier of the virtual port and an identifier of a transmission mode for the network packet;
recording the metadata item in a data structure identifying an address space of the hypervisor;
determining, by the processing device executing the hypervisor, in view of the identifier of the transmission mode of the metadata item, whether the transmission mode is one of a link aggregation (LA) mode, a high availability (HA) mode, or a combined LA and HA mode;
identifying a network interface controller (NIC) of the host machine for processing the network packet according to the determined transmission mode; and
transmitting the network packet to the NIC according to the determined transmission mode.

US Pat. No. 10,248,446

RECOMMENDING AN ASYMMETRIC MULTIPROCESSOR FABRIC LINK AGGREGATION

International Business Ma...

6. A system for recommending an asymmetric multiprocessing fabric link aggregation, the system comprising:a processor; and
a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the processor to cause the system to perform a method, the method comprising:
creating, based upon user defined parameters, a system plan for a single symmetric multiprocessing server having a plurality of computing nodes with at least one hypervisor that spans across the plurality of computing nodes, wherein the single symmetric multiprocessing server has a symmetric multiprocessor structure in which each of the plurality of computing nodes is connected to a shared memory and each input/output device of the single symmetric multiprocessing server;
determining, based upon the user defined parameters, an asymmetric cabling structure between the plurality of computing nodes of the single symmetric multiprocessing server for the system plan while maintaining the symmetric multiprocessor structure of the single symmetric multiprocessing server;
wherein determining the asymmetric cabling structure further includes determining, based on the user defined parameters, which nodes in the plurality of computing nodes are expected to communicate with each other more frequently;
wherein the asymmetric cabling structure is determined to increase bandwidth between the nodes of the plurality of computing nodes that are expected to communicate with each other more frequently while maintaining at least a minimum bandwidth between other nodes of the plurality of computing nodes; and
displaying to a user through a graphical user interface, a recommendation to alter one or more cables connecting the plurality of computing nodes of the symmetric multiprocessing server to conform to the system plan and the asymmetric cabling structure.

US Pat. No. 10,248,445

PROVISIONING OF COMPUTER SYSTEMS USING VIRTUAL MACHINES

VMware, Inc., Palo Alto,...

1. A method for creating a virtualized computer system, the method comprising:receiving information identifying a desired computer configuration to deploy a virtual machine thereon, the information comprising characteristics of a desired hardware platform;
based on the received information, selecting a staged virtual machine from a plurality of staged virtual machines, the plurality of staged virtual machines are created from pre-configured model virtual machines, wherein the plurality of staged virtual machines having at least one model virtual machine identifier removed;
based on the characteristics of the desired hardware platform, selecting, from a plurality of physical host platforms, a physical host platform that is compatible with the staged virtual machine and comprises the desired computer configuration; and
automatically configuring and deploying, on the physical host platform, the staged virtual machine according to the information, wherein the configuring and deploying comprises installing an application in the staged virtual machine when the application is requested via the information and the application is not pre-installed in the staged virtual machine.

US Pat. No. 10,248,444

METHOD OF MIGRATING VIRTUAL MACHINES BETWEEN NON-UNIFORM MEMORY ACCESS NODES WITHIN AN INFORMATION HANDLING SYSTEM

Dell Products, L.P., Rou...

1. A computer implemented method for allocating virtual machines (VMs) to run within a non-uniform memory access system having at least a first processing node and a second processing node, the method comprising:arranging multiple VMs into an ordered array of VMs based on relative percentages of utilization of memory resources, measured in cycles, by the individual VMs associated with the first processing node as a primary weighing factor utilized in ranking the VMs of the first processing node, and utilizing a utilization of processor resources as a secondary weighting factor, wherein arranging the multiple VMs include:
ranking the multiple VMs based on processor usage and memory usage, the memory usage including a second memory usage value from a second memory associated with the second processing node and wherein the second memory usage value is the amount of memory used by VMs executing on the first processing node; and
generating the ordered array of the multiple VMs executing on the first processing node based on the ranking;
receiving a request at the first processing node for additional capacity for establishing an additional VM on the first processing node having multiple VMs executing thereon;
in response to receiving the request, identifying whether the first processing node has the additional capacity requested;
in response to identifying that the first processing node does not have the additional capacity requested, selecting from the ordered array of the multiple VMs executing on the first processing node, at least one VM having low processor and memory usage relative to the other VMs to be re-assigned for execution from the first processing node to the second processing node;
migrating the at least one selected VM from the first processing node to the second processing node for execution; and
establishing the additional VM on the first processing node when the migrating of the at least one VM to the second processing node provides the additional capacity requested on the first processing node.

US Pat. No. 10,248,443

VIRTUAL MODEM TERMINATION SYSTEM MIGRATION IN A CABLE MODEM NETWORK ENVIRONMENT

Cisco Technology, Inc., ...

1. A method comprising:spawning, by an orchestration component executing using a processor, a first instance of a virtual network function (VNF) on a first server in a cable modem network, wherein the VNF is associated with a specific hardware interface in the cable modem network;
storing state of the first instance as state information in an external database;
spawning a second instance of the VNF on a second server, the second server being different from the first server;
synchronizing state of the second instance with the state information stored in the external database, wherein synchronizing includes associating the second instance with the specific hardware interface;
creating a first communication tunnel between the second instance and a remote physical layer (R-PHY) entity in the cable modem network, wherein the R-PHY entity is communicatively coupled to the first instance and communicates data traffic with the first instance;
creating a second communication tunnel between the first instance and the second instance;
communicating heartbeat messages between the first instance and the second instance over the second communication tunnel;
switching over the data traffic to the first communication tunnel between the second instance and the R-PHY entity; and
deleting the first instance.

US Pat. No. 10,248,442

AUTOMATED PROVISIONING OF VIRTUAL MACHINES

Unisys Corporation, Blue...

1. A computer-implemented method for automatically provisioning virtual machines within a programmable processing system, the method comprising:detecting when processing demand within the programmable processing system exceeds a predefined capacity limit;
starting a virtual machine when processing demand exceeded the predefined capacity limit;
assigning at least one community-of-interest to the virtual machine when the processing demand on the virtual machine is detected to have exceeded the predefined capacity limit, wherein the virtual machine and other virtual machines within the community-of-interest form an enclave; and
configuring the virtual machine for communications with a virtual gateway in the community-of-interest, wherein a client communicates with virtual machines of the enclave through the virtual gateway;
wherein all virtual machines within the enclave communicate with each other through a common bus, the common bus is encrypted with a key of the community-of-interest;
wherein the virtual gateway decrypts a communication when communicating with the client; and
wherein the community-of-interest being defined by a role played by the virtual machine in the community of interest and by capabilities of the virtual machine.

US Pat. No. 10,248,441

REMOTE TECHNOLOGY ASSISTANCE THROUGH DYNAMIC FLOWS OF VISUAL AND AUDITORY INSTRUCTIONS

International Business Ma...

1. A method, comprising:receiving, by a first device, action information describing a first action of a plurality of actions performed on a second device, wherein the action information was generated based on system calls generated on the second device when a user performed the first action on a target object on the second device;
identifying the target object on the second device based on metadata included in the action information;
determining one or more attributes of the target object, based on the metadata included in the action information;
identifying, based on the one or more attributes of the target object, a corresponding object on the first device;
outputting, by the first device:
a sequence of images depicting performance of the first action on the second device;
a textual instruction proximate to the corresponding object, wherein the textual instruction specifies how to perform the first action on the corresponding object on the first device; and
an audio instruction specifying how to perform the first action on the corresponding object on the first device; and
upon determining the first action has successfully been performed on the corresponding object on the first device:
transmitting an indication that the first action has successfully performed the first action on the corresponding object on the first device; and
receiving, by the first device, action information describing a second action of the plurality of actions performed on the second device.

US Pat. No. 10,248,440

PROVIDING A SET OF USER INPUT ACTIONS TO A MOBILE DEVICE TO CAUSE PERFORMANCE OF THE SET OF USER INPUT ACTIONS

GOOGLE LLC, Mountain Vie...

1. A method comprising:receiving a selection of a first screen capture image representing a screen captured on a mobile device associated with a user, the first image having a first timestamp;
determining, using a data store of images of previously captured screens of the mobile device, a reference image from the data store that has a timestamp prior to the first timestamp;
identifying a plurality of images in the data store that have respective timestamps between the timestamp for the reference image and the first timestamp;
determining a set of stored user input actions that occur prior to the first timestamp of the first image and after a timestamp corresponding to the reference image; and
providing the reference image, the plurality of images, the first image, and the set of user input actions to the mobile device, wherein providing the reference image, the plurality of images, the first image, and the set of user input actions to the mobile device causes the mobile device to perform the set of user input actions starting from a state corresponding to the reference image, wherein in performing the set of stored user input actions the mobile device automatically performs the actions using a virtual screen that is not visible via the mobile device.

US Pat. No. 10,248,439

FORMAT OBJECT TASK PANE

MICROSOFT TECHNOLOGY LICE...

1. A method for providing formatting controls in a format object task pane in an application, the method comprising:receiving a request for a formatting functionality;
in response to receiving the request, presenting a format object task pane, wherein the format object task pane is mode less to thereby enable performance of formatting tasks on multiple objects without having to dismiss and relaunch the format object task pane and the format object task pane is presented within an application window such that the format object task pane does not obstruct a document workspace;
receiving a selection of a first object displayed in the document workspace of the application, wherein the first object is of a first object type and in response to the selection of the first object,
displaying in the format object task pane a first set of formatting controls that are applicable to the first object type;
receiving a selection of a second object displayed in the document workspace of the application, wherein the second object is different from the first object and is of a second object type, and in response to the selection of the second object, displaying in the format object task pane a second set of formatting controls that are applicable to the second object type; and
receiving a selection of a third object displayed in the document workspace of the application, wherein the third object is different from the first object and the second object, and wherein the third object comprises both the first object type and the second object type, and in response to a selection of the third object, initially displaying in the format object task pane the first set of formatting controls and an options toggle that is operable to replace display of the first set of formatting controls with display of the second set of formatting controls in the format object task pane upon selection.

US Pat. No. 10,248,435

SUPPORTING OPERATION OF DEVICE

International Business Ma...

1. A method for supporting an operation by an operator of a target device, the method comprising:storing, in advance, by one or more processors, a first topology as a template indicating dependency relationship of a plurality of device types including a device type of the target device;
responsive to an event occurring with the target device, generating, by the one or more processors, a second topology indicating dependency relationship of a plurality of devices including the target device and one or more devices adjacent to the target device, by performing, based on the first topology, a topology discovery for the plurality of devices, each of the plurality of devices having any one of the plurality of device types; and
providing, by the one or more processors, an operation sequence of the plurality of devices to the operator, the operation sequence being generated based on the second topology.

US Pat. No. 10,248,434

LAUNCHING AN APPLICATION

BlackBerry Limited, Wate...

1. A method performed by a hardware processor of a mobile device, comprising:configuring, at the mobile device, a plurality of process classes, wherein each of the process classes is associated with a template process among a plurality of template processes, each template process of the plurality of template processes is associated with a different randomized memory layout among a plurality of randomized memory layouts, and at least one of the randomized memory layouts is associated with a plurality of applications in a same template process;
receiving, at the mobile device, a launching request for an application;
in response to receiving the launching request for the application, determining a process class, among the plurality of process classes, that is associated with the application; and
in response to determining the process class associated with the application, launching the application through a forked template process associated with the determined process class, wherein other different forked template processes from the plurality of template processes are running on the mobile device.

US Pat. No. 10,248,432

INFORMATION PROCESSING APPARATUS INCLUDING MAIN SYSTEM AND SUBSYSTEM

Canon Kabushiki Kaisha, ...

1. An information processing apparatus comprising:a main system which includes a main processor;
a subsystem which includes a first sub processor, a memory used for storing a program to be executed by the first sub processor, and a second sub processor; and
a connecting circuit which connects the main system and the subsystem,
wherein, based on a shift event to shift the information processing apparatus to a power-saving state, the subsystem shifts to a subsystem power-saving state and the main system shifts to a main system power-saving state,
wherein, after the shift event to shift the information processing apparatus to the power-saving state is detected and before the subsystem shifts to the subsystem power-saving state, the main processor of the main system transfers a boot program of the subsystem from the main system into the memory of the subsystem via the connecting circuit and shifts the memory of the subsystem that has stored the transferred boot program of the subsystem into a self-refresh state, and
wherein, after a return event to return at least the subsystem from the subsystem power-saving state is detected, the second sub processor causes the memory of the sub system to cancel the self-refresh state and the first sub processor of the subsystem executes, without necessity to transfer the boot program from the main system into the memory of the subsystem after the return event is detected, the boot program that has been transferred into the memory of the subsystem before the subsystem shifts to the subsystem power-saving state and has remained stored in the memory of the subsystem while the subsystem has been in the subsystem power-saving state.

US Pat. No. 10,248,430

RUNTIME RECONFIGURABLE DISSIMILAR PROCESSING PLATFORM

HAMILTON SUNDSTRAND CORPO...

1. A configurable channel system, comprising:a plurality of control channels; and
a plurality of processing platforms,
each of the plurality of processing platforms being associated with one of the plurality of control channels and being configured to perform channel management and channel monitoring of the associated one of the plurality of control channels, each of the plurality of processing platforms comprising:
a first microcontroller comprising a first core; and
a second microcontroller comprising a second core,
wherein the second microcontroller is dissimilar to the first microcontroller,
wherein each of the plurality of processing platforms loads a unique soft core from a corresponding flash memory at a runtime and executes on the first core and the second core resident software in one of an active state and a monitor state,
wherein the first core is configured in the active state to perform the channel management of the associated one of the plurality of control channels, and
wherein the second core is configured in the monitor state to perform the channel monitoring of the associated one of the plurality of control channels.

US Pat. No. 10,248,429

CONFIGURATION BASED ON A BLUEPRINT

HEWLETT PACKARD ENTERPRIS...

1. A configurable computing device, comprising:a plurality of configurable components;
non-volatile storage including a plurality of blueprints, each blueprint defining a particular configuration for the configurable components; and
processing logic coupled to the non-volatile storage and to:
receive a selection of one of the blueprints from the non-volatile storage;
validate the selected blueprint by validating a digital signature of the selected blueprint, authenticating a hash value associated with the selected blueprint, and determining whether the plurality of configurable components can be configured as defined by the selected blueprint; and
configure the configurable components in accordance with the selected and validated blueprint.

US Pat. No. 10,248,427

SEMICONDUCTOR DEVICE PERFORMING BOOT-UP OPERATION ON NONVOLATILE MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:one or more internal circuits;
a nonvolatile memory circuit having a first region suitable for storing first data for operation of the nonvolatile memory circuit itself and a second region suitable for storing second data for the internal circuits;
a first register suitable for temporarily storing the first data transferred from the nonvolatile memory and being used to optimize the nonvolatile memory;
one or more second registers suitable for temporarily storing the second data transferred from the nonvolatile memory and being used for an operation of the one or more internal circuits; and
a control circuit suitable for controlling the nonvolatile memory circuit to transmit the first data to the first register and controlling the nonvolatile memory circuit to transmit the second data to the second register after the first data is transferred to the first register and the nonvolatile memory circuit is optimized, when a boot up operation is performed.

US Pat. No. 10,248,425

PROCESSOR WITH SLAVE FREE LIST THAT HANDLES OVERFLOW OF RECYCLED PHYSICAL REGISTERS AND METHOD OF RECYCLING PHYSICAL REGISTERS IN A PROCESSOR USING A SLAVE FREE LIST

VIA ALLIANCE SEMICONDUCTO...

1. A processor, comprising:a plurality of physical registers, each identified by a physical register index;
a reorder buffer comprising a plurality of instruction entries each storing up to two physical register indexes for recycling corresponding physical registers, wherein said reorder buffer retires up to N instructions in each processor cycle in which N is a positive integer;
a master free list and a slave free list, each comprising N input ports and storing corresponding physical register indexes of said physical registers, wherein said physical registers whose corresponding physical register indexes are stored in said master free list are for allocating to instructions being issued;
a master recycle circuit that routes a first physical register index, which is stored in an instruction entry of an instruction, to one of said N input ports of said master free list when said instruction is retired; and
a slave recycle circuit that routes a second physical register index, which is stored in said instruction entry of said instruction, to one of said N input ports of said slave free list when said instruction is retired;
wherein the processor further comprises a transfer circuit that, for any given processor cycle in which said master recycle circuit routes less than N physical register indexes by a difference number, transfers up to said difference number of physical register indexes stored in said slave free list to available input ports of said master free list.

US Pat. No. 10,248,424

CONTROL FLOW INTEGRITY

Intel Corporation, Santa...

1. An apparatus comprising:control flow graph (CFG) generator circuitry to generate a CFG for a target application, wherein the CFG comprises a plurality of nodes that each includes a start address of a first basic block, an end address of the first basic block, and a next possible address of a second basic block or a not found tag;
collector circuitry to, during execution of the target application, capture processor trace (PT) data from a PT driver, the PT data comprising a first target instruction pointer (TIP) packet comprising a first runtime target address of an indirect branch instruction of the executing target application, and cause the PT driver to configure PT circuitry to limit collected PT data to TIP packets;
decoder circuitry to extract the first TIP packet from the PT data and to decode the first TIP packet to yield the first runtime target address; and
control flow validator circuitry to determine, based at least in part on the generated CFG, whether a control flow transfer to the first runtime target address corresponds to a control flow violation.

US Pat. No. 10,248,423

EXECUTING SHORT POINTER MODE APPLICATIONS

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method of facilitating processing in a computing environment, said computer-implemented method comprising:executing a short pointer mode application loaded in an address space configured for use by a plurality of types of applications including the short pointer mode application and a long pointer mode application, the address space having a first portion addressable by short pointers of a defined size and a second portion addressable by long pointers of another defined size, the other defined size being different from the defined size; and
based on executing the short pointer mode application:
converting one or more short pointers of the short pointer mode application to one or more long pointers;
based on using a long format service function, passing an in-memory short pointer as a parameter in a long format to use the long format service function, wherein the passing includes loading or accessing a long pointer representation in a parameter list holding an image of a long form register representation of the parameter; and
using the one or more long pointers to access memory within the first portion of the address space addressable by short pointers.

US Pat. No. 10,248,422

SYSTEMS, APPARATUSES, AND METHODS FOR SNOOPING PERSISTENT MEMORY STORE ADDRESSES

Intel Corporation, Santa...

1. An apparatus comprising:a decoder circuit to decode an instruction having fields to specify an opcode, a source operand, and a destination operand; and
execution circuitry to execute the decoded instruction to determine whether a tag from the address from the source operand matches a tag in any of N selected cache lines of a N-way set-associative non-volatile memory address cache (NVMAC), the N cache lines being selected by an index from the address from the source operand, wherein, to make the determination, the execution circuitry is to:
compare a tag value from each selected cache line to the tag from the address from the source operand, each of the comparisons to determine whether there is a match,
AND each comparison result with a valid bit from the respective selected cache line,
OR the outputs of the AND operations, and
store the output of the OR in the destination operand, the result of the OR comprising a hit indication;
wherein when there is a match, the hit indication is stored in the destination operand, and when there is not a match, a no hit indication is stored in the destination operand and the NVMAC is updated with the tag from the address from the source operand.

US Pat. No. 10,248,421

OPERATION OF A MULTI-SLICE PROCESSOR WITH REDUCED FLUSH AND RESTORE LATENCY

International Business Ma...

1. A method of operation of a multi-slice processor, the multi-slice processor including a plurality of execution slices and a plurality of load/store slices, each execution slice comprising an issue queue, one or more general purpose registers, a history buffer, and a plurality of execution units including one or more floating point units and one or more vector/scalar units wherein the load/store slices are coupled to the execution slices via a results bus, the method comprising: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; and when the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush for the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and when an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.

US Pat. No. 10,248,419

IN-MEMORY/REGISTER VECTOR RADIX SORT

International Business Ma...

1. A computer-implemented method, comprising:retrieving a plurality of cache lines of data from an input buffer, wherein each cache line comprises a plurality of elements;
scattering the plurality of elements of each retrieved cache line into a plurality of bins, wherein said scattering comprises using one or more vector instructions;
forming a bin cache line in a corresponding one of the plurality of bins, wherein the bin cache line comprises a group of the plurality of elements which were scattered from multiple distinct cache lines among the plurality of cache lines to the corresponding one of the plurality of bins;
writing the bin cache line from the corresponding one of the plurality of bins to a memory, wherein said writing the bin cache line to the memory comprises using one or more predicated instructions, and wherein the one or more predicated instructions are predicated based on the occupied size of the bin relative to the size of the bin cache line; and
loading the bin cache line from the memory to the input buffer;
wherein the steps are carried out by at least one computing device.

US Pat. No. 10,248,416

ENHANCING CODE REVIEW THROUGHPUT BASED ON SEPARATE REVIEWER AND AUTHOR PROFILES

International Business Ma...

1. A computer-implemented method for enhancing code review throughput based on separate profiles, comprising:generating a first type of profile for a first user based on a collection of first source associated with the first user, wherein the first type of profile indicates different types of errors that occurred in the collection of first source code greater than at least one of a first predefined threshold number of times and a first predefined percentage of time;
determining, based on the first type of profile for the first user, that the different types of errors have a likelihood of occurring in source code written by the first user, when the first type of profile indicates that frequency of occurrence of the different types of errors is greater than at least one of the first predefined threshold number of times and the first predefined percentage of time;
receiving second source code associated with the first user;
determining, for each of one or more second users, one or more coding review attributes associated with the second user from a second type of profile for the second user;determining a set of metrics for each of the second users, based on a collection of third source code associated with different users, wherein the set of metrics comprises at least one of: (i) a number of the different types of errors identified for every predetermined number of lines of the third source code and (ii) a code review throughput of the third source code;generating, based on the one or more metrics, a proficiency score associated with each coding review attribute of each of the second users;
evaluating the one or more coding review attributes based on the proficiency score assigned to each coding review attribute, wherein the proficiency score for each coding review attribute indicates a number of times the second user identified at least one of the different types of errors indicated in the first type of profile greater than at least one of a second predefined number of times and a second predefined percentage of time when reviewing source code;
selecting at least one of the second users to review the first user's second source code based at least in part on the evaluation;
sending the second source code to the selected at least one second user to review; and
after sending the second source code, highlighting different portions of the second source code on an interface of the selected at least one second user based on the first type of profile for the first user to increase efficiency of code review by the selected at least one second user, wherein the different portions of the second source code are associated with the different types of errors that have the likelihood of occurring in source code written by the first user.

US Pat. No. 10,248,415

DYNAMIC CODE GENERATION AND MEMORY MANAGEMENT FOR COMPONENT OBJECT MODEL DATA CONSTRUCTS

Microsoft Technology Lice...

1. A computing device, comprising:a processor communicatively coupled to a memory, the memory storing computing executable instructions that when executed cause the processor to:
initiate a request to reclaim memory associated with a script code object with a dependency to a native code object represented in native code;
in a first phase, request the script code object and the native code object to prepare for the request to reclaim the memory associated with the script code object; and
in a second phase, only in response to receiving confirmation from the script code object that the script code object is prepared for the request and in response to receiving confirmation from the native object that the native object is prepared for the request, unwind the dependency to the native code object represented in native code and proceed to reclaim the memory associated with the script code object.

US Pat. No. 10,248,414

SYSTEM AND METHOD FOR DETERMINING COMPONENT VERSION COMPATIBILITY ACROSS A DEVICE ECOSYSTEM

Duo Security, Inc., Ann ...

1. A method comprising:at a network connected platform, collecting component version data from a plurality of device instances;
constructing a device version dataset for each device instance of the plurality of device instances based on the component version data;
classifying the device version dataset for each device instance into a device profile repository;
at the network connected platform, querying the device profile repository in response to a component version query request from a requesting entity, wherein the component version query request comprises component version specification data; and
sending, to the requesting entity in response to the component version query request, query response data relating to results of the querying the device profile repository.

US Pat. No. 10,248,413

MERIT BASED INCLUSION OF CHANGES IN A BUILD OF A SOFTWARE SYSTEM

INTERNATIONAL BUSINESS MA...

1. A computer-implemented method, comprising:receiving, from a first user, a change to a software system under development from a first user;
calculating, based upon success of prior changes received from the first user, a merit score for the first user;
comparing the merit score for the first user with a merit threshold for the software system under development;
determining that the merit score for the first user complies with the merit threshold; and
accepting, responsive to the determining, the change for inclusion in a build of the software system under development, wherein
the merit score for the first user is increased responsive to approval of the change by a second user having at least a minimum merit score.

US Pat. No. 10,248,411

DYNAMIC DATA INGESTION

International Business Ma...

1. A method comprising:receiving, at a virtual scan group manager (VSGM) stored on a software asset management (SAM) server, a plurality of respective device scans from a plurality of respective devices;
determining, for each respective device scan, a respective size of the respective device scan and a respective interval between a previous device scan and a current device scan for the respective device;
selecting respective device scans having a respective interval between a previous device scan and a current device scan above a time threshold;
compiling selected device scans in a plurality of respective virtual scan groups (VSGs);
processing the plurality of VSGs containing selected device scans by loading respective device scans of each respective VSG into a data repository stored on the SAM server; and
recording each processed device scan in a VSGM logfile stored in the VSGM.

US Pat. No. 10,248,409

LIMITING THE EFFECTS OF SOURCE CODE PATCHES ON CORRESPONDING NATIVE-CODE PATCHES

Amazon Technologies, Inc....

1. A method, comprising:performing by one or more computers:
creating a source code patch for a first source code representation of a software program;
generating a binary update to be applied to a first binary code representation of the software program during execution of the first binary code representation of the software program, wherein generating the binary update comprises:
transforming the source code patch to avoid introducing differences between line number information that is embedded in the first binary code representation of the software program and line number information that will be embedded in a new binary code representation of the software program other than in the portion of the new binary representation of the software program that includes the binary update;
applying the transformed source code patch to the first source code representation of the software program to produce a patched version of the source code representation of the software program;
determining that a representation of a source code file name that will be embedded in the new binary code representation of the software program does not match a representation of a corresponding source code file name that is embedded in the first binary code representation of the software program;
responsive to the determination, transforming the representation of the source code file name that will be embedded in the new binary code representation of the software program prior to creating the new binary code representation of the software program from the patched version of the source code representation of the software program;
creating the new binary code representation of the software program from the patched version of the source code representation of the software program, wherein the new binary code representation includes at least one instance of the transformed representation of the source code file name;
comparing the first binary code representation of the software program to the new binary code representation of the software program; and
generating the binary update, based at least in part on said comparing; and
applying the binary update to the first binary code representation of the software program during execution of the first binary code representation of the software program.

US Pat. No. 10,248,406

LOCALE OBJECT MANAGEMENT

International Business Ma...

1. A computer system comprising:a processor in communication with a memory;
a functional unit in communication with the processor having a locale object management daemon to perform context-switch based locale object management, the locale object management daemon to:
identify a task being performed on data by an application, the application having a pre-loaded first locale object, wherein the first locale object contains at least one first display format parameter;
perform a first comparison including compare the identified task to a locale object switch pattern;
identify the locale object switch pattern based on the first comparison;
perform a pre-emptive locale object switch operation comprising:
identify a switch reference;
perform a second comparison including compare the identified task to the identified switch reference;
identify the application performing the identified task based on the second comparison;
interrupt execution of the identified application;
over-ride the pre-loaded first locale object including:
select a second locale object based on the identified switch reference, wherein the second locale object contains at least one second display format parameter; and
load, in real-time, the second locale object into the interrupted application; and
resume execution of the interrupted application with the second locale object, including formatting the data based on the second display format parameter.

US Pat. No. 10,248,404

MANAGING UPDATE DEPLOYMENT

Amazon Technologies, Inc....

1. A system for managing update deployment, the system comprising:a data store including computer-executable instructions; and
one or more processors configured to execute the computer-executable instructions, wherein execution of the computer-executable instructions causes the system to:
obtain an update to be deployed and implemented within a target computing environment, wherein the target computing environment includes a plurality of receiving computing devices on which to implement the update to provide functionality corresponding to the update on behalf of at least one client;
determine a deployment schedule corresponding to a schedule for deployment of the update to the plurality of receiving computing devices;
determine criteria for modifying the schedule for deployment, wherein the criteria comprise rules for modifying the schedule for deployment based at least in part on a measured effect on a set of monitored computing devices of deploying the update;
cause deployment of the update to at least a first computing device of the plurality of receiving computing devices;
receive, from the set of monitored computing devices, monitoring information representing a measured effect of deploying the update to the first computing device;
modify the deployment schedule according to the criteria based at least in part on the received monitoring information, wherein modifying the deployment schedule comprises at least one of increasing a rate of deployment when the measured effect of deploying the update to the first computing device is positive or decreasing the rate of deployment when the measured effect of deploying the update to the first computing device is negative; and
cause deployment of the update in accordance with the modified deployment schedule.

US Pat. No. 10,248,402

AUTOMATED CODE DEPLOYMENT SYSTEM

Bank of America Corporati...

1. A system for automated code deployment, the system comprising:at least one non-transitory storage device;
at least one processor; and
at least one module stored in said memory and comprising instruction code that is executable by the at least one processor and configured to cause said at least one processor to:
retrieve an updated software code block from a source database;
in response to retrieving the updated software code block, generate the presentation of a user interface, wherein the user interface comprises at least a status of potential deployment of the updated software code block, a unique identifier associated with the potential deployment, a unique identifier associated with the one or more edges for the potential deployment, a source database associated with the potential deployment, a time associated with the deployment, a job type and a deployment priority, and wherein the job type comprises at least one of an upload, a download, or a distribution;
subsequently to the retrieving, determine one or more edges to install the updated software code block, wherein the one or more edges comprise:
an existing software code block,
one or more servers associated with at least one of a testing environment, user acceptance test environment, staging environment, and production environment,
wherein the one or more servers are configured to test and measure the performance of the software code block;
in response to determining the one or more edges, updating the user interface with the determined unique identifiers associated with the determined one or more edges;
subsequently to determining the edges, capture a snapshot of the source database and the one or more edges, wherein the snapshot comprises one or more listing file sizes, modification times and dates, security permissions, and sharing configuration;
in response to capturing a snapshot, updating the user interface to identify the source database associated with the potential deployment;
based on the snapshot of the source database and the one or more edges, determine a minimum code to transfer from the source database to the one or more edges so that the edges mirror the updated software code block from the source database, wherein the minimum code is the difference between the existing software code block and the updated software code block;
determine one or more transport engines to enable deployment of the minimum code, wherein determining one or more transport engines comprises retrieving the geographic location of the one or more edges;
in response to determining the minimum code and the transport engines, performing the steps of:
updating the user interface to initialize a status of the deployment of the minimum code, a unique identifier associated with the deployment of the minimum code and a job type associated with the deployment;
retrieve the existing software code block from the one or more edges; and
store the retrieved existing software code block in a back-up database prior to deploying the minimum code;
based on determining the minimum code to transfer and determining one or more transport engines, automatically deploy the minimum code retrieved from the source database to the one or more edges using the one or more transport engines;
in response to automatically deploying the minimum code, updating the user interface to a new status in regards to the deployment;
subsequent to the deploying, install the updated software code block in the one or more edges;
in response to the installing, updating the user interface to a new status in regards to the deployment;
determine that the updated software code block in the one or more edges is malfunctioning;
in response to the determined malfunction, retrieve, from the back-up database, the stored software code block previously associated with the one or more edges determined to be malfunctioning and
automatically revert the one or more malfunctioning edges with the retrieved stored software code block and update the user interface with the new status.

US Pat. No. 10,248,401

MULTIPLATFORM AND MULTICHANNEL DISTRIBUTION OF WEB APPLICATIONS ACROSS DEVICES

GOOGLE LLC, Mountain Vie...

1. A method for installation of user device configured web applications, the method comprising:storing a plurality of files in a plurality of logical locations, each logical location of the plurality of logical locations being associated with at least one of a configuration, a platform and a setting associated with at least one potential user device, each of the plurality of files being associated with execution of a corresponding web application;
receiving, from a user device, a request to install a web application;
determining information about the user device, including at least one of a configuration, a platform and a setting associated with the user device;
determining whether a logical location, from the plurality of logical locations, exists for the requested web application for the user device, wherein the determination is based on at least one of the configuration, the platform and the setting associated with the user device by:
generating a search term based on at least one of the configuration, the platform and the setting associated with the user device; and
searching a manifest associated with the web application for the search term;
upon determining the logical location exists, providing files stored in the determined logical location for installation of the web application;
upon determining the logical location does not exist:
determining whether a default logical location exists; and
upon determining the default logical location exists, providing files stored in the determined default logical location for installation of the web application.

US Pat. No. 10,248,399

APPARATUS AND METHOD FOR CONTROLLING INTERNET OF THINGS DEVICES

Samsung Electronics Co., ...

1. An electronic device comprising:a wireless communication interface;
a memory;
a display; and
an application processor electrically connected to the communication interface, the memory, and the display,
wherein the memory stores instructions that, when executed by the application processor, cause the electronic device to:
acquire information on a first external electronic device;
access, through the communication interface, a server that stores a software program related to the first external electronic device, based on at least a portion of the information on the first external electronic device;
receive at least a portion of the software program associated with the first external electronic device, from the server, through the communication interface;
install, on the electronic device, the at least a portion of the software program received from the server;
transmit at least one part of the received at least a portion of the software program, to a second external electronic device, through the communication interface; and
provide a user interface on the display, using the installed at least a portion of the software program, and
wherein the user interface is configured to receive a user input for the second external electronic device to perform an operation associated with the first external electronic device.

US Pat. No. 10,248,398

METHOD FOR VIRTUALIZING SOFTWARE APPLICATIONS

BlackBerry Limited, Wate...

1. A method for virtualizing software applications, the method comprising:initializing a virtual environment created by a virtual engine executed over a computer;
launching an installation process of a software application to be virtualized, wherein the installation process runs in the virtual environment; and
capturing all data writes performed during the installation process and saving the captured data writes to a new data file,
wherein the new data file, upon completion of the installation process, does not store an operating system.

US Pat. No. 10,248,397

INTELLIGENT AND AUTOMATED CODE DEPLOYMENT

INTERNATIONAL BUSINESS MA...

1. A system for deploying code in a computing sysplex environment, comprising:a processor executing instructions stored in a memory, wherein when executing the instructions, the processor:
applies a system-wide trending mechanism, including matching at least one of a non-scheduled idle time and a low Central Processing Unit (CPU) utilization time of one system in the sysplex environment with an estimated deployment time obtained from at least one of a latest measured period of time and a calculated time trend;
applies a system-wide coordination mechanism, including recommending performing a staggered code deployment operation for at least one node of the system at an optimum system time generated from the matching such that the staggered code deployment operation is performed at a time based on the optimum system time in lieu of a time scheduled by an administrator;
records data obtained from the code deployment operation, including recording a new latest measured period of time, the data used to generate an updated time trend, wherein the new latest measured period of time and the updated time trend is utilized in a subsequent matching operation for another system in the sysplex environment for a subsequent code deployment operation;
establishes a predetermined tracking period for the one system for one of a calculated and specified time interval, wherein the matching is performed at least once during the predetermined tracking period;
registers at least one priority for a production task in the code deployment operation, wherein the at least one priority is used in conjunction with the matching to obtain the recommendation; and
downloads code images to a centralized service point for subsequent deployment to the one system in the sysplex environment.

US Pat. No. 10,248,396

CODE REVIEW WITH AUTOMATED TRANSLATION

Amazon Technologies, Inc....

1. A system comprising:one or more server computers comprising:
a source control system configured to be in communication with a developer interface and a code reviewer interface, the developer interface being configured to submit a request for code review of program source code and the code reviewer interface being configured to review the program source code, the program source code containing resource files containing content in a first language, and the source control system being configured to manage changes to the program source code resulting from the code review;
a resource file translator configured to translate the resource files from the first language into one or more second languages; and
a workflow manager in communication with the source control system and the resource file translator, the workflow manager being configured to control interaction between the source control system and the resource file translator,
wherein:
responsive to receipt of the code review request, the source control system is configured to notify the workflow manager that the resource files contain the content for translation from the first language into the one or more second languages;
the workflow manager is configured to notify the resource file translator that the resource files contain the content for translation from the first language to the one or more second languages;
the resource file translator is configured to identify resource files in the program source code that contain the content for translation from the first language to the one or more second languages;
the resource file translator is configured to cause translation of the resource files into translated resource files containing respective ones of the one or more second language translations of the content;
the source control system is configured to receive reviewed program source code from the code reviewer interface; and
the resource file translator is configured to update the program source code under review with the translated resource files.

US Pat. No. 10,248,392

REPLICATING A WEB TECHNOLOGY

ENTIT SOFTWARE LLC, Sunn...

1. A method for replicating a web technology, the method comprising:identifying asynchronous scripting code within isolated scripting code of the web technology, the isolated scripting code being part of larger client-side code of the web technology;
executing the asynchronous scripting code to cause a request to be sent to a remote server and recording the request;
listening for return data received from the remote server in response to the request and saving the return data; and
generating mock server-side code based on the request and the return data.

US Pat. No. 10,248,389

GRAPHICAL USER INTERFACE EDITOR SYSTEM AND METHOD FOR PERSONAL DEVICES

Amer Sports Digital Servi...

5. A diving computer comprising:a graphical user interface editor system for editing the graphical user interface of the diving computer having one or more display views, each of which having a set of data fields being arranged in a predetermined manner on the display view, each data field showing the value of a user-definable diving parameter in the user interface,wherein the editor system provides user access to at least one data field of the set of data fields to allow user selection of user-definable diving parameters in the field,whereby a list of parameter options valid for the field is displayed for selection by the user, the parameter value of which is to be displayed in the field,wherein the graphical user interface includes two or more alternative display modes where the predetermined set of data fields is arranged in a different manner for each mode on the display view, andwhereby the value for the user-defined diving parameter which is measured and processed by the diving computer is viewed in said field in a display view on the display of the diving computer.

US Pat. No. 10,248,388

PROGRAMMING IN A PRECISE SYNTAX USING NATURAL LANGUAGE

Wolfram Alpha LLC, Champ...

1. A method, comprising:receiving, via a user interface device, user input for inclusion in a workspace document corresponding to a spreadsheet file, wherein the workspace document is displayed in a graphical user interface of a spreadsheet application that, when executed by one or more computer processors, is configured to evaluate instructions in a precise syntax;
after receiving the user input, displaying, on a display device, the user input in the workspace document;
determining, at the one or more computer processors, whether at least a portion of the user input i) is in the precise syntax, or ii) is in an imprecise syntax, including analyzing the user input to determine if the user input includes a user indication, in the precise syntax, that indicates whether at least the portion of the user input i) is in the precise syntax, or ii) is in an imprecise syntax;
when it is determined that at least the portion of the user input is in the precise syntax,
evaluating, at the one or more computer processors, at least the portion of the user input according to the precise syntax;
when it is determined that at least the portion of the user input is in the imprecise syntax,
generating, at the one or more computer processors, an application programming interface (API) call that includes i) the at least the portion of the user input in the imprecise syntax, and ii) information indicating a result of a previous evaluation, by the spreadsheet application, of a user input previously entered into the workspace document,
sending, by the one or more computer processors, the API call to a natural language processing (NLP) system implemented by a server system executing machine readable instructions,
processing, at the server system, the API call to determine the instruction in the precise syntax that corresponds to the user input in the imprecise syntax, wherein the instruction in the precise syntax is for generating a modification of the result of the previous evaluation,
formatting, at the server system, the instruction in the precise syntax according to a format recognized by the spreadsheet application,
receiving, at the one or more computer processors, the instruction in the precise syntax from the NLP system implemented by the server system executing machine readable instructions, wherein receiving the instruction in the precise syntax from the server system is responsive to sending the API call to the server system,
including, by one or more computer processors, the instruction in the precise syntax in the workspace document such that the spreadsheet application executed by one or more computer processors can evaluate the instruction in the precise syntax, including simultaneously displaying, on the display device, at least the portion of the user input in the imprecise syntax and the instruction in the precise syntax in the workspace document, and
after including the instruction in the precise syntax in the workspace document, evaluating, at one or more computing devices, the instruction in the precise syntax.

US Pat. No. 10,248,382

USER INTERFACE AND METHOD FOR ASSISTING A USER WITH THE OPERATION OF AN OPERATING UNIT

Volkswagen Aktiengesellsc...

1. A method of operating a touch-sensitive operator control unit for a vehicle, comprising:displaying a graphical symbol on the operator control unit;
detecting the presence of input means in a predefined first area in front of the operator control unit in an area of the displayed graphical symbol, wherein the predefined first area comprises an area parallel above a surface of the operator control unit; and
generating a predefined first audio output comprising a context-specific sound associated with a vehicle function of the graphical display symbol in response to the detected presence of the input means; and
detecting direct contact of the input means with the displayed graphical symbol to cause execution of the vehicle function; and
generating another predefined audio output comprising a context-specific sound associated with the vehicle function of the graphical display symbol in response to the detected direct contact with the displayed graphical symbol.

US Pat. No. 10,248,378

DYNAMICALLY INSERTING ADDITIONAL CONTENT ITEMS TARGETING A VARIABLE DURATION FOR A REAL-TIME CONTENT STREAM

ADSWIZZ INC., San Mateo,...

8. A system comprising:a processor;
a non-transitory computer readable storage medium comprising stored instructions for dynamically inserting additional content items targeting a delay value for a live content stream, that when executed by the processor, cause the processor to:
retrieve, by one or more computing devices, a plurality of regular content replacement parts from a computer storage device, each regular content replacement part being a content item from a third party content provider, each regular content replacement part having durations within a single range of values;
retrieve, by the one or more computing devices, one or more alternative content replacement parts from the computer storage device, each alternative content replacement part being a content item with a duration within one of a plurality of consecutive ranges;
detect, by the one or more computing devices, a start of a content replacement break in a live content stream that is transmitted to a client device as a listener content stream by detecting a marker embedded within a digital audio data of the live content stream, the listener content stream shifted by a listener delay value from the live content stream, the listener delay value computed by determining a difference in time between the listener content stream and the live content stream, and wherein the live content stream is received from a publisher at the same time as a corresponding content stream is generated;
modify the waveform of the listener content stream at a first point in the listener content stream corresponding to the content replacement break to insert one or more of the plurality of regular content replacement parts;
detect an end of the content replacement break for the live content stream;
sort the one or more alternative content replacement parts in ascending order by an absolute value of the difference between the listener delay value of the listener content stream and a target delay value were the alternative content replacement part inserted into the listener content stream, the target delay value being a previously specified duration of time;
select an alternative content replacement part that is a top entry in the sorted one or more alternative content replacement parts;
modify the waveform of the listener content stream to insert the selected alternative replacement part; and
transmit the listener content stream to the client device.

US Pat. No. 10,248,359

SYSTEM, METHOD AND APPARATUS FOR ACCELERATING FAST BLOCK DEVICES

1. A method of fast data storage on a block storage device, comprising:determining if a given empty write block is empty based on state data, said given empty write block being from a list of empty write blocks, wherein the state data is associated with an entry in a lookup table for the empty write blocks;
linearly writing new data to a data field segment within said empty write block,
wherein said linearly writing comprises writing meta data associated with said new data to a control field within said empty write block,
wherein said meta data within said control field is written in both a front portion at the start of said empty write segment and contiguous said new data and a back portion after said new data and contiguous thereto, and
wherein said writing of said new data and said meta data is done linearly across the empty write block in a time-received order and not a logical order.

US Pat. No. 10,248,357

DATA STORAGE SYSTEM WITH HARDWARE-BASED MESSAGE ROUTING

Seagate Technology LLC, ...

1. A method comprising:activating a data storage system connecting first and second data storage devices with a host via a network, the network comprising a network controller having a message module;
generating a buffer progression plan with the message module;
assigning a first system message to a first buffer and first computing unit of the first data storage device;
assigning a second system message to a second buffer and second computing unit of the second data storage device;
servicing the first and second system messages with the respective first and second computing units; and
activating firmware with the message module in response to a failure in servicing the first or second system messages.

US Pat. No. 10,248,356

USING SCRATCH EXTENTS TO FACILITATE COPYING OPERATIONS IN AN APPEND-ONLY STORAGE SYSTEM

Dropbox, Inc., San Franc...

1. A computer-implemented method, comprising:at one or more devices comprising one or more processors and memory storing instructions executed by the one or more processors to perform the method, performing the following operations:
receiving a request to copy an extent from a source storage device to a destination storage device;
creating a scratch extent on the destination storage device;
associating the scratch extent with a private identifier;
performing a copying operation that copies the extent from the source storage device to the scratch extent on the destination storage device;
wherein the scratch extent is associated with the private identifier while the copying operation is being performed;
after the copying operation is complete and the scratch extent is closed, associating the scratch extent with a public identifier;
wherein associating the scratch extent with the private identifier comprises using the private identifier to create a first entry in a lookup structure stored at the destination storage device, the first entry for accessing the scratch extent using the private identifier, the first entry retrievable from the lookup structure using the private identifier; and
wherein associating the scratch extent with the public identifier comprises using the public identifier to create a second entry in the lookup structure, the second entry for accessing the scratch extent using the public identifier, the second entry retrievable from the lookup structure using the public identifier.